1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int toc_save_offset; /* offset to save the TOC pointer */
95 int varargs_save_offset; /* offset to save the varargs registers */
96 int ehrd_offset; /* offset to EH return data */
97 int reg_size; /* register size (4 or 8) */
98 int varargs_size; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size; /* variable save area size */
100 int parm_size; /* outgoing parameter size */
101 int save_size; /* save area size */
102 int fixed_size; /* fixed size of stack frame */
103 int gp_size; /* size of saved GP registers */
104 int fp_size; /* size of saved FP registers */
105 int altivec_size; /* size of saved AltiVec registers */
106 int cr_size; /* size to hold CR if not in save_size */
107 int lr_size; /* size to hold LR if not in save_size */
108 int vrsave_size; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size; /* size of altivec alignment padding if
111 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size;
113 int toc_size; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu;
121 struct rs6000_cpu_select rs6000_select[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str;
138 int rs6000_sched_restricted_insns_priority;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load;
150 /* Support targetm.vectorize.builtin_mask_for_store. */
151 static GTY(()) tree altivec_builtin_mask_for_store;
153 /* Size of long double */
154 const char *rs6000_long_double_size_string;
155 int rs6000_long_double_type_size;
157 /* Whether -mabi=altivec has appeared */
158 int rs6000_altivec_abi;
160 /* Whether VRSAVE instructions should be generated. */
161 int rs6000_altivec_vrsave;
163 /* String from -mvrsave= option. */
164 const char *rs6000_altivec_vrsave_string;
166 /* Nonzero if we want SPE ABI extensions. */
169 /* Whether isel instructions should be generated. */
172 /* Whether SPE simd instructions should be generated. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
179 int rs6000_darwin64_abi;
181 /* String from -mfloat-gprs=. */
182 const char *rs6000_float_gprs_string;
184 /* String from -misel=. */
185 const char *rs6000_isel_string;
187 /* String from -mspe=. */
188 const char *rs6000_spe_string;
190 /* Set to nonzero once AIX common-mode calls have been defined. */
191 static GTY(()) int common_mode_defined;
193 /* Save information from a "cmpxx" operation until the branch or scc is
195 rtx rs6000_compare_op0, rs6000_compare_op1;
196 int rs6000_compare_fp_p;
198 /* Label number of label created for -mrelocatable, to call to so we can
199 get the address of the GOT section */
200 int rs6000_pic_labelno;
203 /* Which abi to adhere to */
204 const char *rs6000_abi_name;
206 /* Semantics of the small data area */
207 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
209 /* Which small data model to use */
210 const char *rs6000_sdata_name = (char *)0;
212 /* Counter for labels which are to be placed in .fixup. */
213 int fixuplabelno = 0;
216 /* Bit size of immediate TLS offsets and string from which it is decoded. */
217 int rs6000_tls_size = 32;
218 const char *rs6000_tls_size_string;
220 /* ABI enumeration available for subtarget to use. */
221 enum rs6000_abi rs6000_current_abi;
223 /* ABI string from -mabi= option. */
224 const char *rs6000_abi_string;
226 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
230 const char *rs6000_debug_name;
231 int rs6000_debug_stack; /* debug stack applications */
232 int rs6000_debug_arg; /* debug argument handling */
234 /* Value is TRUE if register/mode pair is accepatable. */
235 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
238 static GTY(()) tree opaque_V2SI_type_node;
239 static GTY(()) tree opaque_V2SF_type_node;
240 static GTY(()) tree opaque_p_V2SI_type_node;
241 static GTY(()) tree V16QI_type_node;
242 static GTY(()) tree V2SI_type_node;
243 static GTY(()) tree V2SF_type_node;
244 static GTY(()) tree V4HI_type_node;
245 static GTY(()) tree V4SI_type_node;
246 static GTY(()) tree V4SF_type_node;
247 static GTY(()) tree V8HI_type_node;
248 static GTY(()) tree unsigned_V16QI_type_node;
249 static GTY(()) tree unsigned_V8HI_type_node;
250 static GTY(()) tree unsigned_V4SI_type_node;
251 static GTY(()) tree bool_char_type_node; /* __bool char */
252 static GTY(()) tree bool_short_type_node; /* __bool short */
253 static GTY(()) tree bool_int_type_node; /* __bool int */
254 static GTY(()) tree pixel_type_node; /* __pixel */
255 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
256 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
257 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
258 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
260 int rs6000_warn_altivec_long = 1; /* On by default. */
261 const char *rs6000_warn_altivec_long_switch;
263 const char *rs6000_traceback_name;
265 traceback_default = 0,
271 /* Flag to say the TOC is initialized */
273 char toc_label_name[10];
275 /* Alias set for saves and restores from the rs6000 stack. */
276 static GTY(()) int rs6000_sr_alias_set;
278 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
279 The only place that looks at this is rs6000_set_default_type_attributes;
280 everywhere else should rely on the presence or absence of a longcall
281 attribute on the function declaration. Exception: init_cumulative_args
282 looks at it too, for libcalls. */
283 int rs6000_default_long_calls;
284 const char *rs6000_longcall_switch;
286 /* Control alignment for fields within structures. */
287 /* String from -malign-XXXXX. */
288 const char *rs6000_alignment_string;
289 int rs6000_alignment_flags;
291 struct builtin_description
293 /* mask is not const because we're going to alter it below. This
294 nonsense will go away when we rewrite the -march infrastructure
295 to give us more target flag bits. */
297 const enum insn_code icode;
298 const char *const name;
299 const enum rs6000_builtins code;
302 /* Target cpu costs. */
304 struct processor_costs {
305 const int mulsi; /* cost of SImode multiplication. */
306 const int mulsi_const; /* cost of SImode multiplication by constant. */
307 const int mulsi_const9; /* cost of SImode mult by short constant. */
308 const int muldi; /* cost of DImode multiplication. */
309 const int divsi; /* cost of SImode division. */
310 const int divdi; /* cost of DImode division. */
311 const int fp; /* cost of simple SFmode and DFmode insns. */
312 const int dmul; /* cost of DFmode multiplication (and fmadd). */
313 const int sdiv; /* cost of SFmode division (fdivs). */
314 const int ddiv; /* cost of DFmode division (fdiv). */
317 const struct processor_costs *rs6000_cost;
319 /* Processor costs (relative to an add) */
321 /* Instruction size costs on 32bit processors. */
323 struct processor_costs size32_cost = {
324 COSTS_N_INSNS (1), /* mulsi */
325 COSTS_N_INSNS (1), /* mulsi_const */
326 COSTS_N_INSNS (1), /* mulsi_const9 */
327 COSTS_N_INSNS (1), /* muldi */
328 COSTS_N_INSNS (1), /* divsi */
329 COSTS_N_INSNS (1), /* divdi */
330 COSTS_N_INSNS (1), /* fp */
331 COSTS_N_INSNS (1), /* dmul */
332 COSTS_N_INSNS (1), /* sdiv */
333 COSTS_N_INSNS (1), /* ddiv */
336 /* Instruction size costs on 64bit processors. */
338 struct processor_costs size64_cost = {
339 COSTS_N_INSNS (1), /* mulsi */
340 COSTS_N_INSNS (1), /* mulsi_const */
341 COSTS_N_INSNS (1), /* mulsi_const9 */
342 COSTS_N_INSNS (1), /* muldi */
343 COSTS_N_INSNS (1), /* divsi */
344 COSTS_N_INSNS (1), /* divdi */
345 COSTS_N_INSNS (1), /* fp */
346 COSTS_N_INSNS (1), /* dmul */
347 COSTS_N_INSNS (1), /* sdiv */
348 COSTS_N_INSNS (1), /* ddiv */
351 /* Instruction costs on RIOS1 processors. */
353 struct processor_costs rios1_cost = {
354 COSTS_N_INSNS (5), /* mulsi */
355 COSTS_N_INSNS (4), /* mulsi_const */
356 COSTS_N_INSNS (3), /* mulsi_const9 */
357 COSTS_N_INSNS (5), /* muldi */
358 COSTS_N_INSNS (19), /* divsi */
359 COSTS_N_INSNS (19), /* divdi */
360 COSTS_N_INSNS (2), /* fp */
361 COSTS_N_INSNS (2), /* dmul */
362 COSTS_N_INSNS (19), /* sdiv */
363 COSTS_N_INSNS (19), /* ddiv */
366 /* Instruction costs on RIOS2 processors. */
368 struct processor_costs rios2_cost = {
369 COSTS_N_INSNS (2), /* mulsi */
370 COSTS_N_INSNS (2), /* mulsi_const */
371 COSTS_N_INSNS (2), /* mulsi_const9 */
372 COSTS_N_INSNS (2), /* muldi */
373 COSTS_N_INSNS (13), /* divsi */
374 COSTS_N_INSNS (13), /* divdi */
375 COSTS_N_INSNS (2), /* fp */
376 COSTS_N_INSNS (2), /* dmul */
377 COSTS_N_INSNS (17), /* sdiv */
378 COSTS_N_INSNS (17), /* ddiv */
381 /* Instruction costs on RS64A processors. */
383 struct processor_costs rs64a_cost = {
384 COSTS_N_INSNS (20), /* mulsi */
385 COSTS_N_INSNS (12), /* mulsi_const */
386 COSTS_N_INSNS (8), /* mulsi_const9 */
387 COSTS_N_INSNS (34), /* muldi */
388 COSTS_N_INSNS (65), /* divsi */
389 COSTS_N_INSNS (67), /* divdi */
390 COSTS_N_INSNS (4), /* fp */
391 COSTS_N_INSNS (4), /* dmul */
392 COSTS_N_INSNS (31), /* sdiv */
393 COSTS_N_INSNS (31), /* ddiv */
396 /* Instruction costs on MPCCORE processors. */
398 struct processor_costs mpccore_cost = {
399 COSTS_N_INSNS (2), /* mulsi */
400 COSTS_N_INSNS (2), /* mulsi_const */
401 COSTS_N_INSNS (2), /* mulsi_const9 */
402 COSTS_N_INSNS (2), /* muldi */
403 COSTS_N_INSNS (6), /* divsi */
404 COSTS_N_INSNS (6), /* divdi */
405 COSTS_N_INSNS (4), /* fp */
406 COSTS_N_INSNS (5), /* dmul */
407 COSTS_N_INSNS (10), /* sdiv */
408 COSTS_N_INSNS (17), /* ddiv */
411 /* Instruction costs on PPC403 processors. */
413 struct processor_costs ppc403_cost = {
414 COSTS_N_INSNS (4), /* mulsi */
415 COSTS_N_INSNS (4), /* mulsi_const */
416 COSTS_N_INSNS (4), /* mulsi_const9 */
417 COSTS_N_INSNS (4), /* muldi */
418 COSTS_N_INSNS (33), /* divsi */
419 COSTS_N_INSNS (33), /* divdi */
420 COSTS_N_INSNS (11), /* fp */
421 COSTS_N_INSNS (11), /* dmul */
422 COSTS_N_INSNS (11), /* sdiv */
423 COSTS_N_INSNS (11), /* ddiv */
426 /* Instruction costs on PPC405 processors. */
428 struct processor_costs ppc405_cost = {
429 COSTS_N_INSNS (5), /* mulsi */
430 COSTS_N_INSNS (4), /* mulsi_const */
431 COSTS_N_INSNS (3), /* mulsi_const9 */
432 COSTS_N_INSNS (5), /* muldi */
433 COSTS_N_INSNS (35), /* divsi */
434 COSTS_N_INSNS (35), /* divdi */
435 COSTS_N_INSNS (11), /* fp */
436 COSTS_N_INSNS (11), /* dmul */
437 COSTS_N_INSNS (11), /* sdiv */
438 COSTS_N_INSNS (11), /* ddiv */
441 /* Instruction costs on PPC440 processors. */
443 struct processor_costs ppc440_cost = {
444 COSTS_N_INSNS (3), /* mulsi */
445 COSTS_N_INSNS (2), /* mulsi_const */
446 COSTS_N_INSNS (2), /* mulsi_const9 */
447 COSTS_N_INSNS (3), /* muldi */
448 COSTS_N_INSNS (34), /* divsi */
449 COSTS_N_INSNS (34), /* divdi */
450 COSTS_N_INSNS (5), /* fp */
451 COSTS_N_INSNS (5), /* dmul */
452 COSTS_N_INSNS (19), /* sdiv */
453 COSTS_N_INSNS (33), /* ddiv */
456 /* Instruction costs on PPC601 processors. */
458 struct processor_costs ppc601_cost = {
459 COSTS_N_INSNS (5), /* mulsi */
460 COSTS_N_INSNS (5), /* mulsi_const */
461 COSTS_N_INSNS (5), /* mulsi_const9 */
462 COSTS_N_INSNS (5), /* muldi */
463 COSTS_N_INSNS (36), /* divsi */
464 COSTS_N_INSNS (36), /* divdi */
465 COSTS_N_INSNS (4), /* fp */
466 COSTS_N_INSNS (5), /* dmul */
467 COSTS_N_INSNS (17), /* sdiv */
468 COSTS_N_INSNS (31), /* ddiv */
471 /* Instruction costs on PPC603 processors. */
473 struct processor_costs ppc603_cost = {
474 COSTS_N_INSNS (5), /* mulsi */
475 COSTS_N_INSNS (3), /* mulsi_const */
476 COSTS_N_INSNS (2), /* mulsi_const9 */
477 COSTS_N_INSNS (5), /* muldi */
478 COSTS_N_INSNS (37), /* divsi */
479 COSTS_N_INSNS (37), /* divdi */
480 COSTS_N_INSNS (3), /* fp */
481 COSTS_N_INSNS (4), /* dmul */
482 COSTS_N_INSNS (18), /* sdiv */
483 COSTS_N_INSNS (33), /* ddiv */
486 /* Instruction costs on PPC604 processors. */
488 struct processor_costs ppc604_cost = {
489 COSTS_N_INSNS (4), /* mulsi */
490 COSTS_N_INSNS (4), /* mulsi_const */
491 COSTS_N_INSNS (4), /* mulsi_const9 */
492 COSTS_N_INSNS (4), /* muldi */
493 COSTS_N_INSNS (20), /* divsi */
494 COSTS_N_INSNS (20), /* divdi */
495 COSTS_N_INSNS (3), /* fp */
496 COSTS_N_INSNS (3), /* dmul */
497 COSTS_N_INSNS (18), /* sdiv */
498 COSTS_N_INSNS (32), /* ddiv */
501 /* Instruction costs on PPC604e processors. */
503 struct processor_costs ppc604e_cost = {
504 COSTS_N_INSNS (2), /* mulsi */
505 COSTS_N_INSNS (2), /* mulsi_const */
506 COSTS_N_INSNS (2), /* mulsi_const9 */
507 COSTS_N_INSNS (2), /* muldi */
508 COSTS_N_INSNS (20), /* divsi */
509 COSTS_N_INSNS (20), /* divdi */
510 COSTS_N_INSNS (3), /* fp */
511 COSTS_N_INSNS (3), /* dmul */
512 COSTS_N_INSNS (18), /* sdiv */
513 COSTS_N_INSNS (32), /* ddiv */
516 /* Instruction costs on PPC620 processors. */
518 struct processor_costs ppc620_cost = {
519 COSTS_N_INSNS (5), /* mulsi */
520 COSTS_N_INSNS (4), /* mulsi_const */
521 COSTS_N_INSNS (3), /* mulsi_const9 */
522 COSTS_N_INSNS (7), /* muldi */
523 COSTS_N_INSNS (21), /* divsi */
524 COSTS_N_INSNS (37), /* divdi */
525 COSTS_N_INSNS (3), /* fp */
526 COSTS_N_INSNS (3), /* dmul */
527 COSTS_N_INSNS (18), /* sdiv */
528 COSTS_N_INSNS (32), /* ddiv */
531 /* Instruction costs on PPC630 processors. */
533 struct processor_costs ppc630_cost = {
534 COSTS_N_INSNS (5), /* mulsi */
535 COSTS_N_INSNS (4), /* mulsi_const */
536 COSTS_N_INSNS (3), /* mulsi_const9 */
537 COSTS_N_INSNS (7), /* muldi */
538 COSTS_N_INSNS (21), /* divsi */
539 COSTS_N_INSNS (37), /* divdi */
540 COSTS_N_INSNS (3), /* fp */
541 COSTS_N_INSNS (3), /* dmul */
542 COSTS_N_INSNS (17), /* sdiv */
543 COSTS_N_INSNS (21), /* ddiv */
546 /* Instruction costs on PPC750 and PPC7400 processors. */
548 struct processor_costs ppc750_cost = {
549 COSTS_N_INSNS (5), /* mulsi */
550 COSTS_N_INSNS (3), /* mulsi_const */
551 COSTS_N_INSNS (2), /* mulsi_const9 */
552 COSTS_N_INSNS (5), /* muldi */
553 COSTS_N_INSNS (17), /* divsi */
554 COSTS_N_INSNS (17), /* divdi */
555 COSTS_N_INSNS (3), /* fp */
556 COSTS_N_INSNS (3), /* dmul */
557 COSTS_N_INSNS (17), /* sdiv */
558 COSTS_N_INSNS (31), /* ddiv */
561 /* Instruction costs on PPC7450 processors. */
563 struct processor_costs ppc7450_cost = {
564 COSTS_N_INSNS (4), /* mulsi */
565 COSTS_N_INSNS (3), /* mulsi_const */
566 COSTS_N_INSNS (3), /* mulsi_const9 */
567 COSTS_N_INSNS (4), /* muldi */
568 COSTS_N_INSNS (23), /* divsi */
569 COSTS_N_INSNS (23), /* divdi */
570 COSTS_N_INSNS (5), /* fp */
571 COSTS_N_INSNS (5), /* dmul */
572 COSTS_N_INSNS (21), /* sdiv */
573 COSTS_N_INSNS (35), /* ddiv */
576 /* Instruction costs on PPC8540 processors. */
578 struct processor_costs ppc8540_cost = {
579 COSTS_N_INSNS (4), /* mulsi */
580 COSTS_N_INSNS (4), /* mulsi_const */
581 COSTS_N_INSNS (4), /* mulsi_const9 */
582 COSTS_N_INSNS (4), /* muldi */
583 COSTS_N_INSNS (19), /* divsi */
584 COSTS_N_INSNS (19), /* divdi */
585 COSTS_N_INSNS (4), /* fp */
586 COSTS_N_INSNS (4), /* dmul */
587 COSTS_N_INSNS (29), /* sdiv */
588 COSTS_N_INSNS (29), /* ddiv */
591 /* Instruction costs on POWER4 and POWER5 processors. */
593 struct processor_costs power4_cost = {
594 COSTS_N_INSNS (3), /* mulsi */
595 COSTS_N_INSNS (2), /* mulsi_const */
596 COSTS_N_INSNS (2), /* mulsi_const9 */
597 COSTS_N_INSNS (4), /* muldi */
598 COSTS_N_INSNS (18), /* divsi */
599 COSTS_N_INSNS (34), /* divdi */
600 COSTS_N_INSNS (3), /* fp */
601 COSTS_N_INSNS (3), /* dmul */
602 COSTS_N_INSNS (17), /* sdiv */
603 COSTS_N_INSNS (17), /* ddiv */
607 static bool rs6000_function_ok_for_sibcall (tree, tree);
608 static int num_insns_constant_wide (HOST_WIDE_INT);
609 static void validate_condition_mode (enum rtx_code, enum machine_mode);
610 static rtx rs6000_generate_compare (enum rtx_code);
611 static void rs6000_maybe_dead (rtx);
612 static void rs6000_emit_stack_tie (void);
613 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
614 static rtx spe_synthesize_frame_save (rtx);
615 static bool spe_func_has_64bit_regs_p (void);
616 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
618 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
619 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
620 static unsigned rs6000_hash_constant (rtx);
621 static unsigned toc_hash_function (const void *);
622 static int toc_hash_eq (const void *, const void *);
623 static int constant_pool_expr_1 (rtx, int *, int *);
624 static bool constant_pool_expr_p (rtx);
625 static bool toc_relative_expr_p (rtx);
626 static bool legitimate_small_data_p (enum machine_mode, rtx);
627 static bool legitimate_indexed_address_p (rtx, int);
628 static bool legitimate_indirect_address_p (rtx, int);
629 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
630 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
631 static struct machine_function * rs6000_init_machine_status (void);
632 static bool rs6000_assemble_integer (rtx, unsigned int, int);
633 #ifdef HAVE_GAS_HIDDEN
634 static void rs6000_assemble_visibility (tree, int);
636 static int rs6000_ra_ever_killed (void);
637 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
638 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
639 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
640 static const char *rs6000_mangle_fundamental_type (tree);
641 extern const struct attribute_spec rs6000_attribute_table[];
642 static void rs6000_set_default_type_attributes (tree);
643 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
644 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
645 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
647 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
648 static bool rs6000_return_in_memory (tree, tree);
649 static void rs6000_file_start (void);
651 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
652 static void rs6000_elf_asm_out_constructor (rtx, int);
653 static void rs6000_elf_asm_out_destructor (rtx, int);
654 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
655 static void rs6000_elf_unique_section (tree, int);
656 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
657 unsigned HOST_WIDE_INT);
658 static void rs6000_elf_encode_section_info (tree, rtx, int)
660 static bool rs6000_elf_in_small_data_p (tree);
663 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
664 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
665 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
666 static void rs6000_xcoff_unique_section (tree, int);
667 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
668 unsigned HOST_WIDE_INT);
669 static const char * rs6000_xcoff_strip_name_encoding (const char *);
670 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
671 static void rs6000_xcoff_file_start (void);
672 static void rs6000_xcoff_file_end (void);
675 static bool rs6000_binds_local_p (tree);
677 static int rs6000_variable_issue (FILE *, int, rtx, int);
678 static bool rs6000_rtx_costs (rtx, int, int, int *);
679 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
680 static bool is_microcoded_insn (rtx);
681 static int is_dispatch_slot_restricted (rtx);
682 static bool is_cracked_insn (rtx);
683 static bool is_branch_slot_insn (rtx);
684 static int rs6000_adjust_priority (rtx, int);
685 static int rs6000_issue_rate (void);
686 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
687 static rtx get_next_active_insn (rtx, rtx);
688 static bool insn_terminates_group_p (rtx , enum group_termination);
689 static bool is_costly_group (rtx *, rtx);
690 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
691 static int redefine_groups (FILE *, int, rtx, rtx);
692 static int pad_groups (FILE *, int, rtx, rtx);
693 static void rs6000_sched_finish (FILE *, int);
694 static int rs6000_use_sched_lookahead (void);
695 static tree rs6000_builtin_mask_for_load (void);
696 static tree rs6000_builtin_mask_for_store (void);
698 static void rs6000_init_builtins (void);
699 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
700 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
701 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
702 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
703 static void altivec_init_builtins (void);
704 static void rs6000_common_init_builtins (void);
705 static void rs6000_init_libfuncs (void);
707 static void enable_mask_for_builtins (struct builtin_description *, int,
708 enum rs6000_builtins,
709 enum rs6000_builtins);
710 static tree build_opaque_vector_type (tree, int);
711 static void spe_init_builtins (void);
712 static rtx spe_expand_builtin (tree, rtx, bool *);
713 static rtx spe_expand_stv_builtin (enum insn_code, tree);
714 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
715 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
716 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
717 static rs6000_stack_t *rs6000_stack_info (void);
718 static void debug_stack_info (rs6000_stack_t *);
720 static rtx altivec_expand_builtin (tree, rtx, bool *);
721 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
722 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
723 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
724 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
725 static rtx altivec_expand_predicate_builtin (enum insn_code,
726 const char *, tree, rtx);
727 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
728 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
729 static void rs6000_parse_abi_options (void);
730 static void rs6000_parse_alignment_option (void);
731 static void rs6000_parse_tls_size_option (void);
732 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
733 static void rs6000_parse_float_gprs_option (void);
734 static int first_altivec_reg_to_save (void);
735 static unsigned int compute_vrsave_mask (void);
736 static void compute_save_world_info(rs6000_stack_t *info_ptr);
737 static void is_altivec_return_reg (rtx, void *);
738 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
739 int easy_vector_constant (rtx, enum machine_mode);
740 static int easy_vector_same (rtx, enum machine_mode);
741 static int easy_vector_splat_const (int, enum machine_mode);
742 static bool is_ev64_opaque_type (tree);
743 static rtx rs6000_dwarf_register_span (rtx);
744 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
745 static rtx rs6000_tls_get_addr (void);
746 static rtx rs6000_got_sym (void);
747 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
748 static const char *rs6000_get_some_local_dynamic_name (void);
749 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
750 static rtx rs6000_complex_function_value (enum machine_mode);
751 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
752 enum machine_mode, tree);
753 static rtx rs6000_darwin64_function_arg (CUMULATIVE_ARGS *,
754 enum machine_mode, tree, int);
755 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
756 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
757 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
758 enum machine_mode, tree,
760 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
763 static void macho_branch_islands (void);
764 static void add_compiler_branch_island (tree, tree, int);
765 static int no_previous_def (tree function_name);
766 static tree get_prev_label (tree function_name);
767 static void rs6000_darwin_file_start (void);
770 static tree rs6000_build_builtin_va_list (void);
771 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
772 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
773 static bool rs6000_vector_mode_supported_p (enum machine_mode);
774 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
776 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
778 static int get_vsel_insn (enum machine_mode);
779 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
782 const int INSN_NOT_AVAILABLE = -1;
783 static enum machine_mode rs6000_eh_return_filter_mode (void);
785 /* Hash table stuff for keeping track of TOC entries. */
787 struct toc_hash_struct GTY(())
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
792 enum machine_mode key_mode;
796 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
798 /* Default register names. */
799 char rs6000_reg_names[][8] =
801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
812 /* AltiVec registers. */
813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
822 #ifdef TARGET_REGNAMES
823 static const char alt_reg_names[][8] =
825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
836 /* AltiVec registers. */
837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
847 #ifndef MASK_STRICT_ALIGN
848 #define MASK_STRICT_ALIGN 0
850 #ifndef TARGET_PROFILE_KERNEL
851 #define TARGET_PROFILE_KERNEL 0
854 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
857 /* Return 1 for a symbol ref for a thread-local storage symbol. */
858 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
859 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
861 /* Initialize the GCC target structure. */
862 #undef TARGET_ATTRIBUTE_TABLE
863 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
864 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
865 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
867 #undef TARGET_ASM_ALIGNED_DI_OP
868 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
870 /* Default unaligned ops are only provided for ELF. Find the ops needed
871 for non-ELF systems. */
872 #ifndef OBJECT_FORMAT_ELF
874 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
876 #undef TARGET_ASM_UNALIGNED_HI_OP
877 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
878 #undef TARGET_ASM_UNALIGNED_SI_OP
879 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
880 #undef TARGET_ASM_UNALIGNED_DI_OP
881 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
884 #undef TARGET_ASM_UNALIGNED_HI_OP
885 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
886 #undef TARGET_ASM_UNALIGNED_SI_OP
887 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
888 #undef TARGET_ASM_UNALIGNED_DI_OP
889 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
890 #undef TARGET_ASM_ALIGNED_DI_OP
891 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
895 /* This hook deals with fixups for relocatable code and DI-mode objects
897 #undef TARGET_ASM_INTEGER
898 #define TARGET_ASM_INTEGER rs6000_assemble_integer
900 #ifdef HAVE_GAS_HIDDEN
901 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
902 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
905 #undef TARGET_HAVE_TLS
906 #define TARGET_HAVE_TLS HAVE_AS_TLS
908 #undef TARGET_CANNOT_FORCE_CONST_MEM
909 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
911 #undef TARGET_ASM_FUNCTION_PROLOGUE
912 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
913 #undef TARGET_ASM_FUNCTION_EPILOGUE
914 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
916 #undef TARGET_SCHED_VARIABLE_ISSUE
917 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
919 #undef TARGET_SCHED_ISSUE_RATE
920 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
921 #undef TARGET_SCHED_ADJUST_COST
922 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
923 #undef TARGET_SCHED_ADJUST_PRIORITY
924 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
925 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
926 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
927 #undef TARGET_SCHED_FINISH
928 #define TARGET_SCHED_FINISH rs6000_sched_finish
930 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
931 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
933 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
934 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
936 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE
937 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE rs6000_builtin_mask_for_store
939 #undef TARGET_INIT_BUILTINS
940 #define TARGET_INIT_BUILTINS rs6000_init_builtins
942 #undef TARGET_EXPAND_BUILTIN
943 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
945 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
946 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
948 #undef TARGET_INIT_LIBFUNCS
949 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
952 #undef TARGET_BINDS_LOCAL_P
953 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
956 #undef TARGET_ASM_OUTPUT_MI_THUNK
957 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
959 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
960 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
962 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
963 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
965 #undef TARGET_RTX_COSTS
966 #define TARGET_RTX_COSTS rs6000_rtx_costs
967 #undef TARGET_ADDRESS_COST
968 #define TARGET_ADDRESS_COST hook_int_rtx_0
970 #undef TARGET_VECTOR_OPAQUE_P
971 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
973 #undef TARGET_DWARF_REGISTER_SPAN
974 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
976 /* On rs6000, function arguments are promoted, as are function return
978 #undef TARGET_PROMOTE_FUNCTION_ARGS
979 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
980 #undef TARGET_PROMOTE_FUNCTION_RETURN
981 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
983 #undef TARGET_RETURN_IN_MEMORY
984 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
986 #undef TARGET_SETUP_INCOMING_VARARGS
987 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
989 /* Always strict argument naming on rs6000. */
990 #undef TARGET_STRICT_ARGUMENT_NAMING
991 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
992 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
993 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
994 #undef TARGET_SPLIT_COMPLEX_ARG
995 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
996 #undef TARGET_MUST_PASS_IN_STACK
997 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
998 #undef TARGET_PASS_BY_REFERENCE
999 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1001 #undef TARGET_BUILD_BUILTIN_VA_LIST
1002 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1004 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1005 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1007 #undef TARGET_EH_RETURN_FILTER_MODE
1008 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1010 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1011 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1013 struct gcc_target targetm = TARGET_INITIALIZER;
1016 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1019 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1021 /* The GPRs can hold any mode, but values bigger than one register
1022 cannot go past R31. */
1023 if (INT_REGNO_P (regno))
1024 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1026 /* The float registers can only hold floating modes and DImode. */
1027 if (FP_REGNO_P (regno))
1029 (GET_MODE_CLASS (mode) == MODE_FLOAT
1030 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1031 || (GET_MODE_CLASS (mode) == MODE_INT
1032 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1034 /* The CR register can only hold CC modes. */
1035 if (CR_REGNO_P (regno))
1036 return GET_MODE_CLASS (mode) == MODE_CC;
1038 if (XER_REGNO_P (regno))
1039 return mode == PSImode;
1041 /* AltiVec only in AldyVec registers. */
1042 if (ALTIVEC_REGNO_P (regno))
1043 return ALTIVEC_VECTOR_MODE (mode);
1045 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1046 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1049 /* We cannot put TImode anywhere except general register and it must be
1050 able to fit within the register set. */
1052 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1055 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1057 rs6000_init_hard_regno_mode_ok (void)
1061 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1062 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1063 if (rs6000_hard_regno_mode_ok (r, m))
1064 rs6000_hard_regno_mode_ok_p[m][r] = true;
1067 /* If not otherwise specified by a target, make 'long double' equivalent to
1070 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1071 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1074 /* Override command line options. Mostly we process the processor
1075 type and sometimes adjust other TARGET_ options. */
1078 rs6000_override_options (const char *default_cpu)
1081 struct rs6000_cpu_select *ptr;
1084 /* Simplifications for entries below. */
1087 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1088 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1091 /* This table occasionally claims that a processor does not support
1092 a particular feature even though it does, but the feature is slower
1093 than the alternative. Thus, it shouldn't be relied on as a
1094 complete description of the processor's support.
1096 Please keep this list in order, and don't forget to update the
1097 documentation in invoke.texi when adding a new processor or
1101 const char *const name; /* Canonical processor name. */
1102 const enum processor_type processor; /* Processor type enum value. */
1103 const int target_enable; /* Target flags to enable. */
1104 } const processor_target_table[]
1105 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1106 {"403", PROCESSOR_PPC403,
1107 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1108 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1109 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1110 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1111 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1112 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1113 {"601", PROCESSOR_PPC601,
1114 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1115 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1116 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1117 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1118 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1119 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1120 {"620", PROCESSOR_PPC620,
1121 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1122 {"630", PROCESSOR_PPC630,
1123 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1124 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1126 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1127 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1129 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1130 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1131 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1132 /* 8548 has a dummy entry for now. */
1133 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1135 {"970", PROCESSOR_POWER4,
1136 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1137 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1138 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1140 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1141 {"G5", PROCESSOR_POWER4,
1142 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1143 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1144 {"power2", PROCESSOR_POWER,
1145 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1146 {"power3", PROCESSOR_PPC630,
1147 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1148 {"power4", PROCESSOR_POWER4,
1149 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1150 {"power5", PROCESSOR_POWER5,
1151 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1153 {"powerpc64", PROCESSOR_POWERPC64,
1154 POWERPC_BASE_MASK | MASK_POWERPC64},
1155 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1156 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1157 {"rios2", PROCESSOR_RIOS2,
1158 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1159 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1160 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1161 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1164 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1166 /* Some OSs don't support saving the high part of 64-bit registers on
1167 context switch. Other OSs don't support saving Altivec registers.
1168 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1169 settings; if the user wants either, the user must explicitly specify
1170 them and we won't interfere with the user's specification. */
1173 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1174 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1175 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1179 rs6000_init_hard_regno_mode_ok ();
1181 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1182 #ifdef OS_MISSING_POWERPC64
1183 if (OS_MISSING_POWERPC64)
1184 set_masks &= ~MASK_POWERPC64;
1186 #ifdef OS_MISSING_ALTIVEC
1187 if (OS_MISSING_ALTIVEC)
1188 set_masks &= ~MASK_ALTIVEC;
1191 /* Don't override these by the processor default if given explicitly. */
1192 set_masks &= ~(target_flags_explicit
1193 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
1195 /* Identify the processor type. */
1196 rs6000_select[0].string = default_cpu;
1197 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1199 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1201 ptr = &rs6000_select[i];
1202 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1204 for (j = 0; j < ptt_size; j++)
1205 if (! strcmp (ptr->string, processor_target_table[j].name))
1207 if (ptr->set_tune_p)
1208 rs6000_cpu = processor_target_table[j].processor;
1210 if (ptr->set_arch_p)
1212 target_flags &= ~set_masks;
1213 target_flags |= (processor_target_table[j].target_enable
1220 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1227 /* If we are optimizing big endian systems for space, use the load/store
1228 multiple and string instructions. */
1229 if (BYTES_BIG_ENDIAN && optimize_size)
1230 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1232 /* Don't allow -mmultiple or -mstring on little endian systems
1233 unless the cpu is a 750, because the hardware doesn't support the
1234 instructions used in little endian mode, and causes an alignment
1235 trap. The 750 does not cause an alignment trap (except when the
1236 target is unaligned). */
1238 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1240 if (TARGET_MULTIPLE)
1242 target_flags &= ~MASK_MULTIPLE;
1243 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1244 warning ("-mmultiple is not supported on little endian systems");
1249 target_flags &= ~MASK_STRING;
1250 if ((target_flags_explicit & MASK_STRING) != 0)
1251 warning ("-mstring is not supported on little endian systems");
1255 /* Set debug flags */
1256 if (rs6000_debug_name)
1258 if (! strcmp (rs6000_debug_name, "all"))
1259 rs6000_debug_stack = rs6000_debug_arg = 1;
1260 else if (! strcmp (rs6000_debug_name, "stack"))
1261 rs6000_debug_stack = 1;
1262 else if (! strcmp (rs6000_debug_name, "arg"))
1263 rs6000_debug_arg = 1;
1265 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1268 if (rs6000_traceback_name)
1270 if (! strncmp (rs6000_traceback_name, "full", 4))
1271 rs6000_traceback = traceback_full;
1272 else if (! strncmp (rs6000_traceback_name, "part", 4))
1273 rs6000_traceback = traceback_part;
1274 else if (! strncmp (rs6000_traceback_name, "no", 2))
1275 rs6000_traceback = traceback_none;
1277 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1278 rs6000_traceback_name);
1281 /* Set size of long double */
1282 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1283 if (rs6000_long_double_size_string)
1286 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1287 if (*tail != '\0' || (size != 64 && size != 128))
1288 error ("Unknown switch -mlong-double-%s",
1289 rs6000_long_double_size_string);
1291 rs6000_long_double_type_size = size;
1294 /* Set Altivec ABI as default for powerpc64 linux. */
1295 if (TARGET_ELF && TARGET_64BIT)
1297 rs6000_altivec_abi = 1;
1298 rs6000_altivec_vrsave = 1;
1301 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1302 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1304 rs6000_darwin64_abi = 1;
1305 /* Setting to empty string is same as "-mone-byte-bool". */
1306 darwin_one_byte_bool = "";
1309 /* Handle -mabi= options. */
1310 rs6000_parse_abi_options ();
1312 /* Handle -malign-XXXXX option. */
1313 rs6000_parse_alignment_option ();
1315 rs6000_parse_float_gprs_option ();
1317 /* Handle generic -mFOO=YES/NO options. */
1318 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1319 &rs6000_altivec_vrsave);
1320 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1322 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1324 /* Handle -mtls-size option. */
1325 rs6000_parse_tls_size_option ();
1327 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1328 SUBTARGET_OVERRIDE_OPTIONS;
1330 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1331 SUBSUBTARGET_OVERRIDE_OPTIONS;
1333 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1334 SUB3TARGET_OVERRIDE_OPTIONS;
1340 error ("AltiVec and E500 instructions cannot coexist");
1342 /* The e500 does not have string instructions, and we set
1343 MASK_STRING above when optimizing for size. */
1344 if ((target_flags & MASK_STRING) != 0)
1345 target_flags = target_flags & ~MASK_STRING;
1347 /* No SPE means 64-bit long doubles, even if an E500. */
1348 if (rs6000_spe_string != 0
1349 && !strcmp (rs6000_spe_string, "no"))
1350 rs6000_long_double_type_size = 64;
1352 else if (rs6000_select[1].string != NULL)
1354 /* For the powerpc-eabispe configuration, we set all these by
1355 default, so let's unset them if we manually set another
1356 CPU that is not the E500. */
1357 if (rs6000_abi_string == 0)
1359 if (rs6000_spe_string == 0)
1361 if (rs6000_float_gprs_string == 0)
1362 rs6000_float_gprs = 0;
1363 if (rs6000_isel_string == 0)
1365 if (rs6000_long_double_size_string == 0)
1366 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1369 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1370 && rs6000_cpu != PROCESSOR_POWER5);
1371 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1372 || rs6000_cpu == PROCESSOR_POWER5);
1374 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1375 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1376 bits in target_flags so TARGET_SWITCHES cannot be used.
1377 Assumption here is that rs6000_longcall_switch points into the
1378 text of the complete option, rather than being a copy, so we can
1379 scan back for the presence or absence of the no- modifier. */
1380 if (rs6000_longcall_switch)
1382 const char *base = rs6000_longcall_switch;
1383 while (base[-1] != 'm') base--;
1385 if (*rs6000_longcall_switch != '\0')
1386 error ("invalid option %qs", base);
1387 rs6000_default_long_calls = (base[0] != 'n');
1390 /* Handle -m(no-)warn-altivec-long similarly. */
1391 if (rs6000_warn_altivec_long_switch)
1393 const char *base = rs6000_warn_altivec_long_switch;
1394 while (base[-1] != 'm') base--;
1396 if (*rs6000_warn_altivec_long_switch != '\0')
1397 error ("invalid option %qs", base);
1398 rs6000_warn_altivec_long = (base[0] != 'n');
1401 /* Handle -mprioritize-restricted-insns option. */
1402 rs6000_sched_restricted_insns_priority
1403 = (rs6000_sched_groups ? 1 : 0);
1404 if (rs6000_sched_restricted_insns_priority_str)
1405 rs6000_sched_restricted_insns_priority =
1406 atoi (rs6000_sched_restricted_insns_priority_str);
1408 /* Handle -msched-costly-dep option. */
1409 rs6000_sched_costly_dep
1410 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1411 if (rs6000_sched_costly_dep_str)
1413 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1414 rs6000_sched_costly_dep = no_dep_costly;
1415 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1416 rs6000_sched_costly_dep = all_deps_costly;
1417 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1418 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1419 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1420 rs6000_sched_costly_dep = store_to_load_dep_costly;
1422 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1425 /* Handle -minsert-sched-nops option. */
1426 rs6000_sched_insert_nops
1427 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1428 if (rs6000_sched_insert_nops_str)
1430 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1431 rs6000_sched_insert_nops = sched_finish_none;
1432 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1433 rs6000_sched_insert_nops = sched_finish_pad_groups;
1434 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1435 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1437 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1440 #ifdef TARGET_REGNAMES
1441 /* If the user desires alternate register names, copy in the
1442 alternate names now. */
1443 if (TARGET_REGNAMES)
1444 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1447 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1448 If -maix-struct-return or -msvr4-struct-return was explicitly
1449 used, don't override with the ABI default. */
1450 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1452 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1453 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1455 target_flags |= MASK_AIX_STRUCT_RET;
1458 if (TARGET_LONG_DOUBLE_128
1459 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1460 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1462 /* Allocate an alias set for register saves & restores from stack. */
1463 rs6000_sr_alias_set = new_alias_set ();
1466 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1468 /* We can only guarantee the availability of DI pseudo-ops when
1469 assembling for 64-bit targets. */
1472 targetm.asm_out.aligned_op.di = NULL;
1473 targetm.asm_out.unaligned_op.di = NULL;
1476 /* Set branch target alignment, if not optimizing for size. */
1479 if (rs6000_sched_groups)
1481 if (align_functions <= 0)
1482 align_functions = 16;
1483 if (align_jumps <= 0)
1485 if (align_loops <= 0)
1488 if (align_jumps_max_skip <= 0)
1489 align_jumps_max_skip = 15;
1490 if (align_loops_max_skip <= 0)
1491 align_loops_max_skip = 15;
1494 /* Arrange to save and restore machine status around nested functions. */
1495 init_machine_status = rs6000_init_machine_status;
1497 /* We should always be splitting complex arguments, but we can't break
1498 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1499 if (DEFAULT_ABI != ABI_AIX)
1500 targetm.calls.split_complex_arg = NULL;
1502 /* Initialize rs6000_cost with the appropriate target costs. */
1504 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1508 case PROCESSOR_RIOS1:
1509 rs6000_cost = &rios1_cost;
1512 case PROCESSOR_RIOS2:
1513 rs6000_cost = &rios2_cost;
1516 case PROCESSOR_RS64A:
1517 rs6000_cost = &rs64a_cost;
1520 case PROCESSOR_MPCCORE:
1521 rs6000_cost = &mpccore_cost;
1524 case PROCESSOR_PPC403:
1525 rs6000_cost = &ppc403_cost;
1528 case PROCESSOR_PPC405:
1529 rs6000_cost = &ppc405_cost;
1532 case PROCESSOR_PPC440:
1533 rs6000_cost = &ppc440_cost;
1536 case PROCESSOR_PPC601:
1537 rs6000_cost = &ppc601_cost;
1540 case PROCESSOR_PPC603:
1541 rs6000_cost = &ppc603_cost;
1544 case PROCESSOR_PPC604:
1545 rs6000_cost = &ppc604_cost;
1548 case PROCESSOR_PPC604e:
1549 rs6000_cost = &ppc604e_cost;
1552 case PROCESSOR_PPC620:
1553 rs6000_cost = &ppc620_cost;
1556 case PROCESSOR_PPC630:
1557 rs6000_cost = &ppc630_cost;
1560 case PROCESSOR_PPC750:
1561 case PROCESSOR_PPC7400:
1562 rs6000_cost = &ppc750_cost;
1565 case PROCESSOR_PPC7450:
1566 rs6000_cost = &ppc7450_cost;
1569 case PROCESSOR_PPC8540:
1570 rs6000_cost = &ppc8540_cost;
1573 case PROCESSOR_POWER4:
1574 case PROCESSOR_POWER5:
1575 rs6000_cost = &power4_cost;
1583 /* Implement targetm.vectorize.builtin_mask_for_load. */
1585 rs6000_builtin_mask_for_load (void)
1588 return altivec_builtin_mask_for_load;
1593 /* Implement targetm.vectorize.builtin_mask_for_store. */
1595 rs6000_builtin_mask_for_store (void)
1598 return altivec_builtin_mask_for_store;
1603 /* Handle generic options of the form -mfoo=yes/no.
1604 NAME is the option name.
1605 VALUE is the option value.
1606 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1607 whether the option value is 'yes' or 'no' respectively. */
1609 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1613 else if (!strcmp (value, "yes"))
1615 else if (!strcmp (value, "no"))
1618 error ("unknown -m%s= option specified: '%s'", name, value);
1621 /* Handle -mabi= options. */
1623 rs6000_parse_abi_options (void)
1625 if (rs6000_abi_string == 0)
1627 else if (! strcmp (rs6000_abi_string, "altivec"))
1629 rs6000_altivec_abi = 1;
1632 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1633 rs6000_altivec_abi = 0;
1634 else if (! strcmp (rs6000_abi_string, "spe"))
1637 rs6000_altivec_abi = 0;
1638 if (!TARGET_SPE_ABI)
1639 error ("not configured for ABI: '%s'", rs6000_abi_string);
1642 /* These are here for testing during development only, do not
1643 document in the manual please. */
1644 else if (! strcmp (rs6000_abi_string, "d64"))
1646 rs6000_darwin64_abi = 1;
1647 warning ("Using darwin64 ABI");
1649 else if (! strcmp (rs6000_abi_string, "d32"))
1651 rs6000_darwin64_abi = 0;
1652 warning ("Using old darwin ABI");
1655 else if (! strcmp (rs6000_abi_string, "no-spe"))
1658 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1661 /* Handle -mfloat-gprs= options. */
1663 rs6000_parse_float_gprs_option (void)
1665 if (rs6000_float_gprs_string == 0)
1667 else if (! strcmp (rs6000_float_gprs_string, "yes")
1668 || ! strcmp (rs6000_float_gprs_string, "single"))
1669 rs6000_float_gprs = 1;
1670 else if (! strcmp (rs6000_float_gprs_string, "double"))
1671 rs6000_float_gprs = 2;
1672 else if (! strcmp (rs6000_float_gprs_string, "no"))
1673 rs6000_float_gprs = 0;
1675 error ("invalid option for -mfloat-gprs");
1678 /* Handle -malign-XXXXXX options. */
1680 rs6000_parse_alignment_option (void)
1682 if (rs6000_alignment_string == 0)
1684 else if (! strcmp (rs6000_alignment_string, "power"))
1685 rs6000_alignment_flags = MASK_ALIGN_POWER;
1686 else if (! strcmp (rs6000_alignment_string, "natural"))
1687 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1689 error ("unknown -malign-XXXXX option specified: '%s'",
1690 rs6000_alignment_string);
1693 /* Validate and record the size specified with the -mtls-size option. */
1696 rs6000_parse_tls_size_option (void)
1698 if (rs6000_tls_size_string == 0)
1700 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1701 rs6000_tls_size = 16;
1702 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1703 rs6000_tls_size = 32;
1704 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1705 rs6000_tls_size = 64;
1707 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1711 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1715 /* Do anything needed at the start of the asm file. */
1718 rs6000_file_start (void)
1722 const char *start = buffer;
1723 struct rs6000_cpu_select *ptr;
1724 const char *default_cpu = TARGET_CPU_DEFAULT;
1725 FILE *file = asm_out_file;
1727 default_file_start ();
1729 #ifdef TARGET_BI_ARCH
1730 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1734 if (flag_verbose_asm)
1736 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1737 rs6000_select[0].string = default_cpu;
1739 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1741 ptr = &rs6000_select[i];
1742 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1744 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1749 #ifdef USING_ELFOS_H
1750 switch (rs6000_sdata)
1752 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1753 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1754 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1755 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1758 if (rs6000_sdata && g_switch_value)
1760 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1772 /* Return nonzero if this function is known to have a null epilogue. */
1775 direct_return (void)
1777 if (reload_completed)
1779 rs6000_stack_t *info = rs6000_stack_info ();
1781 if (info->first_gp_reg_save == 32
1782 && info->first_fp_reg_save == 64
1783 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1784 && ! info->lr_save_p
1785 && ! info->cr_save_p
1786 && info->vrsave_mask == 0
1794 /* Returns 1 always. */
1797 any_operand (rtx op ATTRIBUTE_UNUSED,
1798 enum machine_mode mode ATTRIBUTE_UNUSED)
1803 /* Returns 1 always. */
1806 any_parallel_operand (rtx op ATTRIBUTE_UNUSED,
1807 enum machine_mode mode ATTRIBUTE_UNUSED)
1812 /* Returns 1 if op is the count register. */
1815 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1817 if (GET_CODE (op) != REG)
1820 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1823 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1829 /* Returns 1 if op is an altivec register. */
1832 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1834 return (register_operand (op, mode)
1835 && (GET_CODE (op) != REG
1836 || REGNO (op) > FIRST_PSEUDO_REGISTER
1837 || ALTIVEC_REGNO_P (REGNO (op))));
1841 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1843 if (GET_CODE (op) != REG)
1846 if (XER_REGNO_P (REGNO (op)))
1852 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1853 by such constants completes more quickly. */
1856 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1858 return (GET_CODE (op) == CONST_INT
1859 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1862 /* Return 1 if OP is a constant that can fit in a D field. */
1865 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1867 return (GET_CODE (op) == CONST_INT
1868 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1871 /* Similar for an unsigned D field. */
1874 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1876 return (GET_CODE (op) == CONST_INT
1877 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1880 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1883 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1885 return (GET_CODE (op) == CONST_INT
1886 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1889 /* Returns 1 if OP is a CONST_INT that is a positive value
1890 and an exact power of 2. */
1893 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1895 return (GET_CODE (op) == CONST_INT
1897 && exact_log2 (INTVAL (op)) >= 0);
1900 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1904 gpc_reg_operand (rtx op, enum machine_mode mode)
1906 return (register_operand (op, mode)
1907 && (GET_CODE (op) != REG
1908 || (REGNO (op) >= ARG_POINTER_REGNUM
1909 && !XER_REGNO_P (REGNO (op)))
1910 || REGNO (op) < MQ_REGNO));
1913 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1917 cc_reg_operand (rtx op, enum machine_mode mode)
1919 return (register_operand (op, mode)
1920 && (GET_CODE (op) != REG
1921 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1922 || CR_REGNO_P (REGNO (op))));
1925 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1926 CR field that isn't CR0. */
1929 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1931 return (register_operand (op, mode)
1932 && (GET_CODE (op) != REG
1933 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1934 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1937 /* Returns 1 if OP is either a constant integer valid for a D-field or
1938 a non-special register. If a register, it must be in the proper
1939 mode unless MODE is VOIDmode. */
1942 reg_or_short_operand (rtx op, enum machine_mode mode)
1944 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1947 /* Similar, except check if the negation of the constant would be
1948 valid for a D-field. Don't allow a constant zero, since all the
1949 patterns that call this predicate use "addic r1,r2,-constant" on
1950 a constant value to set a carry when r2 is greater or equal to
1951 "constant". That doesn't work for zero. */
1954 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1956 if (GET_CODE (op) == CONST_INT)
1957 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
1959 return gpc_reg_operand (op, mode);
1962 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1963 a non-special register. If a register, it must be in the proper
1964 mode unless MODE is VOIDmode. */
1967 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1969 if (gpc_reg_operand (op, mode))
1971 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1978 /* Return 1 if the operand is either a register or an integer whose
1979 high-order 16 bits are zero. */
1982 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1984 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1987 /* Return 1 is the operand is either a non-special register or ANY
1988 constant integer. */
1991 reg_or_cint_operand (rtx op, enum machine_mode mode)
1993 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1996 /* Return 1 is the operand is either a non-special register or ANY
1997 32-bit signed constant integer. */
2000 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
2002 return (gpc_reg_operand (op, mode)
2003 || (GET_CODE (op) == CONST_INT
2004 #if HOST_BITS_PER_WIDE_INT != 32
2005 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
2006 < (unsigned HOST_WIDE_INT) 0x100000000ll)
2011 /* Return 1 is the operand is either a non-special register or a 32-bit
2012 signed constant integer valid for 64-bit addition. */
2015 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
2017 return (gpc_reg_operand (op, mode)
2018 || (GET_CODE (op) == CONST_INT
2019 #if HOST_BITS_PER_WIDE_INT == 32
2020 && INTVAL (op) < 0x7fff8000
2022 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
2028 /* Return 1 is the operand is either a non-special register or a 32-bit
2029 signed constant integer valid for 64-bit subtraction. */
2032 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
2034 return (gpc_reg_operand (op, mode)
2035 || (GET_CODE (op) == CONST_INT
2036 #if HOST_BITS_PER_WIDE_INT == 32
2037 && (- INTVAL (op)) < 0x7fff8000
2039 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
2045 /* Return 1 is the operand is either a non-special register or ANY
2046 32-bit unsigned constant integer. */
2049 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
2051 if (GET_CODE (op) == CONST_INT)
2053 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
2055 if (GET_MODE_BITSIZE (mode) <= 32)
2058 if (INTVAL (op) < 0)
2062 return ((INTVAL (op) & GET_MODE_MASK (mode)
2063 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
2065 else if (GET_CODE (op) == CONST_DOUBLE)
2067 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2071 return CONST_DOUBLE_HIGH (op) == 0;
2074 return gpc_reg_operand (op, mode);
2077 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2080 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2082 return (GET_CODE (op) == SYMBOL_REF
2083 || GET_CODE (op) == CONST
2084 || GET_CODE (op) == LABEL_REF);
2087 /* Return 1 if the operand is a simple references that can be loaded via
2088 the GOT (labels involving addition aren't allowed). */
2091 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2093 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
2096 /* Return the number of instructions it takes to form a constant in an
2097 integer register. */
2100 num_insns_constant_wide (HOST_WIDE_INT value)
2102 /* signed constant loadable with {cal|addi} */
2103 if (CONST_OK_FOR_LETTER_P (value, 'I'))
2106 /* constant loadable with {cau|addis} */
2107 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2110 #if HOST_BITS_PER_WIDE_INT == 64
2111 else if (TARGET_POWERPC64)
2113 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2114 HOST_WIDE_INT high = value >> 31;
2116 if (high == 0 || high == -1)
2122 return num_insns_constant_wide (high) + 1;
2124 return (num_insns_constant_wide (high)
2125 + num_insns_constant_wide (low) + 1);
2134 num_insns_constant (rtx op, enum machine_mode mode)
2136 if (GET_CODE (op) == CONST_INT)
2138 #if HOST_BITS_PER_WIDE_INT == 64
2139 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2140 && mask64_operand (op, mode))
2144 return num_insns_constant_wide (INTVAL (op));
2147 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
2152 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2153 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2154 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2157 else if (GET_CODE (op) == CONST_DOUBLE)
2163 int endian = (WORDS_BIG_ENDIAN == 0);
2165 if (mode == VOIDmode || mode == DImode)
2167 high = CONST_DOUBLE_HIGH (op);
2168 low = CONST_DOUBLE_LOW (op);
2172 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2173 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2175 low = l[1 - endian];
2179 return (num_insns_constant_wide (low)
2180 + num_insns_constant_wide (high));
2184 if (high == 0 && low >= 0)
2185 return num_insns_constant_wide (low);
2187 else if (high == -1 && low < 0)
2188 return num_insns_constant_wide (low);
2190 else if (mask64_operand (op, mode))
2194 return num_insns_constant_wide (high) + 1;
2197 return (num_insns_constant_wide (high)
2198 + num_insns_constant_wide (low) + 1);
2206 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2207 register with one instruction per word. We only do this if we can
2208 safely read CONST_DOUBLE_{LOW,HIGH}. */
2211 easy_fp_constant (rtx op, enum machine_mode mode)
2213 if (GET_CODE (op) != CONST_DOUBLE
2214 || GET_MODE (op) != mode
2215 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
2218 /* Consider all constants with -msoft-float to be easy. */
2219 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
2223 /* If we are using V.4 style PIC, consider all constants to be hard. */
2224 if (flag_pic && DEFAULT_ABI == ABI_V4)
2227 #ifdef TARGET_RELOCATABLE
2228 /* Similarly if we are using -mrelocatable, consider all constants
2230 if (TARGET_RELOCATABLE)
2239 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2240 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
2242 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2243 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
2244 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
2245 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
2248 else if (mode == DFmode)
2253 if (TARGET_E500_DOUBLE)
2256 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2257 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
2259 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2260 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
2263 else if (mode == SFmode)
2268 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2269 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2271 return num_insns_constant_wide (l) == 1;
2274 else if (mode == DImode)
2275 return ((TARGET_POWERPC64
2276 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
2277 || (num_insns_constant (op, DImode) <= 2));
2279 else if (mode == SImode)
2285 /* Returns the constant for the splat instruction, if exists. */
2288 easy_vector_splat_const (int cst, enum machine_mode mode)
2293 if (EASY_VECTOR_15 (cst)
2294 || EASY_VECTOR_15_ADD_SELF (cst))
2296 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2302 if (EASY_VECTOR_15 (cst)
2303 || EASY_VECTOR_15_ADD_SELF (cst))
2305 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2311 if (EASY_VECTOR_15 (cst)
2312 || EASY_VECTOR_15_ADD_SELF (cst))
2321 /* Return nonzero if all elements of a vector have the same value. */
2324 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2328 units = CONST_VECTOR_NUNITS (op);
2330 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2331 for (i = 1; i < units; ++i)
2332 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2334 if (i == units && easy_vector_splat_const (cst, mode))
2339 /* Return 1 if the operand is a CONST_INT and can be put into a
2340 register without using memory. */
2343 easy_vector_constant (rtx op, enum machine_mode mode)
2347 if (GET_CODE (op) != CONST_VECTOR
2352 if (zero_constant (op, mode)
2353 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
2354 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
2357 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2360 if (TARGET_SPE && mode == V1DImode)
2363 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2364 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
2366 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2368 evmergelo r0, r0, r0
2371 I don't know how efficient it would be to allow bigger constants,
2372 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2373 instructions is better than a 64-bit memory load, but I don't
2374 have the e500 timing specs. */
2375 if (TARGET_SPE && mode == V2SImode
2376 && cst >= -0x7fff && cst <= 0x7fff
2377 && cst2 >= -0x7fff && cst2 <= 0x7fff)
2381 && easy_vector_same (op, mode))
2383 cst = easy_vector_splat_const (cst, mode);
2384 if (EASY_VECTOR_15_ADD_SELF (cst)
2385 || EASY_VECTOR_15 (cst))
2391 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2394 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
2398 && GET_CODE (op) == CONST_VECTOR
2399 && easy_vector_same (op, mode))
2401 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
2402 if (EASY_VECTOR_15_ADD_SELF (cst))
2408 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2411 gen_easy_vector_constant_add_self (rtx op)
2415 units = GET_MODE_NUNITS (GET_MODE (op));
2416 v = rtvec_alloc (units);
2418 for (i = 0; i < units; i++)
2420 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2421 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2425 output_vec_const_move (rtx *operands)
2428 enum machine_mode mode;
2434 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2435 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2436 mode = GET_MODE (dest);
2440 if (zero_constant (vec, mode))
2441 return "vxor %0,%0,%0";
2442 else if (easy_vector_constant (vec, mode))
2444 operands[1] = GEN_INT (cst);
2448 if (EASY_VECTOR_15 (cst))
2450 operands[1] = GEN_INT (cst);
2451 return "vspltisw %0,%1";
2453 else if (EASY_VECTOR_15_ADD_SELF (cst))
2459 if (EASY_VECTOR_15 (cst))
2461 operands[1] = GEN_INT (cst);
2462 return "vspltish %0,%1";
2464 else if (EASY_VECTOR_15_ADD_SELF (cst))
2470 if (EASY_VECTOR_15 (cst))
2472 operands[1] = GEN_INT (cst);
2473 return "vspltisb %0,%1";
2475 else if (EASY_VECTOR_15_ADD_SELF (cst))
2488 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2489 pattern of V1DI, V4HI, and V2SF.
2491 FIXME: We should probably return # and add post reload
2492 splitters for these, but this way is so easy ;-). */
2493 operands[1] = GEN_INT (cst);
2494 operands[2] = GEN_INT (cst2);
2496 return "li %0,%1\n\tevmergelo %0,%0,%0";
2498 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2504 /* Return 1 if the operand is the constant 0. This works for scalars
2505 as well as vectors. */
2507 zero_constant (rtx op, enum machine_mode mode)
2509 return op == CONST0_RTX (mode);
2512 /* Return 1 if the operand is 0.0. */
2514 zero_fp_constant (rtx op, enum machine_mode mode)
2516 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
2519 /* Return 1 if the operand is in volatile memory. Note that during
2520 the RTL generation phase, memory_operand does not return TRUE for
2521 volatile memory references. So this function allows us to
2522 recognize volatile references where its safe. */
2525 volatile_mem_operand (rtx op, enum machine_mode mode)
2527 if (GET_CODE (op) != MEM)
2530 if (!MEM_VOLATILE_P (op))
2533 if (mode != GET_MODE (op))
2536 if (reload_completed)
2537 return memory_operand (op, mode);
2539 if (reload_in_progress)
2540 return strict_memory_address_p (mode, XEXP (op, 0));
2542 return memory_address_p (mode, XEXP (op, 0));
2545 /* Return 1 if the operand is an offsettable memory operand. */
2548 offsettable_mem_operand (rtx op, enum machine_mode mode)
2550 return ((GET_CODE (op) == MEM)
2551 && offsettable_address_p (reload_completed || reload_in_progress,
2552 mode, XEXP (op, 0)));
2555 /* Return 1 if the operand is either an easy FP constant (see above) or
2559 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
2561 return memory_operand (op, mode) || easy_fp_constant (op, mode);
2564 /* Return 1 if the operand is either a non-special register or an item
2565 that can be used as the operand of a `mode' add insn. */
2568 add_operand (rtx op, enum machine_mode mode)
2570 if (GET_CODE (op) == CONST_INT)
2571 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2572 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2574 return gpc_reg_operand (op, mode);
2577 /* Return 1 if OP is a constant but not a valid add_operand. */
2580 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2582 return (GET_CODE (op) == CONST_INT
2583 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2584 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2587 /* Return 1 if the operand is a non-special register or a constant that
2588 can be used as the operand of an OR or XOR insn on the RS/6000. */
2591 logical_operand (rtx op, enum machine_mode mode)
2593 HOST_WIDE_INT opl, oph;
2595 if (gpc_reg_operand (op, mode))
2598 if (GET_CODE (op) == CONST_INT)
2600 opl = INTVAL (op) & GET_MODE_MASK (mode);
2602 #if HOST_BITS_PER_WIDE_INT <= 32
2603 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
2607 else if (GET_CODE (op) == CONST_DOUBLE)
2609 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2612 opl = CONST_DOUBLE_LOW (op);
2613 oph = CONST_DOUBLE_HIGH (op);
2620 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2621 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2624 /* Return 1 if C is a constant that is not a logical operand (as
2625 above), but could be split into one. */
2628 non_logical_cint_operand (rtx op, enum machine_mode mode)
2630 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2631 && ! logical_operand (op, mode)
2632 && reg_or_logical_cint_operand (op, mode));
2635 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2636 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2637 Reject all ones and all zeros, since these should have been optimized
2638 away and confuse the making of MB and ME. */
2641 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2643 HOST_WIDE_INT c, lsb;
2645 if (GET_CODE (op) != CONST_INT)
2650 /* Fail in 64-bit mode if the mask wraps around because the upper
2651 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2652 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2655 /* We don't change the number of transitions by inverting,
2656 so make sure we start with the LS bit zero. */
2660 /* Reject all zeros or all ones. */
2664 /* Find the first transition. */
2667 /* Invert to look for a second transition. */
2670 /* Erase first transition. */
2673 /* Find the second transition (if any). */
2676 /* Match if all the bits above are 1's (or c is zero). */
2680 /* Return 1 for the PowerPC64 rlwinm corner case. */
2683 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2685 HOST_WIDE_INT c, lsb;
2687 if (GET_CODE (op) != CONST_INT)
2692 if ((c & 0x80000001) != 0x80000001)
2706 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2707 It is if there are no more than one 1->0 or 0->1 transitions.
2708 Reject all zeros, since zero should have been optimized away and
2709 confuses the making of MB and ME. */
2712 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2714 if (GET_CODE (op) == CONST_INT)
2716 HOST_WIDE_INT c, lsb;
2720 /* Reject all zeros. */
2724 /* We don't change the number of transitions by inverting,
2725 so make sure we start with the LS bit zero. */
2729 /* Find the transition, and check that all bits above are 1's. */
2732 /* Match if all the bits above are 1's (or c is zero). */
2739 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2742 if (GET_CODE (op) == CONST_INT)
2744 HOST_WIDE_INT c, lsb;
2749 /* Disallow all zeros. */
2753 /* We can use a single rlwinm insn if no upper bits of C are set
2754 AND there are zero, one or two transitions in the _whole_ of
2756 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2758 /* We don't change the number of transitions by inverting,
2759 so make sure we start with the LS bit zero. */
2763 /* Find the first transition. */
2766 /* Invert to look for a second transition. */
2769 /* Erase first transition. */
2772 /* Find the second transition. */
2775 /* Invert to look for a third transition. */
2778 /* Erase second transition. */
2781 if (one_ok && !(allow_one || c))
2784 /* Find the third transition (if any). */
2787 /* Match if all the bits above are 1's (or c is zero). */
2793 /* Like mask64_operand, but allow up to three transitions. This
2794 predicate is used by insn patterns that generate two rldicl or
2795 rldicr machine insns. */
2796 int mask64_2_operand (rtx op, enum machine_mode mode)
2798 return mask64_1or2_operand (op, mode, false);
2801 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2802 implement ANDing by the mask IN. */
2804 build_mask64_2_operands (rtx in, rtx *out)
2806 #if HOST_BITS_PER_WIDE_INT >= 64
2807 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2810 if (GET_CODE (in) != CONST_INT)
2816 /* Assume c initially something like 0x00fff000000fffff. The idea
2817 is to rotate the word so that the middle ^^^^^^ group of zeros
2818 is at the MS end and can be cleared with an rldicl mask. We then
2819 rotate back and clear off the MS ^^ group of zeros with a
2821 c = ~c; /* c == 0xff000ffffff00000 */
2822 lsb = c & -c; /* lsb == 0x0000000000100000 */
2823 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2824 c = ~c; /* c == 0x00fff000000fffff */
2825 c &= -lsb; /* c == 0x00fff00000000000 */
2826 lsb = c & -c; /* lsb == 0x0000100000000000 */
2827 c = ~c; /* c == 0xff000fffffffffff */
2828 c &= -lsb; /* c == 0xff00000000000000 */
2830 while ((lsb >>= 1) != 0)
2831 shift++; /* shift == 44 on exit from loop */
2832 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2833 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2834 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2838 /* Assume c initially something like 0xff000f0000000000. The idea
2839 is to rotate the word so that the ^^^ middle group of zeros
2840 is at the LS end and can be cleared with an rldicr mask. We then
2841 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2843 lsb = c & -c; /* lsb == 0x0000010000000000 */
2844 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2845 c = ~c; /* c == 0x00fff0ffffffffff */
2846 c &= -lsb; /* c == 0x00fff00000000000 */
2847 lsb = c & -c; /* lsb == 0x0000100000000000 */
2848 c = ~c; /* c == 0xff000fffffffffff */
2849 c &= -lsb; /* c == 0xff00000000000000 */
2851 while ((lsb >>= 1) != 0)
2852 shift++; /* shift == 44 on exit from loop */
2853 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2854 m1 >>= shift; /* m1 == 0x0000000000000fff */
2855 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2858 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2859 masks will be all 1's. We are guaranteed more than one transition. */
2860 out[0] = GEN_INT (64 - shift);
2861 out[1] = GEN_INT (m1);
2862 out[2] = GEN_INT (shift);
2863 out[3] = GEN_INT (m2);
2871 /* Return 1 if the operand is either a non-special register or a constant
2872 that can be used as the operand of a PowerPC64 logical AND insn. */
2875 and64_operand (rtx op, enum machine_mode mode)
2877 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2878 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2880 return (logical_operand (op, mode) || mask64_operand (op, mode));
2883 /* Like the above, but also match constants that can be implemented
2884 with two rldicl or rldicr insns. */
2887 and64_2_operand (rtx op, enum machine_mode mode)
2889 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2890 return gpc_reg_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2892 return logical_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2895 /* Return 1 if the operand is either a non-special register or a
2896 constant that can be used as the operand of an RS/6000 logical AND insn. */
2899 and_operand (rtx op, enum machine_mode mode)
2901 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2902 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2904 return (logical_operand (op, mode) || mask_operand (op, mode));
2907 /* Return 1 if the operand is a general register or memory operand. */
2910 reg_or_mem_operand (rtx op, enum machine_mode mode)
2912 return (gpc_reg_operand (op, mode)
2913 || memory_operand (op, mode)
2914 || macho_lo_sum_memory_operand (op, mode)
2915 || volatile_mem_operand (op, mode));
2918 /* Return 1 if the operand is a general register or memory operand without
2919 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2923 lwa_operand (rtx op, enum machine_mode mode)
2927 if (reload_completed && GET_CODE (inner) == SUBREG)
2928 inner = SUBREG_REG (inner);
2930 return gpc_reg_operand (inner, mode)
2931 || (memory_operand (inner, mode)
2932 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2933 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2934 && (GET_CODE (XEXP (inner, 0)) != PLUS
2935 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2936 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2939 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2942 symbol_ref_operand (rtx op, enum machine_mode mode)
2944 if (mode != VOIDmode && GET_MODE (op) != mode)
2947 return (GET_CODE (op) == SYMBOL_REF
2948 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2951 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2952 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2955 call_operand (rtx op, enum machine_mode mode)
2957 if (mode != VOIDmode && GET_MODE (op) != mode)
2960 return (GET_CODE (op) == SYMBOL_REF
2961 || (GET_CODE (op) == REG
2962 && (REGNO (op) == LINK_REGISTER_REGNUM
2963 || REGNO (op) == COUNT_REGISTER_REGNUM
2964 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2967 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2971 current_file_function_operand (rtx op,
2972 enum machine_mode mode ATTRIBUTE_UNUSED)
2974 return (GET_CODE (op) == SYMBOL_REF
2975 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2976 && (SYMBOL_REF_LOCAL_P (op)
2977 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2980 /* Return 1 if this operand is a valid input for a move insn. */
2983 input_operand (rtx op, enum machine_mode mode)
2985 /* Memory is always valid. */
2986 if (memory_operand (op, mode))
2989 /* For floating-point, easy constants are valid. */
2990 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2992 && easy_fp_constant (op, mode))
2995 /* Allow any integer constant. */
2996 if (GET_MODE_CLASS (mode) == MODE_INT
2997 && (GET_CODE (op) == CONST_INT
2998 || GET_CODE (op) == CONST_DOUBLE))
3001 /* Allow easy vector constants. */
3002 if (GET_CODE (op) == CONST_VECTOR
3003 && easy_vector_constant (op, mode))
3006 /* For floating-point or multi-word mode, the only remaining valid type
3008 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3009 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3010 return register_operand (op, mode);
3012 /* The only cases left are integral modes one word or smaller (we
3013 do not get called for MODE_CC values). These can be in any
3015 if (register_operand (op, mode))
3018 /* A SYMBOL_REF referring to the TOC is valid. */
3019 if (legitimate_constant_pool_address_p (op))
3022 /* A constant pool expression (relative to the TOC) is valid */
3023 if (toc_relative_expr_p (op))
3026 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
3028 if (DEFAULT_ABI == ABI_V4
3029 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
3030 && small_data_operand (op, Pmode))
3037 /* Darwin, AIX increases natural record alignment to doubleword if the first
3038 field is an FP double while the FP fields remain word aligned. */
3041 rs6000_special_round_type_align (tree type, int computed, int specified)
3043 tree field = TYPE_FIELDS (type);
3045 /* Skip all the static variables only if ABI is greater than
3047 while (field != NULL && TREE_CODE (field) == VAR_DECL)
3048 field = TREE_CHAIN (field);
3050 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
3051 return MAX (computed, specified);
3053 return MAX (MAX (computed, specified), 64);
3056 /* Return 1 for an operand in small memory on V.4/eabi. */
3059 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3060 enum machine_mode mode ATTRIBUTE_UNUSED)
3065 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3068 if (DEFAULT_ABI != ABI_V4)
3071 if (GET_CODE (op) == SYMBOL_REF)
3074 else if (GET_CODE (op) != CONST
3075 || GET_CODE (XEXP (op, 0)) != PLUS
3076 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3077 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3082 rtx sum = XEXP (op, 0);
3083 HOST_WIDE_INT summand;
3085 /* We have to be careful here, because it is the referenced address
3086 that must be 32k from _SDA_BASE_, not just the symbol. */
3087 summand = INTVAL (XEXP (sum, 1));
3088 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3091 sym_ref = XEXP (sum, 0);
3094 return SYMBOL_REF_SMALL_P (sym_ref);
3100 /* Return true, if operand is a memory operand and has a
3101 displacement divisible by 4. */
3104 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3109 if (!memory_operand (op, mode))
3112 addr = XEXP (op, 0);
3113 if (GET_CODE (addr) == PLUS
3114 && GET_CODE (XEXP (addr, 0)) == REG
3115 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3116 off = INTVAL (XEXP (addr, 1));
3118 return (off % 4) == 0;
3121 /* Return true if either operand is a general purpose register. */
3124 gpr_or_gpr_p (rtx op0, rtx op1)
3126 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3127 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3131 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3134 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3136 switch (GET_CODE(op))
3139 if (RS6000_SYMBOL_REF_TLS_P (op))
3141 else if (CONSTANT_POOL_ADDRESS_P (op))
3143 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3151 else if (! strcmp (XSTR (op, 0), toc_label_name))
3160 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3161 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3163 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3172 constant_pool_expr_p (rtx op)
3176 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3180 toc_relative_expr_p (rtx op)
3184 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3188 legitimate_constant_pool_address_p (rtx x)
3191 && GET_CODE (x) == PLUS
3192 && GET_CODE (XEXP (x, 0)) == REG
3193 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3194 && constant_pool_expr_p (XEXP (x, 1)));
3198 legitimate_small_data_p (enum machine_mode mode, rtx x)
3200 return (DEFAULT_ABI == ABI_V4
3201 && !flag_pic && !TARGET_TOC
3202 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3203 && small_data_operand (x, mode));
3206 /* SPE offset addressing is limited to 5-bits worth of double words. */
3207 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3210 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3212 unsigned HOST_WIDE_INT offset, extra;
3214 if (GET_CODE (x) != PLUS)
3216 if (GET_CODE (XEXP (x, 0)) != REG)
3218 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3220 if (legitimate_constant_pool_address_p (x))
3222 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3225 offset = INTVAL (XEXP (x, 1));
3233 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3234 which leaves the only valid constant offset of zero, which by
3235 canonicalization rules is also invalid. */
3242 /* SPE vector modes. */
3243 return SPE_CONST_OFFSET_OK (offset);
3246 if (TARGET_E500_DOUBLE)
3247 return SPE_CONST_OFFSET_OK (offset);
3250 if (mode == DFmode || !TARGET_POWERPC64)
3252 else if (offset & 3)
3258 if (mode == TFmode || !TARGET_POWERPC64)
3260 else if (offset & 3)
3271 return (offset < 0x10000) && (offset + extra < 0x10000);
3275 legitimate_indexed_address_p (rtx x, int strict)
3279 if (GET_CODE (x) != PLUS)
3285 if (!REG_P (op0) || !REG_P (op1))
3288 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
3289 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3290 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3291 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
3295 legitimate_indirect_address_p (rtx x, int strict)
3297 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3301 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3303 if (!TARGET_MACHO || !flag_pic
3304 || mode != SImode || GET_CODE(x) != MEM)
3308 if (GET_CODE (x) != LO_SUM)
3310 if (GET_CODE (XEXP (x, 0)) != REG)
3312 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3316 return CONSTANT_P (x);
3320 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3322 if (GET_CODE (x) != LO_SUM)
3324 if (GET_CODE (XEXP (x, 0)) != REG)
3326 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3328 if (TARGET_E500_DOUBLE && mode == DFmode)
3332 if (TARGET_ELF || TARGET_MACHO)
3334 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3338 if (GET_MODE_NUNITS (mode) != 1)
3340 if (GET_MODE_BITSIZE (mode) > 64)
3343 return CONSTANT_P (x);
3350 /* Try machine-dependent ways of modifying an illegitimate address
3351 to be legitimate. If we find one, return the new, valid address.
3352 This is used from only one place: `memory_address' in explow.c.
3354 OLDX is the address as it was before break_out_memory_refs was
3355 called. In some cases it is useful to look at this to decide what
3358 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3360 It is always safe for this function to do nothing. It exists to
3361 recognize opportunities to optimize the output.
3363 On RS/6000, first check for the sum of a register with a constant
3364 integer that is out of range. If so, generate code to add the
3365 constant with the low-order 16 bits masked to the register and force
3366 this result into another register (this can be done with `cau').
3367 Then generate an address of REG+(CONST&0xffff), allowing for the
3368 possibility of bit 16 being a one.
3370 Then check for the sum of a register and something not constant, try to
3371 load the other things into a register and return the sum. */
3374 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3375 enum machine_mode mode)
3377 if (GET_CODE (x) == SYMBOL_REF)
3379 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3381 return rs6000_legitimize_tls_address (x, model);
3384 if (GET_CODE (x) == PLUS
3385 && GET_CODE (XEXP (x, 0)) == REG
3386 && GET_CODE (XEXP (x, 1)) == CONST_INT
3387 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3389 HOST_WIDE_INT high_int, low_int;
3391 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3392 high_int = INTVAL (XEXP (x, 1)) - low_int;
3393 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3394 GEN_INT (high_int)), 0);
3395 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3397 else if (GET_CODE (x) == PLUS
3398 && GET_CODE (XEXP (x, 0)) == REG
3399 && GET_CODE (XEXP (x, 1)) != CONST_INT
3400 && GET_MODE_NUNITS (mode) == 1
3401 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3403 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3404 && (TARGET_POWERPC64 || mode != DImode)
3407 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3408 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3410 else if (ALTIVEC_VECTOR_MODE (mode))
3414 /* Make sure both operands are registers. */
3415 if (GET_CODE (x) == PLUS)
3416 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3417 force_reg (Pmode, XEXP (x, 1)));
3419 reg = force_reg (Pmode, x);
3422 else if (SPE_VECTOR_MODE (mode)
3423 || (TARGET_E500_DOUBLE && mode == DFmode))
3425 /* We accept [reg + reg] and [reg + OFFSET]. */
3427 if (GET_CODE (x) == PLUS)
3429 rtx op1 = XEXP (x, 0);
3430 rtx op2 = XEXP (x, 1);
3432 op1 = force_reg (Pmode, op1);
3434 if (GET_CODE (op2) != REG
3435 && (GET_CODE (op2) != CONST_INT
3436 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3437 op2 = force_reg (Pmode, op2);
3439 return gen_rtx_PLUS (Pmode, op1, op2);
3442 return force_reg (Pmode, x);
3448 && GET_CODE (x) != CONST_INT
3449 && GET_CODE (x) != CONST_DOUBLE
3451 && GET_MODE_NUNITS (mode) == 1
3452 && (GET_MODE_BITSIZE (mode) <= 32
3453 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3455 rtx reg = gen_reg_rtx (Pmode);
3456 emit_insn (gen_elf_high (reg, x));
3457 return gen_rtx_LO_SUM (Pmode, reg, x);
3459 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3462 && ! MACHO_DYNAMIC_NO_PIC_P
3464 && GET_CODE (x) != CONST_INT
3465 && GET_CODE (x) != CONST_DOUBLE
3467 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3471 rtx reg = gen_reg_rtx (Pmode);
3472 emit_insn (gen_macho_high (reg, x));
3473 return gen_rtx_LO_SUM (Pmode, reg, x);
3476 && constant_pool_expr_p (x)
3477 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3479 return create_TOC_reference (x);
3485 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3486 We need to emit DTP-relative relocations. */
3489 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3494 fputs ("\t.long\t", file);
3497 fputs (DOUBLE_INT_ASM_OP, file);
3502 output_addr_const (file, x);
3503 fputs ("@dtprel+0x8000", file);
3506 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3508 static GTY(()) rtx rs6000_tls_symbol;
3510 rs6000_tls_get_addr (void)
3512 if (!rs6000_tls_symbol)
3513 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3515 return rs6000_tls_symbol;
3518 /* Construct the SYMBOL_REF for TLS GOT references. */
3520 static GTY(()) rtx rs6000_got_symbol;
3522 rs6000_got_sym (void)
3524 if (!rs6000_got_symbol)
3526 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3527 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3528 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3531 return rs6000_got_symbol;
3534 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3535 this (thread-local) address. */
3538 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3542 dest = gen_reg_rtx (Pmode);
3543 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3549 tlsreg = gen_rtx_REG (Pmode, 13);
3550 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3554 tlsreg = gen_rtx_REG (Pmode, 2);
3555 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3559 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3563 tmp = gen_reg_rtx (Pmode);
3566 tlsreg = gen_rtx_REG (Pmode, 13);
3567 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3571 tlsreg = gen_rtx_REG (Pmode, 2);
3572 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3576 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3578 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3583 rtx r3, got, tga, tmp1, tmp2, eqv;
3586 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3590 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3593 rtx gsym = rs6000_got_sym ();
3594 got = gen_reg_rtx (Pmode);
3596 rs6000_emit_move (got, gsym, Pmode);
3600 static int tls_got_labelno = 0;
3601 rtx tempLR, lab, tmp3, mem;
3604 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
3605 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
3606 tempLR = gen_reg_rtx (Pmode);
3607 tmp1 = gen_reg_rtx (Pmode);
3608 tmp2 = gen_reg_rtx (Pmode);
3609 tmp3 = gen_reg_rtx (Pmode);
3610 mem = gen_const_mem (Pmode, tmp1);
3612 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
3614 emit_move_insn (tmp1, tempLR);
3615 emit_move_insn (tmp2, mem);
3616 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3617 last = emit_move_insn (got, tmp3);
3618 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3620 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3622 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3628 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3630 r3 = gen_rtx_REG (Pmode, 3);
3632 insn = gen_tls_gd_64 (r3, got, addr);
3634 insn = gen_tls_gd_32 (r3, got, addr);
3637 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3638 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3639 insn = emit_call_insn (insn);
3640 CONST_OR_PURE_CALL_P (insn) = 1;
3641 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3642 insn = get_insns ();
3644 emit_libcall_block (insn, dest, r3, addr);
3646 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3648 r3 = gen_rtx_REG (Pmode, 3);
3650 insn = gen_tls_ld_64 (r3, got);
3652 insn = gen_tls_ld_32 (r3, got);
3655 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3656 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3657 insn = emit_call_insn (insn);
3658 CONST_OR_PURE_CALL_P (insn) = 1;
3659 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3660 insn = get_insns ();
3662 tmp1 = gen_reg_rtx (Pmode);
3663 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3665 emit_libcall_block (insn, tmp1, r3, eqv);
3666 if (rs6000_tls_size == 16)
3669 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3671 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3673 else if (rs6000_tls_size == 32)
3675 tmp2 = gen_reg_rtx (Pmode);
3677 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3679 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3682 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3684 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3688 tmp2 = gen_reg_rtx (Pmode);
3690 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3692 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3694 insn = gen_rtx_SET (Pmode, dest,
3695 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3701 /* IE, or 64 bit offset LE. */
3702 tmp2 = gen_reg_rtx (Pmode);
3704 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3706 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3709 insn = gen_tls_tls_64 (dest, tmp2, addr);
3711 insn = gen_tls_tls_32 (dest, tmp2, addr);
3719 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3720 instruction definitions. */
3723 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3725 return RS6000_SYMBOL_REF_TLS_P (x);
3728 /* Return 1 if X contains a thread-local symbol. */
3731 rs6000_tls_referenced_p (rtx x)
3733 if (! TARGET_HAVE_TLS)
3736 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3739 /* Return 1 if *X is a thread-local symbol. This is the same as
3740 rs6000_tls_symbol_ref except for the type of the unused argument. */
3743 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3745 return RS6000_SYMBOL_REF_TLS_P (*x);
3748 /* The convention appears to be to define this wherever it is used.
3749 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3750 is now used here. */
3751 #ifndef REG_MODE_OK_FOR_BASE_P
3752 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3755 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3756 replace the input X, or the original X if no replacement is called for.
3757 The output parameter *WIN is 1 if the calling macro should goto WIN,
3760 For RS/6000, we wish to handle large displacements off a base
3761 register by splitting the addend across an addiu/addis and the mem insn.
3762 This cuts number of extra insns needed from 3 to 1.
3764 On Darwin, we use this to generate code for floating point constants.
3765 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3766 The Darwin code is inside #if TARGET_MACHO because only then is
3767 machopic_function_base_name() defined. */
3769 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3770 int opnum, int type,
3771 int ind_levels ATTRIBUTE_UNUSED, int *win)
3773 /* We must recognize output that we have already generated ourselves. */
3774 if (GET_CODE (x) == PLUS
3775 && GET_CODE (XEXP (x, 0)) == PLUS
3776 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3777 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3778 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3780 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3781 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3782 opnum, (enum reload_type)type);
3788 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3789 && GET_CODE (x) == LO_SUM
3790 && GET_CODE (XEXP (x, 0)) == PLUS
3791 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3792 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3793 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3794 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3795 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3796 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3797 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3799 /* Result of previous invocation of this function on Darwin
3800 floating point constant. */
3801 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3802 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3803 opnum, (enum reload_type)type);
3808 if (GET_CODE (x) == PLUS
3809 && GET_CODE (XEXP (x, 0)) == REG
3810 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3811 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3812 && GET_CODE (XEXP (x, 1)) == CONST_INT
3813 && !SPE_VECTOR_MODE (mode)
3814 && !(TARGET_E500_DOUBLE && mode == DFmode)
3815 && !ALTIVEC_VECTOR_MODE (mode))
3817 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3818 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3820 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3822 /* Check for 32-bit overflow. */
3823 if (high + low != val)
3829 /* Reload the high part into a base reg; leave the low part
3830 in the mem directly. */
3832 x = gen_rtx_PLUS (GET_MODE (x),
3833 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3837 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3838 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3839 opnum, (enum reload_type)type);
3844 if (GET_CODE (x) == SYMBOL_REF
3845 && DEFAULT_ABI == ABI_DARWIN
3846 && !ALTIVEC_VECTOR_MODE (mode)
3847 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3848 /* Don't do this for TFmode, since the result isn't offsettable. */
3853 rtx offset = gen_rtx_CONST (Pmode,
3854 gen_rtx_MINUS (Pmode, x,
3855 machopic_function_base_sym ()));
3856 x = gen_rtx_LO_SUM (GET_MODE (x),
3857 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3858 gen_rtx_HIGH (Pmode, offset)), offset);
3861 x = gen_rtx_LO_SUM (GET_MODE (x),
3862 gen_rtx_HIGH (Pmode, x), x);
3864 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3865 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3866 opnum, (enum reload_type)type);
3872 && constant_pool_expr_p (x)
3873 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3875 (x) = create_TOC_reference (x);
3883 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3884 that is a valid memory address for an instruction.
3885 The MODE argument is the machine mode for the MEM expression
3886 that wants to use this address.
3888 On the RS/6000, there are four valid address: a SYMBOL_REF that
3889 refers to a constant pool entry of an address (or the sum of it
3890 plus a constant), a short (16-bit signed) constant plus a register,
3891 the sum of two registers, or a register indirect, possibly with an
3892 auto-increment. For DFmode and DImode with a constant plus register,
3893 we must ensure that both words are addressable or PowerPC64 with offset
3896 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3897 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3898 adjacent memory cells are accessed by adding word-sized offsets
3899 during assembly output. */
3901 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3903 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3905 && ALTIVEC_VECTOR_MODE (mode)
3906 && GET_CODE (x) == AND
3907 && GET_CODE (XEXP (x, 1)) == CONST_INT
3908 && INTVAL (XEXP (x, 1)) == -16)
3911 if (RS6000_SYMBOL_REF_TLS_P (x))
3913 if (legitimate_indirect_address_p (x, reg_ok_strict))
3915 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3916 && !ALTIVEC_VECTOR_MODE (mode)
3917 && !SPE_VECTOR_MODE (mode)
3918 && !(TARGET_E500_DOUBLE && mode == DFmode)
3920 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3922 if (legitimate_small_data_p (mode, x))
3924 if (legitimate_constant_pool_address_p (x))
3926 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3928 && GET_CODE (x) == PLUS
3929 && GET_CODE (XEXP (x, 0)) == REG
3930 && (XEXP (x, 0) == virtual_stack_vars_rtx
3931 || XEXP (x, 0) == arg_pointer_rtx)
3932 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3934 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3938 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3940 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3941 && (TARGET_POWERPC64 || mode != DImode)
3942 && legitimate_indexed_address_p (x, reg_ok_strict))
3944 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3949 /* Go to LABEL if ADDR (a legitimate address expression)
3950 has an effect that depends on the machine mode it is used for.
3952 On the RS/6000 this is true of all integral offsets (since AltiVec
3953 modes don't allow them) or is a pre-increment or decrement.
3955 ??? Except that due to conceptual problems in offsettable_address_p
3956 we can't really report the problems of integral offsets. So leave
3957 this assuming that the adjustable offset must be valid for the
3958 sub-words of a TFmode operand, which is what we had before. */
3961 rs6000_mode_dependent_address (rtx addr)
3963 switch (GET_CODE (addr))
3966 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3968 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3969 return val + 12 + 0x8000 >= 0x10000;
3978 return TARGET_UPDATE;
3987 /* Return number of consecutive hard regs needed starting at reg REGNO
3988 to hold something of mode MODE.
3989 This is ordinarily the length in words of a value of mode MODE
3990 but can be less for certain modes in special long registers.
3992 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3993 scalar instructions. The upper 32 bits are only available to the
3996 POWER and PowerPC GPRs hold 32 bits worth;
3997 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4000 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4002 if (FP_REGNO_P (regno))
4003 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4005 if (TARGET_E500_DOUBLE && mode == DFmode)
4008 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4009 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4011 if (ALTIVEC_REGNO_P (regno))
4013 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4015 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4018 /* Change register usage conditional on target flags. */
4020 rs6000_conditional_register_usage (void)
4024 /* Set MQ register fixed (already call_used) if not POWER
4025 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4030 /* 64-bit AIX reserves GPR13 for thread-private data. */
4032 fixed_regs[13] = call_used_regs[13]
4033 = call_really_used_regs[13] = 1;
4035 /* Conditionally disable FPRs. */
4036 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4037 for (i = 32; i < 64; i++)
4038 fixed_regs[i] = call_used_regs[i]
4039 = call_really_used_regs[i] = 1;
4041 if (DEFAULT_ABI == ABI_V4
4042 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4044 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4046 if (DEFAULT_ABI == ABI_V4
4047 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4049 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4050 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4051 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4053 if (DEFAULT_ABI == ABI_DARWIN
4054 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4055 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4056 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4057 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4058 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4060 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4061 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4062 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4065 global_regs[VSCR_REGNO] = 1;
4069 global_regs[SPEFSCR_REGNO] = 1;
4070 fixed_regs[FIXED_SCRATCH]
4071 = call_used_regs[FIXED_SCRATCH]
4072 = call_really_used_regs[FIXED_SCRATCH] = 1;
4075 if (! TARGET_ALTIVEC)
4077 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4078 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4079 call_really_used_regs[VRSAVE_REGNO] = 1;
4082 if (TARGET_ALTIVEC_ABI)
4083 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4084 call_used_regs[i] = call_really_used_regs[i] = 1;
4087 /* Try to output insns to set TARGET equal to the constant C if it can
4088 be done in less than N insns. Do all computations in MODE.
4089 Returns the place where the output has been placed if it can be
4090 done and the insns have been emitted. If it would take more than N
4091 insns, zero is returned and no insns and emitted. */
4094 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4095 rtx source, int n ATTRIBUTE_UNUSED)
4097 rtx result, insn, set;
4098 HOST_WIDE_INT c0, c1;
4100 if (mode == QImode || mode == HImode)
4103 dest = gen_reg_rtx (mode);
4104 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4107 else if (mode == SImode)
4109 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4111 emit_insn (gen_rtx_SET (VOIDmode, result,
4112 GEN_INT (INTVAL (source)
4113 & (~ (HOST_WIDE_INT) 0xffff))));
4114 emit_insn (gen_rtx_SET (VOIDmode, dest,
4115 gen_rtx_IOR (SImode, result,
4116 GEN_INT (INTVAL (source) & 0xffff))));
4119 else if (mode == DImode)
4121 if (GET_CODE (source) == CONST_INT)
4123 c0 = INTVAL (source);
4126 else if (GET_CODE (source) == CONST_DOUBLE)
4128 #if HOST_BITS_PER_WIDE_INT >= 64
4129 c0 = CONST_DOUBLE_LOW (source);
4132 c0 = CONST_DOUBLE_LOW (source);
4133 c1 = CONST_DOUBLE_HIGH (source);
4139 result = rs6000_emit_set_long_const (dest, c0, c1);
4144 insn = get_last_insn ();
4145 set = single_set (insn);
4146 if (! CONSTANT_P (SET_SRC (set)))
4147 set_unique_reg_note (insn, REG_EQUAL, source);
4152 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4153 fall back to a straight forward decomposition. We do this to avoid
4154 exponential run times encountered when looking for longer sequences
4155 with rs6000_emit_set_const. */
4157 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4159 if (!TARGET_POWERPC64)
4161 rtx operand1, operand2;
4163 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4165 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4167 emit_move_insn (operand1, GEN_INT (c1));
4168 emit_move_insn (operand2, GEN_INT (c2));
4172 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4175 ud2 = (c1 & 0xffff0000) >> 16;
4176 #if HOST_BITS_PER_WIDE_INT >= 64
4180 ud4 = (c2 & 0xffff0000) >> 16;
4182 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4183 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4186 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4188 emit_move_insn (dest, GEN_INT (ud1));
4191 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4192 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4195 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4198 emit_move_insn (dest, GEN_INT (ud2 << 16));
4200 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4202 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4203 || (ud4 == 0 && ! (ud3 & 0x8000)))
4206 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4209 emit_move_insn (dest, GEN_INT (ud3 << 16));
4212 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4213 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4215 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4220 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4223 emit_move_insn (dest, GEN_INT (ud4 << 16));
4226 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4228 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4230 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4231 GEN_INT (ud2 << 16)));
4233 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4239 /* Helper for the following. Get rid of [r+r] memory refs
4240 in cases where it won't work (TImode, TFmode). */
4243 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4245 if (GET_CODE (operands[0]) == MEM
4246 && GET_CODE (XEXP (operands[0], 0)) != REG
4247 && ! reload_in_progress)
4249 = replace_equiv_address (operands[0],
4250 copy_addr_to_reg (XEXP (operands[0], 0)));
4252 if (GET_CODE (operands[1]) == MEM
4253 && GET_CODE (XEXP (operands[1], 0)) != REG
4254 && ! reload_in_progress)
4256 = replace_equiv_address (operands[1],
4257 copy_addr_to_reg (XEXP (operands[1], 0)));
4260 /* Emit a move from SOURCE to DEST in mode MODE. */
4262 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4266 operands[1] = source;
4268 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4269 if (GET_CODE (operands[1]) == CONST_DOUBLE
4270 && ! FLOAT_MODE_P (mode)
4271 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4273 /* FIXME. This should never happen. */
4274 /* Since it seems that it does, do the safe thing and convert
4276 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4278 if (GET_CODE (operands[1]) == CONST_DOUBLE
4279 && ! FLOAT_MODE_P (mode)
4280 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
4281 && CONST_DOUBLE_LOW (operands[1]) >= 0)
4282 || (CONST_DOUBLE_HIGH (operands[1]) == -1
4283 && CONST_DOUBLE_LOW (operands[1]) < 0)))
4286 /* Check if GCC is setting up a block move that will end up using FP
4287 registers as temporaries. We must make sure this is acceptable. */
4288 if (GET_CODE (operands[0]) == MEM
4289 && GET_CODE (operands[1]) == MEM
4291 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4292 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4293 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4294 ? 32 : MEM_ALIGN (operands[0])))
4295 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4297 : MEM_ALIGN (operands[1]))))
4298 && ! MEM_VOLATILE_P (operands [0])
4299 && ! MEM_VOLATILE_P (operands [1]))
4301 emit_move_insn (adjust_address (operands[0], SImode, 0),
4302 adjust_address (operands[1], SImode, 0));
4303 emit_move_insn (adjust_address (operands[0], SImode, 4),
4304 adjust_address (operands[1], SImode, 4));
4308 if (!no_new_pseudos && GET_CODE (operands[0]) != REG
4309 && !gpc_reg_operand (operands[1], mode))
4310 operands[1] = force_reg (mode, operands[1]);
4312 if (mode == SFmode && ! TARGET_POWERPC
4313 && TARGET_HARD_FLOAT && TARGET_FPRS
4314 && GET_CODE (operands[0]) == MEM)
4318 if (reload_in_progress || reload_completed)
4319 regnum = true_regnum (operands[1]);
4320 else if (GET_CODE (operands[1]) == REG)
4321 regnum = REGNO (operands[1]);
4325 /* If operands[1] is a register, on POWER it may have
4326 double-precision data in it, so truncate it to single
4328 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4331 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4332 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4333 operands[1] = newreg;
4337 /* Recognize the case where operand[1] is a reference to thread-local
4338 data and load its address to a register. */
4339 if (GET_CODE (operands[1]) == SYMBOL_REF)
4341 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
4343 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
4346 /* Handle the case where reload calls us with an invalid address. */
4347 if (reload_in_progress && mode == Pmode
4348 && (! general_operand (operands[1], mode)
4349 || ! nonimmediate_operand (operands[0], mode)))
4352 /* 128-bit constant floating-point values on Darwin should really be
4353 loaded as two parts. */
4354 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
4355 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4356 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4358 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4359 know how to get a DFmode SUBREG of a TFmode. */
4360 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4361 simplify_gen_subreg (DImode, operands[1], mode, 0),
4363 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4364 GET_MODE_SIZE (DImode)),
4365 simplify_gen_subreg (DImode, operands[1], mode,
4366 GET_MODE_SIZE (DImode)),
4371 /* FIXME: In the long term, this switch statement should go away
4372 and be replaced by a sequence of tests based on things like
4378 if (CONSTANT_P (operands[1])
4379 && GET_CODE (operands[1]) != CONST_INT)
4380 operands[1] = force_const_mem (mode, operands[1]);
4384 rs6000_eliminate_indexed_memrefs (operands);
4389 if (CONSTANT_P (operands[1])
4390 && ! easy_fp_constant (operands[1], mode))
4391 operands[1] = force_const_mem (mode, operands[1]);
4402 if (CONSTANT_P (operands[1])
4403 && !easy_vector_constant (operands[1], mode))
4404 operands[1] = force_const_mem (mode, operands[1]);
4409 /* Use default pattern for address of ELF small data */
4412 && DEFAULT_ABI == ABI_V4
4413 && (GET_CODE (operands[1]) == SYMBOL_REF
4414 || GET_CODE (operands[1]) == CONST)
4415 && small_data_operand (operands[1], mode))
4417 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4421 if (DEFAULT_ABI == ABI_V4
4422 && mode == Pmode && mode == SImode
4423 && flag_pic == 1 && got_operand (operands[1], mode))
4425 emit_insn (gen_movsi_got (operands[0], operands[1]));
4429 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4433 && CONSTANT_P (operands[1])
4434 && GET_CODE (operands[1]) != HIGH
4435 && GET_CODE (operands[1]) != CONST_INT)
4437 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4439 /* If this is a function address on -mcall-aixdesc,
4440 convert it to the address of the descriptor. */
4441 if (DEFAULT_ABI == ABI_AIX
4442 && GET_CODE (operands[1]) == SYMBOL_REF
4443 && XSTR (operands[1], 0)[0] == '.')
4445 const char *name = XSTR (operands[1], 0);
4447 while (*name == '.')
4449 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4450 CONSTANT_POOL_ADDRESS_P (new_ref)
4451 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4452 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4453 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4454 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
4455 operands[1] = new_ref;
4458 if (DEFAULT_ABI == ABI_DARWIN)
4461 if (MACHO_DYNAMIC_NO_PIC_P)
4463 /* Take care of any required data indirection. */
4464 operands[1] = rs6000_machopic_legitimize_pic_address (
4465 operands[1], mode, operands[0]);
4466 if (operands[0] != operands[1])
4467 emit_insn (gen_rtx_SET (VOIDmode,
4468 operands[0], operands[1]));
4472 emit_insn (gen_macho_high (target, operands[1]));
4473 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4477 emit_insn (gen_elf_high (target, operands[1]));
4478 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4482 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4483 and we have put it in the TOC, we just need to make a TOC-relative
4486 && GET_CODE (operands[1]) == SYMBOL_REF
4487 && constant_pool_expr_p (operands[1])
4488 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4489 get_pool_mode (operands[1])))
4491 operands[1] = create_TOC_reference (operands[1]);
4493 else if (mode == Pmode
4494 && CONSTANT_P (operands[1])
4495 && ((GET_CODE (operands[1]) != CONST_INT
4496 && ! easy_fp_constant (operands[1], mode))
4497 || (GET_CODE (operands[1]) == CONST_INT
4498 && num_insns_constant (operands[1], mode) > 2)
4499 || (GET_CODE (operands[0]) == REG
4500 && FP_REGNO_P (REGNO (operands[0]))))
4501 && GET_CODE (operands[1]) != HIGH
4502 && ! legitimate_constant_pool_address_p (operands[1])
4503 && ! toc_relative_expr_p (operands[1]))
4505 /* Emit a USE operation so that the constant isn't deleted if
4506 expensive optimizations are turned on because nobody
4507 references it. This should only be done for operands that
4508 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4509 This should not be done for operands that contain LABEL_REFs.
4510 For now, we just handle the obvious case. */
4511 if (GET_CODE (operands[1]) != LABEL_REF)
4512 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4515 /* Darwin uses a special PIC legitimizer. */
4516 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4519 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4521 if (operands[0] != operands[1])
4522 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4527 /* If we are to limit the number of things we put in the TOC and
4528 this is a symbol plus a constant we can add in one insn,
4529 just put the symbol in the TOC and add the constant. Don't do
4530 this if reload is in progress. */
4531 if (GET_CODE (operands[1]) == CONST
4532 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4533 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4534 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4535 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4536 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4537 && ! side_effects_p (operands[0]))
4540 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4541 rtx other = XEXP (XEXP (operands[1], 0), 1);
4543 sym = force_reg (mode, sym);
4545 emit_insn (gen_addsi3 (operands[0], sym, other));
4547 emit_insn (gen_adddi3 (operands[0], sym, other));
4551 operands[1] = force_const_mem (mode, operands[1]);
4554 && constant_pool_expr_p (XEXP (operands[1], 0))
4555 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4556 get_pool_constant (XEXP (operands[1], 0)),
4557 get_pool_mode (XEXP (operands[1], 0))))
4560 = gen_const_mem (mode,
4561 create_TOC_reference (XEXP (operands[1], 0)));
4562 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4568 rs6000_eliminate_indexed_memrefs (operands);
4572 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4574 gen_rtx_SET (VOIDmode,
4575 operands[0], operands[1]),
4576 gen_rtx_CLOBBER (VOIDmode,
4577 gen_rtx_SCRATCH (SImode)))));
4586 /* Above, we may have called force_const_mem which may have returned
4587 an invalid address. If we can, fix this up; otherwise, reload will
4588 have to deal with it. */
4589 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4590 operands[1] = validize_mem (operands[1]);
4593 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4596 /* Nonzero if we can use a floating-point register to pass this arg. */
4597 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4598 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4599 && (CUM)->fregno <= FP_ARG_MAX_REG \
4600 && TARGET_HARD_FLOAT && TARGET_FPRS)
4602 /* Nonzero if we can use an AltiVec register to pass this arg. */
4603 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4604 (ALTIVEC_VECTOR_MODE (MODE) \
4605 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4606 && TARGET_ALTIVEC_ABI \
4609 /* Return a nonzero value to say to return the function value in
4610 memory, just as large structures are always returned. TYPE will be
4611 the data type of the value, and FNTYPE will be the type of the
4612 function doing the returning, or @code{NULL} for libcalls.
4614 The AIX ABI for the RS/6000 specifies that all structures are
4615 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4616 specifies that structures <= 8 bytes are returned in r3/r4, but a
4617 draft put them in memory, and GCC used to implement the draft
4618 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4619 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4620 compatibility can change DRAFT_V4_STRUCT_RET to override the
4621 default, and -m switches get the final word. See
4622 rs6000_override_options for more details.
4624 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4625 long double support is enabled. These values are returned in memory.
4627 int_size_in_bytes returns -1 for variable size objects, which go in
4628 memory always. The cast to unsigned makes -1 > 8. */
4631 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4633 /* In the darwin64 abi, try to use registers for larger structs
4635 if (AGGREGATE_TYPE_P (type)
4636 && rs6000_darwin64_abi
4637 && TREE_CODE (type) == RECORD_TYPE
4638 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 32)
4639 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 0))
4642 if (AGGREGATE_TYPE_P (type)
4643 && (TARGET_AIX_STRUCT_RET
4644 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4647 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4648 modes only exist for GCC vector types if -maltivec. */
4649 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4650 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4653 /* Return synthetic vectors in memory. */
4654 if (TREE_CODE (type) == VECTOR_TYPE
4655 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4657 static bool warned_for_return_big_vectors = false;
4658 if (!warned_for_return_big_vectors)
4660 warning ("GCC vector returned by reference: "
4661 "non-standard ABI extension with no compatibility guarantee");
4662 warned_for_return_big_vectors = true;
4667 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4673 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4674 for a call to a function whose data type is FNTYPE.
4675 For a library call, FNTYPE is 0.
4677 For incoming args we set the number of arguments in the prototype large
4678 so we never return a PARALLEL. */
4681 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4682 rtx libname ATTRIBUTE_UNUSED, int incoming,
4683 int libcall, int n_named_args)
4685 static CUMULATIVE_ARGS zero_cumulative;
4687 *cum = zero_cumulative;
4689 cum->fregno = FP_ARG_MIN_REG;
4690 cum->vregno = ALTIVEC_ARG_MIN_REG;
4691 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4692 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4693 ? CALL_LIBCALL : CALL_NORMAL);
4694 cum->sysv_gregno = GP_ARG_MIN_REG;
4695 cum->stdarg = fntype
4696 && (TYPE_ARG_TYPES (fntype) != 0
4697 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4698 != void_type_node));
4700 cum->nargs_prototype = 0;
4701 if (incoming || cum->prototype)
4702 cum->nargs_prototype = n_named_args;
4704 /* Check for a longcall attribute. */
4705 if ((!fntype && rs6000_default_long_calls)
4707 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4708 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4709 cum->call_cookie |= CALL_LONG;
4711 if (TARGET_DEBUG_ARG)
4713 fprintf (stderr, "\ninit_cumulative_args:");
4716 tree ret_type = TREE_TYPE (fntype);
4717 fprintf (stderr, " ret code = %s,",
4718 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4721 if (cum->call_cookie & CALL_LONG)
4722 fprintf (stderr, " longcall,");
4724 fprintf (stderr, " proto = %d, nargs = %d\n",
4725 cum->prototype, cum->nargs_prototype);
4730 && TARGET_ALTIVEC_ABI
4731 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4733 error ("Cannot return value in vector register because"
4734 " altivec instructions are disabled, use -maltivec"
4735 " to enable them.");
4739 /* Return true if TYPE must be passed on the stack and not in registers. */
4742 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4744 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4745 return must_pass_in_stack_var_size (mode, type);
4747 return must_pass_in_stack_var_size_or_pad (mode, type);
4750 /* If defined, a C expression which determines whether, and in which
4751 direction, to pad out an argument with extra space. The value
4752 should be of type `enum direction': either `upward' to pad above
4753 the argument, `downward' to pad below, or `none' to inhibit
4756 For the AIX ABI structs are always stored left shifted in their
4760 function_arg_padding (enum machine_mode mode, tree type)
4762 #ifndef AGGREGATE_PADDING_FIXED
4763 #define AGGREGATE_PADDING_FIXED 0
4765 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4766 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4769 if (!AGGREGATE_PADDING_FIXED)
4771 /* GCC used to pass structures of the same size as integer types as
4772 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4773 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4774 passed padded downward, except that -mstrict-align further
4775 muddied the water in that multi-component structures of 2 and 4
4776 bytes in size were passed padded upward.
4778 The following arranges for best compatibility with previous
4779 versions of gcc, but removes the -mstrict-align dependency. */
4780 if (BYTES_BIG_ENDIAN)
4782 HOST_WIDE_INT size = 0;
4784 if (mode == BLKmode)
4786 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4787 size = int_size_in_bytes (type);
4790 size = GET_MODE_SIZE (mode);
4792 if (size == 1 || size == 2 || size == 4)
4798 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4800 if (type != 0 && AGGREGATE_TYPE_P (type))
4804 /* Fall back to the default. */
4805 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4808 /* If defined, a C expression that gives the alignment boundary, in bits,
4809 of an argument with the specified mode and type. If it is not defined,
4810 PARM_BOUNDARY is used for all arguments.
4812 V.4 wants long longs to be double word aligned.
4813 Doubleword align SPE vectors.
4814 Quadword align Altivec vectors.
4815 Quadword align large synthetic vector types. */
4818 function_arg_boundary (enum machine_mode mode, tree type)
4820 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4822 else if (SPE_VECTOR_MODE (mode)
4823 || (type && TREE_CODE (type) == VECTOR_TYPE
4824 && int_size_in_bytes (type) >= 8
4825 && int_size_in_bytes (type) < 16))
4827 else if (ALTIVEC_VECTOR_MODE (mode)
4828 || (type && TREE_CODE (type) == VECTOR_TYPE
4829 && int_size_in_bytes (type) >= 16))
4832 return PARM_BOUNDARY;
4835 /* Compute the size (in words) of a function argument. */
4837 static unsigned long
4838 rs6000_arg_size (enum machine_mode mode, tree type)
4842 if (mode != BLKmode)
4843 size = GET_MODE_SIZE (mode);
4845 size = int_size_in_bytes (type);
4848 return (size + 3) >> 2;
4850 return (size + 7) >> 3;
4853 /* The darwin64 ABI calls for us to recurse down through structs,
4854 applying the same rules to struct elements as if a reference to
4855 each were being passed directly. */
4858 darwin64_function_arg_advance (CUMULATIVE_ARGS *cum, tree type,
4859 int named, int depth)
4864 switch (TREE_CODE (type))
4867 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4868 if (TREE_CODE (f) == FIELD_DECL)
4870 ftype = TREE_TYPE (f);
4871 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4877 tot = int_size_in_bytes (type);
4880 ftype = TREE_TYPE (type);
4881 tot /= int_size_in_bytes (ftype);
4883 for (i = 0; i < tot; ++i)
4885 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4895 /* Update the data in CUM to advance over an argument
4896 of mode MODE and data type TYPE.
4897 (TYPE is null for libcalls where that information may not be available.)
4899 Note that for args passed by reference, function_arg will be called
4900 with MODE and TYPE set to that of the pointer to the arg, not the arg
4904 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4905 tree type, int named, int depth)
4907 /* Only tick off an argument if we're not recursing. */
4909 cum->nargs_prototype--;
4911 if (TARGET_ALTIVEC_ABI
4912 && (ALTIVEC_VECTOR_MODE (mode)
4913 || (type && TREE_CODE (type) == VECTOR_TYPE
4914 && int_size_in_bytes (type) == 16)))
4918 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4921 if (!TARGET_ALTIVEC)
4922 error ("Cannot pass argument in vector register because"
4923 " altivec instructions are disabled, use -maltivec"
4924 " to enable them.");
4926 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4927 even if it is going to be passed in a vector register.
4928 Darwin does the same for variable-argument functions. */
4929 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4930 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4940 /* Vector parameters must be 16-byte aligned. This places
4941 them at 2 mod 4 in terms of words in 32-bit mode, since
4942 the parameter save area starts at offset 24 from the
4943 stack. In 64-bit mode, they just have to start on an
4944 even word, since the parameter save area is 16-byte
4945 aligned. Space for GPRs is reserved even if the argument
4946 will be passed in memory. */
4948 align = (2 - cum->words) & 3;
4950 align = cum->words & 1;
4951 cum->words += align + rs6000_arg_size (mode, type);
4953 if (TARGET_DEBUG_ARG)
4955 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4957 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4958 cum->nargs_prototype, cum->prototype,
4959 GET_MODE_NAME (mode));
4963 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4965 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4968 else if (rs6000_darwin64_abi
4970 && (TREE_CODE (type) == RECORD_TYPE
4971 || TREE_CODE (type) == ARRAY_TYPE))
4972 darwin64_function_arg_advance (cum, type, named, depth);
4974 else if (DEFAULT_ABI == ABI_V4)
4976 if (TARGET_HARD_FLOAT && TARGET_FPRS
4977 && (mode == SFmode || mode == DFmode))
4979 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4984 cum->words += cum->words & 1;
4985 cum->words += rs6000_arg_size (mode, type);
4990 int n_words = rs6000_arg_size (mode, type);
4991 int gregno = cum->sysv_gregno;
4993 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4994 (r7,r8) or (r9,r10). As does any other 2 word item such
4995 as complex int due to a historical mistake. */
4997 gregno += (1 - gregno) & 1;
4999 /* Multi-reg args are not split between registers and stack. */
5000 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5002 /* Long long and SPE vectors are aligned on the stack.
5003 So are other 2 word items such as complex int due to
5004 a historical mistake. */
5006 cum->words += cum->words & 1;
5007 cum->words += n_words;
5010 /* Note: continuing to accumulate gregno past when we've started
5011 spilling to the stack indicates the fact that we've started
5012 spilling to the stack to expand_builtin_saveregs. */
5013 cum->sysv_gregno = gregno + n_words;
5016 if (TARGET_DEBUG_ARG)
5018 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5019 cum->words, cum->fregno);
5020 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5021 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5022 fprintf (stderr, "mode = %4s, named = %d\n",
5023 GET_MODE_NAME (mode), named);
5028 int n_words = rs6000_arg_size (mode, type);
5029 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5031 /* The simple alignment calculation here works because
5032 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
5033 If we ever want to handle alignments larger than 8 bytes for
5034 32-bit or 16 bytes for 64-bit, then we'll need to take into
5035 account the offset to the start of the parm save area. */
5036 align &= cum->words;
5037 cum->words += align + n_words;
5039 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5040 && TARGET_HARD_FLOAT && TARGET_FPRS)
5041 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5043 if (TARGET_DEBUG_ARG)
5045 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5046 cum->words, cum->fregno);
5047 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5048 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5049 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5050 named, align, depth);
5056 spe_build_register_parallel (enum machine_mode mode, int gregno)
5059 enum machine_mode inner = SImode;
5063 r1 = gen_rtx_REG (inner, gregno);
5064 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
5065 r2 = gen_rtx_REG (inner, gregno + 1);
5066 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4));
5067 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5069 else if (mode == DCmode)
5071 r1 = gen_rtx_REG (inner, gregno);
5072 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
5073 r2 = gen_rtx_REG (inner, gregno + 1);
5074 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4));
5075 r3 = gen_rtx_REG (inner, gregno + 2);
5076 r3 = gen_rtx_EXPR_LIST (SImode, r3, GEN_INT (8));
5077 r4 = gen_rtx_REG (inner, gregno + 3);
5078 r4 = gen_rtx_EXPR_LIST (SImode, r4, GEN_INT (12));
5079 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r2, r3, r4));
5086 /* Determine where to put a SIMD argument on the SPE. */
5088 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5091 int gregno = cum->sysv_gregno;
5093 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5094 are passed and returned in a pair of GPRs for ABI compatibility. */
5095 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
5097 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5098 gregno += (1 - gregno) & 1;
5100 /* We do not split between registers and stack. */
5101 if (gregno + 1 > GP_ARG_MAX_REG)
5104 return spe_build_register_parallel (mode, gregno);
5108 int n_words = rs6000_arg_size (mode, type);
5110 /* SPE vectors are put in odd registers. */
5111 if (n_words == 2 && (gregno & 1) == 0)
5114 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5117 enum machine_mode m = SImode;
5119 r1 = gen_rtx_REG (m, gregno);
5120 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5121 r2 = gen_rtx_REG (m, gregno + 1);
5122 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5123 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5130 if (gregno <= GP_ARG_MAX_REG)
5131 return gen_rtx_REG (mode, gregno);
5137 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5138 the register(s) to be used for each field and subfield of a struct
5139 being passed by value, along with the offset of where the
5140 register's value may be found in the block. */
5143 rs6000_darwin64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5144 tree type, int named)
5146 tree f, ftype, offset;
5147 rtx rvec[FIRST_PSEUDO_REGISTER], sub, suboff, roffset;
5148 int k = 0, i, j, bytepos, subbytepos, tot;
5149 CUMULATIVE_ARGS saved_cum = *cum;
5150 enum machine_mode submode;
5152 switch (TREE_CODE (type))
5155 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5156 if (TREE_CODE (f) == FIELD_DECL)
5158 ftype = TREE_TYPE (f);
5159 offset = DECL_FIELD_OFFSET (f);
5160 bytepos = int_bit_position (f) / BITS_PER_UNIT;
5161 /* Force substructs to be handled as BLKmode even if
5162 they're small enough to be recorded as DImode, so we
5163 drill through to non-record fields. */
5164 submode = TYPE_MODE (ftype);
5165 if (TREE_CODE (ftype) == RECORD_TYPE)
5167 sub = function_arg (cum, submode, ftype, named);
5168 if (sub == NULL_RTX)
5170 if (GET_CODE (sub) == PARALLEL)
5172 for (i = 0; i < XVECLEN (sub, 0); i++)
5174 rtx subsub = XVECEXP (sub, 0, i);
5175 suboff = XEXP (subsub, 1);
5176 subbytepos = INTVAL (suboff);
5177 subbytepos += bytepos;
5178 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5179 subsub = XEXP (subsub, 0);
5180 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5185 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5186 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5188 /* Now do an arg advance to get all the cumulative arg
5189 stuff set correctly for the next subfield. Note that it
5190 has no lasting effect, because it is being done on a
5191 temporary copy of the cumulative arg data. */
5192 function_arg_advance (cum, submode, ftype, named, 1);
5197 tot = rs6000_arg_size (mode, type);
5202 for (j = 0; j < tot; ++j)
5204 sub = gen_rtx_REG ((TARGET_64BIT ? DImode : SImode), GP_ARG_MIN_REG + cum->words++);
5205 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5206 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5207 if (cum->words >= GP_ARG_NUM_REG)
5209 bytepos += (TARGET_64BIT ? 8 : 4);
5214 tot = int_size_in_bytes (type);
5217 ftype = TREE_TYPE (type);
5218 tot /= int_size_in_bytes (ftype);
5221 for (j = 0; j < tot; ++j)
5223 /* Force substructs to be handled as BLKmode even if
5224 they're small enough to be recorded as DImode, so we
5225 drill through to non-record fields. */
5226 submode = TYPE_MODE (ftype);
5227 if (TREE_CODE (ftype) == RECORD_TYPE)
5229 sub = function_arg (cum, submode, ftype, named);
5230 if (sub == NULL_RTX)
5232 if (GET_CODE (sub) == PARALLEL)
5234 for (i = 0; i < XVECLEN (sub, 0); i++)
5236 rtx subsub = XVECEXP (sub, 0, i);
5238 suboff = XEXP (subsub, 1);
5239 subbytepos = INTVAL (suboff);
5240 subbytepos += bytepos;
5241 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5242 subsub = XEXP (subsub, 0);
5243 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5248 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5249 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5251 /* Now do an arg advance to get all the cumulative arg
5252 stuff set correctly for the next subfield. Note that it
5253 has no lasting effect, because it is being done on a
5254 temporary copy of the cumulative arg data. */
5255 function_arg_advance (cum, submode, ftype, named, 1);
5256 bytepos += int_size_in_bytes (ftype);
5266 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5271 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5274 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5278 rtx rvec[GP_ARG_NUM_REG + 1];
5280 if (align_words >= GP_ARG_NUM_REG)
5283 n_units = rs6000_arg_size (mode, type);
5285 /* Optimize the simple case where the arg fits in one gpr, except in
5286 the case of BLKmode due to assign_parms assuming that registers are
5287 BITS_PER_WORD wide. */
5289 || (n_units == 1 && mode != BLKmode))
5290 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5293 if (align_words + n_units > GP_ARG_NUM_REG)
5294 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5295 using a magic NULL_RTX component.
5296 FIXME: This is not strictly correct. Only some of the arg
5297 belongs in memory, not all of it. However, there isn't any way
5298 to do this currently, apart from building rtx descriptions for
5299 the pieces of memory we want stored. Due to bugs in the generic
5300 code we can't use the normal function_arg_partial_nregs scheme
5301 with the PARALLEL arg description we emit here.
5302 In any case, the code to store the whole arg to memory is often
5303 more efficient than code to store pieces, and we know that space
5304 is available in the right place for the whole arg. */
5305 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5310 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5311 rtx off = GEN_INT (i++ * 4);
5312 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5314 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5316 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5319 /* Determine where to put an argument to a function.
5320 Value is zero to push the argument on the stack,
5321 or a hard register in which to store the argument.
5323 MODE is the argument's machine mode.
5324 TYPE is the data type of the argument (as a tree).
5325 This is null for libcalls where that information may
5327 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5328 the preceding args and about the function being called.
5329 NAMED is nonzero if this argument is a named parameter
5330 (otherwise it is an extra parameter matching an ellipsis).
5332 On RS/6000 the first eight words of non-FP are normally in registers
5333 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5334 Under V.4, the first 8 FP args are in registers.
5336 If this is floating-point and no prototype is specified, we use
5337 both an FP and integer register (or possibly FP reg and stack). Library
5338 functions (when CALL_LIBCALL is set) always have the proper types for args,
5339 so we can pass the FP value just in one register. emit_library_function
5340 doesn't support PARALLEL anyway.
5342 Note that for args passed by reference, function_arg will be called
5343 with MODE and TYPE set to that of the pointer to the arg, not the arg
5347 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5348 tree type, int named)
5350 enum rs6000_abi abi = DEFAULT_ABI;
5352 /* Return a marker to indicate whether CR1 needs to set or clear the
5353 bit that V.4 uses to say fp args were passed in registers.
5354 Assume that we don't need the marker for software floating point,
5355 or compiler generated library calls. */
5356 if (mode == VOIDmode)
5359 && cum->nargs_prototype < 0
5360 && (cum->call_cookie & CALL_LIBCALL) == 0
5361 && (cum->prototype || TARGET_NO_PROTOTYPE))
5363 /* For the SPE, we need to crxor CR6 always. */
5365 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5366 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5367 return GEN_INT (cum->call_cookie
5368 | ((cum->fregno == FP_ARG_MIN_REG)
5369 ? CALL_V4_SET_FP_ARGS
5370 : CALL_V4_CLEAR_FP_ARGS));
5373 return GEN_INT (cum->call_cookie);
5377 && rs6000_darwin64_abi
5378 && (TREE_CODE (type) == RECORD_TYPE
5379 || TREE_CODE (type) == UNION_TYPE
5380 || TREE_CODE (type) == ARRAY_TYPE))
5382 rtx rslt = rs6000_darwin64_function_arg (cum, mode, type, named);
5383 if (rslt != NULL_RTX)
5385 /* Else fall through to usual handling. */
5388 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5389 if (TARGET_64BIT && ! cum->prototype)
5391 /* Vector parameters get passed in vector register
5392 and also in GPRs or memory, in absence of prototype. */
5395 align_words = (cum->words + 1) & ~1;
5397 if (align_words >= GP_ARG_NUM_REG)
5403 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5405 return gen_rtx_PARALLEL (mode,
5407 gen_rtx_EXPR_LIST (VOIDmode,
5409 gen_rtx_EXPR_LIST (VOIDmode,
5410 gen_rtx_REG (mode, cum->vregno),
5414 return gen_rtx_REG (mode, cum->vregno);
5415 else if (TARGET_ALTIVEC_ABI
5416 && (ALTIVEC_VECTOR_MODE (mode)
5417 || (type && TREE_CODE (type) == VECTOR_TYPE
5418 && int_size_in_bytes (type) == 16)))
5420 if (named || abi == ABI_V4)
5424 /* Vector parameters to varargs functions under AIX or Darwin
5425 get passed in memory and possibly also in GPRs. */
5426 int align, align_words, n_words;
5427 enum machine_mode part_mode;
5429 /* Vector parameters must be 16-byte aligned. This places them at
5430 2 mod 4 in terms of words in 32-bit mode, since the parameter
5431 save area starts at offset 24 from the stack. In 64-bit mode,
5432 they just have to start on an even word, since the parameter
5433 save area is 16-byte aligned. */
5435 align = (2 - cum->words) & 3;
5437 align = cum->words & 1;
5438 align_words = cum->words + align;
5440 /* Out of registers? Memory, then. */
5441 if (align_words >= GP_ARG_NUM_REG)
5444 if (TARGET_32BIT && TARGET_POWERPC64)
5445 return rs6000_mixed_function_arg (mode, type, align_words);
5447 /* The vector value goes in GPRs. Only the part of the
5448 value in GPRs is reported here. */
5450 n_words = rs6000_arg_size (mode, type);
5451 if (align_words + n_words > GP_ARG_NUM_REG)
5452 /* Fortunately, there are only two possibilities, the value
5453 is either wholly in GPRs or half in GPRs and half not. */
5456 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5459 else if (TARGET_SPE_ABI && TARGET_SPE
5460 && (SPE_VECTOR_MODE (mode)
5461 || (TARGET_E500_DOUBLE && (mode == DFmode
5462 || mode == DCmode))))
5463 return rs6000_spe_function_arg (cum, mode, type);
5465 else if (abi == ABI_V4)
5467 if (TARGET_HARD_FLOAT && TARGET_FPRS
5468 && (mode == SFmode || mode == DFmode))
5470 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5471 return gen_rtx_REG (mode, cum->fregno);
5477 int n_words = rs6000_arg_size (mode, type);
5478 int gregno = cum->sysv_gregno;
5480 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5481 (r7,r8) or (r9,r10). As does any other 2 word item such
5482 as complex int due to a historical mistake. */
5484 gregno += (1 - gregno) & 1;
5486 /* Multi-reg args are not split between registers and stack. */
5487 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5490 if (TARGET_32BIT && TARGET_POWERPC64)
5491 return rs6000_mixed_function_arg (mode, type,
5492 gregno - GP_ARG_MIN_REG);
5493 return gen_rtx_REG (mode, gregno);
5498 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5499 int align_words = cum->words + (cum->words & align);
5501 if (USE_FP_FOR_ARG_P (cum, mode, type))
5503 rtx rvec[GP_ARG_NUM_REG + 1];
5507 enum machine_mode fmode = mode;
5508 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5510 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5512 /* Currently, we only ever need one reg here because complex
5513 doubles are split. */
5514 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
5517 /* Long double split over regs and memory. */
5521 /* Do we also need to pass this arg in the parameter save
5524 && (cum->nargs_prototype <= 0
5525 || (DEFAULT_ABI == ABI_AIX
5527 && align_words >= GP_ARG_NUM_REG)));
5529 if (!needs_psave && mode == fmode)
5530 return gen_rtx_REG (fmode, cum->fregno);
5535 /* Describe the part that goes in gprs or the stack.
5536 This piece must come first, before the fprs. */
5537 if (align_words < GP_ARG_NUM_REG)
5539 unsigned long n_words = rs6000_arg_size (mode, type);
5541 if (align_words + n_words > GP_ARG_NUM_REG
5542 || (TARGET_32BIT && TARGET_POWERPC64))
5544 /* If this is partially on the stack, then we only
5545 include the portion actually in registers here. */
5546 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5549 if (align_words + n_words > GP_ARG_NUM_REG
5550 && (TARGET_32BIT && TARGET_POWERPC64))
5551 /* Not all of the arg fits in gprs. Say that it
5552 goes in memory too, using a magic NULL_RTX
5553 component. Also see comment in
5554 rs6000_mixed_function_arg for why the normal
5555 function_arg_partial_nregs scheme doesn't work
5557 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5561 r = gen_rtx_REG (rmode,
5562 GP_ARG_MIN_REG + align_words);
5563 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5564 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5566 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5570 /* The whole arg fits in gprs. */
5571 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5572 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5576 /* It's entirely in memory. */
5577 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5580 /* Describe where this piece goes in the fprs. */
5581 r = gen_rtx_REG (fmode, cum->fregno);
5582 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5584 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5586 else if (align_words < GP_ARG_NUM_REG)
5588 if (TARGET_32BIT && TARGET_POWERPC64)
5589 return rs6000_mixed_function_arg (mode, type, align_words);
5591 if (mode == BLKmode)
5594 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5601 /* For an arg passed partly in registers and partly in memory, this is
5602 the number of registers used. For args passed entirely in registers
5603 or entirely in memory, zero. When an arg is described by a PARALLEL,
5604 perhaps using more than one register type, this function returns the
5605 number of registers used by the first element of the PARALLEL. */
5608 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5609 tree type, int named)
5616 if (DEFAULT_ABI == ABI_V4)
5619 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5620 && cum->nargs_prototype >= 0)
5623 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5624 parm_offset = TARGET_32BIT ? 2 : 0;
5625 align_words = cum->words + ((parm_offset - cum->words) & align);
5627 if (USE_FP_FOR_ARG_P (cum, mode, type)
5628 /* If we are passing this arg in gprs as well, then this function
5629 should return the number of gprs (or memory) partially passed,
5630 *not* the number of fprs. */
5632 && (cum->nargs_prototype <= 0
5633 || (DEFAULT_ABI == ABI_AIX
5635 && align_words >= GP_ARG_NUM_REG))))
5637 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5638 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
5639 else if (cum->nargs_prototype >= 0)
5643 if (align_words < GP_ARG_NUM_REG
5644 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5645 ret = GP_ARG_NUM_REG - align_words;
5647 if (ret != 0 && TARGET_DEBUG_ARG)
5648 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
5653 /* A C expression that indicates when an argument must be passed by
5654 reference. If nonzero for an argument, a copy of that argument is
5655 made in memory and a pointer to the argument is passed instead of
5656 the argument itself. The pointer is passed in whatever way is
5657 appropriate for passing a pointer to that type.
5659 Under V.4, aggregates and long double are passed by reference.
5661 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5662 reference unless the AltiVec vector extension ABI is in force.
5664 As an extension to all ABIs, variable sized types are passed by
5668 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5669 enum machine_mode mode, tree type,
5670 bool named ATTRIBUTE_UNUSED)
5672 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5674 if (TARGET_DEBUG_ARG)
5675 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5682 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5684 if (TARGET_DEBUG_ARG)
5685 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5689 if (int_size_in_bytes (type) < 0)
5691 if (TARGET_DEBUG_ARG)
5692 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5696 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5697 modes only exist for GCC vector types if -maltivec. */
5698 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5700 if (TARGET_DEBUG_ARG)
5701 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5705 /* Pass synthetic vectors in memory. */
5706 if (TREE_CODE (type) == VECTOR_TYPE
5707 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5709 static bool warned_for_pass_big_vectors = false;
5710 if (TARGET_DEBUG_ARG)
5711 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5712 if (!warned_for_pass_big_vectors)
5714 warning ("GCC vector passed by reference: "
5715 "non-standard ABI extension with no compatibility guarantee");
5716 warned_for_pass_big_vectors = true;
5725 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5728 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5733 for (i = 0; i < nregs; i++)
5735 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5736 if (reload_completed)
5738 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5741 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5742 i * GET_MODE_SIZE(reg_mode));
5745 tem = replace_equiv_address (tem, XEXP (tem, 0));
5747 if (tem == NULL_RTX)
5750 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5754 /* Perform any needed actions needed for a function that is receiving a
5755 variable number of arguments.
5759 MODE and TYPE are the mode and type of the current parameter.
5761 PRETEND_SIZE is a variable that should be set to the amount of stack
5762 that must be pushed by the prolog to pretend that our caller pushed
5765 Normally, this macro will push all remaining incoming registers on the
5766 stack and set PRETEND_SIZE to the length of the registers pushed. */
5769 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5770 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5773 CUMULATIVE_ARGS next_cum;
5774 int reg_size = TARGET_32BIT ? 4 : 8;
5775 rtx save_area = NULL_RTX, mem;
5776 int first_reg_offset, set;
5778 /* Skip the last named argument. */
5780 function_arg_advance (&next_cum, mode, type, 1, 0);
5782 if (DEFAULT_ABI == ABI_V4)
5785 save_area = plus_constant (virtual_stack_vars_rtx,
5786 - RS6000_VARARGS_SIZE);
5788 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5792 first_reg_offset = next_cum.words;
5793 save_area = virtual_incoming_args_rtx;
5795 if (targetm.calls.must_pass_in_stack (mode, type))
5796 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5799 set = get_varargs_alias_set ();
5800 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5802 mem = gen_rtx_MEM (BLKmode,
5803 plus_constant (save_area,
5804 first_reg_offset * reg_size)),
5805 set_mem_alias_set (mem, set);
5806 set_mem_align (mem, BITS_PER_WORD);
5808 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5809 GP_ARG_NUM_REG - first_reg_offset);
5812 /* Save FP registers if needed. */
5813 if (DEFAULT_ABI == ABI_V4
5814 && TARGET_HARD_FLOAT && TARGET_FPRS
5816 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5818 int fregno = next_cum.fregno;
5819 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5820 rtx lab = gen_label_rtx ();
5821 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5824 (gen_rtx_SET (VOIDmode,
5826 gen_rtx_IF_THEN_ELSE (VOIDmode,
5827 gen_rtx_NE (VOIDmode, cr1,
5829 gen_rtx_LABEL_REF (VOIDmode, lab),
5832 while (fregno <= FP_ARG_V4_MAX_REG)
5834 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5835 set_mem_alias_set (mem, set);
5836 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5837 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5846 /* Create the va_list data type. */
5849 rs6000_build_builtin_va_list (void)
5851 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5853 /* For AIX, prefer 'char *' because that's what the system
5854 header files like. */
5855 if (DEFAULT_ABI != ABI_V4)
5856 return build_pointer_type (char_type_node);
5858 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5859 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5861 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5862 unsigned_char_type_node);
5863 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5864 unsigned_char_type_node);
5865 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5867 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5868 short_unsigned_type_node);
5869 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5871 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5874 DECL_FIELD_CONTEXT (f_gpr) = record;
5875 DECL_FIELD_CONTEXT (f_fpr) = record;
5876 DECL_FIELD_CONTEXT (f_res) = record;
5877 DECL_FIELD_CONTEXT (f_ovf) = record;
5878 DECL_FIELD_CONTEXT (f_sav) = record;
5880 TREE_CHAIN (record) = type_decl;
5881 TYPE_NAME (record) = type_decl;
5882 TYPE_FIELDS (record) = f_gpr;
5883 TREE_CHAIN (f_gpr) = f_fpr;
5884 TREE_CHAIN (f_fpr) = f_res;
5885 TREE_CHAIN (f_res) = f_ovf;
5886 TREE_CHAIN (f_ovf) = f_sav;
5888 layout_type (record);
5890 /* The correct type is an array type of one element. */
5891 return build_array_type (record, build_index_type (size_zero_node));
5894 /* Implement va_start. */
5897 rs6000_va_start (tree valist, rtx nextarg)
5899 HOST_WIDE_INT words, n_gpr, n_fpr;
5900 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5901 tree gpr, fpr, ovf, sav, t;
5903 /* Only SVR4 needs something special. */
5904 if (DEFAULT_ABI != ABI_V4)
5906 std_expand_builtin_va_start (valist, nextarg);
5910 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5911 f_fpr = TREE_CHAIN (f_gpr);
5912 f_res = TREE_CHAIN (f_fpr);
5913 f_ovf = TREE_CHAIN (f_res);
5914 f_sav = TREE_CHAIN (f_ovf);
5916 valist = build_va_arg_indirect_ref (valist);
5917 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5918 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5919 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5920 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5922 /* Count number of gp and fp argument registers used. */
5923 words = current_function_args_info.words;
5924 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
5925 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
5927 if (TARGET_DEBUG_ARG)
5928 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5929 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5930 words, n_gpr, n_fpr);
5932 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5933 build_int_cst (NULL_TREE, n_gpr));
5934 TREE_SIDE_EFFECTS (t) = 1;
5935 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5937 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5938 build_int_cst (NULL_TREE, n_fpr));
5939 TREE_SIDE_EFFECTS (t) = 1;
5940 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5942 /* Find the overflow area. */
5943 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5945 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5946 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5947 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5948 TREE_SIDE_EFFECTS (t) = 1;
5949 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5951 /* Find the register save area. */
5952 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5953 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5954 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5955 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5956 TREE_SIDE_EFFECTS (t) = 1;
5957 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5960 /* Implement va_arg. */
5963 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5965 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5966 tree gpr, fpr, ovf, sav, reg, t, u;
5967 int size, rsize, n_reg, sav_ofs, sav_scale;
5968 tree lab_false, lab_over, addr;
5970 tree ptrtype = build_pointer_type (type);
5972 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5974 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5975 return build_va_arg_indirect_ref (t);
5978 if (DEFAULT_ABI != ABI_V4)
5980 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5982 tree elem_type = TREE_TYPE (type);
5983 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5984 int elem_size = GET_MODE_SIZE (elem_mode);
5986 if (elem_size < UNITS_PER_WORD)
5988 tree real_part, imag_part;
5989 tree post = NULL_TREE;
5991 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5993 /* Copy the value into a temporary, lest the formal temporary
5994 be reused out from under us. */
5995 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5996 append_to_statement_list (post, pre_p);
5998 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6001 return build (COMPLEX_EXPR, type, real_part, imag_part);
6005 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6008 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6009 f_fpr = TREE_CHAIN (f_gpr);
6010 f_res = TREE_CHAIN (f_fpr);
6011 f_ovf = TREE_CHAIN (f_res);
6012 f_sav = TREE_CHAIN (f_ovf);
6014 valist = build_va_arg_indirect_ref (valist);
6015 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6016 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6017 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6018 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6020 size = int_size_in_bytes (type);
6021 rsize = (size + 3) / 4;
6024 if (TARGET_HARD_FLOAT && TARGET_FPRS
6025 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
6027 /* FP args go in FP registers, if present. */
6032 if (TYPE_MODE (type) == DFmode)
6037 /* Otherwise into GP registers. */
6046 /* Pull the value out of the saved registers.... */
6049 addr = create_tmp_var (ptr_type_node, "addr");
6050 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6052 /* AltiVec vectors never go in registers when -mabi=altivec. */
6053 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6057 lab_false = create_artificial_label ();
6058 lab_over = create_artificial_label ();
6060 /* Long long and SPE vectors are aligned in the registers.
6061 As are any other 2 gpr item such as complex int due to a
6062 historical mistake. */
6066 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6067 size_int (n_reg - 1));
6068 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6071 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6072 t = build2 (GE_EXPR, boolean_type_node, u, t);
6073 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6074 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6075 gimplify_and_add (t, pre_p);
6079 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6081 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6082 u = build1 (CONVERT_EXPR, integer_type_node, u);
6083 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6084 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6086 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
6087 gimplify_and_add (t, pre_p);
6089 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6090 gimplify_and_add (t, pre_p);
6092 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6093 append_to_statement_list (t, pre_p);
6097 /* Ensure that we don't find any more args in regs.
6098 Alignment has taken care of the n_reg == 2 case. */
6099 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
6100 gimplify_and_add (t, pre_p);
6104 /* ... otherwise out of the overflow area. */
6106 /* Care for on-stack alignment if needed. */
6110 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6111 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6112 build_int_cst (NULL_TREE, -align));
6114 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6116 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
6117 gimplify_and_add (u, pre_p);
6119 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6120 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6121 gimplify_and_add (t, pre_p);
6125 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6126 append_to_statement_list (t, pre_p);
6129 addr = fold_convert (ptrtype, addr);
6130 return build_va_arg_indirect_ref (addr);
6135 #define def_builtin(MASK, NAME, TYPE, CODE) \
6137 if ((MASK) & target_flags) \
6138 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
6142 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6144 static const struct builtin_description bdesc_3arg[] =
6146 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6147 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6148 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6149 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6150 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6151 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6152 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6153 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6154 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6155 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6156 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6157 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6158 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6159 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6160 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6161 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6162 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6163 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6164 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6165 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6166 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6167 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6168 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6171 /* DST operations: void foo (void *, const int, const char). */
6173 static const struct builtin_description bdesc_dst[] =
6175 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6176 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6177 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6178 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
6181 /* Simple binary operations: VECc = foo (VECa, VECb). */
6183 static struct builtin_description bdesc_2arg[] =
6185 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6186 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6187 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6188 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6189 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6190 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6191 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6192 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6193 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6194 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6195 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6196 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6197 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6198 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6199 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6200 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6201 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6202 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6203 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6204 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6205 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6206 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6207 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6208 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6209 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6210 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6211 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6212 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6213 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6214 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6215 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6216 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6217 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6218 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6219 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6220 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6221 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6222 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6223 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6224 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6225 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6226 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6227 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6228 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6229 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6230 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6231 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6232 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6233 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6234 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6235 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6236 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6237 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6238 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6239 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6240 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6241 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6242 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6243 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6244 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6245 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6246 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6247 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6248 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6249 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6250 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6251 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6252 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6253 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6254 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
6255 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6256 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
6257 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6258 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6259 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6260 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6261 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6262 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6263 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6264 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6265 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6266 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6267 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6268 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6269 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6270 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6271 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6272 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6273 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6274 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6275 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6276 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6277 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6278 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6279 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6280 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6281 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6282 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6283 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6284 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6285 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6286 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6287 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6288 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6289 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6290 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6291 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6292 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6293 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6294 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6295 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6296 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6297 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6299 /* Place holder, leave as first spe builtin. */
6300 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6301 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6302 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6303 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6304 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6305 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6306 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6307 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6308 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6309 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6310 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6311 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6312 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6313 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6314 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6315 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6316 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6317 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6318 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6319 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6320 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6321 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6322 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6323 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6324 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6325 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6326 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6327 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6328 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6329 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6330 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6331 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6332 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6333 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6334 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6335 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6336 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6337 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6338 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6339 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6340 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6341 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6342 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6343 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6344 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6345 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6346 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6347 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6348 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6349 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6350 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6351 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6352 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6353 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6354 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6355 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6356 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6357 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6358 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6359 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6360 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6361 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6362 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6363 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6364 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6365 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6366 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6367 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6368 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6369 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6370 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6371 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6372 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6373 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6374 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6375 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6376 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6377 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6378 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6379 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6380 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6381 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6382 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6383 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6384 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6385 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6386 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6387 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6388 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6389 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6390 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6391 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6392 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6393 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6394 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6395 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6396 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6397 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6398 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6399 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6400 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6401 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6402 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6403 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6404 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6405 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6406 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6407 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6408 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6410 /* SPE binary operations expecting a 5-bit unsigned literal. */
6411 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6413 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6414 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6415 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6416 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6417 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6418 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6419 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6420 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6421 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6422 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6423 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6424 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6425 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6426 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6427 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6428 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6429 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6430 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6431 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6432 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6433 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6434 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6435 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6436 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6437 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6438 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6440 /* Place-holder. Leave as last binary SPE builtin. */
6441 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
6444 /* AltiVec predicates. */
6446 struct builtin_description_predicates
6448 const unsigned int mask;
6449 const enum insn_code icode;
6451 const char *const name;
6452 const enum rs6000_builtins code;
6455 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6457 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6458 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6459 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6460 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6461 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6462 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6463 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6464 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6465 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6466 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6467 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6468 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6469 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
6472 /* SPE predicates. */
6473 static struct builtin_description bdesc_spe_predicates[] =
6475 /* Place-holder. Leave as first. */
6476 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6477 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6478 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6479 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6480 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6481 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6482 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6483 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6484 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6485 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6486 /* Place-holder. Leave as last. */
6487 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6490 /* SPE evsel predicates. */
6491 static struct builtin_description bdesc_spe_evsel[] =
6493 /* Place-holder. Leave as first. */
6494 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6495 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6496 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6497 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6498 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6499 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6500 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6501 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6502 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6503 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6504 /* Place-holder. Leave as last. */
6505 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6508 /* ABS* operations. */
6510 static const struct builtin_description bdesc_abs[] =
6512 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6513 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6514 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6515 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6516 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6521 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6524 static struct builtin_description bdesc_1arg[] =
6526 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6528 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6529 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6530 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6531 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6532 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6533 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6534 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6535 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6536 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6537 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6538 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6539 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6540 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6541 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6542 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6544 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6545 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6546 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6547 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6548 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6549 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6550 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6551 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6552 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6553 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6554 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6555 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6556 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6557 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6558 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6559 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6560 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6561 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6562 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6563 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6564 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6565 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6566 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6567 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6568 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6569 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6570 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6571 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6572 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6573 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6575 /* Place-holder. Leave as last unary SPE builtin. */
6576 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
6580 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6583 tree arg0 = TREE_VALUE (arglist);
6584 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6585 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6586 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6588 if (icode == CODE_FOR_nothing)
6589 /* Builtin not supported on this processor. */
6592 /* If we got invalid arguments bail out before generating bad rtl. */
6593 if (arg0 == error_mark_node)
6596 if (icode == CODE_FOR_altivec_vspltisb
6597 || icode == CODE_FOR_altivec_vspltish
6598 || icode == CODE_FOR_altivec_vspltisw
6599 || icode == CODE_FOR_spe_evsplatfi
6600 || icode == CODE_FOR_spe_evsplati)
6602 /* Only allow 5-bit *signed* literals. */
6603 if (GET_CODE (op0) != CONST_INT
6604 || INTVAL (op0) > 0x1f
6605 || INTVAL (op0) < -0x1f)
6607 error ("argument 1 must be a 5-bit signed literal");
6613 || GET_MODE (target) != tmode
6614 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6615 target = gen_reg_rtx (tmode);
6617 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6618 op0 = copy_to_mode_reg (mode0, op0);
6620 pat = GEN_FCN (icode) (target, op0);
6629 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6631 rtx pat, scratch1, scratch2;
6632 tree arg0 = TREE_VALUE (arglist);
6633 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6634 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6635 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6637 /* If we have invalid arguments, bail out before generating bad rtl. */
6638 if (arg0 == error_mark_node)
6642 || GET_MODE (target) != tmode
6643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6644 target = gen_reg_rtx (tmode);
6646 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6647 op0 = copy_to_mode_reg (mode0, op0);
6649 scratch1 = gen_reg_rtx (mode0);
6650 scratch2 = gen_reg_rtx (mode0);
6652 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6661 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6664 tree arg0 = TREE_VALUE (arglist);
6665 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6666 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6667 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6668 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6669 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6670 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6672 if (icode == CODE_FOR_nothing)
6673 /* Builtin not supported on this processor. */
6676 /* If we got invalid arguments bail out before generating bad rtl. */
6677 if (arg0 == error_mark_node || arg1 == error_mark_node)
6680 if (icode == CODE_FOR_altivec_vcfux
6681 || icode == CODE_FOR_altivec_vcfsx
6682 || icode == CODE_FOR_altivec_vctsxs
6683 || icode == CODE_FOR_altivec_vctuxs
6684 || icode == CODE_FOR_altivec_vspltb
6685 || icode == CODE_FOR_altivec_vsplth
6686 || icode == CODE_FOR_altivec_vspltw
6687 || icode == CODE_FOR_spe_evaddiw
6688 || icode == CODE_FOR_spe_evldd
6689 || icode == CODE_FOR_spe_evldh
6690 || icode == CODE_FOR_spe_evldw
6691 || icode == CODE_FOR_spe_evlhhesplat
6692 || icode == CODE_FOR_spe_evlhhossplat
6693 || icode == CODE_FOR_spe_evlhhousplat
6694 || icode == CODE_FOR_spe_evlwhe
6695 || icode == CODE_FOR_spe_evlwhos
6696 || icode == CODE_FOR_spe_evlwhou
6697 || icode == CODE_FOR_spe_evlwhsplat
6698 || icode == CODE_FOR_spe_evlwwsplat
6699 || icode == CODE_FOR_spe_evrlwi
6700 || icode == CODE_FOR_spe_evslwi
6701 || icode == CODE_FOR_spe_evsrwis
6702 || icode == CODE_FOR_spe_evsubifw
6703 || icode == CODE_FOR_spe_evsrwiu)
6705 /* Only allow 5-bit unsigned literals. */
6707 if (TREE_CODE (arg1) != INTEGER_CST
6708 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6710 error ("argument 2 must be a 5-bit unsigned literal");
6716 || GET_MODE (target) != tmode
6717 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6718 target = gen_reg_rtx (tmode);
6720 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6721 op0 = copy_to_mode_reg (mode0, op0);
6722 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6723 op1 = copy_to_mode_reg (mode1, op1);
6725 pat = GEN_FCN (icode) (target, op0, op1);
6734 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6735 tree arglist, rtx target)
6738 tree cr6_form = TREE_VALUE (arglist);
6739 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6740 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6741 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6742 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6743 enum machine_mode tmode = SImode;
6744 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6745 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6748 if (TREE_CODE (cr6_form) != INTEGER_CST)
6750 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6754 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6759 /* If we have invalid arguments, bail out before generating bad rtl. */
6760 if (arg0 == error_mark_node || arg1 == error_mark_node)
6764 || GET_MODE (target) != tmode
6765 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6766 target = gen_reg_rtx (tmode);
6768 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6769 op0 = copy_to_mode_reg (mode0, op0);
6770 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6771 op1 = copy_to_mode_reg (mode1, op1);
6773 scratch = gen_reg_rtx (mode0);
6775 pat = GEN_FCN (icode) (scratch, op0, op1,
6776 gen_rtx_SYMBOL_REF (Pmode, opcode));
6781 /* The vec_any* and vec_all* predicates use the same opcodes for two
6782 different operations, but the bits in CR6 will be different
6783 depending on what information we want. So we have to play tricks
6784 with CR6 to get the right bits out.
6786 If you think this is disgusting, look at the specs for the
6787 AltiVec predicates. */
6789 switch (cr6_form_int)
6792 emit_insn (gen_cr6_test_for_zero (target));
6795 emit_insn (gen_cr6_test_for_zero_reverse (target));
6798 emit_insn (gen_cr6_test_for_lt (target));
6801 emit_insn (gen_cr6_test_for_lt_reverse (target));
6804 error ("argument 1 of __builtin_altivec_predicate is out of range");
6812 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6815 tree arg0 = TREE_VALUE (arglist);
6816 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6817 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6818 enum machine_mode mode0 = Pmode;
6819 enum machine_mode mode1 = Pmode;
6820 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6821 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6823 if (icode == CODE_FOR_nothing)
6824 /* Builtin not supported on this processor. */
6827 /* If we got invalid arguments bail out before generating bad rtl. */
6828 if (arg0 == error_mark_node || arg1 == error_mark_node)
6832 || GET_MODE (target) != tmode
6833 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6834 target = gen_reg_rtx (tmode);
6836 op1 = copy_to_mode_reg (mode1, op1);
6838 if (op0 == const0_rtx)
6840 addr = gen_rtx_MEM (tmode, op1);
6844 op0 = copy_to_mode_reg (mode0, op0);
6845 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6848 pat = GEN_FCN (icode) (target, addr);
6858 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6860 tree arg0 = TREE_VALUE (arglist);
6861 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6862 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6863 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6864 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6865 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6867 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6868 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6869 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6871 /* Invalid arguments. Bail before doing anything stoopid! */
6872 if (arg0 == error_mark_node
6873 || arg1 == error_mark_node
6874 || arg2 == error_mark_node)
6877 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6878 op0 = copy_to_mode_reg (mode2, op0);
6879 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6880 op1 = copy_to_mode_reg (mode0, op1);
6881 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6882 op2 = copy_to_mode_reg (mode1, op2);
6884 pat = GEN_FCN (icode) (op1, op2, op0);
6891 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6893 tree arg0 = TREE_VALUE (arglist);
6894 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6895 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6896 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6897 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6898 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6900 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6901 enum machine_mode mode1 = Pmode;
6902 enum machine_mode mode2 = Pmode;
6904 /* Invalid arguments. Bail before doing anything stoopid! */
6905 if (arg0 == error_mark_node
6906 || arg1 == error_mark_node
6907 || arg2 == error_mark_node)
6910 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6911 op0 = copy_to_mode_reg (tmode, op0);
6913 op2 = copy_to_mode_reg (mode2, op2);
6915 if (op1 == const0_rtx)
6917 addr = gen_rtx_MEM (tmode, op2);
6921 op1 = copy_to_mode_reg (mode1, op1);
6922 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6925 pat = GEN_FCN (icode) (addr, op0);
6932 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6935 tree arg0 = TREE_VALUE (arglist);
6936 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6937 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6938 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6939 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6940 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6941 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6942 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6943 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6944 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6946 if (icode == CODE_FOR_nothing)
6947 /* Builtin not supported on this processor. */
6950 /* If we got invalid arguments bail out before generating bad rtl. */
6951 if (arg0 == error_mark_node
6952 || arg1 == error_mark_node
6953 || arg2 == error_mark_node)
6956 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6957 || icode == CODE_FOR_altivec_vsldoi_v4si
6958 || icode == CODE_FOR_altivec_vsldoi_v8hi
6959 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6961 /* Only allow 4-bit unsigned literals. */
6963 if (TREE_CODE (arg2) != INTEGER_CST
6964 || TREE_INT_CST_LOW (arg2) & ~0xf)
6966 error ("argument 3 must be a 4-bit unsigned literal");
6972 || GET_MODE (target) != tmode
6973 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6974 target = gen_reg_rtx (tmode);
6976 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6977 op0 = copy_to_mode_reg (mode0, op0);
6978 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6979 op1 = copy_to_mode_reg (mode1, op1);
6980 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6981 op2 = copy_to_mode_reg (mode2, op2);
6983 pat = GEN_FCN (icode) (target, op0, op1, op2);
6991 /* Expand the lvx builtins. */
6993 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6995 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6996 tree arglist = TREE_OPERAND (exp, 1);
6997 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6999 enum machine_mode tmode, mode0;
7001 enum insn_code icode;
7005 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7006 icode = CODE_FOR_altivec_lvx_v16qi;
7008 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7009 icode = CODE_FOR_altivec_lvx_v8hi;
7011 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7012 icode = CODE_FOR_altivec_lvx_v4si;
7014 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7015 icode = CODE_FOR_altivec_lvx_v4sf;
7024 arg0 = TREE_VALUE (arglist);
7025 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7026 tmode = insn_data[icode].operand[0].mode;
7027 mode0 = insn_data[icode].operand[1].mode;
7030 || GET_MODE (target) != tmode
7031 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7032 target = gen_reg_rtx (tmode);
7034 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7035 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7037 pat = GEN_FCN (icode) (target, op0);
7044 /* Expand the stvx builtins. */
7046 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7049 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7050 tree arglist = TREE_OPERAND (exp, 1);
7051 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7053 enum machine_mode mode0, mode1;
7055 enum insn_code icode;
7059 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7060 icode = CODE_FOR_altivec_stvx_v16qi;
7062 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7063 icode = CODE_FOR_altivec_stvx_v8hi;
7065 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7066 icode = CODE_FOR_altivec_stvx_v4si;
7068 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7069 icode = CODE_FOR_altivec_stvx_v4sf;
7076 arg0 = TREE_VALUE (arglist);
7077 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7078 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7079 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7080 mode0 = insn_data[icode].operand[0].mode;
7081 mode1 = insn_data[icode].operand[1].mode;
7083 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7084 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7085 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7086 op1 = copy_to_mode_reg (mode1, op1);
7088 pat = GEN_FCN (icode) (op0, op1);
7096 /* Expand the dst builtins. */
7098 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7101 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7102 tree arglist = TREE_OPERAND (exp, 1);
7103 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7104 tree arg0, arg1, arg2;
7105 enum machine_mode mode0, mode1, mode2;
7106 rtx pat, op0, op1, op2;
7107 struct builtin_description *d;
7112 /* Handle DST variants. */
7113 d = (struct builtin_description *) bdesc_dst;
7114 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7115 if (d->code == fcode)
7117 arg0 = TREE_VALUE (arglist);
7118 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7119 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7120 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7121 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7122 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7123 mode0 = insn_data[d->icode].operand[0].mode;
7124 mode1 = insn_data[d->icode].operand[1].mode;
7125 mode2 = insn_data[d->icode].operand[2].mode;
7127 /* Invalid arguments, bail out before generating bad rtl. */
7128 if (arg0 == error_mark_node
7129 || arg1 == error_mark_node
7130 || arg2 == error_mark_node)
7135 if (TREE_CODE (arg2) != INTEGER_CST
7136 || TREE_INT_CST_LOW (arg2) & ~0x3)
7138 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7142 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7143 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7144 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7145 op1 = copy_to_mode_reg (mode1, op1);
7147 pat = GEN_FCN (d->icode) (op0, op1, op2);
7157 /* Expand the builtin in EXP and store the result in TARGET. Store
7158 true in *EXPANDEDP if we found a builtin to expand. */
7160 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7162 struct builtin_description *d;
7163 struct builtin_description_predicates *dp;
7165 enum insn_code icode;
7166 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7167 tree arglist = TREE_OPERAND (exp, 1);
7170 enum machine_mode tmode, mode0;
7171 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7173 target = altivec_expand_ld_builtin (exp, target, expandedp);
7177 target = altivec_expand_st_builtin (exp, target, expandedp);
7181 target = altivec_expand_dst_builtin (exp, target, expandedp);
7189 case ALTIVEC_BUILTIN_STVX:
7190 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7191 case ALTIVEC_BUILTIN_STVEBX:
7192 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7193 case ALTIVEC_BUILTIN_STVEHX:
7194 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7195 case ALTIVEC_BUILTIN_STVEWX:
7196 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7197 case ALTIVEC_BUILTIN_STVXL:
7198 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7200 case ALTIVEC_BUILTIN_MFVSCR:
7201 icode = CODE_FOR_altivec_mfvscr;
7202 tmode = insn_data[icode].operand[0].mode;
7205 || GET_MODE (target) != tmode
7206 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7207 target = gen_reg_rtx (tmode);
7209 pat = GEN_FCN (icode) (target);
7215 case ALTIVEC_BUILTIN_MTVSCR:
7216 icode = CODE_FOR_altivec_mtvscr;
7217 arg0 = TREE_VALUE (arglist);
7218 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7219 mode0 = insn_data[icode].operand[0].mode;
7221 /* If we got invalid arguments bail out before generating bad rtl. */
7222 if (arg0 == error_mark_node)
7225 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7226 op0 = copy_to_mode_reg (mode0, op0);
7228 pat = GEN_FCN (icode) (op0);
7233 case ALTIVEC_BUILTIN_DSSALL:
7234 emit_insn (gen_altivec_dssall ());
7237 case ALTIVEC_BUILTIN_DSS:
7238 icode = CODE_FOR_altivec_dss;
7239 arg0 = TREE_VALUE (arglist);
7241 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7242 mode0 = insn_data[icode].operand[0].mode;
7244 /* If we got invalid arguments bail out before generating bad rtl. */
7245 if (arg0 == error_mark_node)
7248 if (TREE_CODE (arg0) != INTEGER_CST
7249 || TREE_INT_CST_LOW (arg0) & ~0x3)
7251 error ("argument to dss must be a 2-bit unsigned literal");
7255 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7256 op0 = copy_to_mode_reg (mode0, op0);
7258 emit_insn (gen_altivec_dss (op0));
7261 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
7262 arg0 = TREE_VALUE (arglist);
7263 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
7264 || TREE_CODE (arg0) == ARRAY_REF)
7265 arg0 = TREE_OPERAND (arg0, 0);
7266 error ("invalid parameter combination for %qs AltiVec intrinsic",
7267 TREE_STRING_POINTER (arg0));
7272 /* Expand abs* operations. */
7273 d = (struct builtin_description *) bdesc_abs;
7274 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7275 if (d->code == fcode)
7276 return altivec_expand_abs_builtin (d->icode, arglist, target);
7278 /* Expand the AltiVec predicates. */
7279 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7280 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7281 if (dp->code == fcode)
7282 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7285 /* LV* are funky. We initialized them differently. */
7288 case ALTIVEC_BUILTIN_LVSL:
7289 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7291 case ALTIVEC_BUILTIN_LVSR:
7292 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7294 case ALTIVEC_BUILTIN_LVEBX:
7295 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7297 case ALTIVEC_BUILTIN_LVEHX:
7298 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7300 case ALTIVEC_BUILTIN_LVEWX:
7301 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7303 case ALTIVEC_BUILTIN_LVXL:
7304 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7306 case ALTIVEC_BUILTIN_LVX:
7307 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7318 /* Binops that need to be initialized manually, but can be expanded
7319 automagically by rs6000_expand_binop_builtin. */
7320 static struct builtin_description bdesc_2arg_spe[] =
7322 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7323 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7324 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7325 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7326 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7327 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7328 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7329 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7330 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7331 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7332 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7333 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7334 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7335 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7336 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7337 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7338 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7339 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7340 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7341 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7342 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7343 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7346 /* Expand the builtin in EXP and store the result in TARGET. Store
7347 true in *EXPANDEDP if we found a builtin to expand.
7349 This expands the SPE builtins that are not simple unary and binary
7352 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7354 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7355 tree arglist = TREE_OPERAND (exp, 1);
7357 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7358 enum insn_code icode;
7359 enum machine_mode tmode, mode0;
7361 struct builtin_description *d;
7366 /* Syntax check for a 5-bit unsigned immediate. */
7369 case SPE_BUILTIN_EVSTDD:
7370 case SPE_BUILTIN_EVSTDH:
7371 case SPE_BUILTIN_EVSTDW:
7372 case SPE_BUILTIN_EVSTWHE:
7373 case SPE_BUILTIN_EVSTWHO:
7374 case SPE_BUILTIN_EVSTWWE:
7375 case SPE_BUILTIN_EVSTWWO:
7376 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7377 if (TREE_CODE (arg1) != INTEGER_CST
7378 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7380 error ("argument 2 must be a 5-bit unsigned literal");
7388 /* The evsplat*i instructions are not quite generic. */
7391 case SPE_BUILTIN_EVSPLATFI:
7392 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7394 case SPE_BUILTIN_EVSPLATI:
7395 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7401 d = (struct builtin_description *) bdesc_2arg_spe;
7402 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7403 if (d->code == fcode)
7404 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7406 d = (struct builtin_description *) bdesc_spe_predicates;
7407 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7408 if (d->code == fcode)
7409 return spe_expand_predicate_builtin (d->icode, arglist, target);
7411 d = (struct builtin_description *) bdesc_spe_evsel;
7412 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7413 if (d->code == fcode)
7414 return spe_expand_evsel_builtin (d->icode, arglist, target);
7418 case SPE_BUILTIN_EVSTDDX:
7419 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7420 case SPE_BUILTIN_EVSTDHX:
7421 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7422 case SPE_BUILTIN_EVSTDWX:
7423 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7424 case SPE_BUILTIN_EVSTWHEX:
7425 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7426 case SPE_BUILTIN_EVSTWHOX:
7427 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7428 case SPE_BUILTIN_EVSTWWEX:
7429 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7430 case SPE_BUILTIN_EVSTWWOX:
7431 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7432 case SPE_BUILTIN_EVSTDD:
7433 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7434 case SPE_BUILTIN_EVSTDH:
7435 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7436 case SPE_BUILTIN_EVSTDW:
7437 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7438 case SPE_BUILTIN_EVSTWHE:
7439 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7440 case SPE_BUILTIN_EVSTWHO:
7441 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7442 case SPE_BUILTIN_EVSTWWE:
7443 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7444 case SPE_BUILTIN_EVSTWWO:
7445 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7446 case SPE_BUILTIN_MFSPEFSCR:
7447 icode = CODE_FOR_spe_mfspefscr;
7448 tmode = insn_data[icode].operand[0].mode;
7451 || GET_MODE (target) != tmode
7452 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7453 target = gen_reg_rtx (tmode);
7455 pat = GEN_FCN (icode) (target);
7460 case SPE_BUILTIN_MTSPEFSCR:
7461 icode = CODE_FOR_spe_mtspefscr;
7462 arg0 = TREE_VALUE (arglist);
7463 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7464 mode0 = insn_data[icode].operand[0].mode;
7466 if (arg0 == error_mark_node)
7469 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7470 op0 = copy_to_mode_reg (mode0, op0);
7472 pat = GEN_FCN (icode) (op0);
7485 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7487 rtx pat, scratch, tmp;
7488 tree form = TREE_VALUE (arglist);
7489 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7490 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7491 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7492 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7493 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7494 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7498 if (TREE_CODE (form) != INTEGER_CST)
7500 error ("argument 1 of __builtin_spe_predicate must be a constant");
7504 form_int = TREE_INT_CST_LOW (form);
7509 if (arg0 == error_mark_node || arg1 == error_mark_node)
7513 || GET_MODE (target) != SImode
7514 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7515 target = gen_reg_rtx (SImode);
7517 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7518 op0 = copy_to_mode_reg (mode0, op0);
7519 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7520 op1 = copy_to_mode_reg (mode1, op1);
7522 scratch = gen_reg_rtx (CCmode);
7524 pat = GEN_FCN (icode) (scratch, op0, op1);
7529 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7530 _lower_. We use one compare, but look in different bits of the
7531 CR for each variant.
7533 There are 2 elements in each SPE simd type (upper/lower). The CR
7534 bits are set as follows:
7536 BIT0 | BIT 1 | BIT 2 | BIT 3
7537 U | L | (U | L) | (U & L)
7539 So, for an "all" relationship, BIT 3 would be set.
7540 For an "any" relationship, BIT 2 would be set. Etc.
7542 Following traditional nomenclature, these bits map to:
7544 BIT0 | BIT 1 | BIT 2 | BIT 3
7547 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7552 /* All variant. OV bit. */
7554 /* We need to get to the OV bit, which is the ORDERED bit. We
7555 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7556 that's ugly and will trigger a validate_condition_mode abort.
7557 So let's just use another pattern. */
7558 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7560 /* Any variant. EQ bit. */
7564 /* Upper variant. LT bit. */
7568 /* Lower variant. GT bit. */
7573 error ("argument 1 of __builtin_spe_predicate is out of range");
7577 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7578 emit_move_insn (target, tmp);
7583 /* The evsel builtins look like this:
7585 e = __builtin_spe_evsel_OP (a, b, c, d);
7589 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7590 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7594 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7597 tree arg0 = TREE_VALUE (arglist);
7598 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7599 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7600 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7601 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7602 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7603 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7604 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7605 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7606 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7611 if (arg0 == error_mark_node || arg1 == error_mark_node
7612 || arg2 == error_mark_node || arg3 == error_mark_node)
7616 || GET_MODE (target) != mode0
7617 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7618 target = gen_reg_rtx (mode0);
7620 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7621 op0 = copy_to_mode_reg (mode0, op0);
7622 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7623 op1 = copy_to_mode_reg (mode0, op1);
7624 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7625 op2 = copy_to_mode_reg (mode0, op2);
7626 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7627 op3 = copy_to_mode_reg (mode0, op3);
7629 /* Generate the compare. */
7630 scratch = gen_reg_rtx (CCmode);
7631 pat = GEN_FCN (icode) (scratch, op0, op1);
7636 if (mode0 == V2SImode)
7637 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7639 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7644 /* Expand an expression EXP that calls a built-in function,
7645 with result going to TARGET if that's convenient
7646 (and in mode MODE if that's convenient).
7647 SUBTARGET may be used as the target for computing one of EXP's operands.
7648 IGNORE is nonzero if the value is to be ignored. */
7651 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7652 enum machine_mode mode ATTRIBUTE_UNUSED,
7653 int ignore ATTRIBUTE_UNUSED)
7655 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7656 tree arglist = TREE_OPERAND (exp, 1);
7657 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7658 struct builtin_description *d;
7663 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7664 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7666 int icode = (int) CODE_FOR_altivec_lvsr;
7667 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7668 enum machine_mode mode = insn_data[icode].operand[1].mode;
7672 if (!TARGET_ALTIVEC)
7675 arg = TREE_VALUE (arglist);
7676 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7678 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7679 addr = memory_address (mode, op);
7680 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7684 /* For the load case need to negate the address. */
7685 op = gen_reg_rtx (GET_MODE (addr));
7686 emit_insn (gen_rtx_SET (VOIDmode, op,
7687 gen_rtx_NEG (GET_MODE (addr), addr)));
7689 op = gen_rtx_MEM (mode, op);
7692 || GET_MODE (target) != tmode
7693 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7694 target = gen_reg_rtx (tmode);
7696 /*pat = gen_altivec_lvsr (target, op);*/
7697 pat = GEN_FCN (icode) (target, op);
7707 ret = altivec_expand_builtin (exp, target, &success);
7714 ret = spe_expand_builtin (exp, target, &success);
7720 if (TARGET_ALTIVEC || TARGET_SPE)
7722 /* Handle simple unary operations. */
7723 d = (struct builtin_description *) bdesc_1arg;
7724 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7725 if (d->code == fcode)
7726 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7728 /* Handle simple binary operations. */
7729 d = (struct builtin_description *) bdesc_2arg;
7730 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7731 if (d->code == fcode)
7732 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7734 /* Handle simple ternary operations. */
7735 d = (struct builtin_description *) bdesc_3arg;
7736 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7737 if (d->code == fcode)
7738 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7746 build_opaque_vector_type (tree node, int nunits)
7748 node = copy_node (node);
7749 TYPE_MAIN_VARIANT (node) = node;
7750 return build_vector_type (node, nunits);
7754 rs6000_init_builtins (void)
7756 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7757 V2SF_type_node = build_vector_type (float_type_node, 2);
7758 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7759 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7760 V4SF_type_node = build_vector_type (float_type_node, 4);
7761 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7762 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7764 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7765 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7766 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7768 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7769 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7770 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7772 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7773 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7774 'vector unsigned short'. */
7776 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7777 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7778 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7779 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7781 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7782 get_identifier ("__bool char"),
7783 bool_char_type_node));
7784 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7785 get_identifier ("__bool short"),
7786 bool_short_type_node));
7787 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7788 get_identifier ("__bool int"),
7789 bool_int_type_node));
7790 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7791 get_identifier ("__pixel"),
7794 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7795 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7796 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7797 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7799 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7800 get_identifier ("__vector unsigned char"),
7801 unsigned_V16QI_type_node));
7802 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7803 get_identifier ("__vector signed char"),
7805 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7806 get_identifier ("__vector __bool char"),
7807 bool_V16QI_type_node));
7809 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7810 get_identifier ("__vector unsigned short"),
7811 unsigned_V8HI_type_node));
7812 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7813 get_identifier ("__vector signed short"),
7815 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7816 get_identifier ("__vector __bool short"),
7817 bool_V8HI_type_node));
7819 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7820 get_identifier ("__vector unsigned int"),
7821 unsigned_V4SI_type_node));
7822 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7823 get_identifier ("__vector signed int"),
7825 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7826 get_identifier ("__vector __bool int"),
7827 bool_V4SI_type_node));
7829 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7830 get_identifier ("__vector float"),
7832 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7833 get_identifier ("__vector __pixel"),
7834 pixel_V8HI_type_node));
7837 spe_init_builtins ();
7839 altivec_init_builtins ();
7840 if (TARGET_ALTIVEC || TARGET_SPE)
7841 rs6000_common_init_builtins ();
7844 /* Search through a set of builtins and enable the mask bits.
7845 DESC is an array of builtins.
7846 SIZE is the total number of builtins.
7847 START is the builtin enum at which to start.
7848 END is the builtin enum at which to end. */
7850 enable_mask_for_builtins (struct builtin_description *desc, int size,
7851 enum rs6000_builtins start,
7852 enum rs6000_builtins end)
7856 for (i = 0; i < size; ++i)
7857 if (desc[i].code == start)
7863 for (; i < size; ++i)
7865 /* Flip all the bits on. */
7866 desc[i].mask = target_flags;
7867 if (desc[i].code == end)
7873 spe_init_builtins (void)
7875 tree endlink = void_list_node;
7876 tree puint_type_node = build_pointer_type (unsigned_type_node);
7877 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7878 struct builtin_description *d;
7881 tree v2si_ftype_4_v2si
7882 = build_function_type
7883 (opaque_V2SI_type_node,
7884 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7885 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7886 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7887 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7890 tree v2sf_ftype_4_v2sf
7891 = build_function_type
7892 (opaque_V2SF_type_node,
7893 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7894 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7895 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7896 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7899 tree int_ftype_int_v2si_v2si
7900 = build_function_type
7902 tree_cons (NULL_TREE, integer_type_node,
7903 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7904 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7907 tree int_ftype_int_v2sf_v2sf
7908 = build_function_type
7910 tree_cons (NULL_TREE, integer_type_node,
7911 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7912 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7915 tree void_ftype_v2si_puint_int
7916 = build_function_type (void_type_node,
7917 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7918 tree_cons (NULL_TREE, puint_type_node,
7919 tree_cons (NULL_TREE,
7923 tree void_ftype_v2si_puint_char
7924 = build_function_type (void_type_node,
7925 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7926 tree_cons (NULL_TREE, puint_type_node,
7927 tree_cons (NULL_TREE,
7931 tree void_ftype_v2si_pv2si_int
7932 = build_function_type (void_type_node,
7933 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7934 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7935 tree_cons (NULL_TREE,
7939 tree void_ftype_v2si_pv2si_char
7940 = build_function_type (void_type_node,
7941 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7942 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7943 tree_cons (NULL_TREE,
7948 = build_function_type (void_type_node,
7949 tree_cons (NULL_TREE, integer_type_node, endlink));
7952 = build_function_type (integer_type_node, endlink);
7954 tree v2si_ftype_pv2si_int
7955 = build_function_type (opaque_V2SI_type_node,
7956 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7957 tree_cons (NULL_TREE, integer_type_node,
7960 tree v2si_ftype_puint_int
7961 = build_function_type (opaque_V2SI_type_node,
7962 tree_cons (NULL_TREE, puint_type_node,
7963 tree_cons (NULL_TREE, integer_type_node,
7966 tree v2si_ftype_pushort_int
7967 = build_function_type (opaque_V2SI_type_node,
7968 tree_cons (NULL_TREE, pushort_type_node,
7969 tree_cons (NULL_TREE, integer_type_node,
7972 tree v2si_ftype_signed_char
7973 = build_function_type (opaque_V2SI_type_node,
7974 tree_cons (NULL_TREE, signed_char_type_node,
7977 /* The initialization of the simple binary and unary builtins is
7978 done in rs6000_common_init_builtins, but we have to enable the
7979 mask bits here manually because we have run out of `target_flags'
7980 bits. We really need to redesign this mask business. */
7982 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7983 ARRAY_SIZE (bdesc_2arg),
7986 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7987 ARRAY_SIZE (bdesc_1arg),
7989 SPE_BUILTIN_EVSUBFUSIAAW);
7990 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7991 ARRAY_SIZE (bdesc_spe_predicates),
7992 SPE_BUILTIN_EVCMPEQ,
7993 SPE_BUILTIN_EVFSTSTLT);
7994 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7995 ARRAY_SIZE (bdesc_spe_evsel),
7996 SPE_BUILTIN_EVSEL_CMPGTS,
7997 SPE_BUILTIN_EVSEL_FSTSTEQ);
7999 (*lang_hooks.decls.pushdecl)
8000 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8001 opaque_V2SI_type_node));
8003 /* Initialize irregular SPE builtins. */
8005 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8006 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8007 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8008 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8009 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8010 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8011 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8012 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8013 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8014 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8015 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8016 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8017 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8018 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8019 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8020 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8021 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8022 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8025 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8026 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8027 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8028 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8029 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8030 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8031 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8032 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8033 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8034 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8035 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8036 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8037 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8038 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8039 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8040 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8041 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8042 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8043 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8044 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8045 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8046 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8049 d = (struct builtin_description *) bdesc_spe_predicates;
8050 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8054 switch (insn_data[d->icode].operand[1].mode)
8057 type = int_ftype_int_v2si_v2si;
8060 type = int_ftype_int_v2sf_v2sf;
8066 def_builtin (d->mask, d->name, type, d->code);
8069 /* Evsel predicates. */
8070 d = (struct builtin_description *) bdesc_spe_evsel;
8071 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8075 switch (insn_data[d->icode].operand[1].mode)
8078 type = v2si_ftype_4_v2si;
8081 type = v2sf_ftype_4_v2sf;
8087 def_builtin (d->mask, d->name, type, d->code);
8092 altivec_init_builtins (void)
8094 struct builtin_description *d;
8095 struct builtin_description_predicates *dp;
8097 tree pfloat_type_node = build_pointer_type (float_type_node);
8098 tree pint_type_node = build_pointer_type (integer_type_node);
8099 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8100 tree pchar_type_node = build_pointer_type (char_type_node);
8102 tree pvoid_type_node = build_pointer_type (void_type_node);
8104 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8105 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8106 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8107 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8109 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8111 tree int_ftype_int_v4si_v4si
8112 = build_function_type_list (integer_type_node,
8113 integer_type_node, V4SI_type_node,
8114 V4SI_type_node, NULL_TREE);
8115 tree v4sf_ftype_pcfloat
8116 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8117 tree void_ftype_pfloat_v4sf
8118 = build_function_type_list (void_type_node,
8119 pfloat_type_node, V4SF_type_node, NULL_TREE);
8120 tree v4si_ftype_pcint
8121 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8122 tree void_ftype_pint_v4si
8123 = build_function_type_list (void_type_node,
8124 pint_type_node, V4SI_type_node, NULL_TREE);
8125 tree v8hi_ftype_pcshort
8126 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8127 tree void_ftype_pshort_v8hi
8128 = build_function_type_list (void_type_node,
8129 pshort_type_node, V8HI_type_node, NULL_TREE);
8130 tree v16qi_ftype_pcchar
8131 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8132 tree void_ftype_pchar_v16qi
8133 = build_function_type_list (void_type_node,
8134 pchar_type_node, V16QI_type_node, NULL_TREE);
8135 tree void_ftype_v4si
8136 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8137 tree v8hi_ftype_void
8138 = build_function_type (V8HI_type_node, void_list_node);
8139 tree void_ftype_void
8140 = build_function_type (void_type_node, void_list_node);
8142 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8144 tree v16qi_ftype_long_pcvoid
8145 = build_function_type_list (V16QI_type_node,
8146 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8147 tree v8hi_ftype_long_pcvoid
8148 = build_function_type_list (V8HI_type_node,
8149 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8150 tree v4si_ftype_long_pcvoid
8151 = build_function_type_list (V4SI_type_node,
8152 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8154 tree void_ftype_v4si_long_pvoid
8155 = build_function_type_list (void_type_node,
8156 V4SI_type_node, long_integer_type_node,
8157 pvoid_type_node, NULL_TREE);
8158 tree void_ftype_v16qi_long_pvoid
8159 = build_function_type_list (void_type_node,
8160 V16QI_type_node, long_integer_type_node,
8161 pvoid_type_node, NULL_TREE);
8162 tree void_ftype_v8hi_long_pvoid
8163 = build_function_type_list (void_type_node,
8164 V8HI_type_node, long_integer_type_node,
8165 pvoid_type_node, NULL_TREE);
8166 tree int_ftype_int_v8hi_v8hi
8167 = build_function_type_list (integer_type_node,
8168 integer_type_node, V8HI_type_node,
8169 V8HI_type_node, NULL_TREE);
8170 tree int_ftype_int_v16qi_v16qi
8171 = build_function_type_list (integer_type_node,
8172 integer_type_node, V16QI_type_node,
8173 V16QI_type_node, NULL_TREE);
8174 tree int_ftype_int_v4sf_v4sf
8175 = build_function_type_list (integer_type_node,
8176 integer_type_node, V4SF_type_node,
8177 V4SF_type_node, NULL_TREE);
8178 tree v4si_ftype_v4si
8179 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8180 tree v8hi_ftype_v8hi
8181 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8182 tree v16qi_ftype_v16qi
8183 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8184 tree v4sf_ftype_v4sf
8185 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8186 tree void_ftype_pcvoid_int_int
8187 = build_function_type_list (void_type_node,
8188 pcvoid_type_node, integer_type_node,
8189 integer_type_node, NULL_TREE);
8190 tree int_ftype_pcchar
8191 = build_function_type_list (integer_type_node,
8192 pcchar_type_node, NULL_TREE);
8194 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8195 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8196 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8197 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8198 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8199 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8200 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8201 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8202 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8203 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8204 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8205 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8206 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8207 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8208 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8209 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8210 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8211 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8212 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8213 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8214 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8215 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8216 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8217 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8218 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8219 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8220 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8221 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8222 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8223 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8224 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8225 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8227 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
8228 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
8229 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
8231 /* Add the DST variants. */
8232 d = (struct builtin_description *) bdesc_dst;
8233 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8234 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8236 /* Initialize the predicates. */
8237 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8238 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8240 enum machine_mode mode1;
8243 mode1 = insn_data[dp->icode].operand[1].mode;
8248 type = int_ftype_int_v4si_v4si;
8251 type = int_ftype_int_v8hi_v8hi;
8254 type = int_ftype_int_v16qi_v16qi;
8257 type = int_ftype_int_v4sf_v4sf;
8263 def_builtin (dp->mask, dp->name, type, dp->code);
8266 /* Initialize the abs* operators. */
8267 d = (struct builtin_description *) bdesc_abs;
8268 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8270 enum machine_mode mode0;
8273 mode0 = insn_data[d->icode].operand[0].mode;
8278 type = v4si_ftype_v4si;
8281 type = v8hi_ftype_v8hi;
8284 type = v16qi_ftype_v16qi;
8287 type = v4sf_ftype_v4sf;
8293 def_builtin (d->mask, d->name, type, d->code);
8300 /* Initialize target builtin that implements
8301 targetm.vectorize.builtin_mask_for_load. */
8303 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8304 v16qi_ftype_long_pcvoid,
8305 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8306 BUILT_IN_MD, NULL, NULL_TREE);
8307 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8308 altivec_builtin_mask_for_load = decl;
8311 /* Initialize target builtin that implements
8312 targetm.vectorize.builtin_mask_for_store. */
8314 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_store",
8315 v16qi_ftype_long_pcvoid,
8316 ALTIVEC_BUILTIN_MASK_FOR_STORE,
8317 BUILT_IN_MD, NULL, NULL_TREE);
8318 /* Record the decl. Will be used by rs6000_builtin_mask_for_store. */
8319 altivec_builtin_mask_for_store = decl;
8324 rs6000_common_init_builtins (void)
8326 struct builtin_description *d;
8329 tree v4sf_ftype_v4sf_v4sf_v16qi
8330 = build_function_type_list (V4SF_type_node,
8331 V4SF_type_node, V4SF_type_node,
8332 V16QI_type_node, NULL_TREE);
8333 tree v4si_ftype_v4si_v4si_v16qi
8334 = build_function_type_list (V4SI_type_node,
8335 V4SI_type_node, V4SI_type_node,
8336 V16QI_type_node, NULL_TREE);
8337 tree v8hi_ftype_v8hi_v8hi_v16qi
8338 = build_function_type_list (V8HI_type_node,
8339 V8HI_type_node, V8HI_type_node,
8340 V16QI_type_node, NULL_TREE);
8341 tree v16qi_ftype_v16qi_v16qi_v16qi
8342 = build_function_type_list (V16QI_type_node,
8343 V16QI_type_node, V16QI_type_node,
8344 V16QI_type_node, NULL_TREE);
8346 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8348 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8349 tree v16qi_ftype_int
8350 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8351 tree v8hi_ftype_v16qi
8352 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8353 tree v4sf_ftype_v4sf
8354 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8356 tree v2si_ftype_v2si_v2si
8357 = build_function_type_list (opaque_V2SI_type_node,
8358 opaque_V2SI_type_node,
8359 opaque_V2SI_type_node, NULL_TREE);
8361 tree v2sf_ftype_v2sf_v2sf
8362 = build_function_type_list (opaque_V2SF_type_node,
8363 opaque_V2SF_type_node,
8364 opaque_V2SF_type_node, NULL_TREE);
8366 tree v2si_ftype_int_int
8367 = build_function_type_list (opaque_V2SI_type_node,
8368 integer_type_node, integer_type_node,
8371 tree v2si_ftype_v2si
8372 = build_function_type_list (opaque_V2SI_type_node,
8373 opaque_V2SI_type_node, NULL_TREE);
8375 tree v2sf_ftype_v2sf
8376 = build_function_type_list (opaque_V2SF_type_node,
8377 opaque_V2SF_type_node, NULL_TREE);
8379 tree v2sf_ftype_v2si
8380 = build_function_type_list (opaque_V2SF_type_node,
8381 opaque_V2SI_type_node, NULL_TREE);
8383 tree v2si_ftype_v2sf
8384 = build_function_type_list (opaque_V2SI_type_node,
8385 opaque_V2SF_type_node, NULL_TREE);
8387 tree v2si_ftype_v2si_char
8388 = build_function_type_list (opaque_V2SI_type_node,
8389 opaque_V2SI_type_node,
8390 char_type_node, NULL_TREE);
8392 tree v2si_ftype_int_char
8393 = build_function_type_list (opaque_V2SI_type_node,
8394 integer_type_node, char_type_node, NULL_TREE);
8396 tree v2si_ftype_char
8397 = build_function_type_list (opaque_V2SI_type_node,
8398 char_type_node, NULL_TREE);
8400 tree int_ftype_int_int
8401 = build_function_type_list (integer_type_node,
8402 integer_type_node, integer_type_node,
8405 tree v4si_ftype_v4si_v4si
8406 = build_function_type_list (V4SI_type_node,
8407 V4SI_type_node, V4SI_type_node, NULL_TREE);
8408 tree v4sf_ftype_v4si_int
8409 = build_function_type_list (V4SF_type_node,
8410 V4SI_type_node, integer_type_node, NULL_TREE);
8411 tree v4si_ftype_v4sf_int
8412 = build_function_type_list (V4SI_type_node,
8413 V4SF_type_node, integer_type_node, NULL_TREE);
8414 tree v4si_ftype_v4si_int
8415 = build_function_type_list (V4SI_type_node,
8416 V4SI_type_node, integer_type_node, NULL_TREE);
8417 tree v8hi_ftype_v8hi_int
8418 = build_function_type_list (V8HI_type_node,
8419 V8HI_type_node, integer_type_node, NULL_TREE);
8420 tree v16qi_ftype_v16qi_int
8421 = build_function_type_list (V16QI_type_node,
8422 V16QI_type_node, integer_type_node, NULL_TREE);
8423 tree v16qi_ftype_v16qi_v16qi_int
8424 = build_function_type_list (V16QI_type_node,
8425 V16QI_type_node, V16QI_type_node,
8426 integer_type_node, NULL_TREE);
8427 tree v8hi_ftype_v8hi_v8hi_int
8428 = build_function_type_list (V8HI_type_node,
8429 V8HI_type_node, V8HI_type_node,
8430 integer_type_node, NULL_TREE);
8431 tree v4si_ftype_v4si_v4si_int
8432 = build_function_type_list (V4SI_type_node,
8433 V4SI_type_node, V4SI_type_node,
8434 integer_type_node, NULL_TREE);
8435 tree v4sf_ftype_v4sf_v4sf_int
8436 = build_function_type_list (V4SF_type_node,
8437 V4SF_type_node, V4SF_type_node,
8438 integer_type_node, NULL_TREE);
8439 tree v4sf_ftype_v4sf_v4sf
8440 = build_function_type_list (V4SF_type_node,
8441 V4SF_type_node, V4SF_type_node, NULL_TREE);
8442 tree v4sf_ftype_v4sf_v4sf_v4si
8443 = build_function_type_list (V4SF_type_node,
8444 V4SF_type_node, V4SF_type_node,
8445 V4SI_type_node, NULL_TREE);
8446 tree v4sf_ftype_v4sf_v4sf_v4sf
8447 = build_function_type_list (V4SF_type_node,
8448 V4SF_type_node, V4SF_type_node,
8449 V4SF_type_node, NULL_TREE);
8450 tree v4si_ftype_v4si_v4si_v4si
8451 = build_function_type_list (V4SI_type_node,
8452 V4SI_type_node, V4SI_type_node,
8453 V4SI_type_node, NULL_TREE);
8454 tree v8hi_ftype_v8hi_v8hi
8455 = build_function_type_list (V8HI_type_node,
8456 V8HI_type_node, V8HI_type_node, NULL_TREE);
8457 tree v8hi_ftype_v8hi_v8hi_v8hi
8458 = build_function_type_list (V8HI_type_node,
8459 V8HI_type_node, V8HI_type_node,
8460 V8HI_type_node, NULL_TREE);
8461 tree v4si_ftype_v8hi_v8hi_v4si
8462 = build_function_type_list (V4SI_type_node,
8463 V8HI_type_node, V8HI_type_node,
8464 V4SI_type_node, NULL_TREE);
8465 tree v4si_ftype_v16qi_v16qi_v4si
8466 = build_function_type_list (V4SI_type_node,
8467 V16QI_type_node, V16QI_type_node,
8468 V4SI_type_node, NULL_TREE);
8469 tree v16qi_ftype_v16qi_v16qi
8470 = build_function_type_list (V16QI_type_node,
8471 V16QI_type_node, V16QI_type_node, NULL_TREE);
8472 tree v4si_ftype_v4sf_v4sf
8473 = build_function_type_list (V4SI_type_node,
8474 V4SF_type_node, V4SF_type_node, NULL_TREE);
8475 tree v8hi_ftype_v16qi_v16qi
8476 = build_function_type_list (V8HI_type_node,
8477 V16QI_type_node, V16QI_type_node, NULL_TREE);
8478 tree v4si_ftype_v8hi_v8hi
8479 = build_function_type_list (V4SI_type_node,
8480 V8HI_type_node, V8HI_type_node, NULL_TREE);
8481 tree v8hi_ftype_v4si_v4si
8482 = build_function_type_list (V8HI_type_node,
8483 V4SI_type_node, V4SI_type_node, NULL_TREE);
8484 tree v16qi_ftype_v8hi_v8hi
8485 = build_function_type_list (V16QI_type_node,
8486 V8HI_type_node, V8HI_type_node, NULL_TREE);
8487 tree v4si_ftype_v16qi_v4si
8488 = build_function_type_list (V4SI_type_node,
8489 V16QI_type_node, V4SI_type_node, NULL_TREE);
8490 tree v4si_ftype_v16qi_v16qi
8491 = build_function_type_list (V4SI_type_node,
8492 V16QI_type_node, V16QI_type_node, NULL_TREE);
8493 tree v4si_ftype_v8hi_v4si
8494 = build_function_type_list (V4SI_type_node,
8495 V8HI_type_node, V4SI_type_node, NULL_TREE);
8496 tree v4si_ftype_v8hi
8497 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8498 tree int_ftype_v4si_v4si
8499 = build_function_type_list (integer_type_node,
8500 V4SI_type_node, V4SI_type_node, NULL_TREE);
8501 tree int_ftype_v4sf_v4sf
8502 = build_function_type_list (integer_type_node,
8503 V4SF_type_node, V4SF_type_node, NULL_TREE);
8504 tree int_ftype_v16qi_v16qi
8505 = build_function_type_list (integer_type_node,
8506 V16QI_type_node, V16QI_type_node, NULL_TREE);
8507 tree int_ftype_v8hi_v8hi
8508 = build_function_type_list (integer_type_node,
8509 V8HI_type_node, V8HI_type_node, NULL_TREE);
8511 /* Add the simple ternary operators. */
8512 d = (struct builtin_description *) bdesc_3arg;
8513 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8516 enum machine_mode mode0, mode1, mode2, mode3;
8519 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8522 mode0 = insn_data[d->icode].operand[0].mode;
8523 mode1 = insn_data[d->icode].operand[1].mode;
8524 mode2 = insn_data[d->icode].operand[2].mode;
8525 mode3 = insn_data[d->icode].operand[3].mode;
8527 /* When all four are of the same mode. */
8528 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8533 type = v4si_ftype_v4si_v4si_v4si;
8536 type = v4sf_ftype_v4sf_v4sf_v4sf;
8539 type = v8hi_ftype_v8hi_v8hi_v8hi;
8542 type = v16qi_ftype_v16qi_v16qi_v16qi;
8548 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8553 type = v4si_ftype_v4si_v4si_v16qi;
8556 type = v4sf_ftype_v4sf_v4sf_v16qi;
8559 type = v8hi_ftype_v8hi_v8hi_v16qi;
8562 type = v16qi_ftype_v16qi_v16qi_v16qi;
8568 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8569 && mode3 == V4SImode)
8570 type = v4si_ftype_v16qi_v16qi_v4si;
8571 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8572 && mode3 == V4SImode)
8573 type = v4si_ftype_v8hi_v8hi_v4si;
8574 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8575 && mode3 == V4SImode)
8576 type = v4sf_ftype_v4sf_v4sf_v4si;
8578 /* vchar, vchar, vchar, 4 bit literal. */
8579 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8581 type = v16qi_ftype_v16qi_v16qi_int;
8583 /* vshort, vshort, vshort, 4 bit literal. */
8584 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8586 type = v8hi_ftype_v8hi_v8hi_int;
8588 /* vint, vint, vint, 4 bit literal. */
8589 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8591 type = v4si_ftype_v4si_v4si_int;
8593 /* vfloat, vfloat, vfloat, 4 bit literal. */
8594 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8596 type = v4sf_ftype_v4sf_v4sf_int;
8601 def_builtin (d->mask, d->name, type, d->code);
8604 /* Add the simple binary operators. */
8605 d = (struct builtin_description *) bdesc_2arg;
8606 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8608 enum machine_mode mode0, mode1, mode2;
8611 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8614 mode0 = insn_data[d->icode].operand[0].mode;
8615 mode1 = insn_data[d->icode].operand[1].mode;
8616 mode2 = insn_data[d->icode].operand[2].mode;
8618 /* When all three operands are of the same mode. */
8619 if (mode0 == mode1 && mode1 == mode2)
8624 type = v4sf_ftype_v4sf_v4sf;
8627 type = v4si_ftype_v4si_v4si;
8630 type = v16qi_ftype_v16qi_v16qi;
8633 type = v8hi_ftype_v8hi_v8hi;
8636 type = v2si_ftype_v2si_v2si;
8639 type = v2sf_ftype_v2sf_v2sf;
8642 type = int_ftype_int_int;
8649 /* A few other combos we really don't want to do manually. */
8651 /* vint, vfloat, vfloat. */
8652 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8653 type = v4si_ftype_v4sf_v4sf;
8655 /* vshort, vchar, vchar. */
8656 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8657 type = v8hi_ftype_v16qi_v16qi;
8659 /* vint, vshort, vshort. */
8660 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8661 type = v4si_ftype_v8hi_v8hi;
8663 /* vshort, vint, vint. */
8664 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8665 type = v8hi_ftype_v4si_v4si;
8667 /* vchar, vshort, vshort. */
8668 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8669 type = v16qi_ftype_v8hi_v8hi;
8671 /* vint, vchar, vint. */
8672 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8673 type = v4si_ftype_v16qi_v4si;
8675 /* vint, vchar, vchar. */
8676 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8677 type = v4si_ftype_v16qi_v16qi;
8679 /* vint, vshort, vint. */
8680 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8681 type = v4si_ftype_v8hi_v4si;
8683 /* vint, vint, 5 bit literal. */
8684 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8685 type = v4si_ftype_v4si_int;
8687 /* vshort, vshort, 5 bit literal. */
8688 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8689 type = v8hi_ftype_v8hi_int;
8691 /* vchar, vchar, 5 bit literal. */
8692 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8693 type = v16qi_ftype_v16qi_int;
8695 /* vfloat, vint, 5 bit literal. */
8696 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8697 type = v4sf_ftype_v4si_int;
8699 /* vint, vfloat, 5 bit literal. */
8700 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8701 type = v4si_ftype_v4sf_int;
8703 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8704 type = v2si_ftype_int_int;
8706 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8707 type = v2si_ftype_v2si_char;
8709 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8710 type = v2si_ftype_int_char;
8713 else if (mode0 == SImode)
8718 type = int_ftype_v4si_v4si;
8721 type = int_ftype_v4sf_v4sf;
8724 type = int_ftype_v16qi_v16qi;
8727 type = int_ftype_v8hi_v8hi;
8737 def_builtin (d->mask, d->name, type, d->code);
8740 /* Add the simple unary operators. */
8741 d = (struct builtin_description *) bdesc_1arg;
8742 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8744 enum machine_mode mode0, mode1;
8747 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8750 mode0 = insn_data[d->icode].operand[0].mode;
8751 mode1 = insn_data[d->icode].operand[1].mode;
8753 if (mode0 == V4SImode && mode1 == QImode)
8754 type = v4si_ftype_int;
8755 else if (mode0 == V8HImode && mode1 == QImode)
8756 type = v8hi_ftype_int;
8757 else if (mode0 == V16QImode && mode1 == QImode)
8758 type = v16qi_ftype_int;
8759 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8760 type = v4sf_ftype_v4sf;
8761 else if (mode0 == V8HImode && mode1 == V16QImode)
8762 type = v8hi_ftype_v16qi;
8763 else if (mode0 == V4SImode && mode1 == V8HImode)
8764 type = v4si_ftype_v8hi;
8765 else if (mode0 == V2SImode && mode1 == V2SImode)
8766 type = v2si_ftype_v2si;
8767 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8768 type = v2sf_ftype_v2sf;
8769 else if (mode0 == V2SFmode && mode1 == V2SImode)
8770 type = v2sf_ftype_v2si;
8771 else if (mode0 == V2SImode && mode1 == V2SFmode)
8772 type = v2si_ftype_v2sf;
8773 else if (mode0 == V2SImode && mode1 == QImode)
8774 type = v2si_ftype_char;
8778 def_builtin (d->mask, d->name, type, d->code);
8783 rs6000_init_libfuncs (void)
8785 if (!TARGET_HARD_FLOAT)
8788 if (DEFAULT_ABI != ABI_V4)
8790 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8792 /* AIX library routines for float->int conversion. */
8793 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8794 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8795 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8796 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8799 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8800 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8801 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8802 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8803 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8807 /* 32-bit SVR4 quad floating point routines. */
8809 set_optab_libfunc (add_optab, TFmode, "_q_add");
8810 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8811 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8812 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8813 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8814 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8815 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8817 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8818 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8819 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8820 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8821 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8822 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8824 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8825 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8826 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8827 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8828 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8829 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8830 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8835 /* Expand a block clear operation, and return 1 if successful. Return 0
8836 if we should let the compiler generate normal code.
8838 operands[0] is the destination
8839 operands[1] is the length
8840 operands[2] is the alignment */
8843 expand_block_clear (rtx operands[])
8845 rtx orig_dest = operands[0];
8846 rtx bytes_rtx = operands[1];
8847 rtx align_rtx = operands[2];
8848 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8849 HOST_WIDE_INT align;
8850 HOST_WIDE_INT bytes;
8855 /* If this is not a fixed size move, just call memcpy */
8859 /* If this is not a fixed size alignment, abort */
8860 if (GET_CODE (align_rtx) != CONST_INT)
8862 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8864 /* Anything to clear? */
8865 bytes = INTVAL (bytes_rtx);
8869 /* Use the builtin memset after a point, to avoid huge code bloat.
8870 When optimize_size, avoid any significant code bloat; calling
8871 memset is about 4 instructions, so allow for one instruction to
8872 load zero and three to do clearing. */
8873 if (TARGET_ALTIVEC && align >= 128)
8875 else if (TARGET_POWERPC64 && align >= 32)
8880 if (optimize_size && bytes > 3 * clear_step)
8882 if (! optimize_size && bytes > 8 * clear_step)
8885 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8887 enum machine_mode mode = BLKmode;
8890 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8895 else if (bytes >= 8 && TARGET_POWERPC64
8896 /* 64-bit loads and stores require word-aligned
8898 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8903 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8904 { /* move 4 bytes */
8908 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8909 { /* move 2 bytes */
8913 else /* move 1 byte at a time */
8919 dest = adjust_address (orig_dest, mode, offset);
8921 emit_move_insn (dest, CONST0_RTX (mode));
8928 /* Expand a block move operation, and return 1 if successful. Return 0
8929 if we should let the compiler generate normal code.
8931 operands[0] is the destination
8932 operands[1] is the source
8933 operands[2] is the length
8934 operands[3] is the alignment */
8936 #define MAX_MOVE_REG 4
8939 expand_block_move (rtx operands[])
8941 rtx orig_dest = operands[0];
8942 rtx orig_src = operands[1];
8943 rtx bytes_rtx = operands[2];
8944 rtx align_rtx = operands[3];
8945 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8950 rtx stores[MAX_MOVE_REG];
8953 /* If this is not a fixed size move, just call memcpy */
8957 /* If this is not a fixed size alignment, abort */
8958 if (GET_CODE (align_rtx) != CONST_INT)
8960 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8962 /* Anything to move? */
8963 bytes = INTVAL (bytes_rtx);
8967 /* store_one_arg depends on expand_block_move to handle at least the size of
8968 reg_parm_stack_space. */
8969 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8972 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8975 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8976 rtx (*mov) (rtx, rtx);
8978 enum machine_mode mode = BLKmode;
8981 /* Altivec first, since it will be faster than a string move
8982 when it applies, and usually not significantly larger. */
8983 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8987 gen_func.mov = gen_movv4si;
8989 else if (TARGET_STRING
8990 && bytes > 24 /* move up to 32 bytes at a time */
8998 && ! fixed_regs[12])
9000 move_bytes = (bytes > 32) ? 32 : bytes;
9001 gen_func.movmemsi = gen_movmemsi_8reg;
9003 else if (TARGET_STRING
9004 && bytes > 16 /* move up to 24 bytes at a time */
9010 && ! fixed_regs[10])
9012 move_bytes = (bytes > 24) ? 24 : bytes;
9013 gen_func.movmemsi = gen_movmemsi_6reg;
9015 else if (TARGET_STRING
9016 && bytes > 8 /* move up to 16 bytes at a time */
9022 move_bytes = (bytes > 16) ? 16 : bytes;
9023 gen_func.movmemsi = gen_movmemsi_4reg;
9025 else if (bytes >= 8 && TARGET_POWERPC64
9026 /* 64-bit loads and stores require word-aligned
9028 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9032 gen_func.mov = gen_movdi;
9034 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9035 { /* move up to 8 bytes at a time */
9036 move_bytes = (bytes > 8) ? 8 : bytes;
9037 gen_func.movmemsi = gen_movmemsi_2reg;
9039 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9040 { /* move 4 bytes */
9043 gen_func.mov = gen_movsi;
9045 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
9046 { /* move 2 bytes */
9049 gen_func.mov = gen_movhi;
9051 else if (TARGET_STRING && bytes > 1)
9052 { /* move up to 4 bytes at a time */
9053 move_bytes = (bytes > 4) ? 4 : bytes;
9054 gen_func.movmemsi = gen_movmemsi_1reg;
9056 else /* move 1 byte at a time */
9060 gen_func.mov = gen_movqi;
9063 src = adjust_address (orig_src, mode, offset);
9064 dest = adjust_address (orig_dest, mode, offset);
9066 if (mode != BLKmode)
9068 rtx tmp_reg = gen_reg_rtx (mode);
9070 emit_insn ((*gen_func.mov) (tmp_reg, src));
9071 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9074 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9077 for (i = 0; i < num_reg; i++)
9078 emit_insn (stores[i]);
9082 if (mode == BLKmode)
9084 /* Move the address into scratch registers. The movmemsi
9085 patterns require zero offset. */
9086 if (!REG_P (XEXP (src, 0)))
9088 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9089 src = replace_equiv_address (src, src_reg);
9091 set_mem_size (src, GEN_INT (move_bytes));
9093 if (!REG_P (XEXP (dest, 0)))
9095 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9096 dest = replace_equiv_address (dest, dest_reg);
9098 set_mem_size (dest, GEN_INT (move_bytes));
9100 emit_insn ((*gen_func.movmemsi) (dest, src,
9101 GEN_INT (move_bytes & 31),
9110 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9111 known to be a PARALLEL. */
9113 save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9118 int count = XVECLEN (op, 0);
9124 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9125 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9128 for (i=1; i <= 18; i++)
9130 elt = XVECEXP (op, 0, index++);
9131 if (GET_CODE (elt) != SET
9132 || GET_CODE (SET_DEST (elt)) != MEM
9133 || ! memory_operand (SET_DEST (elt), DFmode)
9134 || GET_CODE (SET_SRC (elt)) != REG
9135 || GET_MODE (SET_SRC (elt)) != DFmode)
9139 for (i=1; i <= 12; i++)
9141 elt = XVECEXP (op, 0, index++);
9142 if (GET_CODE (elt) != SET
9143 || GET_CODE (SET_DEST (elt)) != MEM
9144 || GET_CODE (SET_SRC (elt)) != REG
9145 || GET_MODE (SET_SRC (elt)) != V4SImode)
9149 for (i=1; i <= 19; i++)
9151 elt = XVECEXP (op, 0, index++);
9152 if (GET_CODE (elt) != SET
9153 || GET_CODE (SET_DEST (elt)) != MEM
9154 || ! memory_operand (SET_DEST (elt), Pmode)
9155 || GET_CODE (SET_SRC (elt)) != REG
9156 || GET_MODE (SET_SRC (elt)) != Pmode)
9160 elt = XVECEXP (op, 0, index++);
9161 if (GET_CODE (elt) != SET
9162 || GET_CODE (SET_DEST (elt)) != MEM
9163 || ! memory_operand (SET_DEST (elt), Pmode)
9164 || GET_CODE (SET_SRC (elt)) != REG
9165 || REGNO (SET_SRC (elt)) != CR2_REGNO
9166 || GET_MODE (SET_SRC (elt)) != Pmode)
9169 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
9170 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9171 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9176 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9177 known to be a PARALLEL. */
9179 restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9184 int count = XVECLEN (op, 0);
9190 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
9191 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9192 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9193 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9196 elt = XVECEXP (op, 0, index++);
9197 if (GET_CODE (elt) != SET
9198 || GET_CODE (SET_SRC (elt)) != MEM
9199 || ! memory_operand (SET_SRC (elt), Pmode)
9200 || GET_CODE (SET_DEST (elt)) != REG
9201 || REGNO (SET_DEST (elt)) != CR2_REGNO
9202 || GET_MODE (SET_DEST (elt)) != Pmode)
9205 for (i=1; i <= 19; i++)
9207 elt = XVECEXP (op, 0, index++);
9208 if (GET_CODE (elt) != SET
9209 || GET_CODE (SET_SRC (elt)) != MEM
9210 || ! memory_operand (SET_SRC (elt), Pmode)
9211 || GET_CODE (SET_DEST (elt)) != REG
9212 || GET_MODE (SET_DEST (elt)) != Pmode)
9216 for (i=1; i <= 12; i++)
9218 elt = XVECEXP (op, 0, index++);
9219 if (GET_CODE (elt) != SET
9220 || GET_CODE (SET_SRC (elt)) != MEM
9221 || GET_CODE (SET_DEST (elt)) != REG
9222 || GET_MODE (SET_DEST (elt)) != V4SImode)
9226 for (i=1; i <= 18; i++)
9228 elt = XVECEXP (op, 0, index++);
9229 if (GET_CODE (elt) != SET
9230 || GET_CODE (SET_SRC (elt)) != MEM
9231 || ! memory_operand (SET_SRC (elt), DFmode)
9232 || GET_CODE (SET_DEST (elt)) != REG
9233 || GET_MODE (SET_DEST (elt)) != DFmode)
9237 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9238 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9239 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9240 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9241 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9247 /* Return 1 if OP is a load multiple operation. It is known to be a
9248 PARALLEL and the first section will be tested. */
9251 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9253 int count = XVECLEN (op, 0);
9254 unsigned int dest_regno;
9258 /* Perform a quick check so we don't blow up below. */
9260 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9261 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9262 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9265 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9266 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9268 for (i = 1; i < count; i++)
9270 rtx elt = XVECEXP (op, 0, i);
9272 if (GET_CODE (elt) != SET
9273 || GET_CODE (SET_DEST (elt)) != REG
9274 || GET_MODE (SET_DEST (elt)) != SImode
9275 || REGNO (SET_DEST (elt)) != dest_regno + i
9276 || GET_CODE (SET_SRC (elt)) != MEM
9277 || GET_MODE (SET_SRC (elt)) != SImode
9278 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
9279 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
9280 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
9281 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
9288 /* Similar, but tests for store multiple. Here, the second vector element
9289 is a CLOBBER. It will be tested later. */
9292 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9294 int count = XVECLEN (op, 0) - 1;
9295 unsigned int src_regno;
9299 /* Perform a quick check so we don't blow up below. */
9301 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9302 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9303 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9306 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9307 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9309 for (i = 1; i < count; i++)
9311 rtx elt = XVECEXP (op, 0, i + 1);
9313 if (GET_CODE (elt) != SET
9314 || GET_CODE (SET_SRC (elt)) != REG
9315 || GET_MODE (SET_SRC (elt)) != SImode
9316 || REGNO (SET_SRC (elt)) != src_regno + i
9317 || GET_CODE (SET_DEST (elt)) != MEM
9318 || GET_MODE (SET_DEST (elt)) != SImode
9319 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
9320 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
9321 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
9322 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
9329 /* Return a string to perform a load_multiple operation.
9330 operands[0] is the vector.
9331 operands[1] is the source address.
9332 operands[2] is the first destination register. */
9335 rs6000_output_load_multiple (rtx operands[3])
9337 /* We have to handle the case where the pseudo used to contain the address
9338 is assigned to one of the output registers. */
9340 int words = XVECLEN (operands[0], 0);
9343 if (XVECLEN (operands[0], 0) == 1)
9344 return "{l|lwz} %2,0(%1)";
9346 for (i = 0; i < words; i++)
9347 if (refers_to_regno_p (REGNO (operands[2]) + i,
9348 REGNO (operands[2]) + i + 1, operands[1], 0))
9352 xop[0] = GEN_INT (4 * (words-1));
9353 xop[1] = operands[1];
9354 xop[2] = operands[2];
9355 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9360 xop[0] = GEN_INT (4 * (words-1));
9361 xop[1] = operands[1];
9362 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9363 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9368 for (j = 0; j < words; j++)
9371 xop[0] = GEN_INT (j * 4);
9372 xop[1] = operands[1];
9373 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9374 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9376 xop[0] = GEN_INT (i * 4);
9377 xop[1] = operands[1];
9378 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9383 return "{lsi|lswi} %2,%1,%N0";
9386 /* Return 1 for a parallel vrsave operation. */
9389 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9391 int count = XVECLEN (op, 0);
9392 unsigned int dest_regno, src_regno;
9396 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9397 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9398 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
9401 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9402 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9404 if (dest_regno != VRSAVE_REGNO
9405 && src_regno != VRSAVE_REGNO)
9408 for (i = 1; i < count; i++)
9410 rtx elt = XVECEXP (op, 0, i);
9412 if (GET_CODE (elt) != CLOBBER
9413 && GET_CODE (elt) != SET)
9420 /* Return 1 for an PARALLEL suitable for mfcr. */
9423 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9425 int count = XVECLEN (op, 0);
9428 /* Perform a quick check so we don't blow up below. */
9430 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9431 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9432 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9435 for (i = 0; i < count; i++)
9437 rtx exp = XVECEXP (op, 0, i);
9442 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
9444 if (GET_CODE (src_reg) != REG
9445 || GET_MODE (src_reg) != CCmode
9446 || ! CR_REGNO_P (REGNO (src_reg)))
9449 if (GET_CODE (exp) != SET
9450 || GET_CODE (SET_DEST (exp)) != REG
9451 || GET_MODE (SET_DEST (exp)) != SImode
9452 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
9454 unspec = SET_SRC (exp);
9455 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
9457 if (GET_CODE (unspec) != UNSPEC
9458 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
9459 || XVECLEN (unspec, 0) != 2
9460 || XVECEXP (unspec, 0, 0) != src_reg
9461 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9462 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9468 /* Return 1 for an PARALLEL suitable for mtcrf. */
9471 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9473 int count = XVECLEN (op, 0);
9477 /* Perform a quick check so we don't blow up below. */
9479 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9480 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9481 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9483 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
9485 if (GET_CODE (src_reg) != REG
9486 || GET_MODE (src_reg) != SImode
9487 || ! INT_REGNO_P (REGNO (src_reg)))
9490 for (i = 0; i < count; i++)
9492 rtx exp = XVECEXP (op, 0, i);
9496 if (GET_CODE (exp) != SET
9497 || GET_CODE (SET_DEST (exp)) != REG
9498 || GET_MODE (SET_DEST (exp)) != CCmode
9499 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
9501 unspec = SET_SRC (exp);
9502 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
9504 if (GET_CODE (unspec) != UNSPEC
9505 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
9506 || XVECLEN (unspec, 0) != 2
9507 || XVECEXP (unspec, 0, 0) != src_reg
9508 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9509 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9515 /* Return 1 for an PARALLEL suitable for lmw. */
9518 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9520 int count = XVECLEN (op, 0);
9521 unsigned int dest_regno;
9523 unsigned int base_regno;
9524 HOST_WIDE_INT offset;
9527 /* Perform a quick check so we don't blow up below. */
9529 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9530 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9531 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9534 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9535 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9538 || count != 32 - (int) dest_regno)
9541 if (legitimate_indirect_address_p (src_addr, 0))
9544 base_regno = REGNO (src_addr);
9545 if (base_regno == 0)
9548 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
9550 offset = INTVAL (XEXP (src_addr, 1));
9551 base_regno = REGNO (XEXP (src_addr, 0));
9556 for (i = 0; i < count; i++)
9558 rtx elt = XVECEXP (op, 0, i);
9561 HOST_WIDE_INT newoffset;
9563 if (GET_CODE (elt) != SET
9564 || GET_CODE (SET_DEST (elt)) != REG
9565 || GET_MODE (SET_DEST (elt)) != SImode
9566 || REGNO (SET_DEST (elt)) != dest_regno + i
9567 || GET_CODE (SET_SRC (elt)) != MEM
9568 || GET_MODE (SET_SRC (elt)) != SImode)
9570 newaddr = XEXP (SET_SRC (elt), 0);
9571 if (legitimate_indirect_address_p (newaddr, 0))
9576 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9578 addr_reg = XEXP (newaddr, 0);
9579 newoffset = INTVAL (XEXP (newaddr, 1));
9583 if (REGNO (addr_reg) != base_regno
9584 || newoffset != offset + 4 * i)
9591 /* Return 1 for an PARALLEL suitable for stmw. */
9594 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9596 int count = XVECLEN (op, 0);
9597 unsigned int src_regno;
9599 unsigned int base_regno;
9600 HOST_WIDE_INT offset;
9603 /* Perform a quick check so we don't blow up below. */
9605 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9606 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9607 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9610 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9611 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9614 || count != 32 - (int) src_regno)
9617 if (legitimate_indirect_address_p (dest_addr, 0))
9620 base_regno = REGNO (dest_addr);
9621 if (base_regno == 0)
9624 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
9626 offset = INTVAL (XEXP (dest_addr, 1));
9627 base_regno = REGNO (XEXP (dest_addr, 0));
9632 for (i = 0; i < count; i++)
9634 rtx elt = XVECEXP (op, 0, i);
9637 HOST_WIDE_INT newoffset;
9639 if (GET_CODE (elt) != SET
9640 || GET_CODE (SET_SRC (elt)) != REG
9641 || GET_MODE (SET_SRC (elt)) != SImode
9642 || REGNO (SET_SRC (elt)) != src_regno + i
9643 || GET_CODE (SET_DEST (elt)) != MEM
9644 || GET_MODE (SET_DEST (elt)) != SImode)
9646 newaddr = XEXP (SET_DEST (elt), 0);
9647 if (legitimate_indirect_address_p (newaddr, 0))
9652 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9654 addr_reg = XEXP (newaddr, 0);
9655 newoffset = INTVAL (XEXP (newaddr, 1));
9659 if (REGNO (addr_reg) != base_regno
9660 || newoffset != offset + 4 * i)
9667 /* A validation routine: say whether CODE, a condition code, and MODE
9668 match. The other alternatives either don't make sense or should
9669 never be generated. */
9672 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9674 if ((GET_RTX_CLASS (code) != RTX_COMPARE
9675 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
9676 || GET_MODE_CLASS (mode) != MODE_CC)
9679 /* These don't make sense. */
9680 if ((code == GT || code == LT || code == GE || code == LE)
9681 && mode == CCUNSmode)
9684 if ((code == GTU || code == LTU || code == GEU || code == LEU)
9685 && mode != CCUNSmode)
9688 if (mode != CCFPmode
9689 && (code == ORDERED || code == UNORDERED
9690 || code == UNEQ || code == LTGT
9691 || code == UNGT || code == UNLT
9692 || code == UNGE || code == UNLE))
9695 /* These should never be generated except for
9696 flag_finite_math_only. */
9697 if (mode == CCFPmode
9698 && ! flag_finite_math_only
9699 && (code == LE || code == GE
9700 || code == UNEQ || code == LTGT
9701 || code == UNGT || code == UNLT))
9704 /* These are invalid; the information is not there. */
9705 if (mode == CCEQmode
9706 && code != EQ && code != NE)
9710 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9711 We only check the opcode against the mode of the CC value here. */
9714 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9716 enum rtx_code code = GET_CODE (op);
9717 enum machine_mode cc_mode;
9719 if (!COMPARISON_P (op))
9722 cc_mode = GET_MODE (XEXP (op, 0));
9723 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
9726 validate_condition_mode (code, cc_mode);
9731 /* Return 1 if OP is a comparison operation that is valid for a branch
9732 insn and which is true if the corresponding bit in the CC register
9736 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
9740 if (! branch_comparison_operator (op, mode))
9743 code = GET_CODE (op);
9744 return (code == EQ || code == LT || code == GT
9745 || code == LTU || code == GTU
9746 || code == UNORDERED);
9749 /* Return 1 if OP is a comparison operation that is valid for an scc
9750 insn: it must be a positive comparison. */
9753 scc_comparison_operator (rtx op, enum machine_mode mode)
9755 return branch_positive_comparison_operator (op, mode);
9759 trap_comparison_operator (rtx op, enum machine_mode mode)
9761 if (mode != VOIDmode && mode != GET_MODE (op))
9763 return COMPARISON_P (op);
9767 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9769 enum rtx_code code = GET_CODE (op);
9770 return (code == AND || code == IOR || code == XOR);
9774 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9776 enum rtx_code code = GET_CODE (op);
9777 return (code == IOR || code == XOR);
9781 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9783 enum rtx_code code = GET_CODE (op);
9784 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
9787 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9788 mask required to convert the result of a rotate insn into a shift
9789 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9792 includes_lshift_p (rtx shiftop, rtx andop)
9794 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9796 shift_mask <<= INTVAL (shiftop);
9798 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9801 /* Similar, but for right shift. */
9804 includes_rshift_p (rtx shiftop, rtx andop)
9806 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9808 shift_mask >>= INTVAL (shiftop);
9810 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9813 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9814 to perform a left shift. It must have exactly SHIFTOP least
9815 significant 0's, then one or more 1's, then zero or more 0's. */
9818 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9820 if (GET_CODE (andop) == CONST_INT)
9822 HOST_WIDE_INT c, lsb, shift_mask;
9825 if (c == 0 || c == ~0)
9829 shift_mask <<= INTVAL (shiftop);
9831 /* Find the least significant one bit. */
9834 /* It must coincide with the LSB of the shift mask. */
9835 if (-lsb != shift_mask)
9838 /* Invert to look for the next transition (if any). */
9841 /* Remove the low group of ones (originally low group of zeros). */
9844 /* Again find the lsb, and check we have all 1's above. */
9848 else if (GET_CODE (andop) == CONST_DOUBLE
9849 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9851 HOST_WIDE_INT low, high, lsb;
9852 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9854 low = CONST_DOUBLE_LOW (andop);
9855 if (HOST_BITS_PER_WIDE_INT < 64)
9856 high = CONST_DOUBLE_HIGH (andop);
9858 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9859 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9862 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9864 shift_mask_high = ~0;
9865 if (INTVAL (shiftop) > 32)
9866 shift_mask_high <<= INTVAL (shiftop) - 32;
9870 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9877 return high == -lsb;
9880 shift_mask_low = ~0;
9881 shift_mask_low <<= INTVAL (shiftop);
9885 if (-lsb != shift_mask_low)
9888 if (HOST_BITS_PER_WIDE_INT < 64)
9893 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9896 return high == -lsb;
9900 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9906 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9907 to perform a left shift. It must have SHIFTOP or more least
9908 significant 0's, with the remainder of the word 1's. */
9911 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9913 if (GET_CODE (andop) == CONST_INT)
9915 HOST_WIDE_INT c, lsb, shift_mask;
9918 shift_mask <<= INTVAL (shiftop);
9921 /* Find the least significant one bit. */
9924 /* It must be covered by the shift mask.
9925 This test also rejects c == 0. */
9926 if ((lsb & shift_mask) == 0)
9929 /* Check we have all 1's above the transition, and reject all 1's. */
9930 return c == -lsb && lsb != 1;
9932 else if (GET_CODE (andop) == CONST_DOUBLE
9933 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9935 HOST_WIDE_INT low, lsb, shift_mask_low;
9937 low = CONST_DOUBLE_LOW (andop);
9939 if (HOST_BITS_PER_WIDE_INT < 64)
9941 HOST_WIDE_INT high, shift_mask_high;
9943 high = CONST_DOUBLE_HIGH (andop);
9947 shift_mask_high = ~0;
9948 if (INTVAL (shiftop) > 32)
9949 shift_mask_high <<= INTVAL (shiftop) - 32;
9953 if ((lsb & shift_mask_high) == 0)
9956 return high == -lsb;
9962 shift_mask_low = ~0;
9963 shift_mask_low <<= INTVAL (shiftop);
9967 if ((lsb & shift_mask_low) == 0)
9970 return low == -lsb && lsb != 1;
9976 /* Return 1 if operands will generate a valid arguments to rlwimi
9977 instruction for insert with right shift in 64-bit mode. The mask may
9978 not start on the first bit or stop on the last bit because wrap-around
9979 effects of instruction do not correspond to semantics of RTL insn. */
9982 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9984 if (INTVAL (startop) < 64
9985 && INTVAL (startop) > 32
9986 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9987 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9988 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9989 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9990 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9996 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9997 for lfq and stfq insns iff the registers are hard registers. */
10000 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10002 /* We might have been passed a SUBREG. */
10003 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10006 /* We might have been passed non floating point registers. */
10007 if (!FP_REGNO_P (REGNO (reg1))
10008 || !FP_REGNO_P (REGNO (reg2)))
10011 return (REGNO (reg1) == REGNO (reg2) - 1);
10014 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10015 addr1 and addr2 must be in consecutive memory locations
10016 (addr2 == addr1 + 8). */
10019 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10025 /* The mems cannot be volatile. */
10026 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10029 addr1 = XEXP (mem1, 0);
10030 addr2 = XEXP (mem2, 0);
10032 /* Extract an offset (if used) from the first addr. */
10033 if (GET_CODE (addr1) == PLUS)
10035 /* If not a REG, return zero. */
10036 if (GET_CODE (XEXP (addr1, 0)) != REG)
10040 reg1 = REGNO (XEXP (addr1, 0));
10041 /* The offset must be constant! */
10042 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10044 offset1 = INTVAL (XEXP (addr1, 1));
10047 else if (GET_CODE (addr1) != REG)
10051 reg1 = REGNO (addr1);
10052 /* This was a simple (mem (reg)) expression. Offset is 0. */
10056 /* Make sure the second address is a (mem (plus (reg) (const_int)))
10057 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
10058 register as addr1. */
10059 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
10061 if (GET_CODE (addr2) != PLUS)
10064 if (GET_CODE (XEXP (addr2, 0)) != REG
10065 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10068 if (reg1 != REGNO (XEXP (addr2, 0)))
10071 /* The offset for the second addr must be 8 more than the first addr. */
10072 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
10075 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10080 /* Return the register class of a scratch register needed to copy IN into
10081 or out of a register in CLASS in MODE. If it can be done directly,
10082 NO_REGS is returned. */
10085 secondary_reload_class (enum reg_class class,
10086 enum machine_mode mode ATTRIBUTE_UNUSED,
10091 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10093 && MACHOPIC_INDIRECT
10097 /* We cannot copy a symbolic operand directly into anything
10098 other than BASE_REGS for TARGET_ELF. So indicate that a
10099 register from BASE_REGS is needed as an intermediate
10102 On Darwin, pic addresses require a load from memory, which
10103 needs a base register. */
10104 if (class != BASE_REGS
10105 && (GET_CODE (in) == SYMBOL_REF
10106 || GET_CODE (in) == HIGH
10107 || GET_CODE (in) == LABEL_REF
10108 || GET_CODE (in) == CONST))
10112 if (GET_CODE (in) == REG)
10114 regno = REGNO (in);
10115 if (regno >= FIRST_PSEUDO_REGISTER)
10117 regno = true_regnum (in);
10118 if (regno >= FIRST_PSEUDO_REGISTER)
10122 else if (GET_CODE (in) == SUBREG)
10124 regno = true_regnum (in);
10125 if (regno >= FIRST_PSEUDO_REGISTER)
10131 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10133 if (class == GENERAL_REGS || class == BASE_REGS
10134 || (regno >= 0 && INT_REGNO_P (regno)))
10137 /* Constants, memory, and FP registers can go into FP registers. */
10138 if ((regno == -1 || FP_REGNO_P (regno))
10139 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10142 /* Memory, and AltiVec registers can go into AltiVec registers. */
10143 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10144 && class == ALTIVEC_REGS)
10147 /* We can copy among the CR registers. */
10148 if ((class == CR_REGS || class == CR0_REGS)
10149 && regno >= 0 && CR_REGNO_P (regno))
10152 /* Otherwise, we need GENERAL_REGS. */
10153 return GENERAL_REGS;
10156 /* Given a comparison operation, return the bit number in CCR to test. We
10157 know this is a valid comparison.
10159 SCC_P is 1 if this is for an scc. That means that %D will have been
10160 used instead of %C, so the bits will be in different places.
10162 Return -1 if OP isn't a valid comparison for some reason. */
10165 ccr_bit (rtx op, int scc_p)
10167 enum rtx_code code = GET_CODE (op);
10168 enum machine_mode cc_mode;
10173 if (!COMPARISON_P (op))
10176 reg = XEXP (op, 0);
10178 if (GET_CODE (reg) != REG
10179 || ! CR_REGNO_P (REGNO (reg)))
10182 cc_mode = GET_MODE (reg);
10183 cc_regnum = REGNO (reg);
10184 base_bit = 4 * (cc_regnum - CR0_REGNO);
10186 validate_condition_mode (code, cc_mode);
10188 /* When generating a sCOND operation, only positive conditions are
10190 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
10191 && code != GTU && code != LTU)
10197 return scc_p ? base_bit + 3 : base_bit + 2;
10199 return base_bit + 2;
10200 case GT: case GTU: case UNLE:
10201 return base_bit + 1;
10202 case LT: case LTU: case UNGE:
10204 case ORDERED: case UNORDERED:
10205 return base_bit + 3;
10208 /* If scc, we will have done a cror to put the bit in the
10209 unordered position. So test that bit. For integer, this is ! LT
10210 unless this is an scc insn. */
10211 return scc_p ? base_bit + 3 : base_bit;
10214 return scc_p ? base_bit + 3 : base_bit + 1;
10221 /* Return the GOT register. */
10224 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10226 /* The second flow pass currently (June 1999) can't update
10227 regs_ever_live without disturbing other parts of the compiler, so
10228 update it here to make the prolog/epilogue code happy. */
10229 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10230 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10232 current_function_uses_pic_offset_table = 1;
10234 return pic_offset_table_rtx;
10237 /* Function to init struct machine_function.
10238 This will be called, via a pointer variable,
10239 from push_function_context. */
10241 static struct machine_function *
10242 rs6000_init_machine_status (void)
10244 return ggc_alloc_cleared (sizeof (machine_function));
10247 /* These macros test for integers and extract the low-order bits. */
10249 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10250 && GET_MODE (X) == VOIDmode)
10252 #define INT_LOWPART(X) \
10253 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10256 extract_MB (rtx op)
10259 unsigned long val = INT_LOWPART (op);
10261 /* If the high bit is zero, the value is the first 1 bit we find
10263 if ((val & 0x80000000) == 0)
10265 if ((val & 0xffffffff) == 0)
10269 while (((val <<= 1) & 0x80000000) == 0)
10274 /* If the high bit is set and the low bit is not, or the mask is all
10275 1's, the value is zero. */
10276 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10279 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10282 while (((val >>= 1) & 1) != 0)
10289 extract_ME (rtx op)
10292 unsigned long val = INT_LOWPART (op);
10294 /* If the low bit is zero, the value is the first 1 bit we find from
10296 if ((val & 1) == 0)
10298 if ((val & 0xffffffff) == 0)
10302 while (((val >>= 1) & 1) == 0)
10308 /* If the low bit is set and the high bit is not, or the mask is all
10309 1's, the value is 31. */
10310 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10313 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10316 while (((val <<= 1) & 0x80000000) != 0)
10322 /* Locate some local-dynamic symbol still in use by this function
10323 so that we can print its name in some tls_ld pattern. */
10325 static const char *
10326 rs6000_get_some_local_dynamic_name (void)
10330 if (cfun->machine->some_ld_name)
10331 return cfun->machine->some_ld_name;
10333 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10335 && for_each_rtx (&PATTERN (insn),
10336 rs6000_get_some_local_dynamic_name_1, 0))
10337 return cfun->machine->some_ld_name;
10342 /* Helper function for rs6000_get_some_local_dynamic_name. */
10345 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10349 if (GET_CODE (x) == SYMBOL_REF)
10351 const char *str = XSTR (x, 0);
10352 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10354 cfun->machine->some_ld_name = str;
10362 /* Write out a function code label. */
10365 rs6000_output_function_entry (FILE *file, const char *fname)
10367 if (fname[0] != '.')
10369 switch (DEFAULT_ABI)
10378 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10387 RS6000_OUTPUT_BASENAME (file, fname);
10389 assemble_name (file, fname);
10392 /* Print an operand. Recognize special options, documented below. */
10395 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10396 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10398 #define SMALL_DATA_RELOC "sda21"
10399 #define SMALL_DATA_REG 0
10403 print_operand (FILE *file, rtx x, int code)
10407 unsigned HOST_WIDE_INT uval;
10412 /* Write out an instruction after the call which may be replaced
10413 with glue code by the loader. This depends on the AIX version. */
10414 asm_fprintf (file, RS6000_CALL_GLUE);
10417 /* %a is output_address. */
10420 /* If X is a constant integer whose low-order 5 bits are zero,
10421 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10422 in the AIX assembler where "sri" with a zero shift count
10423 writes a trash instruction. */
10424 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10431 /* If constant, low-order 16 bits of constant, unsigned.
10432 Otherwise, write normally. */
10434 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10436 print_operand (file, x, 0);
10440 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10441 for 64-bit mask direction. */
10442 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
10445 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10449 /* X is a CR register. Print the number of the GT bit of the CR. */
10450 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10451 output_operand_lossage ("invalid %%E value");
10453 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10457 /* Like 'J' but get to the EQ bit. */
10458 if (GET_CODE (x) != REG)
10461 /* Bit 1 is EQ bit. */
10462 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10464 /* If we want bit 31, write a shift count of zero, not 32. */
10465 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10469 /* X is a CR register. Print the number of the EQ bit of the CR */
10470 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10471 output_operand_lossage ("invalid %%E value");
10473 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10477 /* X is a CR register. Print the shift count needed to move it
10478 to the high-order four bits. */
10479 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10480 output_operand_lossage ("invalid %%f value");
10482 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10486 /* Similar, but print the count for the rotate in the opposite
10488 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10489 output_operand_lossage ("invalid %%F value");
10491 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10495 /* X is a constant integer. If it is negative, print "m",
10496 otherwise print "z". This is to make an aze or ame insn. */
10497 if (GET_CODE (x) != CONST_INT)
10498 output_operand_lossage ("invalid %%G value");
10499 else if (INTVAL (x) >= 0)
10506 /* If constant, output low-order five bits. Otherwise, write
10509 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10511 print_operand (file, x, 0);
10515 /* If constant, output low-order six bits. Otherwise, write
10518 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10520 print_operand (file, x, 0);
10524 /* Print `i' if this is a constant, else nothing. */
10530 /* Write the bit number in CCR for jump. */
10531 i = ccr_bit (x, 0);
10533 output_operand_lossage ("invalid %%j code");
10535 fprintf (file, "%d", i);
10539 /* Similar, but add one for shift count in rlinm for scc and pass
10540 scc flag to `ccr_bit'. */
10541 i = ccr_bit (x, 1);
10543 output_operand_lossage ("invalid %%J code");
10545 /* If we want bit 31, write a shift count of zero, not 32. */
10546 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10550 /* X must be a constant. Write the 1's complement of the
10553 output_operand_lossage ("invalid %%k value");
10555 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10559 /* X must be a symbolic constant on ELF. Write an
10560 expression suitable for an 'addi' that adds in the low 16
10561 bits of the MEM. */
10562 if (GET_CODE (x) != CONST)
10564 print_operand_address (file, x);
10565 fputs ("@l", file);
10569 if (GET_CODE (XEXP (x, 0)) != PLUS
10570 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10571 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10572 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10573 output_operand_lossage ("invalid %%K value");
10574 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10575 fputs ("@l", file);
10576 /* For GNU as, there must be a non-alphanumeric character
10577 between 'l' and the number. The '-' is added by
10578 print_operand() already. */
10579 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10581 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10585 /* %l is output_asm_label. */
10588 /* Write second word of DImode or DFmode reference. Works on register
10589 or non-indexed memory only. */
10590 if (GET_CODE (x) == REG)
10591 fputs (reg_names[REGNO (x) + 1], file);
10592 else if (GET_CODE (x) == MEM)
10594 /* Handle possible auto-increment. Since it is pre-increment and
10595 we have already done it, we can just use an offset of word. */
10596 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10597 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10598 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10601 output_address (XEXP (adjust_address_nv (x, SImode,
10605 if (small_data_operand (x, GET_MODE (x)))
10606 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10607 reg_names[SMALL_DATA_REG]);
10612 /* MB value for a mask operand. */
10613 if (! mask_operand (x, SImode))
10614 output_operand_lossage ("invalid %%m value");
10616 fprintf (file, "%d", extract_MB (x));
10620 /* ME value for a mask operand. */
10621 if (! mask_operand (x, SImode))
10622 output_operand_lossage ("invalid %%M value");
10624 fprintf (file, "%d", extract_ME (x));
10627 /* %n outputs the negative of its operand. */
10630 /* Write the number of elements in the vector times 4. */
10631 if (GET_CODE (x) != PARALLEL)
10632 output_operand_lossage ("invalid %%N value");
10634 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10638 /* Similar, but subtract 1 first. */
10639 if (GET_CODE (x) != PARALLEL)
10640 output_operand_lossage ("invalid %%O value");
10642 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10646 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10648 || INT_LOWPART (x) < 0
10649 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10650 output_operand_lossage ("invalid %%p value");
10652 fprintf (file, "%d", i);
10656 /* The operand must be an indirect memory reference. The result
10657 is the register name. */
10658 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10659 || REGNO (XEXP (x, 0)) >= 32)
10660 output_operand_lossage ("invalid %%P value");
10662 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10666 /* This outputs the logical code corresponding to a boolean
10667 expression. The expression may have one or both operands
10668 negated (if one, only the first one). For condition register
10669 logical operations, it will also treat the negated
10670 CR codes as NOTs, but not handle NOTs of them. */
10672 const char *const *t = 0;
10674 enum rtx_code code = GET_CODE (x);
10675 static const char * const tbl[3][3] = {
10676 { "and", "andc", "nor" },
10677 { "or", "orc", "nand" },
10678 { "xor", "eqv", "xor" } };
10682 else if (code == IOR)
10684 else if (code == XOR)
10687 output_operand_lossage ("invalid %%q value");
10689 if (GET_CODE (XEXP (x, 0)) != NOT)
10693 if (GET_CODE (XEXP (x, 1)) == NOT)
10711 /* X is a CR register. Print the mask for `mtcrf'. */
10712 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10713 output_operand_lossage ("invalid %%R value");
10715 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10719 /* Low 5 bits of 32 - value */
10721 output_operand_lossage ("invalid %%s value");
10723 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10727 /* PowerPC64 mask position. All 0's is excluded.
10728 CONST_INT 32-bit mask is considered sign-extended so any
10729 transition must occur within the CONST_INT, not on the boundary. */
10730 if (! mask64_operand (x, DImode))
10731 output_operand_lossage ("invalid %%S value");
10733 uval = INT_LOWPART (x);
10735 if (uval & 1) /* Clear Left */
10737 #if HOST_BITS_PER_WIDE_INT > 64
10738 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10742 else /* Clear Right */
10745 #if HOST_BITS_PER_WIDE_INT > 64
10746 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10754 fprintf (file, "%d", i);
10758 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10759 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
10762 /* Bit 3 is OV bit. */
10763 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10765 /* If we want bit 31, write a shift count of zero, not 32. */
10766 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10770 /* Print the symbolic name of a branch target register. */
10771 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10772 && REGNO (x) != COUNT_REGISTER_REGNUM))
10773 output_operand_lossage ("invalid %%T value");
10774 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10775 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10777 fputs ("ctr", file);
10781 /* High-order 16 bits of constant for use in unsigned operand. */
10783 output_operand_lossage ("invalid %%u value");
10785 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10786 (INT_LOWPART (x) >> 16) & 0xffff);
10790 /* High-order 16 bits of constant for use in signed operand. */
10792 output_operand_lossage ("invalid %%v value");
10794 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10795 (INT_LOWPART (x) >> 16) & 0xffff);
10799 /* Print `u' if this has an auto-increment or auto-decrement. */
10800 if (GET_CODE (x) == MEM
10801 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10802 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10807 /* Print the trap code for this operand. */
10808 switch (GET_CODE (x))
10811 fputs ("eq", file); /* 4 */
10814 fputs ("ne", file); /* 24 */
10817 fputs ("lt", file); /* 16 */
10820 fputs ("le", file); /* 20 */
10823 fputs ("gt", file); /* 8 */
10826 fputs ("ge", file); /* 12 */
10829 fputs ("llt", file); /* 2 */
10832 fputs ("lle", file); /* 6 */
10835 fputs ("lgt", file); /* 1 */
10838 fputs ("lge", file); /* 5 */
10846 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10849 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10850 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10852 print_operand (file, x, 0);
10856 /* MB value for a PowerPC64 rldic operand. */
10857 val = (GET_CODE (x) == CONST_INT
10858 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10863 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10864 if ((val <<= 1) < 0)
10867 #if HOST_BITS_PER_WIDE_INT == 32
10868 if (GET_CODE (x) == CONST_INT && i >= 0)
10869 i += 32; /* zero-extend high-part was all 0's */
10870 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10872 val = CONST_DOUBLE_LOW (x);
10879 for ( ; i < 64; i++)
10880 if ((val <<= 1) < 0)
10885 fprintf (file, "%d", i + 1);
10889 if (GET_CODE (x) == MEM
10890 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10895 /* Like 'L', for third word of TImode */
10896 if (GET_CODE (x) == REG)
10897 fputs (reg_names[REGNO (x) + 2], file);
10898 else if (GET_CODE (x) == MEM)
10900 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10901 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10902 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10904 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10905 if (small_data_operand (x, GET_MODE (x)))
10906 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10907 reg_names[SMALL_DATA_REG]);
10912 /* X is a SYMBOL_REF. Write out the name preceded by a
10913 period and without any trailing data in brackets. Used for function
10914 names. If we are configured for System V (or the embedded ABI) on
10915 the PowerPC, do not emit the period, since those systems do not use
10916 TOCs and the like. */
10917 if (GET_CODE (x) != SYMBOL_REF)
10920 /* Mark the decl as referenced so that cgraph will output the
10922 if (SYMBOL_REF_DECL (x))
10923 mark_decl_referenced (SYMBOL_REF_DECL (x));
10925 /* For macho, check to see if we need a stub. */
10928 const char *name = XSTR (x, 0);
10930 if (MACHOPIC_INDIRECT
10931 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10932 name = machopic_indirection_name (x, /*stub_p=*/true);
10934 assemble_name (file, name);
10936 else if (!DOT_SYMBOLS)
10937 assemble_name (file, XSTR (x, 0));
10939 rs6000_output_function_entry (file, XSTR (x, 0));
10943 /* Like 'L', for last word of TImode. */
10944 if (GET_CODE (x) == REG)
10945 fputs (reg_names[REGNO (x) + 3], file);
10946 else if (GET_CODE (x) == MEM)
10948 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10949 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10950 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10952 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10953 if (small_data_operand (x, GET_MODE (x)))
10954 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10955 reg_names[SMALL_DATA_REG]);
10959 /* Print AltiVec or SPE memory operand. */
10964 if (GET_CODE (x) != MEM)
10971 /* Handle [reg]. */
10972 if (GET_CODE (tmp) == REG)
10974 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10977 /* Handle [reg+UIMM]. */
10978 else if (GET_CODE (tmp) == PLUS &&
10979 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10983 if (GET_CODE (XEXP (tmp, 0)) != REG)
10986 x = INTVAL (XEXP (tmp, 1));
10987 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10991 /* Fall through. Must be [reg+reg]. */
10994 && GET_CODE (tmp) == AND
10995 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10996 && INTVAL (XEXP (tmp, 1)) == -16)
10997 tmp = XEXP (tmp, 0);
10998 if (GET_CODE (tmp) == REG)
10999 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11000 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
11002 if (REGNO (XEXP (tmp, 0)) == 0)
11003 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11004 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11006 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11007 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11015 if (GET_CODE (x) == REG)
11016 fprintf (file, "%s", reg_names[REGNO (x)]);
11017 else if (GET_CODE (x) == MEM)
11019 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11020 know the width from the mode. */
11021 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11022 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11023 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11024 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11025 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11026 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11028 output_address (XEXP (x, 0));
11031 output_addr_const (file, x);
11035 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11039 output_operand_lossage ("invalid %%xn code");
11043 /* Print the address of an operand. */
11046 print_operand_address (FILE *file, rtx x)
11048 if (GET_CODE (x) == REG)
11049 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11050 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11051 || GET_CODE (x) == LABEL_REF)
11053 output_addr_const (file, x);
11054 if (small_data_operand (x, GET_MODE (x)))
11055 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11056 reg_names[SMALL_DATA_REG]);
11057 else if (TARGET_TOC)
11060 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11062 if (REGNO (XEXP (x, 0)) == 0)
11063 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11064 reg_names[ REGNO (XEXP (x, 0)) ]);
11066 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11067 reg_names[ REGNO (XEXP (x, 1)) ]);
11069 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11070 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11071 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11073 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11074 && CONSTANT_P (XEXP (x, 1)))
11076 output_addr_const (file, XEXP (x, 1));
11077 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11081 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11082 && CONSTANT_P (XEXP (x, 1)))
11084 fprintf (file, "lo16(");
11085 output_addr_const (file, XEXP (x, 1));
11086 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11089 else if (legitimate_constant_pool_address_p (x))
11091 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11093 rtx contains_minus = XEXP (x, 1);
11097 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11098 turn it into (sym) for output_addr_const. */
11099 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11100 contains_minus = XEXP (contains_minus, 0);
11102 minus = XEXP (contains_minus, 0);
11103 symref = XEXP (minus, 0);
11104 XEXP (contains_minus, 0) = symref;
11109 name = XSTR (symref, 0);
11110 newname = alloca (strlen (name) + sizeof ("@toc"));
11111 strcpy (newname, name);
11112 strcat (newname, "@toc");
11113 XSTR (symref, 0) = newname;
11115 output_addr_const (file, XEXP (x, 1));
11117 XSTR (symref, 0) = name;
11118 XEXP (contains_minus, 0) = minus;
11121 output_addr_const (file, XEXP (x, 1));
11123 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11129 /* Target hook for assembling integer objects. The PowerPC version has
11130 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11131 is defined. It also needs to handle DI-mode objects on 64-bit
11135 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11137 #ifdef RELOCATABLE_NEEDS_FIXUP
11138 /* Special handling for SI values. */
11139 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11141 extern int in_toc_section (void);
11142 static int recurse = 0;
11144 /* For -mrelocatable, we mark all addresses that need to be fixed up
11145 in the .fixup section. */
11146 if (TARGET_RELOCATABLE
11147 && !in_toc_section ()
11148 && !in_text_section ()
11149 && !in_unlikely_text_section ()
11151 && GET_CODE (x) != CONST_INT
11152 && GET_CODE (x) != CONST_DOUBLE
11158 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11160 ASM_OUTPUT_LABEL (asm_out_file, buf);
11161 fprintf (asm_out_file, "\t.long\t(");
11162 output_addr_const (asm_out_file, x);
11163 fprintf (asm_out_file, ")@fixup\n");
11164 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11165 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11166 fprintf (asm_out_file, "\t.long\t");
11167 assemble_name (asm_out_file, buf);
11168 fprintf (asm_out_file, "\n\t.previous\n");
11172 /* Remove initial .'s to turn a -mcall-aixdesc function
11173 address into the address of the descriptor, not the function
11175 else if (GET_CODE (x) == SYMBOL_REF
11176 && XSTR (x, 0)[0] == '.'
11177 && DEFAULT_ABI == ABI_AIX)
11179 const char *name = XSTR (x, 0);
11180 while (*name == '.')
11183 fprintf (asm_out_file, "\t.long\t%s\n", name);
11187 #endif /* RELOCATABLE_NEEDS_FIXUP */
11188 return default_assemble_integer (x, size, aligned_p);
11191 #ifdef HAVE_GAS_HIDDEN
11192 /* Emit an assembler directive to set symbol visibility for DECL to
11193 VISIBILITY_TYPE. */
11196 rs6000_assemble_visibility (tree decl, int vis)
11198 /* Functions need to have their entry point symbol visibility set as
11199 well as their descriptor symbol visibility. */
11200 if (DEFAULT_ABI == ABI_AIX
11202 && TREE_CODE (decl) == FUNCTION_DECL)
11204 static const char * const visibility_types[] = {
11205 NULL, "internal", "hidden", "protected"
11208 const char *name, *type;
11210 name = ((* targetm.strip_name_encoding)
11211 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11212 type = visibility_types[vis];
11214 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11215 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11218 default_assemble_visibility (decl, vis);
11223 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11225 /* Reversal of FP compares takes care -- an ordered compare
11226 becomes an unordered compare and vice versa. */
11227 if (mode == CCFPmode
11228 && (!flag_finite_math_only
11229 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11230 || code == UNEQ || code == LTGT))
11231 return reverse_condition_maybe_unordered (code);
11233 return reverse_condition (code);
11236 /* Generate a compare for CODE. Return a brand-new rtx that
11237 represents the result of the compare. */
11240 rs6000_generate_compare (enum rtx_code code)
11242 enum machine_mode comp_mode;
11243 rtx compare_result;
11245 if (rs6000_compare_fp_p)
11246 comp_mode = CCFPmode;
11247 else if (code == GTU || code == LTU
11248 || code == GEU || code == LEU)
11249 comp_mode = CCUNSmode;
11250 else if ((code == EQ || code == NE)
11251 && GET_CODE (rs6000_compare_op0) == SUBREG
11252 && GET_CODE (rs6000_compare_op1) == SUBREG
11253 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11254 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11255 /* These are unsigned values, perhaps there will be a later
11256 ordering compare that can be shared with this one.
11257 Unfortunately we cannot detect the signedness of the operands
11258 for non-subregs. */
11259 comp_mode = CCUNSmode;
11261 comp_mode = CCmode;
11263 /* First, the compare. */
11264 compare_result = gen_reg_rtx (comp_mode);
11266 /* SPE FP compare instructions on the GPRs. Yuck! */
11267 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11268 && rs6000_compare_fp_p)
11270 rtx cmp, or1, or2, or_result, compare_result2;
11271 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11273 if (op_mode == VOIDmode)
11274 op_mode = GET_MODE (rs6000_compare_op1);
11276 /* Note: The E500 comparison instructions set the GT bit (x +
11277 1), on success. This explains the mess. */
11281 case EQ: case UNEQ: case NE: case LTGT:
11282 if (op_mode == SFmode)
11283 cmp = flag_finite_math_only
11284 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11285 rs6000_compare_op1)
11286 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11287 rs6000_compare_op1);
11288 else if (op_mode == DFmode)
11289 cmp = flag_finite_math_only
11290 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11291 rs6000_compare_op1)
11292 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11293 rs6000_compare_op1);
11296 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11297 if (op_mode == SFmode)
11298 cmp = flag_finite_math_only
11299 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11300 rs6000_compare_op1)
11301 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11302 rs6000_compare_op1);
11303 else if (op_mode == DFmode)
11304 cmp = flag_finite_math_only
11305 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11306 rs6000_compare_op1)
11307 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11308 rs6000_compare_op1);
11311 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11312 if (op_mode == SFmode)
11313 cmp = flag_finite_math_only
11314 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11315 rs6000_compare_op1)
11316 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11317 rs6000_compare_op1);
11318 else if (op_mode == DFmode)
11319 cmp = flag_finite_math_only
11320 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11321 rs6000_compare_op1)
11322 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11323 rs6000_compare_op1);
11330 /* Synthesize LE and GE from LT/GT || EQ. */
11331 if (code == LE || code == GE || code == LEU || code == GEU)
11337 case LE: code = LT; break;
11338 case GE: code = GT; break;
11339 case LEU: code = LT; break;
11340 case GEU: code = GT; break;
11344 or1 = gen_reg_rtx (SImode);
11345 or2 = gen_reg_rtx (SImode);
11346 or_result = gen_reg_rtx (CCEQmode);
11347 compare_result2 = gen_reg_rtx (CCFPmode);
11350 if (op_mode == SFmode)
11351 cmp = flag_finite_math_only
11352 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11353 rs6000_compare_op1)
11354 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11355 rs6000_compare_op1);
11356 else if (op_mode == DFmode)
11357 cmp = flag_finite_math_only
11358 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11359 rs6000_compare_op1)
11360 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11361 rs6000_compare_op1);
11365 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
11366 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
11368 /* OR them together. */
11369 cmp = gen_rtx_SET (VOIDmode, or_result,
11370 gen_rtx_COMPARE (CCEQmode,
11371 gen_rtx_IOR (SImode, or1, or2),
11373 compare_result = or_result;
11378 if (code == NE || code == LTGT)
11387 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11388 gen_rtx_COMPARE (comp_mode,
11389 rs6000_compare_op0,
11390 rs6000_compare_op1)));
11392 /* Some kinds of FP comparisons need an OR operation;
11393 under flag_finite_math_only we don't bother. */
11394 if (rs6000_compare_fp_p
11395 && ! flag_finite_math_only
11396 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11397 && (code == LE || code == GE
11398 || code == UNEQ || code == LTGT
11399 || code == UNGT || code == UNLT))
11401 enum rtx_code or1, or2;
11402 rtx or1_rtx, or2_rtx, compare2_rtx;
11403 rtx or_result = gen_reg_rtx (CCEQmode);
11407 case LE: or1 = LT; or2 = EQ; break;
11408 case GE: or1 = GT; or2 = EQ; break;
11409 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11410 case LTGT: or1 = LT; or2 = GT; break;
11411 case UNGT: or1 = UNORDERED; or2 = GT; break;
11412 case UNLT: or1 = UNORDERED; or2 = LT; break;
11415 validate_condition_mode (or1, comp_mode);
11416 validate_condition_mode (or2, comp_mode);
11417 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11418 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11419 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11420 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11422 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11424 compare_result = or_result;
11428 validate_condition_mode (code, GET_MODE (compare_result));
11430 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11434 /* Emit the RTL for an sCOND pattern. */
11437 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11440 enum machine_mode op_mode;
11441 enum rtx_code cond_code;
11443 condition_rtx = rs6000_generate_compare (code);
11444 cond_code = GET_CODE (condition_rtx);
11446 if (TARGET_E500 && rs6000_compare_fp_p
11447 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11451 PUT_MODE (condition_rtx, SImode);
11452 t = XEXP (condition_rtx, 0);
11454 if (cond_code != NE && cond_code != EQ)
11457 if (cond_code == NE)
11458 emit_insn (gen_e500_flip_eq_bit (t, t));
11460 emit_insn (gen_move_from_CR_eq_bit (result, t));
11464 if (cond_code == NE
11465 || cond_code == GE || cond_code == LE
11466 || cond_code == GEU || cond_code == LEU
11467 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11469 rtx not_result = gen_reg_rtx (CCEQmode);
11470 rtx not_op, rev_cond_rtx;
11471 enum machine_mode cc_mode;
11473 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11475 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11476 SImode, XEXP (condition_rtx, 0), const0_rtx);
11477 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11478 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11479 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11482 op_mode = GET_MODE (rs6000_compare_op0);
11483 if (op_mode == VOIDmode)
11484 op_mode = GET_MODE (rs6000_compare_op1);
11486 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11488 PUT_MODE (condition_rtx, DImode);
11489 convert_move (result, condition_rtx, 0);
11493 PUT_MODE (condition_rtx, SImode);
11494 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11498 /* Emit a branch of kind CODE to location LOC. */
11501 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11503 rtx condition_rtx, loc_ref;
11505 condition_rtx = rs6000_generate_compare (code);
11506 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11507 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11508 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11509 loc_ref, pc_rtx)));
11512 /* Return the string to output a conditional branch to LABEL, which is
11513 the operand number of the label, or -1 if the branch is really a
11514 conditional return.
11516 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11517 condition code register and its mode specifies what kind of
11518 comparison we made.
11520 REVERSED is nonzero if we should reverse the sense of the comparison.
11522 INSN is the insn. */
11525 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11527 static char string[64];
11528 enum rtx_code code = GET_CODE (op);
11529 rtx cc_reg = XEXP (op, 0);
11530 enum machine_mode mode = GET_MODE (cc_reg);
11531 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11532 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11533 int really_reversed = reversed ^ need_longbranch;
11539 validate_condition_mode (code, mode);
11541 /* Work out which way this really branches. We could use
11542 reverse_condition_maybe_unordered here always but this
11543 makes the resulting assembler clearer. */
11544 if (really_reversed)
11546 /* Reversal of FP compares takes care -- an ordered compare
11547 becomes an unordered compare and vice versa. */
11548 if (mode == CCFPmode)
11549 code = reverse_condition_maybe_unordered (code);
11551 code = reverse_condition (code);
11554 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11556 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11559 /* Opposite of GT. */
11561 else if (code == NE)
11569 /* Not all of these are actually distinct opcodes, but
11570 we distinguish them for clarity of the resulting assembler. */
11571 case NE: case LTGT:
11572 ccode = "ne"; break;
11573 case EQ: case UNEQ:
11574 ccode = "eq"; break;
11576 ccode = "ge"; break;
11577 case GT: case GTU: case UNGT:
11578 ccode = "gt"; break;
11580 ccode = "le"; break;
11581 case LT: case LTU: case UNLT:
11582 ccode = "lt"; break;
11583 case UNORDERED: ccode = "un"; break;
11584 case ORDERED: ccode = "nu"; break;
11585 case UNGE: ccode = "nl"; break;
11586 case UNLE: ccode = "ng"; break;
11591 /* Maybe we have a guess as to how likely the branch is.
11592 The old mnemonics don't have a way to specify this information. */
11594 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11595 if (note != NULL_RTX)
11597 /* PROB is the difference from 50%. */
11598 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11600 /* Only hint for highly probable/improbable branches on newer
11601 cpus as static prediction overrides processor dynamic
11602 prediction. For older cpus we may as well always hint, but
11603 assume not taken for branches that are very close to 50% as a
11604 mispredicted taken branch is more expensive than a
11605 mispredicted not-taken branch. */
11606 if (rs6000_always_hint
11607 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11609 if (abs (prob) > REG_BR_PROB_BASE / 20
11610 && ((prob > 0) ^ need_longbranch))
11618 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11620 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11622 /* We need to escape any '%' characters in the reg_names string.
11623 Assume they'd only be the first character.... */
11624 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11626 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11630 /* If the branch distance was too far, we may have to use an
11631 unconditional branch to go the distance. */
11632 if (need_longbranch)
11633 s += sprintf (s, ",$+8\n\tb %s", label);
11635 s += sprintf (s, ",%s", label);
11641 /* Return the string to flip the EQ bit on a CR. */
11643 output_e500_flip_eq_bit (rtx dst, rtx src)
11645 static char string[64];
11648 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
11649 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
11653 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
11654 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
11656 sprintf (string, "crnot %d,%d", a, b);
11660 /* Return insn index for the vector compare instruction for given CODE,
11661 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11665 get_vec_cmp_insn (enum rtx_code code,
11666 enum machine_mode dest_mode,
11667 enum machine_mode op_mode)
11669 if (!TARGET_ALTIVEC)
11670 return INSN_NOT_AVAILABLE;
11675 if (dest_mode == V16QImode && op_mode == V16QImode)
11676 return UNSPEC_VCMPEQUB;
11677 if (dest_mode == V8HImode && op_mode == V8HImode)
11678 return UNSPEC_VCMPEQUH;
11679 if (dest_mode == V4SImode && op_mode == V4SImode)
11680 return UNSPEC_VCMPEQUW;
11681 if (dest_mode == V4SImode && op_mode == V4SFmode)
11682 return UNSPEC_VCMPEQFP;
11685 if (dest_mode == V4SImode && op_mode == V4SFmode)
11686 return UNSPEC_VCMPGEFP;
11688 if (dest_mode == V16QImode && op_mode == V16QImode)
11689 return UNSPEC_VCMPGTSB;
11690 if (dest_mode == V8HImode && op_mode == V8HImode)
11691 return UNSPEC_VCMPGTSH;
11692 if (dest_mode == V4SImode && op_mode == V4SImode)
11693 return UNSPEC_VCMPGTSW;
11694 if (dest_mode == V4SImode && op_mode == V4SFmode)
11695 return UNSPEC_VCMPGTFP;
11698 if (dest_mode == V16QImode && op_mode == V16QImode)
11699 return UNSPEC_VCMPGTUB;
11700 if (dest_mode == V8HImode && op_mode == V8HImode)
11701 return UNSPEC_VCMPGTUH;
11702 if (dest_mode == V4SImode && op_mode == V4SImode)
11703 return UNSPEC_VCMPGTUW;
11708 return INSN_NOT_AVAILABLE;
11711 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11712 DMODE is expected destination mode. This is a recursive function. */
11715 rs6000_emit_vector_compare (enum rtx_code rcode,
11717 enum machine_mode dmode)
11721 enum machine_mode dest_mode;
11722 enum machine_mode op_mode = GET_MODE (op1);
11724 #ifdef ENABLE_CHECKING
11725 if (!TARGET_ALTIVEC)
11728 if (GET_MODE (op0) != GET_MODE (op1))
11732 /* Floating point vector compare instructions uses destination V4SImode.
11733 Move destination to appropriate mode later. */
11734 if (dmode == V4SFmode)
11735 dest_mode = V4SImode;
11739 mask = gen_reg_rtx (dest_mode);
11740 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11742 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11744 bool swap_operands = false;
11745 bool try_again = false;
11750 swap_operands = true;
11755 swap_operands = true;
11759 /* Treat A != B as ~(A==B). */
11761 enum insn_code nor_code;
11762 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11765 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11766 if (nor_code == CODE_FOR_nothing)
11768 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11770 if (dmode != dest_mode)
11772 rtx temp = gen_reg_rtx (dest_mode);
11773 convert_move (temp, mask, 0);
11783 /* Try GT/GTU/LT/LTU OR EQ */
11786 enum insn_code ior_code;
11787 enum rtx_code new_code;
11791 else if (rcode == GEU)
11793 else if (rcode == LE)
11795 else if (rcode == LEU)
11800 c_rtx = rs6000_emit_vector_compare (new_code,
11801 op0, op1, dest_mode);
11802 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11805 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11806 if (ior_code == CODE_FOR_nothing)
11808 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11809 if (dmode != dest_mode)
11811 rtx temp = gen_reg_rtx (dest_mode);
11812 convert_move (temp, mask, 0);
11824 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11825 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11826 /* You only get two chances. */
11839 emit_insn (gen_rtx_fmt_ee (SET,
11842 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11843 gen_rtvec (2, op0, op1),
11845 if (dmode != dest_mode)
11847 rtx temp = gen_reg_rtx (dest_mode);
11848 convert_move (temp, mask, 0);
11854 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11855 valid insn doesn exist for given mode. */
11858 get_vsel_insn (enum machine_mode mode)
11863 return UNSPEC_VSEL4SI;
11866 return UNSPEC_VSEL4SF;
11869 return UNSPEC_VSEL8HI;
11872 return UNSPEC_VSEL16QI;
11875 return INSN_NOT_AVAILABLE;
11878 return INSN_NOT_AVAILABLE;
11881 /* Emit vector select insn where DEST is destination using
11882 operands OP1, OP2 and MASK. */
11885 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11888 enum machine_mode dest_mode = GET_MODE (dest);
11889 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11891 temp = gen_reg_rtx (dest_mode);
11893 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
11894 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11895 gen_rtvec (3, op1, op2, mask),
11898 emit_move_insn (dest, temp);
11902 /* Emit vector conditional expression.
11903 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11904 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11907 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11908 rtx cond, rtx cc_op0, rtx cc_op1)
11910 enum machine_mode dest_mode = GET_MODE (dest);
11911 enum rtx_code rcode = GET_CODE (cond);
11914 if (!TARGET_ALTIVEC)
11917 /* Get the vector mask for the given relational operations. */
11918 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11920 rs6000_emit_vector_select (dest, op1, op2, mask);
11925 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11926 operands of the last comparison is nonzero/true, FALSE_COND if it
11927 is zero/false. Return 0 if the hardware has no such operation. */
11930 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11932 enum rtx_code code = GET_CODE (op);
11933 rtx op0 = rs6000_compare_op0;
11934 rtx op1 = rs6000_compare_op1;
11935 REAL_VALUE_TYPE c1;
11936 enum machine_mode compare_mode = GET_MODE (op0);
11937 enum machine_mode result_mode = GET_MODE (dest);
11939 bool is_against_zero;
11941 /* These modes should always match. */
11942 if (GET_MODE (op1) != compare_mode
11943 /* In the isel case however, we can use a compare immediate, so
11944 op1 may be a small constant. */
11945 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11947 if (GET_MODE (true_cond) != result_mode)
11949 if (GET_MODE (false_cond) != result_mode)
11952 /* First, work out if the hardware can do this at all, or
11953 if it's too slow.... */
11954 if (! rs6000_compare_fp_p)
11957 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11960 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11961 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11964 is_against_zero = op1 == CONST0_RTX (compare_mode);
11966 /* A floating-point subtract might overflow, underflow, or produce
11967 an inexact result, thus changing the floating-point flags, so it
11968 can't be generated if we care about that. It's safe if one side
11969 of the construct is zero, since then no subtract will be
11971 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11972 && flag_trapping_math && ! is_against_zero)
11975 /* Eliminate half of the comparisons by switching operands, this
11976 makes the remaining code simpler. */
11977 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11978 || code == LTGT || code == LT || code == UNLE)
11980 code = reverse_condition_maybe_unordered (code);
11982 true_cond = false_cond;
11986 /* UNEQ and LTGT take four instructions for a comparison with zero,
11987 it'll probably be faster to use a branch here too. */
11988 if (code == UNEQ && HONOR_NANS (compare_mode))
11991 if (GET_CODE (op1) == CONST_DOUBLE)
11992 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11994 /* We're going to try to implement comparisons by performing
11995 a subtract, then comparing against zero. Unfortunately,
11996 Inf - Inf is NaN which is not zero, and so if we don't
11997 know that the operand is finite and the comparison
11998 would treat EQ different to UNORDERED, we can't do it. */
11999 if (HONOR_INFINITIES (compare_mode)
12000 && code != GT && code != UNGE
12001 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12002 /* Constructs of the form (a OP b ? a : b) are safe. */
12003 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12004 || (! rtx_equal_p (op0, true_cond)
12005 && ! rtx_equal_p (op1, true_cond))))
12008 /* At this point we know we can use fsel. */
12010 /* Reduce the comparison to a comparison against zero. */
12011 if (! is_against_zero)
12013 temp = gen_reg_rtx (compare_mode);
12014 emit_insn (gen_rtx_SET (VOIDmode, temp,
12015 gen_rtx_MINUS (compare_mode, op0, op1)));
12017 op1 = CONST0_RTX (compare_mode);
12020 /* If we don't care about NaNs we can reduce some of the comparisons
12021 down to faster ones. */
12022 if (! HONOR_NANS (compare_mode))
12028 true_cond = false_cond;
12041 /* Now, reduce everything down to a GE. */
12048 temp = gen_reg_rtx (compare_mode);
12049 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12054 temp = gen_reg_rtx (compare_mode);
12055 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12060 temp = gen_reg_rtx (compare_mode);
12061 emit_insn (gen_rtx_SET (VOIDmode, temp,
12062 gen_rtx_NEG (compare_mode,
12063 gen_rtx_ABS (compare_mode, op0))));
12068 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12069 temp = gen_reg_rtx (result_mode);
12070 emit_insn (gen_rtx_SET (VOIDmode, temp,
12071 gen_rtx_IF_THEN_ELSE (result_mode,
12072 gen_rtx_GE (VOIDmode,
12074 true_cond, false_cond)));
12075 false_cond = true_cond;
12078 temp = gen_reg_rtx (compare_mode);
12079 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12084 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12085 temp = gen_reg_rtx (result_mode);
12086 emit_insn (gen_rtx_SET (VOIDmode, temp,
12087 gen_rtx_IF_THEN_ELSE (result_mode,
12088 gen_rtx_GE (VOIDmode,
12090 true_cond, false_cond)));
12091 true_cond = false_cond;
12094 temp = gen_reg_rtx (compare_mode);
12095 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12103 emit_insn (gen_rtx_SET (VOIDmode, dest,
12104 gen_rtx_IF_THEN_ELSE (result_mode,
12105 gen_rtx_GE (VOIDmode,
12107 true_cond, false_cond)));
12111 /* Same as above, but for ints (isel). */
12114 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12116 rtx condition_rtx, cr;
12118 /* All isel implementations thus far are 32-bits. */
12119 if (GET_MODE (rs6000_compare_op0) != SImode)
12122 /* We still have to do the compare, because isel doesn't do a
12123 compare, it just looks at the CRx bits set by a previous compare
12125 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12126 cr = XEXP (condition_rtx, 0);
12128 if (GET_MODE (cr) == CCmode)
12129 emit_insn (gen_isel_signed (dest, condition_rtx,
12130 true_cond, false_cond, cr));
12132 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12133 true_cond, false_cond, cr));
12139 output_isel (rtx *operands)
12141 enum rtx_code code;
12143 code = GET_CODE (operands[1]);
12144 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12146 PUT_CODE (operands[1], reverse_condition (code));
12147 return "isel %0,%3,%2,%j1";
12150 return "isel %0,%2,%3,%j1";
12154 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12156 enum machine_mode mode = GET_MODE (op0);
12160 if (code == SMAX || code == SMIN)
12165 if (code == SMAX || code == UMAX)
12166 target = emit_conditional_move (dest, c, op0, op1, mode,
12167 op0, op1, mode, 0);
12169 target = emit_conditional_move (dest, c, op0, op1, mode,
12170 op1, op0, mode, 0);
12171 if (target == NULL_RTX)
12173 if (target != dest)
12174 emit_move_insn (dest, target);
12177 /* Emit instructions to move SRC to DST. Called by splitters for
12178 multi-register moves. It will emit at most one instruction for
12179 each register that is accessed; that is, it won't emit li/lis pairs
12180 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12184 rs6000_split_multireg_move (rtx dst, rtx src)
12186 /* The register number of the first register being moved. */
12188 /* The mode that is to be moved. */
12189 enum machine_mode mode;
12190 /* The mode that the move is being done in, and its size. */
12191 enum machine_mode reg_mode;
12193 /* The number of registers that will be moved. */
12196 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12197 mode = GET_MODE (dst);
12198 nregs = HARD_REGNO_NREGS (reg, mode);
12199 if (FP_REGNO_P (reg))
12201 else if (ALTIVEC_REGNO_P (reg))
12202 reg_mode = V16QImode;
12204 reg_mode = word_mode;
12205 reg_mode_size = GET_MODE_SIZE (reg_mode);
12207 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
12210 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12212 /* Move register range backwards, if we might have destructive
12215 for (i = nregs - 1; i >= 0; i--)
12216 emit_insn (gen_rtx_SET (VOIDmode,
12217 simplify_gen_subreg (reg_mode, dst, mode,
12218 i * reg_mode_size),
12219 simplify_gen_subreg (reg_mode, src, mode,
12220 i * reg_mode_size)));
12226 bool used_update = false;
12228 if (MEM_P (src) && INT_REGNO_P (reg))
12232 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12233 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12236 breg = XEXP (XEXP (src, 0), 0);
12237 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12238 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12239 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12240 emit_insn (TARGET_32BIT
12241 ? gen_addsi3 (breg, breg, delta_rtx)
12242 : gen_adddi3 (breg, breg, delta_rtx));
12243 src = gen_rtx_MEM (mode, breg);
12245 else if (! offsettable_memref_p (src))
12247 rtx newsrc, basereg;
12248 basereg = gen_rtx_REG (Pmode, reg);
12249 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12250 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
12251 MEM_COPY_ATTRIBUTES (newsrc, src);
12255 breg = XEXP (src, 0);
12256 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12257 breg = XEXP (breg, 0);
12259 /* If the base register we are using to address memory is
12260 also a destination reg, then change that register last. */
12262 && REGNO (breg) >= REGNO (dst)
12263 && REGNO (breg) < REGNO (dst) + nregs)
12264 j = REGNO (breg) - REGNO (dst);
12267 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12271 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12272 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12275 breg = XEXP (XEXP (dst, 0), 0);
12276 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12277 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12278 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12280 /* We have to update the breg before doing the store.
12281 Use store with update, if available. */
12285 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12286 emit_insn (TARGET_32BIT
12287 ? (TARGET_POWERPC64
12288 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12289 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12290 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12291 used_update = true;
12294 emit_insn (TARGET_32BIT
12295 ? gen_addsi3 (breg, breg, delta_rtx)
12296 : gen_adddi3 (breg, breg, delta_rtx));
12297 dst = gen_rtx_MEM (mode, breg);
12299 else if (! offsettable_memref_p (dst))
12303 for (i = 0; i < nregs; i++)
12305 /* Calculate index to next subword. */
12310 /* If compiler already emitted move of first word by
12311 store with update, no need to do anything. */
12312 if (j == 0 && used_update)
12315 emit_insn (gen_rtx_SET (VOIDmode,
12316 simplify_gen_subreg (reg_mode, dst, mode,
12317 j * reg_mode_size),
12318 simplify_gen_subreg (reg_mode, src, mode,
12319 j * reg_mode_size)));
12325 /* This page contains routines that are used to determine what the
12326 function prologue and epilogue code will do and write them out. */
12328 /* Return the first fixed-point register that is required to be
12329 saved. 32 if none. */
12332 first_reg_to_save (void)
12336 /* Find lowest numbered live register. */
12337 for (first_reg = 13; first_reg <= 31; first_reg++)
12338 if (regs_ever_live[first_reg]
12339 && (! call_used_regs[first_reg]
12340 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12341 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12342 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12343 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12348 && current_function_uses_pic_offset_table
12349 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12350 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12356 /* Similar, for FP regs. */
12359 first_fp_reg_to_save (void)
12363 /* Find lowest numbered live register. */
12364 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12365 if (regs_ever_live[first_reg])
12371 /* Similar, for AltiVec regs. */
12374 first_altivec_reg_to_save (void)
12378 /* Stack frame remains as is unless we are in AltiVec ABI. */
12379 if (! TARGET_ALTIVEC_ABI)
12380 return LAST_ALTIVEC_REGNO + 1;
12382 /* Find lowest numbered live register. */
12383 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12384 if (regs_ever_live[i])
12390 /* Return a 32-bit mask of the AltiVec registers we need to set in
12391 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12392 the 32-bit word is 0. */
12394 static unsigned int
12395 compute_vrsave_mask (void)
12397 unsigned int i, mask = 0;
12399 /* First, find out if we use _any_ altivec registers. */
12400 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12401 if (regs_ever_live[i])
12402 mask |= ALTIVEC_REG_BIT (i);
12407 /* Next, remove the argument registers from the set. These must
12408 be in the VRSAVE mask set by the caller, so we don't need to add
12409 them in again. More importantly, the mask we compute here is
12410 used to generate CLOBBERs in the set_vrsave insn, and we do not
12411 wish the argument registers to die. */
12412 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12413 mask &= ~ALTIVEC_REG_BIT (i);
12415 /* Similarly, remove the return value from the set. */
12418 diddle_return_value (is_altivec_return_reg, &yes);
12420 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12426 /* For a very restricted set of circumstances, we can cut down the
12427 size of prologues/epilogues by calling our own save/restore-the-world
12431 compute_save_world_info (rs6000_stack_t *info_ptr)
12433 info_ptr->world_save_p = 1;
12434 info_ptr->world_save_p
12435 = (WORLD_SAVE_P (info_ptr)
12436 && DEFAULT_ABI == ABI_DARWIN
12437 && ! (current_function_calls_setjmp && flag_exceptions)
12438 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12439 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12440 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12441 && info_ptr->cr_save_p);
12443 /* This will not work in conjunction with sibcalls. Make sure there
12444 are none. (This check is expensive, but seldom executed.) */
12445 if (WORLD_SAVE_P (info_ptr))
12448 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12449 if ( GET_CODE (insn) == CALL_INSN
12450 && SIBLING_CALL_P (insn))
12452 info_ptr->world_save_p = 0;
12457 if (WORLD_SAVE_P (info_ptr))
12459 /* Even if we're not touching VRsave, make sure there's room on the
12460 stack for it, if it looks like we're calling SAVE_WORLD, which
12461 will attempt to save it. */
12462 info_ptr->vrsave_size = 4;
12464 /* "Save" the VRsave register too if we're saving the world. */
12465 if (info_ptr->vrsave_mask == 0)
12466 info_ptr->vrsave_mask = compute_vrsave_mask ();
12468 /* Because the Darwin register save/restore routines only handle
12469 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12470 check and abort if there's something worng. */
12471 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
12472 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
12480 is_altivec_return_reg (rtx reg, void *xyes)
12482 bool *yes = (bool *) xyes;
12483 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12488 /* Calculate the stack information for the current function. This is
12489 complicated by having two separate calling sequences, the AIX calling
12490 sequence and the V.4 calling sequence.
12492 AIX (and Darwin/Mac OS X) stack frames look like:
12494 SP----> +---------------------------------------+
12495 | back chain to caller | 0 0
12496 +---------------------------------------+
12497 | saved CR | 4 8 (8-11)
12498 +---------------------------------------+
12500 +---------------------------------------+
12501 | reserved for compilers | 12 24
12502 +---------------------------------------+
12503 | reserved for binders | 16 32
12504 +---------------------------------------+
12505 | saved TOC pointer | 20 40
12506 +---------------------------------------+
12507 | Parameter save area (P) | 24 48
12508 +---------------------------------------+
12509 | Alloca space (A) | 24+P etc.
12510 +---------------------------------------+
12511 | Local variable space (L) | 24+P+A
12512 +---------------------------------------+
12513 | Float/int conversion temporary (X) | 24+P+A+L
12514 +---------------------------------------+
12515 | Save area for AltiVec registers (W) | 24+P+A+L+X
12516 +---------------------------------------+
12517 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12518 +---------------------------------------+
12519 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12520 +---------------------------------------+
12521 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12522 +---------------------------------------+
12523 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12524 +---------------------------------------+
12525 old SP->| back chain to caller's caller |
12526 +---------------------------------------+
12528 The required alignment for AIX configurations is two words (i.e., 8
12532 V.4 stack frames look like:
12534 SP----> +---------------------------------------+
12535 | back chain to caller | 0
12536 +---------------------------------------+
12537 | caller's saved LR | 4
12538 +---------------------------------------+
12539 | Parameter save area (P) | 8
12540 +---------------------------------------+
12541 | Alloca space (A) | 8+P
12542 +---------------------------------------+
12543 | Varargs save area (V) | 8+P+A
12544 +---------------------------------------+
12545 | Local variable space (L) | 8+P+A+V
12546 +---------------------------------------+
12547 | Float/int conversion temporary (X) | 8+P+A+V+L
12548 +---------------------------------------+
12549 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12550 +---------------------------------------+
12551 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12552 +---------------------------------------+
12553 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12554 +---------------------------------------+
12555 | SPE: area for 64-bit GP registers |
12556 +---------------------------------------+
12557 | SPE alignment padding |
12558 +---------------------------------------+
12559 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12560 +---------------------------------------+
12561 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12562 +---------------------------------------+
12563 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12564 +---------------------------------------+
12565 old SP->| back chain to caller's caller |
12566 +---------------------------------------+
12568 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12569 given. (But note below and in sysv4.h that we require only 8 and
12570 may round up the size of our stack frame anyways. The historical
12571 reason is early versions of powerpc-linux which didn't properly
12572 align the stack at program startup. A happy side-effect is that
12573 -mno-eabi libraries can be used with -meabi programs.)
12575 The EABI configuration defaults to the V.4 layout. However,
12576 the stack alignment requirements may differ. If -mno-eabi is not
12577 given, the required stack alignment is 8 bytes; if -mno-eabi is
12578 given, the required alignment is 16 bytes. (But see V.4 comment
12581 #ifndef ABI_STACK_BOUNDARY
12582 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12585 static rs6000_stack_t *
12586 rs6000_stack_info (void)
12588 static rs6000_stack_t info, zero_info;
12589 rs6000_stack_t *info_ptr = &info;
12590 int reg_size = TARGET_32BIT ? 4 : 8;
12593 HOST_WIDE_INT non_fixed_size;
12595 /* Zero all fields portably. */
12600 /* Cache value so we don't rescan instruction chain over and over. */
12601 if (cfun->machine->insn_chain_scanned_p == 0)
12603 cfun->machine->insn_chain_scanned_p = 1;
12604 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
12608 /* Select which calling sequence. */
12609 info_ptr->abi = DEFAULT_ABI;
12611 /* Calculate which registers need to be saved & save area size. */
12612 info_ptr->first_gp_reg_save = first_reg_to_save ();
12613 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12614 even if it currently looks like we won't. */
12615 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12616 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12617 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12618 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12619 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12621 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12623 /* For the SPE, we have an additional upper 32-bits on each GPR.
12624 Ideally we should save the entire 64-bits only when the upper
12625 half is used in SIMD instructions. Since we only record
12626 registers live (not the size they are used in), this proves
12627 difficult because we'd have to traverse the instruction chain at
12628 the right time, taking reload into account. This is a real pain,
12629 so we opt to save the GPRs in 64-bits always if but one register
12630 gets used in 64-bits. Otherwise, all the registers in the frame
12631 get saved in 32-bits.
12633 So... since when we save all GPRs (except the SP) in 64-bits, the
12634 traditional GP save area will be empty. */
12635 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12636 info_ptr->gp_size = 0;
12638 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12639 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12641 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12642 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12643 - info_ptr->first_altivec_reg_save);
12645 /* Does this function call anything? */
12646 info_ptr->calls_p = (! current_function_is_leaf
12647 || cfun->machine->ra_needs_full_frame);
12649 /* Determine if we need to save the link register. */
12650 if (rs6000_ra_ever_killed ()
12651 || (DEFAULT_ABI == ABI_AIX
12652 && current_function_profile
12653 && !TARGET_PROFILE_KERNEL)
12654 #ifdef TARGET_RELOCATABLE
12655 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12657 || (info_ptr->first_fp_reg_save != 64
12658 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12659 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12660 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12661 || (DEFAULT_ABI == ABI_DARWIN
12663 && current_function_uses_pic_offset_table)
12664 || info_ptr->calls_p)
12666 info_ptr->lr_save_p = 1;
12667 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12670 /* Determine if we need to save the condition code registers. */
12671 if (regs_ever_live[CR2_REGNO]
12672 || regs_ever_live[CR3_REGNO]
12673 || regs_ever_live[CR4_REGNO])
12675 info_ptr->cr_save_p = 1;
12676 if (DEFAULT_ABI == ABI_V4)
12677 info_ptr->cr_size = reg_size;
12680 /* If the current function calls __builtin_eh_return, then we need
12681 to allocate stack space for registers that will hold data for
12682 the exception handler. */
12683 if (current_function_calls_eh_return)
12686 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12689 /* SPE saves EH registers in 64-bits. */
12690 ehrd_size = i * (TARGET_SPE_ABI
12691 && info_ptr->spe_64bit_regs_used != 0
12692 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12697 /* Determine various sizes. */
12698 info_ptr->reg_size = reg_size;
12699 info_ptr->fixed_size = RS6000_SAVE_AREA;
12700 info_ptr->varargs_size = RS6000_VARARGS_AREA;
12701 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12702 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12703 TARGET_ALTIVEC ? 16 : 8);
12705 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12706 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12708 info_ptr->spe_gp_size = 0;
12710 if (TARGET_ALTIVEC_ABI)
12711 info_ptr->vrsave_mask = compute_vrsave_mask ();
12713 info_ptr->vrsave_mask = 0;
12715 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12716 info_ptr->vrsave_size = 4;
12718 info_ptr->vrsave_size = 0;
12720 compute_save_world_info (info_ptr);
12722 /* Calculate the offsets. */
12723 switch (DEFAULT_ABI)
12731 info_ptr->fp_save_offset = - info_ptr->fp_size;
12732 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12734 if (TARGET_ALTIVEC_ABI)
12736 info_ptr->vrsave_save_offset
12737 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12739 /* Align stack so vector save area is on a quadword boundary. */
12740 if (info_ptr->altivec_size != 0)
12741 info_ptr->altivec_padding_size
12742 = 16 - (-info_ptr->vrsave_save_offset % 16);
12744 info_ptr->altivec_padding_size = 0;
12746 info_ptr->altivec_save_offset
12747 = info_ptr->vrsave_save_offset
12748 - info_ptr->altivec_padding_size
12749 - info_ptr->altivec_size;
12751 /* Adjust for AltiVec case. */
12752 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12755 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12756 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12757 info_ptr->lr_save_offset = 2*reg_size;
12761 info_ptr->fp_save_offset = - info_ptr->fp_size;
12762 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12763 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12765 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12767 /* Align stack so SPE GPR save area is aligned on a
12768 double-word boundary. */
12769 if (info_ptr->spe_gp_size != 0)
12770 info_ptr->spe_padding_size
12771 = 8 - (-info_ptr->cr_save_offset % 8);
12773 info_ptr->spe_padding_size = 0;
12775 info_ptr->spe_gp_save_offset
12776 = info_ptr->cr_save_offset
12777 - info_ptr->spe_padding_size
12778 - info_ptr->spe_gp_size;
12780 /* Adjust for SPE case. */
12781 info_ptr->toc_save_offset
12782 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12784 else if (TARGET_ALTIVEC_ABI)
12786 info_ptr->vrsave_save_offset
12787 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12789 /* Align stack so vector save area is on a quadword boundary. */
12790 if (info_ptr->altivec_size != 0)
12791 info_ptr->altivec_padding_size
12792 = 16 - (-info_ptr->vrsave_save_offset % 16);
12794 info_ptr->altivec_padding_size = 0;
12796 info_ptr->altivec_save_offset
12797 = info_ptr->vrsave_save_offset
12798 - info_ptr->altivec_padding_size
12799 - info_ptr->altivec_size;
12801 /* Adjust for AltiVec case. */
12802 info_ptr->toc_save_offset
12803 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12806 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12807 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12808 info_ptr->lr_save_offset = reg_size;
12812 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12813 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12814 + info_ptr->gp_size
12815 + info_ptr->altivec_size
12816 + info_ptr->altivec_padding_size
12817 + info_ptr->spe_gp_size
12818 + info_ptr->spe_padding_size
12820 + info_ptr->cr_size
12821 + info_ptr->lr_size
12822 + info_ptr->vrsave_size
12823 + info_ptr->toc_size,
12826 non_fixed_size = (info_ptr->vars_size
12827 + info_ptr->parm_size
12828 + info_ptr->save_size
12829 + info_ptr->varargs_size);
12831 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12832 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12834 /* Determine if we need to allocate any stack frame:
12836 For AIX we need to push the stack if a frame pointer is needed
12837 (because the stack might be dynamically adjusted), if we are
12838 debugging, if we make calls, or if the sum of fp_save, gp_save,
12839 and local variables are more than the space needed to save all
12840 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12841 + 18*8 = 288 (GPR13 reserved).
12843 For V.4 we don't have the stack cushion that AIX uses, but assume
12844 that the debugger can handle stackless frames. */
12846 if (info_ptr->calls_p)
12847 info_ptr->push_p = 1;
12849 else if (DEFAULT_ABI == ABI_V4)
12850 info_ptr->push_p = non_fixed_size != 0;
12852 else if (frame_pointer_needed)
12853 info_ptr->push_p = 1;
12855 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12856 info_ptr->push_p = 1;
12859 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12861 /* Zero offsets if we're not saving those registers. */
12862 if (info_ptr->fp_size == 0)
12863 info_ptr->fp_save_offset = 0;
12865 if (info_ptr->gp_size == 0)
12866 info_ptr->gp_save_offset = 0;
12868 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12869 info_ptr->altivec_save_offset = 0;
12871 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12872 info_ptr->vrsave_save_offset = 0;
12874 if (! TARGET_SPE_ABI
12875 || info_ptr->spe_64bit_regs_used == 0
12876 || info_ptr->spe_gp_size == 0)
12877 info_ptr->spe_gp_save_offset = 0;
12879 if (! info_ptr->lr_save_p)
12880 info_ptr->lr_save_offset = 0;
12882 if (! info_ptr->cr_save_p)
12883 info_ptr->cr_save_offset = 0;
12885 if (! info_ptr->toc_save_p)
12886 info_ptr->toc_save_offset = 0;
12891 /* Return true if the current function uses any GPRs in 64-bit SIMD
12895 spe_func_has_64bit_regs_p (void)
12899 /* Functions that save and restore all the call-saved registers will
12900 need to save/restore the registers in 64-bits. */
12901 if (current_function_calls_eh_return
12902 || current_function_calls_setjmp
12903 || current_function_has_nonlocal_goto)
12906 insns = get_insns ();
12908 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12914 i = PATTERN (insn);
12915 if (GET_CODE (i) == SET)
12917 enum machine_mode mode = GET_MODE (SET_SRC (i));
12919 if (SPE_VECTOR_MODE (mode))
12921 if (TARGET_E500_DOUBLE && mode == DFmode)
12931 debug_stack_info (rs6000_stack_t *info)
12933 const char *abi_string;
12936 info = rs6000_stack_info ();
12938 fprintf (stderr, "\nStack information for function %s:\n",
12939 ((current_function_decl && DECL_NAME (current_function_decl))
12940 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12945 default: abi_string = "Unknown"; break;
12946 case ABI_NONE: abi_string = "NONE"; break;
12947 case ABI_AIX: abi_string = "AIX"; break;
12948 case ABI_DARWIN: abi_string = "Darwin"; break;
12949 case ABI_V4: abi_string = "V.4"; break;
12952 fprintf (stderr, "\tABI = %5s\n", abi_string);
12954 if (TARGET_ALTIVEC_ABI)
12955 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12957 if (TARGET_SPE_ABI)
12958 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12960 if (info->first_gp_reg_save != 32)
12961 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12963 if (info->first_fp_reg_save != 64)
12964 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12966 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12967 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12968 info->first_altivec_reg_save);
12970 if (info->lr_save_p)
12971 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
12973 if (info->cr_save_p)
12974 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12976 if (info->toc_save_p)
12977 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12979 if (info->vrsave_mask)
12980 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12983 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12986 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12988 if (info->gp_save_offset)
12989 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12991 if (info->fp_save_offset)
12992 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12994 if (info->altivec_save_offset)
12995 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12996 info->altivec_save_offset);
12998 if (info->spe_gp_save_offset)
12999 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13000 info->spe_gp_save_offset);
13002 if (info->vrsave_save_offset)
13003 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13004 info->vrsave_save_offset);
13006 if (info->lr_save_offset)
13007 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13009 if (info->cr_save_offset)
13010 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13012 if (info->toc_save_offset)
13013 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
13015 if (info->varargs_save_offset)
13016 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13018 if (info->total_size)
13019 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13022 if (info->varargs_size)
13023 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
13025 if (info->vars_size)
13026 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13029 if (info->parm_size)
13030 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13032 if (info->fixed_size)
13033 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13036 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13038 if (info->spe_gp_size)
13039 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13042 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13044 if (info->altivec_size)
13045 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13047 if (info->vrsave_size)
13048 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13050 if (info->altivec_padding_size)
13051 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13052 info->altivec_padding_size);
13054 if (info->spe_padding_size)
13055 fprintf (stderr, "\tspe_padding_size = %5d\n",
13056 info->spe_padding_size);
13059 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
13062 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13064 if (info->toc_size)
13065 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
13067 if (info->save_size)
13068 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13070 if (info->reg_size != 4)
13071 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13073 fprintf (stderr, "\n");
13077 rs6000_return_addr (int count, rtx frame)
13079 /* Currently we don't optimize very well between prolog and body
13080 code and for PIC code the code can be actually quite bad, so
13081 don't try to be too clever here. */
13082 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13084 cfun->machine->ra_needs_full_frame = 1;
13091 plus_constant (copy_to_reg
13092 (gen_rtx_MEM (Pmode,
13093 memory_address (Pmode, frame))),
13094 RETURN_ADDRESS_OFFSET)));
13097 cfun->machine->ra_need_lr = 1;
13098 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13101 /* Say whether a function is a candidate for sibcall handling or not.
13102 We do not allow indirect calls to be optimized into sibling calls.
13103 Also, we can't do it if there are any vector parameters; there's
13104 nowhere to put the VRsave code so it works; note that functions with
13105 vector parameters are required to have a prototype, so the argument
13106 type info must be available here. (The tail recursion case can work
13107 with vector parameters, but there's no way to distinguish here.) */
13109 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13114 if (TARGET_ALTIVEC_VRSAVE)
13116 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13117 type; type = TREE_CHAIN (type))
13119 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13123 if (DEFAULT_ABI == ABI_DARWIN
13124 || (*targetm.binds_local_p) (decl))
13126 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13128 if (!lookup_attribute ("longcall", attr_list)
13129 || lookup_attribute ("shortcall", attr_list))
13137 rs6000_ra_ever_killed (void)
13143 if (current_function_is_thunk)
13146 /* regs_ever_live has LR marked as used if any sibcalls are present,
13147 but this should not force saving and restoring in the
13148 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13149 clobbers LR, so that is inappropriate. */
13151 /* Also, the prologue can generate a store into LR that
13152 doesn't really count, like this:
13155 bcl to set PIC register
13159 When we're called from the epilogue, we need to avoid counting
13160 this as a store. */
13162 push_topmost_sequence ();
13163 top = get_insns ();
13164 pop_topmost_sequence ();
13165 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13167 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13171 if (FIND_REG_INC_NOTE (insn, reg))
13173 else if (GET_CODE (insn) == CALL_INSN
13174 && !SIBLING_CALL_P (insn))
13176 else if (set_of (reg, insn) != NULL_RTX
13177 && !prologue_epilogue_contains (insn))
13184 /* Add a REG_MAYBE_DEAD note to the insn. */
13186 rs6000_maybe_dead (rtx insn)
13188 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13193 /* Emit instructions needed to load the TOC register.
13194 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13195 a constant pool; or for SVR4 -fpic. */
13198 rs6000_emit_load_toc_table (int fromprolog)
13201 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13203 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13205 rtx temp = (fromprolog
13206 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13207 : gen_reg_rtx (Pmode));
13208 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
13210 rs6000_maybe_dead (insn);
13211 insn = emit_move_insn (dest, temp);
13213 rs6000_maybe_dead (insn);
13215 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13218 rtx tempLR = (fromprolog
13219 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13220 : gen_reg_rtx (Pmode));
13221 rtx temp0 = (fromprolog
13222 ? gen_rtx_REG (Pmode, 0)
13223 : gen_reg_rtx (Pmode));
13226 /* possibly create the toc section */
13227 if (! toc_initialized)
13230 function_section (current_function_decl);
13237 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13238 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13240 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13241 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13243 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13245 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13246 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13253 static int reload_toc_labelno = 0;
13255 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13257 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
13258 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13260 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
13261 emit_move_insn (dest, tempLR);
13262 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13264 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13266 rs6000_maybe_dead (insn);
13268 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13270 /* This is for AIX code running in non-PIC ELF32. */
13273 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13274 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13276 insn = emit_insn (gen_elf_high (dest, realsym));
13278 rs6000_maybe_dead (insn);
13279 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13281 rs6000_maybe_dead (insn);
13283 else if (DEFAULT_ABI == ABI_AIX)
13286 insn = emit_insn (gen_load_toc_aix_si (dest));
13288 insn = emit_insn (gen_load_toc_aix_di (dest));
13290 rs6000_maybe_dead (insn);
13296 /* Emit instructions to restore the link register after determining where
13297 its value has been stored. */
13300 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13302 rs6000_stack_t *info = rs6000_stack_info ();
13305 operands[0] = source;
13306 operands[1] = scratch;
13308 if (info->lr_save_p)
13310 rtx frame_rtx = stack_pointer_rtx;
13311 HOST_WIDE_INT sp_offset = 0;
13314 if (frame_pointer_needed
13315 || current_function_calls_alloca
13316 || info->total_size > 32767)
13318 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13319 frame_rtx = operands[1];
13321 else if (info->push_p)
13322 sp_offset = info->total_size;
13324 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13325 tmp = gen_rtx_MEM (Pmode, tmp);
13326 emit_move_insn (tmp, operands[0]);
13329 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13332 static GTY(()) int set = -1;
13335 get_TOC_alias_set (void)
13338 set = new_alias_set ();
13342 /* This returns nonzero if the current function uses the TOC. This is
13343 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13344 is generated by the ABI_V4 load_toc_* patterns. */
13351 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13354 rtx pat = PATTERN (insn);
13357 if (GET_CODE (pat) == PARALLEL)
13358 for (i = 0; i < XVECLEN (pat, 0); i++)
13360 rtx sub = XVECEXP (pat, 0, i);
13361 if (GET_CODE (sub) == USE)
13363 sub = XEXP (sub, 0);
13364 if (GET_CODE (sub) == UNSPEC
13365 && XINT (sub, 1) == UNSPEC_TOC)
13375 create_TOC_reference (rtx symbol)
13377 return gen_rtx_PLUS (Pmode,
13378 gen_rtx_REG (Pmode, TOC_REGISTER),
13379 gen_rtx_CONST (Pmode,
13380 gen_rtx_MINUS (Pmode, symbol,
13381 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13384 /* If _Unwind_* has been called from within the same module,
13385 toc register is not guaranteed to be saved to 40(1) on function
13386 entry. Save it there in that case. */
13389 rs6000_aix_emit_builtin_unwind_init (void)
13392 rtx stack_top = gen_reg_rtx (Pmode);
13393 rtx opcode_addr = gen_reg_rtx (Pmode);
13394 rtx opcode = gen_reg_rtx (SImode);
13395 rtx tocompare = gen_reg_rtx (SImode);
13396 rtx no_toc_save_needed = gen_label_rtx ();
13398 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
13399 emit_move_insn (stack_top, mem);
13401 mem = gen_rtx_MEM (Pmode,
13402 gen_rtx_PLUS (Pmode, stack_top,
13403 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13404 emit_move_insn (opcode_addr, mem);
13405 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13406 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13407 : 0xE8410028, SImode));
13409 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13410 SImode, NULL_RTX, NULL_RTX,
13411 no_toc_save_needed);
13413 mem = gen_rtx_MEM (Pmode,
13414 gen_rtx_PLUS (Pmode, stack_top,
13415 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13416 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13417 emit_label (no_toc_save_needed);
13420 /* This ties together stack memory (MEM with an alias set of
13421 rs6000_sr_alias_set) and the change to the stack pointer. */
13424 rs6000_emit_stack_tie (void)
13426 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13428 set_mem_alias_set (mem, rs6000_sr_alias_set);
13429 emit_insn (gen_stack_tie (mem));
13432 /* Emit the correct code for allocating stack space, as insns.
13433 If COPY_R12, make sure a copy of the old frame is left in r12.
13434 The generated code may use hard register 0 as a temporary. */
13437 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13440 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13441 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13442 rtx todec = gen_int_mode (-size, Pmode);
13444 if (INTVAL (todec) != -size)
13446 warning("stack frame too large");
13447 emit_insn (gen_trap ());
13451 if (current_function_limit_stack)
13453 if (REG_P (stack_limit_rtx)
13454 && REGNO (stack_limit_rtx) > 1
13455 && REGNO (stack_limit_rtx) <= 31)
13457 emit_insn (TARGET_32BIT
13458 ? gen_addsi3 (tmp_reg,
13461 : gen_adddi3 (tmp_reg,
13465 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13468 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13470 && DEFAULT_ABI == ABI_V4)
13472 rtx toload = gen_rtx_CONST (VOIDmode,
13473 gen_rtx_PLUS (Pmode,
13477 emit_insn (gen_elf_high (tmp_reg, toload));
13478 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13479 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13483 warning ("stack limit expression is not supported");
13486 if (copy_r12 || ! TARGET_UPDATE)
13487 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13493 /* Need a note here so that try_split doesn't get confused. */
13494 if (get_last_insn() == NULL_RTX)
13495 emit_note (NOTE_INSN_DELETED);
13496 insn = emit_move_insn (tmp_reg, todec);
13497 try_split (PATTERN (insn), insn, 0);
13501 insn = emit_insn (TARGET_32BIT
13502 ? gen_movsi_update (stack_reg, stack_reg,
13504 : gen_movdi_di_update (stack_reg, stack_reg,
13505 todec, stack_reg));
13509 insn = emit_insn (TARGET_32BIT
13510 ? gen_addsi3 (stack_reg, stack_reg, todec)
13511 : gen_adddi3 (stack_reg, stack_reg, todec));
13512 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13513 gen_rtx_REG (Pmode, 12));
13516 RTX_FRAME_RELATED_P (insn) = 1;
13518 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13519 gen_rtx_SET (VOIDmode, stack_reg,
13520 gen_rtx_PLUS (Pmode, stack_reg,
13525 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13526 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13527 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13528 deduce these equivalences by itself so it wasn't necessary to hold
13529 its hand so much. */
13532 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13533 rtx reg2, rtx rreg)
13537 /* copy_rtx will not make unique copies of registers, so we need to
13538 ensure we don't have unwanted sharing here. */
13540 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13543 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13545 real = copy_rtx (PATTERN (insn));
13547 if (reg2 != NULL_RTX)
13548 real = replace_rtx (real, reg2, rreg);
13550 real = replace_rtx (real, reg,
13551 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13552 STACK_POINTER_REGNUM),
13555 /* We expect that 'real' is either a SET or a PARALLEL containing
13556 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13557 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13559 if (GET_CODE (real) == SET)
13563 temp = simplify_rtx (SET_SRC (set));
13565 SET_SRC (set) = temp;
13566 temp = simplify_rtx (SET_DEST (set));
13568 SET_DEST (set) = temp;
13569 if (GET_CODE (SET_DEST (set)) == MEM)
13571 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13573 XEXP (SET_DEST (set), 0) = temp;
13576 else if (GET_CODE (real) == PARALLEL)
13579 for (i = 0; i < XVECLEN (real, 0); i++)
13580 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13582 rtx set = XVECEXP (real, 0, i);
13584 temp = simplify_rtx (SET_SRC (set));
13586 SET_SRC (set) = temp;
13587 temp = simplify_rtx (SET_DEST (set));
13589 SET_DEST (set) = temp;
13590 if (GET_CODE (SET_DEST (set)) == MEM)
13592 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13594 XEXP (SET_DEST (set), 0) = temp;
13596 RTX_FRAME_RELATED_P (set) = 1;
13603 real = spe_synthesize_frame_save (real);
13605 RTX_FRAME_RELATED_P (insn) = 1;
13606 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13611 /* Given an SPE frame note, return a PARALLEL of SETs with the
13612 original note, plus a synthetic register save. */
13615 spe_synthesize_frame_save (rtx real)
13617 rtx synth, offset, reg, real2;
13619 if (GET_CODE (real) != SET
13620 || GET_MODE (SET_SRC (real)) != V2SImode)
13623 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13624 frame related note. The parallel contains a set of the register
13625 being saved, and another set to a synthetic register (n+1200).
13626 This is so we can differentiate between 64-bit and 32-bit saves.
13627 Words cannot describe this nastiness. */
13629 if (GET_CODE (SET_DEST (real)) != MEM
13630 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
13631 || GET_CODE (SET_SRC (real)) != REG)
13635 (set (mem (plus (reg x) (const y)))
13638 (set (mem (plus (reg x) (const y+4)))
13642 real2 = copy_rtx (real);
13643 PUT_MODE (SET_DEST (real2), SImode);
13644 reg = SET_SRC (real2);
13645 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13646 synth = copy_rtx (real2);
13648 if (BYTES_BIG_ENDIAN)
13650 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13651 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13654 reg = SET_SRC (synth);
13656 synth = replace_rtx (synth, reg,
13657 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13659 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13660 synth = replace_rtx (synth, offset,
13661 GEN_INT (INTVAL (offset)
13662 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13664 RTX_FRAME_RELATED_P (synth) = 1;
13665 RTX_FRAME_RELATED_P (real2) = 1;
13666 if (BYTES_BIG_ENDIAN)
13667 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13669 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13674 /* Returns an insn that has a vrsave set operation with the
13675 appropriate CLOBBERs. */
13678 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13681 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13682 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13685 = gen_rtx_SET (VOIDmode,
13687 gen_rtx_UNSPEC_VOLATILE (SImode,
13688 gen_rtvec (2, reg, vrsave),
13693 /* We need to clobber the registers in the mask so the scheduler
13694 does not move sets to VRSAVE before sets of AltiVec registers.
13696 However, if the function receives nonlocal gotos, reload will set
13697 all call saved registers live. We will end up with:
13699 (set (reg 999) (mem))
13700 (parallel [ (set (reg vrsave) (unspec blah))
13701 (clobber (reg 999))])
13703 The clobber will cause the store into reg 999 to be dead, and
13704 flow will attempt to delete an epilogue insn. In this case, we
13705 need an unspec use/set of the register. */
13707 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13708 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13710 if (!epiloguep || call_used_regs [i])
13711 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13712 gen_rtx_REG (V4SImode, i));
13715 rtx reg = gen_rtx_REG (V4SImode, i);
13718 = gen_rtx_SET (VOIDmode,
13720 gen_rtx_UNSPEC (V4SImode,
13721 gen_rtvec (1, reg), 27));
13725 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13727 for (i = 0; i < nclobs; ++i)
13728 XVECEXP (insn, 0, i) = clobs[i];
13733 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13734 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13737 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13738 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13740 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13741 rtx replacea, replaceb;
13743 int_rtx = GEN_INT (offset);
13745 /* Some cases that need register indexed addressing. */
13746 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13747 || (TARGET_E500_DOUBLE && mode == DFmode)
13749 && SPE_VECTOR_MODE (mode)
13750 && !SPE_CONST_OFFSET_OK (offset)))
13752 /* Whomever calls us must make sure r11 is available in the
13753 flow path of instructions in the prologue. */
13754 offset_rtx = gen_rtx_REG (Pmode, 11);
13755 emit_move_insn (offset_rtx, int_rtx);
13757 replacea = offset_rtx;
13758 replaceb = int_rtx;
13762 offset_rtx = int_rtx;
13763 replacea = NULL_RTX;
13764 replaceb = NULL_RTX;
13767 reg = gen_rtx_REG (mode, regno);
13768 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13769 mem = gen_rtx_MEM (mode, addr);
13770 set_mem_alias_set (mem, rs6000_sr_alias_set);
13772 insn = emit_move_insn (mem, reg);
13774 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13777 /* Emit an offset memory reference suitable for a frame store, while
13778 converting to a valid addressing mode. */
13781 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13783 rtx int_rtx, offset_rtx;
13785 int_rtx = GEN_INT (offset);
13787 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13788 || (TARGET_E500_DOUBLE && mode == DFmode))
13790 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13791 emit_move_insn (offset_rtx, int_rtx);
13794 offset_rtx = int_rtx;
13796 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13799 #ifndef TARGET_FIX_AND_CONTINUE
13800 #define TARGET_FIX_AND_CONTINUE 0
13803 /* Emit function prologue as insns. */
13806 rs6000_emit_prologue (void)
13808 rs6000_stack_t *info = rs6000_stack_info ();
13809 enum machine_mode reg_mode = Pmode;
13810 int reg_size = TARGET_32BIT ? 4 : 8;
13811 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13812 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13813 rtx frame_reg_rtx = sp_reg_rtx;
13814 rtx cr_save_rtx = NULL_RTX;
13816 int saving_FPRs_inline;
13817 int using_store_multiple;
13818 HOST_WIDE_INT sp_offset = 0;
13820 if (TARGET_FIX_AND_CONTINUE)
13822 /* gdb on darwin arranges to forward a function from the old
13823 address by modifying the first 4 instructions of the function
13824 to branch to the overriding function. This is necessary to
13825 permit function pointers that point to the old function to
13826 actually forward to the new function. */
13827 emit_insn (gen_nop ());
13828 emit_insn (gen_nop ());
13829 emit_insn (gen_nop ());
13830 emit_insn (gen_nop ());
13833 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13835 reg_mode = V2SImode;
13839 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13840 && (!TARGET_SPE_ABI
13841 || info->spe_64bit_regs_used == 0)
13842 && info->first_gp_reg_save < 31);
13843 saving_FPRs_inline = (info->first_fp_reg_save == 64
13844 || FP_SAVE_INLINE (info->first_fp_reg_save)
13845 || current_function_calls_eh_return
13846 || cfun->machine->ra_need_lr);
13848 /* For V.4, update stack before we do any saving and set back pointer. */
13850 && (DEFAULT_ABI == ABI_V4
13851 || current_function_calls_eh_return))
13853 if (info->total_size < 32767)
13854 sp_offset = info->total_size;
13856 frame_reg_rtx = frame_ptr_rtx;
13857 rs6000_emit_allocate_stack (info->total_size,
13858 (frame_reg_rtx != sp_reg_rtx
13859 && (info->cr_save_p
13861 || info->first_fp_reg_save < 64
13862 || info->first_gp_reg_save < 32
13864 if (frame_reg_rtx != sp_reg_rtx)
13865 rs6000_emit_stack_tie ();
13868 /* Handle world saves specially here. */
13869 if (WORLD_SAVE_P (info))
13875 /* save_world expects lr in r0. */
13876 if (info->lr_save_p)
13878 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13879 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13880 RTX_FRAME_RELATED_P (insn) = 1;
13883 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13884 assumptions about the offsets of various bits of the stack
13885 frame. Abort if things aren't what they should be. */
13886 if (info->gp_save_offset != -220
13887 || info->fp_save_offset != -144
13888 || info->lr_save_offset != 8
13889 || info->cr_save_offset != 4
13891 || !info->lr_save_p
13892 || (current_function_calls_eh_return && info->ehrd_offset != -432)
13893 || (info->vrsave_save_offset != -224
13894 || info->altivec_save_offset != (-224 -16 -192)))
13897 treg = gen_rtx_REG (SImode, 11);
13898 emit_move_insn (treg, GEN_INT (-info->total_size));
13900 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13901 in R11. It also clobbers R12, so beware! */
13903 /* Preserve CR2 for save_world prologues */
13905 sz += 32 - info->first_gp_reg_save;
13906 sz += 64 - info->first_fp_reg_save;
13907 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13908 p = rtvec_alloc (sz);
13910 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13911 gen_rtx_REG (Pmode,
13912 LINK_REGISTER_REGNUM));
13913 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13914 gen_rtx_SYMBOL_REF (Pmode,
13916 /* We do floats first so that the instruction pattern matches
13918 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13920 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13921 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13922 GEN_INT (info->fp_save_offset
13923 + sp_offset + 8 * i));
13924 rtx mem = gen_rtx_MEM (DFmode, addr);
13925 set_mem_alias_set (mem, rs6000_sr_alias_set);
13927 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13929 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13931 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13932 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13933 GEN_INT (info->altivec_save_offset
13934 + sp_offset + 16 * i));
13935 rtx mem = gen_rtx_MEM (V4SImode, addr);
13936 set_mem_alias_set (mem, rs6000_sr_alias_set);
13938 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13940 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13942 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13943 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13944 GEN_INT (info->gp_save_offset
13945 + sp_offset + reg_size * i));
13946 rtx mem = gen_rtx_MEM (reg_mode, addr);
13947 set_mem_alias_set (mem, rs6000_sr_alias_set);
13949 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13953 /* CR register traditionally saved as CR2. */
13954 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13955 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13956 GEN_INT (info->cr_save_offset
13958 rtx mem = gen_rtx_MEM (reg_mode, addr);
13959 set_mem_alias_set (mem, rs6000_sr_alias_set);
13961 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13963 /* Prevent any attempt to delete the setting of r0 and treg! */
13964 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13965 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13966 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13968 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13969 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13970 NULL_RTX, NULL_RTX);
13972 if (current_function_calls_eh_return)
13977 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13978 if (regno == INVALID_REGNUM)
13980 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13981 info->ehrd_offset + sp_offset
13982 + reg_size * (int) i,
13988 /* Save AltiVec registers if needed. */
13989 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13993 /* There should be a non inline version of this, for when we
13994 are saving lots of vector registers. */
13995 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13996 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13998 rtx areg, savereg, mem;
14001 offset = info->altivec_save_offset + sp_offset
14002 + 16 * (i - info->first_altivec_reg_save);
14004 savereg = gen_rtx_REG (V4SImode, i);
14006 areg = gen_rtx_REG (Pmode, 0);
14007 emit_move_insn (areg, GEN_INT (offset));
14009 /* AltiVec addressing mode is [reg+reg]. */
14010 mem = gen_rtx_MEM (V4SImode,
14011 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14013 set_mem_alias_set (mem, rs6000_sr_alias_set);
14015 insn = emit_move_insn (mem, savereg);
14017 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14018 areg, GEN_INT (offset));
14022 /* VRSAVE is a bit vector representing which AltiVec registers
14023 are used. The OS uses this to determine which vector
14024 registers to save on a context switch. We need to save
14025 VRSAVE on the stack frame, add whatever AltiVec registers we
14026 used in this function, and do the corresponding magic in the
14029 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14030 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
14032 rtx reg, mem, vrsave;
14035 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14036 as frame_reg_rtx and r11 as the static chain pointer for
14037 nested functions. */
14038 reg = gen_rtx_REG (SImode, 0);
14039 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14041 emit_insn (gen_get_vrsave_internal (reg));
14043 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14046 offset = info->vrsave_save_offset + sp_offset;
14048 = gen_rtx_MEM (SImode,
14049 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
14050 set_mem_alias_set (mem, rs6000_sr_alias_set);
14051 insn = emit_move_insn (mem, reg);
14053 /* Include the registers in the mask. */
14054 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14056 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14059 /* If we use the link register, get it into r0. */
14060 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14062 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14063 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14064 RTX_FRAME_RELATED_P (insn) = 1;
14067 /* If we need to save CR, put it into r12. */
14068 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14072 cr_save_rtx = gen_rtx_REG (SImode, 12);
14073 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14074 RTX_FRAME_RELATED_P (insn) = 1;
14075 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14076 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14077 But that's OK. All we have to do is specify that _one_ condition
14078 code register is saved in this stack slot. The thrower's epilogue
14079 will then restore all the call-saved registers.
14080 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14081 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14082 gen_rtx_REG (SImode, CR2_REGNO));
14083 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14088 /* Do any required saving of fpr's. If only one or two to save, do
14089 it ourselves. Otherwise, call function. */
14090 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14093 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14094 if ((regs_ever_live[info->first_fp_reg_save+i]
14095 && ! call_used_regs[info->first_fp_reg_save+i]))
14096 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14097 info->first_fp_reg_save + i,
14098 info->fp_save_offset + sp_offset + 8 * i,
14101 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14105 const char *alloc_rname;
14107 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14109 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14110 gen_rtx_REG (Pmode,
14111 LINK_REGISTER_REGNUM));
14112 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14113 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14114 alloc_rname = ggc_strdup (rname);
14115 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14116 gen_rtx_SYMBOL_REF (Pmode,
14118 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14120 rtx addr, reg, mem;
14121 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14122 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14123 GEN_INT (info->fp_save_offset
14124 + sp_offset + 8*i));
14125 mem = gen_rtx_MEM (DFmode, addr);
14126 set_mem_alias_set (mem, rs6000_sr_alias_set);
14128 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14130 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14131 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14132 NULL_RTX, NULL_RTX);
14135 /* Save GPRs. This is done as a PARALLEL if we are using
14136 the store-multiple instructions. */
14137 if (!WORLD_SAVE_P (info) && using_store_multiple)
14141 p = rtvec_alloc (32 - info->first_gp_reg_save);
14142 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14144 rtx addr, reg, mem;
14145 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14146 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14147 GEN_INT (info->gp_save_offset
14150 mem = gen_rtx_MEM (reg_mode, addr);
14151 set_mem_alias_set (mem, rs6000_sr_alias_set);
14153 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14155 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14156 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14157 NULL_RTX, NULL_RTX);
14159 else if (!WORLD_SAVE_P (info))
14162 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14163 if ((regs_ever_live[info->first_gp_reg_save+i]
14164 && (! call_used_regs[info->first_gp_reg_save+i]
14165 || (i+info->first_gp_reg_save
14166 == RS6000_PIC_OFFSET_TABLE_REGNUM
14167 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14168 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14169 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14170 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14172 rtx addr, reg, mem;
14173 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14175 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14177 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14180 if (!SPE_CONST_OFFSET_OK (offset))
14182 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14183 emit_move_insn (b, GEN_INT (offset));
14186 b = GEN_INT (offset);
14188 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14189 mem = gen_rtx_MEM (V2SImode, addr);
14190 set_mem_alias_set (mem, rs6000_sr_alias_set);
14191 insn = emit_move_insn (mem, reg);
14193 if (GET_CODE (b) == CONST_INT)
14194 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14195 NULL_RTX, NULL_RTX);
14197 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14198 b, GEN_INT (offset));
14202 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14203 GEN_INT (info->gp_save_offset
14206 mem = gen_rtx_MEM (reg_mode, addr);
14207 set_mem_alias_set (mem, rs6000_sr_alias_set);
14209 insn = emit_move_insn (mem, reg);
14210 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14211 NULL_RTX, NULL_RTX);
14216 /* ??? There's no need to emit actual instructions here, but it's the
14217 easiest way to get the frame unwind information emitted. */
14218 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14220 unsigned int i, regno;
14222 /* In AIX ABI we need to pretend we save r2 here. */
14225 rtx addr, reg, mem;
14227 reg = gen_rtx_REG (reg_mode, 2);
14228 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14229 GEN_INT (sp_offset + 5 * reg_size));
14230 mem = gen_rtx_MEM (reg_mode, addr);
14231 set_mem_alias_set (mem, rs6000_sr_alias_set);
14233 insn = emit_move_insn (mem, reg);
14234 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14235 NULL_RTX, NULL_RTX);
14236 PATTERN (insn) = gen_blockage ();
14241 regno = EH_RETURN_DATA_REGNO (i);
14242 if (regno == INVALID_REGNUM)
14245 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14246 info->ehrd_offset + sp_offset
14247 + reg_size * (int) i,
14252 /* Save lr if we used it. */
14253 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14255 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14256 GEN_INT (info->lr_save_offset + sp_offset));
14257 rtx reg = gen_rtx_REG (Pmode, 0);
14258 rtx mem = gen_rtx_MEM (Pmode, addr);
14259 /* This should not be of rs6000_sr_alias_set, because of
14260 __builtin_return_address. */
14262 insn = emit_move_insn (mem, reg);
14263 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14264 NULL_RTX, NULL_RTX);
14267 /* Save CR if we use any that must be preserved. */
14268 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14270 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14271 GEN_INT (info->cr_save_offset + sp_offset));
14272 rtx mem = gen_rtx_MEM (SImode, addr);
14273 /* See the large comment above about why CR2_REGNO is used. */
14274 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14276 set_mem_alias_set (mem, rs6000_sr_alias_set);
14278 /* If r12 was used to hold the original sp, copy cr into r0 now
14280 if (REGNO (frame_reg_rtx) == 12)
14284 cr_save_rtx = gen_rtx_REG (SImode, 0);
14285 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14286 RTX_FRAME_RELATED_P (insn) = 1;
14287 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14288 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14293 insn = emit_move_insn (mem, cr_save_rtx);
14295 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14296 NULL_RTX, NULL_RTX);
14299 /* Update stack and set back pointer unless this is V.4,
14300 for which it was done previously. */
14301 if (!WORLD_SAVE_P (info) && info->push_p
14302 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14303 rs6000_emit_allocate_stack (info->total_size, FALSE);
14305 /* Set frame pointer, if needed. */
14306 if (frame_pointer_needed)
14308 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
14310 RTX_FRAME_RELATED_P (insn) = 1;
14313 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14314 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14315 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
14316 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14318 /* If emit_load_toc_table will use the link register, we need to save
14319 it. We use R12 for this purpose because emit_load_toc_table
14320 can use register 0. This allows us to use a plain 'blr' to return
14321 from the procedure more often. */
14322 int save_LR_around_toc_setup = (TARGET_ELF
14323 && DEFAULT_ABI != ABI_AIX
14325 && ! info->lr_save_p
14326 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14327 if (save_LR_around_toc_setup)
14329 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14331 insn = emit_move_insn (frame_ptr_rtx, lr);
14332 rs6000_maybe_dead (insn);
14333 RTX_FRAME_RELATED_P (insn) = 1;
14335 rs6000_emit_load_toc_table (TRUE);
14337 insn = emit_move_insn (lr, frame_ptr_rtx);
14338 rs6000_maybe_dead (insn);
14339 RTX_FRAME_RELATED_P (insn) = 1;
14342 rs6000_emit_load_toc_table (TRUE);
14346 if (DEFAULT_ABI == ABI_DARWIN
14347 && flag_pic && current_function_uses_pic_offset_table)
14349 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14350 rtx src = machopic_function_base_sym ();
14352 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14354 insn = emit_move_insn (gen_rtx_REG (Pmode,
14355 RS6000_PIC_OFFSET_TABLE_REGNUM),
14357 rs6000_maybe_dead (insn);
14362 /* Write function prologue. */
14365 rs6000_output_function_prologue (FILE *file,
14366 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14368 rs6000_stack_t *info = rs6000_stack_info ();
14370 if (TARGET_DEBUG_STACK)
14371 debug_stack_info (info);
14373 /* Write .extern for any function we will call to save and restore
14375 if (info->first_fp_reg_save < 64
14376 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14377 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14378 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14379 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14380 RESTORE_FP_SUFFIX);
14382 /* Write .extern for AIX common mode routines, if needed. */
14383 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14385 fputs ("\t.extern __mulh\n", file);
14386 fputs ("\t.extern __mull\n", file);
14387 fputs ("\t.extern __divss\n", file);
14388 fputs ("\t.extern __divus\n", file);
14389 fputs ("\t.extern __quoss\n", file);
14390 fputs ("\t.extern __quous\n", file);
14391 common_mode_defined = 1;
14394 if (! HAVE_prologue)
14398 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14399 the "toplevel" insn chain. */
14400 emit_note (NOTE_INSN_DELETED);
14401 rs6000_emit_prologue ();
14402 emit_note (NOTE_INSN_DELETED);
14404 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14408 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14410 INSN_ADDRESSES_NEW (insn, addr);
14415 if (TARGET_DEBUG_STACK)
14416 debug_rtx_list (get_insns (), 100);
14417 final (get_insns (), file, FALSE, FALSE);
14421 rs6000_pic_labelno++;
14424 /* Emit function epilogue as insns.
14426 At present, dwarf2out_frame_debug_expr doesn't understand
14427 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14428 anywhere in the epilogue. Most of the insns below would in any case
14429 need special notes to explain where r11 is in relation to the stack. */
14432 rs6000_emit_epilogue (int sibcall)
14434 rs6000_stack_t *info;
14435 int restoring_FPRs_inline;
14436 int using_load_multiple;
14437 int using_mfcr_multiple;
14438 int use_backchain_to_restore_sp;
14440 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14441 rtx frame_reg_rtx = sp_reg_rtx;
14442 enum machine_mode reg_mode = Pmode;
14443 int reg_size = TARGET_32BIT ? 4 : 8;
14446 info = rs6000_stack_info ();
14448 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14450 reg_mode = V2SImode;
14454 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14455 && (!TARGET_SPE_ABI
14456 || info->spe_64bit_regs_used == 0)
14457 && info->first_gp_reg_save < 31);
14458 restoring_FPRs_inline = (sibcall
14459 || current_function_calls_eh_return
14460 || info->first_fp_reg_save == 64
14461 || FP_SAVE_INLINE (info->first_fp_reg_save));
14462 use_backchain_to_restore_sp = (frame_pointer_needed
14463 || current_function_calls_alloca
14464 || info->total_size > 32767);
14465 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14466 || rs6000_cpu == PROCESSOR_PPC603
14467 || rs6000_cpu == PROCESSOR_PPC750
14470 if (WORLD_SAVE_P (info))
14474 const char *alloc_rname;
14477 /* eh_rest_world_r10 will return to the location saved in the LR
14478 stack slot (which is not likely to be our caller.)
14479 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14480 rest_world is similar, except any R10 parameter is ignored.
14481 The exception-handling stuff that was here in 2.95 is no
14482 longer necessary. */
14486 + 32 - info->first_gp_reg_save
14487 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14488 + 63 + 1 - info->first_fp_reg_save);
14490 strcpy (rname, ((current_function_calls_eh_return) ?
14491 "*eh_rest_world_r10" : "*rest_world"));
14492 alloc_rname = ggc_strdup (rname);
14495 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14496 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14497 gen_rtx_REG (Pmode,
14498 LINK_REGISTER_REGNUM));
14500 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14501 /* The instruction pattern requires a clobber here;
14502 it is shared with the restVEC helper. */
14504 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14507 /* CR register traditionally saved as CR2. */
14508 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14509 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14510 GEN_INT (info->cr_save_offset));
14511 rtx mem = gen_rtx_MEM (reg_mode, addr);
14512 set_mem_alias_set (mem, rs6000_sr_alias_set);
14514 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14517 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14519 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14520 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14521 GEN_INT (info->gp_save_offset
14523 rtx mem = gen_rtx_MEM (reg_mode, addr);
14524 set_mem_alias_set (mem, rs6000_sr_alias_set);
14526 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14528 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14530 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14531 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14532 GEN_INT (info->altivec_save_offset
14534 rtx mem = gen_rtx_MEM (V4SImode, addr);
14535 set_mem_alias_set (mem, rs6000_sr_alias_set);
14537 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14539 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14541 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14542 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14543 GEN_INT (info->fp_save_offset
14545 rtx mem = gen_rtx_MEM (DFmode, addr);
14546 set_mem_alias_set (mem, rs6000_sr_alias_set);
14548 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14551 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14553 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14555 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14557 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14559 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14560 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14565 /* If we have a frame pointer, a call to alloca, or a large stack
14566 frame, restore the old stack pointer using the backchain. Otherwise,
14567 we know what size to update it with. */
14568 if (use_backchain_to_restore_sp)
14570 /* Under V.4, don't reset the stack pointer until after we're done
14571 loading the saved registers. */
14572 if (DEFAULT_ABI == ABI_V4)
14573 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14575 emit_move_insn (frame_reg_rtx,
14576 gen_rtx_MEM (Pmode, sp_reg_rtx));
14579 else if (info->push_p)
14581 if (DEFAULT_ABI == ABI_V4
14582 || current_function_calls_eh_return)
14583 sp_offset = info->total_size;
14586 emit_insn (TARGET_32BIT
14587 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14588 GEN_INT (info->total_size))
14589 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14590 GEN_INT (info->total_size)));
14594 /* Restore AltiVec registers if needed. */
14595 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14599 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14600 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14602 rtx addr, areg, mem;
14604 areg = gen_rtx_REG (Pmode, 0);
14606 (areg, GEN_INT (info->altivec_save_offset
14608 + 16 * (i - info->first_altivec_reg_save)));
14610 /* AltiVec addressing mode is [reg+reg]. */
14611 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14612 mem = gen_rtx_MEM (V4SImode, addr);
14613 set_mem_alias_set (mem, rs6000_sr_alias_set);
14615 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14619 /* Restore VRSAVE if needed. */
14620 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14621 && info->vrsave_mask != 0)
14623 rtx addr, mem, reg;
14625 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14626 GEN_INT (info->vrsave_save_offset + sp_offset));
14627 mem = gen_rtx_MEM (SImode, addr);
14628 set_mem_alias_set (mem, rs6000_sr_alias_set);
14629 reg = gen_rtx_REG (SImode, 12);
14630 emit_move_insn (reg, mem);
14632 emit_insn (generate_set_vrsave (reg, info, 1));
14635 /* Get the old lr if we saved it. */
14636 if (info->lr_save_p)
14638 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14639 info->lr_save_offset + sp_offset);
14641 set_mem_alias_set (mem, rs6000_sr_alias_set);
14643 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14646 /* Get the old cr if we saved it. */
14647 if (info->cr_save_p)
14649 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14650 GEN_INT (info->cr_save_offset + sp_offset));
14651 rtx mem = gen_rtx_MEM (SImode, addr);
14653 set_mem_alias_set (mem, rs6000_sr_alias_set);
14655 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14658 /* Set LR here to try to overlap restores below. */
14659 if (info->lr_save_p)
14660 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14661 gen_rtx_REG (Pmode, 0));
14663 /* Load exception handler data registers, if needed. */
14664 if (current_function_calls_eh_return)
14666 unsigned int i, regno;
14670 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14671 GEN_INT (sp_offset + 5 * reg_size));
14672 rtx mem = gen_rtx_MEM (reg_mode, addr);
14674 set_mem_alias_set (mem, rs6000_sr_alias_set);
14676 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14683 regno = EH_RETURN_DATA_REGNO (i);
14684 if (regno == INVALID_REGNUM)
14687 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14688 info->ehrd_offset + sp_offset
14689 + reg_size * (int) i);
14690 set_mem_alias_set (mem, rs6000_sr_alias_set);
14692 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14696 /* Restore GPRs. This is done as a PARALLEL if we are using
14697 the load-multiple instructions. */
14698 if (using_load_multiple)
14701 p = rtvec_alloc (32 - info->first_gp_reg_save);
14702 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14704 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14705 GEN_INT (info->gp_save_offset
14708 rtx mem = gen_rtx_MEM (reg_mode, addr);
14710 set_mem_alias_set (mem, rs6000_sr_alias_set);
14713 gen_rtx_SET (VOIDmode,
14714 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14717 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14720 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14721 if ((regs_ever_live[info->first_gp_reg_save+i]
14722 && (! call_used_regs[info->first_gp_reg_save+i]
14723 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14724 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14725 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14726 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14727 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14729 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14730 GEN_INT (info->gp_save_offset
14733 rtx mem = gen_rtx_MEM (reg_mode, addr);
14735 /* Restore 64-bit quantities for SPE. */
14736 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14738 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14741 if (!SPE_CONST_OFFSET_OK (offset))
14743 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14744 emit_move_insn (b, GEN_INT (offset));
14747 b = GEN_INT (offset);
14749 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14750 mem = gen_rtx_MEM (V2SImode, addr);
14753 set_mem_alias_set (mem, rs6000_sr_alias_set);
14755 emit_move_insn (gen_rtx_REG (reg_mode,
14756 info->first_gp_reg_save + i), mem);
14759 /* Restore fpr's if we need to do it without calling a function. */
14760 if (restoring_FPRs_inline)
14761 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14762 if ((regs_ever_live[info->first_fp_reg_save+i]
14763 && ! call_used_regs[info->first_fp_reg_save+i]))
14766 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14767 GEN_INT (info->fp_save_offset
14770 mem = gen_rtx_MEM (DFmode, addr);
14771 set_mem_alias_set (mem, rs6000_sr_alias_set);
14773 emit_move_insn (gen_rtx_REG (DFmode,
14774 info->first_fp_reg_save + i),
14778 /* If we saved cr, restore it here. Just those that were used. */
14779 if (info->cr_save_p)
14781 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14784 if (using_mfcr_multiple)
14786 for (i = 0; i < 8; i++)
14787 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14793 if (using_mfcr_multiple && count > 1)
14798 p = rtvec_alloc (count);
14801 for (i = 0; i < 8; i++)
14802 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14804 rtvec r = rtvec_alloc (2);
14805 RTVEC_ELT (r, 0) = r12_rtx;
14806 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14807 RTVEC_ELT (p, ndx) =
14808 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14809 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14812 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14817 for (i = 0; i < 8; i++)
14818 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14820 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14826 /* If this is V.4, unwind the stack pointer after all of the loads
14827 have been done. We need to emit a block here so that sched
14828 doesn't decide to move the sp change before the register restores
14829 (which may not have any obvious dependency on the stack). This
14830 doesn't hurt performance, because there is no scheduling that can
14831 be done after this point. */
14832 if (DEFAULT_ABI == ABI_V4
14833 || current_function_calls_eh_return)
14835 if (frame_reg_rtx != sp_reg_rtx)
14836 rs6000_emit_stack_tie ();
14838 if (use_backchain_to_restore_sp)
14840 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14842 else if (sp_offset != 0)
14844 emit_insn (TARGET_32BIT
14845 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14846 GEN_INT (sp_offset))
14847 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14848 GEN_INT (sp_offset)));
14852 if (current_function_calls_eh_return)
14854 rtx sa = EH_RETURN_STACKADJ_RTX;
14855 emit_insn (TARGET_32BIT
14856 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14857 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14863 if (! restoring_FPRs_inline)
14864 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14866 p = rtvec_alloc (2);
14868 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14869 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14870 gen_rtx_REG (Pmode,
14871 LINK_REGISTER_REGNUM));
14873 /* If we have to restore more than two FP registers, branch to the
14874 restore function. It will return to our caller. */
14875 if (! restoring_FPRs_inline)
14879 const char *alloc_rname;
14881 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14882 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14883 alloc_rname = ggc_strdup (rname);
14884 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14885 gen_rtx_SYMBOL_REF (Pmode,
14888 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14891 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14892 GEN_INT (info->fp_save_offset + 8*i));
14893 mem = gen_rtx_MEM (DFmode, addr);
14894 set_mem_alias_set (mem, rs6000_sr_alias_set);
14896 RTVEC_ELT (p, i+3) =
14897 gen_rtx_SET (VOIDmode,
14898 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14903 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14907 /* Write function epilogue. */
14910 rs6000_output_function_epilogue (FILE *file,
14911 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14913 rs6000_stack_t *info = rs6000_stack_info ();
14915 if (! HAVE_epilogue)
14917 rtx insn = get_last_insn ();
14918 /* If the last insn was a BARRIER, we don't have to write anything except
14919 the trace table. */
14920 if (GET_CODE (insn) == NOTE)
14921 insn = prev_nonnote_insn (insn);
14922 if (insn == 0 || GET_CODE (insn) != BARRIER)
14924 /* This is slightly ugly, but at least we don't have two
14925 copies of the epilogue-emitting code. */
14928 /* A NOTE_INSN_DELETED is supposed to be at the start
14929 and end of the "toplevel" insn chain. */
14930 emit_note (NOTE_INSN_DELETED);
14931 rs6000_emit_epilogue (FALSE);
14932 emit_note (NOTE_INSN_DELETED);
14934 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14938 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14940 INSN_ADDRESSES_NEW (insn, addr);
14945 if (TARGET_DEBUG_STACK)
14946 debug_rtx_list (get_insns (), 100);
14947 final (get_insns (), file, FALSE, FALSE);
14953 macho_branch_islands ();
14954 /* Mach-O doesn't support labels at the end of objects, so if
14955 it looks like we might want one, insert a NOP. */
14957 rtx insn = get_last_insn ();
14960 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14961 insn = PREV_INSN (insn);
14965 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14966 fputs ("\tnop\n", file);
14970 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14973 We don't output a traceback table if -finhibit-size-directive was
14974 used. The documentation for -finhibit-size-directive reads
14975 ``don't output a @code{.size} assembler directive, or anything
14976 else that would cause trouble if the function is split in the
14977 middle, and the two halves are placed at locations far apart in
14978 memory.'' The traceback table has this property, since it
14979 includes the offset from the start of the function to the
14980 traceback table itself.
14982 System V.4 Powerpc's (and the embedded ABI derived from it) use a
14983 different traceback table. */
14984 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14985 && rs6000_traceback != traceback_none)
14987 const char *fname = NULL;
14988 const char *language_string = lang_hooks.name;
14989 int fixed_parms = 0, float_parms = 0, parm_info = 0;
14991 int optional_tbtab;
14993 if (rs6000_traceback == traceback_full)
14994 optional_tbtab = 1;
14995 else if (rs6000_traceback == traceback_part)
14996 optional_tbtab = 0;
14998 optional_tbtab = !optimize_size && !TARGET_ELF;
15000 if (optional_tbtab)
15002 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15003 while (*fname == '.') /* V.4 encodes . in the name */
15006 /* Need label immediately before tbtab, so we can compute
15007 its offset from the function start. */
15008 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15009 ASM_OUTPUT_LABEL (file, fname);
15012 /* The .tbtab pseudo-op can only be used for the first eight
15013 expressions, since it can't handle the possibly variable
15014 length fields that follow. However, if you omit the optional
15015 fields, the assembler outputs zeros for all optional fields
15016 anyways, giving each variable length field is minimum length
15017 (as defined in sys/debug.h). Thus we can not use the .tbtab
15018 pseudo-op at all. */
15020 /* An all-zero word flags the start of the tbtab, for debuggers
15021 that have to find it by searching forward from the entry
15022 point or from the current pc. */
15023 fputs ("\t.long 0\n", file);
15025 /* Tbtab format type. Use format type 0. */
15026 fputs ("\t.byte 0,", file);
15028 /* Language type. Unfortunately, there does not seem to be any
15029 official way to discover the language being compiled, so we
15030 use language_string.
15031 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15032 Java is 13. Objective-C is 14. */
15033 if (! strcmp (language_string, "GNU C"))
15035 else if (! strcmp (language_string, "GNU F77")
15036 || ! strcmp (language_string, "GNU F95"))
15038 else if (! strcmp (language_string, "GNU Pascal"))
15040 else if (! strcmp (language_string, "GNU Ada"))
15042 else if (! strcmp (language_string, "GNU C++"))
15044 else if (! strcmp (language_string, "GNU Java"))
15046 else if (! strcmp (language_string, "GNU Objective-C"))
15050 fprintf (file, "%d,", i);
15052 /* 8 single bit fields: global linkage (not set for C extern linkage,
15053 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15054 from start of procedure stored in tbtab, internal function, function
15055 has controlled storage, function has no toc, function uses fp,
15056 function logs/aborts fp operations. */
15057 /* Assume that fp operations are used if any fp reg must be saved. */
15058 fprintf (file, "%d,",
15059 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15061 /* 6 bitfields: function is interrupt handler, name present in
15062 proc table, function calls alloca, on condition directives
15063 (controls stack walks, 3 bits), saves condition reg, saves
15065 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15066 set up as a frame pointer, even when there is no alloca call. */
15067 fprintf (file, "%d,",
15068 ((optional_tbtab << 6)
15069 | ((optional_tbtab & frame_pointer_needed) << 5)
15070 | (info->cr_save_p << 1)
15071 | (info->lr_save_p)));
15073 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15075 fprintf (file, "%d,",
15076 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15078 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15079 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15081 if (optional_tbtab)
15083 /* Compute the parameter info from the function decl argument
15086 int next_parm_info_bit = 31;
15088 for (decl = DECL_ARGUMENTS (current_function_decl);
15089 decl; decl = TREE_CHAIN (decl))
15091 rtx parameter = DECL_INCOMING_RTL (decl);
15092 enum machine_mode mode = GET_MODE (parameter);
15094 if (GET_CODE (parameter) == REG)
15096 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
15102 if (mode == SFmode)
15104 else if (mode == DFmode || mode == TFmode)
15109 /* If only one bit will fit, don't or in this entry. */
15110 if (next_parm_info_bit > 0)
15111 parm_info |= (bits << (next_parm_info_bit - 1));
15112 next_parm_info_bit -= 2;
15116 fixed_parms += ((GET_MODE_SIZE (mode)
15117 + (UNITS_PER_WORD - 1))
15119 next_parm_info_bit -= 1;
15125 /* Number of fixed point parameters. */
15126 /* This is actually the number of words of fixed point parameters; thus
15127 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15128 fprintf (file, "%d,", fixed_parms);
15130 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15132 /* This is actually the number of fp registers that hold parameters;
15133 and thus the maximum value is 13. */
15134 /* Set parameters on stack bit if parameters are not in their original
15135 registers, regardless of whether they are on the stack? Xlc
15136 seems to set the bit when not optimizing. */
15137 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15139 if (! optional_tbtab)
15142 /* Optional fields follow. Some are variable length. */
15144 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15145 11 double float. */
15146 /* There is an entry for each parameter in a register, in the order that
15147 they occur in the parameter list. Any intervening arguments on the
15148 stack are ignored. If the list overflows a long (max possible length
15149 34 bits) then completely leave off all elements that don't fit. */
15150 /* Only emit this long if there was at least one parameter. */
15151 if (fixed_parms || float_parms)
15152 fprintf (file, "\t.long %d\n", parm_info);
15154 /* Offset from start of code to tb table. */
15155 fputs ("\t.long ", file);
15156 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15158 RS6000_OUTPUT_BASENAME (file, fname);
15160 assemble_name (file, fname);
15162 rs6000_output_function_entry (file, fname);
15165 /* Interrupt handler mask. */
15166 /* Omit this long, since we never set the interrupt handler bit
15169 /* Number of CTL (controlled storage) anchors. */
15170 /* Omit this long, since the has_ctl bit is never set above. */
15172 /* Displacement into stack of each CTL anchor. */
15173 /* Omit this list of longs, because there are no CTL anchors. */
15175 /* Length of function name. */
15178 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15180 /* Function name. */
15181 assemble_string (fname, strlen (fname));
15183 /* Register for alloca automatic storage; this is always reg 31.
15184 Only emit this if the alloca bit was set above. */
15185 if (frame_pointer_needed)
15186 fputs ("\t.byte 31\n", file);
15188 fputs ("\t.align 2\n", file);
15192 /* A C compound statement that outputs the assembler code for a thunk
15193 function, used to implement C++ virtual function calls with
15194 multiple inheritance. The thunk acts as a wrapper around a virtual
15195 function, adjusting the implicit object parameter before handing
15196 control off to the real function.
15198 First, emit code to add the integer DELTA to the location that
15199 contains the incoming first argument. Assume that this argument
15200 contains a pointer, and is the one used to pass the `this' pointer
15201 in C++. This is the incoming argument *before* the function
15202 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15203 values of all other incoming arguments.
15205 After the addition, emit code to jump to FUNCTION, which is a
15206 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15207 not touch the return address. Hence returning from FUNCTION will
15208 return to whoever called the current `thunk'.
15210 The effect must be as if FUNCTION had been called directly with the
15211 adjusted first argument. This macro is responsible for emitting
15212 all of the code for a thunk function; output_function_prologue()
15213 and output_function_epilogue() are not invoked.
15215 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15216 been extracted from it.) It might possibly be useful on some
15217 targets, but probably not.
15219 If you do not define this macro, the target-independent code in the
15220 C++ frontend will generate a less efficient heavyweight thunk that
15221 calls FUNCTION instead of jumping to it. The generic approach does
15222 not support varargs. */
15225 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15226 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15229 rtx this, insn, funexp;
15231 reload_completed = 1;
15232 epilogue_completed = 1;
15233 no_new_pseudos = 1;
15234 reset_block_changes ();
15236 /* Mark the end of the (empty) prologue. */
15237 emit_note (NOTE_INSN_PROLOGUE_END);
15239 /* Find the "this" pointer. If the function returns a structure,
15240 the structure return pointer is in r3. */
15241 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15242 this = gen_rtx_REG (Pmode, 4);
15244 this = gen_rtx_REG (Pmode, 3);
15246 /* Apply the constant offset, if required. */
15249 rtx delta_rtx = GEN_INT (delta);
15250 emit_insn (TARGET_32BIT
15251 ? gen_addsi3 (this, this, delta_rtx)
15252 : gen_adddi3 (this, this, delta_rtx));
15255 /* Apply the offset from the vtable, if required. */
15258 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15259 rtx tmp = gen_rtx_REG (Pmode, 12);
15261 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15262 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15264 emit_insn (TARGET_32BIT
15265 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15266 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15267 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15271 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15273 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15275 emit_insn (TARGET_32BIT
15276 ? gen_addsi3 (this, this, tmp)
15277 : gen_adddi3 (this, this, tmp));
15280 /* Generate a tail call to the target function. */
15281 if (!TREE_USED (function))
15283 assemble_external (function);
15284 TREE_USED (function) = 1;
15286 funexp = XEXP (DECL_RTL (function), 0);
15287 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15290 if (MACHOPIC_INDIRECT)
15291 funexp = machopic_indirect_call_target (funexp);
15294 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15295 generate sibcall RTL explicitly to avoid constraint abort. */
15296 insn = emit_call_insn (
15297 gen_rtx_PARALLEL (VOIDmode,
15299 gen_rtx_CALL (VOIDmode,
15300 funexp, const0_rtx),
15301 gen_rtx_USE (VOIDmode, const0_rtx),
15302 gen_rtx_USE (VOIDmode,
15303 gen_rtx_REG (SImode,
15304 LINK_REGISTER_REGNUM)),
15305 gen_rtx_RETURN (VOIDmode))));
15306 SIBLING_CALL_P (insn) = 1;
15309 /* Run just enough of rest_of_compilation to get the insns emitted.
15310 There's not really enough bulk here to make other passes such as
15311 instruction scheduling worth while. Note that use_thunk calls
15312 assemble_start_function and assemble_end_function. */
15313 insn = get_insns ();
15314 insn_locators_initialize ();
15315 shorten_branches (insn);
15316 final_start_function (insn, file, 1);
15317 final (insn, file, 1, 0);
15318 final_end_function ();
15320 reload_completed = 0;
15321 epilogue_completed = 0;
15322 no_new_pseudos = 0;
15325 /* A quick summary of the various types of 'constant-pool tables'
15328 Target Flags Name One table per
15329 AIX (none) AIX TOC object file
15330 AIX -mfull-toc AIX TOC object file
15331 AIX -mminimal-toc AIX minimal TOC translation unit
15332 SVR4/EABI (none) SVR4 SDATA object file
15333 SVR4/EABI -fpic SVR4 pic object file
15334 SVR4/EABI -fPIC SVR4 PIC translation unit
15335 SVR4/EABI -mrelocatable EABI TOC function
15336 SVR4/EABI -maix AIX TOC object file
15337 SVR4/EABI -maix -mminimal-toc
15338 AIX minimal TOC translation unit
15340 Name Reg. Set by entries contains:
15341 made by addrs? fp? sum?
15343 AIX TOC 2 crt0 as Y option option
15344 AIX minimal TOC 30 prolog gcc Y Y option
15345 SVR4 SDATA 13 crt0 gcc N Y N
15346 SVR4 pic 30 prolog ld Y not yet N
15347 SVR4 PIC 30 prolog gcc Y option option
15348 EABI TOC 30 prolog gcc Y option option
15352 /* Hash functions for the hash table. */
15355 rs6000_hash_constant (rtx k)
15357 enum rtx_code code = GET_CODE (k);
15358 enum machine_mode mode = GET_MODE (k);
15359 unsigned result = (code << 3) ^ mode;
15360 const char *format;
15363 format = GET_RTX_FORMAT (code);
15364 flen = strlen (format);
15370 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15373 if (mode != VOIDmode)
15374 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15386 for (; fidx < flen; fidx++)
15387 switch (format[fidx])
15392 const char *str = XSTR (k, fidx);
15393 len = strlen (str);
15394 result = result * 613 + len;
15395 for (i = 0; i < len; i++)
15396 result = result * 613 + (unsigned) str[i];
15401 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15405 result = result * 613 + (unsigned) XINT (k, fidx);
15408 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15409 result = result * 613 + (unsigned) XWINT (k, fidx);
15413 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
15414 result = result * 613 + (unsigned) (XWINT (k, fidx)
15428 toc_hash_function (const void *hash_entry)
15430 const struct toc_hash_struct *thc =
15431 (const struct toc_hash_struct *) hash_entry;
15432 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15435 /* Compare H1 and H2 for equivalence. */
15438 toc_hash_eq (const void *h1, const void *h2)
15440 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15441 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15443 if (((const struct toc_hash_struct *) h1)->key_mode
15444 != ((const struct toc_hash_struct *) h2)->key_mode)
15447 return rtx_equal_p (r1, r2);
15450 /* These are the names given by the C++ front-end to vtables, and
15451 vtable-like objects. Ideally, this logic should not be here;
15452 instead, there should be some programmatic way of inquiring as
15453 to whether or not an object is a vtable. */
15455 #define VTABLE_NAME_P(NAME) \
15456 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15457 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15458 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15459 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15460 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15463 rs6000_output_symbol_ref (FILE *file, rtx x)
15465 /* Currently C++ toc references to vtables can be emitted before it
15466 is decided whether the vtable is public or private. If this is
15467 the case, then the linker will eventually complain that there is
15468 a reference to an unknown section. Thus, for vtables only,
15469 we emit the TOC reference to reference the symbol and not the
15471 const char *name = XSTR (x, 0);
15473 if (VTABLE_NAME_P (name))
15475 RS6000_OUTPUT_BASENAME (file, name);
15478 assemble_name (file, name);
15481 /* Output a TOC entry. We derive the entry name from what is being
15485 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15488 const char *name = buf;
15489 const char *real_name;
15496 /* When the linker won't eliminate them, don't output duplicate
15497 TOC entries (this happens on AIX if there is any kind of TOC,
15498 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15500 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15502 struct toc_hash_struct *h;
15505 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15506 time because GGC is not initialized at that point. */
15507 if (toc_hash_table == NULL)
15508 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15509 toc_hash_eq, NULL);
15511 h = ggc_alloc (sizeof (*h));
15513 h->key_mode = mode;
15514 h->labelno = labelno;
15516 found = htab_find_slot (toc_hash_table, h, 1);
15517 if (*found == NULL)
15519 else /* This is indeed a duplicate.
15520 Set this label equal to that label. */
15522 fputs ("\t.set ", file);
15523 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15524 fprintf (file, "%d,", labelno);
15525 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15526 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15532 /* If we're going to put a double constant in the TOC, make sure it's
15533 aligned properly when strict alignment is on. */
15534 if (GET_CODE (x) == CONST_DOUBLE
15535 && STRICT_ALIGNMENT
15536 && GET_MODE_BITSIZE (mode) >= 64
15537 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15538 ASM_OUTPUT_ALIGN (file, 3);
15541 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15543 /* Handle FP constants specially. Note that if we have a minimal
15544 TOC, things we put here aren't actually in the TOC, so we can allow
15546 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15548 REAL_VALUE_TYPE rv;
15551 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15552 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15556 if (TARGET_MINIMAL_TOC)
15557 fputs (DOUBLE_INT_ASM_OP, file);
15559 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15560 k[0] & 0xffffffff, k[1] & 0xffffffff,
15561 k[2] & 0xffffffff, k[3] & 0xffffffff);
15562 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15563 k[0] & 0xffffffff, k[1] & 0xffffffff,
15564 k[2] & 0xffffffff, k[3] & 0xffffffff);
15569 if (TARGET_MINIMAL_TOC)
15570 fputs ("\t.long ", file);
15572 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15573 k[0] & 0xffffffff, k[1] & 0xffffffff,
15574 k[2] & 0xffffffff, k[3] & 0xffffffff);
15575 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15576 k[0] & 0xffffffff, k[1] & 0xffffffff,
15577 k[2] & 0xffffffff, k[3] & 0xffffffff);
15581 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15583 REAL_VALUE_TYPE rv;
15586 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15587 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15591 if (TARGET_MINIMAL_TOC)
15592 fputs (DOUBLE_INT_ASM_OP, file);
15594 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15595 k[0] & 0xffffffff, k[1] & 0xffffffff);
15596 fprintf (file, "0x%lx%08lx\n",
15597 k[0] & 0xffffffff, k[1] & 0xffffffff);
15602 if (TARGET_MINIMAL_TOC)
15603 fputs ("\t.long ", file);
15605 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15606 k[0] & 0xffffffff, k[1] & 0xffffffff);
15607 fprintf (file, "0x%lx,0x%lx\n",
15608 k[0] & 0xffffffff, k[1] & 0xffffffff);
15612 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15614 REAL_VALUE_TYPE rv;
15617 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15618 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15622 if (TARGET_MINIMAL_TOC)
15623 fputs (DOUBLE_INT_ASM_OP, file);
15625 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15626 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15631 if (TARGET_MINIMAL_TOC)
15632 fputs ("\t.long ", file);
15634 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15635 fprintf (file, "0x%lx\n", l & 0xffffffff);
15639 else if (GET_MODE (x) == VOIDmode
15640 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15642 unsigned HOST_WIDE_INT low;
15643 HOST_WIDE_INT high;
15645 if (GET_CODE (x) == CONST_DOUBLE)
15647 low = CONST_DOUBLE_LOW (x);
15648 high = CONST_DOUBLE_HIGH (x);
15651 #if HOST_BITS_PER_WIDE_INT == 32
15654 high = (low & 0x80000000) ? ~0 : 0;
15658 low = INTVAL (x) & 0xffffffff;
15659 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15663 /* TOC entries are always Pmode-sized, but since this
15664 is a bigendian machine then if we're putting smaller
15665 integer constants in the TOC we have to pad them.
15666 (This is still a win over putting the constants in
15667 a separate constant pool, because then we'd have
15668 to have both a TOC entry _and_ the actual constant.)
15670 For a 32-bit target, CONST_INT values are loaded and shifted
15671 entirely within `low' and can be stored in one TOC entry. */
15673 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
15674 abort ();/* It would be easy to make this work, but it doesn't now. */
15676 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15678 #if HOST_BITS_PER_WIDE_INT == 32
15679 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15680 POINTER_SIZE, &low, &high, 0);
15683 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15684 high = (HOST_WIDE_INT) low >> 32;
15691 if (TARGET_MINIMAL_TOC)
15692 fputs (DOUBLE_INT_ASM_OP, file);
15694 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15695 (long) high & 0xffffffff, (long) low & 0xffffffff);
15696 fprintf (file, "0x%lx%08lx\n",
15697 (long) high & 0xffffffff, (long) low & 0xffffffff);
15702 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15704 if (TARGET_MINIMAL_TOC)
15705 fputs ("\t.long ", file);
15707 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15708 (long) high & 0xffffffff, (long) low & 0xffffffff);
15709 fprintf (file, "0x%lx,0x%lx\n",
15710 (long) high & 0xffffffff, (long) low & 0xffffffff);
15714 if (TARGET_MINIMAL_TOC)
15715 fputs ("\t.long ", file);
15717 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15718 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15724 if (GET_CODE (x) == CONST)
15726 if (GET_CODE (XEXP (x, 0)) != PLUS)
15729 base = XEXP (XEXP (x, 0), 0);
15730 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15733 if (GET_CODE (base) == SYMBOL_REF)
15734 name = XSTR (base, 0);
15735 else if (GET_CODE (base) == LABEL_REF)
15736 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
15737 else if (GET_CODE (base) == CODE_LABEL)
15738 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15742 real_name = (*targetm.strip_name_encoding) (name);
15743 if (TARGET_MINIMAL_TOC)
15744 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15747 fprintf (file, "\t.tc %s", real_name);
15750 fprintf (file, ".N%d", - offset);
15752 fprintf (file, ".P%d", offset);
15754 fputs ("[TC],", file);
15757 /* Currently C++ toc references to vtables can be emitted before it
15758 is decided whether the vtable is public or private. If this is
15759 the case, then the linker will eventually complain that there is
15760 a TOC reference to an unknown section. Thus, for vtables only,
15761 we emit the TOC reference to reference the symbol and not the
15763 if (VTABLE_NAME_P (name))
15765 RS6000_OUTPUT_BASENAME (file, name);
15767 fprintf (file, "%d", offset);
15768 else if (offset > 0)
15769 fprintf (file, "+%d", offset);
15772 output_addr_const (file, x);
15776 /* Output an assembler pseudo-op to write an ASCII string of N characters
15777 starting at P to FILE.
15779 On the RS/6000, we have to do this using the .byte operation and
15780 write out special characters outside the quoted string.
15781 Also, the assembler is broken; very long strings are truncated,
15782 so we must artificially break them up early. */
15785 output_ascii (FILE *file, const char *p, int n)
15788 int i, count_string;
15789 const char *for_string = "\t.byte \"";
15790 const char *for_decimal = "\t.byte ";
15791 const char *to_close = NULL;
15794 for (i = 0; i < n; i++)
15797 if (c >= ' ' && c < 0177)
15800 fputs (for_string, file);
15803 /* Write two quotes to get one. */
15811 for_decimal = "\"\n\t.byte ";
15815 if (count_string >= 512)
15817 fputs (to_close, file);
15819 for_string = "\t.byte \"";
15820 for_decimal = "\t.byte ";
15828 fputs (for_decimal, file);
15829 fprintf (file, "%d", c);
15831 for_string = "\n\t.byte \"";
15832 for_decimal = ", ";
15838 /* Now close the string if we have written one. Then end the line. */
15840 fputs (to_close, file);
15843 /* Generate a unique section name for FILENAME for a section type
15844 represented by SECTION_DESC. Output goes into BUF.
15846 SECTION_DESC can be any string, as long as it is different for each
15847 possible section type.
15849 We name the section in the same manner as xlc. The name begins with an
15850 underscore followed by the filename (after stripping any leading directory
15851 names) with the last period replaced by the string SECTION_DESC. If
15852 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15856 rs6000_gen_section_name (char **buf, const char *filename,
15857 const char *section_desc)
15859 const char *q, *after_last_slash, *last_period = 0;
15863 after_last_slash = filename;
15864 for (q = filename; *q; q++)
15867 after_last_slash = q + 1;
15868 else if (*q == '.')
15872 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15873 *buf = (char *) xmalloc (len);
15878 for (q = after_last_slash; *q; q++)
15880 if (q == last_period)
15882 strcpy (p, section_desc);
15883 p += strlen (section_desc);
15887 else if (ISALNUM (*q))
15891 if (last_period == 0)
15892 strcpy (p, section_desc);
15897 /* Emit profile function. */
15900 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
15902 if (TARGET_PROFILE_KERNEL)
15905 if (DEFAULT_ABI == ABI_AIX)
15907 #ifndef NO_PROFILE_COUNTERS
15908 # define NO_PROFILE_COUNTERS 0
15910 if (NO_PROFILE_COUNTERS)
15911 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15915 const char *label_name;
15918 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15919 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15920 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15922 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15926 else if (DEFAULT_ABI == ABI_DARWIN)
15928 const char *mcount_name = RS6000_MCOUNT;
15929 int caller_addr_regno = LINK_REGISTER_REGNUM;
15931 /* Be conservative and always set this, at least for now. */
15932 current_function_uses_pic_offset_table = 1;
15935 /* For PIC code, set up a stub and collect the caller's address
15936 from r0, which is where the prologue puts it. */
15937 if (MACHOPIC_INDIRECT
15938 && current_function_uses_pic_offset_table)
15939 caller_addr_regno = 0;
15941 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15943 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15947 /* Write function profiler code. */
15950 output_function_profiler (FILE *file, int labelno)
15955 switch (DEFAULT_ABI)
15964 warning ("no profiling of 64-bit code for this ABI");
15967 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15968 fprintf (file, "\tmflr %s\n", reg_names[0]);
15971 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
15972 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15973 reg_names[0], save_lr, reg_names[1]);
15974 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15975 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
15976 assemble_name (file, buf);
15977 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
15979 else if (flag_pic > 1)
15981 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15982 reg_names[0], save_lr, reg_names[1]);
15983 /* Now, we need to get the address of the label. */
15984 fputs ("\tbl 1f\n\t.long ", file);
15985 assemble_name (file, buf);
15986 fputs ("-.\n1:", file);
15987 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
15988 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
15989 reg_names[0], reg_names[11]);
15990 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15991 reg_names[0], reg_names[0], reg_names[11]);
15995 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
15996 assemble_name (file, buf);
15997 fputs ("@ha\n", file);
15998 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15999 reg_names[0], save_lr, reg_names[1]);
16000 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16001 assemble_name (file, buf);
16002 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16005 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16006 fprintf (file, "\tbl %s%s\n",
16007 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16012 if (!TARGET_PROFILE_KERNEL)
16014 /* Don't do anything, done in output_profile_hook (). */
16021 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16022 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16024 if (cfun->static_chain_decl != NULL)
16026 asm_fprintf (file, "\tstd %s,24(%s)\n",
16027 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16028 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16029 asm_fprintf (file, "\tld %s,24(%s)\n",
16030 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16033 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16040 /* Power4 load update and store update instructions are cracked into a
16041 load or store and an integer insn which are executed in the same cycle.
16042 Branches have their own dispatch slot which does not count against the
16043 GCC issue rate, but it changes the program flow so there are no other
16044 instructions to issue in this cycle. */
16047 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16048 int verbose ATTRIBUTE_UNUSED,
16049 rtx insn, int more)
16051 if (GET_CODE (PATTERN (insn)) == USE
16052 || GET_CODE (PATTERN (insn)) == CLOBBER)
16055 if (rs6000_sched_groups)
16057 if (is_microcoded_insn (insn))
16059 else if (is_cracked_insn (insn))
16060 return more > 2 ? more - 2 : 0;
16066 /* Adjust the cost of a scheduling dependency. Return the new cost of
16067 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16070 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16072 if (! recog_memoized (insn))
16075 if (REG_NOTE_KIND (link) != 0)
16078 if (REG_NOTE_KIND (link) == 0)
16080 /* Data dependency; DEP_INSN writes a register that INSN reads
16081 some cycles later. */
16083 /* Separate a load from a narrower, dependent store. */
16084 if (rs6000_sched_groups
16085 && GET_CODE (PATTERN (insn)) == SET
16086 && GET_CODE (PATTERN (dep_insn)) == SET
16087 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16088 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16089 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16090 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16093 switch (get_attr_type (insn))
16096 /* Tell the first scheduling pass about the latency between
16097 a mtctr and bctr (and mtlr and br/blr). The first
16098 scheduling pass will not know about this latency since
16099 the mtctr instruction, which has the latency associated
16100 to it, will be generated by reload. */
16101 return TARGET_POWER ? 5 : 4;
16103 /* Leave some extra cycles between a compare and its
16104 dependent branch, to inhibit expensive mispredicts. */
16105 if ((rs6000_cpu_attr == CPU_PPC603
16106 || rs6000_cpu_attr == CPU_PPC604
16107 || rs6000_cpu_attr == CPU_PPC604E
16108 || rs6000_cpu_attr == CPU_PPC620
16109 || rs6000_cpu_attr == CPU_PPC630
16110 || rs6000_cpu_attr == CPU_PPC750
16111 || rs6000_cpu_attr == CPU_PPC7400
16112 || rs6000_cpu_attr == CPU_PPC7450
16113 || rs6000_cpu_attr == CPU_POWER4
16114 || rs6000_cpu_attr == CPU_POWER5)
16115 && recog_memoized (dep_insn)
16116 && (INSN_CODE (dep_insn) >= 0)
16117 && (get_attr_type (dep_insn) == TYPE_CMP
16118 || get_attr_type (dep_insn) == TYPE_COMPARE
16119 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16120 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16121 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16122 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16123 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16124 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16129 /* Fall out to return default cost. */
16135 /* The function returns a true if INSN is microcoded.
16136 Return false otherwise. */
16139 is_microcoded_insn (rtx insn)
16141 if (!insn || !INSN_P (insn)
16142 || GET_CODE (PATTERN (insn)) == USE
16143 || GET_CODE (PATTERN (insn)) == CLOBBER)
16146 if (rs6000_sched_groups)
16148 enum attr_type type = get_attr_type (insn);
16149 if (type == TYPE_LOAD_EXT_U
16150 || type == TYPE_LOAD_EXT_UX
16151 || type == TYPE_LOAD_UX
16152 || type == TYPE_STORE_UX
16153 || type == TYPE_MFCR)
16160 /* The function returns a nonzero value if INSN can be scheduled only
16161 as the first insn in a dispatch group ("dispatch-slot restricted").
16162 In this case, the returned value indicates how many dispatch slots
16163 the insn occupies (at the beginning of the group).
16164 Return 0 otherwise. */
16167 is_dispatch_slot_restricted (rtx insn)
16169 enum attr_type type;
16171 if (!rs6000_sched_groups)
16175 || insn == NULL_RTX
16176 || GET_CODE (insn) == NOTE
16177 || GET_CODE (PATTERN (insn)) == USE
16178 || GET_CODE (PATTERN (insn)) == CLOBBER)
16181 type = get_attr_type (insn);
16188 case TYPE_DELAYED_CR:
16189 case TYPE_CR_LOGICAL:
16197 if (rs6000_cpu == PROCESSOR_POWER5
16198 && is_cracked_insn (insn))
16204 /* The function returns true if INSN is cracked into 2 instructions
16205 by the processor (and therefore occupies 2 issue slots). */
16208 is_cracked_insn (rtx insn)
16210 if (!insn || !INSN_P (insn)
16211 || GET_CODE (PATTERN (insn)) == USE
16212 || GET_CODE (PATTERN (insn)) == CLOBBER)
16215 if (rs6000_sched_groups)
16217 enum attr_type type = get_attr_type (insn);
16218 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16219 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16220 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16221 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16222 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16223 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16224 || type == TYPE_IDIV || type == TYPE_LDIV
16225 || type == TYPE_INSERT_WORD)
16232 /* The function returns true if INSN can be issued only from
16233 the branch slot. */
16236 is_branch_slot_insn (rtx insn)
16238 if (!insn || !INSN_P (insn)
16239 || GET_CODE (PATTERN (insn)) == USE
16240 || GET_CODE (PATTERN (insn)) == CLOBBER)
16243 if (rs6000_sched_groups)
16245 enum attr_type type = get_attr_type (insn);
16246 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16254 /* A C statement (sans semicolon) to update the integer scheduling
16255 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16256 INSN earlier, reduce the priority to execute INSN later. Do not
16257 define this macro if you do not need to adjust the scheduling
16258 priorities of insns. */
16261 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16263 /* On machines (like the 750) which have asymmetric integer units,
16264 where one integer unit can do multiply and divides and the other
16265 can't, reduce the priority of multiply/divide so it is scheduled
16266 before other integer operations. */
16269 if (! INSN_P (insn))
16272 if (GET_CODE (PATTERN (insn)) == USE)
16275 switch (rs6000_cpu_attr) {
16277 switch (get_attr_type (insn))
16284 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16285 priority, priority);
16286 if (priority >= 0 && priority < 0x01000000)
16293 if (is_dispatch_slot_restricted (insn)
16294 && reload_completed
16295 && current_sched_info->sched_max_insns_priority
16296 && rs6000_sched_restricted_insns_priority)
16299 /* Prioritize insns that can be dispatched only in the first
16301 if (rs6000_sched_restricted_insns_priority == 1)
16302 /* Attach highest priority to insn. This means that in
16303 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16304 precede 'priority' (critical path) considerations. */
16305 return current_sched_info->sched_max_insns_priority;
16306 else if (rs6000_sched_restricted_insns_priority == 2)
16307 /* Increase priority of insn by a minimal amount. This means that in
16308 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16309 considerations precede dispatch-slot restriction considerations. */
16310 return (priority + 1);
16316 /* Return how many instructions the machine can issue per cycle. */
16319 rs6000_issue_rate (void)
16321 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16322 if (!reload_completed)
16325 switch (rs6000_cpu_attr) {
16326 case CPU_RIOS1: /* ? */
16328 case CPU_PPC601: /* ? */
16351 /* Return how many instructions to look ahead for better insn
16355 rs6000_use_sched_lookahead (void)
16357 if (rs6000_cpu_attr == CPU_PPC8540)
16362 /* Determine is PAT refers to memory. */
16365 is_mem_ref (rtx pat)
16371 if (GET_CODE (pat) == MEM)
16374 /* Recursively process the pattern. */
16375 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16377 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16380 ret |= is_mem_ref (XEXP (pat, i));
16381 else if (fmt[i] == 'E')
16382 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16383 ret |= is_mem_ref (XVECEXP (pat, i, j));
16389 /* Determine if PAT is a PATTERN of a load insn. */
16392 is_load_insn1 (rtx pat)
16394 if (!pat || pat == NULL_RTX)
16397 if (GET_CODE (pat) == SET)
16398 return is_mem_ref (SET_SRC (pat));
16400 if (GET_CODE (pat) == PARALLEL)
16404 for (i = 0; i < XVECLEN (pat, 0); i++)
16405 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16412 /* Determine if INSN loads from memory. */
16415 is_load_insn (rtx insn)
16417 if (!insn || !INSN_P (insn))
16420 if (GET_CODE (insn) == CALL_INSN)
16423 return is_load_insn1 (PATTERN (insn));
16426 /* Determine if PAT is a PATTERN of a store insn. */
16429 is_store_insn1 (rtx pat)
16431 if (!pat || pat == NULL_RTX)
16434 if (GET_CODE (pat) == SET)
16435 return is_mem_ref (SET_DEST (pat));
16437 if (GET_CODE (pat) == PARALLEL)
16441 for (i = 0; i < XVECLEN (pat, 0); i++)
16442 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16449 /* Determine if INSN stores to memory. */
16452 is_store_insn (rtx insn)
16454 if (!insn || !INSN_P (insn))
16457 return is_store_insn1 (PATTERN (insn));
16460 /* Returns whether the dependence between INSN and NEXT is considered
16461 costly by the given target. */
16464 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16467 /* If the flag is not enbled - no dependence is considered costly;
16468 allow all dependent insns in the same group.
16469 This is the most aggressive option. */
16470 if (rs6000_sched_costly_dep == no_dep_costly)
16473 /* If the flag is set to 1 - a dependence is always considered costly;
16474 do not allow dependent instructions in the same group.
16475 This is the most conservative option. */
16476 if (rs6000_sched_costly_dep == all_deps_costly)
16479 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16480 && is_load_insn (next)
16481 && is_store_insn (insn))
16482 /* Prevent load after store in the same group. */
16485 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16486 && is_load_insn (next)
16487 && is_store_insn (insn)
16488 && (!link || (int) REG_NOTE_KIND (link) == 0))
16489 /* Prevent load after store in the same group if it is a true
16493 /* The flag is set to X; dependences with latency >= X are considered costly,
16494 and will not be scheduled in the same group. */
16495 if (rs6000_sched_costly_dep <= max_dep_latency
16496 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16502 /* Return the next insn after INSN that is found before TAIL is reached,
16503 skipping any "non-active" insns - insns that will not actually occupy
16504 an issue slot. Return NULL_RTX if such an insn is not found. */
16507 get_next_active_insn (rtx insn, rtx tail)
16511 if (!insn || insn == tail)
16514 next_insn = NEXT_INSN (insn);
16517 && next_insn != tail
16518 && (GET_CODE(next_insn) == NOTE
16519 || GET_CODE (PATTERN (next_insn)) == USE
16520 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16522 next_insn = NEXT_INSN (next_insn);
16525 if (!next_insn || next_insn == tail)
16531 /* Return whether the presence of INSN causes a dispatch group termination
16532 of group WHICH_GROUP.
16534 If WHICH_GROUP == current_group, this function will return true if INSN
16535 causes the termination of the current group (i.e, the dispatch group to
16536 which INSN belongs). This means that INSN will be the last insn in the
16537 group it belongs to.
16539 If WHICH_GROUP == previous_group, this function will return true if INSN
16540 causes the termination of the previous group (i.e, the dispatch group that
16541 precedes the group to which INSN belongs). This means that INSN will be
16542 the first insn in the group it belongs to). */
16545 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16547 enum attr_type type;
16552 type = get_attr_type (insn);
16554 if (is_microcoded_insn (insn))
16557 if (which_group == current_group)
16559 if (is_branch_slot_insn (insn))
16563 else if (which_group == previous_group)
16565 if (is_dispatch_slot_restricted (insn))
16573 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16574 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16577 is_costly_group (rtx *group_insns, rtx next_insn)
16582 int issue_rate = rs6000_issue_rate ();
16584 for (i = 0; i < issue_rate; i++)
16586 rtx insn = group_insns[i];
16589 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16591 rtx next = XEXP (link, 0);
16592 if (next == next_insn)
16594 cost = insn_cost (insn, link, next_insn);
16595 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16604 /* Utility of the function redefine_groups.
16605 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16606 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16607 to keep it "far" (in a separate group) from GROUP_INSNS, following
16608 one of the following schemes, depending on the value of the flag
16609 -minsert_sched_nops = X:
16610 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16611 in order to force NEXT_INSN into a separate group.
16612 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16613 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16614 insertion (has a group just ended, how many vacant issue slots remain in the
16615 last group, and how many dispatch groups were encountered so far). */
16618 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16619 rtx next_insn, bool *group_end, int can_issue_more,
16624 int issue_rate = rs6000_issue_rate ();
16625 bool end = *group_end;
16628 if (next_insn == NULL_RTX)
16629 return can_issue_more;
16631 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16632 return can_issue_more;
16634 force = is_costly_group (group_insns, next_insn);
16636 return can_issue_more;
16638 if (sched_verbose > 6)
16639 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16640 *group_count ,can_issue_more);
16642 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16645 can_issue_more = 0;
16647 /* Since only a branch can be issued in the last issue_slot, it is
16648 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16649 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16650 in this case the last nop will start a new group and the branch
16651 will be forced to the new group. */
16652 if (can_issue_more && !is_branch_slot_insn (next_insn))
16655 while (can_issue_more > 0)
16658 emit_insn_before (nop, next_insn);
16666 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16668 int n_nops = rs6000_sched_insert_nops;
16670 /* Nops can't be issued from the branch slot, so the effective
16671 issue_rate for nops is 'issue_rate - 1'. */
16672 if (can_issue_more == 0)
16673 can_issue_more = issue_rate;
16675 if (can_issue_more == 0)
16677 can_issue_more = issue_rate - 1;
16680 for (i = 0; i < issue_rate; i++)
16682 group_insns[i] = 0;
16689 emit_insn_before (nop, next_insn);
16690 if (can_issue_more == issue_rate - 1) /* new group begins */
16693 if (can_issue_more == 0)
16695 can_issue_more = issue_rate - 1;
16698 for (i = 0; i < issue_rate; i++)
16700 group_insns[i] = 0;
16706 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16709 /* Is next_insn going to start a new group? */
16712 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16713 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16714 || (can_issue_more < issue_rate &&
16715 insn_terminates_group_p (next_insn, previous_group)));
16716 if (*group_end && end)
16719 if (sched_verbose > 6)
16720 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16721 *group_count, can_issue_more);
16722 return can_issue_more;
16725 return can_issue_more;
16728 /* This function tries to synch the dispatch groups that the compiler "sees"
16729 with the dispatch groups that the processor dispatcher is expected to
16730 form in practice. It tries to achieve this synchronization by forcing the
16731 estimated processor grouping on the compiler (as opposed to the function
16732 'pad_goups' which tries to force the scheduler's grouping on the processor).
16734 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16735 examines the (estimated) dispatch groups that will be formed by the processor
16736 dispatcher. It marks these group boundaries to reflect the estimated
16737 processor grouping, overriding the grouping that the scheduler had marked.
16738 Depending on the value of the flag '-minsert-sched-nops' this function can
16739 force certain insns into separate groups or force a certain distance between
16740 them by inserting nops, for example, if there exists a "costly dependence"
16743 The function estimates the group boundaries that the processor will form as
16744 folllows: It keeps track of how many vacant issue slots are available after
16745 each insn. A subsequent insn will start a new group if one of the following
16747 - no more vacant issue slots remain in the current dispatch group.
16748 - only the last issue slot, which is the branch slot, is vacant, but the next
16749 insn is not a branch.
16750 - only the last 2 or less issue slots, including the branch slot, are vacant,
16751 which means that a cracked insn (which occupies two issue slots) can't be
16752 issued in this group.
16753 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16754 start a new group. */
16757 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16759 rtx insn, next_insn;
16761 int can_issue_more;
16764 int group_count = 0;
16768 issue_rate = rs6000_issue_rate ();
16769 group_insns = alloca (issue_rate * sizeof (rtx));
16770 for (i = 0; i < issue_rate; i++)
16772 group_insns[i] = 0;
16774 can_issue_more = issue_rate;
16776 insn = get_next_active_insn (prev_head_insn, tail);
16779 while (insn != NULL_RTX)
16781 slot = (issue_rate - can_issue_more);
16782 group_insns[slot] = insn;
16784 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16785 if (insn_terminates_group_p (insn, current_group))
16786 can_issue_more = 0;
16788 next_insn = get_next_active_insn (insn, tail);
16789 if (next_insn == NULL_RTX)
16790 return group_count + 1;
16792 /* Is next_insn going to start a new group? */
16794 = (can_issue_more == 0
16795 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16796 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16797 || (can_issue_more < issue_rate &&
16798 insn_terminates_group_p (next_insn, previous_group)));
16800 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16801 next_insn, &group_end, can_issue_more,
16807 can_issue_more = 0;
16808 for (i = 0; i < issue_rate; i++)
16810 group_insns[i] = 0;
16814 if (GET_MODE (next_insn) == TImode && can_issue_more)
16815 PUT_MODE(next_insn, VOIDmode);
16816 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16817 PUT_MODE (next_insn, TImode);
16820 if (can_issue_more == 0)
16821 can_issue_more = issue_rate;
16824 return group_count;
16827 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16828 dispatch group boundaries that the scheduler had marked. Pad with nops
16829 any dispatch groups which have vacant issue slots, in order to force the
16830 scheduler's grouping on the processor dispatcher. The function
16831 returns the number of dispatch groups found. */
16834 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16836 rtx insn, next_insn;
16839 int can_issue_more;
16841 int group_count = 0;
16843 /* Initialize issue_rate. */
16844 issue_rate = rs6000_issue_rate ();
16845 can_issue_more = issue_rate;
16847 insn = get_next_active_insn (prev_head_insn, tail);
16848 next_insn = get_next_active_insn (insn, tail);
16850 while (insn != NULL_RTX)
16853 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16855 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16857 if (next_insn == NULL_RTX)
16862 /* If the scheduler had marked group termination at this location
16863 (between insn and next_indn), and neither insn nor next_insn will
16864 force group termination, pad the group with nops to force group
16867 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16868 && !insn_terminates_group_p (insn, current_group)
16869 && !insn_terminates_group_p (next_insn, previous_group))
16871 if (!is_branch_slot_insn(next_insn))
16874 while (can_issue_more)
16877 emit_insn_before (nop, next_insn);
16882 can_issue_more = issue_rate;
16887 next_insn = get_next_active_insn (insn, tail);
16890 return group_count;
16893 /* The following function is called at the end of scheduling BB.
16894 After reload, it inserts nops at insn group bundling. */
16897 rs6000_sched_finish (FILE *dump, int sched_verbose)
16902 fprintf (dump, "=== Finishing schedule.\n");
16904 if (reload_completed && rs6000_sched_groups)
16906 if (rs6000_sched_insert_nops == sched_finish_none)
16909 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
16910 n_groups = pad_groups (dump, sched_verbose,
16911 current_sched_info->prev_head,
16912 current_sched_info->next_tail);
16914 n_groups = redefine_groups (dump, sched_verbose,
16915 current_sched_info->prev_head,
16916 current_sched_info->next_tail);
16918 if (sched_verbose >= 6)
16920 fprintf (dump, "ngroups = %d\n", n_groups);
16921 print_rtl (dump, current_sched_info->prev_head);
16922 fprintf (dump, "Done finish_sched\n");
16927 /* Length in units of the trampoline for entering a nested function. */
16930 rs6000_trampoline_size (void)
16934 switch (DEFAULT_ABI)
16940 ret = (TARGET_32BIT) ? 12 : 24;
16945 ret = (TARGET_32BIT) ? 40 : 48;
16952 /* Emit RTL insns to initialize the variable parts of a trampoline.
16953 FNADDR is an RTX for the address of the function's pure code.
16954 CXT is an RTX for the static chain value for the function. */
16957 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
16959 enum machine_mode pmode = Pmode;
16960 int regsize = (TARGET_32BIT) ? 4 : 8;
16961 rtx ctx_reg = force_reg (pmode, cxt);
16963 switch (DEFAULT_ABI)
16968 /* Macros to shorten the code expansions below. */
16969 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16970 #define MEM_PLUS(addr,offset) \
16971 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16973 /* Under AIX, just build the 3 word function descriptor */
16976 rtx fn_reg = gen_reg_rtx (pmode);
16977 rtx toc_reg = gen_reg_rtx (pmode);
16978 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
16979 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
16980 emit_move_insn (MEM_DEREF (addr), fn_reg);
16981 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16982 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16986 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16989 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
16990 FALSE, VOIDmode, 4,
16992 GEN_INT (rs6000_trampoline_size ()), SImode,
17002 /* Table of valid machine attributes. */
17004 const struct attribute_spec rs6000_attribute_table[] =
17006 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17007 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17008 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17009 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17010 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17011 SUBTARGET_ATTRIBUTE_TABLE,
17013 { NULL, 0, 0, false, false, false, NULL }
17016 /* Handle the "altivec" attribute. The attribute may have
17017 arguments as follows:
17019 __attribute__((altivec(vector__)))
17020 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17021 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17023 and may appear more than once (e.g., 'vector bool char') in a
17024 given declaration. */
17027 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
17028 int flags ATTRIBUTE_UNUSED,
17029 bool *no_add_attrs)
17031 tree type = *node, result = NULL_TREE;
17032 enum machine_mode mode;
17035 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17036 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17037 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17040 while (POINTER_TYPE_P (type)
17041 || TREE_CODE (type) == FUNCTION_TYPE
17042 || TREE_CODE (type) == METHOD_TYPE
17043 || TREE_CODE (type) == ARRAY_TYPE)
17044 type = TREE_TYPE (type);
17046 mode = TYPE_MODE (type);
17048 if (rs6000_warn_altivec_long
17049 && (type == long_unsigned_type_node || type == long_integer_type_node))
17050 warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
17052 switch (altivec_type)
17055 unsigned_p = TYPE_UNSIGNED (type);
17059 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17062 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17065 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17067 case SFmode: result = V4SF_type_node; break;
17068 /* If the user says 'vector int bool', we may be handed the 'bool'
17069 attribute _before_ the 'vector' attribute, and so select the
17070 proper type in the 'b' case below. */
17071 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17079 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17080 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17081 case QImode: case V16QImode: result = bool_V16QI_type_node;
17088 case V8HImode: result = pixel_V8HI_type_node;
17094 if (result && result != type && TYPE_READONLY (type))
17095 result = build_qualified_type (result, TYPE_QUAL_CONST);
17097 *no_add_attrs = true; /* No need to hang on to the attribute. */
17100 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
17102 *node = reconstruct_complex_type (*node, result);
17107 /* AltiVec defines four built-in scalar types that serve as vector
17108 elements; we must teach the compiler how to mangle them. */
17110 static const char *
17111 rs6000_mangle_fundamental_type (tree type)
17113 if (type == bool_char_type_node) return "U6__boolc";
17114 if (type == bool_short_type_node) return "U6__bools";
17115 if (type == pixel_type_node) return "u7__pixel";
17116 if (type == bool_int_type_node) return "U6__booli";
17118 /* For all other types, use normal C++ mangling. */
17122 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17123 struct attribute_spec.handler. */
17126 rs6000_handle_longcall_attribute (tree *node, tree name,
17127 tree args ATTRIBUTE_UNUSED,
17128 int flags ATTRIBUTE_UNUSED,
17129 bool *no_add_attrs)
17131 if (TREE_CODE (*node) != FUNCTION_TYPE
17132 && TREE_CODE (*node) != FIELD_DECL
17133 && TREE_CODE (*node) != TYPE_DECL)
17135 warning ("%qs attribute only applies to functions",
17136 IDENTIFIER_POINTER (name));
17137 *no_add_attrs = true;
17143 /* Set longcall attributes on all functions declared when
17144 rs6000_default_long_calls is true. */
17146 rs6000_set_default_type_attributes (tree type)
17148 if (rs6000_default_long_calls
17149 && (TREE_CODE (type) == FUNCTION_TYPE
17150 || TREE_CODE (type) == METHOD_TYPE))
17151 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17153 TYPE_ATTRIBUTES (type));
17156 /* Return a reference suitable for calling a function with the
17157 longcall attribute. */
17160 rs6000_longcall_ref (rtx call_ref)
17162 const char *call_name;
17165 if (GET_CODE (call_ref) != SYMBOL_REF)
17168 /* System V adds '.' to the internal name, so skip them. */
17169 call_name = XSTR (call_ref, 0);
17170 if (*call_name == '.')
17172 while (*call_name == '.')
17175 node = get_identifier (call_name);
17176 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17179 return force_reg (Pmode, call_ref);
17182 #ifdef USING_ELFOS_H
17184 /* A C statement or statements to switch to the appropriate section
17185 for output of RTX in mode MODE. You can assume that RTX is some
17186 kind of constant in RTL. The argument MODE is redundant except in
17187 the case of a `const_int' rtx. Select the section by calling
17188 `text_section' or one of the alternatives for other sections.
17190 Do not define this macro if you put all constants in the read-only
17194 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17195 unsigned HOST_WIDE_INT align)
17197 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17200 default_elf_select_rtx_section (mode, x, align);
17203 /* A C statement or statements to switch to the appropriate
17204 section for output of DECL. DECL is either a `VAR_DECL' node
17205 or a constant of some sort. RELOC indicates whether forming
17206 the initial value of DECL requires link-time relocations. */
17209 rs6000_elf_select_section (tree decl, int reloc,
17210 unsigned HOST_WIDE_INT align)
17212 /* Pretend that we're always building for a shared library when
17213 ABI_AIX, because otherwise we end up with dynamic relocations
17214 in read-only sections. This happens for function pointers,
17215 references to vtables in typeinfo, and probably other cases. */
17216 default_elf_select_section_1 (decl, reloc, align,
17217 flag_pic || DEFAULT_ABI == ABI_AIX);
17220 /* A C statement to build up a unique section name, expressed as a
17221 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17222 RELOC indicates whether the initial value of EXP requires
17223 link-time relocations. If you do not define this macro, GCC will use
17224 the symbol name prefixed by `.' as the section name. Note - this
17225 macro can now be called for uninitialized data items as well as
17226 initialized data and functions. */
17229 rs6000_elf_unique_section (tree decl, int reloc)
17231 /* As above, pretend that we're always building for a shared library
17232 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17233 default_unique_section_1 (decl, reloc,
17234 flag_pic || DEFAULT_ABI == ABI_AIX);
17237 /* For a SYMBOL_REF, set generic flags and then perform some
17238 target-specific processing.
17240 When the AIX ABI is requested on a non-AIX system, replace the
17241 function name with the real name (with a leading .) rather than the
17242 function descriptor name. This saves a lot of overriding code to
17243 read the prefixes. */
17246 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17248 default_encode_section_info (decl, rtl, first);
17251 && TREE_CODE (decl) == FUNCTION_DECL
17253 && DEFAULT_ABI == ABI_AIX)
17255 rtx sym_ref = XEXP (rtl, 0);
17256 size_t len = strlen (XSTR (sym_ref, 0));
17257 char *str = alloca (len + 2);
17259 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17260 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17265 rs6000_elf_in_small_data_p (tree decl)
17267 if (rs6000_sdata == SDATA_NONE)
17270 /* We want to merge strings, so we never consider them small data. */
17271 if (TREE_CODE (decl) == STRING_CST)
17274 /* Functions are never in the small data area. */
17275 if (TREE_CODE (decl) == FUNCTION_DECL)
17278 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17280 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17281 if (strcmp (section, ".sdata") == 0
17282 || strcmp (section, ".sdata2") == 0
17283 || strcmp (section, ".sbss") == 0
17284 || strcmp (section, ".sbss2") == 0
17285 || strcmp (section, ".PPC.EMB.sdata0") == 0
17286 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17291 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17294 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17295 /* If it's not public, and we're not going to reference it there,
17296 there's no need to put it in the small data section. */
17297 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17304 #endif /* USING_ELFOS_H */
17307 /* Return a REG that occurs in ADDR with coefficient 1.
17308 ADDR can be effectively incremented by incrementing REG.
17310 r0 is special and we must not select it as an address
17311 register by this routine since our caller will try to
17312 increment the returned register via an "la" instruction. */
17315 find_addr_reg (rtx addr)
17317 while (GET_CODE (addr) == PLUS)
17319 if (GET_CODE (XEXP (addr, 0)) == REG
17320 && REGNO (XEXP (addr, 0)) != 0)
17321 addr = XEXP (addr, 0);
17322 else if (GET_CODE (XEXP (addr, 1)) == REG
17323 && REGNO (XEXP (addr, 1)) != 0)
17324 addr = XEXP (addr, 1);
17325 else if (CONSTANT_P (XEXP (addr, 0)))
17326 addr = XEXP (addr, 1);
17327 else if (CONSTANT_P (XEXP (addr, 1)))
17328 addr = XEXP (addr, 0);
17332 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
17338 rs6000_fatal_bad_address (rtx op)
17340 fatal_insn ("bad address", op);
17345 static tree branch_island_list = 0;
17347 /* Remember to generate a branch island for far calls to the given
17351 add_compiler_branch_island (tree label_name, tree function_name,
17354 tree branch_island = build_tree_list (function_name, label_name);
17355 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17356 TREE_CHAIN (branch_island) = branch_island_list;
17357 branch_island_list = branch_island;
17360 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17361 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17362 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17363 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17365 /* Generate far-jump branch islands for everything on the
17366 branch_island_list. Invoked immediately after the last instruction
17367 of the epilogue has been emitted; the branch-islands must be
17368 appended to, and contiguous with, the function body. Mach-O stubs
17369 are generated in machopic_output_stub(). */
17372 macho_branch_islands (void)
17375 tree branch_island;
17377 for (branch_island = branch_island_list;
17379 branch_island = TREE_CHAIN (branch_island))
17381 const char *label =
17382 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17384 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17385 char name_buf[512];
17386 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17387 if (name[0] == '*' || name[0] == '&')
17388 strcpy (name_buf, name+1);
17392 strcpy (name_buf+1, name);
17394 strcpy (tmp_buf, "\n");
17395 strcat (tmp_buf, label);
17396 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17397 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17398 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17399 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17402 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17403 strcat (tmp_buf, label);
17404 strcat (tmp_buf, "_pic\n");
17405 strcat (tmp_buf, label);
17406 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17408 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17409 strcat (tmp_buf, name_buf);
17410 strcat (tmp_buf, " - ");
17411 strcat (tmp_buf, label);
17412 strcat (tmp_buf, "_pic)\n");
17414 strcat (tmp_buf, "\tmtlr r0\n");
17416 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17417 strcat (tmp_buf, name_buf);
17418 strcat (tmp_buf, " - ");
17419 strcat (tmp_buf, label);
17420 strcat (tmp_buf, "_pic)\n");
17422 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17426 strcat (tmp_buf, ":\nlis r12,hi16(");
17427 strcat (tmp_buf, name_buf);
17428 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17429 strcat (tmp_buf, name_buf);
17430 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17432 output_asm_insn (tmp_buf, 0);
17433 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17434 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17435 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17436 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17439 branch_island_list = 0;
17442 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17443 already there or not. */
17446 no_previous_def (tree function_name)
17448 tree branch_island;
17449 for (branch_island = branch_island_list;
17451 branch_island = TREE_CHAIN (branch_island))
17452 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17457 /* GET_PREV_LABEL gets the label name from the previous definition of
17461 get_prev_label (tree function_name)
17463 tree branch_island;
17464 for (branch_island = branch_island_list;
17466 branch_island = TREE_CHAIN (branch_island))
17467 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17468 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17472 /* INSN is either a function call or a millicode call. It may have an
17473 unconditional jump in its delay slot.
17475 CALL_DEST is the routine we are calling. */
17478 output_call (rtx insn, rtx *operands, int dest_operand_number,
17479 int cookie_operand_number)
17481 static char buf[256];
17482 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17483 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17486 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17488 if (no_previous_def (funname))
17490 int line_number = 0;
17491 rtx label_rtx = gen_label_rtx ();
17492 char *label_buf, temp_buf[256];
17493 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17494 CODE_LABEL_NUMBER (label_rtx));
17495 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17496 labelname = get_identifier (label_buf);
17497 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17499 line_number = NOTE_LINE_NUMBER (insn);
17500 add_compiler_branch_island (labelname, funname, line_number);
17503 labelname = get_prev_label (funname);
17505 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17506 instruction will reach 'foo', otherwise link as 'bl L42'".
17507 "L42" should be a 'branch island', that will do a far jump to
17508 'foo'. Branch islands are generated in
17509 macho_branch_islands(). */
17510 sprintf (buf, "jbsr %%z%d,%.246s",
17511 dest_operand_number, IDENTIFIER_POINTER (labelname));
17514 sprintf (buf, "bl %%z%d", dest_operand_number);
17518 /* Generate PIC and indirect symbol stubs. */
17521 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17523 unsigned int length;
17524 char *symbol_name, *lazy_ptr_name;
17525 char *local_label_0;
17526 static int label = 0;
17528 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17529 symb = (*targetm.strip_name_encoding) (symb);
17532 length = strlen (symb);
17533 symbol_name = alloca (length + 32);
17534 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17536 lazy_ptr_name = alloca (length + 32);
17537 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17540 machopic_picsymbol_stub1_section ();
17542 machopic_symbol_stub1_section ();
17546 fprintf (file, "\t.align 5\n");
17548 fprintf (file, "%s:\n", stub);
17549 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17552 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
17553 sprintf (local_label_0, "\"L%011d$spb\"", label);
17555 fprintf (file, "\tmflr r0\n");
17556 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17557 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17558 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17559 lazy_ptr_name, local_label_0);
17560 fprintf (file, "\tmtlr r0\n");
17561 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17562 (TARGET_64BIT ? "ldu" : "lwzu"),
17563 lazy_ptr_name, local_label_0);
17564 fprintf (file, "\tmtctr r12\n");
17565 fprintf (file, "\tbctr\n");
17569 fprintf (file, "\t.align 4\n");
17571 fprintf (file, "%s:\n", stub);
17572 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17574 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17575 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
17576 fprintf (file, "\tmtctr r12\n");
17577 fprintf (file, "\tbctr\n");
17580 machopic_lazy_symbol_ptr_section ();
17581 fprintf (file, "%s:\n", lazy_ptr_name);
17582 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17583 fprintf (file, "%sdyld_stub_binding_helper\n",
17584 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17587 /* Legitimize PIC addresses. If the address is already
17588 position-independent, we return ORIG. Newly generated
17589 position-independent addresses go into a reg. This is REG if non
17590 zero, otherwise we allocate register(s) as necessary. */
17592 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17595 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17600 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17601 reg = gen_reg_rtx (Pmode);
17603 if (GET_CODE (orig) == CONST)
17605 if (GET_CODE (XEXP (orig, 0)) == PLUS
17606 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17609 if (GET_CODE (XEXP (orig, 0)) == PLUS)
17611 /* Use a different reg for the intermediate value, as
17612 it will be marked UNCHANGING. */
17613 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17616 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17619 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17625 if (GET_CODE (offset) == CONST_INT)
17627 if (SMALL_INT (offset))
17628 return plus_constant (base, INTVAL (offset));
17629 else if (! reload_in_progress && ! reload_completed)
17630 offset = force_reg (Pmode, offset);
17633 rtx mem = force_const_mem (Pmode, orig);
17634 return machopic_legitimize_pic_address (mem, Pmode, reg);
17637 return gen_rtx_PLUS (Pmode, base, offset);
17640 /* Fall back on generic machopic code. */
17641 return machopic_legitimize_pic_address (orig, mode, reg);
17644 /* This is just a placeholder to make linking work without having to
17645 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17646 ever needed for Darwin (not too likely!) this would have to get a
17647 real definition. */
17654 /* Output a .machine directive for the Darwin assembler, and call
17655 the generic start_file routine. */
17658 rs6000_darwin_file_start (void)
17660 static const struct
17666 { "ppc64", "ppc64", MASK_64BIT },
17667 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17668 { "power4", "ppc970", 0 },
17669 { "G5", "ppc970", 0 },
17670 { "7450", "ppc7450", 0 },
17671 { "7400", "ppc7400", MASK_ALTIVEC },
17672 { "G4", "ppc7400", 0 },
17673 { "750", "ppc750", 0 },
17674 { "740", "ppc750", 0 },
17675 { "G3", "ppc750", 0 },
17676 { "604e", "ppc604e", 0 },
17677 { "604", "ppc604", 0 },
17678 { "603e", "ppc603", 0 },
17679 { "603", "ppc603", 0 },
17680 { "601", "ppc601", 0 },
17681 { NULL, "ppc", 0 } };
17682 const char *cpu_id = "";
17685 rs6000_file_start();
17687 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17688 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17689 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17690 && rs6000_select[i].string[0] != '\0')
17691 cpu_id = rs6000_select[i].string;
17693 /* Look through the mapping array. Pick the first name that either
17694 matches the argument, has a bit set in IF_SET that is also set
17695 in the target flags, or has a NULL name. */
17698 while (mapping[i].arg != NULL
17699 && strcmp (mapping[i].arg, cpu_id) != 0
17700 && (mapping[i].if_set & target_flags) == 0)
17703 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17706 #endif /* TARGET_MACHO */
17709 static unsigned int
17710 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17712 return default_section_type_flags_1 (decl, name, reloc,
17713 flag_pic || DEFAULT_ABI == ABI_AIX);
17716 /* Record an element in the table of global constructors. SYMBOL is
17717 a SYMBOL_REF of the function to be called; PRIORITY is a number
17718 between 0 and MAX_INIT_PRIORITY.
17720 This differs from default_named_section_asm_out_constructor in
17721 that we have special handling for -mrelocatable. */
17724 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17726 const char *section = ".ctors";
17729 if (priority != DEFAULT_INIT_PRIORITY)
17731 sprintf (buf, ".ctors.%.5u",
17732 /* Invert the numbering so the linker puts us in the proper
17733 order; constructors are run from right to left, and the
17734 linker sorts in increasing order. */
17735 MAX_INIT_PRIORITY - priority);
17739 named_section_flags (section, SECTION_WRITE);
17740 assemble_align (POINTER_SIZE);
17742 if (TARGET_RELOCATABLE)
17744 fputs ("\t.long (", asm_out_file);
17745 output_addr_const (asm_out_file, symbol);
17746 fputs (")@fixup\n", asm_out_file);
17749 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17753 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17755 const char *section = ".dtors";
17758 if (priority != DEFAULT_INIT_PRIORITY)
17760 sprintf (buf, ".dtors.%.5u",
17761 /* Invert the numbering so the linker puts us in the proper
17762 order; constructors are run from right to left, and the
17763 linker sorts in increasing order. */
17764 MAX_INIT_PRIORITY - priority);
17768 named_section_flags (section, SECTION_WRITE);
17769 assemble_align (POINTER_SIZE);
17771 if (TARGET_RELOCATABLE)
17773 fputs ("\t.long (", asm_out_file);
17774 output_addr_const (asm_out_file, symbol);
17775 fputs (")@fixup\n", asm_out_file);
17778 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17782 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17786 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17787 ASM_OUTPUT_LABEL (file, name);
17788 fputs (DOUBLE_INT_ASM_OP, file);
17789 rs6000_output_function_entry (file, name);
17790 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17793 fputs ("\t.size\t", file);
17794 assemble_name (file, name);
17795 fputs (",24\n\t.type\t.", file);
17796 assemble_name (file, name);
17797 fputs (",@function\n", file);
17798 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17800 fputs ("\t.globl\t.", file);
17801 assemble_name (file, name);
17806 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17807 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17808 rs6000_output_function_entry (file, name);
17809 fputs (":\n", file);
17813 if (TARGET_RELOCATABLE
17814 && (get_pool_size () != 0 || current_function_profile)
17819 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17821 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17822 fprintf (file, "\t.long ");
17823 assemble_name (file, buf);
17825 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17826 assemble_name (file, buf);
17830 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17831 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17833 if (DEFAULT_ABI == ABI_AIX)
17835 const char *desc_name, *orig_name;
17837 orig_name = (*targetm.strip_name_encoding) (name);
17838 desc_name = orig_name;
17839 while (*desc_name == '.')
17842 if (TREE_PUBLIC (decl))
17843 fprintf (file, "\t.globl %s\n", desc_name);
17845 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17846 fprintf (file, "%s:\n", desc_name);
17847 fprintf (file, "\t.long %s\n", orig_name);
17848 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17849 if (DEFAULT_ABI == ABI_AIX)
17850 fputs ("\t.long 0\n", file);
17851 fprintf (file, "\t.previous\n");
17853 ASM_OUTPUT_LABEL (file, name);
17859 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
17861 fputs (GLOBAL_ASM_OP, stream);
17862 RS6000_OUTPUT_BASENAME (stream, name);
17863 putc ('\n', stream);
17867 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17868 tree decl ATTRIBUTE_UNUSED)
17871 static const char * const suffix[3] = { "PR", "RO", "RW" };
17873 if (flags & SECTION_CODE)
17875 else if (flags & SECTION_WRITE)
17880 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
17881 (flags & SECTION_CODE) ? "." : "",
17882 name, suffix[smclass], flags & SECTION_ENTSIZE);
17886 rs6000_xcoff_select_section (tree decl, int reloc,
17887 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17889 if (decl_readonly_section_1 (decl, reloc, 1))
17891 if (TREE_PUBLIC (decl))
17892 read_only_data_section ();
17894 read_only_private_data_section ();
17898 if (TREE_PUBLIC (decl))
17901 private_data_section ();
17906 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
17910 /* Use select_section for private and uninitialized data. */
17911 if (!TREE_PUBLIC (decl)
17912 || DECL_COMMON (decl)
17913 || DECL_INITIAL (decl) == NULL_TREE
17914 || DECL_INITIAL (decl) == error_mark_node
17915 || (flag_zero_initialized_in_bss
17916 && initializer_zerop (DECL_INITIAL (decl))))
17919 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17920 name = (*targetm.strip_name_encoding) (name);
17921 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
17924 /* Select section for constant in constant pool.
17926 On RS/6000, all constants are in the private read-only data area.
17927 However, if this is being placed in the TOC it must be output as a
17931 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
17932 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17934 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17937 read_only_private_data_section ();
17940 /* Remove any trailing [DS] or the like from the symbol name. */
17942 static const char *
17943 rs6000_xcoff_strip_name_encoding (const char *name)
17948 len = strlen (name);
17949 if (name[len - 1] == ']')
17950 return ggc_alloc_string (name, len - 4);
17955 /* Section attributes. AIX is always PIC. */
17957 static unsigned int
17958 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
17960 unsigned int align;
17961 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17963 /* Align to at least UNIT size. */
17964 if (flags & SECTION_CODE)
17965 align = MIN_UNITS_PER_WORD;
17967 /* Increase alignment of large objects if not already stricter. */
17968 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17969 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17970 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17972 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
17975 /* Output at beginning of assembler file.
17977 Initialize the section names for the RS/6000 at this point.
17979 Specify filename, including full path, to assembler.
17981 We want to go into the TOC section so at least one .toc will be emitted.
17982 Also, in order to output proper .bs/.es pairs, we need at least one static
17983 [RW] section emitted.
17985 Finally, declare mcount when profiling to make the assembler happy. */
17988 rs6000_xcoff_file_start (void)
17990 rs6000_gen_section_name (&xcoff_bss_section_name,
17991 main_input_filename, ".bss_");
17992 rs6000_gen_section_name (&xcoff_private_data_section_name,
17993 main_input_filename, ".rw_");
17994 rs6000_gen_section_name (&xcoff_read_only_section_name,
17995 main_input_filename, ".ro_");
17997 fputs ("\t.file\t", asm_out_file);
17998 output_quoted_string (asm_out_file, main_input_filename);
17999 fputc ('\n', asm_out_file);
18001 if (write_symbols != NO_DEBUG)
18002 private_data_section ();
18005 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18006 rs6000_file_start ();
18009 /* Output at end of assembler file.
18010 On the RS/6000, referencing data should automatically pull in text. */
18013 rs6000_xcoff_file_end (void)
18016 fputs ("_section_.text:\n", asm_out_file);
18018 fputs (TARGET_32BIT
18019 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18022 #endif /* TARGET_XCOFF */
18025 /* Cross-module name binding. Darwin does not support overriding
18026 functions at dynamic-link time. */
18029 rs6000_binds_local_p (tree decl)
18031 return default_binds_local_p_1 (decl, 0);
18035 /* Compute a (partial) cost for rtx X. Return true if the complete
18036 cost has been computed, and false if subexpressions should be
18037 scanned. In either case, *TOTAL contains the cost result. */
18040 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18042 enum machine_mode mode = GET_MODE (x);
18046 /* On the RS/6000, if it is valid in the insn, it is free. */
18048 if (((outer_code == SET
18049 || outer_code == PLUS
18050 || outer_code == MINUS)
18051 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18052 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18053 || (outer_code == AND
18054 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18055 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18056 mode == SImode ? 'L' : 'J'))
18057 || mask_operand (x, VOIDmode)))
18058 || ((outer_code == IOR || outer_code == XOR)
18059 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18060 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18061 mode == SImode ? 'L' : 'J'))))
18062 || outer_code == ASHIFT
18063 || outer_code == ASHIFTRT
18064 || outer_code == LSHIFTRT
18065 || outer_code == ROTATE
18066 || outer_code == ROTATERT
18067 || outer_code == ZERO_EXTRACT
18068 || (outer_code == MULT
18069 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18070 || ((outer_code == DIV || outer_code == UDIV
18071 || outer_code == MOD || outer_code == UMOD)
18072 && exact_log2 (INTVAL (x)) >= 0)
18073 || (outer_code == COMPARE
18074 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18075 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18076 || (outer_code == EQ
18077 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18078 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18079 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18080 mode == SImode ? 'L' : 'J'))))
18081 || (outer_code == GTU
18082 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18083 || (outer_code == LTU
18084 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18089 else if ((outer_code == PLUS
18090 && reg_or_add_cint64_operand (x, VOIDmode))
18091 || (outer_code == MINUS
18092 && reg_or_sub_cint64_operand (x, VOIDmode))
18093 || ((outer_code == SET
18094 || outer_code == IOR
18095 || outer_code == XOR)
18097 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18099 *total = COSTS_N_INSNS (1);
18106 && ((outer_code == AND
18107 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18108 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18109 || mask64_operand (x, DImode)))
18110 || ((outer_code == IOR || outer_code == XOR)
18111 && CONST_DOUBLE_HIGH (x) == 0
18112 && (CONST_DOUBLE_LOW (x)
18113 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18118 else if (mode == DImode
18119 && (outer_code == SET
18120 || outer_code == IOR
18121 || outer_code == XOR)
18122 && CONST_DOUBLE_HIGH (x) == 0)
18124 *total = COSTS_N_INSNS (1);
18133 /* When optimizing for size, MEM should be slightly more expensive
18134 than generating address, e.g., (plus (reg) (const)).
18135 L1 cache latency is about two instructions. */
18136 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18144 if (mode == DFmode)
18146 if (GET_CODE (XEXP (x, 0)) == MULT)
18148 /* FNMA accounted in outer NEG. */
18149 if (outer_code == NEG)
18150 *total = rs6000_cost->dmul - rs6000_cost->fp;
18152 *total = rs6000_cost->dmul;
18155 *total = rs6000_cost->fp;
18157 else if (mode == SFmode)
18159 /* FNMA accounted in outer NEG. */
18160 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18163 *total = rs6000_cost->fp;
18165 else if (GET_CODE (XEXP (x, 0)) == MULT)
18167 /* The rs6000 doesn't have shift-and-add instructions. */
18168 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
18169 *total += COSTS_N_INSNS (1);
18172 *total = COSTS_N_INSNS (1);
18176 if (mode == DFmode)
18178 if (GET_CODE (XEXP (x, 0)) == MULT)
18180 /* FNMA accounted in outer NEG. */
18181 if (outer_code == NEG)
18184 *total = rs6000_cost->dmul;
18187 *total = rs6000_cost->fp;
18189 else if (mode == SFmode)
18191 /* FNMA accounted in outer NEG. */
18192 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18195 *total = rs6000_cost->fp;
18197 else if (GET_CODE (XEXP (x, 0)) == MULT)
18199 /* The rs6000 doesn't have shift-and-sub instructions. */
18200 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
18201 *total += COSTS_N_INSNS (1);
18204 *total = COSTS_N_INSNS (1);
18208 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18209 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18211 if (INTVAL (XEXP (x, 1)) >= -256
18212 && INTVAL (XEXP (x, 1)) <= 255)
18213 *total = rs6000_cost->mulsi_const9;
18215 *total = rs6000_cost->mulsi_const;
18217 /* FMA accounted in outer PLUS/MINUS. */
18218 else if ((mode == DFmode || mode == SFmode)
18219 && (outer_code == PLUS || outer_code == MINUS))
18221 else if (mode == DFmode)
18222 *total = rs6000_cost->dmul;
18223 else if (mode == SFmode)
18224 *total = rs6000_cost->fp;
18225 else if (mode == DImode)
18226 *total = rs6000_cost->muldi;
18228 *total = rs6000_cost->mulsi;
18233 if (FLOAT_MODE_P (mode))
18235 *total = mode == DFmode ? rs6000_cost->ddiv
18236 : rs6000_cost->sdiv;
18243 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18244 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18246 if (code == DIV || code == MOD)
18248 *total = COSTS_N_INSNS (2);
18251 *total = COSTS_N_INSNS (1);
18255 if (GET_MODE (XEXP (x, 1)) == DImode)
18256 *total = rs6000_cost->divdi;
18258 *total = rs6000_cost->divsi;
18260 /* Add in shift and subtract for MOD. */
18261 if (code == MOD || code == UMOD)
18262 *total += COSTS_N_INSNS (2);
18266 *total = COSTS_N_INSNS (4);
18270 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18281 *total = COSTS_N_INSNS (1);
18289 /* Handle mul_highpart. */
18290 if (outer_code == TRUNCATE
18291 && GET_CODE (XEXP (x, 0)) == MULT)
18293 if (mode == DImode)
18294 *total = rs6000_cost->muldi;
18296 *total = rs6000_cost->mulsi;
18299 else if (outer_code == AND)
18302 *total = COSTS_N_INSNS (1);
18307 if (GET_CODE (XEXP (x, 0)) == MEM)
18310 *total = COSTS_N_INSNS (1);
18316 if (!FLOAT_MODE_P (mode))
18318 *total = COSTS_N_INSNS (1);
18324 case UNSIGNED_FLOAT:
18328 case FLOAT_TRUNCATE:
18329 *total = rs6000_cost->fp;
18333 switch (XINT (x, 1))
18336 *total = rs6000_cost->fp;
18348 *total = COSTS_N_INSNS (1);
18351 else if (FLOAT_MODE_P (mode)
18352 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18354 *total = rs6000_cost->fp;
18362 /* Carry bit requires mode == Pmode.
18363 NEG or PLUS already counted so only add one. */
18365 && (outer_code == NEG || outer_code == PLUS))
18367 *total = COSTS_N_INSNS (1);
18370 if (outer_code == SET)
18372 if (XEXP (x, 1) == const0_rtx)
18374 *total = COSTS_N_INSNS (2);
18377 else if (mode == Pmode)
18379 *total = COSTS_N_INSNS (3);
18388 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18390 *total = COSTS_N_INSNS (2);
18394 if (outer_code == COMPARE)
18408 /* A C expression returning the cost of moving data from a register of class
18409 CLASS1 to one of CLASS2. */
18412 rs6000_register_move_cost (enum machine_mode mode,
18413 enum reg_class from, enum reg_class to)
18415 /* Moves from/to GENERAL_REGS. */
18416 if (reg_classes_intersect_p (to, GENERAL_REGS)
18417 || reg_classes_intersect_p (from, GENERAL_REGS))
18419 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18422 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18423 return (rs6000_memory_move_cost (mode, from, 0)
18424 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18426 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18428 else if (from == CR_REGS)
18432 /* A move will cost one instruction per GPR moved. */
18433 return 2 * HARD_REGNO_NREGS (0, mode);
18436 /* Moving between two similar registers is just one instruction. */
18437 else if (reg_classes_intersect_p (to, from))
18438 return mode == TFmode ? 4 : 2;
18440 /* Everything else has to go through GENERAL_REGS. */
18442 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18443 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18446 /* A C expressions returning the cost of moving data of MODE from a register to
18450 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18451 int in ATTRIBUTE_UNUSED)
18453 if (reg_classes_intersect_p (class, GENERAL_REGS))
18454 return 4 * HARD_REGNO_NREGS (0, mode);
18455 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18456 return 4 * HARD_REGNO_NREGS (32, mode);
18457 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18458 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
18460 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18463 /* Return an RTX representing where to find the function value of a
18464 function returning MODE. */
18466 rs6000_complex_function_value (enum machine_mode mode)
18468 unsigned int regno;
18470 enum machine_mode inner = GET_MODE_INNER (mode);
18471 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18473 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18474 regno = FP_ARG_RETURN;
18477 regno = GP_ARG_RETURN;
18479 /* 32-bit is OK since it'll go in r3/r4. */
18480 if (TARGET_32BIT && inner_bytes >= 4)
18481 return gen_rtx_REG (mode, regno);
18484 if (inner_bytes >= 8)
18485 return gen_rtx_REG (mode, regno);
18487 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18489 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18490 GEN_INT (inner_bytes));
18491 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18494 /* Compose a PARALLEL for a darwin64 struct being returned by
18498 rs6000_darwin64_function_value (CUMULATIVE_ARGS *cum, tree valtype)
18501 rtx rvec[FIRST_PSEUDO_REGISTER], sub, roffset, suboff;
18502 int k = 0, bytepos, tot, elt, i, subbytepos;
18503 enum machine_mode fmode;
18505 switch (TREE_CODE (valtype))
18508 for (f = TYPE_FIELDS (valtype); f ; f = TREE_CHAIN (f))
18509 if (TREE_CODE (f) == FIELD_DECL)
18511 ftype = TREE_TYPE (f);
18512 fmode = TYPE_MODE (ftype);
18513 bytepos = int_bit_position (f) / BITS_PER_UNIT;
18514 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18516 sub = gen_rtx_REG (fmode, cum->fregno++);
18517 cum->sysv_gregno++;
18519 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18521 sub = gen_rtx_REG (fmode, cum->vregno++);
18522 cum->sysv_gregno++;
18524 else if (fmode == BLKmode
18525 && (TREE_CODE (ftype) == RECORD_TYPE
18526 || TREE_CODE (ftype) == ARRAY_TYPE))
18527 sub = rs6000_darwin64_function_value (cum, ftype);
18529 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18530 if (sub == NULL_RTX)
18532 else if (GET_CODE (sub) == PARALLEL)
18534 for (i = 0; i < XVECLEN (sub, 0); i++)
18536 rtx subsub = XVECEXP (sub, 0, i);
18538 suboff = XEXP (subsub, 1);
18539 subbytepos = INTVAL (suboff);
18540 subbytepos += bytepos;
18541 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18542 subsub = XEXP (subsub, 0);
18543 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18548 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18549 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18553 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18558 /* If passing by value won't work, give up. */
18559 if (int_size_in_bytes (valtype) <= 0)
18561 ftype = TREE_TYPE (valtype);
18562 fmode = TYPE_MODE (ftype);
18563 tot = int_size_in_bytes (valtype) / int_size_in_bytes (ftype);
18565 for (elt = 0; elt < tot; ++elt)
18567 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18569 sub = gen_rtx_REG (fmode, cum->fregno++);
18570 cum->sysv_gregno++;
18572 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18574 sub = gen_rtx_REG (fmode, cum->vregno++);
18575 cum->sysv_gregno++;
18577 else if (fmode == BLKmode
18578 && (TREE_CODE (ftype) == RECORD_TYPE
18579 || TREE_CODE (ftype) == ARRAY_TYPE))
18580 sub = rs6000_darwin64_function_value (cum, ftype);
18582 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18583 if (sub == NULL_RTX)
18585 else if (GET_CODE (sub) == PARALLEL)
18587 for (i = 0; i < XVECLEN (sub, 0); i++)
18589 rtx subsub = XVECEXP (sub, 0, i);
18591 suboff = XEXP (subsub, 1);
18592 subbytepos = INTVAL (suboff);
18593 subbytepos += bytepos;
18594 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18595 subsub = XEXP (subsub, 0);
18596 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18601 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18602 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18604 bytepos += int_size_in_bytes (ftype);
18607 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18616 /* Define how to find the value returned by a function.
18617 VALTYPE is the data type of the value (as a tree).
18618 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18619 otherwise, FUNC is 0.
18621 On the SPE, both FPs and vectors are returned in r3.
18623 On RS/6000 an integer value is in r3 and a floating-point value is in
18624 fp1, unless -msoft-float. */
18627 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18629 enum machine_mode mode;
18630 unsigned int regno;
18632 /* Special handling for structs in darwin64. */
18633 if (rs6000_darwin64_abi
18634 && TYPE_MODE (valtype) == BLKmode
18635 && (TREE_CODE (valtype) == RECORD_TYPE
18636 || TREE_CODE (valtype) == ARRAY_TYPE))
18638 CUMULATIVE_ARGS valcum;
18641 valcum.sysv_gregno = GP_ARG_RETURN;
18642 valcum.fregno = FP_ARG_MIN_REG;
18643 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18644 valret = rs6000_darwin64_function_value (&valcum, valtype);
18647 /* Otherwise fall through to standard ABI rules. */
18650 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18652 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18653 return gen_rtx_PARALLEL (DImode,
18655 gen_rtx_EXPR_LIST (VOIDmode,
18656 gen_rtx_REG (SImode, GP_ARG_RETURN),
18658 gen_rtx_EXPR_LIST (VOIDmode,
18659 gen_rtx_REG (SImode,
18660 GP_ARG_RETURN + 1),
18664 if ((INTEGRAL_TYPE_P (valtype)
18665 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18666 || POINTER_TYPE_P (valtype))
18667 mode = TARGET_32BIT ? SImode : DImode;
18669 mode = TYPE_MODE (valtype);
18671 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18672 regno = FP_ARG_RETURN;
18673 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18674 && targetm.calls.split_complex_arg)
18675 return rs6000_complex_function_value (mode);
18676 else if (TREE_CODE (valtype) == VECTOR_TYPE
18677 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18678 && ALTIVEC_VECTOR_MODE (mode))
18679 regno = ALTIVEC_ARG_RETURN;
18680 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18681 && (mode == DFmode || mode == DCmode))
18682 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18684 regno = GP_ARG_RETURN;
18686 return gen_rtx_REG (mode, regno);
18689 /* Define how to find the value returned by a library function
18690 assuming the value has mode MODE. */
18692 rs6000_libcall_value (enum machine_mode mode)
18694 unsigned int regno;
18696 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18698 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18699 return gen_rtx_PARALLEL (DImode,
18701 gen_rtx_EXPR_LIST (VOIDmode,
18702 gen_rtx_REG (SImode, GP_ARG_RETURN),
18704 gen_rtx_EXPR_LIST (VOIDmode,
18705 gen_rtx_REG (SImode,
18706 GP_ARG_RETURN + 1),
18710 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18711 && TARGET_HARD_FLOAT && TARGET_FPRS)
18712 regno = FP_ARG_RETURN;
18713 else if (ALTIVEC_VECTOR_MODE (mode)
18714 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18715 regno = ALTIVEC_ARG_RETURN;
18716 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18717 return rs6000_complex_function_value (mode);
18718 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18719 && (mode == DFmode || mode == DCmode))
18720 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18722 regno = GP_ARG_RETURN;
18724 return gen_rtx_REG (mode, regno);
18727 /* Define the offset between two registers, FROM to be eliminated and its
18728 replacement TO, at the start of a routine. */
18730 rs6000_initial_elimination_offset (int from, int to)
18732 rs6000_stack_t *info = rs6000_stack_info ();
18733 HOST_WIDE_INT offset;
18735 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18736 offset = info->push_p ? 0 : -info->total_size;
18737 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
18738 offset = info->total_size;
18739 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18740 offset = info->push_p ? info->total_size : 0;
18741 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18749 /* Return true if TYPE is of type __ev64_opaque__. */
18752 is_ev64_opaque_type (tree type)
18755 && (type == opaque_V2SI_type_node
18756 || type == opaque_V2SF_type_node
18757 || type == opaque_p_V2SI_type_node));
18761 rs6000_dwarf_register_span (rtx reg)
18766 && (SPE_VECTOR_MODE (GET_MODE (reg))
18767 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18772 regno = REGNO (reg);
18774 /* The duality of the SPE register size wreaks all kinds of havoc.
18775 This is a way of distinguishing r0 in 32-bits from r0 in
18778 gen_rtx_PARALLEL (VOIDmode,
18781 gen_rtx_REG (SImode, regno + 1200),
18782 gen_rtx_REG (SImode, regno))
18784 gen_rtx_REG (SImode, regno),
18785 gen_rtx_REG (SImode, regno + 1200)));
18788 /* Map internal gcc register numbers to DWARF2 register numbers. */
18791 rs6000_dbx_register_number (unsigned int regno)
18793 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18795 if (regno == MQ_REGNO)
18797 if (regno == LINK_REGISTER_REGNUM)
18799 if (regno == COUNT_REGISTER_REGNUM)
18801 if (CR_REGNO_P (regno))
18802 return regno - CR0_REGNO + 86;
18803 if (regno == XER_REGNO)
18805 if (ALTIVEC_REGNO_P (regno))
18806 return regno - FIRST_ALTIVEC_REGNO + 1124;
18807 if (regno == VRSAVE_REGNO)
18809 if (regno == VSCR_REGNO)
18811 if (regno == SPE_ACC_REGNO)
18813 if (regno == SPEFSCR_REGNO)
18815 /* SPE high reg number. We get these values of regno from
18816 rs6000_dwarf_register_span. */
18817 if (regno >= 1200 && regno < 1232)
18823 /* target hook eh_return_filter_mode */
18824 static enum machine_mode
18825 rs6000_eh_return_filter_mode (void)
18827 return TARGET_32BIT ? SImode : word_mode;
18830 /* Target hook for vector_mode_supported_p. */
18832 rs6000_vector_mode_supported_p (enum machine_mode mode)
18835 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18838 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18845 #include "gt-rs6000.h"