1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 /* Always emit branch hint bits. */
142 static GTY(()) bool rs6000_always_hint;
144 /* Schedule instructions for group formation. */
145 static GTY(()) bool rs6000_sched_groups;
147 /* Support for -msched-costly-dep option. */
148 const char *rs6000_sched_costly_dep_str;
149 enum rs6000_dependence_cost rs6000_sched_costly_dep;
151 /* Support for -minsert-sched-nops option. */
152 const char *rs6000_sched_insert_nops_str;
153 enum rs6000_nop_insertion rs6000_sched_insert_nops;
155 /* Support targetm.vectorize.builtin_mask_for_load. */
156 static GTY(()) tree altivec_builtin_mask_for_load;
158 /* Size of long double */
159 int rs6000_long_double_type_size;
161 /* Whether -mabi=altivec has appeared */
162 int rs6000_altivec_abi;
164 /* Nonzero if we want SPE ABI extensions. */
167 /* Nonzero if floating point operations are done in the GPRs. */
168 int rs6000_float_gprs = 0;
170 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
171 int rs6000_darwin64_abi;
173 /* Set to nonzero once AIX common-mode calls have been defined. */
174 static GTY(()) int common_mode_defined;
176 /* Save information from a "cmpxx" operation until the branch or scc is
178 rtx rs6000_compare_op0, rs6000_compare_op1;
179 int rs6000_compare_fp_p;
181 /* Label number of label created for -mrelocatable, to call to so we can
182 get the address of the GOT section */
183 int rs6000_pic_labelno;
186 /* Which abi to adhere to */
187 const char *rs6000_abi_name;
189 /* Semantics of the small data area */
190 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
192 /* Which small data model to use */
193 const char *rs6000_sdata_name = (char *)0;
195 /* Counter for labels which are to be placed in .fixup. */
196 int fixuplabelno = 0;
199 /* Bit size of immediate TLS offsets and string from which it is decoded. */
200 int rs6000_tls_size = 32;
201 const char *rs6000_tls_size_string;
203 /* ABI enumeration available for subtarget to use. */
204 enum rs6000_abi rs6000_current_abi;
206 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
210 const char *rs6000_debug_name;
211 int rs6000_debug_stack; /* debug stack applications */
212 int rs6000_debug_arg; /* debug argument handling */
214 /* Value is TRUE if register/mode pair is acceptable. */
215 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
217 /* Built in types. */
219 tree rs6000_builtin_types[RS6000_BTI_MAX];
220 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
222 const char *rs6000_traceback_name;
224 traceback_default = 0,
230 /* Flag to say the TOC is initialized */
232 char toc_label_name[10];
234 static GTY(()) section *read_only_data_section;
235 static GTY(()) section *private_data_section;
236 static GTY(()) section *read_only_private_data_section;
237 static GTY(()) section *sdata2_section;
238 static GTY(()) section *toc_section;
240 /* Control alignment for fields within structures. */
241 /* String from -malign-XXXXX. */
242 int rs6000_alignment_flags;
244 /* True for any options that were explicitly set. */
246 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
247 bool alignment; /* True if -malign- was used. */
248 bool abi; /* True if -mabi= was used. */
249 bool spe; /* True if -mspe= was used. */
250 bool float_gprs; /* True if -mfloat-gprs= was used. */
251 bool isel; /* True if -misel was used. */
252 bool long_double; /* True if -mlong-double- was used. */
253 } rs6000_explicit_options;
255 struct builtin_description
257 /* mask is not const because we're going to alter it below. This
258 nonsense will go away when we rewrite the -march infrastructure
259 to give us more target flag bits. */
261 const enum insn_code icode;
262 const char *const name;
263 const enum rs6000_builtins code;
266 /* Target cpu costs. */
268 struct processor_costs {
269 const int mulsi; /* cost of SImode multiplication. */
270 const int mulsi_const; /* cost of SImode multiplication by constant. */
271 const int mulsi_const9; /* cost of SImode mult by short constant. */
272 const int muldi; /* cost of DImode multiplication. */
273 const int divsi; /* cost of SImode division. */
274 const int divdi; /* cost of DImode division. */
275 const int fp; /* cost of simple SFmode and DFmode insns. */
276 const int dmul; /* cost of DFmode multiplication (and fmadd). */
277 const int sdiv; /* cost of SFmode division (fdivs). */
278 const int ddiv; /* cost of DFmode division (fdiv). */
281 const struct processor_costs *rs6000_cost;
283 /* Processor costs (relative to an add) */
285 /* Instruction size costs on 32bit processors. */
287 struct processor_costs size32_cost = {
288 COSTS_N_INSNS (1), /* mulsi */
289 COSTS_N_INSNS (1), /* mulsi_const */
290 COSTS_N_INSNS (1), /* mulsi_const9 */
291 COSTS_N_INSNS (1), /* muldi */
292 COSTS_N_INSNS (1), /* divsi */
293 COSTS_N_INSNS (1), /* divdi */
294 COSTS_N_INSNS (1), /* fp */
295 COSTS_N_INSNS (1), /* dmul */
296 COSTS_N_INSNS (1), /* sdiv */
297 COSTS_N_INSNS (1), /* ddiv */
300 /* Instruction size costs on 64bit processors. */
302 struct processor_costs size64_cost = {
303 COSTS_N_INSNS (1), /* mulsi */
304 COSTS_N_INSNS (1), /* mulsi_const */
305 COSTS_N_INSNS (1), /* mulsi_const9 */
306 COSTS_N_INSNS (1), /* muldi */
307 COSTS_N_INSNS (1), /* divsi */
308 COSTS_N_INSNS (1), /* divdi */
309 COSTS_N_INSNS (1), /* fp */
310 COSTS_N_INSNS (1), /* dmul */
311 COSTS_N_INSNS (1), /* sdiv */
312 COSTS_N_INSNS (1), /* ddiv */
315 /* Instruction costs on RIOS1 processors. */
317 struct processor_costs rios1_cost = {
318 COSTS_N_INSNS (5), /* mulsi */
319 COSTS_N_INSNS (4), /* mulsi_const */
320 COSTS_N_INSNS (3), /* mulsi_const9 */
321 COSTS_N_INSNS (5), /* muldi */
322 COSTS_N_INSNS (19), /* divsi */
323 COSTS_N_INSNS (19), /* divdi */
324 COSTS_N_INSNS (2), /* fp */
325 COSTS_N_INSNS (2), /* dmul */
326 COSTS_N_INSNS (19), /* sdiv */
327 COSTS_N_INSNS (19), /* ddiv */
330 /* Instruction costs on RIOS2 processors. */
332 struct processor_costs rios2_cost = {
333 COSTS_N_INSNS (2), /* mulsi */
334 COSTS_N_INSNS (2), /* mulsi_const */
335 COSTS_N_INSNS (2), /* mulsi_const9 */
336 COSTS_N_INSNS (2), /* muldi */
337 COSTS_N_INSNS (13), /* divsi */
338 COSTS_N_INSNS (13), /* divdi */
339 COSTS_N_INSNS (2), /* fp */
340 COSTS_N_INSNS (2), /* dmul */
341 COSTS_N_INSNS (17), /* sdiv */
342 COSTS_N_INSNS (17), /* ddiv */
345 /* Instruction costs on RS64A processors. */
347 struct processor_costs rs64a_cost = {
348 COSTS_N_INSNS (20), /* mulsi */
349 COSTS_N_INSNS (12), /* mulsi_const */
350 COSTS_N_INSNS (8), /* mulsi_const9 */
351 COSTS_N_INSNS (34), /* muldi */
352 COSTS_N_INSNS (65), /* divsi */
353 COSTS_N_INSNS (67), /* divdi */
354 COSTS_N_INSNS (4), /* fp */
355 COSTS_N_INSNS (4), /* dmul */
356 COSTS_N_INSNS (31), /* sdiv */
357 COSTS_N_INSNS (31), /* ddiv */
360 /* Instruction costs on MPCCORE processors. */
362 struct processor_costs mpccore_cost = {
363 COSTS_N_INSNS (2), /* mulsi */
364 COSTS_N_INSNS (2), /* mulsi_const */
365 COSTS_N_INSNS (2), /* mulsi_const9 */
366 COSTS_N_INSNS (2), /* muldi */
367 COSTS_N_INSNS (6), /* divsi */
368 COSTS_N_INSNS (6), /* divdi */
369 COSTS_N_INSNS (4), /* fp */
370 COSTS_N_INSNS (5), /* dmul */
371 COSTS_N_INSNS (10), /* sdiv */
372 COSTS_N_INSNS (17), /* ddiv */
375 /* Instruction costs on PPC403 processors. */
377 struct processor_costs ppc403_cost = {
378 COSTS_N_INSNS (4), /* mulsi */
379 COSTS_N_INSNS (4), /* mulsi_const */
380 COSTS_N_INSNS (4), /* mulsi_const9 */
381 COSTS_N_INSNS (4), /* muldi */
382 COSTS_N_INSNS (33), /* divsi */
383 COSTS_N_INSNS (33), /* divdi */
384 COSTS_N_INSNS (11), /* fp */
385 COSTS_N_INSNS (11), /* dmul */
386 COSTS_N_INSNS (11), /* sdiv */
387 COSTS_N_INSNS (11), /* ddiv */
390 /* Instruction costs on PPC405 processors. */
392 struct processor_costs ppc405_cost = {
393 COSTS_N_INSNS (5), /* mulsi */
394 COSTS_N_INSNS (4), /* mulsi_const */
395 COSTS_N_INSNS (3), /* mulsi_const9 */
396 COSTS_N_INSNS (5), /* muldi */
397 COSTS_N_INSNS (35), /* divsi */
398 COSTS_N_INSNS (35), /* divdi */
399 COSTS_N_INSNS (11), /* fp */
400 COSTS_N_INSNS (11), /* dmul */
401 COSTS_N_INSNS (11), /* sdiv */
402 COSTS_N_INSNS (11), /* ddiv */
405 /* Instruction costs on PPC440 processors. */
407 struct processor_costs ppc440_cost = {
408 COSTS_N_INSNS (3), /* mulsi */
409 COSTS_N_INSNS (2), /* mulsi_const */
410 COSTS_N_INSNS (2), /* mulsi_const9 */
411 COSTS_N_INSNS (3), /* muldi */
412 COSTS_N_INSNS (34), /* divsi */
413 COSTS_N_INSNS (34), /* divdi */
414 COSTS_N_INSNS (5), /* fp */
415 COSTS_N_INSNS (5), /* dmul */
416 COSTS_N_INSNS (19), /* sdiv */
417 COSTS_N_INSNS (33), /* ddiv */
420 /* Instruction costs on PPC601 processors. */
422 struct processor_costs ppc601_cost = {
423 COSTS_N_INSNS (5), /* mulsi */
424 COSTS_N_INSNS (5), /* mulsi_const */
425 COSTS_N_INSNS (5), /* mulsi_const9 */
426 COSTS_N_INSNS (5), /* muldi */
427 COSTS_N_INSNS (36), /* divsi */
428 COSTS_N_INSNS (36), /* divdi */
429 COSTS_N_INSNS (4), /* fp */
430 COSTS_N_INSNS (5), /* dmul */
431 COSTS_N_INSNS (17), /* sdiv */
432 COSTS_N_INSNS (31), /* ddiv */
435 /* Instruction costs on PPC603 processors. */
437 struct processor_costs ppc603_cost = {
438 COSTS_N_INSNS (5), /* mulsi */
439 COSTS_N_INSNS (3), /* mulsi_const */
440 COSTS_N_INSNS (2), /* mulsi_const9 */
441 COSTS_N_INSNS (5), /* muldi */
442 COSTS_N_INSNS (37), /* divsi */
443 COSTS_N_INSNS (37), /* divdi */
444 COSTS_N_INSNS (3), /* fp */
445 COSTS_N_INSNS (4), /* dmul */
446 COSTS_N_INSNS (18), /* sdiv */
447 COSTS_N_INSNS (33), /* ddiv */
450 /* Instruction costs on PPC604 processors. */
452 struct processor_costs ppc604_cost = {
453 COSTS_N_INSNS (4), /* mulsi */
454 COSTS_N_INSNS (4), /* mulsi_const */
455 COSTS_N_INSNS (4), /* mulsi_const9 */
456 COSTS_N_INSNS (4), /* muldi */
457 COSTS_N_INSNS (20), /* divsi */
458 COSTS_N_INSNS (20), /* divdi */
459 COSTS_N_INSNS (3), /* fp */
460 COSTS_N_INSNS (3), /* dmul */
461 COSTS_N_INSNS (18), /* sdiv */
462 COSTS_N_INSNS (32), /* ddiv */
465 /* Instruction costs on PPC604e processors. */
467 struct processor_costs ppc604e_cost = {
468 COSTS_N_INSNS (2), /* mulsi */
469 COSTS_N_INSNS (2), /* mulsi_const */
470 COSTS_N_INSNS (2), /* mulsi_const9 */
471 COSTS_N_INSNS (2), /* muldi */
472 COSTS_N_INSNS (20), /* divsi */
473 COSTS_N_INSNS (20), /* divdi */
474 COSTS_N_INSNS (3), /* fp */
475 COSTS_N_INSNS (3), /* dmul */
476 COSTS_N_INSNS (18), /* sdiv */
477 COSTS_N_INSNS (32), /* ddiv */
480 /* Instruction costs on PPC620 processors. */
482 struct processor_costs ppc620_cost = {
483 COSTS_N_INSNS (5), /* mulsi */
484 COSTS_N_INSNS (4), /* mulsi_const */
485 COSTS_N_INSNS (3), /* mulsi_const9 */
486 COSTS_N_INSNS (7), /* muldi */
487 COSTS_N_INSNS (21), /* divsi */
488 COSTS_N_INSNS (37), /* divdi */
489 COSTS_N_INSNS (3), /* fp */
490 COSTS_N_INSNS (3), /* dmul */
491 COSTS_N_INSNS (18), /* sdiv */
492 COSTS_N_INSNS (32), /* ddiv */
495 /* Instruction costs on PPC630 processors. */
497 struct processor_costs ppc630_cost = {
498 COSTS_N_INSNS (5), /* mulsi */
499 COSTS_N_INSNS (4), /* mulsi_const */
500 COSTS_N_INSNS (3), /* mulsi_const9 */
501 COSTS_N_INSNS (7), /* muldi */
502 COSTS_N_INSNS (21), /* divsi */
503 COSTS_N_INSNS (37), /* divdi */
504 COSTS_N_INSNS (3), /* fp */
505 COSTS_N_INSNS (3), /* dmul */
506 COSTS_N_INSNS (17), /* sdiv */
507 COSTS_N_INSNS (21), /* ddiv */
510 /* Instruction costs on PPC750 and PPC7400 processors. */
512 struct processor_costs ppc750_cost = {
513 COSTS_N_INSNS (5), /* mulsi */
514 COSTS_N_INSNS (3), /* mulsi_const */
515 COSTS_N_INSNS (2), /* mulsi_const9 */
516 COSTS_N_INSNS (5), /* muldi */
517 COSTS_N_INSNS (17), /* divsi */
518 COSTS_N_INSNS (17), /* divdi */
519 COSTS_N_INSNS (3), /* fp */
520 COSTS_N_INSNS (3), /* dmul */
521 COSTS_N_INSNS (17), /* sdiv */
522 COSTS_N_INSNS (31), /* ddiv */
525 /* Instruction costs on PPC7450 processors. */
527 struct processor_costs ppc7450_cost = {
528 COSTS_N_INSNS (4), /* mulsi */
529 COSTS_N_INSNS (3), /* mulsi_const */
530 COSTS_N_INSNS (3), /* mulsi_const9 */
531 COSTS_N_INSNS (4), /* muldi */
532 COSTS_N_INSNS (23), /* divsi */
533 COSTS_N_INSNS (23), /* divdi */
534 COSTS_N_INSNS (5), /* fp */
535 COSTS_N_INSNS (5), /* dmul */
536 COSTS_N_INSNS (21), /* sdiv */
537 COSTS_N_INSNS (35), /* ddiv */
540 /* Instruction costs on PPC8540 processors. */
542 struct processor_costs ppc8540_cost = {
543 COSTS_N_INSNS (4), /* mulsi */
544 COSTS_N_INSNS (4), /* mulsi_const */
545 COSTS_N_INSNS (4), /* mulsi_const9 */
546 COSTS_N_INSNS (4), /* muldi */
547 COSTS_N_INSNS (19), /* divsi */
548 COSTS_N_INSNS (19), /* divdi */
549 COSTS_N_INSNS (4), /* fp */
550 COSTS_N_INSNS (4), /* dmul */
551 COSTS_N_INSNS (29), /* sdiv */
552 COSTS_N_INSNS (29), /* ddiv */
555 /* Instruction costs on POWER4 and POWER5 processors. */
557 struct processor_costs power4_cost = {
558 COSTS_N_INSNS (3), /* mulsi */
559 COSTS_N_INSNS (2), /* mulsi_const */
560 COSTS_N_INSNS (2), /* mulsi_const9 */
561 COSTS_N_INSNS (4), /* muldi */
562 COSTS_N_INSNS (18), /* divsi */
563 COSTS_N_INSNS (34), /* divdi */
564 COSTS_N_INSNS (3), /* fp */
565 COSTS_N_INSNS (3), /* dmul */
566 COSTS_N_INSNS (17), /* sdiv */
567 COSTS_N_INSNS (17), /* ddiv */
571 static bool rs6000_function_ok_for_sibcall (tree, tree);
572 static const char *rs6000_invalid_within_doloop (rtx);
573 static rtx rs6000_generate_compare (enum rtx_code);
574 static void rs6000_maybe_dead (rtx);
575 static void rs6000_emit_stack_tie (void);
576 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
577 static rtx spe_synthesize_frame_save (rtx);
578 static bool spe_func_has_64bit_regs_p (void);
579 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
581 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
582 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
583 static unsigned rs6000_hash_constant (rtx);
584 static unsigned toc_hash_function (const void *);
585 static int toc_hash_eq (const void *, const void *);
586 static int constant_pool_expr_1 (rtx, int *, int *);
587 static bool constant_pool_expr_p (rtx);
588 static bool legitimate_indexed_address_p (rtx, int);
589 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
590 static struct machine_function * rs6000_init_machine_status (void);
591 static bool rs6000_assemble_integer (rtx, unsigned int, int);
592 static bool no_global_regs_above (int);
593 #ifdef HAVE_GAS_HIDDEN
594 static void rs6000_assemble_visibility (tree, int);
596 static int rs6000_ra_ever_killed (void);
597 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
598 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
599 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
600 static const char *rs6000_mangle_fundamental_type (tree);
601 extern const struct attribute_spec rs6000_attribute_table[];
602 static void rs6000_set_default_type_attributes (tree);
603 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
604 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
605 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
607 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
608 static bool rs6000_return_in_memory (tree, tree);
609 static void rs6000_file_start (void);
611 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
612 static void rs6000_elf_asm_out_constructor (rtx, int);
613 static void rs6000_elf_asm_out_destructor (rtx, int);
614 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
615 static void rs6000_elf_asm_init_sections (void);
616 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
617 static void rs6000_elf_unique_section (tree, int);
618 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
619 unsigned HOST_WIDE_INT);
620 static void rs6000_elf_encode_section_info (tree, rtx, int)
624 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
625 static void rs6000_xcoff_asm_init_sections (void);
626 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
627 static section *rs6000_xcoff_select_section (tree, int,
628 unsigned HOST_WIDE_INT);
629 static void rs6000_xcoff_unique_section (tree, int);
630 static section *rs6000_xcoff_select_rtx_section
631 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
632 static const char * rs6000_xcoff_strip_name_encoding (const char *);
633 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
634 static void rs6000_xcoff_file_start (void);
635 static void rs6000_xcoff_file_end (void);
637 static int rs6000_variable_issue (FILE *, int, rtx, int);
638 static bool rs6000_rtx_costs (rtx, int, int, int *);
639 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
640 static bool is_microcoded_insn (rtx);
641 static int is_dispatch_slot_restricted (rtx);
642 static bool is_cracked_insn (rtx);
643 static bool is_branch_slot_insn (rtx);
644 static int rs6000_adjust_priority (rtx, int);
645 static int rs6000_issue_rate (void);
646 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
647 static rtx get_next_active_insn (rtx, rtx);
648 static bool insn_terminates_group_p (rtx , enum group_termination);
649 static bool is_costly_group (rtx *, rtx);
650 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
651 static int redefine_groups (FILE *, int, rtx, rtx);
652 static int pad_groups (FILE *, int, rtx, rtx);
653 static void rs6000_sched_finish (FILE *, int);
654 static int rs6000_use_sched_lookahead (void);
655 static tree rs6000_builtin_mask_for_load (void);
657 static void def_builtin (int, const char *, tree, int);
658 static void rs6000_init_builtins (void);
659 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
660 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
661 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
662 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
663 static void altivec_init_builtins (void);
664 static void rs6000_common_init_builtins (void);
665 static void rs6000_init_libfuncs (void);
667 static void enable_mask_for_builtins (struct builtin_description *, int,
668 enum rs6000_builtins,
669 enum rs6000_builtins);
670 static tree build_opaque_vector_type (tree, int);
671 static void spe_init_builtins (void);
672 static rtx spe_expand_builtin (tree, rtx, bool *);
673 static rtx spe_expand_stv_builtin (enum insn_code, tree);
674 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
675 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
676 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
677 static rs6000_stack_t *rs6000_stack_info (void);
678 static void debug_stack_info (rs6000_stack_t *);
680 static rtx altivec_expand_builtin (tree, rtx, bool *);
681 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
682 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
683 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
684 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
685 static rtx altivec_expand_predicate_builtin (enum insn_code,
686 const char *, tree, rtx);
687 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
688 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
689 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
690 static rtx altivec_expand_vec_set_builtin (tree);
691 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
692 static int get_element_number (tree, tree);
693 static bool rs6000_handle_option (size_t, const char *, int);
694 static void rs6000_parse_tls_size_option (void);
695 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
696 static int first_altivec_reg_to_save (void);
697 static unsigned int compute_vrsave_mask (void);
698 static void compute_save_world_info (rs6000_stack_t *info_ptr);
699 static void is_altivec_return_reg (rtx, void *);
700 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
701 int easy_vector_constant (rtx, enum machine_mode);
702 static bool rs6000_is_opaque_type (tree);
703 static rtx rs6000_dwarf_register_span (rtx);
704 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
705 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
706 static rtx rs6000_tls_get_addr (void);
707 static rtx rs6000_got_sym (void);
708 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
709 static const char *rs6000_get_some_local_dynamic_name (void);
710 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
711 static rtx rs6000_complex_function_value (enum machine_mode);
712 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
713 enum machine_mode, tree);
714 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
716 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
717 tree, HOST_WIDE_INT);
718 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
721 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
724 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
725 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
726 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
727 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
728 enum machine_mode, tree,
730 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
732 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
734 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
736 static void macho_branch_islands (void);
737 static void add_compiler_branch_island (tree, tree, int);
738 static int no_previous_def (tree function_name);
739 static tree get_prev_label (tree function_name);
740 static void rs6000_darwin_file_start (void);
743 static tree rs6000_build_builtin_va_list (void);
744 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
745 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
746 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
747 static bool rs6000_vector_mode_supported_p (enum machine_mode);
748 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
750 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
752 static int get_vsel_insn (enum machine_mode);
753 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
754 static tree rs6000_stack_protect_fail (void);
756 const int INSN_NOT_AVAILABLE = -1;
757 static enum machine_mode rs6000_eh_return_filter_mode (void);
759 /* Hash table stuff for keeping track of TOC entries. */
761 struct toc_hash_struct GTY(())
763 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
764 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
766 enum machine_mode key_mode;
770 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
772 /* Default register names. */
773 char rs6000_reg_names[][8] =
775 "0", "1", "2", "3", "4", "5", "6", "7",
776 "8", "9", "10", "11", "12", "13", "14", "15",
777 "16", "17", "18", "19", "20", "21", "22", "23",
778 "24", "25", "26", "27", "28", "29", "30", "31",
779 "0", "1", "2", "3", "4", "5", "6", "7",
780 "8", "9", "10", "11", "12", "13", "14", "15",
781 "16", "17", "18", "19", "20", "21", "22", "23",
782 "24", "25", "26", "27", "28", "29", "30", "31",
783 "mq", "lr", "ctr","ap",
784 "0", "1", "2", "3", "4", "5", "6", "7",
786 /* AltiVec registers. */
787 "0", "1", "2", "3", "4", "5", "6", "7",
788 "8", "9", "10", "11", "12", "13", "14", "15",
789 "16", "17", "18", "19", "20", "21", "22", "23",
790 "24", "25", "26", "27", "28", "29", "30", "31",
793 "spe_acc", "spefscr",
794 /* Soft frame pointer. */
798 #ifdef TARGET_REGNAMES
799 static const char alt_reg_names[][8] =
801 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
802 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
803 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
804 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
805 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
806 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
807 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
808 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
809 "mq", "lr", "ctr", "ap",
810 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
812 /* AltiVec registers. */
813 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
814 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
815 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
816 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
819 "spe_acc", "spefscr",
820 /* Soft frame pointer. */
825 #ifndef MASK_STRICT_ALIGN
826 #define MASK_STRICT_ALIGN 0
828 #ifndef TARGET_PROFILE_KERNEL
829 #define TARGET_PROFILE_KERNEL 0
832 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
833 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
835 /* Initialize the GCC target structure. */
836 #undef TARGET_ATTRIBUTE_TABLE
837 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
838 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
839 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
841 #undef TARGET_ASM_ALIGNED_DI_OP
842 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
844 /* Default unaligned ops are only provided for ELF. Find the ops needed
845 for non-ELF systems. */
846 #ifndef OBJECT_FORMAT_ELF
848 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
850 #undef TARGET_ASM_UNALIGNED_HI_OP
851 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
852 #undef TARGET_ASM_UNALIGNED_SI_OP
853 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
854 #undef TARGET_ASM_UNALIGNED_DI_OP
855 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
858 #undef TARGET_ASM_UNALIGNED_HI_OP
859 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
860 #undef TARGET_ASM_UNALIGNED_SI_OP
861 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
862 #undef TARGET_ASM_UNALIGNED_DI_OP
863 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
864 #undef TARGET_ASM_ALIGNED_DI_OP
865 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
869 /* This hook deals with fixups for relocatable code and DI-mode objects
871 #undef TARGET_ASM_INTEGER
872 #define TARGET_ASM_INTEGER rs6000_assemble_integer
874 #ifdef HAVE_GAS_HIDDEN
875 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
876 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
879 #undef TARGET_HAVE_TLS
880 #define TARGET_HAVE_TLS HAVE_AS_TLS
882 #undef TARGET_CANNOT_FORCE_CONST_MEM
883 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
885 #undef TARGET_ASM_FUNCTION_PROLOGUE
886 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
887 #undef TARGET_ASM_FUNCTION_EPILOGUE
888 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
890 #undef TARGET_SCHED_VARIABLE_ISSUE
891 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
893 #undef TARGET_SCHED_ISSUE_RATE
894 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
895 #undef TARGET_SCHED_ADJUST_COST
896 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
897 #undef TARGET_SCHED_ADJUST_PRIORITY
898 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
899 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
900 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
901 #undef TARGET_SCHED_FINISH
902 #define TARGET_SCHED_FINISH rs6000_sched_finish
904 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
905 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
907 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
908 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
910 #undef TARGET_INIT_BUILTINS
911 #define TARGET_INIT_BUILTINS rs6000_init_builtins
913 #undef TARGET_EXPAND_BUILTIN
914 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
916 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
917 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
919 #undef TARGET_INIT_LIBFUNCS
920 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
923 #undef TARGET_BINDS_LOCAL_P
924 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
927 #undef TARGET_ASM_OUTPUT_MI_THUNK
928 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
930 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
931 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
933 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
934 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
936 #undef TARGET_INVALID_WITHIN_DOLOOP
937 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
939 #undef TARGET_RTX_COSTS
940 #define TARGET_RTX_COSTS rs6000_rtx_costs
941 #undef TARGET_ADDRESS_COST
942 #define TARGET_ADDRESS_COST hook_int_rtx_0
944 #undef TARGET_VECTOR_OPAQUE_P
945 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
947 #undef TARGET_DWARF_REGISTER_SPAN
948 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
950 /* On rs6000, function arguments are promoted, as are function return
952 #undef TARGET_PROMOTE_FUNCTION_ARGS
953 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
954 #undef TARGET_PROMOTE_FUNCTION_RETURN
955 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
957 #undef TARGET_RETURN_IN_MEMORY
958 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
960 #undef TARGET_SETUP_INCOMING_VARARGS
961 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
963 /* Always strict argument naming on rs6000. */
964 #undef TARGET_STRICT_ARGUMENT_NAMING
965 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
966 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
967 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
968 #undef TARGET_SPLIT_COMPLEX_ARG
969 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
970 #undef TARGET_MUST_PASS_IN_STACK
971 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
972 #undef TARGET_PASS_BY_REFERENCE
973 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
974 #undef TARGET_ARG_PARTIAL_BYTES
975 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
977 #undef TARGET_BUILD_BUILTIN_VA_LIST
978 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
980 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
981 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
983 #undef TARGET_EH_RETURN_FILTER_MODE
984 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
986 #undef TARGET_SCALAR_MODE_SUPPORTED_P
987 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
989 #undef TARGET_VECTOR_MODE_SUPPORTED_P
990 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
992 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
993 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
995 #undef TARGET_HANDLE_OPTION
996 #define TARGET_HANDLE_OPTION rs6000_handle_option
998 #undef TARGET_DEFAULT_TARGET_FLAGS
999 #define TARGET_DEFAULT_TARGET_FLAGS \
1000 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
1002 #undef TARGET_STACK_PROTECT_FAIL
1003 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1005 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1006 The PowerPC architecture requires only weak consistency among
1007 processors--that is, memory accesses between processors need not be
1008 sequentially consistent and memory accesses among processors can occur
1009 in any order. The ability to order memory accesses weakly provides
1010 opportunities for more efficient use of the system bus. Unless a
1011 dependency exists, the 604e allows read operations to precede store
1013 #undef TARGET_RELAXED_ORDERING
1014 #define TARGET_RELAXED_ORDERING true
1017 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1018 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1021 struct gcc_target targetm = TARGET_INITIALIZER;
1024 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1027 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1029 /* The GPRs can hold any mode, but values bigger than one register
1030 cannot go past R31. */
1031 if (INT_REGNO_P (regno))
1032 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1034 /* The float registers can only hold floating modes and DImode.
1035 This also excludes decimal float modes. */
1036 if (FP_REGNO_P (regno))
1038 (SCALAR_FLOAT_MODE_P (mode)
1039 && !DECIMAL_FLOAT_MODE_P (mode)
1040 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1041 || (GET_MODE_CLASS (mode) == MODE_INT
1042 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1044 /* The CR register can only hold CC modes. */
1045 if (CR_REGNO_P (regno))
1046 return GET_MODE_CLASS (mode) == MODE_CC;
1048 if (XER_REGNO_P (regno))
1049 return mode == PSImode;
1051 /* AltiVec only in AldyVec registers. */
1052 if (ALTIVEC_REGNO_P (regno))
1053 return ALTIVEC_VECTOR_MODE (mode);
1055 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1056 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1059 /* We cannot put TImode anywhere except general register and it must be
1060 able to fit within the register set. */
1062 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1065 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1067 rs6000_init_hard_regno_mode_ok (void)
1071 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1072 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1073 if (rs6000_hard_regno_mode_ok (r, m))
1074 rs6000_hard_regno_mode_ok_p[m][r] = true;
1077 /* If not otherwise specified by a target, make 'long double' equivalent to
1080 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1081 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1084 /* Override command line options. Mostly we process the processor
1085 type and sometimes adjust other TARGET_ options. */
1088 rs6000_override_options (const char *default_cpu)
1091 struct rs6000_cpu_select *ptr;
1094 /* Simplifications for entries below. */
1097 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1098 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1101 /* This table occasionally claims that a processor does not support
1102 a particular feature even though it does, but the feature is slower
1103 than the alternative. Thus, it shouldn't be relied on as a
1104 complete description of the processor's support.
1106 Please keep this list in order, and don't forget to update the
1107 documentation in invoke.texi when adding a new processor or
1111 const char *const name; /* Canonical processor name. */
1112 const enum processor_type processor; /* Processor type enum value. */
1113 const int target_enable; /* Target flags to enable. */
1114 } const processor_target_table[]
1115 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1116 {"403", PROCESSOR_PPC403,
1117 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1118 {"405", PROCESSOR_PPC405,
1119 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1120 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_MULHW},
1121 {"440", PROCESSOR_PPC440,
1122 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1123 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_MULHW},
1124 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1125 {"601", PROCESSOR_PPC601,
1126 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1127 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1130 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1131 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1132 {"620", PROCESSOR_PPC620,
1133 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1134 {"630", PROCESSOR_PPC630,
1135 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1136 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1138 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1139 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1140 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1141 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1142 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1143 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1144 /* 8548 has a dummy entry for now. */
1145 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1146 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1147 {"970", PROCESSOR_POWER4,
1148 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1149 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1150 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1151 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1152 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1153 {"G5", PROCESSOR_POWER4,
1154 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1155 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1156 {"power2", PROCESSOR_POWER,
1157 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1158 {"power3", PROCESSOR_PPC630,
1159 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1160 {"power4", PROCESSOR_POWER4,
1161 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1162 {"power5", PROCESSOR_POWER5,
1163 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1164 | MASK_MFCRF | MASK_POPCNTB},
1165 {"power5+", PROCESSOR_POWER5,
1166 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1167 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1168 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1169 {"powerpc64", PROCESSOR_POWERPC64,
1170 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1171 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1172 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1173 {"rios2", PROCESSOR_RIOS2,
1174 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1175 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1176 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1177 {"rs64", PROCESSOR_RS64A,
1178 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1181 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1183 /* Some OSs don't support saving the high part of 64-bit registers on
1184 context switch. Other OSs don't support saving Altivec registers.
1185 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1186 settings; if the user wants either, the user must explicitly specify
1187 them and we won't interfere with the user's specification. */
1190 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1191 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1192 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1193 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW)
1196 rs6000_init_hard_regno_mode_ok ();
1198 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1199 #ifdef OS_MISSING_POWERPC64
1200 if (OS_MISSING_POWERPC64)
1201 set_masks &= ~MASK_POWERPC64;
1203 #ifdef OS_MISSING_ALTIVEC
1204 if (OS_MISSING_ALTIVEC)
1205 set_masks &= ~MASK_ALTIVEC;
1208 /* Don't override by the processor default if given explicitly. */
1209 set_masks &= ~target_flags_explicit;
1211 /* Identify the processor type. */
1212 rs6000_select[0].string = default_cpu;
1213 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1215 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1217 ptr = &rs6000_select[i];
1218 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1220 for (j = 0; j < ptt_size; j++)
1221 if (! strcmp (ptr->string, processor_target_table[j].name))
1223 if (ptr->set_tune_p)
1224 rs6000_cpu = processor_target_table[j].processor;
1226 if (ptr->set_arch_p)
1228 target_flags &= ~set_masks;
1229 target_flags |= (processor_target_table[j].target_enable
1236 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1243 /* If we are optimizing big endian systems for space, use the load/store
1244 multiple and string instructions. */
1245 if (BYTES_BIG_ENDIAN && optimize_size)
1246 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1248 /* Don't allow -mmultiple or -mstring on little endian systems
1249 unless the cpu is a 750, because the hardware doesn't support the
1250 instructions used in little endian mode, and causes an alignment
1251 trap. The 750 does not cause an alignment trap (except when the
1252 target is unaligned). */
1254 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1256 if (TARGET_MULTIPLE)
1258 target_flags &= ~MASK_MULTIPLE;
1259 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1260 warning (0, "-mmultiple is not supported on little endian systems");
1265 target_flags &= ~MASK_STRING;
1266 if ((target_flags_explicit & MASK_STRING) != 0)
1267 warning (0, "-mstring is not supported on little endian systems");
1271 /* Set debug flags */
1272 if (rs6000_debug_name)
1274 if (! strcmp (rs6000_debug_name, "all"))
1275 rs6000_debug_stack = rs6000_debug_arg = 1;
1276 else if (! strcmp (rs6000_debug_name, "stack"))
1277 rs6000_debug_stack = 1;
1278 else if (! strcmp (rs6000_debug_name, "arg"))
1279 rs6000_debug_arg = 1;
1281 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1284 if (rs6000_traceback_name)
1286 if (! strncmp (rs6000_traceback_name, "full", 4))
1287 rs6000_traceback = traceback_full;
1288 else if (! strncmp (rs6000_traceback_name, "part", 4))
1289 rs6000_traceback = traceback_part;
1290 else if (! strncmp (rs6000_traceback_name, "no", 2))
1291 rs6000_traceback = traceback_none;
1293 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1294 rs6000_traceback_name);
1297 if (!rs6000_explicit_options.long_double)
1298 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1300 /* Set Altivec ABI as default for powerpc64 linux. */
1301 if (TARGET_ELF && TARGET_64BIT)
1303 rs6000_altivec_abi = 1;
1304 TARGET_ALTIVEC_VRSAVE = 1;
1307 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1308 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1310 rs6000_darwin64_abi = 1;
1312 darwin_one_byte_bool = 1;
1314 /* Default to natural alignment, for better performance. */
1315 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1318 /* Handle -mtls-size option. */
1319 rs6000_parse_tls_size_option ();
1321 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1322 SUBTARGET_OVERRIDE_OPTIONS;
1324 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1325 SUBSUBTARGET_OVERRIDE_OPTIONS;
1327 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1328 SUB3TARGET_OVERRIDE_OPTIONS;
1334 error ("AltiVec and E500 instructions cannot coexist");
1336 /* The e500 does not have string instructions, and we set
1337 MASK_STRING above when optimizing for size. */
1338 if ((target_flags & MASK_STRING) != 0)
1339 target_flags = target_flags & ~MASK_STRING;
1341 else if (rs6000_select[1].string != NULL)
1343 /* For the powerpc-eabispe configuration, we set all these by
1344 default, so let's unset them if we manually set another
1345 CPU that is not the E500. */
1346 if (!rs6000_explicit_options.abi)
1348 if (!rs6000_explicit_options.spe)
1350 if (!rs6000_explicit_options.float_gprs)
1351 rs6000_float_gprs = 0;
1352 if (!rs6000_explicit_options.isel)
1354 if (!rs6000_explicit_options.long_double)
1355 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1358 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1359 && rs6000_cpu != PROCESSOR_POWER5);
1360 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1361 || rs6000_cpu == PROCESSOR_POWER5);
1363 rs6000_sched_restricted_insns_priority
1364 = (rs6000_sched_groups ? 1 : 0);
1366 /* Handle -msched-costly-dep option. */
1367 rs6000_sched_costly_dep
1368 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1370 if (rs6000_sched_costly_dep_str)
1372 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1373 rs6000_sched_costly_dep = no_dep_costly;
1374 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1375 rs6000_sched_costly_dep = all_deps_costly;
1376 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1377 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1378 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1379 rs6000_sched_costly_dep = store_to_load_dep_costly;
1381 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1384 /* Handle -minsert-sched-nops option. */
1385 rs6000_sched_insert_nops
1386 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1388 if (rs6000_sched_insert_nops_str)
1390 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1391 rs6000_sched_insert_nops = sched_finish_none;
1392 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1393 rs6000_sched_insert_nops = sched_finish_pad_groups;
1394 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1395 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1397 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1400 #ifdef TARGET_REGNAMES
1401 /* If the user desires alternate register names, copy in the
1402 alternate names now. */
1403 if (TARGET_REGNAMES)
1404 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1407 /* Set aix_struct_return last, after the ABI is determined.
1408 If -maix-struct-return or -msvr4-struct-return was explicitly
1409 used, don't override with the ABI default. */
1410 if (!rs6000_explicit_options.aix_struct_ret)
1411 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1413 if (TARGET_LONG_DOUBLE_128
1414 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1415 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1418 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1420 /* We can only guarantee the availability of DI pseudo-ops when
1421 assembling for 64-bit targets. */
1424 targetm.asm_out.aligned_op.di = NULL;
1425 targetm.asm_out.unaligned_op.di = NULL;
1428 /* Set branch target alignment, if not optimizing for size. */
1431 if (rs6000_sched_groups)
1433 if (align_functions <= 0)
1434 align_functions = 16;
1435 if (align_jumps <= 0)
1437 if (align_loops <= 0)
1440 if (align_jumps_max_skip <= 0)
1441 align_jumps_max_skip = 15;
1442 if (align_loops_max_skip <= 0)
1443 align_loops_max_skip = 15;
1446 /* Arrange to save and restore machine status around nested functions. */
1447 init_machine_status = rs6000_init_machine_status;
1449 /* We should always be splitting complex arguments, but we can't break
1450 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1451 if (DEFAULT_ABI != ABI_AIX)
1452 targetm.calls.split_complex_arg = NULL;
1454 /* Initialize rs6000_cost with the appropriate target costs. */
1456 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1460 case PROCESSOR_RIOS1:
1461 rs6000_cost = &rios1_cost;
1464 case PROCESSOR_RIOS2:
1465 rs6000_cost = &rios2_cost;
1468 case PROCESSOR_RS64A:
1469 rs6000_cost = &rs64a_cost;
1472 case PROCESSOR_MPCCORE:
1473 rs6000_cost = &mpccore_cost;
1476 case PROCESSOR_PPC403:
1477 rs6000_cost = &ppc403_cost;
1480 case PROCESSOR_PPC405:
1481 rs6000_cost = &ppc405_cost;
1484 case PROCESSOR_PPC440:
1485 rs6000_cost = &ppc440_cost;
1488 case PROCESSOR_PPC601:
1489 rs6000_cost = &ppc601_cost;
1492 case PROCESSOR_PPC603:
1493 rs6000_cost = &ppc603_cost;
1496 case PROCESSOR_PPC604:
1497 rs6000_cost = &ppc604_cost;
1500 case PROCESSOR_PPC604e:
1501 rs6000_cost = &ppc604e_cost;
1504 case PROCESSOR_PPC620:
1505 rs6000_cost = &ppc620_cost;
1508 case PROCESSOR_PPC630:
1509 rs6000_cost = &ppc630_cost;
1512 case PROCESSOR_PPC750:
1513 case PROCESSOR_PPC7400:
1514 rs6000_cost = &ppc750_cost;
1517 case PROCESSOR_PPC7450:
1518 rs6000_cost = &ppc7450_cost;
1521 case PROCESSOR_PPC8540:
1522 rs6000_cost = &ppc8540_cost;
1525 case PROCESSOR_POWER4:
1526 case PROCESSOR_POWER5:
1527 rs6000_cost = &power4_cost;
1535 /* Implement targetm.vectorize.builtin_mask_for_load. */
1537 rs6000_builtin_mask_for_load (void)
1540 return altivec_builtin_mask_for_load;
1545 /* Handle generic options of the form -mfoo=yes/no.
1546 NAME is the option name.
1547 VALUE is the option value.
1548 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1549 whether the option value is 'yes' or 'no' respectively. */
1551 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1555 else if (!strcmp (value, "yes"))
1557 else if (!strcmp (value, "no"))
1560 error ("unknown -m%s= option specified: '%s'", name, value);
1563 /* Validate and record the size specified with the -mtls-size option. */
1566 rs6000_parse_tls_size_option (void)
1568 if (rs6000_tls_size_string == 0)
1570 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1571 rs6000_tls_size = 16;
1572 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1573 rs6000_tls_size = 32;
1574 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1575 rs6000_tls_size = 64;
1577 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1581 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1583 if (DEFAULT_ABI == ABI_DARWIN)
1584 /* The Darwin libraries never set errno, so we might as well
1585 avoid calling them when that's the only reason we would. */
1586 flag_errno_math = 0;
1588 /* Double growth factor to counter reduced min jump length. */
1589 set_param_value ("max-grow-copy-bb-insns", 16);
1592 /* Implement TARGET_HANDLE_OPTION. */
1595 rs6000_handle_option (size_t code, const char *arg, int value)
1600 target_flags &= ~(MASK_POWER | MASK_POWER2
1601 | MASK_MULTIPLE | MASK_STRING);
1602 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1603 | MASK_MULTIPLE | MASK_STRING);
1605 case OPT_mno_powerpc:
1606 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1607 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1608 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1609 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1612 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1613 | MASK_NO_SUM_IN_TOC);
1614 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1615 | MASK_NO_SUM_IN_TOC);
1616 #ifdef TARGET_USES_SYSV4_OPT
1617 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1618 just the same as -mminimal-toc. */
1619 target_flags |= MASK_MINIMAL_TOC;
1620 target_flags_explicit |= MASK_MINIMAL_TOC;
1624 #ifdef TARGET_USES_SYSV4_OPT
1626 /* Make -mtoc behave like -mminimal-toc. */
1627 target_flags |= MASK_MINIMAL_TOC;
1628 target_flags_explicit |= MASK_MINIMAL_TOC;
1632 #ifdef TARGET_USES_AIX64_OPT
1637 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1638 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1639 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1642 #ifdef TARGET_USES_AIX64_OPT
1647 target_flags &= ~MASK_POWERPC64;
1648 target_flags_explicit |= MASK_POWERPC64;
1651 case OPT_minsert_sched_nops_:
1652 rs6000_sched_insert_nops_str = arg;
1655 case OPT_mminimal_toc:
1658 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1659 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1666 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1667 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1674 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1675 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1679 case OPT_mpowerpc_gpopt:
1680 case OPT_mpowerpc_gfxopt:
1683 target_flags |= MASK_POWERPC;
1684 target_flags_explicit |= MASK_POWERPC;
1688 case OPT_maix_struct_return:
1689 case OPT_msvr4_struct_return:
1690 rs6000_explicit_options.aix_struct_ret = true;
1694 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1698 rs6000_explicit_options.isel = true;
1699 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1703 rs6000_explicit_options.spe = true;
1704 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1705 /* No SPE means 64-bit long doubles, even if an E500. */
1707 rs6000_long_double_type_size = 64;
1711 rs6000_debug_name = arg;
1714 #ifdef TARGET_USES_SYSV4_OPT
1716 rs6000_abi_name = arg;
1720 rs6000_sdata_name = arg;
1723 case OPT_mtls_size_:
1724 rs6000_tls_size_string = arg;
1727 case OPT_mrelocatable:
1730 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1731 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1735 case OPT_mrelocatable_lib:
1738 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1739 | MASK_NO_FP_IN_TOC;
1740 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1741 | MASK_NO_FP_IN_TOC;
1745 target_flags &= ~MASK_RELOCATABLE;
1746 target_flags_explicit |= MASK_RELOCATABLE;
1752 rs6000_explicit_options.abi = true;
1753 if (!strcmp (arg, "altivec"))
1755 rs6000_altivec_abi = 1;
1758 else if (! strcmp (arg, "no-altivec"))
1759 rs6000_altivec_abi = 0;
1760 else if (! strcmp (arg, "spe"))
1763 rs6000_altivec_abi = 0;
1764 if (!TARGET_SPE_ABI)
1765 error ("not configured for ABI: '%s'", arg);
1767 else if (! strcmp (arg, "no-spe"))
1770 /* These are here for testing during development only, do not
1771 document in the manual please. */
1772 else if (! strcmp (arg, "d64"))
1774 rs6000_darwin64_abi = 1;
1775 warning (0, "Using darwin64 ABI");
1777 else if (! strcmp (arg, "d32"))
1779 rs6000_darwin64_abi = 0;
1780 warning (0, "Using old darwin ABI");
1785 error ("unknown ABI specified: '%s'", arg);
1791 rs6000_select[1].string = arg;
1795 rs6000_select[2].string = arg;
1798 case OPT_mtraceback_:
1799 rs6000_traceback_name = arg;
1802 case OPT_mfloat_gprs_:
1803 rs6000_explicit_options.float_gprs = true;
1804 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1805 rs6000_float_gprs = 1;
1806 else if (! strcmp (arg, "double"))
1807 rs6000_float_gprs = 2;
1808 else if (! strcmp (arg, "no"))
1809 rs6000_float_gprs = 0;
1812 error ("invalid option for -mfloat-gprs: '%s'", arg);
1817 case OPT_mlong_double_:
1818 rs6000_explicit_options.long_double = true;
1819 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1820 if (value != 64 && value != 128)
1822 error ("Unknown switch -mlong-double-%s", arg);
1823 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1827 rs6000_long_double_type_size = value;
1830 case OPT_msched_costly_dep_:
1831 rs6000_sched_costly_dep_str = arg;
1835 rs6000_explicit_options.alignment = true;
1836 if (! strcmp (arg, "power"))
1838 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1839 some C library functions, so warn about it. The flag may be
1840 useful for performance studies from time to time though, so
1841 don't disable it entirely. */
1842 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1843 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1844 " it is incompatible with the installed C and C++ libraries");
1845 rs6000_alignment_flags = MASK_ALIGN_POWER;
1847 else if (! strcmp (arg, "natural"))
1848 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1851 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1859 /* Do anything needed at the start of the asm file. */
1862 rs6000_file_start (void)
1866 const char *start = buffer;
1867 struct rs6000_cpu_select *ptr;
1868 const char *default_cpu = TARGET_CPU_DEFAULT;
1869 FILE *file = asm_out_file;
1871 default_file_start ();
1873 #ifdef TARGET_BI_ARCH
1874 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1878 if (flag_verbose_asm)
1880 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1881 rs6000_select[0].string = default_cpu;
1883 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1885 ptr = &rs6000_select[i];
1886 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1888 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1893 if (PPC405_ERRATUM77)
1895 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1899 #ifdef USING_ELFOS_H
1900 switch (rs6000_sdata)
1902 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1903 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1904 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1905 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1908 if (rs6000_sdata && g_switch_value)
1910 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1920 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1922 switch_to_section (toc_section);
1923 switch_to_section (text_section);
1928 /* Return nonzero if this function is known to have a null epilogue. */
1931 direct_return (void)
1933 if (reload_completed)
1935 rs6000_stack_t *info = rs6000_stack_info ();
1937 if (info->first_gp_reg_save == 32
1938 && info->first_fp_reg_save == 64
1939 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1940 && ! info->lr_save_p
1941 && ! info->cr_save_p
1942 && info->vrsave_mask == 0
1950 /* Return the number of instructions it takes to form a constant in an
1951 integer register. */
1954 num_insns_constant_wide (HOST_WIDE_INT value)
1956 /* signed constant loadable with {cal|addi} */
1957 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1960 /* constant loadable with {cau|addis} */
1961 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1964 #if HOST_BITS_PER_WIDE_INT == 64
1965 else if (TARGET_POWERPC64)
1967 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1968 HOST_WIDE_INT high = value >> 31;
1970 if (high == 0 || high == -1)
1976 return num_insns_constant_wide (high) + 1;
1978 return (num_insns_constant_wide (high)
1979 + num_insns_constant_wide (low) + 1);
1988 num_insns_constant (rtx op, enum machine_mode mode)
1990 HOST_WIDE_INT low, high;
1992 switch (GET_CODE (op))
1995 #if HOST_BITS_PER_WIDE_INT == 64
1996 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1997 && mask64_operand (op, mode))
2001 return num_insns_constant_wide (INTVAL (op));
2009 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2010 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2011 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2014 if (mode == VOIDmode || mode == DImode)
2016 high = CONST_DOUBLE_HIGH (op);
2017 low = CONST_DOUBLE_LOW (op);
2024 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2025 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2026 high = l[WORDS_BIG_ENDIAN == 0];
2027 low = l[WORDS_BIG_ENDIAN != 0];
2031 return (num_insns_constant_wide (low)
2032 + num_insns_constant_wide (high));
2035 if ((high == 0 && low >= 0)
2036 || (high == -1 && low < 0))
2037 return num_insns_constant_wide (low);
2039 else if (mask64_operand (op, mode))
2043 return num_insns_constant_wide (high) + 1;
2046 return (num_insns_constant_wide (high)
2047 + num_insns_constant_wide (low) + 1);
2056 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2057 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2058 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2059 all items are set to the same value and contain COPIES replicas of the
2060 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2061 operand and the others are set to the value of the operand's msb. */
2064 vspltis_constant (rtx op, unsigned step, unsigned copies)
2066 enum machine_mode mode = GET_MODE (op);
2067 enum machine_mode inner = GET_MODE_INNER (mode);
2070 unsigned nunits = GET_MODE_NUNITS (mode);
2071 unsigned bitsize = GET_MODE_BITSIZE (inner);
2072 unsigned mask = GET_MODE_MASK (inner);
2074 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2075 HOST_WIDE_INT val = INTVAL (last);
2076 HOST_WIDE_INT splat_val = val;
2077 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2079 /* Construct the value to be splatted, if possible. If not, return 0. */
2080 for (i = 2; i <= copies; i *= 2)
2082 HOST_WIDE_INT small_val;
2084 small_val = splat_val >> bitsize;
2086 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2088 splat_val = small_val;
2091 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2092 if (EASY_VECTOR_15 (splat_val))
2095 /* Also check if we can splat, and then add the result to itself. Do so if
2096 the value is positive, of if the splat instruction is using OP's mode;
2097 for splat_val < 0, the splat and the add should use the same mode. */
2098 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2099 && (splat_val >= 0 || (step == 1 && copies == 1)))
2105 /* Check if VAL is present in every STEP-th element, and the
2106 other elements are filled with its most significant bit. */
2107 for (i = 0; i < nunits - 1; ++i)
2109 HOST_WIDE_INT desired_val;
2110 if (((i + 1) & (step - 1)) == 0)
2113 desired_val = msb_val;
2115 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2123 /* Return true if OP is of the given MODE and can be synthesized
2124 with a vspltisb, vspltish or vspltisw. */
2127 easy_altivec_constant (rtx op, enum machine_mode mode)
2129 unsigned step, copies;
2131 if (mode == VOIDmode)
2132 mode = GET_MODE (op);
2133 else if (mode != GET_MODE (op))
2136 /* Start with a vspltisw. */
2137 step = GET_MODE_NUNITS (mode) / 4;
2140 if (vspltis_constant (op, step, copies))
2143 /* Then try with a vspltish. */
2149 if (vspltis_constant (op, step, copies))
2152 /* And finally a vspltisb. */
2158 if (vspltis_constant (op, step, copies))
2164 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2165 result is OP. Abort if it is not possible. */
2168 gen_easy_altivec_constant (rtx op)
2170 enum machine_mode mode = GET_MODE (op);
2171 int nunits = GET_MODE_NUNITS (mode);
2172 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2173 unsigned step = nunits / 4;
2174 unsigned copies = 1;
2176 /* Start with a vspltisw. */
2177 if (vspltis_constant (op, step, copies))
2178 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2180 /* Then try with a vspltish. */
2186 if (vspltis_constant (op, step, copies))
2187 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2189 /* And finally a vspltisb. */
2195 if (vspltis_constant (op, step, copies))
2196 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2202 output_vec_const_move (rtx *operands)
2205 enum machine_mode mode;
2210 mode = GET_MODE (dest);
2215 if (zero_constant (vec, mode))
2216 return "vxor %0,%0,%0";
2218 splat_vec = gen_easy_altivec_constant (vec);
2219 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2220 operands[1] = XEXP (splat_vec, 0);
2221 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2224 switch (GET_MODE (splat_vec))
2227 return "vspltisw %0,%1";
2230 return "vspltish %0,%1";
2233 return "vspltisb %0,%1";
2240 gcc_assert (TARGET_SPE);
2242 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2243 pattern of V1DI, V4HI, and V2SF.
2245 FIXME: We should probably return # and add post reload
2246 splitters for these, but this way is so easy ;-). */
2247 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2248 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2249 operands[1] = CONST_VECTOR_ELT (vec, 0);
2250 operands[2] = CONST_VECTOR_ELT (vec, 1);
2252 return "li %0,%1\n\tevmergelo %0,%0,%0";
2254 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2257 /* Initialize vector TARGET to VALS. */
2260 rs6000_expand_vector_init (rtx target, rtx vals)
2262 enum machine_mode mode = GET_MODE (target);
2263 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2264 int n_elts = GET_MODE_NUNITS (mode);
2265 int n_var = 0, one_var = -1;
2266 bool all_same = true, all_const_zero = true;
2270 for (i = 0; i < n_elts; ++i)
2272 x = XVECEXP (vals, 0, i);
2273 if (!CONSTANT_P (x))
2274 ++n_var, one_var = i;
2275 else if (x != CONST0_RTX (inner_mode))
2276 all_const_zero = false;
2278 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2284 if (mode != V4SFmode && all_const_zero)
2286 /* Zero register. */
2287 emit_insn (gen_rtx_SET (VOIDmode, target,
2288 gen_rtx_XOR (mode, target, target)));
2291 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2293 /* Splat immediate. */
2294 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2298 ; /* Splat vector element. */
2301 /* Load from constant pool. */
2302 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2307 /* Store value to stack temp. Load vector element. Splat. */
2310 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2311 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2312 XVECEXP (vals, 0, 0));
2313 x = gen_rtx_UNSPEC (VOIDmode,
2314 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2315 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2317 gen_rtx_SET (VOIDmode,
2320 x = gen_rtx_VEC_SELECT (inner_mode, target,
2321 gen_rtx_PARALLEL (VOIDmode,
2322 gen_rtvec (1, const0_rtx)));
2323 emit_insn (gen_rtx_SET (VOIDmode, target,
2324 gen_rtx_VEC_DUPLICATE (mode, x)));
2328 /* One field is non-constant. Load constant then overwrite
2332 rtx copy = copy_rtx (vals);
2334 /* Load constant part of vector, substitute neighboring value for
2336 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2337 rs6000_expand_vector_init (target, copy);
2339 /* Insert variable. */
2340 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2344 /* Construct the vector in memory one field at a time
2345 and load the whole vector. */
2346 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2347 for (i = 0; i < n_elts; i++)
2348 emit_move_insn (adjust_address_nv (mem, inner_mode,
2349 i * GET_MODE_SIZE (inner_mode)),
2350 XVECEXP (vals, 0, i));
2351 emit_move_insn (target, mem);
2354 /* Set field ELT of TARGET to VAL. */
2357 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2359 enum machine_mode mode = GET_MODE (target);
2360 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2361 rtx reg = gen_reg_rtx (mode);
2363 int width = GET_MODE_SIZE (inner_mode);
2366 /* Load single variable value. */
2367 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2368 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2369 x = gen_rtx_UNSPEC (VOIDmode,
2370 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2371 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2373 gen_rtx_SET (VOIDmode,
2377 /* Linear sequence. */
2378 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2379 for (i = 0; i < 16; ++i)
2380 XVECEXP (mask, 0, i) = GEN_INT (i);
2382 /* Set permute mask to insert element into target. */
2383 for (i = 0; i < width; ++i)
2384 XVECEXP (mask, 0, elt*width + i)
2385 = GEN_INT (i + 0x10);
2386 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2387 x = gen_rtx_UNSPEC (mode,
2388 gen_rtvec (3, target, reg,
2389 force_reg (V16QImode, x)),
2391 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2394 /* Extract field ELT from VEC into TARGET. */
2397 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2399 enum machine_mode mode = GET_MODE (vec);
2400 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2403 /* Allocate mode-sized buffer. */
2404 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2406 /* Add offset to field within buffer matching vector element. */
2407 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2409 /* Store single field into mode-sized buffer. */
2410 x = gen_rtx_UNSPEC (VOIDmode,
2411 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2412 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2414 gen_rtx_SET (VOIDmode,
2417 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2420 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2421 implement ANDing by the mask IN. */
2423 build_mask64_2_operands (rtx in, rtx *out)
2425 #if HOST_BITS_PER_WIDE_INT >= 64
2426 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2429 gcc_assert (GET_CODE (in) == CONST_INT);
2434 /* Assume c initially something like 0x00fff000000fffff. The idea
2435 is to rotate the word so that the middle ^^^^^^ group of zeros
2436 is at the MS end and can be cleared with an rldicl mask. We then
2437 rotate back and clear off the MS ^^ group of zeros with a
2439 c = ~c; /* c == 0xff000ffffff00000 */
2440 lsb = c & -c; /* lsb == 0x0000000000100000 */
2441 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2442 c = ~c; /* c == 0x00fff000000fffff */
2443 c &= -lsb; /* c == 0x00fff00000000000 */
2444 lsb = c & -c; /* lsb == 0x0000100000000000 */
2445 c = ~c; /* c == 0xff000fffffffffff */
2446 c &= -lsb; /* c == 0xff00000000000000 */
2448 while ((lsb >>= 1) != 0)
2449 shift++; /* shift == 44 on exit from loop */
2450 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2451 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2452 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2456 /* Assume c initially something like 0xff000f0000000000. The idea
2457 is to rotate the word so that the ^^^ middle group of zeros
2458 is at the LS end and can be cleared with an rldicr mask. We then
2459 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2461 lsb = c & -c; /* lsb == 0x0000010000000000 */
2462 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2463 c = ~c; /* c == 0x00fff0ffffffffff */
2464 c &= -lsb; /* c == 0x00fff00000000000 */
2465 lsb = c & -c; /* lsb == 0x0000100000000000 */
2466 c = ~c; /* c == 0xff000fffffffffff */
2467 c &= -lsb; /* c == 0xff00000000000000 */
2469 while ((lsb >>= 1) != 0)
2470 shift++; /* shift == 44 on exit from loop */
2471 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2472 m1 >>= shift; /* m1 == 0x0000000000000fff */
2473 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2476 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2477 masks will be all 1's. We are guaranteed more than one transition. */
2478 out[0] = GEN_INT (64 - shift);
2479 out[1] = GEN_INT (m1);
2480 out[2] = GEN_INT (shift);
2481 out[3] = GEN_INT (m2);
2489 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2492 invalid_e500_subreg (rtx op, enum machine_mode mode)
2494 /* Reject (subreg:SI (reg:DF)). */
2495 if (GET_CODE (op) == SUBREG
2497 && REG_P (SUBREG_REG (op))
2498 && GET_MODE (SUBREG_REG (op)) == DFmode)
2501 /* Reject (subreg:DF (reg:DI)). */
2502 if (GET_CODE (op) == SUBREG
2504 && REG_P (SUBREG_REG (op))
2505 && GET_MODE (SUBREG_REG (op)) == DImode)
2511 /* Darwin, AIX increases natural record alignment to doubleword if the first
2512 field is an FP double while the FP fields remain word aligned. */
2515 rs6000_special_round_type_align (tree type, unsigned int computed,
2516 unsigned int specified)
2518 unsigned int align = MAX (computed, specified);
2519 tree field = TYPE_FIELDS (type);
2521 /* Skip all non field decls */
2522 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2523 field = TREE_CHAIN (field);
2525 if (field != NULL && field != type)
2527 type = TREE_TYPE (field);
2528 while (TREE_CODE (type) == ARRAY_TYPE)
2529 type = TREE_TYPE (type);
2531 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2532 align = MAX (align, 64);
2538 /* Return 1 for an operand in small memory on V.4/eabi. */
2541 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2542 enum machine_mode mode ATTRIBUTE_UNUSED)
2547 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2550 if (DEFAULT_ABI != ABI_V4)
2553 if (GET_CODE (op) == SYMBOL_REF)
2556 else if (GET_CODE (op) != CONST
2557 || GET_CODE (XEXP (op, 0)) != PLUS
2558 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2559 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2564 rtx sum = XEXP (op, 0);
2565 HOST_WIDE_INT summand;
2567 /* We have to be careful here, because it is the referenced address
2568 that must be 32k from _SDA_BASE_, not just the symbol. */
2569 summand = INTVAL (XEXP (sum, 1));
2570 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2573 sym_ref = XEXP (sum, 0);
2576 return SYMBOL_REF_SMALL_P (sym_ref);
2582 /* Return true if either operand is a general purpose register. */
2585 gpr_or_gpr_p (rtx op0, rtx op1)
2587 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2588 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2592 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2595 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2597 switch (GET_CODE (op))
2600 if (RS6000_SYMBOL_REF_TLS_P (op))
2602 else if (CONSTANT_POOL_ADDRESS_P (op))
2604 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2612 else if (! strcmp (XSTR (op, 0), toc_label_name))
2621 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2622 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2624 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2633 constant_pool_expr_p (rtx op)
2637 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2641 toc_relative_expr_p (rtx op)
2645 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2649 legitimate_constant_pool_address_p (rtx x)
2652 && GET_CODE (x) == PLUS
2653 && GET_CODE (XEXP (x, 0)) == REG
2654 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2655 && constant_pool_expr_p (XEXP (x, 1)));
2659 rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x)
2661 return (DEFAULT_ABI == ABI_V4
2662 && !flag_pic && !TARGET_TOC
2663 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2664 && small_data_operand (x, mode));
2667 /* SPE offset addressing is limited to 5-bits worth of double words. */
2668 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2671 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2673 unsigned HOST_WIDE_INT offset, extra;
2675 if (GET_CODE (x) != PLUS)
2677 if (GET_CODE (XEXP (x, 0)) != REG)
2679 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2681 if (legitimate_constant_pool_address_p (x))
2683 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2686 offset = INTVAL (XEXP (x, 1));
2694 /* AltiVec vector modes. Only reg+reg addressing is valid and
2695 constant offset zero should not occur due to canonicalization.
2696 Allow any offset when not strict before reload. */
2703 /* SPE vector modes. */
2704 return SPE_CONST_OFFSET_OK (offset);
2707 if (TARGET_E500_DOUBLE)
2708 return SPE_CONST_OFFSET_OK (offset);
2711 /* On e500v2, we may have:
2713 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2715 Which gets addressed with evldd instructions. */
2716 if (TARGET_E500_DOUBLE)
2717 return SPE_CONST_OFFSET_OK (offset);
2719 if (mode == DFmode || !TARGET_POWERPC64)
2721 else if (offset & 3)
2727 if (mode == TFmode || !TARGET_POWERPC64)
2729 else if (offset & 3)
2740 return (offset < 0x10000) && (offset + extra < 0x10000);
2744 legitimate_indexed_address_p (rtx x, int strict)
2748 if (GET_CODE (x) != PLUS)
2754 /* Recognize the rtl generated by reload which we know will later be
2755 replaced with proper base and index regs. */
2757 && reload_in_progress
2758 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2762 return (REG_P (op0) && REG_P (op1)
2763 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2764 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2765 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2766 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2770 legitimate_indirect_address_p (rtx x, int strict)
2772 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2776 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2778 if (!TARGET_MACHO || !flag_pic
2779 || mode != SImode || GET_CODE (x) != MEM)
2783 if (GET_CODE (x) != LO_SUM)
2785 if (GET_CODE (XEXP (x, 0)) != REG)
2787 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2791 return CONSTANT_P (x);
2795 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2797 if (GET_CODE (x) != LO_SUM)
2799 if (GET_CODE (XEXP (x, 0)) != REG)
2801 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2803 /* Restrict addressing for DI because of our SUBREG hackery. */
2804 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2808 if (TARGET_ELF || TARGET_MACHO)
2810 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2814 if (GET_MODE_NUNITS (mode) != 1)
2816 if (GET_MODE_BITSIZE (mode) > 64
2817 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2818 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2821 return CONSTANT_P (x);
2828 /* Try machine-dependent ways of modifying an illegitimate address
2829 to be legitimate. If we find one, return the new, valid address.
2830 This is used from only one place: `memory_address' in explow.c.
2832 OLDX is the address as it was before break_out_memory_refs was
2833 called. In some cases it is useful to look at this to decide what
2836 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2838 It is always safe for this function to do nothing. It exists to
2839 recognize opportunities to optimize the output.
2841 On RS/6000, first check for the sum of a register with a constant
2842 integer that is out of range. If so, generate code to add the
2843 constant with the low-order 16 bits masked to the register and force
2844 this result into another register (this can be done with `cau').
2845 Then generate an address of REG+(CONST&0xffff), allowing for the
2846 possibility of bit 16 being a one.
2848 Then check for the sum of a register and something not constant, try to
2849 load the other things into a register and return the sum. */
2852 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2853 enum machine_mode mode)
2855 if (GET_CODE (x) == SYMBOL_REF)
2857 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2859 return rs6000_legitimize_tls_address (x, model);
2862 if (GET_CODE (x) == PLUS
2863 && GET_CODE (XEXP (x, 0)) == REG
2864 && GET_CODE (XEXP (x, 1)) == CONST_INT
2865 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2867 HOST_WIDE_INT high_int, low_int;
2869 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2870 high_int = INTVAL (XEXP (x, 1)) - low_int;
2871 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2872 GEN_INT (high_int)), 0);
2873 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2875 else if (GET_CODE (x) == PLUS
2876 && GET_CODE (XEXP (x, 0)) == REG
2877 && GET_CODE (XEXP (x, 1)) != CONST_INT
2878 && GET_MODE_NUNITS (mode) == 1
2879 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2881 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2883 && (TARGET_POWERPC64 || mode != DImode)
2886 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2887 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2889 else if (ALTIVEC_VECTOR_MODE (mode))
2893 /* Make sure both operands are registers. */
2894 if (GET_CODE (x) == PLUS)
2895 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2896 force_reg (Pmode, XEXP (x, 1)));
2898 reg = force_reg (Pmode, x);
2901 else if (SPE_VECTOR_MODE (mode)
2902 || (TARGET_E500_DOUBLE && (mode == DFmode
2903 || mode == DImode)))
2907 /* We accept [reg + reg] and [reg + OFFSET]. */
2909 if (GET_CODE (x) == PLUS)
2911 rtx op1 = XEXP (x, 0);
2912 rtx op2 = XEXP (x, 1);
2914 op1 = force_reg (Pmode, op1);
2916 if (GET_CODE (op2) != REG
2917 && (GET_CODE (op2) != CONST_INT
2918 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2919 op2 = force_reg (Pmode, op2);
2921 return gen_rtx_PLUS (Pmode, op1, op2);
2924 return force_reg (Pmode, x);
2930 && GET_CODE (x) != CONST_INT
2931 && GET_CODE (x) != CONST_DOUBLE
2933 && GET_MODE_NUNITS (mode) == 1
2934 && (GET_MODE_BITSIZE (mode) <= 32
2935 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2937 rtx reg = gen_reg_rtx (Pmode);
2938 emit_insn (gen_elf_high (reg, x));
2939 return gen_rtx_LO_SUM (Pmode, reg, x);
2941 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2944 && ! MACHO_DYNAMIC_NO_PIC_P
2946 && GET_CODE (x) != CONST_INT
2947 && GET_CODE (x) != CONST_DOUBLE
2949 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2953 rtx reg = gen_reg_rtx (Pmode);
2954 emit_insn (gen_macho_high (reg, x));
2955 return gen_rtx_LO_SUM (Pmode, reg, x);
2958 && constant_pool_expr_p (x)
2959 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2961 return create_TOC_reference (x);
2967 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
2968 We need to emit DTP-relative relocations. */
2971 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2976 fputs ("\t.long\t", file);
2979 fputs (DOUBLE_INT_ASM_OP, file);
2984 output_addr_const (file, x);
2985 fputs ("@dtprel+0x8000", file);
2988 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2990 static GTY(()) rtx rs6000_tls_symbol;
2992 rs6000_tls_get_addr (void)
2994 if (!rs6000_tls_symbol)
2995 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2997 return rs6000_tls_symbol;
3000 /* Construct the SYMBOL_REF for TLS GOT references. */
3002 static GTY(()) rtx rs6000_got_symbol;
3004 rs6000_got_sym (void)
3006 if (!rs6000_got_symbol)
3008 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3009 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3010 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3013 return rs6000_got_symbol;
3016 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3017 this (thread-local) address. */
3020 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3024 dest = gen_reg_rtx (Pmode);
3025 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3031 tlsreg = gen_rtx_REG (Pmode, 13);
3032 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3036 tlsreg = gen_rtx_REG (Pmode, 2);
3037 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3041 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3045 tmp = gen_reg_rtx (Pmode);
3048 tlsreg = gen_rtx_REG (Pmode, 13);
3049 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3053 tlsreg = gen_rtx_REG (Pmode, 2);
3054 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3058 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3060 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3065 rtx r3, got, tga, tmp1, tmp2, eqv;
3067 /* We currently use relocations like @got@tlsgd for tls, which
3068 means the linker will handle allocation of tls entries, placing
3069 them in the .got section. So use a pointer to the .got section,
3070 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3071 or to secondary GOT sections used by 32-bit -fPIC. */
3073 got = gen_rtx_REG (Pmode, 2);
3077 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3080 rtx gsym = rs6000_got_sym ();
3081 got = gen_reg_rtx (Pmode);
3083 rs6000_emit_move (got, gsym, Pmode);
3086 rtx tempLR, tmp3, mem;
3089 tempLR = gen_reg_rtx (Pmode);
3090 tmp1 = gen_reg_rtx (Pmode);
3091 tmp2 = gen_reg_rtx (Pmode);
3092 tmp3 = gen_reg_rtx (Pmode);
3093 mem = gen_const_mem (Pmode, tmp1);
3095 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3096 emit_move_insn (tmp1, tempLR);
3097 emit_move_insn (tmp2, mem);
3098 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3099 last = emit_move_insn (got, tmp3);
3100 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3102 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3104 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3110 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3112 r3 = gen_rtx_REG (Pmode, 3);
3114 insn = gen_tls_gd_64 (r3, got, addr);
3116 insn = gen_tls_gd_32 (r3, got, addr);
3119 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3120 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3121 insn = emit_call_insn (insn);
3122 CONST_OR_PURE_CALL_P (insn) = 1;
3123 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3124 insn = get_insns ();
3126 emit_libcall_block (insn, dest, r3, addr);
3128 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3130 r3 = gen_rtx_REG (Pmode, 3);
3132 insn = gen_tls_ld_64 (r3, got);
3134 insn = gen_tls_ld_32 (r3, got);
3137 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3138 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3139 insn = emit_call_insn (insn);
3140 CONST_OR_PURE_CALL_P (insn) = 1;
3141 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3142 insn = get_insns ();
3144 tmp1 = gen_reg_rtx (Pmode);
3145 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3147 emit_libcall_block (insn, tmp1, r3, eqv);
3148 if (rs6000_tls_size == 16)
3151 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3153 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3155 else if (rs6000_tls_size == 32)
3157 tmp2 = gen_reg_rtx (Pmode);
3159 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3161 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3164 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3166 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3170 tmp2 = gen_reg_rtx (Pmode);
3172 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3174 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3176 insn = gen_rtx_SET (Pmode, dest,
3177 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3183 /* IE, or 64 bit offset LE. */
3184 tmp2 = gen_reg_rtx (Pmode);
3186 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3188 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3191 insn = gen_tls_tls_64 (dest, tmp2, addr);
3193 insn = gen_tls_tls_32 (dest, tmp2, addr);
3201 /* Return 1 if X contains a thread-local symbol. */
3204 rs6000_tls_referenced_p (rtx x)
3206 if (! TARGET_HAVE_TLS)
3209 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3212 /* Return 1 if *X is a thread-local symbol. This is the same as
3213 rs6000_tls_symbol_ref except for the type of the unused argument. */
3216 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3218 return RS6000_SYMBOL_REF_TLS_P (*x);
3221 /* The convention appears to be to define this wherever it is used.
3222 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3223 is now used here. */
3224 #ifndef REG_MODE_OK_FOR_BASE_P
3225 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3228 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3229 replace the input X, or the original X if no replacement is called for.
3230 The output parameter *WIN is 1 if the calling macro should goto WIN,
3233 For RS/6000, we wish to handle large displacements off a base
3234 register by splitting the addend across an addiu/addis and the mem insn.
3235 This cuts number of extra insns needed from 3 to 1.
3237 On Darwin, we use this to generate code for floating point constants.
3238 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3239 The Darwin code is inside #if TARGET_MACHO because only then is
3240 machopic_function_base_name() defined. */
3242 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3243 int opnum, int type,
3244 int ind_levels ATTRIBUTE_UNUSED, int *win)
3246 /* We must recognize output that we have already generated ourselves. */
3247 if (GET_CODE (x) == PLUS
3248 && GET_CODE (XEXP (x, 0)) == PLUS
3249 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3250 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3251 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3253 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3254 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3255 opnum, (enum reload_type)type);
3261 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3262 && GET_CODE (x) == LO_SUM
3263 && GET_CODE (XEXP (x, 0)) == PLUS
3264 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3265 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3266 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3267 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3268 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3269 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3270 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3272 /* Result of previous invocation of this function on Darwin
3273 floating point constant. */
3274 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3275 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3276 opnum, (enum reload_type)type);
3282 /* Force ld/std non-word aligned offset into base register by wrapping
3284 if (GET_CODE (x) == PLUS
3285 && GET_CODE (XEXP (x, 0)) == REG
3286 && REGNO (XEXP (x, 0)) < 32
3287 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3288 && GET_CODE (XEXP (x, 1)) == CONST_INT
3289 && (INTVAL (XEXP (x, 1)) & 3) != 0
3290 && !ALTIVEC_VECTOR_MODE (mode)
3291 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3292 && TARGET_POWERPC64)
3294 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3295 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3296 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3297 opnum, (enum reload_type) type);
3302 if (GET_CODE (x) == PLUS
3303 && GET_CODE (XEXP (x, 0)) == REG
3304 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3305 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3306 && GET_CODE (XEXP (x, 1)) == CONST_INT
3307 && !SPE_VECTOR_MODE (mode)
3308 && !(TARGET_E500_DOUBLE && (mode == DFmode
3310 && !ALTIVEC_VECTOR_MODE (mode))
3312 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3313 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3315 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3317 /* Check for 32-bit overflow. */
3318 if (high + low != val)
3324 /* Reload the high part into a base reg; leave the low part
3325 in the mem directly. */
3327 x = gen_rtx_PLUS (GET_MODE (x),
3328 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3332 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3333 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3334 opnum, (enum reload_type)type);
3339 if (GET_CODE (x) == SYMBOL_REF
3340 && !ALTIVEC_VECTOR_MODE (mode)
3342 && DEFAULT_ABI == ABI_DARWIN
3343 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3345 && DEFAULT_ABI == ABI_V4
3348 /* Don't do this for TFmode, since the result isn't offsettable.
3349 The same goes for DImode without 64-bit gprs. */
3351 && (mode != DImode || TARGET_POWERPC64))
3356 rtx offset = gen_rtx_CONST (Pmode,
3357 gen_rtx_MINUS (Pmode, x,
3358 machopic_function_base_sym ()));
3359 x = gen_rtx_LO_SUM (GET_MODE (x),
3360 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3361 gen_rtx_HIGH (Pmode, offset)), offset);
3365 x = gen_rtx_LO_SUM (GET_MODE (x),
3366 gen_rtx_HIGH (Pmode, x), x);
3368 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3369 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3370 opnum, (enum reload_type)type);
3375 /* Reload an offset address wrapped by an AND that represents the
3376 masking of the lower bits. Strip the outer AND and let reload
3377 convert the offset address into an indirect address. */
3379 && ALTIVEC_VECTOR_MODE (mode)
3380 && GET_CODE (x) == AND
3381 && GET_CODE (XEXP (x, 0)) == PLUS
3382 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3383 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3384 && GET_CODE (XEXP (x, 1)) == CONST_INT
3385 && INTVAL (XEXP (x, 1)) == -16)
3393 && constant_pool_expr_p (x)
3394 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3396 (x) = create_TOC_reference (x);
3404 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3405 that is a valid memory address for an instruction.
3406 The MODE argument is the machine mode for the MEM expression
3407 that wants to use this address.
3409 On the RS/6000, there are four valid address: a SYMBOL_REF that
3410 refers to a constant pool entry of an address (or the sum of it
3411 plus a constant), a short (16-bit signed) constant plus a register,
3412 the sum of two registers, or a register indirect, possibly with an
3413 auto-increment. For DFmode and DImode with a constant plus register,
3414 we must ensure that both words are addressable or PowerPC64 with offset
3417 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3418 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3419 adjacent memory cells are accessed by adding word-sized offsets
3420 during assembly output. */
3422 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3424 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3426 && ALTIVEC_VECTOR_MODE (mode)
3427 && GET_CODE (x) == AND
3428 && GET_CODE (XEXP (x, 1)) == CONST_INT
3429 && INTVAL (XEXP (x, 1)) == -16)
3432 if (RS6000_SYMBOL_REF_TLS_P (x))
3434 if (legitimate_indirect_address_p (x, reg_ok_strict))
3436 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3437 && !ALTIVEC_VECTOR_MODE (mode)
3438 && !SPE_VECTOR_MODE (mode)
3439 /* Restrict addressing for DI because of our SUBREG hackery. */
3440 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3442 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3444 if (rs6000_legitimate_small_data_p (mode, x))
3446 if (legitimate_constant_pool_address_p (x))
3448 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3450 && GET_CODE (x) == PLUS
3451 && GET_CODE (XEXP (x, 0)) == REG
3452 && (XEXP (x, 0) == virtual_stack_vars_rtx
3453 || XEXP (x, 0) == arg_pointer_rtx)
3454 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3456 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3460 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3462 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3463 && (TARGET_POWERPC64 || mode != DImode)
3464 && legitimate_indexed_address_p (x, reg_ok_strict))
3466 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3471 /* Go to LABEL if ADDR (a legitimate address expression)
3472 has an effect that depends on the machine mode it is used for.
3474 On the RS/6000 this is true of all integral offsets (since AltiVec
3475 modes don't allow them) or is a pre-increment or decrement.
3477 ??? Except that due to conceptual problems in offsettable_address_p
3478 we can't really report the problems of integral offsets. So leave
3479 this assuming that the adjustable offset must be valid for the
3480 sub-words of a TFmode operand, which is what we had before. */
3483 rs6000_mode_dependent_address (rtx addr)
3485 switch (GET_CODE (addr))
3488 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3490 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3491 return val + 12 + 0x8000 >= 0x10000;
3500 return TARGET_UPDATE;
3509 /* Return number of consecutive hard regs needed starting at reg REGNO
3510 to hold something of mode MODE.
3511 This is ordinarily the length in words of a value of mode MODE
3512 but can be less for certain modes in special long registers.
3514 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3515 scalar instructions. The upper 32 bits are only available to the
3518 POWER and PowerPC GPRs hold 32 bits worth;
3519 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3522 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3524 if (FP_REGNO_P (regno))
3525 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3527 if (TARGET_E500_DOUBLE && mode == DFmode)
3530 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3531 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3533 if (ALTIVEC_REGNO_P (regno))
3535 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3537 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3540 /* Change register usage conditional on target flags. */
3542 rs6000_conditional_register_usage (void)
3546 /* Set MQ register fixed (already call_used) if not POWER
3547 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3552 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3554 fixed_regs[13] = call_used_regs[13]
3555 = call_really_used_regs[13] = 1;
3557 /* Conditionally disable FPRs. */
3558 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3559 for (i = 32; i < 64; i++)
3560 fixed_regs[i] = call_used_regs[i]
3561 = call_really_used_regs[i] = 1;
3563 /* The TOC register is not killed across calls in a way that is
3564 visible to the compiler. */
3565 if (DEFAULT_ABI == ABI_AIX)
3566 call_really_used_regs[2] = 0;
3568 if (DEFAULT_ABI == ABI_V4
3569 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3571 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3573 if (DEFAULT_ABI == ABI_V4
3574 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3576 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3577 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3578 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3580 if (DEFAULT_ABI == ABI_DARWIN
3581 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3582 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3583 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3584 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3586 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3587 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3588 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3591 global_regs[VSCR_REGNO] = 1;
3595 global_regs[SPEFSCR_REGNO] = 1;
3596 fixed_regs[FIXED_SCRATCH]
3597 = call_used_regs[FIXED_SCRATCH]
3598 = call_really_used_regs[FIXED_SCRATCH] = 1;
3601 if (! TARGET_ALTIVEC)
3603 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3604 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3605 call_really_used_regs[VRSAVE_REGNO] = 1;
3608 if (TARGET_ALTIVEC_ABI)
3609 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3610 call_used_regs[i] = call_really_used_regs[i] = 1;
3613 /* Try to output insns to set TARGET equal to the constant C if it can
3614 be done in less than N insns. Do all computations in MODE.
3615 Returns the place where the output has been placed if it can be
3616 done and the insns have been emitted. If it would take more than N
3617 insns, zero is returned and no insns and emitted. */
3620 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3621 rtx source, int n ATTRIBUTE_UNUSED)
3623 rtx result, insn, set;
3624 HOST_WIDE_INT c0, c1;
3631 dest = gen_reg_rtx (mode);
3632 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3636 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3638 emit_insn (gen_rtx_SET (VOIDmode, result,
3639 GEN_INT (INTVAL (source)
3640 & (~ (HOST_WIDE_INT) 0xffff))));
3641 emit_insn (gen_rtx_SET (VOIDmode, dest,
3642 gen_rtx_IOR (SImode, result,
3643 GEN_INT (INTVAL (source) & 0xffff))));
3648 switch (GET_CODE (source))
3651 c0 = INTVAL (source);
3656 #if HOST_BITS_PER_WIDE_INT >= 64
3657 c0 = CONST_DOUBLE_LOW (source);
3660 c0 = CONST_DOUBLE_LOW (source);
3661 c1 = CONST_DOUBLE_HIGH (source);
3669 result = rs6000_emit_set_long_const (dest, c0, c1);
3676 insn = get_last_insn ();
3677 set = single_set (insn);
3678 if (! CONSTANT_P (SET_SRC (set)))
3679 set_unique_reg_note (insn, REG_EQUAL, source);
3684 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3685 fall back to a straight forward decomposition. We do this to avoid
3686 exponential run times encountered when looking for longer sequences
3687 with rs6000_emit_set_const. */
3689 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3691 if (!TARGET_POWERPC64)
3693 rtx operand1, operand2;
3695 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3697 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3699 emit_move_insn (operand1, GEN_INT (c1));
3700 emit_move_insn (operand2, GEN_INT (c2));
3704 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3707 ud2 = (c1 & 0xffff0000) >> 16;
3708 #if HOST_BITS_PER_WIDE_INT >= 64
3712 ud4 = (c2 & 0xffff0000) >> 16;
3714 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3715 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3718 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3720 emit_move_insn (dest, GEN_INT (ud1));
3723 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3724 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3727 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3730 emit_move_insn (dest, GEN_INT (ud2 << 16));
3732 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3734 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3735 || (ud4 == 0 && ! (ud3 & 0x8000)))
3738 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3741 emit_move_insn (dest, GEN_INT (ud3 << 16));
3744 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3745 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3747 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3752 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3755 emit_move_insn (dest, GEN_INT (ud4 << 16));
3758 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3760 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3762 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3763 GEN_INT (ud2 << 16)));
3765 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3771 /* Helper for the following. Get rid of [r+r] memory refs
3772 in cases where it won't work (TImode, TFmode). */
3775 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3777 if (GET_CODE (operands[0]) == MEM
3778 && GET_CODE (XEXP (operands[0], 0)) != REG
3779 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3780 && ! reload_in_progress)
3782 = replace_equiv_address (operands[0],
3783 copy_addr_to_reg (XEXP (operands[0], 0)));
3785 if (GET_CODE (operands[1]) == MEM
3786 && GET_CODE (XEXP (operands[1], 0)) != REG
3787 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3788 && ! reload_in_progress)
3790 = replace_equiv_address (operands[1],
3791 copy_addr_to_reg (XEXP (operands[1], 0)));
3794 /* Emit a move from SOURCE to DEST in mode MODE. */
3796 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3800 operands[1] = source;
3802 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3803 if (GET_CODE (operands[1]) == CONST_DOUBLE
3804 && ! FLOAT_MODE_P (mode)
3805 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3807 /* FIXME. This should never happen. */
3808 /* Since it seems that it does, do the safe thing and convert
3810 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3812 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3813 || FLOAT_MODE_P (mode)
3814 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3815 || CONST_DOUBLE_LOW (operands[1]) < 0)
3816 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3817 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3819 /* Check if GCC is setting up a block move that will end up using FP
3820 registers as temporaries. We must make sure this is acceptable. */
3821 if (GET_CODE (operands[0]) == MEM
3822 && GET_CODE (operands[1]) == MEM
3824 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3825 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3826 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3827 ? 32 : MEM_ALIGN (operands[0])))
3828 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3830 : MEM_ALIGN (operands[1]))))
3831 && ! MEM_VOLATILE_P (operands [0])
3832 && ! MEM_VOLATILE_P (operands [1]))
3834 emit_move_insn (adjust_address (operands[0], SImode, 0),
3835 adjust_address (operands[1], SImode, 0));
3836 emit_move_insn (adjust_address (operands[0], SImode, 4),
3837 adjust_address (operands[1], SImode, 4));
3841 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3842 && !gpc_reg_operand (operands[1], mode))
3843 operands[1] = force_reg (mode, operands[1]);
3845 if (mode == SFmode && ! TARGET_POWERPC
3846 && TARGET_HARD_FLOAT && TARGET_FPRS
3847 && GET_CODE (operands[0]) == MEM)
3851 if (reload_in_progress || reload_completed)
3852 regnum = true_regnum (operands[1]);
3853 else if (GET_CODE (operands[1]) == REG)
3854 regnum = REGNO (operands[1]);
3858 /* If operands[1] is a register, on POWER it may have
3859 double-precision data in it, so truncate it to single
3861 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3864 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3865 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3866 operands[1] = newreg;
3870 /* Recognize the case where operand[1] is a reference to thread-local
3871 data and load its address to a register. */
3872 if (rs6000_tls_referenced_p (operands[1]))
3874 enum tls_model model;
3875 rtx tmp = operands[1];
3878 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3880 addend = XEXP (XEXP (tmp, 0), 1);
3881 tmp = XEXP (XEXP (tmp, 0), 0);
3884 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3885 model = SYMBOL_REF_TLS_MODEL (tmp);
3886 gcc_assert (model != 0);
3888 tmp = rs6000_legitimize_tls_address (tmp, model);
3891 tmp = gen_rtx_PLUS (mode, tmp, addend);
3892 tmp = force_operand (tmp, operands[0]);
3897 /* Handle the case where reload calls us with an invalid address. */
3898 if (reload_in_progress && mode == Pmode
3899 && (! general_operand (operands[1], mode)
3900 || ! nonimmediate_operand (operands[0], mode)))
3903 /* 128-bit constant floating-point values on Darwin should really be
3904 loaded as two parts. */
3905 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3906 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3907 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3909 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3910 know how to get a DFmode SUBREG of a TFmode. */
3911 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3912 simplify_gen_subreg (DImode, operands[1], mode, 0),
3914 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3915 GET_MODE_SIZE (DImode)),
3916 simplify_gen_subreg (DImode, operands[1], mode,
3917 GET_MODE_SIZE (DImode)),
3922 /* FIXME: In the long term, this switch statement should go away
3923 and be replaced by a sequence of tests based on things like
3929 if (CONSTANT_P (operands[1])
3930 && GET_CODE (operands[1]) != CONST_INT)
3931 operands[1] = force_const_mem (mode, operands[1]);
3935 rs6000_eliminate_indexed_memrefs (operands);
3940 if (CONSTANT_P (operands[1])
3941 && ! easy_fp_constant (operands[1], mode))
3942 operands[1] = force_const_mem (mode, operands[1]);
3953 if (CONSTANT_P (operands[1])
3954 && !easy_vector_constant (operands[1], mode))
3955 operands[1] = force_const_mem (mode, operands[1]);
3960 /* Use default pattern for address of ELF small data */
3963 && DEFAULT_ABI == ABI_V4
3964 && (GET_CODE (operands[1]) == SYMBOL_REF
3965 || GET_CODE (operands[1]) == CONST)
3966 && small_data_operand (operands[1], mode))
3968 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3972 if (DEFAULT_ABI == ABI_V4
3973 && mode == Pmode && mode == SImode
3974 && flag_pic == 1 && got_operand (operands[1], mode))
3976 emit_insn (gen_movsi_got (operands[0], operands[1]));
3980 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3984 && CONSTANT_P (operands[1])
3985 && GET_CODE (operands[1]) != HIGH
3986 && GET_CODE (operands[1]) != CONST_INT)
3988 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3990 /* If this is a function address on -mcall-aixdesc,
3991 convert it to the address of the descriptor. */
3992 if (DEFAULT_ABI == ABI_AIX
3993 && GET_CODE (operands[1]) == SYMBOL_REF
3994 && XSTR (operands[1], 0)[0] == '.')
3996 const char *name = XSTR (operands[1], 0);
3998 while (*name == '.')
4000 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4001 CONSTANT_POOL_ADDRESS_P (new_ref)
4002 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4003 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4004 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4005 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4006 operands[1] = new_ref;
4009 if (DEFAULT_ABI == ABI_DARWIN)
4012 if (MACHO_DYNAMIC_NO_PIC_P)
4014 /* Take care of any required data indirection. */
4015 operands[1] = rs6000_machopic_legitimize_pic_address (
4016 operands[1], mode, operands[0]);
4017 if (operands[0] != operands[1])
4018 emit_insn (gen_rtx_SET (VOIDmode,
4019 operands[0], operands[1]));
4023 emit_insn (gen_macho_high (target, operands[1]));
4024 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4028 emit_insn (gen_elf_high (target, operands[1]));
4029 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4033 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4034 and we have put it in the TOC, we just need to make a TOC-relative
4037 && GET_CODE (operands[1]) == SYMBOL_REF
4038 && constant_pool_expr_p (operands[1])
4039 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4040 get_pool_mode (operands[1])))
4042 operands[1] = create_TOC_reference (operands[1]);
4044 else if (mode == Pmode
4045 && CONSTANT_P (operands[1])
4046 && ((GET_CODE (operands[1]) != CONST_INT
4047 && ! easy_fp_constant (operands[1], mode))
4048 || (GET_CODE (operands[1]) == CONST_INT
4049 && num_insns_constant (operands[1], mode) > 2)
4050 || (GET_CODE (operands[0]) == REG
4051 && FP_REGNO_P (REGNO (operands[0]))))
4052 && GET_CODE (operands[1]) != HIGH
4053 && ! legitimate_constant_pool_address_p (operands[1])
4054 && ! toc_relative_expr_p (operands[1]))
4056 /* Emit a USE operation so that the constant isn't deleted if
4057 expensive optimizations are turned on because nobody
4058 references it. This should only be done for operands that
4059 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4060 This should not be done for operands that contain LABEL_REFs.
4061 For now, we just handle the obvious case. */
4062 if (GET_CODE (operands[1]) != LABEL_REF)
4063 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4066 /* Darwin uses a special PIC legitimizer. */
4067 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4070 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4072 if (operands[0] != operands[1])
4073 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4078 /* If we are to limit the number of things we put in the TOC and
4079 this is a symbol plus a constant we can add in one insn,
4080 just put the symbol in the TOC and add the constant. Don't do
4081 this if reload is in progress. */
4082 if (GET_CODE (operands[1]) == CONST
4083 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4084 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4085 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4086 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4087 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4088 && ! side_effects_p (operands[0]))
4091 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4092 rtx other = XEXP (XEXP (operands[1], 0), 1);
4094 sym = force_reg (mode, sym);
4096 emit_insn (gen_addsi3 (operands[0], sym, other));
4098 emit_insn (gen_adddi3 (operands[0], sym, other));
4102 operands[1] = force_const_mem (mode, operands[1]);
4105 && constant_pool_expr_p (XEXP (operands[1], 0))
4106 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4107 get_pool_constant (XEXP (operands[1], 0)),
4108 get_pool_mode (XEXP (operands[1], 0))))
4111 = gen_const_mem (mode,
4112 create_TOC_reference (XEXP (operands[1], 0)));
4113 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4119 rs6000_eliminate_indexed_memrefs (operands);
4123 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4125 gen_rtx_SET (VOIDmode,
4126 operands[0], operands[1]),
4127 gen_rtx_CLOBBER (VOIDmode,
4128 gen_rtx_SCRATCH (SImode)))));
4137 /* Above, we may have called force_const_mem which may have returned
4138 an invalid address. If we can, fix this up; otherwise, reload will
4139 have to deal with it. */
4140 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4141 operands[1] = validize_mem (operands[1]);
4144 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4147 /* Nonzero if we can use a floating-point register to pass this arg. */
4148 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4149 (SCALAR_FLOAT_MODE_P (MODE) \
4150 && !DECIMAL_FLOAT_MODE_P (MODE) \
4151 && (CUM)->fregno <= FP_ARG_MAX_REG \
4152 && TARGET_HARD_FLOAT && TARGET_FPRS)
4154 /* Nonzero if we can use an AltiVec register to pass this arg. */
4155 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4156 (ALTIVEC_VECTOR_MODE (MODE) \
4157 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4158 && TARGET_ALTIVEC_ABI \
4161 /* Return a nonzero value to say to return the function value in
4162 memory, just as large structures are always returned. TYPE will be
4163 the data type of the value, and FNTYPE will be the type of the
4164 function doing the returning, or @code{NULL} for libcalls.
4166 The AIX ABI for the RS/6000 specifies that all structures are
4167 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4168 specifies that structures <= 8 bytes are returned in r3/r4, but a
4169 draft put them in memory, and GCC used to implement the draft
4170 instead of the final standard. Therefore, aix_struct_return
4171 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4172 compatibility can change DRAFT_V4_STRUCT_RET to override the
4173 default, and -m switches get the final word. See
4174 rs6000_override_options for more details.
4176 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4177 long double support is enabled. These values are returned in memory.
4179 int_size_in_bytes returns -1 for variable size objects, which go in
4180 memory always. The cast to unsigned makes -1 > 8. */
4183 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4185 /* In the darwin64 abi, try to use registers for larger structs
4187 if (rs6000_darwin64_abi
4188 && TREE_CODE (type) == RECORD_TYPE
4189 && int_size_in_bytes (type) > 0)
4191 CUMULATIVE_ARGS valcum;
4195 valcum.fregno = FP_ARG_MIN_REG;
4196 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4197 /* Do a trial code generation as if this were going to be passed
4198 as an argument; if any part goes in memory, we return NULL. */
4199 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4202 /* Otherwise fall through to more conventional ABI rules. */
4205 if (AGGREGATE_TYPE_P (type)
4206 && (aix_struct_return
4207 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4210 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4211 modes only exist for GCC vector types if -maltivec. */
4212 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4213 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4216 /* Return synthetic vectors in memory. */
4217 if (TREE_CODE (type) == VECTOR_TYPE
4218 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4220 static bool warned_for_return_big_vectors = false;
4221 if (!warned_for_return_big_vectors)
4223 warning (0, "GCC vector returned by reference: "
4224 "non-standard ABI extension with no compatibility guarantee");
4225 warned_for_return_big_vectors = true;
4230 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4236 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4237 for a call to a function whose data type is FNTYPE.
4238 For a library call, FNTYPE is 0.
4240 For incoming args we set the number of arguments in the prototype large
4241 so we never return a PARALLEL. */
4244 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4245 rtx libname ATTRIBUTE_UNUSED, int incoming,
4246 int libcall, int n_named_args)
4248 static CUMULATIVE_ARGS zero_cumulative;
4250 *cum = zero_cumulative;
4252 cum->fregno = FP_ARG_MIN_REG;
4253 cum->vregno = ALTIVEC_ARG_MIN_REG;
4254 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4255 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4256 ? CALL_LIBCALL : CALL_NORMAL);
4257 cum->sysv_gregno = GP_ARG_MIN_REG;
4258 cum->stdarg = fntype
4259 && (TYPE_ARG_TYPES (fntype) != 0
4260 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4261 != void_type_node));
4263 cum->nargs_prototype = 0;
4264 if (incoming || cum->prototype)
4265 cum->nargs_prototype = n_named_args;
4267 /* Check for a longcall attribute. */
4268 if ((!fntype && rs6000_default_long_calls)
4270 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4271 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4272 cum->call_cookie |= CALL_LONG;
4274 if (TARGET_DEBUG_ARG)
4276 fprintf (stderr, "\ninit_cumulative_args:");
4279 tree ret_type = TREE_TYPE (fntype);
4280 fprintf (stderr, " ret code = %s,",
4281 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4284 if (cum->call_cookie & CALL_LONG)
4285 fprintf (stderr, " longcall,");
4287 fprintf (stderr, " proto = %d, nargs = %d\n",
4288 cum->prototype, cum->nargs_prototype);
4293 && TARGET_ALTIVEC_ABI
4294 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4296 error ("cannot return value in vector register because"
4297 " altivec instructions are disabled, use -maltivec"
4302 /* Return true if TYPE must be passed on the stack and not in registers. */
4305 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4307 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4308 return must_pass_in_stack_var_size (mode, type);
4310 return must_pass_in_stack_var_size_or_pad (mode, type);
4313 /* If defined, a C expression which determines whether, and in which
4314 direction, to pad out an argument with extra space. The value
4315 should be of type `enum direction': either `upward' to pad above
4316 the argument, `downward' to pad below, or `none' to inhibit
4319 For the AIX ABI structs are always stored left shifted in their
4323 function_arg_padding (enum machine_mode mode, tree type)
4325 #ifndef AGGREGATE_PADDING_FIXED
4326 #define AGGREGATE_PADDING_FIXED 0
4328 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4329 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4332 if (!AGGREGATE_PADDING_FIXED)
4334 /* GCC used to pass structures of the same size as integer types as
4335 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4336 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4337 passed padded downward, except that -mstrict-align further
4338 muddied the water in that multi-component structures of 2 and 4
4339 bytes in size were passed padded upward.
4341 The following arranges for best compatibility with previous
4342 versions of gcc, but removes the -mstrict-align dependency. */
4343 if (BYTES_BIG_ENDIAN)
4345 HOST_WIDE_INT size = 0;
4347 if (mode == BLKmode)
4349 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4350 size = int_size_in_bytes (type);
4353 size = GET_MODE_SIZE (mode);
4355 if (size == 1 || size == 2 || size == 4)
4361 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4363 if (type != 0 && AGGREGATE_TYPE_P (type))
4367 /* Fall back to the default. */
4368 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4371 /* If defined, a C expression that gives the alignment boundary, in bits,
4372 of an argument with the specified mode and type. If it is not defined,
4373 PARM_BOUNDARY is used for all arguments.
4375 V.4 wants long longs to be double word aligned.
4376 Doubleword align SPE vectors.
4377 Quadword align Altivec vectors.
4378 Quadword align large synthetic vector types. */
4381 function_arg_boundary (enum machine_mode mode, tree type)
4383 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4385 else if (SPE_VECTOR_MODE (mode)
4386 || (type && TREE_CODE (type) == VECTOR_TYPE
4387 && int_size_in_bytes (type) >= 8
4388 && int_size_in_bytes (type) < 16))
4390 else if (ALTIVEC_VECTOR_MODE (mode)
4391 || (type && TREE_CODE (type) == VECTOR_TYPE
4392 && int_size_in_bytes (type) >= 16))
4394 else if (rs6000_darwin64_abi && mode == BLKmode
4395 && type && TYPE_ALIGN (type) > 64)
4398 return PARM_BOUNDARY;
4401 /* For a function parm of MODE and TYPE, return the starting word in
4402 the parameter area. NWORDS of the parameter area are already used. */
4405 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4408 unsigned int parm_offset;
4410 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4411 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4412 return nwords + (-(parm_offset + nwords) & align);
4415 /* Compute the size (in words) of a function argument. */
4417 static unsigned long
4418 rs6000_arg_size (enum machine_mode mode, tree type)
4422 if (mode != BLKmode)
4423 size = GET_MODE_SIZE (mode);
4425 size = int_size_in_bytes (type);
4428 return (size + 3) >> 2;
4430 return (size + 7) >> 3;
4433 /* Use this to flush pending int fields. */
4436 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4437 HOST_WIDE_INT bitpos)
4439 unsigned int startbit, endbit;
4440 int intregs, intoffset;
4441 enum machine_mode mode;
4443 if (cum->intoffset == -1)
4446 intoffset = cum->intoffset;
4447 cum->intoffset = -1;
4449 if (intoffset % BITS_PER_WORD != 0)
4451 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4453 if (mode == BLKmode)
4455 /* We couldn't find an appropriate mode, which happens,
4456 e.g., in packed structs when there are 3 bytes to load.
4457 Back intoffset back to the beginning of the word in this
4459 intoffset = intoffset & -BITS_PER_WORD;
4463 startbit = intoffset & -BITS_PER_WORD;
4464 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4465 intregs = (endbit - startbit) / BITS_PER_WORD;
4466 cum->words += intregs;
4469 /* The darwin64 ABI calls for us to recurse down through structs,
4470 looking for elements passed in registers. Unfortunately, we have
4471 to track int register count here also because of misalignments
4472 in powerpc alignment mode. */
4475 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4477 HOST_WIDE_INT startbitpos)
4481 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4482 if (TREE_CODE (f) == FIELD_DECL)
4484 HOST_WIDE_INT bitpos = startbitpos;
4485 tree ftype = TREE_TYPE (f);
4486 enum machine_mode mode = TYPE_MODE (ftype);
4488 if (DECL_SIZE (f) != 0
4489 && host_integerp (bit_position (f), 1))
4490 bitpos += int_bit_position (f);
4492 /* ??? FIXME: else assume zero offset. */
4494 if (TREE_CODE (ftype) == RECORD_TYPE)
4495 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4496 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4498 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4499 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4500 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4502 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4504 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4508 else if (cum->intoffset == -1)
4509 cum->intoffset = bitpos;
4513 /* Update the data in CUM to advance over an argument
4514 of mode MODE and data type TYPE.
4515 (TYPE is null for libcalls where that information may not be available.)
4517 Note that for args passed by reference, function_arg will be called
4518 with MODE and TYPE set to that of the pointer to the arg, not the arg
4522 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4523 tree type, int named, int depth)
4527 /* Only tick off an argument if we're not recursing. */
4529 cum->nargs_prototype--;
4531 if (TARGET_ALTIVEC_ABI
4532 && (ALTIVEC_VECTOR_MODE (mode)
4533 || (type && TREE_CODE (type) == VECTOR_TYPE
4534 && int_size_in_bytes (type) == 16)))
4538 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4541 if (!TARGET_ALTIVEC)
4542 error ("cannot pass argument in vector register because"
4543 " altivec instructions are disabled, use -maltivec"
4546 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4547 even if it is going to be passed in a vector register.
4548 Darwin does the same for variable-argument functions. */
4549 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4550 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4560 /* Vector parameters must be 16-byte aligned. This places
4561 them at 2 mod 4 in terms of words in 32-bit mode, since
4562 the parameter save area starts at offset 24 from the
4563 stack. In 64-bit mode, they just have to start on an
4564 even word, since the parameter save area is 16-byte
4565 aligned. Space for GPRs is reserved even if the argument
4566 will be passed in memory. */
4568 align = (2 - cum->words) & 3;
4570 align = cum->words & 1;
4571 cum->words += align + rs6000_arg_size (mode, type);
4573 if (TARGET_DEBUG_ARG)
4575 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4577 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4578 cum->nargs_prototype, cum->prototype,
4579 GET_MODE_NAME (mode));
4583 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4585 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4588 else if (rs6000_darwin64_abi
4590 && TREE_CODE (type) == RECORD_TYPE
4591 && (size = int_size_in_bytes (type)) > 0)
4593 /* Variable sized types have size == -1 and are
4594 treated as if consisting entirely of ints.
4595 Pad to 16 byte boundary if needed. */
4596 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4597 && (cum->words % 2) != 0)
4599 /* For varargs, we can just go up by the size of the struct. */
4601 cum->words += (size + 7) / 8;
4604 /* It is tempting to say int register count just goes up by
4605 sizeof(type)/8, but this is wrong in a case such as
4606 { int; double; int; } [powerpc alignment]. We have to
4607 grovel through the fields for these too. */
4609 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4610 rs6000_darwin64_record_arg_advance_flush (cum,
4611 size * BITS_PER_UNIT);
4614 else if (DEFAULT_ABI == ABI_V4)
4616 if (TARGET_HARD_FLOAT && TARGET_FPRS
4617 && (mode == SFmode || mode == DFmode))
4619 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4624 cum->words += cum->words & 1;
4625 cum->words += rs6000_arg_size (mode, type);
4630 int n_words = rs6000_arg_size (mode, type);
4631 int gregno = cum->sysv_gregno;
4633 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4634 (r7,r8) or (r9,r10). As does any other 2 word item such
4635 as complex int due to a historical mistake. */
4637 gregno += (1 - gregno) & 1;
4639 /* Multi-reg args are not split between registers and stack. */
4640 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4642 /* Long long and SPE vectors are aligned on the stack.
4643 So are other 2 word items such as complex int due to
4644 a historical mistake. */
4646 cum->words += cum->words & 1;
4647 cum->words += n_words;
4650 /* Note: continuing to accumulate gregno past when we've started
4651 spilling to the stack indicates the fact that we've started
4652 spilling to the stack to expand_builtin_saveregs. */
4653 cum->sysv_gregno = gregno + n_words;
4656 if (TARGET_DEBUG_ARG)
4658 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4659 cum->words, cum->fregno);
4660 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4661 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4662 fprintf (stderr, "mode = %4s, named = %d\n",
4663 GET_MODE_NAME (mode), named);
4668 int n_words = rs6000_arg_size (mode, type);
4669 int start_words = cum->words;
4670 int align_words = rs6000_parm_start (mode, type, start_words);
4672 cum->words = align_words + n_words;
4674 if (SCALAR_FLOAT_MODE_P (mode)
4675 && !DECIMAL_FLOAT_MODE_P (mode)
4676 && TARGET_HARD_FLOAT && TARGET_FPRS)
4677 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4679 if (TARGET_DEBUG_ARG)
4681 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4682 cum->words, cum->fregno);
4683 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4684 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4685 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4686 named, align_words - start_words, depth);
4692 spe_build_register_parallel (enum machine_mode mode, int gregno)
4699 r1 = gen_rtx_REG (DImode, gregno);
4700 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4701 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4704 r1 = gen_rtx_REG (DImode, gregno);
4705 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4706 r3 = gen_rtx_REG (DImode, gregno + 2);
4707 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4708 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4715 /* Determine where to put a SIMD argument on the SPE. */
4717 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4720 int gregno = cum->sysv_gregno;
4722 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4723 are passed and returned in a pair of GPRs for ABI compatibility. */
4724 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4726 int n_words = rs6000_arg_size (mode, type);
4728 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4730 gregno += (1 - gregno) & 1;
4732 /* Multi-reg args are not split between registers and stack. */
4733 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4736 return spe_build_register_parallel (mode, gregno);
4740 int n_words = rs6000_arg_size (mode, type);
4742 /* SPE vectors are put in odd registers. */
4743 if (n_words == 2 && (gregno & 1) == 0)
4746 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4749 enum machine_mode m = SImode;
4751 r1 = gen_rtx_REG (m, gregno);
4752 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4753 r2 = gen_rtx_REG (m, gregno + 1);
4754 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4755 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4762 if (gregno <= GP_ARG_MAX_REG)
4763 return gen_rtx_REG (mode, gregno);
4769 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4770 structure between cum->intoffset and bitpos to integer registers. */
4773 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4774 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4776 enum machine_mode mode;
4778 unsigned int startbit, endbit;
4779 int this_regno, intregs, intoffset;
4782 if (cum->intoffset == -1)
4785 intoffset = cum->intoffset;
4786 cum->intoffset = -1;
4788 /* If this is the trailing part of a word, try to only load that
4789 much into the register. Otherwise load the whole register. Note
4790 that in the latter case we may pick up unwanted bits. It's not a
4791 problem at the moment but may wish to revisit. */
4793 if (intoffset % BITS_PER_WORD != 0)
4795 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4797 if (mode == BLKmode)
4799 /* We couldn't find an appropriate mode, which happens,
4800 e.g., in packed structs when there are 3 bytes to load.
4801 Back intoffset back to the beginning of the word in this
4803 intoffset = intoffset & -BITS_PER_WORD;
4810 startbit = intoffset & -BITS_PER_WORD;
4811 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4812 intregs = (endbit - startbit) / BITS_PER_WORD;
4813 this_regno = cum->words + intoffset / BITS_PER_WORD;
4815 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4818 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4822 intoffset /= BITS_PER_UNIT;
4825 regno = GP_ARG_MIN_REG + this_regno;
4826 reg = gen_rtx_REG (mode, regno);
4828 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4831 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4835 while (intregs > 0);
4838 /* Recursive workhorse for the following. */
4841 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4842 HOST_WIDE_INT startbitpos, rtx rvec[],
4847 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4848 if (TREE_CODE (f) == FIELD_DECL)
4850 HOST_WIDE_INT bitpos = startbitpos;
4851 tree ftype = TREE_TYPE (f);
4852 enum machine_mode mode = TYPE_MODE (ftype);
4854 if (DECL_SIZE (f) != 0
4855 && host_integerp (bit_position (f), 1))
4856 bitpos += int_bit_position (f);
4858 /* ??? FIXME: else assume zero offset. */
4860 if (TREE_CODE (ftype) == RECORD_TYPE)
4861 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4862 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4867 case SCmode: mode = SFmode; break;
4868 case DCmode: mode = DFmode; break;
4869 case TCmode: mode = TFmode; break;
4873 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4875 = gen_rtx_EXPR_LIST (VOIDmode,
4876 gen_rtx_REG (mode, cum->fregno++),
4877 GEN_INT (bitpos / BITS_PER_UNIT));
4881 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4883 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4885 = gen_rtx_EXPR_LIST (VOIDmode,
4886 gen_rtx_REG (mode, cum->vregno++),
4887 GEN_INT (bitpos / BITS_PER_UNIT));
4889 else if (cum->intoffset == -1)
4890 cum->intoffset = bitpos;
4894 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4895 the register(s) to be used for each field and subfield of a struct
4896 being passed by value, along with the offset of where the
4897 register's value may be found in the block. FP fields go in FP
4898 register, vector fields go in vector registers, and everything
4899 else goes in int registers, packed as in memory.
4901 This code is also used for function return values. RETVAL indicates
4902 whether this is the case.
4904 Much of this is taken from the SPARC V9 port, which has a similar
4905 calling convention. */
4908 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4909 int named, bool retval)
4911 rtx rvec[FIRST_PSEUDO_REGISTER];
4912 int k = 1, kbase = 1;
4913 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4914 /* This is a copy; modifications are not visible to our caller. */
4915 CUMULATIVE_ARGS copy_cum = *orig_cum;
4916 CUMULATIVE_ARGS *cum = ©_cum;
4918 /* Pad to 16 byte boundary if needed. */
4919 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4920 && (cum->words % 2) != 0)
4927 /* Put entries into rvec[] for individual FP and vector fields, and
4928 for the chunks of memory that go in int regs. Note we start at
4929 element 1; 0 is reserved for an indication of using memory, and
4930 may or may not be filled in below. */
4931 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4932 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4934 /* If any part of the struct went on the stack put all of it there.
4935 This hack is because the generic code for
4936 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4937 parts of the struct are not at the beginning. */
4941 return NULL_RTX; /* doesn't go in registers at all */
4943 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4945 if (k > 1 || cum->use_stack)
4946 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4951 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4954 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4958 rtx rvec[GP_ARG_NUM_REG + 1];
4960 if (align_words >= GP_ARG_NUM_REG)
4963 n_units = rs6000_arg_size (mode, type);
4965 /* Optimize the simple case where the arg fits in one gpr, except in
4966 the case of BLKmode due to assign_parms assuming that registers are
4967 BITS_PER_WORD wide. */
4969 || (n_units == 1 && mode != BLKmode))
4970 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4973 if (align_words + n_units > GP_ARG_NUM_REG)
4974 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4975 using a magic NULL_RTX component.
4976 FIXME: This is not strictly correct. Only some of the arg
4977 belongs in memory, not all of it. However, there isn't any way
4978 to do this currently, apart from building rtx descriptions for
4979 the pieces of memory we want stored. Due to bugs in the generic
4980 code we can't use the normal function_arg_partial_nregs scheme
4981 with the PARALLEL arg description we emit here.
4982 In any case, the code to store the whole arg to memory is often
4983 more efficient than code to store pieces, and we know that space
4984 is available in the right place for the whole arg. */
4985 /* FIXME: This should be fixed since the conversion to
4986 TARGET_ARG_PARTIAL_BYTES. */
4987 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4992 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4993 rtx off = GEN_INT (i++ * 4);
4994 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4996 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4998 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5001 /* Determine where to put an argument to a function.
5002 Value is zero to push the argument on the stack,
5003 or a hard register in which to store the argument.
5005 MODE is the argument's machine mode.
5006 TYPE is the data type of the argument (as a tree).
5007 This is null for libcalls where that information may
5009 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5010 the preceding args and about the function being called. It is
5011 not modified in this routine.
5012 NAMED is nonzero if this argument is a named parameter
5013 (otherwise it is an extra parameter matching an ellipsis).
5015 On RS/6000 the first eight words of non-FP are normally in registers
5016 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5017 Under V.4, the first 8 FP args are in registers.
5019 If this is floating-point and no prototype is specified, we use
5020 both an FP and integer register (or possibly FP reg and stack). Library
5021 functions (when CALL_LIBCALL is set) always have the proper types for args,
5022 so we can pass the FP value just in one register. emit_library_function
5023 doesn't support PARALLEL anyway.
5025 Note that for args passed by reference, function_arg will be called
5026 with MODE and TYPE set to that of the pointer to the arg, not the arg
5030 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5031 tree type, int named)
5033 enum rs6000_abi abi = DEFAULT_ABI;
5035 /* Return a marker to indicate whether CR1 needs to set or clear the
5036 bit that V.4 uses to say fp args were passed in registers.
5037 Assume that we don't need the marker for software floating point,
5038 or compiler generated library calls. */
5039 if (mode == VOIDmode)
5042 && (cum->call_cookie & CALL_LIBCALL) == 0
5044 || (cum->nargs_prototype < 0
5045 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5047 /* For the SPE, we need to crxor CR6 always. */
5049 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5050 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5051 return GEN_INT (cum->call_cookie
5052 | ((cum->fregno == FP_ARG_MIN_REG)
5053 ? CALL_V4_SET_FP_ARGS
5054 : CALL_V4_CLEAR_FP_ARGS));
5057 return GEN_INT (cum->call_cookie);
5060 if (rs6000_darwin64_abi && mode == BLKmode
5061 && TREE_CODE (type) == RECORD_TYPE)
5063 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5064 if (rslt != NULL_RTX)
5066 /* Else fall through to usual handling. */
5069 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5070 if (TARGET_64BIT && ! cum->prototype)
5072 /* Vector parameters get passed in vector register
5073 and also in GPRs or memory, in absence of prototype. */
5076 align_words = (cum->words + 1) & ~1;
5078 if (align_words >= GP_ARG_NUM_REG)
5084 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5086 return gen_rtx_PARALLEL (mode,
5088 gen_rtx_EXPR_LIST (VOIDmode,
5090 gen_rtx_EXPR_LIST (VOIDmode,
5091 gen_rtx_REG (mode, cum->vregno),
5095 return gen_rtx_REG (mode, cum->vregno);
5096 else if (TARGET_ALTIVEC_ABI
5097 && (ALTIVEC_VECTOR_MODE (mode)
5098 || (type && TREE_CODE (type) == VECTOR_TYPE
5099 && int_size_in_bytes (type) == 16)))
5101 if (named || abi == ABI_V4)
5105 /* Vector parameters to varargs functions under AIX or Darwin
5106 get passed in memory and possibly also in GPRs. */
5107 int align, align_words, n_words;
5108 enum machine_mode part_mode;
5110 /* Vector parameters must be 16-byte aligned. This places them at
5111 2 mod 4 in terms of words in 32-bit mode, since the parameter
5112 save area starts at offset 24 from the stack. In 64-bit mode,
5113 they just have to start on an even word, since the parameter
5114 save area is 16-byte aligned. */
5116 align = (2 - cum->words) & 3;
5118 align = cum->words & 1;
5119 align_words = cum->words + align;
5121 /* Out of registers? Memory, then. */
5122 if (align_words >= GP_ARG_NUM_REG)
5125 if (TARGET_32BIT && TARGET_POWERPC64)
5126 return rs6000_mixed_function_arg (mode, type, align_words);
5128 /* The vector value goes in GPRs. Only the part of the
5129 value in GPRs is reported here. */
5131 n_words = rs6000_arg_size (mode, type);
5132 if (align_words + n_words > GP_ARG_NUM_REG)
5133 /* Fortunately, there are only two possibilities, the value
5134 is either wholly in GPRs or half in GPRs and half not. */
5137 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5140 else if (TARGET_SPE_ABI && TARGET_SPE
5141 && (SPE_VECTOR_MODE (mode)
5142 || (TARGET_E500_DOUBLE && (mode == DFmode
5143 || mode == DCmode))))
5144 return rs6000_spe_function_arg (cum, mode, type);
5146 else if (abi == ABI_V4)
5148 if (TARGET_HARD_FLOAT && TARGET_FPRS
5149 && (mode == SFmode || mode == DFmode))
5151 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5152 return gen_rtx_REG (mode, cum->fregno);
5158 int n_words = rs6000_arg_size (mode, type);
5159 int gregno = cum->sysv_gregno;
5161 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5162 (r7,r8) or (r9,r10). As does any other 2 word item such
5163 as complex int due to a historical mistake. */
5165 gregno += (1 - gregno) & 1;
5167 /* Multi-reg args are not split between registers and stack. */
5168 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5171 if (TARGET_32BIT && TARGET_POWERPC64)
5172 return rs6000_mixed_function_arg (mode, type,
5173 gregno - GP_ARG_MIN_REG);
5174 return gen_rtx_REG (mode, gregno);
5179 int align_words = rs6000_parm_start (mode, type, cum->words);
5181 if (USE_FP_FOR_ARG_P (cum, mode, type))
5183 rtx rvec[GP_ARG_NUM_REG + 1];
5187 enum machine_mode fmode = mode;
5188 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5190 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5192 /* Currently, we only ever need one reg here because complex
5193 doubles are split. */
5194 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5196 /* Long double split over regs and memory. */
5200 /* Do we also need to pass this arg in the parameter save
5203 && (cum->nargs_prototype <= 0
5204 || (DEFAULT_ABI == ABI_AIX
5206 && align_words >= GP_ARG_NUM_REG)));
5208 if (!needs_psave && mode == fmode)
5209 return gen_rtx_REG (fmode, cum->fregno);
5214 /* Describe the part that goes in gprs or the stack.
5215 This piece must come first, before the fprs. */
5216 if (align_words < GP_ARG_NUM_REG)
5218 unsigned long n_words = rs6000_arg_size (mode, type);
5220 if (align_words + n_words > GP_ARG_NUM_REG
5221 || (TARGET_32BIT && TARGET_POWERPC64))
5223 /* If this is partially on the stack, then we only
5224 include the portion actually in registers here. */
5225 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5228 if (align_words + n_words > GP_ARG_NUM_REG
5229 && (TARGET_32BIT && TARGET_POWERPC64))
5230 /* Not all of the arg fits in gprs. Say that it
5231 goes in memory too, using a magic NULL_RTX
5232 component. Also see comment in
5233 rs6000_mixed_function_arg for why the normal
5234 function_arg_partial_nregs scheme doesn't work
5236 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5240 r = gen_rtx_REG (rmode,
5241 GP_ARG_MIN_REG + align_words);
5242 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5243 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5245 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5249 /* The whole arg fits in gprs. */
5250 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5251 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5255 /* It's entirely in memory. */
5256 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5259 /* Describe where this piece goes in the fprs. */
5260 r = gen_rtx_REG (fmode, cum->fregno);
5261 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5263 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5265 else if (align_words < GP_ARG_NUM_REG)
5267 if (TARGET_32BIT && TARGET_POWERPC64)
5268 return rs6000_mixed_function_arg (mode, type, align_words);
5270 if (mode == BLKmode)
5273 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5280 /* For an arg passed partly in registers and partly in memory, this is
5281 the number of bytes passed in registers. For args passed entirely in
5282 registers or entirely in memory, zero. When an arg is described by a
5283 PARALLEL, perhaps using more than one register type, this function
5284 returns the number of bytes used by the first element of the PARALLEL. */
5287 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5288 tree type, bool named)
5293 if (DEFAULT_ABI == ABI_V4)
5296 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5297 && cum->nargs_prototype >= 0)
5300 /* In this complicated case we just disable the partial_nregs code. */
5301 if (rs6000_darwin64_abi && mode == BLKmode
5302 && TREE_CODE (type) == RECORD_TYPE
5303 && int_size_in_bytes (type) > 0)
5306 align_words = rs6000_parm_start (mode, type, cum->words);
5308 if (USE_FP_FOR_ARG_P (cum, mode, type)
5309 /* If we are passing this arg in the fixed parameter save area
5310 (gprs or memory) as well as fprs, then this function should
5311 return the number of bytes passed in the parameter save area
5312 rather than bytes passed in fprs. */
5314 && (cum->nargs_prototype <= 0
5315 || (DEFAULT_ABI == ABI_AIX
5317 && align_words >= GP_ARG_NUM_REG))))
5319 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5320 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5321 else if (cum->nargs_prototype >= 0)
5325 if (align_words < GP_ARG_NUM_REG
5326 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5327 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5329 if (ret != 0 && TARGET_DEBUG_ARG)
5330 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5335 /* A C expression that indicates when an argument must be passed by
5336 reference. If nonzero for an argument, a copy of that argument is
5337 made in memory and a pointer to the argument is passed instead of
5338 the argument itself. The pointer is passed in whatever way is
5339 appropriate for passing a pointer to that type.
5341 Under V.4, aggregates and long double are passed by reference.
5343 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5344 reference unless the AltiVec vector extension ABI is in force.
5346 As an extension to all ABIs, variable sized types are passed by
5350 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5351 enum machine_mode mode, tree type,
5352 bool named ATTRIBUTE_UNUSED)
5354 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5356 if (TARGET_DEBUG_ARG)
5357 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5364 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5366 if (TARGET_DEBUG_ARG)
5367 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5371 if (int_size_in_bytes (type) < 0)
5373 if (TARGET_DEBUG_ARG)
5374 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5378 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5379 modes only exist for GCC vector types if -maltivec. */
5380 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5382 if (TARGET_DEBUG_ARG)
5383 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5387 /* Pass synthetic vectors in memory. */
5388 if (TREE_CODE (type) == VECTOR_TYPE
5389 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5391 static bool warned_for_pass_big_vectors = false;
5392 if (TARGET_DEBUG_ARG)
5393 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5394 if (!warned_for_pass_big_vectors)
5396 warning (0, "GCC vector passed by reference: "
5397 "non-standard ABI extension with no compatibility guarantee");
5398 warned_for_pass_big_vectors = true;
5407 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5410 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5415 for (i = 0; i < nregs; i++)
5417 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5418 if (reload_completed)
5420 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5423 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5424 i * GET_MODE_SIZE (reg_mode));
5427 tem = replace_equiv_address (tem, XEXP (tem, 0));
5431 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5435 /* Perform any needed actions needed for a function that is receiving a
5436 variable number of arguments.
5440 MODE and TYPE are the mode and type of the current parameter.
5442 PRETEND_SIZE is a variable that should be set to the amount of stack
5443 that must be pushed by the prolog to pretend that our caller pushed
5446 Normally, this macro will push all remaining incoming registers on the
5447 stack and set PRETEND_SIZE to the length of the registers pushed. */
5450 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5451 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5454 CUMULATIVE_ARGS next_cum;
5455 int reg_size = TARGET_32BIT ? 4 : 8;
5456 rtx save_area = NULL_RTX, mem;
5457 int first_reg_offset, set;
5459 /* Skip the last named argument. */
5461 function_arg_advance (&next_cum, mode, type, 1, 0);
5463 if (DEFAULT_ABI == ABI_V4)
5465 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5469 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5470 HOST_WIDE_INT offset = 0;
5472 /* Try to optimize the size of the varargs save area.
5473 The ABI requires that ap.reg_save_area is doubleword
5474 aligned, but we don't need to allocate space for all
5475 the bytes, only those to which we actually will save
5477 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5478 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5479 if (TARGET_HARD_FLOAT && TARGET_FPRS
5480 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5481 && cfun->va_list_fpr_size)
5484 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5485 * UNITS_PER_FP_WORD;
5486 if (cfun->va_list_fpr_size
5487 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5488 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5490 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5491 * UNITS_PER_FP_WORD;
5495 offset = -((first_reg_offset * reg_size) & ~7);
5496 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5498 gpr_reg_num = cfun->va_list_gpr_size;
5499 if (reg_size == 4 && (first_reg_offset & 1))
5502 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5505 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5507 - (int) (GP_ARG_NUM_REG * reg_size);
5509 if (gpr_size + fpr_size)
5512 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5513 gcc_assert (GET_CODE (reg_save_area) == MEM);
5514 reg_save_area = XEXP (reg_save_area, 0);
5515 if (GET_CODE (reg_save_area) == PLUS)
5517 gcc_assert (XEXP (reg_save_area, 0)
5518 == virtual_stack_vars_rtx);
5519 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5520 offset += INTVAL (XEXP (reg_save_area, 1));
5523 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5526 cfun->machine->varargs_save_offset = offset;
5527 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5532 first_reg_offset = next_cum.words;
5533 save_area = virtual_incoming_args_rtx;
5535 if (targetm.calls.must_pass_in_stack (mode, type))
5536 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5539 set = get_varargs_alias_set ();
5540 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5541 && cfun->va_list_gpr_size)
5543 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5545 if (va_list_gpr_counter_field)
5547 /* V4 va_list_gpr_size counts number of registers needed. */
5548 if (nregs > cfun->va_list_gpr_size)
5549 nregs = cfun->va_list_gpr_size;
5553 /* char * va_list instead counts number of bytes needed. */
5554 if (nregs > cfun->va_list_gpr_size / reg_size)
5555 nregs = cfun->va_list_gpr_size / reg_size;
5558 mem = gen_rtx_MEM (BLKmode,
5559 plus_constant (save_area,
5560 first_reg_offset * reg_size));
5561 MEM_NOTRAP_P (mem) = 1;
5562 set_mem_alias_set (mem, set);
5563 set_mem_align (mem, BITS_PER_WORD);
5565 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5569 /* Save FP registers if needed. */
5570 if (DEFAULT_ABI == ABI_V4
5571 && TARGET_HARD_FLOAT && TARGET_FPRS
5573 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5574 && cfun->va_list_fpr_size)
5576 int fregno = next_cum.fregno, nregs;
5577 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5578 rtx lab = gen_label_rtx ();
5579 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5580 * UNITS_PER_FP_WORD);
5583 (gen_rtx_SET (VOIDmode,
5585 gen_rtx_IF_THEN_ELSE (VOIDmode,
5586 gen_rtx_NE (VOIDmode, cr1,
5588 gen_rtx_LABEL_REF (VOIDmode, lab),
5592 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5593 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5595 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5596 MEM_NOTRAP_P (mem) = 1;
5597 set_mem_alias_set (mem, set);
5598 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5599 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5606 /* Create the va_list data type. */
5609 rs6000_build_builtin_va_list (void)
5611 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5613 /* For AIX, prefer 'char *' because that's what the system
5614 header files like. */
5615 if (DEFAULT_ABI != ABI_V4)
5616 return build_pointer_type (char_type_node);
5618 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5619 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5621 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5622 unsigned_char_type_node);
5623 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5624 unsigned_char_type_node);
5625 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5627 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5628 short_unsigned_type_node);
5629 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5631 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5634 va_list_gpr_counter_field = f_gpr;
5635 va_list_fpr_counter_field = f_fpr;
5637 DECL_FIELD_CONTEXT (f_gpr) = record;
5638 DECL_FIELD_CONTEXT (f_fpr) = record;
5639 DECL_FIELD_CONTEXT (f_res) = record;
5640 DECL_FIELD_CONTEXT (f_ovf) = record;
5641 DECL_FIELD_CONTEXT (f_sav) = record;
5643 TREE_CHAIN (record) = type_decl;
5644 TYPE_NAME (record) = type_decl;
5645 TYPE_FIELDS (record) = f_gpr;
5646 TREE_CHAIN (f_gpr) = f_fpr;
5647 TREE_CHAIN (f_fpr) = f_res;
5648 TREE_CHAIN (f_res) = f_ovf;
5649 TREE_CHAIN (f_ovf) = f_sav;
5651 layout_type (record);
5653 /* The correct type is an array type of one element. */
5654 return build_array_type (record, build_index_type (size_zero_node));
5657 /* Implement va_start. */
5660 rs6000_va_start (tree valist, rtx nextarg)
5662 HOST_WIDE_INT words, n_gpr, n_fpr;
5663 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5664 tree gpr, fpr, ovf, sav, t;
5666 /* Only SVR4 needs something special. */
5667 if (DEFAULT_ABI != ABI_V4)
5669 std_expand_builtin_va_start (valist, nextarg);
5673 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5674 f_fpr = TREE_CHAIN (f_gpr);
5675 f_res = TREE_CHAIN (f_fpr);
5676 f_ovf = TREE_CHAIN (f_res);
5677 f_sav = TREE_CHAIN (f_ovf);
5679 valist = build_va_arg_indirect_ref (valist);
5680 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5681 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5682 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5683 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5685 /* Count number of gp and fp argument registers used. */
5686 words = current_function_args_info.words;
5687 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5689 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5692 if (TARGET_DEBUG_ARG)
5693 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5694 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5695 words, n_gpr, n_fpr);
5697 if (cfun->va_list_gpr_size)
5699 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5700 build_int_cst (NULL_TREE, n_gpr));
5701 TREE_SIDE_EFFECTS (t) = 1;
5702 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5705 if (cfun->va_list_fpr_size)
5707 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5708 build_int_cst (NULL_TREE, n_fpr));
5709 TREE_SIDE_EFFECTS (t) = 1;
5710 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5713 /* Find the overflow area. */
5714 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5716 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5717 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5718 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5719 TREE_SIDE_EFFECTS (t) = 1;
5720 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5722 /* If there were no va_arg invocations, don't set up the register
5724 if (!cfun->va_list_gpr_size
5725 && !cfun->va_list_fpr_size
5726 && n_gpr < GP_ARG_NUM_REG
5727 && n_fpr < FP_ARG_V4_MAX_REG)
5730 /* Find the register save area. */
5731 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5732 if (cfun->machine->varargs_save_offset)
5733 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5734 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5735 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5736 TREE_SIDE_EFFECTS (t) = 1;
5737 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5740 /* Implement va_arg. */
5743 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5745 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5746 tree gpr, fpr, ovf, sav, reg, t, u;
5747 int size, rsize, n_reg, sav_ofs, sav_scale;
5748 tree lab_false, lab_over, addr;
5750 tree ptrtype = build_pointer_type (type);
5752 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5754 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5755 return build_va_arg_indirect_ref (t);
5758 if (DEFAULT_ABI != ABI_V4)
5760 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5762 tree elem_type = TREE_TYPE (type);
5763 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5764 int elem_size = GET_MODE_SIZE (elem_mode);
5766 if (elem_size < UNITS_PER_WORD)
5768 tree real_part, imag_part;
5769 tree post = NULL_TREE;
5771 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5773 /* Copy the value into a temporary, lest the formal temporary
5774 be reused out from under us. */
5775 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5776 append_to_statement_list (post, pre_p);
5778 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5781 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5785 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5788 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5789 f_fpr = TREE_CHAIN (f_gpr);
5790 f_res = TREE_CHAIN (f_fpr);
5791 f_ovf = TREE_CHAIN (f_res);
5792 f_sav = TREE_CHAIN (f_ovf);
5794 valist = build_va_arg_indirect_ref (valist);
5795 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5796 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5797 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5798 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5800 size = int_size_in_bytes (type);
5801 rsize = (size + 3) / 4;
5804 if (TARGET_HARD_FLOAT && TARGET_FPRS
5805 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5807 /* FP args go in FP registers, if present. */
5812 if (TYPE_MODE (type) == DFmode)
5817 /* Otherwise into GP registers. */
5826 /* Pull the value out of the saved registers.... */
5829 addr = create_tmp_var (ptr_type_node, "addr");
5830 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5832 /* AltiVec vectors never go in registers when -mabi=altivec. */
5833 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5837 lab_false = create_artificial_label ();
5838 lab_over = create_artificial_label ();
5840 /* Long long and SPE vectors are aligned in the registers.
5841 As are any other 2 gpr item such as complex int due to a
5842 historical mistake. */
5846 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5847 size_int (n_reg - 1));
5848 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5851 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5852 t = build2 (GE_EXPR, boolean_type_node, u, t);
5853 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5854 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5855 gimplify_and_add (t, pre_p);
5859 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5861 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5862 u = build1 (CONVERT_EXPR, integer_type_node, u);
5863 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5864 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5866 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5867 gimplify_and_add (t, pre_p);
5869 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5870 gimplify_and_add (t, pre_p);
5872 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5873 append_to_statement_list (t, pre_p);
5877 /* Ensure that we don't find any more args in regs.
5878 Alignment has taken care of the n_reg == 2 case. */
5879 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5880 gimplify_and_add (t, pre_p);
5884 /* ... otherwise out of the overflow area. */
5886 /* Care for on-stack alignment if needed. */
5890 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5891 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5892 build_int_cst (NULL_TREE, -align));
5894 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5896 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5897 gimplify_and_add (u, pre_p);
5899 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5900 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5901 gimplify_and_add (t, pre_p);
5905 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5906 append_to_statement_list (t, pre_p);
5909 addr = fold_convert (ptrtype, addr);
5910 return build_va_arg_indirect_ref (addr);
5916 def_builtin (int mask, const char *name, tree type, int code)
5918 if (mask & target_flags)
5920 if (rs6000_builtin_decls[code])
5923 rs6000_builtin_decls[code] =
5924 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5929 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5931 static const struct builtin_description bdesc_3arg[] =
5933 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5934 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5935 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5936 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5937 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5938 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5939 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5940 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5941 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5942 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5943 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5944 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5945 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5946 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5947 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5948 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5949 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5950 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5951 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5952 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5953 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5954 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5955 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5957 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5958 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5959 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5960 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5961 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5962 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5963 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5964 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5965 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5966 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5967 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5968 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5969 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5970 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5971 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
5974 /* DST operations: void foo (void *, const int, const char). */
5976 static const struct builtin_description bdesc_dst[] =
5978 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5979 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5980 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5981 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5983 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5984 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5985 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5986 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
5989 /* Simple binary operations: VECc = foo (VECa, VECb). */
5991 static struct builtin_description bdesc_2arg[] =
5993 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5994 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5995 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5996 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5997 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5998 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5999 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6000 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6001 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6002 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6003 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6004 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6005 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6006 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6007 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6008 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6009 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6010 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6011 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6012 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6013 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6014 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6015 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6017 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6019 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6020 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6021 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6025 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6026 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6027 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6028 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6029 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6030 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6031 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6032 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6033 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6034 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6035 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6036 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6037 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6038 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6039 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6040 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6041 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6042 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6043 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6044 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6045 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6046 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6047 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6048 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6049 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6050 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6053 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6054 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6055 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6056 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6057 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6058 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6059 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6060 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6061 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6062 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6063 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6064 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6065 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6066 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6067 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6068 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6069 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6070 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6071 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6072 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6073 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6074 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6075 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6076 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6077 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6078 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6079 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6080 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6081 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6082 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6083 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6084 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6086 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6087 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6088 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6089 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6090 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6094 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6096 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6097 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6099 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6100 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6101 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6102 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6103 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6105 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6106 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6107 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6108 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6109 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6110 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6111 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6112 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6113 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6114 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6115 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6116 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6117 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6118 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6119 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6120 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6121 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6122 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6123 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6124 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6125 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6126 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6127 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6128 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6129 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6139 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6140 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6141 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6142 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6143 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6146 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6149 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6233 /* Place holder, leave as first spe builtin. */
6234 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6235 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6236 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6237 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6238 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6239 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6240 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6241 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6242 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6243 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6244 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6245 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6246 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6247 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6248 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6249 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6250 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6251 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6252 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6253 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6254 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6255 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6256 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6257 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6258 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6259 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6260 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6261 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6262 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6263 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6264 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6265 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6266 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6267 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6268 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6269 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6270 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6271 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6272 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6273 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6274 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6275 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6276 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6277 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6278 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6279 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6280 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6281 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6282 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6283 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6284 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6285 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6286 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6287 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6288 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6289 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6290 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6291 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6292 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6293 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6294 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6295 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6296 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6297 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6298 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6299 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6300 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6301 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6302 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6303 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6304 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6305 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6306 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6307 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6308 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6309 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6310 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6311 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6312 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6313 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6314 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6315 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6316 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6317 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6318 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6319 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6320 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6321 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6322 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6323 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6324 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6325 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6326 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6327 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6328 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6329 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6330 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6331 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6332 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6333 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6334 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6335 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6336 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6337 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6338 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6339 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6340 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6341 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6342 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6344 /* SPE binary operations expecting a 5-bit unsigned literal. */
6345 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6347 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6348 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6349 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6350 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6351 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6352 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6353 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6354 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6355 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6356 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6357 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6358 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6359 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6360 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6361 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6362 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6363 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6364 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6365 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6366 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6367 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6368 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6369 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6370 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6371 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6372 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6374 /* Place-holder. Leave as last binary SPE builtin. */
6375 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6378 /* AltiVec predicates. */
6380 struct builtin_description_predicates
6382 const unsigned int mask;
6383 const enum insn_code icode;
6385 const char *const name;
6386 const enum rs6000_builtins code;
6389 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6391 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6392 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6393 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6394 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6395 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6396 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6397 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6398 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6399 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6400 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6401 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6402 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6403 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6405 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6406 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6407 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6410 /* SPE predicates. */
6411 static struct builtin_description bdesc_spe_predicates[] =
6413 /* Place-holder. Leave as first. */
6414 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6415 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6416 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6417 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6418 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6419 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6420 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6421 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6422 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6423 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6424 /* Place-holder. Leave as last. */
6425 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6428 /* SPE evsel predicates. */
6429 static struct builtin_description bdesc_spe_evsel[] =
6431 /* Place-holder. Leave as first. */
6432 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6433 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6434 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6435 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6436 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6437 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6438 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6439 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6440 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6441 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6442 /* Place-holder. Leave as last. */
6443 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6446 /* ABS* operations. */
6448 static const struct builtin_description bdesc_abs[] =
6450 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6451 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6452 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6453 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6454 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6455 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6456 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6459 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6462 static struct builtin_description bdesc_1arg[] =
6464 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6465 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6466 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6467 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6468 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6469 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6470 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6471 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6472 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6473 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6474 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6475 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6476 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6477 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6478 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6479 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6480 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6482 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6483 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6484 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6485 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6486 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6487 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6488 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6489 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6490 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6491 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6492 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6493 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6494 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6495 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6496 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6497 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6498 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6499 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6500 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6502 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6503 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6504 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6505 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6506 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6507 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6508 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6509 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6510 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6511 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6512 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6513 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6514 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6515 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6516 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6517 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6518 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6519 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6520 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6521 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6522 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6523 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6524 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6525 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6526 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6527 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6528 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6529 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6530 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6531 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6533 /* Place-holder. Leave as last unary SPE builtin. */
6534 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6538 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6541 tree arg0 = TREE_VALUE (arglist);
6542 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6543 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6544 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6546 if (icode == CODE_FOR_nothing)
6547 /* Builtin not supported on this processor. */
6550 /* If we got invalid arguments bail out before generating bad rtl. */
6551 if (arg0 == error_mark_node)
6554 if (icode == CODE_FOR_altivec_vspltisb
6555 || icode == CODE_FOR_altivec_vspltish
6556 || icode == CODE_FOR_altivec_vspltisw
6557 || icode == CODE_FOR_spe_evsplatfi
6558 || icode == CODE_FOR_spe_evsplati)
6560 /* Only allow 5-bit *signed* literals. */
6561 if (GET_CODE (op0) != CONST_INT
6562 || INTVAL (op0) > 15
6563 || INTVAL (op0) < -16)
6565 error ("argument 1 must be a 5-bit signed literal");
6571 || GET_MODE (target) != tmode
6572 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6573 target = gen_reg_rtx (tmode);
6575 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6576 op0 = copy_to_mode_reg (mode0, op0);
6578 pat = GEN_FCN (icode) (target, op0);
6587 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6589 rtx pat, scratch1, scratch2;
6590 tree arg0 = TREE_VALUE (arglist);
6591 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6592 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6593 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6595 /* If we have invalid arguments, bail out before generating bad rtl. */
6596 if (arg0 == error_mark_node)
6600 || GET_MODE (target) != tmode
6601 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6602 target = gen_reg_rtx (tmode);
6604 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6605 op0 = copy_to_mode_reg (mode0, op0);
6607 scratch1 = gen_reg_rtx (mode0);
6608 scratch2 = gen_reg_rtx (mode0);
6610 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6619 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6622 tree arg0 = TREE_VALUE (arglist);
6623 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6624 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6625 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6626 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6627 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6628 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6630 if (icode == CODE_FOR_nothing)
6631 /* Builtin not supported on this processor. */
6634 /* If we got invalid arguments bail out before generating bad rtl. */
6635 if (arg0 == error_mark_node || arg1 == error_mark_node)
6638 if (icode == CODE_FOR_altivec_vcfux
6639 || icode == CODE_FOR_altivec_vcfsx
6640 || icode == CODE_FOR_altivec_vctsxs
6641 || icode == CODE_FOR_altivec_vctuxs
6642 || icode == CODE_FOR_altivec_vspltb
6643 || icode == CODE_FOR_altivec_vsplth
6644 || icode == CODE_FOR_altivec_vspltw
6645 || icode == CODE_FOR_spe_evaddiw
6646 || icode == CODE_FOR_spe_evldd
6647 || icode == CODE_FOR_spe_evldh
6648 || icode == CODE_FOR_spe_evldw
6649 || icode == CODE_FOR_spe_evlhhesplat
6650 || icode == CODE_FOR_spe_evlhhossplat
6651 || icode == CODE_FOR_spe_evlhhousplat
6652 || icode == CODE_FOR_spe_evlwhe
6653 || icode == CODE_FOR_spe_evlwhos
6654 || icode == CODE_FOR_spe_evlwhou
6655 || icode == CODE_FOR_spe_evlwhsplat
6656 || icode == CODE_FOR_spe_evlwwsplat
6657 || icode == CODE_FOR_spe_evrlwi
6658 || icode == CODE_FOR_spe_evslwi
6659 || icode == CODE_FOR_spe_evsrwis
6660 || icode == CODE_FOR_spe_evsubifw
6661 || icode == CODE_FOR_spe_evsrwiu)
6663 /* Only allow 5-bit unsigned literals. */
6665 if (TREE_CODE (arg1) != INTEGER_CST
6666 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6668 error ("argument 2 must be a 5-bit unsigned literal");
6674 || GET_MODE (target) != tmode
6675 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6676 target = gen_reg_rtx (tmode);
6678 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6679 op0 = copy_to_mode_reg (mode0, op0);
6680 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6681 op1 = copy_to_mode_reg (mode1, op1);
6683 pat = GEN_FCN (icode) (target, op0, op1);
6692 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6693 tree arglist, rtx target)
6696 tree cr6_form = TREE_VALUE (arglist);
6697 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6698 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6699 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6700 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6701 enum machine_mode tmode = SImode;
6702 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6703 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6706 if (TREE_CODE (cr6_form) != INTEGER_CST)
6708 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6712 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6714 gcc_assert (mode0 == mode1);
6716 /* If we have invalid arguments, bail out before generating bad rtl. */
6717 if (arg0 == error_mark_node || arg1 == error_mark_node)
6721 || GET_MODE (target) != tmode
6722 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6723 target = gen_reg_rtx (tmode);
6725 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6726 op0 = copy_to_mode_reg (mode0, op0);
6727 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6728 op1 = copy_to_mode_reg (mode1, op1);
6730 scratch = gen_reg_rtx (mode0);
6732 pat = GEN_FCN (icode) (scratch, op0, op1,
6733 gen_rtx_SYMBOL_REF (Pmode, opcode));
6738 /* The vec_any* and vec_all* predicates use the same opcodes for two
6739 different operations, but the bits in CR6 will be different
6740 depending on what information we want. So we have to play tricks
6741 with CR6 to get the right bits out.
6743 If you think this is disgusting, look at the specs for the
6744 AltiVec predicates. */
6746 switch (cr6_form_int)
6749 emit_insn (gen_cr6_test_for_zero (target));
6752 emit_insn (gen_cr6_test_for_zero_reverse (target));
6755 emit_insn (gen_cr6_test_for_lt (target));
6758 emit_insn (gen_cr6_test_for_lt_reverse (target));
6761 error ("argument 1 of __builtin_altivec_predicate is out of range");
6769 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6772 tree arg0 = TREE_VALUE (arglist);
6773 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6774 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6775 enum machine_mode mode0 = Pmode;
6776 enum machine_mode mode1 = Pmode;
6777 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6778 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6780 if (icode == CODE_FOR_nothing)
6781 /* Builtin not supported on this processor. */
6784 /* If we got invalid arguments bail out before generating bad rtl. */
6785 if (arg0 == error_mark_node || arg1 == error_mark_node)
6789 || GET_MODE (target) != tmode
6790 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6791 target = gen_reg_rtx (tmode);
6793 op1 = copy_to_mode_reg (mode1, op1);
6795 if (op0 == const0_rtx)
6797 addr = gen_rtx_MEM (tmode, op1);
6801 op0 = copy_to_mode_reg (mode0, op0);
6802 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6805 pat = GEN_FCN (icode) (target, addr);
6815 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6817 tree arg0 = TREE_VALUE (arglist);
6818 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6819 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6820 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6821 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6822 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6824 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6825 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6826 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6828 /* Invalid arguments. Bail before doing anything stoopid! */
6829 if (arg0 == error_mark_node
6830 || arg1 == error_mark_node
6831 || arg2 == error_mark_node)
6834 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6835 op0 = copy_to_mode_reg (mode2, op0);
6836 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6837 op1 = copy_to_mode_reg (mode0, op1);
6838 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6839 op2 = copy_to_mode_reg (mode1, op2);
6841 pat = GEN_FCN (icode) (op1, op2, op0);
6848 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6850 tree arg0 = TREE_VALUE (arglist);
6851 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6852 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6853 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6854 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6855 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6857 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6858 enum machine_mode mode1 = Pmode;
6859 enum machine_mode mode2 = Pmode;
6861 /* Invalid arguments. Bail before doing anything stoopid! */
6862 if (arg0 == error_mark_node
6863 || arg1 == error_mark_node
6864 || arg2 == error_mark_node)
6867 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6868 op0 = copy_to_mode_reg (tmode, op0);
6870 op2 = copy_to_mode_reg (mode2, op2);
6872 if (op1 == const0_rtx)
6874 addr = gen_rtx_MEM (tmode, op2);
6878 op1 = copy_to_mode_reg (mode1, op1);
6879 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6882 pat = GEN_FCN (icode) (addr, op0);
6889 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6892 tree arg0 = TREE_VALUE (arglist);
6893 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6894 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6895 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6896 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6897 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6898 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6899 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6900 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6901 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6903 if (icode == CODE_FOR_nothing)
6904 /* Builtin not supported on this processor. */
6907 /* If we got invalid arguments bail out before generating bad rtl. */
6908 if (arg0 == error_mark_node
6909 || arg1 == error_mark_node
6910 || arg2 == error_mark_node)
6913 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6914 || icode == CODE_FOR_altivec_vsldoi_v4si
6915 || icode == CODE_FOR_altivec_vsldoi_v8hi
6916 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6918 /* Only allow 4-bit unsigned literals. */
6920 if (TREE_CODE (arg2) != INTEGER_CST
6921 || TREE_INT_CST_LOW (arg2) & ~0xf)
6923 error ("argument 3 must be a 4-bit unsigned literal");
6929 || GET_MODE (target) != tmode
6930 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6931 target = gen_reg_rtx (tmode);
6933 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6934 op0 = copy_to_mode_reg (mode0, op0);
6935 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6936 op1 = copy_to_mode_reg (mode1, op1);
6937 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6938 op2 = copy_to_mode_reg (mode2, op2);
6940 pat = GEN_FCN (icode) (target, op0, op1, op2);
6948 /* Expand the lvx builtins. */
6950 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6952 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6953 tree arglist = TREE_OPERAND (exp, 1);
6954 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6956 enum machine_mode tmode, mode0;
6958 enum insn_code icode;
6962 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6963 icode = CODE_FOR_altivec_lvx_v16qi;
6965 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6966 icode = CODE_FOR_altivec_lvx_v8hi;
6968 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6969 icode = CODE_FOR_altivec_lvx_v4si;
6971 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6972 icode = CODE_FOR_altivec_lvx_v4sf;
6981 arg0 = TREE_VALUE (arglist);
6982 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6983 tmode = insn_data[icode].operand[0].mode;
6984 mode0 = insn_data[icode].operand[1].mode;
6987 || GET_MODE (target) != tmode
6988 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6989 target = gen_reg_rtx (tmode);
6991 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6992 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6994 pat = GEN_FCN (icode) (target, op0);
7001 /* Expand the stvx builtins. */
7003 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7006 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7007 tree arglist = TREE_OPERAND (exp, 1);
7008 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7010 enum machine_mode mode0, mode1;
7012 enum insn_code icode;
7016 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7017 icode = CODE_FOR_altivec_stvx_v16qi;
7019 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7020 icode = CODE_FOR_altivec_stvx_v8hi;
7022 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7023 icode = CODE_FOR_altivec_stvx_v4si;
7025 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7026 icode = CODE_FOR_altivec_stvx_v4sf;
7033 arg0 = TREE_VALUE (arglist);
7034 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7035 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7036 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7037 mode0 = insn_data[icode].operand[0].mode;
7038 mode1 = insn_data[icode].operand[1].mode;
7040 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7041 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7042 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7043 op1 = copy_to_mode_reg (mode1, op1);
7045 pat = GEN_FCN (icode) (op0, op1);
7053 /* Expand the dst builtins. */
7055 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7058 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7059 tree arglist = TREE_OPERAND (exp, 1);
7060 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7061 tree arg0, arg1, arg2;
7062 enum machine_mode mode0, mode1, mode2;
7063 rtx pat, op0, op1, op2;
7064 struct builtin_description *d;
7069 /* Handle DST variants. */
7070 d = (struct builtin_description *) bdesc_dst;
7071 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7072 if (d->code == fcode)
7074 arg0 = TREE_VALUE (arglist);
7075 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7076 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7077 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7078 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7079 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7080 mode0 = insn_data[d->icode].operand[0].mode;
7081 mode1 = insn_data[d->icode].operand[1].mode;
7082 mode2 = insn_data[d->icode].operand[2].mode;
7084 /* Invalid arguments, bail out before generating bad rtl. */
7085 if (arg0 == error_mark_node
7086 || arg1 == error_mark_node
7087 || arg2 == error_mark_node)
7092 if (TREE_CODE (arg2) != INTEGER_CST
7093 || TREE_INT_CST_LOW (arg2) & ~0x3)
7095 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7099 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7100 op0 = copy_to_mode_reg (Pmode, op0);
7101 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7102 op1 = copy_to_mode_reg (mode1, op1);
7104 pat = GEN_FCN (d->icode) (op0, op1, op2);
7114 /* Expand vec_init builtin. */
7116 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7118 enum machine_mode tmode = TYPE_MODE (type);
7119 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7120 int i, n_elt = GET_MODE_NUNITS (tmode);
7121 rtvec v = rtvec_alloc (n_elt);
7123 gcc_assert (VECTOR_MODE_P (tmode));
7125 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7127 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
7128 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7131 gcc_assert (arglist == NULL);
7133 if (!target || !register_operand (target, tmode))
7134 target = gen_reg_rtx (tmode);
7136 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7140 /* Return the integer constant in ARG. Constrain it to be in the range
7141 of the subparts of VEC_TYPE; issue an error if not. */
7144 get_element_number (tree vec_type, tree arg)
7146 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7148 if (!host_integerp (arg, 1)
7149 || (elt = tree_low_cst (arg, 1), elt > max))
7151 error ("selector must be an integer constant in the range 0..%wi", max);
7158 /* Expand vec_set builtin. */
7160 altivec_expand_vec_set_builtin (tree arglist)
7162 enum machine_mode tmode, mode1;
7163 tree arg0, arg1, arg2;
7167 arg0 = TREE_VALUE (arglist);
7168 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7169 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7171 tmode = TYPE_MODE (TREE_TYPE (arg0));
7172 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7173 gcc_assert (VECTOR_MODE_P (tmode));
7175 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7176 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7177 elt = get_element_number (TREE_TYPE (arg0), arg2);
7179 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7180 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7182 op0 = force_reg (tmode, op0);
7183 op1 = force_reg (mode1, op1);
7185 rs6000_expand_vector_set (op0, op1, elt);
7190 /* Expand vec_ext builtin. */
7192 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7194 enum machine_mode tmode, mode0;
7199 arg0 = TREE_VALUE (arglist);
7200 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7202 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7203 elt = get_element_number (TREE_TYPE (arg0), arg1);
7205 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7206 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7207 gcc_assert (VECTOR_MODE_P (mode0));
7209 op0 = force_reg (mode0, op0);
7211 if (optimize || !target || !register_operand (target, tmode))
7212 target = gen_reg_rtx (tmode);
7214 rs6000_expand_vector_extract (target, op0, elt);
7219 /* Expand the builtin in EXP and store the result in TARGET. Store
7220 true in *EXPANDEDP if we found a builtin to expand. */
7222 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7224 struct builtin_description *d;
7225 struct builtin_description_predicates *dp;
7227 enum insn_code icode;
7228 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7229 tree arglist = TREE_OPERAND (exp, 1);
7232 enum machine_mode tmode, mode0;
7233 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7235 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7236 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7239 error ("unresolved overload for Altivec builtin %qF", fndecl);
7243 target = altivec_expand_ld_builtin (exp, target, expandedp);
7247 target = altivec_expand_st_builtin (exp, target, expandedp);
7251 target = altivec_expand_dst_builtin (exp, target, expandedp);
7259 case ALTIVEC_BUILTIN_STVX:
7260 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7261 case ALTIVEC_BUILTIN_STVEBX:
7262 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7263 case ALTIVEC_BUILTIN_STVEHX:
7264 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7265 case ALTIVEC_BUILTIN_STVEWX:
7266 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7267 case ALTIVEC_BUILTIN_STVXL:
7268 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7270 case ALTIVEC_BUILTIN_MFVSCR:
7271 icode = CODE_FOR_altivec_mfvscr;
7272 tmode = insn_data[icode].operand[0].mode;
7275 || GET_MODE (target) != tmode
7276 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7277 target = gen_reg_rtx (tmode);
7279 pat = GEN_FCN (icode) (target);
7285 case ALTIVEC_BUILTIN_MTVSCR:
7286 icode = CODE_FOR_altivec_mtvscr;
7287 arg0 = TREE_VALUE (arglist);
7288 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7289 mode0 = insn_data[icode].operand[0].mode;
7291 /* If we got invalid arguments bail out before generating bad rtl. */
7292 if (arg0 == error_mark_node)
7295 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7296 op0 = copy_to_mode_reg (mode0, op0);
7298 pat = GEN_FCN (icode) (op0);
7303 case ALTIVEC_BUILTIN_DSSALL:
7304 emit_insn (gen_altivec_dssall ());
7307 case ALTIVEC_BUILTIN_DSS:
7308 icode = CODE_FOR_altivec_dss;
7309 arg0 = TREE_VALUE (arglist);
7311 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7312 mode0 = insn_data[icode].operand[0].mode;
7314 /* If we got invalid arguments bail out before generating bad rtl. */
7315 if (arg0 == error_mark_node)
7318 if (TREE_CODE (arg0) != INTEGER_CST
7319 || TREE_INT_CST_LOW (arg0) & ~0x3)
7321 error ("argument to dss must be a 2-bit unsigned literal");
7325 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7326 op0 = copy_to_mode_reg (mode0, op0);
7328 emit_insn (gen_altivec_dss (op0));
7331 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7332 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7333 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7334 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7335 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7337 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7338 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7339 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7340 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7341 return altivec_expand_vec_set_builtin (arglist);
7343 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7344 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7345 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7346 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7347 return altivec_expand_vec_ext_builtin (arglist, target);
7354 /* Expand abs* operations. */
7355 d = (struct builtin_description *) bdesc_abs;
7356 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7357 if (d->code == fcode)
7358 return altivec_expand_abs_builtin (d->icode, arglist, target);
7360 /* Expand the AltiVec predicates. */
7361 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7362 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7363 if (dp->code == fcode)
7364 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7367 /* LV* are funky. We initialized them differently. */
7370 case ALTIVEC_BUILTIN_LVSL:
7371 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7373 case ALTIVEC_BUILTIN_LVSR:
7374 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7376 case ALTIVEC_BUILTIN_LVEBX:
7377 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7379 case ALTIVEC_BUILTIN_LVEHX:
7380 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7382 case ALTIVEC_BUILTIN_LVEWX:
7383 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7385 case ALTIVEC_BUILTIN_LVXL:
7386 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7388 case ALTIVEC_BUILTIN_LVX:
7389 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7400 /* Binops that need to be initialized manually, but can be expanded
7401 automagically by rs6000_expand_binop_builtin. */
7402 static struct builtin_description bdesc_2arg_spe[] =
7404 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7405 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7406 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7407 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7408 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7409 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7410 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7411 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7412 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7413 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7414 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7415 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7416 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7417 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7418 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7419 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7420 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7421 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7422 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7423 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7424 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7425 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7428 /* Expand the builtin in EXP and store the result in TARGET. Store
7429 true in *EXPANDEDP if we found a builtin to expand.
7431 This expands the SPE builtins that are not simple unary and binary
7434 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7436 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7437 tree arglist = TREE_OPERAND (exp, 1);
7439 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7440 enum insn_code icode;
7441 enum machine_mode tmode, mode0;
7443 struct builtin_description *d;
7448 /* Syntax check for a 5-bit unsigned immediate. */
7451 case SPE_BUILTIN_EVSTDD:
7452 case SPE_BUILTIN_EVSTDH:
7453 case SPE_BUILTIN_EVSTDW:
7454 case SPE_BUILTIN_EVSTWHE:
7455 case SPE_BUILTIN_EVSTWHO:
7456 case SPE_BUILTIN_EVSTWWE:
7457 case SPE_BUILTIN_EVSTWWO:
7458 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7459 if (TREE_CODE (arg1) != INTEGER_CST
7460 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7462 error ("argument 2 must be a 5-bit unsigned literal");
7470 /* The evsplat*i instructions are not quite generic. */
7473 case SPE_BUILTIN_EVSPLATFI:
7474 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7476 case SPE_BUILTIN_EVSPLATI:
7477 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7483 d = (struct builtin_description *) bdesc_2arg_spe;
7484 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7485 if (d->code == fcode)
7486 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7488 d = (struct builtin_description *) bdesc_spe_predicates;
7489 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7490 if (d->code == fcode)
7491 return spe_expand_predicate_builtin (d->icode, arglist, target);
7493 d = (struct builtin_description *) bdesc_spe_evsel;
7494 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7495 if (d->code == fcode)
7496 return spe_expand_evsel_builtin (d->icode, arglist, target);
7500 case SPE_BUILTIN_EVSTDDX:
7501 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7502 case SPE_BUILTIN_EVSTDHX:
7503 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7504 case SPE_BUILTIN_EVSTDWX:
7505 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7506 case SPE_BUILTIN_EVSTWHEX:
7507 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7508 case SPE_BUILTIN_EVSTWHOX:
7509 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7510 case SPE_BUILTIN_EVSTWWEX:
7511 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7512 case SPE_BUILTIN_EVSTWWOX:
7513 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7514 case SPE_BUILTIN_EVSTDD:
7515 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7516 case SPE_BUILTIN_EVSTDH:
7517 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7518 case SPE_BUILTIN_EVSTDW:
7519 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7520 case SPE_BUILTIN_EVSTWHE:
7521 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7522 case SPE_BUILTIN_EVSTWHO:
7523 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7524 case SPE_BUILTIN_EVSTWWE:
7525 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7526 case SPE_BUILTIN_EVSTWWO:
7527 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7528 case SPE_BUILTIN_MFSPEFSCR:
7529 icode = CODE_FOR_spe_mfspefscr;
7530 tmode = insn_data[icode].operand[0].mode;
7533 || GET_MODE (target) != tmode
7534 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7535 target = gen_reg_rtx (tmode);
7537 pat = GEN_FCN (icode) (target);
7542 case SPE_BUILTIN_MTSPEFSCR:
7543 icode = CODE_FOR_spe_mtspefscr;
7544 arg0 = TREE_VALUE (arglist);
7545 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7546 mode0 = insn_data[icode].operand[0].mode;
7548 if (arg0 == error_mark_node)
7551 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7552 op0 = copy_to_mode_reg (mode0, op0);
7554 pat = GEN_FCN (icode) (op0);
7567 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7569 rtx pat, scratch, tmp;
7570 tree form = TREE_VALUE (arglist);
7571 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7572 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7573 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7574 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7575 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7576 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7580 if (TREE_CODE (form) != INTEGER_CST)
7582 error ("argument 1 of __builtin_spe_predicate must be a constant");
7586 form_int = TREE_INT_CST_LOW (form);
7588 gcc_assert (mode0 == mode1);
7590 if (arg0 == error_mark_node || arg1 == error_mark_node)
7594 || GET_MODE (target) != SImode
7595 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7596 target = gen_reg_rtx (SImode);
7598 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7599 op0 = copy_to_mode_reg (mode0, op0);
7600 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7601 op1 = copy_to_mode_reg (mode1, op1);
7603 scratch = gen_reg_rtx (CCmode);
7605 pat = GEN_FCN (icode) (scratch, op0, op1);
7610 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7611 _lower_. We use one compare, but look in different bits of the
7612 CR for each variant.
7614 There are 2 elements in each SPE simd type (upper/lower). The CR
7615 bits are set as follows:
7617 BIT0 | BIT 1 | BIT 2 | BIT 3
7618 U | L | (U | L) | (U & L)
7620 So, for an "all" relationship, BIT 3 would be set.
7621 For an "any" relationship, BIT 2 would be set. Etc.
7623 Following traditional nomenclature, these bits map to:
7625 BIT0 | BIT 1 | BIT 2 | BIT 3
7628 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7633 /* All variant. OV bit. */
7635 /* We need to get to the OV bit, which is the ORDERED bit. We
7636 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7637 that's ugly and will make validate_condition_mode die.
7638 So let's just use another pattern. */
7639 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7641 /* Any variant. EQ bit. */
7645 /* Upper variant. LT bit. */
7649 /* Lower variant. GT bit. */
7654 error ("argument 1 of __builtin_spe_predicate is out of range");
7658 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7659 emit_move_insn (target, tmp);
7664 /* The evsel builtins look like this:
7666 e = __builtin_spe_evsel_OP (a, b, c, d);
7670 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7671 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7675 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7678 tree arg0 = TREE_VALUE (arglist);
7679 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7680 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7681 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7682 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7683 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7684 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7685 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7686 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7687 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7689 gcc_assert (mode0 == mode1);
7691 if (arg0 == error_mark_node || arg1 == error_mark_node
7692 || arg2 == error_mark_node || arg3 == error_mark_node)
7696 || GET_MODE (target) != mode0
7697 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7698 target = gen_reg_rtx (mode0);
7700 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7701 op0 = copy_to_mode_reg (mode0, op0);
7702 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7703 op1 = copy_to_mode_reg (mode0, op1);
7704 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7705 op2 = copy_to_mode_reg (mode0, op2);
7706 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7707 op3 = copy_to_mode_reg (mode0, op3);
7709 /* Generate the compare. */
7710 scratch = gen_reg_rtx (CCmode);
7711 pat = GEN_FCN (icode) (scratch, op0, op1);
7716 if (mode0 == V2SImode)
7717 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7719 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7724 /* Expand an expression EXP that calls a built-in function,
7725 with result going to TARGET if that's convenient
7726 (and in mode MODE if that's convenient).
7727 SUBTARGET may be used as the target for computing one of EXP's operands.
7728 IGNORE is nonzero if the value is to be ignored. */
7731 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7732 enum machine_mode mode ATTRIBUTE_UNUSED,
7733 int ignore ATTRIBUTE_UNUSED)
7735 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7736 tree arglist = TREE_OPERAND (exp, 1);
7737 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7738 struct builtin_description *d;
7743 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7744 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7746 int icode = (int) CODE_FOR_altivec_lvsr;
7747 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7748 enum machine_mode mode = insn_data[icode].operand[1].mode;
7752 gcc_assert (TARGET_ALTIVEC);
7754 arg = TREE_VALUE (arglist);
7755 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7756 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7757 addr = memory_address (mode, op);
7758 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7762 /* For the load case need to negate the address. */
7763 op = gen_reg_rtx (GET_MODE (addr));
7764 emit_insn (gen_rtx_SET (VOIDmode, op,
7765 gen_rtx_NEG (GET_MODE (addr), addr)));
7767 op = gen_rtx_MEM (mode, op);
7770 || GET_MODE (target) != tmode
7771 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7772 target = gen_reg_rtx (tmode);
7774 /*pat = gen_altivec_lvsr (target, op);*/
7775 pat = GEN_FCN (icode) (target, op);
7785 ret = altivec_expand_builtin (exp, target, &success);
7792 ret = spe_expand_builtin (exp, target, &success);
7798 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7800 /* Handle simple unary operations. */
7801 d = (struct builtin_description *) bdesc_1arg;
7802 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7803 if (d->code == fcode)
7804 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7806 /* Handle simple binary operations. */
7807 d = (struct builtin_description *) bdesc_2arg;
7808 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7809 if (d->code == fcode)
7810 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7812 /* Handle simple ternary operations. */
7813 d = (struct builtin_description *) bdesc_3arg;
7814 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7815 if (d->code == fcode)
7816 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7822 build_opaque_vector_type (tree node, int nunits)
7824 node = copy_node (node);
7825 TYPE_MAIN_VARIANT (node) = node;
7826 return build_vector_type (node, nunits);
7830 rs6000_init_builtins (void)
7832 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7833 V2SF_type_node = build_vector_type (float_type_node, 2);
7834 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7835 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7836 V4SF_type_node = build_vector_type (float_type_node, 4);
7837 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7838 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7840 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7841 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7842 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7844 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7845 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7846 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7847 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7849 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7850 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7851 'vector unsigned short'. */
7853 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7854 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7855 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7856 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7858 long_integer_type_internal_node = long_integer_type_node;
7859 long_unsigned_type_internal_node = long_unsigned_type_node;
7860 intQI_type_internal_node = intQI_type_node;
7861 uintQI_type_internal_node = unsigned_intQI_type_node;
7862 intHI_type_internal_node = intHI_type_node;
7863 uintHI_type_internal_node = unsigned_intHI_type_node;
7864 intSI_type_internal_node = intSI_type_node;
7865 uintSI_type_internal_node = unsigned_intSI_type_node;
7866 float_type_internal_node = float_type_node;
7867 void_type_internal_node = void_type_node;
7869 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7870 get_identifier ("__bool char"),
7871 bool_char_type_node));
7872 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7873 get_identifier ("__bool short"),
7874 bool_short_type_node));
7875 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7876 get_identifier ("__bool int"),
7877 bool_int_type_node));
7878 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7879 get_identifier ("__pixel"),
7882 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7883 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7884 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7885 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7887 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7888 get_identifier ("__vector unsigned char"),
7889 unsigned_V16QI_type_node));
7890 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7891 get_identifier ("__vector signed char"),
7893 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7894 get_identifier ("__vector __bool char"),
7895 bool_V16QI_type_node));
7897 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7898 get_identifier ("__vector unsigned short"),
7899 unsigned_V8HI_type_node));
7900 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7901 get_identifier ("__vector signed short"),
7903 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7904 get_identifier ("__vector __bool short"),
7905 bool_V8HI_type_node));
7907 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7908 get_identifier ("__vector unsigned int"),
7909 unsigned_V4SI_type_node));
7910 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7911 get_identifier ("__vector signed int"),
7913 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7914 get_identifier ("__vector __bool int"),
7915 bool_V4SI_type_node));
7917 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7918 get_identifier ("__vector float"),
7920 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7921 get_identifier ("__vector __pixel"),
7922 pixel_V8HI_type_node));
7925 spe_init_builtins ();
7927 altivec_init_builtins ();
7928 if (TARGET_ALTIVEC || TARGET_SPE)
7929 rs6000_common_init_builtins ();
7932 /* Search through a set of builtins and enable the mask bits.
7933 DESC is an array of builtins.
7934 SIZE is the total number of builtins.
7935 START is the builtin enum at which to start.
7936 END is the builtin enum at which to end. */
7938 enable_mask_for_builtins (struct builtin_description *desc, int size,
7939 enum rs6000_builtins start,
7940 enum rs6000_builtins end)
7944 for (i = 0; i < size; ++i)
7945 if (desc[i].code == start)
7951 for (; i < size; ++i)
7953 /* Flip all the bits on. */
7954 desc[i].mask = target_flags;
7955 if (desc[i].code == end)
7961 spe_init_builtins (void)
7963 tree endlink = void_list_node;
7964 tree puint_type_node = build_pointer_type (unsigned_type_node);
7965 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7966 struct builtin_description *d;
7969 tree v2si_ftype_4_v2si
7970 = build_function_type
7971 (opaque_V2SI_type_node,
7972 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7973 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7974 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7975 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7978 tree v2sf_ftype_4_v2sf
7979 = build_function_type
7980 (opaque_V2SF_type_node,
7981 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7982 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7983 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7984 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7987 tree int_ftype_int_v2si_v2si
7988 = build_function_type
7990 tree_cons (NULL_TREE, integer_type_node,
7991 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7992 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7995 tree int_ftype_int_v2sf_v2sf
7996 = build_function_type
7998 tree_cons (NULL_TREE, integer_type_node,
7999 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8000 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8003 tree void_ftype_v2si_puint_int
8004 = build_function_type (void_type_node,
8005 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8006 tree_cons (NULL_TREE, puint_type_node,
8007 tree_cons (NULL_TREE,
8011 tree void_ftype_v2si_puint_char
8012 = build_function_type (void_type_node,
8013 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8014 tree_cons (NULL_TREE, puint_type_node,
8015 tree_cons (NULL_TREE,
8019 tree void_ftype_v2si_pv2si_int
8020 = build_function_type (void_type_node,
8021 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8022 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8023 tree_cons (NULL_TREE,
8027 tree void_ftype_v2si_pv2si_char
8028 = build_function_type (void_type_node,
8029 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8030 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8031 tree_cons (NULL_TREE,
8036 = build_function_type (void_type_node,
8037 tree_cons (NULL_TREE, integer_type_node, endlink));
8040 = build_function_type (integer_type_node, endlink);
8042 tree v2si_ftype_pv2si_int
8043 = build_function_type (opaque_V2SI_type_node,
8044 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8045 tree_cons (NULL_TREE, integer_type_node,
8048 tree v2si_ftype_puint_int
8049 = build_function_type (opaque_V2SI_type_node,
8050 tree_cons (NULL_TREE, puint_type_node,
8051 tree_cons (NULL_TREE, integer_type_node,
8054 tree v2si_ftype_pushort_int
8055 = build_function_type (opaque_V2SI_type_node,
8056 tree_cons (NULL_TREE, pushort_type_node,
8057 tree_cons (NULL_TREE, integer_type_node,
8060 tree v2si_ftype_signed_char
8061 = build_function_type (opaque_V2SI_type_node,
8062 tree_cons (NULL_TREE, signed_char_type_node,
8065 /* The initialization of the simple binary and unary builtins is
8066 done in rs6000_common_init_builtins, but we have to enable the
8067 mask bits here manually because we have run out of `target_flags'
8068 bits. We really need to redesign this mask business. */
8070 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8071 ARRAY_SIZE (bdesc_2arg),
8074 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8075 ARRAY_SIZE (bdesc_1arg),
8077 SPE_BUILTIN_EVSUBFUSIAAW);
8078 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8079 ARRAY_SIZE (bdesc_spe_predicates),
8080 SPE_BUILTIN_EVCMPEQ,
8081 SPE_BUILTIN_EVFSTSTLT);
8082 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8083 ARRAY_SIZE (bdesc_spe_evsel),
8084 SPE_BUILTIN_EVSEL_CMPGTS,
8085 SPE_BUILTIN_EVSEL_FSTSTEQ);
8087 (*lang_hooks.decls.pushdecl)
8088 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8089 opaque_V2SI_type_node));
8091 /* Initialize irregular SPE builtins. */
8093 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8094 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8095 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8096 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8097 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8098 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8099 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8100 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8101 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8102 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8103 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8104 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8105 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8106 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8107 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8108 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8109 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8110 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8113 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8114 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8115 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8116 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8117 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8118 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8119 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8120 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8121 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8122 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8123 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8124 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8125 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8126 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8127 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8128 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8129 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8130 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8131 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8132 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8133 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8134 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8137 d = (struct builtin_description *) bdesc_spe_predicates;
8138 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8142 switch (insn_data[d->icode].operand[1].mode)
8145 type = int_ftype_int_v2si_v2si;
8148 type = int_ftype_int_v2sf_v2sf;
8154 def_builtin (d->mask, d->name, type, d->code);
8157 /* Evsel predicates. */
8158 d = (struct builtin_description *) bdesc_spe_evsel;
8159 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8163 switch (insn_data[d->icode].operand[1].mode)
8166 type = v2si_ftype_4_v2si;
8169 type = v2sf_ftype_4_v2sf;
8175 def_builtin (d->mask, d->name, type, d->code);
8180 altivec_init_builtins (void)
8182 struct builtin_description *d;
8183 struct builtin_description_predicates *dp;
8187 tree pfloat_type_node = build_pointer_type (float_type_node);
8188 tree pint_type_node = build_pointer_type (integer_type_node);
8189 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8190 tree pchar_type_node = build_pointer_type (char_type_node);
8192 tree pvoid_type_node = build_pointer_type (void_type_node);
8194 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8195 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8196 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8197 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8199 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8201 tree int_ftype_opaque
8202 = build_function_type_list (integer_type_node,
8203 opaque_V4SI_type_node, NULL_TREE);
8205 tree opaque_ftype_opaque_int
8206 = build_function_type_list (opaque_V4SI_type_node,
8207 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8208 tree opaque_ftype_opaque_opaque_int
8209 = build_function_type_list (opaque_V4SI_type_node,
8210 opaque_V4SI_type_node, opaque_V4SI_type_node,
8211 integer_type_node, NULL_TREE);
8212 tree int_ftype_int_opaque_opaque
8213 = build_function_type_list (integer_type_node,
8214 integer_type_node, opaque_V4SI_type_node,
8215 opaque_V4SI_type_node, NULL_TREE);
8216 tree int_ftype_int_v4si_v4si
8217 = build_function_type_list (integer_type_node,
8218 integer_type_node, V4SI_type_node,
8219 V4SI_type_node, NULL_TREE);
8220 tree v4sf_ftype_pcfloat
8221 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8222 tree void_ftype_pfloat_v4sf
8223 = build_function_type_list (void_type_node,
8224 pfloat_type_node, V4SF_type_node, NULL_TREE);
8225 tree v4si_ftype_pcint
8226 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8227 tree void_ftype_pint_v4si
8228 = build_function_type_list (void_type_node,
8229 pint_type_node, V4SI_type_node, NULL_TREE);
8230 tree v8hi_ftype_pcshort
8231 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8232 tree void_ftype_pshort_v8hi
8233 = build_function_type_list (void_type_node,
8234 pshort_type_node, V8HI_type_node, NULL_TREE);
8235 tree v16qi_ftype_pcchar
8236 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8237 tree void_ftype_pchar_v16qi
8238 = build_function_type_list (void_type_node,
8239 pchar_type_node, V16QI_type_node, NULL_TREE);
8240 tree void_ftype_v4si
8241 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8242 tree v8hi_ftype_void
8243 = build_function_type (V8HI_type_node, void_list_node);
8244 tree void_ftype_void
8245 = build_function_type (void_type_node, void_list_node);
8247 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8249 tree opaque_ftype_long_pcvoid
8250 = build_function_type_list (opaque_V4SI_type_node,
8251 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8252 tree v16qi_ftype_long_pcvoid
8253 = build_function_type_list (V16QI_type_node,
8254 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8255 tree v8hi_ftype_long_pcvoid
8256 = build_function_type_list (V8HI_type_node,
8257 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8258 tree v4si_ftype_long_pcvoid
8259 = build_function_type_list (V4SI_type_node,
8260 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8262 tree void_ftype_opaque_long_pvoid
8263 = build_function_type_list (void_type_node,
8264 opaque_V4SI_type_node, long_integer_type_node,
8265 pvoid_type_node, NULL_TREE);
8266 tree void_ftype_v4si_long_pvoid
8267 = build_function_type_list (void_type_node,
8268 V4SI_type_node, long_integer_type_node,
8269 pvoid_type_node, NULL_TREE);
8270 tree void_ftype_v16qi_long_pvoid
8271 = build_function_type_list (void_type_node,
8272 V16QI_type_node, long_integer_type_node,
8273 pvoid_type_node, NULL_TREE);
8274 tree void_ftype_v8hi_long_pvoid
8275 = build_function_type_list (void_type_node,
8276 V8HI_type_node, long_integer_type_node,
8277 pvoid_type_node, NULL_TREE);
8278 tree int_ftype_int_v8hi_v8hi
8279 = build_function_type_list (integer_type_node,
8280 integer_type_node, V8HI_type_node,
8281 V8HI_type_node, NULL_TREE);
8282 tree int_ftype_int_v16qi_v16qi
8283 = build_function_type_list (integer_type_node,
8284 integer_type_node, V16QI_type_node,
8285 V16QI_type_node, NULL_TREE);
8286 tree int_ftype_int_v4sf_v4sf
8287 = build_function_type_list (integer_type_node,
8288 integer_type_node, V4SF_type_node,
8289 V4SF_type_node, NULL_TREE);
8290 tree v4si_ftype_v4si
8291 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8292 tree v8hi_ftype_v8hi
8293 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8294 tree v16qi_ftype_v16qi
8295 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8296 tree v4sf_ftype_v4sf
8297 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8298 tree void_ftype_pcvoid_int_int
8299 = build_function_type_list (void_type_node,
8300 pcvoid_type_node, integer_type_node,
8301 integer_type_node, NULL_TREE);
8303 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8304 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8305 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8306 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8307 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8308 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8309 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8310 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8311 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8312 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8313 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8314 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8315 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8316 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8317 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8318 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8319 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8320 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8321 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8322 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8323 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8324 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8325 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8326 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8327 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8328 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8329 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8330 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8331 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8332 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8333 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8334 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8335 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8336 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8337 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8338 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8339 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8340 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8341 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8342 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8343 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8344 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8345 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8346 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8347 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8348 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8350 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8352 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8353 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8354 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8355 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8356 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8357 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8358 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8359 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8360 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8361 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8363 /* Add the DST variants. */
8364 d = (struct builtin_description *) bdesc_dst;
8365 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8366 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8368 /* Initialize the predicates. */
8369 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8370 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8372 enum machine_mode mode1;
8374 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8375 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8380 mode1 = insn_data[dp->icode].operand[1].mode;
8385 type = int_ftype_int_opaque_opaque;
8388 type = int_ftype_int_v4si_v4si;
8391 type = int_ftype_int_v8hi_v8hi;
8394 type = int_ftype_int_v16qi_v16qi;
8397 type = int_ftype_int_v4sf_v4sf;
8403 def_builtin (dp->mask, dp->name, type, dp->code);
8406 /* Initialize the abs* operators. */
8407 d = (struct builtin_description *) bdesc_abs;
8408 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8410 enum machine_mode mode0;
8413 mode0 = insn_data[d->icode].operand[0].mode;
8418 type = v4si_ftype_v4si;
8421 type = v8hi_ftype_v8hi;
8424 type = v16qi_ftype_v16qi;
8427 type = v4sf_ftype_v4sf;
8433 def_builtin (d->mask, d->name, type, d->code);
8440 /* Initialize target builtin that implements
8441 targetm.vectorize.builtin_mask_for_load. */
8443 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8444 v16qi_ftype_long_pcvoid,
8445 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8447 tree_cons (get_identifier ("const"),
8448 NULL_TREE, NULL_TREE));
8449 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8450 altivec_builtin_mask_for_load = decl;
8453 /* Access to the vec_init patterns. */
8454 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8455 integer_type_node, integer_type_node,
8456 integer_type_node, NULL_TREE);
8457 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8458 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8460 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8461 short_integer_type_node,
8462 short_integer_type_node,
8463 short_integer_type_node,
8464 short_integer_type_node,
8465 short_integer_type_node,
8466 short_integer_type_node,
8467 short_integer_type_node, NULL_TREE);
8468 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8469 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8471 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8472 char_type_node, char_type_node,
8473 char_type_node, char_type_node,
8474 char_type_node, char_type_node,
8475 char_type_node, char_type_node,
8476 char_type_node, char_type_node,
8477 char_type_node, char_type_node,
8478 char_type_node, char_type_node,
8479 char_type_node, NULL_TREE);
8480 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8481 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8483 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8484 float_type_node, float_type_node,
8485 float_type_node, NULL_TREE);
8486 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8487 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8489 /* Access to the vec_set patterns. */
8490 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8492 integer_type_node, NULL_TREE);
8493 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8494 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8496 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8498 integer_type_node, NULL_TREE);
8499 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8500 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8502 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8504 integer_type_node, NULL_TREE);
8505 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8506 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8508 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8510 integer_type_node, NULL_TREE);
8511 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8512 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8514 /* Access to the vec_extract patterns. */
8515 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8516 integer_type_node, NULL_TREE);
8517 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8518 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8520 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8521 integer_type_node, NULL_TREE);
8522 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8523 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8525 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8526 integer_type_node, NULL_TREE);
8527 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8528 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8530 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8531 integer_type_node, NULL_TREE);
8532 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8533 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8537 rs6000_common_init_builtins (void)
8539 struct builtin_description *d;
8542 tree v4sf_ftype_v4sf_v4sf_v16qi
8543 = build_function_type_list (V4SF_type_node,
8544 V4SF_type_node, V4SF_type_node,
8545 V16QI_type_node, NULL_TREE);
8546 tree v4si_ftype_v4si_v4si_v16qi
8547 = build_function_type_list (V4SI_type_node,
8548 V4SI_type_node, V4SI_type_node,
8549 V16QI_type_node, NULL_TREE);
8550 tree v8hi_ftype_v8hi_v8hi_v16qi
8551 = build_function_type_list (V8HI_type_node,
8552 V8HI_type_node, V8HI_type_node,
8553 V16QI_type_node, NULL_TREE);
8554 tree v16qi_ftype_v16qi_v16qi_v16qi
8555 = build_function_type_list (V16QI_type_node,
8556 V16QI_type_node, V16QI_type_node,
8557 V16QI_type_node, NULL_TREE);
8559 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8561 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8562 tree v16qi_ftype_int
8563 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8564 tree v8hi_ftype_v16qi
8565 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8566 tree v4sf_ftype_v4sf
8567 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8569 tree v2si_ftype_v2si_v2si
8570 = build_function_type_list (opaque_V2SI_type_node,
8571 opaque_V2SI_type_node,
8572 opaque_V2SI_type_node, NULL_TREE);
8574 tree v2sf_ftype_v2sf_v2sf
8575 = build_function_type_list (opaque_V2SF_type_node,
8576 opaque_V2SF_type_node,
8577 opaque_V2SF_type_node, NULL_TREE);
8579 tree v2si_ftype_int_int
8580 = build_function_type_list (opaque_V2SI_type_node,
8581 integer_type_node, integer_type_node,
8584 tree opaque_ftype_opaque
8585 = build_function_type_list (opaque_V4SI_type_node,
8586 opaque_V4SI_type_node, NULL_TREE);
8588 tree v2si_ftype_v2si
8589 = build_function_type_list (opaque_V2SI_type_node,
8590 opaque_V2SI_type_node, NULL_TREE);
8592 tree v2sf_ftype_v2sf
8593 = build_function_type_list (opaque_V2SF_type_node,
8594 opaque_V2SF_type_node, NULL_TREE);
8596 tree v2sf_ftype_v2si
8597 = build_function_type_list (opaque_V2SF_type_node,
8598 opaque_V2SI_type_node, NULL_TREE);
8600 tree v2si_ftype_v2sf
8601 = build_function_type_list (opaque_V2SI_type_node,
8602 opaque_V2SF_type_node, NULL_TREE);
8604 tree v2si_ftype_v2si_char
8605 = build_function_type_list (opaque_V2SI_type_node,
8606 opaque_V2SI_type_node,
8607 char_type_node, NULL_TREE);
8609 tree v2si_ftype_int_char
8610 = build_function_type_list (opaque_V2SI_type_node,
8611 integer_type_node, char_type_node, NULL_TREE);
8613 tree v2si_ftype_char
8614 = build_function_type_list (opaque_V2SI_type_node,
8615 char_type_node, NULL_TREE);
8617 tree int_ftype_int_int
8618 = build_function_type_list (integer_type_node,
8619 integer_type_node, integer_type_node,
8622 tree opaque_ftype_opaque_opaque
8623 = build_function_type_list (opaque_V4SI_type_node,
8624 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8625 tree v4si_ftype_v4si_v4si
8626 = build_function_type_list (V4SI_type_node,
8627 V4SI_type_node, V4SI_type_node, NULL_TREE);
8628 tree v4sf_ftype_v4si_int
8629 = build_function_type_list (V4SF_type_node,
8630 V4SI_type_node, integer_type_node, NULL_TREE);
8631 tree v4si_ftype_v4sf_int
8632 = build_function_type_list (V4SI_type_node,
8633 V4SF_type_node, integer_type_node, NULL_TREE);
8634 tree v4si_ftype_v4si_int
8635 = build_function_type_list (V4SI_type_node,
8636 V4SI_type_node, integer_type_node, NULL_TREE);
8637 tree v8hi_ftype_v8hi_int
8638 = build_function_type_list (V8HI_type_node,
8639 V8HI_type_node, integer_type_node, NULL_TREE);
8640 tree v16qi_ftype_v16qi_int
8641 = build_function_type_list (V16QI_type_node,
8642 V16QI_type_node, integer_type_node, NULL_TREE);
8643 tree v16qi_ftype_v16qi_v16qi_int
8644 = build_function_type_list (V16QI_type_node,
8645 V16QI_type_node, V16QI_type_node,
8646 integer_type_node, NULL_TREE);
8647 tree v8hi_ftype_v8hi_v8hi_int
8648 = build_function_type_list (V8HI_type_node,
8649 V8HI_type_node, V8HI_type_node,
8650 integer_type_node, NULL_TREE);
8651 tree v4si_ftype_v4si_v4si_int
8652 = build_function_type_list (V4SI_type_node,
8653 V4SI_type_node, V4SI_type_node,
8654 integer_type_node, NULL_TREE);
8655 tree v4sf_ftype_v4sf_v4sf_int
8656 = build_function_type_list (V4SF_type_node,
8657 V4SF_type_node, V4SF_type_node,
8658 integer_type_node, NULL_TREE);
8659 tree v4sf_ftype_v4sf_v4sf
8660 = build_function_type_list (V4SF_type_node,
8661 V4SF_type_node, V4SF_type_node, NULL_TREE);
8662 tree opaque_ftype_opaque_opaque_opaque
8663 = build_function_type_list (opaque_V4SI_type_node,
8664 opaque_V4SI_type_node, opaque_V4SI_type_node,
8665 opaque_V4SI_type_node, NULL_TREE);
8666 tree v4sf_ftype_v4sf_v4sf_v4si
8667 = build_function_type_list (V4SF_type_node,
8668 V4SF_type_node, V4SF_type_node,
8669 V4SI_type_node, NULL_TREE);
8670 tree v4sf_ftype_v4sf_v4sf_v4sf
8671 = build_function_type_list (V4SF_type_node,
8672 V4SF_type_node, V4SF_type_node,
8673 V4SF_type_node, NULL_TREE);
8674 tree v4si_ftype_v4si_v4si_v4si
8675 = build_function_type_list (V4SI_type_node,
8676 V4SI_type_node, V4SI_type_node,
8677 V4SI_type_node, NULL_TREE);
8678 tree v8hi_ftype_v8hi_v8hi
8679 = build_function_type_list (V8HI_type_node,
8680 V8HI_type_node, V8HI_type_node, NULL_TREE);
8681 tree v8hi_ftype_v8hi_v8hi_v8hi
8682 = build_function_type_list (V8HI_type_node,
8683 V8HI_type_node, V8HI_type_node,
8684 V8HI_type_node, NULL_TREE);
8685 tree v4si_ftype_v8hi_v8hi_v4si
8686 = build_function_type_list (V4SI_type_node,
8687 V8HI_type_node, V8HI_type_node,
8688 V4SI_type_node, NULL_TREE);
8689 tree v4si_ftype_v16qi_v16qi_v4si
8690 = build_function_type_list (V4SI_type_node,
8691 V16QI_type_node, V16QI_type_node,
8692 V4SI_type_node, NULL_TREE);
8693 tree v16qi_ftype_v16qi_v16qi
8694 = build_function_type_list (V16QI_type_node,
8695 V16QI_type_node, V16QI_type_node, NULL_TREE);
8696 tree v4si_ftype_v4sf_v4sf
8697 = build_function_type_list (V4SI_type_node,
8698 V4SF_type_node, V4SF_type_node, NULL_TREE);
8699 tree v8hi_ftype_v16qi_v16qi
8700 = build_function_type_list (V8HI_type_node,
8701 V16QI_type_node, V16QI_type_node, NULL_TREE);
8702 tree v4si_ftype_v8hi_v8hi
8703 = build_function_type_list (V4SI_type_node,
8704 V8HI_type_node, V8HI_type_node, NULL_TREE);
8705 tree v8hi_ftype_v4si_v4si
8706 = build_function_type_list (V8HI_type_node,
8707 V4SI_type_node, V4SI_type_node, NULL_TREE);
8708 tree v16qi_ftype_v8hi_v8hi
8709 = build_function_type_list (V16QI_type_node,
8710 V8HI_type_node, V8HI_type_node, NULL_TREE);
8711 tree v4si_ftype_v16qi_v4si
8712 = build_function_type_list (V4SI_type_node,
8713 V16QI_type_node, V4SI_type_node, NULL_TREE);
8714 tree v4si_ftype_v16qi_v16qi
8715 = build_function_type_list (V4SI_type_node,
8716 V16QI_type_node, V16QI_type_node, NULL_TREE);
8717 tree v4si_ftype_v8hi_v4si
8718 = build_function_type_list (V4SI_type_node,
8719 V8HI_type_node, V4SI_type_node, NULL_TREE);
8720 tree v4si_ftype_v8hi
8721 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8722 tree int_ftype_v4si_v4si
8723 = build_function_type_list (integer_type_node,
8724 V4SI_type_node, V4SI_type_node, NULL_TREE);
8725 tree int_ftype_v4sf_v4sf
8726 = build_function_type_list (integer_type_node,
8727 V4SF_type_node, V4SF_type_node, NULL_TREE);
8728 tree int_ftype_v16qi_v16qi
8729 = build_function_type_list (integer_type_node,
8730 V16QI_type_node, V16QI_type_node, NULL_TREE);
8731 tree int_ftype_v8hi_v8hi
8732 = build_function_type_list (integer_type_node,
8733 V8HI_type_node, V8HI_type_node, NULL_TREE);
8735 /* Add the simple ternary operators. */
8736 d = (struct builtin_description *) bdesc_3arg;
8737 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8739 enum machine_mode mode0, mode1, mode2, mode3;
8741 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8742 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8753 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8756 mode0 = insn_data[d->icode].operand[0].mode;
8757 mode1 = insn_data[d->icode].operand[1].mode;
8758 mode2 = insn_data[d->icode].operand[2].mode;
8759 mode3 = insn_data[d->icode].operand[3].mode;
8762 /* When all four are of the same mode. */
8763 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8768 type = opaque_ftype_opaque_opaque_opaque;
8771 type = v4si_ftype_v4si_v4si_v4si;
8774 type = v4sf_ftype_v4sf_v4sf_v4sf;
8777 type = v8hi_ftype_v8hi_v8hi_v8hi;
8780 type = v16qi_ftype_v16qi_v16qi_v16qi;
8786 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8791 type = v4si_ftype_v4si_v4si_v16qi;
8794 type = v4sf_ftype_v4sf_v4sf_v16qi;
8797 type = v8hi_ftype_v8hi_v8hi_v16qi;
8800 type = v16qi_ftype_v16qi_v16qi_v16qi;
8806 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8807 && mode3 == V4SImode)
8808 type = v4si_ftype_v16qi_v16qi_v4si;
8809 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8810 && mode3 == V4SImode)
8811 type = v4si_ftype_v8hi_v8hi_v4si;
8812 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8813 && mode3 == V4SImode)
8814 type = v4sf_ftype_v4sf_v4sf_v4si;
8816 /* vchar, vchar, vchar, 4 bit literal. */
8817 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8819 type = v16qi_ftype_v16qi_v16qi_int;
8821 /* vshort, vshort, vshort, 4 bit literal. */
8822 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8824 type = v8hi_ftype_v8hi_v8hi_int;
8826 /* vint, vint, vint, 4 bit literal. */
8827 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8829 type = v4si_ftype_v4si_v4si_int;
8831 /* vfloat, vfloat, vfloat, 4 bit literal. */
8832 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8834 type = v4sf_ftype_v4sf_v4sf_int;
8839 def_builtin (d->mask, d->name, type, d->code);
8842 /* Add the simple binary operators. */
8843 d = (struct builtin_description *) bdesc_2arg;
8844 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8846 enum machine_mode mode0, mode1, mode2;
8848 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8849 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8859 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8862 mode0 = insn_data[d->icode].operand[0].mode;
8863 mode1 = insn_data[d->icode].operand[1].mode;
8864 mode2 = insn_data[d->icode].operand[2].mode;
8867 /* When all three operands are of the same mode. */
8868 if (mode0 == mode1 && mode1 == mode2)
8873 type = opaque_ftype_opaque_opaque;
8876 type = v4sf_ftype_v4sf_v4sf;
8879 type = v4si_ftype_v4si_v4si;
8882 type = v16qi_ftype_v16qi_v16qi;
8885 type = v8hi_ftype_v8hi_v8hi;
8888 type = v2si_ftype_v2si_v2si;
8891 type = v2sf_ftype_v2sf_v2sf;
8894 type = int_ftype_int_int;
8901 /* A few other combos we really don't want to do manually. */
8903 /* vint, vfloat, vfloat. */
8904 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8905 type = v4si_ftype_v4sf_v4sf;
8907 /* vshort, vchar, vchar. */
8908 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8909 type = v8hi_ftype_v16qi_v16qi;
8911 /* vint, vshort, vshort. */
8912 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8913 type = v4si_ftype_v8hi_v8hi;
8915 /* vshort, vint, vint. */
8916 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8917 type = v8hi_ftype_v4si_v4si;
8919 /* vchar, vshort, vshort. */
8920 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8921 type = v16qi_ftype_v8hi_v8hi;
8923 /* vint, vchar, vint. */
8924 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8925 type = v4si_ftype_v16qi_v4si;
8927 /* vint, vchar, vchar. */
8928 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8929 type = v4si_ftype_v16qi_v16qi;
8931 /* vint, vshort, vint. */
8932 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8933 type = v4si_ftype_v8hi_v4si;
8935 /* vint, vint, 5 bit literal. */
8936 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8937 type = v4si_ftype_v4si_int;
8939 /* vshort, vshort, 5 bit literal. */
8940 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8941 type = v8hi_ftype_v8hi_int;
8943 /* vchar, vchar, 5 bit literal. */
8944 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8945 type = v16qi_ftype_v16qi_int;
8947 /* vfloat, vint, 5 bit literal. */
8948 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8949 type = v4sf_ftype_v4si_int;
8951 /* vint, vfloat, 5 bit literal. */
8952 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8953 type = v4si_ftype_v4sf_int;
8955 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8956 type = v2si_ftype_int_int;
8958 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8959 type = v2si_ftype_v2si_char;
8961 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8962 type = v2si_ftype_int_char;
8967 gcc_assert (mode0 == SImode);
8971 type = int_ftype_v4si_v4si;
8974 type = int_ftype_v4sf_v4sf;
8977 type = int_ftype_v16qi_v16qi;
8980 type = int_ftype_v8hi_v8hi;
8987 def_builtin (d->mask, d->name, type, d->code);
8990 /* Add the simple unary operators. */
8991 d = (struct builtin_description *) bdesc_1arg;
8992 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8994 enum machine_mode mode0, mode1;
8996 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8997 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9006 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9009 mode0 = insn_data[d->icode].operand[0].mode;
9010 mode1 = insn_data[d->icode].operand[1].mode;
9013 if (mode0 == V4SImode && mode1 == QImode)
9014 type = v4si_ftype_int;
9015 else if (mode0 == V8HImode && mode1 == QImode)
9016 type = v8hi_ftype_int;
9017 else if (mode0 == V16QImode && mode1 == QImode)
9018 type = v16qi_ftype_int;
9019 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9020 type = opaque_ftype_opaque;
9021 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9022 type = v4sf_ftype_v4sf;
9023 else if (mode0 == V8HImode && mode1 == V16QImode)
9024 type = v8hi_ftype_v16qi;
9025 else if (mode0 == V4SImode && mode1 == V8HImode)
9026 type = v4si_ftype_v8hi;
9027 else if (mode0 == V2SImode && mode1 == V2SImode)
9028 type = v2si_ftype_v2si;
9029 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9030 type = v2sf_ftype_v2sf;
9031 else if (mode0 == V2SFmode && mode1 == V2SImode)
9032 type = v2sf_ftype_v2si;
9033 else if (mode0 == V2SImode && mode1 == V2SFmode)
9034 type = v2si_ftype_v2sf;
9035 else if (mode0 == V2SImode && mode1 == QImode)
9036 type = v2si_ftype_char;
9040 def_builtin (d->mask, d->name, type, d->code);
9045 rs6000_init_libfuncs (void)
9047 if (!TARGET_HARD_FLOAT)
9050 if (DEFAULT_ABI != ABI_V4)
9052 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
9054 /* AIX library routines for float->int conversion. */
9055 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9056 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9057 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9058 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9061 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9062 if (!TARGET_XL_COMPAT)
9064 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9065 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9066 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9067 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9071 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9072 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9073 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9074 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9079 /* 32-bit SVR4 quad floating point routines. */
9081 set_optab_libfunc (add_optab, TFmode, "_q_add");
9082 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9083 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9084 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9085 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9086 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9087 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9089 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9090 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9091 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9092 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9093 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9094 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9096 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9097 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9098 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9099 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9100 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9101 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9102 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9103 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9108 /* Expand a block clear operation, and return 1 if successful. Return 0
9109 if we should let the compiler generate normal code.
9111 operands[0] is the destination
9112 operands[1] is the length
9113 operands[3] is the alignment */
9116 expand_block_clear (rtx operands[])
9118 rtx orig_dest = operands[0];
9119 rtx bytes_rtx = operands[1];
9120 rtx align_rtx = operands[3];
9121 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9122 HOST_WIDE_INT align;
9123 HOST_WIDE_INT bytes;
9128 /* If this is not a fixed size move, just call memcpy */
9132 /* This must be a fixed size alignment */
9133 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9134 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9136 /* Anything to clear? */
9137 bytes = INTVAL (bytes_rtx);
9141 /* Use the builtin memset after a point, to avoid huge code bloat.
9142 When optimize_size, avoid any significant code bloat; calling
9143 memset is about 4 instructions, so allow for one instruction to
9144 load zero and three to do clearing. */
9145 if (TARGET_ALTIVEC && align >= 128)
9147 else if (TARGET_POWERPC64 && align >= 32)
9152 if (optimize_size && bytes > 3 * clear_step)
9154 if (! optimize_size && bytes > 8 * clear_step)
9157 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9159 enum machine_mode mode = BLKmode;
9162 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9167 else if (bytes >= 8 && TARGET_POWERPC64
9168 /* 64-bit loads and stores require word-aligned
9170 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9175 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9176 { /* move 4 bytes */
9180 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9181 { /* move 2 bytes */
9185 else /* move 1 byte at a time */
9191 dest = adjust_address (orig_dest, mode, offset);
9193 emit_move_insn (dest, CONST0_RTX (mode));
9200 /* Expand a block move operation, and return 1 if successful. Return 0
9201 if we should let the compiler generate normal code.
9203 operands[0] is the destination
9204 operands[1] is the source
9205 operands[2] is the length
9206 operands[3] is the alignment */
9208 #define MAX_MOVE_REG 4
9211 expand_block_move (rtx operands[])
9213 rtx orig_dest = operands[0];
9214 rtx orig_src = operands[1];
9215 rtx bytes_rtx = operands[2];
9216 rtx align_rtx = operands[3];
9217 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9222 rtx stores[MAX_MOVE_REG];
9225 /* If this is not a fixed size move, just call memcpy */
9229 /* This must be a fixed size alignment */
9230 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9231 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9233 /* Anything to move? */
9234 bytes = INTVAL (bytes_rtx);
9238 /* store_one_arg depends on expand_block_move to handle at least the size of
9239 reg_parm_stack_space. */
9240 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9243 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9246 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9247 rtx (*mov) (rtx, rtx);
9249 enum machine_mode mode = BLKmode;
9252 /* Altivec first, since it will be faster than a string move
9253 when it applies, and usually not significantly larger. */
9254 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9258 gen_func.mov = gen_movv4si;
9260 else if (TARGET_STRING
9261 && bytes > 24 /* move up to 32 bytes at a time */
9269 && ! fixed_regs[12])
9271 move_bytes = (bytes > 32) ? 32 : bytes;
9272 gen_func.movmemsi = gen_movmemsi_8reg;
9274 else if (TARGET_STRING
9275 && bytes > 16 /* move up to 24 bytes at a time */
9281 && ! fixed_regs[10])
9283 move_bytes = (bytes > 24) ? 24 : bytes;
9284 gen_func.movmemsi = gen_movmemsi_6reg;
9286 else if (TARGET_STRING
9287 && bytes > 8 /* move up to 16 bytes at a time */
9293 move_bytes = (bytes > 16) ? 16 : bytes;
9294 gen_func.movmemsi = gen_movmemsi_4reg;
9296 else if (bytes >= 8 && TARGET_POWERPC64
9297 /* 64-bit loads and stores require word-aligned
9299 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9303 gen_func.mov = gen_movdi;
9305 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9306 { /* move up to 8 bytes at a time */
9307 move_bytes = (bytes > 8) ? 8 : bytes;
9308 gen_func.movmemsi = gen_movmemsi_2reg;
9310 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9311 { /* move 4 bytes */
9314 gen_func.mov = gen_movsi;
9316 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9317 { /* move 2 bytes */
9320 gen_func.mov = gen_movhi;
9322 else if (TARGET_STRING && bytes > 1)
9323 { /* move up to 4 bytes at a time */
9324 move_bytes = (bytes > 4) ? 4 : bytes;
9325 gen_func.movmemsi = gen_movmemsi_1reg;
9327 else /* move 1 byte at a time */
9331 gen_func.mov = gen_movqi;
9334 src = adjust_address (orig_src, mode, offset);
9335 dest = adjust_address (orig_dest, mode, offset);
9337 if (mode != BLKmode)
9339 rtx tmp_reg = gen_reg_rtx (mode);
9341 emit_insn ((*gen_func.mov) (tmp_reg, src));
9342 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9345 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9348 for (i = 0; i < num_reg; i++)
9349 emit_insn (stores[i]);
9353 if (mode == BLKmode)
9355 /* Move the address into scratch registers. The movmemsi
9356 patterns require zero offset. */
9357 if (!REG_P (XEXP (src, 0)))
9359 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9360 src = replace_equiv_address (src, src_reg);
9362 set_mem_size (src, GEN_INT (move_bytes));
9364 if (!REG_P (XEXP (dest, 0)))
9366 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9367 dest = replace_equiv_address (dest, dest_reg);
9369 set_mem_size (dest, GEN_INT (move_bytes));
9371 emit_insn ((*gen_func.movmemsi) (dest, src,
9372 GEN_INT (move_bytes & 31),
9381 /* Return a string to perform a load_multiple operation.
9382 operands[0] is the vector.
9383 operands[1] is the source address.
9384 operands[2] is the first destination register. */
9387 rs6000_output_load_multiple (rtx operands[3])
9389 /* We have to handle the case where the pseudo used to contain the address
9390 is assigned to one of the output registers. */
9392 int words = XVECLEN (operands[0], 0);
9395 if (XVECLEN (operands[0], 0) == 1)
9396 return "{l|lwz} %2,0(%1)";
9398 for (i = 0; i < words; i++)
9399 if (refers_to_regno_p (REGNO (operands[2]) + i,
9400 REGNO (operands[2]) + i + 1, operands[1], 0))
9404 xop[0] = GEN_INT (4 * (words-1));
9405 xop[1] = operands[1];
9406 xop[2] = operands[2];
9407 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9412 xop[0] = GEN_INT (4 * (words-1));
9413 xop[1] = operands[1];
9414 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9415 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9420 for (j = 0; j < words; j++)
9423 xop[0] = GEN_INT (j * 4);
9424 xop[1] = operands[1];
9425 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9426 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9428 xop[0] = GEN_INT (i * 4);
9429 xop[1] = operands[1];
9430 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9435 return "{lsi|lswi} %2,%1,%N0";
9439 /* A validation routine: say whether CODE, a condition code, and MODE
9440 match. The other alternatives either don't make sense or should
9441 never be generated. */
9444 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9446 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9447 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9448 && GET_MODE_CLASS (mode) == MODE_CC);
9450 /* These don't make sense. */
9451 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9452 || mode != CCUNSmode);
9454 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9455 || mode == CCUNSmode);
9457 gcc_assert (mode == CCFPmode
9458 || (code != ORDERED && code != UNORDERED
9459 && code != UNEQ && code != LTGT
9460 && code != UNGT && code != UNLT
9461 && code != UNGE && code != UNLE));
9463 /* These should never be generated except for
9464 flag_finite_math_only. */
9465 gcc_assert (mode != CCFPmode
9466 || flag_finite_math_only
9467 || (code != LE && code != GE
9468 && code != UNEQ && code != LTGT
9469 && code != UNGT && code != UNLT));
9471 /* These are invalid; the information is not there. */
9472 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9476 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9477 mask required to convert the result of a rotate insn into a shift
9478 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9481 includes_lshift_p (rtx shiftop, rtx andop)
9483 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9485 shift_mask <<= INTVAL (shiftop);
9487 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9490 /* Similar, but for right shift. */
9493 includes_rshift_p (rtx shiftop, rtx andop)
9495 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9497 shift_mask >>= INTVAL (shiftop);
9499 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9502 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9503 to perform a left shift. It must have exactly SHIFTOP least
9504 significant 0's, then one or more 1's, then zero or more 0's. */
9507 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9509 if (GET_CODE (andop) == CONST_INT)
9511 HOST_WIDE_INT c, lsb, shift_mask;
9514 if (c == 0 || c == ~0)
9518 shift_mask <<= INTVAL (shiftop);
9520 /* Find the least significant one bit. */
9523 /* It must coincide with the LSB of the shift mask. */
9524 if (-lsb != shift_mask)
9527 /* Invert to look for the next transition (if any). */
9530 /* Remove the low group of ones (originally low group of zeros). */
9533 /* Again find the lsb, and check we have all 1's above. */
9537 else if (GET_CODE (andop) == CONST_DOUBLE
9538 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9540 HOST_WIDE_INT low, high, lsb;
9541 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9543 low = CONST_DOUBLE_LOW (andop);
9544 if (HOST_BITS_PER_WIDE_INT < 64)
9545 high = CONST_DOUBLE_HIGH (andop);
9547 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9548 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9551 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9553 shift_mask_high = ~0;
9554 if (INTVAL (shiftop) > 32)
9555 shift_mask_high <<= INTVAL (shiftop) - 32;
9559 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9566 return high == -lsb;
9569 shift_mask_low = ~0;
9570 shift_mask_low <<= INTVAL (shiftop);
9574 if (-lsb != shift_mask_low)
9577 if (HOST_BITS_PER_WIDE_INT < 64)
9582 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9585 return high == -lsb;
9589 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9595 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9596 to perform a left shift. It must have SHIFTOP or more least
9597 significant 0's, with the remainder of the word 1's. */
9600 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9602 if (GET_CODE (andop) == CONST_INT)
9604 HOST_WIDE_INT c, lsb, shift_mask;
9607 shift_mask <<= INTVAL (shiftop);
9610 /* Find the least significant one bit. */
9613 /* It must be covered by the shift mask.
9614 This test also rejects c == 0. */
9615 if ((lsb & shift_mask) == 0)
9618 /* Check we have all 1's above the transition, and reject all 1's. */
9619 return c == -lsb && lsb != 1;
9621 else if (GET_CODE (andop) == CONST_DOUBLE
9622 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9624 HOST_WIDE_INT low, lsb, shift_mask_low;
9626 low = CONST_DOUBLE_LOW (andop);
9628 if (HOST_BITS_PER_WIDE_INT < 64)
9630 HOST_WIDE_INT high, shift_mask_high;
9632 high = CONST_DOUBLE_HIGH (andop);
9636 shift_mask_high = ~0;
9637 if (INTVAL (shiftop) > 32)
9638 shift_mask_high <<= INTVAL (shiftop) - 32;
9642 if ((lsb & shift_mask_high) == 0)
9645 return high == -lsb;
9651 shift_mask_low = ~0;
9652 shift_mask_low <<= INTVAL (shiftop);
9656 if ((lsb & shift_mask_low) == 0)
9659 return low == -lsb && lsb != 1;
9665 /* Return 1 if operands will generate a valid arguments to rlwimi
9666 instruction for insert with right shift in 64-bit mode. The mask may
9667 not start on the first bit or stop on the last bit because wrap-around
9668 effects of instruction do not correspond to semantics of RTL insn. */
9671 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9673 if (INTVAL (startop) < 64
9674 && INTVAL (startop) > 32
9675 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9676 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9677 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9678 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9679 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9685 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9686 for lfq and stfq insns iff the registers are hard registers. */
9689 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9691 /* We might have been passed a SUBREG. */
9692 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9695 /* We might have been passed non floating point registers. */
9696 if (!FP_REGNO_P (REGNO (reg1))
9697 || !FP_REGNO_P (REGNO (reg2)))
9700 return (REGNO (reg1) == REGNO (reg2) - 1);
9703 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9704 addr1 and addr2 must be in consecutive memory locations
9705 (addr2 == addr1 + 8). */
9708 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9711 unsigned int reg1, reg2;
9712 int offset1, offset2;
9714 /* The mems cannot be volatile. */
9715 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9718 addr1 = XEXP (mem1, 0);
9719 addr2 = XEXP (mem2, 0);
9721 /* Extract an offset (if used) from the first addr. */
9722 if (GET_CODE (addr1) == PLUS)
9724 /* If not a REG, return zero. */
9725 if (GET_CODE (XEXP (addr1, 0)) != REG)
9729 reg1 = REGNO (XEXP (addr1, 0));
9730 /* The offset must be constant! */
9731 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9733 offset1 = INTVAL (XEXP (addr1, 1));
9736 else if (GET_CODE (addr1) != REG)
9740 reg1 = REGNO (addr1);
9741 /* This was a simple (mem (reg)) expression. Offset is 0. */
9745 /* And now for the second addr. */
9746 if (GET_CODE (addr2) == PLUS)
9748 /* If not a REG, return zero. */
9749 if (GET_CODE (XEXP (addr2, 0)) != REG)
9753 reg2 = REGNO (XEXP (addr2, 0));
9754 /* The offset must be constant. */
9755 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9757 offset2 = INTVAL (XEXP (addr2, 1));
9760 else if (GET_CODE (addr2) != REG)
9764 reg2 = REGNO (addr2);
9765 /* This was a simple (mem (reg)) expression. Offset is 0. */
9769 /* Both of these must have the same base register. */
9773 /* The offset for the second addr must be 8 more than the first addr. */
9774 if (offset2 != offset1 + 8)
9777 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9782 /* Return the register class of a scratch register needed to copy IN into
9783 or out of a register in CLASS in MODE. If it can be done directly,
9784 NO_REGS is returned. */
9787 rs6000_secondary_reload_class (enum reg_class class,
9788 enum machine_mode mode ATTRIBUTE_UNUSED,
9793 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9795 && MACHOPIC_INDIRECT
9799 /* We cannot copy a symbolic operand directly into anything
9800 other than BASE_REGS for TARGET_ELF. So indicate that a
9801 register from BASE_REGS is needed as an intermediate
9804 On Darwin, pic addresses require a load from memory, which
9805 needs a base register. */
9806 if (class != BASE_REGS
9807 && (GET_CODE (in) == SYMBOL_REF
9808 || GET_CODE (in) == HIGH
9809 || GET_CODE (in) == LABEL_REF
9810 || GET_CODE (in) == CONST))
9814 if (GET_CODE (in) == REG)
9817 if (regno >= FIRST_PSEUDO_REGISTER)
9819 regno = true_regnum (in);
9820 if (regno >= FIRST_PSEUDO_REGISTER)
9824 else if (GET_CODE (in) == SUBREG)
9826 regno = true_regnum (in);
9827 if (regno >= FIRST_PSEUDO_REGISTER)
9833 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9835 if (class == GENERAL_REGS || class == BASE_REGS
9836 || (regno >= 0 && INT_REGNO_P (regno)))
9839 /* Constants, memory, and FP registers can go into FP registers. */
9840 if ((regno == -1 || FP_REGNO_P (regno))
9841 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9844 /* Memory, and AltiVec registers can go into AltiVec registers. */
9845 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9846 && class == ALTIVEC_REGS)
9849 /* We can copy among the CR registers. */
9850 if ((class == CR_REGS || class == CR0_REGS)
9851 && regno >= 0 && CR_REGNO_P (regno))
9854 /* Otherwise, we need GENERAL_REGS. */
9855 return GENERAL_REGS;
9858 /* Given a comparison operation, return the bit number in CCR to test. We
9859 know this is a valid comparison.
9861 SCC_P is 1 if this is for an scc. That means that %D will have been
9862 used instead of %C, so the bits will be in different places.
9864 Return -1 if OP isn't a valid comparison for some reason. */
9867 ccr_bit (rtx op, int scc_p)
9869 enum rtx_code code = GET_CODE (op);
9870 enum machine_mode cc_mode;
9875 if (!COMPARISON_P (op))
9880 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9882 cc_mode = GET_MODE (reg);
9883 cc_regnum = REGNO (reg);
9884 base_bit = 4 * (cc_regnum - CR0_REGNO);
9886 validate_condition_mode (code, cc_mode);
9888 /* When generating a sCOND operation, only positive conditions are
9891 || code == EQ || code == GT || code == LT || code == UNORDERED
9892 || code == GTU || code == LTU);
9897 return scc_p ? base_bit + 3 : base_bit + 2;
9899 return base_bit + 2;
9900 case GT: case GTU: case UNLE:
9901 return base_bit + 1;
9902 case LT: case LTU: case UNGE:
9904 case ORDERED: case UNORDERED:
9905 return base_bit + 3;
9908 /* If scc, we will have done a cror to put the bit in the
9909 unordered position. So test that bit. For integer, this is ! LT
9910 unless this is an scc insn. */
9911 return scc_p ? base_bit + 3 : base_bit;
9914 return scc_p ? base_bit + 3 : base_bit + 1;
9921 /* Return the GOT register. */
9924 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9926 /* The second flow pass currently (June 1999) can't update
9927 regs_ever_live without disturbing other parts of the compiler, so
9928 update it here to make the prolog/epilogue code happy. */
9929 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9930 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9932 current_function_uses_pic_offset_table = 1;
9934 return pic_offset_table_rtx;
9937 /* Function to init struct machine_function.
9938 This will be called, via a pointer variable,
9939 from push_function_context. */
9941 static struct machine_function *
9942 rs6000_init_machine_status (void)
9944 return ggc_alloc_cleared (sizeof (machine_function));
9947 /* These macros test for integers and extract the low-order bits. */
9949 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9950 && GET_MODE (X) == VOIDmode)
9952 #define INT_LOWPART(X) \
9953 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9959 unsigned long val = INT_LOWPART (op);
9961 /* If the high bit is zero, the value is the first 1 bit we find
9963 if ((val & 0x80000000) == 0)
9965 gcc_assert (val & 0xffffffff);
9968 while (((val <<= 1) & 0x80000000) == 0)
9973 /* If the high bit is set and the low bit is not, or the mask is all
9974 1's, the value is zero. */
9975 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9978 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9981 while (((val >>= 1) & 1) != 0)
9991 unsigned long val = INT_LOWPART (op);
9993 /* If the low bit is zero, the value is the first 1 bit we find from
9997 gcc_assert (val & 0xffffffff);
10000 while (((val >>= 1) & 1) == 0)
10006 /* If the low bit is set and the high bit is not, or the mask is all
10007 1's, the value is 31. */
10008 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10011 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10014 while (((val <<= 1) & 0x80000000) != 0)
10020 /* Locate some local-dynamic symbol still in use by this function
10021 so that we can print its name in some tls_ld pattern. */
10023 static const char *
10024 rs6000_get_some_local_dynamic_name (void)
10028 if (cfun->machine->some_ld_name)
10029 return cfun->machine->some_ld_name;
10031 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10033 && for_each_rtx (&PATTERN (insn),
10034 rs6000_get_some_local_dynamic_name_1, 0))
10035 return cfun->machine->some_ld_name;
10037 gcc_unreachable ();
10040 /* Helper function for rs6000_get_some_local_dynamic_name. */
10043 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10047 if (GET_CODE (x) == SYMBOL_REF)
10049 const char *str = XSTR (x, 0);
10050 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10052 cfun->machine->some_ld_name = str;
10060 /* Write out a function code label. */
10063 rs6000_output_function_entry (FILE *file, const char *fname)
10065 if (fname[0] != '.')
10067 switch (DEFAULT_ABI)
10070 gcc_unreachable ();
10076 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10085 RS6000_OUTPUT_BASENAME (file, fname);
10087 assemble_name (file, fname);
10090 /* Print an operand. Recognize special options, documented below. */
10093 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10094 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10096 #define SMALL_DATA_RELOC "sda21"
10097 #define SMALL_DATA_REG 0
10101 print_operand (FILE *file, rtx x, int code)
10105 unsigned HOST_WIDE_INT uval;
10110 /* Write out an instruction after the call which may be replaced
10111 with glue code by the loader. This depends on the AIX version. */
10112 asm_fprintf (file, RS6000_CALL_GLUE);
10115 /* %a is output_address. */
10118 /* If X is a constant integer whose low-order 5 bits are zero,
10119 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10120 in the AIX assembler where "sri" with a zero shift count
10121 writes a trash instruction. */
10122 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10129 /* If constant, low-order 16 bits of constant, unsigned.
10130 Otherwise, write normally. */
10132 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10134 print_operand (file, x, 0);
10138 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10139 for 64-bit mask direction. */
10140 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10143 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10147 /* X is a CR register. Print the number of the GT bit of the CR. */
10148 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10149 output_operand_lossage ("invalid %%E value");
10151 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10155 /* Like 'J' but get to the EQ bit. */
10156 gcc_assert (GET_CODE (x) == REG);
10158 /* Bit 1 is EQ bit. */
10159 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10161 fprintf (file, "%d", i);
10165 /* X is a CR register. Print the number of the EQ bit of the CR */
10166 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10167 output_operand_lossage ("invalid %%E value");
10169 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10173 /* X is a CR register. Print the shift count needed to move it
10174 to the high-order four bits. */
10175 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10176 output_operand_lossage ("invalid %%f value");
10178 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10182 /* Similar, but print the count for the rotate in the opposite
10184 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10185 output_operand_lossage ("invalid %%F value");
10187 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10191 /* X is a constant integer. If it is negative, print "m",
10192 otherwise print "z". This is to make an aze or ame insn. */
10193 if (GET_CODE (x) != CONST_INT)
10194 output_operand_lossage ("invalid %%G value");
10195 else if (INTVAL (x) >= 0)
10202 /* If constant, output low-order five bits. Otherwise, write
10205 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10207 print_operand (file, x, 0);
10211 /* If constant, output low-order six bits. Otherwise, write
10214 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10216 print_operand (file, x, 0);
10220 /* Print `i' if this is a constant, else nothing. */
10226 /* Write the bit number in CCR for jump. */
10227 i = ccr_bit (x, 0);
10229 output_operand_lossage ("invalid %%j code");
10231 fprintf (file, "%d", i);
10235 /* Similar, but add one for shift count in rlinm for scc and pass
10236 scc flag to `ccr_bit'. */
10237 i = ccr_bit (x, 1);
10239 output_operand_lossage ("invalid %%J code");
10241 /* If we want bit 31, write a shift count of zero, not 32. */
10242 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10246 /* X must be a constant. Write the 1's complement of the
10249 output_operand_lossage ("invalid %%k value");
10251 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10255 /* X must be a symbolic constant on ELF. Write an
10256 expression suitable for an 'addi' that adds in the low 16
10257 bits of the MEM. */
10258 if (GET_CODE (x) != CONST)
10260 print_operand_address (file, x);
10261 fputs ("@l", file);
10265 if (GET_CODE (XEXP (x, 0)) != PLUS
10266 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10267 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10268 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10269 output_operand_lossage ("invalid %%K value");
10270 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10271 fputs ("@l", file);
10272 /* For GNU as, there must be a non-alphanumeric character
10273 between 'l' and the number. The '-' is added by
10274 print_operand() already. */
10275 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10277 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10281 /* %l is output_asm_label. */
10284 /* Write second word of DImode or DFmode reference. Works on register
10285 or non-indexed memory only. */
10286 if (GET_CODE (x) == REG)
10287 fputs (reg_names[REGNO (x) + 1], file);
10288 else if (GET_CODE (x) == MEM)
10290 /* Handle possible auto-increment. Since it is pre-increment and
10291 we have already done it, we can just use an offset of word. */
10292 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10293 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10294 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10297 output_address (XEXP (adjust_address_nv (x, SImode,
10301 if (small_data_operand (x, GET_MODE (x)))
10302 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10303 reg_names[SMALL_DATA_REG]);
10308 /* MB value for a mask operand. */
10309 if (! mask_operand (x, SImode))
10310 output_operand_lossage ("invalid %%m value");
10312 fprintf (file, "%d", extract_MB (x));
10316 /* ME value for a mask operand. */
10317 if (! mask_operand (x, SImode))
10318 output_operand_lossage ("invalid %%M value");
10320 fprintf (file, "%d", extract_ME (x));
10323 /* %n outputs the negative of its operand. */
10326 /* Write the number of elements in the vector times 4. */
10327 if (GET_CODE (x) != PARALLEL)
10328 output_operand_lossage ("invalid %%N value");
10330 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10334 /* Similar, but subtract 1 first. */
10335 if (GET_CODE (x) != PARALLEL)
10336 output_operand_lossage ("invalid %%O value");
10338 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10342 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10344 || INT_LOWPART (x) < 0
10345 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10346 output_operand_lossage ("invalid %%p value");
10348 fprintf (file, "%d", i);
10352 /* The operand must be an indirect memory reference. The result
10353 is the register name. */
10354 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10355 || REGNO (XEXP (x, 0)) >= 32)
10356 output_operand_lossage ("invalid %%P value");
10358 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10362 /* This outputs the logical code corresponding to a boolean
10363 expression. The expression may have one or both operands
10364 negated (if one, only the first one). For condition register
10365 logical operations, it will also treat the negated
10366 CR codes as NOTs, but not handle NOTs of them. */
10368 const char *const *t = 0;
10370 enum rtx_code code = GET_CODE (x);
10371 static const char * const tbl[3][3] = {
10372 { "and", "andc", "nor" },
10373 { "or", "orc", "nand" },
10374 { "xor", "eqv", "xor" } };
10378 else if (code == IOR)
10380 else if (code == XOR)
10383 output_operand_lossage ("invalid %%q value");
10385 if (GET_CODE (XEXP (x, 0)) != NOT)
10389 if (GET_CODE (XEXP (x, 1)) == NOT)
10407 /* X is a CR register. Print the mask for `mtcrf'. */
10408 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10409 output_operand_lossage ("invalid %%R value");
10411 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10415 /* Low 5 bits of 32 - value */
10417 output_operand_lossage ("invalid %%s value");
10419 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10423 /* PowerPC64 mask position. All 0's is excluded.
10424 CONST_INT 32-bit mask is considered sign-extended so any
10425 transition must occur within the CONST_INT, not on the boundary. */
10426 if (! mask64_operand (x, DImode))
10427 output_operand_lossage ("invalid %%S value");
10429 uval = INT_LOWPART (x);
10431 if (uval & 1) /* Clear Left */
10433 #if HOST_BITS_PER_WIDE_INT > 64
10434 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10438 else /* Clear Right */
10441 #if HOST_BITS_PER_WIDE_INT > 64
10442 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10448 gcc_assert (i >= 0);
10449 fprintf (file, "%d", i);
10453 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10454 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10456 /* Bit 3 is OV bit. */
10457 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10459 /* If we want bit 31, write a shift count of zero, not 32. */
10460 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10464 /* Print the symbolic name of a branch target register. */
10465 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10466 && REGNO (x) != COUNT_REGISTER_REGNUM))
10467 output_operand_lossage ("invalid %%T value");
10468 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10469 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10471 fputs ("ctr", file);
10475 /* High-order 16 bits of constant for use in unsigned operand. */
10477 output_operand_lossage ("invalid %%u value");
10479 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10480 (INT_LOWPART (x) >> 16) & 0xffff);
10484 /* High-order 16 bits of constant for use in signed operand. */
10486 output_operand_lossage ("invalid %%v value");
10488 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10489 (INT_LOWPART (x) >> 16) & 0xffff);
10493 /* Print `u' if this has an auto-increment or auto-decrement. */
10494 if (GET_CODE (x) == MEM
10495 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10496 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10501 /* Print the trap code for this operand. */
10502 switch (GET_CODE (x))
10505 fputs ("eq", file); /* 4 */
10508 fputs ("ne", file); /* 24 */
10511 fputs ("lt", file); /* 16 */
10514 fputs ("le", file); /* 20 */
10517 fputs ("gt", file); /* 8 */
10520 fputs ("ge", file); /* 12 */
10523 fputs ("llt", file); /* 2 */
10526 fputs ("lle", file); /* 6 */
10529 fputs ("lgt", file); /* 1 */
10532 fputs ("lge", file); /* 5 */
10535 gcc_unreachable ();
10540 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10543 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10544 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10546 print_operand (file, x, 0);
10550 /* MB value for a PowerPC64 rldic operand. */
10551 val = (GET_CODE (x) == CONST_INT
10552 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10557 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10558 if ((val <<= 1) < 0)
10561 #if HOST_BITS_PER_WIDE_INT == 32
10562 if (GET_CODE (x) == CONST_INT && i >= 0)
10563 i += 32; /* zero-extend high-part was all 0's */
10564 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10566 val = CONST_DOUBLE_LOW (x);
10572 for ( ; i < 64; i++)
10573 if ((val <<= 1) < 0)
10578 fprintf (file, "%d", i + 1);
10582 if (GET_CODE (x) == MEM
10583 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10588 /* Like 'L', for third word of TImode */
10589 if (GET_CODE (x) == REG)
10590 fputs (reg_names[REGNO (x) + 2], file);
10591 else if (GET_CODE (x) == MEM)
10593 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10594 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10595 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10597 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10598 if (small_data_operand (x, GET_MODE (x)))
10599 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10600 reg_names[SMALL_DATA_REG]);
10605 /* X is a SYMBOL_REF. Write out the name preceded by a
10606 period and without any trailing data in brackets. Used for function
10607 names. If we are configured for System V (or the embedded ABI) on
10608 the PowerPC, do not emit the period, since those systems do not use
10609 TOCs and the like. */
10610 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10612 /* Mark the decl as referenced so that cgraph will output the
10614 if (SYMBOL_REF_DECL (x))
10615 mark_decl_referenced (SYMBOL_REF_DECL (x));
10617 /* For macho, check to see if we need a stub. */
10620 const char *name = XSTR (x, 0);
10622 if (MACHOPIC_INDIRECT
10623 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10624 name = machopic_indirection_name (x, /*stub_p=*/true);
10626 assemble_name (file, name);
10628 else if (!DOT_SYMBOLS)
10629 assemble_name (file, XSTR (x, 0));
10631 rs6000_output_function_entry (file, XSTR (x, 0));
10635 /* Like 'L', for last word of TImode. */
10636 if (GET_CODE (x) == REG)
10637 fputs (reg_names[REGNO (x) + 3], file);
10638 else if (GET_CODE (x) == MEM)
10640 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10641 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10642 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10644 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10645 if (small_data_operand (x, GET_MODE (x)))
10646 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10647 reg_names[SMALL_DATA_REG]);
10651 /* Print AltiVec or SPE memory operand. */
10656 gcc_assert (GET_CODE (x) == MEM);
10662 /* Handle [reg]. */
10663 if (GET_CODE (tmp) == REG)
10665 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10668 /* Handle [reg+UIMM]. */
10669 else if (GET_CODE (tmp) == PLUS &&
10670 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10674 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10676 x = INTVAL (XEXP (tmp, 1));
10677 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10681 /* Fall through. Must be [reg+reg]. */
10684 && GET_CODE (tmp) == AND
10685 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10686 && INTVAL (XEXP (tmp, 1)) == -16)
10687 tmp = XEXP (tmp, 0);
10688 if (GET_CODE (tmp) == REG)
10689 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10692 gcc_assert (GET_CODE (tmp) == PLUS
10693 && REG_P (XEXP (tmp, 0))
10694 && REG_P (XEXP (tmp, 1)));
10696 if (REGNO (XEXP (tmp, 0)) == 0)
10697 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10698 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10700 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10701 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10707 if (GET_CODE (x) == REG)
10708 fprintf (file, "%s", reg_names[REGNO (x)]);
10709 else if (GET_CODE (x) == MEM)
10711 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10712 know the width from the mode. */
10713 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10714 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10715 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10716 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10717 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10718 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10720 output_address (XEXP (x, 0));
10723 output_addr_const (file, x);
10727 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10731 output_operand_lossage ("invalid %%xn code");
10735 /* Print the address of an operand. */
10738 print_operand_address (FILE *file, rtx x)
10740 if (GET_CODE (x) == REG)
10741 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10742 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10743 || GET_CODE (x) == LABEL_REF)
10745 output_addr_const (file, x);
10746 if (small_data_operand (x, GET_MODE (x)))
10747 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10748 reg_names[SMALL_DATA_REG]);
10750 gcc_assert (!TARGET_TOC);
10752 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10754 gcc_assert (REG_P (XEXP (x, 0)));
10755 if (REGNO (XEXP (x, 0)) == 0)
10756 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10757 reg_names[ REGNO (XEXP (x, 0)) ]);
10759 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10760 reg_names[ REGNO (XEXP (x, 1)) ]);
10762 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10763 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10764 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10766 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10767 && CONSTANT_P (XEXP (x, 1)))
10769 output_addr_const (file, XEXP (x, 1));
10770 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10774 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10775 && CONSTANT_P (XEXP (x, 1)))
10777 fprintf (file, "lo16(");
10778 output_addr_const (file, XEXP (x, 1));
10779 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10782 else if (legitimate_constant_pool_address_p (x))
10784 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10786 rtx contains_minus = XEXP (x, 1);
10790 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10791 turn it into (sym) for output_addr_const. */
10792 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10793 contains_minus = XEXP (contains_minus, 0);
10795 minus = XEXP (contains_minus, 0);
10796 symref = XEXP (minus, 0);
10797 XEXP (contains_minus, 0) = symref;
10802 name = XSTR (symref, 0);
10803 newname = alloca (strlen (name) + sizeof ("@toc"));
10804 strcpy (newname, name);
10805 strcat (newname, "@toc");
10806 XSTR (symref, 0) = newname;
10808 output_addr_const (file, XEXP (x, 1));
10810 XSTR (symref, 0) = name;
10811 XEXP (contains_minus, 0) = minus;
10814 output_addr_const (file, XEXP (x, 1));
10816 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10819 gcc_unreachable ();
10822 /* Target hook for assembling integer objects. The PowerPC version has
10823 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10824 is defined. It also needs to handle DI-mode objects on 64-bit
10828 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10830 #ifdef RELOCATABLE_NEEDS_FIXUP
10831 /* Special handling for SI values. */
10832 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10834 static int recurse = 0;
10836 /* For -mrelocatable, we mark all addresses that need to be fixed up
10837 in the .fixup section. */
10838 if (TARGET_RELOCATABLE
10839 && in_section != toc_section
10840 && in_section != text_section
10841 && !unlikely_text_section_p (in_section)
10843 && GET_CODE (x) != CONST_INT
10844 && GET_CODE (x) != CONST_DOUBLE
10850 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10852 ASM_OUTPUT_LABEL (asm_out_file, buf);
10853 fprintf (asm_out_file, "\t.long\t(");
10854 output_addr_const (asm_out_file, x);
10855 fprintf (asm_out_file, ")@fixup\n");
10856 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10857 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10858 fprintf (asm_out_file, "\t.long\t");
10859 assemble_name (asm_out_file, buf);
10860 fprintf (asm_out_file, "\n\t.previous\n");
10864 /* Remove initial .'s to turn a -mcall-aixdesc function
10865 address into the address of the descriptor, not the function
10867 else if (GET_CODE (x) == SYMBOL_REF
10868 && XSTR (x, 0)[0] == '.'
10869 && DEFAULT_ABI == ABI_AIX)
10871 const char *name = XSTR (x, 0);
10872 while (*name == '.')
10875 fprintf (asm_out_file, "\t.long\t%s\n", name);
10879 #endif /* RELOCATABLE_NEEDS_FIXUP */
10880 return default_assemble_integer (x, size, aligned_p);
10883 #ifdef HAVE_GAS_HIDDEN
10884 /* Emit an assembler directive to set symbol visibility for DECL to
10885 VISIBILITY_TYPE. */
10888 rs6000_assemble_visibility (tree decl, int vis)
10890 /* Functions need to have their entry point symbol visibility set as
10891 well as their descriptor symbol visibility. */
10892 if (DEFAULT_ABI == ABI_AIX
10894 && TREE_CODE (decl) == FUNCTION_DECL)
10896 static const char * const visibility_types[] = {
10897 NULL, "internal", "hidden", "protected"
10900 const char *name, *type;
10902 name = ((* targetm.strip_name_encoding)
10903 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10904 type = visibility_types[vis];
10906 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10907 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10910 default_assemble_visibility (decl, vis);
10915 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10917 /* Reversal of FP compares takes care -- an ordered compare
10918 becomes an unordered compare and vice versa. */
10919 if (mode == CCFPmode
10920 && (!flag_finite_math_only
10921 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10922 || code == UNEQ || code == LTGT))
10923 return reverse_condition_maybe_unordered (code);
10925 return reverse_condition (code);
10928 /* Generate a compare for CODE. Return a brand-new rtx that
10929 represents the result of the compare. */
10932 rs6000_generate_compare (enum rtx_code code)
10934 enum machine_mode comp_mode;
10935 rtx compare_result;
10937 if (rs6000_compare_fp_p)
10938 comp_mode = CCFPmode;
10939 else if (code == GTU || code == LTU
10940 || code == GEU || code == LEU)
10941 comp_mode = CCUNSmode;
10942 else if ((code == EQ || code == NE)
10943 && GET_CODE (rs6000_compare_op0) == SUBREG
10944 && GET_CODE (rs6000_compare_op1) == SUBREG
10945 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10946 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10947 /* These are unsigned values, perhaps there will be a later
10948 ordering compare that can be shared with this one.
10949 Unfortunately we cannot detect the signedness of the operands
10950 for non-subregs. */
10951 comp_mode = CCUNSmode;
10953 comp_mode = CCmode;
10955 /* First, the compare. */
10956 compare_result = gen_reg_rtx (comp_mode);
10958 /* SPE FP compare instructions on the GPRs. Yuck! */
10959 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10960 && rs6000_compare_fp_p)
10962 rtx cmp, or_result, compare_result2;
10963 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10965 if (op_mode == VOIDmode)
10966 op_mode = GET_MODE (rs6000_compare_op1);
10968 /* Note: The E500 comparison instructions set the GT bit (x +
10969 1), on success. This explains the mess. */
10973 case EQ: case UNEQ: case NE: case LTGT:
10977 cmp = flag_unsafe_math_optimizations
10978 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10979 rs6000_compare_op1)
10980 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10981 rs6000_compare_op1);
10985 cmp = flag_unsafe_math_optimizations
10986 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10987 rs6000_compare_op1)
10988 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10989 rs6000_compare_op1);
10993 gcc_unreachable ();
10997 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11001 cmp = flag_unsafe_math_optimizations
11002 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11003 rs6000_compare_op1)
11004 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11005 rs6000_compare_op1);
11009 cmp = flag_unsafe_math_optimizations
11010 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11011 rs6000_compare_op1)
11012 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11013 rs6000_compare_op1);
11017 gcc_unreachable ();
11021 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11025 cmp = flag_unsafe_math_optimizations
11026 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11027 rs6000_compare_op1)
11028 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11029 rs6000_compare_op1);
11033 cmp = flag_unsafe_math_optimizations
11034 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11035 rs6000_compare_op1)
11036 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11037 rs6000_compare_op1);
11041 gcc_unreachable ();
11045 gcc_unreachable ();
11048 /* Synthesize LE and GE from LT/GT || EQ. */
11049 if (code == LE || code == GE || code == LEU || code == GEU)
11055 case LE: code = LT; break;
11056 case GE: code = GT; break;
11057 case LEU: code = LT; break;
11058 case GEU: code = GT; break;
11059 default: gcc_unreachable ();
11062 compare_result2 = gen_reg_rtx (CCFPmode);
11068 cmp = flag_unsafe_math_optimizations
11069 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11070 rs6000_compare_op1)
11071 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11072 rs6000_compare_op1);
11076 cmp = flag_unsafe_math_optimizations
11077 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11078 rs6000_compare_op1)
11079 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11080 rs6000_compare_op1);
11084 gcc_unreachable ();
11088 /* OR them together. */
11089 or_result = gen_reg_rtx (CCFPmode);
11090 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11092 compare_result = or_result;
11097 if (code == NE || code == LTGT)
11107 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11108 CLOBBERs to match cmptf_internal2 pattern. */
11109 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11110 && GET_MODE (rs6000_compare_op0) == TFmode
11111 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11112 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11113 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11115 gen_rtx_SET (VOIDmode,
11117 gen_rtx_COMPARE (comp_mode,
11118 rs6000_compare_op0,
11119 rs6000_compare_op1)),
11120 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11121 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11122 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11123 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11124 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11125 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11126 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11127 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11128 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11129 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11131 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11132 comp_mode = CCEQmode;
11133 compare_result = gen_reg_rtx (CCEQmode);
11135 emit_insn (gen_stack_protect_testdi (compare_result,
11136 rs6000_compare_op0, op1));
11138 emit_insn (gen_stack_protect_testsi (compare_result,
11139 rs6000_compare_op0, op1));
11142 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11143 gen_rtx_COMPARE (comp_mode,
11144 rs6000_compare_op0,
11145 rs6000_compare_op1)));
11148 /* Some kinds of FP comparisons need an OR operation;
11149 under flag_finite_math_only we don't bother. */
11150 if (rs6000_compare_fp_p
11151 && !flag_finite_math_only
11152 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11153 && (code == LE || code == GE
11154 || code == UNEQ || code == LTGT
11155 || code == UNGT || code == UNLT))
11157 enum rtx_code or1, or2;
11158 rtx or1_rtx, or2_rtx, compare2_rtx;
11159 rtx or_result = gen_reg_rtx (CCEQmode);
11163 case LE: or1 = LT; or2 = EQ; break;
11164 case GE: or1 = GT; or2 = EQ; break;
11165 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11166 case LTGT: or1 = LT; or2 = GT; break;
11167 case UNGT: or1 = UNORDERED; or2 = GT; break;
11168 case UNLT: or1 = UNORDERED; or2 = LT; break;
11169 default: gcc_unreachable ();
11171 validate_condition_mode (or1, comp_mode);
11172 validate_condition_mode (or2, comp_mode);
11173 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11174 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11175 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11176 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11178 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11180 compare_result = or_result;
11184 validate_condition_mode (code, GET_MODE (compare_result));
11186 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11190 /* Emit the RTL for an sCOND pattern. */
11193 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11196 enum machine_mode op_mode;
11197 enum rtx_code cond_code;
11199 condition_rtx = rs6000_generate_compare (code);
11200 cond_code = GET_CODE (condition_rtx);
11202 if (TARGET_E500 && rs6000_compare_fp_p
11203 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11207 PUT_MODE (condition_rtx, SImode);
11208 t = XEXP (condition_rtx, 0);
11210 gcc_assert (cond_code == NE || cond_code == EQ);
11212 if (cond_code == NE)
11213 emit_insn (gen_e500_flip_gt_bit (t, t));
11215 emit_insn (gen_move_from_CR_gt_bit (result, t));
11219 if (cond_code == NE
11220 || cond_code == GE || cond_code == LE
11221 || cond_code == GEU || cond_code == LEU
11222 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11224 rtx not_result = gen_reg_rtx (CCEQmode);
11225 rtx not_op, rev_cond_rtx;
11226 enum machine_mode cc_mode;
11228 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11230 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11231 SImode, XEXP (condition_rtx, 0), const0_rtx);
11232 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11233 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11234 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11237 op_mode = GET_MODE (rs6000_compare_op0);
11238 if (op_mode == VOIDmode)
11239 op_mode = GET_MODE (rs6000_compare_op1);
11241 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11243 PUT_MODE (condition_rtx, DImode);
11244 convert_move (result, condition_rtx, 0);
11248 PUT_MODE (condition_rtx, SImode);
11249 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11253 /* Emit a branch of kind CODE to location LOC. */
11256 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11258 rtx condition_rtx, loc_ref;
11260 condition_rtx = rs6000_generate_compare (code);
11261 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11262 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11263 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11264 loc_ref, pc_rtx)));
11267 /* Return the string to output a conditional branch to LABEL, which is
11268 the operand number of the label, or -1 if the branch is really a
11269 conditional return.
11271 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11272 condition code register and its mode specifies what kind of
11273 comparison we made.
11275 REVERSED is nonzero if we should reverse the sense of the comparison.
11277 INSN is the insn. */
11280 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11282 static char string[64];
11283 enum rtx_code code = GET_CODE (op);
11284 rtx cc_reg = XEXP (op, 0);
11285 enum machine_mode mode = GET_MODE (cc_reg);
11286 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11287 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11288 int really_reversed = reversed ^ need_longbranch;
11294 validate_condition_mode (code, mode);
11296 /* Work out which way this really branches. We could use
11297 reverse_condition_maybe_unordered here always but this
11298 makes the resulting assembler clearer. */
11299 if (really_reversed)
11301 /* Reversal of FP compares takes care -- an ordered compare
11302 becomes an unordered compare and vice versa. */
11303 if (mode == CCFPmode)
11304 code = reverse_condition_maybe_unordered (code);
11306 code = reverse_condition (code);
11309 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11311 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11316 /* Opposite of GT. */
11325 gcc_unreachable ();
11331 /* Not all of these are actually distinct opcodes, but
11332 we distinguish them for clarity of the resulting assembler. */
11333 case NE: case LTGT:
11334 ccode = "ne"; break;
11335 case EQ: case UNEQ:
11336 ccode = "eq"; break;
11338 ccode = "ge"; break;
11339 case GT: case GTU: case UNGT:
11340 ccode = "gt"; break;
11342 ccode = "le"; break;
11343 case LT: case LTU: case UNLT:
11344 ccode = "lt"; break;
11345 case UNORDERED: ccode = "un"; break;
11346 case ORDERED: ccode = "nu"; break;
11347 case UNGE: ccode = "nl"; break;
11348 case UNLE: ccode = "ng"; break;
11350 gcc_unreachable ();
11353 /* Maybe we have a guess as to how likely the branch is.
11354 The old mnemonics don't have a way to specify this information. */
11356 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11357 if (note != NULL_RTX)
11359 /* PROB is the difference from 50%. */
11360 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11362 /* Only hint for highly probable/improbable branches on newer
11363 cpus as static prediction overrides processor dynamic
11364 prediction. For older cpus we may as well always hint, but
11365 assume not taken for branches that are very close to 50% as a
11366 mispredicted taken branch is more expensive than a
11367 mispredicted not-taken branch. */
11368 if (rs6000_always_hint
11369 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11371 if (abs (prob) > REG_BR_PROB_BASE / 20
11372 && ((prob > 0) ^ need_longbranch))
11380 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11382 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11384 /* We need to escape any '%' characters in the reg_names string.
11385 Assume they'd only be the first character.... */
11386 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11388 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11392 /* If the branch distance was too far, we may have to use an
11393 unconditional branch to go the distance. */
11394 if (need_longbranch)
11395 s += sprintf (s, ",$+8\n\tb %s", label);
11397 s += sprintf (s, ",%s", label);
11403 /* Return the string to flip the GT bit on a CR. */
11405 output_e500_flip_gt_bit (rtx dst, rtx src)
11407 static char string[64];
11410 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11411 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11414 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11415 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11417 sprintf (string, "crnot %d,%d", a, b);
11421 /* Return insn index for the vector compare instruction for given CODE,
11422 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11426 get_vec_cmp_insn (enum rtx_code code,
11427 enum machine_mode dest_mode,
11428 enum machine_mode op_mode)
11430 if (!TARGET_ALTIVEC)
11431 return INSN_NOT_AVAILABLE;
11436 if (dest_mode == V16QImode && op_mode == V16QImode)
11437 return UNSPEC_VCMPEQUB;
11438 if (dest_mode == V8HImode && op_mode == V8HImode)
11439 return UNSPEC_VCMPEQUH;
11440 if (dest_mode == V4SImode && op_mode == V4SImode)
11441 return UNSPEC_VCMPEQUW;
11442 if (dest_mode == V4SImode && op_mode == V4SFmode)
11443 return UNSPEC_VCMPEQFP;
11446 if (dest_mode == V4SImode && op_mode == V4SFmode)
11447 return UNSPEC_VCMPGEFP;
11449 if (dest_mode == V16QImode && op_mode == V16QImode)
11450 return UNSPEC_VCMPGTSB;
11451 if (dest_mode == V8HImode && op_mode == V8HImode)
11452 return UNSPEC_VCMPGTSH;
11453 if (dest_mode == V4SImode && op_mode == V4SImode)
11454 return UNSPEC_VCMPGTSW;
11455 if (dest_mode == V4SImode && op_mode == V4SFmode)
11456 return UNSPEC_VCMPGTFP;
11459 if (dest_mode == V16QImode && op_mode == V16QImode)
11460 return UNSPEC_VCMPGTUB;
11461 if (dest_mode == V8HImode && op_mode == V8HImode)
11462 return UNSPEC_VCMPGTUH;
11463 if (dest_mode == V4SImode && op_mode == V4SImode)
11464 return UNSPEC_VCMPGTUW;
11469 return INSN_NOT_AVAILABLE;
11472 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11473 DMODE is expected destination mode. This is a recursive function. */
11476 rs6000_emit_vector_compare (enum rtx_code rcode,
11478 enum machine_mode dmode)
11482 enum machine_mode dest_mode;
11483 enum machine_mode op_mode = GET_MODE (op1);
11485 gcc_assert (TARGET_ALTIVEC);
11486 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11488 /* Floating point vector compare instructions uses destination V4SImode.
11489 Move destination to appropriate mode later. */
11490 if (dmode == V4SFmode)
11491 dest_mode = V4SImode;
11495 mask = gen_reg_rtx (dest_mode);
11496 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11498 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11500 bool swap_operands = false;
11501 bool try_again = false;
11506 swap_operands = true;
11511 swap_operands = true;
11515 /* Treat A != B as ~(A==B). */
11517 enum insn_code nor_code;
11518 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11521 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11522 gcc_assert (nor_code != CODE_FOR_nothing);
11523 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11525 if (dmode != dest_mode)
11527 rtx temp = gen_reg_rtx (dest_mode);
11528 convert_move (temp, mask, 0);
11538 /* Try GT/GTU/LT/LTU OR EQ */
11541 enum insn_code ior_code;
11542 enum rtx_code new_code;
11563 gcc_unreachable ();
11566 c_rtx = rs6000_emit_vector_compare (new_code,
11567 op0, op1, dest_mode);
11568 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11571 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11572 gcc_assert (ior_code != CODE_FOR_nothing);
11573 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11574 if (dmode != dest_mode)
11576 rtx temp = gen_reg_rtx (dest_mode);
11577 convert_move (temp, mask, 0);
11584 gcc_unreachable ();
11589 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11590 /* You only get two chances. */
11591 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11603 emit_insn (gen_rtx_SET (VOIDmode, mask,
11604 gen_rtx_UNSPEC (dest_mode,
11605 gen_rtvec (2, op0, op1),
11607 if (dmode != dest_mode)
11609 rtx temp = gen_reg_rtx (dest_mode);
11610 convert_move (temp, mask, 0);
11616 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11617 valid insn doesn exist for given mode. */
11620 get_vsel_insn (enum machine_mode mode)
11625 return UNSPEC_VSEL4SI;
11628 return UNSPEC_VSEL4SF;
11631 return UNSPEC_VSEL8HI;
11634 return UNSPEC_VSEL16QI;
11637 return INSN_NOT_AVAILABLE;
11640 return INSN_NOT_AVAILABLE;
11643 /* Emit vector select insn where DEST is destination using
11644 operands OP1, OP2 and MASK. */
11647 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11650 enum machine_mode dest_mode = GET_MODE (dest);
11651 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11653 temp = gen_reg_rtx (dest_mode);
11655 /* For each vector element, select op1 when mask is 1 otherwise
11657 t = gen_rtx_SET (VOIDmode, temp,
11658 gen_rtx_UNSPEC (dest_mode,
11659 gen_rtvec (3, op2, op1, mask),
11662 emit_move_insn (dest, temp);
11666 /* Emit vector conditional expression.
11667 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11668 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11671 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11672 rtx cond, rtx cc_op0, rtx cc_op1)
11674 enum machine_mode dest_mode = GET_MODE (dest);
11675 enum rtx_code rcode = GET_CODE (cond);
11678 if (!TARGET_ALTIVEC)
11681 /* Get the vector mask for the given relational operations. */
11682 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11684 rs6000_emit_vector_select (dest, op1, op2, mask);
11689 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11690 operands of the last comparison is nonzero/true, FALSE_COND if it
11691 is zero/false. Return 0 if the hardware has no such operation. */
11694 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11696 enum rtx_code code = GET_CODE (op);
11697 rtx op0 = rs6000_compare_op0;
11698 rtx op1 = rs6000_compare_op1;
11699 REAL_VALUE_TYPE c1;
11700 enum machine_mode compare_mode = GET_MODE (op0);
11701 enum machine_mode result_mode = GET_MODE (dest);
11703 bool is_against_zero;
11705 /* These modes should always match. */
11706 if (GET_MODE (op1) != compare_mode
11707 /* In the isel case however, we can use a compare immediate, so
11708 op1 may be a small constant. */
11709 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11711 if (GET_MODE (true_cond) != result_mode)
11713 if (GET_MODE (false_cond) != result_mode)
11716 /* First, work out if the hardware can do this at all, or
11717 if it's too slow.... */
11718 if (! rs6000_compare_fp_p)
11721 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11724 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11725 && SCALAR_FLOAT_MODE_P (compare_mode))
11728 is_against_zero = op1 == CONST0_RTX (compare_mode);
11730 /* A floating-point subtract might overflow, underflow, or produce
11731 an inexact result, thus changing the floating-point flags, so it
11732 can't be generated if we care about that. It's safe if one side
11733 of the construct is zero, since then no subtract will be
11735 if (SCALAR_FLOAT_MODE_P (compare_mode)
11736 && flag_trapping_math && ! is_against_zero)
11739 /* Eliminate half of the comparisons by switching operands, this
11740 makes the remaining code simpler. */
11741 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11742 || code == LTGT || code == LT || code == UNLE)
11744 code = reverse_condition_maybe_unordered (code);
11746 true_cond = false_cond;
11750 /* UNEQ and LTGT take four instructions for a comparison with zero,
11751 it'll probably be faster to use a branch here too. */
11752 if (code == UNEQ && HONOR_NANS (compare_mode))
11755 if (GET_CODE (op1) == CONST_DOUBLE)
11756 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11758 /* We're going to try to implement comparisons by performing
11759 a subtract, then comparing against zero. Unfortunately,
11760 Inf - Inf is NaN which is not zero, and so if we don't
11761 know that the operand is finite and the comparison
11762 would treat EQ different to UNORDERED, we can't do it. */
11763 if (HONOR_INFINITIES (compare_mode)
11764 && code != GT && code != UNGE
11765 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11766 /* Constructs of the form (a OP b ? a : b) are safe. */
11767 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11768 || (! rtx_equal_p (op0, true_cond)
11769 && ! rtx_equal_p (op1, true_cond))))
11772 /* At this point we know we can use fsel. */
11774 /* Reduce the comparison to a comparison against zero. */
11775 if (! is_against_zero)
11777 temp = gen_reg_rtx (compare_mode);
11778 emit_insn (gen_rtx_SET (VOIDmode, temp,
11779 gen_rtx_MINUS (compare_mode, op0, op1)));
11781 op1 = CONST0_RTX (compare_mode);
11784 /* If we don't care about NaNs we can reduce some of the comparisons
11785 down to faster ones. */
11786 if (! HONOR_NANS (compare_mode))
11792 true_cond = false_cond;
11805 /* Now, reduce everything down to a GE. */
11812 temp = gen_reg_rtx (compare_mode);
11813 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11818 temp = gen_reg_rtx (compare_mode);
11819 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11824 temp = gen_reg_rtx (compare_mode);
11825 emit_insn (gen_rtx_SET (VOIDmode, temp,
11826 gen_rtx_NEG (compare_mode,
11827 gen_rtx_ABS (compare_mode, op0))));
11832 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11833 temp = gen_reg_rtx (result_mode);
11834 emit_insn (gen_rtx_SET (VOIDmode, temp,
11835 gen_rtx_IF_THEN_ELSE (result_mode,
11836 gen_rtx_GE (VOIDmode,
11838 true_cond, false_cond)));
11839 false_cond = true_cond;
11842 temp = gen_reg_rtx (compare_mode);
11843 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11848 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11849 temp = gen_reg_rtx (result_mode);
11850 emit_insn (gen_rtx_SET (VOIDmode, temp,
11851 gen_rtx_IF_THEN_ELSE (result_mode,
11852 gen_rtx_GE (VOIDmode,
11854 true_cond, false_cond)));
11855 true_cond = false_cond;
11858 temp = gen_reg_rtx (compare_mode);
11859 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11864 gcc_unreachable ();
11867 emit_insn (gen_rtx_SET (VOIDmode, dest,
11868 gen_rtx_IF_THEN_ELSE (result_mode,
11869 gen_rtx_GE (VOIDmode,
11871 true_cond, false_cond)));
11875 /* Same as above, but for ints (isel). */
11878 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11880 rtx condition_rtx, cr;
11882 /* All isel implementations thus far are 32-bits. */
11883 if (GET_MODE (rs6000_compare_op0) != SImode)
11886 /* We still have to do the compare, because isel doesn't do a
11887 compare, it just looks at the CRx bits set by a previous compare
11889 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11890 cr = XEXP (condition_rtx, 0);
11892 if (GET_MODE (cr) == CCmode)
11893 emit_insn (gen_isel_signed (dest, condition_rtx,
11894 true_cond, false_cond, cr));
11896 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11897 true_cond, false_cond, cr));
11903 output_isel (rtx *operands)
11905 enum rtx_code code;
11907 code = GET_CODE (operands[1]);
11908 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11910 PUT_CODE (operands[1], reverse_condition (code));
11911 return "isel %0,%3,%2,%j1";
11914 return "isel %0,%2,%3,%j1";
11918 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11920 enum machine_mode mode = GET_MODE (op0);
11924 if (code == SMAX || code == SMIN)
11929 if (code == SMAX || code == UMAX)
11930 target = emit_conditional_move (dest, c, op0, op1, mode,
11931 op0, op1, mode, 0);
11933 target = emit_conditional_move (dest, c, op0, op1, mode,
11934 op1, op0, mode, 0);
11935 gcc_assert (target);
11936 if (target != dest)
11937 emit_move_insn (dest, target);
11940 /* Emit instructions to perform a load-reserved/store-conditional operation.
11941 The operation performed is an atomic
11942 (set M (CODE:MODE M OP))
11943 If not NULL, BEFORE is atomically set to M before the operation, and
11944 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11945 If SYNC_P then a memory barrier is emitted before the operation.
11946 Either OP or M may be wrapped in a NOT operation. */
11949 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11950 rtx m, rtx op, rtx before_param, rtx after_param,
11953 enum machine_mode used_mode;
11954 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11957 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11958 rtx shift = NULL_RTX;
11961 emit_insn (gen_memory_barrier ());
11963 if (GET_CODE (m) == NOT)
11964 used_m = XEXP (m, 0);
11968 /* If this is smaller than SImode, we'll have to use SImode with
11970 if (mode == QImode || mode == HImode)
11974 if (MEM_ALIGN (used_m) >= 32)
11977 if (BYTES_BIG_ENDIAN)
11978 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11980 shift = GEN_INT (ishift);
11984 rtx addrSI, aligned_addr;
11985 int shift_mask = mode == QImode ? 0x18 : 0x10;
11987 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11988 XEXP (used_m, 0)));
11989 shift = gen_reg_rtx (SImode);
11991 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11992 GEN_INT (shift_mask)));
11993 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
11995 aligned_addr = expand_binop (Pmode, and_optab,
11997 GEN_INT (-4), NULL_RTX,
11998 1, OPTAB_LIB_WIDEN);
11999 used_m = change_address (used_m, SImode, aligned_addr);
12000 set_mem_align (used_m, 32);
12001 /* It's safe to keep the old alias set of USED_M, because
12002 the operation is atomic and only affects the original
12004 if (GET_CODE (m) == NOT)
12005 m = gen_rtx_NOT (SImode, used_m);
12010 if (GET_CODE (op) == NOT)
12012 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12013 oldop = gen_rtx_NOT (SImode, oldop);
12016 oldop = lowpart_subreg (SImode, op, mode);
12022 newop = expand_binop (SImode, and_optab,
12023 oldop, GEN_INT (imask), NULL_RTX,
12024 1, OPTAB_LIB_WIDEN);
12025 emit_insn (gen_ashlsi3 (newop, newop, shift));
12029 newop = expand_binop (SImode, ior_optab,
12030 oldop, GEN_INT (~imask), NULL_RTX,
12031 1, OPTAB_LIB_WIDEN);
12032 emit_insn (gen_rotlsi3 (newop, newop, shift));
12040 newop = expand_binop (SImode, and_optab,
12041 oldop, GEN_INT (imask), NULL_RTX,
12042 1, OPTAB_LIB_WIDEN);
12043 emit_insn (gen_ashlsi3 (newop, newop, shift));
12045 mask = gen_reg_rtx (SImode);
12046 emit_move_insn (mask, GEN_INT (imask));
12047 emit_insn (gen_ashlsi3 (mask, mask, shift));
12050 newop = gen_rtx_PLUS (SImode, m, newop);
12052 newop = gen_rtx_MINUS (SImode, m, newop);
12053 newop = gen_rtx_AND (SImode, newop, mask);
12054 newop = gen_rtx_IOR (SImode, newop,
12055 gen_rtx_AND (SImode,
12056 gen_rtx_NOT (SImode, mask),
12062 gcc_unreachable ();
12065 if (GET_CODE (m) == NOT)
12069 mask = gen_reg_rtx (SImode);
12070 emit_move_insn (mask, GEN_INT (imask));
12071 emit_insn (gen_ashlsi3 (mask, mask, shift));
12073 xorm = gen_rtx_XOR (SImode, used_m, mask);
12074 /* Depending on the value of 'op', the XOR or the operation might
12075 be able to be simplified away. */
12076 newop = simplify_gen_binary (code, SImode, xorm, newop);
12079 used_mode = SImode;
12080 before = gen_reg_rtx (used_mode);
12081 after = gen_reg_rtx (used_mode);
12086 before = before_param;
12087 after = after_param;
12089 if (before == NULL_RTX)
12090 before = gen_reg_rtx (used_mode);
12091 if (after == NULL_RTX)
12092 after = gen_reg_rtx (used_mode);
12095 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12096 && used_mode != mode)
12097 the_op = op; /* Computed above. */
12098 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12099 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12101 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12103 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12104 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12105 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12106 gen_rtx_UNSPEC (used_mode,
12107 gen_rtvec (1, the_op),
12109 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12111 if ((code == PLUS || code == MINUS) && used_mode != mode)
12112 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12113 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12115 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12116 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12118 /* Shift and mask the return values properly. */
12119 if (used_mode != mode && before_param)
12121 emit_insn (gen_lshrsi3 (before, before, shift));
12122 convert_move (before_param, before, 1);
12125 if (used_mode != mode && after_param)
12127 emit_insn (gen_lshrsi3 (after, after, shift));
12128 convert_move (after_param, after, 1);
12131 /* The previous sequence will end with a branch that's dependent on
12132 the conditional store, so placing an isync will ensure that no
12133 other instructions (especially, no load or store instructions)
12134 can start before the atomic operation completes. */
12136 emit_insn (gen_isync ());
12139 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12140 COND is true. Mark the jump as unlikely to be taken. */
12143 emit_unlikely_jump (rtx cond, rtx label)
12145 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12148 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12149 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12150 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12153 /* A subroutine of the atomic operation splitters. Emit a load-locked
12154 instruction in MODE. */
12157 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12159 rtx (*fn) (rtx, rtx) = NULL;
12160 if (mode == SImode)
12161 fn = gen_load_locked_si;
12162 else if (mode == DImode)
12163 fn = gen_load_locked_di;
12164 emit_insn (fn (reg, mem));
12167 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12168 instruction in MODE. */
12171 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12173 rtx (*fn) (rtx, rtx, rtx) = NULL;
12174 if (mode == SImode)
12175 fn = gen_store_conditional_si;
12176 else if (mode == DImode)
12177 fn = gen_store_conditional_di;
12179 /* Emit sync before stwcx. to address PPC405 Erratum. */
12180 if (PPC405_ERRATUM77)
12181 emit_insn (gen_memory_barrier ());
12183 emit_insn (fn (res, mem, val));
12186 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12187 to perform. MEM is the memory on which to operate. VAL is the second
12188 operand of the binary operator. BEFORE and AFTER are optional locations to
12189 return the value of MEM either before of after the operation. SCRATCH is
12190 a scratch register. */
12193 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12194 rtx before, rtx after, rtx scratch)
12196 enum machine_mode mode = GET_MODE (mem);
12197 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12199 emit_insn (gen_memory_barrier ());
12201 label = gen_label_rtx ();
12202 emit_label (label);
12203 label = gen_rtx_LABEL_REF (VOIDmode, label);
12205 if (before == NULL_RTX)
12207 emit_load_locked (mode, before, mem);
12210 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12211 else if (code == AND)
12212 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12214 x = gen_rtx_fmt_ee (code, mode, before, val);
12216 if (after != NULL_RTX)
12217 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12218 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12220 emit_store_conditional (mode, cond, mem, scratch);
12222 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12223 emit_unlikely_jump (x, label);
12225 emit_insn (gen_isync ());
12228 /* Expand an atomic compare and swap operation. MEM is the memory on which
12229 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12230 value to be stored. SCRATCH is a scratch GPR. */
12233 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12236 enum machine_mode mode = GET_MODE (mem);
12237 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12239 emit_insn (gen_memory_barrier ());
12241 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12242 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12243 emit_label (XEXP (label1, 0));
12245 emit_load_locked (mode, retval, mem);
12247 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12248 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12250 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12251 emit_unlikely_jump (x, label2);
12253 emit_move_insn (scratch, newval);
12254 emit_store_conditional (mode, cond, mem, scratch);
12256 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12257 emit_unlikely_jump (x, label1);
12259 emit_insn (gen_isync ());
12260 emit_label (XEXP (label2, 0));
12263 /* Expand an atomic test and set operation. MEM is the memory on which
12264 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12267 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12269 enum machine_mode mode = GET_MODE (mem);
12270 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12272 emit_insn (gen_memory_barrier ());
12274 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12275 emit_label (XEXP (label, 0));
12277 emit_load_locked (mode, retval, mem);
12278 emit_move_insn (scratch, val);
12279 emit_store_conditional (mode, cond, mem, scratch);
12281 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12282 emit_unlikely_jump (x, label);
12284 emit_insn (gen_isync ());
12288 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12290 enum machine_mode mode = GET_MODE (mem);
12291 rtx addrSI, align, wdst, shift, mask;
12292 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12293 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12295 /* Shift amount for subword relative to aligned word. */
12296 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12297 shift = gen_reg_rtx (SImode);
12298 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12299 GEN_INT (shift_mask)));
12300 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12302 /* Shift and mask old value into position within word. */
12303 oldval = convert_modes (SImode, mode, oldval, 1);
12304 oldval = expand_binop (SImode, and_optab,
12305 oldval, GEN_INT (imask), NULL_RTX,
12306 1, OPTAB_LIB_WIDEN);
12307 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12309 /* Shift and mask new value into position within word. */
12310 newval = convert_modes (SImode, mode, newval, 1);
12311 newval = expand_binop (SImode, and_optab,
12312 newval, GEN_INT (imask), NULL_RTX,
12313 1, OPTAB_LIB_WIDEN);
12314 emit_insn (gen_ashlsi3 (newval, newval, shift));
12316 /* Mask for insertion. */
12317 mask = gen_reg_rtx (SImode);
12318 emit_move_insn (mask, GEN_INT (imask));
12319 emit_insn (gen_ashlsi3 (mask, mask, shift));
12321 /* Address of aligned word containing subword. */
12322 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12323 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12324 mem = change_address (mem, SImode, align);
12325 set_mem_align (mem, 32);
12326 MEM_VOLATILE_P (mem) = 1;
12328 wdst = gen_reg_rtx (SImode);
12329 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12330 oldval, newval, mem));
12332 emit_move_insn (dst, gen_lowpart (mode, wdst));
12336 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12337 rtx oldval, rtx newval, rtx mem,
12340 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12342 emit_insn (gen_memory_barrier ());
12343 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12344 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12345 emit_label (XEXP (label1, 0));
12347 emit_load_locked (SImode, scratch, mem);
12349 /* Mask subword within loaded value for comparison with oldval.
12350 Use UNSPEC_AND to avoid clobber.*/
12351 emit_insn (gen_rtx_SET (SImode, dest,
12352 gen_rtx_UNSPEC (SImode,
12353 gen_rtvec (2, scratch, mask),
12356 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12357 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12359 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12360 emit_unlikely_jump (x, label2);
12362 /* Clear subword within loaded value for insertion of new value. */
12363 emit_insn (gen_rtx_SET (SImode, scratch,
12364 gen_rtx_AND (SImode,
12365 gen_rtx_NOT (SImode, mask), scratch)));
12366 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12367 emit_store_conditional (SImode, cond, mem, scratch);
12369 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12370 emit_unlikely_jump (x, label1);
12372 emit_insn (gen_isync ());
12373 emit_label (XEXP (label2, 0));
12377 /* Emit instructions to move SRC to DST. Called by splitters for
12378 multi-register moves. It will emit at most one instruction for
12379 each register that is accessed; that is, it won't emit li/lis pairs
12380 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12384 rs6000_split_multireg_move (rtx dst, rtx src)
12386 /* The register number of the first register being moved. */
12388 /* The mode that is to be moved. */
12389 enum machine_mode mode;
12390 /* The mode that the move is being done in, and its size. */
12391 enum machine_mode reg_mode;
12393 /* The number of registers that will be moved. */
12396 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12397 mode = GET_MODE (dst);
12398 nregs = hard_regno_nregs[reg][mode];
12399 if (FP_REGNO_P (reg))
12401 else if (ALTIVEC_REGNO_P (reg))
12402 reg_mode = V16QImode;
12404 reg_mode = word_mode;
12405 reg_mode_size = GET_MODE_SIZE (reg_mode);
12407 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12409 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12411 /* Move register range backwards, if we might have destructive
12414 for (i = nregs - 1; i >= 0; i--)
12415 emit_insn (gen_rtx_SET (VOIDmode,
12416 simplify_gen_subreg (reg_mode, dst, mode,
12417 i * reg_mode_size),
12418 simplify_gen_subreg (reg_mode, src, mode,
12419 i * reg_mode_size)));
12425 bool used_update = false;
12427 if (MEM_P (src) && INT_REGNO_P (reg))
12431 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12432 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12435 breg = XEXP (XEXP (src, 0), 0);
12436 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12437 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12438 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12439 emit_insn (TARGET_32BIT
12440 ? gen_addsi3 (breg, breg, delta_rtx)
12441 : gen_adddi3 (breg, breg, delta_rtx));
12442 src = replace_equiv_address (src, breg);
12444 else if (! offsettable_memref_p (src))
12447 basereg = gen_rtx_REG (Pmode, reg);
12448 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12449 src = replace_equiv_address (src, basereg);
12452 breg = XEXP (src, 0);
12453 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12454 breg = XEXP (breg, 0);
12456 /* If the base register we are using to address memory is
12457 also a destination reg, then change that register last. */
12459 && REGNO (breg) >= REGNO (dst)
12460 && REGNO (breg) < REGNO (dst) + nregs)
12461 j = REGNO (breg) - REGNO (dst);
12464 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12468 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12469 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12472 breg = XEXP (XEXP (dst, 0), 0);
12473 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12474 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12475 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12477 /* We have to update the breg before doing the store.
12478 Use store with update, if available. */
12482 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12483 emit_insn (TARGET_32BIT
12484 ? (TARGET_POWERPC64
12485 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12486 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12487 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12488 used_update = true;
12491 emit_insn (TARGET_32BIT
12492 ? gen_addsi3 (breg, breg, delta_rtx)
12493 : gen_adddi3 (breg, breg, delta_rtx));
12494 dst = replace_equiv_address (dst, breg);
12497 gcc_assert (offsettable_memref_p (dst));
12500 for (i = 0; i < nregs; i++)
12502 /* Calculate index to next subword. */
12507 /* If compiler already emitted move of first word by
12508 store with update, no need to do anything. */
12509 if (j == 0 && used_update)
12512 emit_insn (gen_rtx_SET (VOIDmode,
12513 simplify_gen_subreg (reg_mode, dst, mode,
12514 j * reg_mode_size),
12515 simplify_gen_subreg (reg_mode, src, mode,
12516 j * reg_mode_size)));
12522 /* This page contains routines that are used to determine what the
12523 function prologue and epilogue code will do and write them out. */
12525 /* Return the first fixed-point register that is required to be
12526 saved. 32 if none. */
12529 first_reg_to_save (void)
12533 /* Find lowest numbered live register. */
12534 for (first_reg = 13; first_reg <= 31; first_reg++)
12535 if (regs_ever_live[first_reg]
12536 && (! call_used_regs[first_reg]
12537 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12538 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12539 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12540 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12545 && current_function_uses_pic_offset_table
12546 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12547 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12553 /* Similar, for FP regs. */
12556 first_fp_reg_to_save (void)
12560 /* Find lowest numbered live register. */
12561 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12562 if (regs_ever_live[first_reg])
12568 /* Similar, for AltiVec regs. */
12571 first_altivec_reg_to_save (void)
12575 /* Stack frame remains as is unless we are in AltiVec ABI. */
12576 if (! TARGET_ALTIVEC_ABI)
12577 return LAST_ALTIVEC_REGNO + 1;
12579 /* Find lowest numbered live register. */
12580 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12581 if (regs_ever_live[i])
12587 /* Return a 32-bit mask of the AltiVec registers we need to set in
12588 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12589 the 32-bit word is 0. */
12591 static unsigned int
12592 compute_vrsave_mask (void)
12594 unsigned int i, mask = 0;
12596 /* First, find out if we use _any_ altivec registers. */
12597 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12598 if (regs_ever_live[i])
12599 mask |= ALTIVEC_REG_BIT (i);
12604 /* Next, remove the argument registers from the set. These must
12605 be in the VRSAVE mask set by the caller, so we don't need to add
12606 them in again. More importantly, the mask we compute here is
12607 used to generate CLOBBERs in the set_vrsave insn, and we do not
12608 wish the argument registers to die. */
12609 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12610 mask &= ~ALTIVEC_REG_BIT (i);
12612 /* Similarly, remove the return value from the set. */
12615 diddle_return_value (is_altivec_return_reg, &yes);
12617 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12623 /* For a very restricted set of circumstances, we can cut down the
12624 size of prologues/epilogues by calling our own save/restore-the-world
12628 compute_save_world_info (rs6000_stack_t *info_ptr)
12630 info_ptr->world_save_p = 1;
12631 info_ptr->world_save_p
12632 = (WORLD_SAVE_P (info_ptr)
12633 && DEFAULT_ABI == ABI_DARWIN
12634 && ! (current_function_calls_setjmp && flag_exceptions)
12635 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12636 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12637 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12638 && info_ptr->cr_save_p);
12640 /* This will not work in conjunction with sibcalls. Make sure there
12641 are none. (This check is expensive, but seldom executed.) */
12642 if (WORLD_SAVE_P (info_ptr))
12645 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12646 if ( GET_CODE (insn) == CALL_INSN
12647 && SIBLING_CALL_P (insn))
12649 info_ptr->world_save_p = 0;
12654 if (WORLD_SAVE_P (info_ptr))
12656 /* Even if we're not touching VRsave, make sure there's room on the
12657 stack for it, if it looks like we're calling SAVE_WORLD, which
12658 will attempt to save it. */
12659 info_ptr->vrsave_size = 4;
12661 /* "Save" the VRsave register too if we're saving the world. */
12662 if (info_ptr->vrsave_mask == 0)
12663 info_ptr->vrsave_mask = compute_vrsave_mask ();
12665 /* Because the Darwin register save/restore routines only handle
12666 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12668 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12669 && (info_ptr->first_altivec_reg_save
12670 >= FIRST_SAVED_ALTIVEC_REGNO));
12677 is_altivec_return_reg (rtx reg, void *xyes)
12679 bool *yes = (bool *) xyes;
12680 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12685 /* Calculate the stack information for the current function. This is
12686 complicated by having two separate calling sequences, the AIX calling
12687 sequence and the V.4 calling sequence.
12689 AIX (and Darwin/Mac OS X) stack frames look like:
12691 SP----> +---------------------------------------+
12692 | back chain to caller | 0 0
12693 +---------------------------------------+
12694 | saved CR | 4 8 (8-11)
12695 +---------------------------------------+
12697 +---------------------------------------+
12698 | reserved for compilers | 12 24
12699 +---------------------------------------+
12700 | reserved for binders | 16 32
12701 +---------------------------------------+
12702 | saved TOC pointer | 20 40
12703 +---------------------------------------+
12704 | Parameter save area (P) | 24 48
12705 +---------------------------------------+
12706 | Alloca space (A) | 24+P etc.
12707 +---------------------------------------+
12708 | Local variable space (L) | 24+P+A
12709 +---------------------------------------+
12710 | Float/int conversion temporary (X) | 24+P+A+L
12711 +---------------------------------------+
12712 | Save area for AltiVec registers (W) | 24+P+A+L+X
12713 +---------------------------------------+
12714 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12715 +---------------------------------------+
12716 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12717 +---------------------------------------+
12718 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12719 +---------------------------------------+
12720 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12721 +---------------------------------------+
12722 old SP->| back chain to caller's caller |
12723 +---------------------------------------+
12725 The required alignment for AIX configurations is two words (i.e., 8
12729 V.4 stack frames look like:
12731 SP----> +---------------------------------------+
12732 | back chain to caller | 0
12733 +---------------------------------------+
12734 | caller's saved LR | 4
12735 +---------------------------------------+
12736 | Parameter save area (P) | 8
12737 +---------------------------------------+
12738 | Alloca space (A) | 8+P
12739 +---------------------------------------+
12740 | Varargs save area (V) | 8+P+A
12741 +---------------------------------------+
12742 | Local variable space (L) | 8+P+A+V
12743 +---------------------------------------+
12744 | Float/int conversion temporary (X) | 8+P+A+V+L
12745 +---------------------------------------+
12746 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12747 +---------------------------------------+
12748 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12749 +---------------------------------------+
12750 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12751 +---------------------------------------+
12752 | SPE: area for 64-bit GP registers |
12753 +---------------------------------------+
12754 | SPE alignment padding |
12755 +---------------------------------------+
12756 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12757 +---------------------------------------+
12758 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12759 +---------------------------------------+
12760 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12761 +---------------------------------------+
12762 old SP->| back chain to caller's caller |
12763 +---------------------------------------+
12765 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12766 given. (But note below and in sysv4.h that we require only 8 and
12767 may round up the size of our stack frame anyways. The historical
12768 reason is early versions of powerpc-linux which didn't properly
12769 align the stack at program startup. A happy side-effect is that
12770 -mno-eabi libraries can be used with -meabi programs.)
12772 The EABI configuration defaults to the V.4 layout. However,
12773 the stack alignment requirements may differ. If -mno-eabi is not
12774 given, the required stack alignment is 8 bytes; if -mno-eabi is
12775 given, the required alignment is 16 bytes. (But see V.4 comment
12778 #ifndef ABI_STACK_BOUNDARY
12779 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12782 static rs6000_stack_t *
12783 rs6000_stack_info (void)
12785 static rs6000_stack_t info;
12786 rs6000_stack_t *info_ptr = &info;
12787 int reg_size = TARGET_32BIT ? 4 : 8;
12790 HOST_WIDE_INT non_fixed_size;
12792 memset (&info, 0, sizeof (info));
12796 /* Cache value so we don't rescan instruction chain over and over. */
12797 if (cfun->machine->insn_chain_scanned_p == 0)
12798 cfun->machine->insn_chain_scanned_p
12799 = spe_func_has_64bit_regs_p () + 1;
12800 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12803 /* Select which calling sequence. */
12804 info_ptr->abi = DEFAULT_ABI;
12806 /* Calculate which registers need to be saved & save area size. */
12807 info_ptr->first_gp_reg_save = first_reg_to_save ();
12808 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12809 even if it currently looks like we won't. */
12810 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12811 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12812 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12813 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12814 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12816 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12818 /* For the SPE, we have an additional upper 32-bits on each GPR.
12819 Ideally we should save the entire 64-bits only when the upper
12820 half is used in SIMD instructions. Since we only record
12821 registers live (not the size they are used in), this proves
12822 difficult because we'd have to traverse the instruction chain at
12823 the right time, taking reload into account. This is a real pain,
12824 so we opt to save the GPRs in 64-bits always if but one register
12825 gets used in 64-bits. Otherwise, all the registers in the frame
12826 get saved in 32-bits.
12828 So... since when we save all GPRs (except the SP) in 64-bits, the
12829 traditional GP save area will be empty. */
12830 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12831 info_ptr->gp_size = 0;
12833 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12834 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12836 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12837 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12838 - info_ptr->first_altivec_reg_save);
12840 /* Does this function call anything? */
12841 info_ptr->calls_p = (! current_function_is_leaf
12842 || cfun->machine->ra_needs_full_frame);
12844 /* Determine if we need to save the link register. */
12845 if ((DEFAULT_ABI == ABI_AIX
12846 && current_function_profile
12847 && !TARGET_PROFILE_KERNEL)
12848 #ifdef TARGET_RELOCATABLE
12849 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12851 || (info_ptr->first_fp_reg_save != 64
12852 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12853 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12854 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12855 || info_ptr->calls_p
12856 || rs6000_ra_ever_killed ())
12858 info_ptr->lr_save_p = 1;
12859 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12862 /* Determine if we need to save the condition code registers. */
12863 if (regs_ever_live[CR2_REGNO]
12864 || regs_ever_live[CR3_REGNO]
12865 || regs_ever_live[CR4_REGNO])
12867 info_ptr->cr_save_p = 1;
12868 if (DEFAULT_ABI == ABI_V4)
12869 info_ptr->cr_size = reg_size;
12872 /* If the current function calls __builtin_eh_return, then we need
12873 to allocate stack space for registers that will hold data for
12874 the exception handler. */
12875 if (current_function_calls_eh_return)
12878 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12881 /* SPE saves EH registers in 64-bits. */
12882 ehrd_size = i * (TARGET_SPE_ABI
12883 && info_ptr->spe_64bit_regs_used != 0
12884 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12889 /* Determine various sizes. */
12890 info_ptr->reg_size = reg_size;
12891 info_ptr->fixed_size = RS6000_SAVE_AREA;
12892 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12893 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12894 TARGET_ALTIVEC ? 16 : 8);
12895 if (FRAME_GROWS_DOWNWARD)
12896 info_ptr->vars_size
12897 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12898 + info_ptr->parm_size,
12899 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12900 - (info_ptr->fixed_size + info_ptr->vars_size
12901 + info_ptr->parm_size);
12903 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12904 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12906 info_ptr->spe_gp_size = 0;
12908 if (TARGET_ALTIVEC_ABI)
12909 info_ptr->vrsave_mask = compute_vrsave_mask ();
12911 info_ptr->vrsave_mask = 0;
12913 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12914 info_ptr->vrsave_size = 4;
12916 info_ptr->vrsave_size = 0;
12918 compute_save_world_info (info_ptr);
12920 /* Calculate the offsets. */
12921 switch (DEFAULT_ABI)
12925 gcc_unreachable ();
12929 info_ptr->fp_save_offset = - info_ptr->fp_size;
12930 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12932 if (TARGET_ALTIVEC_ABI)
12934 info_ptr->vrsave_save_offset
12935 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12937 /* Align stack so vector save area is on a quadword boundary. */
12938 if (info_ptr->altivec_size != 0)
12939 info_ptr->altivec_padding_size
12940 = 16 - (-info_ptr->vrsave_save_offset % 16);
12942 info_ptr->altivec_padding_size = 0;
12944 info_ptr->altivec_save_offset
12945 = info_ptr->vrsave_save_offset
12946 - info_ptr->altivec_padding_size
12947 - info_ptr->altivec_size;
12949 /* Adjust for AltiVec case. */
12950 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12953 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12954 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12955 info_ptr->lr_save_offset = 2*reg_size;
12959 info_ptr->fp_save_offset = - info_ptr->fp_size;
12960 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12961 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12963 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12965 /* Align stack so SPE GPR save area is aligned on a
12966 double-word boundary. */
12967 if (info_ptr->spe_gp_size != 0)
12968 info_ptr->spe_padding_size
12969 = 8 - (-info_ptr->cr_save_offset % 8);
12971 info_ptr->spe_padding_size = 0;
12973 info_ptr->spe_gp_save_offset
12974 = info_ptr->cr_save_offset
12975 - info_ptr->spe_padding_size
12976 - info_ptr->spe_gp_size;
12978 /* Adjust for SPE case. */
12979 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
12981 else if (TARGET_ALTIVEC_ABI)
12983 info_ptr->vrsave_save_offset
12984 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12986 /* Align stack so vector save area is on a quadword boundary. */
12987 if (info_ptr->altivec_size != 0)
12988 info_ptr->altivec_padding_size
12989 = 16 - (-info_ptr->vrsave_save_offset % 16);
12991 info_ptr->altivec_padding_size = 0;
12993 info_ptr->altivec_save_offset
12994 = info_ptr->vrsave_save_offset
12995 - info_ptr->altivec_padding_size
12996 - info_ptr->altivec_size;
12998 /* Adjust for AltiVec case. */
12999 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13002 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13003 info_ptr->ehrd_offset -= ehrd_size;
13004 info_ptr->lr_save_offset = reg_size;
13008 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13009 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13010 + info_ptr->gp_size
13011 + info_ptr->altivec_size
13012 + info_ptr->altivec_padding_size
13013 + info_ptr->spe_gp_size
13014 + info_ptr->spe_padding_size
13016 + info_ptr->cr_size
13017 + info_ptr->vrsave_size,
13020 non_fixed_size = (info_ptr->vars_size
13021 + info_ptr->parm_size
13022 + info_ptr->save_size);
13024 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13025 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13027 /* Determine if we need to allocate any stack frame:
13029 For AIX we need to push the stack if a frame pointer is needed
13030 (because the stack might be dynamically adjusted), if we are
13031 debugging, if we make calls, or if the sum of fp_save, gp_save,
13032 and local variables are more than the space needed to save all
13033 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13034 + 18*8 = 288 (GPR13 reserved).
13036 For V.4 we don't have the stack cushion that AIX uses, but assume
13037 that the debugger can handle stackless frames. */
13039 if (info_ptr->calls_p)
13040 info_ptr->push_p = 1;
13042 else if (DEFAULT_ABI == ABI_V4)
13043 info_ptr->push_p = non_fixed_size != 0;
13045 else if (frame_pointer_needed)
13046 info_ptr->push_p = 1;
13048 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13049 info_ptr->push_p = 1;
13052 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13054 /* Zero offsets if we're not saving those registers. */
13055 if (info_ptr->fp_size == 0)
13056 info_ptr->fp_save_offset = 0;
13058 if (info_ptr->gp_size == 0)
13059 info_ptr->gp_save_offset = 0;
13061 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13062 info_ptr->altivec_save_offset = 0;
13064 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13065 info_ptr->vrsave_save_offset = 0;
13067 if (! TARGET_SPE_ABI
13068 || info_ptr->spe_64bit_regs_used == 0
13069 || info_ptr->spe_gp_size == 0)
13070 info_ptr->spe_gp_save_offset = 0;
13072 if (! info_ptr->lr_save_p)
13073 info_ptr->lr_save_offset = 0;
13075 if (! info_ptr->cr_save_p)
13076 info_ptr->cr_save_offset = 0;
13081 /* Return true if the current function uses any GPRs in 64-bit SIMD
13085 spe_func_has_64bit_regs_p (void)
13089 /* Functions that save and restore all the call-saved registers will
13090 need to save/restore the registers in 64-bits. */
13091 if (current_function_calls_eh_return
13092 || current_function_calls_setjmp
13093 || current_function_has_nonlocal_goto)
13096 insns = get_insns ();
13098 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13104 /* FIXME: This should be implemented with attributes...
13106 (set_attr "spe64" "true")....then,
13107 if (get_spe64(insn)) return true;
13109 It's the only reliable way to do the stuff below. */
13111 i = PATTERN (insn);
13112 if (GET_CODE (i) == SET)
13114 enum machine_mode mode = GET_MODE (SET_SRC (i));
13116 if (SPE_VECTOR_MODE (mode))
13118 if (TARGET_E500_DOUBLE && mode == DFmode)
13128 debug_stack_info (rs6000_stack_t *info)
13130 const char *abi_string;
13133 info = rs6000_stack_info ();
13135 fprintf (stderr, "\nStack information for function %s:\n",
13136 ((current_function_decl && DECL_NAME (current_function_decl))
13137 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13142 default: abi_string = "Unknown"; break;
13143 case ABI_NONE: abi_string = "NONE"; break;
13144 case ABI_AIX: abi_string = "AIX"; break;
13145 case ABI_DARWIN: abi_string = "Darwin"; break;
13146 case ABI_V4: abi_string = "V.4"; break;
13149 fprintf (stderr, "\tABI = %5s\n", abi_string);
13151 if (TARGET_ALTIVEC_ABI)
13152 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13154 if (TARGET_SPE_ABI)
13155 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13157 if (info->first_gp_reg_save != 32)
13158 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13160 if (info->first_fp_reg_save != 64)
13161 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13163 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13164 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13165 info->first_altivec_reg_save);
13167 if (info->lr_save_p)
13168 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13170 if (info->cr_save_p)
13171 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13173 if (info->vrsave_mask)
13174 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13177 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13180 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13182 if (info->gp_save_offset)
13183 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13185 if (info->fp_save_offset)
13186 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13188 if (info->altivec_save_offset)
13189 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13190 info->altivec_save_offset);
13192 if (info->spe_gp_save_offset)
13193 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13194 info->spe_gp_save_offset);
13196 if (info->vrsave_save_offset)
13197 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13198 info->vrsave_save_offset);
13200 if (info->lr_save_offset)
13201 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13203 if (info->cr_save_offset)
13204 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13206 if (info->varargs_save_offset)
13207 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13209 if (info->total_size)
13210 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13213 if (info->vars_size)
13214 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13217 if (info->parm_size)
13218 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13220 if (info->fixed_size)
13221 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13224 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13226 if (info->spe_gp_size)
13227 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13230 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13232 if (info->altivec_size)
13233 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13235 if (info->vrsave_size)
13236 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13238 if (info->altivec_padding_size)
13239 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13240 info->altivec_padding_size);
13242 if (info->spe_padding_size)
13243 fprintf (stderr, "\tspe_padding_size = %5d\n",
13244 info->spe_padding_size);
13247 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13249 if (info->save_size)
13250 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13252 if (info->reg_size != 4)
13253 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13255 fprintf (stderr, "\n");
13259 rs6000_return_addr (int count, rtx frame)
13261 /* Currently we don't optimize very well between prolog and body
13262 code and for PIC code the code can be actually quite bad, so
13263 don't try to be too clever here. */
13264 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13266 cfun->machine->ra_needs_full_frame = 1;
13273 plus_constant (copy_to_reg
13274 (gen_rtx_MEM (Pmode,
13275 memory_address (Pmode, frame))),
13276 RETURN_ADDRESS_OFFSET)));
13279 cfun->machine->ra_need_lr = 1;
13280 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13283 /* Say whether a function is a candidate for sibcall handling or not.
13284 We do not allow indirect calls to be optimized into sibling calls.
13285 Also, we can't do it if there are any vector parameters; there's
13286 nowhere to put the VRsave code so it works; note that functions with
13287 vector parameters are required to have a prototype, so the argument
13288 type info must be available here. (The tail recursion case can work
13289 with vector parameters, but there's no way to distinguish here.) */
13291 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13296 if (TARGET_ALTIVEC_VRSAVE)
13298 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13299 type; type = TREE_CHAIN (type))
13301 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13305 if (DEFAULT_ABI == ABI_DARWIN
13306 || (*targetm.binds_local_p) (decl))
13308 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13310 if (!lookup_attribute ("longcall", attr_list)
13311 || lookup_attribute ("shortcall", attr_list))
13318 /* NULL if INSN insn is valid within a low-overhead loop.
13319 Otherwise return why doloop cannot be applied.
13320 PowerPC uses the COUNT register for branch on table instructions. */
13322 static const char *
13323 rs6000_invalid_within_doloop (rtx insn)
13326 return "Function call in the loop.";
13329 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13330 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13331 return "Computed branch in the loop.";
13337 rs6000_ra_ever_killed (void)
13343 if (current_function_is_thunk)
13346 /* regs_ever_live has LR marked as used if any sibcalls are present,
13347 but this should not force saving and restoring in the
13348 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13349 clobbers LR, so that is inappropriate. */
13351 /* Also, the prologue can generate a store into LR that
13352 doesn't really count, like this:
13355 bcl to set PIC register
13359 When we're called from the epilogue, we need to avoid counting
13360 this as a store. */
13362 push_topmost_sequence ();
13363 top = get_insns ();
13364 pop_topmost_sequence ();
13365 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13367 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13373 if (!SIBLING_CALL_P (insn))
13376 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13378 else if (set_of (reg, insn) != NULL_RTX
13379 && !prologue_epilogue_contains (insn))
13386 /* Add a REG_MAYBE_DEAD note to the insn. */
13388 rs6000_maybe_dead (rtx insn)
13390 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13395 /* Emit instructions needed to load the TOC register.
13396 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13397 a constant pool; or for SVR4 -fpic. */
13400 rs6000_emit_load_toc_table (int fromprolog)
13403 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13405 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13408 rtx lab, tmp1, tmp2, got, tempLR;
13410 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13411 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13413 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13415 got = rs6000_got_sym ();
13416 tmp1 = tmp2 = dest;
13419 tmp1 = gen_reg_rtx (Pmode);
13420 tmp2 = gen_reg_rtx (Pmode);
13422 tempLR = (fromprolog
13423 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13424 : gen_reg_rtx (Pmode));
13425 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13427 rs6000_maybe_dead (insn);
13428 insn = emit_move_insn (tmp1, tempLR);
13430 rs6000_maybe_dead (insn);
13431 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13433 rs6000_maybe_dead (insn);
13434 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13436 rs6000_maybe_dead (insn);
13438 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13440 rtx tempLR = (fromprolog
13441 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13442 : gen_reg_rtx (Pmode));
13444 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13446 rs6000_maybe_dead (insn);
13447 insn = emit_move_insn (dest, tempLR);
13449 rs6000_maybe_dead (insn);
13451 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13454 rtx tempLR = (fromprolog
13455 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13456 : gen_reg_rtx (Pmode));
13457 rtx temp0 = (fromprolog
13458 ? gen_rtx_REG (Pmode, 0)
13459 : gen_reg_rtx (Pmode));
13465 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13466 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13468 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13469 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13471 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13473 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13474 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13482 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13483 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13484 emit_move_insn (dest, tempLR);
13485 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13487 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13489 rs6000_maybe_dead (insn);
13491 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13493 /* This is for AIX code running in non-PIC ELF32. */
13496 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13497 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13499 insn = emit_insn (gen_elf_high (dest, realsym));
13501 rs6000_maybe_dead (insn);
13502 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13504 rs6000_maybe_dead (insn);
13508 gcc_assert (DEFAULT_ABI == ABI_AIX);
13511 insn = emit_insn (gen_load_toc_aix_si (dest));
13513 insn = emit_insn (gen_load_toc_aix_di (dest));
13515 rs6000_maybe_dead (insn);
13519 /* Emit instructions to restore the link register after determining where
13520 its value has been stored. */
13523 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13525 rs6000_stack_t *info = rs6000_stack_info ();
13528 operands[0] = source;
13529 operands[1] = scratch;
13531 if (info->lr_save_p)
13533 rtx frame_rtx = stack_pointer_rtx;
13534 HOST_WIDE_INT sp_offset = 0;
13537 if (frame_pointer_needed
13538 || current_function_calls_alloca
13539 || info->total_size > 32767)
13541 tmp = gen_frame_mem (Pmode, frame_rtx);
13542 emit_move_insn (operands[1], tmp);
13543 frame_rtx = operands[1];
13545 else if (info->push_p)
13546 sp_offset = info->total_size;
13548 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13549 tmp = gen_frame_mem (Pmode, tmp);
13550 emit_move_insn (tmp, operands[0]);
13553 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13556 static GTY(()) int set = -1;
13559 get_TOC_alias_set (void)
13562 set = new_alias_set ();
13566 /* This returns nonzero if the current function uses the TOC. This is
13567 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13568 is generated by the ABI_V4 load_toc_* patterns. */
13575 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13578 rtx pat = PATTERN (insn);
13581 if (GET_CODE (pat) == PARALLEL)
13582 for (i = 0; i < XVECLEN (pat, 0); i++)
13584 rtx sub = XVECEXP (pat, 0, i);
13585 if (GET_CODE (sub) == USE)
13587 sub = XEXP (sub, 0);
13588 if (GET_CODE (sub) == UNSPEC
13589 && XINT (sub, 1) == UNSPEC_TOC)
13599 create_TOC_reference (rtx symbol)
13601 if (no_new_pseudos)
13602 regs_ever_live[TOC_REGISTER] = 1;
13603 return gen_rtx_PLUS (Pmode,
13604 gen_rtx_REG (Pmode, TOC_REGISTER),
13605 gen_rtx_CONST (Pmode,
13606 gen_rtx_MINUS (Pmode, symbol,
13607 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13610 /* If _Unwind_* has been called from within the same module,
13611 toc register is not guaranteed to be saved to 40(1) on function
13612 entry. Save it there in that case. */
13615 rs6000_aix_emit_builtin_unwind_init (void)
13618 rtx stack_top = gen_reg_rtx (Pmode);
13619 rtx opcode_addr = gen_reg_rtx (Pmode);
13620 rtx opcode = gen_reg_rtx (SImode);
13621 rtx tocompare = gen_reg_rtx (SImode);
13622 rtx no_toc_save_needed = gen_label_rtx ();
13624 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13625 emit_move_insn (stack_top, mem);
13627 mem = gen_frame_mem (Pmode,
13628 gen_rtx_PLUS (Pmode, stack_top,
13629 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13630 emit_move_insn (opcode_addr, mem);
13631 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13632 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13633 : 0xE8410028, SImode));
13635 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13636 SImode, NULL_RTX, NULL_RTX,
13637 no_toc_save_needed);
13639 mem = gen_frame_mem (Pmode,
13640 gen_rtx_PLUS (Pmode, stack_top,
13641 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13642 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13643 emit_label (no_toc_save_needed);
13646 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13647 and the change to the stack pointer. */
13650 rs6000_emit_stack_tie (void)
13652 rtx mem = gen_frame_mem (BLKmode,
13653 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13655 emit_insn (gen_stack_tie (mem));
13658 /* Emit the correct code for allocating stack space, as insns.
13659 If COPY_R12, make sure a copy of the old frame is left in r12.
13660 The generated code may use hard register 0 as a temporary. */
13663 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13666 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13667 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13668 rtx todec = gen_int_mode (-size, Pmode);
13670 if (INTVAL (todec) != -size)
13672 warning (0, "stack frame too large");
13673 emit_insn (gen_trap ());
13677 if (current_function_limit_stack)
13679 if (REG_P (stack_limit_rtx)
13680 && REGNO (stack_limit_rtx) > 1
13681 && REGNO (stack_limit_rtx) <= 31)
13683 emit_insn (TARGET_32BIT
13684 ? gen_addsi3 (tmp_reg,
13687 : gen_adddi3 (tmp_reg,
13691 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13694 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13696 && DEFAULT_ABI == ABI_V4)
13698 rtx toload = gen_rtx_CONST (VOIDmode,
13699 gen_rtx_PLUS (Pmode,
13703 emit_insn (gen_elf_high (tmp_reg, toload));
13704 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13705 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13709 warning (0, "stack limit expression is not supported");
13712 if (copy_r12 || ! TARGET_UPDATE)
13713 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13719 /* Need a note here so that try_split doesn't get confused. */
13720 if (get_last_insn () == NULL_RTX)
13721 emit_note (NOTE_INSN_DELETED);
13722 insn = emit_move_insn (tmp_reg, todec);
13723 try_split (PATTERN (insn), insn, 0);
13727 insn = emit_insn (TARGET_32BIT
13728 ? gen_movsi_update (stack_reg, stack_reg,
13730 : gen_movdi_di_update (stack_reg, stack_reg,
13731 todec, stack_reg));
13735 insn = emit_insn (TARGET_32BIT
13736 ? gen_addsi3 (stack_reg, stack_reg, todec)
13737 : gen_adddi3 (stack_reg, stack_reg, todec));
13738 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13739 gen_rtx_REG (Pmode, 12));
13742 RTX_FRAME_RELATED_P (insn) = 1;
13744 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13745 gen_rtx_SET (VOIDmode, stack_reg,
13746 gen_rtx_PLUS (Pmode, stack_reg,
13751 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13752 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13753 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13754 deduce these equivalences by itself so it wasn't necessary to hold
13755 its hand so much. */
13758 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13759 rtx reg2, rtx rreg)
13763 /* copy_rtx will not make unique copies of registers, so we need to
13764 ensure we don't have unwanted sharing here. */
13766 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13769 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13771 real = copy_rtx (PATTERN (insn));
13773 if (reg2 != NULL_RTX)
13774 real = replace_rtx (real, reg2, rreg);
13776 real = replace_rtx (real, reg,
13777 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13778 STACK_POINTER_REGNUM),
13781 /* We expect that 'real' is either a SET or a PARALLEL containing
13782 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13783 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13785 if (GET_CODE (real) == SET)
13789 temp = simplify_rtx (SET_SRC (set));
13791 SET_SRC (set) = temp;
13792 temp = simplify_rtx (SET_DEST (set));
13794 SET_DEST (set) = temp;
13795 if (GET_CODE (SET_DEST (set)) == MEM)
13797 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13799 XEXP (SET_DEST (set), 0) = temp;
13806 gcc_assert (GET_CODE (real) == PARALLEL);
13807 for (i = 0; i < XVECLEN (real, 0); i++)
13808 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13810 rtx set = XVECEXP (real, 0, i);
13812 temp = simplify_rtx (SET_SRC (set));
13814 SET_SRC (set) = temp;
13815 temp = simplify_rtx (SET_DEST (set));
13817 SET_DEST (set) = temp;
13818 if (GET_CODE (SET_DEST (set)) == MEM)
13820 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13822 XEXP (SET_DEST (set), 0) = temp;
13824 RTX_FRAME_RELATED_P (set) = 1;
13829 real = spe_synthesize_frame_save (real);
13831 RTX_FRAME_RELATED_P (insn) = 1;
13832 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13837 /* Given an SPE frame note, return a PARALLEL of SETs with the
13838 original note, plus a synthetic register save. */
13841 spe_synthesize_frame_save (rtx real)
13843 rtx synth, offset, reg, real2;
13845 if (GET_CODE (real) != SET
13846 || GET_MODE (SET_SRC (real)) != V2SImode)
13849 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13850 frame related note. The parallel contains a set of the register
13851 being saved, and another set to a synthetic register (n+1200).
13852 This is so we can differentiate between 64-bit and 32-bit saves.
13853 Words cannot describe this nastiness. */
13855 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13856 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13857 && GET_CODE (SET_SRC (real)) == REG);
13860 (set (mem (plus (reg x) (const y)))
13863 (set (mem (plus (reg x) (const y+4)))
13867 real2 = copy_rtx (real);
13868 PUT_MODE (SET_DEST (real2), SImode);
13869 reg = SET_SRC (real2);
13870 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13871 synth = copy_rtx (real2);
13873 if (BYTES_BIG_ENDIAN)
13875 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13876 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13879 reg = SET_SRC (synth);
13881 synth = replace_rtx (synth, reg,
13882 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13884 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13885 synth = replace_rtx (synth, offset,
13886 GEN_INT (INTVAL (offset)
13887 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13889 RTX_FRAME_RELATED_P (synth) = 1;
13890 RTX_FRAME_RELATED_P (real2) = 1;
13891 if (BYTES_BIG_ENDIAN)
13892 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13894 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13899 /* Returns an insn that has a vrsave set operation with the
13900 appropriate CLOBBERs. */
13903 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13906 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13907 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13910 = gen_rtx_SET (VOIDmode,
13912 gen_rtx_UNSPEC_VOLATILE (SImode,
13913 gen_rtvec (2, reg, vrsave),
13914 UNSPECV_SET_VRSAVE));
13918 /* We need to clobber the registers in the mask so the scheduler
13919 does not move sets to VRSAVE before sets of AltiVec registers.
13921 However, if the function receives nonlocal gotos, reload will set
13922 all call saved registers live. We will end up with:
13924 (set (reg 999) (mem))
13925 (parallel [ (set (reg vrsave) (unspec blah))
13926 (clobber (reg 999))])
13928 The clobber will cause the store into reg 999 to be dead, and
13929 flow will attempt to delete an epilogue insn. In this case, we
13930 need an unspec use/set of the register. */
13932 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13933 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13935 if (!epiloguep || call_used_regs [i])
13936 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13937 gen_rtx_REG (V4SImode, i));
13940 rtx reg = gen_rtx_REG (V4SImode, i);
13943 = gen_rtx_SET (VOIDmode,
13945 gen_rtx_UNSPEC (V4SImode,
13946 gen_rtvec (1, reg), 27));
13950 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13952 for (i = 0; i < nclobs; ++i)
13953 XVECEXP (insn, 0, i) = clobs[i];
13958 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13959 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13962 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13963 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13965 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13966 rtx replacea, replaceb;
13968 int_rtx = GEN_INT (offset);
13970 /* Some cases that need register indexed addressing. */
13971 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13972 || (TARGET_E500_DOUBLE && mode == DFmode)
13974 && SPE_VECTOR_MODE (mode)
13975 && !SPE_CONST_OFFSET_OK (offset)))
13977 /* Whomever calls us must make sure r11 is available in the
13978 flow path of instructions in the prologue. */
13979 offset_rtx = gen_rtx_REG (Pmode, 11);
13980 emit_move_insn (offset_rtx, int_rtx);
13982 replacea = offset_rtx;
13983 replaceb = int_rtx;
13987 offset_rtx = int_rtx;
13988 replacea = NULL_RTX;
13989 replaceb = NULL_RTX;
13992 reg = gen_rtx_REG (mode, regno);
13993 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13994 mem = gen_frame_mem (mode, addr);
13996 insn = emit_move_insn (mem, reg);
13998 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14001 /* Emit an offset memory reference suitable for a frame store, while
14002 converting to a valid addressing mode. */
14005 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14007 rtx int_rtx, offset_rtx;
14009 int_rtx = GEN_INT (offset);
14011 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14012 || (TARGET_E500_DOUBLE && mode == DFmode))
14014 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14015 emit_move_insn (offset_rtx, int_rtx);
14018 offset_rtx = int_rtx;
14020 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14023 /* Look for user-defined global regs. We should not save and restore these,
14024 and cannot use stmw/lmw if there are any in its range. */
14027 no_global_regs_above (int first_greg)
14030 for (i = 0; i < 32 - first_greg; i++)
14031 if (global_regs[first_greg + i])
14036 #ifndef TARGET_FIX_AND_CONTINUE
14037 #define TARGET_FIX_AND_CONTINUE 0
14040 /* Emit function prologue as insns. */
14043 rs6000_emit_prologue (void)
14045 rs6000_stack_t *info = rs6000_stack_info ();
14046 enum machine_mode reg_mode = Pmode;
14047 int reg_size = TARGET_32BIT ? 4 : 8;
14048 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14049 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14050 rtx frame_reg_rtx = sp_reg_rtx;
14051 rtx cr_save_rtx = NULL_RTX;
14053 int saving_FPRs_inline;
14054 int using_store_multiple;
14055 HOST_WIDE_INT sp_offset = 0;
14057 if (TARGET_FIX_AND_CONTINUE)
14059 /* gdb on darwin arranges to forward a function from the old
14060 address by modifying the first 5 instructions of the function
14061 to branch to the overriding function. This is necessary to
14062 permit function pointers that point to the old function to
14063 actually forward to the new function. */
14064 emit_insn (gen_nop ());
14065 emit_insn (gen_nop ());
14066 emit_insn (gen_nop ());
14067 emit_insn (gen_nop ());
14068 emit_insn (gen_nop ());
14071 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14073 reg_mode = V2SImode;
14077 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14078 && (!TARGET_SPE_ABI
14079 || info->spe_64bit_regs_used == 0)
14080 && info->first_gp_reg_save < 31
14081 && no_global_regs_above (info->first_gp_reg_save));
14082 saving_FPRs_inline = (info->first_fp_reg_save == 64
14083 || FP_SAVE_INLINE (info->first_fp_reg_save)
14084 || current_function_calls_eh_return
14085 || cfun->machine->ra_need_lr);
14087 /* For V.4, update stack before we do any saving and set back pointer. */
14089 && (DEFAULT_ABI == ABI_V4
14090 || current_function_calls_eh_return))
14092 if (info->total_size < 32767)
14093 sp_offset = info->total_size;
14095 frame_reg_rtx = frame_ptr_rtx;
14096 rs6000_emit_allocate_stack (info->total_size,
14097 (frame_reg_rtx != sp_reg_rtx
14098 && (info->cr_save_p
14100 || info->first_fp_reg_save < 64
14101 || info->first_gp_reg_save < 32
14103 if (frame_reg_rtx != sp_reg_rtx)
14104 rs6000_emit_stack_tie ();
14107 /* Handle world saves specially here. */
14108 if (WORLD_SAVE_P (info))
14114 /* save_world expects lr in r0. */
14115 if (info->lr_save_p)
14117 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14118 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14119 RTX_FRAME_RELATED_P (insn) = 1;
14122 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14123 assumptions about the offsets of various bits of the stack
14125 gcc_assert (info->gp_save_offset == -220
14126 && info->fp_save_offset == -144
14127 && info->lr_save_offset == 8
14128 && info->cr_save_offset == 4
14131 && (!current_function_calls_eh_return
14132 || info->ehrd_offset == -432)
14133 && info->vrsave_save_offset == -224
14134 && info->altivec_save_offset == (-224 -16 -192));
14136 treg = gen_rtx_REG (SImode, 11);
14137 emit_move_insn (treg, GEN_INT (-info->total_size));
14139 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14140 in R11. It also clobbers R12, so beware! */
14142 /* Preserve CR2 for save_world prologues */
14144 sz += 32 - info->first_gp_reg_save;
14145 sz += 64 - info->first_fp_reg_save;
14146 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14147 p = rtvec_alloc (sz);
14149 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14150 gen_rtx_REG (Pmode,
14151 LINK_REGISTER_REGNUM));
14152 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14153 gen_rtx_SYMBOL_REF (Pmode,
14155 /* We do floats first so that the instruction pattern matches
14157 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14159 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14160 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14161 GEN_INT (info->fp_save_offset
14162 + sp_offset + 8 * i));
14163 rtx mem = gen_frame_mem (DFmode, addr);
14165 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14167 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14169 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14170 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14171 GEN_INT (info->altivec_save_offset
14172 + sp_offset + 16 * i));
14173 rtx mem = gen_frame_mem (V4SImode, addr);
14175 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14177 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14179 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14180 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14181 GEN_INT (info->gp_save_offset
14182 + sp_offset + reg_size * i));
14183 rtx mem = gen_frame_mem (reg_mode, addr);
14185 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14189 /* CR register traditionally saved as CR2. */
14190 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14191 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14192 GEN_INT (info->cr_save_offset
14194 rtx mem = gen_frame_mem (reg_mode, addr);
14196 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14198 /* Prevent any attempt to delete the setting of r0 and treg! */
14199 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14200 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14201 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14203 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14204 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14205 NULL_RTX, NULL_RTX);
14207 if (current_function_calls_eh_return)
14212 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14213 if (regno == INVALID_REGNUM)
14215 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14216 info->ehrd_offset + sp_offset
14217 + reg_size * (int) i,
14223 /* Save AltiVec registers if needed. */
14224 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14228 /* There should be a non inline version of this, for when we
14229 are saving lots of vector registers. */
14230 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14231 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14233 rtx areg, savereg, mem;
14236 offset = info->altivec_save_offset + sp_offset
14237 + 16 * (i - info->first_altivec_reg_save);
14239 savereg = gen_rtx_REG (V4SImode, i);
14241 areg = gen_rtx_REG (Pmode, 0);
14242 emit_move_insn (areg, GEN_INT (offset));
14244 /* AltiVec addressing mode is [reg+reg]. */
14245 mem = gen_frame_mem (V4SImode,
14246 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14248 insn = emit_move_insn (mem, savereg);
14250 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14251 areg, GEN_INT (offset));
14255 /* VRSAVE is a bit vector representing which AltiVec registers
14256 are used. The OS uses this to determine which vector
14257 registers to save on a context switch. We need to save
14258 VRSAVE on the stack frame, add whatever AltiVec registers we
14259 used in this function, and do the corresponding magic in the
14262 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14263 && info->vrsave_mask != 0)
14265 rtx reg, mem, vrsave;
14268 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14269 as frame_reg_rtx and r11 as the static chain pointer for
14270 nested functions. */
14271 reg = gen_rtx_REG (SImode, 0);
14272 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14274 emit_insn (gen_get_vrsave_internal (reg));
14276 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14278 if (!WORLD_SAVE_P (info))
14281 offset = info->vrsave_save_offset + sp_offset;
14282 mem = gen_frame_mem (SImode,
14283 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14284 GEN_INT (offset)));
14285 insn = emit_move_insn (mem, reg);
14288 /* Include the registers in the mask. */
14289 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14291 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14294 /* If we use the link register, get it into r0. */
14295 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14297 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14298 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14299 RTX_FRAME_RELATED_P (insn) = 1;
14302 /* If we need to save CR, put it into r12. */
14303 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14307 cr_save_rtx = gen_rtx_REG (SImode, 12);
14308 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14309 RTX_FRAME_RELATED_P (insn) = 1;
14310 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14311 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14312 But that's OK. All we have to do is specify that _one_ condition
14313 code register is saved in this stack slot. The thrower's epilogue
14314 will then restore all the call-saved registers.
14315 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14316 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14317 gen_rtx_REG (SImode, CR2_REGNO));
14318 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14323 /* Do any required saving of fpr's. If only one or two to save, do
14324 it ourselves. Otherwise, call function. */
14325 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14328 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14329 if ((regs_ever_live[info->first_fp_reg_save+i]
14330 && ! call_used_regs[info->first_fp_reg_save+i]))
14331 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14332 info->first_fp_reg_save + i,
14333 info->fp_save_offset + sp_offset + 8 * i,
14336 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14340 const char *alloc_rname;
14342 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14344 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14345 gen_rtx_REG (Pmode,
14346 LINK_REGISTER_REGNUM));
14347 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14348 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14349 alloc_rname = ggc_strdup (rname);
14350 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14351 gen_rtx_SYMBOL_REF (Pmode,
14353 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14355 rtx addr, reg, mem;
14356 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14357 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14358 GEN_INT (info->fp_save_offset
14359 + sp_offset + 8*i));
14360 mem = gen_frame_mem (DFmode, addr);
14362 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14364 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14365 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14366 NULL_RTX, NULL_RTX);
14369 /* Save GPRs. This is done as a PARALLEL if we are using
14370 the store-multiple instructions. */
14371 if (!WORLD_SAVE_P (info) && using_store_multiple)
14375 p = rtvec_alloc (32 - info->first_gp_reg_save);
14376 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14378 rtx addr, reg, mem;
14379 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14380 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14381 GEN_INT (info->gp_save_offset
14384 mem = gen_frame_mem (reg_mode, addr);
14386 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14388 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14389 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14390 NULL_RTX, NULL_RTX);
14392 else if (!WORLD_SAVE_P (info))
14395 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14396 if ((regs_ever_live[info->first_gp_reg_save + i]
14397 && (!call_used_regs[info->first_gp_reg_save + i]
14398 || (i + info->first_gp_reg_save
14399 == RS6000_PIC_OFFSET_TABLE_REGNUM
14400 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14401 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14402 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14403 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14405 rtx addr, reg, mem;
14406 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14408 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14410 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14413 if (!SPE_CONST_OFFSET_OK (offset))
14415 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14416 emit_move_insn (b, GEN_INT (offset));
14419 b = GEN_INT (offset);
14421 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14422 mem = gen_frame_mem (V2SImode, addr);
14423 insn = emit_move_insn (mem, reg);
14425 if (GET_CODE (b) == CONST_INT)
14426 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14427 NULL_RTX, NULL_RTX);
14429 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14430 b, GEN_INT (offset));
14434 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14435 GEN_INT (info->gp_save_offset
14438 mem = gen_frame_mem (reg_mode, addr);
14440 insn = emit_move_insn (mem, reg);
14441 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14442 NULL_RTX, NULL_RTX);
14447 /* ??? There's no need to emit actual instructions here, but it's the
14448 easiest way to get the frame unwind information emitted. */
14449 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14451 unsigned int i, regno;
14453 /* In AIX ABI we need to pretend we save r2 here. */
14456 rtx addr, reg, mem;
14458 reg = gen_rtx_REG (reg_mode, 2);
14459 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14460 GEN_INT (sp_offset + 5 * reg_size));
14461 mem = gen_frame_mem (reg_mode, addr);
14463 insn = emit_move_insn (mem, reg);
14464 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14465 NULL_RTX, NULL_RTX);
14466 PATTERN (insn) = gen_blockage ();
14471 regno = EH_RETURN_DATA_REGNO (i);
14472 if (regno == INVALID_REGNUM)
14475 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14476 info->ehrd_offset + sp_offset
14477 + reg_size * (int) i,
14482 /* Save lr if we used it. */
14483 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14485 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14486 GEN_INT (info->lr_save_offset + sp_offset));
14487 rtx reg = gen_rtx_REG (Pmode, 0);
14488 rtx mem = gen_rtx_MEM (Pmode, addr);
14489 /* This should not be of frame_alias_set, because of
14490 __builtin_return_address. */
14492 insn = emit_move_insn (mem, reg);
14493 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14494 NULL_RTX, NULL_RTX);
14497 /* Save CR if we use any that must be preserved. */
14498 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14500 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14501 GEN_INT (info->cr_save_offset + sp_offset));
14502 rtx mem = gen_frame_mem (SImode, addr);
14503 /* See the large comment above about why CR2_REGNO is used. */
14504 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14506 /* If r12 was used to hold the original sp, copy cr into r0 now
14508 if (REGNO (frame_reg_rtx) == 12)
14512 cr_save_rtx = gen_rtx_REG (SImode, 0);
14513 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14514 RTX_FRAME_RELATED_P (insn) = 1;
14515 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14516 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14521 insn = emit_move_insn (mem, cr_save_rtx);
14523 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14524 NULL_RTX, NULL_RTX);
14527 /* Update stack and set back pointer unless this is V.4,
14528 for which it was done previously. */
14529 if (!WORLD_SAVE_P (info) && info->push_p
14530 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14531 rs6000_emit_allocate_stack (info->total_size, FALSE);
14533 /* Set frame pointer, if needed. */
14534 if (frame_pointer_needed)
14536 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14538 RTX_FRAME_RELATED_P (insn) = 1;
14541 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14542 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14543 || (DEFAULT_ABI == ABI_V4
14544 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14545 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14547 /* If emit_load_toc_table will use the link register, we need to save
14548 it. We use R12 for this purpose because emit_load_toc_table
14549 can use register 0. This allows us to use a plain 'blr' to return
14550 from the procedure more often. */
14551 int save_LR_around_toc_setup = (TARGET_ELF
14552 && DEFAULT_ABI != ABI_AIX
14554 && ! info->lr_save_p
14555 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14556 if (save_LR_around_toc_setup)
14558 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14560 insn = emit_move_insn (frame_ptr_rtx, lr);
14561 rs6000_maybe_dead (insn);
14562 RTX_FRAME_RELATED_P (insn) = 1;
14564 rs6000_emit_load_toc_table (TRUE);
14566 insn = emit_move_insn (lr, frame_ptr_rtx);
14567 rs6000_maybe_dead (insn);
14568 RTX_FRAME_RELATED_P (insn) = 1;
14571 rs6000_emit_load_toc_table (TRUE);
14575 if (DEFAULT_ABI == ABI_DARWIN
14576 && flag_pic && current_function_uses_pic_offset_table)
14578 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14579 rtx src = machopic_function_base_sym ();
14581 /* Save and restore LR locally around this call (in R0). */
14582 if (!info->lr_save_p)
14583 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14585 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14587 insn = emit_move_insn (gen_rtx_REG (Pmode,
14588 RS6000_PIC_OFFSET_TABLE_REGNUM),
14590 rs6000_maybe_dead (insn);
14592 if (!info->lr_save_p)
14593 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14598 /* Write function prologue. */
14601 rs6000_output_function_prologue (FILE *file,
14602 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14604 rs6000_stack_t *info = rs6000_stack_info ();
14606 if (TARGET_DEBUG_STACK)
14607 debug_stack_info (info);
14609 /* Write .extern for any function we will call to save and restore
14611 if (info->first_fp_reg_save < 64
14612 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14613 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14614 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14615 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14616 RESTORE_FP_SUFFIX);
14618 /* Write .extern for AIX common mode routines, if needed. */
14619 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14621 fputs ("\t.extern __mulh\n", file);
14622 fputs ("\t.extern __mull\n", file);
14623 fputs ("\t.extern __divss\n", file);
14624 fputs ("\t.extern __divus\n", file);
14625 fputs ("\t.extern __quoss\n", file);
14626 fputs ("\t.extern __quous\n", file);
14627 common_mode_defined = 1;
14630 if (! HAVE_prologue)
14634 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14635 the "toplevel" insn chain. */
14636 emit_note (NOTE_INSN_DELETED);
14637 rs6000_emit_prologue ();
14638 emit_note (NOTE_INSN_DELETED);
14640 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14644 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14646 INSN_ADDRESSES_NEW (insn, addr);
14651 if (TARGET_DEBUG_STACK)
14652 debug_rtx_list (get_insns (), 100);
14653 final (get_insns (), file, FALSE);
14657 rs6000_pic_labelno++;
14660 /* Emit function epilogue as insns.
14662 At present, dwarf2out_frame_debug_expr doesn't understand
14663 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14664 anywhere in the epilogue. Most of the insns below would in any case
14665 need special notes to explain where r11 is in relation to the stack. */
14668 rs6000_emit_epilogue (int sibcall)
14670 rs6000_stack_t *info;
14671 int restoring_FPRs_inline;
14672 int using_load_multiple;
14673 int using_mfcr_multiple;
14674 int use_backchain_to_restore_sp;
14676 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14677 rtx frame_reg_rtx = sp_reg_rtx;
14678 enum machine_mode reg_mode = Pmode;
14679 int reg_size = TARGET_32BIT ? 4 : 8;
14682 info = rs6000_stack_info ();
14684 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14686 reg_mode = V2SImode;
14690 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14691 && (!TARGET_SPE_ABI
14692 || info->spe_64bit_regs_used == 0)
14693 && info->first_gp_reg_save < 31
14694 && no_global_regs_above (info->first_gp_reg_save));
14695 restoring_FPRs_inline = (sibcall
14696 || current_function_calls_eh_return
14697 || info->first_fp_reg_save == 64
14698 || FP_SAVE_INLINE (info->first_fp_reg_save));
14699 use_backchain_to_restore_sp = (frame_pointer_needed
14700 || current_function_calls_alloca
14701 || info->total_size > 32767);
14702 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14703 || rs6000_cpu == PROCESSOR_PPC603
14704 || rs6000_cpu == PROCESSOR_PPC750
14707 if (WORLD_SAVE_P (info))
14711 const char *alloc_rname;
14714 /* eh_rest_world_r10 will return to the location saved in the LR
14715 stack slot (which is not likely to be our caller.)
14716 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14717 rest_world is similar, except any R10 parameter is ignored.
14718 The exception-handling stuff that was here in 2.95 is no
14719 longer necessary. */
14723 + 32 - info->first_gp_reg_save
14724 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14725 + 63 + 1 - info->first_fp_reg_save);
14727 strcpy (rname, ((current_function_calls_eh_return) ?
14728 "*eh_rest_world_r10" : "*rest_world"));
14729 alloc_rname = ggc_strdup (rname);
14732 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14733 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14734 gen_rtx_REG (Pmode,
14735 LINK_REGISTER_REGNUM));
14737 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14738 /* The instruction pattern requires a clobber here;
14739 it is shared with the restVEC helper. */
14741 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14744 /* CR register traditionally saved as CR2. */
14745 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14746 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14747 GEN_INT (info->cr_save_offset));
14748 rtx mem = gen_frame_mem (reg_mode, addr);
14750 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14753 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14755 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14756 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14757 GEN_INT (info->gp_save_offset
14759 rtx mem = gen_frame_mem (reg_mode, addr);
14761 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14763 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14765 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14766 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14767 GEN_INT (info->altivec_save_offset
14769 rtx mem = gen_frame_mem (V4SImode, addr);
14771 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14773 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14775 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14776 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14777 GEN_INT (info->fp_save_offset
14779 rtx mem = gen_frame_mem (DFmode, addr);
14781 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14784 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14786 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14788 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14790 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14792 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14793 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14798 /* If we have a frame pointer, a call to alloca, or a large stack
14799 frame, restore the old stack pointer using the backchain. Otherwise,
14800 we know what size to update it with. */
14801 if (use_backchain_to_restore_sp)
14803 /* Under V.4, don't reset the stack pointer until after we're done
14804 loading the saved registers. */
14805 if (DEFAULT_ABI == ABI_V4)
14806 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14808 emit_move_insn (frame_reg_rtx,
14809 gen_rtx_MEM (Pmode, sp_reg_rtx));
14811 else if (info->push_p)
14813 if (DEFAULT_ABI == ABI_V4
14814 || current_function_calls_eh_return)
14815 sp_offset = info->total_size;
14818 emit_insn (TARGET_32BIT
14819 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14820 GEN_INT (info->total_size))
14821 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14822 GEN_INT (info->total_size)));
14826 /* Restore AltiVec registers if needed. */
14827 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14831 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14832 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14834 rtx addr, areg, mem;
14836 areg = gen_rtx_REG (Pmode, 0);
14838 (areg, GEN_INT (info->altivec_save_offset
14840 + 16 * (i - info->first_altivec_reg_save)));
14842 /* AltiVec addressing mode is [reg+reg]. */
14843 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14844 mem = gen_frame_mem (V4SImode, addr);
14846 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14850 /* Restore VRSAVE if needed. */
14851 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14852 && info->vrsave_mask != 0)
14854 rtx addr, mem, reg;
14856 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14857 GEN_INT (info->vrsave_save_offset + sp_offset));
14858 mem = gen_frame_mem (SImode, addr);
14859 reg = gen_rtx_REG (SImode, 12);
14860 emit_move_insn (reg, mem);
14862 emit_insn (generate_set_vrsave (reg, info, 1));
14865 /* Get the old lr if we saved it. */
14866 if (info->lr_save_p)
14868 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14869 info->lr_save_offset + sp_offset);
14871 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14874 /* Get the old cr if we saved it. */
14875 if (info->cr_save_p)
14877 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14878 GEN_INT (info->cr_save_offset + sp_offset));
14879 rtx mem = gen_frame_mem (SImode, addr);
14881 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14884 /* Set LR here to try to overlap restores below. */
14885 if (info->lr_save_p)
14886 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14887 gen_rtx_REG (Pmode, 0));
14889 /* Load exception handler data registers, if needed. */
14890 if (current_function_calls_eh_return)
14892 unsigned int i, regno;
14896 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14897 GEN_INT (sp_offset + 5 * reg_size));
14898 rtx mem = gen_frame_mem (reg_mode, addr);
14900 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14907 regno = EH_RETURN_DATA_REGNO (i);
14908 if (regno == INVALID_REGNUM)
14911 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14912 info->ehrd_offset + sp_offset
14913 + reg_size * (int) i);
14915 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14919 /* Restore GPRs. This is done as a PARALLEL if we are using
14920 the load-multiple instructions. */
14921 if (using_load_multiple)
14924 p = rtvec_alloc (32 - info->first_gp_reg_save);
14925 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14927 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14928 GEN_INT (info->gp_save_offset
14931 rtx mem = gen_frame_mem (reg_mode, addr);
14934 gen_rtx_SET (VOIDmode,
14935 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14938 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14941 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14942 if ((regs_ever_live[info->first_gp_reg_save + i]
14943 && (!call_used_regs[info->first_gp_reg_save + i]
14944 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14945 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14946 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14947 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14948 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14950 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14951 GEN_INT (info->gp_save_offset
14954 rtx mem = gen_frame_mem (reg_mode, addr);
14956 /* Restore 64-bit quantities for SPE. */
14957 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14959 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14962 if (!SPE_CONST_OFFSET_OK (offset))
14964 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14965 emit_move_insn (b, GEN_INT (offset));
14968 b = GEN_INT (offset);
14970 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14971 mem = gen_frame_mem (V2SImode, addr);
14974 emit_move_insn (gen_rtx_REG (reg_mode,
14975 info->first_gp_reg_save + i), mem);
14978 /* Restore fpr's if we need to do it without calling a function. */
14979 if (restoring_FPRs_inline)
14980 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14981 if ((regs_ever_live[info->first_fp_reg_save+i]
14982 && ! call_used_regs[info->first_fp_reg_save+i]))
14985 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14986 GEN_INT (info->fp_save_offset
14989 mem = gen_frame_mem (DFmode, addr);
14991 emit_move_insn (gen_rtx_REG (DFmode,
14992 info->first_fp_reg_save + i),
14996 /* If we saved cr, restore it here. Just those that were used. */
14997 if (info->cr_save_p)
14999 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15002 if (using_mfcr_multiple)
15004 for (i = 0; i < 8; i++)
15005 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15007 gcc_assert (count);
15010 if (using_mfcr_multiple && count > 1)
15015 p = rtvec_alloc (count);
15018 for (i = 0; i < 8; i++)
15019 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15021 rtvec r = rtvec_alloc (2);
15022 RTVEC_ELT (r, 0) = r12_rtx;
15023 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15024 RTVEC_ELT (p, ndx) =
15025 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15026 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15029 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15030 gcc_assert (ndx == count);
15033 for (i = 0; i < 8; i++)
15034 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15036 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15042 /* If this is V.4, unwind the stack pointer after all of the loads
15044 if (frame_reg_rtx != sp_reg_rtx)
15046 /* This blockage is needed so that sched doesn't decide to move
15047 the sp change before the register restores. */
15048 rs6000_emit_stack_tie ();
15049 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15051 else if (sp_offset != 0)
15052 emit_insn (TARGET_32BIT
15053 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15054 GEN_INT (sp_offset))
15055 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15056 GEN_INT (sp_offset)));
15058 if (current_function_calls_eh_return)
15060 rtx sa = EH_RETURN_STACKADJ_RTX;
15061 emit_insn (TARGET_32BIT
15062 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15063 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15069 if (! restoring_FPRs_inline)
15070 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15072 p = rtvec_alloc (2);
15074 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15075 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15076 gen_rtx_REG (Pmode,
15077 LINK_REGISTER_REGNUM));
15079 /* If we have to restore more than two FP registers, branch to the
15080 restore function. It will return to our caller. */
15081 if (! restoring_FPRs_inline)
15085 const char *alloc_rname;
15087 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15088 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15089 alloc_rname = ggc_strdup (rname);
15090 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15091 gen_rtx_SYMBOL_REF (Pmode,
15094 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15097 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15098 GEN_INT (info->fp_save_offset + 8*i));
15099 mem = gen_frame_mem (DFmode, addr);
15101 RTVEC_ELT (p, i+3) =
15102 gen_rtx_SET (VOIDmode,
15103 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15108 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15112 /* Write function epilogue. */
15115 rs6000_output_function_epilogue (FILE *file,
15116 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15118 rs6000_stack_t *info = rs6000_stack_info ();
15120 if (! HAVE_epilogue)
15122 rtx insn = get_last_insn ();
15123 /* If the last insn was a BARRIER, we don't have to write anything except
15124 the trace table. */
15125 if (GET_CODE (insn) == NOTE)
15126 insn = prev_nonnote_insn (insn);
15127 if (insn == 0 || GET_CODE (insn) != BARRIER)
15129 /* This is slightly ugly, but at least we don't have two
15130 copies of the epilogue-emitting code. */
15133 /* A NOTE_INSN_DELETED is supposed to be at the start
15134 and end of the "toplevel" insn chain. */
15135 emit_note (NOTE_INSN_DELETED);
15136 rs6000_emit_epilogue (FALSE);
15137 emit_note (NOTE_INSN_DELETED);
15139 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15143 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15145 INSN_ADDRESSES_NEW (insn, addr);
15150 if (TARGET_DEBUG_STACK)
15151 debug_rtx_list (get_insns (), 100);
15152 final (get_insns (), file, FALSE);
15158 macho_branch_islands ();
15159 /* Mach-O doesn't support labels at the end of objects, so if
15160 it looks like we might want one, insert a NOP. */
15162 rtx insn = get_last_insn ();
15165 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15166 insn = PREV_INSN (insn);
15170 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15171 fputs ("\tnop\n", file);
15175 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15178 We don't output a traceback table if -finhibit-size-directive was
15179 used. The documentation for -finhibit-size-directive reads
15180 ``don't output a @code{.size} assembler directive, or anything
15181 else that would cause trouble if the function is split in the
15182 middle, and the two halves are placed at locations far apart in
15183 memory.'' The traceback table has this property, since it
15184 includes the offset from the start of the function to the
15185 traceback table itself.
15187 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15188 different traceback table. */
15189 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15190 && rs6000_traceback != traceback_none)
15192 const char *fname = NULL;
15193 const char *language_string = lang_hooks.name;
15194 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15196 int optional_tbtab;
15198 if (rs6000_traceback == traceback_full)
15199 optional_tbtab = 1;
15200 else if (rs6000_traceback == traceback_part)
15201 optional_tbtab = 0;
15203 optional_tbtab = !optimize_size && !TARGET_ELF;
15205 if (optional_tbtab)
15207 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15208 while (*fname == '.') /* V.4 encodes . in the name */
15211 /* Need label immediately before tbtab, so we can compute
15212 its offset from the function start. */
15213 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15214 ASM_OUTPUT_LABEL (file, fname);
15217 /* The .tbtab pseudo-op can only be used for the first eight
15218 expressions, since it can't handle the possibly variable
15219 length fields that follow. However, if you omit the optional
15220 fields, the assembler outputs zeros for all optional fields
15221 anyways, giving each variable length field is minimum length
15222 (as defined in sys/debug.h). Thus we can not use the .tbtab
15223 pseudo-op at all. */
15225 /* An all-zero word flags the start of the tbtab, for debuggers
15226 that have to find it by searching forward from the entry
15227 point or from the current pc. */
15228 fputs ("\t.long 0\n", file);
15230 /* Tbtab format type. Use format type 0. */
15231 fputs ("\t.byte 0,", file);
15233 /* Language type. Unfortunately, there does not seem to be any
15234 official way to discover the language being compiled, so we
15235 use language_string.
15236 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15237 Java is 13. Objective-C is 14. */
15238 if (! strcmp (language_string, "GNU C"))
15240 else if (! strcmp (language_string, "GNU F77")
15241 || ! strcmp (language_string, "GNU F95"))
15243 else if (! strcmp (language_string, "GNU Pascal"))
15245 else if (! strcmp (language_string, "GNU Ada"))
15247 else if (! strcmp (language_string, "GNU C++"))
15249 else if (! strcmp (language_string, "GNU Java"))
15251 else if (! strcmp (language_string, "GNU Objective-C"))
15254 gcc_unreachable ();
15255 fprintf (file, "%d,", i);
15257 /* 8 single bit fields: global linkage (not set for C extern linkage,
15258 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15259 from start of procedure stored in tbtab, internal function, function
15260 has controlled storage, function has no toc, function uses fp,
15261 function logs/aborts fp operations. */
15262 /* Assume that fp operations are used if any fp reg must be saved. */
15263 fprintf (file, "%d,",
15264 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15266 /* 6 bitfields: function is interrupt handler, name present in
15267 proc table, function calls alloca, on condition directives
15268 (controls stack walks, 3 bits), saves condition reg, saves
15270 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15271 set up as a frame pointer, even when there is no alloca call. */
15272 fprintf (file, "%d,",
15273 ((optional_tbtab << 6)
15274 | ((optional_tbtab & frame_pointer_needed) << 5)
15275 | (info->cr_save_p << 1)
15276 | (info->lr_save_p)));
15278 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15280 fprintf (file, "%d,",
15281 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15283 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15284 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15286 if (optional_tbtab)
15288 /* Compute the parameter info from the function decl argument
15291 int next_parm_info_bit = 31;
15293 for (decl = DECL_ARGUMENTS (current_function_decl);
15294 decl; decl = TREE_CHAIN (decl))
15296 rtx parameter = DECL_INCOMING_RTL (decl);
15297 enum machine_mode mode = GET_MODE (parameter);
15299 if (GET_CODE (parameter) == REG)
15301 if (SCALAR_FLOAT_MODE_P (mode))
15319 gcc_unreachable ();
15322 /* If only one bit will fit, don't or in this entry. */
15323 if (next_parm_info_bit > 0)
15324 parm_info |= (bits << (next_parm_info_bit - 1));
15325 next_parm_info_bit -= 2;
15329 fixed_parms += ((GET_MODE_SIZE (mode)
15330 + (UNITS_PER_WORD - 1))
15332 next_parm_info_bit -= 1;
15338 /* Number of fixed point parameters. */
15339 /* This is actually the number of words of fixed point parameters; thus
15340 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15341 fprintf (file, "%d,", fixed_parms);
15343 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15345 /* This is actually the number of fp registers that hold parameters;
15346 and thus the maximum value is 13. */
15347 /* Set parameters on stack bit if parameters are not in their original
15348 registers, regardless of whether they are on the stack? Xlc
15349 seems to set the bit when not optimizing. */
15350 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15352 if (! optional_tbtab)
15355 /* Optional fields follow. Some are variable length. */
15357 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15358 11 double float. */
15359 /* There is an entry for each parameter in a register, in the order that
15360 they occur in the parameter list. Any intervening arguments on the
15361 stack are ignored. If the list overflows a long (max possible length
15362 34 bits) then completely leave off all elements that don't fit. */
15363 /* Only emit this long if there was at least one parameter. */
15364 if (fixed_parms || float_parms)
15365 fprintf (file, "\t.long %d\n", parm_info);
15367 /* Offset from start of code to tb table. */
15368 fputs ("\t.long ", file);
15369 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15371 RS6000_OUTPUT_BASENAME (file, fname);
15373 assemble_name (file, fname);
15375 rs6000_output_function_entry (file, fname);
15378 /* Interrupt handler mask. */
15379 /* Omit this long, since we never set the interrupt handler bit
15382 /* Number of CTL (controlled storage) anchors. */
15383 /* Omit this long, since the has_ctl bit is never set above. */
15385 /* Displacement into stack of each CTL anchor. */
15386 /* Omit this list of longs, because there are no CTL anchors. */
15388 /* Length of function name. */
15391 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15393 /* Function name. */
15394 assemble_string (fname, strlen (fname));
15396 /* Register for alloca automatic storage; this is always reg 31.
15397 Only emit this if the alloca bit was set above. */
15398 if (frame_pointer_needed)
15399 fputs ("\t.byte 31\n", file);
15401 fputs ("\t.align 2\n", file);
15405 /* A C compound statement that outputs the assembler code for a thunk
15406 function, used to implement C++ virtual function calls with
15407 multiple inheritance. The thunk acts as a wrapper around a virtual
15408 function, adjusting the implicit object parameter before handing
15409 control off to the real function.
15411 First, emit code to add the integer DELTA to the location that
15412 contains the incoming first argument. Assume that this argument
15413 contains a pointer, and is the one used to pass the `this' pointer
15414 in C++. This is the incoming argument *before* the function
15415 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15416 values of all other incoming arguments.
15418 After the addition, emit code to jump to FUNCTION, which is a
15419 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15420 not touch the return address. Hence returning from FUNCTION will
15421 return to whoever called the current `thunk'.
15423 The effect must be as if FUNCTION had been called directly with the
15424 adjusted first argument. This macro is responsible for emitting
15425 all of the code for a thunk function; output_function_prologue()
15426 and output_function_epilogue() are not invoked.
15428 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15429 been extracted from it.) It might possibly be useful on some
15430 targets, but probably not.
15432 If you do not define this macro, the target-independent code in the
15433 C++ frontend will generate a less efficient heavyweight thunk that
15434 calls FUNCTION instead of jumping to it. The generic approach does
15435 not support varargs. */
15438 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15439 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15442 rtx this, insn, funexp;
15444 reload_completed = 1;
15445 epilogue_completed = 1;
15446 no_new_pseudos = 1;
15447 reset_block_changes ();
15449 /* Mark the end of the (empty) prologue. */
15450 emit_note (NOTE_INSN_PROLOGUE_END);
15452 /* Find the "this" pointer. If the function returns a structure,
15453 the structure return pointer is in r3. */
15454 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15455 this = gen_rtx_REG (Pmode, 4);
15457 this = gen_rtx_REG (Pmode, 3);
15459 /* Apply the constant offset, if required. */
15462 rtx delta_rtx = GEN_INT (delta);
15463 emit_insn (TARGET_32BIT
15464 ? gen_addsi3 (this, this, delta_rtx)
15465 : gen_adddi3 (this, this, delta_rtx));
15468 /* Apply the offset from the vtable, if required. */
15471 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15472 rtx tmp = gen_rtx_REG (Pmode, 12);
15474 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15475 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15477 emit_insn (TARGET_32BIT
15478 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15479 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15480 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15484 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15486 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15488 emit_insn (TARGET_32BIT
15489 ? gen_addsi3 (this, this, tmp)
15490 : gen_adddi3 (this, this, tmp));
15493 /* Generate a tail call to the target function. */
15494 if (!TREE_USED (function))
15496 assemble_external (function);
15497 TREE_USED (function) = 1;
15499 funexp = XEXP (DECL_RTL (function), 0);
15500 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15503 if (MACHOPIC_INDIRECT)
15504 funexp = machopic_indirect_call_target (funexp);
15507 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15508 generate sibcall RTL explicitly. */
15509 insn = emit_call_insn (
15510 gen_rtx_PARALLEL (VOIDmode,
15512 gen_rtx_CALL (VOIDmode,
15513 funexp, const0_rtx),
15514 gen_rtx_USE (VOIDmode, const0_rtx),
15515 gen_rtx_USE (VOIDmode,
15516 gen_rtx_REG (SImode,
15517 LINK_REGISTER_REGNUM)),
15518 gen_rtx_RETURN (VOIDmode))));
15519 SIBLING_CALL_P (insn) = 1;
15522 /* Run just enough of rest_of_compilation to get the insns emitted.
15523 There's not really enough bulk here to make other passes such as
15524 instruction scheduling worth while. Note that use_thunk calls
15525 assemble_start_function and assemble_end_function. */
15526 insn = get_insns ();
15527 insn_locators_initialize ();
15528 shorten_branches (insn);
15529 final_start_function (insn, file, 1);
15530 final (insn, file, 1);
15531 final_end_function ();
15533 reload_completed = 0;
15534 epilogue_completed = 0;
15535 no_new_pseudos = 0;
15538 /* A quick summary of the various types of 'constant-pool tables'
15541 Target Flags Name One table per
15542 AIX (none) AIX TOC object file
15543 AIX -mfull-toc AIX TOC object file
15544 AIX -mminimal-toc AIX minimal TOC translation unit
15545 SVR4/EABI (none) SVR4 SDATA object file
15546 SVR4/EABI -fpic SVR4 pic object file
15547 SVR4/EABI -fPIC SVR4 PIC translation unit
15548 SVR4/EABI -mrelocatable EABI TOC function
15549 SVR4/EABI -maix AIX TOC object file
15550 SVR4/EABI -maix -mminimal-toc
15551 AIX minimal TOC translation unit
15553 Name Reg. Set by entries contains:
15554 made by addrs? fp? sum?
15556 AIX TOC 2 crt0 as Y option option
15557 AIX minimal TOC 30 prolog gcc Y Y option
15558 SVR4 SDATA 13 crt0 gcc N Y N
15559 SVR4 pic 30 prolog ld Y not yet N
15560 SVR4 PIC 30 prolog gcc Y option option
15561 EABI TOC 30 prolog gcc Y option option
15565 /* Hash functions for the hash table. */
15568 rs6000_hash_constant (rtx k)
15570 enum rtx_code code = GET_CODE (k);
15571 enum machine_mode mode = GET_MODE (k);
15572 unsigned result = (code << 3) ^ mode;
15573 const char *format;
15576 format = GET_RTX_FORMAT (code);
15577 flen = strlen (format);
15583 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15586 if (mode != VOIDmode)
15587 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15599 for (; fidx < flen; fidx++)
15600 switch (format[fidx])
15605 const char *str = XSTR (k, fidx);
15606 len = strlen (str);
15607 result = result * 613 + len;
15608 for (i = 0; i < len; i++)
15609 result = result * 613 + (unsigned) str[i];
15614 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15618 result = result * 613 + (unsigned) XINT (k, fidx);
15621 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15622 result = result * 613 + (unsigned) XWINT (k, fidx);
15626 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15627 result = result * 613 + (unsigned) (XWINT (k, fidx)
15634 gcc_unreachable ();
15641 toc_hash_function (const void *hash_entry)
15643 const struct toc_hash_struct *thc =
15644 (const struct toc_hash_struct *) hash_entry;
15645 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15648 /* Compare H1 and H2 for equivalence. */
15651 toc_hash_eq (const void *h1, const void *h2)
15653 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15654 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15656 if (((const struct toc_hash_struct *) h1)->key_mode
15657 != ((const struct toc_hash_struct *) h2)->key_mode)
15660 return rtx_equal_p (r1, r2);
15663 /* These are the names given by the C++ front-end to vtables, and
15664 vtable-like objects. Ideally, this logic should not be here;
15665 instead, there should be some programmatic way of inquiring as
15666 to whether or not an object is a vtable. */
15668 #define VTABLE_NAME_P(NAME) \
15669 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15670 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15671 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15672 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15673 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15676 rs6000_output_symbol_ref (FILE *file, rtx x)
15678 /* Currently C++ toc references to vtables can be emitted before it
15679 is decided whether the vtable is public or private. If this is
15680 the case, then the linker will eventually complain that there is
15681 a reference to an unknown section. Thus, for vtables only,
15682 we emit the TOC reference to reference the symbol and not the
15684 const char *name = XSTR (x, 0);
15686 if (VTABLE_NAME_P (name))
15688 RS6000_OUTPUT_BASENAME (file, name);
15691 assemble_name (file, name);
15694 /* Output a TOC entry. We derive the entry name from what is being
15698 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15701 const char *name = buf;
15702 const char *real_name;
15704 HOST_WIDE_INT offset = 0;
15706 gcc_assert (!TARGET_NO_TOC);
15708 /* When the linker won't eliminate them, don't output duplicate
15709 TOC entries (this happens on AIX if there is any kind of TOC,
15710 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15712 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15714 struct toc_hash_struct *h;
15717 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15718 time because GGC is not initialized at that point. */
15719 if (toc_hash_table == NULL)
15720 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15721 toc_hash_eq, NULL);
15723 h = ggc_alloc (sizeof (*h));
15725 h->key_mode = mode;
15726 h->labelno = labelno;
15728 found = htab_find_slot (toc_hash_table, h, 1);
15729 if (*found == NULL)
15731 else /* This is indeed a duplicate.
15732 Set this label equal to that label. */
15734 fputs ("\t.set ", file);
15735 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15736 fprintf (file, "%d,", labelno);
15737 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15738 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15744 /* If we're going to put a double constant in the TOC, make sure it's
15745 aligned properly when strict alignment is on. */
15746 if (GET_CODE (x) == CONST_DOUBLE
15747 && STRICT_ALIGNMENT
15748 && GET_MODE_BITSIZE (mode) >= 64
15749 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15750 ASM_OUTPUT_ALIGN (file, 3);
15753 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15755 /* Handle FP constants specially. Note that if we have a minimal
15756 TOC, things we put here aren't actually in the TOC, so we can allow
15758 if (GET_CODE (x) == CONST_DOUBLE &&
15759 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15761 REAL_VALUE_TYPE rv;
15764 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15765 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15766 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15768 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15772 if (TARGET_MINIMAL_TOC)
15773 fputs (DOUBLE_INT_ASM_OP, file);
15775 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15776 k[0] & 0xffffffff, k[1] & 0xffffffff,
15777 k[2] & 0xffffffff, k[3] & 0xffffffff);
15778 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15779 k[0] & 0xffffffff, k[1] & 0xffffffff,
15780 k[2] & 0xffffffff, k[3] & 0xffffffff);
15785 if (TARGET_MINIMAL_TOC)
15786 fputs ("\t.long ", file);
15788 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15789 k[0] & 0xffffffff, k[1] & 0xffffffff,
15790 k[2] & 0xffffffff, k[3] & 0xffffffff);
15791 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15792 k[0] & 0xffffffff, k[1] & 0xffffffff,
15793 k[2] & 0xffffffff, k[3] & 0xffffffff);
15797 else if (GET_CODE (x) == CONST_DOUBLE &&
15798 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
15800 REAL_VALUE_TYPE rv;
15803 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15805 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15806 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
15808 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15812 if (TARGET_MINIMAL_TOC)
15813 fputs (DOUBLE_INT_ASM_OP, file);
15815 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15816 k[0] & 0xffffffff, k[1] & 0xffffffff);
15817 fprintf (file, "0x%lx%08lx\n",
15818 k[0] & 0xffffffff, k[1] & 0xffffffff);
15823 if (TARGET_MINIMAL_TOC)
15824 fputs ("\t.long ", file);
15826 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15827 k[0] & 0xffffffff, k[1] & 0xffffffff);
15828 fprintf (file, "0x%lx,0x%lx\n",
15829 k[0] & 0xffffffff, k[1] & 0xffffffff);
15833 else if (GET_CODE (x) == CONST_DOUBLE &&
15834 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
15836 REAL_VALUE_TYPE rv;
15839 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15840 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15841 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
15843 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15847 if (TARGET_MINIMAL_TOC)
15848 fputs (DOUBLE_INT_ASM_OP, file);
15850 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15851 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15856 if (TARGET_MINIMAL_TOC)
15857 fputs ("\t.long ", file);
15859 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15860 fprintf (file, "0x%lx\n", l & 0xffffffff);
15864 else if (GET_MODE (x) == VOIDmode
15865 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15867 unsigned HOST_WIDE_INT low;
15868 HOST_WIDE_INT high;
15870 if (GET_CODE (x) == CONST_DOUBLE)
15872 low = CONST_DOUBLE_LOW (x);
15873 high = CONST_DOUBLE_HIGH (x);
15876 #if HOST_BITS_PER_WIDE_INT == 32
15879 high = (low & 0x80000000) ? ~0 : 0;
15883 low = INTVAL (x) & 0xffffffff;
15884 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15888 /* TOC entries are always Pmode-sized, but since this
15889 is a bigendian machine then if we're putting smaller
15890 integer constants in the TOC we have to pad them.
15891 (This is still a win over putting the constants in
15892 a separate constant pool, because then we'd have
15893 to have both a TOC entry _and_ the actual constant.)
15895 For a 32-bit target, CONST_INT values are loaded and shifted
15896 entirely within `low' and can be stored in one TOC entry. */
15898 /* It would be easy to make this work, but it doesn't now. */
15899 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15901 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15903 #if HOST_BITS_PER_WIDE_INT == 32
15904 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15905 POINTER_SIZE, &low, &high, 0);
15908 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15909 high = (HOST_WIDE_INT) low >> 32;
15916 if (TARGET_MINIMAL_TOC)
15917 fputs (DOUBLE_INT_ASM_OP, file);
15919 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15920 (long) high & 0xffffffff, (long) low & 0xffffffff);
15921 fprintf (file, "0x%lx%08lx\n",
15922 (long) high & 0xffffffff, (long) low & 0xffffffff);
15927 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15929 if (TARGET_MINIMAL_TOC)
15930 fputs ("\t.long ", file);
15932 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15933 (long) high & 0xffffffff, (long) low & 0xffffffff);
15934 fprintf (file, "0x%lx,0x%lx\n",
15935 (long) high & 0xffffffff, (long) low & 0xffffffff);
15939 if (TARGET_MINIMAL_TOC)
15940 fputs ("\t.long ", file);
15942 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15943 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15949 if (GET_CODE (x) == CONST)
15951 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15953 base = XEXP (XEXP (x, 0), 0);
15954 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15957 switch (GET_CODE (base))
15960 name = XSTR (base, 0);
15964 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15965 CODE_LABEL_NUMBER (XEXP (base, 0)));
15969 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15973 gcc_unreachable ();
15976 real_name = (*targetm.strip_name_encoding) (name);
15977 if (TARGET_MINIMAL_TOC)
15978 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15981 fprintf (file, "\t.tc %s", real_name);
15984 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
15986 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
15988 fputs ("[TC],", file);
15991 /* Currently C++ toc references to vtables can be emitted before it
15992 is decided whether the vtable is public or private. If this is
15993 the case, then the linker will eventually complain that there is
15994 a TOC reference to an unknown section. Thus, for vtables only,
15995 we emit the TOC reference to reference the symbol and not the
15997 if (VTABLE_NAME_P (name))
15999 RS6000_OUTPUT_BASENAME (file, name);
16001 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16002 else if (offset > 0)
16003 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16006 output_addr_const (file, x);
16010 /* Output an assembler pseudo-op to write an ASCII string of N characters
16011 starting at P to FILE.
16013 On the RS/6000, we have to do this using the .byte operation and
16014 write out special characters outside the quoted string.
16015 Also, the assembler is broken; very long strings are truncated,
16016 so we must artificially break them up early. */
16019 output_ascii (FILE *file, const char *p, int n)
16022 int i, count_string;
16023 const char *for_string = "\t.byte \"";
16024 const char *for_decimal = "\t.byte ";
16025 const char *to_close = NULL;
16028 for (i = 0; i < n; i++)
16031 if (c >= ' ' && c < 0177)
16034 fputs (for_string, file);
16037 /* Write two quotes to get one. */
16045 for_decimal = "\"\n\t.byte ";
16049 if (count_string >= 512)
16051 fputs (to_close, file);
16053 for_string = "\t.byte \"";
16054 for_decimal = "\t.byte ";
16062 fputs (for_decimal, file);
16063 fprintf (file, "%d", c);
16065 for_string = "\n\t.byte \"";
16066 for_decimal = ", ";
16072 /* Now close the string if we have written one. Then end the line. */
16074 fputs (to_close, file);
16077 /* Generate a unique section name for FILENAME for a section type
16078 represented by SECTION_DESC. Output goes into BUF.
16080 SECTION_DESC can be any string, as long as it is different for each
16081 possible section type.
16083 We name the section in the same manner as xlc. The name begins with an
16084 underscore followed by the filename (after stripping any leading directory
16085 names) with the last period replaced by the string SECTION_DESC. If
16086 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16090 rs6000_gen_section_name (char **buf, const char *filename,
16091 const char *section_desc)
16093 const char *q, *after_last_slash, *last_period = 0;
16097 after_last_slash = filename;
16098 for (q = filename; *q; q++)
16101 after_last_slash = q + 1;
16102 else if (*q == '.')
16106 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16107 *buf = (char *) xmalloc (len);
16112 for (q = after_last_slash; *q; q++)
16114 if (q == last_period)
16116 strcpy (p, section_desc);
16117 p += strlen (section_desc);
16121 else if (ISALNUM (*q))
16125 if (last_period == 0)
16126 strcpy (p, section_desc);
16131 /* Emit profile function. */
16134 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16136 /* Non-standard profiling for kernels, which just saves LR then calls
16137 _mcount without worrying about arg saves. The idea is to change
16138 the function prologue as little as possible as it isn't easy to
16139 account for arg save/restore code added just for _mcount. */
16140 if (TARGET_PROFILE_KERNEL)
16143 if (DEFAULT_ABI == ABI_AIX)
16145 #ifndef NO_PROFILE_COUNTERS
16146 # define NO_PROFILE_COUNTERS 0
16148 if (NO_PROFILE_COUNTERS)
16149 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16153 const char *label_name;
16156 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16157 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16158 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16160 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16164 else if (DEFAULT_ABI == ABI_DARWIN)
16166 const char *mcount_name = RS6000_MCOUNT;
16167 int caller_addr_regno = LINK_REGISTER_REGNUM;
16169 /* Be conservative and always set this, at least for now. */
16170 current_function_uses_pic_offset_table = 1;
16173 /* For PIC code, set up a stub and collect the caller's address
16174 from r0, which is where the prologue puts it. */
16175 if (MACHOPIC_INDIRECT
16176 && current_function_uses_pic_offset_table)
16177 caller_addr_regno = 0;
16179 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16181 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16185 /* Write function profiler code. */
16188 output_function_profiler (FILE *file, int labelno)
16192 switch (DEFAULT_ABI)
16195 gcc_unreachable ();
16200 warning (0, "no profiling of 64-bit code for this ABI");
16203 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16204 fprintf (file, "\tmflr %s\n", reg_names[0]);
16205 if (NO_PROFILE_COUNTERS)
16207 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16208 reg_names[0], reg_names[1]);
16210 else if (TARGET_SECURE_PLT && flag_pic)
16212 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16213 reg_names[0], reg_names[1]);
16214 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16215 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16216 reg_names[12], reg_names[12]);
16217 assemble_name (file, buf);
16218 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16219 assemble_name (file, buf);
16220 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16222 else if (flag_pic == 1)
16224 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16225 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16226 reg_names[0], reg_names[1]);
16227 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16228 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16229 assemble_name (file, buf);
16230 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16232 else if (flag_pic > 1)
16234 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16235 reg_names[0], reg_names[1]);
16236 /* Now, we need to get the address of the label. */
16237 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16238 assemble_name (file, buf);
16239 fputs ("-.\n1:", file);
16240 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16241 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16242 reg_names[0], reg_names[11]);
16243 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16244 reg_names[0], reg_names[0], reg_names[11]);
16248 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16249 assemble_name (file, buf);
16250 fputs ("@ha\n", file);
16251 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16252 reg_names[0], reg_names[1]);
16253 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16254 assemble_name (file, buf);
16255 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16258 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16259 fprintf (file, "\tbl %s%s\n",
16260 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16265 if (!TARGET_PROFILE_KERNEL)
16267 /* Don't do anything, done in output_profile_hook (). */
16271 gcc_assert (!TARGET_32BIT);
16273 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16274 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16276 if (cfun->static_chain_decl != NULL)
16278 asm_fprintf (file, "\tstd %s,24(%s)\n",
16279 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16280 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16281 asm_fprintf (file, "\tld %s,24(%s)\n",
16282 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16285 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16292 /* Power4 load update and store update instructions are cracked into a
16293 load or store and an integer insn which are executed in the same cycle.
16294 Branches have their own dispatch slot which does not count against the
16295 GCC issue rate, but it changes the program flow so there are no other
16296 instructions to issue in this cycle. */
16299 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16300 int verbose ATTRIBUTE_UNUSED,
16301 rtx insn, int more)
16303 if (GET_CODE (PATTERN (insn)) == USE
16304 || GET_CODE (PATTERN (insn)) == CLOBBER)
16307 if (rs6000_sched_groups)
16309 if (is_microcoded_insn (insn))
16311 else if (is_cracked_insn (insn))
16312 return more > 2 ? more - 2 : 0;
16318 /* Adjust the cost of a scheduling dependency. Return the new cost of
16319 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16322 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16324 if (! recog_memoized (insn))
16327 if (REG_NOTE_KIND (link) != 0)
16330 if (REG_NOTE_KIND (link) == 0)
16332 /* Data dependency; DEP_INSN writes a register that INSN reads
16333 some cycles later. */
16335 /* Separate a load from a narrower, dependent store. */
16336 if (rs6000_sched_groups
16337 && GET_CODE (PATTERN (insn)) == SET
16338 && GET_CODE (PATTERN (dep_insn)) == SET
16339 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16340 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16341 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16342 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16345 switch (get_attr_type (insn))
16348 /* Tell the first scheduling pass about the latency between
16349 a mtctr and bctr (and mtlr and br/blr). The first
16350 scheduling pass will not know about this latency since
16351 the mtctr instruction, which has the latency associated
16352 to it, will be generated by reload. */
16353 return TARGET_POWER ? 5 : 4;
16355 /* Leave some extra cycles between a compare and its
16356 dependent branch, to inhibit expensive mispredicts. */
16357 if ((rs6000_cpu_attr == CPU_PPC603
16358 || rs6000_cpu_attr == CPU_PPC604
16359 || rs6000_cpu_attr == CPU_PPC604E
16360 || rs6000_cpu_attr == CPU_PPC620
16361 || rs6000_cpu_attr == CPU_PPC630
16362 || rs6000_cpu_attr == CPU_PPC750
16363 || rs6000_cpu_attr == CPU_PPC7400
16364 || rs6000_cpu_attr == CPU_PPC7450
16365 || rs6000_cpu_attr == CPU_POWER4
16366 || rs6000_cpu_attr == CPU_POWER5)
16367 && recog_memoized (dep_insn)
16368 && (INSN_CODE (dep_insn) >= 0)
16369 && (get_attr_type (dep_insn) == TYPE_CMP
16370 || get_attr_type (dep_insn) == TYPE_COMPARE
16371 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16372 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16373 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16374 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16375 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16376 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16381 /* Fall out to return default cost. */
16387 /* The function returns a true if INSN is microcoded.
16388 Return false otherwise. */
16391 is_microcoded_insn (rtx insn)
16393 if (!insn || !INSN_P (insn)
16394 || GET_CODE (PATTERN (insn)) == USE
16395 || GET_CODE (PATTERN (insn)) == CLOBBER)
16398 if (rs6000_sched_groups)
16400 enum attr_type type = get_attr_type (insn);
16401 if (type == TYPE_LOAD_EXT_U
16402 || type == TYPE_LOAD_EXT_UX
16403 || type == TYPE_LOAD_UX
16404 || type == TYPE_STORE_UX
16405 || type == TYPE_MFCR)
16412 /* The function returns a nonzero value if INSN can be scheduled only
16413 as the first insn in a dispatch group ("dispatch-slot restricted").
16414 In this case, the returned value indicates how many dispatch slots
16415 the insn occupies (at the beginning of the group).
16416 Return 0 otherwise. */
16419 is_dispatch_slot_restricted (rtx insn)
16421 enum attr_type type;
16423 if (!rs6000_sched_groups)
16427 || insn == NULL_RTX
16428 || GET_CODE (insn) == NOTE
16429 || GET_CODE (PATTERN (insn)) == USE
16430 || GET_CODE (PATTERN (insn)) == CLOBBER)
16433 type = get_attr_type (insn);
16440 case TYPE_DELAYED_CR:
16441 case TYPE_CR_LOGICAL:
16454 if (rs6000_cpu == PROCESSOR_POWER5
16455 && is_cracked_insn (insn))
16461 /* The function returns true if INSN is cracked into 2 instructions
16462 by the processor (and therefore occupies 2 issue slots). */
16465 is_cracked_insn (rtx insn)
16467 if (!insn || !INSN_P (insn)
16468 || GET_CODE (PATTERN (insn)) == USE
16469 || GET_CODE (PATTERN (insn)) == CLOBBER)
16472 if (rs6000_sched_groups)
16474 enum attr_type type = get_attr_type (insn);
16475 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16476 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16477 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16478 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16479 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16480 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16481 || type == TYPE_IDIV || type == TYPE_LDIV
16482 || type == TYPE_INSERT_WORD)
16489 /* The function returns true if INSN can be issued only from
16490 the branch slot. */
16493 is_branch_slot_insn (rtx insn)
16495 if (!insn || !INSN_P (insn)
16496 || GET_CODE (PATTERN (insn)) == USE
16497 || GET_CODE (PATTERN (insn)) == CLOBBER)
16500 if (rs6000_sched_groups)
16502 enum attr_type type = get_attr_type (insn);
16503 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16511 /* A C statement (sans semicolon) to update the integer scheduling
16512 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16513 INSN earlier, reduce the priority to execute INSN later. Do not
16514 define this macro if you do not need to adjust the scheduling
16515 priorities of insns. */
16518 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16520 /* On machines (like the 750) which have asymmetric integer units,
16521 where one integer unit can do multiply and divides and the other
16522 can't, reduce the priority of multiply/divide so it is scheduled
16523 before other integer operations. */
16526 if (! INSN_P (insn))
16529 if (GET_CODE (PATTERN (insn)) == USE)
16532 switch (rs6000_cpu_attr) {
16534 switch (get_attr_type (insn))
16541 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16542 priority, priority);
16543 if (priority >= 0 && priority < 0x01000000)
16550 if (is_dispatch_slot_restricted (insn)
16551 && reload_completed
16552 && current_sched_info->sched_max_insns_priority
16553 && rs6000_sched_restricted_insns_priority)
16556 /* Prioritize insns that can be dispatched only in the first
16558 if (rs6000_sched_restricted_insns_priority == 1)
16559 /* Attach highest priority to insn. This means that in
16560 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16561 precede 'priority' (critical path) considerations. */
16562 return current_sched_info->sched_max_insns_priority;
16563 else if (rs6000_sched_restricted_insns_priority == 2)
16564 /* Increase priority of insn by a minimal amount. This means that in
16565 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16566 considerations precede dispatch-slot restriction considerations. */
16567 return (priority + 1);
16573 /* Return how many instructions the machine can issue per cycle. */
16576 rs6000_issue_rate (void)
16578 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16579 if (!reload_completed)
16582 switch (rs6000_cpu_attr) {
16583 case CPU_RIOS1: /* ? */
16585 case CPU_PPC601: /* ? */
16608 /* Return how many instructions to look ahead for better insn
16612 rs6000_use_sched_lookahead (void)
16614 if (rs6000_cpu_attr == CPU_PPC8540)
16619 /* Determine is PAT refers to memory. */
16622 is_mem_ref (rtx pat)
16628 if (GET_CODE (pat) == MEM)
16631 /* Recursively process the pattern. */
16632 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16634 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16637 ret |= is_mem_ref (XEXP (pat, i));
16638 else if (fmt[i] == 'E')
16639 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16640 ret |= is_mem_ref (XVECEXP (pat, i, j));
16646 /* Determine if PAT is a PATTERN of a load insn. */
16649 is_load_insn1 (rtx pat)
16651 if (!pat || pat == NULL_RTX)
16654 if (GET_CODE (pat) == SET)
16655 return is_mem_ref (SET_SRC (pat));
16657 if (GET_CODE (pat) == PARALLEL)
16661 for (i = 0; i < XVECLEN (pat, 0); i++)
16662 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16669 /* Determine if INSN loads from memory. */
16672 is_load_insn (rtx insn)
16674 if (!insn || !INSN_P (insn))
16677 if (GET_CODE (insn) == CALL_INSN)
16680 return is_load_insn1 (PATTERN (insn));
16683 /* Determine if PAT is a PATTERN of a store insn. */
16686 is_store_insn1 (rtx pat)
16688 if (!pat || pat == NULL_RTX)
16691 if (GET_CODE (pat) == SET)
16692 return is_mem_ref (SET_DEST (pat));
16694 if (GET_CODE (pat) == PARALLEL)
16698 for (i = 0; i < XVECLEN (pat, 0); i++)
16699 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16706 /* Determine if INSN stores to memory. */
16709 is_store_insn (rtx insn)
16711 if (!insn || !INSN_P (insn))
16714 return is_store_insn1 (PATTERN (insn));
16717 /* Returns whether the dependence between INSN and NEXT is considered
16718 costly by the given target. */
16721 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16724 /* If the flag is not enabled - no dependence is considered costly;
16725 allow all dependent insns in the same group.
16726 This is the most aggressive option. */
16727 if (rs6000_sched_costly_dep == no_dep_costly)
16730 /* If the flag is set to 1 - a dependence is always considered costly;
16731 do not allow dependent instructions in the same group.
16732 This is the most conservative option. */
16733 if (rs6000_sched_costly_dep == all_deps_costly)
16736 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16737 && is_load_insn (next)
16738 && is_store_insn (insn))
16739 /* Prevent load after store in the same group. */
16742 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16743 && is_load_insn (next)
16744 && is_store_insn (insn)
16745 && (!link || (int) REG_NOTE_KIND (link) == 0))
16746 /* Prevent load after store in the same group if it is a true
16750 /* The flag is set to X; dependences with latency >= X are considered costly,
16751 and will not be scheduled in the same group. */
16752 if (rs6000_sched_costly_dep <= max_dep_latency
16753 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16759 /* Return the next insn after INSN that is found before TAIL is reached,
16760 skipping any "non-active" insns - insns that will not actually occupy
16761 an issue slot. Return NULL_RTX if such an insn is not found. */
16764 get_next_active_insn (rtx insn, rtx tail)
16766 if (insn == NULL_RTX || insn == tail)
16771 insn = NEXT_INSN (insn);
16772 if (insn == NULL_RTX || insn == tail)
16777 || (NONJUMP_INSN_P (insn)
16778 && GET_CODE (PATTERN (insn)) != USE
16779 && GET_CODE (PATTERN (insn)) != CLOBBER
16780 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16786 /* Return whether the presence of INSN causes a dispatch group termination
16787 of group WHICH_GROUP.
16789 If WHICH_GROUP == current_group, this function will return true if INSN
16790 causes the termination of the current group (i.e, the dispatch group to
16791 which INSN belongs). This means that INSN will be the last insn in the
16792 group it belongs to.
16794 If WHICH_GROUP == previous_group, this function will return true if INSN
16795 causes the termination of the previous group (i.e, the dispatch group that
16796 precedes the group to which INSN belongs). This means that INSN will be
16797 the first insn in the group it belongs to). */
16800 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16802 enum attr_type type;
16807 type = get_attr_type (insn);
16809 if (is_microcoded_insn (insn))
16812 if (which_group == current_group)
16814 if (is_branch_slot_insn (insn))
16818 else if (which_group == previous_group)
16820 if (is_dispatch_slot_restricted (insn))
16828 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16829 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16832 is_costly_group (rtx *group_insns, rtx next_insn)
16837 int issue_rate = rs6000_issue_rate ();
16839 for (i = 0; i < issue_rate; i++)
16841 rtx insn = group_insns[i];
16844 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16846 rtx next = XEXP (link, 0);
16847 if (next == next_insn)
16849 cost = insn_cost (insn, link, next_insn);
16850 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16859 /* Utility of the function redefine_groups.
16860 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16861 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16862 to keep it "far" (in a separate group) from GROUP_INSNS, following
16863 one of the following schemes, depending on the value of the flag
16864 -minsert_sched_nops = X:
16865 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16866 in order to force NEXT_INSN into a separate group.
16867 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16868 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16869 insertion (has a group just ended, how many vacant issue slots remain in the
16870 last group, and how many dispatch groups were encountered so far). */
16873 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16874 rtx next_insn, bool *group_end, int can_issue_more,
16879 int issue_rate = rs6000_issue_rate ();
16880 bool end = *group_end;
16883 if (next_insn == NULL_RTX)
16884 return can_issue_more;
16886 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16887 return can_issue_more;
16889 force = is_costly_group (group_insns, next_insn);
16891 return can_issue_more;
16893 if (sched_verbose > 6)
16894 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16895 *group_count ,can_issue_more);
16897 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16900 can_issue_more = 0;
16902 /* Since only a branch can be issued in the last issue_slot, it is
16903 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16904 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16905 in this case the last nop will start a new group and the branch
16906 will be forced to the new group. */
16907 if (can_issue_more && !is_branch_slot_insn (next_insn))
16910 while (can_issue_more > 0)
16913 emit_insn_before (nop, next_insn);
16921 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16923 int n_nops = rs6000_sched_insert_nops;
16925 /* Nops can't be issued from the branch slot, so the effective
16926 issue_rate for nops is 'issue_rate - 1'. */
16927 if (can_issue_more == 0)
16928 can_issue_more = issue_rate;
16930 if (can_issue_more == 0)
16932 can_issue_more = issue_rate - 1;
16935 for (i = 0; i < issue_rate; i++)
16937 group_insns[i] = 0;
16944 emit_insn_before (nop, next_insn);
16945 if (can_issue_more == issue_rate - 1) /* new group begins */
16948 if (can_issue_more == 0)
16950 can_issue_more = issue_rate - 1;
16953 for (i = 0; i < issue_rate; i++)
16955 group_insns[i] = 0;
16961 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16964 /* Is next_insn going to start a new group? */
16967 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16968 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16969 || (can_issue_more < issue_rate &&
16970 insn_terminates_group_p (next_insn, previous_group)));
16971 if (*group_end && end)
16974 if (sched_verbose > 6)
16975 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16976 *group_count, can_issue_more);
16977 return can_issue_more;
16980 return can_issue_more;
16983 /* This function tries to synch the dispatch groups that the compiler "sees"
16984 with the dispatch groups that the processor dispatcher is expected to
16985 form in practice. It tries to achieve this synchronization by forcing the
16986 estimated processor grouping on the compiler (as opposed to the function
16987 'pad_goups' which tries to force the scheduler's grouping on the processor).
16989 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16990 examines the (estimated) dispatch groups that will be formed by the processor
16991 dispatcher. It marks these group boundaries to reflect the estimated
16992 processor grouping, overriding the grouping that the scheduler had marked.
16993 Depending on the value of the flag '-minsert-sched-nops' this function can
16994 force certain insns into separate groups or force a certain distance between
16995 them by inserting nops, for example, if there exists a "costly dependence"
16998 The function estimates the group boundaries that the processor will form as
16999 follows: It keeps track of how many vacant issue slots are available after
17000 each insn. A subsequent insn will start a new group if one of the following
17002 - no more vacant issue slots remain in the current dispatch group.
17003 - only the last issue slot, which is the branch slot, is vacant, but the next
17004 insn is not a branch.
17005 - only the last 2 or less issue slots, including the branch slot, are vacant,
17006 which means that a cracked insn (which occupies two issue slots) can't be
17007 issued in this group.
17008 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17009 start a new group. */
17012 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17014 rtx insn, next_insn;
17016 int can_issue_more;
17019 int group_count = 0;
17023 issue_rate = rs6000_issue_rate ();
17024 group_insns = alloca (issue_rate * sizeof (rtx));
17025 for (i = 0; i < issue_rate; i++)
17027 group_insns[i] = 0;
17029 can_issue_more = issue_rate;
17031 insn = get_next_active_insn (prev_head_insn, tail);
17034 while (insn != NULL_RTX)
17036 slot = (issue_rate - can_issue_more);
17037 group_insns[slot] = insn;
17039 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17040 if (insn_terminates_group_p (insn, current_group))
17041 can_issue_more = 0;
17043 next_insn = get_next_active_insn (insn, tail);
17044 if (next_insn == NULL_RTX)
17045 return group_count + 1;
17047 /* Is next_insn going to start a new group? */
17049 = (can_issue_more == 0
17050 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17051 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17052 || (can_issue_more < issue_rate &&
17053 insn_terminates_group_p (next_insn, previous_group)));
17055 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17056 next_insn, &group_end, can_issue_more,
17062 can_issue_more = 0;
17063 for (i = 0; i < issue_rate; i++)
17065 group_insns[i] = 0;
17069 if (GET_MODE (next_insn) == TImode && can_issue_more)
17070 PUT_MODE (next_insn, VOIDmode);
17071 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17072 PUT_MODE (next_insn, TImode);
17075 if (can_issue_more == 0)
17076 can_issue_more = issue_rate;
17079 return group_count;
17082 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17083 dispatch group boundaries that the scheduler had marked. Pad with nops
17084 any dispatch groups which have vacant issue slots, in order to force the
17085 scheduler's grouping on the processor dispatcher. The function
17086 returns the number of dispatch groups found. */
17089 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17091 rtx insn, next_insn;
17094 int can_issue_more;
17096 int group_count = 0;
17098 /* Initialize issue_rate. */
17099 issue_rate = rs6000_issue_rate ();
17100 can_issue_more = issue_rate;
17102 insn = get_next_active_insn (prev_head_insn, tail);
17103 next_insn = get_next_active_insn (insn, tail);
17105 while (insn != NULL_RTX)
17108 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17110 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17112 if (next_insn == NULL_RTX)
17117 /* If the scheduler had marked group termination at this location
17118 (between insn and next_indn), and neither insn nor next_insn will
17119 force group termination, pad the group with nops to force group
17122 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17123 && !insn_terminates_group_p (insn, current_group)
17124 && !insn_terminates_group_p (next_insn, previous_group))
17126 if (!is_branch_slot_insn (next_insn))
17129 while (can_issue_more)
17132 emit_insn_before (nop, next_insn);
17137 can_issue_more = issue_rate;
17142 next_insn = get_next_active_insn (insn, tail);
17145 return group_count;
17148 /* The following function is called at the end of scheduling BB.
17149 After reload, it inserts nops at insn group bundling. */
17152 rs6000_sched_finish (FILE *dump, int sched_verbose)
17157 fprintf (dump, "=== Finishing schedule.\n");
17159 if (reload_completed && rs6000_sched_groups)
17161 if (rs6000_sched_insert_nops == sched_finish_none)
17164 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17165 n_groups = pad_groups (dump, sched_verbose,
17166 current_sched_info->prev_head,
17167 current_sched_info->next_tail);
17169 n_groups = redefine_groups (dump, sched_verbose,
17170 current_sched_info->prev_head,
17171 current_sched_info->next_tail);
17173 if (sched_verbose >= 6)
17175 fprintf (dump, "ngroups = %d\n", n_groups);
17176 print_rtl (dump, current_sched_info->prev_head);
17177 fprintf (dump, "Done finish_sched\n");
17182 /* Length in units of the trampoline for entering a nested function. */
17185 rs6000_trampoline_size (void)
17189 switch (DEFAULT_ABI)
17192 gcc_unreachable ();
17195 ret = (TARGET_32BIT) ? 12 : 24;
17200 ret = (TARGET_32BIT) ? 40 : 48;
17207 /* Emit RTL insns to initialize the variable parts of a trampoline.
17208 FNADDR is an RTX for the address of the function's pure code.
17209 CXT is an RTX for the static chain value for the function. */
17212 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17214 enum machine_mode pmode = Pmode;
17215 int regsize = (TARGET_32BIT) ? 4 : 8;
17216 rtx ctx_reg = force_reg (pmode, cxt);
17218 switch (DEFAULT_ABI)
17221 gcc_unreachable ();
17223 /* Macros to shorten the code expansions below. */
17224 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17225 #define MEM_PLUS(addr,offset) \
17226 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17228 /* Under AIX, just build the 3 word function descriptor */
17231 rtx fn_reg = gen_reg_rtx (pmode);
17232 rtx toc_reg = gen_reg_rtx (pmode);
17233 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17234 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17235 emit_move_insn (MEM_DEREF (addr), fn_reg);
17236 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17237 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17241 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17244 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17245 FALSE, VOIDmode, 4,
17247 GEN_INT (rs6000_trampoline_size ()), SImode,
17257 /* Table of valid machine attributes. */
17259 const struct attribute_spec rs6000_attribute_table[] =
17261 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17262 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17263 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17264 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17265 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17266 SUBTARGET_ATTRIBUTE_TABLE,
17268 { NULL, 0, 0, false, false, false, NULL }
17271 /* Handle the "altivec" attribute. The attribute may have
17272 arguments as follows:
17274 __attribute__((altivec(vector__)))
17275 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17276 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17278 and may appear more than once (e.g., 'vector bool char') in a
17279 given declaration. */
17282 rs6000_handle_altivec_attribute (tree *node,
17283 tree name ATTRIBUTE_UNUSED,
17285 int flags ATTRIBUTE_UNUSED,
17286 bool *no_add_attrs)
17288 tree type = *node, result = NULL_TREE;
17289 enum machine_mode mode;
17292 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17293 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17294 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17297 while (POINTER_TYPE_P (type)
17298 || TREE_CODE (type) == FUNCTION_TYPE
17299 || TREE_CODE (type) == METHOD_TYPE
17300 || TREE_CODE (type) == ARRAY_TYPE)
17301 type = TREE_TYPE (type);
17303 mode = TYPE_MODE (type);
17305 /* Check for invalid AltiVec type qualifiers. */
17306 if (type == long_unsigned_type_node || type == long_integer_type_node)
17309 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17310 else if (rs6000_warn_altivec_long)
17311 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17313 else if (type == long_long_unsigned_type_node
17314 || type == long_long_integer_type_node)
17315 error ("use of %<long long%> in AltiVec types is invalid");
17316 else if (type == double_type_node)
17317 error ("use of %<double%> in AltiVec types is invalid");
17318 else if (type == long_double_type_node)
17319 error ("use of %<long double%> in AltiVec types is invalid");
17320 else if (type == boolean_type_node)
17321 error ("use of boolean types in AltiVec types is invalid");
17322 else if (TREE_CODE (type) == COMPLEX_TYPE)
17323 error ("use of %<complex%> in AltiVec types is invalid");
17324 else if (DECIMAL_FLOAT_MODE_P (mode))
17325 error ("use of decimal floating point types in AltiVec types is invalid");
17327 switch (altivec_type)
17330 unsigned_p = TYPE_UNSIGNED (type);
17334 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17337 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17340 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17342 case SFmode: result = V4SF_type_node; break;
17343 /* If the user says 'vector int bool', we may be handed the 'bool'
17344 attribute _before_ the 'vector' attribute, and so select the
17345 proper type in the 'b' case below. */
17346 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17354 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17355 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17356 case QImode: case V16QImode: result = bool_V16QI_type_node;
17363 case V8HImode: result = pixel_V8HI_type_node;
17369 if (result && result != type && TYPE_READONLY (type))
17370 result = build_qualified_type (result, TYPE_QUAL_CONST);
17372 *no_add_attrs = true; /* No need to hang on to the attribute. */
17375 *node = reconstruct_complex_type (*node, result);
17380 /* AltiVec defines four built-in scalar types that serve as vector
17381 elements; we must teach the compiler how to mangle them. */
17383 static const char *
17384 rs6000_mangle_fundamental_type (tree type)
17386 if (type == bool_char_type_node) return "U6__boolc";
17387 if (type == bool_short_type_node) return "U6__bools";
17388 if (type == pixel_type_node) return "u7__pixel";
17389 if (type == bool_int_type_node) return "U6__booli";
17391 /* For all other types, use normal C++ mangling. */
17395 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17396 struct attribute_spec.handler. */
17399 rs6000_handle_longcall_attribute (tree *node, tree name,
17400 tree args ATTRIBUTE_UNUSED,
17401 int flags ATTRIBUTE_UNUSED,
17402 bool *no_add_attrs)
17404 if (TREE_CODE (*node) != FUNCTION_TYPE
17405 && TREE_CODE (*node) != FIELD_DECL
17406 && TREE_CODE (*node) != TYPE_DECL)
17408 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17409 IDENTIFIER_POINTER (name));
17410 *no_add_attrs = true;
17416 /* Set longcall attributes on all functions declared when
17417 rs6000_default_long_calls is true. */
17419 rs6000_set_default_type_attributes (tree type)
17421 if (rs6000_default_long_calls
17422 && (TREE_CODE (type) == FUNCTION_TYPE
17423 || TREE_CODE (type) == METHOD_TYPE))
17424 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17426 TYPE_ATTRIBUTES (type));
17429 /* Return a reference suitable for calling a function with the
17430 longcall attribute. */
17433 rs6000_longcall_ref (rtx call_ref)
17435 const char *call_name;
17438 if (GET_CODE (call_ref) != SYMBOL_REF)
17441 /* System V adds '.' to the internal name, so skip them. */
17442 call_name = XSTR (call_ref, 0);
17443 if (*call_name == '.')
17445 while (*call_name == '.')
17448 node = get_identifier (call_name);
17449 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17452 return force_reg (Pmode, call_ref);
17455 #ifdef USING_ELFOS_H
17457 /* A get_unnamed_section callback, used for switching to toc_section. */
17460 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17462 if (DEFAULT_ABI == ABI_AIX
17463 && TARGET_MINIMAL_TOC
17464 && !TARGET_RELOCATABLE)
17466 if (!toc_initialized)
17468 toc_initialized = 1;
17469 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17470 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17471 fprintf (asm_out_file, "\t.tc ");
17472 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17473 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17474 fprintf (asm_out_file, "\n");
17476 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17477 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17478 fprintf (asm_out_file, " = .+32768\n");
17481 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17483 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17484 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17487 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17488 if (!toc_initialized)
17490 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17491 fprintf (asm_out_file, " = .+32768\n");
17492 toc_initialized = 1;
17497 /* Implement TARGET_ASM_INIT_SECTIONS. */
17500 rs6000_elf_asm_init_sections (void)
17503 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17506 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17507 SDATA2_SECTION_ASM_OP);
17510 /* Implement TARGET_SELECT_RTX_SECTION. */
17513 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17514 unsigned HOST_WIDE_INT align)
17516 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17517 return toc_section;
17519 return default_elf_select_rtx_section (mode, x, align);
17522 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17525 rs6000_elf_select_section (tree decl, int reloc,
17526 unsigned HOST_WIDE_INT align)
17528 /* Pretend that we're always building for a shared library when
17529 ABI_AIX, because otherwise we end up with dynamic relocations
17530 in read-only sections. This happens for function pointers,
17531 references to vtables in typeinfo, and probably other cases. */
17532 return default_elf_select_section_1 (decl, reloc, align,
17533 flag_pic || DEFAULT_ABI == ABI_AIX);
17536 /* A C statement to build up a unique section name, expressed as a
17537 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17538 RELOC indicates whether the initial value of EXP requires
17539 link-time relocations. If you do not define this macro, GCC will use
17540 the symbol name prefixed by `.' as the section name. Note - this
17541 macro can now be called for uninitialized data items as well as
17542 initialized data and functions. */
17545 rs6000_elf_unique_section (tree decl, int reloc)
17547 /* As above, pretend that we're always building for a shared library
17548 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17549 default_unique_section_1 (decl, reloc,
17550 flag_pic || DEFAULT_ABI == ABI_AIX);
17553 /* For a SYMBOL_REF, set generic flags and then perform some
17554 target-specific processing.
17556 When the AIX ABI is requested on a non-AIX system, replace the
17557 function name with the real name (with a leading .) rather than the
17558 function descriptor name. This saves a lot of overriding code to
17559 read the prefixes. */
17562 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17564 default_encode_section_info (decl, rtl, first);
17567 && TREE_CODE (decl) == FUNCTION_DECL
17569 && DEFAULT_ABI == ABI_AIX)
17571 rtx sym_ref = XEXP (rtl, 0);
17572 size_t len = strlen (XSTR (sym_ref, 0));
17573 char *str = alloca (len + 2);
17575 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17576 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17581 rs6000_elf_in_small_data_p (tree decl)
17583 if (rs6000_sdata == SDATA_NONE)
17586 /* We want to merge strings, so we never consider them small data. */
17587 if (TREE_CODE (decl) == STRING_CST)
17590 /* Functions are never in the small data area. */
17591 if (TREE_CODE (decl) == FUNCTION_DECL)
17594 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17596 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17597 if (strcmp (section, ".sdata") == 0
17598 || strcmp (section, ".sdata2") == 0
17599 || strcmp (section, ".sbss") == 0
17600 || strcmp (section, ".sbss2") == 0
17601 || strcmp (section, ".PPC.EMB.sdata0") == 0
17602 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17607 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17610 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17611 /* If it's not public, and we're not going to reference it there,
17612 there's no need to put it in the small data section. */
17613 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17620 #endif /* USING_ELFOS_H */
17623 /* Return a REG that occurs in ADDR with coefficient 1.
17624 ADDR can be effectively incremented by incrementing REG.
17626 r0 is special and we must not select it as an address
17627 register by this routine since our caller will try to
17628 increment the returned register via an "la" instruction. */
17631 find_addr_reg (rtx addr)
17633 while (GET_CODE (addr) == PLUS)
17635 if (GET_CODE (XEXP (addr, 0)) == REG
17636 && REGNO (XEXP (addr, 0)) != 0)
17637 addr = XEXP (addr, 0);
17638 else if (GET_CODE (XEXP (addr, 1)) == REG
17639 && REGNO (XEXP (addr, 1)) != 0)
17640 addr = XEXP (addr, 1);
17641 else if (CONSTANT_P (XEXP (addr, 0)))
17642 addr = XEXP (addr, 1);
17643 else if (CONSTANT_P (XEXP (addr, 1)))
17644 addr = XEXP (addr, 0);
17646 gcc_unreachable ();
17648 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17653 rs6000_fatal_bad_address (rtx op)
17655 fatal_insn ("bad address", op);
17660 static tree branch_island_list = 0;
17662 /* Remember to generate a branch island for far calls to the given
17666 add_compiler_branch_island (tree label_name, tree function_name,
17669 tree branch_island = build_tree_list (function_name, label_name);
17670 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17671 TREE_CHAIN (branch_island) = branch_island_list;
17672 branch_island_list = branch_island;
17675 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17676 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17677 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17678 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17680 /* Generate far-jump branch islands for everything on the
17681 branch_island_list. Invoked immediately after the last instruction
17682 of the epilogue has been emitted; the branch-islands must be
17683 appended to, and contiguous with, the function body. Mach-O stubs
17684 are generated in machopic_output_stub(). */
17687 macho_branch_islands (void)
17690 tree branch_island;
17692 for (branch_island = branch_island_list;
17694 branch_island = TREE_CHAIN (branch_island))
17696 const char *label =
17697 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17699 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17700 char name_buf[512];
17701 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17702 if (name[0] == '*' || name[0] == '&')
17703 strcpy (name_buf, name+1);
17707 strcpy (name_buf+1, name);
17709 strcpy (tmp_buf, "\n");
17710 strcat (tmp_buf, label);
17711 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17712 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17713 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17714 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17717 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17718 strcat (tmp_buf, label);
17719 strcat (tmp_buf, "_pic\n");
17720 strcat (tmp_buf, label);
17721 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17723 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17724 strcat (tmp_buf, name_buf);
17725 strcat (tmp_buf, " - ");
17726 strcat (tmp_buf, label);
17727 strcat (tmp_buf, "_pic)\n");
17729 strcat (tmp_buf, "\tmtlr r0\n");
17731 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17732 strcat (tmp_buf, name_buf);
17733 strcat (tmp_buf, " - ");
17734 strcat (tmp_buf, label);
17735 strcat (tmp_buf, "_pic)\n");
17737 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17741 strcat (tmp_buf, ":\nlis r12,hi16(");
17742 strcat (tmp_buf, name_buf);
17743 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17744 strcat (tmp_buf, name_buf);
17745 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17747 output_asm_insn (tmp_buf, 0);
17748 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17749 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17750 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17751 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17754 branch_island_list = 0;
17757 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17758 already there or not. */
17761 no_previous_def (tree function_name)
17763 tree branch_island;
17764 for (branch_island = branch_island_list;
17766 branch_island = TREE_CHAIN (branch_island))
17767 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17772 /* GET_PREV_LABEL gets the label name from the previous definition of
17776 get_prev_label (tree function_name)
17778 tree branch_island;
17779 for (branch_island = branch_island_list;
17781 branch_island = TREE_CHAIN (branch_island))
17782 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17783 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17787 /* INSN is either a function call or a millicode call. It may have an
17788 unconditional jump in its delay slot.
17790 CALL_DEST is the routine we are calling. */
17793 output_call (rtx insn, rtx *operands, int dest_operand_number,
17794 int cookie_operand_number)
17796 static char buf[256];
17797 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17798 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17801 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17803 if (no_previous_def (funname))
17805 int line_number = 0;
17806 rtx label_rtx = gen_label_rtx ();
17807 char *label_buf, temp_buf[256];
17808 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17809 CODE_LABEL_NUMBER (label_rtx));
17810 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17811 labelname = get_identifier (label_buf);
17812 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17814 line_number = NOTE_LINE_NUMBER (insn);
17815 add_compiler_branch_island (labelname, funname, line_number);
17818 labelname = get_prev_label (funname);
17820 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17821 instruction will reach 'foo', otherwise link as 'bl L42'".
17822 "L42" should be a 'branch island', that will do a far jump to
17823 'foo'. Branch islands are generated in
17824 macho_branch_islands(). */
17825 sprintf (buf, "jbsr %%z%d,%.246s",
17826 dest_operand_number, IDENTIFIER_POINTER (labelname));
17829 sprintf (buf, "bl %%z%d", dest_operand_number);
17833 /* Generate PIC and indirect symbol stubs. */
17836 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17838 unsigned int length;
17839 char *symbol_name, *lazy_ptr_name;
17840 char *local_label_0;
17841 static int label = 0;
17843 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17844 symb = (*targetm.strip_name_encoding) (symb);
17847 length = strlen (symb);
17848 symbol_name = alloca (length + 32);
17849 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17851 lazy_ptr_name = alloca (length + 32);
17852 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17855 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
17857 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
17861 fprintf (file, "\t.align 5\n");
17863 fprintf (file, "%s:\n", stub);
17864 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17867 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17868 sprintf (local_label_0, "\"L%011d$spb\"", label);
17870 fprintf (file, "\tmflr r0\n");
17871 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17872 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17873 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17874 lazy_ptr_name, local_label_0);
17875 fprintf (file, "\tmtlr r0\n");
17876 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17877 (TARGET_64BIT ? "ldu" : "lwzu"),
17878 lazy_ptr_name, local_label_0);
17879 fprintf (file, "\tmtctr r12\n");
17880 fprintf (file, "\tbctr\n");
17884 fprintf (file, "\t.align 4\n");
17886 fprintf (file, "%s:\n", stub);
17887 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17889 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17890 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17891 (TARGET_64BIT ? "ldu" : "lwzu"),
17893 fprintf (file, "\tmtctr r12\n");
17894 fprintf (file, "\tbctr\n");
17897 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
17898 fprintf (file, "%s:\n", lazy_ptr_name);
17899 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17900 fprintf (file, "%sdyld_stub_binding_helper\n",
17901 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17904 /* Legitimize PIC addresses. If the address is already
17905 position-independent, we return ORIG. Newly generated
17906 position-independent addresses go into a reg. This is REG if non
17907 zero, otherwise we allocate register(s) as necessary. */
17909 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17912 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17917 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17918 reg = gen_reg_rtx (Pmode);
17920 if (GET_CODE (orig) == CONST)
17924 if (GET_CODE (XEXP (orig, 0)) == PLUS
17925 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17928 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17930 /* Use a different reg for the intermediate value, as
17931 it will be marked UNCHANGING. */
17932 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17933 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17936 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17939 if (GET_CODE (offset) == CONST_INT)
17941 if (SMALL_INT (offset))
17942 return plus_constant (base, INTVAL (offset));
17943 else if (! reload_in_progress && ! reload_completed)
17944 offset = force_reg (Pmode, offset);
17947 rtx mem = force_const_mem (Pmode, orig);
17948 return machopic_legitimize_pic_address (mem, Pmode, reg);
17951 return gen_rtx_PLUS (Pmode, base, offset);
17954 /* Fall back on generic machopic code. */
17955 return machopic_legitimize_pic_address (orig, mode, reg);
17958 /* Output a .machine directive for the Darwin assembler, and call
17959 the generic start_file routine. */
17962 rs6000_darwin_file_start (void)
17964 static const struct
17970 { "ppc64", "ppc64", MASK_64BIT },
17971 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17972 { "power4", "ppc970", 0 },
17973 { "G5", "ppc970", 0 },
17974 { "7450", "ppc7450", 0 },
17975 { "7400", "ppc7400", MASK_ALTIVEC },
17976 { "G4", "ppc7400", 0 },
17977 { "750", "ppc750", 0 },
17978 { "740", "ppc750", 0 },
17979 { "G3", "ppc750", 0 },
17980 { "604e", "ppc604e", 0 },
17981 { "604", "ppc604", 0 },
17982 { "603e", "ppc603", 0 },
17983 { "603", "ppc603", 0 },
17984 { "601", "ppc601", 0 },
17985 { NULL, "ppc", 0 } };
17986 const char *cpu_id = "";
17989 rs6000_file_start ();
17991 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17992 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17993 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17994 && rs6000_select[i].string[0] != '\0')
17995 cpu_id = rs6000_select[i].string;
17997 /* Look through the mapping array. Pick the first name that either
17998 matches the argument, has a bit set in IF_SET that is also set
17999 in the target flags, or has a NULL name. */
18002 while (mapping[i].arg != NULL
18003 && strcmp (mapping[i].arg, cpu_id) != 0
18004 && (mapping[i].if_set & target_flags) == 0)
18007 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18010 #endif /* TARGET_MACHO */
18013 static unsigned int
18014 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
18016 return default_section_type_flags_1 (decl, name, reloc,
18017 flag_pic || DEFAULT_ABI == ABI_AIX);
18020 /* Record an element in the table of global constructors. SYMBOL is
18021 a SYMBOL_REF of the function to be called; PRIORITY is a number
18022 between 0 and MAX_INIT_PRIORITY.
18024 This differs from default_named_section_asm_out_constructor in
18025 that we have special handling for -mrelocatable. */
18028 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18030 const char *section = ".ctors";
18033 if (priority != DEFAULT_INIT_PRIORITY)
18035 sprintf (buf, ".ctors.%.5u",
18036 /* Invert the numbering so the linker puts us in the proper
18037 order; constructors are run from right to left, and the
18038 linker sorts in increasing order. */
18039 MAX_INIT_PRIORITY - priority);
18043 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18044 assemble_align (POINTER_SIZE);
18046 if (TARGET_RELOCATABLE)
18048 fputs ("\t.long (", asm_out_file);
18049 output_addr_const (asm_out_file, symbol);
18050 fputs (")@fixup\n", asm_out_file);
18053 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18057 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18059 const char *section = ".dtors";
18062 if (priority != DEFAULT_INIT_PRIORITY)
18064 sprintf (buf, ".dtors.%.5u",
18065 /* Invert the numbering so the linker puts us in the proper
18066 order; constructors are run from right to left, and the
18067 linker sorts in increasing order. */
18068 MAX_INIT_PRIORITY - priority);
18072 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18073 assemble_align (POINTER_SIZE);
18075 if (TARGET_RELOCATABLE)
18077 fputs ("\t.long (", asm_out_file);
18078 output_addr_const (asm_out_file, symbol);
18079 fputs (")@fixup\n", asm_out_file);
18082 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18086 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18090 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18091 ASM_OUTPUT_LABEL (file, name);
18092 fputs (DOUBLE_INT_ASM_OP, file);
18093 rs6000_output_function_entry (file, name);
18094 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18097 fputs ("\t.size\t", file);
18098 assemble_name (file, name);
18099 fputs (",24\n\t.type\t.", file);
18100 assemble_name (file, name);
18101 fputs (",@function\n", file);
18102 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18104 fputs ("\t.globl\t.", file);
18105 assemble_name (file, name);
18110 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18111 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18112 rs6000_output_function_entry (file, name);
18113 fputs (":\n", file);
18117 if (TARGET_RELOCATABLE
18118 && !TARGET_SECURE_PLT
18119 && (get_pool_size () != 0 || current_function_profile)
18124 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18126 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18127 fprintf (file, "\t.long ");
18128 assemble_name (file, buf);
18130 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18131 assemble_name (file, buf);
18135 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18136 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18138 if (DEFAULT_ABI == ABI_AIX)
18140 const char *desc_name, *orig_name;
18142 orig_name = (*targetm.strip_name_encoding) (name);
18143 desc_name = orig_name;
18144 while (*desc_name == '.')
18147 if (TREE_PUBLIC (decl))
18148 fprintf (file, "\t.globl %s\n", desc_name);
18150 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18151 fprintf (file, "%s:\n", desc_name);
18152 fprintf (file, "\t.long %s\n", orig_name);
18153 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18154 if (DEFAULT_ABI == ABI_AIX)
18155 fputs ("\t.long 0\n", file);
18156 fprintf (file, "\t.previous\n");
18158 ASM_OUTPUT_LABEL (file, name);
18162 rs6000_elf_end_indicate_exec_stack (void)
18165 file_end_indicate_exec_stack ();
18171 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18173 fputs (GLOBAL_ASM_OP, stream);
18174 RS6000_OUTPUT_BASENAME (stream, name);
18175 putc ('\n', stream);
18178 /* A get_unnamed_decl callback, used for read-only sections. PTR
18179 points to the section string variable. */
18182 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18184 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18185 *(const char *const *) directive);
18188 /* Likewise for read-write sections. */
18191 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18193 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18194 *(const char *const *) directive);
18197 /* A get_unnamed_section callback, used for switching to toc_section. */
18200 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18202 if (TARGET_MINIMAL_TOC)
18204 /* toc_section is always selected at least once from
18205 rs6000_xcoff_file_start, so this is guaranteed to
18206 always be defined once and only once in each file. */
18207 if (!toc_initialized)
18209 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18210 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18211 toc_initialized = 1;
18213 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18214 (TARGET_32BIT ? "" : ",3"));
18217 fputs ("\t.toc\n", asm_out_file);
18220 /* Implement TARGET_ASM_INIT_SECTIONS. */
18223 rs6000_xcoff_asm_init_sections (void)
18225 read_only_data_section
18226 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18227 &xcoff_read_only_section_name);
18229 private_data_section
18230 = get_unnamed_section (SECTION_WRITE,
18231 rs6000_xcoff_output_readwrite_section_asm_op,
18232 &xcoff_private_data_section_name);
18234 read_only_private_data_section
18235 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18236 &xcoff_private_data_section_name);
18239 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18241 readonly_data_section = read_only_data_section;
18242 exception_section = data_section;
18246 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18247 tree decl ATTRIBUTE_UNUSED)
18250 static const char * const suffix[3] = { "PR", "RO", "RW" };
18252 if (flags & SECTION_CODE)
18254 else if (flags & SECTION_WRITE)
18259 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18260 (flags & SECTION_CODE) ? "." : "",
18261 name, suffix[smclass], flags & SECTION_ENTSIZE);
18265 rs6000_xcoff_select_section (tree decl, int reloc,
18266 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18268 if (decl_readonly_section_1 (decl, reloc, 1))
18270 if (TREE_PUBLIC (decl))
18271 return read_only_data_section;
18273 return read_only_private_data_section;
18277 if (TREE_PUBLIC (decl))
18278 return data_section;
18280 return private_data_section;
18285 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18289 /* Use select_section for private and uninitialized data. */
18290 if (!TREE_PUBLIC (decl)
18291 || DECL_COMMON (decl)
18292 || DECL_INITIAL (decl) == NULL_TREE
18293 || DECL_INITIAL (decl) == error_mark_node
18294 || (flag_zero_initialized_in_bss
18295 && initializer_zerop (DECL_INITIAL (decl))))
18298 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18299 name = (*targetm.strip_name_encoding) (name);
18300 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18303 /* Select section for constant in constant pool.
18305 On RS/6000, all constants are in the private read-only data area.
18306 However, if this is being placed in the TOC it must be output as a
18310 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18311 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18313 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18314 return toc_section;
18316 return read_only_private_data_section;
18319 /* Remove any trailing [DS] or the like from the symbol name. */
18321 static const char *
18322 rs6000_xcoff_strip_name_encoding (const char *name)
18327 len = strlen (name);
18328 if (name[len - 1] == ']')
18329 return ggc_alloc_string (name, len - 4);
18334 /* Section attributes. AIX is always PIC. */
18336 static unsigned int
18337 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18339 unsigned int align;
18340 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18342 /* Align to at least UNIT size. */
18343 if (flags & SECTION_CODE)
18344 align = MIN_UNITS_PER_WORD;
18346 /* Increase alignment of large objects if not already stricter. */
18347 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18348 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18349 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18351 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18354 /* Output at beginning of assembler file.
18356 Initialize the section names for the RS/6000 at this point.
18358 Specify filename, including full path, to assembler.
18360 We want to go into the TOC section so at least one .toc will be emitted.
18361 Also, in order to output proper .bs/.es pairs, we need at least one static
18362 [RW] section emitted.
18364 Finally, declare mcount when profiling to make the assembler happy. */
18367 rs6000_xcoff_file_start (void)
18369 rs6000_gen_section_name (&xcoff_bss_section_name,
18370 main_input_filename, ".bss_");
18371 rs6000_gen_section_name (&xcoff_private_data_section_name,
18372 main_input_filename, ".rw_");
18373 rs6000_gen_section_name (&xcoff_read_only_section_name,
18374 main_input_filename, ".ro_");
18376 fputs ("\t.file\t", asm_out_file);
18377 output_quoted_string (asm_out_file, main_input_filename);
18378 fputc ('\n', asm_out_file);
18379 if (write_symbols != NO_DEBUG)
18380 switch_to_section (private_data_section);
18381 switch_to_section (text_section);
18383 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18384 rs6000_file_start ();
18387 /* Output at end of assembler file.
18388 On the RS/6000, referencing data should automatically pull in text. */
18391 rs6000_xcoff_file_end (void)
18393 switch_to_section (text_section);
18394 fputs ("_section_.text:\n", asm_out_file);
18395 switch_to_section (data_section);
18396 fputs (TARGET_32BIT
18397 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18400 #endif /* TARGET_XCOFF */
18402 /* Compute a (partial) cost for rtx X. Return true if the complete
18403 cost has been computed, and false if subexpressions should be
18404 scanned. In either case, *TOTAL contains the cost result. */
18407 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18409 enum machine_mode mode = GET_MODE (x);
18413 /* On the RS/6000, if it is valid in the insn, it is free. */
18415 if (((outer_code == SET
18416 || outer_code == PLUS
18417 || outer_code == MINUS)
18418 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18419 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18420 || (outer_code == AND
18421 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18422 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18423 mode == SImode ? 'L' : 'J'))
18424 || mask_operand (x, mode)
18426 && mask64_operand (x, DImode))))
18427 || ((outer_code == IOR || outer_code == XOR)
18428 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18429 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18430 mode == SImode ? 'L' : 'J'))))
18431 || outer_code == ASHIFT
18432 || outer_code == ASHIFTRT
18433 || outer_code == LSHIFTRT
18434 || outer_code == ROTATE
18435 || outer_code == ROTATERT
18436 || outer_code == ZERO_EXTRACT
18437 || (outer_code == MULT
18438 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18439 || ((outer_code == DIV || outer_code == UDIV
18440 || outer_code == MOD || outer_code == UMOD)
18441 && exact_log2 (INTVAL (x)) >= 0)
18442 || (outer_code == COMPARE
18443 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18444 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18445 || (outer_code == EQ
18446 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18447 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18448 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18449 mode == SImode ? 'L' : 'J'))))
18450 || (outer_code == GTU
18451 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18452 || (outer_code == LTU
18453 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18458 else if ((outer_code == PLUS
18459 && reg_or_add_cint_operand (x, VOIDmode))
18460 || (outer_code == MINUS
18461 && reg_or_sub_cint_operand (x, VOIDmode))
18462 || ((outer_code == SET
18463 || outer_code == IOR
18464 || outer_code == XOR)
18466 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18468 *total = COSTS_N_INSNS (1);
18475 && ((outer_code == AND
18476 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18477 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18478 || mask_operand (x, DImode)
18479 || mask64_operand (x, DImode)))
18480 || ((outer_code == IOR || outer_code == XOR)
18481 && CONST_DOUBLE_HIGH (x) == 0
18482 && (CONST_DOUBLE_LOW (x)
18483 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18488 else if (mode == DImode
18489 && (outer_code == SET
18490 || outer_code == IOR
18491 || outer_code == XOR)
18492 && CONST_DOUBLE_HIGH (x) == 0)
18494 *total = COSTS_N_INSNS (1);
18503 /* When optimizing for size, MEM should be slightly more expensive
18504 than generating address, e.g., (plus (reg) (const)).
18505 L1 cache latency is about two instructions. */
18506 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18514 if (mode == DFmode)
18516 if (GET_CODE (XEXP (x, 0)) == MULT)
18518 /* FNMA accounted in outer NEG. */
18519 if (outer_code == NEG)
18520 *total = rs6000_cost->dmul - rs6000_cost->fp;
18522 *total = rs6000_cost->dmul;
18525 *total = rs6000_cost->fp;
18527 else if (mode == SFmode)
18529 /* FNMA accounted in outer NEG. */
18530 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18533 *total = rs6000_cost->fp;
18536 *total = COSTS_N_INSNS (1);
18540 if (mode == DFmode)
18542 if (GET_CODE (XEXP (x, 0)) == MULT)
18544 /* FNMA accounted in outer NEG. */
18545 if (outer_code == NEG)
18548 *total = rs6000_cost->dmul;
18551 *total = rs6000_cost->fp;
18553 else if (mode == SFmode)
18555 /* FNMA accounted in outer NEG. */
18556 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18559 *total = rs6000_cost->fp;
18562 *total = COSTS_N_INSNS (1);
18566 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18567 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18569 if (INTVAL (XEXP (x, 1)) >= -256
18570 && INTVAL (XEXP (x, 1)) <= 255)
18571 *total = rs6000_cost->mulsi_const9;
18573 *total = rs6000_cost->mulsi_const;
18575 /* FMA accounted in outer PLUS/MINUS. */
18576 else if ((mode == DFmode || mode == SFmode)
18577 && (outer_code == PLUS || outer_code == MINUS))
18579 else if (mode == DFmode)
18580 *total = rs6000_cost->dmul;
18581 else if (mode == SFmode)
18582 *total = rs6000_cost->fp;
18583 else if (mode == DImode)
18584 *total = rs6000_cost->muldi;
18586 *total = rs6000_cost->mulsi;
18591 if (FLOAT_MODE_P (mode))
18593 *total = mode == DFmode ? rs6000_cost->ddiv
18594 : rs6000_cost->sdiv;
18601 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18602 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18604 if (code == DIV || code == MOD)
18606 *total = COSTS_N_INSNS (2);
18609 *total = COSTS_N_INSNS (1);
18613 if (GET_MODE (XEXP (x, 1)) == DImode)
18614 *total = rs6000_cost->divdi;
18616 *total = rs6000_cost->divsi;
18618 /* Add in shift and subtract for MOD. */
18619 if (code == MOD || code == UMOD)
18620 *total += COSTS_N_INSNS (2);
18624 *total = COSTS_N_INSNS (4);
18628 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18639 *total = COSTS_N_INSNS (1);
18647 /* Handle mul_highpart. */
18648 if (outer_code == TRUNCATE
18649 && GET_CODE (XEXP (x, 0)) == MULT)
18651 if (mode == DImode)
18652 *total = rs6000_cost->muldi;
18654 *total = rs6000_cost->mulsi;
18657 else if (outer_code == AND)
18660 *total = COSTS_N_INSNS (1);
18665 if (GET_CODE (XEXP (x, 0)) == MEM)
18668 *total = COSTS_N_INSNS (1);
18674 if (!FLOAT_MODE_P (mode))
18676 *total = COSTS_N_INSNS (1);
18682 case UNSIGNED_FLOAT:
18685 case FLOAT_TRUNCATE:
18686 *total = rs6000_cost->fp;
18690 if (mode == DFmode)
18693 *total = rs6000_cost->fp;
18697 switch (XINT (x, 1))
18700 *total = rs6000_cost->fp;
18712 *total = COSTS_N_INSNS (1);
18715 else if (FLOAT_MODE_P (mode)
18716 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18718 *total = rs6000_cost->fp;
18726 /* Carry bit requires mode == Pmode.
18727 NEG or PLUS already counted so only add one. */
18729 && (outer_code == NEG || outer_code == PLUS))
18731 *total = COSTS_N_INSNS (1);
18734 if (outer_code == SET)
18736 if (XEXP (x, 1) == const0_rtx)
18738 *total = COSTS_N_INSNS (2);
18741 else if (mode == Pmode)
18743 *total = COSTS_N_INSNS (3);
18752 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18754 *total = COSTS_N_INSNS (2);
18758 if (outer_code == COMPARE)
18772 /* A C expression returning the cost of moving data from a register of class
18773 CLASS1 to one of CLASS2. */
18776 rs6000_register_move_cost (enum machine_mode mode,
18777 enum reg_class from, enum reg_class to)
18779 /* Moves from/to GENERAL_REGS. */
18780 if (reg_classes_intersect_p (to, GENERAL_REGS)
18781 || reg_classes_intersect_p (from, GENERAL_REGS))
18783 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18786 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18787 return (rs6000_memory_move_cost (mode, from, 0)
18788 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18790 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18792 else if (from == CR_REGS)
18796 /* A move will cost one instruction per GPR moved. */
18797 return 2 * hard_regno_nregs[0][mode];
18800 /* Moving between two similar registers is just one instruction. */
18801 else if (reg_classes_intersect_p (to, from))
18802 return mode == TFmode ? 4 : 2;
18804 /* Everything else has to go through GENERAL_REGS. */
18806 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18807 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18810 /* A C expressions returning the cost of moving data of MODE from a register to
18814 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18815 int in ATTRIBUTE_UNUSED)
18817 if (reg_classes_intersect_p (class, GENERAL_REGS))
18818 return 4 * hard_regno_nregs[0][mode];
18819 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18820 return 4 * hard_regno_nregs[32][mode];
18821 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18822 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18824 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18827 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18828 Assumes no trapping math and finite arguments. */
18831 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18833 rtx x0, e0, e1, y1, u0, v0, one;
18835 x0 = gen_reg_rtx (SFmode);
18836 e0 = gen_reg_rtx (SFmode);
18837 e1 = gen_reg_rtx (SFmode);
18838 y1 = gen_reg_rtx (SFmode);
18839 u0 = gen_reg_rtx (SFmode);
18840 v0 = gen_reg_rtx (SFmode);
18841 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18843 /* x0 = 1./d estimate */
18844 emit_insn (gen_rtx_SET (VOIDmode, x0,
18845 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18847 /* e0 = 1. - d * x0 */
18848 emit_insn (gen_rtx_SET (VOIDmode, e0,
18849 gen_rtx_MINUS (SFmode, one,
18850 gen_rtx_MULT (SFmode, d, x0))));
18851 /* e1 = e0 + e0 * e0 */
18852 emit_insn (gen_rtx_SET (VOIDmode, e1,
18853 gen_rtx_PLUS (SFmode,
18854 gen_rtx_MULT (SFmode, e0, e0), e0)));
18855 /* y1 = x0 + e1 * x0 */
18856 emit_insn (gen_rtx_SET (VOIDmode, y1,
18857 gen_rtx_PLUS (SFmode,
18858 gen_rtx_MULT (SFmode, e1, x0), x0)));
18860 emit_insn (gen_rtx_SET (VOIDmode, u0,
18861 gen_rtx_MULT (SFmode, n, y1)));
18862 /* v0 = n - d * u0 */
18863 emit_insn (gen_rtx_SET (VOIDmode, v0,
18864 gen_rtx_MINUS (SFmode, n,
18865 gen_rtx_MULT (SFmode, d, u0))));
18866 /* res = u0 + v0 * y1 */
18867 emit_insn (gen_rtx_SET (VOIDmode, res,
18868 gen_rtx_PLUS (SFmode,
18869 gen_rtx_MULT (SFmode, v0, y1), u0)));
18872 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18873 Assumes no trapping math and finite arguments. */
18876 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18878 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18880 x0 = gen_reg_rtx (DFmode);
18881 e0 = gen_reg_rtx (DFmode);
18882 e1 = gen_reg_rtx (DFmode);
18883 e2 = gen_reg_rtx (DFmode);
18884 y1 = gen_reg_rtx (DFmode);
18885 y2 = gen_reg_rtx (DFmode);
18886 y3 = gen_reg_rtx (DFmode);
18887 u0 = gen_reg_rtx (DFmode);
18888 v0 = gen_reg_rtx (DFmode);
18889 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18891 /* x0 = 1./d estimate */
18892 emit_insn (gen_rtx_SET (VOIDmode, x0,
18893 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18895 /* e0 = 1. - d * x0 */
18896 emit_insn (gen_rtx_SET (VOIDmode, e0,
18897 gen_rtx_MINUS (DFmode, one,
18898 gen_rtx_MULT (SFmode, d, x0))));
18899 /* y1 = x0 + e0 * x0 */
18900 emit_insn (gen_rtx_SET (VOIDmode, y1,
18901 gen_rtx_PLUS (DFmode,
18902 gen_rtx_MULT (DFmode, e0, x0), x0)));
18904 emit_insn (gen_rtx_SET (VOIDmode, e1,
18905 gen_rtx_MULT (DFmode, e0, e0)));
18906 /* y2 = y1 + e1 * y1 */
18907 emit_insn (gen_rtx_SET (VOIDmode, y2,
18908 gen_rtx_PLUS (DFmode,
18909 gen_rtx_MULT (DFmode, e1, y1), y1)));
18911 emit_insn (gen_rtx_SET (VOIDmode, e2,
18912 gen_rtx_MULT (DFmode, e1, e1)));
18913 /* y3 = y2 + e2 * y2 */
18914 emit_insn (gen_rtx_SET (VOIDmode, y3,
18915 gen_rtx_PLUS (DFmode,
18916 gen_rtx_MULT (DFmode, e2, y2), y2)));
18918 emit_insn (gen_rtx_SET (VOIDmode, u0,
18919 gen_rtx_MULT (DFmode, n, y3)));
18920 /* v0 = n - d * u0 */
18921 emit_insn (gen_rtx_SET (VOIDmode, v0,
18922 gen_rtx_MINUS (DFmode, n,
18923 gen_rtx_MULT (DFmode, d, u0))));
18924 /* res = u0 + v0 * y3 */
18925 emit_insn (gen_rtx_SET (VOIDmode, res,
18926 gen_rtx_PLUS (DFmode,
18927 gen_rtx_MULT (DFmode, v0, y3), u0)));
18930 /* Return an RTX representing where to find the function value of a
18931 function returning MODE. */
18933 rs6000_complex_function_value (enum machine_mode mode)
18935 unsigned int regno;
18937 enum machine_mode inner = GET_MODE_INNER (mode);
18938 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18940 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18941 regno = FP_ARG_RETURN;
18944 regno = GP_ARG_RETURN;
18946 /* 32-bit is OK since it'll go in r3/r4. */
18947 if (TARGET_32BIT && inner_bytes >= 4)
18948 return gen_rtx_REG (mode, regno);
18951 if (inner_bytes >= 8)
18952 return gen_rtx_REG (mode, regno);
18954 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18956 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18957 GEN_INT (inner_bytes));
18958 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18961 /* Define how to find the value returned by a function.
18962 VALTYPE is the data type of the value (as a tree).
18963 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18964 otherwise, FUNC is 0.
18966 On the SPE, both FPs and vectors are returned in r3.
18968 On RS/6000 an integer value is in r3 and a floating-point value is in
18969 fp1, unless -msoft-float. */
18972 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18974 enum machine_mode mode;
18975 unsigned int regno;
18977 /* Special handling for structs in darwin64. */
18978 if (rs6000_darwin64_abi
18979 && TYPE_MODE (valtype) == BLKmode
18980 && TREE_CODE (valtype) == RECORD_TYPE
18981 && int_size_in_bytes (valtype) > 0)
18983 CUMULATIVE_ARGS valcum;
18987 valcum.fregno = FP_ARG_MIN_REG;
18988 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18989 /* Do a trial code generation as if this were going to be passed as
18990 an argument; if any part goes in memory, we return NULL. */
18991 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
18994 /* Otherwise fall through to standard ABI rules. */
18997 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18999 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19000 return gen_rtx_PARALLEL (DImode,
19002 gen_rtx_EXPR_LIST (VOIDmode,
19003 gen_rtx_REG (SImode, GP_ARG_RETURN),
19005 gen_rtx_EXPR_LIST (VOIDmode,
19006 gen_rtx_REG (SImode,
19007 GP_ARG_RETURN + 1),
19010 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19012 return gen_rtx_PARALLEL (DCmode,
19014 gen_rtx_EXPR_LIST (VOIDmode,
19015 gen_rtx_REG (SImode, GP_ARG_RETURN),
19017 gen_rtx_EXPR_LIST (VOIDmode,
19018 gen_rtx_REG (SImode,
19019 GP_ARG_RETURN + 1),
19021 gen_rtx_EXPR_LIST (VOIDmode,
19022 gen_rtx_REG (SImode,
19023 GP_ARG_RETURN + 2),
19025 gen_rtx_EXPR_LIST (VOIDmode,
19026 gen_rtx_REG (SImode,
19027 GP_ARG_RETURN + 3),
19030 if ((INTEGRAL_TYPE_P (valtype)
19031 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
19032 || POINTER_TYPE_P (valtype))
19033 mode = TARGET_32BIT ? SImode : DImode;
19035 mode = TYPE_MODE (valtype);
19037 if (DECIMAL_FLOAT_MODE_P (mode))
19038 regno = GP_ARG_RETURN;
19039 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19040 regno = FP_ARG_RETURN;
19041 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19042 && targetm.calls.split_complex_arg)
19043 return rs6000_complex_function_value (mode);
19044 else if (TREE_CODE (valtype) == VECTOR_TYPE
19045 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19046 && ALTIVEC_VECTOR_MODE (mode))
19047 regno = ALTIVEC_ARG_RETURN;
19048 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19049 && (mode == DFmode || mode == DCmode))
19050 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19052 regno = GP_ARG_RETURN;
19054 return gen_rtx_REG (mode, regno);
19057 /* Define how to find the value returned by a library function
19058 assuming the value has mode MODE. */
19060 rs6000_libcall_value (enum machine_mode mode)
19062 unsigned int regno;
19064 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19066 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19067 return gen_rtx_PARALLEL (DImode,
19069 gen_rtx_EXPR_LIST (VOIDmode,
19070 gen_rtx_REG (SImode, GP_ARG_RETURN),
19072 gen_rtx_EXPR_LIST (VOIDmode,
19073 gen_rtx_REG (SImode,
19074 GP_ARG_RETURN + 1),
19078 if (DECIMAL_FLOAT_MODE_P (mode))
19079 regno = GP_ARG_RETURN;
19080 else if (SCALAR_FLOAT_MODE_P (mode)
19081 && TARGET_HARD_FLOAT && TARGET_FPRS)
19082 regno = FP_ARG_RETURN;
19083 else if (ALTIVEC_VECTOR_MODE (mode)
19084 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19085 regno = ALTIVEC_ARG_RETURN;
19086 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19087 return rs6000_complex_function_value (mode);
19088 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19089 && (mode == DFmode || mode == DCmode))
19090 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19092 regno = GP_ARG_RETURN;
19094 return gen_rtx_REG (mode, regno);
19097 /* Define the offset between two registers, FROM to be eliminated and its
19098 replacement TO, at the start of a routine. */
19100 rs6000_initial_elimination_offset (int from, int to)
19102 rs6000_stack_t *info = rs6000_stack_info ();
19103 HOST_WIDE_INT offset;
19105 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19106 offset = info->push_p ? 0 : -info->total_size;
19107 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19109 offset = info->push_p ? 0 : -info->total_size;
19110 if (FRAME_GROWS_DOWNWARD)
19111 offset += info->fixed_size + info->vars_size + info->parm_size;
19113 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19114 offset = FRAME_GROWS_DOWNWARD
19115 ? info->fixed_size + info->vars_size + info->parm_size
19117 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19118 offset = info->total_size;
19119 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19120 offset = info->push_p ? info->total_size : 0;
19121 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19124 gcc_unreachable ();
19129 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19132 rs6000_is_opaque_type (tree type)
19134 return (type == opaque_V2SI_type_node
19135 || type == opaque_V2SF_type_node
19136 || type == opaque_p_V2SI_type_node
19137 || type == opaque_V4SI_type_node);
19141 rs6000_dwarf_register_span (rtx reg)
19146 && (SPE_VECTOR_MODE (GET_MODE (reg))
19147 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19152 regno = REGNO (reg);
19154 /* The duality of the SPE register size wreaks all kinds of havoc.
19155 This is a way of distinguishing r0 in 32-bits from r0 in
19158 gen_rtx_PARALLEL (VOIDmode,
19161 gen_rtx_REG (SImode, regno + 1200),
19162 gen_rtx_REG (SImode, regno))
19164 gen_rtx_REG (SImode, regno),
19165 gen_rtx_REG (SImode, regno + 1200)));
19168 /* Map internal gcc register numbers to DWARF2 register numbers. */
19171 rs6000_dbx_register_number (unsigned int regno)
19173 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19175 if (regno == MQ_REGNO)
19177 if (regno == LINK_REGISTER_REGNUM)
19179 if (regno == COUNT_REGISTER_REGNUM)
19181 if (CR_REGNO_P (regno))
19182 return regno - CR0_REGNO + 86;
19183 if (regno == XER_REGNO)
19185 if (ALTIVEC_REGNO_P (regno))
19186 return regno - FIRST_ALTIVEC_REGNO + 1124;
19187 if (regno == VRSAVE_REGNO)
19189 if (regno == VSCR_REGNO)
19191 if (regno == SPE_ACC_REGNO)
19193 if (regno == SPEFSCR_REGNO)
19195 /* SPE high reg number. We get these values of regno from
19196 rs6000_dwarf_register_span. */
19197 gcc_assert (regno >= 1200 && regno < 1232);
19201 /* target hook eh_return_filter_mode */
19202 static enum machine_mode
19203 rs6000_eh_return_filter_mode (void)
19205 return TARGET_32BIT ? SImode : word_mode;
19208 /* Target hook for scalar_mode_supported_p. */
19210 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19212 if (DECIMAL_FLOAT_MODE_P (mode))
19215 return default_scalar_mode_supported_p (mode);
19218 /* Target hook for vector_mode_supported_p. */
19220 rs6000_vector_mode_supported_p (enum machine_mode mode)
19223 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19226 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19233 /* Target hook for invalid_arg_for_unprototyped_fn. */
19234 static const char *
19235 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19237 return (!rs6000_darwin64_abi
19239 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19240 && (funcdecl == NULL_TREE
19241 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19242 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19243 ? N_("AltiVec argument passed to unprototyped function")
19247 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19248 setup by using __stack_chk_fail_local hidden function instead of
19249 calling __stack_chk_fail directly. Otherwise it is better to call
19250 __stack_chk_fail directly. */
19253 rs6000_stack_protect_fail (void)
19255 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19256 ? default_hidden_stack_protect_fail ()
19257 : default_external_stack_protect_fail ();
19260 #include "gt-rs6000.h"