1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 static GTY(()) bool rs6000_cell_dont_microcode;
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups;
150 /* Align branch targets. */
151 static GTY(()) bool rs6000_align_branch_targets;
153 /* Support for -msched-costly-dep option. */
154 const char *rs6000_sched_costly_dep_str;
155 enum rs6000_dependence_cost rs6000_sched_costly_dep;
157 /* Support for -minsert-sched-nops option. */
158 const char *rs6000_sched_insert_nops_str;
159 enum rs6000_nop_insertion rs6000_sched_insert_nops;
161 /* Support targetm.vectorize.builtin_mask_for_load. */
162 static GTY(()) tree altivec_builtin_mask_for_load;
164 /* Size of long double. */
165 int rs6000_long_double_type_size;
167 /* IEEE quad extended precision long double. */
170 /* Whether -mabi=altivec has appeared. */
171 int rs6000_altivec_abi;
173 /* Nonzero if we want SPE ABI extensions. */
176 /* Nonzero if floating point operations are done in the GPRs. */
177 int rs6000_float_gprs = 0;
179 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
180 int rs6000_darwin64_abi;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Save information from a "cmpxx" operation until the branch or scc is
187 rtx rs6000_compare_op0, rs6000_compare_op1;
188 int rs6000_compare_fp_p;
190 /* Label number of label created for -mrelocatable, to call to so we can
191 get the address of the GOT section */
192 int rs6000_pic_labelno;
195 /* Which abi to adhere to */
196 const char *rs6000_abi_name;
198 /* Semantics of the small data area */
199 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
201 /* Which small data model to use */
202 const char *rs6000_sdata_name = (char *)0;
204 /* Counter for labels which are to be placed in .fixup. */
205 int fixuplabelno = 0;
208 /* Bit size of immediate TLS offsets and string from which it is decoded. */
209 int rs6000_tls_size = 32;
210 const char *rs6000_tls_size_string;
212 /* ABI enumeration available for subtarget to use. */
213 enum rs6000_abi rs6000_current_abi;
215 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
219 const char *rs6000_debug_name;
220 int rs6000_debug_stack; /* debug stack applications */
221 int rs6000_debug_arg; /* debug argument handling */
223 /* Value is TRUE if register/mode pair is acceptable. */
224 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Built in types. */
228 tree rs6000_builtin_types[RS6000_BTI_MAX];
229 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
231 const char *rs6000_traceback_name;
233 traceback_default = 0,
239 /* Flag to say the TOC is initialized */
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *read_only_private_data_section;
250 static GTY(()) section *sdata2_section;
251 static GTY(()) section *toc_section;
253 /* Control alignment for fields within structures. */
254 /* String from -malign-XXXXX. */
255 int rs6000_alignment_flags;
257 /* True for any options that were explicitly set. */
259 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
260 bool alignment; /* True if -malign- was used. */
261 bool abi; /* True if -mabi=spe/nospe was used. */
262 bool spe; /* True if -mspe= was used. */
263 bool float_gprs; /* True if -mfloat-gprs= was used. */
264 bool isel; /* True if -misel was used. */
265 bool long_double; /* True if -mlong-double- was used. */
266 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
267 } rs6000_explicit_options;
269 struct builtin_description
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
280 /* Target cpu costs. */
282 struct processor_costs {
283 const int mulsi; /* cost of SImode multiplication. */
284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
295 const struct processor_costs *rs6000_cost;
297 /* Processor costs (relative to an add) */
299 /* Instruction size costs on 32bit processors. */
301 struct processor_costs size32_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction size costs on 64bit processors. */
316 struct processor_costs size64_cost = {
317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction costs on RIOS1 processors. */
331 struct processor_costs rios1_cost = {
332 COSTS_N_INSNS (5), /* mulsi */
333 COSTS_N_INSNS (4), /* mulsi_const */
334 COSTS_N_INSNS (3), /* mulsi_const9 */
335 COSTS_N_INSNS (5), /* muldi */
336 COSTS_N_INSNS (19), /* divsi */
337 COSTS_N_INSNS (19), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (19), /* sdiv */
341 COSTS_N_INSNS (19), /* ddiv */
344 /* Instruction costs on RIOS2 processors. */
346 struct processor_costs rios2_cost = {
347 COSTS_N_INSNS (2), /* mulsi */
348 COSTS_N_INSNS (2), /* mulsi_const */
349 COSTS_N_INSNS (2), /* mulsi_const9 */
350 COSTS_N_INSNS (2), /* muldi */
351 COSTS_N_INSNS (13), /* divsi */
352 COSTS_N_INSNS (13), /* divdi */
353 COSTS_N_INSNS (2), /* fp */
354 COSTS_N_INSNS (2), /* dmul */
355 COSTS_N_INSNS (17), /* sdiv */
356 COSTS_N_INSNS (17), /* ddiv */
359 /* Instruction costs on RS64A processors. */
361 struct processor_costs rs64a_cost = {
362 COSTS_N_INSNS (20), /* mulsi */
363 COSTS_N_INSNS (12), /* mulsi_const */
364 COSTS_N_INSNS (8), /* mulsi_const9 */
365 COSTS_N_INSNS (34), /* muldi */
366 COSTS_N_INSNS (65), /* divsi */
367 COSTS_N_INSNS (67), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (4), /* dmul */
370 COSTS_N_INSNS (31), /* sdiv */
371 COSTS_N_INSNS (31), /* ddiv */
374 /* Instruction costs on MPCCORE processors. */
376 struct processor_costs mpccore_cost = {
377 COSTS_N_INSNS (2), /* mulsi */
378 COSTS_N_INSNS (2), /* mulsi_const */
379 COSTS_N_INSNS (2), /* mulsi_const9 */
380 COSTS_N_INSNS (2), /* muldi */
381 COSTS_N_INSNS (6), /* divsi */
382 COSTS_N_INSNS (6), /* divdi */
383 COSTS_N_INSNS (4), /* fp */
384 COSTS_N_INSNS (5), /* dmul */
385 COSTS_N_INSNS (10), /* sdiv */
386 COSTS_N_INSNS (17), /* ddiv */
389 /* Instruction costs on PPC403 processors. */
391 struct processor_costs ppc403_cost = {
392 COSTS_N_INSNS (4), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (4), /* mulsi_const9 */
395 COSTS_N_INSNS (4), /* muldi */
396 COSTS_N_INSNS (33), /* divsi */
397 COSTS_N_INSNS (33), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC405 processors. */
406 struct processor_costs ppc405_cost = {
407 COSTS_N_INSNS (5), /* mulsi */
408 COSTS_N_INSNS (4), /* mulsi_const */
409 COSTS_N_INSNS (3), /* mulsi_const9 */
410 COSTS_N_INSNS (5), /* muldi */
411 COSTS_N_INSNS (35), /* divsi */
412 COSTS_N_INSNS (35), /* divdi */
413 COSTS_N_INSNS (11), /* fp */
414 COSTS_N_INSNS (11), /* dmul */
415 COSTS_N_INSNS (11), /* sdiv */
416 COSTS_N_INSNS (11), /* ddiv */
419 /* Instruction costs on PPC440 processors. */
421 struct processor_costs ppc440_cost = {
422 COSTS_N_INSNS (3), /* mulsi */
423 COSTS_N_INSNS (2), /* mulsi_const */
424 COSTS_N_INSNS (2), /* mulsi_const9 */
425 COSTS_N_INSNS (3), /* muldi */
426 COSTS_N_INSNS (34), /* divsi */
427 COSTS_N_INSNS (34), /* divdi */
428 COSTS_N_INSNS (5), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (19), /* sdiv */
431 COSTS_N_INSNS (33), /* ddiv */
434 /* Instruction costs on PPC601 processors. */
436 struct processor_costs ppc601_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (5), /* mulsi_const */
439 COSTS_N_INSNS (5), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (36), /* divsi */
442 COSTS_N_INSNS (36), /* divdi */
443 COSTS_N_INSNS (4), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (17), /* sdiv */
446 COSTS_N_INSNS (31), /* ddiv */
449 /* Instruction costs on PPC603 processors. */
451 struct processor_costs ppc603_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (3), /* mulsi_const */
454 COSTS_N_INSNS (2), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (37), /* divsi */
457 COSTS_N_INSNS (37), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (4), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (33), /* ddiv */
464 /* Instruction costs on PPC604 processors. */
466 struct processor_costs ppc604_cost = {
467 COSTS_N_INSNS (4), /* mulsi */
468 COSTS_N_INSNS (4), /* mulsi_const */
469 COSTS_N_INSNS (4), /* mulsi_const9 */
470 COSTS_N_INSNS (4), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC604e processors. */
481 struct processor_costs ppc604e_cost = {
482 COSTS_N_INSNS (2), /* mulsi */
483 COSTS_N_INSNS (2), /* mulsi_const */
484 COSTS_N_INSNS (2), /* mulsi_const9 */
485 COSTS_N_INSNS (2), /* muldi */
486 COSTS_N_INSNS (20), /* divsi */
487 COSTS_N_INSNS (20), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC620 processors. */
496 struct processor_costs ppc620_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (18), /* sdiv */
506 COSTS_N_INSNS (32), /* ddiv */
509 /* Instruction costs on PPC630 processors. */
511 struct processor_costs ppc630_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (7), /* muldi */
516 COSTS_N_INSNS (21), /* divsi */
517 COSTS_N_INSNS (37), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (21), /* ddiv */
524 /* Instruction costs on Cell processor. */
525 /* COSTS_N_INSNS (1) ~ one add. */
527 struct processor_costs ppccell_cost = {
528 COSTS_N_INSNS (9/2)+2, /* mulsi */
529 COSTS_N_INSNS (6/2), /* mulsi_const */
530 COSTS_N_INSNS (6/2), /* mulsi_const9 */
531 COSTS_N_INSNS (15/2)+2, /* muldi */
532 COSTS_N_INSNS (38/2), /* divsi */
533 COSTS_N_INSNS (70/2), /* divdi */
534 COSTS_N_INSNS (10/2), /* fp */
535 COSTS_N_INSNS (10/2), /* dmul */
536 COSTS_N_INSNS (74/2), /* sdiv */
537 COSTS_N_INSNS (74/2), /* ddiv */
540 /* Instruction costs on PPC750 and PPC7400 processors. */
542 struct processor_costs ppc750_cost = {
543 COSTS_N_INSNS (5), /* mulsi */
544 COSTS_N_INSNS (3), /* mulsi_const */
545 COSTS_N_INSNS (2), /* mulsi_const9 */
546 COSTS_N_INSNS (5), /* muldi */
547 COSTS_N_INSNS (17), /* divsi */
548 COSTS_N_INSNS (17), /* divdi */
549 COSTS_N_INSNS (3), /* fp */
550 COSTS_N_INSNS (3), /* dmul */
551 COSTS_N_INSNS (17), /* sdiv */
552 COSTS_N_INSNS (31), /* ddiv */
555 /* Instruction costs on PPC7450 processors. */
557 struct processor_costs ppc7450_cost = {
558 COSTS_N_INSNS (4), /* mulsi */
559 COSTS_N_INSNS (3), /* mulsi_const */
560 COSTS_N_INSNS (3), /* mulsi_const9 */
561 COSTS_N_INSNS (4), /* muldi */
562 COSTS_N_INSNS (23), /* divsi */
563 COSTS_N_INSNS (23), /* divdi */
564 COSTS_N_INSNS (5), /* fp */
565 COSTS_N_INSNS (5), /* dmul */
566 COSTS_N_INSNS (21), /* sdiv */
567 COSTS_N_INSNS (35), /* ddiv */
570 /* Instruction costs on PPC8540 processors. */
572 struct processor_costs ppc8540_cost = {
573 COSTS_N_INSNS (4), /* mulsi */
574 COSTS_N_INSNS (4), /* mulsi_const */
575 COSTS_N_INSNS (4), /* mulsi_const9 */
576 COSTS_N_INSNS (4), /* muldi */
577 COSTS_N_INSNS (19), /* divsi */
578 COSTS_N_INSNS (19), /* divdi */
579 COSTS_N_INSNS (4), /* fp */
580 COSTS_N_INSNS (4), /* dmul */
581 COSTS_N_INSNS (29), /* sdiv */
582 COSTS_N_INSNS (29), /* ddiv */
585 /* Instruction costs on POWER4 and POWER5 processors. */
587 struct processor_costs power4_cost = {
588 COSTS_N_INSNS (3), /* mulsi */
589 COSTS_N_INSNS (2), /* mulsi_const */
590 COSTS_N_INSNS (2), /* mulsi_const9 */
591 COSTS_N_INSNS (4), /* muldi */
592 COSTS_N_INSNS (18), /* divsi */
593 COSTS_N_INSNS (34), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (17), /* sdiv */
597 COSTS_N_INSNS (17), /* ddiv */
600 /* Instruction costs on POWER6 processors. */
602 struct processor_costs power6_cost = {
603 COSTS_N_INSNS (8), /* mulsi */
604 COSTS_N_INSNS (8), /* mulsi_const */
605 COSTS_N_INSNS (8), /* mulsi_const9 */
606 COSTS_N_INSNS (8), /* muldi */
607 COSTS_N_INSNS (22), /* divsi */
608 COSTS_N_INSNS (28), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (13), /* sdiv */
612 COSTS_N_INSNS (16), /* ddiv */
616 static bool rs6000_function_ok_for_sibcall (tree, tree);
617 static const char *rs6000_invalid_within_doloop (rtx);
618 static rtx rs6000_generate_compare (enum rtx_code);
619 static void rs6000_maybe_dead (rtx);
620 static void rs6000_emit_stack_tie (void);
621 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
622 static rtx spe_synthesize_frame_save (rtx);
623 static bool spe_func_has_64bit_regs_p (void);
624 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
626 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
627 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
628 static unsigned rs6000_hash_constant (rtx);
629 static unsigned toc_hash_function (const void *);
630 static int toc_hash_eq (const void *, const void *);
631 static int constant_pool_expr_1 (rtx, int *, int *);
632 static bool constant_pool_expr_p (rtx);
633 static bool legitimate_small_data_p (enum machine_mode, rtx);
634 static bool legitimate_indexed_address_p (rtx, int);
635 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
636 static struct machine_function * rs6000_init_machine_status (void);
637 static bool rs6000_assemble_integer (rtx, unsigned int, int);
638 static bool no_global_regs_above (int);
639 #ifdef HAVE_GAS_HIDDEN
640 static void rs6000_assemble_visibility (tree, int);
642 static int rs6000_ra_ever_killed (void);
643 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
644 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
645 static bool rs6000_ms_bitfield_layout_p (tree);
646 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
647 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
648 static const char *rs6000_mangle_fundamental_type (tree);
649 extern const struct attribute_spec rs6000_attribute_table[];
650 static void rs6000_set_default_type_attributes (tree);
651 static bool rs6000_reg_live_or_pic_offset_p (int);
652 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
653 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
654 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
656 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
657 static bool rs6000_return_in_memory (tree, tree);
658 static void rs6000_file_start (void);
660 static int rs6000_elf_reloc_rw_mask (void);
661 static void rs6000_elf_asm_out_constructor (rtx, int);
662 static void rs6000_elf_asm_out_destructor (rtx, int);
663 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
664 static void rs6000_elf_asm_init_sections (void);
665 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
666 unsigned HOST_WIDE_INT);
667 static void rs6000_elf_encode_section_info (tree, rtx, int)
670 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
672 static void rs6000_xcoff_asm_output_anchor (rtx);
673 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
674 static void rs6000_xcoff_asm_init_sections (void);
675 static int rs6000_xcoff_reloc_rw_mask (void);
676 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
677 static section *rs6000_xcoff_select_section (tree, int,
678 unsigned HOST_WIDE_INT);
679 static void rs6000_xcoff_unique_section (tree, int);
680 static section *rs6000_xcoff_select_rtx_section
681 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
682 static const char * rs6000_xcoff_strip_name_encoding (const char *);
683 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
684 static void rs6000_xcoff_file_start (void);
685 static void rs6000_xcoff_file_end (void);
687 static int rs6000_variable_issue (FILE *, int, rtx, int);
688 static bool rs6000_rtx_costs (rtx, int, int, int *);
689 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
690 static void rs6000_sched_init (FILE *, int, int);
691 static bool is_microcoded_insn (rtx);
692 static bool is_nonpipeline_insn (rtx);
693 static bool is_cracked_insn (rtx);
694 static bool is_branch_slot_insn (rtx);
695 static bool is_load_insn (rtx);
696 static rtx get_store_dest (rtx pat);
697 static bool is_store_insn (rtx);
698 static bool set_to_load_agen (rtx,rtx);
699 static bool adjacent_mem_locations (rtx,rtx);
700 static int rs6000_adjust_priority (rtx, int);
701 static int rs6000_issue_rate (void);
702 static bool rs6000_is_costly_dependence (dep_t, int, int);
703 static rtx get_next_active_insn (rtx, rtx);
704 static bool insn_terminates_group_p (rtx , enum group_termination);
705 static bool insn_must_be_first_in_group (rtx);
706 static bool insn_must_be_last_in_group (rtx);
707 static bool is_costly_group (rtx *, rtx);
708 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
709 static int redefine_groups (FILE *, int, rtx, rtx);
710 static int pad_groups (FILE *, int, rtx, rtx);
711 static void rs6000_sched_finish (FILE *, int);
712 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
713 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
714 static int rs6000_use_sched_lookahead (void);
715 static int rs6000_use_sched_lookahead_guard (rtx);
716 static tree rs6000_builtin_mask_for_load (void);
717 static tree rs6000_builtin_mul_widen_even (tree);
718 static tree rs6000_builtin_mul_widen_odd (tree);
719 static tree rs6000_builtin_conversion (enum tree_code, tree);
721 static void def_builtin (int, const char *, tree, int);
722 static void rs6000_init_builtins (void);
723 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
724 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
725 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
726 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
727 static void altivec_init_builtins (void);
728 static void rs6000_common_init_builtins (void);
729 static void rs6000_init_libfuncs (void);
731 static void enable_mask_for_builtins (struct builtin_description *, int,
732 enum rs6000_builtins,
733 enum rs6000_builtins);
734 static tree build_opaque_vector_type (tree, int);
735 static void spe_init_builtins (void);
736 static rtx spe_expand_builtin (tree, rtx, bool *);
737 static rtx spe_expand_stv_builtin (enum insn_code, tree);
738 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
739 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
740 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
741 static rs6000_stack_t *rs6000_stack_info (void);
742 static void debug_stack_info (rs6000_stack_t *);
744 static rtx altivec_expand_builtin (tree, rtx, bool *);
745 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
746 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
747 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
748 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
749 static rtx altivec_expand_predicate_builtin (enum insn_code,
750 const char *, tree, rtx);
751 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
752 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
753 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
754 static rtx altivec_expand_vec_set_builtin (tree);
755 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
756 static int get_element_number (tree, tree);
757 static bool rs6000_handle_option (size_t, const char *, int);
758 static void rs6000_parse_tls_size_option (void);
759 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
760 static int first_altivec_reg_to_save (void);
761 static unsigned int compute_vrsave_mask (void);
762 static void compute_save_world_info (rs6000_stack_t *info_ptr);
763 static void is_altivec_return_reg (rtx, void *);
764 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
765 int easy_vector_constant (rtx, enum machine_mode);
766 static bool rs6000_is_opaque_type (tree);
767 static rtx rs6000_dwarf_register_span (rtx);
768 static void rs6000_init_dwarf_reg_sizes_extra (tree);
769 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
770 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
771 static rtx rs6000_tls_get_addr (void);
772 static rtx rs6000_got_sym (void);
773 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
774 static const char *rs6000_get_some_local_dynamic_name (void);
775 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
776 static rtx rs6000_complex_function_value (enum machine_mode);
777 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
778 enum machine_mode, tree);
779 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
781 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
782 tree, HOST_WIDE_INT);
783 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
786 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
789 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
790 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
791 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
792 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
793 enum machine_mode, tree,
795 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
797 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
799 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
801 static void macho_branch_islands (void);
802 static int no_previous_def (tree function_name);
803 static tree get_prev_label (tree function_name);
804 static void rs6000_darwin_file_start (void);
807 static tree rs6000_build_builtin_va_list (void);
808 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
809 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
810 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
811 static bool rs6000_vector_mode_supported_p (enum machine_mode);
812 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
814 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
816 static int get_vsel_insn (enum machine_mode);
817 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
818 static tree rs6000_stack_protect_fail (void);
820 const int INSN_NOT_AVAILABLE = -1;
821 static enum machine_mode rs6000_eh_return_filter_mode (void);
823 /* Hash table stuff for keeping track of TOC entries. */
825 struct toc_hash_struct GTY(())
827 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
828 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
830 enum machine_mode key_mode;
834 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
836 /* Default register names. */
837 char rs6000_reg_names[][8] =
839 "0", "1", "2", "3", "4", "5", "6", "7",
840 "8", "9", "10", "11", "12", "13", "14", "15",
841 "16", "17", "18", "19", "20", "21", "22", "23",
842 "24", "25", "26", "27", "28", "29", "30", "31",
843 "0", "1", "2", "3", "4", "5", "6", "7",
844 "8", "9", "10", "11", "12", "13", "14", "15",
845 "16", "17", "18", "19", "20", "21", "22", "23",
846 "24", "25", "26", "27", "28", "29", "30", "31",
847 "mq", "lr", "ctr","ap",
848 "0", "1", "2", "3", "4", "5", "6", "7",
850 /* AltiVec registers. */
851 "0", "1", "2", "3", "4", "5", "6", "7",
852 "8", "9", "10", "11", "12", "13", "14", "15",
853 "16", "17", "18", "19", "20", "21", "22", "23",
854 "24", "25", "26", "27", "28", "29", "30", "31",
857 "spe_acc", "spefscr",
858 /* Soft frame pointer. */
862 #ifdef TARGET_REGNAMES
863 static const char alt_reg_names[][8] =
865 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
866 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
867 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
868 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
869 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
870 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
871 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
872 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
873 "mq", "lr", "ctr", "ap",
874 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
876 /* AltiVec registers. */
877 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
878 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
879 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
880 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
883 "spe_acc", "spefscr",
884 /* Soft frame pointer. */
889 #ifndef MASK_STRICT_ALIGN
890 #define MASK_STRICT_ALIGN 0
892 #ifndef TARGET_PROFILE_KERNEL
893 #define TARGET_PROFILE_KERNEL 0
896 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
897 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
899 /* Initialize the GCC target structure. */
900 #undef TARGET_ATTRIBUTE_TABLE
901 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
902 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
903 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
905 #undef TARGET_ASM_ALIGNED_DI_OP
906 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
908 /* Default unaligned ops are only provided for ELF. Find the ops needed
909 for non-ELF systems. */
910 #ifndef OBJECT_FORMAT_ELF
912 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
914 #undef TARGET_ASM_UNALIGNED_HI_OP
915 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
916 #undef TARGET_ASM_UNALIGNED_SI_OP
917 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
918 #undef TARGET_ASM_UNALIGNED_DI_OP
919 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
922 #undef TARGET_ASM_UNALIGNED_HI_OP
923 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
924 #undef TARGET_ASM_UNALIGNED_SI_OP
925 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
926 #undef TARGET_ASM_UNALIGNED_DI_OP
927 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
928 #undef TARGET_ASM_ALIGNED_DI_OP
929 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
933 /* This hook deals with fixups for relocatable code and DI-mode objects
935 #undef TARGET_ASM_INTEGER
936 #define TARGET_ASM_INTEGER rs6000_assemble_integer
938 #ifdef HAVE_GAS_HIDDEN
939 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
940 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
943 #undef TARGET_HAVE_TLS
944 #define TARGET_HAVE_TLS HAVE_AS_TLS
946 #undef TARGET_CANNOT_FORCE_CONST_MEM
947 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
949 #undef TARGET_ASM_FUNCTION_PROLOGUE
950 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
951 #undef TARGET_ASM_FUNCTION_EPILOGUE
952 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
954 #undef TARGET_SCHED_VARIABLE_ISSUE
955 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
957 #undef TARGET_SCHED_ISSUE_RATE
958 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
959 #undef TARGET_SCHED_ADJUST_COST
960 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
961 #undef TARGET_SCHED_ADJUST_PRIORITY
962 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
963 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
964 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
965 #undef TARGET_SCHED_INIT
966 #define TARGET_SCHED_INIT rs6000_sched_init
967 #undef TARGET_SCHED_FINISH
968 #define TARGET_SCHED_FINISH rs6000_sched_finish
969 #undef TARGET_SCHED_REORDER
970 #define TARGET_SCHED_REORDER rs6000_sched_reorder
971 #undef TARGET_SCHED_REORDER2
972 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
974 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
975 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
977 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
978 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
980 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
981 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
982 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
983 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
984 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
985 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
986 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
987 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
989 #undef TARGET_INIT_BUILTINS
990 #define TARGET_INIT_BUILTINS rs6000_init_builtins
992 #undef TARGET_EXPAND_BUILTIN
993 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
995 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
996 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
998 #undef TARGET_INIT_LIBFUNCS
999 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1002 #undef TARGET_BINDS_LOCAL_P
1003 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1006 #undef TARGET_MS_BITFIELD_LAYOUT_P
1007 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1009 #undef TARGET_ASM_OUTPUT_MI_THUNK
1010 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1012 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1013 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1015 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1016 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1018 #undef TARGET_INVALID_WITHIN_DOLOOP
1019 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1021 #undef TARGET_RTX_COSTS
1022 #define TARGET_RTX_COSTS rs6000_rtx_costs
1023 #undef TARGET_ADDRESS_COST
1024 #define TARGET_ADDRESS_COST hook_int_rtx_0
1026 #undef TARGET_VECTOR_OPAQUE_P
1027 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1029 #undef TARGET_DWARF_REGISTER_SPAN
1030 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1032 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1033 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1035 /* On rs6000, function arguments are promoted, as are function return
1037 #undef TARGET_PROMOTE_FUNCTION_ARGS
1038 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1039 #undef TARGET_PROMOTE_FUNCTION_RETURN
1040 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1042 #undef TARGET_RETURN_IN_MEMORY
1043 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1045 #undef TARGET_SETUP_INCOMING_VARARGS
1046 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1048 /* Always strict argument naming on rs6000. */
1049 #undef TARGET_STRICT_ARGUMENT_NAMING
1050 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1051 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1052 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1053 #undef TARGET_SPLIT_COMPLEX_ARG
1054 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1055 #undef TARGET_MUST_PASS_IN_STACK
1056 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1057 #undef TARGET_PASS_BY_REFERENCE
1058 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1059 #undef TARGET_ARG_PARTIAL_BYTES
1060 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1062 #undef TARGET_BUILD_BUILTIN_VA_LIST
1063 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1065 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1066 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1068 #undef TARGET_EH_RETURN_FILTER_MODE
1069 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1071 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1072 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1074 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1075 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1077 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1078 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1080 #undef TARGET_HANDLE_OPTION
1081 #define TARGET_HANDLE_OPTION rs6000_handle_option
1083 #undef TARGET_DEFAULT_TARGET_FLAGS
1084 #define TARGET_DEFAULT_TARGET_FLAGS \
1087 #undef TARGET_STACK_PROTECT_FAIL
1088 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1090 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1091 The PowerPC architecture requires only weak consistency among
1092 processors--that is, memory accesses between processors need not be
1093 sequentially consistent and memory accesses among processors can occur
1094 in any order. The ability to order memory accesses weakly provides
1095 opportunities for more efficient use of the system bus. Unless a
1096 dependency exists, the 604e allows read operations to precede store
1098 #undef TARGET_RELAXED_ORDERING
1099 #define TARGET_RELAXED_ORDERING true
1102 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1103 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1106 /* Use a 32-bit anchor range. This leads to sequences like:
1108 addis tmp,anchor,high
1111 where tmp itself acts as an anchor, and can be shared between
1112 accesses to the same 64k page. */
1113 #undef TARGET_MIN_ANCHOR_OFFSET
1114 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1115 #undef TARGET_MAX_ANCHOR_OFFSET
1116 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1117 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1118 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1120 struct gcc_target targetm = TARGET_INITIALIZER;
1123 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1126 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1128 /* The GPRs can hold any mode, but values bigger than one register
1129 cannot go past R31. */
1130 if (INT_REGNO_P (regno))
1131 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1133 /* The float registers can only hold floating modes and DImode.
1134 This excludes the 32-bit decimal float mode for now. */
1135 if (FP_REGNO_P (regno))
1137 (SCALAR_FLOAT_MODE_P (mode)
1138 && (mode != TDmode || (regno % 2) == 0)
1140 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1141 || (GET_MODE_CLASS (mode) == MODE_INT
1142 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1144 /* The CR register can only hold CC modes. */
1145 if (CR_REGNO_P (regno))
1146 return GET_MODE_CLASS (mode) == MODE_CC;
1148 if (XER_REGNO_P (regno))
1149 return mode == PSImode;
1151 /* AltiVec only in AldyVec registers. */
1152 if (ALTIVEC_REGNO_P (regno))
1153 return ALTIVEC_VECTOR_MODE (mode);
1155 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1156 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1159 /* We cannot put TImode anywhere except general register and it must be
1160 able to fit within the register set. */
1162 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1165 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1167 rs6000_init_hard_regno_mode_ok (void)
1171 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1172 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1173 if (rs6000_hard_regno_mode_ok (r, m))
1174 rs6000_hard_regno_mode_ok_p[m][r] = true;
1178 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1181 darwin_rs6000_override_options (void)
1183 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1185 rs6000_altivec_abi = 1;
1186 TARGET_ALTIVEC_VRSAVE = 1;
1187 if (DEFAULT_ABI == ABI_DARWIN)
1189 if (MACHO_DYNAMIC_NO_PIC_P)
1192 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1195 else if (flag_pic == 1)
1200 if (TARGET_64BIT && ! TARGET_POWERPC64)
1202 target_flags |= MASK_POWERPC64;
1203 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1207 rs6000_default_long_calls = 1;
1208 target_flags |= MASK_SOFT_FLOAT;
1211 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1213 if (!flag_mkernel && !flag_apple_kext
1215 && ! (target_flags_explicit & MASK_ALTIVEC))
1216 target_flags |= MASK_ALTIVEC;
1218 /* Unless the user (not the configurer) has explicitly overridden
1219 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1220 G4 unless targetting the kernel. */
1223 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1224 && ! (target_flags_explicit & MASK_ALTIVEC)
1225 && ! rs6000_select[1].string)
1227 target_flags |= MASK_ALTIVEC;
1232 /* If not otherwise specified by a target, make 'long double' equivalent to
1235 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1236 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1239 /* Override command line options. Mostly we process the processor
1240 type and sometimes adjust other TARGET_ options. */
1243 rs6000_override_options (const char *default_cpu)
1246 struct rs6000_cpu_select *ptr;
1249 /* Simplifications for entries below. */
1252 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1253 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1256 /* This table occasionally claims that a processor does not support
1257 a particular feature even though it does, but the feature is slower
1258 than the alternative. Thus, it shouldn't be relied on as a
1259 complete description of the processor's support.
1261 Please keep this list in order, and don't forget to update the
1262 documentation in invoke.texi when adding a new processor or
1266 const char *const name; /* Canonical processor name. */
1267 const enum processor_type processor; /* Processor type enum value. */
1268 const int target_enable; /* Target flags to enable. */
1269 } const processor_target_table[]
1270 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1271 {"403", PROCESSOR_PPC403,
1272 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1273 {"405", PROCESSOR_PPC405,
1274 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1275 {"405fp", PROCESSOR_PPC405,
1276 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1277 {"440", PROCESSOR_PPC440,
1278 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1279 {"440fp", PROCESSOR_PPC440,
1280 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1281 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1282 {"601", PROCESSOR_PPC601,
1283 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1284 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1285 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1286 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1287 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1288 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1289 {"620", PROCESSOR_PPC620,
1290 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1291 {"630", PROCESSOR_PPC630,
1292 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1293 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1294 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1295 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1296 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1297 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1298 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1299 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1300 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1301 /* 8548 has a dummy entry for now. */
1302 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1303 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1304 {"970", PROCESSOR_POWER4,
1305 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1306 {"cell", PROCESSOR_CELL,
1307 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1308 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1309 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1310 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1311 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1312 {"G5", PROCESSOR_POWER4,
1313 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1314 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1315 {"power2", PROCESSOR_POWER,
1316 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1317 {"power3", PROCESSOR_PPC630,
1318 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1319 {"power4", PROCESSOR_POWER4,
1320 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1321 {"power5", PROCESSOR_POWER5,
1322 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1323 | MASK_MFCRF | MASK_POPCNTB},
1324 {"power5+", PROCESSOR_POWER5,
1325 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1326 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1327 {"power6", PROCESSOR_POWER6,
1328 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1329 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1330 {"power6x", PROCESSOR_POWER6,
1331 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1332 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1333 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1334 {"powerpc64", PROCESSOR_POWERPC64,
1335 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1336 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1337 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1338 {"rios2", PROCESSOR_RIOS2,
1339 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1340 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1341 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1342 {"rs64", PROCESSOR_RS64A,
1343 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1346 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1348 /* Some OSs don't support saving the high part of 64-bit registers on
1349 context switch. Other OSs don't support saving Altivec registers.
1350 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1351 settings; if the user wants either, the user must explicitly specify
1352 them and we won't interfere with the user's specification. */
1355 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1356 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1357 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1358 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1359 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1362 rs6000_init_hard_regno_mode_ok ();
1364 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1365 #ifdef OS_MISSING_POWERPC64
1366 if (OS_MISSING_POWERPC64)
1367 set_masks &= ~MASK_POWERPC64;
1369 #ifdef OS_MISSING_ALTIVEC
1370 if (OS_MISSING_ALTIVEC)
1371 set_masks &= ~MASK_ALTIVEC;
1374 /* Don't override by the processor default if given explicitly. */
1375 set_masks &= ~target_flags_explicit;
1377 /* Identify the processor type. */
1378 rs6000_select[0].string = default_cpu;
1379 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1381 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1383 ptr = &rs6000_select[i];
1384 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1386 for (j = 0; j < ptt_size; j++)
1387 if (! strcmp (ptr->string, processor_target_table[j].name))
1389 if (ptr->set_tune_p)
1390 rs6000_cpu = processor_target_table[j].processor;
1392 if (ptr->set_arch_p)
1394 target_flags &= ~set_masks;
1395 target_flags |= (processor_target_table[j].target_enable
1402 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1409 /* If we are optimizing big endian systems for space, use the load/store
1410 multiple and string instructions. */
1411 if (BYTES_BIG_ENDIAN && optimize_size)
1412 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1414 /* Don't allow -mmultiple or -mstring on little endian systems
1415 unless the cpu is a 750, because the hardware doesn't support the
1416 instructions used in little endian mode, and causes an alignment
1417 trap. The 750 does not cause an alignment trap (except when the
1418 target is unaligned). */
1420 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1422 if (TARGET_MULTIPLE)
1424 target_flags &= ~MASK_MULTIPLE;
1425 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1426 warning (0, "-mmultiple is not supported on little endian systems");
1431 target_flags &= ~MASK_STRING;
1432 if ((target_flags_explicit & MASK_STRING) != 0)
1433 warning (0, "-mstring is not supported on little endian systems");
1437 /* Set debug flags */
1438 if (rs6000_debug_name)
1440 if (! strcmp (rs6000_debug_name, "all"))
1441 rs6000_debug_stack = rs6000_debug_arg = 1;
1442 else if (! strcmp (rs6000_debug_name, "stack"))
1443 rs6000_debug_stack = 1;
1444 else if (! strcmp (rs6000_debug_name, "arg"))
1445 rs6000_debug_arg = 1;
1447 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1450 if (rs6000_traceback_name)
1452 if (! strncmp (rs6000_traceback_name, "full", 4))
1453 rs6000_traceback = traceback_full;
1454 else if (! strncmp (rs6000_traceback_name, "part", 4))
1455 rs6000_traceback = traceback_part;
1456 else if (! strncmp (rs6000_traceback_name, "no", 2))
1457 rs6000_traceback = traceback_none;
1459 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1460 rs6000_traceback_name);
1463 if (!rs6000_explicit_options.long_double)
1464 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1466 #ifndef POWERPC_LINUX
1467 if (!rs6000_explicit_options.ieee)
1468 rs6000_ieeequad = 1;
1471 /* Set Altivec ABI as default for powerpc64 linux. */
1472 if (TARGET_ELF && TARGET_64BIT)
1474 rs6000_altivec_abi = 1;
1475 TARGET_ALTIVEC_VRSAVE = 1;
1478 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1479 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1481 rs6000_darwin64_abi = 1;
1483 darwin_one_byte_bool = 1;
1485 /* Default to natural alignment, for better performance. */
1486 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1489 /* Place FP constants in the constant pool instead of TOC
1490 if section anchors enabled. */
1491 if (flag_section_anchors)
1492 TARGET_NO_FP_IN_TOC = 1;
1494 /* Handle -mtls-size option. */
1495 rs6000_parse_tls_size_option ();
1497 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1498 SUBTARGET_OVERRIDE_OPTIONS;
1500 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1501 SUBSUBTARGET_OVERRIDE_OPTIONS;
1503 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1504 SUB3TARGET_OVERRIDE_OPTIONS;
1509 /* The e500 does not have string instructions, and we set
1510 MASK_STRING above when optimizing for size. */
1511 if ((target_flags & MASK_STRING) != 0)
1512 target_flags = target_flags & ~MASK_STRING;
1514 else if (rs6000_select[1].string != NULL)
1516 /* For the powerpc-eabispe configuration, we set all these by
1517 default, so let's unset them if we manually set another
1518 CPU that is not the E500. */
1519 if (!rs6000_explicit_options.abi)
1521 if (!rs6000_explicit_options.spe)
1523 if (!rs6000_explicit_options.float_gprs)
1524 rs6000_float_gprs = 0;
1525 if (!rs6000_explicit_options.isel)
1529 /* Detect invalid option combinations with E500. */
1532 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1533 && rs6000_cpu != PROCESSOR_POWER5
1534 && rs6000_cpu != PROCESSOR_POWER6
1535 && rs6000_cpu != PROCESSOR_CELL);
1536 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1537 || rs6000_cpu == PROCESSOR_POWER5);
1538 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1539 || rs6000_cpu == PROCESSOR_POWER5
1540 || rs6000_cpu == PROCESSOR_POWER6);
1542 rs6000_sched_restricted_insns_priority
1543 = (rs6000_sched_groups ? 1 : 0);
1545 /* Handle -msched-costly-dep option. */
1546 rs6000_sched_costly_dep
1547 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1549 if (rs6000_sched_costly_dep_str)
1551 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1552 rs6000_sched_costly_dep = no_dep_costly;
1553 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1554 rs6000_sched_costly_dep = all_deps_costly;
1555 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1556 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1557 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1558 rs6000_sched_costly_dep = store_to_load_dep_costly;
1560 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1563 /* Handle -minsert-sched-nops option. */
1564 rs6000_sched_insert_nops
1565 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1567 if (rs6000_sched_insert_nops_str)
1569 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1570 rs6000_sched_insert_nops = sched_finish_none;
1571 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1572 rs6000_sched_insert_nops = sched_finish_pad_groups;
1573 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1574 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1576 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1579 #ifdef TARGET_REGNAMES
1580 /* If the user desires alternate register names, copy in the
1581 alternate names now. */
1582 if (TARGET_REGNAMES)
1583 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1586 /* Set aix_struct_return last, after the ABI is determined.
1587 If -maix-struct-return or -msvr4-struct-return was explicitly
1588 used, don't override with the ABI default. */
1589 if (!rs6000_explicit_options.aix_struct_ret)
1590 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1592 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1593 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1596 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1598 /* We can only guarantee the availability of DI pseudo-ops when
1599 assembling for 64-bit targets. */
1602 targetm.asm_out.aligned_op.di = NULL;
1603 targetm.asm_out.unaligned_op.di = NULL;
1606 /* Set branch target alignment, if not optimizing for size. */
1609 /* Cell wants to be aligned 8byte for dual issue. */
1610 if (rs6000_cpu == PROCESSOR_CELL)
1612 if (align_functions <= 0)
1613 align_functions = 8;
1614 if (align_jumps <= 0)
1616 if (align_loops <= 0)
1619 if (rs6000_align_branch_targets)
1621 if (align_functions <= 0)
1622 align_functions = 16;
1623 if (align_jumps <= 0)
1625 if (align_loops <= 0)
1628 if (align_jumps_max_skip <= 0)
1629 align_jumps_max_skip = 15;
1630 if (align_loops_max_skip <= 0)
1631 align_loops_max_skip = 15;
1634 /* Arrange to save and restore machine status around nested functions. */
1635 init_machine_status = rs6000_init_machine_status;
1637 /* We should always be splitting complex arguments, but we can't break
1638 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1639 if (DEFAULT_ABI != ABI_AIX)
1640 targetm.calls.split_complex_arg = NULL;
1642 /* Initialize rs6000_cost with the appropriate target costs. */
1644 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1648 case PROCESSOR_RIOS1:
1649 rs6000_cost = &rios1_cost;
1652 case PROCESSOR_RIOS2:
1653 rs6000_cost = &rios2_cost;
1656 case PROCESSOR_RS64A:
1657 rs6000_cost = &rs64a_cost;
1660 case PROCESSOR_MPCCORE:
1661 rs6000_cost = &mpccore_cost;
1664 case PROCESSOR_PPC403:
1665 rs6000_cost = &ppc403_cost;
1668 case PROCESSOR_PPC405:
1669 rs6000_cost = &ppc405_cost;
1672 case PROCESSOR_PPC440:
1673 rs6000_cost = &ppc440_cost;
1676 case PROCESSOR_PPC601:
1677 rs6000_cost = &ppc601_cost;
1680 case PROCESSOR_PPC603:
1681 rs6000_cost = &ppc603_cost;
1684 case PROCESSOR_PPC604:
1685 rs6000_cost = &ppc604_cost;
1688 case PROCESSOR_PPC604e:
1689 rs6000_cost = &ppc604e_cost;
1692 case PROCESSOR_PPC620:
1693 rs6000_cost = &ppc620_cost;
1696 case PROCESSOR_PPC630:
1697 rs6000_cost = &ppc630_cost;
1700 case PROCESSOR_CELL:
1701 rs6000_cost = &ppccell_cost;
1704 case PROCESSOR_PPC750:
1705 case PROCESSOR_PPC7400:
1706 rs6000_cost = &ppc750_cost;
1709 case PROCESSOR_PPC7450:
1710 rs6000_cost = &ppc7450_cost;
1713 case PROCESSOR_PPC8540:
1714 rs6000_cost = &ppc8540_cost;
1717 case PROCESSOR_POWER4:
1718 case PROCESSOR_POWER5:
1719 rs6000_cost = &power4_cost;
1722 case PROCESSOR_POWER6:
1723 rs6000_cost = &power6_cost;
1731 /* Implement targetm.vectorize.builtin_mask_for_load. */
1733 rs6000_builtin_mask_for_load (void)
1736 return altivec_builtin_mask_for_load;
1741 /* Implement targetm.vectorize.builtin_conversion. */
1743 rs6000_builtin_conversion (enum tree_code code, tree type)
1745 if (!TARGET_ALTIVEC)
1751 switch (TYPE_MODE (type))
1754 return TYPE_UNSIGNED (type) ?
1755 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1756 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1765 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1767 rs6000_builtin_mul_widen_even (tree type)
1769 if (!TARGET_ALTIVEC)
1772 switch (TYPE_MODE (type))
1775 return TYPE_UNSIGNED (type) ?
1776 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1777 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1780 return TYPE_UNSIGNED (type) ?
1781 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1782 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1788 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1790 rs6000_builtin_mul_widen_odd (tree type)
1792 if (!TARGET_ALTIVEC)
1795 switch (TYPE_MODE (type))
1798 return TYPE_UNSIGNED (type) ?
1799 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1800 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1803 return TYPE_UNSIGNED (type) ?
1804 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1805 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1811 /* Handle generic options of the form -mfoo=yes/no.
1812 NAME is the option name.
1813 VALUE is the option value.
1814 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1815 whether the option value is 'yes' or 'no' respectively. */
1817 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1821 else if (!strcmp (value, "yes"))
1823 else if (!strcmp (value, "no"))
1826 error ("unknown -m%s= option specified: '%s'", name, value);
1829 /* Validate and record the size specified with the -mtls-size option. */
1832 rs6000_parse_tls_size_option (void)
1834 if (rs6000_tls_size_string == 0)
1836 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1837 rs6000_tls_size = 16;
1838 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1839 rs6000_tls_size = 32;
1840 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1841 rs6000_tls_size = 64;
1843 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1847 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1849 if (DEFAULT_ABI == ABI_DARWIN)
1850 /* The Darwin libraries never set errno, so we might as well
1851 avoid calling them when that's the only reason we would. */
1852 flag_errno_math = 0;
1854 /* Double growth factor to counter reduced min jump length. */
1855 set_param_value ("max-grow-copy-bb-insns", 16);
1857 /* Enable section anchors by default.
1858 Skip section anchors for Objective C and Objective C++
1859 until front-ends fixed. */
1860 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1861 flag_section_anchors = 1;
1864 /* Implement TARGET_HANDLE_OPTION. */
1867 rs6000_handle_option (size_t code, const char *arg, int value)
1872 target_flags &= ~(MASK_POWER | MASK_POWER2
1873 | MASK_MULTIPLE | MASK_STRING);
1874 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1875 | MASK_MULTIPLE | MASK_STRING);
1877 case OPT_mno_powerpc:
1878 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1879 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1880 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1881 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1884 target_flags &= ~MASK_MINIMAL_TOC;
1885 TARGET_NO_FP_IN_TOC = 0;
1886 TARGET_NO_SUM_IN_TOC = 0;
1887 target_flags_explicit |= MASK_MINIMAL_TOC;
1888 #ifdef TARGET_USES_SYSV4_OPT
1889 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1890 just the same as -mminimal-toc. */
1891 target_flags |= MASK_MINIMAL_TOC;
1892 target_flags_explicit |= MASK_MINIMAL_TOC;
1896 #ifdef TARGET_USES_SYSV4_OPT
1898 /* Make -mtoc behave like -mminimal-toc. */
1899 target_flags |= MASK_MINIMAL_TOC;
1900 target_flags_explicit |= MASK_MINIMAL_TOC;
1904 #ifdef TARGET_USES_AIX64_OPT
1909 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1910 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1911 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1914 #ifdef TARGET_USES_AIX64_OPT
1919 target_flags &= ~MASK_POWERPC64;
1920 target_flags_explicit |= MASK_POWERPC64;
1923 case OPT_minsert_sched_nops_:
1924 rs6000_sched_insert_nops_str = arg;
1927 case OPT_mminimal_toc:
1930 TARGET_NO_FP_IN_TOC = 0;
1931 TARGET_NO_SUM_IN_TOC = 0;
1938 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1939 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1946 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1947 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1951 case OPT_mpowerpc_gpopt:
1952 case OPT_mpowerpc_gfxopt:
1955 target_flags |= MASK_POWERPC;
1956 target_flags_explicit |= MASK_POWERPC;
1960 case OPT_maix_struct_return:
1961 case OPT_msvr4_struct_return:
1962 rs6000_explicit_options.aix_struct_ret = true;
1966 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1970 rs6000_explicit_options.isel = true;
1971 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1975 rs6000_explicit_options.spe = true;
1976 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1980 rs6000_debug_name = arg;
1983 #ifdef TARGET_USES_SYSV4_OPT
1985 rs6000_abi_name = arg;
1989 rs6000_sdata_name = arg;
1992 case OPT_mtls_size_:
1993 rs6000_tls_size_string = arg;
1996 case OPT_mrelocatable:
1999 target_flags |= MASK_MINIMAL_TOC;
2000 target_flags_explicit |= MASK_MINIMAL_TOC;
2001 TARGET_NO_FP_IN_TOC = 1;
2005 case OPT_mrelocatable_lib:
2008 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2009 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2010 TARGET_NO_FP_IN_TOC = 1;
2014 target_flags &= ~MASK_RELOCATABLE;
2015 target_flags_explicit |= MASK_RELOCATABLE;
2021 if (!strcmp (arg, "altivec"))
2023 rs6000_explicit_options.abi = true;
2024 rs6000_altivec_abi = 1;
2027 else if (! strcmp (arg, "no-altivec"))
2029 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2030 the default for rs6000_spe_abi to be chosen later. */
2031 rs6000_altivec_abi = 0;
2033 else if (! strcmp (arg, "spe"))
2035 rs6000_explicit_options.abi = true;
2037 rs6000_altivec_abi = 0;
2038 if (!TARGET_SPE_ABI)
2039 error ("not configured for ABI: '%s'", arg);
2041 else if (! strcmp (arg, "no-spe"))
2043 rs6000_explicit_options.abi = true;
2047 /* These are here for testing during development only, do not
2048 document in the manual please. */
2049 else if (! strcmp (arg, "d64"))
2051 rs6000_darwin64_abi = 1;
2052 warning (0, "Using darwin64 ABI");
2054 else if (! strcmp (arg, "d32"))
2056 rs6000_darwin64_abi = 0;
2057 warning (0, "Using old darwin ABI");
2060 else if (! strcmp (arg, "ibmlongdouble"))
2062 rs6000_explicit_options.ieee = true;
2063 rs6000_ieeequad = 0;
2064 warning (0, "Using IBM extended precision long double");
2066 else if (! strcmp (arg, "ieeelongdouble"))
2068 rs6000_explicit_options.ieee = true;
2069 rs6000_ieeequad = 1;
2070 warning (0, "Using IEEE extended precision long double");
2075 error ("unknown ABI specified: '%s'", arg);
2081 rs6000_select[1].string = arg;
2085 rs6000_select[2].string = arg;
2088 case OPT_mtraceback_:
2089 rs6000_traceback_name = arg;
2092 case OPT_mfloat_gprs_:
2093 rs6000_explicit_options.float_gprs = true;
2094 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2095 rs6000_float_gprs = 1;
2096 else if (! strcmp (arg, "double"))
2097 rs6000_float_gprs = 2;
2098 else if (! strcmp (arg, "no"))
2099 rs6000_float_gprs = 0;
2102 error ("invalid option for -mfloat-gprs: '%s'", arg);
2107 case OPT_mlong_double_:
2108 rs6000_explicit_options.long_double = true;
2109 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2110 if (value != 64 && value != 128)
2112 error ("Unknown switch -mlong-double-%s", arg);
2113 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2117 rs6000_long_double_type_size = value;
2120 case OPT_msched_costly_dep_:
2121 rs6000_sched_costly_dep_str = arg;
2125 rs6000_explicit_options.alignment = true;
2126 if (! strcmp (arg, "power"))
2128 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2129 some C library functions, so warn about it. The flag may be
2130 useful for performance studies from time to time though, so
2131 don't disable it entirely. */
2132 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2133 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2134 " it is incompatible with the installed C and C++ libraries");
2135 rs6000_alignment_flags = MASK_ALIGN_POWER;
2137 else if (! strcmp (arg, "natural"))
2138 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2141 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2149 /* Do anything needed at the start of the asm file. */
2152 rs6000_file_start (void)
2156 const char *start = buffer;
2157 struct rs6000_cpu_select *ptr;
2158 const char *default_cpu = TARGET_CPU_DEFAULT;
2159 FILE *file = asm_out_file;
2161 default_file_start ();
2163 #ifdef TARGET_BI_ARCH
2164 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2168 if (flag_verbose_asm)
2170 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2171 rs6000_select[0].string = default_cpu;
2173 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2175 ptr = &rs6000_select[i];
2176 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2178 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2183 if (PPC405_ERRATUM77)
2185 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2189 #ifdef USING_ELFOS_H
2190 switch (rs6000_sdata)
2192 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2193 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2194 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2195 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2198 if (rs6000_sdata && g_switch_value)
2200 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2210 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2212 switch_to_section (toc_section);
2213 switch_to_section (text_section);
2218 /* Return nonzero if this function is known to have a null epilogue. */
2221 direct_return (void)
2223 if (reload_completed)
2225 rs6000_stack_t *info = rs6000_stack_info ();
2227 if (info->first_gp_reg_save == 32
2228 && info->first_fp_reg_save == 64
2229 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2230 && ! info->lr_save_p
2231 && ! info->cr_save_p
2232 && info->vrsave_mask == 0
2240 /* Return the number of instructions it takes to form a constant in an
2241 integer register. */
2244 num_insns_constant_wide (HOST_WIDE_INT value)
2246 /* signed constant loadable with {cal|addi} */
2247 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2250 /* constant loadable with {cau|addis} */
2251 else if ((value & 0xffff) == 0
2252 && (value >> 31 == -1 || value >> 31 == 0))
2255 #if HOST_BITS_PER_WIDE_INT == 64
2256 else if (TARGET_POWERPC64)
2258 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2259 HOST_WIDE_INT high = value >> 31;
2261 if (high == 0 || high == -1)
2267 return num_insns_constant_wide (high) + 1;
2269 return (num_insns_constant_wide (high)
2270 + num_insns_constant_wide (low) + 1);
2279 num_insns_constant (rtx op, enum machine_mode mode)
2281 HOST_WIDE_INT low, high;
2283 switch (GET_CODE (op))
2286 #if HOST_BITS_PER_WIDE_INT == 64
2287 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2288 && mask64_operand (op, mode))
2292 return num_insns_constant_wide (INTVAL (op));
2300 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2301 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2302 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2305 if (mode == VOIDmode || mode == DImode)
2307 high = CONST_DOUBLE_HIGH (op);
2308 low = CONST_DOUBLE_LOW (op);
2315 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2316 if (DECIMAL_FLOAT_MODE_P (mode))
2317 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2319 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2320 high = l[WORDS_BIG_ENDIAN == 0];
2321 low = l[WORDS_BIG_ENDIAN != 0];
2325 return (num_insns_constant_wide (low)
2326 + num_insns_constant_wide (high));
2329 if ((high == 0 && low >= 0)
2330 || (high == -1 && low < 0))
2331 return num_insns_constant_wide (low);
2333 else if (mask64_operand (op, mode))
2337 return num_insns_constant_wide (high) + 1;
2340 return (num_insns_constant_wide (high)
2341 + num_insns_constant_wide (low) + 1);
2349 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2350 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2351 corresponding element of the vector, but for V4SFmode and V2SFmode,
2352 the corresponding "float" is interpreted as an SImode integer. */
2354 static HOST_WIDE_INT
2355 const_vector_elt_as_int (rtx op, unsigned int elt)
2357 rtx tmp = CONST_VECTOR_ELT (op, elt);
2358 if (GET_MODE (op) == V4SFmode
2359 || GET_MODE (op) == V2SFmode)
2360 tmp = gen_lowpart (SImode, tmp);
2361 return INTVAL (tmp);
2364 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2365 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2366 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2367 all items are set to the same value and contain COPIES replicas of the
2368 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2369 operand and the others are set to the value of the operand's msb. */
2372 vspltis_constant (rtx op, unsigned step, unsigned copies)
2374 enum machine_mode mode = GET_MODE (op);
2375 enum machine_mode inner = GET_MODE_INNER (mode);
2378 unsigned nunits = GET_MODE_NUNITS (mode);
2379 unsigned bitsize = GET_MODE_BITSIZE (inner);
2380 unsigned mask = GET_MODE_MASK (inner);
2382 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2383 HOST_WIDE_INT splat_val = val;
2384 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2386 /* Construct the value to be splatted, if possible. If not, return 0. */
2387 for (i = 2; i <= copies; i *= 2)
2389 HOST_WIDE_INT small_val;
2391 small_val = splat_val >> bitsize;
2393 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2395 splat_val = small_val;
2398 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2399 if (EASY_VECTOR_15 (splat_val))
2402 /* Also check if we can splat, and then add the result to itself. Do so if
2403 the value is positive, of if the splat instruction is using OP's mode;
2404 for splat_val < 0, the splat and the add should use the same mode. */
2405 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2406 && (splat_val >= 0 || (step == 1 && copies == 1)))
2412 /* Check if VAL is present in every STEP-th element, and the
2413 other elements are filled with its most significant bit. */
2414 for (i = 0; i < nunits - 1; ++i)
2416 HOST_WIDE_INT desired_val;
2417 if (((i + 1) & (step - 1)) == 0)
2420 desired_val = msb_val;
2422 if (desired_val != const_vector_elt_as_int (op, i))
2430 /* Return true if OP is of the given MODE and can be synthesized
2431 with a vspltisb, vspltish or vspltisw. */
2434 easy_altivec_constant (rtx op, enum machine_mode mode)
2436 unsigned step, copies;
2438 if (mode == VOIDmode)
2439 mode = GET_MODE (op);
2440 else if (mode != GET_MODE (op))
2443 /* Start with a vspltisw. */
2444 step = GET_MODE_NUNITS (mode) / 4;
2447 if (vspltis_constant (op, step, copies))
2450 /* Then try with a vspltish. */
2456 if (vspltis_constant (op, step, copies))
2459 /* And finally a vspltisb. */
2465 if (vspltis_constant (op, step, copies))
2471 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2472 result is OP. Abort if it is not possible. */
2475 gen_easy_altivec_constant (rtx op)
2477 enum machine_mode mode = GET_MODE (op);
2478 int nunits = GET_MODE_NUNITS (mode);
2479 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2480 unsigned step = nunits / 4;
2481 unsigned copies = 1;
2483 /* Start with a vspltisw. */
2484 if (vspltis_constant (op, step, copies))
2485 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2487 /* Then try with a vspltish. */
2493 if (vspltis_constant (op, step, copies))
2494 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2496 /* And finally a vspltisb. */
2502 if (vspltis_constant (op, step, copies))
2503 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2509 output_vec_const_move (rtx *operands)
2512 enum machine_mode mode;
2517 mode = GET_MODE (dest);
2522 if (zero_constant (vec, mode))
2523 return "vxor %0,%0,%0";
2525 splat_vec = gen_easy_altivec_constant (vec);
2526 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2527 operands[1] = XEXP (splat_vec, 0);
2528 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2531 switch (GET_MODE (splat_vec))
2534 return "vspltisw %0,%1";
2537 return "vspltish %0,%1";
2540 return "vspltisb %0,%1";
2547 gcc_assert (TARGET_SPE);
2549 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2550 pattern of V1DI, V4HI, and V2SF.
2552 FIXME: We should probably return # and add post reload
2553 splitters for these, but this way is so easy ;-). */
2554 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2555 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2556 operands[1] = CONST_VECTOR_ELT (vec, 0);
2557 operands[2] = CONST_VECTOR_ELT (vec, 1);
2559 return "li %0,%1\n\tevmergelo %0,%0,%0";
2561 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2564 /* Initialize vector TARGET to VALS. */
2567 rs6000_expand_vector_init (rtx target, rtx vals)
2569 enum machine_mode mode = GET_MODE (target);
2570 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2571 int n_elts = GET_MODE_NUNITS (mode);
2572 int n_var = 0, one_var = -1;
2573 bool all_same = true, all_const_zero = true;
2577 for (i = 0; i < n_elts; ++i)
2579 x = XVECEXP (vals, 0, i);
2580 if (!CONSTANT_P (x))
2581 ++n_var, one_var = i;
2582 else if (x != CONST0_RTX (inner_mode))
2583 all_const_zero = false;
2585 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2591 if (mode != V4SFmode && all_const_zero)
2593 /* Zero register. */
2594 emit_insn (gen_rtx_SET (VOIDmode, target,
2595 gen_rtx_XOR (mode, target, target)));
2598 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2600 /* Splat immediate. */
2601 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2605 ; /* Splat vector element. */
2608 /* Load from constant pool. */
2609 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2614 /* Store value to stack temp. Load vector element. Splat. */
2617 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2618 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2619 XVECEXP (vals, 0, 0));
2620 x = gen_rtx_UNSPEC (VOIDmode,
2621 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2622 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2624 gen_rtx_SET (VOIDmode,
2627 x = gen_rtx_VEC_SELECT (inner_mode, target,
2628 gen_rtx_PARALLEL (VOIDmode,
2629 gen_rtvec (1, const0_rtx)));
2630 emit_insn (gen_rtx_SET (VOIDmode, target,
2631 gen_rtx_VEC_DUPLICATE (mode, x)));
2635 /* One field is non-constant. Load constant then overwrite
2639 rtx copy = copy_rtx (vals);
2641 /* Load constant part of vector, substitute neighboring value for
2643 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2644 rs6000_expand_vector_init (target, copy);
2646 /* Insert variable. */
2647 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2651 /* Construct the vector in memory one field at a time
2652 and load the whole vector. */
2653 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2654 for (i = 0; i < n_elts; i++)
2655 emit_move_insn (adjust_address_nv (mem, inner_mode,
2656 i * GET_MODE_SIZE (inner_mode)),
2657 XVECEXP (vals, 0, i));
2658 emit_move_insn (target, mem);
2661 /* Set field ELT of TARGET to VAL. */
2664 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2666 enum machine_mode mode = GET_MODE (target);
2667 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2668 rtx reg = gen_reg_rtx (mode);
2670 int width = GET_MODE_SIZE (inner_mode);
2673 /* Load single variable value. */
2674 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2675 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2676 x = gen_rtx_UNSPEC (VOIDmode,
2677 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2678 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2680 gen_rtx_SET (VOIDmode,
2684 /* Linear sequence. */
2685 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2686 for (i = 0; i < 16; ++i)
2687 XVECEXP (mask, 0, i) = GEN_INT (i);
2689 /* Set permute mask to insert element into target. */
2690 for (i = 0; i < width; ++i)
2691 XVECEXP (mask, 0, elt*width + i)
2692 = GEN_INT (i + 0x10);
2693 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2694 x = gen_rtx_UNSPEC (mode,
2695 gen_rtvec (3, target, reg,
2696 force_reg (V16QImode, x)),
2698 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2701 /* Extract field ELT from VEC into TARGET. */
2704 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2706 enum machine_mode mode = GET_MODE (vec);
2707 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2710 /* Allocate mode-sized buffer. */
2711 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2713 /* Add offset to field within buffer matching vector element. */
2714 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2716 /* Store single field into mode-sized buffer. */
2717 x = gen_rtx_UNSPEC (VOIDmode,
2718 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2719 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2721 gen_rtx_SET (VOIDmode,
2724 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2727 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2728 implement ANDing by the mask IN. */
2730 build_mask64_2_operands (rtx in, rtx *out)
2732 #if HOST_BITS_PER_WIDE_INT >= 64
2733 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2736 gcc_assert (GET_CODE (in) == CONST_INT);
2741 /* Assume c initially something like 0x00fff000000fffff. The idea
2742 is to rotate the word so that the middle ^^^^^^ group of zeros
2743 is at the MS end and can be cleared with an rldicl mask. We then
2744 rotate back and clear off the MS ^^ group of zeros with a
2746 c = ~c; /* c == 0xff000ffffff00000 */
2747 lsb = c & -c; /* lsb == 0x0000000000100000 */
2748 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2749 c = ~c; /* c == 0x00fff000000fffff */
2750 c &= -lsb; /* c == 0x00fff00000000000 */
2751 lsb = c & -c; /* lsb == 0x0000100000000000 */
2752 c = ~c; /* c == 0xff000fffffffffff */
2753 c &= -lsb; /* c == 0xff00000000000000 */
2755 while ((lsb >>= 1) != 0)
2756 shift++; /* shift == 44 on exit from loop */
2757 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2758 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2759 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2763 /* Assume c initially something like 0xff000f0000000000. The idea
2764 is to rotate the word so that the ^^^ middle group of zeros
2765 is at the LS end and can be cleared with an rldicr mask. We then
2766 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2768 lsb = c & -c; /* lsb == 0x0000010000000000 */
2769 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2770 c = ~c; /* c == 0x00fff0ffffffffff */
2771 c &= -lsb; /* c == 0x00fff00000000000 */
2772 lsb = c & -c; /* lsb == 0x0000100000000000 */
2773 c = ~c; /* c == 0xff000fffffffffff */
2774 c &= -lsb; /* c == 0xff00000000000000 */
2776 while ((lsb >>= 1) != 0)
2777 shift++; /* shift == 44 on exit from loop */
2778 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2779 m1 >>= shift; /* m1 == 0x0000000000000fff */
2780 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2783 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2784 masks will be all 1's. We are guaranteed more than one transition. */
2785 out[0] = GEN_INT (64 - shift);
2786 out[1] = GEN_INT (m1);
2787 out[2] = GEN_INT (shift);
2788 out[3] = GEN_INT (m2);
2796 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2799 invalid_e500_subreg (rtx op, enum machine_mode mode)
2801 if (TARGET_E500_DOUBLE)
2803 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2804 subreg:TI and reg:TF. */
2805 if (GET_CODE (op) == SUBREG
2806 && (mode == SImode || mode == DImode || mode == TImode)
2807 && REG_P (SUBREG_REG (op))
2808 && (GET_MODE (SUBREG_REG (op)) == DFmode
2809 || GET_MODE (SUBREG_REG (op)) == TFmode))
2812 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2814 if (GET_CODE (op) == SUBREG
2815 && (mode == DFmode || mode == TFmode)
2816 && REG_P (SUBREG_REG (op))
2817 && (GET_MODE (SUBREG_REG (op)) == DImode
2818 || GET_MODE (SUBREG_REG (op)) == TImode))
2823 && GET_CODE (op) == SUBREG
2825 && REG_P (SUBREG_REG (op))
2826 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2832 /* AIX increases natural record alignment to doubleword if the first
2833 field is an FP double while the FP fields remain word aligned. */
2836 rs6000_special_round_type_align (tree type, unsigned int computed,
2837 unsigned int specified)
2839 unsigned int align = MAX (computed, specified);
2840 tree field = TYPE_FIELDS (type);
2842 /* Skip all non field decls */
2843 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2844 field = TREE_CHAIN (field);
2846 if (field != NULL && field != type)
2848 type = TREE_TYPE (field);
2849 while (TREE_CODE (type) == ARRAY_TYPE)
2850 type = TREE_TYPE (type);
2852 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2853 align = MAX (align, 64);
2859 /* Darwin increases record alignment to the natural alignment of
2863 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
2864 unsigned int specified)
2866 unsigned int align = MAX (computed, specified);
2868 if (TYPE_PACKED (type))
2871 /* Find the first field, looking down into aggregates. */
2873 tree field = TYPE_FIELDS (type);
2874 /* Skip all non field decls */
2875 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2876 field = TREE_CHAIN (field);
2879 type = TREE_TYPE (field);
2880 while (TREE_CODE (type) == ARRAY_TYPE)
2881 type = TREE_TYPE (type);
2882 } while (AGGREGATE_TYPE_P (type));
2884 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
2885 align = MAX (align, TYPE_ALIGN (type));
2890 /* Return 1 for an operand in small memory on V.4/eabi. */
2893 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2894 enum machine_mode mode ATTRIBUTE_UNUSED)
2899 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2902 if (DEFAULT_ABI != ABI_V4)
2905 if (GET_CODE (op) == SYMBOL_REF)
2908 else if (GET_CODE (op) != CONST
2909 || GET_CODE (XEXP (op, 0)) != PLUS
2910 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2911 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2916 rtx sum = XEXP (op, 0);
2917 HOST_WIDE_INT summand;
2919 /* We have to be careful here, because it is the referenced address
2920 that must be 32k from _SDA_BASE_, not just the symbol. */
2921 summand = INTVAL (XEXP (sum, 1));
2922 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2925 sym_ref = XEXP (sum, 0);
2928 return SYMBOL_REF_SMALL_P (sym_ref);
2934 /* Return true if either operand is a general purpose register. */
2937 gpr_or_gpr_p (rtx op0, rtx op1)
2939 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2940 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2944 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2947 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2949 switch (GET_CODE (op))
2952 if (RS6000_SYMBOL_REF_TLS_P (op))
2954 else if (CONSTANT_POOL_ADDRESS_P (op))
2956 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2964 else if (! strcmp (XSTR (op, 0), toc_label_name))
2973 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2974 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2976 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2985 constant_pool_expr_p (rtx op)
2989 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2993 toc_relative_expr_p (rtx op)
2997 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3001 legitimate_constant_pool_address_p (rtx x)
3004 && GET_CODE (x) == PLUS
3005 && GET_CODE (XEXP (x, 0)) == REG
3006 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3007 && constant_pool_expr_p (XEXP (x, 1)));
3011 legitimate_small_data_p (enum machine_mode mode, rtx x)
3013 return (DEFAULT_ABI == ABI_V4
3014 && !flag_pic && !TARGET_TOC
3015 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3016 && small_data_operand (x, mode));
3019 /* SPE offset addressing is limited to 5-bits worth of double words. */
3020 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3023 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3025 unsigned HOST_WIDE_INT offset, extra;
3027 if (GET_CODE (x) != PLUS)
3029 if (GET_CODE (XEXP (x, 0)) != REG)
3031 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3033 if (legitimate_constant_pool_address_p (x))
3035 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3038 offset = INTVAL (XEXP (x, 1));
3046 /* AltiVec vector modes. Only reg+reg addressing is valid and
3047 constant offset zero should not occur due to canonicalization.
3048 Allow any offset when not strict before reload. */
3055 /* SPE vector modes. */
3056 return SPE_CONST_OFFSET_OK (offset);
3060 if (TARGET_E500_DOUBLE)
3061 return SPE_CONST_OFFSET_OK (offset);
3064 /* On e500v2, we may have:
3066 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3068 Which gets addressed with evldd instructions. */
3069 if (TARGET_E500_DOUBLE)
3070 return SPE_CONST_OFFSET_OK (offset);
3072 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3074 else if (offset & 3)
3079 if (TARGET_E500_DOUBLE)
3080 return (SPE_CONST_OFFSET_OK (offset)
3081 && SPE_CONST_OFFSET_OK (offset + 8));
3085 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3087 else if (offset & 3)
3098 return (offset < 0x10000) && (offset + extra < 0x10000);
3102 legitimate_indexed_address_p (rtx x, int strict)
3106 if (GET_CODE (x) != PLUS)
3112 /* Recognize the rtl generated by reload which we know will later be
3113 replaced with proper base and index regs. */
3115 && reload_in_progress
3116 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3120 return (REG_P (op0) && REG_P (op1)
3121 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3122 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3123 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3124 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3128 legitimate_indirect_address_p (rtx x, int strict)
3130 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3134 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3136 if (!TARGET_MACHO || !flag_pic
3137 || mode != SImode || GET_CODE (x) != MEM)
3141 if (GET_CODE (x) != LO_SUM)
3143 if (GET_CODE (XEXP (x, 0)) != REG)
3145 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3149 return CONSTANT_P (x);
3153 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3155 if (GET_CODE (x) != LO_SUM)
3157 if (GET_CODE (XEXP (x, 0)) != REG)
3159 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3161 /* Restrict addressing for DI because of our SUBREG hackery. */
3162 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3167 if (TARGET_ELF || TARGET_MACHO)
3169 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3173 if (GET_MODE_NUNITS (mode) != 1)
3175 if (GET_MODE_BITSIZE (mode) > 64
3176 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3177 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3180 return CONSTANT_P (x);
3187 /* Try machine-dependent ways of modifying an illegitimate address
3188 to be legitimate. If we find one, return the new, valid address.
3189 This is used from only one place: `memory_address' in explow.c.
3191 OLDX is the address as it was before break_out_memory_refs was
3192 called. In some cases it is useful to look at this to decide what
3195 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3197 It is always safe for this function to do nothing. It exists to
3198 recognize opportunities to optimize the output.
3200 On RS/6000, first check for the sum of a register with a constant
3201 integer that is out of range. If so, generate code to add the
3202 constant with the low-order 16 bits masked to the register and force
3203 this result into another register (this can be done with `cau').
3204 Then generate an address of REG+(CONST&0xffff), allowing for the
3205 possibility of bit 16 being a one.
3207 Then check for the sum of a register and something not constant, try to
3208 load the other things into a register and return the sum. */
3211 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3212 enum machine_mode mode)
3214 if (GET_CODE (x) == SYMBOL_REF)
3216 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3218 return rs6000_legitimize_tls_address (x, model);
3221 if (GET_CODE (x) == PLUS
3222 && GET_CODE (XEXP (x, 0)) == REG
3223 && GET_CODE (XEXP (x, 1)) == CONST_INT
3224 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3226 HOST_WIDE_INT high_int, low_int;
3228 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3229 high_int = INTVAL (XEXP (x, 1)) - low_int;
3230 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3231 GEN_INT (high_int)), 0);
3232 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3234 else if (GET_CODE (x) == PLUS
3235 && GET_CODE (XEXP (x, 0)) == REG
3236 && GET_CODE (XEXP (x, 1)) != CONST_INT
3237 && GET_MODE_NUNITS (mode) == 1
3238 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3240 || (((mode != DImode && mode != DFmode && mode != DDmode)
3241 || TARGET_E500_DOUBLE)
3242 && mode != TFmode && mode != TDmode))
3243 && (TARGET_POWERPC64 || mode != DImode)
3246 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3247 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3249 else if (ALTIVEC_VECTOR_MODE (mode))
3253 /* Make sure both operands are registers. */
3254 if (GET_CODE (x) == PLUS)
3255 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3256 force_reg (Pmode, XEXP (x, 1)));
3258 reg = force_reg (Pmode, x);
3261 else if (SPE_VECTOR_MODE (mode)
3262 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3263 || mode == DDmode || mode == TDmode
3264 || mode == DImode)))
3268 /* We accept [reg + reg] and [reg + OFFSET]. */
3270 if (GET_CODE (x) == PLUS)
3272 rtx op1 = XEXP (x, 0);
3273 rtx op2 = XEXP (x, 1);
3275 op1 = force_reg (Pmode, op1);
3277 if (GET_CODE (op2) != REG
3278 && (GET_CODE (op2) != CONST_INT
3279 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3280 op2 = force_reg (Pmode, op2);
3282 return gen_rtx_PLUS (Pmode, op1, op2);
3285 return force_reg (Pmode, x);
3291 && GET_CODE (x) != CONST_INT
3292 && GET_CODE (x) != CONST_DOUBLE
3294 && GET_MODE_NUNITS (mode) == 1
3295 && (GET_MODE_BITSIZE (mode) <= 32
3296 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3298 rtx reg = gen_reg_rtx (Pmode);
3299 emit_insn (gen_elf_high (reg, x));
3300 return gen_rtx_LO_SUM (Pmode, reg, x);
3302 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3305 && ! MACHO_DYNAMIC_NO_PIC_P
3307 && GET_CODE (x) != CONST_INT
3308 && GET_CODE (x) != CONST_DOUBLE
3310 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3314 rtx reg = gen_reg_rtx (Pmode);
3315 emit_insn (gen_macho_high (reg, x));
3316 return gen_rtx_LO_SUM (Pmode, reg, x);
3319 && constant_pool_expr_p (x)
3320 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3322 return create_TOC_reference (x);
3328 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3329 We need to emit DTP-relative relocations. */
3332 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3337 fputs ("\t.long\t", file);
3340 fputs (DOUBLE_INT_ASM_OP, file);
3345 output_addr_const (file, x);
3346 fputs ("@dtprel+0x8000", file);
3349 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3351 static GTY(()) rtx rs6000_tls_symbol;
3353 rs6000_tls_get_addr (void)
3355 if (!rs6000_tls_symbol)
3356 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3358 return rs6000_tls_symbol;
3361 /* Construct the SYMBOL_REF for TLS GOT references. */
3363 static GTY(()) rtx rs6000_got_symbol;
3365 rs6000_got_sym (void)
3367 if (!rs6000_got_symbol)
3369 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3370 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3371 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3374 return rs6000_got_symbol;
3377 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3378 this (thread-local) address. */
3381 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3385 dest = gen_reg_rtx (Pmode);
3386 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3392 tlsreg = gen_rtx_REG (Pmode, 13);
3393 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3397 tlsreg = gen_rtx_REG (Pmode, 2);
3398 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3402 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3406 tmp = gen_reg_rtx (Pmode);
3409 tlsreg = gen_rtx_REG (Pmode, 13);
3410 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3414 tlsreg = gen_rtx_REG (Pmode, 2);
3415 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3419 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3421 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3426 rtx r3, got, tga, tmp1, tmp2, eqv;
3428 /* We currently use relocations like @got@tlsgd for tls, which
3429 means the linker will handle allocation of tls entries, placing
3430 them in the .got section. So use a pointer to the .got section,
3431 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3432 or to secondary GOT sections used by 32-bit -fPIC. */
3434 got = gen_rtx_REG (Pmode, 2);
3438 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3441 rtx gsym = rs6000_got_sym ();
3442 got = gen_reg_rtx (Pmode);
3444 rs6000_emit_move (got, gsym, Pmode);
3450 tmp1 = gen_reg_rtx (Pmode);
3451 tmp2 = gen_reg_rtx (Pmode);
3452 tmp3 = gen_reg_rtx (Pmode);
3453 mem = gen_const_mem (Pmode, tmp1);
3455 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3456 emit_move_insn (tmp1,
3457 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
3458 emit_move_insn (tmp2, mem);
3459 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3460 last = emit_move_insn (got, tmp3);
3461 set_unique_reg_note (last, REG_EQUAL, gsym);
3462 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3464 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3470 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3472 r3 = gen_rtx_REG (Pmode, 3);
3474 insn = gen_tls_gd_64 (r3, got, addr);
3476 insn = gen_tls_gd_32 (r3, got, addr);
3479 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3480 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3481 insn = emit_call_insn (insn);
3482 CONST_OR_PURE_CALL_P (insn) = 1;
3483 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3484 insn = get_insns ();
3486 emit_libcall_block (insn, dest, r3, addr);
3488 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3490 r3 = gen_rtx_REG (Pmode, 3);
3492 insn = gen_tls_ld_64 (r3, got);
3494 insn = gen_tls_ld_32 (r3, got);
3497 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3498 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3499 insn = emit_call_insn (insn);
3500 CONST_OR_PURE_CALL_P (insn) = 1;
3501 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3502 insn = get_insns ();
3504 tmp1 = gen_reg_rtx (Pmode);
3505 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3507 emit_libcall_block (insn, tmp1, r3, eqv);
3508 if (rs6000_tls_size == 16)
3511 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3513 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3515 else if (rs6000_tls_size == 32)
3517 tmp2 = gen_reg_rtx (Pmode);
3519 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3521 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3524 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3526 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3530 tmp2 = gen_reg_rtx (Pmode);
3532 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3534 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3536 insn = gen_rtx_SET (Pmode, dest,
3537 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3543 /* IE, or 64-bit offset LE. */
3544 tmp2 = gen_reg_rtx (Pmode);
3546 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3548 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3551 insn = gen_tls_tls_64 (dest, tmp2, addr);
3553 insn = gen_tls_tls_32 (dest, tmp2, addr);
3561 /* Return 1 if X contains a thread-local symbol. */
3564 rs6000_tls_referenced_p (rtx x)
3566 if (! TARGET_HAVE_TLS)
3569 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3572 /* Return 1 if *X is a thread-local symbol. This is the same as
3573 rs6000_tls_symbol_ref except for the type of the unused argument. */
3576 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3578 return RS6000_SYMBOL_REF_TLS_P (*x);
3581 /* The convention appears to be to define this wherever it is used.
3582 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3583 is now used here. */
3584 #ifndef REG_MODE_OK_FOR_BASE_P
3585 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3588 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3589 replace the input X, or the original X if no replacement is called for.
3590 The output parameter *WIN is 1 if the calling macro should goto WIN,
3593 For RS/6000, we wish to handle large displacements off a base
3594 register by splitting the addend across an addiu/addis and the mem insn.
3595 This cuts number of extra insns needed from 3 to 1.
3597 On Darwin, we use this to generate code for floating point constants.
3598 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3599 The Darwin code is inside #if TARGET_MACHO because only then is
3600 machopic_function_base_name() defined. */
3602 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3603 int opnum, int type,
3604 int ind_levels ATTRIBUTE_UNUSED, int *win)
3606 /* We must recognize output that we have already generated ourselves. */
3607 if (GET_CODE (x) == PLUS
3608 && GET_CODE (XEXP (x, 0)) == PLUS
3609 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3610 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3611 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3613 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3614 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3615 opnum, (enum reload_type)type);
3621 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3622 && GET_CODE (x) == LO_SUM
3623 && GET_CODE (XEXP (x, 0)) == PLUS
3624 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3625 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3626 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3627 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3628 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3629 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3630 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3632 /* Result of previous invocation of this function on Darwin
3633 floating point constant. */
3634 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3635 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3636 opnum, (enum reload_type)type);
3642 /* Force ld/std non-word aligned offset into base register by wrapping
3644 if (GET_CODE (x) == PLUS
3645 && GET_CODE (XEXP (x, 0)) == REG
3646 && REGNO (XEXP (x, 0)) < 32
3647 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3648 && GET_CODE (XEXP (x, 1)) == CONST_INT
3649 && (INTVAL (XEXP (x, 1)) & 3) != 0
3650 && !ALTIVEC_VECTOR_MODE (mode)
3651 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3652 && TARGET_POWERPC64)
3654 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3655 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3656 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3657 opnum, (enum reload_type) type);
3662 if (GET_CODE (x) == PLUS
3663 && GET_CODE (XEXP (x, 0)) == REG
3664 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3665 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3666 && GET_CODE (XEXP (x, 1)) == CONST_INT
3667 && !SPE_VECTOR_MODE (mode)
3668 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3670 && !ALTIVEC_VECTOR_MODE (mode))
3672 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3673 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3675 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3677 /* Check for 32-bit overflow. */
3678 if (high + low != val)
3684 /* Reload the high part into a base reg; leave the low part
3685 in the mem directly. */
3687 x = gen_rtx_PLUS (GET_MODE (x),
3688 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3692 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3693 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3694 opnum, (enum reload_type)type);
3699 if (GET_CODE (x) == SYMBOL_REF
3700 && !ALTIVEC_VECTOR_MODE (mode)
3701 && !SPE_VECTOR_MODE (mode)
3703 && DEFAULT_ABI == ABI_DARWIN
3704 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3706 && DEFAULT_ABI == ABI_V4
3709 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3710 The same goes for DImode without 64-bit gprs and DFmode
3714 && (mode != DImode || TARGET_POWERPC64)
3715 && (mode != DFmode || TARGET_POWERPC64
3716 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3721 rtx offset = gen_rtx_CONST (Pmode,
3722 gen_rtx_MINUS (Pmode, x,
3723 machopic_function_base_sym ()));
3724 x = gen_rtx_LO_SUM (GET_MODE (x),
3725 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3726 gen_rtx_HIGH (Pmode, offset)), offset);
3730 x = gen_rtx_LO_SUM (GET_MODE (x),
3731 gen_rtx_HIGH (Pmode, x), x);
3733 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3734 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3735 opnum, (enum reload_type)type);
3740 /* Reload an offset address wrapped by an AND that represents the
3741 masking of the lower bits. Strip the outer AND and let reload
3742 convert the offset address into an indirect address. */
3744 && ALTIVEC_VECTOR_MODE (mode)
3745 && GET_CODE (x) == AND
3746 && GET_CODE (XEXP (x, 0)) == PLUS
3747 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3748 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3749 && GET_CODE (XEXP (x, 1)) == CONST_INT
3750 && INTVAL (XEXP (x, 1)) == -16)
3758 && constant_pool_expr_p (x)
3759 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3761 x = create_TOC_reference (x);
3769 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3770 that is a valid memory address for an instruction.
3771 The MODE argument is the machine mode for the MEM expression
3772 that wants to use this address.
3774 On the RS/6000, there are four valid address: a SYMBOL_REF that
3775 refers to a constant pool entry of an address (or the sum of it
3776 plus a constant), a short (16-bit signed) constant plus a register,
3777 the sum of two registers, or a register indirect, possibly with an
3778 auto-increment. For DFmode and DImode with a constant plus register,
3779 we must ensure that both words are addressable or PowerPC64 with offset
3782 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3783 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3784 because adjacent memory cells are accessed by adding word-sized offsets
3785 during assembly output. */
3787 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3789 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3791 && ALTIVEC_VECTOR_MODE (mode)
3792 && GET_CODE (x) == AND
3793 && GET_CODE (XEXP (x, 1)) == CONST_INT
3794 && INTVAL (XEXP (x, 1)) == -16)
3797 if (RS6000_SYMBOL_REF_TLS_P (x))
3799 if (legitimate_indirect_address_p (x, reg_ok_strict))
3801 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3802 && !ALTIVEC_VECTOR_MODE (mode)
3803 && !SPE_VECTOR_MODE (mode)
3806 /* Restrict addressing for DI because of our SUBREG hackery. */
3807 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3810 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3812 if (legitimate_small_data_p (mode, x))
3814 if (legitimate_constant_pool_address_p (x))
3816 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3818 && GET_CODE (x) == PLUS
3819 && GET_CODE (XEXP (x, 0)) == REG
3820 && (XEXP (x, 0) == virtual_stack_vars_rtx
3821 || XEXP (x, 0) == arg_pointer_rtx)
3822 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3824 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3829 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3831 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3832 && (TARGET_POWERPC64 || mode != DImode)
3833 && legitimate_indexed_address_p (x, reg_ok_strict))
3835 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3840 /* Go to LABEL if ADDR (a legitimate address expression)
3841 has an effect that depends on the machine mode it is used for.
3843 On the RS/6000 this is true of all integral offsets (since AltiVec
3844 modes don't allow them) or is a pre-increment or decrement.
3846 ??? Except that due to conceptual problems in offsettable_address_p
3847 we can't really report the problems of integral offsets. So leave
3848 this assuming that the adjustable offset must be valid for the
3849 sub-words of a TFmode operand, which is what we had before. */
3852 rs6000_mode_dependent_address (rtx addr)
3854 switch (GET_CODE (addr))
3857 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3859 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3860 return val + 12 + 0x8000 >= 0x10000;
3867 /* Auto-increment cases are now treated generically in recog.c. */
3876 /* More elaborate version of recog's offsettable_memref_p predicate
3877 that works around the ??? note of rs6000_mode_dependent_address.
3878 In particular it accepts
3880 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3882 in 32-bit mode, that the recog predicate rejects. */
3885 rs6000_offsettable_memref_p (rtx op)
3890 /* First mimic offsettable_memref_p. */
3891 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3894 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3895 the latter predicate knows nothing about the mode of the memory
3896 reference and, therefore, assumes that it is the largest supported
3897 mode (TFmode). As a consequence, legitimate offsettable memory
3898 references are rejected. rs6000_legitimate_offset_address_p contains
3899 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3900 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3903 /* Return number of consecutive hard regs needed starting at reg REGNO
3904 to hold something of mode MODE.
3905 This is ordinarily the length in words of a value of mode MODE
3906 but can be less for certain modes in special long registers.
3908 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3909 scalar instructions. The upper 32 bits are only available to the
3912 POWER and PowerPC GPRs hold 32 bits worth;
3913 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3916 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3918 if (FP_REGNO_P (regno))
3919 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3921 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3922 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3924 if (ALTIVEC_REGNO_P (regno))
3926 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3928 /* The value returned for SCmode in the E500 double case is 2 for
3929 ABI compatibility; storing an SCmode value in a single register
3930 would require function_arg and rs6000_spe_function_arg to handle
3931 SCmode so as to pass the value correctly in a pair of
3933 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
3934 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3936 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3939 /* Change register usage conditional on target flags. */
3941 rs6000_conditional_register_usage (void)
3945 /* Set MQ register fixed (already call_used) if not POWER
3946 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3951 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3953 fixed_regs[13] = call_used_regs[13]
3954 = call_really_used_regs[13] = 1;
3956 /* Conditionally disable FPRs. */
3957 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3958 for (i = 32; i < 64; i++)
3959 fixed_regs[i] = call_used_regs[i]
3960 = call_really_used_regs[i] = 1;
3962 /* The TOC register is not killed across calls in a way that is
3963 visible to the compiler. */
3964 if (DEFAULT_ABI == ABI_AIX)
3965 call_really_used_regs[2] = 0;
3967 if (DEFAULT_ABI == ABI_V4
3968 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3970 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3972 if (DEFAULT_ABI == ABI_V4
3973 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3975 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3976 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3977 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3979 if (DEFAULT_ABI == ABI_DARWIN
3980 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3981 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3982 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3983 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3985 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3986 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3987 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3990 global_regs[VSCR_REGNO] = 1;
3994 global_regs[SPEFSCR_REGNO] = 1;
3995 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
3996 registers in prologues and epilogues. We no longer use r14
3997 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
3998 pool for link-compatibility with older versions of GCC. Once
3999 "old" code has died out, we can return r14 to the allocation
4002 = call_used_regs[14]
4003 = call_really_used_regs[14] = 1;
4006 if (! TARGET_ALTIVEC)
4008 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4009 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4010 call_really_used_regs[VRSAVE_REGNO] = 1;
4013 if (TARGET_ALTIVEC_ABI)
4014 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4015 call_used_regs[i] = call_really_used_regs[i] = 1;
4018 /* Try to output insns to set TARGET equal to the constant C if it can
4019 be done in less than N insns. Do all computations in MODE.
4020 Returns the place where the output has been placed if it can be
4021 done and the insns have been emitted. If it would take more than N
4022 insns, zero is returned and no insns and emitted. */
4025 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4026 rtx source, int n ATTRIBUTE_UNUSED)
4028 rtx result, insn, set;
4029 HOST_WIDE_INT c0, c1;
4036 dest = gen_reg_rtx (mode);
4037 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4041 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4043 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4044 GEN_INT (INTVAL (source)
4045 & (~ (HOST_WIDE_INT) 0xffff))));
4046 emit_insn (gen_rtx_SET (VOIDmode, dest,
4047 gen_rtx_IOR (SImode, copy_rtx (result),
4048 GEN_INT (INTVAL (source) & 0xffff))));
4053 switch (GET_CODE (source))
4056 c0 = INTVAL (source);
4061 #if HOST_BITS_PER_WIDE_INT >= 64
4062 c0 = CONST_DOUBLE_LOW (source);
4065 c0 = CONST_DOUBLE_LOW (source);
4066 c1 = CONST_DOUBLE_HIGH (source);
4074 result = rs6000_emit_set_long_const (dest, c0, c1);
4081 insn = get_last_insn ();
4082 set = single_set (insn);
4083 if (! CONSTANT_P (SET_SRC (set)))
4084 set_unique_reg_note (insn, REG_EQUAL, source);
4089 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4090 fall back to a straight forward decomposition. We do this to avoid
4091 exponential run times encountered when looking for longer sequences
4092 with rs6000_emit_set_const. */
4094 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4096 if (!TARGET_POWERPC64)
4098 rtx operand1, operand2;
4100 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4102 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4104 emit_move_insn (operand1, GEN_INT (c1));
4105 emit_move_insn (operand2, GEN_INT (c2));
4109 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4112 ud2 = (c1 & 0xffff0000) >> 16;
4113 #if HOST_BITS_PER_WIDE_INT >= 64
4117 ud4 = (c2 & 0xffff0000) >> 16;
4119 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4120 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4123 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4125 emit_move_insn (dest, GEN_INT (ud1));
4128 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4129 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4132 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4135 emit_move_insn (dest, GEN_INT (ud2 << 16));
4137 emit_move_insn (copy_rtx (dest),
4138 gen_rtx_IOR (DImode, copy_rtx (dest),
4141 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4142 || (ud4 == 0 && ! (ud3 & 0x8000)))
4145 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4148 emit_move_insn (dest, GEN_INT (ud3 << 16));
4151 emit_move_insn (copy_rtx (dest),
4152 gen_rtx_IOR (DImode, copy_rtx (dest),
4154 emit_move_insn (copy_rtx (dest),
4155 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4158 emit_move_insn (copy_rtx (dest),
4159 gen_rtx_IOR (DImode, copy_rtx (dest),
4165 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4168 emit_move_insn (dest, GEN_INT (ud4 << 16));
4171 emit_move_insn (copy_rtx (dest),
4172 gen_rtx_IOR (DImode, copy_rtx (dest),
4175 emit_move_insn (copy_rtx (dest),
4176 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4179 emit_move_insn (copy_rtx (dest),
4180 gen_rtx_IOR (DImode, copy_rtx (dest),
4181 GEN_INT (ud2 << 16)));
4183 emit_move_insn (copy_rtx (dest),
4184 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4190 /* Helper for the following. Get rid of [r+r] memory refs
4191 in cases where it won't work (TImode, TFmode, TDmode). */
4194 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4196 if (GET_CODE (operands[0]) == MEM
4197 && GET_CODE (XEXP (operands[0], 0)) != REG
4198 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4199 && ! reload_in_progress)
4201 = replace_equiv_address (operands[0],
4202 copy_addr_to_reg (XEXP (operands[0], 0)));
4204 if (GET_CODE (operands[1]) == MEM
4205 && GET_CODE (XEXP (operands[1], 0)) != REG
4206 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4207 && ! reload_in_progress)
4209 = replace_equiv_address (operands[1],
4210 copy_addr_to_reg (XEXP (operands[1], 0)));
4213 /* Emit a move from SOURCE to DEST in mode MODE. */
4215 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4219 operands[1] = source;
4221 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4222 if (GET_CODE (operands[1]) == CONST_DOUBLE
4223 && ! FLOAT_MODE_P (mode)
4224 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4226 /* FIXME. This should never happen. */
4227 /* Since it seems that it does, do the safe thing and convert
4229 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4231 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4232 || FLOAT_MODE_P (mode)
4233 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4234 || CONST_DOUBLE_LOW (operands[1]) < 0)
4235 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4236 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4238 /* Check if GCC is setting up a block move that will end up using FP
4239 registers as temporaries. We must make sure this is acceptable. */
4240 if (GET_CODE (operands[0]) == MEM
4241 && GET_CODE (operands[1]) == MEM
4243 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4244 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4245 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4246 ? 32 : MEM_ALIGN (operands[0])))
4247 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4249 : MEM_ALIGN (operands[1]))))
4250 && ! MEM_VOLATILE_P (operands [0])
4251 && ! MEM_VOLATILE_P (operands [1]))
4253 emit_move_insn (adjust_address (operands[0], SImode, 0),
4254 adjust_address (operands[1], SImode, 0));
4255 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4256 adjust_address (copy_rtx (operands[1]), SImode, 4));
4260 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
4261 && !gpc_reg_operand (operands[1], mode))
4262 operands[1] = force_reg (mode, operands[1]);
4264 if (mode == SFmode && ! TARGET_POWERPC
4265 && TARGET_HARD_FLOAT && TARGET_FPRS
4266 && GET_CODE (operands[0]) == MEM)
4270 if (reload_in_progress || reload_completed)
4271 regnum = true_regnum (operands[1]);
4272 else if (GET_CODE (operands[1]) == REG)
4273 regnum = REGNO (operands[1]);
4277 /* If operands[1] is a register, on POWER it may have
4278 double-precision data in it, so truncate it to single
4280 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4283 newreg = (no_new_pseudos ? copy_rtx (operands[1])
4284 : gen_reg_rtx (mode));
4285 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4286 operands[1] = newreg;
4290 /* Recognize the case where operand[1] is a reference to thread-local
4291 data and load its address to a register. */
4292 if (rs6000_tls_referenced_p (operands[1]))
4294 enum tls_model model;
4295 rtx tmp = operands[1];
4298 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4300 addend = XEXP (XEXP (tmp, 0), 1);
4301 tmp = XEXP (XEXP (tmp, 0), 0);
4304 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4305 model = SYMBOL_REF_TLS_MODEL (tmp);
4306 gcc_assert (model != 0);
4308 tmp = rs6000_legitimize_tls_address (tmp, model);
4311 tmp = gen_rtx_PLUS (mode, tmp, addend);
4312 tmp = force_operand (tmp, operands[0]);
4317 /* Handle the case where reload calls us with an invalid address. */
4318 if (reload_in_progress && mode == Pmode
4319 && (! general_operand (operands[1], mode)
4320 || ! nonimmediate_operand (operands[0], mode)))
4323 /* 128-bit constant floating-point values on Darwin should really be
4324 loaded as two parts. */
4325 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4326 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4328 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4329 know how to get a DFmode SUBREG of a TFmode. */
4330 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4331 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4332 simplify_gen_subreg (imode, operands[1], mode, 0),
4334 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4335 GET_MODE_SIZE (imode)),
4336 simplify_gen_subreg (imode, operands[1], mode,
4337 GET_MODE_SIZE (imode)),
4342 /* FIXME: In the long term, this switch statement should go away
4343 and be replaced by a sequence of tests based on things like
4349 if (CONSTANT_P (operands[1])
4350 && GET_CODE (operands[1]) != CONST_INT)
4351 operands[1] = force_const_mem (mode, operands[1]);
4356 rs6000_eliminate_indexed_memrefs (operands);
4362 if (CONSTANT_P (operands[1])
4363 && ! easy_fp_constant (operands[1], mode))
4364 operands[1] = force_const_mem (mode, operands[1]);
4375 if (CONSTANT_P (operands[1])
4376 && !easy_vector_constant (operands[1], mode))
4377 operands[1] = force_const_mem (mode, operands[1]);
4382 /* Use default pattern for address of ELF small data */
4385 && DEFAULT_ABI == ABI_V4
4386 && (GET_CODE (operands[1]) == SYMBOL_REF
4387 || GET_CODE (operands[1]) == CONST)
4388 && small_data_operand (operands[1], mode))
4390 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4394 if (DEFAULT_ABI == ABI_V4
4395 && mode == Pmode && mode == SImode
4396 && flag_pic == 1 && got_operand (operands[1], mode))
4398 emit_insn (gen_movsi_got (operands[0], operands[1]));
4402 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4406 && CONSTANT_P (operands[1])
4407 && GET_CODE (operands[1]) != HIGH
4408 && GET_CODE (operands[1]) != CONST_INT)
4410 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4412 /* If this is a function address on -mcall-aixdesc,
4413 convert it to the address of the descriptor. */
4414 if (DEFAULT_ABI == ABI_AIX
4415 && GET_CODE (operands[1]) == SYMBOL_REF
4416 && XSTR (operands[1], 0)[0] == '.')
4418 const char *name = XSTR (operands[1], 0);
4420 while (*name == '.')
4422 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4423 CONSTANT_POOL_ADDRESS_P (new_ref)
4424 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4425 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4426 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4427 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4428 operands[1] = new_ref;
4431 if (DEFAULT_ABI == ABI_DARWIN)
4434 if (MACHO_DYNAMIC_NO_PIC_P)
4436 /* Take care of any required data indirection. */
4437 operands[1] = rs6000_machopic_legitimize_pic_address (
4438 operands[1], mode, operands[0]);
4439 if (operands[0] != operands[1])
4440 emit_insn (gen_rtx_SET (VOIDmode,
4441 operands[0], operands[1]));
4445 emit_insn (gen_macho_high (target, operands[1]));
4446 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4450 emit_insn (gen_elf_high (target, operands[1]));
4451 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4455 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4456 and we have put it in the TOC, we just need to make a TOC-relative
4459 && GET_CODE (operands[1]) == SYMBOL_REF
4460 && constant_pool_expr_p (operands[1])
4461 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4462 get_pool_mode (operands[1])))
4464 operands[1] = create_TOC_reference (operands[1]);
4466 else if (mode == Pmode
4467 && CONSTANT_P (operands[1])
4468 && ((GET_CODE (operands[1]) != CONST_INT
4469 && ! easy_fp_constant (operands[1], mode))
4470 || (GET_CODE (operands[1]) == CONST_INT
4471 && num_insns_constant (operands[1], mode) > 2)
4472 || (GET_CODE (operands[0]) == REG
4473 && FP_REGNO_P (REGNO (operands[0]))))
4474 && GET_CODE (operands[1]) != HIGH
4475 && ! legitimate_constant_pool_address_p (operands[1])
4476 && ! toc_relative_expr_p (operands[1]))
4478 /* Emit a USE operation so that the constant isn't deleted if
4479 expensive optimizations are turned on because nobody
4480 references it. This should only be done for operands that
4481 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4482 This should not be done for operands that contain LABEL_REFs.
4483 For now, we just handle the obvious case. */
4484 if (GET_CODE (operands[1]) != LABEL_REF)
4485 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4488 /* Darwin uses a special PIC legitimizer. */
4489 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4492 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4494 if (operands[0] != operands[1])
4495 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4500 /* If we are to limit the number of things we put in the TOC and
4501 this is a symbol plus a constant we can add in one insn,
4502 just put the symbol in the TOC and add the constant. Don't do
4503 this if reload is in progress. */
4504 if (GET_CODE (operands[1]) == CONST
4505 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4506 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4507 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4508 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4509 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4510 && ! side_effects_p (operands[0]))
4513 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4514 rtx other = XEXP (XEXP (operands[1], 0), 1);
4516 sym = force_reg (mode, sym);
4518 emit_insn (gen_addsi3 (operands[0], sym, other));
4520 emit_insn (gen_adddi3 (operands[0], sym, other));
4524 operands[1] = force_const_mem (mode, operands[1]);
4527 && constant_pool_expr_p (XEXP (operands[1], 0))
4528 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4529 get_pool_constant (XEXP (operands[1], 0)),
4530 get_pool_mode (XEXP (operands[1], 0))))
4533 = gen_const_mem (mode,
4534 create_TOC_reference (XEXP (operands[1], 0)));
4535 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4541 rs6000_eliminate_indexed_memrefs (operands);
4545 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4547 gen_rtx_SET (VOIDmode,
4548 operands[0], operands[1]),
4549 gen_rtx_CLOBBER (VOIDmode,
4550 gen_rtx_SCRATCH (SImode)))));
4559 /* Above, we may have called force_const_mem which may have returned
4560 an invalid address. If we can, fix this up; otherwise, reload will
4561 have to deal with it. */
4562 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4563 operands[1] = validize_mem (operands[1]);
4566 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4569 /* Nonzero if we can use a floating-point register to pass this arg. */
4570 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4571 (SCALAR_FLOAT_MODE_P (MODE) \
4572 && (MODE) != SDmode \
4573 && (CUM)->fregno <= FP_ARG_MAX_REG \
4574 && TARGET_HARD_FLOAT && TARGET_FPRS)
4576 /* Nonzero if we can use an AltiVec register to pass this arg. */
4577 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4578 (ALTIVEC_VECTOR_MODE (MODE) \
4579 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4580 && TARGET_ALTIVEC_ABI \
4583 /* Return a nonzero value to say to return the function value in
4584 memory, just as large structures are always returned. TYPE will be
4585 the data type of the value, and FNTYPE will be the type of the
4586 function doing the returning, or @code{NULL} for libcalls.
4588 The AIX ABI for the RS/6000 specifies that all structures are
4589 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4590 specifies that structures <= 8 bytes are returned in r3/r4, but a
4591 draft put them in memory, and GCC used to implement the draft
4592 instead of the final standard. Therefore, aix_struct_return
4593 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4594 compatibility can change DRAFT_V4_STRUCT_RET to override the
4595 default, and -m switches get the final word. See
4596 rs6000_override_options for more details.
4598 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4599 long double support is enabled. These values are returned in memory.
4601 int_size_in_bytes returns -1 for variable size objects, which go in
4602 memory always. The cast to unsigned makes -1 > 8. */
4605 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4607 /* In the darwin64 abi, try to use registers for larger structs
4609 if (rs6000_darwin64_abi
4610 && TREE_CODE (type) == RECORD_TYPE
4611 && int_size_in_bytes (type) > 0)
4613 CUMULATIVE_ARGS valcum;
4617 valcum.fregno = FP_ARG_MIN_REG;
4618 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4619 /* Do a trial code generation as if this were going to be passed
4620 as an argument; if any part goes in memory, we return NULL. */
4621 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4624 /* Otherwise fall through to more conventional ABI rules. */
4627 if (AGGREGATE_TYPE_P (type)
4628 && (aix_struct_return
4629 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4632 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4633 modes only exist for GCC vector types if -maltivec. */
4634 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4635 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4638 /* Return synthetic vectors in memory. */
4639 if (TREE_CODE (type) == VECTOR_TYPE
4640 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4642 static bool warned_for_return_big_vectors = false;
4643 if (!warned_for_return_big_vectors)
4645 warning (0, "GCC vector returned by reference: "
4646 "non-standard ABI extension with no compatibility guarantee");
4647 warned_for_return_big_vectors = true;
4652 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4658 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4659 for a call to a function whose data type is FNTYPE.
4660 For a library call, FNTYPE is 0.
4662 For incoming args we set the number of arguments in the prototype large
4663 so we never return a PARALLEL. */
4666 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4667 rtx libname ATTRIBUTE_UNUSED, int incoming,
4668 int libcall, int n_named_args)
4670 static CUMULATIVE_ARGS zero_cumulative;
4672 *cum = zero_cumulative;
4674 cum->fregno = FP_ARG_MIN_REG;
4675 cum->vregno = ALTIVEC_ARG_MIN_REG;
4676 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4677 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4678 ? CALL_LIBCALL : CALL_NORMAL);
4679 cum->sysv_gregno = GP_ARG_MIN_REG;
4680 cum->stdarg = fntype
4681 && (TYPE_ARG_TYPES (fntype) != 0
4682 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4683 != void_type_node));
4685 cum->nargs_prototype = 0;
4686 if (incoming || cum->prototype)
4687 cum->nargs_prototype = n_named_args;
4689 /* Check for a longcall attribute. */
4690 if ((!fntype && rs6000_default_long_calls)
4692 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4693 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4694 cum->call_cookie |= CALL_LONG;
4696 if (TARGET_DEBUG_ARG)
4698 fprintf (stderr, "\ninit_cumulative_args:");
4701 tree ret_type = TREE_TYPE (fntype);
4702 fprintf (stderr, " ret code = %s,",
4703 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4706 if (cum->call_cookie & CALL_LONG)
4707 fprintf (stderr, " longcall,");
4709 fprintf (stderr, " proto = %d, nargs = %d\n",
4710 cum->prototype, cum->nargs_prototype);
4715 && TARGET_ALTIVEC_ABI
4716 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4718 error ("cannot return value in vector register because"
4719 " altivec instructions are disabled, use -maltivec"
4724 /* Return true if TYPE must be passed on the stack and not in registers. */
4727 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4729 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4730 return must_pass_in_stack_var_size (mode, type);
4732 return must_pass_in_stack_var_size_or_pad (mode, type);
4735 /* If defined, a C expression which determines whether, and in which
4736 direction, to pad out an argument with extra space. The value
4737 should be of type `enum direction': either `upward' to pad above
4738 the argument, `downward' to pad below, or `none' to inhibit
4741 For the AIX ABI structs are always stored left shifted in their
4745 function_arg_padding (enum machine_mode mode, tree type)
4747 #ifndef AGGREGATE_PADDING_FIXED
4748 #define AGGREGATE_PADDING_FIXED 0
4750 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4751 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4754 if (!AGGREGATE_PADDING_FIXED)
4756 /* GCC used to pass structures of the same size as integer types as
4757 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4758 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4759 passed padded downward, except that -mstrict-align further
4760 muddied the water in that multi-component structures of 2 and 4
4761 bytes in size were passed padded upward.
4763 The following arranges for best compatibility with previous
4764 versions of gcc, but removes the -mstrict-align dependency. */
4765 if (BYTES_BIG_ENDIAN)
4767 HOST_WIDE_INT size = 0;
4769 if (mode == BLKmode)
4771 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4772 size = int_size_in_bytes (type);
4775 size = GET_MODE_SIZE (mode);
4777 if (size == 1 || size == 2 || size == 4)
4783 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4785 if (type != 0 && AGGREGATE_TYPE_P (type))
4789 /* Fall back to the default. */
4790 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4793 /* If defined, a C expression that gives the alignment boundary, in bits,
4794 of an argument with the specified mode and type. If it is not defined,
4795 PARM_BOUNDARY is used for all arguments.
4797 V.4 wants long longs and doubles to be double word aligned. Just
4798 testing the mode size is a boneheaded way to do this as it means
4799 that other types such as complex int are also double word aligned.
4800 However, we're stuck with this because changing the ABI might break
4801 existing library interfaces.
4803 Doubleword align SPE vectors.
4804 Quadword align Altivec vectors.
4805 Quadword align large synthetic vector types. */
4808 function_arg_boundary (enum machine_mode mode, tree type)
4810 if (DEFAULT_ABI == ABI_V4
4811 && (GET_MODE_SIZE (mode) == 8
4812 || (TARGET_HARD_FLOAT
4814 && (mode == TFmode || mode == TDmode))))
4816 else if (SPE_VECTOR_MODE (mode)
4817 || (type && TREE_CODE (type) == VECTOR_TYPE
4818 && int_size_in_bytes (type) >= 8
4819 && int_size_in_bytes (type) < 16))
4821 else if (ALTIVEC_VECTOR_MODE (mode)
4822 || (type && TREE_CODE (type) == VECTOR_TYPE
4823 && int_size_in_bytes (type) >= 16))
4825 else if (rs6000_darwin64_abi && mode == BLKmode
4826 && type && TYPE_ALIGN (type) > 64)
4829 return PARM_BOUNDARY;
4832 /* For a function parm of MODE and TYPE, return the starting word in
4833 the parameter area. NWORDS of the parameter area are already used. */
4836 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4839 unsigned int parm_offset;
4841 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4842 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4843 return nwords + (-(parm_offset + nwords) & align);
4846 /* Compute the size (in words) of a function argument. */
4848 static unsigned long
4849 rs6000_arg_size (enum machine_mode mode, tree type)
4853 if (mode != BLKmode)
4854 size = GET_MODE_SIZE (mode);
4856 size = int_size_in_bytes (type);
4859 return (size + 3) >> 2;
4861 return (size + 7) >> 3;
4864 /* Use this to flush pending int fields. */
4867 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4868 HOST_WIDE_INT bitpos)
4870 unsigned int startbit, endbit;
4871 int intregs, intoffset;
4872 enum machine_mode mode;
4874 if (cum->intoffset == -1)
4877 intoffset = cum->intoffset;
4878 cum->intoffset = -1;
4880 if (intoffset % BITS_PER_WORD != 0)
4882 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4884 if (mode == BLKmode)
4886 /* We couldn't find an appropriate mode, which happens,
4887 e.g., in packed structs when there are 3 bytes to load.
4888 Back intoffset back to the beginning of the word in this
4890 intoffset = intoffset & -BITS_PER_WORD;
4894 startbit = intoffset & -BITS_PER_WORD;
4895 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4896 intregs = (endbit - startbit) / BITS_PER_WORD;
4897 cum->words += intregs;
4900 /* The darwin64 ABI calls for us to recurse down through structs,
4901 looking for elements passed in registers. Unfortunately, we have
4902 to track int register count here also because of misalignments
4903 in powerpc alignment mode. */
4906 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4908 HOST_WIDE_INT startbitpos)
4912 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4913 if (TREE_CODE (f) == FIELD_DECL)
4915 HOST_WIDE_INT bitpos = startbitpos;
4916 tree ftype = TREE_TYPE (f);
4917 enum machine_mode mode;
4918 if (ftype == error_mark_node)
4920 mode = TYPE_MODE (ftype);
4922 if (DECL_SIZE (f) != 0
4923 && host_integerp (bit_position (f), 1))
4924 bitpos += int_bit_position (f);
4926 /* ??? FIXME: else assume zero offset. */
4928 if (TREE_CODE (ftype) == RECORD_TYPE)
4929 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4930 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4932 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4933 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4934 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4936 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4938 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4942 else if (cum->intoffset == -1)
4943 cum->intoffset = bitpos;
4947 /* Update the data in CUM to advance over an argument
4948 of mode MODE and data type TYPE.
4949 (TYPE is null for libcalls where that information may not be available.)
4951 Note that for args passed by reference, function_arg will be called
4952 with MODE and TYPE set to that of the pointer to the arg, not the arg
4956 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4957 tree type, int named, int depth)
4961 /* Only tick off an argument if we're not recursing. */
4963 cum->nargs_prototype--;
4965 if (TARGET_ALTIVEC_ABI
4966 && (ALTIVEC_VECTOR_MODE (mode)
4967 || (type && TREE_CODE (type) == VECTOR_TYPE
4968 && int_size_in_bytes (type) == 16)))
4972 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4975 if (!TARGET_ALTIVEC)
4976 error ("cannot pass argument in vector register because"
4977 " altivec instructions are disabled, use -maltivec"
4980 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4981 even if it is going to be passed in a vector register.
4982 Darwin does the same for variable-argument functions. */
4983 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4984 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4994 /* Vector parameters must be 16-byte aligned. This places
4995 them at 2 mod 4 in terms of words in 32-bit mode, since
4996 the parameter save area starts at offset 24 from the
4997 stack. In 64-bit mode, they just have to start on an
4998 even word, since the parameter save area is 16-byte
4999 aligned. Space for GPRs is reserved even if the argument
5000 will be passed in memory. */
5002 align = (2 - cum->words) & 3;
5004 align = cum->words & 1;
5005 cum->words += align + rs6000_arg_size (mode, type);
5007 if (TARGET_DEBUG_ARG)
5009 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5011 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5012 cum->nargs_prototype, cum->prototype,
5013 GET_MODE_NAME (mode));
5017 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5019 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5022 else if (rs6000_darwin64_abi
5024 && TREE_CODE (type) == RECORD_TYPE
5025 && (size = int_size_in_bytes (type)) > 0)
5027 /* Variable sized types have size == -1 and are
5028 treated as if consisting entirely of ints.
5029 Pad to 16 byte boundary if needed. */
5030 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5031 && (cum->words % 2) != 0)
5033 /* For varargs, we can just go up by the size of the struct. */
5035 cum->words += (size + 7) / 8;
5038 /* It is tempting to say int register count just goes up by
5039 sizeof(type)/8, but this is wrong in a case such as
5040 { int; double; int; } [powerpc alignment]. We have to
5041 grovel through the fields for these too. */
5043 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5044 rs6000_darwin64_record_arg_advance_flush (cum,
5045 size * BITS_PER_UNIT);
5048 else if (DEFAULT_ABI == ABI_V4)
5050 if (TARGET_HARD_FLOAT && TARGET_FPRS
5051 && (mode == SFmode || mode == DFmode
5052 || mode == DDmode || mode == TDmode
5053 || (mode == TFmode && !TARGET_IEEEQUAD)))
5055 /* _Decimal128 must use an even/odd register pair. This assumes
5056 that the register number is odd when fregno is odd. */
5057 if (mode == TDmode && (cum->fregno % 2) == 1)
5060 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5061 <= FP_ARG_V4_MAX_REG)
5062 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5065 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5066 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5067 cum->words += cum->words & 1;
5068 cum->words += rs6000_arg_size (mode, type);
5073 int n_words = rs6000_arg_size (mode, type);
5074 int gregno = cum->sysv_gregno;
5076 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5077 (r7,r8) or (r9,r10). As does any other 2 word item such
5078 as complex int due to a historical mistake. */
5080 gregno += (1 - gregno) & 1;
5082 /* Multi-reg args are not split between registers and stack. */
5083 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5085 /* Long long and SPE vectors are aligned on the stack.
5086 So are other 2 word items such as complex int due to
5087 a historical mistake. */
5089 cum->words += cum->words & 1;
5090 cum->words += n_words;
5093 /* Note: continuing to accumulate gregno past when we've started
5094 spilling to the stack indicates the fact that we've started
5095 spilling to the stack to expand_builtin_saveregs. */
5096 cum->sysv_gregno = gregno + n_words;
5099 if (TARGET_DEBUG_ARG)
5101 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5102 cum->words, cum->fregno);
5103 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5104 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5105 fprintf (stderr, "mode = %4s, named = %d\n",
5106 GET_MODE_NAME (mode), named);
5111 int n_words = rs6000_arg_size (mode, type);
5112 int start_words = cum->words;
5113 int align_words = rs6000_parm_start (mode, type, start_words);
5115 cum->words = align_words + n_words;
5117 if (SCALAR_FLOAT_MODE_P (mode)
5119 && TARGET_HARD_FLOAT && TARGET_FPRS)
5121 /* _Decimal128 must be passed in an even/odd float register pair.
5122 This assumes that the register number is odd when fregno is
5124 if (mode == TDmode && (cum->fregno % 2) == 1)
5126 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5129 if (TARGET_DEBUG_ARG)
5131 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5132 cum->words, cum->fregno);
5133 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5134 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5135 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5136 named, align_words - start_words, depth);
5142 spe_build_register_parallel (enum machine_mode mode, int gregno)
5149 r1 = gen_rtx_REG (DImode, gregno);
5150 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5151 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5155 r1 = gen_rtx_REG (DImode, gregno);
5156 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5157 r3 = gen_rtx_REG (DImode, gregno + 2);
5158 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5159 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5162 r1 = gen_rtx_REG (DImode, gregno);
5163 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5164 r3 = gen_rtx_REG (DImode, gregno + 2);
5165 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5166 r5 = gen_rtx_REG (DImode, gregno + 4);
5167 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5168 r7 = gen_rtx_REG (DImode, gregno + 6);
5169 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5170 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5177 /* Determine where to put a SIMD argument on the SPE. */
5179 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5182 int gregno = cum->sysv_gregno;
5184 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5185 are passed and returned in a pair of GPRs for ABI compatibility. */
5186 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5187 || mode == TFmode || mode == TCmode))
5189 int n_words = rs6000_arg_size (mode, type);
5191 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5193 gregno += (1 - gregno) & 1;
5195 /* Multi-reg args are not split between registers and stack. */
5196 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5199 return spe_build_register_parallel (mode, gregno);
5203 int n_words = rs6000_arg_size (mode, type);
5205 /* SPE vectors are put in odd registers. */
5206 if (n_words == 2 && (gregno & 1) == 0)
5209 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5212 enum machine_mode m = SImode;
5214 r1 = gen_rtx_REG (m, gregno);
5215 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5216 r2 = gen_rtx_REG (m, gregno + 1);
5217 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5218 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5225 if (gregno <= GP_ARG_MAX_REG)
5226 return gen_rtx_REG (mode, gregno);
5232 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5233 structure between cum->intoffset and bitpos to integer registers. */
5236 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5237 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5239 enum machine_mode mode;
5241 unsigned int startbit, endbit;
5242 int this_regno, intregs, intoffset;
5245 if (cum->intoffset == -1)
5248 intoffset = cum->intoffset;
5249 cum->intoffset = -1;
5251 /* If this is the trailing part of a word, try to only load that
5252 much into the register. Otherwise load the whole register. Note
5253 that in the latter case we may pick up unwanted bits. It's not a
5254 problem at the moment but may wish to revisit. */
5256 if (intoffset % BITS_PER_WORD != 0)
5258 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5260 if (mode == BLKmode)
5262 /* We couldn't find an appropriate mode, which happens,
5263 e.g., in packed structs when there are 3 bytes to load.
5264 Back intoffset back to the beginning of the word in this
5266 intoffset = intoffset & -BITS_PER_WORD;
5273 startbit = intoffset & -BITS_PER_WORD;
5274 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5275 intregs = (endbit - startbit) / BITS_PER_WORD;
5276 this_regno = cum->words + intoffset / BITS_PER_WORD;
5278 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5281 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5285 intoffset /= BITS_PER_UNIT;
5288 regno = GP_ARG_MIN_REG + this_regno;
5289 reg = gen_rtx_REG (mode, regno);
5291 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5294 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5298 while (intregs > 0);
5301 /* Recursive workhorse for the following. */
5304 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5305 HOST_WIDE_INT startbitpos, rtx rvec[],
5310 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5311 if (TREE_CODE (f) == FIELD_DECL)
5313 HOST_WIDE_INT bitpos = startbitpos;
5314 tree ftype = TREE_TYPE (f);
5315 enum machine_mode mode;
5316 if (ftype == error_mark_node)
5318 mode = TYPE_MODE (ftype);
5320 if (DECL_SIZE (f) != 0
5321 && host_integerp (bit_position (f), 1))
5322 bitpos += int_bit_position (f);
5324 /* ??? FIXME: else assume zero offset. */
5326 if (TREE_CODE (ftype) == RECORD_TYPE)
5327 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5328 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5333 case SCmode: mode = SFmode; break;
5334 case DCmode: mode = DFmode; break;
5335 case TCmode: mode = TFmode; break;
5339 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5341 = gen_rtx_EXPR_LIST (VOIDmode,
5342 gen_rtx_REG (mode, cum->fregno++),
5343 GEN_INT (bitpos / BITS_PER_UNIT));
5344 if (mode == TFmode || mode == TDmode)
5347 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5349 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5351 = gen_rtx_EXPR_LIST (VOIDmode,
5352 gen_rtx_REG (mode, cum->vregno++),
5353 GEN_INT (bitpos / BITS_PER_UNIT));
5355 else if (cum->intoffset == -1)
5356 cum->intoffset = bitpos;
5360 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5361 the register(s) to be used for each field and subfield of a struct
5362 being passed by value, along with the offset of where the
5363 register's value may be found in the block. FP fields go in FP
5364 register, vector fields go in vector registers, and everything
5365 else goes in int registers, packed as in memory.
5367 This code is also used for function return values. RETVAL indicates
5368 whether this is the case.
5370 Much of this is taken from the SPARC V9 port, which has a similar
5371 calling convention. */
5374 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5375 int named, bool retval)
5377 rtx rvec[FIRST_PSEUDO_REGISTER];
5378 int k = 1, kbase = 1;
5379 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5380 /* This is a copy; modifications are not visible to our caller. */
5381 CUMULATIVE_ARGS copy_cum = *orig_cum;
5382 CUMULATIVE_ARGS *cum = ©_cum;
5384 /* Pad to 16 byte boundary if needed. */
5385 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5386 && (cum->words % 2) != 0)
5393 /* Put entries into rvec[] for individual FP and vector fields, and
5394 for the chunks of memory that go in int regs. Note we start at
5395 element 1; 0 is reserved for an indication of using memory, and
5396 may or may not be filled in below. */
5397 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5398 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5400 /* If any part of the struct went on the stack put all of it there.
5401 This hack is because the generic code for
5402 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5403 parts of the struct are not at the beginning. */
5407 return NULL_RTX; /* doesn't go in registers at all */
5409 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5411 if (k > 1 || cum->use_stack)
5412 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5417 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5420 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5424 rtx rvec[GP_ARG_NUM_REG + 1];
5426 if (align_words >= GP_ARG_NUM_REG)
5429 n_units = rs6000_arg_size (mode, type);
5431 /* Optimize the simple case where the arg fits in one gpr, except in
5432 the case of BLKmode due to assign_parms assuming that registers are
5433 BITS_PER_WORD wide. */
5435 || (n_units == 1 && mode != BLKmode))
5436 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5439 if (align_words + n_units > GP_ARG_NUM_REG)
5440 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5441 using a magic NULL_RTX component.
5442 This is not strictly correct. Only some of the arg belongs in
5443 memory, not all of it. However, the normal scheme using
5444 function_arg_partial_nregs can result in unusual subregs, eg.
5445 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5446 store the whole arg to memory is often more efficient than code
5447 to store pieces, and we know that space is available in the right
5448 place for the whole arg. */
5449 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5454 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5455 rtx off = GEN_INT (i++ * 4);
5456 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5458 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5460 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5463 /* Determine where to put an argument to a function.
5464 Value is zero to push the argument on the stack,
5465 or a hard register in which to store the argument.
5467 MODE is the argument's machine mode.
5468 TYPE is the data type of the argument (as a tree).
5469 This is null for libcalls where that information may
5471 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5472 the preceding args and about the function being called. It is
5473 not modified in this routine.
5474 NAMED is nonzero if this argument is a named parameter
5475 (otherwise it is an extra parameter matching an ellipsis).
5477 On RS/6000 the first eight words of non-FP are normally in registers
5478 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5479 Under V.4, the first 8 FP args are in registers.
5481 If this is floating-point and no prototype is specified, we use
5482 both an FP and integer register (or possibly FP reg and stack). Library
5483 functions (when CALL_LIBCALL is set) always have the proper types for args,
5484 so we can pass the FP value just in one register. emit_library_function
5485 doesn't support PARALLEL anyway.
5487 Note that for args passed by reference, function_arg will be called
5488 with MODE and TYPE set to that of the pointer to the arg, not the arg
5492 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5493 tree type, int named)
5495 enum rs6000_abi abi = DEFAULT_ABI;
5497 /* Return a marker to indicate whether CR1 needs to set or clear the
5498 bit that V.4 uses to say fp args were passed in registers.
5499 Assume that we don't need the marker for software floating point,
5500 or compiler generated library calls. */
5501 if (mode == VOIDmode)
5504 && (cum->call_cookie & CALL_LIBCALL) == 0
5506 || (cum->nargs_prototype < 0
5507 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5509 /* For the SPE, we need to crxor CR6 always. */
5511 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5512 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5513 return GEN_INT (cum->call_cookie
5514 | ((cum->fregno == FP_ARG_MIN_REG)
5515 ? CALL_V4_SET_FP_ARGS
5516 : CALL_V4_CLEAR_FP_ARGS));
5519 return GEN_INT (cum->call_cookie);
5522 if (rs6000_darwin64_abi && mode == BLKmode
5523 && TREE_CODE (type) == RECORD_TYPE)
5525 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5526 if (rslt != NULL_RTX)
5528 /* Else fall through to usual handling. */
5531 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5532 if (TARGET_64BIT && ! cum->prototype)
5534 /* Vector parameters get passed in vector register
5535 and also in GPRs or memory, in absence of prototype. */
5538 align_words = (cum->words + 1) & ~1;
5540 if (align_words >= GP_ARG_NUM_REG)
5546 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5548 return gen_rtx_PARALLEL (mode,
5550 gen_rtx_EXPR_LIST (VOIDmode,
5552 gen_rtx_EXPR_LIST (VOIDmode,
5553 gen_rtx_REG (mode, cum->vregno),
5557 return gen_rtx_REG (mode, cum->vregno);
5558 else if (TARGET_ALTIVEC_ABI
5559 && (ALTIVEC_VECTOR_MODE (mode)
5560 || (type && TREE_CODE (type) == VECTOR_TYPE
5561 && int_size_in_bytes (type) == 16)))
5563 if (named || abi == ABI_V4)
5567 /* Vector parameters to varargs functions under AIX or Darwin
5568 get passed in memory and possibly also in GPRs. */
5569 int align, align_words, n_words;
5570 enum machine_mode part_mode;
5572 /* Vector parameters must be 16-byte aligned. This places them at
5573 2 mod 4 in terms of words in 32-bit mode, since the parameter
5574 save area starts at offset 24 from the stack. In 64-bit mode,
5575 they just have to start on an even word, since the parameter
5576 save area is 16-byte aligned. */
5578 align = (2 - cum->words) & 3;
5580 align = cum->words & 1;
5581 align_words = cum->words + align;
5583 /* Out of registers? Memory, then. */
5584 if (align_words >= GP_ARG_NUM_REG)
5587 if (TARGET_32BIT && TARGET_POWERPC64)
5588 return rs6000_mixed_function_arg (mode, type, align_words);
5590 /* The vector value goes in GPRs. Only the part of the
5591 value in GPRs is reported here. */
5593 n_words = rs6000_arg_size (mode, type);
5594 if (align_words + n_words > GP_ARG_NUM_REG)
5595 /* Fortunately, there are only two possibilities, the value
5596 is either wholly in GPRs or half in GPRs and half not. */
5599 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5602 else if (TARGET_SPE_ABI && TARGET_SPE
5603 && (SPE_VECTOR_MODE (mode)
5604 || (TARGET_E500_DOUBLE && (mode == DFmode
5609 || mode == TCmode))))
5610 return rs6000_spe_function_arg (cum, mode, type);
5612 else if (abi == ABI_V4)
5614 if (TARGET_HARD_FLOAT && TARGET_FPRS
5615 && (mode == SFmode || mode == DFmode
5616 || (mode == TFmode && !TARGET_IEEEQUAD)
5617 || mode == DDmode || mode == TDmode))
5619 /* _Decimal128 must use an even/odd register pair. This assumes
5620 that the register number is odd when fregno is odd. */
5621 if (mode == TDmode && (cum->fregno % 2) == 1)
5624 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5625 <= FP_ARG_V4_MAX_REG)
5626 return gen_rtx_REG (mode, cum->fregno);
5632 int n_words = rs6000_arg_size (mode, type);
5633 int gregno = cum->sysv_gregno;
5635 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5636 (r7,r8) or (r9,r10). As does any other 2 word item such
5637 as complex int due to a historical mistake. */
5639 gregno += (1 - gregno) & 1;
5641 /* Multi-reg args are not split between registers and stack. */
5642 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5645 if (TARGET_32BIT && TARGET_POWERPC64)
5646 return rs6000_mixed_function_arg (mode, type,
5647 gregno - GP_ARG_MIN_REG);
5648 return gen_rtx_REG (mode, gregno);
5653 int align_words = rs6000_parm_start (mode, type, cum->words);
5655 /* _Decimal128 must be passed in an even/odd float register pair.
5656 This assumes that the register number is odd when fregno is odd. */
5657 if (mode == TDmode && (cum->fregno % 2) == 1)
5660 if (USE_FP_FOR_ARG_P (cum, mode, type))
5662 rtx rvec[GP_ARG_NUM_REG + 1];
5666 enum machine_mode fmode = mode;
5667 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5669 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5671 /* Currently, we only ever need one reg here because complex
5672 doubles are split. */
5673 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5674 && (fmode == TFmode || fmode == TDmode));
5676 /* Long double or _Decimal128 split over regs and memory. */
5677 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5680 /* Do we also need to pass this arg in the parameter save
5683 && (cum->nargs_prototype <= 0
5684 || (DEFAULT_ABI == ABI_AIX
5686 && align_words >= GP_ARG_NUM_REG)));
5688 if (!needs_psave && mode == fmode)
5689 return gen_rtx_REG (fmode, cum->fregno);
5694 /* Describe the part that goes in gprs or the stack.
5695 This piece must come first, before the fprs. */
5696 if (align_words < GP_ARG_NUM_REG)
5698 unsigned long n_words = rs6000_arg_size (mode, type);
5700 if (align_words + n_words > GP_ARG_NUM_REG
5701 || (TARGET_32BIT && TARGET_POWERPC64))
5703 /* If this is partially on the stack, then we only
5704 include the portion actually in registers here. */
5705 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5708 if (align_words + n_words > GP_ARG_NUM_REG)
5709 /* Not all of the arg fits in gprs. Say that it
5710 goes in memory too, using a magic NULL_RTX
5711 component. Also see comment in
5712 rs6000_mixed_function_arg for why the normal
5713 function_arg_partial_nregs scheme doesn't work
5715 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5719 r = gen_rtx_REG (rmode,
5720 GP_ARG_MIN_REG + align_words);
5721 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5722 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5724 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5728 /* The whole arg fits in gprs. */
5729 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5730 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5734 /* It's entirely in memory. */
5735 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5738 /* Describe where this piece goes in the fprs. */
5739 r = gen_rtx_REG (fmode, cum->fregno);
5740 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5742 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5744 else if (align_words < GP_ARG_NUM_REG)
5746 if (TARGET_32BIT && TARGET_POWERPC64)
5747 return rs6000_mixed_function_arg (mode, type, align_words);
5749 if (mode == BLKmode)
5752 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5759 /* For an arg passed partly in registers and partly in memory, this is
5760 the number of bytes passed in registers. For args passed entirely in
5761 registers or entirely in memory, zero. When an arg is described by a
5762 PARALLEL, perhaps using more than one register type, this function
5763 returns the number of bytes used by the first element of the PARALLEL. */
5766 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5767 tree type, bool named)
5772 if (DEFAULT_ABI == ABI_V4)
5775 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5776 && cum->nargs_prototype >= 0)
5779 /* In this complicated case we just disable the partial_nregs code. */
5780 if (rs6000_darwin64_abi && mode == BLKmode
5781 && TREE_CODE (type) == RECORD_TYPE
5782 && int_size_in_bytes (type) > 0)
5785 align_words = rs6000_parm_start (mode, type, cum->words);
5787 if (USE_FP_FOR_ARG_P (cum, mode, type))
5789 /* If we are passing this arg in the fixed parameter save area
5790 (gprs or memory) as well as fprs, then this function should
5791 return the number of partial bytes passed in the parameter
5792 save area rather than partial bytes passed in fprs. */
5794 && (cum->nargs_prototype <= 0
5795 || (DEFAULT_ABI == ABI_AIX
5797 && align_words >= GP_ARG_NUM_REG)))
5799 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5800 > FP_ARG_MAX_REG + 1)
5801 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5802 else if (cum->nargs_prototype >= 0)
5806 if (align_words < GP_ARG_NUM_REG
5807 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5808 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5810 if (ret != 0 && TARGET_DEBUG_ARG)
5811 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5816 /* A C expression that indicates when an argument must be passed by
5817 reference. If nonzero for an argument, a copy of that argument is
5818 made in memory and a pointer to the argument is passed instead of
5819 the argument itself. The pointer is passed in whatever way is
5820 appropriate for passing a pointer to that type.
5822 Under V.4, aggregates and long double are passed by reference.
5824 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5825 reference unless the AltiVec vector extension ABI is in force.
5827 As an extension to all ABIs, variable sized types are passed by
5831 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5832 enum machine_mode mode, tree type,
5833 bool named ATTRIBUTE_UNUSED)
5835 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5837 if (TARGET_DEBUG_ARG)
5838 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5845 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5847 if (TARGET_DEBUG_ARG)
5848 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5852 if (int_size_in_bytes (type) < 0)
5854 if (TARGET_DEBUG_ARG)
5855 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5859 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5860 modes only exist for GCC vector types if -maltivec. */
5861 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5863 if (TARGET_DEBUG_ARG)
5864 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5868 /* Pass synthetic vectors in memory. */
5869 if (TREE_CODE (type) == VECTOR_TYPE
5870 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5872 static bool warned_for_pass_big_vectors = false;
5873 if (TARGET_DEBUG_ARG)
5874 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5875 if (!warned_for_pass_big_vectors)
5877 warning (0, "GCC vector passed by reference: "
5878 "non-standard ABI extension with no compatibility guarantee");
5879 warned_for_pass_big_vectors = true;
5888 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5891 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5896 for (i = 0; i < nregs; i++)
5898 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5899 if (reload_completed)
5901 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5904 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5905 i * GET_MODE_SIZE (reg_mode));
5908 tem = replace_equiv_address (tem, XEXP (tem, 0));
5912 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5916 /* Perform any needed actions needed for a function that is receiving a
5917 variable number of arguments.
5921 MODE and TYPE are the mode and type of the current parameter.
5923 PRETEND_SIZE is a variable that should be set to the amount of stack
5924 that must be pushed by the prolog to pretend that our caller pushed
5927 Normally, this macro will push all remaining incoming registers on the
5928 stack and set PRETEND_SIZE to the length of the registers pushed. */
5931 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5932 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5935 CUMULATIVE_ARGS next_cum;
5936 int reg_size = TARGET_32BIT ? 4 : 8;
5937 rtx save_area = NULL_RTX, mem;
5938 int first_reg_offset, set;
5940 /* Skip the last named argument. */
5942 function_arg_advance (&next_cum, mode, type, 1, 0);
5944 if (DEFAULT_ABI == ABI_V4)
5946 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5950 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5951 HOST_WIDE_INT offset = 0;
5953 /* Try to optimize the size of the varargs save area.
5954 The ABI requires that ap.reg_save_area is doubleword
5955 aligned, but we don't need to allocate space for all
5956 the bytes, only those to which we actually will save
5958 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5959 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5960 if (TARGET_HARD_FLOAT && TARGET_FPRS
5961 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5962 && cfun->va_list_fpr_size)
5965 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5966 * UNITS_PER_FP_WORD;
5967 if (cfun->va_list_fpr_size
5968 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5969 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5971 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5972 * UNITS_PER_FP_WORD;
5976 offset = -((first_reg_offset * reg_size) & ~7);
5977 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5979 gpr_reg_num = cfun->va_list_gpr_size;
5980 if (reg_size == 4 && (first_reg_offset & 1))
5983 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5986 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5988 - (int) (GP_ARG_NUM_REG * reg_size);
5990 if (gpr_size + fpr_size)
5993 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5994 gcc_assert (GET_CODE (reg_save_area) == MEM);
5995 reg_save_area = XEXP (reg_save_area, 0);
5996 if (GET_CODE (reg_save_area) == PLUS)
5998 gcc_assert (XEXP (reg_save_area, 0)
5999 == virtual_stack_vars_rtx);
6000 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6001 offset += INTVAL (XEXP (reg_save_area, 1));
6004 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6007 cfun->machine->varargs_save_offset = offset;
6008 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6013 first_reg_offset = next_cum.words;
6014 save_area = virtual_incoming_args_rtx;
6016 if (targetm.calls.must_pass_in_stack (mode, type))
6017 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6020 set = get_varargs_alias_set ();
6021 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6022 && cfun->va_list_gpr_size)
6024 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6026 if (va_list_gpr_counter_field)
6028 /* V4 va_list_gpr_size counts number of registers needed. */
6029 if (nregs > cfun->va_list_gpr_size)
6030 nregs = cfun->va_list_gpr_size;
6034 /* char * va_list instead counts number of bytes needed. */
6035 if (nregs > cfun->va_list_gpr_size / reg_size)
6036 nregs = cfun->va_list_gpr_size / reg_size;
6039 mem = gen_rtx_MEM (BLKmode,
6040 plus_constant (save_area,
6041 first_reg_offset * reg_size));
6042 MEM_NOTRAP_P (mem) = 1;
6043 set_mem_alias_set (mem, set);
6044 set_mem_align (mem, BITS_PER_WORD);
6046 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6050 /* Save FP registers if needed. */
6051 if (DEFAULT_ABI == ABI_V4
6052 && TARGET_HARD_FLOAT && TARGET_FPRS
6054 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6055 && cfun->va_list_fpr_size)
6057 int fregno = next_cum.fregno, nregs;
6058 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6059 rtx lab = gen_label_rtx ();
6060 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6061 * UNITS_PER_FP_WORD);
6064 (gen_rtx_SET (VOIDmode,
6066 gen_rtx_IF_THEN_ELSE (VOIDmode,
6067 gen_rtx_NE (VOIDmode, cr1,
6069 gen_rtx_LABEL_REF (VOIDmode, lab),
6073 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6074 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6076 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6077 MEM_NOTRAP_P (mem) = 1;
6078 set_mem_alias_set (mem, set);
6079 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6080 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6087 /* Create the va_list data type. */
6090 rs6000_build_builtin_va_list (void)
6092 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6094 /* For AIX, prefer 'char *' because that's what the system
6095 header files like. */
6096 if (DEFAULT_ABI != ABI_V4)
6097 return build_pointer_type (char_type_node);
6099 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6100 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6102 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6103 unsigned_char_type_node);
6104 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6105 unsigned_char_type_node);
6106 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6108 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6109 short_unsigned_type_node);
6110 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6112 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6115 va_list_gpr_counter_field = f_gpr;
6116 va_list_fpr_counter_field = f_fpr;
6118 DECL_FIELD_CONTEXT (f_gpr) = record;
6119 DECL_FIELD_CONTEXT (f_fpr) = record;
6120 DECL_FIELD_CONTEXT (f_res) = record;
6121 DECL_FIELD_CONTEXT (f_ovf) = record;
6122 DECL_FIELD_CONTEXT (f_sav) = record;
6124 TREE_CHAIN (record) = type_decl;
6125 TYPE_NAME (record) = type_decl;
6126 TYPE_FIELDS (record) = f_gpr;
6127 TREE_CHAIN (f_gpr) = f_fpr;
6128 TREE_CHAIN (f_fpr) = f_res;
6129 TREE_CHAIN (f_res) = f_ovf;
6130 TREE_CHAIN (f_ovf) = f_sav;
6132 layout_type (record);
6134 /* The correct type is an array type of one element. */
6135 return build_array_type (record, build_index_type (size_zero_node));
6138 /* Implement va_start. */
6141 rs6000_va_start (tree valist, rtx nextarg)
6143 HOST_WIDE_INT words, n_gpr, n_fpr;
6144 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6145 tree gpr, fpr, ovf, sav, t;
6147 /* Only SVR4 needs something special. */
6148 if (DEFAULT_ABI != ABI_V4)
6150 std_expand_builtin_va_start (valist, nextarg);
6154 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6155 f_fpr = TREE_CHAIN (f_gpr);
6156 f_res = TREE_CHAIN (f_fpr);
6157 f_ovf = TREE_CHAIN (f_res);
6158 f_sav = TREE_CHAIN (f_ovf);
6160 valist = build_va_arg_indirect_ref (valist);
6161 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6162 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6163 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6164 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6166 /* Count number of gp and fp argument registers used. */
6167 words = current_function_args_info.words;
6168 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6170 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6173 if (TARGET_DEBUG_ARG)
6174 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6175 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6176 words, n_gpr, n_fpr);
6178 if (cfun->va_list_gpr_size)
6180 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6181 build_int_cst (NULL_TREE, n_gpr));
6182 TREE_SIDE_EFFECTS (t) = 1;
6183 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6186 if (cfun->va_list_fpr_size)
6188 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6189 build_int_cst (NULL_TREE, n_fpr));
6190 TREE_SIDE_EFFECTS (t) = 1;
6191 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6194 /* Find the overflow area. */
6195 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6197 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
6198 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
6199 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6200 TREE_SIDE_EFFECTS (t) = 1;
6201 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6203 /* If there were no va_arg invocations, don't set up the register
6205 if (!cfun->va_list_gpr_size
6206 && !cfun->va_list_fpr_size
6207 && n_gpr < GP_ARG_NUM_REG
6208 && n_fpr < FP_ARG_V4_MAX_REG)
6211 /* Find the register save area. */
6212 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6213 if (cfun->machine->varargs_save_offset)
6214 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
6215 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
6216 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6217 TREE_SIDE_EFFECTS (t) = 1;
6218 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6221 /* Implement va_arg. */
6224 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6226 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6227 tree gpr, fpr, ovf, sav, reg, t, u;
6228 int size, rsize, n_reg, sav_ofs, sav_scale;
6229 tree lab_false, lab_over, addr;
6231 tree ptrtype = build_pointer_type (type);
6234 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6236 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6237 return build_va_arg_indirect_ref (t);
6240 if (DEFAULT_ABI != ABI_V4)
6242 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6244 tree elem_type = TREE_TYPE (type);
6245 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6246 int elem_size = GET_MODE_SIZE (elem_mode);
6248 if (elem_size < UNITS_PER_WORD)
6250 tree real_part, imag_part;
6251 tree post = NULL_TREE;
6253 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6255 /* Copy the value into a temporary, lest the formal temporary
6256 be reused out from under us. */
6257 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6258 append_to_statement_list (post, pre_p);
6260 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6263 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6267 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6270 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6271 f_fpr = TREE_CHAIN (f_gpr);
6272 f_res = TREE_CHAIN (f_fpr);
6273 f_ovf = TREE_CHAIN (f_res);
6274 f_sav = TREE_CHAIN (f_ovf);
6276 valist = build_va_arg_indirect_ref (valist);
6277 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6278 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6279 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6280 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6282 size = int_size_in_bytes (type);
6283 rsize = (size + 3) / 4;
6286 if (TARGET_HARD_FLOAT && TARGET_FPRS
6287 && (TYPE_MODE (type) == SFmode
6288 || TYPE_MODE (type) == DFmode
6289 || TYPE_MODE (type) == TFmode
6290 || TYPE_MODE (type) == DDmode
6291 || TYPE_MODE (type) == TDmode))
6293 /* FP args go in FP registers, if present. */
6295 n_reg = (size + 7) / 8;
6298 if (TYPE_MODE (type) != SFmode)
6303 /* Otherwise into GP registers. */
6312 /* Pull the value out of the saved registers.... */
6315 addr = create_tmp_var (ptr_type_node, "addr");
6316 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6318 /* AltiVec vectors never go in registers when -mabi=altivec. */
6319 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6323 lab_false = create_artificial_label ();
6324 lab_over = create_artificial_label ();
6326 /* Long long and SPE vectors are aligned in the registers.
6327 As are any other 2 gpr item such as complex int due to a
6328 historical mistake. */
6330 if (n_reg == 2 && reg == gpr)
6333 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6334 size_int (n_reg - 1));
6335 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6337 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6338 reg number is 0 for f1, so we want to make it odd. */
6339 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6342 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6343 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6346 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6347 t = build2 (GE_EXPR, boolean_type_node, u, t);
6348 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6349 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6350 gimplify_and_add (t, pre_p);
6354 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6356 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6357 u = build1 (CONVERT_EXPR, integer_type_node, u);
6358 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6359 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6361 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6362 gimplify_and_add (t, pre_p);
6364 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6365 gimplify_and_add (t, pre_p);
6367 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6368 append_to_statement_list (t, pre_p);
6370 if ((n_reg == 2 && !regalign) || n_reg > 2)
6372 /* Ensure that we don't find any more args in regs.
6373 Alignment has taken care of for special cases. */
6374 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6375 gimplify_and_add (t, pre_p);
6379 /* ... otherwise out of the overflow area. */
6381 /* Care for on-stack alignment if needed. */
6385 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6386 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6387 build_int_cst (NULL_TREE, -align));
6389 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6391 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6392 gimplify_and_add (u, pre_p);
6394 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6395 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6396 gimplify_and_add (t, pre_p);
6400 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6401 append_to_statement_list (t, pre_p);
6404 if (STRICT_ALIGNMENT
6405 && (TYPE_ALIGN (type)
6406 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6408 /* The value (of type complex double, for example) may not be
6409 aligned in memory in the saved registers, so copy via a
6410 temporary. (This is the same code as used for SPARC.) */
6411 tree tmp = create_tmp_var (type, "va_arg_tmp");
6412 tree dest_addr = build_fold_addr_expr (tmp);
6414 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6415 3, dest_addr, addr, size_int (rsize * 4));
6417 gimplify_and_add (copy, pre_p);
6421 addr = fold_convert (ptrtype, addr);
6422 return build_va_arg_indirect_ref (addr);
6428 def_builtin (int mask, const char *name, tree type, int code)
6430 if (mask & target_flags)
6432 if (rs6000_builtin_decls[code])
6435 rs6000_builtin_decls[code] =
6436 add_builtin_function (name, type, code, BUILT_IN_MD,
6441 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6443 static const struct builtin_description bdesc_3arg[] =
6445 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6446 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6447 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6448 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6449 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6450 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6451 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6452 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6453 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6454 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6455 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6456 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6457 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6458 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6459 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6460 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6461 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6462 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6463 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6464 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6465 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6466 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6467 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6469 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6470 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6471 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6472 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6473 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6474 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6475 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6476 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6477 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6478 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6479 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6480 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6481 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6482 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6483 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6486 /* DST operations: void foo (void *, const int, const char). */
6488 static const struct builtin_description bdesc_dst[] =
6490 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6491 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6492 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6493 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6495 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6496 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6497 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6498 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6501 /* Simple binary operations: VECc = foo (VECa, VECb). */
6503 static struct builtin_description bdesc_2arg[] =
6505 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6506 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6507 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6508 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6509 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6510 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6511 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6512 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6513 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6514 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6515 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6516 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6517 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6520 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6521 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6522 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6523 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6524 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6525 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6526 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6528 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6529 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6530 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6531 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6532 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6533 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6534 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6535 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6536 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6537 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6538 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6539 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6540 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6541 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6542 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6543 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6544 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6545 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6546 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6547 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6548 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6549 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6550 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6551 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6552 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6553 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6554 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6555 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6556 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6557 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6558 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6559 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6560 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6561 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6562 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6563 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6564 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6565 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6566 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6567 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6568 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6569 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6570 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6571 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6572 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6573 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6574 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6575 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6576 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6577 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6578 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6579 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6580 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6581 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6582 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6583 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6584 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6585 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6586 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6587 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6588 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6589 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6590 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6591 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6592 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6593 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6594 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6595 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6596 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6597 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6598 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6599 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6600 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6601 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6602 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6603 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6604 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6605 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6606 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6607 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6608 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6609 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6610 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6611 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6613 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6614 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6615 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6617 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6618 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6619 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6620 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6621 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6622 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6623 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6624 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6625 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6626 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6627 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6628 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6629 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6630 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6631 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6632 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6633 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6634 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6635 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6636 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6637 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6638 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6639 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6640 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6641 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6642 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6643 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6644 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6645 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6646 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6647 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6648 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6660 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6661 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6665 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6666 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6667 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6668 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6669 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6670 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6671 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6672 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6673 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6674 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6675 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6676 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6677 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6678 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6680 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6681 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6682 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6683 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6684 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6685 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6686 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6687 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6688 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6689 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6690 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6691 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6692 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6693 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6694 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6695 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6696 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6697 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6698 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6699 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6700 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6701 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6702 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6703 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6704 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6705 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6706 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6707 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6708 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6709 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6710 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6711 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6712 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6713 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6714 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6715 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6716 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6717 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6718 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6719 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6720 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6721 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6722 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6723 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6724 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6725 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6726 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6727 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6728 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6729 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6730 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6731 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6732 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6733 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6734 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6735 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6736 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6737 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6738 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6739 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6740 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6741 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6742 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6743 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6745 /* Place holder, leave as first spe builtin. */
6746 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6747 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6748 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6749 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6750 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6751 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6752 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6753 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6754 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6755 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6756 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6757 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6758 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6759 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6760 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6761 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6762 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6763 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6764 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6765 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6766 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6767 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6768 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6769 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6770 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6771 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6772 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6773 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6774 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6775 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6776 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6777 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6778 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6779 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6780 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6781 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6782 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6783 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6784 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6785 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6786 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6787 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6788 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6789 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6790 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6791 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6792 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6793 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6794 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6795 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6796 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6797 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6798 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6799 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6800 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6801 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6802 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6803 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6804 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6805 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6806 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6807 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6808 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6809 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6810 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6811 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6812 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6813 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6814 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6815 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6816 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6817 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6818 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6819 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6820 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6821 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6822 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6823 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6824 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6825 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6826 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6827 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6828 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6829 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6830 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6831 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6832 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6833 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6834 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6835 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6836 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6837 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6838 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6839 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6840 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6841 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6842 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6843 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6844 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6845 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6846 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6847 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6848 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6849 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6850 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6851 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6852 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6853 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6854 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6856 /* SPE binary operations expecting a 5-bit unsigned literal. */
6857 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6859 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6860 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6861 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6862 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6863 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6864 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6865 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6866 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6867 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6868 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6869 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6870 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6871 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6872 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6873 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6874 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6875 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6876 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6877 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6878 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6879 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6880 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6881 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6882 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6883 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6884 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6886 /* Place-holder. Leave as last binary SPE builtin. */
6887 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6890 /* AltiVec predicates. */
6892 struct builtin_description_predicates
6894 const unsigned int mask;
6895 const enum insn_code icode;
6897 const char *const name;
6898 const enum rs6000_builtins code;
6901 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6903 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6904 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6905 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6906 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6907 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6908 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6909 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6910 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6911 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6912 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6913 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6914 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6915 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6917 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6918 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6919 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6922 /* SPE predicates. */
6923 static struct builtin_description bdesc_spe_predicates[] =
6925 /* Place-holder. Leave as first. */
6926 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6927 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6928 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6929 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6930 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6931 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6932 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6933 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6934 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6935 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6936 /* Place-holder. Leave as last. */
6937 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6940 /* SPE evsel predicates. */
6941 static struct builtin_description bdesc_spe_evsel[] =
6943 /* Place-holder. Leave as first. */
6944 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6945 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6946 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6947 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6948 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6949 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6950 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6951 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6952 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6953 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6954 /* Place-holder. Leave as last. */
6955 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6958 /* ABS* operations. */
6960 static const struct builtin_description bdesc_abs[] =
6962 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6963 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6964 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6965 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6966 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6967 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6968 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6971 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6974 static struct builtin_description bdesc_1arg[] =
6976 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6977 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6978 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6979 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6980 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6981 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6982 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6983 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6984 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6985 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6986 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6987 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6988 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6989 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6990 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6991 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6992 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6994 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6995 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6996 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6997 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6998 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6999 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7000 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7001 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7002 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7003 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7004 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7005 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7006 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7007 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7008 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7009 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7010 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7011 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7012 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7014 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7015 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7016 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7017 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7018 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7019 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7020 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7021 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7022 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7023 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7024 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7025 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7026 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7027 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7028 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7029 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7030 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7031 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7032 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7033 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7034 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7035 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7036 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7037 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7038 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7039 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7040 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7041 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7042 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7043 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7045 /* Place-holder. Leave as last unary SPE builtin. */
7046 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7050 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7053 tree arg0 = CALL_EXPR_ARG (exp, 0);
7054 rtx op0 = expand_normal (arg0);
7055 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7056 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7058 if (icode == CODE_FOR_nothing)
7059 /* Builtin not supported on this processor. */
7062 /* If we got invalid arguments bail out before generating bad rtl. */
7063 if (arg0 == error_mark_node)
7066 if (icode == CODE_FOR_altivec_vspltisb
7067 || icode == CODE_FOR_altivec_vspltish
7068 || icode == CODE_FOR_altivec_vspltisw
7069 || icode == CODE_FOR_spe_evsplatfi
7070 || icode == CODE_FOR_spe_evsplati)
7072 /* Only allow 5-bit *signed* literals. */
7073 if (GET_CODE (op0) != CONST_INT
7074 || INTVAL (op0) > 15
7075 || INTVAL (op0) < -16)
7077 error ("argument 1 must be a 5-bit signed literal");
7083 || GET_MODE (target) != tmode
7084 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7085 target = gen_reg_rtx (tmode);
7087 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7088 op0 = copy_to_mode_reg (mode0, op0);
7090 pat = GEN_FCN (icode) (target, op0);
7099 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7101 rtx pat, scratch1, scratch2;
7102 tree arg0 = CALL_EXPR_ARG (exp, 0);
7103 rtx op0 = expand_normal (arg0);
7104 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7105 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7107 /* If we have invalid arguments, bail out before generating bad rtl. */
7108 if (arg0 == error_mark_node)
7112 || GET_MODE (target) != tmode
7113 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7114 target = gen_reg_rtx (tmode);
7116 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7117 op0 = copy_to_mode_reg (mode0, op0);
7119 scratch1 = gen_reg_rtx (mode0);
7120 scratch2 = gen_reg_rtx (mode0);
7122 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7131 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7134 tree arg0 = CALL_EXPR_ARG (exp, 0);
7135 tree arg1 = CALL_EXPR_ARG (exp, 1);
7136 rtx op0 = expand_normal (arg0);
7137 rtx op1 = expand_normal (arg1);
7138 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7139 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7140 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7142 if (icode == CODE_FOR_nothing)
7143 /* Builtin not supported on this processor. */
7146 /* If we got invalid arguments bail out before generating bad rtl. */
7147 if (arg0 == error_mark_node || arg1 == error_mark_node)
7150 if (icode == CODE_FOR_altivec_vcfux
7151 || icode == CODE_FOR_altivec_vcfsx
7152 || icode == CODE_FOR_altivec_vctsxs
7153 || icode == CODE_FOR_altivec_vctuxs
7154 || icode == CODE_FOR_altivec_vspltb
7155 || icode == CODE_FOR_altivec_vsplth
7156 || icode == CODE_FOR_altivec_vspltw
7157 || icode == CODE_FOR_spe_evaddiw
7158 || icode == CODE_FOR_spe_evldd
7159 || icode == CODE_FOR_spe_evldh
7160 || icode == CODE_FOR_spe_evldw
7161 || icode == CODE_FOR_spe_evlhhesplat
7162 || icode == CODE_FOR_spe_evlhhossplat
7163 || icode == CODE_FOR_spe_evlhhousplat
7164 || icode == CODE_FOR_spe_evlwhe
7165 || icode == CODE_FOR_spe_evlwhos
7166 || icode == CODE_FOR_spe_evlwhou
7167 || icode == CODE_FOR_spe_evlwhsplat
7168 || icode == CODE_FOR_spe_evlwwsplat
7169 || icode == CODE_FOR_spe_evrlwi
7170 || icode == CODE_FOR_spe_evslwi
7171 || icode == CODE_FOR_spe_evsrwis
7172 || icode == CODE_FOR_spe_evsubifw
7173 || icode == CODE_FOR_spe_evsrwiu)
7175 /* Only allow 5-bit unsigned literals. */
7177 if (TREE_CODE (arg1) != INTEGER_CST
7178 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7180 error ("argument 2 must be a 5-bit unsigned literal");
7186 || GET_MODE (target) != tmode
7187 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7188 target = gen_reg_rtx (tmode);
7190 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7191 op0 = copy_to_mode_reg (mode0, op0);
7192 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7193 op1 = copy_to_mode_reg (mode1, op1);
7195 pat = GEN_FCN (icode) (target, op0, op1);
7204 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7205 tree exp, rtx target)
7208 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7209 tree arg0 = CALL_EXPR_ARG (exp, 1);
7210 tree arg1 = CALL_EXPR_ARG (exp, 2);
7211 rtx op0 = expand_normal (arg0);
7212 rtx op1 = expand_normal (arg1);
7213 enum machine_mode tmode = SImode;
7214 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7215 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7218 if (TREE_CODE (cr6_form) != INTEGER_CST)
7220 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7224 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7226 gcc_assert (mode0 == mode1);
7228 /* If we have invalid arguments, bail out before generating bad rtl. */
7229 if (arg0 == error_mark_node || arg1 == error_mark_node)
7233 || GET_MODE (target) != tmode
7234 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7235 target = gen_reg_rtx (tmode);
7237 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7238 op0 = copy_to_mode_reg (mode0, op0);
7239 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7240 op1 = copy_to_mode_reg (mode1, op1);
7242 scratch = gen_reg_rtx (mode0);
7244 pat = GEN_FCN (icode) (scratch, op0, op1,
7245 gen_rtx_SYMBOL_REF (Pmode, opcode));
7250 /* The vec_any* and vec_all* predicates use the same opcodes for two
7251 different operations, but the bits in CR6 will be different
7252 depending on what information we want. So we have to play tricks
7253 with CR6 to get the right bits out.
7255 If you think this is disgusting, look at the specs for the
7256 AltiVec predicates. */
7258 switch (cr6_form_int)
7261 emit_insn (gen_cr6_test_for_zero (target));
7264 emit_insn (gen_cr6_test_for_zero_reverse (target));
7267 emit_insn (gen_cr6_test_for_lt (target));
7270 emit_insn (gen_cr6_test_for_lt_reverse (target));
7273 error ("argument 1 of __builtin_altivec_predicate is out of range");
7281 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7284 tree arg0 = CALL_EXPR_ARG (exp, 0);
7285 tree arg1 = CALL_EXPR_ARG (exp, 1);
7286 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7287 enum machine_mode mode0 = Pmode;
7288 enum machine_mode mode1 = Pmode;
7289 rtx op0 = expand_normal (arg0);
7290 rtx op1 = expand_normal (arg1);
7292 if (icode == CODE_FOR_nothing)
7293 /* Builtin not supported on this processor. */
7296 /* If we got invalid arguments bail out before generating bad rtl. */
7297 if (arg0 == error_mark_node || arg1 == error_mark_node)
7301 || GET_MODE (target) != tmode
7302 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7303 target = gen_reg_rtx (tmode);
7305 op1 = copy_to_mode_reg (mode1, op1);
7307 if (op0 == const0_rtx)
7309 addr = gen_rtx_MEM (tmode, op1);
7313 op0 = copy_to_mode_reg (mode0, op0);
7314 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7317 pat = GEN_FCN (icode) (target, addr);
7327 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7329 tree arg0 = CALL_EXPR_ARG (exp, 0);
7330 tree arg1 = CALL_EXPR_ARG (exp, 1);
7331 tree arg2 = CALL_EXPR_ARG (exp, 2);
7332 rtx op0 = expand_normal (arg0);
7333 rtx op1 = expand_normal (arg1);
7334 rtx op2 = expand_normal (arg2);
7336 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7337 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7338 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7340 /* Invalid arguments. Bail before doing anything stoopid! */
7341 if (arg0 == error_mark_node
7342 || arg1 == error_mark_node
7343 || arg2 == error_mark_node)
7346 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7347 op0 = copy_to_mode_reg (mode2, op0);
7348 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7349 op1 = copy_to_mode_reg (mode0, op1);
7350 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7351 op2 = copy_to_mode_reg (mode1, op2);
7353 pat = GEN_FCN (icode) (op1, op2, op0);
7360 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7362 tree arg0 = CALL_EXPR_ARG (exp, 0);
7363 tree arg1 = CALL_EXPR_ARG (exp, 1);
7364 tree arg2 = CALL_EXPR_ARG (exp, 2);
7365 rtx op0 = expand_normal (arg0);
7366 rtx op1 = expand_normal (arg1);
7367 rtx op2 = expand_normal (arg2);
7369 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7370 enum machine_mode mode1 = Pmode;
7371 enum machine_mode mode2 = Pmode;
7373 /* Invalid arguments. Bail before doing anything stoopid! */
7374 if (arg0 == error_mark_node
7375 || arg1 == error_mark_node
7376 || arg2 == error_mark_node)
7379 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7380 op0 = copy_to_mode_reg (tmode, op0);
7382 op2 = copy_to_mode_reg (mode2, op2);
7384 if (op1 == const0_rtx)
7386 addr = gen_rtx_MEM (tmode, op2);
7390 op1 = copy_to_mode_reg (mode1, op1);
7391 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7394 pat = GEN_FCN (icode) (addr, op0);
7401 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7404 tree arg0 = CALL_EXPR_ARG (exp, 0);
7405 tree arg1 = CALL_EXPR_ARG (exp, 1);
7406 tree arg2 = CALL_EXPR_ARG (exp, 2);
7407 rtx op0 = expand_normal (arg0);
7408 rtx op1 = expand_normal (arg1);
7409 rtx op2 = expand_normal (arg2);
7410 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7411 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7412 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7413 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7415 if (icode == CODE_FOR_nothing)
7416 /* Builtin not supported on this processor. */
7419 /* If we got invalid arguments bail out before generating bad rtl. */
7420 if (arg0 == error_mark_node
7421 || arg1 == error_mark_node
7422 || arg2 == error_mark_node)
7425 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7426 || icode == CODE_FOR_altivec_vsldoi_v4si
7427 || icode == CODE_FOR_altivec_vsldoi_v8hi
7428 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7430 /* Only allow 4-bit unsigned literals. */
7432 if (TREE_CODE (arg2) != INTEGER_CST
7433 || TREE_INT_CST_LOW (arg2) & ~0xf)
7435 error ("argument 3 must be a 4-bit unsigned literal");
7441 || GET_MODE (target) != tmode
7442 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7443 target = gen_reg_rtx (tmode);
7445 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7446 op0 = copy_to_mode_reg (mode0, op0);
7447 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7448 op1 = copy_to_mode_reg (mode1, op1);
7449 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7450 op2 = copy_to_mode_reg (mode2, op2);
7452 pat = GEN_FCN (icode) (target, op0, op1, op2);
7460 /* Expand the lvx builtins. */
7462 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7464 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7465 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7467 enum machine_mode tmode, mode0;
7469 enum insn_code icode;
7473 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7474 icode = CODE_FOR_altivec_lvx_v16qi;
7476 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7477 icode = CODE_FOR_altivec_lvx_v8hi;
7479 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7480 icode = CODE_FOR_altivec_lvx_v4si;
7482 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7483 icode = CODE_FOR_altivec_lvx_v4sf;
7492 arg0 = CALL_EXPR_ARG (exp, 0);
7493 op0 = expand_normal (arg0);
7494 tmode = insn_data[icode].operand[0].mode;
7495 mode0 = insn_data[icode].operand[1].mode;
7498 || GET_MODE (target) != tmode
7499 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7500 target = gen_reg_rtx (tmode);
7502 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7503 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7505 pat = GEN_FCN (icode) (target, op0);
7512 /* Expand the stvx builtins. */
7514 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7517 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7518 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7520 enum machine_mode mode0, mode1;
7522 enum insn_code icode;
7526 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7527 icode = CODE_FOR_altivec_stvx_v16qi;
7529 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7530 icode = CODE_FOR_altivec_stvx_v8hi;
7532 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7533 icode = CODE_FOR_altivec_stvx_v4si;
7535 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7536 icode = CODE_FOR_altivec_stvx_v4sf;
7543 arg0 = CALL_EXPR_ARG (exp, 0);
7544 arg1 = CALL_EXPR_ARG (exp, 1);
7545 op0 = expand_normal (arg0);
7546 op1 = expand_normal (arg1);
7547 mode0 = insn_data[icode].operand[0].mode;
7548 mode1 = insn_data[icode].operand[1].mode;
7550 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7551 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7552 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7553 op1 = copy_to_mode_reg (mode1, op1);
7555 pat = GEN_FCN (icode) (op0, op1);
7563 /* Expand the dst builtins. */
7565 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7568 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7569 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7570 tree arg0, arg1, arg2;
7571 enum machine_mode mode0, mode1, mode2;
7572 rtx pat, op0, op1, op2;
7573 struct builtin_description *d;
7578 /* Handle DST variants. */
7579 d = (struct builtin_description *) bdesc_dst;
7580 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7581 if (d->code == fcode)
7583 arg0 = CALL_EXPR_ARG (exp, 0);
7584 arg1 = CALL_EXPR_ARG (exp, 1);
7585 arg2 = CALL_EXPR_ARG (exp, 2);
7586 op0 = expand_normal (arg0);
7587 op1 = expand_normal (arg1);
7588 op2 = expand_normal (arg2);
7589 mode0 = insn_data[d->icode].operand[0].mode;
7590 mode1 = insn_data[d->icode].operand[1].mode;
7591 mode2 = insn_data[d->icode].operand[2].mode;
7593 /* Invalid arguments, bail out before generating bad rtl. */
7594 if (arg0 == error_mark_node
7595 || arg1 == error_mark_node
7596 || arg2 == error_mark_node)
7601 if (TREE_CODE (arg2) != INTEGER_CST
7602 || TREE_INT_CST_LOW (arg2) & ~0x3)
7604 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7608 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7609 op0 = copy_to_mode_reg (Pmode, op0);
7610 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7611 op1 = copy_to_mode_reg (mode1, op1);
7613 pat = GEN_FCN (d->icode) (op0, op1, op2);
7623 /* Expand vec_init builtin. */
7625 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7627 enum machine_mode tmode = TYPE_MODE (type);
7628 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7629 int i, n_elt = GET_MODE_NUNITS (tmode);
7630 rtvec v = rtvec_alloc (n_elt);
7632 gcc_assert (VECTOR_MODE_P (tmode));
7633 gcc_assert (n_elt == call_expr_nargs (exp));
7635 for (i = 0; i < n_elt; ++i)
7637 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7638 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7641 if (!target || !register_operand (target, tmode))
7642 target = gen_reg_rtx (tmode);
7644 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7648 /* Return the integer constant in ARG. Constrain it to be in the range
7649 of the subparts of VEC_TYPE; issue an error if not. */
7652 get_element_number (tree vec_type, tree arg)
7654 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7656 if (!host_integerp (arg, 1)
7657 || (elt = tree_low_cst (arg, 1), elt > max))
7659 error ("selector must be an integer constant in the range 0..%wi", max);
7666 /* Expand vec_set builtin. */
7668 altivec_expand_vec_set_builtin (tree exp)
7670 enum machine_mode tmode, mode1;
7671 tree arg0, arg1, arg2;
7675 arg0 = CALL_EXPR_ARG (exp, 0);
7676 arg1 = CALL_EXPR_ARG (exp, 1);
7677 arg2 = CALL_EXPR_ARG (exp, 2);
7679 tmode = TYPE_MODE (TREE_TYPE (arg0));
7680 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7681 gcc_assert (VECTOR_MODE_P (tmode));
7683 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7684 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7685 elt = get_element_number (TREE_TYPE (arg0), arg2);
7687 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7688 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7690 op0 = force_reg (tmode, op0);
7691 op1 = force_reg (mode1, op1);
7693 rs6000_expand_vector_set (op0, op1, elt);
7698 /* Expand vec_ext builtin. */
7700 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7702 enum machine_mode tmode, mode0;
7707 arg0 = CALL_EXPR_ARG (exp, 0);
7708 arg1 = CALL_EXPR_ARG (exp, 1);
7710 op0 = expand_normal (arg0);
7711 elt = get_element_number (TREE_TYPE (arg0), arg1);
7713 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7714 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7715 gcc_assert (VECTOR_MODE_P (mode0));
7717 op0 = force_reg (mode0, op0);
7719 if (optimize || !target || !register_operand (target, tmode))
7720 target = gen_reg_rtx (tmode);
7722 rs6000_expand_vector_extract (target, op0, elt);
7727 /* Expand the builtin in EXP and store the result in TARGET. Store
7728 true in *EXPANDEDP if we found a builtin to expand. */
7730 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7732 struct builtin_description *d;
7733 struct builtin_description_predicates *dp;
7735 enum insn_code icode;
7736 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7739 enum machine_mode tmode, mode0;
7740 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7742 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7743 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7746 error ("unresolved overload for Altivec builtin %qF", fndecl);
7750 target = altivec_expand_ld_builtin (exp, target, expandedp);
7754 target = altivec_expand_st_builtin (exp, target, expandedp);
7758 target = altivec_expand_dst_builtin (exp, target, expandedp);
7766 case ALTIVEC_BUILTIN_STVX:
7767 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7768 case ALTIVEC_BUILTIN_STVEBX:
7769 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7770 case ALTIVEC_BUILTIN_STVEHX:
7771 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7772 case ALTIVEC_BUILTIN_STVEWX:
7773 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7774 case ALTIVEC_BUILTIN_STVXL:
7775 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7777 case ALTIVEC_BUILTIN_MFVSCR:
7778 icode = CODE_FOR_altivec_mfvscr;
7779 tmode = insn_data[icode].operand[0].mode;
7782 || GET_MODE (target) != tmode
7783 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7784 target = gen_reg_rtx (tmode);
7786 pat = GEN_FCN (icode) (target);
7792 case ALTIVEC_BUILTIN_MTVSCR:
7793 icode = CODE_FOR_altivec_mtvscr;
7794 arg0 = CALL_EXPR_ARG (exp, 0);
7795 op0 = expand_normal (arg0);
7796 mode0 = insn_data[icode].operand[0].mode;
7798 /* If we got invalid arguments bail out before generating bad rtl. */
7799 if (arg0 == error_mark_node)
7802 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7803 op0 = copy_to_mode_reg (mode0, op0);
7805 pat = GEN_FCN (icode) (op0);
7810 case ALTIVEC_BUILTIN_DSSALL:
7811 emit_insn (gen_altivec_dssall ());
7814 case ALTIVEC_BUILTIN_DSS:
7815 icode = CODE_FOR_altivec_dss;
7816 arg0 = CALL_EXPR_ARG (exp, 0);
7818 op0 = expand_normal (arg0);
7819 mode0 = insn_data[icode].operand[0].mode;
7821 /* If we got invalid arguments bail out before generating bad rtl. */
7822 if (arg0 == error_mark_node)
7825 if (TREE_CODE (arg0) != INTEGER_CST
7826 || TREE_INT_CST_LOW (arg0) & ~0x3)
7828 error ("argument to dss must be a 2-bit unsigned literal");
7832 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7833 op0 = copy_to_mode_reg (mode0, op0);
7835 emit_insn (gen_altivec_dss (op0));
7838 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7839 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7840 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7841 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7842 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
7844 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7845 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7846 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7847 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7848 return altivec_expand_vec_set_builtin (exp);
7850 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7851 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7852 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7853 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7854 return altivec_expand_vec_ext_builtin (exp, target);
7861 /* Expand abs* operations. */
7862 d = (struct builtin_description *) bdesc_abs;
7863 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7864 if (d->code == fcode)
7865 return altivec_expand_abs_builtin (d->icode, exp, target);
7867 /* Expand the AltiVec predicates. */
7868 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7869 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7870 if (dp->code == fcode)
7871 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7874 /* LV* are funky. We initialized them differently. */
7877 case ALTIVEC_BUILTIN_LVSL:
7878 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7880 case ALTIVEC_BUILTIN_LVSR:
7881 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7883 case ALTIVEC_BUILTIN_LVEBX:
7884 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7886 case ALTIVEC_BUILTIN_LVEHX:
7887 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7889 case ALTIVEC_BUILTIN_LVEWX:
7890 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7892 case ALTIVEC_BUILTIN_LVXL:
7893 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7895 case ALTIVEC_BUILTIN_LVX:
7896 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7907 /* Binops that need to be initialized manually, but can be expanded
7908 automagically by rs6000_expand_binop_builtin. */
7909 static struct builtin_description bdesc_2arg_spe[] =
7911 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7912 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7913 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7914 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7915 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7916 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7917 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7918 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7919 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7920 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7921 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7922 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7923 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7924 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7925 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7926 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7927 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7928 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7929 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7930 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7931 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7932 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7935 /* Expand the builtin in EXP and store the result in TARGET. Store
7936 true in *EXPANDEDP if we found a builtin to expand.
7938 This expands the SPE builtins that are not simple unary and binary
7941 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7943 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7945 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7946 enum insn_code icode;
7947 enum machine_mode tmode, mode0;
7949 struct builtin_description *d;
7954 /* Syntax check for a 5-bit unsigned immediate. */
7957 case SPE_BUILTIN_EVSTDD:
7958 case SPE_BUILTIN_EVSTDH:
7959 case SPE_BUILTIN_EVSTDW:
7960 case SPE_BUILTIN_EVSTWHE:
7961 case SPE_BUILTIN_EVSTWHO:
7962 case SPE_BUILTIN_EVSTWWE:
7963 case SPE_BUILTIN_EVSTWWO:
7964 arg1 = CALL_EXPR_ARG (exp, 2);
7965 if (TREE_CODE (arg1) != INTEGER_CST
7966 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7968 error ("argument 2 must be a 5-bit unsigned literal");
7976 /* The evsplat*i instructions are not quite generic. */
7979 case SPE_BUILTIN_EVSPLATFI:
7980 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7982 case SPE_BUILTIN_EVSPLATI:
7983 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7989 d = (struct builtin_description *) bdesc_2arg_spe;
7990 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7991 if (d->code == fcode)
7992 return rs6000_expand_binop_builtin (d->icode, exp, target);
7994 d = (struct builtin_description *) bdesc_spe_predicates;
7995 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7996 if (d->code == fcode)
7997 return spe_expand_predicate_builtin (d->icode, exp, target);
7999 d = (struct builtin_description *) bdesc_spe_evsel;
8000 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8001 if (d->code == fcode)
8002 return spe_expand_evsel_builtin (d->icode, exp, target);
8006 case SPE_BUILTIN_EVSTDDX:
8007 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8008 case SPE_BUILTIN_EVSTDHX:
8009 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8010 case SPE_BUILTIN_EVSTDWX:
8011 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8012 case SPE_BUILTIN_EVSTWHEX:
8013 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8014 case SPE_BUILTIN_EVSTWHOX:
8015 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8016 case SPE_BUILTIN_EVSTWWEX:
8017 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8018 case SPE_BUILTIN_EVSTWWOX:
8019 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8020 case SPE_BUILTIN_EVSTDD:
8021 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8022 case SPE_BUILTIN_EVSTDH:
8023 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8024 case SPE_BUILTIN_EVSTDW:
8025 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8026 case SPE_BUILTIN_EVSTWHE:
8027 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8028 case SPE_BUILTIN_EVSTWHO:
8029 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8030 case SPE_BUILTIN_EVSTWWE:
8031 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8032 case SPE_BUILTIN_EVSTWWO:
8033 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8034 case SPE_BUILTIN_MFSPEFSCR:
8035 icode = CODE_FOR_spe_mfspefscr;
8036 tmode = insn_data[icode].operand[0].mode;
8039 || GET_MODE (target) != tmode
8040 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8041 target = gen_reg_rtx (tmode);
8043 pat = GEN_FCN (icode) (target);
8048 case SPE_BUILTIN_MTSPEFSCR:
8049 icode = CODE_FOR_spe_mtspefscr;
8050 arg0 = CALL_EXPR_ARG (exp, 0);
8051 op0 = expand_normal (arg0);
8052 mode0 = insn_data[icode].operand[0].mode;
8054 if (arg0 == error_mark_node)
8057 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8058 op0 = copy_to_mode_reg (mode0, op0);
8060 pat = GEN_FCN (icode) (op0);
8073 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8075 rtx pat, scratch, tmp;
8076 tree form = CALL_EXPR_ARG (exp, 0);
8077 tree arg0 = CALL_EXPR_ARG (exp, 1);
8078 tree arg1 = CALL_EXPR_ARG (exp, 2);
8079 rtx op0 = expand_normal (arg0);
8080 rtx op1 = expand_normal (arg1);
8081 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8082 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8086 if (TREE_CODE (form) != INTEGER_CST)
8088 error ("argument 1 of __builtin_spe_predicate must be a constant");
8092 form_int = TREE_INT_CST_LOW (form);
8094 gcc_assert (mode0 == mode1);
8096 if (arg0 == error_mark_node || arg1 == error_mark_node)
8100 || GET_MODE (target) != SImode
8101 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8102 target = gen_reg_rtx (SImode);
8104 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8105 op0 = copy_to_mode_reg (mode0, op0);
8106 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8107 op1 = copy_to_mode_reg (mode1, op1);
8109 scratch = gen_reg_rtx (CCmode);
8111 pat = GEN_FCN (icode) (scratch, op0, op1);
8116 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8117 _lower_. We use one compare, but look in different bits of the
8118 CR for each variant.
8120 There are 2 elements in each SPE simd type (upper/lower). The CR
8121 bits are set as follows:
8123 BIT0 | BIT 1 | BIT 2 | BIT 3
8124 U | L | (U | L) | (U & L)
8126 So, for an "all" relationship, BIT 3 would be set.
8127 For an "any" relationship, BIT 2 would be set. Etc.
8129 Following traditional nomenclature, these bits map to:
8131 BIT0 | BIT 1 | BIT 2 | BIT 3
8134 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8139 /* All variant. OV bit. */
8141 /* We need to get to the OV bit, which is the ORDERED bit. We
8142 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8143 that's ugly and will make validate_condition_mode die.
8144 So let's just use another pattern. */
8145 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8147 /* Any variant. EQ bit. */
8151 /* Upper variant. LT bit. */
8155 /* Lower variant. GT bit. */
8160 error ("argument 1 of __builtin_spe_predicate is out of range");
8164 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8165 emit_move_insn (target, tmp);
8170 /* The evsel builtins look like this:
8172 e = __builtin_spe_evsel_OP (a, b, c, d);
8176 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8177 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8181 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8184 tree arg0 = CALL_EXPR_ARG (exp, 0);
8185 tree arg1 = CALL_EXPR_ARG (exp, 1);
8186 tree arg2 = CALL_EXPR_ARG (exp, 2);
8187 tree arg3 = CALL_EXPR_ARG (exp, 3);
8188 rtx op0 = expand_normal (arg0);
8189 rtx op1 = expand_normal (arg1);
8190 rtx op2 = expand_normal (arg2);
8191 rtx op3 = expand_normal (arg3);
8192 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8193 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8195 gcc_assert (mode0 == mode1);
8197 if (arg0 == error_mark_node || arg1 == error_mark_node
8198 || arg2 == error_mark_node || arg3 == error_mark_node)
8202 || GET_MODE (target) != mode0
8203 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8204 target = gen_reg_rtx (mode0);
8206 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8207 op0 = copy_to_mode_reg (mode0, op0);
8208 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8209 op1 = copy_to_mode_reg (mode0, op1);
8210 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8211 op2 = copy_to_mode_reg (mode0, op2);
8212 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8213 op3 = copy_to_mode_reg (mode0, op3);
8215 /* Generate the compare. */
8216 scratch = gen_reg_rtx (CCmode);
8217 pat = GEN_FCN (icode) (scratch, op0, op1);
8222 if (mode0 == V2SImode)
8223 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8225 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8230 /* Expand an expression EXP that calls a built-in function,
8231 with result going to TARGET if that's convenient
8232 (and in mode MODE if that's convenient).
8233 SUBTARGET may be used as the target for computing one of EXP's operands.
8234 IGNORE is nonzero if the value is to be ignored. */
8237 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8238 enum machine_mode mode ATTRIBUTE_UNUSED,
8239 int ignore ATTRIBUTE_UNUSED)
8241 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8242 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8243 struct builtin_description *d;
8248 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8249 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8251 int icode = (int) CODE_FOR_altivec_lvsr;
8252 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8253 enum machine_mode mode = insn_data[icode].operand[1].mode;
8257 gcc_assert (TARGET_ALTIVEC);
8259 arg = CALL_EXPR_ARG (exp, 0);
8260 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8261 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8262 addr = memory_address (mode, op);
8263 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8267 /* For the load case need to negate the address. */
8268 op = gen_reg_rtx (GET_MODE (addr));
8269 emit_insn (gen_rtx_SET (VOIDmode, op,
8270 gen_rtx_NEG (GET_MODE (addr), addr)));
8272 op = gen_rtx_MEM (mode, op);
8275 || GET_MODE (target) != tmode
8276 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8277 target = gen_reg_rtx (tmode);
8279 /*pat = gen_altivec_lvsr (target, op);*/
8280 pat = GEN_FCN (icode) (target, op);
8288 /* FIXME: There's got to be a nicer way to handle this case than
8289 constructing a new CALL_EXPR. */
8290 if (fcode == ALTIVEC_BUILTIN_VCFUX
8291 || fcode == ALTIVEC_BUILTIN_VCFSX)
8293 if (call_expr_nargs (exp) == 1)
8294 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8295 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8300 ret = altivec_expand_builtin (exp, target, &success);
8307 ret = spe_expand_builtin (exp, target, &success);
8313 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8315 /* Handle simple unary operations. */
8316 d = (struct builtin_description *) bdesc_1arg;
8317 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8318 if (d->code == fcode)
8319 return rs6000_expand_unop_builtin (d->icode, exp, target);
8321 /* Handle simple binary operations. */
8322 d = (struct builtin_description *) bdesc_2arg;
8323 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8324 if (d->code == fcode)
8325 return rs6000_expand_binop_builtin (d->icode, exp, target);
8327 /* Handle simple ternary operations. */
8328 d = (struct builtin_description *) bdesc_3arg;
8329 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8330 if (d->code == fcode)
8331 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8337 build_opaque_vector_type (tree node, int nunits)
8339 node = copy_node (node);
8340 TYPE_MAIN_VARIANT (node) = node;
8341 return build_vector_type (node, nunits);
8345 rs6000_init_builtins (void)
8347 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8348 V2SF_type_node = build_vector_type (float_type_node, 2);
8349 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8350 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8351 V4SF_type_node = build_vector_type (float_type_node, 4);
8352 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8353 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8355 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8356 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8357 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8359 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8360 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8361 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8362 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8364 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8365 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8366 'vector unsigned short'. */
8368 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8369 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8370 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8371 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8373 long_integer_type_internal_node = long_integer_type_node;
8374 long_unsigned_type_internal_node = long_unsigned_type_node;
8375 intQI_type_internal_node = intQI_type_node;
8376 uintQI_type_internal_node = unsigned_intQI_type_node;
8377 intHI_type_internal_node = intHI_type_node;
8378 uintHI_type_internal_node = unsigned_intHI_type_node;
8379 intSI_type_internal_node = intSI_type_node;
8380 uintSI_type_internal_node = unsigned_intSI_type_node;
8381 float_type_internal_node = float_type_node;
8382 void_type_internal_node = void_type_node;
8384 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8385 get_identifier ("__bool char"),
8386 bool_char_type_node));
8387 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8388 get_identifier ("__bool short"),
8389 bool_short_type_node));
8390 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8391 get_identifier ("__bool int"),
8392 bool_int_type_node));
8393 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8394 get_identifier ("__pixel"),
8397 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8398 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8399 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8400 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8402 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8403 get_identifier ("__vector unsigned char"),
8404 unsigned_V16QI_type_node));
8405 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8406 get_identifier ("__vector signed char"),
8408 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8409 get_identifier ("__vector __bool char"),
8410 bool_V16QI_type_node));
8412 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8413 get_identifier ("__vector unsigned short"),
8414 unsigned_V8HI_type_node));
8415 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8416 get_identifier ("__vector signed short"),
8418 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8419 get_identifier ("__vector __bool short"),
8420 bool_V8HI_type_node));
8422 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8423 get_identifier ("__vector unsigned int"),
8424 unsigned_V4SI_type_node));
8425 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8426 get_identifier ("__vector signed int"),
8428 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8429 get_identifier ("__vector __bool int"),
8430 bool_V4SI_type_node));
8432 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8433 get_identifier ("__vector float"),
8435 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8436 get_identifier ("__vector __pixel"),
8437 pixel_V8HI_type_node));
8440 spe_init_builtins ();
8442 altivec_init_builtins ();
8443 if (TARGET_ALTIVEC || TARGET_SPE)
8444 rs6000_common_init_builtins ();
8447 /* AIX libm provides clog as __clog. */
8448 if (built_in_decls [BUILT_IN_CLOG])
8449 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8453 /* Search through a set of builtins and enable the mask bits.
8454 DESC is an array of builtins.
8455 SIZE is the total number of builtins.
8456 START is the builtin enum at which to start.
8457 END is the builtin enum at which to end. */
8459 enable_mask_for_builtins (struct builtin_description *desc, int size,
8460 enum rs6000_builtins start,
8461 enum rs6000_builtins end)
8465 for (i = 0; i < size; ++i)
8466 if (desc[i].code == start)
8472 for (; i < size; ++i)
8474 /* Flip all the bits on. */
8475 desc[i].mask = target_flags;
8476 if (desc[i].code == end)
8482 spe_init_builtins (void)
8484 tree endlink = void_list_node;
8485 tree puint_type_node = build_pointer_type (unsigned_type_node);
8486 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8487 struct builtin_description *d;
8490 tree v2si_ftype_4_v2si
8491 = build_function_type
8492 (opaque_V2SI_type_node,
8493 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8494 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8495 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8496 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8499 tree v2sf_ftype_4_v2sf
8500 = build_function_type
8501 (opaque_V2SF_type_node,
8502 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8503 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8504 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8505 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8508 tree int_ftype_int_v2si_v2si
8509 = build_function_type
8511 tree_cons (NULL_TREE, integer_type_node,
8512 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8513 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8516 tree int_ftype_int_v2sf_v2sf
8517 = build_function_type
8519 tree_cons (NULL_TREE, integer_type_node,
8520 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8521 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8524 tree void_ftype_v2si_puint_int
8525 = build_function_type (void_type_node,
8526 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8527 tree_cons (NULL_TREE, puint_type_node,
8528 tree_cons (NULL_TREE,
8532 tree void_ftype_v2si_puint_char
8533 = build_function_type (void_type_node,
8534 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8535 tree_cons (NULL_TREE, puint_type_node,
8536 tree_cons (NULL_TREE,
8540 tree void_ftype_v2si_pv2si_int
8541 = build_function_type (void_type_node,
8542 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8543 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8544 tree_cons (NULL_TREE,
8548 tree void_ftype_v2si_pv2si_char
8549 = build_function_type (void_type_node,
8550 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8551 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8552 tree_cons (NULL_TREE,
8557 = build_function_type (void_type_node,
8558 tree_cons (NULL_TREE, integer_type_node, endlink));
8561 = build_function_type (integer_type_node, endlink);
8563 tree v2si_ftype_pv2si_int
8564 = build_function_type (opaque_V2SI_type_node,
8565 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8566 tree_cons (NULL_TREE, integer_type_node,
8569 tree v2si_ftype_puint_int
8570 = build_function_type (opaque_V2SI_type_node,
8571 tree_cons (NULL_TREE, puint_type_node,
8572 tree_cons (NULL_TREE, integer_type_node,
8575 tree v2si_ftype_pushort_int
8576 = build_function_type (opaque_V2SI_type_node,
8577 tree_cons (NULL_TREE, pushort_type_node,
8578 tree_cons (NULL_TREE, integer_type_node,
8581 tree v2si_ftype_signed_char
8582 = build_function_type (opaque_V2SI_type_node,
8583 tree_cons (NULL_TREE, signed_char_type_node,
8586 /* The initialization of the simple binary and unary builtins is
8587 done in rs6000_common_init_builtins, but we have to enable the
8588 mask bits here manually because we have run out of `target_flags'
8589 bits. We really need to redesign this mask business. */
8591 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8592 ARRAY_SIZE (bdesc_2arg),
8595 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8596 ARRAY_SIZE (bdesc_1arg),
8598 SPE_BUILTIN_EVSUBFUSIAAW);
8599 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8600 ARRAY_SIZE (bdesc_spe_predicates),
8601 SPE_BUILTIN_EVCMPEQ,
8602 SPE_BUILTIN_EVFSTSTLT);
8603 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8604 ARRAY_SIZE (bdesc_spe_evsel),
8605 SPE_BUILTIN_EVSEL_CMPGTS,
8606 SPE_BUILTIN_EVSEL_FSTSTEQ);
8608 (*lang_hooks.decls.pushdecl)
8609 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8610 opaque_V2SI_type_node));
8612 /* Initialize irregular SPE builtins. */
8614 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8615 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8616 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8617 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8618 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8619 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8620 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8621 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8622 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8623 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8624 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8625 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8626 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8627 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8628 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8629 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8630 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8631 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8634 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8635 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8636 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8637 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8638 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8639 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8640 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8641 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8642 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8643 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8644 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8645 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8646 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8647 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8648 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8649 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8650 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8651 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8652 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8653 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8654 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8655 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8658 d = (struct builtin_description *) bdesc_spe_predicates;
8659 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8663 switch (insn_data[d->icode].operand[1].mode)
8666 type = int_ftype_int_v2si_v2si;
8669 type = int_ftype_int_v2sf_v2sf;
8675 def_builtin (d->mask, d->name, type, d->code);
8678 /* Evsel predicates. */
8679 d = (struct builtin_description *) bdesc_spe_evsel;
8680 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8684 switch (insn_data[d->icode].operand[1].mode)
8687 type = v2si_ftype_4_v2si;
8690 type = v2sf_ftype_4_v2sf;
8696 def_builtin (d->mask, d->name, type, d->code);
8701 altivec_init_builtins (void)
8703 struct builtin_description *d;
8704 struct builtin_description_predicates *dp;
8708 tree pfloat_type_node = build_pointer_type (float_type_node);
8709 tree pint_type_node = build_pointer_type (integer_type_node);
8710 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8711 tree pchar_type_node = build_pointer_type (char_type_node);
8713 tree pvoid_type_node = build_pointer_type (void_type_node);
8715 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8716 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8717 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8718 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8720 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8722 tree int_ftype_opaque
8723 = build_function_type_list (integer_type_node,
8724 opaque_V4SI_type_node, NULL_TREE);
8726 tree opaque_ftype_opaque_int
8727 = build_function_type_list (opaque_V4SI_type_node,
8728 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8729 tree opaque_ftype_opaque_opaque_int
8730 = build_function_type_list (opaque_V4SI_type_node,
8731 opaque_V4SI_type_node, opaque_V4SI_type_node,
8732 integer_type_node, NULL_TREE);
8733 tree int_ftype_int_opaque_opaque
8734 = build_function_type_list (integer_type_node,
8735 integer_type_node, opaque_V4SI_type_node,
8736 opaque_V4SI_type_node, NULL_TREE);
8737 tree int_ftype_int_v4si_v4si
8738 = build_function_type_list (integer_type_node,
8739 integer_type_node, V4SI_type_node,
8740 V4SI_type_node, NULL_TREE);
8741 tree v4sf_ftype_pcfloat
8742 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8743 tree void_ftype_pfloat_v4sf
8744 = build_function_type_list (void_type_node,
8745 pfloat_type_node, V4SF_type_node, NULL_TREE);
8746 tree v4si_ftype_pcint
8747 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8748 tree void_ftype_pint_v4si
8749 = build_function_type_list (void_type_node,
8750 pint_type_node, V4SI_type_node, NULL_TREE);
8751 tree v8hi_ftype_pcshort
8752 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8753 tree void_ftype_pshort_v8hi
8754 = build_function_type_list (void_type_node,
8755 pshort_type_node, V8HI_type_node, NULL_TREE);
8756 tree v16qi_ftype_pcchar
8757 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8758 tree void_ftype_pchar_v16qi
8759 = build_function_type_list (void_type_node,
8760 pchar_type_node, V16QI_type_node, NULL_TREE);
8761 tree void_ftype_v4si
8762 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8763 tree v8hi_ftype_void
8764 = build_function_type (V8HI_type_node, void_list_node);
8765 tree void_ftype_void
8766 = build_function_type (void_type_node, void_list_node);
8768 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8770 tree opaque_ftype_long_pcvoid
8771 = build_function_type_list (opaque_V4SI_type_node,
8772 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8773 tree v16qi_ftype_long_pcvoid
8774 = build_function_type_list (V16QI_type_node,
8775 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8776 tree v8hi_ftype_long_pcvoid
8777 = build_function_type_list (V8HI_type_node,
8778 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8779 tree v4si_ftype_long_pcvoid
8780 = build_function_type_list (V4SI_type_node,
8781 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8783 tree void_ftype_opaque_long_pvoid
8784 = build_function_type_list (void_type_node,
8785 opaque_V4SI_type_node, long_integer_type_node,
8786 pvoid_type_node, NULL_TREE);
8787 tree void_ftype_v4si_long_pvoid
8788 = build_function_type_list (void_type_node,
8789 V4SI_type_node, long_integer_type_node,
8790 pvoid_type_node, NULL_TREE);
8791 tree void_ftype_v16qi_long_pvoid
8792 = build_function_type_list (void_type_node,
8793 V16QI_type_node, long_integer_type_node,
8794 pvoid_type_node, NULL_TREE);
8795 tree void_ftype_v8hi_long_pvoid
8796 = build_function_type_list (void_type_node,
8797 V8HI_type_node, long_integer_type_node,
8798 pvoid_type_node, NULL_TREE);
8799 tree int_ftype_int_v8hi_v8hi
8800 = build_function_type_list (integer_type_node,
8801 integer_type_node, V8HI_type_node,
8802 V8HI_type_node, NULL_TREE);
8803 tree int_ftype_int_v16qi_v16qi
8804 = build_function_type_list (integer_type_node,
8805 integer_type_node, V16QI_type_node,
8806 V16QI_type_node, NULL_TREE);
8807 tree int_ftype_int_v4sf_v4sf
8808 = build_function_type_list (integer_type_node,
8809 integer_type_node, V4SF_type_node,
8810 V4SF_type_node, NULL_TREE);
8811 tree v4si_ftype_v4si
8812 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8813 tree v8hi_ftype_v8hi
8814 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8815 tree v16qi_ftype_v16qi
8816 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8817 tree v4sf_ftype_v4sf
8818 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8819 tree void_ftype_pcvoid_int_int
8820 = build_function_type_list (void_type_node,
8821 pcvoid_type_node, integer_type_node,
8822 integer_type_node, NULL_TREE);
8824 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8825 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8826 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8827 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8828 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8829 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8830 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8831 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8832 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8833 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8834 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8835 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8836 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8837 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8838 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8839 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8840 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8841 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8842 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8843 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8844 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8845 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8846 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8847 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8848 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8849 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8850 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8851 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8852 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8853 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8854 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8855 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8856 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8857 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8858 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8859 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8860 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8861 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8862 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8863 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8864 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8865 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8866 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8867 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8868 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8869 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8871 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8873 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8874 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8875 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8876 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8877 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8878 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8879 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8880 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8881 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8882 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8884 /* Add the DST variants. */
8885 d = (struct builtin_description *) bdesc_dst;
8886 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8887 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8889 /* Initialize the predicates. */
8890 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8891 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8893 enum machine_mode mode1;
8895 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8896 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8901 mode1 = insn_data[dp->icode].operand[1].mode;
8906 type = int_ftype_int_opaque_opaque;
8909 type = int_ftype_int_v4si_v4si;
8912 type = int_ftype_int_v8hi_v8hi;
8915 type = int_ftype_int_v16qi_v16qi;
8918 type = int_ftype_int_v4sf_v4sf;
8924 def_builtin (dp->mask, dp->name, type, dp->code);
8927 /* Initialize the abs* operators. */
8928 d = (struct builtin_description *) bdesc_abs;
8929 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8931 enum machine_mode mode0;
8934 mode0 = insn_data[d->icode].operand[0].mode;
8939 type = v4si_ftype_v4si;
8942 type = v8hi_ftype_v8hi;
8945 type = v16qi_ftype_v16qi;
8948 type = v4sf_ftype_v4sf;
8954 def_builtin (d->mask, d->name, type, d->code);
8961 /* Initialize target builtin that implements
8962 targetm.vectorize.builtin_mask_for_load. */
8964 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
8965 v16qi_ftype_long_pcvoid,
8966 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8967 BUILT_IN_MD, NULL, NULL_TREE);
8968 TREE_READONLY (decl) = 1;
8969 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8970 altivec_builtin_mask_for_load = decl;
8973 /* Access to the vec_init patterns. */
8974 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8975 integer_type_node, integer_type_node,
8976 integer_type_node, NULL_TREE);
8977 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8978 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8980 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8981 short_integer_type_node,
8982 short_integer_type_node,
8983 short_integer_type_node,
8984 short_integer_type_node,
8985 short_integer_type_node,
8986 short_integer_type_node,
8987 short_integer_type_node, NULL_TREE);
8988 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8989 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8991 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8992 char_type_node, char_type_node,
8993 char_type_node, char_type_node,
8994 char_type_node, char_type_node,
8995 char_type_node, char_type_node,
8996 char_type_node, char_type_node,
8997 char_type_node, char_type_node,
8998 char_type_node, char_type_node,
8999 char_type_node, NULL_TREE);
9000 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9001 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9003 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9004 float_type_node, float_type_node,
9005 float_type_node, NULL_TREE);
9006 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9007 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9009 /* Access to the vec_set patterns. */
9010 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9012 integer_type_node, NULL_TREE);
9013 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9014 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9016 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9018 integer_type_node, NULL_TREE);
9019 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9020 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9022 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9024 integer_type_node, NULL_TREE);
9025 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9026 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9028 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9030 integer_type_node, NULL_TREE);
9031 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9032 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9034 /* Access to the vec_extract patterns. */
9035 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9036 integer_type_node, NULL_TREE);
9037 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9038 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9040 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9041 integer_type_node, NULL_TREE);
9042 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9043 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9045 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9046 integer_type_node, NULL_TREE);
9047 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9048 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9050 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9051 integer_type_node, NULL_TREE);
9052 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9053 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9057 rs6000_common_init_builtins (void)
9059 struct builtin_description *d;
9062 tree v4sf_ftype_v4sf_v4sf_v16qi
9063 = build_function_type_list (V4SF_type_node,
9064 V4SF_type_node, V4SF_type_node,
9065 V16QI_type_node, NULL_TREE);
9066 tree v4si_ftype_v4si_v4si_v16qi
9067 = build_function_type_list (V4SI_type_node,
9068 V4SI_type_node, V4SI_type_node,
9069 V16QI_type_node, NULL_TREE);
9070 tree v8hi_ftype_v8hi_v8hi_v16qi
9071 = build_function_type_list (V8HI_type_node,
9072 V8HI_type_node, V8HI_type_node,
9073 V16QI_type_node, NULL_TREE);
9074 tree v16qi_ftype_v16qi_v16qi_v16qi
9075 = build_function_type_list (V16QI_type_node,
9076 V16QI_type_node, V16QI_type_node,
9077 V16QI_type_node, NULL_TREE);
9079 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9081 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9082 tree v16qi_ftype_int
9083 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9084 tree v8hi_ftype_v16qi
9085 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9086 tree v4sf_ftype_v4sf
9087 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9089 tree v2si_ftype_v2si_v2si
9090 = build_function_type_list (opaque_V2SI_type_node,
9091 opaque_V2SI_type_node,
9092 opaque_V2SI_type_node, NULL_TREE);
9094 tree v2sf_ftype_v2sf_v2sf
9095 = build_function_type_list (opaque_V2SF_type_node,
9096 opaque_V2SF_type_node,
9097 opaque_V2SF_type_node, NULL_TREE);
9099 tree v2si_ftype_int_int
9100 = build_function_type_list (opaque_V2SI_type_node,
9101 integer_type_node, integer_type_node,
9104 tree opaque_ftype_opaque
9105 = build_function_type_list (opaque_V4SI_type_node,
9106 opaque_V4SI_type_node, NULL_TREE);
9108 tree v2si_ftype_v2si
9109 = build_function_type_list (opaque_V2SI_type_node,
9110 opaque_V2SI_type_node, NULL_TREE);
9112 tree v2sf_ftype_v2sf
9113 = build_function_type_list (opaque_V2SF_type_node,
9114 opaque_V2SF_type_node, NULL_TREE);
9116 tree v2sf_ftype_v2si
9117 = build_function_type_list (opaque_V2SF_type_node,
9118 opaque_V2SI_type_node, NULL_TREE);
9120 tree v2si_ftype_v2sf
9121 = build_function_type_list (opaque_V2SI_type_node,
9122 opaque_V2SF_type_node, NULL_TREE);
9124 tree v2si_ftype_v2si_char
9125 = build_function_type_list (opaque_V2SI_type_node,
9126 opaque_V2SI_type_node,
9127 char_type_node, NULL_TREE);
9129 tree v2si_ftype_int_char
9130 = build_function_type_list (opaque_V2SI_type_node,
9131 integer_type_node, char_type_node, NULL_TREE);
9133 tree v2si_ftype_char
9134 = build_function_type_list (opaque_V2SI_type_node,
9135 char_type_node, NULL_TREE);
9137 tree int_ftype_int_int
9138 = build_function_type_list (integer_type_node,
9139 integer_type_node, integer_type_node,
9142 tree opaque_ftype_opaque_opaque
9143 = build_function_type_list (opaque_V4SI_type_node,
9144 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9145 tree v4si_ftype_v4si_v4si
9146 = build_function_type_list (V4SI_type_node,
9147 V4SI_type_node, V4SI_type_node, NULL_TREE);
9148 tree v4sf_ftype_v4si_int
9149 = build_function_type_list (V4SF_type_node,
9150 V4SI_type_node, integer_type_node, NULL_TREE);
9151 tree v4si_ftype_v4sf_int
9152 = build_function_type_list (V4SI_type_node,
9153 V4SF_type_node, integer_type_node, NULL_TREE);
9154 tree v4si_ftype_v4si_int
9155 = build_function_type_list (V4SI_type_node,
9156 V4SI_type_node, integer_type_node, NULL_TREE);
9157 tree v8hi_ftype_v8hi_int
9158 = build_function_type_list (V8HI_type_node,
9159 V8HI_type_node, integer_type_node, NULL_TREE);
9160 tree v16qi_ftype_v16qi_int
9161 = build_function_type_list (V16QI_type_node,
9162 V16QI_type_node, integer_type_node, NULL_TREE);
9163 tree v16qi_ftype_v16qi_v16qi_int
9164 = build_function_type_list (V16QI_type_node,
9165 V16QI_type_node, V16QI_type_node,
9166 integer_type_node, NULL_TREE);
9167 tree v8hi_ftype_v8hi_v8hi_int
9168 = build_function_type_list (V8HI_type_node,
9169 V8HI_type_node, V8HI_type_node,
9170 integer_type_node, NULL_TREE);
9171 tree v4si_ftype_v4si_v4si_int
9172 = build_function_type_list (V4SI_type_node,
9173 V4SI_type_node, V4SI_type_node,
9174 integer_type_node, NULL_TREE);
9175 tree v4sf_ftype_v4sf_v4sf_int
9176 = build_function_type_list (V4SF_type_node,
9177 V4SF_type_node, V4SF_type_node,
9178 integer_type_node, NULL_TREE);
9179 tree v4sf_ftype_v4sf_v4sf
9180 = build_function_type_list (V4SF_type_node,
9181 V4SF_type_node, V4SF_type_node, NULL_TREE);
9182 tree opaque_ftype_opaque_opaque_opaque
9183 = build_function_type_list (opaque_V4SI_type_node,
9184 opaque_V4SI_type_node, opaque_V4SI_type_node,
9185 opaque_V4SI_type_node, NULL_TREE);
9186 tree v4sf_ftype_v4sf_v4sf_v4si
9187 = build_function_type_list (V4SF_type_node,
9188 V4SF_type_node, V4SF_type_node,
9189 V4SI_type_node, NULL_TREE);
9190 tree v4sf_ftype_v4sf_v4sf_v4sf
9191 = build_function_type_list (V4SF_type_node,
9192 V4SF_type_node, V4SF_type_node,
9193 V4SF_type_node, NULL_TREE);
9194 tree v4si_ftype_v4si_v4si_v4si
9195 = build_function_type_list (V4SI_type_node,
9196 V4SI_type_node, V4SI_type_node,
9197 V4SI_type_node, NULL_TREE);
9198 tree v8hi_ftype_v8hi_v8hi
9199 = build_function_type_list (V8HI_type_node,
9200 V8HI_type_node, V8HI_type_node, NULL_TREE);
9201 tree v8hi_ftype_v8hi_v8hi_v8hi
9202 = build_function_type_list (V8HI_type_node,
9203 V8HI_type_node, V8HI_type_node,
9204 V8HI_type_node, NULL_TREE);
9205 tree v4si_ftype_v8hi_v8hi_v4si
9206 = build_function_type_list (V4SI_type_node,
9207 V8HI_type_node, V8HI_type_node,
9208 V4SI_type_node, NULL_TREE);
9209 tree v4si_ftype_v16qi_v16qi_v4si
9210 = build_function_type_list (V4SI_type_node,
9211 V16QI_type_node, V16QI_type_node,
9212 V4SI_type_node, NULL_TREE);
9213 tree v16qi_ftype_v16qi_v16qi
9214 = build_function_type_list (V16QI_type_node,
9215 V16QI_type_node, V16QI_type_node, NULL_TREE);
9216 tree v4si_ftype_v4sf_v4sf
9217 = build_function_type_list (V4SI_type_node,
9218 V4SF_type_node, V4SF_type_node, NULL_TREE);
9219 tree v8hi_ftype_v16qi_v16qi
9220 = build_function_type_list (V8HI_type_node,
9221 V16QI_type_node, V16QI_type_node, NULL_TREE);
9222 tree v4si_ftype_v8hi_v8hi
9223 = build_function_type_list (V4SI_type_node,
9224 V8HI_type_node, V8HI_type_node, NULL_TREE);
9225 tree v8hi_ftype_v4si_v4si
9226 = build_function_type_list (V8HI_type_node,
9227 V4SI_type_node, V4SI_type_node, NULL_TREE);
9228 tree v16qi_ftype_v8hi_v8hi
9229 = build_function_type_list (V16QI_type_node,
9230 V8HI_type_node, V8HI_type_node, NULL_TREE);
9231 tree v4si_ftype_v16qi_v4si
9232 = build_function_type_list (V4SI_type_node,
9233 V16QI_type_node, V4SI_type_node, NULL_TREE);
9234 tree v4si_ftype_v16qi_v16qi
9235 = build_function_type_list (V4SI_type_node,
9236 V16QI_type_node, V16QI_type_node, NULL_TREE);
9237 tree v4si_ftype_v8hi_v4si
9238 = build_function_type_list (V4SI_type_node,
9239 V8HI_type_node, V4SI_type_node, NULL_TREE);
9240 tree v4si_ftype_v8hi
9241 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9242 tree int_ftype_v4si_v4si
9243 = build_function_type_list (integer_type_node,
9244 V4SI_type_node, V4SI_type_node, NULL_TREE);
9245 tree int_ftype_v4sf_v4sf
9246 = build_function_type_list (integer_type_node,
9247 V4SF_type_node, V4SF_type_node, NULL_TREE);
9248 tree int_ftype_v16qi_v16qi
9249 = build_function_type_list (integer_type_node,
9250 V16QI_type_node, V16QI_type_node, NULL_TREE);
9251 tree int_ftype_v8hi_v8hi
9252 = build_function_type_list (integer_type_node,
9253 V8HI_type_node, V8HI_type_node, NULL_TREE);
9255 /* Add the simple ternary operators. */
9256 d = (struct builtin_description *) bdesc_3arg;
9257 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9259 enum machine_mode mode0, mode1, mode2, mode3;
9261 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9262 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9273 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9276 mode0 = insn_data[d->icode].operand[0].mode;
9277 mode1 = insn_data[d->icode].operand[1].mode;
9278 mode2 = insn_data[d->icode].operand[2].mode;
9279 mode3 = insn_data[d->icode].operand[3].mode;
9282 /* When all four are of the same mode. */
9283 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9288 type = opaque_ftype_opaque_opaque_opaque;
9291 type = v4si_ftype_v4si_v4si_v4si;
9294 type = v4sf_ftype_v4sf_v4sf_v4sf;
9297 type = v8hi_ftype_v8hi_v8hi_v8hi;
9300 type = v16qi_ftype_v16qi_v16qi_v16qi;
9306 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9311 type = v4si_ftype_v4si_v4si_v16qi;
9314 type = v4sf_ftype_v4sf_v4sf_v16qi;
9317 type = v8hi_ftype_v8hi_v8hi_v16qi;
9320 type = v16qi_ftype_v16qi_v16qi_v16qi;
9326 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9327 && mode3 == V4SImode)
9328 type = v4si_ftype_v16qi_v16qi_v4si;
9329 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9330 && mode3 == V4SImode)
9331 type = v4si_ftype_v8hi_v8hi_v4si;
9332 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9333 && mode3 == V4SImode)
9334 type = v4sf_ftype_v4sf_v4sf_v4si;
9336 /* vchar, vchar, vchar, 4-bit literal. */
9337 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9339 type = v16qi_ftype_v16qi_v16qi_int;
9341 /* vshort, vshort, vshort, 4-bit literal. */
9342 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9344 type = v8hi_ftype_v8hi_v8hi_int;
9346 /* vint, vint, vint, 4-bit literal. */
9347 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9349 type = v4si_ftype_v4si_v4si_int;
9351 /* vfloat, vfloat, vfloat, 4-bit literal. */
9352 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9354 type = v4sf_ftype_v4sf_v4sf_int;
9359 def_builtin (d->mask, d->name, type, d->code);
9362 /* Add the simple binary operators. */
9363 d = (struct builtin_description *) bdesc_2arg;
9364 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9366 enum machine_mode mode0, mode1, mode2;
9368 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9369 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9379 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9382 mode0 = insn_data[d->icode].operand[0].mode;
9383 mode1 = insn_data[d->icode].operand[1].mode;
9384 mode2 = insn_data[d->icode].operand[2].mode;
9387 /* When all three operands are of the same mode. */
9388 if (mode0 == mode1 && mode1 == mode2)
9393 type = opaque_ftype_opaque_opaque;
9396 type = v4sf_ftype_v4sf_v4sf;
9399 type = v4si_ftype_v4si_v4si;
9402 type = v16qi_ftype_v16qi_v16qi;
9405 type = v8hi_ftype_v8hi_v8hi;
9408 type = v2si_ftype_v2si_v2si;
9411 type = v2sf_ftype_v2sf_v2sf;
9414 type = int_ftype_int_int;
9421 /* A few other combos we really don't want to do manually. */
9423 /* vint, vfloat, vfloat. */
9424 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9425 type = v4si_ftype_v4sf_v4sf;
9427 /* vshort, vchar, vchar. */
9428 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9429 type = v8hi_ftype_v16qi_v16qi;
9431 /* vint, vshort, vshort. */
9432 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9433 type = v4si_ftype_v8hi_v8hi;
9435 /* vshort, vint, vint. */
9436 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9437 type = v8hi_ftype_v4si_v4si;
9439 /* vchar, vshort, vshort. */
9440 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9441 type = v16qi_ftype_v8hi_v8hi;
9443 /* vint, vchar, vint. */
9444 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9445 type = v4si_ftype_v16qi_v4si;
9447 /* vint, vchar, vchar. */
9448 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9449 type = v4si_ftype_v16qi_v16qi;
9451 /* vint, vshort, vint. */
9452 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9453 type = v4si_ftype_v8hi_v4si;
9455 /* vint, vint, 5-bit literal. */
9456 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9457 type = v4si_ftype_v4si_int;
9459 /* vshort, vshort, 5-bit literal. */
9460 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9461 type = v8hi_ftype_v8hi_int;
9463 /* vchar, vchar, 5-bit literal. */
9464 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9465 type = v16qi_ftype_v16qi_int;
9467 /* vfloat, vint, 5-bit literal. */
9468 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9469 type = v4sf_ftype_v4si_int;
9471 /* vint, vfloat, 5-bit literal. */
9472 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9473 type = v4si_ftype_v4sf_int;
9475 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9476 type = v2si_ftype_int_int;
9478 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9479 type = v2si_ftype_v2si_char;
9481 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9482 type = v2si_ftype_int_char;
9487 gcc_assert (mode0 == SImode);
9491 type = int_ftype_v4si_v4si;
9494 type = int_ftype_v4sf_v4sf;
9497 type = int_ftype_v16qi_v16qi;
9500 type = int_ftype_v8hi_v8hi;
9507 def_builtin (d->mask, d->name, type, d->code);
9510 /* Add the simple unary operators. */
9511 d = (struct builtin_description *) bdesc_1arg;
9512 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9514 enum machine_mode mode0, mode1;
9516 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9517 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9526 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9529 mode0 = insn_data[d->icode].operand[0].mode;
9530 mode1 = insn_data[d->icode].operand[1].mode;
9533 if (mode0 == V4SImode && mode1 == QImode)
9534 type = v4si_ftype_int;
9535 else if (mode0 == V8HImode && mode1 == QImode)
9536 type = v8hi_ftype_int;
9537 else if (mode0 == V16QImode && mode1 == QImode)
9538 type = v16qi_ftype_int;
9539 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9540 type = opaque_ftype_opaque;
9541 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9542 type = v4sf_ftype_v4sf;
9543 else if (mode0 == V8HImode && mode1 == V16QImode)
9544 type = v8hi_ftype_v16qi;
9545 else if (mode0 == V4SImode && mode1 == V8HImode)
9546 type = v4si_ftype_v8hi;
9547 else if (mode0 == V2SImode && mode1 == V2SImode)
9548 type = v2si_ftype_v2si;
9549 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9550 type = v2sf_ftype_v2sf;
9551 else if (mode0 == V2SFmode && mode1 == V2SImode)
9552 type = v2sf_ftype_v2si;
9553 else if (mode0 == V2SImode && mode1 == V2SFmode)
9554 type = v2si_ftype_v2sf;
9555 else if (mode0 == V2SImode && mode1 == QImode)
9556 type = v2si_ftype_char;
9560 def_builtin (d->mask, d->name, type, d->code);
9565 rs6000_init_libfuncs (void)
9567 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9568 && !TARGET_POWER2 && !TARGET_POWERPC)
9570 /* AIX library routines for float->int conversion. */
9571 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9572 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9573 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9574 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9577 if (!TARGET_IEEEQUAD)
9578 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9579 if (!TARGET_XL_COMPAT)
9581 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9582 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9583 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9584 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9586 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9588 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9589 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9590 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9591 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9592 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9593 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9594 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9596 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9597 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9598 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9599 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9600 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9601 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9602 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9603 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9606 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
9607 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9611 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9612 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9613 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9614 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9618 /* 32-bit SVR4 quad floating point routines. */
9620 set_optab_libfunc (add_optab, TFmode, "_q_add");
9621 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9622 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9623 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9624 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9625 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9626 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9628 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9629 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9630 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9631 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9632 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9633 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9635 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9636 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9637 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9638 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9639 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9640 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9641 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9642 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9647 /* Expand a block clear operation, and return 1 if successful. Return 0
9648 if we should let the compiler generate normal code.
9650 operands[0] is the destination
9651 operands[1] is the length
9652 operands[3] is the alignment */
9655 expand_block_clear (rtx operands[])
9657 rtx orig_dest = operands[0];
9658 rtx bytes_rtx = operands[1];
9659 rtx align_rtx = operands[3];
9660 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9661 HOST_WIDE_INT align;
9662 HOST_WIDE_INT bytes;
9667 /* If this is not a fixed size move, just call memcpy */
9671 /* This must be a fixed size alignment */
9672 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9673 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9675 /* Anything to clear? */
9676 bytes = INTVAL (bytes_rtx);
9680 /* Use the builtin memset after a point, to avoid huge code bloat.
9681 When optimize_size, avoid any significant code bloat; calling
9682 memset is about 4 instructions, so allow for one instruction to
9683 load zero and three to do clearing. */
9684 if (TARGET_ALTIVEC && align >= 128)
9686 else if (TARGET_POWERPC64 && align >= 32)
9691 if (optimize_size && bytes > 3 * clear_step)
9693 if (! optimize_size && bytes > 8 * clear_step)
9696 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9698 enum machine_mode mode = BLKmode;
9701 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9706 else if (bytes >= 8 && TARGET_POWERPC64
9707 /* 64-bit loads and stores require word-aligned
9709 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9714 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9715 { /* move 4 bytes */
9719 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9720 { /* move 2 bytes */
9724 else /* move 1 byte at a time */
9730 dest = adjust_address (orig_dest, mode, offset);
9732 emit_move_insn (dest, CONST0_RTX (mode));
9739 /* Expand a block move operation, and return 1 if successful. Return 0
9740 if we should let the compiler generate normal code.
9742 operands[0] is the destination
9743 operands[1] is the source
9744 operands[2] is the length
9745 operands[3] is the alignment */
9747 #define MAX_MOVE_REG 4
9750 expand_block_move (rtx operands[])
9752 rtx orig_dest = operands[0];
9753 rtx orig_src = operands[1];
9754 rtx bytes_rtx = operands[2];
9755 rtx align_rtx = operands[3];
9756 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9761 rtx stores[MAX_MOVE_REG];
9764 /* If this is not a fixed size move, just call memcpy */
9768 /* This must be a fixed size alignment */
9769 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9770 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9772 /* Anything to move? */
9773 bytes = INTVAL (bytes_rtx);
9777 /* store_one_arg depends on expand_block_move to handle at least the size of
9778 reg_parm_stack_space. */
9779 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9782 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9785 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9786 rtx (*mov) (rtx, rtx);
9788 enum machine_mode mode = BLKmode;
9791 /* Altivec first, since it will be faster than a string move
9792 when it applies, and usually not significantly larger. */
9793 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9797 gen_func.mov = gen_movv4si;
9799 else if (TARGET_STRING
9800 && bytes > 24 /* move up to 32 bytes at a time */
9808 && ! fixed_regs[12])
9810 move_bytes = (bytes > 32) ? 32 : bytes;
9811 gen_func.movmemsi = gen_movmemsi_8reg;
9813 else if (TARGET_STRING
9814 && bytes > 16 /* move up to 24 bytes at a time */
9820 && ! fixed_regs[10])
9822 move_bytes = (bytes > 24) ? 24 : bytes;
9823 gen_func.movmemsi = gen_movmemsi_6reg;
9825 else if (TARGET_STRING
9826 && bytes > 8 /* move up to 16 bytes at a time */
9832 move_bytes = (bytes > 16) ? 16 : bytes;
9833 gen_func.movmemsi = gen_movmemsi_4reg;
9835 else if (bytes >= 8 && TARGET_POWERPC64
9836 /* 64-bit loads and stores require word-aligned
9838 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9842 gen_func.mov = gen_movdi;
9844 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9845 { /* move up to 8 bytes at a time */
9846 move_bytes = (bytes > 8) ? 8 : bytes;
9847 gen_func.movmemsi = gen_movmemsi_2reg;
9849 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9850 { /* move 4 bytes */
9853 gen_func.mov = gen_movsi;
9855 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9856 { /* move 2 bytes */
9859 gen_func.mov = gen_movhi;
9861 else if (TARGET_STRING && bytes > 1)
9862 { /* move up to 4 bytes at a time */
9863 move_bytes = (bytes > 4) ? 4 : bytes;
9864 gen_func.movmemsi = gen_movmemsi_1reg;
9866 else /* move 1 byte at a time */
9870 gen_func.mov = gen_movqi;
9873 src = adjust_address (orig_src, mode, offset);
9874 dest = adjust_address (orig_dest, mode, offset);
9876 if (mode != BLKmode)
9878 rtx tmp_reg = gen_reg_rtx (mode);
9880 emit_insn ((*gen_func.mov) (tmp_reg, src));
9881 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9884 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9887 for (i = 0; i < num_reg; i++)
9888 emit_insn (stores[i]);
9892 if (mode == BLKmode)
9894 /* Move the address into scratch registers. The movmemsi
9895 patterns require zero offset. */
9896 if (!REG_P (XEXP (src, 0)))
9898 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9899 src = replace_equiv_address (src, src_reg);
9901 set_mem_size (src, GEN_INT (move_bytes));
9903 if (!REG_P (XEXP (dest, 0)))
9905 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9906 dest = replace_equiv_address (dest, dest_reg);
9908 set_mem_size (dest, GEN_INT (move_bytes));
9910 emit_insn ((*gen_func.movmemsi) (dest, src,
9911 GEN_INT (move_bytes & 31),
9920 /* Return a string to perform a load_multiple operation.
9921 operands[0] is the vector.
9922 operands[1] is the source address.
9923 operands[2] is the first destination register. */
9926 rs6000_output_load_multiple (rtx operands[3])
9928 /* We have to handle the case where the pseudo used to contain the address
9929 is assigned to one of the output registers. */
9931 int words = XVECLEN (operands[0], 0);
9934 if (XVECLEN (operands[0], 0) == 1)
9935 return "{l|lwz} %2,0(%1)";
9937 for (i = 0; i < words; i++)
9938 if (refers_to_regno_p (REGNO (operands[2]) + i,
9939 REGNO (operands[2]) + i + 1, operands[1], 0))
9943 xop[0] = GEN_INT (4 * (words-1));
9944 xop[1] = operands[1];
9945 xop[2] = operands[2];
9946 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9951 xop[0] = GEN_INT (4 * (words-1));
9952 xop[1] = operands[1];
9953 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9954 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9959 for (j = 0; j < words; j++)
9962 xop[0] = GEN_INT (j * 4);
9963 xop[1] = operands[1];
9964 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9965 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9967 xop[0] = GEN_INT (i * 4);
9968 xop[1] = operands[1];
9969 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9974 return "{lsi|lswi} %2,%1,%N0";
9978 /* A validation routine: say whether CODE, a condition code, and MODE
9979 match. The other alternatives either don't make sense or should
9980 never be generated. */
9983 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9985 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9986 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9987 && GET_MODE_CLASS (mode) == MODE_CC);
9989 /* These don't make sense. */
9990 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9991 || mode != CCUNSmode);
9993 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9994 || mode == CCUNSmode);
9996 gcc_assert (mode == CCFPmode
9997 || (code != ORDERED && code != UNORDERED
9998 && code != UNEQ && code != LTGT
9999 && code != UNGT && code != UNLT
10000 && code != UNGE && code != UNLE));
10002 /* These should never be generated except for
10003 flag_finite_math_only. */
10004 gcc_assert (mode != CCFPmode
10005 || flag_finite_math_only
10006 || (code != LE && code != GE
10007 && code != UNEQ && code != LTGT
10008 && code != UNGT && code != UNLT));
10010 /* These are invalid; the information is not there. */
10011 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10015 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10016 mask required to convert the result of a rotate insn into a shift
10017 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10020 includes_lshift_p (rtx shiftop, rtx andop)
10022 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10024 shift_mask <<= INTVAL (shiftop);
10026 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10029 /* Similar, but for right shift. */
10032 includes_rshift_p (rtx shiftop, rtx andop)
10034 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10036 shift_mask >>= INTVAL (shiftop);
10038 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10041 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10042 to perform a left shift. It must have exactly SHIFTOP least
10043 significant 0's, then one or more 1's, then zero or more 0's. */
10046 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10048 if (GET_CODE (andop) == CONST_INT)
10050 HOST_WIDE_INT c, lsb, shift_mask;
10052 c = INTVAL (andop);
10053 if (c == 0 || c == ~0)
10057 shift_mask <<= INTVAL (shiftop);
10059 /* Find the least significant one bit. */
10062 /* It must coincide with the LSB of the shift mask. */
10063 if (-lsb != shift_mask)
10066 /* Invert to look for the next transition (if any). */
10069 /* Remove the low group of ones (originally low group of zeros). */
10072 /* Again find the lsb, and check we have all 1's above. */
10076 else if (GET_CODE (andop) == CONST_DOUBLE
10077 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10079 HOST_WIDE_INT low, high, lsb;
10080 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10082 low = CONST_DOUBLE_LOW (andop);
10083 if (HOST_BITS_PER_WIDE_INT < 64)
10084 high = CONST_DOUBLE_HIGH (andop);
10086 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10087 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10090 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10092 shift_mask_high = ~0;
10093 if (INTVAL (shiftop) > 32)
10094 shift_mask_high <<= INTVAL (shiftop) - 32;
10096 lsb = high & -high;
10098 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10104 lsb = high & -high;
10105 return high == -lsb;
10108 shift_mask_low = ~0;
10109 shift_mask_low <<= INTVAL (shiftop);
10113 if (-lsb != shift_mask_low)
10116 if (HOST_BITS_PER_WIDE_INT < 64)
10121 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10123 lsb = high & -high;
10124 return high == -lsb;
10128 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10134 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10135 to perform a left shift. It must have SHIFTOP or more least
10136 significant 0's, with the remainder of the word 1's. */
10139 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10141 if (GET_CODE (andop) == CONST_INT)
10143 HOST_WIDE_INT c, lsb, shift_mask;
10146 shift_mask <<= INTVAL (shiftop);
10147 c = INTVAL (andop);
10149 /* Find the least significant one bit. */
10152 /* It must be covered by the shift mask.
10153 This test also rejects c == 0. */
10154 if ((lsb & shift_mask) == 0)
10157 /* Check we have all 1's above the transition, and reject all 1's. */
10158 return c == -lsb && lsb != 1;
10160 else if (GET_CODE (andop) == CONST_DOUBLE
10161 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10163 HOST_WIDE_INT low, lsb, shift_mask_low;
10165 low = CONST_DOUBLE_LOW (andop);
10167 if (HOST_BITS_PER_WIDE_INT < 64)
10169 HOST_WIDE_INT high, shift_mask_high;
10171 high = CONST_DOUBLE_HIGH (andop);
10175 shift_mask_high = ~0;
10176 if (INTVAL (shiftop) > 32)
10177 shift_mask_high <<= INTVAL (shiftop) - 32;
10179 lsb = high & -high;
10181 if ((lsb & shift_mask_high) == 0)
10184 return high == -lsb;
10190 shift_mask_low = ~0;
10191 shift_mask_low <<= INTVAL (shiftop);
10195 if ((lsb & shift_mask_low) == 0)
10198 return low == -lsb && lsb != 1;
10204 /* Return 1 if operands will generate a valid arguments to rlwimi
10205 instruction for insert with right shift in 64-bit mode. The mask may
10206 not start on the first bit or stop on the last bit because wrap-around
10207 effects of instruction do not correspond to semantics of RTL insn. */
10210 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10212 if (INTVAL (startop) > 32
10213 && INTVAL (startop) < 64
10214 && INTVAL (sizeop) > 1
10215 && INTVAL (sizeop) + INTVAL (startop) < 64
10216 && INTVAL (shiftop) > 0
10217 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10218 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10224 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10225 for lfq and stfq insns iff the registers are hard registers. */
10228 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10230 /* We might have been passed a SUBREG. */
10231 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10234 /* We might have been passed non floating point registers. */
10235 if (!FP_REGNO_P (REGNO (reg1))
10236 || !FP_REGNO_P (REGNO (reg2)))
10239 return (REGNO (reg1) == REGNO (reg2) - 1);
10242 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10243 addr1 and addr2 must be in consecutive memory locations
10244 (addr2 == addr1 + 8). */
10247 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10250 unsigned int reg1, reg2;
10251 int offset1, offset2;
10253 /* The mems cannot be volatile. */
10254 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10257 addr1 = XEXP (mem1, 0);
10258 addr2 = XEXP (mem2, 0);
10260 /* Extract an offset (if used) from the first addr. */
10261 if (GET_CODE (addr1) == PLUS)
10263 /* If not a REG, return zero. */
10264 if (GET_CODE (XEXP (addr1, 0)) != REG)
10268 reg1 = REGNO (XEXP (addr1, 0));
10269 /* The offset must be constant! */
10270 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10272 offset1 = INTVAL (XEXP (addr1, 1));
10275 else if (GET_CODE (addr1) != REG)
10279 reg1 = REGNO (addr1);
10280 /* This was a simple (mem (reg)) expression. Offset is 0. */
10284 /* And now for the second addr. */
10285 if (GET_CODE (addr2) == PLUS)
10287 /* If not a REG, return zero. */
10288 if (GET_CODE (XEXP (addr2, 0)) != REG)
10292 reg2 = REGNO (XEXP (addr2, 0));
10293 /* The offset must be constant. */
10294 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10296 offset2 = INTVAL (XEXP (addr2, 1));
10299 else if (GET_CODE (addr2) != REG)
10303 reg2 = REGNO (addr2);
10304 /* This was a simple (mem (reg)) expression. Offset is 0. */
10308 /* Both of these must have the same base register. */
10312 /* The offset for the second addr must be 8 more than the first addr. */
10313 if (offset2 != offset1 + 8)
10316 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10321 /* Return the register class of a scratch register needed to copy IN into
10322 or out of a register in CLASS in MODE. If it can be done directly,
10323 NO_REGS is returned. */
10326 rs6000_secondary_reload_class (enum reg_class class,
10327 enum machine_mode mode ATTRIBUTE_UNUSED,
10332 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10334 && MACHOPIC_INDIRECT
10338 /* We cannot copy a symbolic operand directly into anything
10339 other than BASE_REGS for TARGET_ELF. So indicate that a
10340 register from BASE_REGS is needed as an intermediate
10343 On Darwin, pic addresses require a load from memory, which
10344 needs a base register. */
10345 if (class != BASE_REGS
10346 && (GET_CODE (in) == SYMBOL_REF
10347 || GET_CODE (in) == HIGH
10348 || GET_CODE (in) == LABEL_REF
10349 || GET_CODE (in) == CONST))
10353 if (GET_CODE (in) == REG)
10355 regno = REGNO (in);
10356 if (regno >= FIRST_PSEUDO_REGISTER)
10358 regno = true_regnum (in);
10359 if (regno >= FIRST_PSEUDO_REGISTER)
10363 else if (GET_CODE (in) == SUBREG)
10365 regno = true_regnum (in);
10366 if (regno >= FIRST_PSEUDO_REGISTER)
10372 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10374 if (class == GENERAL_REGS || class == BASE_REGS
10375 || (regno >= 0 && INT_REGNO_P (regno)))
10378 /* Constants, memory, and FP registers can go into FP registers. */
10379 if ((regno == -1 || FP_REGNO_P (regno))
10380 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10383 /* Memory, and AltiVec registers can go into AltiVec registers. */
10384 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10385 && class == ALTIVEC_REGS)
10388 /* We can copy among the CR registers. */
10389 if ((class == CR_REGS || class == CR0_REGS)
10390 && regno >= 0 && CR_REGNO_P (regno))
10393 /* Otherwise, we need GENERAL_REGS. */
10394 return GENERAL_REGS;
10397 /* Given a comparison operation, return the bit number in CCR to test. We
10398 know this is a valid comparison.
10400 SCC_P is 1 if this is for an scc. That means that %D will have been
10401 used instead of %C, so the bits will be in different places.
10403 Return -1 if OP isn't a valid comparison for some reason. */
10406 ccr_bit (rtx op, int scc_p)
10408 enum rtx_code code = GET_CODE (op);
10409 enum machine_mode cc_mode;
10414 if (!COMPARISON_P (op))
10417 reg = XEXP (op, 0);
10419 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10421 cc_mode = GET_MODE (reg);
10422 cc_regnum = REGNO (reg);
10423 base_bit = 4 * (cc_regnum - CR0_REGNO);
10425 validate_condition_mode (code, cc_mode);
10427 /* When generating a sCOND operation, only positive conditions are
10430 || code == EQ || code == GT || code == LT || code == UNORDERED
10431 || code == GTU || code == LTU);
10436 return scc_p ? base_bit + 3 : base_bit + 2;
10438 return base_bit + 2;
10439 case GT: case GTU: case UNLE:
10440 return base_bit + 1;
10441 case LT: case LTU: case UNGE:
10443 case ORDERED: case UNORDERED:
10444 return base_bit + 3;
10447 /* If scc, we will have done a cror to put the bit in the
10448 unordered position. So test that bit. For integer, this is ! LT
10449 unless this is an scc insn. */
10450 return scc_p ? base_bit + 3 : base_bit;
10453 return scc_p ? base_bit + 3 : base_bit + 1;
10456 gcc_unreachable ();
10460 /* Return the GOT register. */
10463 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10465 /* The second flow pass currently (June 1999) can't update
10466 regs_ever_live without disturbing other parts of the compiler, so
10467 update it here to make the prolog/epilogue code happy. */
10468 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10469 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10471 current_function_uses_pic_offset_table = 1;
10473 return pic_offset_table_rtx;
10476 /* Function to init struct machine_function.
10477 This will be called, via a pointer variable,
10478 from push_function_context. */
10480 static struct machine_function *
10481 rs6000_init_machine_status (void)
10483 return ggc_alloc_cleared (sizeof (machine_function));
10486 /* These macros test for integers and extract the low-order bits. */
10488 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10489 && GET_MODE (X) == VOIDmode)
10491 #define INT_LOWPART(X) \
10492 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10495 extract_MB (rtx op)
10498 unsigned long val = INT_LOWPART (op);
10500 /* If the high bit is zero, the value is the first 1 bit we find
10502 if ((val & 0x80000000) == 0)
10504 gcc_assert (val & 0xffffffff);
10507 while (((val <<= 1) & 0x80000000) == 0)
10512 /* If the high bit is set and the low bit is not, or the mask is all
10513 1's, the value is zero. */
10514 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10517 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10520 while (((val >>= 1) & 1) != 0)
10527 extract_ME (rtx op)
10530 unsigned long val = INT_LOWPART (op);
10532 /* If the low bit is zero, the value is the first 1 bit we find from
10534 if ((val & 1) == 0)
10536 gcc_assert (val & 0xffffffff);
10539 while (((val >>= 1) & 1) == 0)
10545 /* If the low bit is set and the high bit is not, or the mask is all
10546 1's, the value is 31. */
10547 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10550 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10553 while (((val <<= 1) & 0x80000000) != 0)
10559 /* Locate some local-dynamic symbol still in use by this function
10560 so that we can print its name in some tls_ld pattern. */
10562 static const char *
10563 rs6000_get_some_local_dynamic_name (void)
10567 if (cfun->machine->some_ld_name)
10568 return cfun->machine->some_ld_name;
10570 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10572 && for_each_rtx (&PATTERN (insn),
10573 rs6000_get_some_local_dynamic_name_1, 0))
10574 return cfun->machine->some_ld_name;
10576 gcc_unreachable ();
10579 /* Helper function for rs6000_get_some_local_dynamic_name. */
10582 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10586 if (GET_CODE (x) == SYMBOL_REF)
10588 const char *str = XSTR (x, 0);
10589 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10591 cfun->machine->some_ld_name = str;
10599 /* Write out a function code label. */
10602 rs6000_output_function_entry (FILE *file, const char *fname)
10604 if (fname[0] != '.')
10606 switch (DEFAULT_ABI)
10609 gcc_unreachable ();
10615 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10624 RS6000_OUTPUT_BASENAME (file, fname);
10626 assemble_name (file, fname);
10629 /* Print an operand. Recognize special options, documented below. */
10632 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10633 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10635 #define SMALL_DATA_RELOC "sda21"
10636 #define SMALL_DATA_REG 0
10640 print_operand (FILE *file, rtx x, int code)
10644 unsigned HOST_WIDE_INT uval;
10649 /* Write out an instruction after the call which may be replaced
10650 with glue code by the loader. This depends on the AIX version. */
10651 asm_fprintf (file, RS6000_CALL_GLUE);
10654 /* %a is output_address. */
10657 /* If X is a constant integer whose low-order 5 bits are zero,
10658 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10659 in the AIX assembler where "sri" with a zero shift count
10660 writes a trash instruction. */
10661 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10668 /* If constant, low-order 16 bits of constant, unsigned.
10669 Otherwise, write normally. */
10671 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10673 print_operand (file, x, 0);
10677 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10678 for 64-bit mask direction. */
10679 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10682 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10686 /* X is a CR register. Print the number of the GT bit of the CR. */
10687 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10688 output_operand_lossage ("invalid %%E value");
10690 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10694 /* Like 'J' but get to the GT bit only. */
10695 gcc_assert (GET_CODE (x) == REG);
10697 /* Bit 1 is GT bit. */
10698 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10700 /* Add one for shift count in rlinm for scc. */
10701 fprintf (file, "%d", i + 1);
10705 /* X is a CR register. Print the number of the EQ bit of the CR */
10706 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10707 output_operand_lossage ("invalid %%E value");
10709 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10713 /* X is a CR register. Print the shift count needed to move it
10714 to the high-order four bits. */
10715 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10716 output_operand_lossage ("invalid %%f value");
10718 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10722 /* Similar, but print the count for the rotate in the opposite
10724 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10725 output_operand_lossage ("invalid %%F value");
10727 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10731 /* X is a constant integer. If it is negative, print "m",
10732 otherwise print "z". This is to make an aze or ame insn. */
10733 if (GET_CODE (x) != CONST_INT)
10734 output_operand_lossage ("invalid %%G value");
10735 else if (INTVAL (x) >= 0)
10742 /* If constant, output low-order five bits. Otherwise, write
10745 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10747 print_operand (file, x, 0);
10751 /* If constant, output low-order six bits. Otherwise, write
10754 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10756 print_operand (file, x, 0);
10760 /* Print `i' if this is a constant, else nothing. */
10766 /* Write the bit number in CCR for jump. */
10767 i = ccr_bit (x, 0);
10769 output_operand_lossage ("invalid %%j code");
10771 fprintf (file, "%d", i);
10775 /* Similar, but add one for shift count in rlinm for scc and pass
10776 scc flag to `ccr_bit'. */
10777 i = ccr_bit (x, 1);
10779 output_operand_lossage ("invalid %%J code");
10781 /* If we want bit 31, write a shift count of zero, not 32. */
10782 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10786 /* X must be a constant. Write the 1's complement of the
10789 output_operand_lossage ("invalid %%k value");
10791 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10795 /* X must be a symbolic constant on ELF. Write an
10796 expression suitable for an 'addi' that adds in the low 16
10797 bits of the MEM. */
10798 if (GET_CODE (x) != CONST)
10800 print_operand_address (file, x);
10801 fputs ("@l", file);
10805 if (GET_CODE (XEXP (x, 0)) != PLUS
10806 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10807 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10808 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10809 output_operand_lossage ("invalid %%K value");
10810 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10811 fputs ("@l", file);
10812 /* For GNU as, there must be a non-alphanumeric character
10813 between 'l' and the number. The '-' is added by
10814 print_operand() already. */
10815 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10817 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10821 /* %l is output_asm_label. */
10824 /* Write second word of DImode or DFmode reference. Works on register
10825 or non-indexed memory only. */
10826 if (GET_CODE (x) == REG)
10827 fputs (reg_names[REGNO (x) + 1], file);
10828 else if (GET_CODE (x) == MEM)
10830 /* Handle possible auto-increment. Since it is pre-increment and
10831 we have already done it, we can just use an offset of word. */
10832 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10833 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10834 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10837 output_address (XEXP (adjust_address_nv (x, SImode,
10841 if (small_data_operand (x, GET_MODE (x)))
10842 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10843 reg_names[SMALL_DATA_REG]);
10848 /* MB value for a mask operand. */
10849 if (! mask_operand (x, SImode))
10850 output_operand_lossage ("invalid %%m value");
10852 fprintf (file, "%d", extract_MB (x));
10856 /* ME value for a mask operand. */
10857 if (! mask_operand (x, SImode))
10858 output_operand_lossage ("invalid %%M value");
10860 fprintf (file, "%d", extract_ME (x));
10863 /* %n outputs the negative of its operand. */
10866 /* Write the number of elements in the vector times 4. */
10867 if (GET_CODE (x) != PARALLEL)
10868 output_operand_lossage ("invalid %%N value");
10870 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10874 /* Similar, but subtract 1 first. */
10875 if (GET_CODE (x) != PARALLEL)
10876 output_operand_lossage ("invalid %%O value");
10878 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10882 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10884 || INT_LOWPART (x) < 0
10885 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10886 output_operand_lossage ("invalid %%p value");
10888 fprintf (file, "%d", i);
10892 /* The operand must be an indirect memory reference. The result
10893 is the register name. */
10894 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10895 || REGNO (XEXP (x, 0)) >= 32)
10896 output_operand_lossage ("invalid %%P value");
10898 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10902 /* This outputs the logical code corresponding to a boolean
10903 expression. The expression may have one or both operands
10904 negated (if one, only the first one). For condition register
10905 logical operations, it will also treat the negated
10906 CR codes as NOTs, but not handle NOTs of them. */
10908 const char *const *t = 0;
10910 enum rtx_code code = GET_CODE (x);
10911 static const char * const tbl[3][3] = {
10912 { "and", "andc", "nor" },
10913 { "or", "orc", "nand" },
10914 { "xor", "eqv", "xor" } };
10918 else if (code == IOR)
10920 else if (code == XOR)
10923 output_operand_lossage ("invalid %%q value");
10925 if (GET_CODE (XEXP (x, 0)) != NOT)
10929 if (GET_CODE (XEXP (x, 1)) == NOT)
10947 /* X is a CR register. Print the mask for `mtcrf'. */
10948 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10949 output_operand_lossage ("invalid %%R value");
10951 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10955 /* Low 5 bits of 32 - value */
10957 output_operand_lossage ("invalid %%s value");
10959 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10963 /* PowerPC64 mask position. All 0's is excluded.
10964 CONST_INT 32-bit mask is considered sign-extended so any
10965 transition must occur within the CONST_INT, not on the boundary. */
10966 if (! mask64_operand (x, DImode))
10967 output_operand_lossage ("invalid %%S value");
10969 uval = INT_LOWPART (x);
10971 if (uval & 1) /* Clear Left */
10973 #if HOST_BITS_PER_WIDE_INT > 64
10974 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10978 else /* Clear Right */
10981 #if HOST_BITS_PER_WIDE_INT > 64
10982 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10988 gcc_assert (i >= 0);
10989 fprintf (file, "%d", i);
10993 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10994 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10996 /* Bit 3 is OV bit. */
10997 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10999 /* If we want bit 31, write a shift count of zero, not 32. */
11000 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11004 /* Print the symbolic name of a branch target register. */
11005 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
11006 && REGNO (x) != COUNT_REGISTER_REGNUM))
11007 output_operand_lossage ("invalid %%T value");
11008 else if (REGNO (x) == LINK_REGISTER_REGNUM)
11009 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11011 fputs ("ctr", file);
11015 /* High-order 16 bits of constant for use in unsigned operand. */
11017 output_operand_lossage ("invalid %%u value");
11019 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11020 (INT_LOWPART (x) >> 16) & 0xffff);
11024 /* High-order 16 bits of constant for use in signed operand. */
11026 output_operand_lossage ("invalid %%v value");
11028 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11029 (INT_LOWPART (x) >> 16) & 0xffff);
11033 /* Print `u' if this has an auto-increment or auto-decrement. */
11034 if (GET_CODE (x) == MEM
11035 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11036 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
11041 /* Print the trap code for this operand. */
11042 switch (GET_CODE (x))
11045 fputs ("eq", file); /* 4 */
11048 fputs ("ne", file); /* 24 */
11051 fputs ("lt", file); /* 16 */
11054 fputs ("le", file); /* 20 */
11057 fputs ("gt", file); /* 8 */
11060 fputs ("ge", file); /* 12 */
11063 fputs ("llt", file); /* 2 */
11066 fputs ("lle", file); /* 6 */
11069 fputs ("lgt", file); /* 1 */
11072 fputs ("lge", file); /* 5 */
11075 gcc_unreachable ();
11080 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11083 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11084 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11086 print_operand (file, x, 0);
11090 /* MB value for a PowerPC64 rldic operand. */
11091 val = (GET_CODE (x) == CONST_INT
11092 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11097 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11098 if ((val <<= 1) < 0)
11101 #if HOST_BITS_PER_WIDE_INT == 32
11102 if (GET_CODE (x) == CONST_INT && i >= 0)
11103 i += 32; /* zero-extend high-part was all 0's */
11104 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11106 val = CONST_DOUBLE_LOW (x);
11112 for ( ; i < 64; i++)
11113 if ((val <<= 1) < 0)
11118 fprintf (file, "%d", i + 1);
11122 if (GET_CODE (x) == MEM
11123 && legitimate_indexed_address_p (XEXP (x, 0), 0))
11128 /* Like 'L', for third word of TImode */
11129 if (GET_CODE (x) == REG)
11130 fputs (reg_names[REGNO (x) + 2], file);
11131 else if (GET_CODE (x) == MEM)
11133 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11134 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11135 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11137 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11138 if (small_data_operand (x, GET_MODE (x)))
11139 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11140 reg_names[SMALL_DATA_REG]);
11145 /* X is a SYMBOL_REF. Write out the name preceded by a
11146 period and without any trailing data in brackets. Used for function
11147 names. If we are configured for System V (or the embedded ABI) on
11148 the PowerPC, do not emit the period, since those systems do not use
11149 TOCs and the like. */
11150 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11152 /* Mark the decl as referenced so that cgraph will output the
11154 if (SYMBOL_REF_DECL (x))
11155 mark_decl_referenced (SYMBOL_REF_DECL (x));
11157 /* For macho, check to see if we need a stub. */
11160 const char *name = XSTR (x, 0);
11162 if (MACHOPIC_INDIRECT
11163 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11164 name = machopic_indirection_name (x, /*stub_p=*/true);
11166 assemble_name (file, name);
11168 else if (!DOT_SYMBOLS)
11169 assemble_name (file, XSTR (x, 0));
11171 rs6000_output_function_entry (file, XSTR (x, 0));
11175 /* Like 'L', for last word of TImode. */
11176 if (GET_CODE (x) == REG)
11177 fputs (reg_names[REGNO (x) + 3], file);
11178 else if (GET_CODE (x) == MEM)
11180 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11181 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11182 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11184 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11185 if (small_data_operand (x, GET_MODE (x)))
11186 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11187 reg_names[SMALL_DATA_REG]);
11191 /* Print AltiVec or SPE memory operand. */
11196 gcc_assert (GET_CODE (x) == MEM);
11200 /* Ugly hack because %y is overloaded. */
11201 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11202 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11203 || GET_MODE (x) == TFmode
11204 || GET_MODE (x) == TImode))
11206 /* Handle [reg]. */
11207 if (GET_CODE (tmp) == REG)
11209 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11212 /* Handle [reg+UIMM]. */
11213 else if (GET_CODE (tmp) == PLUS &&
11214 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11218 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11220 x = INTVAL (XEXP (tmp, 1));
11221 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11225 /* Fall through. Must be [reg+reg]. */
11228 && GET_CODE (tmp) == AND
11229 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11230 && INTVAL (XEXP (tmp, 1)) == -16)
11231 tmp = XEXP (tmp, 0);
11232 if (GET_CODE (tmp) == REG)
11233 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11236 gcc_assert (GET_CODE (tmp) == PLUS
11237 && REG_P (XEXP (tmp, 0))
11238 && REG_P (XEXP (tmp, 1)));
11240 if (REGNO (XEXP (tmp, 0)) == 0)
11241 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11242 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11244 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11245 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11251 if (GET_CODE (x) == REG)
11252 fprintf (file, "%s", reg_names[REGNO (x)]);
11253 else if (GET_CODE (x) == MEM)
11255 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11256 know the width from the mode. */
11257 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11258 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11259 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11260 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11261 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11262 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11264 output_address (XEXP (x, 0));
11267 output_addr_const (file, x);
11271 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11275 output_operand_lossage ("invalid %%xn code");
11279 /* Print the address of an operand. */
11282 print_operand_address (FILE *file, rtx x)
11284 if (GET_CODE (x) == REG)
11285 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11286 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11287 || GET_CODE (x) == LABEL_REF)
11289 output_addr_const (file, x);
11290 if (small_data_operand (x, GET_MODE (x)))
11291 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11292 reg_names[SMALL_DATA_REG]);
11294 gcc_assert (!TARGET_TOC);
11296 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11298 gcc_assert (REG_P (XEXP (x, 0)));
11299 if (REGNO (XEXP (x, 0)) == 0)
11300 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11301 reg_names[ REGNO (XEXP (x, 0)) ]);
11303 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11304 reg_names[ REGNO (XEXP (x, 1)) ]);
11306 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11307 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11308 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11310 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11311 && CONSTANT_P (XEXP (x, 1)))
11313 output_addr_const (file, XEXP (x, 1));
11314 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11318 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11319 && CONSTANT_P (XEXP (x, 1)))
11321 fprintf (file, "lo16(");
11322 output_addr_const (file, XEXP (x, 1));
11323 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11326 else if (legitimate_constant_pool_address_p (x))
11328 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11330 rtx contains_minus = XEXP (x, 1);
11334 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11335 turn it into (sym) for output_addr_const. */
11336 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11337 contains_minus = XEXP (contains_minus, 0);
11339 minus = XEXP (contains_minus, 0);
11340 symref = XEXP (minus, 0);
11341 XEXP (contains_minus, 0) = symref;
11346 name = XSTR (symref, 0);
11347 newname = alloca (strlen (name) + sizeof ("@toc"));
11348 strcpy (newname, name);
11349 strcat (newname, "@toc");
11350 XSTR (symref, 0) = newname;
11352 output_addr_const (file, XEXP (x, 1));
11354 XSTR (symref, 0) = name;
11355 XEXP (contains_minus, 0) = minus;
11358 output_addr_const (file, XEXP (x, 1));
11360 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11363 gcc_unreachable ();
11366 /* Target hook for assembling integer objects. The PowerPC version has
11367 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11368 is defined. It also needs to handle DI-mode objects on 64-bit
11372 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11374 #ifdef RELOCATABLE_NEEDS_FIXUP
11375 /* Special handling for SI values. */
11376 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11378 static int recurse = 0;
11380 /* For -mrelocatable, we mark all addresses that need to be fixed up
11381 in the .fixup section. */
11382 if (TARGET_RELOCATABLE
11383 && in_section != toc_section
11384 && in_section != text_section
11385 && !unlikely_text_section_p (in_section)
11387 && GET_CODE (x) != CONST_INT
11388 && GET_CODE (x) != CONST_DOUBLE
11394 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11396 ASM_OUTPUT_LABEL (asm_out_file, buf);
11397 fprintf (asm_out_file, "\t.long\t(");
11398 output_addr_const (asm_out_file, x);
11399 fprintf (asm_out_file, ")@fixup\n");
11400 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11401 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11402 fprintf (asm_out_file, "\t.long\t");
11403 assemble_name (asm_out_file, buf);
11404 fprintf (asm_out_file, "\n\t.previous\n");
11408 /* Remove initial .'s to turn a -mcall-aixdesc function
11409 address into the address of the descriptor, not the function
11411 else if (GET_CODE (x) == SYMBOL_REF
11412 && XSTR (x, 0)[0] == '.'
11413 && DEFAULT_ABI == ABI_AIX)
11415 const char *name = XSTR (x, 0);
11416 while (*name == '.')
11419 fprintf (asm_out_file, "\t.long\t%s\n", name);
11423 #endif /* RELOCATABLE_NEEDS_FIXUP */
11424 return default_assemble_integer (x, size, aligned_p);
11427 #ifdef HAVE_GAS_HIDDEN
11428 /* Emit an assembler directive to set symbol visibility for DECL to
11429 VISIBILITY_TYPE. */
11432 rs6000_assemble_visibility (tree decl, int vis)
11434 /* Functions need to have their entry point symbol visibility set as
11435 well as their descriptor symbol visibility. */
11436 if (DEFAULT_ABI == ABI_AIX
11438 && TREE_CODE (decl) == FUNCTION_DECL)
11440 static const char * const visibility_types[] = {
11441 NULL, "internal", "hidden", "protected"
11444 const char *name, *type;
11446 name = ((* targetm.strip_name_encoding)
11447 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11448 type = visibility_types[vis];
11450 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11451 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11454 default_assemble_visibility (decl, vis);
11459 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11461 /* Reversal of FP compares takes care -- an ordered compare
11462 becomes an unordered compare and vice versa. */
11463 if (mode == CCFPmode
11464 && (!flag_finite_math_only
11465 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11466 || code == UNEQ || code == LTGT))
11467 return reverse_condition_maybe_unordered (code);
11469 return reverse_condition (code);
11472 /* Generate a compare for CODE. Return a brand-new rtx that
11473 represents the result of the compare. */
11476 rs6000_generate_compare (enum rtx_code code)
11478 enum machine_mode comp_mode;
11479 rtx compare_result;
11481 if (rs6000_compare_fp_p)
11482 comp_mode = CCFPmode;
11483 else if (code == GTU || code == LTU
11484 || code == GEU || code == LEU)
11485 comp_mode = CCUNSmode;
11486 else if ((code == EQ || code == NE)
11487 && GET_CODE (rs6000_compare_op0) == SUBREG
11488 && GET_CODE (rs6000_compare_op1) == SUBREG
11489 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11490 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11491 /* These are unsigned values, perhaps there will be a later
11492 ordering compare that can be shared with this one.
11493 Unfortunately we cannot detect the signedness of the operands
11494 for non-subregs. */
11495 comp_mode = CCUNSmode;
11497 comp_mode = CCmode;
11499 /* First, the compare. */
11500 compare_result = gen_reg_rtx (comp_mode);
11502 /* E500 FP compare instructions on the GPRs. Yuck! */
11503 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11504 && rs6000_compare_fp_p)
11506 rtx cmp, or_result, compare_result2;
11507 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11509 if (op_mode == VOIDmode)
11510 op_mode = GET_MODE (rs6000_compare_op1);
11512 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11513 This explains the following mess. */
11517 case EQ: case UNEQ: case NE: case LTGT:
11521 cmp = flag_unsafe_math_optimizations
11522 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11523 rs6000_compare_op1)
11524 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11525 rs6000_compare_op1);
11529 cmp = flag_unsafe_math_optimizations
11530 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11531 rs6000_compare_op1)
11532 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11533 rs6000_compare_op1);
11537 cmp = flag_unsafe_math_optimizations
11538 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11539 rs6000_compare_op1)
11540 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11541 rs6000_compare_op1);
11545 gcc_unreachable ();
11549 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11553 cmp = flag_unsafe_math_optimizations
11554 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11555 rs6000_compare_op1)
11556 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11557 rs6000_compare_op1);
11561 cmp = flag_unsafe_math_optimizations
11562 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11563 rs6000_compare_op1)
11564 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11565 rs6000_compare_op1);
11569 cmp = flag_unsafe_math_optimizations
11570 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11571 rs6000_compare_op1)
11572 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11573 rs6000_compare_op1);
11577 gcc_unreachable ();
11581 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11585 cmp = flag_unsafe_math_optimizations
11586 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11587 rs6000_compare_op1)
11588 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11589 rs6000_compare_op1);
11593 cmp = flag_unsafe_math_optimizations
11594 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11595 rs6000_compare_op1)
11596 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11597 rs6000_compare_op1);
11601 cmp = flag_unsafe_math_optimizations
11602 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11603 rs6000_compare_op1)
11604 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11605 rs6000_compare_op1);
11609 gcc_unreachable ();
11613 gcc_unreachable ();
11616 /* Synthesize LE and GE from LT/GT || EQ. */
11617 if (code == LE || code == GE || code == LEU || code == GEU)
11623 case LE: code = LT; break;
11624 case GE: code = GT; break;
11625 case LEU: code = LT; break;
11626 case GEU: code = GT; break;
11627 default: gcc_unreachable ();
11630 compare_result2 = gen_reg_rtx (CCFPmode);
11636 cmp = flag_unsafe_math_optimizations
11637 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11638 rs6000_compare_op1)
11639 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11640 rs6000_compare_op1);
11644 cmp = flag_unsafe_math_optimizations
11645 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11646 rs6000_compare_op1)
11647 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11648 rs6000_compare_op1);
11652 cmp = flag_unsafe_math_optimizations
11653 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11654 rs6000_compare_op1)
11655 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11656 rs6000_compare_op1);
11660 gcc_unreachable ();
11664 /* OR them together. */
11665 or_result = gen_reg_rtx (CCFPmode);
11666 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11668 compare_result = or_result;
11673 if (code == NE || code == LTGT)
11683 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11684 CLOBBERs to match cmptf_internal2 pattern. */
11685 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11686 && GET_MODE (rs6000_compare_op0) == TFmode
11687 && !TARGET_IEEEQUAD
11688 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11689 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11691 gen_rtx_SET (VOIDmode,
11693 gen_rtx_COMPARE (comp_mode,
11694 rs6000_compare_op0,
11695 rs6000_compare_op1)),
11696 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11697 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11698 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11699 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11700 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11701 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11702 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11703 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11704 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11705 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11707 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11708 comp_mode = CCEQmode;
11709 compare_result = gen_reg_rtx (CCEQmode);
11711 emit_insn (gen_stack_protect_testdi (compare_result,
11712 rs6000_compare_op0, op1));
11714 emit_insn (gen_stack_protect_testsi (compare_result,
11715 rs6000_compare_op0, op1));
11718 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11719 gen_rtx_COMPARE (comp_mode,
11720 rs6000_compare_op0,
11721 rs6000_compare_op1)));
11724 /* Some kinds of FP comparisons need an OR operation;
11725 under flag_finite_math_only we don't bother. */
11726 if (rs6000_compare_fp_p
11727 && !flag_finite_math_only
11728 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11729 && (code == LE || code == GE
11730 || code == UNEQ || code == LTGT
11731 || code == UNGT || code == UNLT))
11733 enum rtx_code or1, or2;
11734 rtx or1_rtx, or2_rtx, compare2_rtx;
11735 rtx or_result = gen_reg_rtx (CCEQmode);
11739 case LE: or1 = LT; or2 = EQ; break;
11740 case GE: or1 = GT; or2 = EQ; break;
11741 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11742 case LTGT: or1 = LT; or2 = GT; break;
11743 case UNGT: or1 = UNORDERED; or2 = GT; break;
11744 case UNLT: or1 = UNORDERED; or2 = LT; break;
11745 default: gcc_unreachable ();
11747 validate_condition_mode (or1, comp_mode);
11748 validate_condition_mode (or2, comp_mode);
11749 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11750 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11751 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11752 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11754 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11756 compare_result = or_result;
11760 validate_condition_mode (code, GET_MODE (compare_result));
11762 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11766 /* Emit the RTL for an sCOND pattern. */
11769 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11772 enum machine_mode op_mode;
11773 enum rtx_code cond_code;
11775 condition_rtx = rs6000_generate_compare (code);
11776 cond_code = GET_CODE (condition_rtx);
11778 if (rs6000_compare_fp_p
11779 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11783 PUT_MODE (condition_rtx, SImode);
11784 t = XEXP (condition_rtx, 0);
11786 gcc_assert (cond_code == NE || cond_code == EQ);
11788 if (cond_code == NE)
11789 emit_insn (gen_e500_flip_gt_bit (t, t));
11791 emit_insn (gen_move_from_CR_gt_bit (result, t));
11795 if (cond_code == NE
11796 || cond_code == GE || cond_code == LE
11797 || cond_code == GEU || cond_code == LEU
11798 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11800 rtx not_result = gen_reg_rtx (CCEQmode);
11801 rtx not_op, rev_cond_rtx;
11802 enum machine_mode cc_mode;
11804 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11806 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11807 SImode, XEXP (condition_rtx, 0), const0_rtx);
11808 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11809 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11810 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11813 op_mode = GET_MODE (rs6000_compare_op0);
11814 if (op_mode == VOIDmode)
11815 op_mode = GET_MODE (rs6000_compare_op1);
11817 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11819 PUT_MODE (condition_rtx, DImode);
11820 convert_move (result, condition_rtx, 0);
11824 PUT_MODE (condition_rtx, SImode);
11825 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11829 /* Emit a branch of kind CODE to location LOC. */
11832 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11834 rtx condition_rtx, loc_ref;
11836 condition_rtx = rs6000_generate_compare (code);
11837 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11838 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11839 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11840 loc_ref, pc_rtx)));
11843 /* Return the string to output a conditional branch to LABEL, which is
11844 the operand number of the label, or -1 if the branch is really a
11845 conditional return.
11847 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11848 condition code register and its mode specifies what kind of
11849 comparison we made.
11851 REVERSED is nonzero if we should reverse the sense of the comparison.
11853 INSN is the insn. */
11856 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11858 static char string[64];
11859 enum rtx_code code = GET_CODE (op);
11860 rtx cc_reg = XEXP (op, 0);
11861 enum machine_mode mode = GET_MODE (cc_reg);
11862 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11863 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11864 int really_reversed = reversed ^ need_longbranch;
11870 validate_condition_mode (code, mode);
11872 /* Work out which way this really branches. We could use
11873 reverse_condition_maybe_unordered here always but this
11874 makes the resulting assembler clearer. */
11875 if (really_reversed)
11877 /* Reversal of FP compares takes care -- an ordered compare
11878 becomes an unordered compare and vice versa. */
11879 if (mode == CCFPmode)
11880 code = reverse_condition_maybe_unordered (code);
11882 code = reverse_condition (code);
11885 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11887 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11892 /* Opposite of GT. */
11901 gcc_unreachable ();
11907 /* Not all of these are actually distinct opcodes, but
11908 we distinguish them for clarity of the resulting assembler. */
11909 case NE: case LTGT:
11910 ccode = "ne"; break;
11911 case EQ: case UNEQ:
11912 ccode = "eq"; break;
11914 ccode = "ge"; break;
11915 case GT: case GTU: case UNGT:
11916 ccode = "gt"; break;
11918 ccode = "le"; break;
11919 case LT: case LTU: case UNLT:
11920 ccode = "lt"; break;
11921 case UNORDERED: ccode = "un"; break;
11922 case ORDERED: ccode = "nu"; break;
11923 case UNGE: ccode = "nl"; break;
11924 case UNLE: ccode = "ng"; break;
11926 gcc_unreachable ();
11929 /* Maybe we have a guess as to how likely the branch is.
11930 The old mnemonics don't have a way to specify this information. */
11932 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11933 if (note != NULL_RTX)
11935 /* PROB is the difference from 50%. */
11936 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11938 /* Only hint for highly probable/improbable branches on newer
11939 cpus as static prediction overrides processor dynamic
11940 prediction. For older cpus we may as well always hint, but
11941 assume not taken for branches that are very close to 50% as a
11942 mispredicted taken branch is more expensive than a
11943 mispredicted not-taken branch. */
11944 if (rs6000_always_hint
11945 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
11946 && br_prob_note_reliable_p (note)))
11948 if (abs (prob) > REG_BR_PROB_BASE / 20
11949 && ((prob > 0) ^ need_longbranch))
11957 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11959 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11961 /* We need to escape any '%' characters in the reg_names string.
11962 Assume they'd only be the first character.... */
11963 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11965 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11969 /* If the branch distance was too far, we may have to use an
11970 unconditional branch to go the distance. */
11971 if (need_longbranch)
11972 s += sprintf (s, ",$+8\n\tb %s", label);
11974 s += sprintf (s, ",%s", label);
11980 /* Return the string to flip the GT bit on a CR. */
11982 output_e500_flip_gt_bit (rtx dst, rtx src)
11984 static char string[64];
11987 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11988 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11991 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11992 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11994 sprintf (string, "crnot %d,%d", a, b);
11998 /* Return insn index for the vector compare instruction for given CODE,
11999 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12003 get_vec_cmp_insn (enum rtx_code code,
12004 enum machine_mode dest_mode,
12005 enum machine_mode op_mode)
12007 if (!TARGET_ALTIVEC)
12008 return INSN_NOT_AVAILABLE;
12013 if (dest_mode == V16QImode && op_mode == V16QImode)
12014 return UNSPEC_VCMPEQUB;
12015 if (dest_mode == V8HImode && op_mode == V8HImode)
12016 return UNSPEC_VCMPEQUH;
12017 if (dest_mode == V4SImode && op_mode == V4SImode)
12018 return UNSPEC_VCMPEQUW;
12019 if (dest_mode == V4SImode && op_mode == V4SFmode)
12020 return UNSPEC_VCMPEQFP;
12023 if (dest_mode == V4SImode && op_mode == V4SFmode)
12024 return UNSPEC_VCMPGEFP;
12026 if (dest_mode == V16QImode && op_mode == V16QImode)
12027 return UNSPEC_VCMPGTSB;
12028 if (dest_mode == V8HImode && op_mode == V8HImode)
12029 return UNSPEC_VCMPGTSH;
12030 if (dest_mode == V4SImode && op_mode == V4SImode)
12031 return UNSPEC_VCMPGTSW;
12032 if (dest_mode == V4SImode && op_mode == V4SFmode)
12033 return UNSPEC_VCMPGTFP;
12036 if (dest_mode == V16QImode && op_mode == V16QImode)
12037 return UNSPEC_VCMPGTUB;
12038 if (dest_mode == V8HImode && op_mode == V8HImode)
12039 return UNSPEC_VCMPGTUH;
12040 if (dest_mode == V4SImode && op_mode == V4SImode)
12041 return UNSPEC_VCMPGTUW;
12046 return INSN_NOT_AVAILABLE;
12049 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12050 DMODE is expected destination mode. This is a recursive function. */
12053 rs6000_emit_vector_compare (enum rtx_code rcode,
12055 enum machine_mode dmode)
12059 enum machine_mode dest_mode;
12060 enum machine_mode op_mode = GET_MODE (op1);
12062 gcc_assert (TARGET_ALTIVEC);
12063 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12065 /* Floating point vector compare instructions uses destination V4SImode.
12066 Move destination to appropriate mode later. */
12067 if (dmode == V4SFmode)
12068 dest_mode = V4SImode;
12072 mask = gen_reg_rtx (dest_mode);
12073 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12075 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12077 bool swap_operands = false;
12078 bool try_again = false;
12083 swap_operands = true;
12088 swap_operands = true;
12096 /* Invert condition and try again.
12097 e.g., A != B becomes ~(A==B). */
12099 enum rtx_code rev_code;
12100 enum insn_code nor_code;
12103 rev_code = reverse_condition_maybe_unordered (rcode);
12104 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12107 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
12108 gcc_assert (nor_code != CODE_FOR_nothing);
12109 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12111 if (dmode != dest_mode)
12113 rtx temp = gen_reg_rtx (dest_mode);
12114 convert_move (temp, mask, 0);
12124 /* Try GT/GTU/LT/LTU OR EQ */
12127 enum insn_code ior_code;
12128 enum rtx_code new_code;
12149 gcc_unreachable ();
12152 c_rtx = rs6000_emit_vector_compare (new_code,
12153 op0, op1, dest_mode);
12154 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12157 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
12158 gcc_assert (ior_code != CODE_FOR_nothing);
12159 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12160 if (dmode != dest_mode)
12162 rtx temp = gen_reg_rtx (dest_mode);
12163 convert_move (temp, mask, 0);
12170 gcc_unreachable ();
12175 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12176 /* You only get two chances. */
12177 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12189 emit_insn (gen_rtx_SET (VOIDmode, mask,
12190 gen_rtx_UNSPEC (dest_mode,
12191 gen_rtvec (2, op0, op1),
12193 if (dmode != dest_mode)
12195 rtx temp = gen_reg_rtx (dest_mode);
12196 convert_move (temp, mask, 0);
12202 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12203 valid insn doesn exist for given mode. */
12206 get_vsel_insn (enum machine_mode mode)
12211 return UNSPEC_VSEL4SI;
12214 return UNSPEC_VSEL4SF;
12217 return UNSPEC_VSEL8HI;
12220 return UNSPEC_VSEL16QI;
12223 return INSN_NOT_AVAILABLE;
12226 return INSN_NOT_AVAILABLE;
12229 /* Emit vector select insn where DEST is destination using
12230 operands OP1, OP2 and MASK. */
12233 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12236 enum machine_mode dest_mode = GET_MODE (dest);
12237 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12239 temp = gen_reg_rtx (dest_mode);
12241 /* For each vector element, select op1 when mask is 1 otherwise
12243 t = gen_rtx_SET (VOIDmode, temp,
12244 gen_rtx_UNSPEC (dest_mode,
12245 gen_rtvec (3, op2, op1, mask),
12248 emit_move_insn (dest, temp);
12252 /* Emit vector conditional expression.
12253 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12254 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12257 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12258 rtx cond, rtx cc_op0, rtx cc_op1)
12260 enum machine_mode dest_mode = GET_MODE (dest);
12261 enum rtx_code rcode = GET_CODE (cond);
12264 if (!TARGET_ALTIVEC)
12267 /* Get the vector mask for the given relational operations. */
12268 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12270 rs6000_emit_vector_select (dest, op1, op2, mask);
12275 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12276 operands of the last comparison is nonzero/true, FALSE_COND if it
12277 is zero/false. Return 0 if the hardware has no such operation. */
12280 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12282 enum rtx_code code = GET_CODE (op);
12283 rtx op0 = rs6000_compare_op0;
12284 rtx op1 = rs6000_compare_op1;
12285 REAL_VALUE_TYPE c1;
12286 enum machine_mode compare_mode = GET_MODE (op0);
12287 enum machine_mode result_mode = GET_MODE (dest);
12289 bool is_against_zero;
12291 /* These modes should always match. */
12292 if (GET_MODE (op1) != compare_mode
12293 /* In the isel case however, we can use a compare immediate, so
12294 op1 may be a small constant. */
12295 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12297 if (GET_MODE (true_cond) != result_mode)
12299 if (GET_MODE (false_cond) != result_mode)
12302 /* First, work out if the hardware can do this at all, or
12303 if it's too slow.... */
12304 if (! rs6000_compare_fp_p)
12307 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12310 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12311 && SCALAR_FLOAT_MODE_P (compare_mode))
12314 is_against_zero = op1 == CONST0_RTX (compare_mode);
12316 /* A floating-point subtract might overflow, underflow, or produce
12317 an inexact result, thus changing the floating-point flags, so it
12318 can't be generated if we care about that. It's safe if one side
12319 of the construct is zero, since then no subtract will be
12321 if (SCALAR_FLOAT_MODE_P (compare_mode)
12322 && flag_trapping_math && ! is_against_zero)
12325 /* Eliminate half of the comparisons by switching operands, this
12326 makes the remaining code simpler. */
12327 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12328 || code == LTGT || code == LT || code == UNLE)
12330 code = reverse_condition_maybe_unordered (code);
12332 true_cond = false_cond;
12336 /* UNEQ and LTGT take four instructions for a comparison with zero,
12337 it'll probably be faster to use a branch here too. */
12338 if (code == UNEQ && HONOR_NANS (compare_mode))
12341 if (GET_CODE (op1) == CONST_DOUBLE)
12342 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12344 /* We're going to try to implement comparisons by performing
12345 a subtract, then comparing against zero. Unfortunately,
12346 Inf - Inf is NaN which is not zero, and so if we don't
12347 know that the operand is finite and the comparison
12348 would treat EQ different to UNORDERED, we can't do it. */
12349 if (HONOR_INFINITIES (compare_mode)
12350 && code != GT && code != UNGE
12351 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12352 /* Constructs of the form (a OP b ? a : b) are safe. */
12353 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12354 || (! rtx_equal_p (op0, true_cond)
12355 && ! rtx_equal_p (op1, true_cond))))
12358 /* At this point we know we can use fsel. */
12360 /* Reduce the comparison to a comparison against zero. */
12361 if (! is_against_zero)
12363 temp = gen_reg_rtx (compare_mode);
12364 emit_insn (gen_rtx_SET (VOIDmode, temp,
12365 gen_rtx_MINUS (compare_mode, op0, op1)));
12367 op1 = CONST0_RTX (compare_mode);
12370 /* If we don't care about NaNs we can reduce some of the comparisons
12371 down to faster ones. */
12372 if (! HONOR_NANS (compare_mode))
12378 true_cond = false_cond;
12391 /* Now, reduce everything down to a GE. */
12398 temp = gen_reg_rtx (compare_mode);
12399 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12404 temp = gen_reg_rtx (compare_mode);
12405 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12410 temp = gen_reg_rtx (compare_mode);
12411 emit_insn (gen_rtx_SET (VOIDmode, temp,
12412 gen_rtx_NEG (compare_mode,
12413 gen_rtx_ABS (compare_mode, op0))));
12418 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12419 temp = gen_reg_rtx (result_mode);
12420 emit_insn (gen_rtx_SET (VOIDmode, temp,
12421 gen_rtx_IF_THEN_ELSE (result_mode,
12422 gen_rtx_GE (VOIDmode,
12424 true_cond, false_cond)));
12425 false_cond = true_cond;
12428 temp = gen_reg_rtx (compare_mode);
12429 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12434 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12435 temp = gen_reg_rtx (result_mode);
12436 emit_insn (gen_rtx_SET (VOIDmode, temp,
12437 gen_rtx_IF_THEN_ELSE (result_mode,
12438 gen_rtx_GE (VOIDmode,
12440 true_cond, false_cond)));
12441 true_cond = false_cond;
12444 temp = gen_reg_rtx (compare_mode);
12445 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12450 gcc_unreachable ();
12453 emit_insn (gen_rtx_SET (VOIDmode, dest,
12454 gen_rtx_IF_THEN_ELSE (result_mode,
12455 gen_rtx_GE (VOIDmode,
12457 true_cond, false_cond)));
12461 /* Same as above, but for ints (isel). */
12464 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12466 rtx condition_rtx, cr;
12468 /* All isel implementations thus far are 32-bits. */
12469 if (GET_MODE (rs6000_compare_op0) != SImode)
12472 /* We still have to do the compare, because isel doesn't do a
12473 compare, it just looks at the CRx bits set by a previous compare
12475 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12476 cr = XEXP (condition_rtx, 0);
12478 if (GET_MODE (cr) == CCmode)
12479 emit_insn (gen_isel_signed (dest, condition_rtx,
12480 true_cond, false_cond, cr));
12482 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12483 true_cond, false_cond, cr));
12489 output_isel (rtx *operands)
12491 enum rtx_code code;
12493 code = GET_CODE (operands[1]);
12494 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12496 PUT_CODE (operands[1], reverse_condition (code));
12497 return "isel %0,%3,%2,%j1";
12500 return "isel %0,%2,%3,%j1";
12504 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12506 enum machine_mode mode = GET_MODE (op0);
12510 if (code == SMAX || code == SMIN)
12515 if (code == SMAX || code == UMAX)
12516 target = emit_conditional_move (dest, c, op0, op1, mode,
12517 op0, op1, mode, 0);
12519 target = emit_conditional_move (dest, c, op0, op1, mode,
12520 op1, op0, mode, 0);
12521 gcc_assert (target);
12522 if (target != dest)
12523 emit_move_insn (dest, target);
12526 /* Emit instructions to perform a load-reserved/store-conditional operation.
12527 The operation performed is an atomic
12528 (set M (CODE:MODE M OP))
12529 If not NULL, BEFORE is atomically set to M before the operation, and
12530 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12531 If SYNC_P then a memory barrier is emitted before the operation.
12532 Either OP or M may be wrapped in a NOT operation. */
12535 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12536 rtx m, rtx op, rtx before_param, rtx after_param,
12539 enum machine_mode used_mode;
12540 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12543 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12544 rtx shift = NULL_RTX;
12547 emit_insn (gen_memory_barrier ());
12549 if (GET_CODE (m) == NOT)
12550 used_m = XEXP (m, 0);
12554 /* If this is smaller than SImode, we'll have to use SImode with
12556 if (mode == QImode || mode == HImode)
12560 if (MEM_ALIGN (used_m) >= 32)
12563 if (BYTES_BIG_ENDIAN)
12564 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12566 shift = GEN_INT (ishift);
12570 rtx addrSI, aligned_addr;
12571 int shift_mask = mode == QImode ? 0x18 : 0x10;
12573 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12574 XEXP (used_m, 0)));
12575 shift = gen_reg_rtx (SImode);
12577 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12578 GEN_INT (shift_mask)));
12579 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12581 aligned_addr = expand_binop (Pmode, and_optab,
12583 GEN_INT (-4), NULL_RTX,
12584 1, OPTAB_LIB_WIDEN);
12585 used_m = change_address (used_m, SImode, aligned_addr);
12586 set_mem_align (used_m, 32);
12587 /* It's safe to keep the old alias set of USED_M, because
12588 the operation is atomic and only affects the original
12590 if (GET_CODE (m) == NOT)
12591 m = gen_rtx_NOT (SImode, used_m);
12596 if (GET_CODE (op) == NOT)
12598 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12599 oldop = gen_rtx_NOT (SImode, oldop);
12602 oldop = lowpart_subreg (SImode, op, mode);
12608 newop = expand_binop (SImode, and_optab,
12609 oldop, GEN_INT (imask), NULL_RTX,
12610 1, OPTAB_LIB_WIDEN);
12611 emit_insn (gen_ashlsi3 (newop, newop, shift));
12615 newop = expand_binop (SImode, ior_optab,
12616 oldop, GEN_INT (~imask), NULL_RTX,
12617 1, OPTAB_LIB_WIDEN);
12618 emit_insn (gen_rotlsi3 (newop, newop, shift));
12626 newop = expand_binop (SImode, and_optab,
12627 oldop, GEN_INT (imask), NULL_RTX,
12628 1, OPTAB_LIB_WIDEN);
12629 emit_insn (gen_ashlsi3 (newop, newop, shift));
12631 mask = gen_reg_rtx (SImode);
12632 emit_move_insn (mask, GEN_INT (imask));
12633 emit_insn (gen_ashlsi3 (mask, mask, shift));
12636 newop = gen_rtx_PLUS (SImode, m, newop);
12638 newop = gen_rtx_MINUS (SImode, m, newop);
12639 newop = gen_rtx_AND (SImode, newop, mask);
12640 newop = gen_rtx_IOR (SImode, newop,
12641 gen_rtx_AND (SImode,
12642 gen_rtx_NOT (SImode, mask),
12648 gcc_unreachable ();
12651 if (GET_CODE (m) == NOT)
12655 mask = gen_reg_rtx (SImode);
12656 emit_move_insn (mask, GEN_INT (imask));
12657 emit_insn (gen_ashlsi3 (mask, mask, shift));
12659 xorm = gen_rtx_XOR (SImode, used_m, mask);
12660 /* Depending on the value of 'op', the XOR or the operation might
12661 be able to be simplified away. */
12662 newop = simplify_gen_binary (code, SImode, xorm, newop);
12665 used_mode = SImode;
12666 before = gen_reg_rtx (used_mode);
12667 after = gen_reg_rtx (used_mode);
12672 before = before_param;
12673 after = after_param;
12675 if (before == NULL_RTX)
12676 before = gen_reg_rtx (used_mode);
12677 if (after == NULL_RTX)
12678 after = gen_reg_rtx (used_mode);
12681 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12682 && used_mode != mode)
12683 the_op = op; /* Computed above. */
12684 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12685 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12687 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12689 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12690 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12691 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12692 gen_rtx_UNSPEC (used_mode,
12693 gen_rtvec (1, the_op),
12695 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12697 if ((code == PLUS || code == MINUS) && used_mode != mode)
12698 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12699 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12701 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12702 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12704 /* Shift and mask the return values properly. */
12705 if (used_mode != mode && before_param)
12707 emit_insn (gen_lshrsi3 (before, before, shift));
12708 convert_move (before_param, before, 1);
12711 if (used_mode != mode && after_param)
12713 emit_insn (gen_lshrsi3 (after, after, shift));
12714 convert_move (after_param, after, 1);
12717 /* The previous sequence will end with a branch that's dependent on
12718 the conditional store, so placing an isync will ensure that no
12719 other instructions (especially, no load or store instructions)
12720 can start before the atomic operation completes. */
12722 emit_insn (gen_isync ());
12725 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12726 COND is true. Mark the jump as unlikely to be taken. */
12729 emit_unlikely_jump (rtx cond, rtx label)
12731 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12734 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12735 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12736 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12739 /* A subroutine of the atomic operation splitters. Emit a load-locked
12740 instruction in MODE. */
12743 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12745 rtx (*fn) (rtx, rtx) = NULL;
12746 if (mode == SImode)
12747 fn = gen_load_locked_si;
12748 else if (mode == DImode)
12749 fn = gen_load_locked_di;
12750 emit_insn (fn (reg, mem));
12753 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12754 instruction in MODE. */
12757 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12759 rtx (*fn) (rtx, rtx, rtx) = NULL;
12760 if (mode == SImode)
12761 fn = gen_store_conditional_si;
12762 else if (mode == DImode)
12763 fn = gen_store_conditional_di;
12765 /* Emit sync before stwcx. to address PPC405 Erratum. */
12766 if (PPC405_ERRATUM77)
12767 emit_insn (gen_memory_barrier ());
12769 emit_insn (fn (res, mem, val));
12772 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12773 to perform. MEM is the memory on which to operate. VAL is the second
12774 operand of the binary operator. BEFORE and AFTER are optional locations to
12775 return the value of MEM either before of after the operation. SCRATCH is
12776 a scratch register. */
12779 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12780 rtx before, rtx after, rtx scratch)
12782 enum machine_mode mode = GET_MODE (mem);
12783 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12785 emit_insn (gen_memory_barrier ());
12787 label = gen_label_rtx ();
12788 emit_label (label);
12789 label = gen_rtx_LABEL_REF (VOIDmode, label);
12791 if (before == NULL_RTX)
12793 emit_load_locked (mode, before, mem);
12796 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12797 else if (code == AND)
12798 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12800 x = gen_rtx_fmt_ee (code, mode, before, val);
12802 if (after != NULL_RTX)
12803 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12804 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12806 emit_store_conditional (mode, cond, mem, scratch);
12808 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12809 emit_unlikely_jump (x, label);
12811 emit_insn (gen_isync ());
12814 /* Expand an atomic compare and swap operation. MEM is the memory on which
12815 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12816 value to be stored. SCRATCH is a scratch GPR. */
12819 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12822 enum machine_mode mode = GET_MODE (mem);
12823 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12825 emit_insn (gen_memory_barrier ());
12827 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12828 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12829 emit_label (XEXP (label1, 0));
12831 emit_load_locked (mode, retval, mem);
12833 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12834 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12836 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12837 emit_unlikely_jump (x, label2);
12839 emit_move_insn (scratch, newval);
12840 emit_store_conditional (mode, cond, mem, scratch);
12842 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12843 emit_unlikely_jump (x, label1);
12845 emit_insn (gen_isync ());
12846 emit_label (XEXP (label2, 0));
12849 /* Expand an atomic test and set operation. MEM is the memory on which
12850 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12853 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12855 enum machine_mode mode = GET_MODE (mem);
12856 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12858 emit_insn (gen_memory_barrier ());
12860 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12861 emit_label (XEXP (label, 0));
12863 emit_load_locked (mode, retval, mem);
12864 emit_move_insn (scratch, val);
12865 emit_store_conditional (mode, cond, mem, scratch);
12867 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12868 emit_unlikely_jump (x, label);
12870 emit_insn (gen_isync ());
12874 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12876 enum machine_mode mode = GET_MODE (mem);
12877 rtx addrSI, align, wdst, shift, mask;
12878 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12879 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12881 /* Shift amount for subword relative to aligned word. */
12882 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12883 shift = gen_reg_rtx (SImode);
12884 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12885 GEN_INT (shift_mask)));
12886 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12888 /* Shift and mask old value into position within word. */
12889 oldval = convert_modes (SImode, mode, oldval, 1);
12890 oldval = expand_binop (SImode, and_optab,
12891 oldval, GEN_INT (imask), NULL_RTX,
12892 1, OPTAB_LIB_WIDEN);
12893 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12895 /* Shift and mask new value into position within word. */
12896 newval = convert_modes (SImode, mode, newval, 1);
12897 newval = expand_binop (SImode, and_optab,
12898 newval, GEN_INT (imask), NULL_RTX,
12899 1, OPTAB_LIB_WIDEN);
12900 emit_insn (gen_ashlsi3 (newval, newval, shift));
12902 /* Mask for insertion. */
12903 mask = gen_reg_rtx (SImode);
12904 emit_move_insn (mask, GEN_INT (imask));
12905 emit_insn (gen_ashlsi3 (mask, mask, shift));
12907 /* Address of aligned word containing subword. */
12908 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12909 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12910 mem = change_address (mem, SImode, align);
12911 set_mem_align (mem, 32);
12912 MEM_VOLATILE_P (mem) = 1;
12914 wdst = gen_reg_rtx (SImode);
12915 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12916 oldval, newval, mem));
12918 emit_move_insn (dst, gen_lowpart (mode, wdst));
12922 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12923 rtx oldval, rtx newval, rtx mem,
12926 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12928 emit_insn (gen_memory_barrier ());
12929 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12930 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12931 emit_label (XEXP (label1, 0));
12933 emit_load_locked (SImode, scratch, mem);
12935 /* Mask subword within loaded value for comparison with oldval.
12936 Use UNSPEC_AND to avoid clobber.*/
12937 emit_insn (gen_rtx_SET (SImode, dest,
12938 gen_rtx_UNSPEC (SImode,
12939 gen_rtvec (2, scratch, mask),
12942 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12943 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12945 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12946 emit_unlikely_jump (x, label2);
12948 /* Clear subword within loaded value for insertion of new value. */
12949 emit_insn (gen_rtx_SET (SImode, scratch,
12950 gen_rtx_AND (SImode,
12951 gen_rtx_NOT (SImode, mask), scratch)));
12952 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12953 emit_store_conditional (SImode, cond, mem, scratch);
12955 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12956 emit_unlikely_jump (x, label1);
12958 emit_insn (gen_isync ());
12959 emit_label (XEXP (label2, 0));
12963 /* Emit instructions to move SRC to DST. Called by splitters for
12964 multi-register moves. It will emit at most one instruction for
12965 each register that is accessed; that is, it won't emit li/lis pairs
12966 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12970 rs6000_split_multireg_move (rtx dst, rtx src)
12972 /* The register number of the first register being moved. */
12974 /* The mode that is to be moved. */
12975 enum machine_mode mode;
12976 /* The mode that the move is being done in, and its size. */
12977 enum machine_mode reg_mode;
12979 /* The number of registers that will be moved. */
12982 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12983 mode = GET_MODE (dst);
12984 nregs = hard_regno_nregs[reg][mode];
12985 if (FP_REGNO_P (reg))
12986 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
12987 else if (ALTIVEC_REGNO_P (reg))
12988 reg_mode = V16QImode;
12989 else if (TARGET_E500_DOUBLE && mode == TFmode)
12992 reg_mode = word_mode;
12993 reg_mode_size = GET_MODE_SIZE (reg_mode);
12995 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12997 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12999 /* Move register range backwards, if we might have destructive
13002 for (i = nregs - 1; i >= 0; i--)
13003 emit_insn (gen_rtx_SET (VOIDmode,
13004 simplify_gen_subreg (reg_mode, dst, mode,
13005 i * reg_mode_size),
13006 simplify_gen_subreg (reg_mode, src, mode,
13007 i * reg_mode_size)));
13013 bool used_update = false;
13015 if (MEM_P (src) && INT_REGNO_P (reg))
13019 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13020 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13023 breg = XEXP (XEXP (src, 0), 0);
13024 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13025 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13026 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13027 emit_insn (TARGET_32BIT
13028 ? gen_addsi3 (breg, breg, delta_rtx)
13029 : gen_adddi3 (breg, breg, delta_rtx));
13030 src = replace_equiv_address (src, breg);
13032 else if (! rs6000_offsettable_memref_p (src))
13035 basereg = gen_rtx_REG (Pmode, reg);
13036 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13037 src = replace_equiv_address (src, basereg);
13040 breg = XEXP (src, 0);
13041 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13042 breg = XEXP (breg, 0);
13044 /* If the base register we are using to address memory is
13045 also a destination reg, then change that register last. */
13047 && REGNO (breg) >= REGNO (dst)
13048 && REGNO (breg) < REGNO (dst) + nregs)
13049 j = REGNO (breg) - REGNO (dst);
13052 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13056 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13057 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13060 breg = XEXP (XEXP (dst, 0), 0);
13061 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13062 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13063 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13065 /* We have to update the breg before doing the store.
13066 Use store with update, if available. */
13070 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13071 emit_insn (TARGET_32BIT
13072 ? (TARGET_POWERPC64
13073 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13074 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13075 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13076 used_update = true;
13079 emit_insn (TARGET_32BIT
13080 ? gen_addsi3 (breg, breg, delta_rtx)
13081 : gen_adddi3 (breg, breg, delta_rtx));
13082 dst = replace_equiv_address (dst, breg);
13085 gcc_assert (rs6000_offsettable_memref_p (dst));
13088 for (i = 0; i < nregs; i++)
13090 /* Calculate index to next subword. */
13095 /* If compiler already emitted move of first word by
13096 store with update, no need to do anything. */
13097 if (j == 0 && used_update)
13100 emit_insn (gen_rtx_SET (VOIDmode,
13101 simplify_gen_subreg (reg_mode, dst, mode,
13102 j * reg_mode_size),
13103 simplify_gen_subreg (reg_mode, src, mode,
13104 j * reg_mode_size)));
13110 /* This page contains routines that are used to determine what the
13111 function prologue and epilogue code will do and write them out. */
13113 /* Return the first fixed-point register that is required to be
13114 saved. 32 if none. */
13117 first_reg_to_save (void)
13121 /* Find lowest numbered live register. */
13122 for (first_reg = 13; first_reg <= 31; first_reg++)
13123 if (regs_ever_live[first_reg]
13124 && (! call_used_regs[first_reg]
13125 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13126 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13127 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13128 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13133 && current_function_uses_pic_offset_table
13134 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13135 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13141 /* Similar, for FP regs. */
13144 first_fp_reg_to_save (void)
13148 /* Find lowest numbered live register. */
13149 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13150 if (regs_ever_live[first_reg])
13156 /* Similar, for AltiVec regs. */
13159 first_altivec_reg_to_save (void)
13163 /* Stack frame remains as is unless we are in AltiVec ABI. */
13164 if (! TARGET_ALTIVEC_ABI)
13165 return LAST_ALTIVEC_REGNO + 1;
13167 /* On Darwin, the unwind routines are compiled without
13168 TARGET_ALTIVEC, and use save_world to save/restore the
13169 altivec registers when necessary. */
13170 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13171 && ! TARGET_ALTIVEC)
13172 return FIRST_ALTIVEC_REGNO + 20;
13174 /* Find lowest numbered live register. */
13175 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13176 if (regs_ever_live[i])
13182 /* Return a 32-bit mask of the AltiVec registers we need to set in
13183 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13184 the 32-bit word is 0. */
13186 static unsigned int
13187 compute_vrsave_mask (void)
13189 unsigned int i, mask = 0;
13191 /* On Darwin, the unwind routines are compiled without
13192 TARGET_ALTIVEC, and use save_world to save/restore the
13193 call-saved altivec registers when necessary. */
13194 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13195 && ! TARGET_ALTIVEC)
13198 /* First, find out if we use _any_ altivec registers. */
13199 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13200 if (regs_ever_live[i])
13201 mask |= ALTIVEC_REG_BIT (i);
13206 /* Next, remove the argument registers from the set. These must
13207 be in the VRSAVE mask set by the caller, so we don't need to add
13208 them in again. More importantly, the mask we compute here is
13209 used to generate CLOBBERs in the set_vrsave insn, and we do not
13210 wish the argument registers to die. */
13211 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13212 mask &= ~ALTIVEC_REG_BIT (i);
13214 /* Similarly, remove the return value from the set. */
13217 diddle_return_value (is_altivec_return_reg, &yes);
13219 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13225 /* For a very restricted set of circumstances, we can cut down the
13226 size of prologues/epilogues by calling our own save/restore-the-world
13230 compute_save_world_info (rs6000_stack_t *info_ptr)
13232 info_ptr->world_save_p = 1;
13233 info_ptr->world_save_p
13234 = (WORLD_SAVE_P (info_ptr)
13235 && DEFAULT_ABI == ABI_DARWIN
13236 && ! (current_function_calls_setjmp && flag_exceptions)
13237 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13238 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13239 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13240 && info_ptr->cr_save_p);
13242 /* This will not work in conjunction with sibcalls. Make sure there
13243 are none. (This check is expensive, but seldom executed.) */
13244 if (WORLD_SAVE_P (info_ptr))
13247 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13248 if ( GET_CODE (insn) == CALL_INSN
13249 && SIBLING_CALL_P (insn))
13251 info_ptr->world_save_p = 0;
13256 if (WORLD_SAVE_P (info_ptr))
13258 /* Even if we're not touching VRsave, make sure there's room on the
13259 stack for it, if it looks like we're calling SAVE_WORLD, which
13260 will attempt to save it. */
13261 info_ptr->vrsave_size = 4;
13263 /* "Save" the VRsave register too if we're saving the world. */
13264 if (info_ptr->vrsave_mask == 0)
13265 info_ptr->vrsave_mask = compute_vrsave_mask ();
13267 /* Because the Darwin register save/restore routines only handle
13268 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13270 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13271 && (info_ptr->first_altivec_reg_save
13272 >= FIRST_SAVED_ALTIVEC_REGNO));
13279 is_altivec_return_reg (rtx reg, void *xyes)
13281 bool *yes = (bool *) xyes;
13282 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13287 /* Calculate the stack information for the current function. This is
13288 complicated by having two separate calling sequences, the AIX calling
13289 sequence and the V.4 calling sequence.
13291 AIX (and Darwin/Mac OS X) stack frames look like:
13293 SP----> +---------------------------------------+
13294 | back chain to caller | 0 0
13295 +---------------------------------------+
13296 | saved CR | 4 8 (8-11)
13297 +---------------------------------------+
13299 +---------------------------------------+
13300 | reserved for compilers | 12 24
13301 +---------------------------------------+
13302 | reserved for binders | 16 32
13303 +---------------------------------------+
13304 | saved TOC pointer | 20 40
13305 +---------------------------------------+
13306 | Parameter save area (P) | 24 48
13307 +---------------------------------------+
13308 | Alloca space (A) | 24+P etc.
13309 +---------------------------------------+
13310 | Local variable space (L) | 24+P+A
13311 +---------------------------------------+
13312 | Float/int conversion temporary (X) | 24+P+A+L
13313 +---------------------------------------+
13314 | Save area for AltiVec registers (W) | 24+P+A+L+X
13315 +---------------------------------------+
13316 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13317 +---------------------------------------+
13318 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13319 +---------------------------------------+
13320 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13321 +---------------------------------------+
13322 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13323 +---------------------------------------+
13324 old SP->| back chain to caller's caller |
13325 +---------------------------------------+
13327 The required alignment for AIX configurations is two words (i.e., 8
13331 V.4 stack frames look like:
13333 SP----> +---------------------------------------+
13334 | back chain to caller | 0
13335 +---------------------------------------+
13336 | caller's saved LR | 4
13337 +---------------------------------------+
13338 | Parameter save area (P) | 8
13339 +---------------------------------------+
13340 | Alloca space (A) | 8+P
13341 +---------------------------------------+
13342 | Varargs save area (V) | 8+P+A
13343 +---------------------------------------+
13344 | Local variable space (L) | 8+P+A+V
13345 +---------------------------------------+
13346 | Float/int conversion temporary (X) | 8+P+A+V+L
13347 +---------------------------------------+
13348 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13349 +---------------------------------------+
13350 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13351 +---------------------------------------+
13352 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13353 +---------------------------------------+
13354 | SPE: area for 64-bit GP registers |
13355 +---------------------------------------+
13356 | SPE alignment padding |
13357 +---------------------------------------+
13358 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13359 +---------------------------------------+
13360 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13361 +---------------------------------------+
13362 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13363 +---------------------------------------+
13364 old SP->| back chain to caller's caller |
13365 +---------------------------------------+
13367 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13368 given. (But note below and in sysv4.h that we require only 8 and
13369 may round up the size of our stack frame anyways. The historical
13370 reason is early versions of powerpc-linux which didn't properly
13371 align the stack at program startup. A happy side-effect is that
13372 -mno-eabi libraries can be used with -meabi programs.)
13374 The EABI configuration defaults to the V.4 layout. However,
13375 the stack alignment requirements may differ. If -mno-eabi is not
13376 given, the required stack alignment is 8 bytes; if -mno-eabi is
13377 given, the required alignment is 16 bytes. (But see V.4 comment
13380 #ifndef ABI_STACK_BOUNDARY
13381 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13384 static rs6000_stack_t *
13385 rs6000_stack_info (void)
13387 static rs6000_stack_t info;
13388 rs6000_stack_t *info_ptr = &info;
13389 int reg_size = TARGET_32BIT ? 4 : 8;
13392 HOST_WIDE_INT non_fixed_size;
13394 memset (&info, 0, sizeof (info));
13398 /* Cache value so we don't rescan instruction chain over and over. */
13399 if (cfun->machine->insn_chain_scanned_p == 0)
13400 cfun->machine->insn_chain_scanned_p
13401 = spe_func_has_64bit_regs_p () + 1;
13402 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13405 /* Select which calling sequence. */
13406 info_ptr->abi = DEFAULT_ABI;
13408 /* Calculate which registers need to be saved & save area size. */
13409 info_ptr->first_gp_reg_save = first_reg_to_save ();
13410 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13411 even if it currently looks like we won't. */
13412 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13413 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13414 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13415 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13416 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13418 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13420 /* For the SPE, we have an additional upper 32-bits on each GPR.
13421 Ideally we should save the entire 64-bits only when the upper
13422 half is used in SIMD instructions. Since we only record
13423 registers live (not the size they are used in), this proves
13424 difficult because we'd have to traverse the instruction chain at
13425 the right time, taking reload into account. This is a real pain,
13426 so we opt to save the GPRs in 64-bits always if but one register
13427 gets used in 64-bits. Otherwise, all the registers in the frame
13428 get saved in 32-bits.
13430 So... since when we save all GPRs (except the SP) in 64-bits, the
13431 traditional GP save area will be empty. */
13432 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13433 info_ptr->gp_size = 0;
13435 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13436 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13438 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13439 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13440 - info_ptr->first_altivec_reg_save);
13442 /* Does this function call anything? */
13443 info_ptr->calls_p = (! current_function_is_leaf
13444 || cfun->machine->ra_needs_full_frame);
13446 /* Determine if we need to save the link register. */
13447 if ((DEFAULT_ABI == ABI_AIX
13448 && current_function_profile
13449 && !TARGET_PROFILE_KERNEL)
13450 #ifdef TARGET_RELOCATABLE
13451 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13453 || (info_ptr->first_fp_reg_save != 64
13454 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13455 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13456 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13457 || info_ptr->calls_p
13458 || rs6000_ra_ever_killed ())
13460 info_ptr->lr_save_p = 1;
13461 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
13464 /* Determine if we need to save the condition code registers. */
13465 if (regs_ever_live[CR2_REGNO]
13466 || regs_ever_live[CR3_REGNO]
13467 || regs_ever_live[CR4_REGNO])
13469 info_ptr->cr_save_p = 1;
13470 if (DEFAULT_ABI == ABI_V4)
13471 info_ptr->cr_size = reg_size;
13474 /* If the current function calls __builtin_eh_return, then we need
13475 to allocate stack space for registers that will hold data for
13476 the exception handler. */
13477 if (current_function_calls_eh_return)
13480 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13483 /* SPE saves EH registers in 64-bits. */
13484 ehrd_size = i * (TARGET_SPE_ABI
13485 && info_ptr->spe_64bit_regs_used != 0
13486 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13491 /* Determine various sizes. */
13492 info_ptr->reg_size = reg_size;
13493 info_ptr->fixed_size = RS6000_SAVE_AREA;
13494 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13495 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13496 TARGET_ALTIVEC ? 16 : 8);
13497 if (FRAME_GROWS_DOWNWARD)
13498 info_ptr->vars_size
13499 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13500 + info_ptr->parm_size,
13501 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13502 - (info_ptr->fixed_size + info_ptr->vars_size
13503 + info_ptr->parm_size);
13505 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13506 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13508 info_ptr->spe_gp_size = 0;
13510 if (TARGET_ALTIVEC_ABI)
13511 info_ptr->vrsave_mask = compute_vrsave_mask ();
13513 info_ptr->vrsave_mask = 0;
13515 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13516 info_ptr->vrsave_size = 4;
13518 info_ptr->vrsave_size = 0;
13520 compute_save_world_info (info_ptr);
13522 /* Calculate the offsets. */
13523 switch (DEFAULT_ABI)
13527 gcc_unreachable ();
13531 info_ptr->fp_save_offset = - info_ptr->fp_size;
13532 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13534 if (TARGET_ALTIVEC_ABI)
13536 info_ptr->vrsave_save_offset
13537 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13539 /* Align stack so vector save area is on a quadword boundary.
13540 The padding goes above the vectors. */
13541 if (info_ptr->altivec_size != 0)
13542 info_ptr->altivec_padding_size
13543 = info_ptr->vrsave_save_offset & 0xF;
13545 info_ptr->altivec_padding_size = 0;
13547 info_ptr->altivec_save_offset
13548 = info_ptr->vrsave_save_offset
13549 - info_ptr->altivec_padding_size
13550 - info_ptr->altivec_size;
13551 gcc_assert (info_ptr->altivec_size == 0
13552 || info_ptr->altivec_save_offset % 16 == 0);
13554 /* Adjust for AltiVec case. */
13555 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13558 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13559 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13560 info_ptr->lr_save_offset = 2*reg_size;
13564 info_ptr->fp_save_offset = - info_ptr->fp_size;
13565 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13566 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13568 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13570 /* Align stack so SPE GPR save area is aligned on a
13571 double-word boundary. */
13572 if (info_ptr->spe_gp_size != 0)
13573 info_ptr->spe_padding_size
13574 = 8 - (-info_ptr->cr_save_offset % 8);
13576 info_ptr->spe_padding_size = 0;
13578 info_ptr->spe_gp_save_offset
13579 = info_ptr->cr_save_offset
13580 - info_ptr->spe_padding_size
13581 - info_ptr->spe_gp_size;
13583 /* Adjust for SPE case. */
13584 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13586 else if (TARGET_ALTIVEC_ABI)
13588 info_ptr->vrsave_save_offset
13589 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13591 /* Align stack so vector save area is on a quadword boundary. */
13592 if (info_ptr->altivec_size != 0)
13593 info_ptr->altivec_padding_size
13594 = 16 - (-info_ptr->vrsave_save_offset % 16);
13596 info_ptr->altivec_padding_size = 0;
13598 info_ptr->altivec_save_offset
13599 = info_ptr->vrsave_save_offset
13600 - info_ptr->altivec_padding_size
13601 - info_ptr->altivec_size;
13603 /* Adjust for AltiVec case. */
13604 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13607 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13608 info_ptr->ehrd_offset -= ehrd_size;
13609 info_ptr->lr_save_offset = reg_size;
13613 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13614 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13615 + info_ptr->gp_size
13616 + info_ptr->altivec_size
13617 + info_ptr->altivec_padding_size
13618 + info_ptr->spe_gp_size
13619 + info_ptr->spe_padding_size
13621 + info_ptr->cr_size
13622 + info_ptr->vrsave_size,
13625 non_fixed_size = (info_ptr->vars_size
13626 + info_ptr->parm_size
13627 + info_ptr->save_size);
13629 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13630 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13632 /* Determine if we need to allocate any stack frame:
13634 For AIX we need to push the stack if a frame pointer is needed
13635 (because the stack might be dynamically adjusted), if we are
13636 debugging, if we make calls, or if the sum of fp_save, gp_save,
13637 and local variables are more than the space needed to save all
13638 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13639 + 18*8 = 288 (GPR13 reserved).
13641 For V.4 we don't have the stack cushion that AIX uses, but assume
13642 that the debugger can handle stackless frames. */
13644 if (info_ptr->calls_p)
13645 info_ptr->push_p = 1;
13647 else if (DEFAULT_ABI == ABI_V4)
13648 info_ptr->push_p = non_fixed_size != 0;
13650 else if (frame_pointer_needed)
13651 info_ptr->push_p = 1;
13653 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13654 info_ptr->push_p = 1;
13657 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13659 /* Zero offsets if we're not saving those registers. */
13660 if (info_ptr->fp_size == 0)
13661 info_ptr->fp_save_offset = 0;
13663 if (info_ptr->gp_size == 0)
13664 info_ptr->gp_save_offset = 0;
13666 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13667 info_ptr->altivec_save_offset = 0;
13669 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13670 info_ptr->vrsave_save_offset = 0;
13672 if (! TARGET_SPE_ABI
13673 || info_ptr->spe_64bit_regs_used == 0
13674 || info_ptr->spe_gp_size == 0)
13675 info_ptr->spe_gp_save_offset = 0;
13677 if (! info_ptr->lr_save_p)
13678 info_ptr->lr_save_offset = 0;
13680 if (! info_ptr->cr_save_p)
13681 info_ptr->cr_save_offset = 0;
13686 /* Return true if the current function uses any GPRs in 64-bit SIMD
13690 spe_func_has_64bit_regs_p (void)
13694 /* Functions that save and restore all the call-saved registers will
13695 need to save/restore the registers in 64-bits. */
13696 if (current_function_calls_eh_return
13697 || current_function_calls_setjmp
13698 || current_function_has_nonlocal_goto)
13701 insns = get_insns ();
13703 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13709 /* FIXME: This should be implemented with attributes...
13711 (set_attr "spe64" "true")....then,
13712 if (get_spe64(insn)) return true;
13714 It's the only reliable way to do the stuff below. */
13716 i = PATTERN (insn);
13717 if (GET_CODE (i) == SET)
13719 enum machine_mode mode = GET_MODE (SET_SRC (i));
13721 if (SPE_VECTOR_MODE (mode))
13723 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13733 debug_stack_info (rs6000_stack_t *info)
13735 const char *abi_string;
13738 info = rs6000_stack_info ();
13740 fprintf (stderr, "\nStack information for function %s:\n",
13741 ((current_function_decl && DECL_NAME (current_function_decl))
13742 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13747 default: abi_string = "Unknown"; break;
13748 case ABI_NONE: abi_string = "NONE"; break;
13749 case ABI_AIX: abi_string = "AIX"; break;
13750 case ABI_DARWIN: abi_string = "Darwin"; break;
13751 case ABI_V4: abi_string = "V.4"; break;
13754 fprintf (stderr, "\tABI = %5s\n", abi_string);
13756 if (TARGET_ALTIVEC_ABI)
13757 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13759 if (TARGET_SPE_ABI)
13760 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13762 if (info->first_gp_reg_save != 32)
13763 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13765 if (info->first_fp_reg_save != 64)
13766 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13768 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13769 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13770 info->first_altivec_reg_save);
13772 if (info->lr_save_p)
13773 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13775 if (info->cr_save_p)
13776 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13778 if (info->vrsave_mask)
13779 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13782 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13785 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13787 if (info->gp_save_offset)
13788 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13790 if (info->fp_save_offset)
13791 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13793 if (info->altivec_save_offset)
13794 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13795 info->altivec_save_offset);
13797 if (info->spe_gp_save_offset)
13798 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13799 info->spe_gp_save_offset);
13801 if (info->vrsave_save_offset)
13802 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13803 info->vrsave_save_offset);
13805 if (info->lr_save_offset)
13806 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13808 if (info->cr_save_offset)
13809 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13811 if (info->varargs_save_offset)
13812 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13814 if (info->total_size)
13815 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13818 if (info->vars_size)
13819 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13822 if (info->parm_size)
13823 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13825 if (info->fixed_size)
13826 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13829 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13831 if (info->spe_gp_size)
13832 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13835 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13837 if (info->altivec_size)
13838 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13840 if (info->vrsave_size)
13841 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13843 if (info->altivec_padding_size)
13844 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13845 info->altivec_padding_size);
13847 if (info->spe_padding_size)
13848 fprintf (stderr, "\tspe_padding_size = %5d\n",
13849 info->spe_padding_size);
13852 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13854 if (info->save_size)
13855 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13857 if (info->reg_size != 4)
13858 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13860 fprintf (stderr, "\n");
13864 rs6000_return_addr (int count, rtx frame)
13866 /* Currently we don't optimize very well between prolog and body
13867 code and for PIC code the code can be actually quite bad, so
13868 don't try to be too clever here. */
13869 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13871 cfun->machine->ra_needs_full_frame = 1;
13878 plus_constant (copy_to_reg
13879 (gen_rtx_MEM (Pmode,
13880 memory_address (Pmode, frame))),
13881 RETURN_ADDRESS_OFFSET)));
13884 cfun->machine->ra_need_lr = 1;
13885 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13888 /* Say whether a function is a candidate for sibcall handling or not.
13889 We do not allow indirect calls to be optimized into sibling calls.
13890 Also, we can't do it if there are any vector parameters; there's
13891 nowhere to put the VRsave code so it works; note that functions with
13892 vector parameters are required to have a prototype, so the argument
13893 type info must be available here. (The tail recursion case can work
13894 with vector parameters, but there's no way to distinguish here.) */
13896 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13901 if (TARGET_ALTIVEC_VRSAVE)
13903 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13904 type; type = TREE_CHAIN (type))
13906 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13910 if (DEFAULT_ABI == ABI_DARWIN
13911 || (*targetm.binds_local_p) (decl))
13913 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13915 if (!lookup_attribute ("longcall", attr_list)
13916 || lookup_attribute ("shortcall", attr_list))
13923 /* NULL if INSN insn is valid within a low-overhead loop.
13924 Otherwise return why doloop cannot be applied.
13925 PowerPC uses the COUNT register for branch on table instructions. */
13927 static const char *
13928 rs6000_invalid_within_doloop (rtx insn)
13931 return "Function call in the loop.";
13934 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13935 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13936 return "Computed branch in the loop.";
13942 rs6000_ra_ever_killed (void)
13948 if (current_function_is_thunk)
13951 /* regs_ever_live has LR marked as used if any sibcalls are present,
13952 but this should not force saving and restoring in the
13953 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13954 clobbers LR, so that is inappropriate. */
13956 /* Also, the prologue can generate a store into LR that
13957 doesn't really count, like this:
13960 bcl to set PIC register
13964 When we're called from the epilogue, we need to avoid counting
13965 this as a store. */
13967 push_topmost_sequence ();
13968 top = get_insns ();
13969 pop_topmost_sequence ();
13970 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13972 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13978 if (!SIBLING_CALL_P (insn))
13981 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13983 else if (set_of (reg, insn) != NULL_RTX
13984 && !prologue_epilogue_contains (insn))
13991 /* Add a REG_MAYBE_DEAD note to the insn. */
13993 rs6000_maybe_dead (rtx insn)
13995 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
14000 /* Emit instructions needed to load the TOC register.
14001 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14002 a constant pool; or for SVR4 -fpic. */
14005 rs6000_emit_load_toc_table (int fromprolog)
14008 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14010 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14013 rtx lab, tmp1, tmp2, got;
14015 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14016 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14018 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14020 got = rs6000_got_sym ();
14021 tmp1 = tmp2 = dest;
14024 tmp1 = gen_reg_rtx (Pmode);
14025 tmp2 = gen_reg_rtx (Pmode);
14027 insn = emit_insn (gen_load_toc_v4_PIC_1 (lab));
14029 rs6000_maybe_dead (insn);
14030 insn = emit_move_insn (tmp1,
14031 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14033 rs6000_maybe_dead (insn);
14034 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14036 rs6000_maybe_dead (insn);
14037 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14039 rs6000_maybe_dead (insn);
14041 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14043 insn = emit_insn (gen_load_toc_v4_pic_si ());
14045 rs6000_maybe_dead (insn);
14046 insn = emit_move_insn (dest,
14047 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14049 rs6000_maybe_dead (insn);
14051 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14054 rtx temp0 = (fromprolog
14055 ? gen_rtx_REG (Pmode, 0)
14056 : gen_reg_rtx (Pmode));
14062 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14063 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14065 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14066 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14068 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (symF)));
14069 rs6000_maybe_dead (emit_move_insn (dest,
14070 gen_rtx_REG (Pmode,
14071 LINK_REGISTER_REGNUM)));
14072 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
14080 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14081 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14082 emit_move_insn (dest,
14083 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14084 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14086 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
14088 rs6000_maybe_dead (insn);
14090 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14092 /* This is for AIX code running in non-PIC ELF32. */
14095 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14096 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14098 insn = emit_insn (gen_elf_high (dest, realsym));
14100 rs6000_maybe_dead (insn);
14101 insn = emit_insn (gen_elf_low (dest, dest, realsym));
14103 rs6000_maybe_dead (insn);
14107 gcc_assert (DEFAULT_ABI == ABI_AIX);
14110 insn = emit_insn (gen_load_toc_aix_si (dest));
14112 insn = emit_insn (gen_load_toc_aix_di (dest));
14114 rs6000_maybe_dead (insn);
14118 /* Emit instructions to restore the link register after determining where
14119 its value has been stored. */
14122 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14124 rs6000_stack_t *info = rs6000_stack_info ();
14127 operands[0] = source;
14128 operands[1] = scratch;
14130 if (info->lr_save_p)
14132 rtx frame_rtx = stack_pointer_rtx;
14133 HOST_WIDE_INT sp_offset = 0;
14136 if (frame_pointer_needed
14137 || current_function_calls_alloca
14138 || info->total_size > 32767)
14140 tmp = gen_frame_mem (Pmode, frame_rtx);
14141 emit_move_insn (operands[1], tmp);
14142 frame_rtx = operands[1];
14144 else if (info->push_p)
14145 sp_offset = info->total_size;
14147 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14148 tmp = gen_frame_mem (Pmode, tmp);
14149 emit_move_insn (tmp, operands[0]);
14152 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14155 static GTY(()) int set = -1;
14158 get_TOC_alias_set (void)
14161 set = new_alias_set ();
14165 /* This returns nonzero if the current function uses the TOC. This is
14166 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14167 is generated by the ABI_V4 load_toc_* patterns. */
14174 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14177 rtx pat = PATTERN (insn);
14180 if (GET_CODE (pat) == PARALLEL)
14181 for (i = 0; i < XVECLEN (pat, 0); i++)
14183 rtx sub = XVECEXP (pat, 0, i);
14184 if (GET_CODE (sub) == USE)
14186 sub = XEXP (sub, 0);
14187 if (GET_CODE (sub) == UNSPEC
14188 && XINT (sub, 1) == UNSPEC_TOC)
14198 create_TOC_reference (rtx symbol)
14200 if (no_new_pseudos)
14201 regs_ever_live[TOC_REGISTER] = 1;
14202 return gen_rtx_PLUS (Pmode,
14203 gen_rtx_REG (Pmode, TOC_REGISTER),
14204 gen_rtx_CONST (Pmode,
14205 gen_rtx_MINUS (Pmode, symbol,
14206 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14209 /* If _Unwind_* has been called from within the same module,
14210 toc register is not guaranteed to be saved to 40(1) on function
14211 entry. Save it there in that case. */
14214 rs6000_aix_emit_builtin_unwind_init (void)
14217 rtx stack_top = gen_reg_rtx (Pmode);
14218 rtx opcode_addr = gen_reg_rtx (Pmode);
14219 rtx opcode = gen_reg_rtx (SImode);
14220 rtx tocompare = gen_reg_rtx (SImode);
14221 rtx no_toc_save_needed = gen_label_rtx ();
14223 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14224 emit_move_insn (stack_top, mem);
14226 mem = gen_frame_mem (Pmode,
14227 gen_rtx_PLUS (Pmode, stack_top,
14228 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14229 emit_move_insn (opcode_addr, mem);
14230 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14231 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14232 : 0xE8410028, SImode));
14234 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14235 SImode, NULL_RTX, NULL_RTX,
14236 no_toc_save_needed);
14238 mem = gen_frame_mem (Pmode,
14239 gen_rtx_PLUS (Pmode, stack_top,
14240 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14241 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14242 emit_label (no_toc_save_needed);
14245 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14246 and the change to the stack pointer. */
14249 rs6000_emit_stack_tie (void)
14251 rtx mem = gen_frame_mem (BLKmode,
14252 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14254 emit_insn (gen_stack_tie (mem));
14257 /* Emit the correct code for allocating stack space, as insns.
14258 If COPY_R12, make sure a copy of the old frame is left in r12.
14259 The generated code may use hard register 0 as a temporary. */
14262 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14265 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14266 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14267 rtx todec = gen_int_mode (-size, Pmode);
14269 if (INTVAL (todec) != -size)
14271 warning (0, "stack frame too large");
14272 emit_insn (gen_trap ());
14276 if (current_function_limit_stack)
14278 if (REG_P (stack_limit_rtx)
14279 && REGNO (stack_limit_rtx) > 1
14280 && REGNO (stack_limit_rtx) <= 31)
14282 emit_insn (TARGET_32BIT
14283 ? gen_addsi3 (tmp_reg,
14286 : gen_adddi3 (tmp_reg,
14290 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14293 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14295 && DEFAULT_ABI == ABI_V4)
14297 rtx toload = gen_rtx_CONST (VOIDmode,
14298 gen_rtx_PLUS (Pmode,
14302 emit_insn (gen_elf_high (tmp_reg, toload));
14303 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14304 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14308 warning (0, "stack limit expression is not supported");
14311 if (copy_r12 || ! TARGET_UPDATE)
14312 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14318 /* Need a note here so that try_split doesn't get confused. */
14319 if (get_last_insn () == NULL_RTX)
14320 emit_note (NOTE_INSN_DELETED);
14321 insn = emit_move_insn (tmp_reg, todec);
14322 try_split (PATTERN (insn), insn, 0);
14326 insn = emit_insn (TARGET_32BIT
14327 ? gen_movsi_update (stack_reg, stack_reg,
14329 : gen_movdi_di_update (stack_reg, stack_reg,
14330 todec, stack_reg));
14334 insn = emit_insn (TARGET_32BIT
14335 ? gen_addsi3 (stack_reg, stack_reg, todec)
14336 : gen_adddi3 (stack_reg, stack_reg, todec));
14337 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14338 gen_rtx_REG (Pmode, 12));
14341 RTX_FRAME_RELATED_P (insn) = 1;
14343 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14344 gen_rtx_SET (VOIDmode, stack_reg,
14345 gen_rtx_PLUS (Pmode, stack_reg,
14350 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14351 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14352 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14353 deduce these equivalences by itself so it wasn't necessary to hold
14354 its hand so much. */
14357 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14358 rtx reg2, rtx rreg)
14362 /* copy_rtx will not make unique copies of registers, so we need to
14363 ensure we don't have unwanted sharing here. */
14365 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14368 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14370 real = copy_rtx (PATTERN (insn));
14372 if (reg2 != NULL_RTX)
14373 real = replace_rtx (real, reg2, rreg);
14375 real = replace_rtx (real, reg,
14376 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14377 STACK_POINTER_REGNUM),
14380 /* We expect that 'real' is either a SET or a PARALLEL containing
14381 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14382 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14384 if (GET_CODE (real) == SET)
14388 temp = simplify_rtx (SET_SRC (set));
14390 SET_SRC (set) = temp;
14391 temp = simplify_rtx (SET_DEST (set));
14393 SET_DEST (set) = temp;
14394 if (GET_CODE (SET_DEST (set)) == MEM)
14396 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14398 XEXP (SET_DEST (set), 0) = temp;
14405 gcc_assert (GET_CODE (real) == PARALLEL);
14406 for (i = 0; i < XVECLEN (real, 0); i++)
14407 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14409 rtx set = XVECEXP (real, 0, i);
14411 temp = simplify_rtx (SET_SRC (set));
14413 SET_SRC (set) = temp;
14414 temp = simplify_rtx (SET_DEST (set));
14416 SET_DEST (set) = temp;
14417 if (GET_CODE (SET_DEST (set)) == MEM)
14419 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14421 XEXP (SET_DEST (set), 0) = temp;
14423 RTX_FRAME_RELATED_P (set) = 1;
14428 real = spe_synthesize_frame_save (real);
14430 RTX_FRAME_RELATED_P (insn) = 1;
14431 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14436 /* Given an SPE frame note, return a PARALLEL of SETs with the
14437 original note, plus a synthetic register save. */
14440 spe_synthesize_frame_save (rtx real)
14442 rtx synth, offset, reg, real2;
14444 if (GET_CODE (real) != SET
14445 || GET_MODE (SET_SRC (real)) != V2SImode)
14448 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14449 frame related note. The parallel contains a set of the register
14450 being saved, and another set to a synthetic register (n+1200).
14451 This is so we can differentiate between 64-bit and 32-bit saves.
14452 Words cannot describe this nastiness. */
14454 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14455 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14456 && GET_CODE (SET_SRC (real)) == REG);
14459 (set (mem (plus (reg x) (const y)))
14462 (set (mem (plus (reg x) (const y+4)))
14466 real2 = copy_rtx (real);
14467 PUT_MODE (SET_DEST (real2), SImode);
14468 reg = SET_SRC (real2);
14469 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14470 synth = copy_rtx (real2);
14472 if (BYTES_BIG_ENDIAN)
14474 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14475 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14478 reg = SET_SRC (synth);
14480 synth = replace_rtx (synth, reg,
14481 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14483 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14484 synth = replace_rtx (synth, offset,
14485 GEN_INT (INTVAL (offset)
14486 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14488 RTX_FRAME_RELATED_P (synth) = 1;
14489 RTX_FRAME_RELATED_P (real2) = 1;
14490 if (BYTES_BIG_ENDIAN)
14491 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14493 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14498 /* Returns an insn that has a vrsave set operation with the
14499 appropriate CLOBBERs. */
14502 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14505 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14506 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14509 = gen_rtx_SET (VOIDmode,
14511 gen_rtx_UNSPEC_VOLATILE (SImode,
14512 gen_rtvec (2, reg, vrsave),
14513 UNSPECV_SET_VRSAVE));
14517 /* We need to clobber the registers in the mask so the scheduler
14518 does not move sets to VRSAVE before sets of AltiVec registers.
14520 However, if the function receives nonlocal gotos, reload will set
14521 all call saved registers live. We will end up with:
14523 (set (reg 999) (mem))
14524 (parallel [ (set (reg vrsave) (unspec blah))
14525 (clobber (reg 999))])
14527 The clobber will cause the store into reg 999 to be dead, and
14528 flow will attempt to delete an epilogue insn. In this case, we
14529 need an unspec use/set of the register. */
14531 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14532 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14534 if (!epiloguep || call_used_regs [i])
14535 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14536 gen_rtx_REG (V4SImode, i));
14539 rtx reg = gen_rtx_REG (V4SImode, i);
14542 = gen_rtx_SET (VOIDmode,
14544 gen_rtx_UNSPEC (V4SImode,
14545 gen_rtvec (1, reg), 27));
14549 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14551 for (i = 0; i < nclobs; ++i)
14552 XVECEXP (insn, 0, i) = clobs[i];
14557 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14558 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14561 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14562 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14564 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14565 rtx replacea, replaceb;
14567 int_rtx = GEN_INT (offset);
14569 /* Some cases that need register indexed addressing. */
14570 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14571 || (TARGET_E500_DOUBLE && mode == DFmode)
14573 && SPE_VECTOR_MODE (mode)
14574 && !SPE_CONST_OFFSET_OK (offset)))
14576 /* Whomever calls us must make sure r11 is available in the
14577 flow path of instructions in the prologue. */
14578 offset_rtx = gen_rtx_REG (Pmode, 11);
14579 emit_move_insn (offset_rtx, int_rtx);
14581 replacea = offset_rtx;
14582 replaceb = int_rtx;
14586 offset_rtx = int_rtx;
14587 replacea = NULL_RTX;
14588 replaceb = NULL_RTX;
14591 reg = gen_rtx_REG (mode, regno);
14592 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14593 mem = gen_frame_mem (mode, addr);
14595 insn = emit_move_insn (mem, reg);
14597 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14600 /* Emit an offset memory reference suitable for a frame store, while
14601 converting to a valid addressing mode. */
14604 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14606 rtx int_rtx, offset_rtx;
14608 int_rtx = GEN_INT (offset);
14610 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14611 || (TARGET_E500_DOUBLE && mode == DFmode))
14613 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14614 emit_move_insn (offset_rtx, int_rtx);
14617 offset_rtx = int_rtx;
14619 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14622 /* Look for user-defined global regs. We should not save and restore these,
14623 and cannot use stmw/lmw if there are any in its range. */
14626 no_global_regs_above (int first_greg)
14629 for (i = 0; i < 32 - first_greg; i++)
14630 if (global_regs[first_greg + i])
14635 #ifndef TARGET_FIX_AND_CONTINUE
14636 #define TARGET_FIX_AND_CONTINUE 0
14639 /* Determine whether the gp REG is really used. */
14642 rs6000_reg_live_or_pic_offset_p (int reg)
14644 return ((regs_ever_live[reg]
14645 && (!call_used_regs[reg]
14646 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14647 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14648 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14649 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14650 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
14653 /* Emit function prologue as insns. */
14656 rs6000_emit_prologue (void)
14658 rs6000_stack_t *info = rs6000_stack_info ();
14659 enum machine_mode reg_mode = Pmode;
14660 int reg_size = TARGET_32BIT ? 4 : 8;
14661 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14662 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14663 rtx frame_reg_rtx = sp_reg_rtx;
14664 rtx cr_save_rtx = NULL_RTX;
14666 int saving_FPRs_inline;
14667 int using_store_multiple;
14668 HOST_WIDE_INT sp_offset = 0;
14670 if (TARGET_FIX_AND_CONTINUE)
14672 /* gdb on darwin arranges to forward a function from the old
14673 address by modifying the first 5 instructions of the function
14674 to branch to the overriding function. This is necessary to
14675 permit function pointers that point to the old function to
14676 actually forward to the new function. */
14677 emit_insn (gen_nop ());
14678 emit_insn (gen_nop ());
14679 emit_insn (gen_nop ());
14680 emit_insn (gen_nop ());
14681 emit_insn (gen_nop ());
14684 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14686 reg_mode = V2SImode;
14690 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14691 && (!TARGET_SPE_ABI
14692 || info->spe_64bit_regs_used == 0)
14693 && info->first_gp_reg_save < 31
14694 && no_global_regs_above (info->first_gp_reg_save));
14695 saving_FPRs_inline = (info->first_fp_reg_save == 64
14696 || FP_SAVE_INLINE (info->first_fp_reg_save)
14697 || current_function_calls_eh_return
14698 || cfun->machine->ra_need_lr);
14700 /* For V.4, update stack before we do any saving and set back pointer. */
14701 if (! WORLD_SAVE_P (info)
14703 && (DEFAULT_ABI == ABI_V4
14704 || current_function_calls_eh_return))
14706 if (info->total_size < 32767)
14707 sp_offset = info->total_size;
14709 frame_reg_rtx = frame_ptr_rtx;
14710 rs6000_emit_allocate_stack (info->total_size,
14711 (frame_reg_rtx != sp_reg_rtx
14712 && (info->cr_save_p
14714 || info->first_fp_reg_save < 64
14715 || info->first_gp_reg_save < 32
14717 if (frame_reg_rtx != sp_reg_rtx)
14718 rs6000_emit_stack_tie ();
14721 /* Handle world saves specially here. */
14722 if (WORLD_SAVE_P (info))
14729 /* save_world expects lr in r0. */
14730 reg0 = gen_rtx_REG (Pmode, 0);
14731 if (info->lr_save_p)
14733 insn = emit_move_insn (reg0,
14734 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14735 RTX_FRAME_RELATED_P (insn) = 1;
14738 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14739 assumptions about the offsets of various bits of the stack
14741 gcc_assert (info->gp_save_offset == -220
14742 && info->fp_save_offset == -144
14743 && info->lr_save_offset == 8
14744 && info->cr_save_offset == 4
14747 && (!current_function_calls_eh_return
14748 || info->ehrd_offset == -432)
14749 && info->vrsave_save_offset == -224
14750 && info->altivec_save_offset == -416);
14752 treg = gen_rtx_REG (SImode, 11);
14753 emit_move_insn (treg, GEN_INT (-info->total_size));
14755 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14756 in R11. It also clobbers R12, so beware! */
14758 /* Preserve CR2 for save_world prologues */
14760 sz += 32 - info->first_gp_reg_save;
14761 sz += 64 - info->first_fp_reg_save;
14762 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14763 p = rtvec_alloc (sz);
14765 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14766 gen_rtx_REG (SImode,
14767 LINK_REGISTER_REGNUM));
14768 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14769 gen_rtx_SYMBOL_REF (Pmode,
14771 /* We do floats first so that the instruction pattern matches
14773 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14775 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14776 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14777 GEN_INT (info->fp_save_offset
14778 + sp_offset + 8 * i));
14779 rtx mem = gen_frame_mem (DFmode, addr);
14781 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14783 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14785 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14786 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14787 GEN_INT (info->altivec_save_offset
14788 + sp_offset + 16 * i));
14789 rtx mem = gen_frame_mem (V4SImode, addr);
14791 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14793 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14795 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14796 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14797 GEN_INT (info->gp_save_offset
14798 + sp_offset + reg_size * i));
14799 rtx mem = gen_frame_mem (reg_mode, addr);
14801 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14805 /* CR register traditionally saved as CR2. */
14806 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14807 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14808 GEN_INT (info->cr_save_offset
14810 rtx mem = gen_frame_mem (reg_mode, addr);
14812 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14814 /* Explain about use of R0. */
14815 if (info->lr_save_p)
14817 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14818 GEN_INT (info->lr_save_offset
14820 rtx mem = gen_frame_mem (reg_mode, addr);
14822 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14824 /* Explain what happens to the stack pointer. */
14826 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14827 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14830 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14831 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14832 treg, GEN_INT (-info->total_size));
14833 sp_offset = info->total_size;
14836 /* If we use the link register, get it into r0. */
14837 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14839 rtx addr, reg, mem;
14841 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14842 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14843 RTX_FRAME_RELATED_P (insn) = 1;
14845 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14846 GEN_INT (info->lr_save_offset + sp_offset));
14847 reg = gen_rtx_REG (Pmode, 0);
14848 mem = gen_rtx_MEM (Pmode, addr);
14849 /* This should not be of rs6000_sr_alias_set, because of
14850 __builtin_return_address. */
14852 insn = emit_move_insn (mem, reg);
14853 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14854 NULL_RTX, NULL_RTX);
14857 /* If we need to save CR, put it into r12. */
14858 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14862 cr_save_rtx = gen_rtx_REG (SImode, 12);
14863 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14864 RTX_FRAME_RELATED_P (insn) = 1;
14865 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14866 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14867 But that's OK. All we have to do is specify that _one_ condition
14868 code register is saved in this stack slot. The thrower's epilogue
14869 will then restore all the call-saved registers.
14870 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14871 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14872 gen_rtx_REG (SImode, CR2_REGNO));
14873 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14878 /* Do any required saving of fpr's. If only one or two to save, do
14879 it ourselves. Otherwise, call function. */
14880 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14883 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14884 if ((regs_ever_live[info->first_fp_reg_save+i]
14885 && ! call_used_regs[info->first_fp_reg_save+i]))
14886 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14887 info->first_fp_reg_save + i,
14888 info->fp_save_offset + sp_offset + 8 * i,
14891 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14895 const char *alloc_rname;
14897 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14899 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14900 gen_rtx_REG (Pmode,
14901 LINK_REGISTER_REGNUM));
14902 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14903 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14904 alloc_rname = ggc_strdup (rname);
14905 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14906 gen_rtx_SYMBOL_REF (Pmode,
14908 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14910 rtx addr, reg, mem;
14911 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14912 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14913 GEN_INT (info->fp_save_offset
14914 + sp_offset + 8*i));
14915 mem = gen_frame_mem (DFmode, addr);
14917 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14919 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14920 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14921 NULL_RTX, NULL_RTX);
14924 /* Save GPRs. This is done as a PARALLEL if we are using
14925 the store-multiple instructions. */
14926 if (!WORLD_SAVE_P (info) && using_store_multiple)
14930 p = rtvec_alloc (32 - info->first_gp_reg_save);
14931 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14933 rtx addr, reg, mem;
14934 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14935 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14936 GEN_INT (info->gp_save_offset
14939 mem = gen_frame_mem (reg_mode, addr);
14941 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14943 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14944 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14945 NULL_RTX, NULL_RTX);
14947 else if (!WORLD_SAVE_P (info)
14949 && info->spe_64bit_regs_used != 0
14950 && info->first_gp_reg_save != 32)
14953 rtx spe_save_area_ptr;
14954 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
14955 && regs_ever_live[STATIC_CHAIN_REGNUM]
14956 && !call_used_regs[STATIC_CHAIN_REGNUM]);
14958 /* Determine whether we can address all of the registers that need
14959 to be saved with an offset from the stack pointer that fits in
14960 the small const field for SPE memory instructions. */
14961 int spe_regs_addressable_via_sp
14962 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
14963 + (32 - info->first_gp_reg_save - 1) * reg_size);
14966 if (spe_regs_addressable_via_sp)
14968 spe_save_area_ptr = sp_reg_rtx;
14969 spe_offset = info->spe_gp_save_offset + sp_offset;
14973 /* Make r11 point to the start of the SPE save area. We need
14974 to be careful here if r11 is holding the static chain. If
14975 it is, then temporarily save it in r0. We would use r0 as
14976 our base register here, but using r0 as a base register in
14977 loads and stores means something different from what we
14979 if (using_static_chain_p)
14981 rtx r0 = gen_rtx_REG (Pmode, 0);
14983 gcc_assert (info->first_gp_reg_save > 11);
14985 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
14988 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
14989 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
14990 GEN_INT (info->spe_gp_save_offset + sp_offset)));
14995 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14996 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
14998 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14999 rtx offset, addr, mem;
15001 /* We're doing all this to ensure that the offset fits into
15002 the immediate offset of 'evstdd'. */
15003 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15005 offset = GEN_INT (reg_size * i + spe_offset);
15006 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15007 mem = gen_rtx_MEM (V2SImode, addr);
15009 insn = emit_move_insn (mem, reg);
15011 rs6000_frame_related (insn, spe_save_area_ptr,
15012 info->spe_gp_save_offset
15013 + sp_offset + reg_size * i,
15014 offset, const0_rtx);
15017 /* Move the static chain pointer back. */
15018 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15019 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15021 else if (!WORLD_SAVE_P (info))
15024 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15025 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15027 rtx addr, reg, mem;
15028 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15030 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15031 GEN_INT (info->gp_save_offset
15034 mem = gen_frame_mem (reg_mode, addr);
15036 insn = emit_move_insn (mem, reg);
15037 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15038 NULL_RTX, NULL_RTX);
15042 /* ??? There's no need to emit actual instructions here, but it's the
15043 easiest way to get the frame unwind information emitted. */
15044 if (current_function_calls_eh_return)
15046 unsigned int i, regno;
15048 /* In AIX ABI we need to pretend we save r2 here. */
15051 rtx addr, reg, mem;
15053 reg = gen_rtx_REG (reg_mode, 2);
15054 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15055 GEN_INT (sp_offset + 5 * reg_size));
15056 mem = gen_frame_mem (reg_mode, addr);
15058 insn = emit_move_insn (mem, reg);
15059 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15060 NULL_RTX, NULL_RTX);
15061 PATTERN (insn) = gen_blockage ();
15066 regno = EH_RETURN_DATA_REGNO (i);
15067 if (regno == INVALID_REGNUM)
15070 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15071 info->ehrd_offset + sp_offset
15072 + reg_size * (int) i,
15077 /* Save CR if we use any that must be preserved. */
15078 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15080 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15081 GEN_INT (info->cr_save_offset + sp_offset));
15082 rtx mem = gen_frame_mem (SImode, addr);
15083 /* See the large comment above about why CR2_REGNO is used. */
15084 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15086 /* If r12 was used to hold the original sp, copy cr into r0 now
15088 if (REGNO (frame_reg_rtx) == 12)
15092 cr_save_rtx = gen_rtx_REG (SImode, 0);
15093 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15094 RTX_FRAME_RELATED_P (insn) = 1;
15095 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15096 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15101 insn = emit_move_insn (mem, cr_save_rtx);
15103 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15104 NULL_RTX, NULL_RTX);
15107 /* Update stack and set back pointer unless this is V.4,
15108 for which it was done previously. */
15109 if (!WORLD_SAVE_P (info) && info->push_p
15110 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15112 if (info->total_size < 32767)
15113 sp_offset = info->total_size;
15115 frame_reg_rtx = frame_ptr_rtx;
15116 rs6000_emit_allocate_stack (info->total_size,
15117 (frame_reg_rtx != sp_reg_rtx
15118 && ((info->altivec_size != 0)
15119 || (info->vrsave_mask != 0)
15121 if (frame_reg_rtx != sp_reg_rtx)
15122 rs6000_emit_stack_tie ();
15125 /* Set frame pointer, if needed. */
15126 if (frame_pointer_needed)
15128 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15130 RTX_FRAME_RELATED_P (insn) = 1;
15133 /* Save AltiVec registers if needed. Save here because the red zone does
15134 not include AltiVec registers. */
15135 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15139 /* There should be a non inline version of this, for when we
15140 are saving lots of vector registers. */
15141 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15142 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15144 rtx areg, savereg, mem;
15147 offset = info->altivec_save_offset + sp_offset
15148 + 16 * (i - info->first_altivec_reg_save);
15150 savereg = gen_rtx_REG (V4SImode, i);
15152 areg = gen_rtx_REG (Pmode, 0);
15153 emit_move_insn (areg, GEN_INT (offset));
15155 /* AltiVec addressing mode is [reg+reg]. */
15156 mem = gen_frame_mem (V4SImode,
15157 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15159 insn = emit_move_insn (mem, savereg);
15161 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15162 areg, GEN_INT (offset));
15166 /* VRSAVE is a bit vector representing which AltiVec registers
15167 are used. The OS uses this to determine which vector
15168 registers to save on a context switch. We need to save
15169 VRSAVE on the stack frame, add whatever AltiVec registers we
15170 used in this function, and do the corresponding magic in the
15173 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15174 && info->vrsave_mask != 0)
15176 rtx reg, mem, vrsave;
15179 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15180 as frame_reg_rtx and r11 as the static chain pointer for
15181 nested functions. */
15182 reg = gen_rtx_REG (SImode, 0);
15183 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15185 emit_insn (gen_get_vrsave_internal (reg));
15187 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15189 if (!WORLD_SAVE_P (info))
15192 offset = info->vrsave_save_offset + sp_offset;
15193 mem = gen_frame_mem (SImode,
15194 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15195 GEN_INT (offset)));
15196 insn = emit_move_insn (mem, reg);
15199 /* Include the registers in the mask. */
15200 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15202 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15205 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15206 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15207 || (DEFAULT_ABI == ABI_V4
15208 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15209 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
15211 /* If emit_load_toc_table will use the link register, we need to save
15212 it. We use R12 for this purpose because emit_load_toc_table
15213 can use register 0. This allows us to use a plain 'blr' to return
15214 from the procedure more often. */
15215 int save_LR_around_toc_setup = (TARGET_ELF
15216 && DEFAULT_ABI != ABI_AIX
15218 && ! info->lr_save_p
15219 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15220 if (save_LR_around_toc_setup)
15222 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15224 insn = emit_move_insn (frame_ptr_rtx, lr);
15225 rs6000_maybe_dead (insn);
15226 RTX_FRAME_RELATED_P (insn) = 1;
15228 rs6000_emit_load_toc_table (TRUE);
15230 insn = emit_move_insn (lr, frame_ptr_rtx);
15231 rs6000_maybe_dead (insn);
15232 RTX_FRAME_RELATED_P (insn) = 1;
15235 rs6000_emit_load_toc_table (TRUE);
15239 if (DEFAULT_ABI == ABI_DARWIN
15240 && flag_pic && current_function_uses_pic_offset_table)
15242 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15243 rtx src = machopic_function_base_sym ();
15245 /* Save and restore LR locally around this call (in R0). */
15246 if (!info->lr_save_p)
15247 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
15249 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (src)));
15251 insn = emit_move_insn (gen_rtx_REG (Pmode,
15252 RS6000_PIC_OFFSET_TABLE_REGNUM),
15254 rs6000_maybe_dead (insn);
15256 if (!info->lr_save_p)
15257 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
15262 /* Write function prologue. */
15265 rs6000_output_function_prologue (FILE *file,
15266 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15268 rs6000_stack_t *info = rs6000_stack_info ();
15270 if (TARGET_DEBUG_STACK)
15271 debug_stack_info (info);
15273 /* Write .extern for any function we will call to save and restore
15275 if (info->first_fp_reg_save < 64
15276 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15277 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15278 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15279 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15280 RESTORE_FP_SUFFIX);
15282 /* Write .extern for AIX common mode routines, if needed. */
15283 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15285 fputs ("\t.extern __mulh\n", file);
15286 fputs ("\t.extern __mull\n", file);
15287 fputs ("\t.extern __divss\n", file);
15288 fputs ("\t.extern __divus\n", file);
15289 fputs ("\t.extern __quoss\n", file);
15290 fputs ("\t.extern __quous\n", file);
15291 common_mode_defined = 1;
15294 if (! HAVE_prologue)
15298 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15299 the "toplevel" insn chain. */
15300 emit_note (NOTE_INSN_DELETED);
15301 rs6000_emit_prologue ();
15302 emit_note (NOTE_INSN_DELETED);
15304 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15308 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15310 INSN_ADDRESSES_NEW (insn, addr);
15315 if (TARGET_DEBUG_STACK)
15316 debug_rtx_list (get_insns (), 100);
15317 final (get_insns (), file, FALSE);
15321 rs6000_pic_labelno++;
15324 /* Emit function epilogue as insns.
15326 At present, dwarf2out_frame_debug_expr doesn't understand
15327 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15328 anywhere in the epilogue. Most of the insns below would in any case
15329 need special notes to explain where r11 is in relation to the stack. */
15332 rs6000_emit_epilogue (int sibcall)
15334 rs6000_stack_t *info;
15335 int restoring_FPRs_inline;
15336 int using_load_multiple;
15337 int using_mtcr_multiple;
15338 int use_backchain_to_restore_sp;
15340 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15341 rtx frame_reg_rtx = sp_reg_rtx;
15342 enum machine_mode reg_mode = Pmode;
15343 int reg_size = TARGET_32BIT ? 4 : 8;
15346 info = rs6000_stack_info ();
15348 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15350 reg_mode = V2SImode;
15354 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15355 && (!TARGET_SPE_ABI
15356 || info->spe_64bit_regs_used == 0)
15357 && info->first_gp_reg_save < 31
15358 && no_global_regs_above (info->first_gp_reg_save));
15359 restoring_FPRs_inline = (sibcall
15360 || current_function_calls_eh_return
15361 || info->first_fp_reg_save == 64
15362 || FP_SAVE_INLINE (info->first_fp_reg_save));
15363 use_backchain_to_restore_sp = (frame_pointer_needed
15364 || current_function_calls_alloca
15365 || info->total_size > 32767);
15366 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15367 || rs6000_cpu == PROCESSOR_PPC603
15368 || rs6000_cpu == PROCESSOR_PPC750
15371 if (WORLD_SAVE_P (info))
15375 const char *alloc_rname;
15378 /* eh_rest_world_r10 will return to the location saved in the LR
15379 stack slot (which is not likely to be our caller.)
15380 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15381 rest_world is similar, except any R10 parameter is ignored.
15382 The exception-handling stuff that was here in 2.95 is no
15383 longer necessary. */
15387 + 32 - info->first_gp_reg_save
15388 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15389 + 63 + 1 - info->first_fp_reg_save);
15391 strcpy (rname, ((current_function_calls_eh_return) ?
15392 "*eh_rest_world_r10" : "*rest_world"));
15393 alloc_rname = ggc_strdup (rname);
15396 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15397 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15398 gen_rtx_REG (Pmode,
15399 LINK_REGISTER_REGNUM));
15401 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15402 /* The instruction pattern requires a clobber here;
15403 it is shared with the restVEC helper. */
15405 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15408 /* CR register traditionally saved as CR2. */
15409 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15410 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15411 GEN_INT (info->cr_save_offset));
15412 rtx mem = gen_frame_mem (reg_mode, addr);
15414 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15417 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15419 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15420 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15421 GEN_INT (info->gp_save_offset
15423 rtx mem = gen_frame_mem (reg_mode, addr);
15425 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15427 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15429 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15430 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15431 GEN_INT (info->altivec_save_offset
15433 rtx mem = gen_frame_mem (V4SImode, addr);
15435 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15437 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15439 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15440 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15441 GEN_INT (info->fp_save_offset
15443 rtx mem = gen_frame_mem (DFmode, addr);
15445 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15448 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15450 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15452 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15454 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15456 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15457 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15462 /* Set sp_offset based on the stack push from the prologue. */
15463 if (info->total_size < 32767)
15464 sp_offset = info->total_size;
15466 /* Restore AltiVec registers if needed. */
15467 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15471 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15472 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15474 rtx addr, areg, mem;
15476 areg = gen_rtx_REG (Pmode, 0);
15478 (areg, GEN_INT (info->altivec_save_offset
15480 + 16 * (i - info->first_altivec_reg_save)));
15482 /* AltiVec addressing mode is [reg+reg]. */
15483 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15484 mem = gen_frame_mem (V4SImode, addr);
15486 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15490 /* Restore VRSAVE if needed. */
15491 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15492 && info->vrsave_mask != 0)
15494 rtx addr, mem, reg;
15496 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15497 GEN_INT (info->vrsave_save_offset + sp_offset));
15498 mem = gen_frame_mem (SImode, addr);
15499 reg = gen_rtx_REG (SImode, 12);
15500 emit_move_insn (reg, mem);
15502 emit_insn (generate_set_vrsave (reg, info, 1));
15507 /* If we have a frame pointer, a call to alloca, or a large stack
15508 frame, restore the old stack pointer using the backchain. Otherwise,
15509 we know what size to update it with. */
15510 if (use_backchain_to_restore_sp)
15512 /* Under V.4, don't reset the stack pointer until after we're done
15513 loading the saved registers. */
15514 if (DEFAULT_ABI == ABI_V4)
15515 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15517 emit_move_insn (frame_reg_rtx,
15518 gen_rtx_MEM (Pmode, sp_reg_rtx));
15520 else if (info->push_p)
15522 if (DEFAULT_ABI == ABI_V4
15523 || current_function_calls_eh_return)
15524 sp_offset = info->total_size;
15527 emit_insn (TARGET_32BIT
15528 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15529 GEN_INT (info->total_size))
15530 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15531 GEN_INT (info->total_size)));
15535 /* Get the old lr if we saved it. */
15536 if (info->lr_save_p)
15538 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15539 info->lr_save_offset + sp_offset);
15541 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15544 /* Get the old cr if we saved it. */
15545 if (info->cr_save_p)
15547 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15548 GEN_INT (info->cr_save_offset + sp_offset));
15549 rtx mem = gen_frame_mem (SImode, addr);
15551 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15554 /* Set LR here to try to overlap restores below. */
15555 if (info->lr_save_p)
15556 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
15557 gen_rtx_REG (Pmode, 0));
15559 /* Load exception handler data registers, if needed. */
15560 if (current_function_calls_eh_return)
15562 unsigned int i, regno;
15566 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15567 GEN_INT (sp_offset + 5 * reg_size));
15568 rtx mem = gen_frame_mem (reg_mode, addr);
15570 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15577 regno = EH_RETURN_DATA_REGNO (i);
15578 if (regno == INVALID_REGNUM)
15581 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15582 info->ehrd_offset + sp_offset
15583 + reg_size * (int) i);
15585 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15589 /* Restore GPRs. This is done as a PARALLEL if we are using
15590 the load-multiple instructions. */
15591 if (using_load_multiple)
15594 p = rtvec_alloc (32 - info->first_gp_reg_save);
15595 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15597 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15598 GEN_INT (info->gp_save_offset
15601 rtx mem = gen_frame_mem (reg_mode, addr);
15604 gen_rtx_SET (VOIDmode,
15605 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15608 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15610 else if (TARGET_SPE_ABI
15611 && info->spe_64bit_regs_used != 0
15612 && info->first_gp_reg_save != 32)
15614 rtx spe_save_area_ptr;
15615 /* Determine whether we can address all of the registers that need
15616 to be saved with an offset from the stack pointer that fits in
15617 the small const field for SPE memory instructions. */
15618 int spe_regs_addressable_via_sp
15619 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15620 + (32 - info->first_gp_reg_save - 1) * reg_size);
15623 if (spe_regs_addressable_via_sp)
15625 spe_save_area_ptr = frame_reg_rtx;
15626 spe_offset = info->spe_gp_save_offset + sp_offset;
15630 /* Make r11 point to the start of the SPE save area. We worried about
15631 not clobbering it when we were saving registers in the prolgoue.
15632 There's no need to worry here because the static chain is passed
15633 anew to every function. */
15634 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15636 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15637 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15642 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15643 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15645 rtx offset, addr, mem;
15647 /* We're doing all this to ensure that the immediate offset
15648 fits into the immediate field of 'evldd'. */
15649 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
15651 offset = GEN_INT (spe_offset + reg_size * i);
15652 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15653 mem = gen_rtx_MEM (V2SImode, addr);
15655 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15660 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15661 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15663 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15664 GEN_INT (info->gp_save_offset
15667 rtx mem = gen_frame_mem (reg_mode, addr);
15669 emit_move_insn (gen_rtx_REG (reg_mode,
15670 info->first_gp_reg_save + i), mem);
15673 /* Restore fpr's if we need to do it without calling a function. */
15674 if (restoring_FPRs_inline)
15675 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15676 if ((regs_ever_live[info->first_fp_reg_save+i]
15677 && ! call_used_regs[info->first_fp_reg_save+i]))
15680 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15681 GEN_INT (info->fp_save_offset
15684 mem = gen_frame_mem (DFmode, addr);
15686 emit_move_insn (gen_rtx_REG (DFmode,
15687 info->first_fp_reg_save + i),
15691 /* If we saved cr, restore it here. Just those that were used. */
15692 if (info->cr_save_p)
15694 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15697 if (using_mtcr_multiple)
15699 for (i = 0; i < 8; i++)
15700 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15702 gcc_assert (count);
15705 if (using_mtcr_multiple && count > 1)
15710 p = rtvec_alloc (count);
15713 for (i = 0; i < 8; i++)
15714 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15716 rtvec r = rtvec_alloc (2);
15717 RTVEC_ELT (r, 0) = r12_rtx;
15718 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15719 RTVEC_ELT (p, ndx) =
15720 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15721 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15724 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15725 gcc_assert (ndx == count);
15728 for (i = 0; i < 8; i++)
15729 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15731 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15737 /* If this is V.4, unwind the stack pointer after all of the loads
15739 if (frame_reg_rtx != sp_reg_rtx)
15741 /* This blockage is needed so that sched doesn't decide to move
15742 the sp change before the register restores. */
15743 rs6000_emit_stack_tie ();
15745 && info->spe_64bit_regs_used != 0
15746 && info->first_gp_reg_save != 32)
15747 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
15748 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
15750 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15752 else if (sp_offset != 0)
15753 emit_insn (TARGET_32BIT
15754 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15755 GEN_INT (sp_offset))
15756 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15757 GEN_INT (sp_offset)));
15759 if (current_function_calls_eh_return)
15761 rtx sa = EH_RETURN_STACKADJ_RTX;
15762 emit_insn (TARGET_32BIT
15763 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15764 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15770 if (! restoring_FPRs_inline)
15771 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15773 p = rtvec_alloc (2);
15775 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15776 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15777 gen_rtx_REG (Pmode,
15778 LINK_REGISTER_REGNUM));
15780 /* If we have to restore more than two FP registers, branch to the
15781 restore function. It will return to our caller. */
15782 if (! restoring_FPRs_inline)
15786 const char *alloc_rname;
15788 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15789 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15790 alloc_rname = ggc_strdup (rname);
15791 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15792 gen_rtx_SYMBOL_REF (Pmode,
15795 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15798 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15799 GEN_INT (info->fp_save_offset + 8*i));
15800 mem = gen_frame_mem (DFmode, addr);
15802 RTVEC_ELT (p, i+3) =
15803 gen_rtx_SET (VOIDmode,
15804 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15809 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15813 /* Write function epilogue. */
15816 rs6000_output_function_epilogue (FILE *file,
15817 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15819 if (! HAVE_epilogue)
15821 rtx insn = get_last_insn ();
15822 /* If the last insn was a BARRIER, we don't have to write anything except
15823 the trace table. */
15824 if (GET_CODE (insn) == NOTE)
15825 insn = prev_nonnote_insn (insn);
15826 if (insn == 0 || GET_CODE (insn) != BARRIER)
15828 /* This is slightly ugly, but at least we don't have two
15829 copies of the epilogue-emitting code. */
15832 /* A NOTE_INSN_DELETED is supposed to be at the start
15833 and end of the "toplevel" insn chain. */
15834 emit_note (NOTE_INSN_DELETED);
15835 rs6000_emit_epilogue (FALSE);
15836 emit_note (NOTE_INSN_DELETED);
15838 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15842 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15844 INSN_ADDRESSES_NEW (insn, addr);
15849 if (TARGET_DEBUG_STACK)
15850 debug_rtx_list (get_insns (), 100);
15851 final (get_insns (), file, FALSE);
15857 macho_branch_islands ();
15858 /* Mach-O doesn't support labels at the end of objects, so if
15859 it looks like we might want one, insert a NOP. */
15861 rtx insn = get_last_insn ();
15864 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
15865 insn = PREV_INSN (insn);
15869 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
15870 fputs ("\tnop\n", file);
15874 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15877 We don't output a traceback table if -finhibit-size-directive was
15878 used. The documentation for -finhibit-size-directive reads
15879 ``don't output a @code{.size} assembler directive, or anything
15880 else that would cause trouble if the function is split in the
15881 middle, and the two halves are placed at locations far apart in
15882 memory.'' The traceback table has this property, since it
15883 includes the offset from the start of the function to the
15884 traceback table itself.
15886 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15887 different traceback table. */
15888 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15889 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15891 const char *fname = NULL;
15892 const char *language_string = lang_hooks.name;
15893 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15895 int optional_tbtab;
15896 rs6000_stack_t *info = rs6000_stack_info ();
15898 if (rs6000_traceback == traceback_full)
15899 optional_tbtab = 1;
15900 else if (rs6000_traceback == traceback_part)
15901 optional_tbtab = 0;
15903 optional_tbtab = !optimize_size && !TARGET_ELF;
15905 if (optional_tbtab)
15907 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15908 while (*fname == '.') /* V.4 encodes . in the name */
15911 /* Need label immediately before tbtab, so we can compute
15912 its offset from the function start. */
15913 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15914 ASM_OUTPUT_LABEL (file, fname);
15917 /* The .tbtab pseudo-op can only be used for the first eight
15918 expressions, since it can't handle the possibly variable
15919 length fields that follow. However, if you omit the optional
15920 fields, the assembler outputs zeros for all optional fields
15921 anyways, giving each variable length field is minimum length
15922 (as defined in sys/debug.h). Thus we can not use the .tbtab
15923 pseudo-op at all. */
15925 /* An all-zero word flags the start of the tbtab, for debuggers
15926 that have to find it by searching forward from the entry
15927 point or from the current pc. */
15928 fputs ("\t.long 0\n", file);
15930 /* Tbtab format type. Use format type 0. */
15931 fputs ("\t.byte 0,", file);
15933 /* Language type. Unfortunately, there does not seem to be any
15934 official way to discover the language being compiled, so we
15935 use language_string.
15936 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15937 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15938 a number, so for now use 9. */
15939 if (! strcmp (language_string, "GNU C"))
15941 else if (! strcmp (language_string, "GNU F77")
15942 || ! strcmp (language_string, "GNU F95"))
15944 else if (! strcmp (language_string, "GNU Pascal"))
15946 else if (! strcmp (language_string, "GNU Ada"))
15948 else if (! strcmp (language_string, "GNU C++")
15949 || ! strcmp (language_string, "GNU Objective-C++"))
15951 else if (! strcmp (language_string, "GNU Java"))
15953 else if (! strcmp (language_string, "GNU Objective-C"))
15956 gcc_unreachable ();
15957 fprintf (file, "%d,", i);
15959 /* 8 single bit fields: global linkage (not set for C extern linkage,
15960 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15961 from start of procedure stored in tbtab, internal function, function
15962 has controlled storage, function has no toc, function uses fp,
15963 function logs/aborts fp operations. */
15964 /* Assume that fp operations are used if any fp reg must be saved. */
15965 fprintf (file, "%d,",
15966 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15968 /* 6 bitfields: function is interrupt handler, name present in
15969 proc table, function calls alloca, on condition directives
15970 (controls stack walks, 3 bits), saves condition reg, saves
15972 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15973 set up as a frame pointer, even when there is no alloca call. */
15974 fprintf (file, "%d,",
15975 ((optional_tbtab << 6)
15976 | ((optional_tbtab & frame_pointer_needed) << 5)
15977 | (info->cr_save_p << 1)
15978 | (info->lr_save_p)));
15980 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15982 fprintf (file, "%d,",
15983 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15985 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15986 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15988 if (optional_tbtab)
15990 /* Compute the parameter info from the function decl argument
15993 int next_parm_info_bit = 31;
15995 for (decl = DECL_ARGUMENTS (current_function_decl);
15996 decl; decl = TREE_CHAIN (decl))
15998 rtx parameter = DECL_INCOMING_RTL (decl);
15999 enum machine_mode mode = GET_MODE (parameter);
16001 if (GET_CODE (parameter) == REG)
16003 if (SCALAR_FLOAT_MODE_P (mode))
16023 gcc_unreachable ();
16026 /* If only one bit will fit, don't or in this entry. */
16027 if (next_parm_info_bit > 0)
16028 parm_info |= (bits << (next_parm_info_bit - 1));
16029 next_parm_info_bit -= 2;
16033 fixed_parms += ((GET_MODE_SIZE (mode)
16034 + (UNITS_PER_WORD - 1))
16036 next_parm_info_bit -= 1;
16042 /* Number of fixed point parameters. */
16043 /* This is actually the number of words of fixed point parameters; thus
16044 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16045 fprintf (file, "%d,", fixed_parms);
16047 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16049 /* This is actually the number of fp registers that hold parameters;
16050 and thus the maximum value is 13. */
16051 /* Set parameters on stack bit if parameters are not in their original
16052 registers, regardless of whether they are on the stack? Xlc
16053 seems to set the bit when not optimizing. */
16054 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16056 if (! optional_tbtab)
16059 /* Optional fields follow. Some are variable length. */
16061 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16062 11 double float. */
16063 /* There is an entry for each parameter in a register, in the order that
16064 they occur in the parameter list. Any intervening arguments on the
16065 stack are ignored. If the list overflows a long (max possible length
16066 34 bits) then completely leave off all elements that don't fit. */
16067 /* Only emit this long if there was at least one parameter. */
16068 if (fixed_parms || float_parms)
16069 fprintf (file, "\t.long %d\n", parm_info);
16071 /* Offset from start of code to tb table. */
16072 fputs ("\t.long ", file);
16073 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16075 RS6000_OUTPUT_BASENAME (file, fname);
16077 assemble_name (file, fname);
16079 rs6000_output_function_entry (file, fname);
16082 /* Interrupt handler mask. */
16083 /* Omit this long, since we never set the interrupt handler bit
16086 /* Number of CTL (controlled storage) anchors. */
16087 /* Omit this long, since the has_ctl bit is never set above. */
16089 /* Displacement into stack of each CTL anchor. */
16090 /* Omit this list of longs, because there are no CTL anchors. */
16092 /* Length of function name. */
16095 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16097 /* Function name. */
16098 assemble_string (fname, strlen (fname));
16100 /* Register for alloca automatic storage; this is always reg 31.
16101 Only emit this if the alloca bit was set above. */
16102 if (frame_pointer_needed)
16103 fputs ("\t.byte 31\n", file);
16105 fputs ("\t.align 2\n", file);
16109 /* A C compound statement that outputs the assembler code for a thunk
16110 function, used to implement C++ virtual function calls with
16111 multiple inheritance. The thunk acts as a wrapper around a virtual
16112 function, adjusting the implicit object parameter before handing
16113 control off to the real function.
16115 First, emit code to add the integer DELTA to the location that
16116 contains the incoming first argument. Assume that this argument
16117 contains a pointer, and is the one used to pass the `this' pointer
16118 in C++. This is the incoming argument *before* the function
16119 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16120 values of all other incoming arguments.
16122 After the addition, emit code to jump to FUNCTION, which is a
16123 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16124 not touch the return address. Hence returning from FUNCTION will
16125 return to whoever called the current `thunk'.
16127 The effect must be as if FUNCTION had been called directly with the
16128 adjusted first argument. This macro is responsible for emitting
16129 all of the code for a thunk function; output_function_prologue()
16130 and output_function_epilogue() are not invoked.
16132 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16133 been extracted from it.) It might possibly be useful on some
16134 targets, but probably not.
16136 If you do not define this macro, the target-independent code in the
16137 C++ frontend will generate a less efficient heavyweight thunk that
16138 calls FUNCTION instead of jumping to it. The generic approach does
16139 not support varargs. */
16142 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16143 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16146 rtx this, insn, funexp;
16148 reload_completed = 1;
16149 epilogue_completed = 1;
16150 no_new_pseudos = 1;
16152 /* Mark the end of the (empty) prologue. */
16153 emit_note (NOTE_INSN_PROLOGUE_END);
16155 /* Find the "this" pointer. If the function returns a structure,
16156 the structure return pointer is in r3. */
16157 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16158 this = gen_rtx_REG (Pmode, 4);
16160 this = gen_rtx_REG (Pmode, 3);
16162 /* Apply the constant offset, if required. */
16165 rtx delta_rtx = GEN_INT (delta);
16166 emit_insn (TARGET_32BIT
16167 ? gen_addsi3 (this, this, delta_rtx)
16168 : gen_adddi3 (this, this, delta_rtx));
16171 /* Apply the offset from the vtable, if required. */
16174 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16175 rtx tmp = gen_rtx_REG (Pmode, 12);
16177 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16178 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16180 emit_insn (TARGET_32BIT
16181 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16182 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16183 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16187 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16189 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16191 emit_insn (TARGET_32BIT
16192 ? gen_addsi3 (this, this, tmp)
16193 : gen_adddi3 (this, this, tmp));
16196 /* Generate a tail call to the target function. */
16197 if (!TREE_USED (function))
16199 assemble_external (function);
16200 TREE_USED (function) = 1;
16202 funexp = XEXP (DECL_RTL (function), 0);
16203 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16206 if (MACHOPIC_INDIRECT)
16207 funexp = machopic_indirect_call_target (funexp);
16210 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16211 generate sibcall RTL explicitly. */
16212 insn = emit_call_insn (
16213 gen_rtx_PARALLEL (VOIDmode,
16215 gen_rtx_CALL (VOIDmode,
16216 funexp, const0_rtx),
16217 gen_rtx_USE (VOIDmode, const0_rtx),
16218 gen_rtx_USE (VOIDmode,
16219 gen_rtx_REG (SImode,
16220 LINK_REGISTER_REGNUM)),
16221 gen_rtx_RETURN (VOIDmode))));
16222 SIBLING_CALL_P (insn) = 1;
16225 /* Run just enough of rest_of_compilation to get the insns emitted.
16226 There's not really enough bulk here to make other passes such as
16227 instruction scheduling worth while. Note that use_thunk calls
16228 assemble_start_function and assemble_end_function. */
16229 insn = get_insns ();
16230 insn_locators_alloc ();
16231 shorten_branches (insn);
16232 final_start_function (insn, file, 1);
16233 final (insn, file, 1);
16234 final_end_function ();
16236 reload_completed = 0;
16237 epilogue_completed = 0;
16238 no_new_pseudos = 0;
16241 /* A quick summary of the various types of 'constant-pool tables'
16244 Target Flags Name One table per
16245 AIX (none) AIX TOC object file
16246 AIX -mfull-toc AIX TOC object file
16247 AIX -mminimal-toc AIX minimal TOC translation unit
16248 SVR4/EABI (none) SVR4 SDATA object file
16249 SVR4/EABI -fpic SVR4 pic object file
16250 SVR4/EABI -fPIC SVR4 PIC translation unit
16251 SVR4/EABI -mrelocatable EABI TOC function
16252 SVR4/EABI -maix AIX TOC object file
16253 SVR4/EABI -maix -mminimal-toc
16254 AIX minimal TOC translation unit
16256 Name Reg. Set by entries contains:
16257 made by addrs? fp? sum?
16259 AIX TOC 2 crt0 as Y option option
16260 AIX minimal TOC 30 prolog gcc Y Y option
16261 SVR4 SDATA 13 crt0 gcc N Y N
16262 SVR4 pic 30 prolog ld Y not yet N
16263 SVR4 PIC 30 prolog gcc Y option option
16264 EABI TOC 30 prolog gcc Y option option
16268 /* Hash functions for the hash table. */
16271 rs6000_hash_constant (rtx k)
16273 enum rtx_code code = GET_CODE (k);
16274 enum machine_mode mode = GET_MODE (k);
16275 unsigned result = (code << 3) ^ mode;
16276 const char *format;
16279 format = GET_RTX_FORMAT (code);
16280 flen = strlen (format);
16286 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16289 if (mode != VOIDmode)
16290 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16302 for (; fidx < flen; fidx++)
16303 switch (format[fidx])
16308 const char *str = XSTR (k, fidx);
16309 len = strlen (str);
16310 result = result * 613 + len;
16311 for (i = 0; i < len; i++)
16312 result = result * 613 + (unsigned) str[i];
16317 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16321 result = result * 613 + (unsigned) XINT (k, fidx);
16324 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16325 result = result * 613 + (unsigned) XWINT (k, fidx);
16329 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16330 result = result * 613 + (unsigned) (XWINT (k, fidx)
16337 gcc_unreachable ();
16344 toc_hash_function (const void *hash_entry)
16346 const struct toc_hash_struct *thc =
16347 (const struct toc_hash_struct *) hash_entry;
16348 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16351 /* Compare H1 and H2 for equivalence. */
16354 toc_hash_eq (const void *h1, const void *h2)
16356 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16357 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16359 if (((const struct toc_hash_struct *) h1)->key_mode
16360 != ((const struct toc_hash_struct *) h2)->key_mode)
16363 return rtx_equal_p (r1, r2);
16366 /* These are the names given by the C++ front-end to vtables, and
16367 vtable-like objects. Ideally, this logic should not be here;
16368 instead, there should be some programmatic way of inquiring as
16369 to whether or not an object is a vtable. */
16371 #define VTABLE_NAME_P(NAME) \
16372 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16373 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16374 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16375 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16376 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16379 rs6000_output_symbol_ref (FILE *file, rtx x)
16381 /* Currently C++ toc references to vtables can be emitted before it
16382 is decided whether the vtable is public or private. If this is
16383 the case, then the linker will eventually complain that there is
16384 a reference to an unknown section. Thus, for vtables only,
16385 we emit the TOC reference to reference the symbol and not the
16387 const char *name = XSTR (x, 0);
16389 if (VTABLE_NAME_P (name))
16391 RS6000_OUTPUT_BASENAME (file, name);
16394 assemble_name (file, name);
16397 /* Output a TOC entry. We derive the entry name from what is being
16401 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16404 const char *name = buf;
16405 const char *real_name;
16407 HOST_WIDE_INT offset = 0;
16409 gcc_assert (!TARGET_NO_TOC);
16411 /* When the linker won't eliminate them, don't output duplicate
16412 TOC entries (this happens on AIX if there is any kind of TOC,
16413 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16415 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16417 struct toc_hash_struct *h;
16420 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16421 time because GGC is not initialized at that point. */
16422 if (toc_hash_table == NULL)
16423 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16424 toc_hash_eq, NULL);
16426 h = ggc_alloc (sizeof (*h));
16428 h->key_mode = mode;
16429 h->labelno = labelno;
16431 found = htab_find_slot (toc_hash_table, h, 1);
16432 if (*found == NULL)
16434 else /* This is indeed a duplicate.
16435 Set this label equal to that label. */
16437 fputs ("\t.set ", file);
16438 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16439 fprintf (file, "%d,", labelno);
16440 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16441 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16447 /* If we're going to put a double constant in the TOC, make sure it's
16448 aligned properly when strict alignment is on. */
16449 if (GET_CODE (x) == CONST_DOUBLE
16450 && STRICT_ALIGNMENT
16451 && GET_MODE_BITSIZE (mode) >= 64
16452 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16453 ASM_OUTPUT_ALIGN (file, 3);
16456 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16458 /* Handle FP constants specially. Note that if we have a minimal
16459 TOC, things we put here aren't actually in the TOC, so we can allow
16461 if (GET_CODE (x) == CONST_DOUBLE &&
16462 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16464 REAL_VALUE_TYPE rv;
16467 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16468 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16469 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16471 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16475 if (TARGET_MINIMAL_TOC)
16476 fputs (DOUBLE_INT_ASM_OP, file);
16478 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16479 k[0] & 0xffffffff, k[1] & 0xffffffff,
16480 k[2] & 0xffffffff, k[3] & 0xffffffff);
16481 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16482 k[0] & 0xffffffff, k[1] & 0xffffffff,
16483 k[2] & 0xffffffff, k[3] & 0xffffffff);
16488 if (TARGET_MINIMAL_TOC)
16489 fputs ("\t.long ", file);
16491 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16492 k[0] & 0xffffffff, k[1] & 0xffffffff,
16493 k[2] & 0xffffffff, k[3] & 0xffffffff);
16494 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16495 k[0] & 0xffffffff, k[1] & 0xffffffff,
16496 k[2] & 0xffffffff, k[3] & 0xffffffff);
16500 else if (GET_CODE (x) == CONST_DOUBLE &&
16501 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16503 REAL_VALUE_TYPE rv;
16506 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16508 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16509 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16511 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16515 if (TARGET_MINIMAL_TOC)
16516 fputs (DOUBLE_INT_ASM_OP, file);
16518 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16519 k[0] & 0xffffffff, k[1] & 0xffffffff);
16520 fprintf (file, "0x%lx%08lx\n",
16521 k[0] & 0xffffffff, k[1] & 0xffffffff);
16526 if (TARGET_MINIMAL_TOC)
16527 fputs ("\t.long ", file);
16529 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16530 k[0] & 0xffffffff, k[1] & 0xffffffff);
16531 fprintf (file, "0x%lx,0x%lx\n",
16532 k[0] & 0xffffffff, k[1] & 0xffffffff);
16536 else if (GET_CODE (x) == CONST_DOUBLE &&
16537 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16539 REAL_VALUE_TYPE rv;
16542 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16543 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16544 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16546 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16550 if (TARGET_MINIMAL_TOC)
16551 fputs (DOUBLE_INT_ASM_OP, file);
16553 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16554 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16559 if (TARGET_MINIMAL_TOC)
16560 fputs ("\t.long ", file);
16562 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16563 fprintf (file, "0x%lx\n", l & 0xffffffff);
16567 else if (GET_MODE (x) == VOIDmode
16568 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16570 unsigned HOST_WIDE_INT low;
16571 HOST_WIDE_INT high;
16573 if (GET_CODE (x) == CONST_DOUBLE)
16575 low = CONST_DOUBLE_LOW (x);
16576 high = CONST_DOUBLE_HIGH (x);
16579 #if HOST_BITS_PER_WIDE_INT == 32
16582 high = (low & 0x80000000) ? ~0 : 0;
16586 low = INTVAL (x) & 0xffffffff;
16587 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16591 /* TOC entries are always Pmode-sized, but since this
16592 is a bigendian machine then if we're putting smaller
16593 integer constants in the TOC we have to pad them.
16594 (This is still a win over putting the constants in
16595 a separate constant pool, because then we'd have
16596 to have both a TOC entry _and_ the actual constant.)
16598 For a 32-bit target, CONST_INT values are loaded and shifted
16599 entirely within `low' and can be stored in one TOC entry. */
16601 /* It would be easy to make this work, but it doesn't now. */
16602 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16604 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16606 #if HOST_BITS_PER_WIDE_INT == 32
16607 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16608 POINTER_SIZE, &low, &high, 0);
16611 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16612 high = (HOST_WIDE_INT) low >> 32;
16619 if (TARGET_MINIMAL_TOC)
16620 fputs (DOUBLE_INT_ASM_OP, file);
16622 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16623 (long) high & 0xffffffff, (long) low & 0xffffffff);
16624 fprintf (file, "0x%lx%08lx\n",
16625 (long) high & 0xffffffff, (long) low & 0xffffffff);
16630 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16632 if (TARGET_MINIMAL_TOC)
16633 fputs ("\t.long ", file);
16635 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16636 (long) high & 0xffffffff, (long) low & 0xffffffff);
16637 fprintf (file, "0x%lx,0x%lx\n",
16638 (long) high & 0xffffffff, (long) low & 0xffffffff);
16642 if (TARGET_MINIMAL_TOC)
16643 fputs ("\t.long ", file);
16645 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16646 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16652 if (GET_CODE (x) == CONST)
16654 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16656 base = XEXP (XEXP (x, 0), 0);
16657 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16660 switch (GET_CODE (base))
16663 name = XSTR (base, 0);
16667 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16668 CODE_LABEL_NUMBER (XEXP (base, 0)));
16672 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16676 gcc_unreachable ();
16679 real_name = (*targetm.strip_name_encoding) (name);
16680 if (TARGET_MINIMAL_TOC)
16681 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16684 fprintf (file, "\t.tc %s", real_name);
16687 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16689 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16691 fputs ("[TC],", file);
16694 /* Currently C++ toc references to vtables can be emitted before it
16695 is decided whether the vtable is public or private. If this is
16696 the case, then the linker will eventually complain that there is
16697 a TOC reference to an unknown section. Thus, for vtables only,
16698 we emit the TOC reference to reference the symbol and not the
16700 if (VTABLE_NAME_P (name))
16702 RS6000_OUTPUT_BASENAME (file, name);
16704 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16705 else if (offset > 0)
16706 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16709 output_addr_const (file, x);
16713 /* Output an assembler pseudo-op to write an ASCII string of N characters
16714 starting at P to FILE.
16716 On the RS/6000, we have to do this using the .byte operation and
16717 write out special characters outside the quoted string.
16718 Also, the assembler is broken; very long strings are truncated,
16719 so we must artificially break them up early. */
16722 output_ascii (FILE *file, const char *p, int n)
16725 int i, count_string;
16726 const char *for_string = "\t.byte \"";
16727 const char *for_decimal = "\t.byte ";
16728 const char *to_close = NULL;
16731 for (i = 0; i < n; i++)
16734 if (c >= ' ' && c < 0177)
16737 fputs (for_string, file);
16740 /* Write two quotes to get one. */
16748 for_decimal = "\"\n\t.byte ";
16752 if (count_string >= 512)
16754 fputs (to_close, file);
16756 for_string = "\t.byte \"";
16757 for_decimal = "\t.byte ";
16765 fputs (for_decimal, file);
16766 fprintf (file, "%d", c);
16768 for_string = "\n\t.byte \"";
16769 for_decimal = ", ";
16775 /* Now close the string if we have written one. Then end the line. */
16777 fputs (to_close, file);
16780 /* Generate a unique section name for FILENAME for a section type
16781 represented by SECTION_DESC. Output goes into BUF.
16783 SECTION_DESC can be any string, as long as it is different for each
16784 possible section type.
16786 We name the section in the same manner as xlc. The name begins with an
16787 underscore followed by the filename (after stripping any leading directory
16788 names) with the last period replaced by the string SECTION_DESC. If
16789 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16793 rs6000_gen_section_name (char **buf, const char *filename,
16794 const char *section_desc)
16796 const char *q, *after_last_slash, *last_period = 0;
16800 after_last_slash = filename;
16801 for (q = filename; *q; q++)
16804 after_last_slash = q + 1;
16805 else if (*q == '.')
16809 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16810 *buf = (char *) xmalloc (len);
16815 for (q = after_last_slash; *q; q++)
16817 if (q == last_period)
16819 strcpy (p, section_desc);
16820 p += strlen (section_desc);
16824 else if (ISALNUM (*q))
16828 if (last_period == 0)
16829 strcpy (p, section_desc);
16834 /* Emit profile function. */
16837 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16839 /* Non-standard profiling for kernels, which just saves LR then calls
16840 _mcount without worrying about arg saves. The idea is to change
16841 the function prologue as little as possible as it isn't easy to
16842 account for arg save/restore code added just for _mcount. */
16843 if (TARGET_PROFILE_KERNEL)
16846 if (DEFAULT_ABI == ABI_AIX)
16848 #ifndef NO_PROFILE_COUNTERS
16849 # define NO_PROFILE_COUNTERS 0
16851 if (NO_PROFILE_COUNTERS)
16852 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16856 const char *label_name;
16859 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16860 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16861 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16863 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16867 else if (DEFAULT_ABI == ABI_DARWIN)
16869 const char *mcount_name = RS6000_MCOUNT;
16870 int caller_addr_regno = LINK_REGISTER_REGNUM;
16872 /* Be conservative and always set this, at least for now. */
16873 current_function_uses_pic_offset_table = 1;
16876 /* For PIC code, set up a stub and collect the caller's address
16877 from r0, which is where the prologue puts it. */
16878 if (MACHOPIC_INDIRECT
16879 && current_function_uses_pic_offset_table)
16880 caller_addr_regno = 0;
16882 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16884 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16888 /* Write function profiler code. */
16891 output_function_profiler (FILE *file, int labelno)
16895 switch (DEFAULT_ABI)
16898 gcc_unreachable ();
16903 warning (0, "no profiling of 64-bit code for this ABI");
16906 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16907 fprintf (file, "\tmflr %s\n", reg_names[0]);
16908 if (NO_PROFILE_COUNTERS)
16910 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16911 reg_names[0], reg_names[1]);
16913 else if (TARGET_SECURE_PLT && flag_pic)
16915 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16916 reg_names[0], reg_names[1]);
16917 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16918 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16919 reg_names[12], reg_names[12]);
16920 assemble_name (file, buf);
16921 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16922 assemble_name (file, buf);
16923 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16925 else if (flag_pic == 1)
16927 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16928 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16929 reg_names[0], reg_names[1]);
16930 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16931 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16932 assemble_name (file, buf);
16933 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16935 else if (flag_pic > 1)
16937 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16938 reg_names[0], reg_names[1]);
16939 /* Now, we need to get the address of the label. */
16940 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16941 assemble_name (file, buf);
16942 fputs ("-.\n1:", file);
16943 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16944 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16945 reg_names[0], reg_names[11]);
16946 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16947 reg_names[0], reg_names[0], reg_names[11]);
16951 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16952 assemble_name (file, buf);
16953 fputs ("@ha\n", file);
16954 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16955 reg_names[0], reg_names[1]);
16956 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16957 assemble_name (file, buf);
16958 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16961 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16962 fprintf (file, "\tbl %s%s\n",
16963 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16968 if (!TARGET_PROFILE_KERNEL)
16970 /* Don't do anything, done in output_profile_hook (). */
16974 gcc_assert (!TARGET_32BIT);
16976 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16977 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16979 if (cfun->static_chain_decl != NULL)
16981 asm_fprintf (file, "\tstd %s,24(%s)\n",
16982 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16983 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16984 asm_fprintf (file, "\tld %s,24(%s)\n",
16985 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16988 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16996 /* The following variable value is the last issued insn. */
16998 static rtx last_scheduled_insn;
17000 /* The following variable helps to balance issuing of load and
17001 store instructions */
17003 static int load_store_pendulum;
17005 /* Power4 load update and store update instructions are cracked into a
17006 load or store and an integer insn which are executed in the same cycle.
17007 Branches have their own dispatch slot which does not count against the
17008 GCC issue rate, but it changes the program flow so there are no other
17009 instructions to issue in this cycle. */
17012 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17013 int verbose ATTRIBUTE_UNUSED,
17014 rtx insn, int more)
17016 last_scheduled_insn = insn;
17017 if (GET_CODE (PATTERN (insn)) == USE
17018 || GET_CODE (PATTERN (insn)) == CLOBBER)
17020 cached_can_issue_more = more;
17021 return cached_can_issue_more;
17024 if (insn_terminates_group_p (insn, current_group))
17026 cached_can_issue_more = 0;
17027 return cached_can_issue_more;
17030 /* If no reservation, but reach here */
17031 if (recog_memoized (insn) < 0)
17034 if (rs6000_sched_groups)
17036 if (is_microcoded_insn (insn))
17037 cached_can_issue_more = 0;
17038 else if (is_cracked_insn (insn))
17039 cached_can_issue_more = more > 2 ? more - 2 : 0;
17041 cached_can_issue_more = more - 1;
17043 return cached_can_issue_more;
17046 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17049 cached_can_issue_more = more - 1;
17050 return cached_can_issue_more;
17053 /* Adjust the cost of a scheduling dependency. Return the new cost of
17054 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17057 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17059 enum attr_type attr_type;
17061 if (! recog_memoized (insn))
17064 switch (REG_NOTE_KIND (link))
17068 /* Data dependency; DEP_INSN writes a register that INSN reads
17069 some cycles later. */
17071 /* Separate a load from a narrower, dependent store. */
17072 if (rs6000_sched_groups
17073 && GET_CODE (PATTERN (insn)) == SET
17074 && GET_CODE (PATTERN (dep_insn)) == SET
17075 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17076 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17077 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17078 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17081 attr_type = get_attr_type (insn);
17086 /* Tell the first scheduling pass about the latency between
17087 a mtctr and bctr (and mtlr and br/blr). The first
17088 scheduling pass will not know about this latency since
17089 the mtctr instruction, which has the latency associated
17090 to it, will be generated by reload. */
17091 return TARGET_POWER ? 5 : 4;
17093 /* Leave some extra cycles between a compare and its
17094 dependent branch, to inhibit expensive mispredicts. */
17095 if ((rs6000_cpu_attr == CPU_PPC603
17096 || rs6000_cpu_attr == CPU_PPC604
17097 || rs6000_cpu_attr == CPU_PPC604E
17098 || rs6000_cpu_attr == CPU_PPC620
17099 || rs6000_cpu_attr == CPU_PPC630
17100 || rs6000_cpu_attr == CPU_PPC750
17101 || rs6000_cpu_attr == CPU_PPC7400
17102 || rs6000_cpu_attr == CPU_PPC7450
17103 || rs6000_cpu_attr == CPU_POWER4
17104 || rs6000_cpu_attr == CPU_POWER5
17105 || rs6000_cpu_attr == CPU_CELL)
17106 && recog_memoized (dep_insn)
17107 && (INSN_CODE (dep_insn) >= 0))
17109 switch (get_attr_type (dep_insn))
17113 case TYPE_DELAYED_COMPARE:
17114 case TYPE_IMUL_COMPARE:
17115 case TYPE_LMUL_COMPARE:
17116 case TYPE_FPCOMPARE:
17117 case TYPE_CR_LOGICAL:
17118 case TYPE_DELAYED_CR:
17127 case TYPE_STORE_UX:
17129 case TYPE_FPSTORE_U:
17130 case TYPE_FPSTORE_UX:
17131 if ((rs6000_cpu == PROCESSOR_POWER6)
17132 && recog_memoized (dep_insn)
17133 && (INSN_CODE (dep_insn) >= 0))
17136 if (GET_CODE (PATTERN (insn)) != SET)
17137 /* If this happens, we have to extend this to schedule
17138 optimally. Return default for now. */
17141 /* Adjust the cost for the case where the value written
17142 by a fixed point operation is used as the address
17143 gen value on a store. */
17144 switch (get_attr_type (dep_insn))
17151 if (! store_data_bypass_p (dep_insn, insn))
17155 case TYPE_LOAD_EXT:
17156 case TYPE_LOAD_EXT_U:
17157 case TYPE_LOAD_EXT_UX:
17158 case TYPE_VAR_SHIFT_ROTATE:
17159 case TYPE_VAR_DELAYED_COMPARE:
17161 if (! store_data_bypass_p (dep_insn, insn))
17167 case TYPE_FAST_COMPARE:
17170 case TYPE_INSERT_WORD:
17171 case TYPE_INSERT_DWORD:
17172 case TYPE_FPLOAD_U:
17173 case TYPE_FPLOAD_UX:
17175 case TYPE_STORE_UX:
17176 case TYPE_FPSTORE_U:
17177 case TYPE_FPSTORE_UX:
17179 if (! store_data_bypass_p (dep_insn, insn))
17187 case TYPE_IMUL_COMPARE:
17188 case TYPE_LMUL_COMPARE:
17190 if (! store_data_bypass_p (dep_insn, insn))
17196 if (! store_data_bypass_p (dep_insn, insn))
17202 if (! store_data_bypass_p (dep_insn, insn))
17215 case TYPE_LOAD_EXT:
17216 case TYPE_LOAD_EXT_U:
17217 case TYPE_LOAD_EXT_UX:
17218 if ((rs6000_cpu == PROCESSOR_POWER6)
17219 && recog_memoized (dep_insn)
17220 && (INSN_CODE (dep_insn) >= 0))
17223 /* Adjust the cost for the case where the value written
17224 by a fixed point instruction is used within the address
17225 gen portion of a subsequent load(u)(x) */
17226 switch (get_attr_type (dep_insn))
17233 if (set_to_load_agen (dep_insn, insn))
17237 case TYPE_LOAD_EXT:
17238 case TYPE_LOAD_EXT_U:
17239 case TYPE_LOAD_EXT_UX:
17240 case TYPE_VAR_SHIFT_ROTATE:
17241 case TYPE_VAR_DELAYED_COMPARE:
17243 if (set_to_load_agen (dep_insn, insn))
17249 case TYPE_FAST_COMPARE:
17252 case TYPE_INSERT_WORD:
17253 case TYPE_INSERT_DWORD:
17254 case TYPE_FPLOAD_U:
17255 case TYPE_FPLOAD_UX:
17257 case TYPE_STORE_UX:
17258 case TYPE_FPSTORE_U:
17259 case TYPE_FPSTORE_UX:
17261 if (set_to_load_agen (dep_insn, insn))
17269 case TYPE_IMUL_COMPARE:
17270 case TYPE_LMUL_COMPARE:
17272 if (set_to_load_agen (dep_insn, insn))
17278 if (set_to_load_agen (dep_insn, insn))
17284 if (set_to_load_agen (dep_insn, insn))
17295 if ((rs6000_cpu == PROCESSOR_POWER6)
17296 && recog_memoized (dep_insn)
17297 && (INSN_CODE (dep_insn) >= 0)
17298 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17305 /* Fall out to return default cost. */
17309 case REG_DEP_OUTPUT:
17310 /* Output dependency; DEP_INSN writes a register that INSN writes some
17312 if ((rs6000_cpu == PROCESSOR_POWER6)
17313 && recog_memoized (dep_insn)
17314 && (INSN_CODE (dep_insn) >= 0))
17316 attr_type = get_attr_type (insn);
17321 if (get_attr_type (dep_insn) == TYPE_FP)
17325 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17333 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17338 gcc_unreachable ();
17344 /* The function returns a true if INSN is microcoded.
17345 Return false otherwise. */
17348 is_microcoded_insn (rtx insn)
17350 if (!insn || !INSN_P (insn)
17351 || GET_CODE (PATTERN (insn)) == USE
17352 || GET_CODE (PATTERN (insn)) == CLOBBER)
17355 if (rs6000_cpu_attr == CPU_CELL)
17356 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17358 if (rs6000_sched_groups)
17360 enum attr_type type = get_attr_type (insn);
17361 if (type == TYPE_LOAD_EXT_U
17362 || type == TYPE_LOAD_EXT_UX
17363 || type == TYPE_LOAD_UX
17364 || type == TYPE_STORE_UX
17365 || type == TYPE_MFCR)
17372 /* The function returns true if INSN is cracked into 2 instructions
17373 by the processor (and therefore occupies 2 issue slots). */
17376 is_cracked_insn (rtx insn)
17378 if (!insn || !INSN_P (insn)
17379 || GET_CODE (PATTERN (insn)) == USE
17380 || GET_CODE (PATTERN (insn)) == CLOBBER)
17383 if (rs6000_sched_groups)
17385 enum attr_type type = get_attr_type (insn);
17386 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17387 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17388 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17389 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17390 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17391 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17392 || type == TYPE_IDIV || type == TYPE_LDIV
17393 || type == TYPE_INSERT_WORD)
17400 /* The function returns true if INSN can be issued only from
17401 the branch slot. */
17404 is_branch_slot_insn (rtx insn)
17406 if (!insn || !INSN_P (insn)
17407 || GET_CODE (PATTERN (insn)) == USE
17408 || GET_CODE (PATTERN (insn)) == CLOBBER)
17411 if (rs6000_sched_groups)
17413 enum attr_type type = get_attr_type (insn);
17414 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17422 /* The function returns true if out_inst sets a value that is
17423 used in the address generation computation of in_insn */
17425 set_to_load_agen (rtx out_insn, rtx in_insn)
17427 rtx out_set, in_set;
17429 /* For performance reasons, only handle the simple case where
17430 both loads are a single_set. */
17431 out_set = single_set (out_insn);
17434 in_set = single_set (in_insn);
17436 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17442 /* The function returns true if the target storage location of
17443 out_insn is adjacent to the target storage location of in_insn */
17444 /* Return 1 if memory locations are adjacent. */
17447 adjacent_mem_locations (rtx insn1, rtx insn2)
17450 rtx a = get_store_dest (PATTERN (insn1));
17451 rtx b = get_store_dest (PATTERN (insn2));
17453 if ((GET_CODE (XEXP (a, 0)) == REG
17454 || (GET_CODE (XEXP (a, 0)) == PLUS
17455 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17456 && (GET_CODE (XEXP (b, 0)) == REG
17457 || (GET_CODE (XEXP (b, 0)) == PLUS
17458 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17460 HOST_WIDE_INT val0 = 0, val1 = 0;
17464 if (GET_CODE (XEXP (a, 0)) == PLUS)
17466 reg0 = XEXP (XEXP (a, 0), 0);
17467 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17470 reg0 = XEXP (a, 0);
17472 if (GET_CODE (XEXP (b, 0)) == PLUS)
17474 reg1 = XEXP (XEXP (b, 0), 0);
17475 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17478 reg1 = XEXP (b, 0);
17480 val_diff = val1 - val0;
17482 return ((REGNO (reg0) == REGNO (reg1))
17483 && (val_diff == INTVAL (MEM_SIZE (a))
17484 || val_diff == -INTVAL (MEM_SIZE (b))));
17490 /* A C statement (sans semicolon) to update the integer scheduling
17491 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17492 INSN earlier, reduce the priority to execute INSN later. Do not
17493 define this macro if you do not need to adjust the scheduling
17494 priorities of insns. */
17497 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17499 /* On machines (like the 750) which have asymmetric integer units,
17500 where one integer unit can do multiply and divides and the other
17501 can't, reduce the priority of multiply/divide so it is scheduled
17502 before other integer operations. */
17505 if (! INSN_P (insn))
17508 if (GET_CODE (PATTERN (insn)) == USE)
17511 switch (rs6000_cpu_attr) {
17513 switch (get_attr_type (insn))
17520 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17521 priority, priority);
17522 if (priority >= 0 && priority < 0x01000000)
17529 if (insn_must_be_first_in_group (insn)
17530 && reload_completed
17531 && current_sched_info->sched_max_insns_priority
17532 && rs6000_sched_restricted_insns_priority)
17535 /* Prioritize insns that can be dispatched only in the first
17537 if (rs6000_sched_restricted_insns_priority == 1)
17538 /* Attach highest priority to insn. This means that in
17539 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17540 precede 'priority' (critical path) considerations. */
17541 return current_sched_info->sched_max_insns_priority;
17542 else if (rs6000_sched_restricted_insns_priority == 2)
17543 /* Increase priority of insn by a minimal amount. This means that in
17544 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17545 considerations precede dispatch-slot restriction considerations. */
17546 return (priority + 1);
17549 if (rs6000_cpu == PROCESSOR_POWER6
17550 && ((load_store_pendulum == -2 && is_load_insn (insn))
17551 || (load_store_pendulum == 2 && is_store_insn (insn))))
17552 /* Attach highest priority to insn if the scheduler has just issued two
17553 stores and this instruction is a load, or two loads and this instruction
17554 is a store. Power6 wants loads and stores scheduled alternately
17556 return current_sched_info->sched_max_insns_priority;
17561 /* Return true if the instruction is nonpipelined on the Cell. */
17563 is_nonpipeline_insn (rtx insn)
17565 enum attr_type type;
17566 if (!insn || !INSN_P (insn)
17567 || GET_CODE (PATTERN (insn)) == USE
17568 || GET_CODE (PATTERN (insn)) == CLOBBER)
17571 type = get_attr_type (insn);
17572 if (type == TYPE_IMUL
17573 || type == TYPE_IMUL2
17574 || type == TYPE_IMUL3
17575 || type == TYPE_LMUL
17576 || type == TYPE_IDIV
17577 || type == TYPE_LDIV
17578 || type == TYPE_SDIV
17579 || type == TYPE_DDIV
17580 || type == TYPE_SSQRT
17581 || type == TYPE_DSQRT
17582 || type == TYPE_MFCR
17583 || type == TYPE_MFCRF
17584 || type == TYPE_MFJMPR)
17592 /* Return how many instructions the machine can issue per cycle. */
17595 rs6000_issue_rate (void)
17597 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17598 if (!reload_completed)
17601 switch (rs6000_cpu_attr) {
17602 case CPU_RIOS1: /* ? */
17604 case CPU_PPC601: /* ? */
17629 /* Return how many instructions to look ahead for better insn
17633 rs6000_use_sched_lookahead (void)
17635 if (rs6000_cpu_attr == CPU_PPC8540)
17637 if (rs6000_cpu_attr == CPU_CELL)
17638 return (reload_completed ? 8 : 0);
17642 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17644 rs6000_use_sched_lookahead_guard (rtx insn)
17646 if (rs6000_cpu_attr != CPU_CELL)
17649 if (insn == NULL_RTX || !INSN_P (insn))
17652 if (!reload_completed
17653 || is_nonpipeline_insn (insn)
17654 || is_microcoded_insn (insn))
17660 /* Determine is PAT refers to memory. */
17663 is_mem_ref (rtx pat)
17669 if (GET_CODE (pat) == MEM)
17672 /* Recursively process the pattern. */
17673 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17675 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17678 ret |= is_mem_ref (XEXP (pat, i));
17679 else if (fmt[i] == 'E')
17680 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17681 ret |= is_mem_ref (XVECEXP (pat, i, j));
17687 /* Determine if PAT is a PATTERN of a load insn. */
17690 is_load_insn1 (rtx pat)
17692 if (!pat || pat == NULL_RTX)
17695 if (GET_CODE (pat) == SET)
17696 return is_mem_ref (SET_SRC (pat));
17698 if (GET_CODE (pat) == PARALLEL)
17702 for (i = 0; i < XVECLEN (pat, 0); i++)
17703 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17710 /* Determine if INSN loads from memory. */
17713 is_load_insn (rtx insn)
17715 if (!insn || !INSN_P (insn))
17718 if (GET_CODE (insn) == CALL_INSN)
17721 return is_load_insn1 (PATTERN (insn));
17724 /* Determine if PAT is a PATTERN of a store insn. */
17727 is_store_insn1 (rtx pat)
17729 if (!pat || pat == NULL_RTX)
17732 if (GET_CODE (pat) == SET)
17733 return is_mem_ref (SET_DEST (pat));
17735 if (GET_CODE (pat) == PARALLEL)
17739 for (i = 0; i < XVECLEN (pat, 0); i++)
17740 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17747 /* Determine if INSN stores to memory. */
17750 is_store_insn (rtx insn)
17752 if (!insn || !INSN_P (insn))
17755 return is_store_insn1 (PATTERN (insn));
17758 /* Return the dest of a store insn. */
17761 get_store_dest (rtx pat)
17763 gcc_assert (is_store_insn1 (pat));
17765 if (GET_CODE (pat) == SET)
17766 return SET_DEST (pat);
17767 else if (GET_CODE (pat) == PARALLEL)
17771 for (i = 0; i < XVECLEN (pat, 0); i++)
17773 rtx inner_pat = XVECEXP (pat, 0, i);
17774 if (GET_CODE (inner_pat) == SET
17775 && is_mem_ref (SET_DEST (inner_pat)))
17779 /* We shouldn't get here, because we should have either a simple
17780 store insn or a store with update which are covered above. */
17784 /* Returns whether the dependence between INSN and NEXT is considered
17785 costly by the given target. */
17788 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17793 /* If the flag is not enabled - no dependence is considered costly;
17794 allow all dependent insns in the same group.
17795 This is the most aggressive option. */
17796 if (rs6000_sched_costly_dep == no_dep_costly)
17799 /* If the flag is set to 1 - a dependence is always considered costly;
17800 do not allow dependent instructions in the same group.
17801 This is the most conservative option. */
17802 if (rs6000_sched_costly_dep == all_deps_costly)
17805 insn = DEP_PRO (dep);
17806 next = DEP_CON (dep);
17808 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17809 && is_load_insn (next)
17810 && is_store_insn (insn))
17811 /* Prevent load after store in the same group. */
17814 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17815 && is_load_insn (next)
17816 && is_store_insn (insn)
17817 && DEP_KIND (dep) == REG_DEP_TRUE)
17818 /* Prevent load after store in the same group if it is a true
17822 /* The flag is set to X; dependences with latency >= X are considered costly,
17823 and will not be scheduled in the same group. */
17824 if (rs6000_sched_costly_dep <= max_dep_latency
17825 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17831 /* Return the next insn after INSN that is found before TAIL is reached,
17832 skipping any "non-active" insns - insns that will not actually occupy
17833 an issue slot. Return NULL_RTX if such an insn is not found. */
17836 get_next_active_insn (rtx insn, rtx tail)
17838 if (insn == NULL_RTX || insn == tail)
17843 insn = NEXT_INSN (insn);
17844 if (insn == NULL_RTX || insn == tail)
17849 || (NONJUMP_INSN_P (insn)
17850 && GET_CODE (PATTERN (insn)) != USE
17851 && GET_CODE (PATTERN (insn)) != CLOBBER
17852 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17858 /* We are about to begin issuing insns for this clock cycle. */
17861 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17862 rtx *ready ATTRIBUTE_UNUSED,
17863 int *pn_ready ATTRIBUTE_UNUSED,
17864 int clock_var ATTRIBUTE_UNUSED)
17866 int n_ready = *pn_ready;
17869 fprintf (dump, "// rs6000_sched_reorder :\n");
17871 /* Reorder the ready list, if the second to last ready insn
17872 is a nonepipeline insn. */
17873 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
17875 if (is_nonpipeline_insn (ready[n_ready - 1])
17876 && (recog_memoized (ready[n_ready - 2]) > 0))
17877 /* Simply swap first two insns. */
17879 rtx tmp = ready[n_ready - 1];
17880 ready[n_ready - 1] = ready[n_ready - 2];
17881 ready[n_ready - 2] = tmp;
17885 if (rs6000_cpu == PROCESSOR_POWER6)
17886 load_store_pendulum = 0;
17888 return rs6000_issue_rate ();
17891 /* Like rs6000_sched_reorder, but called after issuing each insn. */
17894 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
17895 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
17898 fprintf (dump, "// rs6000_sched_reorder2 :\n");
17900 /* For Power6, we need to handle some special cases to try and keep the
17901 store queue from overflowing and triggering expensive flushes.
17903 This code monitors how load and store instructions are being issued
17904 and skews the ready list one way or the other to increase the likelihood
17905 that a desired instruction is issued at the proper time.
17907 A couple of things are done. First, we maintain a "load_store_pendulum"
17908 to track the current state of load/store issue.
17910 - If the pendulum is at zero, then no loads or stores have been
17911 issued in the current cycle so we do nothing.
17913 - If the pendulum is 1, then a single load has been issued in this
17914 cycle and we attempt to locate another load in the ready list to
17917 - If the pendulum is -2, then two stores have already been
17918 issued in this cycle, so we increase the priority of the first load
17919 in the ready list to increase it's likelihood of being chosen first
17922 - If the pendulum is -1, then a single store has been issued in this
17923 cycle and we attempt to locate another store in the ready list to
17924 issue with it, preferring a store to an adjacent memory location to
17925 facilitate store pairing in the store queue.
17927 - If the pendulum is 2, then two loads have already been
17928 issued in this cycle, so we increase the priority of the first store
17929 in the ready list to increase it's likelihood of being chosen first
17932 - If the pendulum < -2 or > 2, then do nothing.
17934 Note: This code covers the most common scenarios. There exist non
17935 load/store instructions which make use of the LSU and which
17936 would need to be accounted for to strictly model the behavior
17937 of the machine. Those instructions are currently unaccounted
17938 for to help minimize compile time overhead of this code.
17940 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
17946 if (is_store_insn (last_scheduled_insn))
17947 /* Issuing a store, swing the load_store_pendulum to the left */
17948 load_store_pendulum--;
17949 else if (is_load_insn (last_scheduled_insn))
17950 /* Issuing a load, swing the load_store_pendulum to the right */
17951 load_store_pendulum++;
17953 return cached_can_issue_more;
17955 /* If the pendulum is balanced, or there is only one instruction on
17956 the ready list, then all is well, so return. */
17957 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
17958 return cached_can_issue_more;
17960 if (load_store_pendulum == 1)
17962 /* A load has been issued in this cycle. Scan the ready list
17963 for another load to issue with it */
17968 if (is_load_insn (ready[pos]))
17970 /* Found a load. Move it to the head of the ready list,
17971 and adjust it's priority so that it is more likely to
17974 for (i=pos; i<*pn_ready-1; i++)
17975 ready[i] = ready[i + 1];
17976 ready[*pn_ready-1] = tmp;
17977 if INSN_PRIORITY_KNOWN (tmp)
17978 INSN_PRIORITY (tmp)++;
17984 else if (load_store_pendulum == -2)
17986 /* Two stores have been issued in this cycle. Increase the
17987 priority of the first load in the ready list to favor it for
17988 issuing in the next cycle. */
17993 if (is_load_insn (ready[pos])
17994 && INSN_PRIORITY_KNOWN (ready[pos]))
17996 INSN_PRIORITY (ready[pos])++;
17998 /* Adjust the pendulum to account for the fact that a load
17999 was found and increased in priority. This is to prevent
18000 increasing the priority of multiple loads */
18001 load_store_pendulum--;
18008 else if (load_store_pendulum == -1)
18010 /* A store has been issued in this cycle. Scan the ready list for
18011 another store to issue with it, preferring a store to an adjacent
18013 int first_store_pos = -1;
18019 if (is_store_insn (ready[pos]))
18021 /* Maintain the index of the first store found on the
18023 if (first_store_pos == -1)
18024 first_store_pos = pos;
18026 if (is_store_insn (last_scheduled_insn)
18027 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18029 /* Found an adjacent store. Move it to the head of the
18030 ready list, and adjust it's priority so that it is
18031 more likely to stay there */
18033 for (i=pos; i<*pn_ready-1; i++)
18034 ready[i] = ready[i + 1];
18035 ready[*pn_ready-1] = tmp;
18036 if INSN_PRIORITY_KNOWN (tmp)
18037 INSN_PRIORITY (tmp)++;
18038 first_store_pos = -1;
18046 if (first_store_pos >= 0)
18048 /* An adjacent store wasn't found, but a non-adjacent store was,
18049 so move the non-adjacent store to the front of the ready
18050 list, and adjust its priority so that it is more likely to
18052 tmp = ready[first_store_pos];
18053 for (i=first_store_pos; i<*pn_ready-1; i++)
18054 ready[i] = ready[i + 1];
18055 ready[*pn_ready-1] = tmp;
18056 if INSN_PRIORITY_KNOWN (tmp)
18057 INSN_PRIORITY (tmp)++;
18060 else if (load_store_pendulum == 2)
18062 /* Two loads have been issued in this cycle. Increase the priority
18063 of the first store in the ready list to favor it for issuing in
18069 if (is_store_insn (ready[pos])
18070 && INSN_PRIORITY_KNOWN (ready[pos]))
18072 INSN_PRIORITY (ready[pos])++;
18074 /* Adjust the pendulum to account for the fact that a store
18075 was found and increased in priority. This is to prevent
18076 increasing the priority of multiple stores */
18077 load_store_pendulum++;
18086 return cached_can_issue_more;
18089 /* Return whether the presence of INSN causes a dispatch group termination
18090 of group WHICH_GROUP.
18092 If WHICH_GROUP == current_group, this function will return true if INSN
18093 causes the termination of the current group (i.e, the dispatch group to
18094 which INSN belongs). This means that INSN will be the last insn in the
18095 group it belongs to.
18097 If WHICH_GROUP == previous_group, this function will return true if INSN
18098 causes the termination of the previous group (i.e, the dispatch group that
18099 precedes the group to which INSN belongs). This means that INSN will be
18100 the first insn in the group it belongs to). */
18103 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18110 first = insn_must_be_first_in_group (insn);
18111 last = insn_must_be_last_in_group (insn);
18116 if (which_group == current_group)
18118 else if (which_group == previous_group)
18126 insn_must_be_first_in_group (rtx insn)
18128 enum attr_type type;
18131 || insn == NULL_RTX
18132 || GET_CODE (insn) == NOTE
18133 || GET_CODE (PATTERN (insn)) == USE
18134 || GET_CODE (PATTERN (insn)) == CLOBBER)
18137 switch (rs6000_cpu)
18139 case PROCESSOR_POWER5:
18140 if (is_cracked_insn (insn))
18142 case PROCESSOR_POWER4:
18143 if (is_microcoded_insn (insn))
18146 if (!rs6000_sched_groups)
18149 type = get_attr_type (insn);
18156 case TYPE_DELAYED_CR:
18157 case TYPE_CR_LOGICAL:
18171 case PROCESSOR_POWER6:
18172 type = get_attr_type (insn);
18176 case TYPE_INSERT_DWORD:
18180 case TYPE_VAR_SHIFT_ROTATE:
18187 case TYPE_INSERT_WORD:
18188 case TYPE_DELAYED_COMPARE:
18189 case TYPE_IMUL_COMPARE:
18190 case TYPE_LMUL_COMPARE:
18191 case TYPE_FPCOMPARE:
18202 case TYPE_LOAD_EXT_UX:
18204 case TYPE_STORE_UX:
18205 case TYPE_FPLOAD_U:
18206 case TYPE_FPLOAD_UX:
18207 case TYPE_FPSTORE_U:
18208 case TYPE_FPSTORE_UX:
18222 insn_must_be_last_in_group (rtx insn)
18224 enum attr_type type;
18227 || insn == NULL_RTX
18228 || GET_CODE (insn) == NOTE
18229 || GET_CODE (PATTERN (insn)) == USE
18230 || GET_CODE (PATTERN (insn)) == CLOBBER)
18233 switch (rs6000_cpu) {
18234 case PROCESSOR_POWER4:
18235 case PROCESSOR_POWER5:
18236 if (is_microcoded_insn (insn))
18239 if (is_branch_slot_insn (insn))
18243 case PROCESSOR_POWER6:
18244 type = get_attr_type (insn);
18251 case TYPE_VAR_SHIFT_ROTATE:
18258 case TYPE_DELAYED_COMPARE:
18259 case TYPE_IMUL_COMPARE:
18260 case TYPE_LMUL_COMPARE:
18261 case TYPE_FPCOMPARE:
18282 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18283 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18286 is_costly_group (rtx *group_insns, rtx next_insn)
18289 int issue_rate = rs6000_issue_rate ();
18291 for (i = 0; i < issue_rate; i++)
18294 rtx insn = group_insns[i];
18299 FOR_EACH_DEP_LINK (link, INSN_FORW_DEPS (insn))
18301 dep_t dep = DEP_LINK_DEP (link);
18302 rtx next = DEP_CON (dep);
18304 if (next == next_insn
18305 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18313 /* Utility of the function redefine_groups.
18314 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18315 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18316 to keep it "far" (in a separate group) from GROUP_INSNS, following
18317 one of the following schemes, depending on the value of the flag
18318 -minsert_sched_nops = X:
18319 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18320 in order to force NEXT_INSN into a separate group.
18321 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18322 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18323 insertion (has a group just ended, how many vacant issue slots remain in the
18324 last group, and how many dispatch groups were encountered so far). */
18327 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18328 rtx next_insn, bool *group_end, int can_issue_more,
18333 int issue_rate = rs6000_issue_rate ();
18334 bool end = *group_end;
18337 if (next_insn == NULL_RTX)
18338 return can_issue_more;
18340 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18341 return can_issue_more;
18343 force = is_costly_group (group_insns, next_insn);
18345 return can_issue_more;
18347 if (sched_verbose > 6)
18348 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18349 *group_count ,can_issue_more);
18351 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18354 can_issue_more = 0;
18356 /* Since only a branch can be issued in the last issue_slot, it is
18357 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18358 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18359 in this case the last nop will start a new group and the branch
18360 will be forced to the new group. */
18361 if (can_issue_more && !is_branch_slot_insn (next_insn))
18364 while (can_issue_more > 0)
18367 emit_insn_before (nop, next_insn);
18375 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18377 int n_nops = rs6000_sched_insert_nops;
18379 /* Nops can't be issued from the branch slot, so the effective
18380 issue_rate for nops is 'issue_rate - 1'. */
18381 if (can_issue_more == 0)
18382 can_issue_more = issue_rate;
18384 if (can_issue_more == 0)
18386 can_issue_more = issue_rate - 1;
18389 for (i = 0; i < issue_rate; i++)
18391 group_insns[i] = 0;
18398 emit_insn_before (nop, next_insn);
18399 if (can_issue_more == issue_rate - 1) /* new group begins */
18402 if (can_issue_more == 0)
18404 can_issue_more = issue_rate - 1;
18407 for (i = 0; i < issue_rate; i++)
18409 group_insns[i] = 0;
18415 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18418 /* Is next_insn going to start a new group? */
18421 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18422 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18423 || (can_issue_more < issue_rate &&
18424 insn_terminates_group_p (next_insn, previous_group)));
18425 if (*group_end && end)
18428 if (sched_verbose > 6)
18429 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18430 *group_count, can_issue_more);
18431 return can_issue_more;
18434 return can_issue_more;
18437 /* This function tries to synch the dispatch groups that the compiler "sees"
18438 with the dispatch groups that the processor dispatcher is expected to
18439 form in practice. It tries to achieve this synchronization by forcing the
18440 estimated processor grouping on the compiler (as opposed to the function
18441 'pad_goups' which tries to force the scheduler's grouping on the processor).
18443 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18444 examines the (estimated) dispatch groups that will be formed by the processor
18445 dispatcher. It marks these group boundaries to reflect the estimated
18446 processor grouping, overriding the grouping that the scheduler had marked.
18447 Depending on the value of the flag '-minsert-sched-nops' this function can
18448 force certain insns into separate groups or force a certain distance between
18449 them by inserting nops, for example, if there exists a "costly dependence"
18452 The function estimates the group boundaries that the processor will form as
18453 follows: It keeps track of how many vacant issue slots are available after
18454 each insn. A subsequent insn will start a new group if one of the following
18456 - no more vacant issue slots remain in the current dispatch group.
18457 - only the last issue slot, which is the branch slot, is vacant, but the next
18458 insn is not a branch.
18459 - only the last 2 or less issue slots, including the branch slot, are vacant,
18460 which means that a cracked insn (which occupies two issue slots) can't be
18461 issued in this group.
18462 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18463 start a new group. */
18466 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18468 rtx insn, next_insn;
18470 int can_issue_more;
18473 int group_count = 0;
18477 issue_rate = rs6000_issue_rate ();
18478 group_insns = alloca (issue_rate * sizeof (rtx));
18479 for (i = 0; i < issue_rate; i++)
18481 group_insns[i] = 0;
18483 can_issue_more = issue_rate;
18485 insn = get_next_active_insn (prev_head_insn, tail);
18488 while (insn != NULL_RTX)
18490 slot = (issue_rate - can_issue_more);
18491 group_insns[slot] = insn;
18493 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18494 if (insn_terminates_group_p (insn, current_group))
18495 can_issue_more = 0;
18497 next_insn = get_next_active_insn (insn, tail);
18498 if (next_insn == NULL_RTX)
18499 return group_count + 1;
18501 /* Is next_insn going to start a new group? */
18503 = (can_issue_more == 0
18504 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18505 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18506 || (can_issue_more < issue_rate &&
18507 insn_terminates_group_p (next_insn, previous_group)));
18509 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18510 next_insn, &group_end, can_issue_more,
18516 can_issue_more = 0;
18517 for (i = 0; i < issue_rate; i++)
18519 group_insns[i] = 0;
18523 if (GET_MODE (next_insn) == TImode && can_issue_more)
18524 PUT_MODE (next_insn, VOIDmode);
18525 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18526 PUT_MODE (next_insn, TImode);
18529 if (can_issue_more == 0)
18530 can_issue_more = issue_rate;
18533 return group_count;
18536 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18537 dispatch group boundaries that the scheduler had marked. Pad with nops
18538 any dispatch groups which have vacant issue slots, in order to force the
18539 scheduler's grouping on the processor dispatcher. The function
18540 returns the number of dispatch groups found. */
18543 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18545 rtx insn, next_insn;
18548 int can_issue_more;
18550 int group_count = 0;
18552 /* Initialize issue_rate. */
18553 issue_rate = rs6000_issue_rate ();
18554 can_issue_more = issue_rate;
18556 insn = get_next_active_insn (prev_head_insn, tail);
18557 next_insn = get_next_active_insn (insn, tail);
18559 while (insn != NULL_RTX)
18562 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18564 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18566 if (next_insn == NULL_RTX)
18571 /* If the scheduler had marked group termination at this location
18572 (between insn and next_indn), and neither insn nor next_insn will
18573 force group termination, pad the group with nops to force group
18576 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18577 && !insn_terminates_group_p (insn, current_group)
18578 && !insn_terminates_group_p (next_insn, previous_group))
18580 if (!is_branch_slot_insn (next_insn))
18583 while (can_issue_more)
18586 emit_insn_before (nop, next_insn);
18591 can_issue_more = issue_rate;
18596 next_insn = get_next_active_insn (insn, tail);
18599 return group_count;
18602 /* We're beginning a new block. Initialize data structures as necessary. */
18605 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18606 int sched_verbose ATTRIBUTE_UNUSED,
18607 int max_ready ATTRIBUTE_UNUSED)
18609 last_scheduled_insn = NULL_RTX;
18610 load_store_pendulum = 0;
18613 /* The following function is called at the end of scheduling BB.
18614 After reload, it inserts nops at insn group bundling. */
18617 rs6000_sched_finish (FILE *dump, int sched_verbose)
18622 fprintf (dump, "=== Finishing schedule.\n");
18624 if (reload_completed && rs6000_sched_groups)
18626 if (rs6000_sched_insert_nops == sched_finish_none)
18629 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18630 n_groups = pad_groups (dump, sched_verbose,
18631 current_sched_info->prev_head,
18632 current_sched_info->next_tail);
18634 n_groups = redefine_groups (dump, sched_verbose,
18635 current_sched_info->prev_head,
18636 current_sched_info->next_tail);
18638 if (sched_verbose >= 6)
18640 fprintf (dump, "ngroups = %d\n", n_groups);
18641 print_rtl (dump, current_sched_info->prev_head);
18642 fprintf (dump, "Done finish_sched\n");
18647 /* Length in units of the trampoline for entering a nested function. */
18650 rs6000_trampoline_size (void)
18654 switch (DEFAULT_ABI)
18657 gcc_unreachable ();
18660 ret = (TARGET_32BIT) ? 12 : 24;
18665 ret = (TARGET_32BIT) ? 40 : 48;
18672 /* Emit RTL insns to initialize the variable parts of a trampoline.
18673 FNADDR is an RTX for the address of the function's pure code.
18674 CXT is an RTX for the static chain value for the function. */
18677 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18679 int regsize = (TARGET_32BIT) ? 4 : 8;
18680 rtx ctx_reg = force_reg (Pmode, cxt);
18682 switch (DEFAULT_ABI)
18685 gcc_unreachable ();
18687 /* Macros to shorten the code expansions below. */
18688 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18689 #define MEM_PLUS(addr,offset) \
18690 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18692 /* Under AIX, just build the 3 word function descriptor */
18695 rtx fn_reg = gen_reg_rtx (Pmode);
18696 rtx toc_reg = gen_reg_rtx (Pmode);
18697 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18698 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18699 emit_move_insn (MEM_DEREF (addr), fn_reg);
18700 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18701 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18705 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18708 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18709 FALSE, VOIDmode, 4,
18711 GEN_INT (rs6000_trampoline_size ()), SImode,
18721 /* Table of valid machine attributes. */
18723 const struct attribute_spec rs6000_attribute_table[] =
18725 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18726 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18727 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18728 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18729 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18730 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18731 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18732 SUBTARGET_ATTRIBUTE_TABLE,
18734 { NULL, 0, 0, false, false, false, NULL }
18737 /* Handle the "altivec" attribute. The attribute may have
18738 arguments as follows:
18740 __attribute__((altivec(vector__)))
18741 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18742 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18744 and may appear more than once (e.g., 'vector bool char') in a
18745 given declaration. */
18748 rs6000_handle_altivec_attribute (tree *node,
18749 tree name ATTRIBUTE_UNUSED,
18751 int flags ATTRIBUTE_UNUSED,
18752 bool *no_add_attrs)
18754 tree type = *node, result = NULL_TREE;
18755 enum machine_mode mode;
18758 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18759 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18760 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18763 while (POINTER_TYPE_P (type)
18764 || TREE_CODE (type) == FUNCTION_TYPE
18765 || TREE_CODE (type) == METHOD_TYPE
18766 || TREE_CODE (type) == ARRAY_TYPE)
18767 type = TREE_TYPE (type);
18769 mode = TYPE_MODE (type);
18771 /* Check for invalid AltiVec type qualifiers. */
18772 if (type == long_unsigned_type_node || type == long_integer_type_node)
18775 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18776 else if (rs6000_warn_altivec_long)
18777 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18779 else if (type == long_long_unsigned_type_node
18780 || type == long_long_integer_type_node)
18781 error ("use of %<long long%> in AltiVec types is invalid");
18782 else if (type == double_type_node)
18783 error ("use of %<double%> in AltiVec types is invalid");
18784 else if (type == long_double_type_node)
18785 error ("use of %<long double%> in AltiVec types is invalid");
18786 else if (type == boolean_type_node)
18787 error ("use of boolean types in AltiVec types is invalid");
18788 else if (TREE_CODE (type) == COMPLEX_TYPE)
18789 error ("use of %<complex%> in AltiVec types is invalid");
18790 else if (DECIMAL_FLOAT_MODE_P (mode))
18791 error ("use of decimal floating point types in AltiVec types is invalid");
18793 switch (altivec_type)
18796 unsigned_p = TYPE_UNSIGNED (type);
18800 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18803 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18806 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18808 case SFmode: result = V4SF_type_node; break;
18809 /* If the user says 'vector int bool', we may be handed the 'bool'
18810 attribute _before_ the 'vector' attribute, and so select the
18811 proper type in the 'b' case below. */
18812 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18820 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18821 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18822 case QImode: case V16QImode: result = bool_V16QI_type_node;
18829 case V8HImode: result = pixel_V8HI_type_node;
18835 if (result && result != type && TYPE_READONLY (type))
18836 result = build_qualified_type (result, TYPE_QUAL_CONST);
18838 *no_add_attrs = true; /* No need to hang on to the attribute. */
18841 *node = reconstruct_complex_type (*node, result);
18846 /* AltiVec defines four built-in scalar types that serve as vector
18847 elements; we must teach the compiler how to mangle them. */
18849 static const char *
18850 rs6000_mangle_fundamental_type (tree type)
18852 if (type == bool_char_type_node) return "U6__boolc";
18853 if (type == bool_short_type_node) return "U6__bools";
18854 if (type == pixel_type_node) return "u7__pixel";
18855 if (type == bool_int_type_node) return "U6__booli";
18857 /* Mangle IBM extended float long double as `g' (__float128) on
18858 powerpc*-linux where long-double-64 previously was the default. */
18859 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
18861 && TARGET_LONG_DOUBLE_128
18862 && !TARGET_IEEEQUAD)
18865 /* For all other types, use normal C++ mangling. */
18869 /* Handle a "longcall" or "shortcall" attribute; arguments as in
18870 struct attribute_spec.handler. */
18873 rs6000_handle_longcall_attribute (tree *node, tree name,
18874 tree args ATTRIBUTE_UNUSED,
18875 int flags ATTRIBUTE_UNUSED,
18876 bool *no_add_attrs)
18878 if (TREE_CODE (*node) != FUNCTION_TYPE
18879 && TREE_CODE (*node) != FIELD_DECL
18880 && TREE_CODE (*node) != TYPE_DECL)
18882 warning (OPT_Wattributes, "%qs attribute only applies to functions",
18883 IDENTIFIER_POINTER (name));
18884 *no_add_attrs = true;
18890 /* Set longcall attributes on all functions declared when
18891 rs6000_default_long_calls is true. */
18893 rs6000_set_default_type_attributes (tree type)
18895 if (rs6000_default_long_calls
18896 && (TREE_CODE (type) == FUNCTION_TYPE
18897 || TREE_CODE (type) == METHOD_TYPE))
18898 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
18900 TYPE_ATTRIBUTES (type));
18903 darwin_set_default_type_attributes (type);
18907 /* Return a reference suitable for calling a function with the
18908 longcall attribute. */
18911 rs6000_longcall_ref (rtx call_ref)
18913 const char *call_name;
18916 if (GET_CODE (call_ref) != SYMBOL_REF)
18919 /* System V adds '.' to the internal name, so skip them. */
18920 call_name = XSTR (call_ref, 0);
18921 if (*call_name == '.')
18923 while (*call_name == '.')
18926 node = get_identifier (call_name);
18927 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
18930 return force_reg (Pmode, call_ref);
18933 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
18934 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
18937 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
18938 struct attribute_spec.handler. */
18940 rs6000_handle_struct_attribute (tree *node, tree name,
18941 tree args ATTRIBUTE_UNUSED,
18942 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
18945 if (DECL_P (*node))
18947 if (TREE_CODE (*node) == TYPE_DECL)
18948 type = &TREE_TYPE (*node);
18953 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
18954 || TREE_CODE (*type) == UNION_TYPE)))
18956 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
18957 *no_add_attrs = true;
18960 else if ((is_attribute_p ("ms_struct", name)
18961 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
18962 || ((is_attribute_p ("gcc_struct", name)
18963 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
18965 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
18966 IDENTIFIER_POINTER (name));
18967 *no_add_attrs = true;
18974 rs6000_ms_bitfield_layout_p (tree record_type)
18976 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
18977 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
18978 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
18981 #ifdef USING_ELFOS_H
18983 /* A get_unnamed_section callback, used for switching to toc_section. */
18986 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18988 if (DEFAULT_ABI == ABI_AIX
18989 && TARGET_MINIMAL_TOC
18990 && !TARGET_RELOCATABLE)
18992 if (!toc_initialized)
18994 toc_initialized = 1;
18995 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18996 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
18997 fprintf (asm_out_file, "\t.tc ");
18998 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
18999 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19000 fprintf (asm_out_file, "\n");
19002 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19003 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19004 fprintf (asm_out_file, " = .+32768\n");
19007 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19009 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19010 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19013 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19014 if (!toc_initialized)
19016 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19017 fprintf (asm_out_file, " = .+32768\n");
19018 toc_initialized = 1;
19023 /* Implement TARGET_ASM_INIT_SECTIONS. */
19026 rs6000_elf_asm_init_sections (void)
19029 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19032 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19033 SDATA2_SECTION_ASM_OP);
19036 /* Implement TARGET_SELECT_RTX_SECTION. */
19039 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19040 unsigned HOST_WIDE_INT align)
19042 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19043 return toc_section;
19045 return default_elf_select_rtx_section (mode, x, align);
19048 /* For a SYMBOL_REF, set generic flags and then perform some
19049 target-specific processing.
19051 When the AIX ABI is requested on a non-AIX system, replace the
19052 function name with the real name (with a leading .) rather than the
19053 function descriptor name. This saves a lot of overriding code to
19054 read the prefixes. */
19057 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19059 default_encode_section_info (decl, rtl, first);
19062 && TREE_CODE (decl) == FUNCTION_DECL
19064 && DEFAULT_ABI == ABI_AIX)
19066 rtx sym_ref = XEXP (rtl, 0);
19067 size_t len = strlen (XSTR (sym_ref, 0));
19068 char *str = alloca (len + 2);
19070 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19071 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19076 rs6000_elf_in_small_data_p (tree decl)
19078 if (rs6000_sdata == SDATA_NONE)
19081 /* We want to merge strings, so we never consider them small data. */
19082 if (TREE_CODE (decl) == STRING_CST)
19085 /* Functions are never in the small data area. */
19086 if (TREE_CODE (decl) == FUNCTION_DECL)
19089 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19091 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19092 if (strcmp (section, ".sdata") == 0
19093 || strcmp (section, ".sdata2") == 0
19094 || strcmp (section, ".sbss") == 0
19095 || strcmp (section, ".sbss2") == 0
19096 || strcmp (section, ".PPC.EMB.sdata0") == 0
19097 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19102 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19105 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19106 /* If it's not public, and we're not going to reference it there,
19107 there's no need to put it in the small data section. */
19108 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19115 #endif /* USING_ELFOS_H */
19117 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19120 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
19122 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19125 /* Return a REG that occurs in ADDR with coefficient 1.
19126 ADDR can be effectively incremented by incrementing REG.
19128 r0 is special and we must not select it as an address
19129 register by this routine since our caller will try to
19130 increment the returned register via an "la" instruction. */
19133 find_addr_reg (rtx addr)
19135 while (GET_CODE (addr) == PLUS)
19137 if (GET_CODE (XEXP (addr, 0)) == REG
19138 && REGNO (XEXP (addr, 0)) != 0)
19139 addr = XEXP (addr, 0);
19140 else if (GET_CODE (XEXP (addr, 1)) == REG
19141 && REGNO (XEXP (addr, 1)) != 0)
19142 addr = XEXP (addr, 1);
19143 else if (CONSTANT_P (XEXP (addr, 0)))
19144 addr = XEXP (addr, 1);
19145 else if (CONSTANT_P (XEXP (addr, 1)))
19146 addr = XEXP (addr, 0);
19148 gcc_unreachable ();
19150 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19155 rs6000_fatal_bad_address (rtx op)
19157 fatal_insn ("bad address", op);
19162 static tree branch_island_list = 0;
19164 /* Remember to generate a branch island for far calls to the given
19168 add_compiler_branch_island (tree label_name, tree function_name,
19171 tree branch_island = build_tree_list (function_name, label_name);
19172 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19173 TREE_CHAIN (branch_island) = branch_island_list;
19174 branch_island_list = branch_island;
19177 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19178 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19179 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19180 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19182 /* Generate far-jump branch islands for everything on the
19183 branch_island_list. Invoked immediately after the last instruction
19184 of the epilogue has been emitted; the branch-islands must be
19185 appended to, and contiguous with, the function body. Mach-O stubs
19186 are generated in machopic_output_stub(). */
19189 macho_branch_islands (void)
19192 tree branch_island;
19194 for (branch_island = branch_island_list;
19196 branch_island = TREE_CHAIN (branch_island))
19198 const char *label =
19199 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19201 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19202 char name_buf[512];
19203 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19204 if (name[0] == '*' || name[0] == '&')
19205 strcpy (name_buf, name+1);
19209 strcpy (name_buf+1, name);
19211 strcpy (tmp_buf, "\n");
19212 strcat (tmp_buf, label);
19213 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19214 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19215 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19216 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19219 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19220 strcat (tmp_buf, label);
19221 strcat (tmp_buf, "_pic\n");
19222 strcat (tmp_buf, label);
19223 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19225 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19226 strcat (tmp_buf, name_buf);
19227 strcat (tmp_buf, " - ");
19228 strcat (tmp_buf, label);
19229 strcat (tmp_buf, "_pic)\n");
19231 strcat (tmp_buf, "\tmtlr r0\n");
19233 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19234 strcat (tmp_buf, name_buf);
19235 strcat (tmp_buf, " - ");
19236 strcat (tmp_buf, label);
19237 strcat (tmp_buf, "_pic)\n");
19239 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19243 strcat (tmp_buf, ":\nlis r12,hi16(");
19244 strcat (tmp_buf, name_buf);
19245 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19246 strcat (tmp_buf, name_buf);
19247 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19249 output_asm_insn (tmp_buf, 0);
19250 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19251 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19252 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19253 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19256 branch_island_list = 0;
19259 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19260 already there or not. */
19263 no_previous_def (tree function_name)
19265 tree branch_island;
19266 for (branch_island = branch_island_list;
19268 branch_island = TREE_CHAIN (branch_island))
19269 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19274 /* GET_PREV_LABEL gets the label name from the previous definition of
19278 get_prev_label (tree function_name)
19280 tree branch_island;
19281 for (branch_island = branch_island_list;
19283 branch_island = TREE_CHAIN (branch_island))
19284 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19285 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19289 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19290 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19293 /* KEXTs still need branch islands. */
19294 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19295 || flag_mkernel || flag_apple_kext)
19297 /* INSN is either a function call or a millicode call. It may have an
19298 unconditional jump in its delay slot.
19300 CALL_DEST is the routine we are calling. */
19303 output_call (rtx insn, rtx *operands, int dest_operand_number,
19304 int cookie_operand_number)
19306 static char buf[256];
19307 if (DARWIN_GENERATE_ISLANDS
19308 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19309 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19312 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19314 if (no_previous_def (funname))
19316 rtx label_rtx = gen_label_rtx ();
19317 char *label_buf, temp_buf[256];
19318 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19319 CODE_LABEL_NUMBER (label_rtx));
19320 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19321 labelname = get_identifier (label_buf);
19322 add_compiler_branch_island (labelname, funname, insn_line (insn));
19325 labelname = get_prev_label (funname);
19327 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19328 instruction will reach 'foo', otherwise link as 'bl L42'".
19329 "L42" should be a 'branch island', that will do a far jump to
19330 'foo'. Branch islands are generated in
19331 macho_branch_islands(). */
19332 sprintf (buf, "jbsr %%z%d,%.246s",
19333 dest_operand_number, IDENTIFIER_POINTER (labelname));
19336 sprintf (buf, "bl %%z%d", dest_operand_number);
19340 /* Generate PIC and indirect symbol stubs. */
19343 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19345 unsigned int length;
19346 char *symbol_name, *lazy_ptr_name;
19347 char *local_label_0;
19348 static int label = 0;
19350 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19351 symb = (*targetm.strip_name_encoding) (symb);
19354 length = strlen (symb);
19355 symbol_name = alloca (length + 32);
19356 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19358 lazy_ptr_name = alloca (length + 32);
19359 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19362 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19364 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19368 fprintf (file, "\t.align 5\n");
19370 fprintf (file, "%s:\n", stub);
19371 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19374 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19375 sprintf (local_label_0, "\"L%011d$spb\"", label);
19377 fprintf (file, "\tmflr r0\n");
19378 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19379 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19380 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19381 lazy_ptr_name, local_label_0);
19382 fprintf (file, "\tmtlr r0\n");
19383 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19384 (TARGET_64BIT ? "ldu" : "lwzu"),
19385 lazy_ptr_name, local_label_0);
19386 fprintf (file, "\tmtctr r12\n");
19387 fprintf (file, "\tbctr\n");
19391 fprintf (file, "\t.align 4\n");
19393 fprintf (file, "%s:\n", stub);
19394 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19396 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19397 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19398 (TARGET_64BIT ? "ldu" : "lwzu"),
19400 fprintf (file, "\tmtctr r12\n");
19401 fprintf (file, "\tbctr\n");
19404 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19405 fprintf (file, "%s:\n", lazy_ptr_name);
19406 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19407 fprintf (file, "%sdyld_stub_binding_helper\n",
19408 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19411 /* Legitimize PIC addresses. If the address is already
19412 position-independent, we return ORIG. Newly generated
19413 position-independent addresses go into a reg. This is REG if non
19414 zero, otherwise we allocate register(s) as necessary. */
19416 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19419 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19424 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19425 reg = gen_reg_rtx (Pmode);
19427 if (GET_CODE (orig) == CONST)
19431 if (GET_CODE (XEXP (orig, 0)) == PLUS
19432 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19435 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19437 /* Use a different reg for the intermediate value, as
19438 it will be marked UNCHANGING. */
19439 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
19440 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19443 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19446 if (GET_CODE (offset) == CONST_INT)
19448 if (SMALL_INT (offset))
19449 return plus_constant (base, INTVAL (offset));
19450 else if (! reload_in_progress && ! reload_completed)
19451 offset = force_reg (Pmode, offset);
19454 rtx mem = force_const_mem (Pmode, orig);
19455 return machopic_legitimize_pic_address (mem, Pmode, reg);
19458 return gen_rtx_PLUS (Pmode, base, offset);
19461 /* Fall back on generic machopic code. */
19462 return machopic_legitimize_pic_address (orig, mode, reg);
19465 /* Output a .machine directive for the Darwin assembler, and call
19466 the generic start_file routine. */
19469 rs6000_darwin_file_start (void)
19471 static const struct
19477 { "ppc64", "ppc64", MASK_64BIT },
19478 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19479 { "power4", "ppc970", 0 },
19480 { "G5", "ppc970", 0 },
19481 { "7450", "ppc7450", 0 },
19482 { "7400", "ppc7400", MASK_ALTIVEC },
19483 { "G4", "ppc7400", 0 },
19484 { "750", "ppc750", 0 },
19485 { "740", "ppc750", 0 },
19486 { "G3", "ppc750", 0 },
19487 { "604e", "ppc604e", 0 },
19488 { "604", "ppc604", 0 },
19489 { "603e", "ppc603", 0 },
19490 { "603", "ppc603", 0 },
19491 { "601", "ppc601", 0 },
19492 { NULL, "ppc", 0 } };
19493 const char *cpu_id = "";
19496 rs6000_file_start ();
19497 darwin_file_start ();
19499 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19500 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19501 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19502 && rs6000_select[i].string[0] != '\0')
19503 cpu_id = rs6000_select[i].string;
19505 /* Look through the mapping array. Pick the first name that either
19506 matches the argument, has a bit set in IF_SET that is also set
19507 in the target flags, or has a NULL name. */
19510 while (mapping[i].arg != NULL
19511 && strcmp (mapping[i].arg, cpu_id) != 0
19512 && (mapping[i].if_set & target_flags) == 0)
19515 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19518 #endif /* TARGET_MACHO */
19522 rs6000_elf_reloc_rw_mask (void)
19526 else if (DEFAULT_ABI == ABI_AIX)
19532 /* Record an element in the table of global constructors. SYMBOL is
19533 a SYMBOL_REF of the function to be called; PRIORITY is a number
19534 between 0 and MAX_INIT_PRIORITY.
19536 This differs from default_named_section_asm_out_constructor in
19537 that we have special handling for -mrelocatable. */
19540 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19542 const char *section = ".ctors";
19545 if (priority != DEFAULT_INIT_PRIORITY)
19547 sprintf (buf, ".ctors.%.5u",
19548 /* Invert the numbering so the linker puts us in the proper
19549 order; constructors are run from right to left, and the
19550 linker sorts in increasing order. */
19551 MAX_INIT_PRIORITY - priority);
19555 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19556 assemble_align (POINTER_SIZE);
19558 if (TARGET_RELOCATABLE)
19560 fputs ("\t.long (", asm_out_file);
19561 output_addr_const (asm_out_file, symbol);
19562 fputs (")@fixup\n", asm_out_file);
19565 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19569 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19571 const char *section = ".dtors";
19574 if (priority != DEFAULT_INIT_PRIORITY)
19576 sprintf (buf, ".dtors.%.5u",
19577 /* Invert the numbering so the linker puts us in the proper
19578 order; constructors are run from right to left, and the
19579 linker sorts in increasing order. */
19580 MAX_INIT_PRIORITY - priority);
19584 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19585 assemble_align (POINTER_SIZE);
19587 if (TARGET_RELOCATABLE)
19589 fputs ("\t.long (", asm_out_file);
19590 output_addr_const (asm_out_file, symbol);
19591 fputs (")@fixup\n", asm_out_file);
19594 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19598 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19602 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19603 ASM_OUTPUT_LABEL (file, name);
19604 fputs (DOUBLE_INT_ASM_OP, file);
19605 rs6000_output_function_entry (file, name);
19606 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19609 fputs ("\t.size\t", file);
19610 assemble_name (file, name);
19611 fputs (",24\n\t.type\t.", file);
19612 assemble_name (file, name);
19613 fputs (",@function\n", file);
19614 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19616 fputs ("\t.globl\t.", file);
19617 assemble_name (file, name);
19622 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19623 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19624 rs6000_output_function_entry (file, name);
19625 fputs (":\n", file);
19629 if (TARGET_RELOCATABLE
19630 && !TARGET_SECURE_PLT
19631 && (get_pool_size () != 0 || current_function_profile)
19636 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19638 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19639 fprintf (file, "\t.long ");
19640 assemble_name (file, buf);
19642 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19643 assemble_name (file, buf);
19647 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19648 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19650 if (DEFAULT_ABI == ABI_AIX)
19652 const char *desc_name, *orig_name;
19654 orig_name = (*targetm.strip_name_encoding) (name);
19655 desc_name = orig_name;
19656 while (*desc_name == '.')
19659 if (TREE_PUBLIC (decl))
19660 fprintf (file, "\t.globl %s\n", desc_name);
19662 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19663 fprintf (file, "%s:\n", desc_name);
19664 fprintf (file, "\t.long %s\n", orig_name);
19665 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19666 if (DEFAULT_ABI == ABI_AIX)
19667 fputs ("\t.long 0\n", file);
19668 fprintf (file, "\t.previous\n");
19670 ASM_OUTPUT_LABEL (file, name);
19674 rs6000_elf_end_indicate_exec_stack (void)
19677 file_end_indicate_exec_stack ();
19683 rs6000_xcoff_asm_output_anchor (rtx symbol)
19687 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19688 SYMBOL_REF_BLOCK_OFFSET (symbol));
19689 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19693 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19695 fputs (GLOBAL_ASM_OP, stream);
19696 RS6000_OUTPUT_BASENAME (stream, name);
19697 putc ('\n', stream);
19700 /* A get_unnamed_decl callback, used for read-only sections. PTR
19701 points to the section string variable. */
19704 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19706 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19707 *(const char *const *) directive);
19710 /* Likewise for read-write sections. */
19713 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19715 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19716 *(const char *const *) directive);
19719 /* A get_unnamed_section callback, used for switching to toc_section. */
19722 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19724 if (TARGET_MINIMAL_TOC)
19726 /* toc_section is always selected at least once from
19727 rs6000_xcoff_file_start, so this is guaranteed to
19728 always be defined once and only once in each file. */
19729 if (!toc_initialized)
19731 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19732 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19733 toc_initialized = 1;
19735 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19736 (TARGET_32BIT ? "" : ",3"));
19739 fputs ("\t.toc\n", asm_out_file);
19742 /* Implement TARGET_ASM_INIT_SECTIONS. */
19745 rs6000_xcoff_asm_init_sections (void)
19747 read_only_data_section
19748 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19749 &xcoff_read_only_section_name);
19751 private_data_section
19752 = get_unnamed_section (SECTION_WRITE,
19753 rs6000_xcoff_output_readwrite_section_asm_op,
19754 &xcoff_private_data_section_name);
19756 read_only_private_data_section
19757 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19758 &xcoff_private_data_section_name);
19761 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19763 readonly_data_section = read_only_data_section;
19764 exception_section = data_section;
19768 rs6000_xcoff_reloc_rw_mask (void)
19774 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19775 tree decl ATTRIBUTE_UNUSED)
19778 static const char * const suffix[3] = { "PR", "RO", "RW" };
19780 if (flags & SECTION_CODE)
19782 else if (flags & SECTION_WRITE)
19787 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19788 (flags & SECTION_CODE) ? "." : "",
19789 name, suffix[smclass], flags & SECTION_ENTSIZE);
19793 rs6000_xcoff_select_section (tree decl, int reloc,
19794 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19796 if (decl_readonly_section (decl, reloc))
19798 if (TREE_PUBLIC (decl))
19799 return read_only_data_section;
19801 return read_only_private_data_section;
19805 if (TREE_PUBLIC (decl))
19806 return data_section;
19808 return private_data_section;
19813 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19817 /* Use select_section for private and uninitialized data. */
19818 if (!TREE_PUBLIC (decl)
19819 || DECL_COMMON (decl)
19820 || DECL_INITIAL (decl) == NULL_TREE
19821 || DECL_INITIAL (decl) == error_mark_node
19822 || (flag_zero_initialized_in_bss
19823 && initializer_zerop (DECL_INITIAL (decl))))
19826 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19827 name = (*targetm.strip_name_encoding) (name);
19828 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19831 /* Select section for constant in constant pool.
19833 On RS/6000, all constants are in the private read-only data area.
19834 However, if this is being placed in the TOC it must be output as a
19838 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19839 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19841 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19842 return toc_section;
19844 return read_only_private_data_section;
19847 /* Remove any trailing [DS] or the like from the symbol name. */
19849 static const char *
19850 rs6000_xcoff_strip_name_encoding (const char *name)
19855 len = strlen (name);
19856 if (name[len - 1] == ']')
19857 return ggc_alloc_string (name, len - 4);
19862 /* Section attributes. AIX is always PIC. */
19864 static unsigned int
19865 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
19867 unsigned int align;
19868 unsigned int flags = default_section_type_flags (decl, name, reloc);
19870 /* Align to at least UNIT size. */
19871 if (flags & SECTION_CODE)
19872 align = MIN_UNITS_PER_WORD;
19874 /* Increase alignment of large objects if not already stricter. */
19875 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
19876 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
19877 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
19879 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
19882 /* Output at beginning of assembler file.
19884 Initialize the section names for the RS/6000 at this point.
19886 Specify filename, including full path, to assembler.
19888 We want to go into the TOC section so at least one .toc will be emitted.
19889 Also, in order to output proper .bs/.es pairs, we need at least one static
19890 [RW] section emitted.
19892 Finally, declare mcount when profiling to make the assembler happy. */
19895 rs6000_xcoff_file_start (void)
19897 rs6000_gen_section_name (&xcoff_bss_section_name,
19898 main_input_filename, ".bss_");
19899 rs6000_gen_section_name (&xcoff_private_data_section_name,
19900 main_input_filename, ".rw_");
19901 rs6000_gen_section_name (&xcoff_read_only_section_name,
19902 main_input_filename, ".ro_");
19904 fputs ("\t.file\t", asm_out_file);
19905 output_quoted_string (asm_out_file, main_input_filename);
19906 fputc ('\n', asm_out_file);
19907 if (write_symbols != NO_DEBUG)
19908 switch_to_section (private_data_section);
19909 switch_to_section (text_section);
19911 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
19912 rs6000_file_start ();
19915 /* Output at end of assembler file.
19916 On the RS/6000, referencing data should automatically pull in text. */
19919 rs6000_xcoff_file_end (void)
19921 switch_to_section (text_section);
19922 fputs ("_section_.text:\n", asm_out_file);
19923 switch_to_section (data_section);
19924 fputs (TARGET_32BIT
19925 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
19928 #endif /* TARGET_XCOFF */
19930 /* Compute a (partial) cost for rtx X. Return true if the complete
19931 cost has been computed, and false if subexpressions should be
19932 scanned. In either case, *TOTAL contains the cost result. */
19935 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
19937 enum machine_mode mode = GET_MODE (x);
19941 /* On the RS/6000, if it is valid in the insn, it is free. */
19943 if (((outer_code == SET
19944 || outer_code == PLUS
19945 || outer_code == MINUS)
19946 && (satisfies_constraint_I (x)
19947 || satisfies_constraint_L (x)))
19948 || (outer_code == AND
19949 && (satisfies_constraint_K (x)
19951 ? satisfies_constraint_L (x)
19952 : satisfies_constraint_J (x))
19953 || mask_operand (x, mode)
19955 && mask64_operand (x, DImode))))
19956 || ((outer_code == IOR || outer_code == XOR)
19957 && (satisfies_constraint_K (x)
19959 ? satisfies_constraint_L (x)
19960 : satisfies_constraint_J (x))))
19961 || outer_code == ASHIFT
19962 || outer_code == ASHIFTRT
19963 || outer_code == LSHIFTRT
19964 || outer_code == ROTATE
19965 || outer_code == ROTATERT
19966 || outer_code == ZERO_EXTRACT
19967 || (outer_code == MULT
19968 && satisfies_constraint_I (x))
19969 || ((outer_code == DIV || outer_code == UDIV
19970 || outer_code == MOD || outer_code == UMOD)
19971 && exact_log2 (INTVAL (x)) >= 0)
19972 || (outer_code == COMPARE
19973 && (satisfies_constraint_I (x)
19974 || satisfies_constraint_K (x)))
19975 || (outer_code == EQ
19976 && (satisfies_constraint_I (x)
19977 || satisfies_constraint_K (x)
19979 ? satisfies_constraint_L (x)
19980 : satisfies_constraint_J (x))))
19981 || (outer_code == GTU
19982 && satisfies_constraint_I (x))
19983 || (outer_code == LTU
19984 && satisfies_constraint_P (x)))
19989 else if ((outer_code == PLUS
19990 && reg_or_add_cint_operand (x, VOIDmode))
19991 || (outer_code == MINUS
19992 && reg_or_sub_cint_operand (x, VOIDmode))
19993 || ((outer_code == SET
19994 || outer_code == IOR
19995 || outer_code == XOR)
19997 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
19999 *total = COSTS_N_INSNS (1);
20005 if (mode == DImode && code == CONST_DOUBLE)
20007 if ((outer_code == IOR || outer_code == XOR)
20008 && CONST_DOUBLE_HIGH (x) == 0
20009 && (CONST_DOUBLE_LOW (x)
20010 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20015 else if ((outer_code == AND && and64_2_operand (x, DImode))
20016 || ((outer_code == SET
20017 || outer_code == IOR
20018 || outer_code == XOR)
20019 && CONST_DOUBLE_HIGH (x) == 0))
20021 *total = COSTS_N_INSNS (1);
20031 /* When optimizing for size, MEM should be slightly more expensive
20032 than generating address, e.g., (plus (reg) (const)).
20033 L1 cache latency is about two instructions. */
20034 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20042 if (mode == DFmode)
20044 if (GET_CODE (XEXP (x, 0)) == MULT)
20046 /* FNMA accounted in outer NEG. */
20047 if (outer_code == NEG)
20048 *total = rs6000_cost->dmul - rs6000_cost->fp;
20050 *total = rs6000_cost->dmul;
20053 *total = rs6000_cost->fp;
20055 else if (mode == SFmode)
20057 /* FNMA accounted in outer NEG. */
20058 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20061 *total = rs6000_cost->fp;
20064 *total = COSTS_N_INSNS (1);
20068 if (mode == DFmode)
20070 if (GET_CODE (XEXP (x, 0)) == MULT
20071 || GET_CODE (XEXP (x, 1)) == MULT)
20073 /* FNMA accounted in outer NEG. */
20074 if (outer_code == NEG)
20075 *total = rs6000_cost->dmul - rs6000_cost->fp;
20077 *total = rs6000_cost->dmul;
20080 *total = rs6000_cost->fp;
20082 else if (mode == SFmode)
20084 /* FNMA accounted in outer NEG. */
20085 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20088 *total = rs6000_cost->fp;
20091 *total = COSTS_N_INSNS (1);
20095 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20096 && satisfies_constraint_I (XEXP (x, 1)))
20098 if (INTVAL (XEXP (x, 1)) >= -256
20099 && INTVAL (XEXP (x, 1)) <= 255)
20100 *total = rs6000_cost->mulsi_const9;
20102 *total = rs6000_cost->mulsi_const;
20104 /* FMA accounted in outer PLUS/MINUS. */
20105 else if ((mode == DFmode || mode == SFmode)
20106 && (outer_code == PLUS || outer_code == MINUS))
20108 else if (mode == DFmode)
20109 *total = rs6000_cost->dmul;
20110 else if (mode == SFmode)
20111 *total = rs6000_cost->fp;
20112 else if (mode == DImode)
20113 *total = rs6000_cost->muldi;
20115 *total = rs6000_cost->mulsi;
20120 if (FLOAT_MODE_P (mode))
20122 *total = mode == DFmode ? rs6000_cost->ddiv
20123 : rs6000_cost->sdiv;
20130 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20131 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20133 if (code == DIV || code == MOD)
20135 *total = COSTS_N_INSNS (2);
20138 *total = COSTS_N_INSNS (1);
20142 if (GET_MODE (XEXP (x, 1)) == DImode)
20143 *total = rs6000_cost->divdi;
20145 *total = rs6000_cost->divsi;
20147 /* Add in shift and subtract for MOD. */
20148 if (code == MOD || code == UMOD)
20149 *total += COSTS_N_INSNS (2);
20153 *total = COSTS_N_INSNS (4);
20157 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20168 *total = COSTS_N_INSNS (1);
20176 /* Handle mul_highpart. */
20177 if (outer_code == TRUNCATE
20178 && GET_CODE (XEXP (x, 0)) == MULT)
20180 if (mode == DImode)
20181 *total = rs6000_cost->muldi;
20183 *total = rs6000_cost->mulsi;
20186 else if (outer_code == AND)
20189 *total = COSTS_N_INSNS (1);
20194 if (GET_CODE (XEXP (x, 0)) == MEM)
20197 *total = COSTS_N_INSNS (1);
20203 if (!FLOAT_MODE_P (mode))
20205 *total = COSTS_N_INSNS (1);
20211 case UNSIGNED_FLOAT:
20214 case FLOAT_TRUNCATE:
20215 *total = rs6000_cost->fp;
20219 if (mode == DFmode)
20222 *total = rs6000_cost->fp;
20226 switch (XINT (x, 1))
20229 *total = rs6000_cost->fp;
20241 *total = COSTS_N_INSNS (1);
20244 else if (FLOAT_MODE_P (mode)
20245 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20247 *total = rs6000_cost->fp;
20255 /* Carry bit requires mode == Pmode.
20256 NEG or PLUS already counted so only add one. */
20258 && (outer_code == NEG || outer_code == PLUS))
20260 *total = COSTS_N_INSNS (1);
20263 if (outer_code == SET)
20265 if (XEXP (x, 1) == const0_rtx)
20267 *total = COSTS_N_INSNS (2);
20270 else if (mode == Pmode)
20272 *total = COSTS_N_INSNS (3);
20281 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20283 *total = COSTS_N_INSNS (2);
20287 if (outer_code == COMPARE)
20301 /* A C expression returning the cost of moving data from a register of class
20302 CLASS1 to one of CLASS2. */
20305 rs6000_register_move_cost (enum machine_mode mode,
20306 enum reg_class from, enum reg_class to)
20308 /* Moves from/to GENERAL_REGS. */
20309 if (reg_classes_intersect_p (to, GENERAL_REGS)
20310 || reg_classes_intersect_p (from, GENERAL_REGS))
20312 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20315 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20316 return (rs6000_memory_move_cost (mode, from, 0)
20317 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20319 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20321 else if (from == CR_REGS)
20325 /* A move will cost one instruction per GPR moved. */
20326 return 2 * hard_regno_nregs[0][mode];
20329 /* Moving between two similar registers is just one instruction. */
20330 else if (reg_classes_intersect_p (to, from))
20331 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20333 /* Everything else has to go through GENERAL_REGS. */
20335 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20336 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20339 /* A C expressions returning the cost of moving data of MODE from a register to
20343 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20344 int in ATTRIBUTE_UNUSED)
20346 if (reg_classes_intersect_p (class, GENERAL_REGS))
20347 return 4 * hard_regno_nregs[0][mode];
20348 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20349 return 4 * hard_regno_nregs[32][mode];
20350 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20351 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20353 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20356 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20357 Assumes no trapping math and finite arguments. */
20360 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20362 rtx x0, e0, e1, y1, u0, v0, one;
20364 x0 = gen_reg_rtx (SFmode);
20365 e0 = gen_reg_rtx (SFmode);
20366 e1 = gen_reg_rtx (SFmode);
20367 y1 = gen_reg_rtx (SFmode);
20368 u0 = gen_reg_rtx (SFmode);
20369 v0 = gen_reg_rtx (SFmode);
20370 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20372 /* x0 = 1./d estimate */
20373 emit_insn (gen_rtx_SET (VOIDmode, x0,
20374 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20376 /* e0 = 1. - d * x0 */
20377 emit_insn (gen_rtx_SET (VOIDmode, e0,
20378 gen_rtx_MINUS (SFmode, one,
20379 gen_rtx_MULT (SFmode, d, x0))));
20380 /* e1 = e0 + e0 * e0 */
20381 emit_insn (gen_rtx_SET (VOIDmode, e1,
20382 gen_rtx_PLUS (SFmode,
20383 gen_rtx_MULT (SFmode, e0, e0), e0)));
20384 /* y1 = x0 + e1 * x0 */
20385 emit_insn (gen_rtx_SET (VOIDmode, y1,
20386 gen_rtx_PLUS (SFmode,
20387 gen_rtx_MULT (SFmode, e1, x0), x0)));
20389 emit_insn (gen_rtx_SET (VOIDmode, u0,
20390 gen_rtx_MULT (SFmode, n, y1)));
20391 /* v0 = n - d * u0 */
20392 emit_insn (gen_rtx_SET (VOIDmode, v0,
20393 gen_rtx_MINUS (SFmode, n,
20394 gen_rtx_MULT (SFmode, d, u0))));
20395 /* res = u0 + v0 * y1 */
20396 emit_insn (gen_rtx_SET (VOIDmode, res,
20397 gen_rtx_PLUS (SFmode,
20398 gen_rtx_MULT (SFmode, v0, y1), u0)));
20401 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20402 Assumes no trapping math and finite arguments. */
20405 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20407 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20409 x0 = gen_reg_rtx (DFmode);
20410 e0 = gen_reg_rtx (DFmode);
20411 e1 = gen_reg_rtx (DFmode);
20412 e2 = gen_reg_rtx (DFmode);
20413 y1 = gen_reg_rtx (DFmode);
20414 y2 = gen_reg_rtx (DFmode);
20415 y3 = gen_reg_rtx (DFmode);
20416 u0 = gen_reg_rtx (DFmode);
20417 v0 = gen_reg_rtx (DFmode);
20418 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20420 /* x0 = 1./d estimate */
20421 emit_insn (gen_rtx_SET (VOIDmode, x0,
20422 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20424 /* e0 = 1. - d * x0 */
20425 emit_insn (gen_rtx_SET (VOIDmode, e0,
20426 gen_rtx_MINUS (DFmode, one,
20427 gen_rtx_MULT (SFmode, d, x0))));
20428 /* y1 = x0 + e0 * x0 */
20429 emit_insn (gen_rtx_SET (VOIDmode, y1,
20430 gen_rtx_PLUS (DFmode,
20431 gen_rtx_MULT (DFmode, e0, x0), x0)));
20433 emit_insn (gen_rtx_SET (VOIDmode, e1,
20434 gen_rtx_MULT (DFmode, e0, e0)));
20435 /* y2 = y1 + e1 * y1 */
20436 emit_insn (gen_rtx_SET (VOIDmode, y2,
20437 gen_rtx_PLUS (DFmode,
20438 gen_rtx_MULT (DFmode, e1, y1), y1)));
20440 emit_insn (gen_rtx_SET (VOIDmode, e2,
20441 gen_rtx_MULT (DFmode, e1, e1)));
20442 /* y3 = y2 + e2 * y2 */
20443 emit_insn (gen_rtx_SET (VOIDmode, y3,
20444 gen_rtx_PLUS (DFmode,
20445 gen_rtx_MULT (DFmode, e2, y2), y2)));
20447 emit_insn (gen_rtx_SET (VOIDmode, u0,
20448 gen_rtx_MULT (DFmode, n, y3)));
20449 /* v0 = n - d * u0 */
20450 emit_insn (gen_rtx_SET (VOIDmode, v0,
20451 gen_rtx_MINUS (DFmode, n,
20452 gen_rtx_MULT (DFmode, d, u0))));
20453 /* res = u0 + v0 * y3 */
20454 emit_insn (gen_rtx_SET (VOIDmode, res,
20455 gen_rtx_PLUS (DFmode,
20456 gen_rtx_MULT (DFmode, v0, y3), u0)));
20460 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20461 target, and SRC is the argument operand. */
20464 rs6000_emit_popcount (rtx dst, rtx src)
20466 enum machine_mode mode = GET_MODE (dst);
20469 tmp1 = gen_reg_rtx (mode);
20471 if (mode == SImode)
20473 emit_insn (gen_popcntbsi2 (tmp1, src));
20474 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20476 tmp2 = force_reg (SImode, tmp2);
20477 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20481 emit_insn (gen_popcntbdi2 (tmp1, src));
20482 tmp2 = expand_mult (DImode, tmp1,
20483 GEN_INT ((HOST_WIDE_INT)
20484 0x01010101 << 32 | 0x01010101),
20486 tmp2 = force_reg (DImode, tmp2);
20487 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20492 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20493 target, and SRC is the argument operand. */
20496 rs6000_emit_parity (rtx dst, rtx src)
20498 enum machine_mode mode = GET_MODE (dst);
20501 tmp = gen_reg_rtx (mode);
20502 if (mode == SImode)
20504 /* Is mult+shift >= shift+xor+shift+xor? */
20505 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20507 rtx tmp1, tmp2, tmp3, tmp4;
20509 tmp1 = gen_reg_rtx (SImode);
20510 emit_insn (gen_popcntbsi2 (tmp1, src));
20512 tmp2 = gen_reg_rtx (SImode);
20513 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20514 tmp3 = gen_reg_rtx (SImode);
20515 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20517 tmp4 = gen_reg_rtx (SImode);
20518 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20519 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20522 rs6000_emit_popcount (tmp, src);
20523 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20527 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20528 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20530 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20532 tmp1 = gen_reg_rtx (DImode);
20533 emit_insn (gen_popcntbdi2 (tmp1, src));
20535 tmp2 = gen_reg_rtx (DImode);
20536 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20537 tmp3 = gen_reg_rtx (DImode);
20538 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20540 tmp4 = gen_reg_rtx (DImode);
20541 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20542 tmp5 = gen_reg_rtx (DImode);
20543 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20545 tmp6 = gen_reg_rtx (DImode);
20546 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20547 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20550 rs6000_emit_popcount (tmp, src);
20551 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20555 /* Return an RTX representing where to find the function value of a
20556 function returning MODE. */
20558 rs6000_complex_function_value (enum machine_mode mode)
20560 unsigned int regno;
20562 enum machine_mode inner = GET_MODE_INNER (mode);
20563 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20565 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20566 regno = FP_ARG_RETURN;
20569 regno = GP_ARG_RETURN;
20571 /* 32-bit is OK since it'll go in r3/r4. */
20572 if (TARGET_32BIT && inner_bytes >= 4)
20573 return gen_rtx_REG (mode, regno);
20576 if (inner_bytes >= 8)
20577 return gen_rtx_REG (mode, regno);
20579 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20581 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20582 GEN_INT (inner_bytes));
20583 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20586 /* Define how to find the value returned by a function.
20587 VALTYPE is the data type of the value (as a tree).
20588 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20589 otherwise, FUNC is 0.
20591 On the SPE, both FPs and vectors are returned in r3.
20593 On RS/6000 an integer value is in r3 and a floating-point value is in
20594 fp1, unless -msoft-float. */
20597 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20599 enum machine_mode mode;
20600 unsigned int regno;
20602 /* Special handling for structs in darwin64. */
20603 if (rs6000_darwin64_abi
20604 && TYPE_MODE (valtype) == BLKmode
20605 && TREE_CODE (valtype) == RECORD_TYPE
20606 && int_size_in_bytes (valtype) > 0)
20608 CUMULATIVE_ARGS valcum;
20612 valcum.fregno = FP_ARG_MIN_REG;
20613 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20614 /* Do a trial code generation as if this were going to be passed as
20615 an argument; if any part goes in memory, we return NULL. */
20616 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20619 /* Otherwise fall through to standard ABI rules. */
20622 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20624 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20625 return gen_rtx_PARALLEL (DImode,
20627 gen_rtx_EXPR_LIST (VOIDmode,
20628 gen_rtx_REG (SImode, GP_ARG_RETURN),
20630 gen_rtx_EXPR_LIST (VOIDmode,
20631 gen_rtx_REG (SImode,
20632 GP_ARG_RETURN + 1),
20635 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20637 return gen_rtx_PARALLEL (DCmode,
20639 gen_rtx_EXPR_LIST (VOIDmode,
20640 gen_rtx_REG (SImode, GP_ARG_RETURN),
20642 gen_rtx_EXPR_LIST (VOIDmode,
20643 gen_rtx_REG (SImode,
20644 GP_ARG_RETURN + 1),
20646 gen_rtx_EXPR_LIST (VOIDmode,
20647 gen_rtx_REG (SImode,
20648 GP_ARG_RETURN + 2),
20650 gen_rtx_EXPR_LIST (VOIDmode,
20651 gen_rtx_REG (SImode,
20652 GP_ARG_RETURN + 3),
20656 mode = TYPE_MODE (valtype);
20657 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20658 || POINTER_TYPE_P (valtype))
20659 mode = TARGET_32BIT ? SImode : DImode;
20661 if (DECIMAL_FLOAT_MODE_P (mode))
20663 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20668 gcc_unreachable ();
20670 regno = GP_ARG_RETURN;
20673 regno = FP_ARG_RETURN;
20676 /* Use f2:f3 specified by the ABI. */
20677 regno = FP_ARG_RETURN + 1;
20682 regno = GP_ARG_RETURN;
20684 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20685 regno = FP_ARG_RETURN;
20686 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20687 && targetm.calls.split_complex_arg)
20688 return rs6000_complex_function_value (mode);
20689 else if (TREE_CODE (valtype) == VECTOR_TYPE
20690 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20691 && ALTIVEC_VECTOR_MODE (mode))
20692 regno = ALTIVEC_ARG_RETURN;
20693 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20694 && (mode == DFmode || mode == DCmode
20695 || mode == TFmode || mode == TCmode))
20696 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20698 regno = GP_ARG_RETURN;
20700 return gen_rtx_REG (mode, regno);
20703 /* Define how to find the value returned by a library function
20704 assuming the value has mode MODE. */
20706 rs6000_libcall_value (enum machine_mode mode)
20708 unsigned int regno;
20710 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20712 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20713 return gen_rtx_PARALLEL (DImode,
20715 gen_rtx_EXPR_LIST (VOIDmode,
20716 gen_rtx_REG (SImode, GP_ARG_RETURN),
20718 gen_rtx_EXPR_LIST (VOIDmode,
20719 gen_rtx_REG (SImode,
20720 GP_ARG_RETURN + 1),
20724 if (DECIMAL_FLOAT_MODE_P (mode))
20726 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20731 gcc_unreachable ();
20733 regno = GP_ARG_RETURN;
20736 regno = FP_ARG_RETURN;
20739 /* Use f2:f3 specified by the ABI. */
20740 regno = FP_ARG_RETURN + 1;
20745 regno = GP_ARG_RETURN;
20747 else if (SCALAR_FLOAT_MODE_P (mode)
20748 && TARGET_HARD_FLOAT && TARGET_FPRS)
20749 regno = FP_ARG_RETURN;
20750 else if (ALTIVEC_VECTOR_MODE (mode)
20751 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20752 regno = ALTIVEC_ARG_RETURN;
20753 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20754 return rs6000_complex_function_value (mode);
20755 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20756 && (mode == DFmode || mode == DCmode
20757 || mode == TFmode || mode == TCmode))
20758 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20760 regno = GP_ARG_RETURN;
20762 return gen_rtx_REG (mode, regno);
20765 /* Define the offset between two registers, FROM to be eliminated and its
20766 replacement TO, at the start of a routine. */
20768 rs6000_initial_elimination_offset (int from, int to)
20770 rs6000_stack_t *info = rs6000_stack_info ();
20771 HOST_WIDE_INT offset;
20773 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20774 offset = info->push_p ? 0 : -info->total_size;
20775 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20777 offset = info->push_p ? 0 : -info->total_size;
20778 if (FRAME_GROWS_DOWNWARD)
20779 offset += info->fixed_size + info->vars_size + info->parm_size;
20781 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20782 offset = FRAME_GROWS_DOWNWARD
20783 ? info->fixed_size + info->vars_size + info->parm_size
20785 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20786 offset = info->total_size;
20787 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20788 offset = info->push_p ? info->total_size : 0;
20789 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20792 gcc_unreachable ();
20797 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20800 rs6000_is_opaque_type (tree type)
20802 return (type == opaque_V2SI_type_node
20803 || type == opaque_V2SF_type_node
20804 || type == opaque_p_V2SI_type_node
20805 || type == opaque_V4SI_type_node);
20809 rs6000_dwarf_register_span (rtx reg)
20814 && (SPE_VECTOR_MODE (GET_MODE (reg))
20815 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20820 regno = REGNO (reg);
20822 /* The duality of the SPE register size wreaks all kinds of havoc.
20823 This is a way of distinguishing r0 in 32-bits from r0 in
20826 gen_rtx_PARALLEL (VOIDmode,
20829 gen_rtx_REG (SImode, regno + 1200),
20830 gen_rtx_REG (SImode, regno))
20832 gen_rtx_REG (SImode, regno),
20833 gen_rtx_REG (SImode, regno + 1200)));
20836 /* Fill in sizes for SPE register high parts in table used by unwinder. */
20839 rs6000_init_dwarf_reg_sizes_extra (tree address)
20844 enum machine_mode mode = TYPE_MODE (char_type_node);
20845 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
20846 rtx mem = gen_rtx_MEM (BLKmode, addr);
20847 rtx value = gen_int_mode (4, mode);
20849 for (i = 1201; i < 1232; i++)
20851 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
20852 HOST_WIDE_INT offset
20853 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
20855 emit_move_insn (adjust_address (mem, mode, offset), value);
20860 /* Map internal gcc register numbers to DWARF2 register numbers. */
20863 rs6000_dbx_register_number (unsigned int regno)
20865 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
20867 if (regno == MQ_REGNO)
20869 if (regno == LINK_REGISTER_REGNUM)
20871 if (regno == COUNT_REGISTER_REGNUM)
20873 if (CR_REGNO_P (regno))
20874 return regno - CR0_REGNO + 86;
20875 if (regno == XER_REGNO)
20877 if (ALTIVEC_REGNO_P (regno))
20878 return regno - FIRST_ALTIVEC_REGNO + 1124;
20879 if (regno == VRSAVE_REGNO)
20881 if (regno == VSCR_REGNO)
20883 if (regno == SPE_ACC_REGNO)
20885 if (regno == SPEFSCR_REGNO)
20887 /* SPE high reg number. We get these values of regno from
20888 rs6000_dwarf_register_span. */
20889 gcc_assert (regno >= 1200 && regno < 1232);
20893 /* target hook eh_return_filter_mode */
20894 static enum machine_mode
20895 rs6000_eh_return_filter_mode (void)
20897 return TARGET_32BIT ? SImode : word_mode;
20900 /* Target hook for scalar_mode_supported_p. */
20902 rs6000_scalar_mode_supported_p (enum machine_mode mode)
20904 if (DECIMAL_FLOAT_MODE_P (mode))
20907 return default_scalar_mode_supported_p (mode);
20910 /* Target hook for vector_mode_supported_p. */
20912 rs6000_vector_mode_supported_p (enum machine_mode mode)
20915 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
20918 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
20925 /* Target hook for invalid_arg_for_unprototyped_fn. */
20926 static const char *
20927 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
20929 return (!rs6000_darwin64_abi
20931 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
20932 && (funcdecl == NULL_TREE
20933 || (TREE_CODE (funcdecl) == FUNCTION_DECL
20934 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
20935 ? N_("AltiVec argument passed to unprototyped function")
20939 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
20940 setup by using __stack_chk_fail_local hidden function instead of
20941 calling __stack_chk_fail directly. Otherwise it is better to call
20942 __stack_chk_fail directly. */
20945 rs6000_stack_protect_fail (void)
20947 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
20948 ? default_hidden_stack_protect_fail ()
20949 : default_external_stack_protect_fail ();
20952 #include "gt-rs6000.h"