1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
40 extern char *language_string;
41 extern int profile_block_flag;
43 #define min(A,B) ((A) < (B) ? (A) : (B))
44 #define max(A,B) ((A) > (B) ? (A) : (B))
48 enum processor_type rs6000_cpu;
49 char *rs6000_cpu_string;
51 /* Set to non-zero by "fix" operation to indicate that itrunc and
52 uitrunc must be defined. */
54 int rs6000_trunc_used;
56 /* Set to non-zero once they have been defined. */
58 static int trunc_defined;
60 /* Set to non-zero once AIX common-mode calls have been defined. */
61 static int common_mode_defined;
62 /* Save information from a "cmpxx" operation until the branch or scc is
65 rtx rs6000_compare_op0, rs6000_compare_op1;
66 int rs6000_compare_fp_p;
69 /* Label number of label created for -mrelocatable, to call to so we can
70 get the address of the GOT section */
71 int rs6000_pic_labelno;
74 /* Whether a System V.4 varargs area was created. */
75 int rs6000_sysv_varargs_p;
77 /* Print the options used in the assembly file. */
79 extern char *version_string, *language_string;
91 output_option (file, type, name, pos)
97 int type_len = strlen (type);
98 int name_len = strlen (name);
100 if (1 + type_len + name_len + pos > MAX_LINE)
102 fprintf (file, "\n # %s%s", type, name);
103 return 3 + type_len + name_len;
105 fprintf (file, " %s%s", type, name);
106 return pos + 1 + type_len + name_len;
109 static struct { char *name; int value; } m_options[] = TARGET_SWITCHES;
112 output_options (file, f_options, f_len, W_options, W_len)
114 struct option *f_options;
116 struct option *W_options;
120 int flags = target_flags;
123 fprintf (file, " # %s %s", language_string, version_string);
128 sprintf (opt_string, "%d", optimize);
129 pos = output_option (file, "-O", opt_string, pos);
133 pos = output_option (file, "-p", "", pos);
135 if (profile_block_flag)
136 pos = output_option (file, "-a", "", pos);
138 if (inhibit_warnings)
139 pos = output_option (file, "-w", "", pos);
141 for (j = 0; j < f_len; j++)
143 if (*f_options[j].variable == f_options[j].on_value)
144 pos = output_option (file, "-f", f_options[j].string, pos);
147 for (j = 0; j < W_len; j++)
149 if (*W_options[j].variable == W_options[j].on_value)
150 pos = output_option (file, "-W", W_options[j].string, pos);
153 for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++)
155 if (m_options[j].name[0] != '\0'
156 && m_options[j].value > 0
157 && ((m_options[j].value & flags) == m_options[j].value))
159 pos = output_option (file, "-m", m_options[j].name, pos);
160 flags &= ~ m_options[j].value;
164 if (rs6000_cpu_string != (char *)0)
165 pos = output_option (file, "-mcpu=", rs6000_cpu_string, pos);
167 fputs ("\n\n", file);
171 /* Override command line options. Mostly we process the processor
172 type and sometimes adjust other TARGET_ options. */
175 rs6000_override_options ()
179 /* Simplify the entries below by making a mask for any POWER
180 variant and any PowerPC variant. */
182 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
183 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
184 | MASK_PPC_GFXOPT | MASK_POWERPC64)
185 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
189 char *name; /* Canonical processor name. */
190 enum processor_type processor; /* Processor type enum value. */
191 int target_enable; /* Target flags to enable. */
192 int target_disable; /* Target flags to disable. */
193 } processor_target_table[]
194 = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS},
195 {"power", PROCESSOR_POWER,
196 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
197 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
198 {"powerpc", PROCESSOR_POWERPC,
199 MASK_POWERPC | MASK_NEW_MNEMONICS,
200 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
201 {"rios", PROCESSOR_RIOS1,
202 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
203 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
204 {"rios1", PROCESSOR_RIOS1,
205 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
206 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
207 {"rsc", PROCESSOR_PPC601,
208 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
209 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
210 {"rsc1", PROCESSOR_PPC601,
211 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
212 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
213 {"rios2", PROCESSOR_RIOS2,
214 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
215 POWERPC_MASKS | MASK_NEW_MNEMONICS},
216 {"403", PROCESSOR_PPC403,
217 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
218 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
219 {"601", PROCESSOR_PPC601,
220 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
221 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
222 {"603", PROCESSOR_PPC603,
223 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
224 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
225 {"604", PROCESSOR_PPC604,
226 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
227 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}};
229 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
231 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
232 int string = TARGET_STRING; /* save current -mstring/-mno-string status */
234 profile_block_flag = 0;
236 /* Identify the processor type */
237 if (rs6000_cpu_string == 0)
238 rs6000_cpu = PROCESSOR_DEFAULT;
241 for (i = 0; i < ptt_size; i++)
242 if (! strcmp (rs6000_cpu_string, processor_target_table[i].name))
244 rs6000_cpu = processor_target_table[i].processor;
245 target_flags |= processor_target_table[i].target_enable;
246 target_flags &= ~processor_target_table[i].target_disable;
252 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string);
253 rs6000_cpu_string = "default";
254 rs6000_cpu = PROCESSOR_DEFAULT;
258 /* If -mmultiple or -mno-multiple was explicitly used, don't
259 override with the processor default */
260 if (TARGET_MULTIPLE_SET)
261 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
263 /* If -mstring or -mno-string was explicitly used, don't
264 override with the processor default */
265 if (TARGET_STRING_SET)
266 target_flags = (target_flags & ~MASK_STRING) | string;
268 /* Don't allow -mmultiple or -mstring on little endian systems, because the
269 hardware doesn't support the instructions used in little endian mode */
270 if (!BYTES_BIG_ENDIAN)
274 target_flags &= ~MASK_MULTIPLE;
275 if (TARGET_MULTIPLE_SET)
276 warning ("-mmultiple is not supported on little endian systems");
281 target_flags &= ~MASK_STRING;
282 if (TARGET_STRING_SET)
283 warning ("-mstring is not supported on little endian systems");
287 #ifdef SUBTARGET_OVERRIDE_OPTIONS
288 SUBTARGET_OVERRIDE_OPTIONS;
292 /* Create a CONST_DOUBLE from a string. */
295 rs6000_float_const (string, mode)
297 enum machine_mode mode;
299 REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode);
300 return immed_real_const_1 (value, mode);
304 /* Create a CONST_DOUBLE like immed_double_const, except reverse the
305 two parts of the constant if the target is little endian. */
308 rs6000_immed_double_const (i0, i1, mode)
309 HOST_WIDE_INT i0, i1;
310 enum machine_mode mode;
312 if (! WORDS_BIG_ENDIAN)
313 return immed_double_const (i1, i0, mode);
315 return immed_double_const (i0, i1, mode);
319 /* Return non-zero if this function is known to have a null epilogue. */
324 if (reload_completed)
326 rs6000_stack_t *info = rs6000_stack_info ();
328 if (info->first_gp_reg_save == 32
329 && info->first_fp_reg_save == 64
339 /* Returns 1 always. */
342 any_operand (op, mode)
344 enum machine_mode mode;
349 /* Return 1 if OP is a constant that can fit in a D field. */
352 short_cint_operand (op, mode)
354 enum machine_mode mode;
356 return (GET_CODE (op) == CONST_INT
357 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
360 /* Similar for a unsigned D field. */
363 u_short_cint_operand (op, mode)
365 enum machine_mode mode;
367 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
370 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
373 non_short_cint_operand (op, mode)
375 enum machine_mode mode;
377 return (GET_CODE (op) == CONST_INT
378 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
381 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
385 gpc_reg_operand (op, mode)
387 enum machine_mode mode;
389 return (register_operand (op, mode)
390 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
393 /* Returns 1 if OP is either a pseudo-register or a register denoting a
397 cc_reg_operand (op, mode)
399 enum machine_mode mode;
401 return (register_operand (op, mode)
402 && (GET_CODE (op) != REG
403 || REGNO (op) >= FIRST_PSEUDO_REGISTER
404 || CR_REGNO_P (REGNO (op))));
407 /* Returns 1 if OP is either a constant integer valid for a D-field or a
408 non-special register. If a register, it must be in the proper mode unless
412 reg_or_short_operand (op, mode)
414 enum machine_mode mode;
416 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
419 /* Similar, except check if the negation of the constant would be valid for
423 reg_or_neg_short_operand (op, mode)
425 enum machine_mode mode;
427 if (GET_CODE (op) == CONST_INT)
428 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
430 return gpc_reg_operand (op, mode);
433 /* Return 1 if the operand is either a register or an integer whose high-order
437 reg_or_u_short_operand (op, mode)
439 enum machine_mode mode;
441 if (GET_CODE (op) == CONST_INT
442 && (INTVAL (op) & 0xffff0000) == 0)
445 return gpc_reg_operand (op, mode);
448 /* Return 1 is the operand is either a non-special register or ANY
452 reg_or_cint_operand (op, mode)
454 enum machine_mode mode;
456 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
459 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
460 with one instruction per word. We only do this if we can safely read
461 CONST_DOUBLE_{LOW,HIGH}. */
464 easy_fp_constant (op, mode)
466 register enum machine_mode mode;
470 if (GET_CODE (op) != CONST_DOUBLE
471 || GET_MODE (op) != mode
472 || GET_MODE_CLASS (mode) != MODE_FLOAT)
475 high = operand_subword (op, 0, 0, mode);
476 low = operand_subword (op, 1, 0, mode);
478 if (high == 0 || ! input_operand (high, word_mode))
481 return (mode == SFmode
482 || (low != 0 && input_operand (low, word_mode)));
485 /* Return 1 if the operand is a constant whose low-order 32 bits are
489 low_32_bit_operand (op, mode)
491 enum machine_mode mode;
495 if (GET_CODE (op) != CONST_DOUBLE && GET_CODE (op) != CONST_INT)
498 low = operand_subword (op, 1, 0, mode);
499 return low != 0 && GET_CODE (low) == CONST_INT && INTVAL (low) == 0;
502 /* Return 1 if the operand is either a floating-point register, a pseudo
503 register, or memory. */
506 fp_reg_or_mem_operand (op, mode)
508 enum machine_mode mode;
510 return (memory_operand (op, mode)
511 || (register_operand (op, mode)
512 && (GET_CODE (op) != REG
513 || REGNO (op) >= FIRST_PSEUDO_REGISTER
514 || FP_REGNO_P (REGNO (op)))));
517 /* Return 1 if the operand is either an easy FP constant (see above) or
521 mem_or_easy_const_operand (op, mode)
523 enum machine_mode mode;
525 return memory_operand (op, mode) || easy_fp_constant (op, mode);
528 /* Return 1 if the operand is either a non-special register or an item
529 that can be used as the operand of an SI add insn. */
532 add_operand (op, mode)
534 enum machine_mode mode;
536 return (reg_or_short_operand (op, mode)
537 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
540 /* Return 1 if OP is a constant but not a valid add_operand. */
543 non_add_cint_operand (op, mode)
545 enum machine_mode mode;
547 return (GET_CODE (op) == CONST_INT
548 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
549 && (INTVAL (op) & 0xffff) != 0);
552 /* Return 1 if the operand is a non-special register or a constant that
553 can be used as the operand of an OR or XOR insn on the RS/6000. */
556 logical_operand (op, mode)
558 enum machine_mode mode;
560 return (gpc_reg_operand (op, mode)
561 || (GET_CODE (op) == CONST_INT
562 && ((INTVAL (op) & 0xffff0000) == 0
563 || (INTVAL (op) & 0xffff) == 0)));
566 /* Return 1 if C is a constant that is not a logical operand (as
570 non_logical_cint_operand (op, mode)
572 enum machine_mode mode;
574 return (GET_CODE (op) == CONST_INT
575 && (INTVAL (op) & 0xffff0000) != 0
576 && (INTVAL (op) & 0xffff) != 0);
579 /* Return 1 if C is a constant that can be encoded in a mask on the
580 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
581 Reject all ones and all zeros, since these should have been optimized
582 away and confuse the making of MB and ME. */
592 if (c == 0 || c == ~0)
595 last_bit_value = c & 1;
597 for (i = 1; i < 32; i++)
598 if (((c >>= 1) & 1) != last_bit_value)
599 last_bit_value ^= 1, transitions++;
601 return transitions <= 2;
604 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
607 mask_operand (op, mode)
609 enum machine_mode mode;
611 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
614 /* Return 1 if the operand is either a non-special register or a
615 constant that can be used as the operand of an RS/6000 logical AND insn. */
618 and_operand (op, mode)
620 enum machine_mode mode;
622 return (reg_or_short_operand (op, mode)
623 || logical_operand (op, mode)
624 || mask_operand (op, mode));
627 /* Return 1 if the operand is a constant but not a valid operand for an AND
631 non_and_cint_operand (op, mode)
633 enum machine_mode mode;
635 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
638 /* Return 1 if the operand is a general register or memory operand. */
641 reg_or_mem_operand (op, mode)
643 register enum machine_mode mode;
645 return gpc_reg_operand (op, mode) || memory_operand (op, mode);
648 /* Return 1 if the operand is a general register or memory operand without
649 pre-inc or pre_dec which produces invalid form of PowerPC lwa
653 lwa_operand (op, mode)
655 register enum machine_mode mode;
659 if (reload_completed && GET_CODE (inner) == SUBREG)
660 inner = SUBREG_REG (inner);
662 return gpc_reg_operand (inner, mode)
663 || (memory_operand (inner, mode)
664 && GET_CODE (XEXP (inner, 0)) != PRE_INC
665 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
668 /* Return 1 if the operand, used inside a MEM, is a valid first argument
669 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
673 call_operand (op, mode)
675 enum machine_mode mode;
677 if (mode != VOIDmode && GET_MODE (op) != mode)
680 return (GET_CODE (op) == SYMBOL_REF
681 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
685 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
689 current_file_function_operand (op, mode)
691 enum machine_mode mode;
693 return (GET_CODE (op) == SYMBOL_REF
694 && (SYMBOL_REF_FLAG (op)
695 || op == XEXP (DECL_RTL (current_function_decl), 0)));
699 /* Return 1 if this operand is a valid input for a move insn. */
702 input_operand (op, mode)
704 enum machine_mode mode;
706 /* Memory is always valid. */
707 if (memory_operand (op, mode))
710 /* For floating-point, easy constants are valid. */
711 if (GET_MODE_CLASS (mode) == MODE_FLOAT
713 && easy_fp_constant (op, mode))
716 /* For floating-point or multi-word mode, the only remaining valid type
718 if (GET_MODE_CLASS (mode) == MODE_FLOAT
719 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
720 return register_operand (op, mode);
722 /* The only cases left are integral modes one word or smaller (we
723 do not get called for MODE_CC values). These can be in any
725 if (register_operand (op, mode))
728 /* For HImode and QImode, any constant is valid. */
729 if ((mode == HImode || mode == QImode)
730 && GET_CODE (op) == CONST_INT)
733 /* A SYMBOL_REF referring to the TOC is valid. */
734 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
737 /* Otherwise, we will be doing this SET with an add, so anything valid
738 for an add will be valid. */
739 return add_operand (op, mode);
742 /* Initialize a variable CUM of type CUMULATIVE_ARGS
743 for a call to a function whose data type is FNTYPE.
744 For a library call, FNTYPE is 0.
746 For incoming args we set the number of arguments in the prototype large
747 so we never return an EXPR_LIST. */
750 init_cumulative_args (cum, fntype, libname, incoming)
751 CUMULATIVE_ARGS *cum;
756 static CUMULATIVE_ARGS zero_cumulative;
758 *cum = zero_cumulative;
760 cum->fregno = FP_ARG_MIN_REG;
761 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
765 cum->nargs_prototype = 1000; /* don't return an EXPR_LIST */
766 #ifdef TARGET_V4_CALLS
768 cum->varargs_offset = RS6000_VARARGS_OFFSET;
772 else if (cum->prototype)
773 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
774 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
775 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
778 cum->nargs_prototype = 0;
780 cum->orig_nargs = cum->nargs_prototype;
781 if (TARGET_DEBUG_ARG)
783 fprintf (stderr, "\ninit_cumulative_args:");
786 tree ret_type = TREE_TYPE (fntype);
787 fprintf (stderr, " ret code = %s,",
788 tree_code_name[ (int)TREE_CODE (ret_type) ]);
791 #ifdef TARGET_V4_CALLS
792 if (TARGET_V4_CALLS && incoming)
793 fprintf (stderr, " varargs = %d, ", cum->varargs_offset);
796 fprintf (stderr, " proto = %d, nargs = %d\n",
797 cum->prototype, cum->nargs_prototype);
801 /* Update the data in CUM to advance over an argument
802 of mode MODE and data type TYPE.
803 (TYPE is null for libcalls where that information may not be available.) */
806 function_arg_advance (cum, mode, type, named)
807 CUMULATIVE_ARGS *cum;
808 enum machine_mode mode;
812 cum->nargs_prototype--;
814 #ifdef TARGET_V4_CALLS
817 /* Long longs must not be split between registers and stack */
818 if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT)
819 && type && !AGGREGATE_TYPE_P (type)
820 && cum->words < GP_ARG_NUM_REG
821 && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
823 cum->words = GP_ARG_NUM_REG;
826 /* Aggregates get passed as pointers */
827 if (type && AGGREGATE_TYPE_P (type))
830 /* Floats go in registers, & don't occupy space in the GP registers
831 like they do for AIX unless software floating point. */
832 else if (GET_MODE_CLASS (mode) == MODE_FLOAT
834 && cum->fregno <= FP_ARG_V4_MAX_REG)
838 cum->words += RS6000_ARG_SIZE (mode, type, 1);
844 cum->words += RS6000_ARG_SIZE (mode, type, named);
845 if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
849 if (TARGET_DEBUG_ARG)
851 "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n",
852 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named);
855 /* Determine where to put an argument to a function.
856 Value is zero to push the argument on the stack,
857 or a hard register in which to store the argument.
859 MODE is the argument's machine mode.
860 TYPE is the data type of the argument (as a tree).
861 This is null for libcalls where that information may
863 CUM is a variable of type CUMULATIVE_ARGS which gives info about
864 the preceding args and about the function being called.
865 NAMED is nonzero if this argument is a named parameter
866 (otherwise it is an extra parameter matching an ellipsis).
868 On RS/6000 the first eight words of non-FP are normally in registers
869 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
870 Under V.4, the first 8 FP args are in registers.
872 If this is floating-point and no prototype is specified, we use
873 both an FP and integer register (or possibly FP reg and stack). Library
874 functions (when TYPE is zero) always have the proper types for args,
875 so we can pass the FP value just in one register. emit_library_function
876 doesn't support EXPR_LIST anyway. */
879 function_arg (cum, mode, type, named)
880 CUMULATIVE_ARGS *cum;
881 enum machine_mode mode;
885 if (TARGET_DEBUG_ARG)
887 "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n",
888 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named);
890 /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4
891 uses to say fp args were passed in registers. Assume that we don't need the
892 marker for software floating point, or compiler generated library calls. */
893 if (mode == VOIDmode)
895 #ifdef TARGET_V4_CALLS
896 if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && cum->nargs_prototype < 0
897 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
898 return GEN_INT ((cum->fregno == FP_ARG_MIN_REG) ? -1 : 1);
906 #ifdef TARGET_V4_CALLS
907 if (!TARGET_V4_CALLS)
912 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
915 if (USE_FP_FOR_ARG_P (*cum, mode, type))
917 if ((cum->nargs_prototype > 0)
918 #ifdef TARGET_V4_CALLS
919 || TARGET_V4_CALLS /* V.4 never passes FP values in GP registers */
922 return gen_rtx (REG, mode, cum->fregno);
924 return gen_rtx (EXPR_LIST, VOIDmode,
925 ((cum->words < GP_ARG_NUM_REG)
926 ? gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words)
928 gen_rtx (REG, mode, cum->fregno));
931 #ifdef TARGET_V4_CALLS
932 /* Long longs won't be split between register and stack */
933 else if (TARGET_V4_CALLS &&
934 cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
940 else if (cum->words < GP_ARG_NUM_REG)
941 return gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words);
946 /* For an arg passed partly in registers and partly in memory,
947 this is the number of registers used.
948 For args passed entirely in registers or entirely in memory, zero. */
951 function_arg_partial_nregs (cum, mode, type, named)
952 CUMULATIVE_ARGS *cum;
953 enum machine_mode mode;
960 #ifdef TARGET_V4_CALLS
965 if (USE_FP_FOR_ARG_P (*cum, mode, type))
967 if (cum->nargs_prototype >= 0)
971 if (cum->words < GP_ARG_NUM_REG
972 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named)))
974 int ret = GP_ARG_NUM_REG - cum->words;
975 if (ret && TARGET_DEBUG_ARG)
976 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
984 /* A C expression that indicates when an argument must be passed by
985 reference. If nonzero for an argument, a copy of that argument is
986 made in memory and a pointer to the argument is passed instead of
987 the argument itself. The pointer is passed in whatever way is
988 appropriate for passing a pointer to that type.
990 Under V.4, structures and unions are passed by reference. */
993 function_arg_pass_by_reference (cum, mode, type, named)
994 CUMULATIVE_ARGS *cum;
995 enum machine_mode mode;
999 #ifdef TARGET_V4_CALLS
1000 if (TARGET_V4_CALLS && type && AGGREGATE_TYPE_P (type))
1002 if (TARGET_DEBUG_ARG)
1003 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
1013 /* Perform any needed actions needed for a function that is receiving a
1014 variable number of arguments.
1018 MODE and TYPE are the mode and type of the current parameter.
1020 PRETEND_SIZE is a variable that should be set to the amount of stack
1021 that must be pushed by the prolog to pretend that our caller pushed
1024 Normally, this macro will push all remaining incoming registers on the
1025 stack and set PRETEND_SIZE to the length of the registers pushed. */
1028 setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1029 CUMULATIVE_ARGS *cum;
1030 enum machine_mode mode;
1036 rtx save_area = virtual_incoming_args_rtx;
1037 int reg_size = (TARGET_64BIT) ? 8 : 4;
1039 if (TARGET_DEBUG_ARG)
1041 "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n",
1042 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl);
1044 #ifdef TARGET_V4_CALLS
1045 if (TARGET_V4_CALLS && !no_rtl)
1047 rs6000_sysv_varargs_p = 1;
1048 save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET);
1054 int first_reg_offset = cum->words;
1056 if (MUST_PASS_IN_STACK (mode, type))
1057 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1);
1059 if (first_reg_offset > GP_ARG_NUM_REG)
1060 first_reg_offset = GP_ARG_NUM_REG;
1062 if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG)
1064 (GP_ARG_MIN_REG + first_reg_offset,
1065 gen_rtx (MEM, BLKmode,
1066 plus_constant (save_area, first_reg_offset * reg_size)),
1067 GP_ARG_NUM_REG - first_reg_offset,
1068 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
1070 *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
1073 #ifdef TARGET_V4_CALLS
1074 /* Save FP registers if needed. */
1075 if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && !no_rtl)
1077 int fregno = cum->fregno;
1078 int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno;
1080 if (num_fp_reg >= 0)
1082 rtx cr1 = gen_rtx (REG, CCmode, 69);
1083 rtx lab = gen_label_rtx ();
1084 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
1086 emit_jump_insn (gen_rtx (SET, VOIDmode,
1088 gen_rtx (IF_THEN_ELSE, VOIDmode,
1089 gen_rtx (NE, VOIDmode, cr1, const0_rtx),
1090 gen_rtx (LABEL_REF, VOIDmode, lab),
1093 while ( num_fp_reg-- >= 0)
1095 emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)),
1096 gen_rtx (REG, DFmode, fregno++));
1106 /* If defined, is a C expression that produces the machine-specific
1107 code for a call to `__builtin_saveregs'. This code will be moved
1108 to the very beginning of the function, before any parameter access
1109 are made. The return value of this function should be an RTX that
1110 contains the value to use as the return of `__builtin_saveregs'.
1112 The argument ARGS is a `tree_list' containing the arguments that
1113 were passed to `__builtin_saveregs'.
1115 If this macro is not defined, the compiler will output an ordinary
1116 call to the library function `__builtin_saveregs'.
1118 On the Power/PowerPC return the address of the area on the stack
1119 used to hold arguments. Under AIX, this includes the 8 word register
1120 save area. Under V.4 this does not. */
1123 expand_builtin_saveregs (args)
1126 return virtual_incoming_args_rtx;
1130 /* Expand a block move operation, and return 1 if successful. Return 0
1131 if we should let the compiler generate normal code.
1133 operands[0] is the destination
1134 operands[1] is the source
1135 operands[2] is the length
1136 operands[3] is the alignment */
1138 #define MAX_MOVE_REG 4
1141 expand_block_move (operands)
1144 rtx bytes_rtx = operands[2];
1145 rtx align_rtx = operands[3];
1146 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
1147 int align = XINT (align_rtx, 0);
1157 rtx stores[MAX_MOVE_REG];
1160 /* If this is not a fixed size move, just call memcpy */
1164 /* Anything to move? */
1165 bytes = INTVAL (bytes_rtx);
1169 /* Don't support real large moves. If string instructions are not used,
1170 then don't generate more than 8 loads. */
1176 else if (!STRICT_ALIGNMENT)
1181 else if (bytes > 8*align)
1184 /* Move the address into scratch registers. */
1185 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
1186 src_reg = copy_addr_to_reg (XEXP (operands[1], 0));
1188 if (TARGET_STRING) /* string instructions are available */
1190 for ( ; bytes > 0; bytes -= move_bytes)
1192 if (bytes > 24 /* move up to 32 bytes at a time */
1202 move_bytes = (bytes > 32) ? 32 : bytes;
1203 emit_insn (gen_movstrsi_8reg (dest_reg,
1205 GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
1208 else if (bytes > 16 /* move up to 24 bytes at a time */
1216 move_bytes = (bytes > 24) ? 24 : bytes;
1217 emit_insn (gen_movstrsi_6reg (dest_reg,
1219 GEN_INT (move_bytes),
1222 else if (bytes > 8 /* move up to 16 bytes at a time */
1228 move_bytes = (bytes > 16) ? 16 : bytes;
1229 emit_insn (gen_movstrsi_4reg (dest_reg,
1231 GEN_INT (move_bytes),
1234 else if (bytes > 4 && !TARGET_64BIT)
1235 { /* move up to 8 bytes at a time */
1236 move_bytes = (bytes > 8) ? 8 : bytes;
1237 emit_insn (gen_movstrsi_2reg (dest_reg,
1239 GEN_INT (move_bytes),
1242 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
1243 { /* move 4 bytes */
1245 tmp_reg = gen_reg_rtx (SImode);
1246 emit_move_insn (tmp_reg, gen_rtx (MEM, SImode, src_reg));
1247 emit_move_insn (gen_rtx (MEM, SImode, dest_reg), tmp_reg);
1249 else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
1250 { /* move 2 bytes */
1252 tmp_reg = gen_reg_rtx (HImode);
1253 emit_move_insn (tmp_reg, gen_rtx (MEM, HImode, src_reg));
1254 emit_move_insn (gen_rtx (MEM, HImode, dest_reg), tmp_reg);
1256 else if (bytes == 1) /* move 1 byte */
1259 tmp_reg = gen_reg_rtx (QImode);
1260 emit_move_insn (tmp_reg, gen_rtx (MEM, QImode, src_reg));
1261 emit_move_insn (gen_rtx (MEM, QImode, dest_reg), tmp_reg);
1264 { /* move up to 4 bytes at a time */
1265 move_bytes = (bytes > 4) ? 4 : bytes;
1266 emit_insn (gen_movstrsi_1reg (dest_reg,
1268 GEN_INT (move_bytes),
1272 if (bytes > move_bytes)
1274 emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
1275 emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
1280 else /* string instructions not available */
1282 num_reg = offset = 0;
1283 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
1285 /* Calculate the correct offset for src/dest */
1289 dest_addr = dest_reg;
1293 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
1294 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
1297 /* Generate the appropriate load and store, saving the stores for later */
1298 if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
1301 tmp_reg = gen_reg_rtx (SImode);
1302 emit_insn (gen_movsi (tmp_reg, gen_rtx (MEM, SImode, src_addr)));
1303 stores[ num_reg++ ] = gen_movsi (gen_rtx (MEM, SImode, dest_addr), tmp_reg);
1305 else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
1308 tmp_reg = gen_reg_rtx (HImode);
1309 emit_insn (gen_movhi (tmp_reg, gen_rtx (MEM, HImode, src_addr)));
1310 stores[ num_reg++ ] = gen_movhi (gen_rtx (MEM, HImode, dest_addr), tmp_reg);
1315 tmp_reg = gen_reg_rtx (QImode);
1316 emit_insn (gen_movqi (tmp_reg, gen_rtx (MEM, QImode, src_addr)));
1317 stores[ num_reg++ ] = gen_movqi (gen_rtx (MEM, QImode, dest_addr), tmp_reg);
1320 if (num_reg >= MAX_MOVE_REG)
1322 for (i = 0; i < num_reg; i++)
1323 emit_insn (stores[i]);
1330 for (i = 0; i < num_reg; i++)
1331 emit_insn (stores[i]);
1339 /* Return 1 if OP is a load multiple operation. It is known to be a
1340 PARALLEL and the first section will be tested. */
1343 load_multiple_operation (op, mode)
1345 enum machine_mode mode;
1347 int count = XVECLEN (op, 0);
1352 /* Perform a quick check so we don't blow up below. */
1354 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1355 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1356 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1359 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1360 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1362 for (i = 1; i < count; i++)
1364 rtx elt = XVECEXP (op, 0, i);
1366 if (GET_CODE (elt) != SET
1367 || GET_CODE (SET_DEST (elt)) != REG
1368 || GET_MODE (SET_DEST (elt)) != SImode
1369 || REGNO (SET_DEST (elt)) != dest_regno + i
1370 || GET_CODE (SET_SRC (elt)) != MEM
1371 || GET_MODE (SET_SRC (elt)) != SImode
1372 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1373 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1374 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1375 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1382 /* Similar, but tests for store multiple. Here, the second vector element
1383 is a CLOBBER. It will be tested later. */
1386 store_multiple_operation (op, mode)
1388 enum machine_mode mode;
1390 int count = XVECLEN (op, 0) - 1;
1395 /* Perform a quick check so we don't blow up below. */
1397 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1398 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1399 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1402 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1403 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1405 for (i = 1; i < count; i++)
1407 rtx elt = XVECEXP (op, 0, i + 1);
1409 if (GET_CODE (elt) != SET
1410 || GET_CODE (SET_SRC (elt)) != REG
1411 || GET_MODE (SET_SRC (elt)) != SImode
1412 || REGNO (SET_SRC (elt)) != src_regno + i
1413 || GET_CODE (SET_DEST (elt)) != MEM
1414 || GET_MODE (SET_DEST (elt)) != SImode
1415 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1416 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1417 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1418 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1425 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
1426 We only check the opcode against the mode of the CC value here. */
1429 branch_comparison_operator (op, mode)
1431 enum machine_mode mode;
1433 enum rtx_code code = GET_CODE (op);
1434 enum machine_mode cc_mode;
1436 if (GET_RTX_CLASS (code) != '<')
1439 cc_mode = GET_MODE (XEXP (op, 0));
1440 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1443 if ((code == GT || code == LT || code == GE || code == LE)
1444 && cc_mode == CCUNSmode)
1447 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1448 && (cc_mode != CCUNSmode))
1454 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
1455 We check the opcode against the mode of the CC value and disallow EQ or
1456 NE comparisons for integers. */
1459 scc_comparison_operator (op, mode)
1461 enum machine_mode mode;
1463 enum rtx_code code = GET_CODE (op);
1464 enum machine_mode cc_mode;
1466 if (GET_MODE (op) != mode && mode != VOIDmode)
1469 if (GET_RTX_CLASS (code) != '<')
1472 cc_mode = GET_MODE (XEXP (op, 0));
1473 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1476 if (code == NE && cc_mode != CCFPmode)
1479 if ((code == GT || code == LT || code == GE || code == LE)
1480 && cc_mode == CCUNSmode)
1483 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1484 && (cc_mode != CCUNSmode))
1487 if (cc_mode == CCEQmode && code != EQ && code != NE)
1493 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
1494 mask required to convert the result of a rotate insn into a shift
1495 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
1498 includes_lshift_p (shiftop, andop)
1499 register rtx shiftop;
1502 int shift_mask = (~0 << INTVAL (shiftop));
1504 return (INTVAL (andop) & ~shift_mask) == 0;
1507 /* Similar, but for right shift. */
1510 includes_rshift_p (shiftop, andop)
1511 register rtx shiftop;
1514 unsigned shift_mask = ~0;
1516 shift_mask >>= INTVAL (shiftop);
1518 return (INTVAL (andop) & ~ shift_mask) == 0;
1521 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
1522 for lfq and stfq insns.
1524 Note reg1 and reg2 *must* be hard registers. To be sure we will
1525 abort if we are passed pseudo registers. */
1528 registers_ok_for_quad_peep (reg1, reg2)
1531 /* We might have been passed a SUBREG. */
1532 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
1535 return (REGNO (reg1) == REGNO (reg2) - 1);
1538 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
1539 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
1542 addrs_ok_for_quad_peep (addr1, addr2)
1549 /* Extract an offset (if used) from the first addr. */
1550 if (GET_CODE (addr1) == PLUS)
1552 /* If not a REG, return zero. */
1553 if (GET_CODE (XEXP (addr1, 0)) != REG)
1557 reg1 = REGNO (XEXP (addr1, 0));
1558 /* The offset must be constant! */
1559 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
1561 offset1 = INTVAL (XEXP (addr1, 1));
1564 else if (GET_CODE (addr1) != REG)
1568 reg1 = REGNO (addr1);
1569 /* This was a simple (mem (reg)) expression. Offset is 0. */
1573 /* Make sure the second address is a (mem (plus (reg) (const_int). */
1574 if (GET_CODE (addr2) != PLUS)
1577 if (GET_CODE (XEXP (addr2, 0)) != REG
1578 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
1581 if (reg1 != REGNO (XEXP (addr2, 0)))
1584 /* The offset for the second addr must be 8 more than the first addr. */
1585 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
1588 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
1593 /* Return the register class of a scratch register needed to copy IN into
1594 or out of a register in CLASS in MODE. If it can be done directly,
1595 NO_REGS is returned. */
1598 secondary_reload_class (class, mode, in)
1599 enum reg_class class;
1600 enum machine_mode mode;
1603 int regno = true_regnum (in);
1605 if (regno >= FIRST_PSEUDO_REGISTER)
1608 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
1610 if (class == GENERAL_REGS || class == BASE_REGS
1611 || (regno >= 0 && INT_REGNO_P (regno)))
1614 /* Constants, memory, and FP registers can go into FP registers. */
1615 if ((regno == -1 || FP_REGNO_P (regno))
1616 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
1619 /* We can copy among the CR registers. */
1620 if ((class == CR_REGS || class == CR0_REGS)
1621 && regno >= 0 && CR_REGNO_P (regno))
1624 /* Otherwise, we need GENERAL_REGS. */
1625 return GENERAL_REGS;
1628 /* Given a comparison operation, return the bit number in CCR to test. We
1629 know this is a valid comparison.
1631 SCC_P is 1 if this is for an scc. That means that %D will have been
1632 used instead of %C, so the bits will be in different places.
1634 Return -1 if OP isn't a valid comparison for some reason. */
1641 enum rtx_code code = GET_CODE (op);
1642 enum machine_mode cc_mode;
1646 if (GET_RTX_CLASS (code) != '<')
1649 cc_mode = GET_MODE (XEXP (op, 0));
1650 cc_regnum = REGNO (XEXP (op, 0));
1651 base_bit = 4 * (cc_regnum - 68);
1653 /* In CCEQmode cases we have made sure that the result is always in the
1654 third bit of the CR field. */
1656 if (cc_mode == CCEQmode)
1657 return base_bit + 3;
1662 return scc_p ? base_bit + 3 : base_bit + 2;
1664 return base_bit + 2;
1666 return base_bit + 1;
1671 /* If floating-point, we will have done a cror to put the bit in the
1672 unordered position. So test that bit. For integer, this is ! LT
1673 unless this is an scc insn. */
1674 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
1677 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
1684 /* Print an operand. Recognize special options, documented below. */
1687 print_operand (file, x, code)
1695 /* These macros test for integers and extract the low-order bits. */
1697 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
1698 && GET_MODE (X) == VOIDmode)
1700 #define INT_LOWPART(X) \
1701 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
1706 /* Write out an instruction after the call which may be replaced
1707 with glue code by the loader. This depends on the AIX version. */
1708 asm_fprintf (file, RS6000_CALL_GLUE);
1712 /* Write the register number of the TOC register. */
1713 fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file);
1717 /* If X is a constant integer whose low-order 5 bits are zero,
1718 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
1719 in the AIX assembler where "sri" with a zero shift count
1720 write a trash instruction. */
1721 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
1728 /* Low-order 16 bits of constant, unsigned. */
1730 output_operand_lossage ("invalid %%b value");
1732 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1736 /* This is an optional cror needed for LE or GE floating-point
1737 comparisons. Otherwise write nothing. */
1738 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
1739 && GET_MODE (XEXP (x, 0)) == CCFPmode)
1741 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1743 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1744 base_bit + 2, base_bit + (GET_CODE (x) == GE));
1749 /* Similar, except that this is for an scc, so we must be able to
1750 encode the test in a single bit that is one. We do the above
1751 for any LE, GE, GEU, or LEU and invert the bit for NE. */
1752 if (GET_CODE (x) == LE || GET_CODE (x) == GE
1753 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
1755 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1757 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1759 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
1762 else if (GET_CODE (x) == NE)
1764 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1766 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
1767 base_bit + 2, base_bit + 2);
1772 /* X is a CR register. Print the number of the third bit of the CR */
1773 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1774 output_operand_lossage ("invalid %%E value");
1776 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
1780 /* X is a CR register. Print the shift count needed to move it
1781 to the high-order four bits. */
1782 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1783 output_operand_lossage ("invalid %%f value");
1785 fprintf (file, "%d", 4 * (REGNO (x) - 68));
1789 /* Similar, but print the count for the rotate in the opposite
1791 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1792 output_operand_lossage ("invalid %%F value");
1794 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
1798 /* X is a constant integer. If it is negative, print "m",
1799 otherwise print "z". This is to make a aze or ame insn. */
1800 if (GET_CODE (x) != CONST_INT)
1801 output_operand_lossage ("invalid %%G value");
1802 else if (INTVAL (x) >= 0)
1809 /* If constant, output low-order five bits. Otherwise,
1812 fprintf (file, "%d", INT_LOWPART (x) & 31);
1814 print_operand (file, x, 0);
1818 /* Print `i' if this is a constant, else nothing. */
1824 /* Write the bit number in CCR for jump. */
1827 output_operand_lossage ("invalid %%j code");
1829 fprintf (file, "%d", i);
1833 /* Similar, but add one for shift count in rlinm for scc and pass
1834 scc flag to `ccr_bit'. */
1837 output_operand_lossage ("invalid %%J code");
1839 /* If we want bit 31, write a shift count of zero, not 32. */
1840 fprintf (file, "%d", i == 31 ? 0 : i + 1);
1844 /* X must be a constant. Write the 1's complement of the
1847 output_operand_lossage ("invalid %%k value");
1849 fprintf (file, "%d", ~ INT_LOWPART (x));
1853 /* Write second word of DImode or DFmode reference. Works on register
1854 or non-indexed memory only. */
1855 if (GET_CODE (x) == REG)
1856 fprintf (file, "%d", REGNO (x) + 1);
1857 else if (GET_CODE (x) == MEM)
1859 /* Handle possible auto-increment. Since it is pre-increment and
1860 we have already done it, we can just use an offset of four. */
1861 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1862 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1863 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1865 output_address (plus_constant (XEXP (x, 0), 4));
1870 /* MB value for a mask operand. */
1871 if (! mask_operand (x, VOIDmode))
1872 output_operand_lossage ("invalid %%m value");
1874 val = INT_LOWPART (x);
1876 /* If the high bit is set and the low bit is not, the value is zero.
1877 If the high bit is zero, the value is the first 1 bit we find from
1879 if (val < 0 && (val & 1) == 0)
1881 fprintf (file, "0");
1886 for (i = 1; i < 32; i++)
1887 if ((val <<= 1) < 0)
1889 fprintf (file, "%d", i);
1893 /* Otherwise, look for the first 0 bit from the right. The result is its
1894 number plus 1. We know the low-order bit is one. */
1895 for (i = 0; i < 32; i++)
1896 if (((val >>= 1) & 1) == 0)
1899 /* If we ended in ...01, I would be 0. The correct value is 31, so
1901 fprintf (file, "%d", 31 - i);
1905 /* ME value for a mask operand. */
1906 if (! mask_operand (x, VOIDmode))
1907 output_operand_lossage ("invalid %%m value");
1909 val = INT_LOWPART (x);
1911 /* If the low bit is set and the high bit is not, the value is 31.
1912 If the low bit is zero, the value is the first 1 bit we find from
1914 if ((val & 1) && val >= 0)
1919 else if ((val & 1) == 0)
1921 for (i = 0; i < 32; i++)
1922 if ((val >>= 1) & 1)
1925 /* If we had ....10, I would be 0. The result should be
1926 30, so we need 30 - i. */
1927 fprintf (file, "%d", 30 - i);
1931 /* Otherwise, look for the first 0 bit from the left. The result is its
1932 number minus 1. We know the high-order bit is one. */
1933 for (i = 0; i < 32; i++)
1934 if ((val <<= 1) >= 0)
1937 fprintf (file, "%d", i);
1941 /* Write the number of elements in the vector times 4. */
1942 if (GET_CODE (x) != PARALLEL)
1943 output_operand_lossage ("invalid %%N value");
1945 fprintf (file, "%d", XVECLEN (x, 0) * 4);
1949 /* Similar, but subtract 1 first. */
1950 if (GET_CODE (x) != PARALLEL)
1951 output_operand_lossage ("invalid %%N value");
1953 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
1957 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1959 || (i = exact_log2 (INT_LOWPART (x))) < 0)
1960 output_operand_lossage ("invalid %%p value");
1962 fprintf (file, "%d", i);
1966 /* The operand must be an indirect memory reference. The result
1967 is the register number. */
1968 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
1969 || REGNO (XEXP (x, 0)) >= 32)
1970 output_operand_lossage ("invalid %%P value");
1972 fprintf (file, "%d", REGNO (XEXP (x, 0)));
1976 /* X is a CR register. Print the mask for `mtcrf'. */
1977 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1978 output_operand_lossage ("invalid %%R value");
1980 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
1984 /* Low 5 bits of 32 - value */
1986 output_operand_lossage ("invalid %%s value");
1988 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
1992 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1993 All floating-point operations except NE branch true and integer
1994 EQ, LT, GT, LTU and GTU also branch true. */
1995 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1996 output_operand_lossage ("invalid %%t value");
1998 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1999 && GET_CODE (x) != NE)
2000 || GET_CODE (x) == EQ
2001 || GET_CODE (x) == LT || GET_CODE (x) == GT
2002 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
2009 /* Opposite of 't': write 4 if this jump operation will branch if true,
2011 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
2012 output_operand_lossage ("invalid %%t value");
2014 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
2015 && GET_CODE (x) != NE)
2016 || GET_CODE (x) == EQ
2017 || GET_CODE (x) == LT || GET_CODE (x) == GT
2018 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
2025 /* High-order 16 bits of constant. */
2027 output_operand_lossage ("invalid %%u value");
2029 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
2033 /* Print `u' if this has an auto-increment or auto-decrement. */
2034 if (GET_CODE (x) == MEM
2035 && (GET_CODE (XEXP (x, 0)) == PRE_INC
2036 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
2041 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
2044 fprintf (file, "%d",
2045 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
2047 print_operand (file, x, 0);
2051 /* If constant, low-order 16 bits of constant, unsigned.
2052 Otherwise, write normally. */
2054 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
2056 print_operand (file, x, 0);
2060 if (GET_CODE (x) == MEM
2061 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
2066 /* Like 'L', for third word of TImode */
2067 if (GET_CODE (x) == REG)
2068 fprintf (file, "%d", REGNO (x) + 2);
2069 else if (GET_CODE (x) == MEM)
2071 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2072 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2073 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
2075 output_address (plus_constant (XEXP (x, 0), 8));
2080 /* X is a SYMBOL_REF. Write out the name preceded by a
2081 period and without any trailing data in brackets. Used for function
2082 names. If we are configured for System V (or the embedded ABI) on
2083 the PowerPC, do not emit the period, since those systems do not use
2084 TOCs and the like. */
2085 if (GET_CODE (x) != SYMBOL_REF)
2088 #ifndef USING_SVR4_H
2091 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
2095 /* Like 'L', for last word of TImode. */
2096 if (GET_CODE (x) == REG)
2097 fprintf (file, "%d", REGNO (x) + 3);
2098 else if (GET_CODE (x) == MEM)
2100 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2101 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2102 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
2104 output_address (plus_constant (XEXP (x, 0), 12));
2109 if (GET_CODE (x) == REG)
2110 fprintf (file, "%s", reg_names[REGNO (x)]);
2111 else if (GET_CODE (x) == MEM)
2113 /* We need to handle PRE_INC and PRE_DEC here, since we need to
2114 know the width from the mode. */
2115 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
2116 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
2117 REGNO (XEXP (XEXP (x, 0), 0)));
2118 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
2119 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
2120 REGNO (XEXP (XEXP (x, 0), 0)));
2122 output_address (XEXP (x, 0));
2125 output_addr_const (file, x);
2129 output_operand_lossage ("invalid %%xn code");
2133 /* Print the address of an operand. */
2136 print_operand_address (file, x)
2140 if (GET_CODE (x) == REG)
2141 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
2142 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2144 output_addr_const (file, x);
2145 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
2146 of the toc pointer. */
2147 #ifdef TARGET_NO_TOC
2152 fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]);
2154 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
2156 if (REGNO (XEXP (x, 0)) == 0)
2157 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
2158 reg_names[ REGNO (XEXP (x, 0)) ]);
2160 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
2161 reg_names[ REGNO (XEXP (x, 1)) ]);
2163 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
2164 fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
2165 else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM
2166 && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1)))
2168 output_addr_const (file, XEXP (x, 1));
2169 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
2175 /* This page contains routines that are used to determine what the function
2176 prologue and epilogue code will do and write them out. */
2178 /* Return the first fixed-point register that is required to be saved. 32 if
2182 first_reg_to_save ()
2186 /* Find lowest numbered live register. */
2187 for (first_reg = 13; first_reg <= 31; first_reg++)
2188 if (regs_ever_live[first_reg])
2191 /* If profiling, then we must save/restore every register that contains
2192 a parameter before/after the .mcount call. Use registers from 30 down
2193 to 23 to do this. Don't use the frame pointer in reg 31.
2195 For now, save enough room for all of the parameter registers. */
2196 #ifndef USING_SVR4_H
2205 /* Similar, for FP regs. */
2208 first_fp_reg_to_save ()
2212 /* Find lowest numbered live register. */
2213 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
2214 if (regs_ever_live[first_reg])
2220 /* Return non-zero if this function makes calls. */
2223 rs6000_makes_calls ()
2227 /* If we are profiling, we will be making a call to mcount. */
2231 for (insn = get_insns (); insn; insn = next_insn (insn))
2232 if (GET_CODE (insn) == CALL_INSN)
2239 /* Calculate the stack information for the current function. This is
2240 complicated by having two separate calling sequences, the AIX calling
2241 sequence and the V.4 calling sequence.
2243 AIX stack frames look like:
2245 SP----> +---------------------------------------+
2246 | back chain to caller | 0
2247 +---------------------------------------+
2249 +---------------------------------------+
2251 +---------------------------------------+
2252 | reserved for compilers | 12
2253 +---------------------------------------+
2254 | reserved for binders | 16
2255 +---------------------------------------+
2256 | saved TOC pointer | 20
2257 +---------------------------------------+
2258 | Parameter save area (P) | 24
2259 +---------------------------------------+
2260 | Alloca space (A) | 24+P
2261 +---------------------------------------+
2262 | Local variable space (L) | 24+P+A
2263 +---------------------------------------+
2264 | Save area for GP registers (G) | 24+P+A+L
2265 +---------------------------------------+
2266 | Save area for FP registers (F) | 24+P+A+L+G
2267 +---------------------------------------+
2268 old SP->| back chain to caller's caller |
2269 +---------------------------------------+
2271 V.4 stack frames look like:
2273 SP----> +---------------------------------------+
2274 | back chain to caller | 0
2275 +---------------------------------------+
2276 | caller's saved LR | 4
2277 +---------------------------------------+
2278 | Parameter save area (P) | 8
2279 +---------------------------------------+
2280 | Alloca space (A) | 8+P
2281 +---------------------------------------+
2282 | Varargs save area (V) | 8+P+A
2283 +---------------------------------------+
2284 | Local variable space (L) | 8+P+A+V
2285 +---------------------------------------+
2286 | saved CR (C) | 8+P+A+V+L
2287 +---------------------------------------+
2288 | Save area for GP registers (G) | 8+P+A+V+L+C
2289 +---------------------------------------+
2290 | Save area for FP registers (F) | 8+P+A+V+L+C+G
2291 +---------------------------------------+
2292 old SP->| back chain to caller's caller |
2293 +---------------------------------------+
2297 rs6000_stack_info ()
2299 static rs6000_stack_t info, zero_info;
2300 rs6000_stack_t *info_ptr = &info;
2301 int reg_size = TARGET_64BIT ? 8 : 4;
2302 enum rs6000_abi abi;
2304 /* Zero all fields portably */
2307 /* Select which calling sequence */
2308 #ifdef TARGET_V4_CALLS
2309 if (TARGET_V4_CALLS)
2315 info_ptr->abi = abi;
2317 /* Calculate which registers need to be saved & save area size */
2318 info_ptr->first_gp_reg_save = first_reg_to_save ();
2319 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
2321 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
2322 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
2324 /* Does this function call anything? */
2325 info_ptr->calls_p = rs6000_makes_calls ();
2327 /* Determine if we need to save the link register */
2328 if (regs_ever_live[65] || profile_flag
2329 #ifdef TARGET_RELOCATABLE
2330 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
2332 || (info_ptr->first_fp_reg_save != 64
2333 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
2334 || (abi == ABI_V4 && current_function_calls_alloca)
2335 || info_ptr->calls_p)
2337 info_ptr->lr_save_p = 1;
2338 regs_ever_live[65] = 1;
2341 /* Determine if we need to save the condition code registers */
2342 if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72])
2344 info_ptr->cr_save_p = 1;
2346 info_ptr->cr_size = reg_size;
2349 /* Determine various sizes */
2350 info_ptr->reg_size = reg_size;
2351 info_ptr->fixed_size = RS6000_SAVE_AREA;
2352 info_ptr->varargs_size = RS6000_VARARGS_AREA;
2353 info_ptr->vars_size = ALIGN (get_frame_size (), 8);
2354 info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8);
2355 info_ptr->save_size = ALIGN (info_ptr->fp_size + info_ptr->gp_size + info_ptr->cr_size, 8);
2356 info_ptr->total_size = ALIGN (info_ptr->vars_size
2357 + info_ptr->parm_size
2358 + info_ptr->save_size
2359 + info_ptr->varargs_size
2360 + info_ptr->fixed_size, STACK_BOUNDARY / BITS_PER_UNIT);
2362 /* Determine if we need to allocate any stack frame.
2363 For AIX We need to push the stack if a frame pointer is needed (because
2364 the stack might be dynamically adjusted), if we are debugging, if the
2365 total stack size is more than 220 bytes, or if we make calls.
2367 For V.4 we don't have the stack cushion that AIX uses, but assume that
2368 the debugger can handle stackless frames. */
2370 if (info_ptr->calls_p)
2371 info_ptr->push_p = 1;
2373 else if (abi == ABI_V4)
2374 info_ptr->push_p = (info_ptr->total_size > info_ptr->fixed_size
2375 || info_ptr->lr_save_p);
2378 info_ptr->push_p = (frame_pointer_needed
2379 || write_symbols != NO_DEBUG
2380 || info_ptr->total_size > 220);
2382 /* Calculate the offsets */
2383 info_ptr->fp_save_offset = - info_ptr->fp_size;
2384 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
2388 info_ptr->cr_save_offset = 4;
2389 info_ptr->lr_save_offset = 8;
2393 info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size;
2394 info_ptr->lr_save_offset = reg_size;
2398 /* Zero offsets if we're not saving those registers */
2399 if (!info_ptr->fp_size)
2400 info_ptr->fp_save_offset = 0;
2402 if (!info_ptr->gp_size)
2403 info_ptr->gp_save_offset = 0;
2405 if (!info_ptr->lr_save_p)
2406 info_ptr->lr_save_offset = 0;
2408 if (!info_ptr->cr_save_p)
2409 info_ptr->cr_save_offset = 0;
2415 debug_stack_info (info)
2416 rs6000_stack_t *info;
2421 info = rs6000_stack_info ();
2423 fprintf (stderr, "\nStack information for function %s:\n",
2424 ((current_function_decl && DECL_NAME (current_function_decl))
2425 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
2430 default: abi_string = "Unknown"; break;
2431 case ABI_NONE: abi_string = "NONE"; break;
2432 case ABI_AIX: abi_string = "AIX"; break;
2433 case ABI_V4: abi_string = "V.4"; break;
2436 fprintf (stderr, "\tABI = %5s\n", abi_string);
2438 if (info->first_gp_reg_save != 32)
2439 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
2441 if (info->first_fp_reg_save != 64)
2442 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
2444 if (info->lr_save_p)
2445 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
2447 if (info->cr_save_p)
2448 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
2451 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
2454 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
2456 if (info->gp_save_offset)
2457 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
2459 if (info->fp_save_offset)
2460 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
2462 if (info->lr_save_offset)
2463 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
2465 if (info->cr_save_offset)
2466 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
2468 if (info->varargs_save_offset)
2469 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
2471 if (info->total_size)
2472 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
2474 if (info->varargs_size)
2475 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
2477 if (info->vars_size)
2478 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
2480 if (info->parm_size)
2481 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
2483 if (info->fixed_size)
2484 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
2487 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
2490 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
2493 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
2495 if (info->save_size)
2496 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
2498 if (info->reg_size != 4)
2499 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
2501 fprintf (stderr, "\n");
2507 /* Write out a System V.4 style traceback table before the prologue
2509 At present, only emit the basic tag table (ie, do not emit tag_types other
2510 than 0, which might use more than 1 tag word).
2512 The first tag word looks like:
2515 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
2516 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2517 | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f|
2518 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2523 svr4_traceback (file, name, decl)
2527 rs6000_stack_t *info = rs6000_stack_info ();
2529 long version = 0; /* version number */
2530 long tag_type = 0; /* function type */
2531 long extended_tag = 0; /* additional tag words needed */
2532 long spare = 0; /* reserved for future use */
2533 long fpscr_max = 0; /* 1 if the function has a FPSCR save word */
2534 long fpr_max = 64 - info->first_fp_reg_save; /* # of floating point registers saved */
2535 long gpr_max = 32 - info->first_gp_reg_save; /* # of general purpose registers saved */
2536 long alloca_reg; /* stack/frame register */
2538 if (frame_pointer_needed)
2541 else if (info->push_p != 0)
2547 tag = ((version << 24)
2549 | (extended_tag << 20)
2551 | (alloca_reg << 14)
2554 | (info->push_p << 3)
2555 | (info->lr_save_p << 2)
2556 | (info->cr_save_p << 1)
2557 | (fpscr_max << 0));
2559 fprintf (file, "\t.long 0x%lx\n", tag);
2562 #endif /* USING_SVR4_H */
2564 /* Write function prologue. */
2566 output_prolog (file, size)
2570 rs6000_stack_t *info = rs6000_stack_info ();
2571 char *store_reg = (TARGET_64BIT) ? "\tstd %s,%d(%s)" : "\t{st|stw} %s,%d(%s)\n";
2573 if (TARGET_DEBUG_STACK)
2574 debug_stack_info (info);
2576 /* Write .extern for any function we will call to save and restore fp
2578 #ifndef USING_SVR4_H
2579 if (info->first_fp_reg_save < 62)
2580 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
2581 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
2582 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
2585 /* Write .extern for truncation routines, if needed. */
2586 if (rs6000_trunc_used && ! trunc_defined)
2588 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
2589 RS6000_ITRUNC, RS6000_UITRUNC);
2593 /* Write .extern for AIX common mode routines, if needed. */
2594 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
2596 fputs ("\t.extern __mulh\n", file);
2597 fputs ("\t.extern __mull\n", file);
2598 fputs ("\t.extern __divss\n", file);
2599 fputs ("\t.extern __divus\n", file);
2600 fputs ("\t.extern __quoss\n", file);
2601 fputs ("\t.extern __quous\n", file);
2602 common_mode_defined = 1;
2605 /* If we use the link register, get it into r0. */
2606 if (info->lr_save_p)
2607 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
2609 /* If we need to save CR, put it into r12. */
2610 if (info->cr_save_p)
2611 asm_fprintf (file, "\tmfcr %s\n", reg_names[12]);
2613 /* Do any required saving of fpr's. If only one or two to save, do it
2614 ourself. Otherwise, call function. Note that since they are statically
2615 linked, we do not need a nop following them. */
2616 if (FP_SAVE_INLINE (info->first_fp_reg_save))
2618 int regno = info->first_fp_reg_save;
2619 int loc = info->fp_save_offset;
2621 for ( ; regno < 64; regno++, loc += 8)
2622 asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]);
2624 else if (info->first_fp_reg_save != 64)
2625 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX,
2626 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
2628 /* Now save gpr's. */
2629 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
2631 int regno = info->first_gp_reg_save;
2632 int loc = info->gp_save_offset;
2633 int reg_size = (TARGET_64BIT) ? 8 : 4;
2635 for ( ; regno < 32; regno++, loc += reg_size)
2636 asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[1]);
2639 else if (info->first_gp_reg_save != 32)
2640 asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n",
2641 reg_names[info->first_gp_reg_save],
2642 info->gp_save_offset,
2645 /* Save lr if we used it. */
2646 if (info->lr_save_p)
2647 asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset, reg_names[1]);
2649 /* Save CR if we use any that must be preserved. */
2650 if (info->cr_save_p)
2651 asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset, reg_names[1]);
2653 /* Update stack and set back pointer. */
2656 if (info->total_size < 32767)
2658 (TARGET_64BIT) ? "\tstdu %s,%d(%s)\n" : "\t{stu|stwu} %s,%d(%s)\n",
2659 reg_names[1], - info->total_size, reg_names[1]);
2662 int neg_size = - info->total_size;
2663 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
2664 reg_names[0], (neg_size >> 16) & 0xffff,
2665 reg_names[0], reg_names[0], neg_size & 0xffff);
2667 (TARGET_64BIT) ? "\tstdux %s,%s,%s\n" : "\t{stux|stwux} %s,%s,%s\n",
2668 reg_names[1], reg_names[1], reg_names[0]);
2672 /* Set frame pointer, if needed. */
2673 if (frame_pointer_needed)
2674 asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]);
2676 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
2677 TOC_TABLE address into register 30. */
2678 if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
2683 if (TARGET_RELOCATABLE)
2685 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
2686 fprintf (file, "\tbl ");
2687 assemble_name (file, buf);
2688 fprintf (file, "\n");
2690 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
2691 fprintf (file, "\tmflr %s\n", reg_names[30]);
2693 if (TARGET_POWERPC64)
2694 fprintf (file, "\tld");
2695 else if (TARGET_NEW_MNEMONICS)
2696 fprintf (file, "\tlwz");
2698 fprintf (file, "\tl");
2700 fprintf (file, " %s,(", reg_names[0]);
2701 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
2702 assemble_name (file, buf);
2703 fprintf (file, "-");
2704 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
2705 assemble_name (file, buf);
2706 fprintf (file, ")(%s)\n", reg_names[30]);
2707 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
2708 reg_names[30], reg_names[0], reg_names[30]);
2709 rs6000_pic_labelno++;
2711 else if (!TARGET_64BIT)
2713 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
2714 asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]);
2715 assemble_name (file, buf);
2716 asm_fprintf (file, "@ha\n");
2717 if (TARGET_NEW_MNEMONICS)
2719 asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]);
2720 assemble_name (file, buf);
2721 asm_fprintf (file, "@l\n");
2725 asm_fprintf (file, "\tcal %s,", reg_names[30]);
2726 assemble_name (file, buf);
2727 asm_fprintf (file, "@l(%s)\n", reg_names[30]);
2733 #else /* !USING_SVR4_H */
2734 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
2735 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]);
2736 assemble_name (file, buf);
2737 asm_fprintf (file, "(%s)\n", reg_names[2]);
2738 #endif /* USING_SVR4_H */
2742 /* Write function epilogue. */
2745 output_epilog (file, size)
2749 rs6000_stack_t *info = rs6000_stack_info ();
2750 char *load_reg = (TARGET_64BIT) ? "\tld %s,%d(%s)" : "\t{l|lwz} %s,%d(%s)\n";
2751 rtx insn = get_last_insn ();
2753 /* If the last insn was a BARRIER, we don't have to write anything except
2755 if (GET_CODE (insn) == NOTE)
2756 insn = prev_nonnote_insn (insn);
2757 if (insn == 0 || GET_CODE (insn) != BARRIER)
2759 /* If we have a frame pointer, a call to alloca, or a large stack
2760 frame, restore the old stack pointer using the backchain. Otherwise,
2761 we know what size to update it with. */
2762 if (frame_pointer_needed || current_function_calls_alloca
2763 || info->total_size > 32767)
2764 asm_fprintf (file, load_reg, reg_names[1], 0, reg_names[1]);
2765 else if (info->push_p)
2767 if (TARGET_NEW_MNEMONICS)
2768 asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size);
2770 asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]);
2773 /* Get the old lr if we saved it. */
2774 if (info->lr_save_p)
2775 asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset, reg_names[1]);
2777 /* Get the old cr if we saved it. */
2778 if (info->cr_save_p)
2779 asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset, reg_names[1]);
2781 /* Set LR here to try to overlap restores below. */
2782 if (info->lr_save_p)
2783 asm_fprintf (file, "\tmtlr %s\n", reg_names[0]);
2785 /* Restore gpr's. */
2786 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
2788 int regno = info->first_gp_reg_save;
2789 int loc = info->gp_save_offset;
2790 int reg_size = (TARGET_64BIT) ? 8 : 4;
2792 for ( ; regno < 32; regno++, loc += reg_size)
2793 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]);
2796 else if (info->first_gp_reg_save != 32)
2797 asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n",
2798 reg_names[info->first_gp_reg_save],
2799 info->gp_save_offset,
2802 /* Restore fpr's if we can do it without calling a function. */
2803 if (FP_SAVE_INLINE (info->first_fp_reg_save))
2805 int regno = info->first_fp_reg_save;
2806 int loc = info->fp_save_offset;
2808 for ( ; regno < 64; regno++, loc += 8)
2809 asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]);
2812 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
2814 if (info->cr_save_p)
2815 asm_fprintf (file, "\tmtcrf %d,%s\n",
2816 (regs_ever_live[70] != 0) * 0x20
2817 + (regs_ever_live[71] != 0) * 0x10
2818 + (regs_ever_live[72] != 0) * 0x8, reg_names[12]);
2820 /* If we have to restore more than two FP registers, branch to the
2821 restore function. It will return to our caller. */
2822 if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
2823 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX,
2824 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
2826 asm_fprintf (file, "\t{br|blr}\n");
2829 /* Output a traceback table here. See /usr/include/sys/debug.h for info
2832 We don't output a traceback table if -finhibit-size-directive was
2833 used. The documentation for -finhibit-size-directive reads
2834 ``don't output a @code{.size} assembler directive, or anything
2835 else that would cause trouble if the function is split in the
2836 middle, and the two halves are placed at locations far apart in
2837 memory.'' The traceback table has this property, since it
2838 includes the offset from the start of the function to the
2839 traceback table itself.
2841 System V.4 Powerpc's (and the embedded ABI derived from it) use a
2842 different traceback table located before the prologue. */
2843 #ifndef USING_SVR4_H
2844 if (! flag_inhibit_size_directive)
2846 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
2847 int fixed_parms, float_parms, parm_info;
2850 /* Need label immediately before tbtab, so we can compute its offset
2851 from the function start. */
2854 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2855 ASM_OUTPUT_LABEL (file, fname);
2857 /* The .tbtab pseudo-op can only be used for the first eight
2858 expressions, since it can't handle the possibly variable
2859 length fields that follow. However, if you omit the optional
2860 fields, the assembler outputs zeros for all optional fields
2861 anyways, giving each variable length field is minimum length
2862 (as defined in sys/debug.h). Thus we can not use the .tbtab
2863 pseudo-op at all. */
2865 /* An all-zero word flags the start of the tbtab, for debuggers
2866 that have to find it by searching forward from the entry
2867 point or from the current pc. */
2868 fprintf (file, "\t.long 0\n");
2870 /* Tbtab format type. Use format type 0. */
2871 fprintf (file, "\t.byte 0,");
2873 /* Language type. Unfortunately, there doesn't seem to be any
2874 official way to get this info, so we use language_string. C
2875 is 0. C++ is 9. No number defined for Obj-C, so use the
2876 value for C for now. */
2877 if (! strcmp (language_string, "GNU C")
2878 || ! strcmp (language_string, "GNU Obj-C"))
2880 else if (! strcmp (language_string, "GNU F77"))
2882 else if (! strcmp (language_string, "GNU Ada"))
2884 else if (! strcmp (language_string, "GNU PASCAL"))
2886 else if (! strcmp (language_string, "GNU C++"))
2890 fprintf (file, "%d,", i);
2892 /* 8 single bit fields: global linkage (not set for C extern linkage,
2893 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
2894 from start of procedure stored in tbtab, internal function, function
2895 has controlled storage, function has no toc, function uses fp,
2896 function logs/aborts fp operations. */
2897 /* Assume that fp operations are used if any fp reg must be saved. */
2898 fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
2900 /* 6 bitfields: function is interrupt handler, name present in
2901 proc table, function calls alloca, on condition directives
2902 (controls stack walks, 3 bits), saves condition reg, saves
2904 /* The `function calls alloca' bit seems to be set whenever reg 31 is
2905 set up as a frame pointer, even when there is no alloca call. */
2906 fprintf (file, "%d,",
2907 ((1 << 6) | (frame_pointer_needed << 5)
2908 | (info->cr_save_p << 1) | (info->lr_save_p)));
2910 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
2912 fprintf (file, "%d,",
2913 (info->push_p << 7) | (64 - info->first_fp_reg_save));
2915 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
2916 fprintf (file, "%d,", (32 - first_reg_to_save ()));
2919 /* Compute the parameter info from the function decl argument
2922 int next_parm_info_bit;
2924 next_parm_info_bit = 31;
2929 for (decl = DECL_ARGUMENTS (current_function_decl);
2930 decl; decl = TREE_CHAIN (decl))
2932 rtx parameter = DECL_INCOMING_RTL (decl);
2933 enum machine_mode mode = GET_MODE (parameter);
2935 if (GET_CODE (parameter) == REG)
2937 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2945 else if (mode == DFmode)
2950 /* If only one bit will fit, don't or in this entry. */
2951 if (next_parm_info_bit > 0)
2952 parm_info |= (bits << (next_parm_info_bit - 1));
2953 next_parm_info_bit -= 2;
2957 fixed_parms += ((GET_MODE_SIZE (mode)
2958 + (UNITS_PER_WORD - 1))
2960 next_parm_info_bit -= 1;
2966 /* Number of fixed point parameters. */
2967 /* This is actually the number of words of fixed point parameters; thus
2968 an 8 byte struct counts as 2; and thus the maximum value is 8. */
2969 fprintf (file, "%d,", fixed_parms);
2971 /* 2 bitfields: number of floating point parameters (7 bits), parameters
2973 /* This is actually the number of fp registers that hold parameters;
2974 and thus the maximum value is 13. */
2975 /* Set parameters on stack bit if parameters are not in their original
2976 registers, regardless of whether they are on the stack? Xlc
2977 seems to set the bit when not optimizing. */
2978 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
2980 /* Optional fields follow. Some are variable length. */
2982 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
2984 /* There is an entry for each parameter in a register, in the order that
2985 they occur in the parameter list. Any intervening arguments on the
2986 stack are ignored. If the list overflows a long (max possible length
2987 34 bits) then completely leave off all elements that don't fit. */
2988 /* Only emit this long if there was at least one parameter. */
2989 if (fixed_parms || float_parms)
2990 fprintf (file, "\t.long %d\n", parm_info);
2992 /* Offset from start of code to tb table. */
2993 fprintf (file, "\t.long ");
2994 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2995 RS6000_OUTPUT_BASENAME (file, fname);
2996 fprintf (file, "-.");
2997 RS6000_OUTPUT_BASENAME (file, fname);
2998 fprintf (file, "\n");
3000 /* Interrupt handler mask. */
3001 /* Omit this long, since we never set the interrupt handler bit
3004 /* Number of CTL (controlled storage) anchors. */
3005 /* Omit this long, since the has_ctl bit is never set above. */
3007 /* Displacement into stack of each CTL anchor. */
3008 /* Omit this list of longs, because there are no CTL anchors. */
3010 /* Length of function name. */
3011 fprintf (file, "\t.short %d\n", strlen (fname));
3013 /* Function name. */
3014 assemble_string (fname, strlen (fname));
3016 /* Register for alloca automatic storage; this is always reg 31.
3017 Only emit this if the alloca bit was set above. */
3018 if (frame_pointer_needed)
3019 fprintf (file, "\t.byte 31\n");
3021 #endif /* !USING_SVR4_H */
3023 /* Reset varargs indicator */
3024 rs6000_sysv_varargs_p = 0;
3027 /* Output a TOC entry. We derive the entry name from what is
3031 output_toc (file, x, labelno)
3044 /* if we're going to put a double constant in the TOC, make sure it's
3045 aligned properly when strict alignment is on. */
3046 if (GET_CODE (x) == CONST_DOUBLE
3048 && GET_MODE (x) == DFmode
3049 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
3050 ASM_OUTPUT_ALIGN (file, 3);
3055 if (TARGET_MINIMAL_TOC)
3057 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
3058 fprintf (file, "%d = .-", labelno);
3059 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
3060 fprintf (file, "1\n");
3063 #endif /* USING_SVR4_H */
3064 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
3066 /* Handle FP constants specially. Note that if we have a minimal
3067 TOC, things we put here aren't actually in the TOC, so we can allow
3069 if (GET_CODE (x) == CONST_DOUBLE
3070 && GET_MODE (x) == DFmode
3071 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
3076 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3077 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
3078 if (TARGET_MINIMAL_TOC)
3079 fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]);
3081 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
3082 l[0], l[1], l[0], l[1]);
3085 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
3086 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
3088 rtx val = operand_subword (x, 0, 0, SFmode);
3090 if (val == 0 || GET_CODE (val) != CONST_INT)
3093 if (TARGET_MINIMAL_TOC)
3094 fprintf (file, "\t.long %d\n", INTVAL (val));
3096 fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val));
3100 if (GET_CODE (x) == CONST)
3102 base = XEXP (XEXP (x, 0), 0);
3103 offset = INTVAL (XEXP (XEXP (x, 0), 1));
3106 if (GET_CODE (base) == SYMBOL_REF)
3107 name = XSTR (base, 0);
3108 else if (GET_CODE (base) == LABEL_REF)
3109 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
3110 else if (GET_CODE (base) == CODE_LABEL)
3111 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
3115 if (TARGET_MINIMAL_TOC)
3116 fprintf (file, "\t.long ");
3119 fprintf (file, "\t.tc ");
3120 RS6000_OUTPUT_BASENAME (file, name);
3123 fprintf (file, ".N%d", - offset);
3125 fprintf (file, ".P%d", offset);
3127 fprintf (file, "[TC],");
3129 output_addr_const (file, x);
3130 fprintf (file, "\n");
3133 /* Output an assembler pseudo-op to write an ASCII string of N characters
3134 starting at P to FILE.
3136 On the RS/6000, we have to do this using the .byte operation and
3137 write out special characters outside the quoted string.
3138 Also, the assembler is broken; very long strings are truncated,
3139 so we must artificially break them up early. */
3142 output_ascii (file, p, n)
3148 int i, count_string;
3149 char *for_string = "\t.byte \"";
3150 char *for_decimal = "\t.byte ";
3151 char *to_close = NULL;
3154 for (i = 0; i < n; i++)
3157 if (c >= ' ' && c < 0177)
3160 fputs (for_string, file);
3163 /* Write two quotes to get one. */
3171 for_decimal = "\"\n\t.byte ";
3175 if (count_string >= 512)
3177 fputs (to_close, file);
3179 for_string = "\t.byte \"";
3180 for_decimal = "\t.byte ";
3188 fputs (for_decimal, file);
3189 fprintf (file, "%d", c);
3191 for_string = "\n\t.byte \"";
3198 /* Now close the string if we have written one. Then end the line. */
3200 fprintf (file, to_close);
3203 /* Generate a unique section name for FILENAME for a section type
3204 represented by SECTION_DESC. Output goes into BUF.
3206 SECTION_DESC can be any string, as long as it is different for each
3207 possible section type.
3209 We name the section in the same manner as xlc. The name begins with an
3210 underscore followed by the filename (after stripping any leading directory
3211 names) with the last period replaced by the string SECTION_DESC. If
3212 FILENAME does not contain a period, SECTION_DESC is appended to the end of
3216 rs6000_gen_section_name (buf, filename, section_desc)
3221 char *q, *after_last_slash, *last_period;
3225 after_last_slash = filename;
3226 for (q = filename; *q; q++)
3229 after_last_slash = q + 1;
3234 len = strlen (after_last_slash) + strlen (section_desc) + 2;
3235 *buf = (char *) permalloc (len);
3240 for (q = after_last_slash; *q; q++)
3242 if (q == last_period)
3244 strcpy (p, section_desc);
3245 p += strlen (section_desc);
3248 else if (isalnum (*q))
3252 if (last_period == 0)
3253 strcpy (p, section_desc);
3258 /* Write function profiler code. */
3261 output_function_profiler (file, labelno)
3268 /* The last used parameter register. */
3273 /* Set up a TOC entry for the profiler label. */
3275 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
3276 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
3277 if (TARGET_MINIMAL_TOC)
3279 fprintf (file, "\t.long ");
3280 assemble_name (file, buf);
3281 fprintf (file, "\n");
3285 fprintf (file, "\t.tc\t");
3286 assemble_name (file, buf);
3287 fprintf (file, "[TC],");
3288 assemble_name (file, buf);
3289 fprintf (file, "\n");
3293 /* Figure out last used parameter register. The proper thing to do is
3294 to walk incoming args of the function. A function might have live
3295 parameter registers even if it has no incoming args. */
3297 for (last_parm_reg = 10;
3298 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
3302 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
3303 it might be set up as the frame pointer. */
3305 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
3306 fprintf (file, "\tai %d,%d,0\n", j, i);
3308 /* Load location address into r3, and call mcount. */
3310 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
3311 fprintf (file, "\tl 3,");
3312 assemble_name (file, buf);
3313 fprintf (file, "(2)\n\tbl .mcount\n");
3315 /* Restore parameter registers. */
3317 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
3318 fprintf (file, "\tai %d,%d,0\n", i, j);
3322 /* Adjust the cost of a scheduling dependency. Return the new cost of
3323 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3326 rs6000_adjust_cost (insn, link, dep_insn, cost)
3332 if (! recog_memoized (insn))
3335 if (REG_NOTE_KIND (link) != 0)
3338 if (REG_NOTE_KIND (link) == 0)
3340 /* Data dependency; DEP_INSN writes a register that INSN reads some
3343 /* Tell the first scheduling pass about the latency between a mtctr
3344 and bctr (and mtlr and br/blr). The first scheduling pass will not
3345 know about this latency since the mtctr instruction, which has the
3346 latency associated to it, will be generated by reload. */
3347 if (get_attr_type (insn) == TYPE_JMPREG)
3348 return TARGET_POWER ? 5 : 4;
3350 /* Fall out to return default cost. */