1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int toc_save_offset; /* offset to save the TOC pointer */
95 int varargs_save_offset; /* offset to save the varargs registers */
96 int ehrd_offset; /* offset to EH return data */
97 int reg_size; /* register size (4 or 8) */
98 int varargs_size; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size; /* variable save area size */
100 int parm_size; /* outgoing parameter size */
101 int save_size; /* save area size */
102 int fixed_size; /* fixed size of stack frame */
103 int gp_size; /* size of saved GP registers */
104 int fp_size; /* size of saved FP registers */
105 int altivec_size; /* size of saved AltiVec registers */
106 int cr_size; /* size to hold CR if not in save_size */
107 int lr_size; /* size to hold LR if not in save_size */
108 int vrsave_size; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size; /* size of altivec alignment padding if
111 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size;
113 int toc_size; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu;
121 struct rs6000_cpu_select rs6000_select[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str;
138 int rs6000_sched_restricted_insns_priority;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load;
150 /* Support targetm.vectorize.builtin_mask_for_store. */
151 static GTY(()) tree altivec_builtin_mask_for_store;
153 /* Size of long double */
154 const char *rs6000_long_double_size_string;
155 int rs6000_long_double_type_size;
157 /* Whether -mabi=altivec has appeared */
158 int rs6000_altivec_abi;
160 /* Whether VRSAVE instructions should be generated. */
161 int rs6000_altivec_vrsave;
163 /* String from -mvrsave= option. */
164 const char *rs6000_altivec_vrsave_string;
166 /* Nonzero if we want SPE ABI extensions. */
169 /* Whether isel instructions should be generated. */
172 /* Whether SPE simd instructions should be generated. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* String from -mfloat-gprs=. */
179 const char *rs6000_float_gprs_string;
181 /* String from -misel=. */
182 const char *rs6000_isel_string;
184 /* String from -mspe=. */
185 const char *rs6000_spe_string;
187 /* Set to nonzero once AIX common-mode calls have been defined. */
188 static GTY(()) int common_mode_defined;
190 /* Save information from a "cmpxx" operation until the branch or scc is
192 rtx rs6000_compare_op0, rs6000_compare_op1;
193 int rs6000_compare_fp_p;
195 /* Label number of label created for -mrelocatable, to call to so we can
196 get the address of the GOT section */
197 int rs6000_pic_labelno;
200 /* Which abi to adhere to */
201 const char *rs6000_abi_name;
203 /* Semantics of the small data area */
204 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
206 /* Which small data model to use */
207 const char *rs6000_sdata_name = (char *)0;
209 /* Counter for labels which are to be placed in .fixup. */
210 int fixuplabelno = 0;
213 /* Bit size of immediate TLS offsets and string from which it is decoded. */
214 int rs6000_tls_size = 32;
215 const char *rs6000_tls_size_string;
217 /* ABI enumeration available for subtarget to use. */
218 enum rs6000_abi rs6000_current_abi;
220 /* ABI string from -mabi= option. */
221 const char *rs6000_abi_string;
223 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
227 const char *rs6000_debug_name;
228 int rs6000_debug_stack; /* debug stack applications */
229 int rs6000_debug_arg; /* debug argument handling */
231 /* Value is TRUE if register/mode pair is accepatable. */
232 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
235 static GTY(()) tree opaque_V2SI_type_node;
236 static GTY(()) tree opaque_V2SF_type_node;
237 static GTY(()) tree opaque_p_V2SI_type_node;
238 static GTY(()) tree V16QI_type_node;
239 static GTY(()) tree V2SI_type_node;
240 static GTY(()) tree V2SF_type_node;
241 static GTY(()) tree V4HI_type_node;
242 static GTY(()) tree V4SI_type_node;
243 static GTY(()) tree V4SF_type_node;
244 static GTY(()) tree V8HI_type_node;
245 static GTY(()) tree unsigned_V16QI_type_node;
246 static GTY(()) tree unsigned_V8HI_type_node;
247 static GTY(()) tree unsigned_V4SI_type_node;
248 static GTY(()) tree bool_char_type_node; /* __bool char */
249 static GTY(()) tree bool_short_type_node; /* __bool short */
250 static GTY(()) tree bool_int_type_node; /* __bool int */
251 static GTY(()) tree pixel_type_node; /* __pixel */
252 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
253 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
254 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
255 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
257 int rs6000_warn_altivec_long = 1; /* On by default. */
258 const char *rs6000_warn_altivec_long_switch;
260 const char *rs6000_traceback_name;
262 traceback_default = 0,
268 /* Flag to say the TOC is initialized */
270 char toc_label_name[10];
272 /* Alias set for saves and restores from the rs6000 stack. */
273 static GTY(()) int rs6000_sr_alias_set;
275 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
276 The only place that looks at this is rs6000_set_default_type_attributes;
277 everywhere else should rely on the presence or absence of a longcall
278 attribute on the function declaration. */
279 int rs6000_default_long_calls;
280 const char *rs6000_longcall_switch;
282 /* Control alignment for fields within structures. */
283 /* String from -malign-XXXXX. */
284 const char *rs6000_alignment_string;
285 int rs6000_alignment_flags;
287 struct builtin_description
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
293 const enum insn_code icode;
294 const char *const name;
295 const enum rs6000_builtins code;
298 /* Target cpu costs. */
300 struct processor_costs {
301 const int mulsi; /* cost of SImode multiplication. */
302 const int mulsi_const; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9; /* cost of SImode mult by short constant. */
304 const int muldi; /* cost of DImode multiplication. */
305 const int divsi; /* cost of SImode division. */
306 const int divdi; /* cost of DImode division. */
307 const int fp; /* cost of simple SFmode and DFmode insns. */
308 const int dmul; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv; /* cost of SFmode division (fdivs). */
310 const int ddiv; /* cost of DFmode division (fdiv). */
313 const struct processor_costs *rs6000_cost;
315 /* Processor costs (relative to an add) */
317 /* Instruction size costs on 32bit processors. */
319 struct processor_costs size32_cost = {
320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
332 /* Instruction size costs on 64bit processors. */
334 struct processor_costs size64_cost = {
335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
347 /* Instruction costs on RIOS1 processors. */
349 struct processor_costs rios1_cost = {
350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
362 /* Instruction costs on RIOS2 processors. */
364 struct processor_costs rios2_cost = {
365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
377 /* Instruction costs on RS64A processors. */
379 struct processor_costs rs64a_cost = {
380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
392 /* Instruction costs on MPCCORE processors. */
394 struct processor_costs mpccore_cost = {
395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
407 /* Instruction costs on PPC403 processors. */
409 struct processor_costs ppc403_cost = {
410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
422 /* Instruction costs on PPC405 processors. */
424 struct processor_costs ppc405_cost = {
425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
437 /* Instruction costs on PPC440 processors. */
439 struct processor_costs ppc440_cost = {
440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
452 /* Instruction costs on PPC601 processors. */
454 struct processor_costs ppc601_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
467 /* Instruction costs on PPC603 processors. */
469 struct processor_costs ppc603_cost = {
470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
482 /* Instruction costs on PPC604 processors. */
484 struct processor_costs ppc604_cost = {
485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
497 /* Instruction costs on PPC604e processors. */
499 struct processor_costs ppc604e_cost = {
500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
512 /* Instruction costs on PPC620 processors. */
514 struct processor_costs ppc620_cost = {
515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
527 /* Instruction costs on PPC630 processors. */
529 struct processor_costs ppc630_cost = {
530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
542 /* Instruction costs on PPC750 and PPC7400 processors. */
544 struct processor_costs ppc750_cost = {
545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
557 /* Instruction costs on PPC7450 processors. */
559 struct processor_costs ppc7450_cost = {
560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
572 /* Instruction costs on PPC8540 processors. */
574 struct processor_costs ppc8540_cost = {
575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
587 /* Instruction costs on POWER4 and POWER5 processors. */
589 struct processor_costs power4_cost = {
590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
603 static bool rs6000_function_ok_for_sibcall (tree, tree);
604 static int num_insns_constant_wide (HOST_WIDE_INT);
605 static void validate_condition_mode (enum rtx_code, enum machine_mode);
606 static rtx rs6000_generate_compare (enum rtx_code);
607 static void rs6000_maybe_dead (rtx);
608 static void rs6000_emit_stack_tie (void);
609 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
610 static rtx spe_synthesize_frame_save (rtx);
611 static bool spe_func_has_64bit_regs_p (void);
612 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
614 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
615 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
616 static unsigned rs6000_hash_constant (rtx);
617 static unsigned toc_hash_function (const void *);
618 static int toc_hash_eq (const void *, const void *);
619 static int constant_pool_expr_1 (rtx, int *, int *);
620 static bool constant_pool_expr_p (rtx);
621 static bool toc_relative_expr_p (rtx);
622 static bool legitimate_small_data_p (enum machine_mode, rtx);
623 static bool legitimate_indexed_address_p (rtx, int);
624 static bool legitimate_indirect_address_p (rtx, int);
625 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
626 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
627 static struct machine_function * rs6000_init_machine_status (void);
628 static bool rs6000_assemble_integer (rtx, unsigned int, int);
629 #ifdef HAVE_GAS_HIDDEN
630 static void rs6000_assemble_visibility (tree, int);
632 static int rs6000_ra_ever_killed (void);
633 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
634 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
635 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
636 static const char *rs6000_mangle_fundamental_type (tree);
637 extern const struct attribute_spec rs6000_attribute_table[];
638 static void rs6000_set_default_type_attributes (tree);
639 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
640 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
641 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
643 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
644 static bool rs6000_return_in_memory (tree, tree);
645 static void rs6000_file_start (void);
647 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
648 static void rs6000_elf_asm_out_constructor (rtx, int);
649 static void rs6000_elf_asm_out_destructor (rtx, int);
650 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
651 static void rs6000_elf_unique_section (tree, int);
652 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
653 unsigned HOST_WIDE_INT);
654 static void rs6000_elf_encode_section_info (tree, rtx, int)
656 static bool rs6000_elf_in_small_data_p (tree);
659 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
660 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
661 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
662 static void rs6000_xcoff_unique_section (tree, int);
663 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
664 unsigned HOST_WIDE_INT);
665 static const char * rs6000_xcoff_strip_name_encoding (const char *);
666 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
667 static void rs6000_xcoff_file_start (void);
668 static void rs6000_xcoff_file_end (void);
671 static bool rs6000_binds_local_p (tree);
673 static int rs6000_variable_issue (FILE *, int, rtx, int);
674 static bool rs6000_rtx_costs (rtx, int, int, int *);
675 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
676 static bool is_microcoded_insn (rtx);
677 static int is_dispatch_slot_restricted (rtx);
678 static bool is_cracked_insn (rtx);
679 static bool is_branch_slot_insn (rtx);
680 static int rs6000_adjust_priority (rtx, int);
681 static int rs6000_issue_rate (void);
682 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
683 static rtx get_next_active_insn (rtx, rtx);
684 static bool insn_terminates_group_p (rtx , enum group_termination);
685 static bool is_costly_group (rtx *, rtx);
686 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
687 static int redefine_groups (FILE *, int, rtx, rtx);
688 static int pad_groups (FILE *, int, rtx, rtx);
689 static void rs6000_sched_finish (FILE *, int);
690 static int rs6000_use_sched_lookahead (void);
691 static tree rs6000_builtin_mask_for_load (void);
692 static tree rs6000_builtin_mask_for_store (void);
694 static void rs6000_init_builtins (void);
695 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
696 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
697 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
698 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
699 static void altivec_init_builtins (void);
700 static void rs6000_common_init_builtins (void);
701 static void rs6000_init_libfuncs (void);
703 static void enable_mask_for_builtins (struct builtin_description *, int,
704 enum rs6000_builtins,
705 enum rs6000_builtins);
706 static tree build_opaque_vector_type (tree, int);
707 static void spe_init_builtins (void);
708 static rtx spe_expand_builtin (tree, rtx, bool *);
709 static rtx spe_expand_stv_builtin (enum insn_code, tree);
710 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
711 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
712 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
713 static rs6000_stack_t *rs6000_stack_info (void);
714 static void debug_stack_info (rs6000_stack_t *);
716 static rtx altivec_expand_builtin (tree, rtx, bool *);
717 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
718 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
719 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
720 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
721 static rtx altivec_expand_predicate_builtin (enum insn_code,
722 const char *, tree, rtx);
723 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
724 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
725 static void rs6000_parse_abi_options (void);
726 static void rs6000_parse_alignment_option (void);
727 static void rs6000_parse_tls_size_option (void);
728 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
729 static void rs6000_parse_float_gprs_option (void);
730 static int first_altivec_reg_to_save (void);
731 static unsigned int compute_vrsave_mask (void);
732 static void compute_save_world_info(rs6000_stack_t *info_ptr);
733 static void is_altivec_return_reg (rtx, void *);
734 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
735 int easy_vector_constant (rtx, enum machine_mode);
736 static int easy_vector_same (rtx, enum machine_mode);
737 static int easy_vector_splat_const (int, enum machine_mode);
738 static bool is_ev64_opaque_type (tree);
739 static rtx rs6000_dwarf_register_span (rtx);
740 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
741 static rtx rs6000_tls_get_addr (void);
742 static rtx rs6000_got_sym (void);
743 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
744 static const char *rs6000_get_some_local_dynamic_name (void);
745 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
746 static rtx rs6000_complex_function_value (enum machine_mode);
747 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
748 enum machine_mode, tree);
749 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
750 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
751 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
752 enum machine_mode, tree,
754 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
757 static void macho_branch_islands (void);
758 static void add_compiler_branch_island (tree, tree, int);
759 static int no_previous_def (tree function_name);
760 static tree get_prev_label (tree function_name);
761 static void rs6000_darwin_file_start (void);
764 static tree rs6000_build_builtin_va_list (void);
765 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
766 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
767 static bool rs6000_vector_mode_supported_p (enum machine_mode);
768 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
770 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
772 static int get_vsel_insn (enum machine_mode);
773 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
776 const int INSN_NOT_AVAILABLE = -1;
777 static enum machine_mode rs6000_eh_return_filter_mode (void);
779 /* Hash table stuff for keeping track of TOC entries. */
781 struct toc_hash_struct GTY(())
783 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
784 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
786 enum machine_mode key_mode;
790 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
792 /* Default register names. */
793 char rs6000_reg_names[][8] =
795 "0", "1", "2", "3", "4", "5", "6", "7",
796 "8", "9", "10", "11", "12", "13", "14", "15",
797 "16", "17", "18", "19", "20", "21", "22", "23",
798 "24", "25", "26", "27", "28", "29", "30", "31",
799 "0", "1", "2", "3", "4", "5", "6", "7",
800 "8", "9", "10", "11", "12", "13", "14", "15",
801 "16", "17", "18", "19", "20", "21", "22", "23",
802 "24", "25", "26", "27", "28", "29", "30", "31",
803 "mq", "lr", "ctr","ap",
804 "0", "1", "2", "3", "4", "5", "6", "7",
806 /* AltiVec registers. */
807 "0", "1", "2", "3", "4", "5", "6", "7",
808 "8", "9", "10", "11", "12", "13", "14", "15",
809 "16", "17", "18", "19", "20", "21", "22", "23",
810 "24", "25", "26", "27", "28", "29", "30", "31",
816 #ifdef TARGET_REGNAMES
817 static const char alt_reg_names[][8] =
819 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
820 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
821 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
822 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
823 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
824 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
825 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
826 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
827 "mq", "lr", "ctr", "ap",
828 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
830 /* AltiVec registers. */
831 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
832 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
833 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
834 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
841 #ifndef MASK_STRICT_ALIGN
842 #define MASK_STRICT_ALIGN 0
844 #ifndef TARGET_PROFILE_KERNEL
845 #define TARGET_PROFILE_KERNEL 0
848 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
849 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
851 /* Return 1 for a symbol ref for a thread-local storage symbol. */
852 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
853 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
855 /* Initialize the GCC target structure. */
856 #undef TARGET_ATTRIBUTE_TABLE
857 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
858 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
859 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
861 #undef TARGET_ASM_ALIGNED_DI_OP
862 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
864 /* Default unaligned ops are only provided for ELF. Find the ops needed
865 for non-ELF systems. */
866 #ifndef OBJECT_FORMAT_ELF
868 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
870 #undef TARGET_ASM_UNALIGNED_HI_OP
871 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
872 #undef TARGET_ASM_UNALIGNED_SI_OP
873 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
874 #undef TARGET_ASM_UNALIGNED_DI_OP
875 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
878 #undef TARGET_ASM_UNALIGNED_HI_OP
879 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
880 #undef TARGET_ASM_UNALIGNED_SI_OP
881 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
882 #undef TARGET_ASM_UNALIGNED_DI_OP
883 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
884 #undef TARGET_ASM_ALIGNED_DI_OP
885 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
889 /* This hook deals with fixups for relocatable code and DI-mode objects
891 #undef TARGET_ASM_INTEGER
892 #define TARGET_ASM_INTEGER rs6000_assemble_integer
894 #ifdef HAVE_GAS_HIDDEN
895 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
896 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
899 #undef TARGET_HAVE_TLS
900 #define TARGET_HAVE_TLS HAVE_AS_TLS
902 #undef TARGET_CANNOT_FORCE_CONST_MEM
903 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
905 #undef TARGET_ASM_FUNCTION_PROLOGUE
906 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
907 #undef TARGET_ASM_FUNCTION_EPILOGUE
908 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
910 #undef TARGET_SCHED_VARIABLE_ISSUE
911 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
913 #undef TARGET_SCHED_ISSUE_RATE
914 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
915 #undef TARGET_SCHED_ADJUST_COST
916 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
917 #undef TARGET_SCHED_ADJUST_PRIORITY
918 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
919 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
920 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
921 #undef TARGET_SCHED_FINISH
922 #define TARGET_SCHED_FINISH rs6000_sched_finish
924 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
925 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
927 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
928 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
930 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE
931 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE rs6000_builtin_mask_for_store
933 #undef TARGET_INIT_BUILTINS
934 #define TARGET_INIT_BUILTINS rs6000_init_builtins
936 #undef TARGET_EXPAND_BUILTIN
937 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
939 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
940 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
942 #undef TARGET_INIT_LIBFUNCS
943 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
946 #undef TARGET_BINDS_LOCAL_P
947 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
950 #undef TARGET_ASM_OUTPUT_MI_THUNK
951 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
953 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
954 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
956 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
957 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
959 #undef TARGET_RTX_COSTS
960 #define TARGET_RTX_COSTS rs6000_rtx_costs
961 #undef TARGET_ADDRESS_COST
962 #define TARGET_ADDRESS_COST hook_int_rtx_0
964 #undef TARGET_VECTOR_OPAQUE_P
965 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
967 #undef TARGET_DWARF_REGISTER_SPAN
968 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
970 /* On rs6000, function arguments are promoted, as are function return
972 #undef TARGET_PROMOTE_FUNCTION_ARGS
973 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
974 #undef TARGET_PROMOTE_FUNCTION_RETURN
975 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
977 #undef TARGET_RETURN_IN_MEMORY
978 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
980 #undef TARGET_SETUP_INCOMING_VARARGS
981 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
983 /* Always strict argument naming on rs6000. */
984 #undef TARGET_STRICT_ARGUMENT_NAMING
985 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
986 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
987 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
988 #undef TARGET_SPLIT_COMPLEX_ARG
989 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
990 #undef TARGET_MUST_PASS_IN_STACK
991 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
992 #undef TARGET_PASS_BY_REFERENCE
993 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
995 #undef TARGET_BUILD_BUILTIN_VA_LIST
996 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
998 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
999 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1001 #undef TARGET_EH_RETURN_FILTER_MODE
1002 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1004 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1005 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1007 struct gcc_target targetm = TARGET_INITIALIZER;
1010 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1013 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1015 /* The GPRs can hold any mode, but values bigger than one register
1016 cannot go past R31. */
1017 if (INT_REGNO_P (regno))
1018 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1020 /* The float registers can only hold floating modes and DImode. */
1021 if (FP_REGNO_P (regno))
1023 (GET_MODE_CLASS (mode) == MODE_FLOAT
1024 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1025 || (GET_MODE_CLASS (mode) == MODE_INT
1026 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1028 /* The CR register can only hold CC modes. */
1029 if (CR_REGNO_P (regno))
1030 return GET_MODE_CLASS (mode) == MODE_CC;
1032 if (XER_REGNO_P (regno))
1033 return mode == PSImode;
1035 /* AltiVec only in AldyVec registers. */
1036 if (ALTIVEC_REGNO_P (regno))
1037 return ALTIVEC_VECTOR_MODE (mode);
1039 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1040 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1043 /* We cannot put TImode anywhere except general register and it must be
1044 able to fit within the register set. */
1046 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1049 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1051 rs6000_init_hard_regno_mode_ok (void)
1055 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1056 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1057 if (rs6000_hard_regno_mode_ok (r, m))
1058 rs6000_hard_regno_mode_ok_p[m][r] = true;
1061 /* If not otherwise specified by a target, make 'long double' equivalent to
1064 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1065 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1068 /* Override command line options. Mostly we process the processor
1069 type and sometimes adjust other TARGET_ options. */
1072 rs6000_override_options (const char *default_cpu)
1075 struct rs6000_cpu_select *ptr;
1078 /* Simplifications for entries below. */
1081 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1082 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1085 /* This table occasionally claims that a processor does not support
1086 a particular feature even though it does, but the feature is slower
1087 than the alternative. Thus, it shouldn't be relied on as a
1088 complete description of the processor's support.
1090 Please keep this list in order, and don't forget to update the
1091 documentation in invoke.texi when adding a new processor or
1095 const char *const name; /* Canonical processor name. */
1096 const enum processor_type processor; /* Processor type enum value. */
1097 const int target_enable; /* Target flags to enable. */
1098 } const processor_target_table[]
1099 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1100 {"403", PROCESSOR_PPC403,
1101 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1102 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1103 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1104 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1105 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1106 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1107 {"601", PROCESSOR_PPC601,
1108 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1109 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1110 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1111 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1112 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1113 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1114 {"620", PROCESSOR_PPC620,
1115 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1116 {"630", PROCESSOR_PPC630,
1117 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1118 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1119 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1120 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1121 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1123 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1124 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1125 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 /* 8548 has a dummy entry for now. */
1127 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1129 {"970", PROCESSOR_POWER4,
1130 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1131 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1132 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1133 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1135 {"G5", PROCESSOR_POWER4,
1136 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1137 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1138 {"power2", PROCESSOR_POWER,
1139 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1140 {"power3", PROCESSOR_PPC630,
1141 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1142 {"power4", PROCESSOR_POWER4,
1143 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1144 {"power5", PROCESSOR_POWER5,
1145 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1147 {"powerpc64", PROCESSOR_POWERPC64,
1148 POWERPC_BASE_MASK | MASK_POWERPC64},
1149 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1150 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1151 {"rios2", PROCESSOR_RIOS2,
1152 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1153 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1154 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1155 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1158 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1160 /* Some OSs don't support saving the high part of 64-bit registers on
1161 context switch. Other OSs don't support saving Altivec registers.
1162 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1163 settings; if the user wants either, the user must explicitly specify
1164 them and we won't interfere with the user's specification. */
1167 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1168 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1169 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1173 rs6000_init_hard_regno_mode_ok ();
1175 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1176 #ifdef OS_MISSING_POWERPC64
1177 if (OS_MISSING_POWERPC64)
1178 set_masks &= ~MASK_POWERPC64;
1180 #ifdef OS_MISSING_ALTIVEC
1181 if (OS_MISSING_ALTIVEC)
1182 set_masks &= ~MASK_ALTIVEC;
1185 /* Don't override these by the processor default if given explicitly. */
1186 set_masks &= ~(target_flags_explicit
1187 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
1189 /* Identify the processor type. */
1190 rs6000_select[0].string = default_cpu;
1191 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1193 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1195 ptr = &rs6000_select[i];
1196 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1198 for (j = 0; j < ptt_size; j++)
1199 if (! strcmp (ptr->string, processor_target_table[j].name))
1201 if (ptr->set_tune_p)
1202 rs6000_cpu = processor_target_table[j].processor;
1204 if (ptr->set_arch_p)
1206 target_flags &= ~set_masks;
1207 target_flags |= (processor_target_table[j].target_enable
1214 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1221 /* If we are optimizing big endian systems for space, use the load/store
1222 multiple and string instructions. */
1223 if (BYTES_BIG_ENDIAN && optimize_size)
1224 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1226 /* Don't allow -mmultiple or -mstring on little endian systems
1227 unless the cpu is a 750, because the hardware doesn't support the
1228 instructions used in little endian mode, and causes an alignment
1229 trap. The 750 does not cause an alignment trap (except when the
1230 target is unaligned). */
1232 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1234 if (TARGET_MULTIPLE)
1236 target_flags &= ~MASK_MULTIPLE;
1237 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1238 warning ("-mmultiple is not supported on little endian systems");
1243 target_flags &= ~MASK_STRING;
1244 if ((target_flags_explicit & MASK_STRING) != 0)
1245 warning ("-mstring is not supported on little endian systems");
1249 /* Set debug flags */
1250 if (rs6000_debug_name)
1252 if (! strcmp (rs6000_debug_name, "all"))
1253 rs6000_debug_stack = rs6000_debug_arg = 1;
1254 else if (! strcmp (rs6000_debug_name, "stack"))
1255 rs6000_debug_stack = 1;
1256 else if (! strcmp (rs6000_debug_name, "arg"))
1257 rs6000_debug_arg = 1;
1259 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1262 if (rs6000_traceback_name)
1264 if (! strncmp (rs6000_traceback_name, "full", 4))
1265 rs6000_traceback = traceback_full;
1266 else if (! strncmp (rs6000_traceback_name, "part", 4))
1267 rs6000_traceback = traceback_part;
1268 else if (! strncmp (rs6000_traceback_name, "no", 2))
1269 rs6000_traceback = traceback_none;
1271 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
1272 rs6000_traceback_name);
1275 /* Set size of long double */
1276 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1277 if (rs6000_long_double_size_string)
1280 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1281 if (*tail != '\0' || (size != 64 && size != 128))
1282 error ("Unknown switch -mlong-double-%s",
1283 rs6000_long_double_size_string);
1285 rs6000_long_double_type_size = size;
1288 /* Set Altivec ABI as default for powerpc64 linux. */
1289 if (TARGET_ELF && TARGET_64BIT)
1291 rs6000_altivec_abi = 1;
1292 rs6000_altivec_vrsave = 1;
1295 /* Handle -mabi= options. */
1296 rs6000_parse_abi_options ();
1298 /* Handle -malign-XXXXX option. */
1299 rs6000_parse_alignment_option ();
1301 rs6000_parse_float_gprs_option ();
1303 /* Handle generic -mFOO=YES/NO options. */
1304 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1305 &rs6000_altivec_vrsave);
1306 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1308 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1310 /* Handle -mtls-size option. */
1311 rs6000_parse_tls_size_option ();
1313 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1314 SUBTARGET_OVERRIDE_OPTIONS;
1316 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1317 SUBSUBTARGET_OVERRIDE_OPTIONS;
1319 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1320 SUB3TARGET_OVERRIDE_OPTIONS;
1326 error ("AltiVec and E500 instructions cannot coexist");
1328 /* The e500 does not have string instructions, and we set
1329 MASK_STRING above when optimizing for size. */
1330 if ((target_flags & MASK_STRING) != 0)
1331 target_flags = target_flags & ~MASK_STRING;
1333 /* No SPE means 64-bit long doubles, even if an E500. */
1334 if (rs6000_spe_string != 0
1335 && !strcmp (rs6000_spe_string, "no"))
1336 rs6000_long_double_type_size = 64;
1338 else if (rs6000_select[1].string != NULL)
1340 /* For the powerpc-eabispe configuration, we set all these by
1341 default, so let's unset them if we manually set another
1342 CPU that is not the E500. */
1343 if (rs6000_abi_string == 0)
1345 if (rs6000_spe_string == 0)
1347 if (rs6000_float_gprs_string == 0)
1348 rs6000_float_gprs = 0;
1349 if (rs6000_isel_string == 0)
1351 if (rs6000_long_double_size_string == 0)
1352 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1355 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1356 && rs6000_cpu != PROCESSOR_POWER5);
1357 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1358 || rs6000_cpu == PROCESSOR_POWER5);
1360 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1361 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1362 bits in target_flags so TARGET_SWITCHES cannot be used.
1363 Assumption here is that rs6000_longcall_switch points into the
1364 text of the complete option, rather than being a copy, so we can
1365 scan back for the presence or absence of the no- modifier. */
1366 if (rs6000_longcall_switch)
1368 const char *base = rs6000_longcall_switch;
1369 while (base[-1] != 'm') base--;
1371 if (*rs6000_longcall_switch != '\0')
1372 error ("invalid option `%s'", base);
1373 rs6000_default_long_calls = (base[0] != 'n');
1376 /* Handle -m(no-)warn-altivec-long similarly. */
1377 if (rs6000_warn_altivec_long_switch)
1379 const char *base = rs6000_warn_altivec_long_switch;
1380 while (base[-1] != 'm') base--;
1382 if (*rs6000_warn_altivec_long_switch != '\0')
1383 error ("invalid option `%s'", base);
1384 rs6000_warn_altivec_long = (base[0] != 'n');
1387 /* Handle -mprioritize-restricted-insns option. */
1388 rs6000_sched_restricted_insns_priority
1389 = (rs6000_sched_groups ? 1 : 0);
1390 if (rs6000_sched_restricted_insns_priority_str)
1391 rs6000_sched_restricted_insns_priority =
1392 atoi (rs6000_sched_restricted_insns_priority_str);
1394 /* Handle -msched-costly-dep option. */
1395 rs6000_sched_costly_dep
1396 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1397 if (rs6000_sched_costly_dep_str)
1399 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1400 rs6000_sched_costly_dep = no_dep_costly;
1401 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1402 rs6000_sched_costly_dep = all_deps_costly;
1403 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1404 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1405 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1406 rs6000_sched_costly_dep = store_to_load_dep_costly;
1408 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1411 /* Handle -minsert-sched-nops option. */
1412 rs6000_sched_insert_nops
1413 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1414 if (rs6000_sched_insert_nops_str)
1416 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1417 rs6000_sched_insert_nops = sched_finish_none;
1418 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1419 rs6000_sched_insert_nops = sched_finish_pad_groups;
1420 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1421 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1423 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1426 #ifdef TARGET_REGNAMES
1427 /* If the user desires alternate register names, copy in the
1428 alternate names now. */
1429 if (TARGET_REGNAMES)
1430 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1433 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1434 If -maix-struct-return or -msvr4-struct-return was explicitly
1435 used, don't override with the ABI default. */
1436 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1438 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1439 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1441 target_flags |= MASK_AIX_STRUCT_RET;
1444 if (TARGET_LONG_DOUBLE_128
1445 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1446 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1448 /* Allocate an alias set for register saves & restores from stack. */
1449 rs6000_sr_alias_set = new_alias_set ();
1452 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1454 /* We can only guarantee the availability of DI pseudo-ops when
1455 assembling for 64-bit targets. */
1458 targetm.asm_out.aligned_op.di = NULL;
1459 targetm.asm_out.unaligned_op.di = NULL;
1462 /* Set branch target alignment, if not optimizing for size. */
1465 if (rs6000_sched_groups)
1467 if (align_functions <= 0)
1468 align_functions = 16;
1469 if (align_jumps <= 0)
1471 if (align_loops <= 0)
1474 if (align_jumps_max_skip <= 0)
1475 align_jumps_max_skip = 15;
1476 if (align_loops_max_skip <= 0)
1477 align_loops_max_skip = 15;
1480 /* Arrange to save and restore machine status around nested functions. */
1481 init_machine_status = rs6000_init_machine_status;
1483 /* We should always be splitting complex arguments, but we can't break
1484 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1485 if (DEFAULT_ABI != ABI_AIX)
1486 targetm.calls.split_complex_arg = NULL;
1488 /* Initialize rs6000_cost with the appropriate target costs. */
1490 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1494 case PROCESSOR_RIOS1:
1495 rs6000_cost = &rios1_cost;
1498 case PROCESSOR_RIOS2:
1499 rs6000_cost = &rios2_cost;
1502 case PROCESSOR_RS64A:
1503 rs6000_cost = &rs64a_cost;
1506 case PROCESSOR_MPCCORE:
1507 rs6000_cost = &mpccore_cost;
1510 case PROCESSOR_PPC403:
1511 rs6000_cost = &ppc403_cost;
1514 case PROCESSOR_PPC405:
1515 rs6000_cost = &ppc405_cost;
1518 case PROCESSOR_PPC440:
1519 rs6000_cost = &ppc440_cost;
1522 case PROCESSOR_PPC601:
1523 rs6000_cost = &ppc601_cost;
1526 case PROCESSOR_PPC603:
1527 rs6000_cost = &ppc603_cost;
1530 case PROCESSOR_PPC604:
1531 rs6000_cost = &ppc604_cost;
1534 case PROCESSOR_PPC604e:
1535 rs6000_cost = &ppc604e_cost;
1538 case PROCESSOR_PPC620:
1539 rs6000_cost = &ppc620_cost;
1542 case PROCESSOR_PPC630:
1543 rs6000_cost = &ppc630_cost;
1546 case PROCESSOR_PPC750:
1547 case PROCESSOR_PPC7400:
1548 rs6000_cost = &ppc750_cost;
1551 case PROCESSOR_PPC7450:
1552 rs6000_cost = &ppc7450_cost;
1555 case PROCESSOR_PPC8540:
1556 rs6000_cost = &ppc8540_cost;
1559 case PROCESSOR_POWER4:
1560 case PROCESSOR_POWER5:
1561 rs6000_cost = &power4_cost;
1569 /* Implement targetm.vectorize.builtin_mask_for_load. */
1571 rs6000_builtin_mask_for_load (void)
1574 return altivec_builtin_mask_for_load;
1579 /* Implement targetm.vectorize.builtin_mask_for_store. */
1581 rs6000_builtin_mask_for_store (void)
1584 return altivec_builtin_mask_for_store;
1589 /* Handle generic options of the form -mfoo=yes/no.
1590 NAME is the option name.
1591 VALUE is the option value.
1592 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1593 whether the option value is 'yes' or 'no' respectively. */
1595 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1599 else if (!strcmp (value, "yes"))
1601 else if (!strcmp (value, "no"))
1604 error ("unknown -m%s= option specified: '%s'", name, value);
1607 /* Handle -mabi= options. */
1609 rs6000_parse_abi_options (void)
1611 if (rs6000_abi_string == 0)
1613 else if (! strcmp (rs6000_abi_string, "altivec"))
1615 rs6000_altivec_abi = 1;
1618 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1619 rs6000_altivec_abi = 0;
1620 else if (! strcmp (rs6000_abi_string, "spe"))
1623 rs6000_altivec_abi = 0;
1624 if (!TARGET_SPE_ABI)
1625 error ("not configured for ABI: '%s'", rs6000_abi_string);
1628 else if (! strcmp (rs6000_abi_string, "no-spe"))
1631 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1634 /* Handle -mfloat-gprs= options. */
1636 rs6000_parse_float_gprs_option (void)
1638 if (rs6000_float_gprs_string == 0)
1640 else if (! strcmp (rs6000_float_gprs_string, "yes")
1641 || ! strcmp (rs6000_float_gprs_string, "single"))
1642 rs6000_float_gprs = 1;
1643 else if (! strcmp (rs6000_float_gprs_string, "double"))
1644 rs6000_float_gprs = 2;
1645 else if (! strcmp (rs6000_float_gprs_string, "no"))
1646 rs6000_float_gprs = 0;
1648 error ("invalid option for -mfloat-gprs");
1651 /* Handle -malign-XXXXXX options. */
1653 rs6000_parse_alignment_option (void)
1655 if (rs6000_alignment_string == 0)
1657 else if (! strcmp (rs6000_alignment_string, "power"))
1658 rs6000_alignment_flags = MASK_ALIGN_POWER;
1659 else if (! strcmp (rs6000_alignment_string, "natural"))
1660 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1662 error ("unknown -malign-XXXXX option specified: '%s'",
1663 rs6000_alignment_string);
1666 /* Validate and record the size specified with the -mtls-size option. */
1669 rs6000_parse_tls_size_option (void)
1671 if (rs6000_tls_size_string == 0)
1673 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1674 rs6000_tls_size = 16;
1675 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1676 rs6000_tls_size = 32;
1677 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1678 rs6000_tls_size = 64;
1680 error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1684 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1688 /* Do anything needed at the start of the asm file. */
1691 rs6000_file_start (void)
1695 const char *start = buffer;
1696 struct rs6000_cpu_select *ptr;
1697 const char *default_cpu = TARGET_CPU_DEFAULT;
1698 FILE *file = asm_out_file;
1700 default_file_start ();
1702 #ifdef TARGET_BI_ARCH
1703 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1707 if (flag_verbose_asm)
1709 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1710 rs6000_select[0].string = default_cpu;
1712 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1714 ptr = &rs6000_select[i];
1715 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1717 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1722 #ifdef USING_ELFOS_H
1723 switch (rs6000_sdata)
1725 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1726 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1727 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1728 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1731 if (rs6000_sdata && g_switch_value)
1733 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1745 /* Return nonzero if this function is known to have a null epilogue. */
1748 direct_return (void)
1750 if (reload_completed)
1752 rs6000_stack_t *info = rs6000_stack_info ();
1754 if (info->first_gp_reg_save == 32
1755 && info->first_fp_reg_save == 64
1756 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1757 && ! info->lr_save_p
1758 && ! info->cr_save_p
1759 && info->vrsave_mask == 0
1767 /* Returns 1 always. */
1770 any_operand (rtx op ATTRIBUTE_UNUSED,
1771 enum machine_mode mode ATTRIBUTE_UNUSED)
1776 /* Returns 1 always. */
1779 any_parallel_operand (rtx op ATTRIBUTE_UNUSED,
1780 enum machine_mode mode ATTRIBUTE_UNUSED)
1785 /* Returns 1 if op is the count register. */
1788 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1790 if (GET_CODE (op) != REG)
1793 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1796 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1802 /* Returns 1 if op is an altivec register. */
1805 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1807 return (register_operand (op, mode)
1808 && (GET_CODE (op) != REG
1809 || REGNO (op) > FIRST_PSEUDO_REGISTER
1810 || ALTIVEC_REGNO_P (REGNO (op))));
1814 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1816 if (GET_CODE (op) != REG)
1819 if (XER_REGNO_P (REGNO (op)))
1825 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1826 by such constants completes more quickly. */
1829 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1831 return (GET_CODE (op) == CONST_INT
1832 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1835 /* Return 1 if OP is a constant that can fit in a D field. */
1838 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1840 return (GET_CODE (op) == CONST_INT
1841 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1844 /* Similar for an unsigned D field. */
1847 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1849 return (GET_CODE (op) == CONST_INT
1850 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1853 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1856 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1858 return (GET_CODE (op) == CONST_INT
1859 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1862 /* Returns 1 if OP is a CONST_INT that is a positive value
1863 and an exact power of 2. */
1866 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1868 return (GET_CODE (op) == CONST_INT
1870 && exact_log2 (INTVAL (op)) >= 0);
1873 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1877 gpc_reg_operand (rtx op, enum machine_mode mode)
1879 return (register_operand (op, mode)
1880 && (GET_CODE (op) != REG
1881 || (REGNO (op) >= ARG_POINTER_REGNUM
1882 && !XER_REGNO_P (REGNO (op)))
1883 || REGNO (op) < MQ_REGNO));
1886 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1890 cc_reg_operand (rtx op, enum machine_mode mode)
1892 return (register_operand (op, mode)
1893 && (GET_CODE (op) != REG
1894 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1895 || CR_REGNO_P (REGNO (op))));
1898 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1899 CR field that isn't CR0. */
1902 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1904 return (register_operand (op, mode)
1905 && (GET_CODE (op) != REG
1906 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1907 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1910 /* Returns 1 if OP is either a constant integer valid for a D-field or
1911 a non-special register. If a register, it must be in the proper
1912 mode unless MODE is VOIDmode. */
1915 reg_or_short_operand (rtx op, enum machine_mode mode)
1917 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1920 /* Similar, except check if the negation of the constant would be
1921 valid for a D-field. Don't allow a constant zero, since all the
1922 patterns that call this predicate use "addic r1,r2,-constant" on
1923 a constant value to set a carry when r2 is greater or equal to
1924 "constant". That doesn't work for zero. */
1927 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1929 if (GET_CODE (op) == CONST_INT)
1930 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
1932 return gpc_reg_operand (op, mode);
1935 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1936 a non-special register. If a register, it must be in the proper
1937 mode unless MODE is VOIDmode. */
1940 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1942 if (gpc_reg_operand (op, mode))
1944 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1951 /* Return 1 if the operand is either a register or an integer whose
1952 high-order 16 bits are zero. */
1955 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1957 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1960 /* Return 1 is the operand is either a non-special register or ANY
1961 constant integer. */
1964 reg_or_cint_operand (rtx op, enum machine_mode mode)
1966 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1969 /* Return 1 is the operand is either a non-special register or ANY
1970 32-bit signed constant integer. */
1973 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1975 return (gpc_reg_operand (op, mode)
1976 || (GET_CODE (op) == CONST_INT
1977 #if HOST_BITS_PER_WIDE_INT != 32
1978 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1979 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1984 /* Return 1 is the operand is either a non-special register or a 32-bit
1985 signed constant integer valid for 64-bit addition. */
1988 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1990 return (gpc_reg_operand (op, mode)
1991 || (GET_CODE (op) == CONST_INT
1992 #if HOST_BITS_PER_WIDE_INT == 32
1993 && INTVAL (op) < 0x7fff8000
1995 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
2001 /* Return 1 is the operand is either a non-special register or a 32-bit
2002 signed constant integer valid for 64-bit subtraction. */
2005 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
2007 return (gpc_reg_operand (op, mode)
2008 || (GET_CODE (op) == CONST_INT
2009 #if HOST_BITS_PER_WIDE_INT == 32
2010 && (- INTVAL (op)) < 0x7fff8000
2012 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
2018 /* Return 1 is the operand is either a non-special register or ANY
2019 32-bit unsigned constant integer. */
2022 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
2024 if (GET_CODE (op) == CONST_INT)
2026 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
2028 if (GET_MODE_BITSIZE (mode) <= 32)
2031 if (INTVAL (op) < 0)
2035 return ((INTVAL (op) & GET_MODE_MASK (mode)
2036 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
2038 else if (GET_CODE (op) == CONST_DOUBLE)
2040 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2044 return CONST_DOUBLE_HIGH (op) == 0;
2047 return gpc_reg_operand (op, mode);
2050 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2053 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2055 return (GET_CODE (op) == SYMBOL_REF
2056 || GET_CODE (op) == CONST
2057 || GET_CODE (op) == LABEL_REF);
2060 /* Return 1 if the operand is a simple references that can be loaded via
2061 the GOT (labels involving addition aren't allowed). */
2064 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2066 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
2069 /* Return the number of instructions it takes to form a constant in an
2070 integer register. */
2073 num_insns_constant_wide (HOST_WIDE_INT value)
2075 /* signed constant loadable with {cal|addi} */
2076 if (CONST_OK_FOR_LETTER_P (value, 'I'))
2079 /* constant loadable with {cau|addis} */
2080 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2083 #if HOST_BITS_PER_WIDE_INT == 64
2084 else if (TARGET_POWERPC64)
2086 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2087 HOST_WIDE_INT high = value >> 31;
2089 if (high == 0 || high == -1)
2095 return num_insns_constant_wide (high) + 1;
2097 return (num_insns_constant_wide (high)
2098 + num_insns_constant_wide (low) + 1);
2107 num_insns_constant (rtx op, enum machine_mode mode)
2109 if (GET_CODE (op) == CONST_INT)
2111 #if HOST_BITS_PER_WIDE_INT == 64
2112 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2113 && mask64_operand (op, mode))
2117 return num_insns_constant_wide (INTVAL (op));
2120 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
2125 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2126 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2127 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2130 else if (GET_CODE (op) == CONST_DOUBLE)
2136 int endian = (WORDS_BIG_ENDIAN == 0);
2138 if (mode == VOIDmode || mode == DImode)
2140 high = CONST_DOUBLE_HIGH (op);
2141 low = CONST_DOUBLE_LOW (op);
2145 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2146 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2148 low = l[1 - endian];
2152 return (num_insns_constant_wide (low)
2153 + num_insns_constant_wide (high));
2157 if (high == 0 && low >= 0)
2158 return num_insns_constant_wide (low);
2160 else if (high == -1 && low < 0)
2161 return num_insns_constant_wide (low);
2163 else if (mask64_operand (op, mode))
2167 return num_insns_constant_wide (high) + 1;
2170 return (num_insns_constant_wide (high)
2171 + num_insns_constant_wide (low) + 1);
2179 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2180 register with one instruction per word. We only do this if we can
2181 safely read CONST_DOUBLE_{LOW,HIGH}. */
2184 easy_fp_constant (rtx op, enum machine_mode mode)
2186 if (GET_CODE (op) != CONST_DOUBLE
2187 || GET_MODE (op) != mode
2188 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
2191 /* Consider all constants with -msoft-float to be easy. */
2192 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
2196 /* If we are using V.4 style PIC, consider all constants to be hard. */
2197 if (flag_pic && DEFAULT_ABI == ABI_V4)
2200 #ifdef TARGET_RELOCATABLE
2201 /* Similarly if we are using -mrelocatable, consider all constants
2203 if (TARGET_RELOCATABLE)
2212 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2213 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
2215 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2216 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
2217 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
2218 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
2221 else if (mode == DFmode)
2226 if (TARGET_E500_DOUBLE)
2229 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2230 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
2232 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2233 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
2236 else if (mode == SFmode)
2241 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2242 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2244 return num_insns_constant_wide (l) == 1;
2247 else if (mode == DImode)
2248 return ((TARGET_POWERPC64
2249 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
2250 || (num_insns_constant (op, DImode) <= 2));
2252 else if (mode == SImode)
2258 /* Returns the constant for the splat instruction, if exists. */
2261 easy_vector_splat_const (int cst, enum machine_mode mode)
2266 if (EASY_VECTOR_15 (cst)
2267 || EASY_VECTOR_15_ADD_SELF (cst))
2269 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2275 if (EASY_VECTOR_15 (cst)
2276 || EASY_VECTOR_15_ADD_SELF (cst))
2278 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2284 if (EASY_VECTOR_15 (cst)
2285 || EASY_VECTOR_15_ADD_SELF (cst))
2294 /* Return nonzero if all elements of a vector have the same value. */
2297 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2301 units = CONST_VECTOR_NUNITS (op);
2303 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2304 for (i = 1; i < units; ++i)
2305 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2307 if (i == units && easy_vector_splat_const (cst, mode))
2312 /* Return 1 if the operand is a CONST_INT and can be put into a
2313 register without using memory. */
2316 easy_vector_constant (rtx op, enum machine_mode mode)
2320 if (GET_CODE (op) != CONST_VECTOR
2325 if (zero_constant (op, mode)
2326 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
2327 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
2330 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2333 if (TARGET_SPE && mode == V1DImode)
2336 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2337 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
2339 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2341 evmergelo r0, r0, r0
2344 I don't know how efficient it would be to allow bigger constants,
2345 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2346 instructions is better than a 64-bit memory load, but I don't
2347 have the e500 timing specs. */
2348 if (TARGET_SPE && mode == V2SImode
2349 && cst >= -0x7fff && cst <= 0x7fff
2350 && cst2 >= -0x7fff && cst2 <= 0x7fff)
2354 && easy_vector_same (op, mode))
2356 cst = easy_vector_splat_const (cst, mode);
2357 if (EASY_VECTOR_15_ADD_SELF (cst)
2358 || EASY_VECTOR_15 (cst))
2364 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2367 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
2371 && GET_CODE (op) == CONST_VECTOR
2372 && easy_vector_same (op, mode))
2374 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
2375 if (EASY_VECTOR_15_ADD_SELF (cst))
2381 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2384 gen_easy_vector_constant_add_self (rtx op)
2388 units = GET_MODE_NUNITS (GET_MODE (op));
2389 v = rtvec_alloc (units);
2391 for (i = 0; i < units; i++)
2393 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2394 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2398 output_vec_const_move (rtx *operands)
2401 enum machine_mode mode;
2407 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2408 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2409 mode = GET_MODE (dest);
2413 if (zero_constant (vec, mode))
2414 return "vxor %0,%0,%0";
2415 else if (easy_vector_constant (vec, mode))
2417 operands[1] = GEN_INT (cst);
2421 if (EASY_VECTOR_15 (cst))
2423 operands[1] = GEN_INT (cst);
2424 return "vspltisw %0,%1";
2426 else if (EASY_VECTOR_15_ADD_SELF (cst))
2432 if (EASY_VECTOR_15 (cst))
2434 operands[1] = GEN_INT (cst);
2435 return "vspltish %0,%1";
2437 else if (EASY_VECTOR_15_ADD_SELF (cst))
2443 if (EASY_VECTOR_15 (cst))
2445 operands[1] = GEN_INT (cst);
2446 return "vspltisb %0,%1";
2448 else if (EASY_VECTOR_15_ADD_SELF (cst))
2461 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2462 pattern of V1DI, V4HI, and V2SF.
2464 FIXME: We should probably return # and add post reload
2465 splitters for these, but this way is so easy ;-). */
2466 operands[1] = GEN_INT (cst);
2467 operands[2] = GEN_INT (cst2);
2469 return "li %0,%1\n\tevmergelo %0,%0,%0";
2471 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2477 /* Return 1 if the operand is the constant 0. This works for scalars
2478 as well as vectors. */
2480 zero_constant (rtx op, enum machine_mode mode)
2482 return op == CONST0_RTX (mode);
2485 /* Return 1 if the operand is 0.0. */
2487 zero_fp_constant (rtx op, enum machine_mode mode)
2489 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
2492 /* Return 1 if the operand is in volatile memory. Note that during
2493 the RTL generation phase, memory_operand does not return TRUE for
2494 volatile memory references. So this function allows us to
2495 recognize volatile references where its safe. */
2498 volatile_mem_operand (rtx op, enum machine_mode mode)
2500 if (GET_CODE (op) != MEM)
2503 if (!MEM_VOLATILE_P (op))
2506 if (mode != GET_MODE (op))
2509 if (reload_completed)
2510 return memory_operand (op, mode);
2512 if (reload_in_progress)
2513 return strict_memory_address_p (mode, XEXP (op, 0));
2515 return memory_address_p (mode, XEXP (op, 0));
2518 /* Return 1 if the operand is an offsettable memory operand. */
2521 offsettable_mem_operand (rtx op, enum machine_mode mode)
2523 return ((GET_CODE (op) == MEM)
2524 && offsettable_address_p (reload_completed || reload_in_progress,
2525 mode, XEXP (op, 0)));
2528 /* Return 1 if the operand is either an easy FP constant (see above) or
2532 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
2534 return memory_operand (op, mode) || easy_fp_constant (op, mode);
2537 /* Return 1 if the operand is either a non-special register or an item
2538 that can be used as the operand of a `mode' add insn. */
2541 add_operand (rtx op, enum machine_mode mode)
2543 if (GET_CODE (op) == CONST_INT)
2544 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2545 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2547 return gpc_reg_operand (op, mode);
2550 /* Return 1 if OP is a constant but not a valid add_operand. */
2553 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2555 return (GET_CODE (op) == CONST_INT
2556 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2557 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2560 /* Return 1 if the operand is a non-special register or a constant that
2561 can be used as the operand of an OR or XOR insn on the RS/6000. */
2564 logical_operand (rtx op, enum machine_mode mode)
2566 HOST_WIDE_INT opl, oph;
2568 if (gpc_reg_operand (op, mode))
2571 if (GET_CODE (op) == CONST_INT)
2573 opl = INTVAL (op) & GET_MODE_MASK (mode);
2575 #if HOST_BITS_PER_WIDE_INT <= 32
2576 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
2580 else if (GET_CODE (op) == CONST_DOUBLE)
2582 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2585 opl = CONST_DOUBLE_LOW (op);
2586 oph = CONST_DOUBLE_HIGH (op);
2593 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2594 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2597 /* Return 1 if C is a constant that is not a logical operand (as
2598 above), but could be split into one. */
2601 non_logical_cint_operand (rtx op, enum machine_mode mode)
2603 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2604 && ! logical_operand (op, mode)
2605 && reg_or_logical_cint_operand (op, mode));
2608 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2609 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2610 Reject all ones and all zeros, since these should have been optimized
2611 away and confuse the making of MB and ME. */
2614 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2616 HOST_WIDE_INT c, lsb;
2618 if (GET_CODE (op) != CONST_INT)
2623 /* Fail in 64-bit mode if the mask wraps around because the upper
2624 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2625 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2628 /* We don't change the number of transitions by inverting,
2629 so make sure we start with the LS bit zero. */
2633 /* Reject all zeros or all ones. */
2637 /* Find the first transition. */
2640 /* Invert to look for a second transition. */
2643 /* Erase first transition. */
2646 /* Find the second transition (if any). */
2649 /* Match if all the bits above are 1's (or c is zero). */
2653 /* Return 1 for the PowerPC64 rlwinm corner case. */
2656 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2658 HOST_WIDE_INT c, lsb;
2660 if (GET_CODE (op) != CONST_INT)
2665 if ((c & 0x80000001) != 0x80000001)
2679 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2680 It is if there are no more than one 1->0 or 0->1 transitions.
2681 Reject all zeros, since zero should have been optimized away and
2682 confuses the making of MB and ME. */
2685 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2687 if (GET_CODE (op) == CONST_INT)
2689 HOST_WIDE_INT c, lsb;
2693 /* Reject all zeros. */
2697 /* We don't change the number of transitions by inverting,
2698 so make sure we start with the LS bit zero. */
2702 /* Find the transition, and check that all bits above are 1's. */
2705 /* Match if all the bits above are 1's (or c is zero). */
2711 /* Like mask64_operand, but allow up to three transitions. This
2712 predicate is used by insn patterns that generate two rldicl or
2713 rldicr machine insns. */
2716 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2718 if (GET_CODE (op) == CONST_INT)
2720 HOST_WIDE_INT c, lsb;
2724 /* Disallow all zeros. */
2728 /* We don't change the number of transitions by inverting,
2729 so make sure we start with the LS bit zero. */
2733 /* Find the first transition. */
2736 /* Invert to look for a second transition. */
2739 /* Erase first transition. */
2742 /* Find the second transition. */
2745 /* Invert to look for a third transition. */
2748 /* Erase second transition. */
2751 /* Find the third transition (if any). */
2754 /* Match if all the bits above are 1's (or c is zero). */
2760 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2761 implement ANDing by the mask IN. */
2763 build_mask64_2_operands (rtx in, rtx *out)
2765 #if HOST_BITS_PER_WIDE_INT >= 64
2766 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2769 if (GET_CODE (in) != CONST_INT)
2775 /* Assume c initially something like 0x00fff000000fffff. The idea
2776 is to rotate the word so that the middle ^^^^^^ group of zeros
2777 is at the MS end and can be cleared with an rldicl mask. We then
2778 rotate back and clear off the MS ^^ group of zeros with a
2780 c = ~c; /* c == 0xff000ffffff00000 */
2781 lsb = c & -c; /* lsb == 0x0000000000100000 */
2782 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2783 c = ~c; /* c == 0x00fff000000fffff */
2784 c &= -lsb; /* c == 0x00fff00000000000 */
2785 lsb = c & -c; /* lsb == 0x0000100000000000 */
2786 c = ~c; /* c == 0xff000fffffffffff */
2787 c &= -lsb; /* c == 0xff00000000000000 */
2789 while ((lsb >>= 1) != 0)
2790 shift++; /* shift == 44 on exit from loop */
2791 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2792 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2793 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2797 /* Assume c initially something like 0xff000f0000000000. The idea
2798 is to rotate the word so that the ^^^ middle group of zeros
2799 is at the LS end and can be cleared with an rldicr mask. We then
2800 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2802 lsb = c & -c; /* lsb == 0x0000010000000000 */
2803 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2804 c = ~c; /* c == 0x00fff0ffffffffff */
2805 c &= -lsb; /* c == 0x00fff00000000000 */
2806 lsb = c & -c; /* lsb == 0x0000100000000000 */
2807 c = ~c; /* c == 0xff000fffffffffff */
2808 c &= -lsb; /* c == 0xff00000000000000 */
2810 while ((lsb >>= 1) != 0)
2811 shift++; /* shift == 44 on exit from loop */
2812 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2813 m1 >>= shift; /* m1 == 0x0000000000000fff */
2814 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2817 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2818 masks will be all 1's. We are guaranteed more than one transition. */
2819 out[0] = GEN_INT (64 - shift);
2820 out[1] = GEN_INT (m1);
2821 out[2] = GEN_INT (shift);
2822 out[3] = GEN_INT (m2);
2830 /* Return 1 if the operand is either a non-special register or a constant
2831 that can be used as the operand of a PowerPC64 logical AND insn. */
2834 and64_operand (rtx op, enum machine_mode mode)
2836 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2837 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2839 return (logical_operand (op, mode) || mask64_operand (op, mode));
2842 /* Like the above, but also match constants that can be implemented
2843 with two rldicl or rldicr insns. */
2846 and64_2_operand (rtx op, enum machine_mode mode)
2848 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2849 return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2851 return logical_operand (op, mode) || mask64_2_operand (op, mode);
2854 /* Return 1 if the operand is either a non-special register or a
2855 constant that can be used as the operand of an RS/6000 logical AND insn. */
2858 and_operand (rtx op, enum machine_mode mode)
2860 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2861 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2863 return (logical_operand (op, mode) || mask_operand (op, mode));
2866 /* Return 1 if the operand is a general register or memory operand. */
2869 reg_or_mem_operand (rtx op, enum machine_mode mode)
2871 return (gpc_reg_operand (op, mode)
2872 || memory_operand (op, mode)
2873 || macho_lo_sum_memory_operand (op, mode)
2874 || volatile_mem_operand (op, mode));
2877 /* Return 1 if the operand is a general register or memory operand without
2878 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2882 lwa_operand (rtx op, enum machine_mode mode)
2886 if (reload_completed && GET_CODE (inner) == SUBREG)
2887 inner = SUBREG_REG (inner);
2889 return gpc_reg_operand (inner, mode)
2890 || (memory_operand (inner, mode)
2891 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2892 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2893 && (GET_CODE (XEXP (inner, 0)) != PLUS
2894 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2895 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2898 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2901 symbol_ref_operand (rtx op, enum machine_mode mode)
2903 if (mode != VOIDmode && GET_MODE (op) != mode)
2906 return (GET_CODE (op) == SYMBOL_REF
2907 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2910 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2911 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2914 call_operand (rtx op, enum machine_mode mode)
2916 if (mode != VOIDmode && GET_MODE (op) != mode)
2919 return (GET_CODE (op) == SYMBOL_REF
2920 || (GET_CODE (op) == REG
2921 && (REGNO (op) == LINK_REGISTER_REGNUM
2922 || REGNO (op) == COUNT_REGISTER_REGNUM
2923 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2926 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2930 current_file_function_operand (rtx op,
2931 enum machine_mode mode ATTRIBUTE_UNUSED)
2933 return (GET_CODE (op) == SYMBOL_REF
2934 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2935 && (SYMBOL_REF_LOCAL_P (op)
2936 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2939 /* Return 1 if this operand is a valid input for a move insn. */
2942 input_operand (rtx op, enum machine_mode mode)
2944 /* Memory is always valid. */
2945 if (memory_operand (op, mode))
2948 /* For floating-point, easy constants are valid. */
2949 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2951 && easy_fp_constant (op, mode))
2954 /* Allow any integer constant. */
2955 if (GET_MODE_CLASS (mode) == MODE_INT
2956 && (GET_CODE (op) == CONST_INT
2957 || GET_CODE (op) == CONST_DOUBLE))
2960 /* Allow easy vector constants. */
2961 if (GET_CODE (op) == CONST_VECTOR
2962 && easy_vector_constant (op, mode))
2965 /* For floating-point or multi-word mode, the only remaining valid type
2967 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2968 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2969 return register_operand (op, mode);
2971 /* The only cases left are integral modes one word or smaller (we
2972 do not get called for MODE_CC values). These can be in any
2974 if (register_operand (op, mode))
2977 /* A SYMBOL_REF referring to the TOC is valid. */
2978 if (legitimate_constant_pool_address_p (op))
2981 /* A constant pool expression (relative to the TOC) is valid */
2982 if (toc_relative_expr_p (op))
2985 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2987 if (DEFAULT_ABI == ABI_V4
2988 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2989 && small_data_operand (op, Pmode))
2996 /* Darwin, AIX increases natural record alignment to doubleword if the first
2997 field is an FP double while the FP fields remain word aligned. */
3000 rs6000_special_round_type_align (tree type, int computed, int specified)
3002 tree field = TYPE_FIELDS (type);
3004 /* Skip all the static variables only if ABI is greater than
3006 while (field != NULL && TREE_CODE (field) == VAR_DECL)
3007 field = TREE_CHAIN (field);
3009 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
3010 return MAX (computed, specified);
3012 return MAX (MAX (computed, specified), 64);
3015 /* Return 1 for an operand in small memory on V.4/eabi. */
3018 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3019 enum machine_mode mode ATTRIBUTE_UNUSED)
3024 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3027 if (DEFAULT_ABI != ABI_V4)
3030 if (GET_CODE (op) == SYMBOL_REF)
3033 else if (GET_CODE (op) != CONST
3034 || GET_CODE (XEXP (op, 0)) != PLUS
3035 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3036 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3041 rtx sum = XEXP (op, 0);
3042 HOST_WIDE_INT summand;
3044 /* We have to be careful here, because it is the referenced address
3045 that must be 32k from _SDA_BASE_, not just the symbol. */
3046 summand = INTVAL (XEXP (sum, 1));
3047 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3050 sym_ref = XEXP (sum, 0);
3053 return SYMBOL_REF_SMALL_P (sym_ref);
3059 /* Return true, if operand is a memory operand and has a
3060 displacement divisible by 4. */
3063 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3068 if (!memory_operand (op, mode))
3071 addr = XEXP (op, 0);
3072 if (GET_CODE (addr) == PLUS
3073 && GET_CODE (XEXP (addr, 0)) == REG
3074 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3075 off = INTVAL (XEXP (addr, 1));
3077 return (off % 4) == 0;
3080 /* Return true if either operand is a general purpose register. */
3083 gpr_or_gpr_p (rtx op0, rtx op1)
3085 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3086 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3090 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3093 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3095 switch (GET_CODE(op))
3098 if (RS6000_SYMBOL_REF_TLS_P (op))
3100 else if (CONSTANT_POOL_ADDRESS_P (op))
3102 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3110 else if (! strcmp (XSTR (op, 0), toc_label_name))
3119 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3120 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3122 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3131 constant_pool_expr_p (rtx op)
3135 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3139 toc_relative_expr_p (rtx op)
3143 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3147 legitimate_constant_pool_address_p (rtx x)
3150 && GET_CODE (x) == PLUS
3151 && GET_CODE (XEXP (x, 0)) == REG
3152 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3153 && constant_pool_expr_p (XEXP (x, 1)));
3157 legitimate_small_data_p (enum machine_mode mode, rtx x)
3159 return (DEFAULT_ABI == ABI_V4
3160 && !flag_pic && !TARGET_TOC
3161 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3162 && small_data_operand (x, mode));
3165 /* SPE offset addressing is limited to 5-bits worth of double words. */
3166 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3169 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3171 unsigned HOST_WIDE_INT offset, extra;
3173 if (GET_CODE (x) != PLUS)
3175 if (GET_CODE (XEXP (x, 0)) != REG)
3177 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3179 if (legitimate_constant_pool_address_p (x))
3181 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3184 offset = INTVAL (XEXP (x, 1));
3192 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3193 which leaves the only valid constant offset of zero, which by
3194 canonicalization rules is also invalid. */
3201 /* SPE vector modes. */
3202 return SPE_CONST_OFFSET_OK (offset);
3205 if (TARGET_E500_DOUBLE)
3206 return SPE_CONST_OFFSET_OK (offset);
3209 if (mode == DFmode || !TARGET_POWERPC64)
3211 else if (offset & 3)
3217 if (mode == TFmode || !TARGET_POWERPC64)
3219 else if (offset & 3)
3230 return (offset < 0x10000) && (offset + extra < 0x10000);
3234 legitimate_indexed_address_p (rtx x, int strict)
3238 if (GET_CODE (x) != PLUS)
3244 if (!REG_P (op0) || !REG_P (op1))
3247 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
3248 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3249 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3250 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
3254 legitimate_indirect_address_p (rtx x, int strict)
3256 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3260 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3262 if (!TARGET_MACHO || !flag_pic
3263 || mode != SImode || GET_CODE(x) != MEM)
3267 if (GET_CODE (x) != LO_SUM)
3269 if (GET_CODE (XEXP (x, 0)) != REG)
3271 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3275 return CONSTANT_P (x);
3279 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3281 if (GET_CODE (x) != LO_SUM)
3283 if (GET_CODE (XEXP (x, 0)) != REG)
3285 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3287 if (TARGET_E500_DOUBLE && mode == DFmode)
3291 if (TARGET_ELF || TARGET_MACHO)
3293 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3297 if (GET_MODE_NUNITS (mode) != 1)
3299 if (GET_MODE_BITSIZE (mode) > 64)
3302 return CONSTANT_P (x);
3309 /* Try machine-dependent ways of modifying an illegitimate address
3310 to be legitimate. If we find one, return the new, valid address.
3311 This is used from only one place: `memory_address' in explow.c.
3313 OLDX is the address as it was before break_out_memory_refs was
3314 called. In some cases it is useful to look at this to decide what
3317 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3319 It is always safe for this function to do nothing. It exists to
3320 recognize opportunities to optimize the output.
3322 On RS/6000, first check for the sum of a register with a constant
3323 integer that is out of range. If so, generate code to add the
3324 constant with the low-order 16 bits masked to the register and force
3325 this result into another register (this can be done with `cau').
3326 Then generate an address of REG+(CONST&0xffff), allowing for the
3327 possibility of bit 16 being a one.
3329 Then check for the sum of a register and something not constant, try to
3330 load the other things into a register and return the sum. */
3333 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3334 enum machine_mode mode)
3336 if (GET_CODE (x) == SYMBOL_REF)
3338 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3340 return rs6000_legitimize_tls_address (x, model);
3343 if (GET_CODE (x) == PLUS
3344 && GET_CODE (XEXP (x, 0)) == REG
3345 && GET_CODE (XEXP (x, 1)) == CONST_INT
3346 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3348 HOST_WIDE_INT high_int, low_int;
3350 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3351 high_int = INTVAL (XEXP (x, 1)) - low_int;
3352 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3353 GEN_INT (high_int)), 0);
3354 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3356 else if (GET_CODE (x) == PLUS
3357 && GET_CODE (XEXP (x, 0)) == REG
3358 && GET_CODE (XEXP (x, 1)) != CONST_INT
3359 && GET_MODE_NUNITS (mode) == 1
3360 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3362 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3363 && (TARGET_POWERPC64 || mode != DImode)
3366 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3367 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3369 else if (ALTIVEC_VECTOR_MODE (mode))
3373 /* Make sure both operands are registers. */
3374 if (GET_CODE (x) == PLUS)
3375 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3376 force_reg (Pmode, XEXP (x, 1)));
3378 reg = force_reg (Pmode, x);
3381 else if (SPE_VECTOR_MODE (mode)
3382 || (TARGET_E500_DOUBLE && mode == DFmode))
3384 /* We accept [reg + reg] and [reg + OFFSET]. */
3386 if (GET_CODE (x) == PLUS)
3388 rtx op1 = XEXP (x, 0);
3389 rtx op2 = XEXP (x, 1);
3391 op1 = force_reg (Pmode, op1);
3393 if (GET_CODE (op2) != REG
3394 && (GET_CODE (op2) != CONST_INT
3395 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3396 op2 = force_reg (Pmode, op2);
3398 return gen_rtx_PLUS (Pmode, op1, op2);
3401 return force_reg (Pmode, x);
3407 && GET_CODE (x) != CONST_INT
3408 && GET_CODE (x) != CONST_DOUBLE
3410 && GET_MODE_NUNITS (mode) == 1
3411 && (GET_MODE_BITSIZE (mode) <= 32
3412 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3414 rtx reg = gen_reg_rtx (Pmode);
3415 emit_insn (gen_elf_high (reg, x));
3416 return gen_rtx_LO_SUM (Pmode, reg, x);
3418 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3421 && ! MACHO_DYNAMIC_NO_PIC_P
3423 && GET_CODE (x) != CONST_INT
3424 && GET_CODE (x) != CONST_DOUBLE
3426 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3430 rtx reg = gen_reg_rtx (Pmode);
3431 emit_insn (gen_macho_high (reg, x));
3432 return gen_rtx_LO_SUM (Pmode, reg, x);
3435 && constant_pool_expr_p (x)
3436 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3438 return create_TOC_reference (x);
3444 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3445 We need to emit DTP-relative relocations. */
3448 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3453 fputs ("\t.long\t", file);
3456 fputs (DOUBLE_INT_ASM_OP, file);
3461 output_addr_const (file, x);
3462 fputs ("@dtprel+0x8000", file);
3465 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3467 static GTY(()) rtx rs6000_tls_symbol;
3469 rs6000_tls_get_addr (void)
3471 if (!rs6000_tls_symbol)
3472 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3474 return rs6000_tls_symbol;
3477 /* Construct the SYMBOL_REF for TLS GOT references. */
3479 static GTY(()) rtx rs6000_got_symbol;
3481 rs6000_got_sym (void)
3483 if (!rs6000_got_symbol)
3485 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3486 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3487 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3490 return rs6000_got_symbol;
3493 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3494 this (thread-local) address. */
3497 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3501 dest = gen_reg_rtx (Pmode);
3502 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3508 tlsreg = gen_rtx_REG (Pmode, 13);
3509 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3513 tlsreg = gen_rtx_REG (Pmode, 2);
3514 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3518 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3522 tmp = gen_reg_rtx (Pmode);
3525 tlsreg = gen_rtx_REG (Pmode, 13);
3526 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3530 tlsreg = gen_rtx_REG (Pmode, 2);
3531 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3535 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3537 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3542 rtx r3, got, tga, tmp1, tmp2, eqv;
3545 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3549 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3552 rtx gsym = rs6000_got_sym ();
3553 got = gen_reg_rtx (Pmode);
3555 rs6000_emit_move (got, gsym, Pmode);
3559 static int tls_got_labelno = 0;
3560 rtx tempLR, lab, tmp3, mem;
3563 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
3564 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
3565 tempLR = gen_reg_rtx (Pmode);
3566 tmp1 = gen_reg_rtx (Pmode);
3567 tmp2 = gen_reg_rtx (Pmode);
3568 tmp3 = gen_reg_rtx (Pmode);
3569 mem = gen_const_mem (Pmode, tmp1);
3571 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
3573 emit_move_insn (tmp1, tempLR);
3574 emit_move_insn (tmp2, mem);
3575 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3576 last = emit_move_insn (got, tmp3);
3577 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3579 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3581 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3587 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3589 r3 = gen_rtx_REG (Pmode, 3);
3591 insn = gen_tls_gd_64 (r3, got, addr);
3593 insn = gen_tls_gd_32 (r3, got, addr);
3596 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3597 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3598 insn = emit_call_insn (insn);
3599 CONST_OR_PURE_CALL_P (insn) = 1;
3600 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3601 insn = get_insns ();
3603 emit_libcall_block (insn, dest, r3, addr);
3605 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3607 r3 = gen_rtx_REG (Pmode, 3);
3609 insn = gen_tls_ld_64 (r3, got);
3611 insn = gen_tls_ld_32 (r3, got);
3614 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3615 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3616 insn = emit_call_insn (insn);
3617 CONST_OR_PURE_CALL_P (insn) = 1;
3618 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3619 insn = get_insns ();
3621 tmp1 = gen_reg_rtx (Pmode);
3622 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3624 emit_libcall_block (insn, tmp1, r3, eqv);
3625 if (rs6000_tls_size == 16)
3628 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3630 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3632 else if (rs6000_tls_size == 32)
3634 tmp2 = gen_reg_rtx (Pmode);
3636 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3638 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3641 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3643 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3647 tmp2 = gen_reg_rtx (Pmode);
3649 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3651 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3653 insn = gen_rtx_SET (Pmode, dest,
3654 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3660 /* IE, or 64 bit offset LE. */
3661 tmp2 = gen_reg_rtx (Pmode);
3663 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3665 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3668 insn = gen_tls_tls_64 (dest, tmp2, addr);
3670 insn = gen_tls_tls_32 (dest, tmp2, addr);
3678 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3679 instruction definitions. */
3682 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3684 return RS6000_SYMBOL_REF_TLS_P (x);
3687 /* Return 1 if X contains a thread-local symbol. */
3690 rs6000_tls_referenced_p (rtx x)
3692 if (! TARGET_HAVE_TLS)
3695 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3698 /* Return 1 if *X is a thread-local symbol. This is the same as
3699 rs6000_tls_symbol_ref except for the type of the unused argument. */
3702 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3704 return RS6000_SYMBOL_REF_TLS_P (*x);
3707 /* The convention appears to be to define this wherever it is used.
3708 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3709 is now used here. */
3710 #ifndef REG_MODE_OK_FOR_BASE_P
3711 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3714 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3715 replace the input X, or the original X if no replacement is called for.
3716 The output parameter *WIN is 1 if the calling macro should goto WIN,
3719 For RS/6000, we wish to handle large displacements off a base
3720 register by splitting the addend across an addiu/addis and the mem insn.
3721 This cuts number of extra insns needed from 3 to 1.
3723 On Darwin, we use this to generate code for floating point constants.
3724 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3725 The Darwin code is inside #if TARGET_MACHO because only then is
3726 machopic_function_base_name() defined. */
3728 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3729 int opnum, int type,
3730 int ind_levels ATTRIBUTE_UNUSED, int *win)
3732 /* We must recognize output that we have already generated ourselves. */
3733 if (GET_CODE (x) == PLUS
3734 && GET_CODE (XEXP (x, 0)) == PLUS
3735 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3736 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3737 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3739 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3740 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3741 opnum, (enum reload_type)type);
3747 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3748 && GET_CODE (x) == LO_SUM
3749 && GET_CODE (XEXP (x, 0)) == PLUS
3750 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3751 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3752 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3753 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3754 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3755 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3756 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3758 /* Result of previous invocation of this function on Darwin
3759 floating point constant. */
3760 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3761 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3762 opnum, (enum reload_type)type);
3767 if (GET_CODE (x) == PLUS
3768 && GET_CODE (XEXP (x, 0)) == REG
3769 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3770 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3771 && GET_CODE (XEXP (x, 1)) == CONST_INT
3772 && !SPE_VECTOR_MODE (mode)
3773 && !(TARGET_E500_DOUBLE && mode == DFmode)
3774 && !ALTIVEC_VECTOR_MODE (mode))
3776 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3777 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3779 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3781 /* Check for 32-bit overflow. */
3782 if (high + low != val)
3788 /* Reload the high part into a base reg; leave the low part
3789 in the mem directly. */
3791 x = gen_rtx_PLUS (GET_MODE (x),
3792 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3796 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3797 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3798 opnum, (enum reload_type)type);
3803 if (GET_CODE (x) == SYMBOL_REF
3804 && DEFAULT_ABI == ABI_DARWIN
3805 && !ALTIVEC_VECTOR_MODE (mode)
3806 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3807 /* Don't do this for TFmode, since the result isn't offsettable. */
3812 rtx offset = gen_rtx_CONST (Pmode,
3813 gen_rtx_MINUS (Pmode, x,
3814 machopic_function_base_sym ()));
3815 x = gen_rtx_LO_SUM (GET_MODE (x),
3816 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3817 gen_rtx_HIGH (Pmode, offset)), offset);
3820 x = gen_rtx_LO_SUM (GET_MODE (x),
3821 gen_rtx_HIGH (Pmode, x), x);
3823 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3824 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3825 opnum, (enum reload_type)type);
3831 && constant_pool_expr_p (x)
3832 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3834 (x) = create_TOC_reference (x);
3842 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3843 that is a valid memory address for an instruction.
3844 The MODE argument is the machine mode for the MEM expression
3845 that wants to use this address.
3847 On the RS/6000, there are four valid address: a SYMBOL_REF that
3848 refers to a constant pool entry of an address (or the sum of it
3849 plus a constant), a short (16-bit signed) constant plus a register,
3850 the sum of two registers, or a register indirect, possibly with an
3851 auto-increment. For DFmode and DImode with a constant plus register,
3852 we must ensure that both words are addressable or PowerPC64 with offset
3855 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3856 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3857 adjacent memory cells are accessed by adding word-sized offsets
3858 during assembly output. */
3860 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3862 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3864 && ALTIVEC_VECTOR_MODE (mode)
3865 && GET_CODE (x) == AND
3866 && GET_CODE (XEXP (x, 1)) == CONST_INT
3867 && INTVAL (XEXP (x, 1)) == -16)
3870 if (RS6000_SYMBOL_REF_TLS_P (x))
3872 if (legitimate_indirect_address_p (x, reg_ok_strict))
3874 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3875 && !ALTIVEC_VECTOR_MODE (mode)
3876 && !SPE_VECTOR_MODE (mode)
3877 && !(TARGET_E500_DOUBLE && mode == DFmode)
3879 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3881 if (legitimate_small_data_p (mode, x))
3883 if (legitimate_constant_pool_address_p (x))
3885 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3887 && GET_CODE (x) == PLUS
3888 && GET_CODE (XEXP (x, 0)) == REG
3889 && (XEXP (x, 0) == virtual_stack_vars_rtx
3890 || XEXP (x, 0) == arg_pointer_rtx)
3891 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3893 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3897 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3899 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3900 && (TARGET_POWERPC64 || mode != DImode)
3901 && legitimate_indexed_address_p (x, reg_ok_strict))
3903 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3908 /* Go to LABEL if ADDR (a legitimate address expression)
3909 has an effect that depends on the machine mode it is used for.
3911 On the RS/6000 this is true of all integral offsets (since AltiVec
3912 modes don't allow them) or is a pre-increment or decrement.
3914 ??? Except that due to conceptual problems in offsettable_address_p
3915 we can't really report the problems of integral offsets. So leave
3916 this assuming that the adjustable offset must be valid for the
3917 sub-words of a TFmode operand, which is what we had before. */
3920 rs6000_mode_dependent_address (rtx addr)
3922 switch (GET_CODE (addr))
3925 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3927 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3928 return val + 12 + 0x8000 >= 0x10000;
3937 return TARGET_UPDATE;
3946 /* Return number of consecutive hard regs needed starting at reg REGNO
3947 to hold something of mode MODE.
3948 This is ordinarily the length in words of a value of mode MODE
3949 but can be less for certain modes in special long registers.
3951 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3952 scalar instructions. The upper 32 bits are only available to the
3955 POWER and PowerPC GPRs hold 32 bits worth;
3956 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3959 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3961 if (FP_REGNO_P (regno))
3962 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3964 if (TARGET_E500_DOUBLE && mode == DFmode)
3967 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3968 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3970 if (ALTIVEC_REGNO_P (regno))
3972 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3974 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3977 /* Change register usage conditional on target flags. */
3979 rs6000_conditional_register_usage (void)
3983 /* Set MQ register fixed (already call_used) if not POWER
3984 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3989 /* 64-bit AIX reserves GPR13 for thread-private data. */
3991 fixed_regs[13] = call_used_regs[13]
3992 = call_really_used_regs[13] = 1;
3994 /* Conditionally disable FPRs. */
3995 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3996 for (i = 32; i < 64; i++)
3997 fixed_regs[i] = call_used_regs[i]
3998 = call_really_used_regs[i] = 1;
4000 if (DEFAULT_ABI == ABI_V4
4001 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4003 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4005 if (DEFAULT_ABI == ABI_V4
4006 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4008 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4009 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4010 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4012 if (DEFAULT_ABI == ABI_DARWIN
4013 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4014 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4015 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4016 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4017 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4019 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4020 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4021 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4024 global_regs[VSCR_REGNO] = 1;
4028 global_regs[SPEFSCR_REGNO] = 1;
4029 fixed_regs[FIXED_SCRATCH]
4030 = call_used_regs[FIXED_SCRATCH]
4031 = call_really_used_regs[FIXED_SCRATCH] = 1;
4034 if (! TARGET_ALTIVEC)
4036 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4037 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4038 call_really_used_regs[VRSAVE_REGNO] = 1;
4041 if (TARGET_ALTIVEC_ABI)
4042 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4043 call_used_regs[i] = call_really_used_regs[i] = 1;
4046 /* Try to output insns to set TARGET equal to the constant C if it can
4047 be done in less than N insns. Do all computations in MODE.
4048 Returns the place where the output has been placed if it can be
4049 done and the insns have been emitted. If it would take more than N
4050 insns, zero is returned and no insns and emitted. */
4053 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4054 rtx source, int n ATTRIBUTE_UNUSED)
4056 rtx result, insn, set;
4057 HOST_WIDE_INT c0, c1;
4059 if (mode == QImode || mode == HImode)
4062 dest = gen_reg_rtx (mode);
4063 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4066 else if (mode == SImode)
4068 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4070 emit_insn (gen_rtx_SET (VOIDmode, result,
4071 GEN_INT (INTVAL (source)
4072 & (~ (HOST_WIDE_INT) 0xffff))));
4073 emit_insn (gen_rtx_SET (VOIDmode, dest,
4074 gen_rtx_IOR (SImode, result,
4075 GEN_INT (INTVAL (source) & 0xffff))));
4078 else if (mode == DImode)
4080 if (GET_CODE (source) == CONST_INT)
4082 c0 = INTVAL (source);
4085 else if (GET_CODE (source) == CONST_DOUBLE)
4087 #if HOST_BITS_PER_WIDE_INT >= 64
4088 c0 = CONST_DOUBLE_LOW (source);
4091 c0 = CONST_DOUBLE_LOW (source);
4092 c1 = CONST_DOUBLE_HIGH (source);
4098 result = rs6000_emit_set_long_const (dest, c0, c1);
4103 insn = get_last_insn ();
4104 set = single_set (insn);
4105 if (! CONSTANT_P (SET_SRC (set)))
4106 set_unique_reg_note (insn, REG_EQUAL, source);
4111 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4112 fall back to a straight forward decomposition. We do this to avoid
4113 exponential run times encountered when looking for longer sequences
4114 with rs6000_emit_set_const. */
4116 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4118 if (!TARGET_POWERPC64)
4120 rtx operand1, operand2;
4122 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4124 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4126 emit_move_insn (operand1, GEN_INT (c1));
4127 emit_move_insn (operand2, GEN_INT (c2));
4131 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4134 ud2 = (c1 & 0xffff0000) >> 16;
4135 #if HOST_BITS_PER_WIDE_INT >= 64
4139 ud4 = (c2 & 0xffff0000) >> 16;
4141 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4142 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4145 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4147 emit_move_insn (dest, GEN_INT (ud1));
4150 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4151 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4154 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4157 emit_move_insn (dest, GEN_INT (ud2 << 16));
4159 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4161 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4162 || (ud4 == 0 && ! (ud3 & 0x8000)))
4165 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4168 emit_move_insn (dest, GEN_INT (ud3 << 16));
4171 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4172 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4174 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4179 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4182 emit_move_insn (dest, GEN_INT (ud4 << 16));
4185 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4187 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4189 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4190 GEN_INT (ud2 << 16)));
4192 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4198 /* Helper for the following. Get rid of [r+r] memory refs
4199 in cases where it won't work (TImode, TFmode). */
4202 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4204 if (GET_CODE (operands[0]) == MEM
4205 && GET_CODE (XEXP (operands[0], 0)) != REG
4206 && ! reload_in_progress)
4208 = replace_equiv_address (operands[0],
4209 copy_addr_to_reg (XEXP (operands[0], 0)));
4211 if (GET_CODE (operands[1]) == MEM
4212 && GET_CODE (XEXP (operands[1], 0)) != REG
4213 && ! reload_in_progress)
4215 = replace_equiv_address (operands[1],
4216 copy_addr_to_reg (XEXP (operands[1], 0)));
4219 /* Emit a move from SOURCE to DEST in mode MODE. */
4221 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4225 operands[1] = source;
4227 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4228 if (GET_CODE (operands[1]) == CONST_DOUBLE
4229 && ! FLOAT_MODE_P (mode)
4230 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4232 /* FIXME. This should never happen. */
4233 /* Since it seems that it does, do the safe thing and convert
4235 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4237 if (GET_CODE (operands[1]) == CONST_DOUBLE
4238 && ! FLOAT_MODE_P (mode)
4239 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
4240 && CONST_DOUBLE_LOW (operands[1]) >= 0)
4241 || (CONST_DOUBLE_HIGH (operands[1]) == -1
4242 && CONST_DOUBLE_LOW (operands[1]) < 0)))
4245 /* Check if GCC is setting up a block move that will end up using FP
4246 registers as temporaries. We must make sure this is acceptable. */
4247 if (GET_CODE (operands[0]) == MEM
4248 && GET_CODE (operands[1]) == MEM
4250 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4251 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4252 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4253 ? 32 : MEM_ALIGN (operands[0])))
4254 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4256 : MEM_ALIGN (operands[1]))))
4257 && ! MEM_VOLATILE_P (operands [0])
4258 && ! MEM_VOLATILE_P (operands [1]))
4260 emit_move_insn (adjust_address (operands[0], SImode, 0),
4261 adjust_address (operands[1], SImode, 0));
4262 emit_move_insn (adjust_address (operands[0], SImode, 4),
4263 adjust_address (operands[1], SImode, 4));
4267 if (!no_new_pseudos && GET_CODE (operands[0]) != REG)
4268 operands[1] = force_reg (mode, operands[1]);
4270 if (mode == SFmode && ! TARGET_POWERPC
4271 && TARGET_HARD_FLOAT && TARGET_FPRS
4272 && GET_CODE (operands[0]) == MEM)
4276 if (reload_in_progress || reload_completed)
4277 regnum = true_regnum (operands[1]);
4278 else if (GET_CODE (operands[1]) == REG)
4279 regnum = REGNO (operands[1]);
4283 /* If operands[1] is a register, on POWER it may have
4284 double-precision data in it, so truncate it to single
4286 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4289 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4290 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4291 operands[1] = newreg;
4295 /* Recognize the case where operand[1] is a reference to thread-local
4296 data and load its address to a register. */
4297 if (GET_CODE (operands[1]) == SYMBOL_REF)
4299 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
4301 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
4304 /* Handle the case where reload calls us with an invalid address. */
4305 if (reload_in_progress && mode == Pmode
4306 && (! general_operand (operands[1], mode)
4307 || ! nonimmediate_operand (operands[0], mode)))
4310 /* 128-bit constant floating-point values on Darwin should really be
4311 loaded as two parts. */
4312 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
4313 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4314 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4316 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4317 know how to get a DFmode SUBREG of a TFmode. */
4318 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4319 simplify_gen_subreg (DImode, operands[1], mode, 0),
4321 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4322 GET_MODE_SIZE (DImode)),
4323 simplify_gen_subreg (DImode, operands[1], mode,
4324 GET_MODE_SIZE (DImode)),
4329 /* FIXME: In the long term, this switch statement should go away
4330 and be replaced by a sequence of tests based on things like
4336 if (CONSTANT_P (operands[1])
4337 && GET_CODE (operands[1]) != CONST_INT)
4338 operands[1] = force_const_mem (mode, operands[1]);
4342 rs6000_eliminate_indexed_memrefs (operands);
4347 if (CONSTANT_P (operands[1])
4348 && ! easy_fp_constant (operands[1], mode))
4349 operands[1] = force_const_mem (mode, operands[1]);
4360 if (CONSTANT_P (operands[1])
4361 && !easy_vector_constant (operands[1], mode))
4362 operands[1] = force_const_mem (mode, operands[1]);
4367 /* Use default pattern for address of ELF small data */
4370 && DEFAULT_ABI == ABI_V4
4371 && (GET_CODE (operands[1]) == SYMBOL_REF
4372 || GET_CODE (operands[1]) == CONST)
4373 && small_data_operand (operands[1], mode))
4375 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4379 if (DEFAULT_ABI == ABI_V4
4380 && mode == Pmode && mode == SImode
4381 && flag_pic == 1 && got_operand (operands[1], mode))
4383 emit_insn (gen_movsi_got (operands[0], operands[1]));
4387 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4391 && CONSTANT_P (operands[1])
4392 && GET_CODE (operands[1]) != HIGH
4393 && GET_CODE (operands[1]) != CONST_INT)
4395 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4397 /* If this is a function address on -mcall-aixdesc,
4398 convert it to the address of the descriptor. */
4399 if (DEFAULT_ABI == ABI_AIX
4400 && GET_CODE (operands[1]) == SYMBOL_REF
4401 && XSTR (operands[1], 0)[0] == '.')
4403 const char *name = XSTR (operands[1], 0);
4405 while (*name == '.')
4407 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4408 CONSTANT_POOL_ADDRESS_P (new_ref)
4409 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4410 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4411 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4412 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
4413 operands[1] = new_ref;
4416 if (DEFAULT_ABI == ABI_DARWIN)
4419 if (MACHO_DYNAMIC_NO_PIC_P)
4421 /* Take care of any required data indirection. */
4422 operands[1] = rs6000_machopic_legitimize_pic_address (
4423 operands[1], mode, operands[0]);
4424 if (operands[0] != operands[1])
4425 emit_insn (gen_rtx_SET (VOIDmode,
4426 operands[0], operands[1]));
4432 emit_insn (gen_macho_high_di (target, operands[1]));
4433 emit_insn (gen_macho_low_di (operands[0], target, operands[1]));
4437 emit_insn (gen_macho_high (target, operands[1]));
4438 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4443 emit_insn (gen_elf_high (target, operands[1]));
4444 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4448 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4449 and we have put it in the TOC, we just need to make a TOC-relative
4452 && GET_CODE (operands[1]) == SYMBOL_REF
4453 && constant_pool_expr_p (operands[1])
4454 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4455 get_pool_mode (operands[1])))
4457 operands[1] = create_TOC_reference (operands[1]);
4459 else if (mode == Pmode
4460 && CONSTANT_P (operands[1])
4461 && ((GET_CODE (operands[1]) != CONST_INT
4462 && ! easy_fp_constant (operands[1], mode))
4463 || (GET_CODE (operands[1]) == CONST_INT
4464 && num_insns_constant (operands[1], mode) > 2)
4465 || (GET_CODE (operands[0]) == REG
4466 && FP_REGNO_P (REGNO (operands[0]))))
4467 && GET_CODE (operands[1]) != HIGH
4468 && ! legitimate_constant_pool_address_p (operands[1])
4469 && ! toc_relative_expr_p (operands[1]))
4471 /* Emit a USE operation so that the constant isn't deleted if
4472 expensive optimizations are turned on because nobody
4473 references it. This should only be done for operands that
4474 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4475 This should not be done for operands that contain LABEL_REFs.
4476 For now, we just handle the obvious case. */
4477 if (GET_CODE (operands[1]) != LABEL_REF)
4478 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4481 /* Darwin uses a special PIC legitimizer. */
4482 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4485 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4487 if (operands[0] != operands[1])
4488 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4493 /* If we are to limit the number of things we put in the TOC and
4494 this is a symbol plus a constant we can add in one insn,
4495 just put the symbol in the TOC and add the constant. Don't do
4496 this if reload is in progress. */
4497 if (GET_CODE (operands[1]) == CONST
4498 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4499 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4500 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4501 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4502 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4503 && ! side_effects_p (operands[0]))
4506 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4507 rtx other = XEXP (XEXP (operands[1], 0), 1);
4509 sym = force_reg (mode, sym);
4511 emit_insn (gen_addsi3 (operands[0], sym, other));
4513 emit_insn (gen_adddi3 (operands[0], sym, other));
4517 operands[1] = force_const_mem (mode, operands[1]);
4520 && constant_pool_expr_p (XEXP (operands[1], 0))
4521 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4522 get_pool_constant (XEXP (operands[1], 0)),
4523 get_pool_mode (XEXP (operands[1], 0))))
4526 = gen_const_mem (mode,
4527 create_TOC_reference (XEXP (operands[1], 0)));
4528 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4534 rs6000_eliminate_indexed_memrefs (operands);
4538 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4540 gen_rtx_SET (VOIDmode,
4541 operands[0], operands[1]),
4542 gen_rtx_CLOBBER (VOIDmode,
4543 gen_rtx_SCRATCH (SImode)))));
4552 /* Above, we may have called force_const_mem which may have returned
4553 an invalid address. If we can, fix this up; otherwise, reload will
4554 have to deal with it. */
4555 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4556 operands[1] = validize_mem (operands[1]);
4559 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4562 /* Nonzero if we can use a floating-point register to pass this arg. */
4563 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4564 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4565 && (CUM)->fregno <= FP_ARG_MAX_REG \
4566 && TARGET_HARD_FLOAT && TARGET_FPRS)
4568 /* Nonzero if we can use an AltiVec register to pass this arg. */
4569 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4570 (ALTIVEC_VECTOR_MODE (MODE) \
4571 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4572 && TARGET_ALTIVEC_ABI \
4575 /* Return a nonzero value to say to return the function value in
4576 memory, just as large structures are always returned. TYPE will be
4577 the data type of the value, and FNTYPE will be the type of the
4578 function doing the returning, or @code{NULL} for libcalls.
4580 The AIX ABI for the RS/6000 specifies that all structures are
4581 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4582 specifies that structures <= 8 bytes are returned in r3/r4, but a
4583 draft put them in memory, and GCC used to implement the draft
4584 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4585 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4586 compatibility can change DRAFT_V4_STRUCT_RET to override the
4587 default, and -m switches get the final word. See
4588 rs6000_override_options for more details.
4590 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4591 long double support is enabled. These values are returned in memory.
4593 int_size_in_bytes returns -1 for variable size objects, which go in
4594 memory always. The cast to unsigned makes -1 > 8. */
4597 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4599 if (AGGREGATE_TYPE_P (type)
4600 && (TARGET_AIX_STRUCT_RET
4601 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4603 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4608 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4609 for a call to a function whose data type is FNTYPE.
4610 For a library call, FNTYPE is 0.
4612 For incoming args we set the number of arguments in the prototype large
4613 so we never return a PARALLEL. */
4616 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4617 rtx libname ATTRIBUTE_UNUSED, int incoming,
4618 int libcall, int n_named_args)
4620 static CUMULATIVE_ARGS zero_cumulative;
4622 *cum = zero_cumulative;
4624 cum->fregno = FP_ARG_MIN_REG;
4625 cum->vregno = ALTIVEC_ARG_MIN_REG;
4626 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4627 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4628 ? CALL_LIBCALL : CALL_NORMAL);
4629 cum->sysv_gregno = GP_ARG_MIN_REG;
4630 cum->stdarg = fntype
4631 && (TYPE_ARG_TYPES (fntype) != 0
4632 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4633 != void_type_node));
4635 cum->nargs_prototype = 0;
4636 if (incoming || cum->prototype)
4637 cum->nargs_prototype = n_named_args;
4639 /* Check for a longcall attribute. */
4641 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4642 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
4643 cum->call_cookie = CALL_LONG;
4645 if (TARGET_DEBUG_ARG)
4647 fprintf (stderr, "\ninit_cumulative_args:");
4650 tree ret_type = TREE_TYPE (fntype);
4651 fprintf (stderr, " ret code = %s,",
4652 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4655 if (cum->call_cookie & CALL_LONG)
4656 fprintf (stderr, " longcall,");
4658 fprintf (stderr, " proto = %d, nargs = %d\n",
4659 cum->prototype, cum->nargs_prototype);
4664 && TARGET_ALTIVEC_ABI
4665 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4667 error ("Cannot return value in vector register because"
4668 " altivec instructions are disabled, use -maltivec"
4669 " to enable them.");
4673 /* Return true if TYPE must be passed on the stack and not in registers. */
4676 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4678 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4679 return must_pass_in_stack_var_size (mode, type);
4681 return must_pass_in_stack_var_size_or_pad (mode, type);
4684 /* If defined, a C expression which determines whether, and in which
4685 direction, to pad out an argument with extra space. The value
4686 should be of type `enum direction': either `upward' to pad above
4687 the argument, `downward' to pad below, or `none' to inhibit
4690 For the AIX ABI structs are always stored left shifted in their
4694 function_arg_padding (enum machine_mode mode, tree type)
4696 #ifndef AGGREGATE_PADDING_FIXED
4697 #define AGGREGATE_PADDING_FIXED 0
4699 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4700 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4703 if (!AGGREGATE_PADDING_FIXED)
4705 /* GCC used to pass structures of the same size as integer types as
4706 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4707 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4708 passed padded downward, except that -mstrict-align further
4709 muddied the water in that multi-component structures of 2 and 4
4710 bytes in size were passed padded upward.
4712 The following arranges for best compatibility with previous
4713 versions of gcc, but removes the -mstrict-align dependency. */
4714 if (BYTES_BIG_ENDIAN)
4716 HOST_WIDE_INT size = 0;
4718 if (mode == BLKmode)
4720 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4721 size = int_size_in_bytes (type);
4724 size = GET_MODE_SIZE (mode);
4726 if (size == 1 || size == 2 || size == 4)
4732 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4734 if (type != 0 && AGGREGATE_TYPE_P (type))
4738 /* Fall back to the default. */
4739 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4742 /* If defined, a C expression that gives the alignment boundary, in bits,
4743 of an argument with the specified mode and type. If it is not defined,
4744 PARM_BOUNDARY is used for all arguments.
4746 V.4 wants long longs to be double word aligned. */
4749 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
4751 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4753 else if (SPE_VECTOR_MODE (mode))
4755 else if (ALTIVEC_VECTOR_MODE (mode))
4758 return PARM_BOUNDARY;
4761 /* Compute the size (in words) of a function argument. */
4763 static unsigned long
4764 rs6000_arg_size (enum machine_mode mode, tree type)
4768 if (mode != BLKmode)
4769 size = GET_MODE_SIZE (mode);
4771 size = int_size_in_bytes (type);
4774 return (size + 3) >> 2;
4776 return (size + 7) >> 3;
4779 /* Update the data in CUM to advance over an argument
4780 of mode MODE and data type TYPE.
4781 (TYPE is null for libcalls where that information may not be available.)
4783 Note that for args passed by reference, function_arg will be called
4784 with MODE and TYPE set to that of the pointer to the arg, not the arg
4788 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4789 tree type, int named)
4791 cum->nargs_prototype--;
4793 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4797 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4800 if (!TARGET_ALTIVEC)
4801 error ("Cannot pass argument in vector register because"
4802 " altivec instructions are disabled, use -maltivec"
4803 " to enable them.");
4805 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4806 even if it is going to be passed in a vector register.
4807 Darwin does the same for variable-argument functions. */
4808 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4809 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4819 /* Vector parameters must be 16-byte aligned. This places
4820 them at 2 mod 4 in terms of words in 32-bit mode, since
4821 the parameter save area starts at offset 24 from the
4822 stack. In 64-bit mode, they just have to start on an
4823 even word, since the parameter save area is 16-byte
4824 aligned. Space for GPRs is reserved even if the argument
4825 will be passed in memory. */
4827 align = (2 - cum->words) & 3;
4829 align = cum->words & 1;
4830 cum->words += align + rs6000_arg_size (mode, type);
4832 if (TARGET_DEBUG_ARG)
4834 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4836 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4837 cum->nargs_prototype, cum->prototype,
4838 GET_MODE_NAME (mode));
4842 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4844 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4846 else if (DEFAULT_ABI == ABI_V4)
4848 if (TARGET_HARD_FLOAT && TARGET_FPRS
4849 && (mode == SFmode || mode == DFmode))
4851 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4856 cum->words += cum->words & 1;
4857 cum->words += rs6000_arg_size (mode, type);
4862 int n_words = rs6000_arg_size (mode, type);
4863 int gregno = cum->sysv_gregno;
4865 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4866 (r7,r8) or (r9,r10). As does any other 2 word item such
4867 as complex int due to a historical mistake. */
4869 gregno += (1 - gregno) & 1;
4871 /* Multi-reg args are not split between registers and stack. */
4872 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4874 /* Long long and SPE vectors are aligned on the stack.
4875 So are other 2 word items such as complex int due to
4876 a historical mistake. */
4878 cum->words += cum->words & 1;
4879 cum->words += n_words;
4882 /* Note: continuing to accumulate gregno past when we've started
4883 spilling to the stack indicates the fact that we've started
4884 spilling to the stack to expand_builtin_saveregs. */
4885 cum->sysv_gregno = gregno + n_words;
4888 if (TARGET_DEBUG_ARG)
4890 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4891 cum->words, cum->fregno);
4892 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4893 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4894 fprintf (stderr, "mode = %4s, named = %d\n",
4895 GET_MODE_NAME (mode), named);
4900 int n_words = rs6000_arg_size (mode, type);
4901 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4903 /* The simple alignment calculation here works because
4904 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
4905 If we ever want to handle alignments larger than 8 bytes for
4906 32-bit or 16 bytes for 64-bit, then we'll need to take into
4907 account the offset to the start of the parm save area. */
4908 align &= cum->words;
4909 cum->words += align + n_words;
4911 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4912 && TARGET_HARD_FLOAT && TARGET_FPRS)
4913 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4915 if (TARGET_DEBUG_ARG)
4917 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4918 cum->words, cum->fregno);
4919 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4920 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4921 fprintf (stderr, "named = %d, align = %d\n", named, align);
4927 spe_build_register_parallel (enum machine_mode mode, int gregno)
4930 enum machine_mode inner;
4931 unsigned int inner_bytes;
4941 r1 = gen_rtx_REG (inner, gregno);
4942 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
4943 r2 = gen_rtx_REG (inner, gregno + 1);
4944 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (inner_bytes));
4945 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4948 /* Determine where to put a SIMD argument on the SPE. */
4950 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4953 int gregno = cum->sysv_gregno;
4955 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4956 are passed and returned in a pair of GPRs for ABI compatibility. */
4957 if (TARGET_E500_DOUBLE && mode == DFmode)
4959 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4960 gregno += (1 - gregno) & 1;
4962 /* We do not split between registers and stack. */
4963 if (gregno + 1 > GP_ARG_MAX_REG)
4966 return spe_build_register_parallel (mode, gregno);
4970 int n_words = rs6000_arg_size (mode, type);
4972 /* SPE vectors are put in odd registers. */
4973 if (n_words == 2 && (gregno & 1) == 0)
4976 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4979 enum machine_mode m = SImode;
4981 r1 = gen_rtx_REG (m, gregno);
4982 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4983 r2 = gen_rtx_REG (m, gregno + 1);
4984 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4985 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4992 if (gregno <= GP_ARG_MAX_REG)
4993 return gen_rtx_REG (mode, gregno);
4999 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5002 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5006 rtx rvec[GP_ARG_NUM_REG + 1];
5008 if (align_words >= GP_ARG_NUM_REG)
5011 n_units = rs6000_arg_size (mode, type);
5013 /* Optimize the simple case where the arg fits in one gpr, except in
5014 the case of BLKmode due to assign_parms assuming that registers are
5015 BITS_PER_WORD wide. */
5017 || (n_units == 1 && mode != BLKmode))
5018 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5021 if (align_words + n_units > GP_ARG_NUM_REG)
5022 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5023 using a magic NULL_RTX component.
5024 FIXME: This is not strictly correct. Only some of the arg
5025 belongs in memory, not all of it. However, there isn't any way
5026 to do this currently, apart from building rtx descriptions for
5027 the pieces of memory we want stored. Due to bugs in the generic
5028 code we can't use the normal function_arg_partial_nregs scheme
5029 with the PARALLEL arg description we emit here.
5030 In any case, the code to store the whole arg to memory is often
5031 more efficient than code to store pieces, and we know that space
5032 is available in the right place for the whole arg. */
5033 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5038 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5039 rtx off = GEN_INT (i++ * 4);
5040 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5042 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5044 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5047 /* Determine where to put an argument to a function.
5048 Value is zero to push the argument on the stack,
5049 or a hard register in which to store the argument.
5051 MODE is the argument's machine mode.
5052 TYPE is the data type of the argument (as a tree).
5053 This is null for libcalls where that information may
5055 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5056 the preceding args and about the function being called.
5057 NAMED is nonzero if this argument is a named parameter
5058 (otherwise it is an extra parameter matching an ellipsis).
5060 On RS/6000 the first eight words of non-FP are normally in registers
5061 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5062 Under V.4, the first 8 FP args are in registers.
5064 If this is floating-point and no prototype is specified, we use
5065 both an FP and integer register (or possibly FP reg and stack). Library
5066 functions (when CALL_LIBCALL is set) always have the proper types for args,
5067 so we can pass the FP value just in one register. emit_library_function
5068 doesn't support PARALLEL anyway.
5070 Note that for args passed by reference, function_arg will be called
5071 with MODE and TYPE set to that of the pointer to the arg, not the arg
5075 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5076 tree type, int named)
5078 enum rs6000_abi abi = DEFAULT_ABI;
5080 /* Return a marker to indicate whether CR1 needs to set or clear the
5081 bit that V.4 uses to say fp args were passed in registers.
5082 Assume that we don't need the marker for software floating point,
5083 or compiler generated library calls. */
5084 if (mode == VOIDmode)
5087 && cum->nargs_prototype < 0
5088 && (cum->call_cookie & CALL_LIBCALL) == 0
5089 && (cum->prototype || TARGET_NO_PROTOTYPE))
5091 /* For the SPE, we need to crxor CR6 always. */
5093 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5094 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5095 return GEN_INT (cum->call_cookie
5096 | ((cum->fregno == FP_ARG_MIN_REG)
5097 ? CALL_V4_SET_FP_ARGS
5098 : CALL_V4_CLEAR_FP_ARGS));
5101 return GEN_INT (cum->call_cookie);
5104 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5105 if (TARGET_64BIT && ! cum->prototype)
5107 /* Vector parameters get passed in vector register
5108 and also in GPRs or memory, in absence of prototype. */
5111 align_words = (cum->words + 1) & ~1;
5113 if (align_words >= GP_ARG_NUM_REG)
5119 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5121 return gen_rtx_PARALLEL (mode,
5123 gen_rtx_EXPR_LIST (VOIDmode,
5125 gen_rtx_EXPR_LIST (VOIDmode,
5126 gen_rtx_REG (mode, cum->vregno),
5130 return gen_rtx_REG (mode, cum->vregno);
5131 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5133 if (named || abi == ABI_V4)
5137 /* Vector parameters to varargs functions under AIX or Darwin
5138 get passed in memory and possibly also in GPRs. */
5139 int align, align_words, n_words;
5140 enum machine_mode part_mode;
5142 /* Vector parameters must be 16-byte aligned. This places them at
5143 2 mod 4 in terms of words in 32-bit mode, since the parameter
5144 save area starts at offset 24 from the stack. In 64-bit mode,
5145 they just have to start on an even word, since the parameter
5146 save area is 16-byte aligned. */
5148 align = (2 - cum->words) & 3;
5150 align = cum->words & 1;
5151 align_words = cum->words + align;
5153 /* Out of registers? Memory, then. */
5154 if (align_words >= GP_ARG_NUM_REG)
5157 if (TARGET_32BIT && TARGET_POWERPC64)
5158 return rs6000_mixed_function_arg (mode, type, align_words);
5160 /* The vector value goes in GPRs. Only the part of the
5161 value in GPRs is reported here. */
5163 n_words = rs6000_arg_size (mode, type);
5164 if (align_words + n_words > GP_ARG_NUM_REG)
5165 /* Fortunately, there are only two possibilities, the value
5166 is either wholly in GPRs or half in GPRs and half not. */
5169 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5172 else if (TARGET_SPE_ABI && TARGET_SPE
5173 && (SPE_VECTOR_MODE (mode)
5174 || (TARGET_E500_DOUBLE && mode == DFmode)))
5175 return rs6000_spe_function_arg (cum, mode, type);
5176 else if (abi == ABI_V4)
5178 if (TARGET_HARD_FLOAT && TARGET_FPRS
5179 && (mode == SFmode || mode == DFmode))
5181 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5182 return gen_rtx_REG (mode, cum->fregno);
5188 int n_words = rs6000_arg_size (mode, type);
5189 int gregno = cum->sysv_gregno;
5191 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5192 (r7,r8) or (r9,r10). As does any other 2 word item such
5193 as complex int due to a historical mistake. */
5195 gregno += (1 - gregno) & 1;
5197 /* Multi-reg args are not split between registers and stack. */
5198 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5201 if (TARGET_32BIT && TARGET_POWERPC64)
5202 return rs6000_mixed_function_arg (mode, type,
5203 gregno - GP_ARG_MIN_REG);
5204 return gen_rtx_REG (mode, gregno);
5209 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5210 int align_words = cum->words + (cum->words & align);
5212 if (USE_FP_FOR_ARG_P (cum, mode, type))
5214 rtx rvec[GP_ARG_NUM_REG + 1];
5218 enum machine_mode fmode = mode;
5219 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5221 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5223 /* Currently, we only ever need one reg here because complex
5224 doubles are split. */
5225 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
5228 /* Long double split over regs and memory. */
5232 /* Do we also need to pass this arg in the parameter save
5235 && (cum->nargs_prototype <= 0
5236 || (DEFAULT_ABI == ABI_AIX
5238 && align_words >= GP_ARG_NUM_REG)));
5240 if (!needs_psave && mode == fmode)
5241 return gen_rtx_REG (fmode, cum->fregno);
5246 /* Describe the part that goes in gprs or the stack.
5247 This piece must come first, before the fprs. */
5248 if (align_words < GP_ARG_NUM_REG)
5250 unsigned long n_words = rs6000_arg_size (mode, type);
5252 if (align_words + n_words > GP_ARG_NUM_REG
5253 || (TARGET_32BIT && TARGET_POWERPC64))
5255 /* If this is partially on the stack, then we only
5256 include the portion actually in registers here. */
5257 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5260 if (align_words + n_words > GP_ARG_NUM_REG
5261 && (TARGET_32BIT && TARGET_POWERPC64))
5262 /* Not all of the arg fits in gprs. Say that it
5263 goes in memory too, using a magic NULL_RTX
5264 component. Also see comment in
5265 rs6000_mixed_function_arg for why the normal
5266 function_arg_partial_nregs scheme doesn't work
5268 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5272 r = gen_rtx_REG (rmode,
5273 GP_ARG_MIN_REG + align_words);
5274 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5275 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5277 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5281 /* The whole arg fits in gprs. */
5282 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5283 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5287 /* It's entirely in memory. */
5288 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5291 /* Describe where this piece goes in the fprs. */
5292 r = gen_rtx_REG (fmode, cum->fregno);
5293 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5295 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5297 else if (align_words < GP_ARG_NUM_REG)
5299 if (TARGET_32BIT && TARGET_POWERPC64)
5300 return rs6000_mixed_function_arg (mode, type, align_words);
5302 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5309 /* For an arg passed partly in registers and partly in memory, this is
5310 the number of registers used. For args passed entirely in registers
5311 or entirely in memory, zero. When an arg is described by a PARALLEL,
5312 perhaps using more than one register type, this function returns the
5313 number of registers used by the first element of the PARALLEL. */
5316 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5317 tree type, int named)
5324 if (DEFAULT_ABI == ABI_V4)
5327 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5328 && cum->nargs_prototype >= 0)
5331 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5332 parm_offset = TARGET_32BIT ? 2 : 0;
5333 align_words = cum->words + ((parm_offset - cum->words) & align);
5335 if (USE_FP_FOR_ARG_P (cum, mode, type)
5336 /* If we are passing this arg in gprs as well, then this function
5337 should return the number of gprs (or memory) partially passed,
5338 *not* the number of fprs. */
5340 && (cum->nargs_prototype <= 0
5341 || (DEFAULT_ABI == ABI_AIX
5343 && align_words >= GP_ARG_NUM_REG))))
5345 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5346 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
5347 else if (cum->nargs_prototype >= 0)
5351 if (align_words < GP_ARG_NUM_REG
5352 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5353 ret = GP_ARG_NUM_REG - align_words;
5355 if (ret != 0 && TARGET_DEBUG_ARG)
5356 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
5361 /* A C expression that indicates when an argument must be passed by
5362 reference. If nonzero for an argument, a copy of that argument is
5363 made in memory and a pointer to the argument is passed instead of
5364 the argument itself. The pointer is passed in whatever way is
5365 appropriate for passing a pointer to that type.
5367 Under V.4, aggregates and long double are passed by reference.
5369 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5370 reference unless the AltiVec vector extension ABI is in force.
5372 As an extension to all ABIs, variable sized types are passed by
5376 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5377 enum machine_mode mode ATTRIBUTE_UNUSED,
5378 tree type, bool named ATTRIBUTE_UNUSED)
5380 if ((DEFAULT_ABI == ABI_V4
5381 && ((type && AGGREGATE_TYPE_P (type))
5383 || (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5384 || (type && int_size_in_bytes (type) < 0))
5386 if (TARGET_DEBUG_ARG)
5387 fprintf (stderr, "function_arg_pass_by_reference\n");
5395 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5398 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5403 for (i = 0; i < nregs; i++)
5405 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5406 if (reload_completed)
5408 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5411 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5412 i * GET_MODE_SIZE(reg_mode));
5415 tem = replace_equiv_address (tem, XEXP (tem, 0));
5417 if (tem == NULL_RTX)
5420 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5424 /* Perform any needed actions needed for a function that is receiving a
5425 variable number of arguments.
5429 MODE and TYPE are the mode and type of the current parameter.
5431 PRETEND_SIZE is a variable that should be set to the amount of stack
5432 that must be pushed by the prolog to pretend that our caller pushed
5435 Normally, this macro will push all remaining incoming registers on the
5436 stack and set PRETEND_SIZE to the length of the registers pushed. */
5439 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5440 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5443 CUMULATIVE_ARGS next_cum;
5444 int reg_size = TARGET_32BIT ? 4 : 8;
5445 rtx save_area = NULL_RTX, mem;
5446 int first_reg_offset, set;
5448 /* Skip the last named argument. */
5450 function_arg_advance (&next_cum, mode, type, 1);
5452 if (DEFAULT_ABI == ABI_V4)
5455 save_area = plus_constant (virtual_stack_vars_rtx,
5456 - RS6000_VARARGS_SIZE);
5458 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5462 first_reg_offset = next_cum.words;
5463 save_area = virtual_incoming_args_rtx;
5465 if (targetm.calls.must_pass_in_stack (mode, type))
5466 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5469 set = get_varargs_alias_set ();
5470 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5472 mem = gen_rtx_MEM (BLKmode,
5473 plus_constant (save_area,
5474 first_reg_offset * reg_size)),
5475 set_mem_alias_set (mem, set);
5476 set_mem_align (mem, BITS_PER_WORD);
5478 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5479 GP_ARG_NUM_REG - first_reg_offset);
5482 /* Save FP registers if needed. */
5483 if (DEFAULT_ABI == ABI_V4
5484 && TARGET_HARD_FLOAT && TARGET_FPRS
5486 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5488 int fregno = next_cum.fregno;
5489 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5490 rtx lab = gen_label_rtx ();
5491 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5494 (gen_rtx_SET (VOIDmode,
5496 gen_rtx_IF_THEN_ELSE (VOIDmode,
5497 gen_rtx_NE (VOIDmode, cr1,
5499 gen_rtx_LABEL_REF (VOIDmode, lab),
5502 while (fregno <= FP_ARG_V4_MAX_REG)
5504 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5505 set_mem_alias_set (mem, set);
5506 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5507 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5516 /* Create the va_list data type. */
5519 rs6000_build_builtin_va_list (void)
5521 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5523 /* For AIX, prefer 'char *' because that's what the system
5524 header files like. */
5525 if (DEFAULT_ABI != ABI_V4)
5526 return build_pointer_type (char_type_node);
5528 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5529 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5531 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5532 unsigned_char_type_node);
5533 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5534 unsigned_char_type_node);
5535 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5537 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5538 short_unsigned_type_node);
5539 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5541 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5544 DECL_FIELD_CONTEXT (f_gpr) = record;
5545 DECL_FIELD_CONTEXT (f_fpr) = record;
5546 DECL_FIELD_CONTEXT (f_res) = record;
5547 DECL_FIELD_CONTEXT (f_ovf) = record;
5548 DECL_FIELD_CONTEXT (f_sav) = record;
5550 TREE_CHAIN (record) = type_decl;
5551 TYPE_NAME (record) = type_decl;
5552 TYPE_FIELDS (record) = f_gpr;
5553 TREE_CHAIN (f_gpr) = f_fpr;
5554 TREE_CHAIN (f_fpr) = f_res;
5555 TREE_CHAIN (f_res) = f_ovf;
5556 TREE_CHAIN (f_ovf) = f_sav;
5558 layout_type (record);
5560 /* The correct type is an array type of one element. */
5561 return build_array_type (record, build_index_type (size_zero_node));
5564 /* Implement va_start. */
5567 rs6000_va_start (tree valist, rtx nextarg)
5569 HOST_WIDE_INT words, n_gpr, n_fpr;
5570 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5571 tree gpr, fpr, ovf, sav, t;
5573 /* Only SVR4 needs something special. */
5574 if (DEFAULT_ABI != ABI_V4)
5576 std_expand_builtin_va_start (valist, nextarg);
5580 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5581 f_fpr = TREE_CHAIN (f_gpr);
5582 f_res = TREE_CHAIN (f_fpr);
5583 f_ovf = TREE_CHAIN (f_res);
5584 f_sav = TREE_CHAIN (f_ovf);
5586 valist = build_va_arg_indirect_ref (valist);
5587 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5588 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5589 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5590 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5592 /* Count number of gp and fp argument registers used. */
5593 words = current_function_args_info.words;
5594 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
5595 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
5597 if (TARGET_DEBUG_ARG)
5598 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5599 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5600 words, n_gpr, n_fpr);
5602 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5603 build_int_cst (NULL_TREE, n_gpr));
5604 TREE_SIDE_EFFECTS (t) = 1;
5605 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5607 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5608 build_int_cst (NULL_TREE, n_fpr));
5609 TREE_SIDE_EFFECTS (t) = 1;
5610 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5612 /* Find the overflow area. */
5613 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5615 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5616 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5617 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5618 TREE_SIDE_EFFECTS (t) = 1;
5619 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5621 /* Find the register save area. */
5622 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5623 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5624 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5625 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5626 TREE_SIDE_EFFECTS (t) = 1;
5627 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5630 /* Implement va_arg. */
5633 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5635 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5636 tree gpr, fpr, ovf, sav, reg, t, u;
5637 int size, rsize, n_reg, sav_ofs, sav_scale;
5638 tree lab_false, lab_over, addr;
5640 tree ptrtype = build_pointer_type (type);
5642 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5644 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5645 return build_va_arg_indirect_ref (t);
5648 if (DEFAULT_ABI != ABI_V4)
5650 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5652 tree elem_type = TREE_TYPE (type);
5653 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5654 int elem_size = GET_MODE_SIZE (elem_mode);
5656 if (elem_size < UNITS_PER_WORD)
5658 tree real_part, imag_part;
5659 tree post = NULL_TREE;
5661 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5663 /* Copy the value into a temporary, lest the formal temporary
5664 be reused out from under us. */
5665 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5666 append_to_statement_list (post, pre_p);
5668 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5671 return build (COMPLEX_EXPR, type, real_part, imag_part);
5675 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5678 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5679 f_fpr = TREE_CHAIN (f_gpr);
5680 f_res = TREE_CHAIN (f_fpr);
5681 f_ovf = TREE_CHAIN (f_res);
5682 f_sav = TREE_CHAIN (f_ovf);
5684 valist = build_va_arg_indirect_ref (valist);
5685 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5686 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5687 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5688 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5690 size = int_size_in_bytes (type);
5691 rsize = (size + 3) / 4;
5694 if (TARGET_HARD_FLOAT && TARGET_FPRS
5695 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5697 /* FP args go in FP registers, if present. */
5702 if (TYPE_MODE (type) == DFmode)
5707 /* Otherwise into GP registers. */
5716 /* Pull the value out of the saved registers.... */
5719 addr = create_tmp_var (ptr_type_node, "addr");
5720 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5722 /* AltiVec vectors never go in registers when -mabi=altivec. */
5723 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5727 lab_false = create_artificial_label ();
5728 lab_over = create_artificial_label ();
5730 /* Long long and SPE vectors are aligned in the registers.
5731 As are any other 2 gpr item such as complex int due to a
5732 historical mistake. */
5736 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5737 size_int (n_reg - 1));
5738 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5741 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5742 t = build2 (GE_EXPR, boolean_type_node, u, t);
5743 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5744 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5745 gimplify_and_add (t, pre_p);
5749 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5751 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5752 u = build1 (CONVERT_EXPR, integer_type_node, u);
5753 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5754 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5756 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5757 gimplify_and_add (t, pre_p);
5759 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5760 gimplify_and_add (t, pre_p);
5762 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5763 append_to_statement_list (t, pre_p);
5767 /* Ensure that we don't find any more args in regs.
5768 Alignment has taken care of the n_reg == 2 case. */
5769 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5770 gimplify_and_add (t, pre_p);
5774 /* ... otherwise out of the overflow area. */
5776 /* Care for on-stack alignment if needed. */
5780 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5781 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5782 build_int_cst (NULL_TREE, -align));
5784 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5786 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5787 gimplify_and_add (u, pre_p);
5789 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5790 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5791 gimplify_and_add (t, pre_p);
5795 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5796 append_to_statement_list (t, pre_p);
5799 addr = fold_convert (ptrtype, addr);
5800 return build_va_arg_indirect_ref (addr);
5805 #define def_builtin(MASK, NAME, TYPE, CODE) \
5807 if ((MASK) & target_flags) \
5808 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5812 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5814 static const struct builtin_description bdesc_3arg[] =
5816 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5817 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5818 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5819 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5820 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5821 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5822 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5823 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5824 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5825 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5826 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5827 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5828 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5829 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5830 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5831 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5832 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5833 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5834 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5835 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5836 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5837 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5838 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5841 /* DST operations: void foo (void *, const int, const char). */
5843 static const struct builtin_description bdesc_dst[] =
5845 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5846 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5847 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5848 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5851 /* Simple binary operations: VECc = foo (VECa, VECb). */
5853 static struct builtin_description bdesc_2arg[] =
5855 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5856 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5857 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5858 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5859 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5860 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5861 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5862 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5863 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5864 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5865 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5866 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5867 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5868 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5869 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5870 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5871 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5872 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5873 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5874 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5875 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5876 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5877 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5878 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5879 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5880 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5881 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5882 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5883 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5884 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5885 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5886 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5887 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5888 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5889 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5890 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5891 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5892 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5893 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5894 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5895 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5896 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5897 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5898 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5899 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5900 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5901 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5902 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5903 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5904 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5905 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5906 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5907 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5908 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5909 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5910 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5911 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5912 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5913 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5914 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5915 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5916 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5917 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5918 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5919 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5920 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5921 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5922 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5923 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5924 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5925 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5926 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5927 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5928 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5929 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5930 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5931 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5932 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5933 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5934 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5935 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5936 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5937 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5938 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5939 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5940 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5941 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5942 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5943 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5944 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5945 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5946 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5947 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5948 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5949 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5950 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5951 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5952 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5953 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5954 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5955 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5956 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5957 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5958 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5959 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5960 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5961 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5962 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5963 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5964 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5965 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5966 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5967 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5969 /* Place holder, leave as first spe builtin. */
5970 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5971 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5972 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5973 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5974 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5975 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5976 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5977 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5978 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5979 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5980 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5981 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5982 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5983 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5984 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5985 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5986 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5987 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5988 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5989 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5990 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5991 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5992 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5993 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5994 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5995 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5996 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5997 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5998 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5999 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6000 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6001 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6002 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6003 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6004 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6005 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6006 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6007 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6008 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6009 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6010 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6011 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6012 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6013 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6014 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6015 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6016 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6017 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6018 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6019 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6020 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6021 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6022 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6023 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6024 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6025 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6026 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6027 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6028 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6029 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6030 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6031 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6032 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6033 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6034 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6035 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6036 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6037 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6038 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6039 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6040 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6041 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6042 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6043 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6044 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6045 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6046 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6047 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6048 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6049 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6050 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6051 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6052 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6053 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6054 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6055 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6056 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6057 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6058 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6059 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6060 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6061 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6062 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6063 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6064 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6065 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6066 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6067 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6068 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6069 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6070 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6071 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6072 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6073 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6074 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6075 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6076 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6077 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6078 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6080 /* SPE binary operations expecting a 5-bit unsigned literal. */
6081 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6083 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6084 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6085 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6086 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6087 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6088 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6089 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6090 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6091 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6092 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6093 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6094 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6095 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6096 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6097 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6098 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6099 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6100 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6101 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6102 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6103 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6104 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6105 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6106 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6107 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6108 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6110 /* Place-holder. Leave as last binary SPE builtin. */
6111 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
6114 /* AltiVec predicates. */
6116 struct builtin_description_predicates
6118 const unsigned int mask;
6119 const enum insn_code icode;
6121 const char *const name;
6122 const enum rs6000_builtins code;
6125 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6127 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6128 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6129 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6130 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6131 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6132 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6133 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6134 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6136 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
6142 /* SPE predicates. */
6143 static struct builtin_description bdesc_spe_predicates[] =
6145 /* Place-holder. Leave as first. */
6146 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6147 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6148 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6149 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6150 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6151 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6152 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6153 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6154 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6155 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6156 /* Place-holder. Leave as last. */
6157 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6160 /* SPE evsel predicates. */
6161 static struct builtin_description bdesc_spe_evsel[] =
6163 /* Place-holder. Leave as first. */
6164 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6165 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6166 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6167 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6168 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6169 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6170 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6171 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6172 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6173 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6174 /* Place-holder. Leave as last. */
6175 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6178 /* ABS* operations. */
6180 static const struct builtin_description bdesc_abs[] =
6182 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6183 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6184 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6185 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6186 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6187 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6188 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6191 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6194 static struct builtin_description bdesc_1arg[] =
6196 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6197 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6198 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6199 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6200 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6201 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6202 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6203 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6204 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6205 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6206 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6207 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6208 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6209 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6210 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6211 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6212 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6214 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6215 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6216 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6217 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6218 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6219 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6220 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6221 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6222 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6223 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6224 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6225 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6226 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6227 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6228 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6229 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6230 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6231 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6232 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6233 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6234 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6235 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6236 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6237 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6238 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6239 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6240 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6241 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6242 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6243 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6245 /* Place-holder. Leave as last unary SPE builtin. */
6246 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
6250 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6253 tree arg0 = TREE_VALUE (arglist);
6254 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6255 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6256 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6258 if (icode == CODE_FOR_nothing)
6259 /* Builtin not supported on this processor. */
6262 /* If we got invalid arguments bail out before generating bad rtl. */
6263 if (arg0 == error_mark_node)
6266 if (icode == CODE_FOR_altivec_vspltisb
6267 || icode == CODE_FOR_altivec_vspltish
6268 || icode == CODE_FOR_altivec_vspltisw
6269 || icode == CODE_FOR_spe_evsplatfi
6270 || icode == CODE_FOR_spe_evsplati)
6272 /* Only allow 5-bit *signed* literals. */
6273 if (GET_CODE (op0) != CONST_INT
6274 || INTVAL (op0) > 0x1f
6275 || INTVAL (op0) < -0x1f)
6277 error ("argument 1 must be a 5-bit signed literal");
6283 || GET_MODE (target) != tmode
6284 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6285 target = gen_reg_rtx (tmode);
6287 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6288 op0 = copy_to_mode_reg (mode0, op0);
6290 pat = GEN_FCN (icode) (target, op0);
6299 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6301 rtx pat, scratch1, scratch2;
6302 tree arg0 = TREE_VALUE (arglist);
6303 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6304 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6305 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6307 /* If we have invalid arguments, bail out before generating bad rtl. */
6308 if (arg0 == error_mark_node)
6312 || GET_MODE (target) != tmode
6313 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6314 target = gen_reg_rtx (tmode);
6316 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6317 op0 = copy_to_mode_reg (mode0, op0);
6319 scratch1 = gen_reg_rtx (mode0);
6320 scratch2 = gen_reg_rtx (mode0);
6322 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6331 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6334 tree arg0 = TREE_VALUE (arglist);
6335 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6336 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6337 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6338 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6339 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6340 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6342 if (icode == CODE_FOR_nothing)
6343 /* Builtin not supported on this processor. */
6346 /* If we got invalid arguments bail out before generating bad rtl. */
6347 if (arg0 == error_mark_node || arg1 == error_mark_node)
6350 if (icode == CODE_FOR_altivec_vcfux
6351 || icode == CODE_FOR_altivec_vcfsx
6352 || icode == CODE_FOR_altivec_vctsxs
6353 || icode == CODE_FOR_altivec_vctuxs
6354 || icode == CODE_FOR_altivec_vspltb
6355 || icode == CODE_FOR_altivec_vsplth
6356 || icode == CODE_FOR_altivec_vspltw
6357 || icode == CODE_FOR_spe_evaddiw
6358 || icode == CODE_FOR_spe_evldd
6359 || icode == CODE_FOR_spe_evldh
6360 || icode == CODE_FOR_spe_evldw
6361 || icode == CODE_FOR_spe_evlhhesplat
6362 || icode == CODE_FOR_spe_evlhhossplat
6363 || icode == CODE_FOR_spe_evlhhousplat
6364 || icode == CODE_FOR_spe_evlwhe
6365 || icode == CODE_FOR_spe_evlwhos
6366 || icode == CODE_FOR_spe_evlwhou
6367 || icode == CODE_FOR_spe_evlwhsplat
6368 || icode == CODE_FOR_spe_evlwwsplat
6369 || icode == CODE_FOR_spe_evrlwi
6370 || icode == CODE_FOR_spe_evslwi
6371 || icode == CODE_FOR_spe_evsrwis
6372 || icode == CODE_FOR_spe_evsubifw
6373 || icode == CODE_FOR_spe_evsrwiu)
6375 /* Only allow 5-bit unsigned literals. */
6377 if (TREE_CODE (arg1) != INTEGER_CST
6378 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6380 error ("argument 2 must be a 5-bit unsigned literal");
6386 || GET_MODE (target) != tmode
6387 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6388 target = gen_reg_rtx (tmode);
6390 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6391 op0 = copy_to_mode_reg (mode0, op0);
6392 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6393 op1 = copy_to_mode_reg (mode1, op1);
6395 pat = GEN_FCN (icode) (target, op0, op1);
6404 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6405 tree arglist, rtx target)
6408 tree cr6_form = TREE_VALUE (arglist);
6409 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6410 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6411 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6412 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6413 enum machine_mode tmode = SImode;
6414 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6415 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6418 if (TREE_CODE (cr6_form) != INTEGER_CST)
6420 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6424 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6429 /* If we have invalid arguments, bail out before generating bad rtl. */
6430 if (arg0 == error_mark_node || arg1 == error_mark_node)
6434 || GET_MODE (target) != tmode
6435 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6436 target = gen_reg_rtx (tmode);
6438 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6439 op0 = copy_to_mode_reg (mode0, op0);
6440 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6441 op1 = copy_to_mode_reg (mode1, op1);
6443 scratch = gen_reg_rtx (mode0);
6445 pat = GEN_FCN (icode) (scratch, op0, op1,
6446 gen_rtx_SYMBOL_REF (Pmode, opcode));
6451 /* The vec_any* and vec_all* predicates use the same opcodes for two
6452 different operations, but the bits in CR6 will be different
6453 depending on what information we want. So we have to play tricks
6454 with CR6 to get the right bits out.
6456 If you think this is disgusting, look at the specs for the
6457 AltiVec predicates. */
6459 switch (cr6_form_int)
6462 emit_insn (gen_cr6_test_for_zero (target));
6465 emit_insn (gen_cr6_test_for_zero_reverse (target));
6468 emit_insn (gen_cr6_test_for_lt (target));
6471 emit_insn (gen_cr6_test_for_lt_reverse (target));
6474 error ("argument 1 of __builtin_altivec_predicate is out of range");
6482 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6485 tree arg0 = TREE_VALUE (arglist);
6486 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6487 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6488 enum machine_mode mode0 = Pmode;
6489 enum machine_mode mode1 = Pmode;
6490 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6491 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6493 if (icode == CODE_FOR_nothing)
6494 /* Builtin not supported on this processor. */
6497 /* If we got invalid arguments bail out before generating bad rtl. */
6498 if (arg0 == error_mark_node || arg1 == error_mark_node)
6502 || GET_MODE (target) != tmode
6503 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6504 target = gen_reg_rtx (tmode);
6506 op1 = copy_to_mode_reg (mode1, op1);
6508 if (op0 == const0_rtx)
6510 addr = gen_rtx_MEM (tmode, op1);
6514 op0 = copy_to_mode_reg (mode0, op0);
6515 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6518 pat = GEN_FCN (icode) (target, addr);
6528 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6530 tree arg0 = TREE_VALUE (arglist);
6531 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6532 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6533 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6534 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6535 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6537 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6538 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6539 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6541 /* Invalid arguments. Bail before doing anything stoopid! */
6542 if (arg0 == error_mark_node
6543 || arg1 == error_mark_node
6544 || arg2 == error_mark_node)
6547 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6548 op0 = copy_to_mode_reg (mode2, op0);
6549 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6550 op1 = copy_to_mode_reg (mode0, op1);
6551 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6552 op2 = copy_to_mode_reg (mode1, op2);
6554 pat = GEN_FCN (icode) (op1, op2, op0);
6561 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6563 tree arg0 = TREE_VALUE (arglist);
6564 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6565 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6566 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6567 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6568 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6570 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6571 enum machine_mode mode1 = Pmode;
6572 enum machine_mode mode2 = Pmode;
6574 /* Invalid arguments. Bail before doing anything stoopid! */
6575 if (arg0 == error_mark_node
6576 || arg1 == error_mark_node
6577 || arg2 == error_mark_node)
6580 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6581 op0 = copy_to_mode_reg (tmode, op0);
6583 op2 = copy_to_mode_reg (mode2, op2);
6585 if (op1 == const0_rtx)
6587 addr = gen_rtx_MEM (tmode, op2);
6591 op1 = copy_to_mode_reg (mode1, op1);
6592 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6595 pat = GEN_FCN (icode) (addr, op0);
6602 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6605 tree arg0 = TREE_VALUE (arglist);
6606 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6607 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6608 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6609 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6610 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6611 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6612 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6613 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6614 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6616 if (icode == CODE_FOR_nothing)
6617 /* Builtin not supported on this processor. */
6620 /* If we got invalid arguments bail out before generating bad rtl. */
6621 if (arg0 == error_mark_node
6622 || arg1 == error_mark_node
6623 || arg2 == error_mark_node)
6626 if (icode == CODE_FOR_altivec_vsldoi_4sf
6627 || icode == CODE_FOR_altivec_vsldoi_4si
6628 || icode == CODE_FOR_altivec_vsldoi_8hi
6629 || icode == CODE_FOR_altivec_vsldoi_16qi)
6631 /* Only allow 4-bit unsigned literals. */
6633 if (TREE_CODE (arg2) != INTEGER_CST
6634 || TREE_INT_CST_LOW (arg2) & ~0xf)
6636 error ("argument 3 must be a 4-bit unsigned literal");
6642 || GET_MODE (target) != tmode
6643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6644 target = gen_reg_rtx (tmode);
6646 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6647 op0 = copy_to_mode_reg (mode0, op0);
6648 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6649 op1 = copy_to_mode_reg (mode1, op1);
6650 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6651 op2 = copy_to_mode_reg (mode2, op2);
6653 pat = GEN_FCN (icode) (target, op0, op1, op2);
6661 /* Expand the lvx builtins. */
6663 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6665 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6666 tree arglist = TREE_OPERAND (exp, 1);
6667 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6669 enum machine_mode tmode, mode0;
6671 enum insn_code icode;
6675 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6676 icode = CODE_FOR_altivec_lvx_16qi;
6678 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6679 icode = CODE_FOR_altivec_lvx_8hi;
6681 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6682 icode = CODE_FOR_altivec_lvx_4si;
6684 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6685 icode = CODE_FOR_altivec_lvx_4sf;
6694 arg0 = TREE_VALUE (arglist);
6695 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6696 tmode = insn_data[icode].operand[0].mode;
6697 mode0 = insn_data[icode].operand[1].mode;
6700 || GET_MODE (target) != tmode
6701 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6702 target = gen_reg_rtx (tmode);
6704 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6705 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6707 pat = GEN_FCN (icode) (target, op0);
6714 /* Expand the stvx builtins. */
6716 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6719 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6720 tree arglist = TREE_OPERAND (exp, 1);
6721 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6723 enum machine_mode mode0, mode1;
6725 enum insn_code icode;
6729 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6730 icode = CODE_FOR_altivec_stvx_16qi;
6732 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6733 icode = CODE_FOR_altivec_stvx_8hi;
6735 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6736 icode = CODE_FOR_altivec_stvx_4si;
6738 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6739 icode = CODE_FOR_altivec_stvx_4sf;
6746 arg0 = TREE_VALUE (arglist);
6747 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6748 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6749 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6750 mode0 = insn_data[icode].operand[0].mode;
6751 mode1 = insn_data[icode].operand[1].mode;
6753 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6754 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6755 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6756 op1 = copy_to_mode_reg (mode1, op1);
6758 pat = GEN_FCN (icode) (op0, op1);
6766 /* Expand the dst builtins. */
6768 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6771 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6772 tree arglist = TREE_OPERAND (exp, 1);
6773 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6774 tree arg0, arg1, arg2;
6775 enum machine_mode mode0, mode1, mode2;
6776 rtx pat, op0, op1, op2;
6777 struct builtin_description *d;
6782 /* Handle DST variants. */
6783 d = (struct builtin_description *) bdesc_dst;
6784 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6785 if (d->code == fcode)
6787 arg0 = TREE_VALUE (arglist);
6788 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6789 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6790 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6791 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6792 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6793 mode0 = insn_data[d->icode].operand[0].mode;
6794 mode1 = insn_data[d->icode].operand[1].mode;
6795 mode2 = insn_data[d->icode].operand[2].mode;
6797 /* Invalid arguments, bail out before generating bad rtl. */
6798 if (arg0 == error_mark_node
6799 || arg1 == error_mark_node
6800 || arg2 == error_mark_node)
6805 if (TREE_CODE (arg2) != INTEGER_CST
6806 || TREE_INT_CST_LOW (arg2) & ~0x3)
6808 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
6812 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6813 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6814 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6815 op1 = copy_to_mode_reg (mode1, op1);
6817 pat = GEN_FCN (d->icode) (op0, op1, op2);
6827 /* Expand the builtin in EXP and store the result in TARGET. Store
6828 true in *EXPANDEDP if we found a builtin to expand. */
6830 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6832 struct builtin_description *d;
6833 struct builtin_description_predicates *dp;
6835 enum insn_code icode;
6836 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6837 tree arglist = TREE_OPERAND (exp, 1);
6840 enum machine_mode tmode, mode0;
6841 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6843 target = altivec_expand_ld_builtin (exp, target, expandedp);
6847 target = altivec_expand_st_builtin (exp, target, expandedp);
6851 target = altivec_expand_dst_builtin (exp, target, expandedp);
6859 case ALTIVEC_BUILTIN_STVX:
6860 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6861 case ALTIVEC_BUILTIN_STVEBX:
6862 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6863 case ALTIVEC_BUILTIN_STVEHX:
6864 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6865 case ALTIVEC_BUILTIN_STVEWX:
6866 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6867 case ALTIVEC_BUILTIN_STVXL:
6868 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6870 case ALTIVEC_BUILTIN_MFVSCR:
6871 icode = CODE_FOR_altivec_mfvscr;
6872 tmode = insn_data[icode].operand[0].mode;
6875 || GET_MODE (target) != tmode
6876 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6877 target = gen_reg_rtx (tmode);
6879 pat = GEN_FCN (icode) (target);
6885 case ALTIVEC_BUILTIN_MTVSCR:
6886 icode = CODE_FOR_altivec_mtvscr;
6887 arg0 = TREE_VALUE (arglist);
6888 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6889 mode0 = insn_data[icode].operand[0].mode;
6891 /* If we got invalid arguments bail out before generating bad rtl. */
6892 if (arg0 == error_mark_node)
6895 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6896 op0 = copy_to_mode_reg (mode0, op0);
6898 pat = GEN_FCN (icode) (op0);
6903 case ALTIVEC_BUILTIN_DSSALL:
6904 emit_insn (gen_altivec_dssall ());
6907 case ALTIVEC_BUILTIN_DSS:
6908 icode = CODE_FOR_altivec_dss;
6909 arg0 = TREE_VALUE (arglist);
6911 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6912 mode0 = insn_data[icode].operand[0].mode;
6914 /* If we got invalid arguments bail out before generating bad rtl. */
6915 if (arg0 == error_mark_node)
6918 if (TREE_CODE (arg0) != INTEGER_CST
6919 || TREE_INT_CST_LOW (arg0) & ~0x3)
6921 error ("argument to dss must be a 2-bit unsigned literal");
6925 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6926 op0 = copy_to_mode_reg (mode0, op0);
6928 emit_insn (gen_altivec_dss (op0));
6931 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6932 arg0 = TREE_VALUE (arglist);
6933 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
6934 || TREE_CODE (arg0) == ARRAY_REF)
6935 arg0 = TREE_OPERAND (arg0, 0);
6936 error ("invalid parameter combination for `%s' AltiVec intrinsic",
6937 TREE_STRING_POINTER (arg0));
6942 /* Expand abs* operations. */
6943 d = (struct builtin_description *) bdesc_abs;
6944 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6945 if (d->code == fcode)
6946 return altivec_expand_abs_builtin (d->icode, arglist, target);
6948 /* Expand the AltiVec predicates. */
6949 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6950 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6951 if (dp->code == fcode)
6952 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6955 /* LV* are funky. We initialized them differently. */
6958 case ALTIVEC_BUILTIN_LVSL:
6959 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6961 case ALTIVEC_BUILTIN_LVSR:
6962 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6964 case ALTIVEC_BUILTIN_LVEBX:
6965 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6967 case ALTIVEC_BUILTIN_LVEHX:
6968 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6970 case ALTIVEC_BUILTIN_LVEWX:
6971 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6973 case ALTIVEC_BUILTIN_LVXL:
6974 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6976 case ALTIVEC_BUILTIN_LVX:
6977 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6988 /* Binops that need to be initialized manually, but can be expanded
6989 automagically by rs6000_expand_binop_builtin. */
6990 static struct builtin_description bdesc_2arg_spe[] =
6992 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6993 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6994 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6995 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6996 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6997 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6998 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6999 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7000 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7001 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7002 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7003 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7004 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7005 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7006 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7007 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7008 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7009 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7010 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7011 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7012 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7013 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7016 /* Expand the builtin in EXP and store the result in TARGET. Store
7017 true in *EXPANDEDP if we found a builtin to expand.
7019 This expands the SPE builtins that are not simple unary and binary
7022 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7024 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7025 tree arglist = TREE_OPERAND (exp, 1);
7027 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7028 enum insn_code icode;
7029 enum machine_mode tmode, mode0;
7031 struct builtin_description *d;
7036 /* Syntax check for a 5-bit unsigned immediate. */
7039 case SPE_BUILTIN_EVSTDD:
7040 case SPE_BUILTIN_EVSTDH:
7041 case SPE_BUILTIN_EVSTDW:
7042 case SPE_BUILTIN_EVSTWHE:
7043 case SPE_BUILTIN_EVSTWHO:
7044 case SPE_BUILTIN_EVSTWWE:
7045 case SPE_BUILTIN_EVSTWWO:
7046 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7047 if (TREE_CODE (arg1) != INTEGER_CST
7048 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7050 error ("argument 2 must be a 5-bit unsigned literal");
7058 /* The evsplat*i instructions are not quite generic. */
7061 case SPE_BUILTIN_EVSPLATFI:
7062 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7064 case SPE_BUILTIN_EVSPLATI:
7065 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7071 d = (struct builtin_description *) bdesc_2arg_spe;
7072 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7073 if (d->code == fcode)
7074 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7076 d = (struct builtin_description *) bdesc_spe_predicates;
7077 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7078 if (d->code == fcode)
7079 return spe_expand_predicate_builtin (d->icode, arglist, target);
7081 d = (struct builtin_description *) bdesc_spe_evsel;
7082 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7083 if (d->code == fcode)
7084 return spe_expand_evsel_builtin (d->icode, arglist, target);
7088 case SPE_BUILTIN_EVSTDDX:
7089 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7090 case SPE_BUILTIN_EVSTDHX:
7091 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7092 case SPE_BUILTIN_EVSTDWX:
7093 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7094 case SPE_BUILTIN_EVSTWHEX:
7095 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7096 case SPE_BUILTIN_EVSTWHOX:
7097 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7098 case SPE_BUILTIN_EVSTWWEX:
7099 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7100 case SPE_BUILTIN_EVSTWWOX:
7101 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7102 case SPE_BUILTIN_EVSTDD:
7103 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7104 case SPE_BUILTIN_EVSTDH:
7105 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7106 case SPE_BUILTIN_EVSTDW:
7107 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7108 case SPE_BUILTIN_EVSTWHE:
7109 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7110 case SPE_BUILTIN_EVSTWHO:
7111 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7112 case SPE_BUILTIN_EVSTWWE:
7113 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7114 case SPE_BUILTIN_EVSTWWO:
7115 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7116 case SPE_BUILTIN_MFSPEFSCR:
7117 icode = CODE_FOR_spe_mfspefscr;
7118 tmode = insn_data[icode].operand[0].mode;
7121 || GET_MODE (target) != tmode
7122 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7123 target = gen_reg_rtx (tmode);
7125 pat = GEN_FCN (icode) (target);
7130 case SPE_BUILTIN_MTSPEFSCR:
7131 icode = CODE_FOR_spe_mtspefscr;
7132 arg0 = TREE_VALUE (arglist);
7133 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7134 mode0 = insn_data[icode].operand[0].mode;
7136 if (arg0 == error_mark_node)
7139 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7140 op0 = copy_to_mode_reg (mode0, op0);
7142 pat = GEN_FCN (icode) (op0);
7155 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7157 rtx pat, scratch, tmp;
7158 tree form = TREE_VALUE (arglist);
7159 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7160 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7161 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7162 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7163 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7164 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7168 if (TREE_CODE (form) != INTEGER_CST)
7170 error ("argument 1 of __builtin_spe_predicate must be a constant");
7174 form_int = TREE_INT_CST_LOW (form);
7179 if (arg0 == error_mark_node || arg1 == error_mark_node)
7183 || GET_MODE (target) != SImode
7184 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7185 target = gen_reg_rtx (SImode);
7187 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7188 op0 = copy_to_mode_reg (mode0, op0);
7189 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7190 op1 = copy_to_mode_reg (mode1, op1);
7192 scratch = gen_reg_rtx (CCmode);
7194 pat = GEN_FCN (icode) (scratch, op0, op1);
7199 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7200 _lower_. We use one compare, but look in different bits of the
7201 CR for each variant.
7203 There are 2 elements in each SPE simd type (upper/lower). The CR
7204 bits are set as follows:
7206 BIT0 | BIT 1 | BIT 2 | BIT 3
7207 U | L | (U | L) | (U & L)
7209 So, for an "all" relationship, BIT 3 would be set.
7210 For an "any" relationship, BIT 2 would be set. Etc.
7212 Following traditional nomenclature, these bits map to:
7214 BIT0 | BIT 1 | BIT 2 | BIT 3
7217 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7222 /* All variant. OV bit. */
7224 /* We need to get to the OV bit, which is the ORDERED bit. We
7225 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7226 that's ugly and will trigger a validate_condition_mode abort.
7227 So let's just use another pattern. */
7228 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7230 /* Any variant. EQ bit. */
7234 /* Upper variant. LT bit. */
7238 /* Lower variant. GT bit. */
7243 error ("argument 1 of __builtin_spe_predicate is out of range");
7247 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7248 emit_move_insn (target, tmp);
7253 /* The evsel builtins look like this:
7255 e = __builtin_spe_evsel_OP (a, b, c, d);
7259 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7260 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7264 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7267 tree arg0 = TREE_VALUE (arglist);
7268 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7269 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7270 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7271 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7272 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7273 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7274 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7275 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7276 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7281 if (arg0 == error_mark_node || arg1 == error_mark_node
7282 || arg2 == error_mark_node || arg3 == error_mark_node)
7286 || GET_MODE (target) != mode0
7287 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7288 target = gen_reg_rtx (mode0);
7290 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7291 op0 = copy_to_mode_reg (mode0, op0);
7292 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7293 op1 = copy_to_mode_reg (mode0, op1);
7294 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7295 op2 = copy_to_mode_reg (mode0, op2);
7296 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7297 op3 = copy_to_mode_reg (mode0, op3);
7299 /* Generate the compare. */
7300 scratch = gen_reg_rtx (CCmode);
7301 pat = GEN_FCN (icode) (scratch, op0, op1);
7306 if (mode0 == V2SImode)
7307 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7309 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7314 /* Expand an expression EXP that calls a built-in function,
7315 with result going to TARGET if that's convenient
7316 (and in mode MODE if that's convenient).
7317 SUBTARGET may be used as the target for computing one of EXP's operands.
7318 IGNORE is nonzero if the value is to be ignored. */
7321 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7322 enum machine_mode mode ATTRIBUTE_UNUSED,
7323 int ignore ATTRIBUTE_UNUSED)
7325 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7326 tree arglist = TREE_OPERAND (exp, 1);
7327 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7328 struct builtin_description *d;
7333 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7334 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7336 int icode = (int) CODE_FOR_altivec_lvsr;
7337 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7338 enum machine_mode mode = insn_data[icode].operand[1].mode;
7342 if (!TARGET_ALTIVEC)
7345 arg = TREE_VALUE (arglist);
7346 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7348 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7349 addr = memory_address (mode, op);
7350 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7354 /* For the load case need to negate the address. */
7355 op = gen_reg_rtx (GET_MODE (addr));
7356 emit_insn (gen_rtx_SET (VOIDmode, op,
7357 gen_rtx_NEG (GET_MODE (addr), addr)));
7359 op = gen_rtx_MEM (mode, op);
7362 || GET_MODE (target) != tmode
7363 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7364 target = gen_reg_rtx (tmode);
7366 /*pat = gen_altivec_lvsr (target, op);*/
7367 pat = GEN_FCN (icode) (target, op);
7377 ret = altivec_expand_builtin (exp, target, &success);
7384 ret = spe_expand_builtin (exp, target, &success);
7390 if (TARGET_ALTIVEC || TARGET_SPE)
7392 /* Handle simple unary operations. */
7393 d = (struct builtin_description *) bdesc_1arg;
7394 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7395 if (d->code == fcode)
7396 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7398 /* Handle simple binary operations. */
7399 d = (struct builtin_description *) bdesc_2arg;
7400 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7401 if (d->code == fcode)
7402 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7404 /* Handle simple ternary operations. */
7405 d = (struct builtin_description *) bdesc_3arg;
7406 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7407 if (d->code == fcode)
7408 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7416 build_opaque_vector_type (tree node, int nunits)
7418 node = copy_node (node);
7419 TYPE_MAIN_VARIANT (node) = node;
7420 return build_vector_type (node, nunits);
7424 rs6000_init_builtins (void)
7426 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7427 V2SF_type_node = build_vector_type (float_type_node, 2);
7428 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7429 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7430 V4SF_type_node = build_vector_type (float_type_node, 4);
7431 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7432 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7434 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7435 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7436 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7438 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7439 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7440 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7442 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7443 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7444 'vector unsigned short'. */
7446 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7447 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7448 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7449 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7451 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7452 get_identifier ("__bool char"),
7453 bool_char_type_node));
7454 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7455 get_identifier ("__bool short"),
7456 bool_short_type_node));
7457 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7458 get_identifier ("__bool int"),
7459 bool_int_type_node));
7460 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7461 get_identifier ("__pixel"),
7464 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7465 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7466 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7467 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7469 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7470 get_identifier ("__vector unsigned char"),
7471 unsigned_V16QI_type_node));
7472 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7473 get_identifier ("__vector signed char"),
7475 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7476 get_identifier ("__vector __bool char"),
7477 bool_V16QI_type_node));
7479 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7480 get_identifier ("__vector unsigned short"),
7481 unsigned_V8HI_type_node));
7482 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7483 get_identifier ("__vector signed short"),
7485 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7486 get_identifier ("__vector __bool short"),
7487 bool_V8HI_type_node));
7489 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7490 get_identifier ("__vector unsigned int"),
7491 unsigned_V4SI_type_node));
7492 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7493 get_identifier ("__vector signed int"),
7495 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7496 get_identifier ("__vector __bool int"),
7497 bool_V4SI_type_node));
7499 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7500 get_identifier ("__vector float"),
7502 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7503 get_identifier ("__vector __pixel"),
7504 pixel_V8HI_type_node));
7507 spe_init_builtins ();
7509 altivec_init_builtins ();
7510 if (TARGET_ALTIVEC || TARGET_SPE)
7511 rs6000_common_init_builtins ();
7514 /* Search through a set of builtins and enable the mask bits.
7515 DESC is an array of builtins.
7516 SIZE is the total number of builtins.
7517 START is the builtin enum at which to start.
7518 END is the builtin enum at which to end. */
7520 enable_mask_for_builtins (struct builtin_description *desc, int size,
7521 enum rs6000_builtins start,
7522 enum rs6000_builtins end)
7526 for (i = 0; i < size; ++i)
7527 if (desc[i].code == start)
7533 for (; i < size; ++i)
7535 /* Flip all the bits on. */
7536 desc[i].mask = target_flags;
7537 if (desc[i].code == end)
7543 spe_init_builtins (void)
7545 tree endlink = void_list_node;
7546 tree puint_type_node = build_pointer_type (unsigned_type_node);
7547 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7548 struct builtin_description *d;
7551 tree v2si_ftype_4_v2si
7552 = build_function_type
7553 (opaque_V2SI_type_node,
7554 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7555 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7556 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7557 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7560 tree v2sf_ftype_4_v2sf
7561 = build_function_type
7562 (opaque_V2SF_type_node,
7563 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7564 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7565 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7566 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7569 tree int_ftype_int_v2si_v2si
7570 = build_function_type
7572 tree_cons (NULL_TREE, integer_type_node,
7573 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7574 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7577 tree int_ftype_int_v2sf_v2sf
7578 = build_function_type
7580 tree_cons (NULL_TREE, integer_type_node,
7581 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7582 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7585 tree void_ftype_v2si_puint_int
7586 = build_function_type (void_type_node,
7587 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7588 tree_cons (NULL_TREE, puint_type_node,
7589 tree_cons (NULL_TREE,
7593 tree void_ftype_v2si_puint_char
7594 = build_function_type (void_type_node,
7595 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7596 tree_cons (NULL_TREE, puint_type_node,
7597 tree_cons (NULL_TREE,
7601 tree void_ftype_v2si_pv2si_int
7602 = build_function_type (void_type_node,
7603 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7604 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7605 tree_cons (NULL_TREE,
7609 tree void_ftype_v2si_pv2si_char
7610 = build_function_type (void_type_node,
7611 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7612 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7613 tree_cons (NULL_TREE,
7618 = build_function_type (void_type_node,
7619 tree_cons (NULL_TREE, integer_type_node, endlink));
7622 = build_function_type (integer_type_node, endlink);
7624 tree v2si_ftype_pv2si_int
7625 = build_function_type (opaque_V2SI_type_node,
7626 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7627 tree_cons (NULL_TREE, integer_type_node,
7630 tree v2si_ftype_puint_int
7631 = build_function_type (opaque_V2SI_type_node,
7632 tree_cons (NULL_TREE, puint_type_node,
7633 tree_cons (NULL_TREE, integer_type_node,
7636 tree v2si_ftype_pushort_int
7637 = build_function_type (opaque_V2SI_type_node,
7638 tree_cons (NULL_TREE, pushort_type_node,
7639 tree_cons (NULL_TREE, integer_type_node,
7642 tree v2si_ftype_signed_char
7643 = build_function_type (opaque_V2SI_type_node,
7644 tree_cons (NULL_TREE, signed_char_type_node,
7647 /* The initialization of the simple binary and unary builtins is
7648 done in rs6000_common_init_builtins, but we have to enable the
7649 mask bits here manually because we have run out of `target_flags'
7650 bits. We really need to redesign this mask business. */
7652 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7653 ARRAY_SIZE (bdesc_2arg),
7656 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7657 ARRAY_SIZE (bdesc_1arg),
7659 SPE_BUILTIN_EVSUBFUSIAAW);
7660 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7661 ARRAY_SIZE (bdesc_spe_predicates),
7662 SPE_BUILTIN_EVCMPEQ,
7663 SPE_BUILTIN_EVFSTSTLT);
7664 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7665 ARRAY_SIZE (bdesc_spe_evsel),
7666 SPE_BUILTIN_EVSEL_CMPGTS,
7667 SPE_BUILTIN_EVSEL_FSTSTEQ);
7669 (*lang_hooks.decls.pushdecl)
7670 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7671 opaque_V2SI_type_node));
7673 /* Initialize irregular SPE builtins. */
7675 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7676 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7677 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7678 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7679 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7680 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7681 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7682 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7683 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7684 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7685 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7686 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7687 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7688 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7689 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7690 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7691 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7692 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7695 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7696 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7697 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7698 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7699 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7700 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7701 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7702 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7703 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7704 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7705 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7706 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7707 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7708 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7709 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7710 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7711 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7712 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7713 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7714 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7715 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7716 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7719 d = (struct builtin_description *) bdesc_spe_predicates;
7720 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7724 switch (insn_data[d->icode].operand[1].mode)
7727 type = int_ftype_int_v2si_v2si;
7730 type = int_ftype_int_v2sf_v2sf;
7736 def_builtin (d->mask, d->name, type, d->code);
7739 /* Evsel predicates. */
7740 d = (struct builtin_description *) bdesc_spe_evsel;
7741 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7745 switch (insn_data[d->icode].operand[1].mode)
7748 type = v2si_ftype_4_v2si;
7751 type = v2sf_ftype_4_v2sf;
7757 def_builtin (d->mask, d->name, type, d->code);
7762 altivec_init_builtins (void)
7764 struct builtin_description *d;
7765 struct builtin_description_predicates *dp;
7767 tree pfloat_type_node = build_pointer_type (float_type_node);
7768 tree pint_type_node = build_pointer_type (integer_type_node);
7769 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7770 tree pchar_type_node = build_pointer_type (char_type_node);
7772 tree pvoid_type_node = build_pointer_type (void_type_node);
7774 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7775 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7776 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7777 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7779 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7781 tree int_ftype_int_v4si_v4si
7782 = build_function_type_list (integer_type_node,
7783 integer_type_node, V4SI_type_node,
7784 V4SI_type_node, NULL_TREE);
7785 tree v4sf_ftype_pcfloat
7786 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7787 tree void_ftype_pfloat_v4sf
7788 = build_function_type_list (void_type_node,
7789 pfloat_type_node, V4SF_type_node, NULL_TREE);
7790 tree v4si_ftype_pcint
7791 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7792 tree void_ftype_pint_v4si
7793 = build_function_type_list (void_type_node,
7794 pint_type_node, V4SI_type_node, NULL_TREE);
7795 tree v8hi_ftype_pcshort
7796 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7797 tree void_ftype_pshort_v8hi
7798 = build_function_type_list (void_type_node,
7799 pshort_type_node, V8HI_type_node, NULL_TREE);
7800 tree v16qi_ftype_pcchar
7801 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7802 tree void_ftype_pchar_v16qi
7803 = build_function_type_list (void_type_node,
7804 pchar_type_node, V16QI_type_node, NULL_TREE);
7805 tree void_ftype_v4si
7806 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7807 tree v8hi_ftype_void
7808 = build_function_type (V8HI_type_node, void_list_node);
7809 tree void_ftype_void
7810 = build_function_type (void_type_node, void_list_node);
7812 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7814 tree v16qi_ftype_long_pcvoid
7815 = build_function_type_list (V16QI_type_node,
7816 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7817 tree v8hi_ftype_long_pcvoid
7818 = build_function_type_list (V8HI_type_node,
7819 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7820 tree v4si_ftype_long_pcvoid
7821 = build_function_type_list (V4SI_type_node,
7822 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7824 tree void_ftype_v4si_long_pvoid
7825 = build_function_type_list (void_type_node,
7826 V4SI_type_node, long_integer_type_node,
7827 pvoid_type_node, NULL_TREE);
7828 tree void_ftype_v16qi_long_pvoid
7829 = build_function_type_list (void_type_node,
7830 V16QI_type_node, long_integer_type_node,
7831 pvoid_type_node, NULL_TREE);
7832 tree void_ftype_v8hi_long_pvoid
7833 = build_function_type_list (void_type_node,
7834 V8HI_type_node, long_integer_type_node,
7835 pvoid_type_node, NULL_TREE);
7836 tree int_ftype_int_v8hi_v8hi
7837 = build_function_type_list (integer_type_node,
7838 integer_type_node, V8HI_type_node,
7839 V8HI_type_node, NULL_TREE);
7840 tree int_ftype_int_v16qi_v16qi
7841 = build_function_type_list (integer_type_node,
7842 integer_type_node, V16QI_type_node,
7843 V16QI_type_node, NULL_TREE);
7844 tree int_ftype_int_v4sf_v4sf
7845 = build_function_type_list (integer_type_node,
7846 integer_type_node, V4SF_type_node,
7847 V4SF_type_node, NULL_TREE);
7848 tree v4si_ftype_v4si
7849 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7850 tree v8hi_ftype_v8hi
7851 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7852 tree v16qi_ftype_v16qi
7853 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7854 tree v4sf_ftype_v4sf
7855 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7856 tree void_ftype_pcvoid_int_int
7857 = build_function_type_list (void_type_node,
7858 pcvoid_type_node, integer_type_node,
7859 integer_type_node, NULL_TREE);
7860 tree int_ftype_pcchar
7861 = build_function_type_list (integer_type_node,
7862 pcchar_type_node, NULL_TREE);
7864 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7865 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7866 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7867 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7868 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7869 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7870 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7871 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7872 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7873 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7874 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7875 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7876 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7877 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7878 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7879 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7880 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7881 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7882 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7883 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7884 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7885 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7886 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7887 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7888 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7889 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7890 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7891 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7892 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7893 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7894 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7895 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7897 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7898 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7899 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7901 /* Add the DST variants. */
7902 d = (struct builtin_description *) bdesc_dst;
7903 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7904 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7906 /* Initialize the predicates. */
7907 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7908 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7910 enum machine_mode mode1;
7913 mode1 = insn_data[dp->icode].operand[1].mode;
7918 type = int_ftype_int_v4si_v4si;
7921 type = int_ftype_int_v8hi_v8hi;
7924 type = int_ftype_int_v16qi_v16qi;
7927 type = int_ftype_int_v4sf_v4sf;
7933 def_builtin (dp->mask, dp->name, type, dp->code);
7936 /* Initialize the abs* operators. */
7937 d = (struct builtin_description *) bdesc_abs;
7938 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7940 enum machine_mode mode0;
7943 mode0 = insn_data[d->icode].operand[0].mode;
7948 type = v4si_ftype_v4si;
7951 type = v8hi_ftype_v8hi;
7954 type = v16qi_ftype_v16qi;
7957 type = v4sf_ftype_v4sf;
7963 def_builtin (d->mask, d->name, type, d->code);
7970 /* Initialize target builtin that implements
7971 targetm.vectorize.builtin_mask_for_load. */
7973 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
7974 v16qi_ftype_long_pcvoid,
7975 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7976 BUILT_IN_MD, NULL, NULL_TREE);
7977 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7978 altivec_builtin_mask_for_load = decl;
7981 /* Initialize target builtin that implements
7982 targetm.vectorize.builtin_mask_for_store. */
7984 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_store",
7985 v16qi_ftype_long_pcvoid,
7986 ALTIVEC_BUILTIN_MASK_FOR_STORE,
7987 BUILT_IN_MD, NULL, NULL_TREE);
7988 /* Record the decl. Will be used by rs6000_builtin_mask_for_store. */
7989 altivec_builtin_mask_for_store = decl;
7994 rs6000_common_init_builtins (void)
7996 struct builtin_description *d;
7999 tree v4sf_ftype_v4sf_v4sf_v16qi
8000 = build_function_type_list (V4SF_type_node,
8001 V4SF_type_node, V4SF_type_node,
8002 V16QI_type_node, NULL_TREE);
8003 tree v4si_ftype_v4si_v4si_v16qi
8004 = build_function_type_list (V4SI_type_node,
8005 V4SI_type_node, V4SI_type_node,
8006 V16QI_type_node, NULL_TREE);
8007 tree v8hi_ftype_v8hi_v8hi_v16qi
8008 = build_function_type_list (V8HI_type_node,
8009 V8HI_type_node, V8HI_type_node,
8010 V16QI_type_node, NULL_TREE);
8011 tree v16qi_ftype_v16qi_v16qi_v16qi
8012 = build_function_type_list (V16QI_type_node,
8013 V16QI_type_node, V16QI_type_node,
8014 V16QI_type_node, NULL_TREE);
8016 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8018 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8019 tree v16qi_ftype_int
8020 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8021 tree v8hi_ftype_v16qi
8022 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8023 tree v4sf_ftype_v4sf
8024 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8026 tree v2si_ftype_v2si_v2si
8027 = build_function_type_list (opaque_V2SI_type_node,
8028 opaque_V2SI_type_node,
8029 opaque_V2SI_type_node, NULL_TREE);
8031 tree v2sf_ftype_v2sf_v2sf
8032 = build_function_type_list (opaque_V2SF_type_node,
8033 opaque_V2SF_type_node,
8034 opaque_V2SF_type_node, NULL_TREE);
8036 tree v2si_ftype_int_int
8037 = build_function_type_list (opaque_V2SI_type_node,
8038 integer_type_node, integer_type_node,
8041 tree v2si_ftype_v2si
8042 = build_function_type_list (opaque_V2SI_type_node,
8043 opaque_V2SI_type_node, NULL_TREE);
8045 tree v2sf_ftype_v2sf
8046 = build_function_type_list (opaque_V2SF_type_node,
8047 opaque_V2SF_type_node, NULL_TREE);
8049 tree v2sf_ftype_v2si
8050 = build_function_type_list (opaque_V2SF_type_node,
8051 opaque_V2SI_type_node, NULL_TREE);
8053 tree v2si_ftype_v2sf
8054 = build_function_type_list (opaque_V2SI_type_node,
8055 opaque_V2SF_type_node, NULL_TREE);
8057 tree v2si_ftype_v2si_char
8058 = build_function_type_list (opaque_V2SI_type_node,
8059 opaque_V2SI_type_node,
8060 char_type_node, NULL_TREE);
8062 tree v2si_ftype_int_char
8063 = build_function_type_list (opaque_V2SI_type_node,
8064 integer_type_node, char_type_node, NULL_TREE);
8066 tree v2si_ftype_char
8067 = build_function_type_list (opaque_V2SI_type_node,
8068 char_type_node, NULL_TREE);
8070 tree int_ftype_int_int
8071 = build_function_type_list (integer_type_node,
8072 integer_type_node, integer_type_node,
8075 tree v4si_ftype_v4si_v4si
8076 = build_function_type_list (V4SI_type_node,
8077 V4SI_type_node, V4SI_type_node, NULL_TREE);
8078 tree v4sf_ftype_v4si_int
8079 = build_function_type_list (V4SF_type_node,
8080 V4SI_type_node, integer_type_node, NULL_TREE);
8081 tree v4si_ftype_v4sf_int
8082 = build_function_type_list (V4SI_type_node,
8083 V4SF_type_node, integer_type_node, NULL_TREE);
8084 tree v4si_ftype_v4si_int
8085 = build_function_type_list (V4SI_type_node,
8086 V4SI_type_node, integer_type_node, NULL_TREE);
8087 tree v8hi_ftype_v8hi_int
8088 = build_function_type_list (V8HI_type_node,
8089 V8HI_type_node, integer_type_node, NULL_TREE);
8090 tree v16qi_ftype_v16qi_int
8091 = build_function_type_list (V16QI_type_node,
8092 V16QI_type_node, integer_type_node, NULL_TREE);
8093 tree v16qi_ftype_v16qi_v16qi_int
8094 = build_function_type_list (V16QI_type_node,
8095 V16QI_type_node, V16QI_type_node,
8096 integer_type_node, NULL_TREE);
8097 tree v8hi_ftype_v8hi_v8hi_int
8098 = build_function_type_list (V8HI_type_node,
8099 V8HI_type_node, V8HI_type_node,
8100 integer_type_node, NULL_TREE);
8101 tree v4si_ftype_v4si_v4si_int
8102 = build_function_type_list (V4SI_type_node,
8103 V4SI_type_node, V4SI_type_node,
8104 integer_type_node, NULL_TREE);
8105 tree v4sf_ftype_v4sf_v4sf_int
8106 = build_function_type_list (V4SF_type_node,
8107 V4SF_type_node, V4SF_type_node,
8108 integer_type_node, NULL_TREE);
8109 tree v4sf_ftype_v4sf_v4sf
8110 = build_function_type_list (V4SF_type_node,
8111 V4SF_type_node, V4SF_type_node, NULL_TREE);
8112 tree v4sf_ftype_v4sf_v4sf_v4si
8113 = build_function_type_list (V4SF_type_node,
8114 V4SF_type_node, V4SF_type_node,
8115 V4SI_type_node, NULL_TREE);
8116 tree v4sf_ftype_v4sf_v4sf_v4sf
8117 = build_function_type_list (V4SF_type_node,
8118 V4SF_type_node, V4SF_type_node,
8119 V4SF_type_node, NULL_TREE);
8120 tree v4si_ftype_v4si_v4si_v4si
8121 = build_function_type_list (V4SI_type_node,
8122 V4SI_type_node, V4SI_type_node,
8123 V4SI_type_node, NULL_TREE);
8124 tree v8hi_ftype_v8hi_v8hi
8125 = build_function_type_list (V8HI_type_node,
8126 V8HI_type_node, V8HI_type_node, NULL_TREE);
8127 tree v8hi_ftype_v8hi_v8hi_v8hi
8128 = build_function_type_list (V8HI_type_node,
8129 V8HI_type_node, V8HI_type_node,
8130 V8HI_type_node, NULL_TREE);
8131 tree v4si_ftype_v8hi_v8hi_v4si
8132 = build_function_type_list (V4SI_type_node,
8133 V8HI_type_node, V8HI_type_node,
8134 V4SI_type_node, NULL_TREE);
8135 tree v4si_ftype_v16qi_v16qi_v4si
8136 = build_function_type_list (V4SI_type_node,
8137 V16QI_type_node, V16QI_type_node,
8138 V4SI_type_node, NULL_TREE);
8139 tree v16qi_ftype_v16qi_v16qi
8140 = build_function_type_list (V16QI_type_node,
8141 V16QI_type_node, V16QI_type_node, NULL_TREE);
8142 tree v4si_ftype_v4sf_v4sf
8143 = build_function_type_list (V4SI_type_node,
8144 V4SF_type_node, V4SF_type_node, NULL_TREE);
8145 tree v8hi_ftype_v16qi_v16qi
8146 = build_function_type_list (V8HI_type_node,
8147 V16QI_type_node, V16QI_type_node, NULL_TREE);
8148 tree v4si_ftype_v8hi_v8hi
8149 = build_function_type_list (V4SI_type_node,
8150 V8HI_type_node, V8HI_type_node, NULL_TREE);
8151 tree v8hi_ftype_v4si_v4si
8152 = build_function_type_list (V8HI_type_node,
8153 V4SI_type_node, V4SI_type_node, NULL_TREE);
8154 tree v16qi_ftype_v8hi_v8hi
8155 = build_function_type_list (V16QI_type_node,
8156 V8HI_type_node, V8HI_type_node, NULL_TREE);
8157 tree v4si_ftype_v16qi_v4si
8158 = build_function_type_list (V4SI_type_node,
8159 V16QI_type_node, V4SI_type_node, NULL_TREE);
8160 tree v4si_ftype_v16qi_v16qi
8161 = build_function_type_list (V4SI_type_node,
8162 V16QI_type_node, V16QI_type_node, NULL_TREE);
8163 tree v4si_ftype_v8hi_v4si
8164 = build_function_type_list (V4SI_type_node,
8165 V8HI_type_node, V4SI_type_node, NULL_TREE);
8166 tree v4si_ftype_v8hi
8167 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8168 tree int_ftype_v4si_v4si
8169 = build_function_type_list (integer_type_node,
8170 V4SI_type_node, V4SI_type_node, NULL_TREE);
8171 tree int_ftype_v4sf_v4sf
8172 = build_function_type_list (integer_type_node,
8173 V4SF_type_node, V4SF_type_node, NULL_TREE);
8174 tree int_ftype_v16qi_v16qi
8175 = build_function_type_list (integer_type_node,
8176 V16QI_type_node, V16QI_type_node, NULL_TREE);
8177 tree int_ftype_v8hi_v8hi
8178 = build_function_type_list (integer_type_node,
8179 V8HI_type_node, V8HI_type_node, NULL_TREE);
8181 /* Add the simple ternary operators. */
8182 d = (struct builtin_description *) bdesc_3arg;
8183 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8186 enum machine_mode mode0, mode1, mode2, mode3;
8189 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8192 mode0 = insn_data[d->icode].operand[0].mode;
8193 mode1 = insn_data[d->icode].operand[1].mode;
8194 mode2 = insn_data[d->icode].operand[2].mode;
8195 mode3 = insn_data[d->icode].operand[3].mode;
8197 /* When all four are of the same mode. */
8198 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8203 type = v4si_ftype_v4si_v4si_v4si;
8206 type = v4sf_ftype_v4sf_v4sf_v4sf;
8209 type = v8hi_ftype_v8hi_v8hi_v8hi;
8212 type = v16qi_ftype_v16qi_v16qi_v16qi;
8218 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8223 type = v4si_ftype_v4si_v4si_v16qi;
8226 type = v4sf_ftype_v4sf_v4sf_v16qi;
8229 type = v8hi_ftype_v8hi_v8hi_v16qi;
8232 type = v16qi_ftype_v16qi_v16qi_v16qi;
8238 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8239 && mode3 == V4SImode)
8240 type = v4si_ftype_v16qi_v16qi_v4si;
8241 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8242 && mode3 == V4SImode)
8243 type = v4si_ftype_v8hi_v8hi_v4si;
8244 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8245 && mode3 == V4SImode)
8246 type = v4sf_ftype_v4sf_v4sf_v4si;
8248 /* vchar, vchar, vchar, 4 bit literal. */
8249 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8251 type = v16qi_ftype_v16qi_v16qi_int;
8253 /* vshort, vshort, vshort, 4 bit literal. */
8254 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8256 type = v8hi_ftype_v8hi_v8hi_int;
8258 /* vint, vint, vint, 4 bit literal. */
8259 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8261 type = v4si_ftype_v4si_v4si_int;
8263 /* vfloat, vfloat, vfloat, 4 bit literal. */
8264 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8266 type = v4sf_ftype_v4sf_v4sf_int;
8271 def_builtin (d->mask, d->name, type, d->code);
8274 /* Add the simple binary operators. */
8275 d = (struct builtin_description *) bdesc_2arg;
8276 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8278 enum machine_mode mode0, mode1, mode2;
8281 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8284 mode0 = insn_data[d->icode].operand[0].mode;
8285 mode1 = insn_data[d->icode].operand[1].mode;
8286 mode2 = insn_data[d->icode].operand[2].mode;
8288 /* When all three operands are of the same mode. */
8289 if (mode0 == mode1 && mode1 == mode2)
8294 type = v4sf_ftype_v4sf_v4sf;
8297 type = v4si_ftype_v4si_v4si;
8300 type = v16qi_ftype_v16qi_v16qi;
8303 type = v8hi_ftype_v8hi_v8hi;
8306 type = v2si_ftype_v2si_v2si;
8309 type = v2sf_ftype_v2sf_v2sf;
8312 type = int_ftype_int_int;
8319 /* A few other combos we really don't want to do manually. */
8321 /* vint, vfloat, vfloat. */
8322 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8323 type = v4si_ftype_v4sf_v4sf;
8325 /* vshort, vchar, vchar. */
8326 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8327 type = v8hi_ftype_v16qi_v16qi;
8329 /* vint, vshort, vshort. */
8330 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8331 type = v4si_ftype_v8hi_v8hi;
8333 /* vshort, vint, vint. */
8334 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8335 type = v8hi_ftype_v4si_v4si;
8337 /* vchar, vshort, vshort. */
8338 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8339 type = v16qi_ftype_v8hi_v8hi;
8341 /* vint, vchar, vint. */
8342 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8343 type = v4si_ftype_v16qi_v4si;
8345 /* vint, vchar, vchar. */
8346 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8347 type = v4si_ftype_v16qi_v16qi;
8349 /* vint, vshort, vint. */
8350 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8351 type = v4si_ftype_v8hi_v4si;
8353 /* vint, vint, 5 bit literal. */
8354 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8355 type = v4si_ftype_v4si_int;
8357 /* vshort, vshort, 5 bit literal. */
8358 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8359 type = v8hi_ftype_v8hi_int;
8361 /* vchar, vchar, 5 bit literal. */
8362 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8363 type = v16qi_ftype_v16qi_int;
8365 /* vfloat, vint, 5 bit literal. */
8366 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8367 type = v4sf_ftype_v4si_int;
8369 /* vint, vfloat, 5 bit literal. */
8370 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8371 type = v4si_ftype_v4sf_int;
8373 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8374 type = v2si_ftype_int_int;
8376 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8377 type = v2si_ftype_v2si_char;
8379 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8380 type = v2si_ftype_int_char;
8383 else if (mode0 == SImode)
8388 type = int_ftype_v4si_v4si;
8391 type = int_ftype_v4sf_v4sf;
8394 type = int_ftype_v16qi_v16qi;
8397 type = int_ftype_v8hi_v8hi;
8407 def_builtin (d->mask, d->name, type, d->code);
8410 /* Add the simple unary operators. */
8411 d = (struct builtin_description *) bdesc_1arg;
8412 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8414 enum machine_mode mode0, mode1;
8417 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8420 mode0 = insn_data[d->icode].operand[0].mode;
8421 mode1 = insn_data[d->icode].operand[1].mode;
8423 if (mode0 == V4SImode && mode1 == QImode)
8424 type = v4si_ftype_int;
8425 else if (mode0 == V8HImode && mode1 == QImode)
8426 type = v8hi_ftype_int;
8427 else if (mode0 == V16QImode && mode1 == QImode)
8428 type = v16qi_ftype_int;
8429 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8430 type = v4sf_ftype_v4sf;
8431 else if (mode0 == V8HImode && mode1 == V16QImode)
8432 type = v8hi_ftype_v16qi;
8433 else if (mode0 == V4SImode && mode1 == V8HImode)
8434 type = v4si_ftype_v8hi;
8435 else if (mode0 == V2SImode && mode1 == V2SImode)
8436 type = v2si_ftype_v2si;
8437 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8438 type = v2sf_ftype_v2sf;
8439 else if (mode0 == V2SFmode && mode1 == V2SImode)
8440 type = v2sf_ftype_v2si;
8441 else if (mode0 == V2SImode && mode1 == V2SFmode)
8442 type = v2si_ftype_v2sf;
8443 else if (mode0 == V2SImode && mode1 == QImode)
8444 type = v2si_ftype_char;
8448 def_builtin (d->mask, d->name, type, d->code);
8453 rs6000_init_libfuncs (void)
8455 if (!TARGET_HARD_FLOAT)
8458 if (DEFAULT_ABI != ABI_V4)
8460 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8462 /* AIX library routines for float->int conversion. */
8463 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8464 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8465 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8466 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8469 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8470 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8471 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8472 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8473 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8477 /* 32-bit SVR4 quad floating point routines. */
8479 set_optab_libfunc (add_optab, TFmode, "_q_add");
8480 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8481 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8482 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8483 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8484 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8485 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8487 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8488 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8489 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8490 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8491 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8492 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8494 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8495 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8496 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8497 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8498 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8499 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8500 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8505 /* Expand a block clear operation, and return 1 if successful. Return 0
8506 if we should let the compiler generate normal code.
8508 operands[0] is the destination
8509 operands[1] is the length
8510 operands[2] is the alignment */
8513 expand_block_clear (rtx operands[])
8515 rtx orig_dest = operands[0];
8516 rtx bytes_rtx = operands[1];
8517 rtx align_rtx = operands[2];
8518 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8519 HOST_WIDE_INT align;
8520 HOST_WIDE_INT bytes;
8525 /* If this is not a fixed size move, just call memcpy */
8529 /* If this is not a fixed size alignment, abort */
8530 if (GET_CODE (align_rtx) != CONST_INT)
8532 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8534 /* Anything to clear? */
8535 bytes = INTVAL (bytes_rtx);
8539 /* Use the builtin memset after a point, to avoid huge code bloat.
8540 When optimize_size, avoid any significant code bloat; calling
8541 memset is about 4 instructions, so allow for one instruction to
8542 load zero and three to do clearing. */
8543 if (TARGET_ALTIVEC && align >= 128)
8545 else if (TARGET_POWERPC64 && align >= 32)
8550 if (optimize_size && bytes > 3 * clear_step)
8552 if (! optimize_size && bytes > 8 * clear_step)
8555 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8557 enum machine_mode mode = BLKmode;
8560 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8565 else if (bytes >= 8 && TARGET_POWERPC64
8566 /* 64-bit loads and stores require word-aligned
8568 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8573 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8574 { /* move 4 bytes */
8578 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8579 { /* move 2 bytes */
8583 else /* move 1 byte at a time */
8589 dest = adjust_address (orig_dest, mode, offset);
8591 emit_move_insn (dest, CONST0_RTX (mode));
8598 /* Expand a block move operation, and return 1 if successful. Return 0
8599 if we should let the compiler generate normal code.
8601 operands[0] is the destination
8602 operands[1] is the source
8603 operands[2] is the length
8604 operands[3] is the alignment */
8606 #define MAX_MOVE_REG 4
8609 expand_block_move (rtx operands[])
8611 rtx orig_dest = operands[0];
8612 rtx orig_src = operands[1];
8613 rtx bytes_rtx = operands[2];
8614 rtx align_rtx = operands[3];
8615 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8620 rtx stores[MAX_MOVE_REG];
8623 /* If this is not a fixed size move, just call memcpy */
8627 /* If this is not a fixed size alignment, abort */
8628 if (GET_CODE (align_rtx) != CONST_INT)
8630 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8632 /* Anything to move? */
8633 bytes = INTVAL (bytes_rtx);
8637 /* store_one_arg depends on expand_block_move to handle at least the size of
8638 reg_parm_stack_space. */
8639 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8642 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8645 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8646 rtx (*mov) (rtx, rtx);
8648 enum machine_mode mode = BLKmode;
8651 /* Altivec first, since it will be faster than a string move
8652 when it applies, and usually not significantly larger. */
8653 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8657 gen_func.mov = gen_movv4si;
8659 else if (TARGET_STRING
8660 && bytes > 24 /* move up to 32 bytes at a time */
8668 && ! fixed_regs[12])
8670 move_bytes = (bytes > 32) ? 32 : bytes;
8671 gen_func.movmemsi = gen_movmemsi_8reg;
8673 else if (TARGET_STRING
8674 && bytes > 16 /* move up to 24 bytes at a time */
8680 && ! fixed_regs[10])
8682 move_bytes = (bytes > 24) ? 24 : bytes;
8683 gen_func.movmemsi = gen_movmemsi_6reg;
8685 else if (TARGET_STRING
8686 && bytes > 8 /* move up to 16 bytes at a time */
8692 move_bytes = (bytes > 16) ? 16 : bytes;
8693 gen_func.movmemsi = gen_movmemsi_4reg;
8695 else if (bytes >= 8 && TARGET_POWERPC64
8696 /* 64-bit loads and stores require word-aligned
8698 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8702 gen_func.mov = gen_movdi;
8704 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8705 { /* move up to 8 bytes at a time */
8706 move_bytes = (bytes > 8) ? 8 : bytes;
8707 gen_func.movmemsi = gen_movmemsi_2reg;
8709 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8710 { /* move 4 bytes */
8713 gen_func.mov = gen_movsi;
8715 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8716 { /* move 2 bytes */
8719 gen_func.mov = gen_movhi;
8721 else if (TARGET_STRING && bytes > 1)
8722 { /* move up to 4 bytes at a time */
8723 move_bytes = (bytes > 4) ? 4 : bytes;
8724 gen_func.movmemsi = gen_movmemsi_1reg;
8726 else /* move 1 byte at a time */
8730 gen_func.mov = gen_movqi;
8733 src = adjust_address (orig_src, mode, offset);
8734 dest = adjust_address (orig_dest, mode, offset);
8736 if (mode != BLKmode)
8738 rtx tmp_reg = gen_reg_rtx (mode);
8740 emit_insn ((*gen_func.mov) (tmp_reg, src));
8741 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8744 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8747 for (i = 0; i < num_reg; i++)
8748 emit_insn (stores[i]);
8752 if (mode == BLKmode)
8754 /* Move the address into scratch registers. The movmemsi
8755 patterns require zero offset. */
8756 if (!REG_P (XEXP (src, 0)))
8758 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8759 src = replace_equiv_address (src, src_reg);
8761 set_mem_size (src, GEN_INT (move_bytes));
8763 if (!REG_P (XEXP (dest, 0)))
8765 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8766 dest = replace_equiv_address (dest, dest_reg);
8768 set_mem_size (dest, GEN_INT (move_bytes));
8770 emit_insn ((*gen_func.movmemsi) (dest, src,
8771 GEN_INT (move_bytes & 31),
8780 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8781 known to be a PARALLEL. */
8783 save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8788 int count = XVECLEN (op, 0);
8794 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8795 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
8798 for (i=1; i <= 18; i++)
8800 elt = XVECEXP (op, 0, index++);
8801 if (GET_CODE (elt) != SET
8802 || GET_CODE (SET_DEST (elt)) != MEM
8803 || ! memory_operand (SET_DEST (elt), DFmode)
8804 || GET_CODE (SET_SRC (elt)) != REG
8805 || GET_MODE (SET_SRC (elt)) != DFmode)
8809 for (i=1; i <= 12; i++)
8811 elt = XVECEXP (op, 0, index++);
8812 if (GET_CODE (elt) != SET
8813 || GET_CODE (SET_DEST (elt)) != MEM
8814 || GET_CODE (SET_SRC (elt)) != REG
8815 || GET_MODE (SET_SRC (elt)) != V4SImode)
8819 for (i=1; i <= 19; i++)
8821 elt = XVECEXP (op, 0, index++);
8822 if (GET_CODE (elt) != SET
8823 || GET_CODE (SET_DEST (elt)) != MEM
8824 || ! memory_operand (SET_DEST (elt), Pmode)
8825 || GET_CODE (SET_SRC (elt)) != REG
8826 || GET_MODE (SET_SRC (elt)) != Pmode)
8830 elt = XVECEXP (op, 0, index++);
8831 if (GET_CODE (elt) != SET
8832 || GET_CODE (SET_DEST (elt)) != MEM
8833 || ! memory_operand (SET_DEST (elt), Pmode)
8834 || GET_CODE (SET_SRC (elt)) != REG
8835 || REGNO (SET_SRC (elt)) != CR2_REGNO
8836 || GET_MODE (SET_SRC (elt)) != Pmode)
8839 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
8840 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8841 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
8846 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8847 known to be a PARALLEL. */
8849 restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8854 int count = XVECLEN (op, 0);
8860 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
8861 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8862 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8863 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
8866 elt = XVECEXP (op, 0, index++);
8867 if (GET_CODE (elt) != SET
8868 || GET_CODE (SET_SRC (elt)) != MEM
8869 || ! memory_operand (SET_SRC (elt), Pmode)
8870 || GET_CODE (SET_DEST (elt)) != REG
8871 || REGNO (SET_DEST (elt)) != CR2_REGNO
8872 || GET_MODE (SET_DEST (elt)) != Pmode)
8875 for (i=1; i <= 19; i++)
8877 elt = XVECEXP (op, 0, index++);
8878 if (GET_CODE (elt) != SET
8879 || GET_CODE (SET_SRC (elt)) != MEM
8880 || ! memory_operand (SET_SRC (elt), Pmode)
8881 || GET_CODE (SET_DEST (elt)) != REG
8882 || GET_MODE (SET_DEST (elt)) != Pmode)
8886 for (i=1; i <= 12; i++)
8888 elt = XVECEXP (op, 0, index++);
8889 if (GET_CODE (elt) != SET
8890 || GET_CODE (SET_SRC (elt)) != MEM
8891 || GET_CODE (SET_DEST (elt)) != REG
8892 || GET_MODE (SET_DEST (elt)) != V4SImode)
8896 for (i=1; i <= 18; i++)
8898 elt = XVECEXP (op, 0, index++);
8899 if (GET_CODE (elt) != SET
8900 || GET_CODE (SET_SRC (elt)) != MEM
8901 || ! memory_operand (SET_SRC (elt), DFmode)
8902 || GET_CODE (SET_DEST (elt)) != REG
8903 || GET_MODE (SET_DEST (elt)) != DFmode)
8907 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8908 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8909 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8910 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8911 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
8917 /* Return 1 if OP is a load multiple operation. It is known to be a
8918 PARALLEL and the first section will be tested. */
8921 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8923 int count = XVECLEN (op, 0);
8924 unsigned int dest_regno;
8928 /* Perform a quick check so we don't blow up below. */
8930 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8931 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8932 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
8935 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8936 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
8938 for (i = 1; i < count; i++)
8940 rtx elt = XVECEXP (op, 0, i);
8942 if (GET_CODE (elt) != SET
8943 || GET_CODE (SET_DEST (elt)) != REG
8944 || GET_MODE (SET_DEST (elt)) != SImode
8945 || REGNO (SET_DEST (elt)) != dest_regno + i
8946 || GET_CODE (SET_SRC (elt)) != MEM
8947 || GET_MODE (SET_SRC (elt)) != SImode
8948 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
8949 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
8950 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
8951 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
8958 /* Similar, but tests for store multiple. Here, the second vector element
8959 is a CLOBBER. It will be tested later. */
8962 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8964 int count = XVECLEN (op, 0) - 1;
8965 unsigned int src_regno;
8969 /* Perform a quick check so we don't blow up below. */
8971 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8972 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
8973 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
8976 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8977 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
8979 for (i = 1; i < count; i++)
8981 rtx elt = XVECEXP (op, 0, i + 1);
8983 if (GET_CODE (elt) != SET
8984 || GET_CODE (SET_SRC (elt)) != REG
8985 || GET_MODE (SET_SRC (elt)) != SImode
8986 || REGNO (SET_SRC (elt)) != src_regno + i
8987 || GET_CODE (SET_DEST (elt)) != MEM
8988 || GET_MODE (SET_DEST (elt)) != SImode
8989 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
8990 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
8991 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
8992 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
8999 /* Return a string to perform a load_multiple operation.
9000 operands[0] is the vector.
9001 operands[1] is the source address.
9002 operands[2] is the first destination register. */
9005 rs6000_output_load_multiple (rtx operands[3])
9007 /* We have to handle the case where the pseudo used to contain the address
9008 is assigned to one of the output registers. */
9010 int words = XVECLEN (operands[0], 0);
9013 if (XVECLEN (operands[0], 0) == 1)
9014 return "{l|lwz} %2,0(%1)";
9016 for (i = 0; i < words; i++)
9017 if (refers_to_regno_p (REGNO (operands[2]) + i,
9018 REGNO (operands[2]) + i + 1, operands[1], 0))
9022 xop[0] = GEN_INT (4 * (words-1));
9023 xop[1] = operands[1];
9024 xop[2] = operands[2];
9025 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9030 xop[0] = GEN_INT (4 * (words-1));
9031 xop[1] = operands[1];
9032 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9033 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9038 for (j = 0; j < words; j++)
9041 xop[0] = GEN_INT (j * 4);
9042 xop[1] = operands[1];
9043 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9044 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9046 xop[0] = GEN_INT (i * 4);
9047 xop[1] = operands[1];
9048 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9053 return "{lsi|lswi} %2,%1,%N0";
9056 /* Return 1 for a parallel vrsave operation. */
9059 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9061 int count = XVECLEN (op, 0);
9062 unsigned int dest_regno, src_regno;
9066 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9067 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9068 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
9071 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9072 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9074 if (dest_regno != VRSAVE_REGNO
9075 && src_regno != VRSAVE_REGNO)
9078 for (i = 1; i < count; i++)
9080 rtx elt = XVECEXP (op, 0, i);
9082 if (GET_CODE (elt) != CLOBBER
9083 && GET_CODE (elt) != SET)
9090 /* Return 1 for an PARALLEL suitable for mfcr. */
9093 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9095 int count = XVECLEN (op, 0);
9098 /* Perform a quick check so we don't blow up below. */
9100 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9101 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9102 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9105 for (i = 0; i < count; i++)
9107 rtx exp = XVECEXP (op, 0, i);
9112 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
9114 if (GET_CODE (src_reg) != REG
9115 || GET_MODE (src_reg) != CCmode
9116 || ! CR_REGNO_P (REGNO (src_reg)))
9119 if (GET_CODE (exp) != SET
9120 || GET_CODE (SET_DEST (exp)) != REG
9121 || GET_MODE (SET_DEST (exp)) != SImode
9122 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
9124 unspec = SET_SRC (exp);
9125 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
9127 if (GET_CODE (unspec) != UNSPEC
9128 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
9129 || XVECLEN (unspec, 0) != 2
9130 || XVECEXP (unspec, 0, 0) != src_reg
9131 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9132 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9138 /* Return 1 for an PARALLEL suitable for mtcrf. */
9141 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9143 int count = XVECLEN (op, 0);
9147 /* Perform a quick check so we don't blow up below. */
9149 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9150 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9151 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9153 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
9155 if (GET_CODE (src_reg) != REG
9156 || GET_MODE (src_reg) != SImode
9157 || ! INT_REGNO_P (REGNO (src_reg)))
9160 for (i = 0; i < count; i++)
9162 rtx exp = XVECEXP (op, 0, i);
9166 if (GET_CODE (exp) != SET
9167 || GET_CODE (SET_DEST (exp)) != REG
9168 || GET_MODE (SET_DEST (exp)) != CCmode
9169 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
9171 unspec = SET_SRC (exp);
9172 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
9174 if (GET_CODE (unspec) != UNSPEC
9175 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
9176 || XVECLEN (unspec, 0) != 2
9177 || XVECEXP (unspec, 0, 0) != src_reg
9178 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9179 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9185 /* Return 1 for an PARALLEL suitable for lmw. */
9188 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9190 int count = XVECLEN (op, 0);
9191 unsigned int dest_regno;
9193 unsigned int base_regno;
9194 HOST_WIDE_INT offset;
9197 /* Perform a quick check so we don't blow up below. */
9199 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9200 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9201 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9204 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9205 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9208 || count != 32 - (int) dest_regno)
9211 if (legitimate_indirect_address_p (src_addr, 0))
9214 base_regno = REGNO (src_addr);
9215 if (base_regno == 0)
9218 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
9220 offset = INTVAL (XEXP (src_addr, 1));
9221 base_regno = REGNO (XEXP (src_addr, 0));
9226 for (i = 0; i < count; i++)
9228 rtx elt = XVECEXP (op, 0, i);
9231 HOST_WIDE_INT newoffset;
9233 if (GET_CODE (elt) != SET
9234 || GET_CODE (SET_DEST (elt)) != REG
9235 || GET_MODE (SET_DEST (elt)) != SImode
9236 || REGNO (SET_DEST (elt)) != dest_regno + i
9237 || GET_CODE (SET_SRC (elt)) != MEM
9238 || GET_MODE (SET_SRC (elt)) != SImode)
9240 newaddr = XEXP (SET_SRC (elt), 0);
9241 if (legitimate_indirect_address_p (newaddr, 0))
9246 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9248 addr_reg = XEXP (newaddr, 0);
9249 newoffset = INTVAL (XEXP (newaddr, 1));
9253 if (REGNO (addr_reg) != base_regno
9254 || newoffset != offset + 4 * i)
9261 /* Return 1 for an PARALLEL suitable for stmw. */
9264 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9266 int count = XVECLEN (op, 0);
9267 unsigned int src_regno;
9269 unsigned int base_regno;
9270 HOST_WIDE_INT offset;
9273 /* Perform a quick check so we don't blow up below. */
9275 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9276 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9277 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9280 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9281 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9284 || count != 32 - (int) src_regno)
9287 if (legitimate_indirect_address_p (dest_addr, 0))
9290 base_regno = REGNO (dest_addr);
9291 if (base_regno == 0)
9294 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
9296 offset = INTVAL (XEXP (dest_addr, 1));
9297 base_regno = REGNO (XEXP (dest_addr, 0));
9302 for (i = 0; i < count; i++)
9304 rtx elt = XVECEXP (op, 0, i);
9307 HOST_WIDE_INT newoffset;
9309 if (GET_CODE (elt) != SET
9310 || GET_CODE (SET_SRC (elt)) != REG
9311 || GET_MODE (SET_SRC (elt)) != SImode
9312 || REGNO (SET_SRC (elt)) != src_regno + i
9313 || GET_CODE (SET_DEST (elt)) != MEM
9314 || GET_MODE (SET_DEST (elt)) != SImode)
9316 newaddr = XEXP (SET_DEST (elt), 0);
9317 if (legitimate_indirect_address_p (newaddr, 0))
9322 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9324 addr_reg = XEXP (newaddr, 0);
9325 newoffset = INTVAL (XEXP (newaddr, 1));
9329 if (REGNO (addr_reg) != base_regno
9330 || newoffset != offset + 4 * i)
9337 /* A validation routine: say whether CODE, a condition code, and MODE
9338 match. The other alternatives either don't make sense or should
9339 never be generated. */
9342 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9344 if ((GET_RTX_CLASS (code) != RTX_COMPARE
9345 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
9346 || GET_MODE_CLASS (mode) != MODE_CC)
9349 /* These don't make sense. */
9350 if ((code == GT || code == LT || code == GE || code == LE)
9351 && mode == CCUNSmode)
9354 if ((code == GTU || code == LTU || code == GEU || code == LEU)
9355 && mode != CCUNSmode)
9358 if (mode != CCFPmode
9359 && (code == ORDERED || code == UNORDERED
9360 || code == UNEQ || code == LTGT
9361 || code == UNGT || code == UNLT
9362 || code == UNGE || code == UNLE))
9365 /* These should never be generated except for
9366 flag_finite_math_only. */
9367 if (mode == CCFPmode
9368 && ! flag_finite_math_only
9369 && (code == LE || code == GE
9370 || code == UNEQ || code == LTGT
9371 || code == UNGT || code == UNLT))
9374 /* These are invalid; the information is not there. */
9375 if (mode == CCEQmode
9376 && code != EQ && code != NE)
9380 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9381 We only check the opcode against the mode of the CC value here. */
9384 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9386 enum rtx_code code = GET_CODE (op);
9387 enum machine_mode cc_mode;
9389 if (!COMPARISON_P (op))
9392 cc_mode = GET_MODE (XEXP (op, 0));
9393 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
9396 validate_condition_mode (code, cc_mode);
9401 /* Return 1 if OP is a comparison operation that is valid for a branch
9402 insn and which is true if the corresponding bit in the CC register
9406 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
9410 if (! branch_comparison_operator (op, mode))
9413 code = GET_CODE (op);
9414 return (code == EQ || code == LT || code == GT
9415 || code == LTU || code == GTU
9416 || code == UNORDERED);
9419 /* Return 1 if OP is a comparison operation that is valid for an scc
9420 insn: it must be a positive comparison. */
9423 scc_comparison_operator (rtx op, enum machine_mode mode)
9425 return branch_positive_comparison_operator (op, mode);
9429 trap_comparison_operator (rtx op, enum machine_mode mode)
9431 if (mode != VOIDmode && mode != GET_MODE (op))
9433 return COMPARISON_P (op);
9437 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9439 enum rtx_code code = GET_CODE (op);
9440 return (code == AND || code == IOR || code == XOR);
9444 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9446 enum rtx_code code = GET_CODE (op);
9447 return (code == IOR || code == XOR);
9451 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9453 enum rtx_code code = GET_CODE (op);
9454 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
9457 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9458 mask required to convert the result of a rotate insn into a shift
9459 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9462 includes_lshift_p (rtx shiftop, rtx andop)
9464 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9466 shift_mask <<= INTVAL (shiftop);
9468 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9471 /* Similar, but for right shift. */
9474 includes_rshift_p (rtx shiftop, rtx andop)
9476 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9478 shift_mask >>= INTVAL (shiftop);
9480 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9483 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9484 to perform a left shift. It must have exactly SHIFTOP least
9485 significant 0's, then one or more 1's, then zero or more 0's. */
9488 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9490 if (GET_CODE (andop) == CONST_INT)
9492 HOST_WIDE_INT c, lsb, shift_mask;
9495 if (c == 0 || c == ~0)
9499 shift_mask <<= INTVAL (shiftop);
9501 /* Find the least significant one bit. */
9504 /* It must coincide with the LSB of the shift mask. */
9505 if (-lsb != shift_mask)
9508 /* Invert to look for the next transition (if any). */
9511 /* Remove the low group of ones (originally low group of zeros). */
9514 /* Again find the lsb, and check we have all 1's above. */
9518 else if (GET_CODE (andop) == CONST_DOUBLE
9519 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9521 HOST_WIDE_INT low, high, lsb;
9522 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9524 low = CONST_DOUBLE_LOW (andop);
9525 if (HOST_BITS_PER_WIDE_INT < 64)
9526 high = CONST_DOUBLE_HIGH (andop);
9528 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9529 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9532 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9534 shift_mask_high = ~0;
9535 if (INTVAL (shiftop) > 32)
9536 shift_mask_high <<= INTVAL (shiftop) - 32;
9540 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9547 return high == -lsb;
9550 shift_mask_low = ~0;
9551 shift_mask_low <<= INTVAL (shiftop);
9555 if (-lsb != shift_mask_low)
9558 if (HOST_BITS_PER_WIDE_INT < 64)
9563 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9566 return high == -lsb;
9570 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9576 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9577 to perform a left shift. It must have SHIFTOP or more least
9578 significant 0's, with the remainder of the word 1's. */
9581 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9583 if (GET_CODE (andop) == CONST_INT)
9585 HOST_WIDE_INT c, lsb, shift_mask;
9588 shift_mask <<= INTVAL (shiftop);
9591 /* Find the least significant one bit. */
9594 /* It must be covered by the shift mask.
9595 This test also rejects c == 0. */
9596 if ((lsb & shift_mask) == 0)
9599 /* Check we have all 1's above the transition, and reject all 1's. */
9600 return c == -lsb && lsb != 1;
9602 else if (GET_CODE (andop) == CONST_DOUBLE
9603 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9605 HOST_WIDE_INT low, lsb, shift_mask_low;
9607 low = CONST_DOUBLE_LOW (andop);
9609 if (HOST_BITS_PER_WIDE_INT < 64)
9611 HOST_WIDE_INT high, shift_mask_high;
9613 high = CONST_DOUBLE_HIGH (andop);
9617 shift_mask_high = ~0;
9618 if (INTVAL (shiftop) > 32)
9619 shift_mask_high <<= INTVAL (shiftop) - 32;
9623 if ((lsb & shift_mask_high) == 0)
9626 return high == -lsb;
9632 shift_mask_low = ~0;
9633 shift_mask_low <<= INTVAL (shiftop);
9637 if ((lsb & shift_mask_low) == 0)
9640 return low == -lsb && lsb != 1;
9646 /* Return 1 if operands will generate a valid arguments to rlwimi
9647 instruction for insert with right shift in 64-bit mode. The mask may
9648 not start on the first bit or stop on the last bit because wrap-around
9649 effects of instruction do not correspond to semantics of RTL insn. */
9652 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9654 if (INTVAL (startop) < 64
9655 && INTVAL (startop) > 32
9656 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9657 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9658 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9659 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9660 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9666 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9667 for lfq and stfq insns iff the registers are hard registers. */
9670 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9672 /* We might have been passed a SUBREG. */
9673 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9676 /* We might have been passed non floating point registers. */
9677 if (!FP_REGNO_P (REGNO (reg1))
9678 || !FP_REGNO_P (REGNO (reg2)))
9681 return (REGNO (reg1) == REGNO (reg2) - 1);
9684 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9685 addr1 and addr2 must be in consecutive memory locations
9686 (addr2 == addr1 + 8). */
9689 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9695 /* The mems cannot be volatile. */
9696 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9699 addr1 = XEXP (mem1, 0);
9700 addr2 = XEXP (mem2, 0);
9702 /* Extract an offset (if used) from the first addr. */
9703 if (GET_CODE (addr1) == PLUS)
9705 /* If not a REG, return zero. */
9706 if (GET_CODE (XEXP (addr1, 0)) != REG)
9710 reg1 = REGNO (XEXP (addr1, 0));
9711 /* The offset must be constant! */
9712 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9714 offset1 = INTVAL (XEXP (addr1, 1));
9717 else if (GET_CODE (addr1) != REG)
9721 reg1 = REGNO (addr1);
9722 /* This was a simple (mem (reg)) expression. Offset is 0. */
9726 /* Make sure the second address is a (mem (plus (reg) (const_int)))
9727 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
9728 register as addr1. */
9729 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
9731 if (GET_CODE (addr2) != PLUS)
9734 if (GET_CODE (XEXP (addr2, 0)) != REG
9735 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9738 if (reg1 != REGNO (XEXP (addr2, 0)))
9741 /* The offset for the second addr must be 8 more than the first addr. */
9742 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
9745 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9750 /* Return the register class of a scratch register needed to copy IN into
9751 or out of a register in CLASS in MODE. If it can be done directly,
9752 NO_REGS is returned. */
9755 secondary_reload_class (enum reg_class class,
9756 enum machine_mode mode ATTRIBUTE_UNUSED,
9761 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9763 && MACHOPIC_INDIRECT
9767 /* We cannot copy a symbolic operand directly into anything
9768 other than BASE_REGS for TARGET_ELF. So indicate that a
9769 register from BASE_REGS is needed as an intermediate
9772 On Darwin, pic addresses require a load from memory, which
9773 needs a base register. */
9774 if (class != BASE_REGS
9775 && (GET_CODE (in) == SYMBOL_REF
9776 || GET_CODE (in) == HIGH
9777 || GET_CODE (in) == LABEL_REF
9778 || GET_CODE (in) == CONST))
9782 if (GET_CODE (in) == REG)
9785 if (regno >= FIRST_PSEUDO_REGISTER)
9787 regno = true_regnum (in);
9788 if (regno >= FIRST_PSEUDO_REGISTER)
9792 else if (GET_CODE (in) == SUBREG)
9794 regno = true_regnum (in);
9795 if (regno >= FIRST_PSEUDO_REGISTER)
9801 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9803 if (class == GENERAL_REGS || class == BASE_REGS
9804 || (regno >= 0 && INT_REGNO_P (regno)))
9807 /* Constants, memory, and FP registers can go into FP registers. */
9808 if ((regno == -1 || FP_REGNO_P (regno))
9809 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9812 /* Memory, and AltiVec registers can go into AltiVec registers. */
9813 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9814 && class == ALTIVEC_REGS)
9817 /* We can copy among the CR registers. */
9818 if ((class == CR_REGS || class == CR0_REGS)
9819 && regno >= 0 && CR_REGNO_P (regno))
9822 /* Otherwise, we need GENERAL_REGS. */
9823 return GENERAL_REGS;
9826 /* Given a comparison operation, return the bit number in CCR to test. We
9827 know this is a valid comparison.
9829 SCC_P is 1 if this is for an scc. That means that %D will have been
9830 used instead of %C, so the bits will be in different places.
9832 Return -1 if OP isn't a valid comparison for some reason. */
9835 ccr_bit (rtx op, int scc_p)
9837 enum rtx_code code = GET_CODE (op);
9838 enum machine_mode cc_mode;
9843 if (!COMPARISON_P (op))
9848 if (GET_CODE (reg) != REG
9849 || ! CR_REGNO_P (REGNO (reg)))
9852 cc_mode = GET_MODE (reg);
9853 cc_regnum = REGNO (reg);
9854 base_bit = 4 * (cc_regnum - CR0_REGNO);
9856 validate_condition_mode (code, cc_mode);
9858 /* When generating a sCOND operation, only positive conditions are
9860 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
9861 && code != GTU && code != LTU)
9867 return scc_p ? base_bit + 3 : base_bit + 2;
9869 return base_bit + 2;
9870 case GT: case GTU: case UNLE:
9871 return base_bit + 1;
9872 case LT: case LTU: case UNGE:
9874 case ORDERED: case UNORDERED:
9875 return base_bit + 3;
9878 /* If scc, we will have done a cror to put the bit in the
9879 unordered position. So test that bit. For integer, this is ! LT
9880 unless this is an scc insn. */
9881 return scc_p ? base_bit + 3 : base_bit;
9884 return scc_p ? base_bit + 3 : base_bit + 1;
9891 /* Return the GOT register. */
9894 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9896 /* The second flow pass currently (June 1999) can't update
9897 regs_ever_live without disturbing other parts of the compiler, so
9898 update it here to make the prolog/epilogue code happy. */
9899 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9900 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9902 current_function_uses_pic_offset_table = 1;
9904 return pic_offset_table_rtx;
9907 /* Function to init struct machine_function.
9908 This will be called, via a pointer variable,
9909 from push_function_context. */
9911 static struct machine_function *
9912 rs6000_init_machine_status (void)
9914 return ggc_alloc_cleared (sizeof (machine_function));
9917 /* These macros test for integers and extract the low-order bits. */
9919 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9920 && GET_MODE (X) == VOIDmode)
9922 #define INT_LOWPART(X) \
9923 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9929 unsigned long val = INT_LOWPART (op);
9931 /* If the high bit is zero, the value is the first 1 bit we find
9933 if ((val & 0x80000000) == 0)
9935 if ((val & 0xffffffff) == 0)
9939 while (((val <<= 1) & 0x80000000) == 0)
9944 /* If the high bit is set and the low bit is not, or the mask is all
9945 1's, the value is zero. */
9946 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9949 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9952 while (((val >>= 1) & 1) != 0)
9962 unsigned long val = INT_LOWPART (op);
9964 /* If the low bit is zero, the value is the first 1 bit we find from
9968 if ((val & 0xffffffff) == 0)
9972 while (((val >>= 1) & 1) == 0)
9978 /* If the low bit is set and the high bit is not, or the mask is all
9979 1's, the value is 31. */
9980 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9983 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9986 while (((val <<= 1) & 0x80000000) != 0)
9992 /* Locate some local-dynamic symbol still in use by this function
9993 so that we can print its name in some tls_ld pattern. */
9996 rs6000_get_some_local_dynamic_name (void)
10000 if (cfun->machine->some_ld_name)
10001 return cfun->machine->some_ld_name;
10003 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10005 && for_each_rtx (&PATTERN (insn),
10006 rs6000_get_some_local_dynamic_name_1, 0))
10007 return cfun->machine->some_ld_name;
10012 /* Helper function for rs6000_get_some_local_dynamic_name. */
10015 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10019 if (GET_CODE (x) == SYMBOL_REF)
10021 const char *str = XSTR (x, 0);
10022 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10024 cfun->machine->some_ld_name = str;
10032 /* Write out a function code label. */
10035 rs6000_output_function_entry (FILE *file, const char *fname)
10037 if (fname[0] != '.')
10039 switch (DEFAULT_ABI)
10048 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10057 RS6000_OUTPUT_BASENAME (file, fname);
10059 assemble_name (file, fname);
10062 /* Print an operand. Recognize special options, documented below. */
10065 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10066 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10068 #define SMALL_DATA_RELOC "sda21"
10069 #define SMALL_DATA_REG 0
10073 print_operand (FILE *file, rtx x, int code)
10077 unsigned HOST_WIDE_INT uval;
10082 /* Write out an instruction after the call which may be replaced
10083 with glue code by the loader. This depends on the AIX version. */
10084 asm_fprintf (file, RS6000_CALL_GLUE);
10087 /* %a is output_address. */
10090 /* If X is a constant integer whose low-order 5 bits are zero,
10091 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10092 in the AIX assembler where "sri" with a zero shift count
10093 writes a trash instruction. */
10094 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10101 /* If constant, low-order 16 bits of constant, unsigned.
10102 Otherwise, write normally. */
10104 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10106 print_operand (file, x, 0);
10110 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10111 for 64-bit mask direction. */
10112 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
10115 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10119 /* X is a CR register. Print the number of the GT bit of the CR. */
10120 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10121 output_operand_lossage ("invalid %%E value");
10123 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10127 /* Like 'J' but get to the EQ bit. */
10128 if (GET_CODE (x) != REG)
10131 /* Bit 1 is EQ bit. */
10132 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10134 /* If we want bit 31, write a shift count of zero, not 32. */
10135 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10139 /* X is a CR register. Print the number of the EQ bit of the CR */
10140 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10141 output_operand_lossage ("invalid %%E value");
10143 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10147 /* X is a CR register. Print the shift count needed to move it
10148 to the high-order four bits. */
10149 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10150 output_operand_lossage ("invalid %%f value");
10152 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10156 /* Similar, but print the count for the rotate in the opposite
10158 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10159 output_operand_lossage ("invalid %%F value");
10161 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10165 /* X is a constant integer. If it is negative, print "m",
10166 otherwise print "z". This is to make an aze or ame insn. */
10167 if (GET_CODE (x) != CONST_INT)
10168 output_operand_lossage ("invalid %%G value");
10169 else if (INTVAL (x) >= 0)
10176 /* If constant, output low-order five bits. Otherwise, write
10179 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10181 print_operand (file, x, 0);
10185 /* If constant, output low-order six bits. Otherwise, write
10188 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10190 print_operand (file, x, 0);
10194 /* Print `i' if this is a constant, else nothing. */
10200 /* Write the bit number in CCR for jump. */
10201 i = ccr_bit (x, 0);
10203 output_operand_lossage ("invalid %%j code");
10205 fprintf (file, "%d", i);
10209 /* Similar, but add one for shift count in rlinm for scc and pass
10210 scc flag to `ccr_bit'. */
10211 i = ccr_bit (x, 1);
10213 output_operand_lossage ("invalid %%J code");
10215 /* If we want bit 31, write a shift count of zero, not 32. */
10216 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10220 /* X must be a constant. Write the 1's complement of the
10223 output_operand_lossage ("invalid %%k value");
10225 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10229 /* X must be a symbolic constant on ELF. Write an
10230 expression suitable for an 'addi' that adds in the low 16
10231 bits of the MEM. */
10232 if (GET_CODE (x) != CONST)
10234 print_operand_address (file, x);
10235 fputs ("@l", file);
10239 if (GET_CODE (XEXP (x, 0)) != PLUS
10240 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10241 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10242 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10243 output_operand_lossage ("invalid %%K value");
10244 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10245 fputs ("@l", file);
10246 /* For GNU as, there must be a non-alphanumeric character
10247 between 'l' and the number. The '-' is added by
10248 print_operand() already. */
10249 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10251 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10255 /* %l is output_asm_label. */
10258 /* Write second word of DImode or DFmode reference. Works on register
10259 or non-indexed memory only. */
10260 if (GET_CODE (x) == REG)
10261 fputs (reg_names[REGNO (x) + 1], file);
10262 else if (GET_CODE (x) == MEM)
10264 /* Handle possible auto-increment. Since it is pre-increment and
10265 we have already done it, we can just use an offset of word. */
10266 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10267 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10268 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10271 output_address (XEXP (adjust_address_nv (x, SImode,
10275 if (small_data_operand (x, GET_MODE (x)))
10276 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10277 reg_names[SMALL_DATA_REG]);
10282 /* MB value for a mask operand. */
10283 if (! mask_operand (x, SImode))
10284 output_operand_lossage ("invalid %%m value");
10286 fprintf (file, "%d", extract_MB (x));
10290 /* ME value for a mask operand. */
10291 if (! mask_operand (x, SImode))
10292 output_operand_lossage ("invalid %%M value");
10294 fprintf (file, "%d", extract_ME (x));
10297 /* %n outputs the negative of its operand. */
10300 /* Write the number of elements in the vector times 4. */
10301 if (GET_CODE (x) != PARALLEL)
10302 output_operand_lossage ("invalid %%N value");
10304 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10308 /* Similar, but subtract 1 first. */
10309 if (GET_CODE (x) != PARALLEL)
10310 output_operand_lossage ("invalid %%O value");
10312 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10316 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10318 || INT_LOWPART (x) < 0
10319 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10320 output_operand_lossage ("invalid %%p value");
10322 fprintf (file, "%d", i);
10326 /* The operand must be an indirect memory reference. The result
10327 is the register name. */
10328 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10329 || REGNO (XEXP (x, 0)) >= 32)
10330 output_operand_lossage ("invalid %%P value");
10332 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10336 /* This outputs the logical code corresponding to a boolean
10337 expression. The expression may have one or both operands
10338 negated (if one, only the first one). For condition register
10339 logical operations, it will also treat the negated
10340 CR codes as NOTs, but not handle NOTs of them. */
10342 const char *const *t = 0;
10344 enum rtx_code code = GET_CODE (x);
10345 static const char * const tbl[3][3] = {
10346 { "and", "andc", "nor" },
10347 { "or", "orc", "nand" },
10348 { "xor", "eqv", "xor" } };
10352 else if (code == IOR)
10354 else if (code == XOR)
10357 output_operand_lossage ("invalid %%q value");
10359 if (GET_CODE (XEXP (x, 0)) != NOT)
10363 if (GET_CODE (XEXP (x, 1)) == NOT)
10381 /* X is a CR register. Print the mask for `mtcrf'. */
10382 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10383 output_operand_lossage ("invalid %%R value");
10385 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10389 /* Low 5 bits of 32 - value */
10391 output_operand_lossage ("invalid %%s value");
10393 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10397 /* PowerPC64 mask position. All 0's is excluded.
10398 CONST_INT 32-bit mask is considered sign-extended so any
10399 transition must occur within the CONST_INT, not on the boundary. */
10400 if (! mask64_operand (x, DImode))
10401 output_operand_lossage ("invalid %%S value");
10403 uval = INT_LOWPART (x);
10405 if (uval & 1) /* Clear Left */
10407 #if HOST_BITS_PER_WIDE_INT > 64
10408 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10412 else /* Clear Right */
10415 #if HOST_BITS_PER_WIDE_INT > 64
10416 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10424 fprintf (file, "%d", i);
10428 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10429 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
10432 /* Bit 3 is OV bit. */
10433 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10435 /* If we want bit 31, write a shift count of zero, not 32. */
10436 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10440 /* Print the symbolic name of a branch target register. */
10441 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10442 && REGNO (x) != COUNT_REGISTER_REGNUM))
10443 output_operand_lossage ("invalid %%T value");
10444 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10445 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10447 fputs ("ctr", file);
10451 /* High-order 16 bits of constant for use in unsigned operand. */
10453 output_operand_lossage ("invalid %%u value");
10455 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10456 (INT_LOWPART (x) >> 16) & 0xffff);
10460 /* High-order 16 bits of constant for use in signed operand. */
10462 output_operand_lossage ("invalid %%v value");
10464 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10465 (INT_LOWPART (x) >> 16) & 0xffff);
10469 /* Print `u' if this has an auto-increment or auto-decrement. */
10470 if (GET_CODE (x) == MEM
10471 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10472 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10477 /* Print the trap code for this operand. */
10478 switch (GET_CODE (x))
10481 fputs ("eq", file); /* 4 */
10484 fputs ("ne", file); /* 24 */
10487 fputs ("lt", file); /* 16 */
10490 fputs ("le", file); /* 20 */
10493 fputs ("gt", file); /* 8 */
10496 fputs ("ge", file); /* 12 */
10499 fputs ("llt", file); /* 2 */
10502 fputs ("lle", file); /* 6 */
10505 fputs ("lgt", file); /* 1 */
10508 fputs ("lge", file); /* 5 */
10516 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10519 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10520 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10522 print_operand (file, x, 0);
10526 /* MB value for a PowerPC64 rldic operand. */
10527 val = (GET_CODE (x) == CONST_INT
10528 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10533 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10534 if ((val <<= 1) < 0)
10537 #if HOST_BITS_PER_WIDE_INT == 32
10538 if (GET_CODE (x) == CONST_INT && i >= 0)
10539 i += 32; /* zero-extend high-part was all 0's */
10540 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10542 val = CONST_DOUBLE_LOW (x);
10549 for ( ; i < 64; i++)
10550 if ((val <<= 1) < 0)
10555 fprintf (file, "%d", i + 1);
10559 if (GET_CODE (x) == MEM
10560 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10565 /* Like 'L', for third word of TImode */
10566 if (GET_CODE (x) == REG)
10567 fputs (reg_names[REGNO (x) + 2], file);
10568 else if (GET_CODE (x) == MEM)
10570 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10571 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10572 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10574 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10575 if (small_data_operand (x, GET_MODE (x)))
10576 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10577 reg_names[SMALL_DATA_REG]);
10582 /* X is a SYMBOL_REF. Write out the name preceded by a
10583 period and without any trailing data in brackets. Used for function
10584 names. If we are configured for System V (or the embedded ABI) on
10585 the PowerPC, do not emit the period, since those systems do not use
10586 TOCs and the like. */
10587 if (GET_CODE (x) != SYMBOL_REF)
10590 /* Mark the decl as referenced so that cgraph will output the
10592 if (SYMBOL_REF_DECL (x))
10593 mark_decl_referenced (SYMBOL_REF_DECL (x));
10595 /* For macho, check to see if we need a stub. */
10598 const char *name = XSTR (x, 0);
10600 if (MACHOPIC_INDIRECT
10601 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10602 name = machopic_indirection_name (x, /*stub_p=*/true);
10604 assemble_name (file, name);
10606 else if (!DOT_SYMBOLS)
10607 assemble_name (file, XSTR (x, 0));
10609 rs6000_output_function_entry (file, XSTR (x, 0));
10613 /* Like 'L', for last word of TImode. */
10614 if (GET_CODE (x) == REG)
10615 fputs (reg_names[REGNO (x) + 3], file);
10616 else if (GET_CODE (x) == MEM)
10618 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10619 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10620 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10622 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10623 if (small_data_operand (x, GET_MODE (x)))
10624 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10625 reg_names[SMALL_DATA_REG]);
10629 /* Print AltiVec or SPE memory operand. */
10634 if (GET_CODE (x) != MEM)
10641 /* Handle [reg]. */
10642 if (GET_CODE (tmp) == REG)
10644 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10647 /* Handle [reg+UIMM]. */
10648 else if (GET_CODE (tmp) == PLUS &&
10649 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10653 if (GET_CODE (XEXP (tmp, 0)) != REG)
10656 x = INTVAL (XEXP (tmp, 1));
10657 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10661 /* Fall through. Must be [reg+reg]. */
10664 && GET_CODE (tmp) == AND
10665 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10666 && INTVAL (XEXP (tmp, 1)) == -16)
10667 tmp = XEXP (tmp, 0);
10668 if (GET_CODE (tmp) == REG)
10669 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10670 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
10672 if (REGNO (XEXP (tmp, 0)) == 0)
10673 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10674 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10676 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10677 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10685 if (GET_CODE (x) == REG)
10686 fprintf (file, "%s", reg_names[REGNO (x)]);
10687 else if (GET_CODE (x) == MEM)
10689 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10690 know the width from the mode. */
10691 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10692 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10693 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10694 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10695 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10696 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10698 output_address (XEXP (x, 0));
10701 output_addr_const (file, x);
10705 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10709 output_operand_lossage ("invalid %%xn code");
10713 /* Print the address of an operand. */
10716 print_operand_address (FILE *file, rtx x)
10718 if (GET_CODE (x) == REG)
10719 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10720 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10721 || GET_CODE (x) == LABEL_REF)
10723 output_addr_const (file, x);
10724 if (small_data_operand (x, GET_MODE (x)))
10725 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10726 reg_names[SMALL_DATA_REG]);
10727 else if (TARGET_TOC)
10730 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10732 if (REGNO (XEXP (x, 0)) == 0)
10733 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10734 reg_names[ REGNO (XEXP (x, 0)) ]);
10736 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10737 reg_names[ REGNO (XEXP (x, 1)) ]);
10739 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10740 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10741 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10743 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10744 && CONSTANT_P (XEXP (x, 1)))
10746 output_addr_const (file, XEXP (x, 1));
10747 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10751 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10752 && CONSTANT_P (XEXP (x, 1)))
10754 fprintf (file, "lo16(");
10755 output_addr_const (file, XEXP (x, 1));
10756 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10759 else if (legitimate_constant_pool_address_p (x))
10761 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10763 rtx contains_minus = XEXP (x, 1);
10767 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10768 turn it into (sym) for output_addr_const. */
10769 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10770 contains_minus = XEXP (contains_minus, 0);
10772 minus = XEXP (contains_minus, 0);
10773 symref = XEXP (minus, 0);
10774 XEXP (contains_minus, 0) = symref;
10779 name = XSTR (symref, 0);
10780 newname = alloca (strlen (name) + sizeof ("@toc"));
10781 strcpy (newname, name);
10782 strcat (newname, "@toc");
10783 XSTR (symref, 0) = newname;
10785 output_addr_const (file, XEXP (x, 1));
10787 XSTR (symref, 0) = name;
10788 XEXP (contains_minus, 0) = minus;
10791 output_addr_const (file, XEXP (x, 1));
10793 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10799 /* Target hook for assembling integer objects. The PowerPC version has
10800 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10801 is defined. It also needs to handle DI-mode objects on 64-bit
10805 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10807 #ifdef RELOCATABLE_NEEDS_FIXUP
10808 /* Special handling for SI values. */
10809 if (size == 4 && aligned_p)
10811 extern int in_toc_section (void);
10812 static int recurse = 0;
10814 /* For -mrelocatable, we mark all addresses that need to be fixed up
10815 in the .fixup section. */
10816 if (TARGET_RELOCATABLE
10817 && !in_toc_section ()
10818 && !in_text_section ()
10819 && !in_unlikely_text_section ()
10821 && GET_CODE (x) != CONST_INT
10822 && GET_CODE (x) != CONST_DOUBLE
10828 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10830 ASM_OUTPUT_LABEL (asm_out_file, buf);
10831 fprintf (asm_out_file, "\t.long\t(");
10832 output_addr_const (asm_out_file, x);
10833 fprintf (asm_out_file, ")@fixup\n");
10834 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10835 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10836 fprintf (asm_out_file, "\t.long\t");
10837 assemble_name (asm_out_file, buf);
10838 fprintf (asm_out_file, "\n\t.previous\n");
10842 /* Remove initial .'s to turn a -mcall-aixdesc function
10843 address into the address of the descriptor, not the function
10845 else if (GET_CODE (x) == SYMBOL_REF
10846 && XSTR (x, 0)[0] == '.'
10847 && DEFAULT_ABI == ABI_AIX)
10849 const char *name = XSTR (x, 0);
10850 while (*name == '.')
10853 fprintf (asm_out_file, "\t.long\t%s\n", name);
10857 #endif /* RELOCATABLE_NEEDS_FIXUP */
10858 return default_assemble_integer (x, size, aligned_p);
10861 #ifdef HAVE_GAS_HIDDEN
10862 /* Emit an assembler directive to set symbol visibility for DECL to
10863 VISIBILITY_TYPE. */
10866 rs6000_assemble_visibility (tree decl, int vis)
10868 /* Functions need to have their entry point symbol visibility set as
10869 well as their descriptor symbol visibility. */
10870 if (DEFAULT_ABI == ABI_AIX
10872 && TREE_CODE (decl) == FUNCTION_DECL)
10874 static const char * const visibility_types[] = {
10875 NULL, "internal", "hidden", "protected"
10878 const char *name, *type;
10880 name = ((* targetm.strip_name_encoding)
10881 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10882 type = visibility_types[vis];
10884 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10885 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10888 default_assemble_visibility (decl, vis);
10893 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10895 /* Reversal of FP compares takes care -- an ordered compare
10896 becomes an unordered compare and vice versa. */
10897 if (mode == CCFPmode
10898 && (!flag_finite_math_only
10899 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10900 || code == UNEQ || code == LTGT))
10901 return reverse_condition_maybe_unordered (code);
10903 return reverse_condition (code);
10906 /* Generate a compare for CODE. Return a brand-new rtx that
10907 represents the result of the compare. */
10910 rs6000_generate_compare (enum rtx_code code)
10912 enum machine_mode comp_mode;
10913 rtx compare_result;
10915 if (rs6000_compare_fp_p)
10916 comp_mode = CCFPmode;
10917 else if (code == GTU || code == LTU
10918 || code == GEU || code == LEU)
10919 comp_mode = CCUNSmode;
10921 comp_mode = CCmode;
10923 /* First, the compare. */
10924 compare_result = gen_reg_rtx (comp_mode);
10926 /* SPE FP compare instructions on the GPRs. Yuck! */
10927 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10928 && rs6000_compare_fp_p)
10930 rtx cmp, or1, or2, or_result, compare_result2;
10931 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10933 if (op_mode == VOIDmode)
10934 op_mode = GET_MODE (rs6000_compare_op1);
10936 /* Note: The E500 comparison instructions set the GT bit (x +
10937 1), on success. This explains the mess. */
10941 case EQ: case UNEQ: case NE: case LTGT:
10942 if (op_mode == SFmode)
10943 cmp = flag_finite_math_only
10944 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10945 rs6000_compare_op1)
10946 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10947 rs6000_compare_op1);
10948 else if (op_mode == DFmode)
10949 cmp = flag_finite_math_only
10950 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10951 rs6000_compare_op1)
10952 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10953 rs6000_compare_op1);
10956 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10957 if (op_mode == SFmode)
10958 cmp = flag_finite_math_only
10959 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10960 rs6000_compare_op1)
10961 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10962 rs6000_compare_op1);
10963 else if (op_mode == DFmode)
10964 cmp = flag_finite_math_only
10965 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10966 rs6000_compare_op1)
10967 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10968 rs6000_compare_op1);
10971 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10972 if (op_mode == SFmode)
10973 cmp = flag_finite_math_only
10974 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10975 rs6000_compare_op1)
10976 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10977 rs6000_compare_op1);
10978 else if (op_mode == DFmode)
10979 cmp = flag_finite_math_only
10980 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10981 rs6000_compare_op1)
10982 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10983 rs6000_compare_op1);
10990 /* Synthesize LE and GE from LT/GT || EQ. */
10991 if (code == LE || code == GE || code == LEU || code == GEU)
10997 case LE: code = LT; break;
10998 case GE: code = GT; break;
10999 case LEU: code = LT; break;
11000 case GEU: code = GT; break;
11004 or1 = gen_reg_rtx (SImode);
11005 or2 = gen_reg_rtx (SImode);
11006 or_result = gen_reg_rtx (CCEQmode);
11007 compare_result2 = gen_reg_rtx (CCFPmode);
11010 if (op_mode == SFmode)
11011 cmp = flag_finite_math_only
11012 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11013 rs6000_compare_op1)
11014 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11015 rs6000_compare_op1);
11016 else if (op_mode == DFmode)
11017 cmp = flag_finite_math_only
11018 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11019 rs6000_compare_op1)
11020 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11021 rs6000_compare_op1);
11025 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
11026 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
11028 /* OR them together. */
11029 cmp = gen_rtx_SET (VOIDmode, or_result,
11030 gen_rtx_COMPARE (CCEQmode,
11031 gen_rtx_IOR (SImode, or1, or2),
11033 compare_result = or_result;
11038 if (code == NE || code == LTGT)
11047 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11048 gen_rtx_COMPARE (comp_mode,
11049 rs6000_compare_op0,
11050 rs6000_compare_op1)));
11052 /* Some kinds of FP comparisons need an OR operation;
11053 under flag_finite_math_only we don't bother. */
11054 if (rs6000_compare_fp_p
11055 && ! flag_finite_math_only
11056 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11057 && (code == LE || code == GE
11058 || code == UNEQ || code == LTGT
11059 || code == UNGT || code == UNLT))
11061 enum rtx_code or1, or2;
11062 rtx or1_rtx, or2_rtx, compare2_rtx;
11063 rtx or_result = gen_reg_rtx (CCEQmode);
11067 case LE: or1 = LT; or2 = EQ; break;
11068 case GE: or1 = GT; or2 = EQ; break;
11069 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11070 case LTGT: or1 = LT; or2 = GT; break;
11071 case UNGT: or1 = UNORDERED; or2 = GT; break;
11072 case UNLT: or1 = UNORDERED; or2 = LT; break;
11075 validate_condition_mode (or1, comp_mode);
11076 validate_condition_mode (or2, comp_mode);
11077 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11078 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11079 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11080 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11082 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11084 compare_result = or_result;
11088 validate_condition_mode (code, GET_MODE (compare_result));
11090 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11094 /* Emit the RTL for an sCOND pattern. */
11097 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11100 enum machine_mode op_mode;
11101 enum rtx_code cond_code;
11103 condition_rtx = rs6000_generate_compare (code);
11104 cond_code = GET_CODE (condition_rtx);
11106 if (TARGET_E500 && rs6000_compare_fp_p
11107 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11111 PUT_MODE (condition_rtx, SImode);
11112 t = XEXP (condition_rtx, 0);
11114 if (cond_code != NE && cond_code != EQ)
11117 if (cond_code == NE)
11118 emit_insn (gen_e500_flip_eq_bit (t, t));
11120 emit_insn (gen_move_from_CR_eq_bit (result, t));
11124 if (cond_code == NE
11125 || cond_code == GE || cond_code == LE
11126 || cond_code == GEU || cond_code == LEU
11127 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11129 rtx not_result = gen_reg_rtx (CCEQmode);
11130 rtx not_op, rev_cond_rtx;
11131 enum machine_mode cc_mode;
11133 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11135 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11136 SImode, XEXP (condition_rtx, 0), const0_rtx);
11137 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11138 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11139 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11142 op_mode = GET_MODE (rs6000_compare_op0);
11143 if (op_mode == VOIDmode)
11144 op_mode = GET_MODE (rs6000_compare_op1);
11146 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11148 PUT_MODE (condition_rtx, DImode);
11149 convert_move (result, condition_rtx, 0);
11153 PUT_MODE (condition_rtx, SImode);
11154 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11158 /* Emit a branch of kind CODE to location LOC. */
11161 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11163 rtx condition_rtx, loc_ref;
11165 condition_rtx = rs6000_generate_compare (code);
11166 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11167 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11168 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11169 loc_ref, pc_rtx)));
11172 /* Return the string to output a conditional branch to LABEL, which is
11173 the operand number of the label, or -1 if the branch is really a
11174 conditional return.
11176 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11177 condition code register and its mode specifies what kind of
11178 comparison we made.
11180 REVERSED is nonzero if we should reverse the sense of the comparison.
11182 INSN is the insn. */
11185 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11187 static char string[64];
11188 enum rtx_code code = GET_CODE (op);
11189 rtx cc_reg = XEXP (op, 0);
11190 enum machine_mode mode = GET_MODE (cc_reg);
11191 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11192 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11193 int really_reversed = reversed ^ need_longbranch;
11199 validate_condition_mode (code, mode);
11201 /* Work out which way this really branches. We could use
11202 reverse_condition_maybe_unordered here always but this
11203 makes the resulting assembler clearer. */
11204 if (really_reversed)
11206 /* Reversal of FP compares takes care -- an ordered compare
11207 becomes an unordered compare and vice versa. */
11208 if (mode == CCFPmode)
11209 code = reverse_condition_maybe_unordered (code);
11211 code = reverse_condition (code);
11214 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11216 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11219 /* Opposite of GT. */
11221 else if (code == NE)
11229 /* Not all of these are actually distinct opcodes, but
11230 we distinguish them for clarity of the resulting assembler. */
11231 case NE: case LTGT:
11232 ccode = "ne"; break;
11233 case EQ: case UNEQ:
11234 ccode = "eq"; break;
11236 ccode = "ge"; break;
11237 case GT: case GTU: case UNGT:
11238 ccode = "gt"; break;
11240 ccode = "le"; break;
11241 case LT: case LTU: case UNLT:
11242 ccode = "lt"; break;
11243 case UNORDERED: ccode = "un"; break;
11244 case ORDERED: ccode = "nu"; break;
11245 case UNGE: ccode = "nl"; break;
11246 case UNLE: ccode = "ng"; break;
11251 /* Maybe we have a guess as to how likely the branch is.
11252 The old mnemonics don't have a way to specify this information. */
11254 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11255 if (note != NULL_RTX)
11257 /* PROB is the difference from 50%. */
11258 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11260 /* Only hint for highly probable/improbable branches on newer
11261 cpus as static prediction overrides processor dynamic
11262 prediction. For older cpus we may as well always hint, but
11263 assume not taken for branches that are very close to 50% as a
11264 mispredicted taken branch is more expensive than a
11265 mispredicted not-taken branch. */
11266 if (rs6000_always_hint
11267 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11269 if (abs (prob) > REG_BR_PROB_BASE / 20
11270 && ((prob > 0) ^ need_longbranch))
11278 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11280 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11282 /* We need to escape any '%' characters in the reg_names string.
11283 Assume they'd only be the first character.... */
11284 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11286 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11290 /* If the branch distance was too far, we may have to use an
11291 unconditional branch to go the distance. */
11292 if (need_longbranch)
11293 s += sprintf (s, ",$+8\n\tb %s", label);
11295 s += sprintf (s, ",%s", label);
11301 /* Return the string to flip the EQ bit on a CR. */
11303 output_e500_flip_eq_bit (rtx dst, rtx src)
11305 static char string[64];
11308 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
11309 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
11313 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
11314 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
11316 sprintf (string, "crnot %d,%d", a, b);
11320 /* Return insn index for the vector compare instruction for given CODE,
11321 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11325 get_vec_cmp_insn (enum rtx_code code,
11326 enum machine_mode dest_mode,
11327 enum machine_mode op_mode)
11329 if (!TARGET_ALTIVEC)
11330 return INSN_NOT_AVAILABLE;
11335 if (dest_mode == V16QImode && op_mode == V16QImode)
11336 return UNSPEC_VCMPEQUB;
11337 if (dest_mode == V8HImode && op_mode == V8HImode)
11338 return UNSPEC_VCMPEQUH;
11339 if (dest_mode == V4SImode && op_mode == V4SImode)
11340 return UNSPEC_VCMPEQUW;
11341 if (dest_mode == V4SImode && op_mode == V4SFmode)
11342 return UNSPEC_VCMPEQFP;
11345 if (dest_mode == V4SImode && op_mode == V4SFmode)
11346 return UNSPEC_VCMPGEFP;
11348 if (dest_mode == V16QImode && op_mode == V16QImode)
11349 return UNSPEC_VCMPGTSB;
11350 if (dest_mode == V8HImode && op_mode == V8HImode)
11351 return UNSPEC_VCMPGTSH;
11352 if (dest_mode == V4SImode && op_mode == V4SImode)
11353 return UNSPEC_VCMPGTSW;
11354 if (dest_mode == V4SImode && op_mode == V4SFmode)
11355 return UNSPEC_VCMPGTFP;
11358 if (dest_mode == V16QImode && op_mode == V16QImode)
11359 return UNSPEC_VCMPGTUB;
11360 if (dest_mode == V8HImode && op_mode == V8HImode)
11361 return UNSPEC_VCMPGTUH;
11362 if (dest_mode == V4SImode && op_mode == V4SImode)
11363 return UNSPEC_VCMPGTUW;
11368 return INSN_NOT_AVAILABLE;
11371 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11372 DMODE is expected destination mode. This is a recursive function. */
11375 rs6000_emit_vector_compare (enum rtx_code rcode,
11377 enum machine_mode dmode)
11381 enum machine_mode dest_mode;
11382 enum machine_mode op_mode = GET_MODE (op1);
11384 #ifdef ENABLE_CHECKING
11385 if (!TARGET_ALTIVEC)
11388 if (GET_MODE (op0) != GET_MODE (op1))
11392 /* Floating point vector compare instructions uses destination V4SImode.
11393 Move destination to appropriate mode later. */
11394 if (dmode == V4SFmode)
11395 dest_mode = V4SImode;
11399 mask = gen_reg_rtx (dest_mode);
11400 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11402 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11404 bool swap_operands = false;
11405 bool try_again = false;
11410 swap_operands = true;
11415 swap_operands = true;
11419 /* Treat A != B as ~(A==B). */
11421 enum insn_code nor_code;
11422 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11425 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11426 if (nor_code == CODE_FOR_nothing)
11428 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11430 if (dmode != dest_mode)
11432 rtx temp = gen_reg_rtx (dest_mode);
11433 convert_move (temp, mask, 0);
11443 /* Try GT/GTU/LT/LTU OR EQ */
11446 enum insn_code ior_code;
11447 enum rtx_code new_code;
11451 else if (rcode == GEU)
11453 else if (rcode == LE)
11455 else if (rcode == LEU)
11460 c_rtx = rs6000_emit_vector_compare (new_code,
11461 op0, op1, dest_mode);
11462 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11465 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11466 if (ior_code == CODE_FOR_nothing)
11468 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11469 if (dmode != dest_mode)
11471 rtx temp = gen_reg_rtx (dest_mode);
11472 convert_move (temp, mask, 0);
11484 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11485 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11486 /* You only get two chances. */
11499 emit_insn (gen_rtx_fmt_ee (SET,
11502 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11503 gen_rtvec (2, op0, op1),
11505 if (dmode != dest_mode)
11507 rtx temp = gen_reg_rtx (dest_mode);
11508 convert_move (temp, mask, 0);
11514 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11515 valid insn doesn exist for given mode. */
11518 get_vsel_insn (enum machine_mode mode)
11523 return UNSPEC_VSEL4SI;
11526 return UNSPEC_VSEL4SF;
11529 return UNSPEC_VSEL8HI;
11532 return UNSPEC_VSEL16QI;
11535 return INSN_NOT_AVAILABLE;
11538 return INSN_NOT_AVAILABLE;
11541 /* Emit vector select insn where DEST is destination using
11542 operands OP1, OP2 and MASK. */
11545 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11548 enum machine_mode dest_mode = GET_MODE (dest);
11549 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11551 temp = gen_reg_rtx (dest_mode);
11553 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
11554 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11555 gen_rtvec (3, op1, op2, mask),
11558 emit_move_insn (dest, temp);
11562 /* Emit vector conditional expression.
11563 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11564 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11567 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11568 rtx cond, rtx cc_op0, rtx cc_op1)
11570 enum machine_mode dest_mode = GET_MODE (dest);
11571 enum rtx_code rcode = GET_CODE (cond);
11574 if (!TARGET_ALTIVEC)
11577 /* Get the vector mask for the given relational operations. */
11578 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11580 rs6000_emit_vector_select (dest, op1, op2, mask);
11585 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11586 operands of the last comparison is nonzero/true, FALSE_COND if it
11587 is zero/false. Return 0 if the hardware has no such operation. */
11590 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11592 enum rtx_code code = GET_CODE (op);
11593 rtx op0 = rs6000_compare_op0;
11594 rtx op1 = rs6000_compare_op1;
11595 REAL_VALUE_TYPE c1;
11596 enum machine_mode compare_mode = GET_MODE (op0);
11597 enum machine_mode result_mode = GET_MODE (dest);
11599 bool is_against_zero;
11601 /* These modes should always match. */
11602 if (GET_MODE (op1) != compare_mode
11603 /* In the isel case however, we can use a compare immediate, so
11604 op1 may be a small constant. */
11605 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11607 if (GET_MODE (true_cond) != result_mode)
11609 if (GET_MODE (false_cond) != result_mode)
11612 /* First, work out if the hardware can do this at all, or
11613 if it's too slow.... */
11614 if (! rs6000_compare_fp_p)
11617 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11620 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11621 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11624 is_against_zero = op1 == CONST0_RTX (compare_mode);
11626 /* A floating-point subtract might overflow, underflow, or produce
11627 an inexact result, thus changing the floating-point flags, so it
11628 can't be generated if we care about that. It's safe if one side
11629 of the construct is zero, since then no subtract will be
11631 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11632 && flag_trapping_math && ! is_against_zero)
11635 /* Eliminate half of the comparisons by switching operands, this
11636 makes the remaining code simpler. */
11637 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11638 || code == LTGT || code == LT || code == UNLE)
11640 code = reverse_condition_maybe_unordered (code);
11642 true_cond = false_cond;
11646 /* UNEQ and LTGT take four instructions for a comparison with zero,
11647 it'll probably be faster to use a branch here too. */
11648 if (code == UNEQ && HONOR_NANS (compare_mode))
11651 if (GET_CODE (op1) == CONST_DOUBLE)
11652 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11654 /* We're going to try to implement comparisons by performing
11655 a subtract, then comparing against zero. Unfortunately,
11656 Inf - Inf is NaN which is not zero, and so if we don't
11657 know that the operand is finite and the comparison
11658 would treat EQ different to UNORDERED, we can't do it. */
11659 if (HONOR_INFINITIES (compare_mode)
11660 && code != GT && code != UNGE
11661 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11662 /* Constructs of the form (a OP b ? a : b) are safe. */
11663 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11664 || (! rtx_equal_p (op0, true_cond)
11665 && ! rtx_equal_p (op1, true_cond))))
11668 /* At this point we know we can use fsel. */
11670 /* Reduce the comparison to a comparison against zero. */
11671 if (! is_against_zero)
11673 temp = gen_reg_rtx (compare_mode);
11674 emit_insn (gen_rtx_SET (VOIDmode, temp,
11675 gen_rtx_MINUS (compare_mode, op0, op1)));
11677 op1 = CONST0_RTX (compare_mode);
11680 /* If we don't care about NaNs we can reduce some of the comparisons
11681 down to faster ones. */
11682 if (! HONOR_NANS (compare_mode))
11688 true_cond = false_cond;
11701 /* Now, reduce everything down to a GE. */
11708 temp = gen_reg_rtx (compare_mode);
11709 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11714 temp = gen_reg_rtx (compare_mode);
11715 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11720 temp = gen_reg_rtx (compare_mode);
11721 emit_insn (gen_rtx_SET (VOIDmode, temp,
11722 gen_rtx_NEG (compare_mode,
11723 gen_rtx_ABS (compare_mode, op0))));
11728 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11729 temp = gen_reg_rtx (result_mode);
11730 emit_insn (gen_rtx_SET (VOIDmode, temp,
11731 gen_rtx_IF_THEN_ELSE (result_mode,
11732 gen_rtx_GE (VOIDmode,
11734 true_cond, false_cond)));
11735 false_cond = true_cond;
11738 temp = gen_reg_rtx (compare_mode);
11739 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11744 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11745 temp = gen_reg_rtx (result_mode);
11746 emit_insn (gen_rtx_SET (VOIDmode, temp,
11747 gen_rtx_IF_THEN_ELSE (result_mode,
11748 gen_rtx_GE (VOIDmode,
11750 true_cond, false_cond)));
11751 true_cond = false_cond;
11754 temp = gen_reg_rtx (compare_mode);
11755 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11763 emit_insn (gen_rtx_SET (VOIDmode, dest,
11764 gen_rtx_IF_THEN_ELSE (result_mode,
11765 gen_rtx_GE (VOIDmode,
11767 true_cond, false_cond)));
11771 /* Same as above, but for ints (isel). */
11774 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11776 rtx condition_rtx, cr;
11778 /* All isel implementations thus far are 32-bits. */
11779 if (GET_MODE (rs6000_compare_op0) != SImode)
11782 /* We still have to do the compare, because isel doesn't do a
11783 compare, it just looks at the CRx bits set by a previous compare
11785 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11786 cr = XEXP (condition_rtx, 0);
11788 if (GET_MODE (cr) == CCmode)
11789 emit_insn (gen_isel_signed (dest, condition_rtx,
11790 true_cond, false_cond, cr));
11792 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11793 true_cond, false_cond, cr));
11799 output_isel (rtx *operands)
11801 enum rtx_code code;
11803 code = GET_CODE (operands[1]);
11804 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11806 PUT_CODE (operands[1], reverse_condition (code));
11807 return "isel %0,%3,%2,%j1";
11810 return "isel %0,%2,%3,%j1";
11814 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11816 enum machine_mode mode = GET_MODE (op0);
11820 if (code == SMAX || code == SMIN)
11825 if (code == SMAX || code == UMAX)
11826 target = emit_conditional_move (dest, c, op0, op1, mode,
11827 op0, op1, mode, 0);
11829 target = emit_conditional_move (dest, c, op0, op1, mode,
11830 op1, op0, mode, 0);
11831 if (target == NULL_RTX)
11833 if (target != dest)
11834 emit_move_insn (dest, target);
11837 /* Emit instructions to move SRC to DST. Called by splitters for
11838 multi-register moves. It will emit at most one instruction for
11839 each register that is accessed; that is, it won't emit li/lis pairs
11840 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11844 rs6000_split_multireg_move (rtx dst, rtx src)
11846 /* The register number of the first register being moved. */
11848 /* The mode that is to be moved. */
11849 enum machine_mode mode;
11850 /* The mode that the move is being done in, and its size. */
11851 enum machine_mode reg_mode;
11853 /* The number of registers that will be moved. */
11856 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
11857 mode = GET_MODE (dst);
11858 nregs = HARD_REGNO_NREGS (reg, mode);
11859 if (FP_REGNO_P (reg))
11861 else if (ALTIVEC_REGNO_P (reg))
11862 reg_mode = V16QImode;
11864 reg_mode = word_mode;
11865 reg_mode_size = GET_MODE_SIZE (reg_mode);
11867 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
11870 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11872 /* Move register range backwards, if we might have destructive
11875 for (i = nregs - 1; i >= 0; i--)
11876 emit_insn (gen_rtx_SET (VOIDmode,
11877 simplify_gen_subreg (reg_mode, dst, mode,
11878 i * reg_mode_size),
11879 simplify_gen_subreg (reg_mode, src, mode,
11880 i * reg_mode_size)));
11886 bool used_update = false;
11888 if (MEM_P (src) && INT_REGNO_P (reg))
11892 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11893 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
11896 breg = XEXP (XEXP (src, 0), 0);
11897 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11898 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11899 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
11900 emit_insn (TARGET_32BIT
11901 ? gen_addsi3 (breg, breg, delta_rtx)
11902 : gen_adddi3 (breg, breg, delta_rtx));
11903 src = gen_rtx_MEM (mode, breg);
11905 else if (! offsettable_memref_p (src))
11907 rtx newsrc, basereg;
11908 basereg = gen_rtx_REG (Pmode, reg);
11909 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11910 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11911 MEM_COPY_ATTRIBUTES (newsrc, src);
11915 breg = XEXP (src, 0);
11916 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11917 breg = XEXP (breg, 0);
11919 /* If the base register we are using to address memory is
11920 also a destination reg, then change that register last. */
11922 && REGNO (breg) >= REGNO (dst)
11923 && REGNO (breg) < REGNO (dst) + nregs)
11924 j = REGNO (breg) - REGNO (dst);
11927 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11931 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11932 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11935 breg = XEXP (XEXP (dst, 0), 0);
11936 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11937 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11938 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
11940 /* We have to update the breg before doing the store.
11941 Use store with update, if available. */
11945 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11946 emit_insn (TARGET_32BIT
11947 ? (TARGET_POWERPC64
11948 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11949 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11950 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
11951 used_update = true;
11954 emit_insn (TARGET_32BIT
11955 ? gen_addsi3 (breg, breg, delta_rtx)
11956 : gen_adddi3 (breg, breg, delta_rtx));
11957 dst = gen_rtx_MEM (mode, breg);
11959 else if (! offsettable_memref_p (dst))
11963 for (i = 0; i < nregs; i++)
11965 /* Calculate index to next subword. */
11970 /* If compiler already emitted move of first word by
11971 store with update, no need to do anything. */
11972 if (j == 0 && used_update)
11975 emit_insn (gen_rtx_SET (VOIDmode,
11976 simplify_gen_subreg (reg_mode, dst, mode,
11977 j * reg_mode_size),
11978 simplify_gen_subreg (reg_mode, src, mode,
11979 j * reg_mode_size)));
11985 /* This page contains routines that are used to determine what the
11986 function prologue and epilogue code will do and write them out. */
11988 /* Return the first fixed-point register that is required to be
11989 saved. 32 if none. */
11992 first_reg_to_save (void)
11996 /* Find lowest numbered live register. */
11997 for (first_reg = 13; first_reg <= 31; first_reg++)
11998 if (regs_ever_live[first_reg]
11999 && (! call_used_regs[first_reg]
12000 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12001 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12002 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12003 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12008 && current_function_uses_pic_offset_table
12009 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12010 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12016 /* Similar, for FP regs. */
12019 first_fp_reg_to_save (void)
12023 /* Find lowest numbered live register. */
12024 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12025 if (regs_ever_live[first_reg])
12031 /* Similar, for AltiVec regs. */
12034 first_altivec_reg_to_save (void)
12038 /* Stack frame remains as is unless we are in AltiVec ABI. */
12039 if (! TARGET_ALTIVEC_ABI)
12040 return LAST_ALTIVEC_REGNO + 1;
12042 /* Find lowest numbered live register. */
12043 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12044 if (regs_ever_live[i])
12050 /* Return a 32-bit mask of the AltiVec registers we need to set in
12051 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12052 the 32-bit word is 0. */
12054 static unsigned int
12055 compute_vrsave_mask (void)
12057 unsigned int i, mask = 0;
12059 /* First, find out if we use _any_ altivec registers. */
12060 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12061 if (regs_ever_live[i])
12062 mask |= ALTIVEC_REG_BIT (i);
12067 /* Next, remove the argument registers from the set. These must
12068 be in the VRSAVE mask set by the caller, so we don't need to add
12069 them in again. More importantly, the mask we compute here is
12070 used to generate CLOBBERs in the set_vrsave insn, and we do not
12071 wish the argument registers to die. */
12072 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12073 mask &= ~ALTIVEC_REG_BIT (i);
12075 /* Similarly, remove the return value from the set. */
12078 diddle_return_value (is_altivec_return_reg, &yes);
12080 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12086 /* For a very restricted set of circumstances, we can cut down the
12087 size of prologs/epilogs by calling our own save/restore-the-world
12091 compute_save_world_info(rs6000_stack_t *info_ptr)
12093 info_ptr->world_save_p =
12094 (DEFAULT_ABI == ABI_DARWIN)
12095 && ! (current_function_calls_setjmp && flag_exceptions)
12096 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12097 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12098 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12099 && info_ptr->cr_save_p;
12101 /* This will not work in conjunction with sibcalls. Make sure there
12102 are none. (This check is expensive, but seldom executed.) */
12103 if ( info_ptr->world_save_p )
12106 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12107 if ( GET_CODE (insn) == CALL_INSN
12108 && SIBLING_CALL_P (insn))
12110 info_ptr->world_save_p = 0;
12115 if (info_ptr->world_save_p)
12117 /* Even if we're not touching VRsave, make sure there's room on the
12118 stack for it, if it looks like we're calling SAVE_WORLD, which
12119 will attempt to save it. */
12120 info_ptr->vrsave_size = 4;
12122 /* "Save" the VRsave register too if we're saving the world. */
12123 if (info_ptr->vrsave_mask == 0)
12124 info_ptr->vrsave_mask = compute_vrsave_mask ();
12126 /* Because the Darwin register save/restore routines only handle
12127 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12128 check and abort if there's something worng. */
12129 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
12130 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
12138 is_altivec_return_reg (rtx reg, void *xyes)
12140 bool *yes = (bool *) xyes;
12141 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12146 /* Calculate the stack information for the current function. This is
12147 complicated by having two separate calling sequences, the AIX calling
12148 sequence and the V.4 calling sequence.
12150 AIX (and Darwin/Mac OS X) stack frames look like:
12152 SP----> +---------------------------------------+
12153 | back chain to caller | 0 0
12154 +---------------------------------------+
12155 | saved CR | 4 8 (8-11)
12156 +---------------------------------------+
12158 +---------------------------------------+
12159 | reserved for compilers | 12 24
12160 +---------------------------------------+
12161 | reserved for binders | 16 32
12162 +---------------------------------------+
12163 | saved TOC pointer | 20 40
12164 +---------------------------------------+
12165 | Parameter save area (P) | 24 48
12166 +---------------------------------------+
12167 | Alloca space (A) | 24+P etc.
12168 +---------------------------------------+
12169 | Local variable space (L) | 24+P+A
12170 +---------------------------------------+
12171 | Float/int conversion temporary (X) | 24+P+A+L
12172 +---------------------------------------+
12173 | Save area for AltiVec registers (W) | 24+P+A+L+X
12174 +---------------------------------------+
12175 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12176 +---------------------------------------+
12177 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12178 +---------------------------------------+
12179 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12180 +---------------------------------------+
12181 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12182 +---------------------------------------+
12183 old SP->| back chain to caller's caller |
12184 +---------------------------------------+
12186 The required alignment for AIX configurations is two words (i.e., 8
12190 V.4 stack frames look like:
12192 SP----> +---------------------------------------+
12193 | back chain to caller | 0
12194 +---------------------------------------+
12195 | caller's saved LR | 4
12196 +---------------------------------------+
12197 | Parameter save area (P) | 8
12198 +---------------------------------------+
12199 | Alloca space (A) | 8+P
12200 +---------------------------------------+
12201 | Varargs save area (V) | 8+P+A
12202 +---------------------------------------+
12203 | Local variable space (L) | 8+P+A+V
12204 +---------------------------------------+
12205 | Float/int conversion temporary (X) | 8+P+A+V+L
12206 +---------------------------------------+
12207 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12208 +---------------------------------------+
12209 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12210 +---------------------------------------+
12211 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12212 +---------------------------------------+
12213 | SPE: area for 64-bit GP registers |
12214 +---------------------------------------+
12215 | SPE alignment padding |
12216 +---------------------------------------+
12217 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12218 +---------------------------------------+
12219 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12220 +---------------------------------------+
12221 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12222 +---------------------------------------+
12223 old SP->| back chain to caller's caller |
12224 +---------------------------------------+
12226 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12227 given. (But note below and in sysv4.h that we require only 8 and
12228 may round up the size of our stack frame anyways. The historical
12229 reason is early versions of powerpc-linux which didn't properly
12230 align the stack at program startup. A happy side-effect is that
12231 -mno-eabi libraries can be used with -meabi programs.)
12233 The EABI configuration defaults to the V.4 layout. However,
12234 the stack alignment requirements may differ. If -mno-eabi is not
12235 given, the required stack alignment is 8 bytes; if -mno-eabi is
12236 given, the required alignment is 16 bytes. (But see V.4 comment
12239 #ifndef ABI_STACK_BOUNDARY
12240 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12243 static rs6000_stack_t *
12244 rs6000_stack_info (void)
12246 static rs6000_stack_t info, zero_info;
12247 rs6000_stack_t *info_ptr = &info;
12248 int reg_size = TARGET_32BIT ? 4 : 8;
12251 HOST_WIDE_INT non_fixed_size;
12253 /* Zero all fields portably. */
12258 /* Cache value so we don't rescan instruction chain over and over. */
12259 if (cfun->machine->insn_chain_scanned_p == 0)
12261 cfun->machine->insn_chain_scanned_p = 1;
12262 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
12266 /* Select which calling sequence. */
12267 info_ptr->abi = DEFAULT_ABI;
12269 /* Calculate which registers need to be saved & save area size. */
12270 info_ptr->first_gp_reg_save = first_reg_to_save ();
12271 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12272 even if it currently looks like we won't. */
12273 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12274 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12275 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12276 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12277 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12279 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12281 /* For the SPE, we have an additional upper 32-bits on each GPR.
12282 Ideally we should save the entire 64-bits only when the upper
12283 half is used in SIMD instructions. Since we only record
12284 registers live (not the size they are used in), this proves
12285 difficult because we'd have to traverse the instruction chain at
12286 the right time, taking reload into account. This is a real pain,
12287 so we opt to save the GPRs in 64-bits always if but one register
12288 gets used in 64-bits. Otherwise, all the registers in the frame
12289 get saved in 32-bits.
12291 So... since when we save all GPRs (except the SP) in 64-bits, the
12292 traditional GP save area will be empty. */
12293 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12294 info_ptr->gp_size = 0;
12296 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12297 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12299 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12300 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12301 - info_ptr->first_altivec_reg_save);
12303 /* Does this function call anything? */
12304 info_ptr->calls_p = (! current_function_is_leaf
12305 || cfun->machine->ra_needs_full_frame);
12307 /* Determine if we need to save the link register. */
12308 if (rs6000_ra_ever_killed ()
12309 || (DEFAULT_ABI == ABI_AIX
12310 && current_function_profile
12311 && !TARGET_PROFILE_KERNEL)
12312 #ifdef TARGET_RELOCATABLE
12313 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12315 || (info_ptr->first_fp_reg_save != 64
12316 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12317 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12318 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12319 || (DEFAULT_ABI == ABI_DARWIN
12321 && current_function_uses_pic_offset_table)
12322 || info_ptr->calls_p)
12324 info_ptr->lr_save_p = 1;
12325 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12328 /* Determine if we need to save the condition code registers. */
12329 if (regs_ever_live[CR2_REGNO]
12330 || regs_ever_live[CR3_REGNO]
12331 || regs_ever_live[CR4_REGNO])
12333 info_ptr->cr_save_p = 1;
12334 if (DEFAULT_ABI == ABI_V4)
12335 info_ptr->cr_size = reg_size;
12338 /* If the current function calls __builtin_eh_return, then we need
12339 to allocate stack space for registers that will hold data for
12340 the exception handler. */
12341 if (current_function_calls_eh_return)
12344 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12347 /* SPE saves EH registers in 64-bits. */
12348 ehrd_size = i * (TARGET_SPE_ABI
12349 && info_ptr->spe_64bit_regs_used != 0
12350 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12355 /* Determine various sizes. */
12356 info_ptr->reg_size = reg_size;
12357 info_ptr->fixed_size = RS6000_SAVE_AREA;
12358 info_ptr->varargs_size = RS6000_VARARGS_AREA;
12359 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12360 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12361 TARGET_ALTIVEC ? 16 : 8);
12363 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12364 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12366 info_ptr->spe_gp_size = 0;
12368 if (TARGET_ALTIVEC_ABI)
12369 info_ptr->vrsave_mask = compute_vrsave_mask ();
12371 info_ptr->vrsave_mask = 0;
12373 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12374 info_ptr->vrsave_size = 4;
12376 info_ptr->vrsave_size = 0;
12378 compute_save_world_info (info_ptr);
12380 /* Calculate the offsets. */
12381 switch (DEFAULT_ABI)
12389 info_ptr->fp_save_offset = - info_ptr->fp_size;
12390 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12392 if (TARGET_ALTIVEC_ABI)
12394 info_ptr->vrsave_save_offset
12395 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12397 /* Align stack so vector save area is on a quadword boundary. */
12398 if (info_ptr->altivec_size != 0)
12399 info_ptr->altivec_padding_size
12400 = 16 - (-info_ptr->vrsave_save_offset % 16);
12402 info_ptr->altivec_padding_size = 0;
12404 info_ptr->altivec_save_offset
12405 = info_ptr->vrsave_save_offset
12406 - info_ptr->altivec_padding_size
12407 - info_ptr->altivec_size;
12409 /* Adjust for AltiVec case. */
12410 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12413 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12414 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12415 info_ptr->lr_save_offset = 2*reg_size;
12419 info_ptr->fp_save_offset = - info_ptr->fp_size;
12420 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12421 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12423 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12425 /* Align stack so SPE GPR save area is aligned on a
12426 double-word boundary. */
12427 if (info_ptr->spe_gp_size != 0)
12428 info_ptr->spe_padding_size
12429 = 8 - (-info_ptr->cr_save_offset % 8);
12431 info_ptr->spe_padding_size = 0;
12433 info_ptr->spe_gp_save_offset
12434 = info_ptr->cr_save_offset
12435 - info_ptr->spe_padding_size
12436 - info_ptr->spe_gp_size;
12438 /* Adjust for SPE case. */
12439 info_ptr->toc_save_offset
12440 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12442 else if (TARGET_ALTIVEC_ABI)
12444 info_ptr->vrsave_save_offset
12445 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12447 /* Align stack so vector save area is on a quadword boundary. */
12448 if (info_ptr->altivec_size != 0)
12449 info_ptr->altivec_padding_size
12450 = 16 - (-info_ptr->vrsave_save_offset % 16);
12452 info_ptr->altivec_padding_size = 0;
12454 info_ptr->altivec_save_offset
12455 = info_ptr->vrsave_save_offset
12456 - info_ptr->altivec_padding_size
12457 - info_ptr->altivec_size;
12459 /* Adjust for AltiVec case. */
12460 info_ptr->toc_save_offset
12461 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12464 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12465 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12466 info_ptr->lr_save_offset = reg_size;
12470 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12471 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12472 + info_ptr->gp_size
12473 + info_ptr->altivec_size
12474 + info_ptr->altivec_padding_size
12475 + info_ptr->spe_gp_size
12476 + info_ptr->spe_padding_size
12478 + info_ptr->cr_size
12479 + info_ptr->lr_size
12480 + info_ptr->vrsave_size
12481 + info_ptr->toc_size,
12484 non_fixed_size = (info_ptr->vars_size
12485 + info_ptr->parm_size
12486 + info_ptr->save_size
12487 + info_ptr->varargs_size);
12489 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12490 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12492 /* Determine if we need to allocate any stack frame:
12494 For AIX we need to push the stack if a frame pointer is needed
12495 (because the stack might be dynamically adjusted), if we are
12496 debugging, if we make calls, or if the sum of fp_save, gp_save,
12497 and local variables are more than the space needed to save all
12498 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12499 + 18*8 = 288 (GPR13 reserved).
12501 For V.4 we don't have the stack cushion that AIX uses, but assume
12502 that the debugger can handle stackless frames. */
12504 if (info_ptr->calls_p)
12505 info_ptr->push_p = 1;
12507 else if (DEFAULT_ABI == ABI_V4)
12508 info_ptr->push_p = non_fixed_size != 0;
12510 else if (frame_pointer_needed)
12511 info_ptr->push_p = 1;
12513 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12514 info_ptr->push_p = 1;
12517 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12519 /* Zero offsets if we're not saving those registers. */
12520 if (info_ptr->fp_size == 0)
12521 info_ptr->fp_save_offset = 0;
12523 if (info_ptr->gp_size == 0)
12524 info_ptr->gp_save_offset = 0;
12526 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12527 info_ptr->altivec_save_offset = 0;
12529 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12530 info_ptr->vrsave_save_offset = 0;
12532 if (! TARGET_SPE_ABI
12533 || info_ptr->spe_64bit_regs_used == 0
12534 || info_ptr->spe_gp_size == 0)
12535 info_ptr->spe_gp_save_offset = 0;
12537 if (! info_ptr->lr_save_p)
12538 info_ptr->lr_save_offset = 0;
12540 if (! info_ptr->cr_save_p)
12541 info_ptr->cr_save_offset = 0;
12543 if (! info_ptr->toc_save_p)
12544 info_ptr->toc_save_offset = 0;
12549 /* Return true if the current function uses any GPRs in 64-bit SIMD
12553 spe_func_has_64bit_regs_p (void)
12557 /* Functions that save and restore all the call-saved registers will
12558 need to save/restore the registers in 64-bits. */
12559 if (current_function_calls_eh_return
12560 || current_function_calls_setjmp
12561 || current_function_has_nonlocal_goto)
12564 insns = get_insns ();
12566 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12572 i = PATTERN (insn);
12573 if (GET_CODE (i) == SET)
12575 enum machine_mode mode = GET_MODE (SET_SRC (i));
12577 if (SPE_VECTOR_MODE (mode))
12579 if (TARGET_E500_DOUBLE && mode == DFmode)
12589 debug_stack_info (rs6000_stack_t *info)
12591 const char *abi_string;
12594 info = rs6000_stack_info ();
12596 fprintf (stderr, "\nStack information for function %s:\n",
12597 ((current_function_decl && DECL_NAME (current_function_decl))
12598 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12603 default: abi_string = "Unknown"; break;
12604 case ABI_NONE: abi_string = "NONE"; break;
12605 case ABI_AIX: abi_string = "AIX"; break;
12606 case ABI_DARWIN: abi_string = "Darwin"; break;
12607 case ABI_V4: abi_string = "V.4"; break;
12610 fprintf (stderr, "\tABI = %5s\n", abi_string);
12612 if (TARGET_ALTIVEC_ABI)
12613 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12615 if (TARGET_SPE_ABI)
12616 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12618 if (info->first_gp_reg_save != 32)
12619 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12621 if (info->first_fp_reg_save != 64)
12622 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12624 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12625 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12626 info->first_altivec_reg_save);
12628 if (info->lr_save_p)
12629 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
12631 if (info->cr_save_p)
12632 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12634 if (info->toc_save_p)
12635 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12637 if (info->vrsave_mask)
12638 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12641 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12644 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12646 if (info->gp_save_offset)
12647 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12649 if (info->fp_save_offset)
12650 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12652 if (info->altivec_save_offset)
12653 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12654 info->altivec_save_offset);
12656 if (info->spe_gp_save_offset)
12657 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12658 info->spe_gp_save_offset);
12660 if (info->vrsave_save_offset)
12661 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12662 info->vrsave_save_offset);
12664 if (info->lr_save_offset)
12665 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12667 if (info->cr_save_offset)
12668 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12670 if (info->toc_save_offset)
12671 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12673 if (info->varargs_save_offset)
12674 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12676 if (info->total_size)
12677 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12680 if (info->varargs_size)
12681 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
12683 if (info->vars_size)
12684 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12687 if (info->parm_size)
12688 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
12690 if (info->fixed_size)
12691 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
12694 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
12696 if (info->spe_gp_size)
12697 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
12700 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
12702 if (info->altivec_size)
12703 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
12705 if (info->vrsave_size)
12706 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
12708 if (info->altivec_padding_size)
12709 fprintf (stderr, "\taltivec_padding_size= %5d\n",
12710 info->altivec_padding_size);
12712 if (info->spe_padding_size)
12713 fprintf (stderr, "\tspe_padding_size = %5d\n",
12714 info->spe_padding_size);
12717 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
12720 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
12722 if (info->toc_size)
12723 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
12725 if (info->save_size)
12726 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
12728 if (info->reg_size != 4)
12729 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
12731 fprintf (stderr, "\n");
12735 rs6000_return_addr (int count, rtx frame)
12737 /* Currently we don't optimize very well between prolog and body
12738 code and for PIC code the code can be actually quite bad, so
12739 don't try to be too clever here. */
12740 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
12742 cfun->machine->ra_needs_full_frame = 1;
12749 plus_constant (copy_to_reg
12750 (gen_rtx_MEM (Pmode,
12751 memory_address (Pmode, frame))),
12752 RETURN_ADDRESS_OFFSET)));
12755 cfun->machine->ra_need_lr = 1;
12756 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
12759 /* Say whether a function is a candidate for sibcall handling or not.
12760 We do not allow indirect calls to be optimized into sibling calls.
12761 Also, we can't do it if there are any vector parameters; there's
12762 nowhere to put the VRsave code so it works; note that functions with
12763 vector parameters are required to have a prototype, so the argument
12764 type info must be available here. (The tail recursion case can work
12765 with vector parameters, but there's no way to distinguish here.) */
12767 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
12772 if (TARGET_ALTIVEC_VRSAVE)
12774 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
12775 type; type = TREE_CHAIN (type))
12777 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
12781 if (DEFAULT_ABI == ABI_DARWIN
12782 || (*targetm.binds_local_p) (decl))
12784 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
12786 if (!lookup_attribute ("longcall", attr_list)
12787 || lookup_attribute ("shortcall", attr_list))
12795 rs6000_ra_ever_killed (void)
12801 if (current_function_is_thunk)
12804 /* regs_ever_live has LR marked as used if any sibcalls are present,
12805 but this should not force saving and restoring in the
12806 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
12807 clobbers LR, so that is inappropriate. */
12809 /* Also, the prologue can generate a store into LR that
12810 doesn't really count, like this:
12813 bcl to set PIC register
12817 When we're called from the epilogue, we need to avoid counting
12818 this as a store. */
12820 push_topmost_sequence ();
12821 top = get_insns ();
12822 pop_topmost_sequence ();
12823 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12825 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
12829 if (FIND_REG_INC_NOTE (insn, reg))
12831 else if (GET_CODE (insn) == CALL_INSN
12832 && !SIBLING_CALL_P (insn))
12834 else if (set_of (reg, insn) != NULL_RTX
12835 && !prologue_epilogue_contains (insn))
12842 /* Add a REG_MAYBE_DEAD note to the insn. */
12844 rs6000_maybe_dead (rtx insn)
12846 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
12851 /* Emit instructions needed to load the TOC register.
12852 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
12853 a constant pool; or for SVR4 -fpic. */
12856 rs6000_emit_load_toc_table (int fromprolog)
12859 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12861 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12863 rtx temp = (fromprolog
12864 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12865 : gen_reg_rtx (Pmode));
12866 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12868 rs6000_maybe_dead (insn);
12869 insn = emit_move_insn (dest, temp);
12871 rs6000_maybe_dead (insn);
12873 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12876 rtx tempLR = (fromprolog
12877 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12878 : gen_reg_rtx (Pmode));
12879 rtx temp0 = (fromprolog
12880 ? gen_rtx_REG (Pmode, 0)
12881 : gen_reg_rtx (Pmode));
12884 /* possibly create the toc section */
12885 if (! toc_initialized)
12888 function_section (current_function_decl);
12895 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12896 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12898 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12899 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12901 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12903 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12904 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12911 static int reload_toc_labelno = 0;
12913 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12915 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
12916 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12918 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
12919 emit_move_insn (dest, tempLR);
12920 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12922 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12924 rs6000_maybe_dead (insn);
12926 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12928 /* This is for AIX code running in non-PIC ELF32. */
12931 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12932 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12934 insn = emit_insn (gen_elf_high (dest, realsym));
12936 rs6000_maybe_dead (insn);
12937 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12939 rs6000_maybe_dead (insn);
12941 else if (DEFAULT_ABI == ABI_AIX)
12944 insn = emit_insn (gen_load_toc_aix_si (dest));
12946 insn = emit_insn (gen_load_toc_aix_di (dest));
12948 rs6000_maybe_dead (insn);
12954 /* Emit instructions to restore the link register after determining where
12955 its value has been stored. */
12958 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12960 rs6000_stack_t *info = rs6000_stack_info ();
12963 operands[0] = source;
12964 operands[1] = scratch;
12966 if (info->lr_save_p)
12968 rtx frame_rtx = stack_pointer_rtx;
12969 HOST_WIDE_INT sp_offset = 0;
12972 if (frame_pointer_needed
12973 || current_function_calls_alloca
12974 || info->total_size > 32767)
12976 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12977 frame_rtx = operands[1];
12979 else if (info->push_p)
12980 sp_offset = info->total_size;
12982 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12983 tmp = gen_rtx_MEM (Pmode, tmp);
12984 emit_move_insn (tmp, operands[0]);
12987 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12990 static GTY(()) int set = -1;
12993 get_TOC_alias_set (void)
12996 set = new_alias_set ();
13000 /* This returns nonzero if the current function uses the TOC. This is
13001 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13002 is generated by the ABI_V4 load_toc_* patterns. */
13009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13012 rtx pat = PATTERN (insn);
13015 if (GET_CODE (pat) == PARALLEL)
13016 for (i = 0; i < XVECLEN (pat, 0); i++)
13018 rtx sub = XVECEXP (pat, 0, i);
13019 if (GET_CODE (sub) == USE)
13021 sub = XEXP (sub, 0);
13022 if (GET_CODE (sub) == UNSPEC
13023 && XINT (sub, 1) == UNSPEC_TOC)
13033 create_TOC_reference (rtx symbol)
13035 return gen_rtx_PLUS (Pmode,
13036 gen_rtx_REG (Pmode, TOC_REGISTER),
13037 gen_rtx_CONST (Pmode,
13038 gen_rtx_MINUS (Pmode, symbol,
13039 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13042 /* If _Unwind_* has been called from within the same module,
13043 toc register is not guaranteed to be saved to 40(1) on function
13044 entry. Save it there in that case. */
13047 rs6000_aix_emit_builtin_unwind_init (void)
13050 rtx stack_top = gen_reg_rtx (Pmode);
13051 rtx opcode_addr = gen_reg_rtx (Pmode);
13052 rtx opcode = gen_reg_rtx (SImode);
13053 rtx tocompare = gen_reg_rtx (SImode);
13054 rtx no_toc_save_needed = gen_label_rtx ();
13056 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
13057 emit_move_insn (stack_top, mem);
13059 mem = gen_rtx_MEM (Pmode,
13060 gen_rtx_PLUS (Pmode, stack_top,
13061 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13062 emit_move_insn (opcode_addr, mem);
13063 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13064 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13065 : 0xE8410028, SImode));
13067 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13068 SImode, NULL_RTX, NULL_RTX,
13069 no_toc_save_needed);
13071 mem = gen_rtx_MEM (Pmode,
13072 gen_rtx_PLUS (Pmode, stack_top,
13073 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13074 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13075 emit_label (no_toc_save_needed);
13078 /* This ties together stack memory (MEM with an alias set of
13079 rs6000_sr_alias_set) and the change to the stack pointer. */
13082 rs6000_emit_stack_tie (void)
13084 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13086 set_mem_alias_set (mem, rs6000_sr_alias_set);
13087 emit_insn (gen_stack_tie (mem));
13090 /* Emit the correct code for allocating stack space, as insns.
13091 If COPY_R12, make sure a copy of the old frame is left in r12.
13092 The generated code may use hard register 0 as a temporary. */
13095 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13098 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13099 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13100 rtx todec = gen_int_mode (-size, Pmode);
13102 if (INTVAL (todec) != -size)
13104 warning("stack frame too large");
13105 emit_insn (gen_trap ());
13109 if (current_function_limit_stack)
13111 if (REG_P (stack_limit_rtx)
13112 && REGNO (stack_limit_rtx) > 1
13113 && REGNO (stack_limit_rtx) <= 31)
13115 emit_insn (TARGET_32BIT
13116 ? gen_addsi3 (tmp_reg,
13119 : gen_adddi3 (tmp_reg,
13123 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13126 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13128 && DEFAULT_ABI == ABI_V4)
13130 rtx toload = gen_rtx_CONST (VOIDmode,
13131 gen_rtx_PLUS (Pmode,
13135 emit_insn (gen_elf_high (tmp_reg, toload));
13136 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13137 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13141 warning ("stack limit expression is not supported");
13144 if (copy_r12 || ! TARGET_UPDATE)
13145 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13151 /* Need a note here so that try_split doesn't get confused. */
13152 if (get_last_insn() == NULL_RTX)
13153 emit_note (NOTE_INSN_DELETED);
13154 insn = emit_move_insn (tmp_reg, todec);
13155 try_split (PATTERN (insn), insn, 0);
13159 insn = emit_insn (TARGET_32BIT
13160 ? gen_movsi_update (stack_reg, stack_reg,
13162 : gen_movdi_di_update (stack_reg, stack_reg,
13163 todec, stack_reg));
13167 insn = emit_insn (TARGET_32BIT
13168 ? gen_addsi3 (stack_reg, stack_reg, todec)
13169 : gen_adddi3 (stack_reg, stack_reg, todec));
13170 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13171 gen_rtx_REG (Pmode, 12));
13174 RTX_FRAME_RELATED_P (insn) = 1;
13176 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13177 gen_rtx_SET (VOIDmode, stack_reg,
13178 gen_rtx_PLUS (Pmode, stack_reg,
13183 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13184 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13185 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13186 deduce these equivalences by itself so it wasn't necessary to hold
13187 its hand so much. */
13190 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13191 rtx reg2, rtx rreg)
13195 /* copy_rtx will not make unique copies of registers, so we need to
13196 ensure we don't have unwanted sharing here. */
13198 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13201 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13203 real = copy_rtx (PATTERN (insn));
13205 if (reg2 != NULL_RTX)
13206 real = replace_rtx (real, reg2, rreg);
13208 real = replace_rtx (real, reg,
13209 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13210 STACK_POINTER_REGNUM),
13213 /* We expect that 'real' is either a SET or a PARALLEL containing
13214 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13215 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13217 if (GET_CODE (real) == SET)
13221 temp = simplify_rtx (SET_SRC (set));
13223 SET_SRC (set) = temp;
13224 temp = simplify_rtx (SET_DEST (set));
13226 SET_DEST (set) = temp;
13227 if (GET_CODE (SET_DEST (set)) == MEM)
13229 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13231 XEXP (SET_DEST (set), 0) = temp;
13234 else if (GET_CODE (real) == PARALLEL)
13237 for (i = 0; i < XVECLEN (real, 0); i++)
13238 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13240 rtx set = XVECEXP (real, 0, i);
13242 temp = simplify_rtx (SET_SRC (set));
13244 SET_SRC (set) = temp;
13245 temp = simplify_rtx (SET_DEST (set));
13247 SET_DEST (set) = temp;
13248 if (GET_CODE (SET_DEST (set)) == MEM)
13250 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13252 XEXP (SET_DEST (set), 0) = temp;
13254 RTX_FRAME_RELATED_P (set) = 1;
13261 real = spe_synthesize_frame_save (real);
13263 RTX_FRAME_RELATED_P (insn) = 1;
13264 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13269 /* Given an SPE frame note, return a PARALLEL of SETs with the
13270 original note, plus a synthetic register save. */
13273 spe_synthesize_frame_save (rtx real)
13275 rtx synth, offset, reg, real2;
13277 if (GET_CODE (real) != SET
13278 || GET_MODE (SET_SRC (real)) != V2SImode)
13281 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13282 frame related note. The parallel contains a set of the register
13283 being saved, and another set to a synthetic register (n+1200).
13284 This is so we can differentiate between 64-bit and 32-bit saves.
13285 Words cannot describe this nastiness. */
13287 if (GET_CODE (SET_DEST (real)) != MEM
13288 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
13289 || GET_CODE (SET_SRC (real)) != REG)
13293 (set (mem (plus (reg x) (const y)))
13296 (set (mem (plus (reg x) (const y+4)))
13300 real2 = copy_rtx (real);
13301 PUT_MODE (SET_DEST (real2), SImode);
13302 reg = SET_SRC (real2);
13303 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13304 synth = copy_rtx (real2);
13306 if (BYTES_BIG_ENDIAN)
13308 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13309 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13312 reg = SET_SRC (synth);
13314 synth = replace_rtx (synth, reg,
13315 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13317 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13318 synth = replace_rtx (synth, offset,
13319 GEN_INT (INTVAL (offset)
13320 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13322 RTX_FRAME_RELATED_P (synth) = 1;
13323 RTX_FRAME_RELATED_P (real2) = 1;
13324 if (BYTES_BIG_ENDIAN)
13325 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13327 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13332 /* Returns an insn that has a vrsave set operation with the
13333 appropriate CLOBBERs. */
13336 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13339 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13340 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13343 = gen_rtx_SET (VOIDmode,
13345 gen_rtx_UNSPEC_VOLATILE (SImode,
13346 gen_rtvec (2, reg, vrsave),
13351 /* We need to clobber the registers in the mask so the scheduler
13352 does not move sets to VRSAVE before sets of AltiVec registers.
13354 However, if the function receives nonlocal gotos, reload will set
13355 all call saved registers live. We will end up with:
13357 (set (reg 999) (mem))
13358 (parallel [ (set (reg vrsave) (unspec blah))
13359 (clobber (reg 999))])
13361 The clobber will cause the store into reg 999 to be dead, and
13362 flow will attempt to delete an epilogue insn. In this case, we
13363 need an unspec use/set of the register. */
13365 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13366 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13368 if (!epiloguep || call_used_regs [i])
13369 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13370 gen_rtx_REG (V4SImode, i));
13373 rtx reg = gen_rtx_REG (V4SImode, i);
13376 = gen_rtx_SET (VOIDmode,
13378 gen_rtx_UNSPEC (V4SImode,
13379 gen_rtvec (1, reg), 27));
13383 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13385 for (i = 0; i < nclobs; ++i)
13386 XVECEXP (insn, 0, i) = clobs[i];
13391 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13392 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13395 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13396 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13398 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13399 rtx replacea, replaceb;
13401 int_rtx = GEN_INT (offset);
13403 /* Some cases that need register indexed addressing. */
13404 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13405 || (TARGET_E500_DOUBLE && mode == DFmode)
13407 && SPE_VECTOR_MODE (mode)
13408 && !SPE_CONST_OFFSET_OK (offset)))
13410 /* Whomever calls us must make sure r11 is available in the
13411 flow path of instructions in the prologue. */
13412 offset_rtx = gen_rtx_REG (Pmode, 11);
13413 emit_move_insn (offset_rtx, int_rtx);
13415 replacea = offset_rtx;
13416 replaceb = int_rtx;
13420 offset_rtx = int_rtx;
13421 replacea = NULL_RTX;
13422 replaceb = NULL_RTX;
13425 reg = gen_rtx_REG (mode, regno);
13426 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13427 mem = gen_rtx_MEM (mode, addr);
13428 set_mem_alias_set (mem, rs6000_sr_alias_set);
13430 insn = emit_move_insn (mem, reg);
13432 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13435 /* Emit an offset memory reference suitable for a frame store, while
13436 converting to a valid addressing mode. */
13439 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13441 rtx int_rtx, offset_rtx;
13443 int_rtx = GEN_INT (offset);
13445 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13446 || (TARGET_E500_DOUBLE && mode == DFmode))
13448 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13449 emit_move_insn (offset_rtx, int_rtx);
13452 offset_rtx = int_rtx;
13454 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13457 #ifndef TARGET_FIX_AND_CONTINUE
13458 #define TARGET_FIX_AND_CONTINUE 0
13461 /* Emit function prologue as insns. */
13464 rs6000_emit_prologue (void)
13466 rs6000_stack_t *info = rs6000_stack_info ();
13467 enum machine_mode reg_mode = Pmode;
13468 int reg_size = TARGET_32BIT ? 4 : 8;
13469 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13470 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13471 rtx frame_reg_rtx = sp_reg_rtx;
13472 rtx cr_save_rtx = NULL_RTX;
13474 int saving_FPRs_inline;
13475 int using_store_multiple;
13476 HOST_WIDE_INT sp_offset = 0;
13478 if (TARGET_FIX_AND_CONTINUE)
13480 /* gdb on darwin arranges to forward a function from the old
13481 address by modifying the first 4 instructions of the function
13482 to branch to the overriding function. This is necessary to
13483 permit function pointers that point to the old function to
13484 actually forward to the new function. */
13485 emit_insn (gen_nop ());
13486 emit_insn (gen_nop ());
13487 emit_insn (gen_nop ());
13488 emit_insn (gen_nop ());
13491 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13493 reg_mode = V2SImode;
13497 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13498 && (!TARGET_SPE_ABI
13499 || info->spe_64bit_regs_used == 0)
13500 && info->first_gp_reg_save < 31);
13501 saving_FPRs_inline = (info->first_fp_reg_save == 64
13502 || FP_SAVE_INLINE (info->first_fp_reg_save)
13503 || current_function_calls_eh_return
13504 || cfun->machine->ra_need_lr);
13506 /* For V.4, update stack before we do any saving and set back pointer. */
13508 && (DEFAULT_ABI == ABI_V4
13509 || current_function_calls_eh_return))
13511 if (info->total_size < 32767)
13512 sp_offset = info->total_size;
13514 frame_reg_rtx = frame_ptr_rtx;
13515 rs6000_emit_allocate_stack (info->total_size,
13516 (frame_reg_rtx != sp_reg_rtx
13517 && (info->cr_save_p
13519 || info->first_fp_reg_save < 64
13520 || info->first_gp_reg_save < 32
13522 if (frame_reg_rtx != sp_reg_rtx)
13523 rs6000_emit_stack_tie ();
13526 /* Handle world saves specially here. */
13527 if (info->world_save_p)
13533 /* save_world expects lr in r0. */
13534 if (info->lr_save_p)
13536 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13537 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13538 RTX_FRAME_RELATED_P (insn) = 1;
13541 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13542 assumptions about the offsets of various bits of the stack
13543 frame. Abort if things aren't what they should be. */
13544 if (info->gp_save_offset != -220
13545 || info->fp_save_offset != -144
13546 || info->lr_save_offset != 8
13547 || info->cr_save_offset != 4
13549 || !info->lr_save_p
13550 || (current_function_calls_eh_return && info->ehrd_offset != -432)
13551 || (info->vrsave_save_offset != -224
13552 || info->altivec_save_offset != (-224 -16 -192)))
13555 treg = gen_rtx_REG (SImode, 11);
13556 emit_move_insn (treg, GEN_INT (-info->total_size));
13558 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13559 in R11. It also clobbers R12, so beware! */
13561 /* Preserve CR2 for save_world prologues */
13563 sz += 32 - info->first_gp_reg_save;
13564 sz += 64 - info->first_fp_reg_save;
13565 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13566 p = rtvec_alloc (sz);
13568 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13569 gen_rtx_REG (Pmode,
13570 LINK_REGISTER_REGNUM));
13571 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13572 gen_rtx_SYMBOL_REF (Pmode,
13574 /* We do floats first so that the instruction pattern matches
13576 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13578 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13579 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13580 GEN_INT (info->fp_save_offset
13581 + sp_offset + 8 * i));
13582 rtx mem = gen_rtx_MEM (DFmode, addr);
13583 set_mem_alias_set (mem, rs6000_sr_alias_set);
13585 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13587 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13589 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13590 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13591 GEN_INT (info->altivec_save_offset
13592 + sp_offset + 16 * i));
13593 rtx mem = gen_rtx_MEM (V4SImode, addr);
13594 set_mem_alias_set (mem, rs6000_sr_alias_set);
13596 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13598 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13600 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13601 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13602 GEN_INT (info->gp_save_offset
13603 + sp_offset + reg_size * i));
13604 rtx mem = gen_rtx_MEM (reg_mode, addr);
13605 set_mem_alias_set (mem, rs6000_sr_alias_set);
13607 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13611 /* CR register traditionally saved as CR2. */
13612 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13613 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13614 GEN_INT (info->cr_save_offset
13616 rtx mem = gen_rtx_MEM (reg_mode, addr);
13617 set_mem_alias_set (mem, rs6000_sr_alias_set);
13619 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13621 /* Prevent any attempt to delete the setting of r0 and treg! */
13622 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13623 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13624 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13626 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13627 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13628 NULL_RTX, NULL_RTX);
13630 if (current_function_calls_eh_return)
13635 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13636 if (regno == INVALID_REGNUM)
13638 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13639 info->ehrd_offset + sp_offset
13640 + reg_size * (int) i,
13646 /* Save AltiVec registers if needed. */
13647 if (! info->world_save_p && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13651 /* There should be a non inline version of this, for when we
13652 are saving lots of vector registers. */
13653 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13654 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13656 rtx areg, savereg, mem;
13659 offset = info->altivec_save_offset + sp_offset
13660 + 16 * (i - info->first_altivec_reg_save);
13662 savereg = gen_rtx_REG (V4SImode, i);
13664 areg = gen_rtx_REG (Pmode, 0);
13665 emit_move_insn (areg, GEN_INT (offset));
13667 /* AltiVec addressing mode is [reg+reg]. */
13668 mem = gen_rtx_MEM (V4SImode,
13669 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
13671 set_mem_alias_set (mem, rs6000_sr_alias_set);
13673 insn = emit_move_insn (mem, savereg);
13675 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13676 areg, GEN_INT (offset));
13680 /* VRSAVE is a bit vector representing which AltiVec registers
13681 are used. The OS uses this to determine which vector
13682 registers to save on a context switch. We need to save
13683 VRSAVE on the stack frame, add whatever AltiVec registers we
13684 used in this function, and do the corresponding magic in the
13687 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13688 && ! info->world_save_p && info->vrsave_mask != 0)
13690 rtx reg, mem, vrsave;
13693 /* Get VRSAVE onto a GPR. */
13694 reg = gen_rtx_REG (SImode, 12);
13695 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13697 emit_insn (gen_get_vrsave_internal (reg));
13699 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
13702 offset = info->vrsave_save_offset + sp_offset;
13704 = gen_rtx_MEM (SImode,
13705 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
13706 set_mem_alias_set (mem, rs6000_sr_alias_set);
13707 insn = emit_move_insn (mem, reg);
13709 /* Include the registers in the mask. */
13710 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
13712 insn = emit_insn (generate_set_vrsave (reg, info, 0));
13715 /* If we use the link register, get it into r0. */
13716 if (! info->world_save_p && info->lr_save_p)
13718 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13719 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13720 RTX_FRAME_RELATED_P (insn) = 1;
13723 /* If we need to save CR, put it into r12. */
13724 if (! info->world_save_p && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
13728 cr_save_rtx = gen_rtx_REG (SImode, 12);
13729 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13730 RTX_FRAME_RELATED_P (insn) = 1;
13731 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13732 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13733 But that's OK. All we have to do is specify that _one_ condition
13734 code register is saved in this stack slot. The thrower's epilogue
13735 will then restore all the call-saved registers.
13736 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13737 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
13738 gen_rtx_REG (SImode, CR2_REGNO));
13739 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13744 /* Do any required saving of fpr's. If only one or two to save, do
13745 it ourselves. Otherwise, call function. */
13746 if (! info->world_save_p && saving_FPRs_inline)
13749 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13750 if ((regs_ever_live[info->first_fp_reg_save+i]
13751 && ! call_used_regs[info->first_fp_reg_save+i]))
13752 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
13753 info->first_fp_reg_save + i,
13754 info->fp_save_offset + sp_offset + 8 * i,
13757 else if (! info->world_save_p && info->first_fp_reg_save != 64)
13761 const char *alloc_rname;
13763 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
13765 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
13766 gen_rtx_REG (Pmode,
13767 LINK_REGISTER_REGNUM));
13768 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
13769 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
13770 alloc_rname = ggc_strdup (rname);
13771 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13772 gen_rtx_SYMBOL_REF (Pmode,
13774 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13776 rtx addr, reg, mem;
13777 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13778 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13779 GEN_INT (info->fp_save_offset
13780 + sp_offset + 8*i));
13781 mem = gen_rtx_MEM (DFmode, addr);
13782 set_mem_alias_set (mem, rs6000_sr_alias_set);
13784 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
13786 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13787 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13788 NULL_RTX, NULL_RTX);
13791 /* Save GPRs. This is done as a PARALLEL if we are using
13792 the store-multiple instructions. */
13793 if (! info->world_save_p && using_store_multiple)
13797 p = rtvec_alloc (32 - info->first_gp_reg_save);
13798 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13800 rtx addr, reg, mem;
13801 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13802 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13803 GEN_INT (info->gp_save_offset
13806 mem = gen_rtx_MEM (reg_mode, addr);
13807 set_mem_alias_set (mem, rs6000_sr_alias_set);
13809 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
13811 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13812 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13813 NULL_RTX, NULL_RTX);
13815 else if (! info->world_save_p)
13818 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13819 if ((regs_ever_live[info->first_gp_reg_save+i]
13820 && (! call_used_regs[info->first_gp_reg_save+i]
13821 || (i+info->first_gp_reg_save
13822 == RS6000_PIC_OFFSET_TABLE_REGNUM
13823 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13824 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13825 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13826 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13828 rtx addr, reg, mem;
13829 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13831 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13833 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13836 if (!SPE_CONST_OFFSET_OK (offset))
13838 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13839 emit_move_insn (b, GEN_INT (offset));
13842 b = GEN_INT (offset);
13844 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13845 mem = gen_rtx_MEM (V2SImode, addr);
13846 set_mem_alias_set (mem, rs6000_sr_alias_set);
13847 insn = emit_move_insn (mem, reg);
13849 if (GET_CODE (b) == CONST_INT)
13850 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13851 NULL_RTX, NULL_RTX);
13853 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13854 b, GEN_INT (offset));
13858 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13859 GEN_INT (info->gp_save_offset
13862 mem = gen_rtx_MEM (reg_mode, addr);
13863 set_mem_alias_set (mem, rs6000_sr_alias_set);
13865 insn = emit_move_insn (mem, reg);
13866 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13867 NULL_RTX, NULL_RTX);
13872 /* ??? There's no need to emit actual instructions here, but it's the
13873 easiest way to get the frame unwind information emitted. */
13874 if (! info->world_save_p && current_function_calls_eh_return)
13876 unsigned int i, regno;
13878 /* In AIX ABI we need to pretend we save r2 here. */
13881 rtx addr, reg, mem;
13883 reg = gen_rtx_REG (reg_mode, 2);
13884 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13885 GEN_INT (sp_offset + 5 * reg_size));
13886 mem = gen_rtx_MEM (reg_mode, addr);
13887 set_mem_alias_set (mem, rs6000_sr_alias_set);
13889 insn = emit_move_insn (mem, reg);
13890 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13891 NULL_RTX, NULL_RTX);
13892 PATTERN (insn) = gen_blockage ();
13897 regno = EH_RETURN_DATA_REGNO (i);
13898 if (regno == INVALID_REGNUM)
13901 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13902 info->ehrd_offset + sp_offset
13903 + reg_size * (int) i,
13908 /* Save lr if we used it. */
13909 if (! info->world_save_p && info->lr_save_p)
13911 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13912 GEN_INT (info->lr_save_offset + sp_offset));
13913 rtx reg = gen_rtx_REG (Pmode, 0);
13914 rtx mem = gen_rtx_MEM (Pmode, addr);
13915 /* This should not be of rs6000_sr_alias_set, because of
13916 __builtin_return_address. */
13918 insn = emit_move_insn (mem, reg);
13919 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13920 NULL_RTX, NULL_RTX);
13923 /* Save CR if we use any that must be preserved. */
13924 if (! info->world_save_p && info->cr_save_p)
13926 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13927 GEN_INT (info->cr_save_offset + sp_offset));
13928 rtx mem = gen_rtx_MEM (SImode, addr);
13929 /* See the large comment above about why CR2_REGNO is used. */
13930 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13932 set_mem_alias_set (mem, rs6000_sr_alias_set);
13934 /* If r12 was used to hold the original sp, copy cr into r0 now
13936 if (REGNO (frame_reg_rtx) == 12)
13940 cr_save_rtx = gen_rtx_REG (SImode, 0);
13941 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13942 RTX_FRAME_RELATED_P (insn) = 1;
13943 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13944 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13949 insn = emit_move_insn (mem, cr_save_rtx);
13951 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13952 NULL_RTX, NULL_RTX);
13955 /* Update stack and set back pointer unless this is V.4,
13956 for which it was done previously. */
13957 if (! info->world_save_p && info->push_p
13958 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13959 rs6000_emit_allocate_stack (info->total_size, FALSE);
13961 /* Set frame pointer, if needed. */
13962 if (frame_pointer_needed)
13964 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
13966 RTX_FRAME_RELATED_P (insn) = 1;
13969 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13970 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13971 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
13972 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13974 /* If emit_load_toc_table will use the link register, we need to save
13975 it. We use R12 for this purpose because emit_load_toc_table
13976 can use register 0. This allows us to use a plain 'blr' to return
13977 from the procedure more often. */
13978 int save_LR_around_toc_setup = (TARGET_ELF
13979 && DEFAULT_ABI != ABI_AIX
13981 && ! info->lr_save_p
13982 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13983 if (save_LR_around_toc_setup)
13985 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13987 insn = emit_move_insn (frame_ptr_rtx, lr);
13988 rs6000_maybe_dead (insn);
13989 RTX_FRAME_RELATED_P (insn) = 1;
13991 rs6000_emit_load_toc_table (TRUE);
13993 insn = emit_move_insn (lr, frame_ptr_rtx);
13994 rs6000_maybe_dead (insn);
13995 RTX_FRAME_RELATED_P (insn) = 1;
13998 rs6000_emit_load_toc_table (TRUE);
14002 if (DEFAULT_ABI == ABI_DARWIN
14003 && flag_pic && current_function_uses_pic_offset_table)
14005 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14006 rtx src = machopic_function_base_sym ();
14008 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14010 insn = emit_move_insn (gen_rtx_REG (Pmode,
14011 RS6000_PIC_OFFSET_TABLE_REGNUM),
14013 rs6000_maybe_dead (insn);
14018 /* Write function prologue. */
14021 rs6000_output_function_prologue (FILE *file,
14022 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14024 rs6000_stack_t *info = rs6000_stack_info ();
14026 if (TARGET_DEBUG_STACK)
14027 debug_stack_info (info);
14029 /* Write .extern for any function we will call to save and restore
14031 if (info->first_fp_reg_save < 64
14032 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14033 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14034 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14035 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14036 RESTORE_FP_SUFFIX);
14038 /* Write .extern for AIX common mode routines, if needed. */
14039 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14041 fputs ("\t.extern __mulh\n", file);
14042 fputs ("\t.extern __mull\n", file);
14043 fputs ("\t.extern __divss\n", file);
14044 fputs ("\t.extern __divus\n", file);
14045 fputs ("\t.extern __quoss\n", file);
14046 fputs ("\t.extern __quous\n", file);
14047 common_mode_defined = 1;
14050 if (! HAVE_prologue)
14054 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14055 the "toplevel" insn chain. */
14056 emit_note (NOTE_INSN_DELETED);
14057 rs6000_emit_prologue ();
14058 emit_note (NOTE_INSN_DELETED);
14060 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14064 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14066 INSN_ADDRESSES_NEW (insn, addr);
14071 if (TARGET_DEBUG_STACK)
14072 debug_rtx_list (get_insns (), 100);
14073 final (get_insns (), file, FALSE, FALSE);
14077 rs6000_pic_labelno++;
14080 /* Emit function epilogue as insns.
14082 At present, dwarf2out_frame_debug_expr doesn't understand
14083 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14084 anywhere in the epilogue. Most of the insns below would in any case
14085 need special notes to explain where r11 is in relation to the stack. */
14088 rs6000_emit_epilogue (int sibcall)
14090 rs6000_stack_t *info;
14091 int restoring_FPRs_inline;
14092 int using_load_multiple;
14093 int using_mfcr_multiple;
14094 int use_backchain_to_restore_sp;
14096 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14097 rtx frame_reg_rtx = sp_reg_rtx;
14098 enum machine_mode reg_mode = Pmode;
14099 int reg_size = TARGET_32BIT ? 4 : 8;
14102 info = rs6000_stack_info ();
14104 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14106 reg_mode = V2SImode;
14110 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14111 && (!TARGET_SPE_ABI
14112 || info->spe_64bit_regs_used == 0)
14113 && info->first_gp_reg_save < 31);
14114 restoring_FPRs_inline = (sibcall
14115 || current_function_calls_eh_return
14116 || info->first_fp_reg_save == 64
14117 || FP_SAVE_INLINE (info->first_fp_reg_save));
14118 use_backchain_to_restore_sp = (frame_pointer_needed
14119 || current_function_calls_alloca
14120 || info->total_size > 32767);
14121 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14122 || rs6000_cpu == PROCESSOR_PPC603
14123 || rs6000_cpu == PROCESSOR_PPC750
14126 if (info->world_save_p)
14130 const char *alloc_rname;
14133 /* eh_rest_world_r10 will return to the location saved in the LR
14134 stack slot (which is not likely to be our caller.)
14135 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14136 rest_world is similar, except any R10 parameter is ignored.
14137 The exception-handling stuff that was here in 2.95 is no
14138 longer necessary. */
14142 + 32 - info->first_gp_reg_save
14143 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14144 + 63 + 1 - info->first_fp_reg_save);
14146 strcpy (rname, ((current_function_calls_eh_return) ?
14147 "*eh_rest_world_r10" : "*rest_world"));
14148 alloc_rname = ggc_strdup (rname);
14151 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14152 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14153 gen_rtx_REG (Pmode,
14154 LINK_REGISTER_REGNUM));
14156 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14157 /* The instruction pattern requires a clobber here;
14158 it is shared with the restVEC helper. */
14160 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14163 /* CR register traditionally saved as CR2. */
14164 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14165 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14166 GEN_INT (info->cr_save_offset));
14167 rtx mem = gen_rtx_MEM (reg_mode, addr);
14168 set_mem_alias_set (mem, rs6000_sr_alias_set);
14170 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14173 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14175 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14176 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14177 GEN_INT (info->gp_save_offset
14179 rtx mem = gen_rtx_MEM (reg_mode, addr);
14180 set_mem_alias_set (mem, rs6000_sr_alias_set);
14182 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14184 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14186 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14187 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14188 GEN_INT (info->altivec_save_offset
14190 rtx mem = gen_rtx_MEM (V4SImode, addr);
14191 set_mem_alias_set (mem, rs6000_sr_alias_set);
14193 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14195 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14197 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14198 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14199 GEN_INT (info->fp_save_offset
14201 rtx mem = gen_rtx_MEM (DFmode, addr);
14202 set_mem_alias_set (mem, rs6000_sr_alias_set);
14204 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14207 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14209 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14211 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14213 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14215 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14216 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14221 /* If we have a frame pointer, a call to alloca, or a large stack
14222 frame, restore the old stack pointer using the backchain. Otherwise,
14223 we know what size to update it with. */
14224 if (use_backchain_to_restore_sp)
14226 /* Under V.4, don't reset the stack pointer until after we're done
14227 loading the saved registers. */
14228 if (DEFAULT_ABI == ABI_V4)
14229 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14231 emit_move_insn (frame_reg_rtx,
14232 gen_rtx_MEM (Pmode, sp_reg_rtx));
14235 else if (info->push_p)
14237 if (DEFAULT_ABI == ABI_V4
14238 || current_function_calls_eh_return)
14239 sp_offset = info->total_size;
14242 emit_insn (TARGET_32BIT
14243 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14244 GEN_INT (info->total_size))
14245 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14246 GEN_INT (info->total_size)));
14250 /* Restore AltiVec registers if needed. */
14251 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14255 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14256 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14258 rtx addr, areg, mem;
14260 areg = gen_rtx_REG (Pmode, 0);
14262 (areg, GEN_INT (info->altivec_save_offset
14264 + 16 * (i - info->first_altivec_reg_save)));
14266 /* AltiVec addressing mode is [reg+reg]. */
14267 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14268 mem = gen_rtx_MEM (V4SImode, addr);
14269 set_mem_alias_set (mem, rs6000_sr_alias_set);
14271 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14275 /* Restore VRSAVE if needed. */
14276 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14277 && info->vrsave_mask != 0)
14279 rtx addr, mem, reg;
14281 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14282 GEN_INT (info->vrsave_save_offset + sp_offset));
14283 mem = gen_rtx_MEM (SImode, addr);
14284 set_mem_alias_set (mem, rs6000_sr_alias_set);
14285 reg = gen_rtx_REG (SImode, 12);
14286 emit_move_insn (reg, mem);
14288 emit_insn (generate_set_vrsave (reg, info, 1));
14291 /* Get the old lr if we saved it. */
14292 if (info->lr_save_p)
14294 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14295 info->lr_save_offset + sp_offset);
14297 set_mem_alias_set (mem, rs6000_sr_alias_set);
14299 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14302 /* Get the old cr if we saved it. */
14303 if (info->cr_save_p)
14305 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14306 GEN_INT (info->cr_save_offset + sp_offset));
14307 rtx mem = gen_rtx_MEM (SImode, addr);
14309 set_mem_alias_set (mem, rs6000_sr_alias_set);
14311 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14314 /* Set LR here to try to overlap restores below. */
14315 if (info->lr_save_p)
14316 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14317 gen_rtx_REG (Pmode, 0));
14319 /* Load exception handler data registers, if needed. */
14320 if (current_function_calls_eh_return)
14322 unsigned int i, regno;
14326 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14327 GEN_INT (sp_offset + 5 * reg_size));
14328 rtx mem = gen_rtx_MEM (reg_mode, addr);
14330 set_mem_alias_set (mem, rs6000_sr_alias_set);
14332 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14339 regno = EH_RETURN_DATA_REGNO (i);
14340 if (regno == INVALID_REGNUM)
14343 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14344 info->ehrd_offset + sp_offset
14345 + reg_size * (int) i);
14346 set_mem_alias_set (mem, rs6000_sr_alias_set);
14348 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14352 /* Restore GPRs. This is done as a PARALLEL if we are using
14353 the load-multiple instructions. */
14354 if (using_load_multiple)
14357 p = rtvec_alloc (32 - info->first_gp_reg_save);
14358 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14360 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14361 GEN_INT (info->gp_save_offset
14364 rtx mem = gen_rtx_MEM (reg_mode, addr);
14366 set_mem_alias_set (mem, rs6000_sr_alias_set);
14369 gen_rtx_SET (VOIDmode,
14370 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14373 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14376 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14377 if ((regs_ever_live[info->first_gp_reg_save+i]
14378 && (! call_used_regs[info->first_gp_reg_save+i]
14379 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14380 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14381 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14382 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14383 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14385 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14386 GEN_INT (info->gp_save_offset
14389 rtx mem = gen_rtx_MEM (reg_mode, addr);
14391 /* Restore 64-bit quantities for SPE. */
14392 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14394 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14397 if (!SPE_CONST_OFFSET_OK (offset))
14399 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14400 emit_move_insn (b, GEN_INT (offset));
14403 b = GEN_INT (offset);
14405 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14406 mem = gen_rtx_MEM (V2SImode, addr);
14409 set_mem_alias_set (mem, rs6000_sr_alias_set);
14411 emit_move_insn (gen_rtx_REG (reg_mode,
14412 info->first_gp_reg_save + i), mem);
14415 /* Restore fpr's if we need to do it without calling a function. */
14416 if (restoring_FPRs_inline)
14417 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14418 if ((regs_ever_live[info->first_fp_reg_save+i]
14419 && ! call_used_regs[info->first_fp_reg_save+i]))
14422 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14423 GEN_INT (info->fp_save_offset
14426 mem = gen_rtx_MEM (DFmode, addr);
14427 set_mem_alias_set (mem, rs6000_sr_alias_set);
14429 emit_move_insn (gen_rtx_REG (DFmode,
14430 info->first_fp_reg_save + i),
14434 /* If we saved cr, restore it here. Just those that were used. */
14435 if (info->cr_save_p)
14437 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14440 if (using_mfcr_multiple)
14442 for (i = 0; i < 8; i++)
14443 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14449 if (using_mfcr_multiple && count > 1)
14454 p = rtvec_alloc (count);
14457 for (i = 0; i < 8; i++)
14458 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14460 rtvec r = rtvec_alloc (2);
14461 RTVEC_ELT (r, 0) = r12_rtx;
14462 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14463 RTVEC_ELT (p, ndx) =
14464 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14465 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14468 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14473 for (i = 0; i < 8; i++)
14474 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14476 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14482 /* If this is V.4, unwind the stack pointer after all of the loads
14483 have been done. We need to emit a block here so that sched
14484 doesn't decide to move the sp change before the register restores
14485 (which may not have any obvious dependency on the stack). This
14486 doesn't hurt performance, because there is no scheduling that can
14487 be done after this point. */
14488 if (DEFAULT_ABI == ABI_V4
14489 || current_function_calls_eh_return)
14491 if (frame_reg_rtx != sp_reg_rtx)
14492 rs6000_emit_stack_tie ();
14494 if (use_backchain_to_restore_sp)
14496 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14498 else if (sp_offset != 0)
14500 emit_insn (TARGET_32BIT
14501 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14502 GEN_INT (sp_offset))
14503 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14504 GEN_INT (sp_offset)));
14508 if (current_function_calls_eh_return)
14510 rtx sa = EH_RETURN_STACKADJ_RTX;
14511 emit_insn (TARGET_32BIT
14512 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14513 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14519 if (! restoring_FPRs_inline)
14520 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14522 p = rtvec_alloc (2);
14524 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14525 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14526 gen_rtx_REG (Pmode,
14527 LINK_REGISTER_REGNUM));
14529 /* If we have to restore more than two FP registers, branch to the
14530 restore function. It will return to our caller. */
14531 if (! restoring_FPRs_inline)
14535 const char *alloc_rname;
14537 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14538 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14539 alloc_rname = ggc_strdup (rname);
14540 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14541 gen_rtx_SYMBOL_REF (Pmode,
14544 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14547 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14548 GEN_INT (info->fp_save_offset + 8*i));
14549 mem = gen_rtx_MEM (DFmode, addr);
14550 set_mem_alias_set (mem, rs6000_sr_alias_set);
14552 RTVEC_ELT (p, i+3) =
14553 gen_rtx_SET (VOIDmode,
14554 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14559 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14563 /* Write function epilogue. */
14566 rs6000_output_function_epilogue (FILE *file,
14567 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14569 rs6000_stack_t *info = rs6000_stack_info ();
14571 if (! HAVE_epilogue)
14573 rtx insn = get_last_insn ();
14574 /* If the last insn was a BARRIER, we don't have to write anything except
14575 the trace table. */
14576 if (GET_CODE (insn) == NOTE)
14577 insn = prev_nonnote_insn (insn);
14578 if (insn == 0 || GET_CODE (insn) != BARRIER)
14580 /* This is slightly ugly, but at least we don't have two
14581 copies of the epilogue-emitting code. */
14584 /* A NOTE_INSN_DELETED is supposed to be at the start
14585 and end of the "toplevel" insn chain. */
14586 emit_note (NOTE_INSN_DELETED);
14587 rs6000_emit_epilogue (FALSE);
14588 emit_note (NOTE_INSN_DELETED);
14590 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14594 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14596 INSN_ADDRESSES_NEW (insn, addr);
14601 if (TARGET_DEBUG_STACK)
14602 debug_rtx_list (get_insns (), 100);
14603 final (get_insns (), file, FALSE, FALSE);
14609 macho_branch_islands ();
14610 /* Mach-O doesn't support labels at the end of objects, so if
14611 it looks like we might want one, insert a NOP. */
14613 rtx insn = get_last_insn ();
14616 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14617 insn = PREV_INSN (insn);
14621 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14622 fputs ("\tnop\n", file);
14626 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14629 We don't output a traceback table if -finhibit-size-directive was
14630 used. The documentation for -finhibit-size-directive reads
14631 ``don't output a @code{.size} assembler directive, or anything
14632 else that would cause trouble if the function is split in the
14633 middle, and the two halves are placed at locations far apart in
14634 memory.'' The traceback table has this property, since it
14635 includes the offset from the start of the function to the
14636 traceback table itself.
14638 System V.4 Powerpc's (and the embedded ABI derived from it) use a
14639 different traceback table. */
14640 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14641 && rs6000_traceback != traceback_none)
14643 const char *fname = NULL;
14644 const char *language_string = lang_hooks.name;
14645 int fixed_parms = 0, float_parms = 0, parm_info = 0;
14647 int optional_tbtab;
14649 if (rs6000_traceback == traceback_full)
14650 optional_tbtab = 1;
14651 else if (rs6000_traceback == traceback_part)
14652 optional_tbtab = 0;
14654 optional_tbtab = !optimize_size && !TARGET_ELF;
14656 if (optional_tbtab)
14658 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14659 while (*fname == '.') /* V.4 encodes . in the name */
14662 /* Need label immediately before tbtab, so we can compute
14663 its offset from the function start. */
14664 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14665 ASM_OUTPUT_LABEL (file, fname);
14668 /* The .tbtab pseudo-op can only be used for the first eight
14669 expressions, since it can't handle the possibly variable
14670 length fields that follow. However, if you omit the optional
14671 fields, the assembler outputs zeros for all optional fields
14672 anyways, giving each variable length field is minimum length
14673 (as defined in sys/debug.h). Thus we can not use the .tbtab
14674 pseudo-op at all. */
14676 /* An all-zero word flags the start of the tbtab, for debuggers
14677 that have to find it by searching forward from the entry
14678 point or from the current pc. */
14679 fputs ("\t.long 0\n", file);
14681 /* Tbtab format type. Use format type 0. */
14682 fputs ("\t.byte 0,", file);
14684 /* Language type. Unfortunately, there does not seem to be any
14685 official way to discover the language being compiled, so we
14686 use language_string.
14687 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14688 Java is 13. Objective-C is 14. */
14689 if (! strcmp (language_string, "GNU C"))
14691 else if (! strcmp (language_string, "GNU F77")
14692 || ! strcmp (language_string, "GNU F95"))
14694 else if (! strcmp (language_string, "GNU Pascal"))
14696 else if (! strcmp (language_string, "GNU Ada"))
14698 else if (! strcmp (language_string, "GNU C++"))
14700 else if (! strcmp (language_string, "GNU Java"))
14702 else if (! strcmp (language_string, "GNU Objective-C"))
14706 fprintf (file, "%d,", i);
14708 /* 8 single bit fields: global linkage (not set for C extern linkage,
14709 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14710 from start of procedure stored in tbtab, internal function, function
14711 has controlled storage, function has no toc, function uses fp,
14712 function logs/aborts fp operations. */
14713 /* Assume that fp operations are used if any fp reg must be saved. */
14714 fprintf (file, "%d,",
14715 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
14717 /* 6 bitfields: function is interrupt handler, name present in
14718 proc table, function calls alloca, on condition directives
14719 (controls stack walks, 3 bits), saves condition reg, saves
14721 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14722 set up as a frame pointer, even when there is no alloca call. */
14723 fprintf (file, "%d,",
14724 ((optional_tbtab << 6)
14725 | ((optional_tbtab & frame_pointer_needed) << 5)
14726 | (info->cr_save_p << 1)
14727 | (info->lr_save_p)));
14729 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
14731 fprintf (file, "%d,",
14732 (info->push_p << 7) | (64 - info->first_fp_reg_save));
14734 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14735 fprintf (file, "%d,", (32 - first_reg_to_save ()));
14737 if (optional_tbtab)
14739 /* Compute the parameter info from the function decl argument
14742 int next_parm_info_bit = 31;
14744 for (decl = DECL_ARGUMENTS (current_function_decl);
14745 decl; decl = TREE_CHAIN (decl))
14747 rtx parameter = DECL_INCOMING_RTL (decl);
14748 enum machine_mode mode = GET_MODE (parameter);
14750 if (GET_CODE (parameter) == REG)
14752 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
14758 if (mode == SFmode)
14760 else if (mode == DFmode || mode == TFmode)
14765 /* If only one bit will fit, don't or in this entry. */
14766 if (next_parm_info_bit > 0)
14767 parm_info |= (bits << (next_parm_info_bit - 1));
14768 next_parm_info_bit -= 2;
14772 fixed_parms += ((GET_MODE_SIZE (mode)
14773 + (UNITS_PER_WORD - 1))
14775 next_parm_info_bit -= 1;
14781 /* Number of fixed point parameters. */
14782 /* This is actually the number of words of fixed point parameters; thus
14783 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14784 fprintf (file, "%d,", fixed_parms);
14786 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14788 /* This is actually the number of fp registers that hold parameters;
14789 and thus the maximum value is 13. */
14790 /* Set parameters on stack bit if parameters are not in their original
14791 registers, regardless of whether they are on the stack? Xlc
14792 seems to set the bit when not optimizing. */
14793 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
14795 if (! optional_tbtab)
14798 /* Optional fields follow. Some are variable length. */
14800 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14801 11 double float. */
14802 /* There is an entry for each parameter in a register, in the order that
14803 they occur in the parameter list. Any intervening arguments on the
14804 stack are ignored. If the list overflows a long (max possible length
14805 34 bits) then completely leave off all elements that don't fit. */
14806 /* Only emit this long if there was at least one parameter. */
14807 if (fixed_parms || float_parms)
14808 fprintf (file, "\t.long %d\n", parm_info);
14810 /* Offset from start of code to tb table. */
14811 fputs ("\t.long ", file);
14812 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14814 RS6000_OUTPUT_BASENAME (file, fname);
14816 assemble_name (file, fname);
14818 rs6000_output_function_entry (file, fname);
14821 /* Interrupt handler mask. */
14822 /* Omit this long, since we never set the interrupt handler bit
14825 /* Number of CTL (controlled storage) anchors. */
14826 /* Omit this long, since the has_ctl bit is never set above. */
14828 /* Displacement into stack of each CTL anchor. */
14829 /* Omit this list of longs, because there are no CTL anchors. */
14831 /* Length of function name. */
14834 fprintf (file, "\t.short %d\n", (int) strlen (fname));
14836 /* Function name. */
14837 assemble_string (fname, strlen (fname));
14839 /* Register for alloca automatic storage; this is always reg 31.
14840 Only emit this if the alloca bit was set above. */
14841 if (frame_pointer_needed)
14842 fputs ("\t.byte 31\n", file);
14844 fputs ("\t.align 2\n", file);
14848 /* A C compound statement that outputs the assembler code for a thunk
14849 function, used to implement C++ virtual function calls with
14850 multiple inheritance. The thunk acts as a wrapper around a virtual
14851 function, adjusting the implicit object parameter before handing
14852 control off to the real function.
14854 First, emit code to add the integer DELTA to the location that
14855 contains the incoming first argument. Assume that this argument
14856 contains a pointer, and is the one used to pass the `this' pointer
14857 in C++. This is the incoming argument *before* the function
14858 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14859 values of all other incoming arguments.
14861 After the addition, emit code to jump to FUNCTION, which is a
14862 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14863 not touch the return address. Hence returning from FUNCTION will
14864 return to whoever called the current `thunk'.
14866 The effect must be as if FUNCTION had been called directly with the
14867 adjusted first argument. This macro is responsible for emitting
14868 all of the code for a thunk function; output_function_prologue()
14869 and output_function_epilogue() are not invoked.
14871 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14872 been extracted from it.) It might possibly be useful on some
14873 targets, but probably not.
14875 If you do not define this macro, the target-independent code in the
14876 C++ frontend will generate a less efficient heavyweight thunk that
14877 calls FUNCTION instead of jumping to it. The generic approach does
14878 not support varargs. */
14881 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14882 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14885 rtx this, insn, funexp;
14887 reload_completed = 1;
14888 epilogue_completed = 1;
14889 no_new_pseudos = 1;
14890 reset_block_changes ();
14892 /* Mark the end of the (empty) prologue. */
14893 emit_note (NOTE_INSN_PROLOGUE_END);
14895 /* Find the "this" pointer. If the function returns a structure,
14896 the structure return pointer is in r3. */
14897 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14898 this = gen_rtx_REG (Pmode, 4);
14900 this = gen_rtx_REG (Pmode, 3);
14902 /* Apply the constant offset, if required. */
14905 rtx delta_rtx = GEN_INT (delta);
14906 emit_insn (TARGET_32BIT
14907 ? gen_addsi3 (this, this, delta_rtx)
14908 : gen_adddi3 (this, this, delta_rtx));
14911 /* Apply the offset from the vtable, if required. */
14914 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14915 rtx tmp = gen_rtx_REG (Pmode, 12);
14917 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14918 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14920 emit_insn (TARGET_32BIT
14921 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14922 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14923 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14927 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14929 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14931 emit_insn (TARGET_32BIT
14932 ? gen_addsi3 (this, this, tmp)
14933 : gen_adddi3 (this, this, tmp));
14936 /* Generate a tail call to the target function. */
14937 if (!TREE_USED (function))
14939 assemble_external (function);
14940 TREE_USED (function) = 1;
14942 funexp = XEXP (DECL_RTL (function), 0);
14943 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14946 if (MACHOPIC_INDIRECT)
14947 funexp = machopic_indirect_call_target (funexp);
14950 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14951 generate sibcall RTL explicitly to avoid constraint abort. */
14952 insn = emit_call_insn (
14953 gen_rtx_PARALLEL (VOIDmode,
14955 gen_rtx_CALL (VOIDmode,
14956 funexp, const0_rtx),
14957 gen_rtx_USE (VOIDmode, const0_rtx),
14958 gen_rtx_USE (VOIDmode,
14959 gen_rtx_REG (SImode,
14960 LINK_REGISTER_REGNUM)),
14961 gen_rtx_RETURN (VOIDmode))));
14962 SIBLING_CALL_P (insn) = 1;
14965 /* Run just enough of rest_of_compilation to get the insns emitted.
14966 There's not really enough bulk here to make other passes such as
14967 instruction scheduling worth while. Note that use_thunk calls
14968 assemble_start_function and assemble_end_function. */
14969 insn = get_insns ();
14970 insn_locators_initialize ();
14971 shorten_branches (insn);
14972 final_start_function (insn, file, 1);
14973 final (insn, file, 1, 0);
14974 final_end_function ();
14976 reload_completed = 0;
14977 epilogue_completed = 0;
14978 no_new_pseudos = 0;
14981 /* A quick summary of the various types of 'constant-pool tables'
14984 Target Flags Name One table per
14985 AIX (none) AIX TOC object file
14986 AIX -mfull-toc AIX TOC object file
14987 AIX -mminimal-toc AIX minimal TOC translation unit
14988 SVR4/EABI (none) SVR4 SDATA object file
14989 SVR4/EABI -fpic SVR4 pic object file
14990 SVR4/EABI -fPIC SVR4 PIC translation unit
14991 SVR4/EABI -mrelocatable EABI TOC function
14992 SVR4/EABI -maix AIX TOC object file
14993 SVR4/EABI -maix -mminimal-toc
14994 AIX minimal TOC translation unit
14996 Name Reg. Set by entries contains:
14997 made by addrs? fp? sum?
14999 AIX TOC 2 crt0 as Y option option
15000 AIX minimal TOC 30 prolog gcc Y Y option
15001 SVR4 SDATA 13 crt0 gcc N Y N
15002 SVR4 pic 30 prolog ld Y not yet N
15003 SVR4 PIC 30 prolog gcc Y option option
15004 EABI TOC 30 prolog gcc Y option option
15008 /* Hash functions for the hash table. */
15011 rs6000_hash_constant (rtx k)
15013 enum rtx_code code = GET_CODE (k);
15014 enum machine_mode mode = GET_MODE (k);
15015 unsigned result = (code << 3) ^ mode;
15016 const char *format;
15019 format = GET_RTX_FORMAT (code);
15020 flen = strlen (format);
15026 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15029 if (mode != VOIDmode)
15030 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15042 for (; fidx < flen; fidx++)
15043 switch (format[fidx])
15048 const char *str = XSTR (k, fidx);
15049 len = strlen (str);
15050 result = result * 613 + len;
15051 for (i = 0; i < len; i++)
15052 result = result * 613 + (unsigned) str[i];
15057 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15061 result = result * 613 + (unsigned) XINT (k, fidx);
15064 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15065 result = result * 613 + (unsigned) XWINT (k, fidx);
15069 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
15070 result = result * 613 + (unsigned) (XWINT (k, fidx)
15084 toc_hash_function (const void *hash_entry)
15086 const struct toc_hash_struct *thc =
15087 (const struct toc_hash_struct *) hash_entry;
15088 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15091 /* Compare H1 and H2 for equivalence. */
15094 toc_hash_eq (const void *h1, const void *h2)
15096 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15097 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15099 if (((const struct toc_hash_struct *) h1)->key_mode
15100 != ((const struct toc_hash_struct *) h2)->key_mode)
15103 return rtx_equal_p (r1, r2);
15106 /* These are the names given by the C++ front-end to vtables, and
15107 vtable-like objects. Ideally, this logic should not be here;
15108 instead, there should be some programmatic way of inquiring as
15109 to whether or not an object is a vtable. */
15111 #define VTABLE_NAME_P(NAME) \
15112 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15113 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15114 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15115 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15116 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15119 rs6000_output_symbol_ref (FILE *file, rtx x)
15121 /* Currently C++ toc references to vtables can be emitted before it
15122 is decided whether the vtable is public or private. If this is
15123 the case, then the linker will eventually complain that there is
15124 a reference to an unknown section. Thus, for vtables only,
15125 we emit the TOC reference to reference the symbol and not the
15127 const char *name = XSTR (x, 0);
15129 if (VTABLE_NAME_P (name))
15131 RS6000_OUTPUT_BASENAME (file, name);
15134 assemble_name (file, name);
15137 /* Output a TOC entry. We derive the entry name from what is being
15141 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15144 const char *name = buf;
15145 const char *real_name;
15152 /* When the linker won't eliminate them, don't output duplicate
15153 TOC entries (this happens on AIX if there is any kind of TOC,
15154 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15156 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15158 struct toc_hash_struct *h;
15161 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15162 time because GGC is not initialized at that point. */
15163 if (toc_hash_table == NULL)
15164 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15165 toc_hash_eq, NULL);
15167 h = ggc_alloc (sizeof (*h));
15169 h->key_mode = mode;
15170 h->labelno = labelno;
15172 found = htab_find_slot (toc_hash_table, h, 1);
15173 if (*found == NULL)
15175 else /* This is indeed a duplicate.
15176 Set this label equal to that label. */
15178 fputs ("\t.set ", file);
15179 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15180 fprintf (file, "%d,", labelno);
15181 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15182 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15188 /* If we're going to put a double constant in the TOC, make sure it's
15189 aligned properly when strict alignment is on. */
15190 if (GET_CODE (x) == CONST_DOUBLE
15191 && STRICT_ALIGNMENT
15192 && GET_MODE_BITSIZE (mode) >= 64
15193 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15194 ASM_OUTPUT_ALIGN (file, 3);
15197 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15199 /* Handle FP constants specially. Note that if we have a minimal
15200 TOC, things we put here aren't actually in the TOC, so we can allow
15202 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15204 REAL_VALUE_TYPE rv;
15207 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15208 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15212 if (TARGET_MINIMAL_TOC)
15213 fputs (DOUBLE_INT_ASM_OP, file);
15215 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15216 k[0] & 0xffffffff, k[1] & 0xffffffff,
15217 k[2] & 0xffffffff, k[3] & 0xffffffff);
15218 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15219 k[0] & 0xffffffff, k[1] & 0xffffffff,
15220 k[2] & 0xffffffff, k[3] & 0xffffffff);
15225 if (TARGET_MINIMAL_TOC)
15226 fputs ("\t.long ", file);
15228 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15229 k[0] & 0xffffffff, k[1] & 0xffffffff,
15230 k[2] & 0xffffffff, k[3] & 0xffffffff);
15231 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15232 k[0] & 0xffffffff, k[1] & 0xffffffff,
15233 k[2] & 0xffffffff, k[3] & 0xffffffff);
15237 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15239 REAL_VALUE_TYPE rv;
15242 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15243 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15247 if (TARGET_MINIMAL_TOC)
15248 fputs (DOUBLE_INT_ASM_OP, file);
15250 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15251 k[0] & 0xffffffff, k[1] & 0xffffffff);
15252 fprintf (file, "0x%lx%08lx\n",
15253 k[0] & 0xffffffff, k[1] & 0xffffffff);
15258 if (TARGET_MINIMAL_TOC)
15259 fputs ("\t.long ", file);
15261 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15262 k[0] & 0xffffffff, k[1] & 0xffffffff);
15263 fprintf (file, "0x%lx,0x%lx\n",
15264 k[0] & 0xffffffff, k[1] & 0xffffffff);
15268 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15270 REAL_VALUE_TYPE rv;
15273 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15274 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15278 if (TARGET_MINIMAL_TOC)
15279 fputs (DOUBLE_INT_ASM_OP, file);
15281 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15282 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15287 if (TARGET_MINIMAL_TOC)
15288 fputs ("\t.long ", file);
15290 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15291 fprintf (file, "0x%lx\n", l & 0xffffffff);
15295 else if (GET_MODE (x) == VOIDmode
15296 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15298 unsigned HOST_WIDE_INT low;
15299 HOST_WIDE_INT high;
15301 if (GET_CODE (x) == CONST_DOUBLE)
15303 low = CONST_DOUBLE_LOW (x);
15304 high = CONST_DOUBLE_HIGH (x);
15307 #if HOST_BITS_PER_WIDE_INT == 32
15310 high = (low & 0x80000000) ? ~0 : 0;
15314 low = INTVAL (x) & 0xffffffff;
15315 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15319 /* TOC entries are always Pmode-sized, but since this
15320 is a bigendian machine then if we're putting smaller
15321 integer constants in the TOC we have to pad them.
15322 (This is still a win over putting the constants in
15323 a separate constant pool, because then we'd have
15324 to have both a TOC entry _and_ the actual constant.)
15326 For a 32-bit target, CONST_INT values are loaded and shifted
15327 entirely within `low' and can be stored in one TOC entry. */
15329 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
15330 abort ();/* It would be easy to make this work, but it doesn't now. */
15332 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15334 #if HOST_BITS_PER_WIDE_INT == 32
15335 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15336 POINTER_SIZE, &low, &high, 0);
15339 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15340 high = (HOST_WIDE_INT) low >> 32;
15347 if (TARGET_MINIMAL_TOC)
15348 fputs (DOUBLE_INT_ASM_OP, file);
15350 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15351 (long) high & 0xffffffff, (long) low & 0xffffffff);
15352 fprintf (file, "0x%lx%08lx\n",
15353 (long) high & 0xffffffff, (long) low & 0xffffffff);
15358 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15360 if (TARGET_MINIMAL_TOC)
15361 fputs ("\t.long ", file);
15363 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15364 (long) high & 0xffffffff, (long) low & 0xffffffff);
15365 fprintf (file, "0x%lx,0x%lx\n",
15366 (long) high & 0xffffffff, (long) low & 0xffffffff);
15370 if (TARGET_MINIMAL_TOC)
15371 fputs ("\t.long ", file);
15373 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15374 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15380 if (GET_CODE (x) == CONST)
15382 if (GET_CODE (XEXP (x, 0)) != PLUS)
15385 base = XEXP (XEXP (x, 0), 0);
15386 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15389 if (GET_CODE (base) == SYMBOL_REF)
15390 name = XSTR (base, 0);
15391 else if (GET_CODE (base) == LABEL_REF)
15392 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
15393 else if (GET_CODE (base) == CODE_LABEL)
15394 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15398 real_name = (*targetm.strip_name_encoding) (name);
15399 if (TARGET_MINIMAL_TOC)
15400 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15403 fprintf (file, "\t.tc %s", real_name);
15406 fprintf (file, ".N%d", - offset);
15408 fprintf (file, ".P%d", offset);
15410 fputs ("[TC],", file);
15413 /* Currently C++ toc references to vtables can be emitted before it
15414 is decided whether the vtable is public or private. If this is
15415 the case, then the linker will eventually complain that there is
15416 a TOC reference to an unknown section. Thus, for vtables only,
15417 we emit the TOC reference to reference the symbol and not the
15419 if (VTABLE_NAME_P (name))
15421 RS6000_OUTPUT_BASENAME (file, name);
15423 fprintf (file, "%d", offset);
15424 else if (offset > 0)
15425 fprintf (file, "+%d", offset);
15428 output_addr_const (file, x);
15432 /* Output an assembler pseudo-op to write an ASCII string of N characters
15433 starting at P to FILE.
15435 On the RS/6000, we have to do this using the .byte operation and
15436 write out special characters outside the quoted string.
15437 Also, the assembler is broken; very long strings are truncated,
15438 so we must artificially break them up early. */
15441 output_ascii (FILE *file, const char *p, int n)
15444 int i, count_string;
15445 const char *for_string = "\t.byte \"";
15446 const char *for_decimal = "\t.byte ";
15447 const char *to_close = NULL;
15450 for (i = 0; i < n; i++)
15453 if (c >= ' ' && c < 0177)
15456 fputs (for_string, file);
15459 /* Write two quotes to get one. */
15467 for_decimal = "\"\n\t.byte ";
15471 if (count_string >= 512)
15473 fputs (to_close, file);
15475 for_string = "\t.byte \"";
15476 for_decimal = "\t.byte ";
15484 fputs (for_decimal, file);
15485 fprintf (file, "%d", c);
15487 for_string = "\n\t.byte \"";
15488 for_decimal = ", ";
15494 /* Now close the string if we have written one. Then end the line. */
15496 fputs (to_close, file);
15499 /* Generate a unique section name for FILENAME for a section type
15500 represented by SECTION_DESC. Output goes into BUF.
15502 SECTION_DESC can be any string, as long as it is different for each
15503 possible section type.
15505 We name the section in the same manner as xlc. The name begins with an
15506 underscore followed by the filename (after stripping any leading directory
15507 names) with the last period replaced by the string SECTION_DESC. If
15508 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15512 rs6000_gen_section_name (char **buf, const char *filename,
15513 const char *section_desc)
15515 const char *q, *after_last_slash, *last_period = 0;
15519 after_last_slash = filename;
15520 for (q = filename; *q; q++)
15523 after_last_slash = q + 1;
15524 else if (*q == '.')
15528 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15529 *buf = (char *) xmalloc (len);
15534 for (q = after_last_slash; *q; q++)
15536 if (q == last_period)
15538 strcpy (p, section_desc);
15539 p += strlen (section_desc);
15543 else if (ISALNUM (*q))
15547 if (last_period == 0)
15548 strcpy (p, section_desc);
15553 /* Emit profile function. */
15556 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
15558 if (TARGET_PROFILE_KERNEL)
15561 if (DEFAULT_ABI == ABI_AIX)
15563 #ifndef NO_PROFILE_COUNTERS
15564 # define NO_PROFILE_COUNTERS 0
15566 if (NO_PROFILE_COUNTERS)
15567 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15571 const char *label_name;
15574 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15575 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15576 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15578 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15582 else if (DEFAULT_ABI == ABI_DARWIN)
15584 const char *mcount_name = RS6000_MCOUNT;
15585 int caller_addr_regno = LINK_REGISTER_REGNUM;
15587 /* Be conservative and always set this, at least for now. */
15588 current_function_uses_pic_offset_table = 1;
15591 /* For PIC code, set up a stub and collect the caller's address
15592 from r0, which is where the prologue puts it. */
15593 if (MACHOPIC_INDIRECT
15594 && current_function_uses_pic_offset_table)
15595 caller_addr_regno = 0;
15597 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15599 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15603 /* Write function profiler code. */
15606 output_function_profiler (FILE *file, int labelno)
15611 switch (DEFAULT_ABI)
15620 warning ("no profiling of 64-bit code for this ABI");
15623 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15624 fprintf (file, "\tmflr %s\n", reg_names[0]);
15627 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
15628 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15629 reg_names[0], save_lr, reg_names[1]);
15630 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15631 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
15632 assemble_name (file, buf);
15633 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
15635 else if (flag_pic > 1)
15637 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15638 reg_names[0], save_lr, reg_names[1]);
15639 /* Now, we need to get the address of the label. */
15640 fputs ("\tbl 1f\n\t.long ", file);
15641 assemble_name (file, buf);
15642 fputs ("-.\n1:", file);
15643 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
15644 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
15645 reg_names[0], reg_names[11]);
15646 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15647 reg_names[0], reg_names[0], reg_names[11]);
15651 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
15652 assemble_name (file, buf);
15653 fputs ("@ha\n", file);
15654 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15655 reg_names[0], save_lr, reg_names[1]);
15656 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
15657 assemble_name (file, buf);
15658 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
15661 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
15662 fprintf (file, "\tbl %s%s\n",
15663 RS6000_MCOUNT, flag_pic ? "@plt" : "");
15668 if (!TARGET_PROFILE_KERNEL)
15670 /* Don't do anything, done in output_profile_hook (). */
15677 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15678 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15680 if (cfun->static_chain_decl != NULL)
15682 asm_fprintf (file, "\tstd %s,24(%s)\n",
15683 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15684 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15685 asm_fprintf (file, "\tld %s,24(%s)\n",
15686 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15689 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15696 /* Power4 load update and store update instructions are cracked into a
15697 load or store and an integer insn which are executed in the same cycle.
15698 Branches have their own dispatch slot which does not count against the
15699 GCC issue rate, but it changes the program flow so there are no other
15700 instructions to issue in this cycle. */
15703 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
15704 int verbose ATTRIBUTE_UNUSED,
15705 rtx insn, int more)
15707 if (GET_CODE (PATTERN (insn)) == USE
15708 || GET_CODE (PATTERN (insn)) == CLOBBER)
15711 if (rs6000_sched_groups)
15713 if (is_microcoded_insn (insn))
15715 else if (is_cracked_insn (insn))
15716 return more > 2 ? more - 2 : 0;
15722 /* Adjust the cost of a scheduling dependency. Return the new cost of
15723 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15726 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
15728 if (! recog_memoized (insn))
15731 if (REG_NOTE_KIND (link) != 0)
15734 if (REG_NOTE_KIND (link) == 0)
15736 /* Data dependency; DEP_INSN writes a register that INSN reads
15737 some cycles later. */
15738 switch (get_attr_type (insn))
15741 /* Tell the first scheduling pass about the latency between
15742 a mtctr and bctr (and mtlr and br/blr). The first
15743 scheduling pass will not know about this latency since
15744 the mtctr instruction, which has the latency associated
15745 to it, will be generated by reload. */
15746 return TARGET_POWER ? 5 : 4;
15748 /* Leave some extra cycles between a compare and its
15749 dependent branch, to inhibit expensive mispredicts. */
15750 if ((rs6000_cpu_attr == CPU_PPC603
15751 || rs6000_cpu_attr == CPU_PPC604
15752 || rs6000_cpu_attr == CPU_PPC604E
15753 || rs6000_cpu_attr == CPU_PPC620
15754 || rs6000_cpu_attr == CPU_PPC630
15755 || rs6000_cpu_attr == CPU_PPC750
15756 || rs6000_cpu_attr == CPU_PPC7400
15757 || rs6000_cpu_attr == CPU_PPC7450
15758 || rs6000_cpu_attr == CPU_POWER4
15759 || rs6000_cpu_attr == CPU_POWER5)
15760 && recog_memoized (dep_insn)
15761 && (INSN_CODE (dep_insn) >= 0)
15762 && (get_attr_type (dep_insn) == TYPE_CMP
15763 || get_attr_type (dep_insn) == TYPE_COMPARE
15764 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
15765 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
15766 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
15767 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
15768 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
15769 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
15774 /* Fall out to return default cost. */
15780 /* The function returns a true if INSN is microcoded.
15781 Return false otherwise. */
15784 is_microcoded_insn (rtx insn)
15786 if (!insn || !INSN_P (insn)
15787 || GET_CODE (PATTERN (insn)) == USE
15788 || GET_CODE (PATTERN (insn)) == CLOBBER)
15791 if (rs6000_sched_groups)
15793 enum attr_type type = get_attr_type (insn);
15794 if (type == TYPE_LOAD_EXT_U
15795 || type == TYPE_LOAD_EXT_UX
15796 || type == TYPE_LOAD_UX
15797 || type == TYPE_STORE_UX
15798 || type == TYPE_MFCR)
15805 /* The function returns a nonzero value if INSN can be scheduled only
15806 as the first insn in a dispatch group ("dispatch-slot restricted").
15807 In this case, the returned value indicates how many dispatch slots
15808 the insn occupies (at the beginning of the group).
15809 Return 0 otherwise. */
15812 is_dispatch_slot_restricted (rtx insn)
15814 enum attr_type type;
15816 if (!rs6000_sched_groups)
15820 || insn == NULL_RTX
15821 || GET_CODE (insn) == NOTE
15822 || GET_CODE (PATTERN (insn)) == USE
15823 || GET_CODE (PATTERN (insn)) == CLOBBER)
15826 type = get_attr_type (insn);
15833 case TYPE_DELAYED_CR:
15834 case TYPE_CR_LOGICAL:
15842 if (rs6000_cpu == PROCESSOR_POWER5
15843 && is_cracked_insn (insn))
15849 /* The function returns true if INSN is cracked into 2 instructions
15850 by the processor (and therefore occupies 2 issue slots). */
15853 is_cracked_insn (rtx insn)
15855 if (!insn || !INSN_P (insn)
15856 || GET_CODE (PATTERN (insn)) == USE
15857 || GET_CODE (PATTERN (insn)) == CLOBBER)
15860 if (rs6000_sched_groups)
15862 enum attr_type type = get_attr_type (insn);
15863 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
15864 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15865 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15866 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15867 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15868 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15869 || type == TYPE_IDIV || type == TYPE_LDIV
15870 || type == TYPE_INSERT_WORD)
15877 /* The function returns true if INSN can be issued only from
15878 the branch slot. */
15881 is_branch_slot_insn (rtx insn)
15883 if (!insn || !INSN_P (insn)
15884 || GET_CODE (PATTERN (insn)) == USE
15885 || GET_CODE (PATTERN (insn)) == CLOBBER)
15888 if (rs6000_sched_groups)
15890 enum attr_type type = get_attr_type (insn);
15891 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
15899 /* A C statement (sans semicolon) to update the integer scheduling
15900 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15901 INSN earlier, reduce the priority to execute INSN later. Do not
15902 define this macro if you do not need to adjust the scheduling
15903 priorities of insns. */
15906 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15908 /* On machines (like the 750) which have asymmetric integer units,
15909 where one integer unit can do multiply and divides and the other
15910 can't, reduce the priority of multiply/divide so it is scheduled
15911 before other integer operations. */
15914 if (! INSN_P (insn))
15917 if (GET_CODE (PATTERN (insn)) == USE)
15920 switch (rs6000_cpu_attr) {
15922 switch (get_attr_type (insn))
15929 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15930 priority, priority);
15931 if (priority >= 0 && priority < 0x01000000)
15938 if (is_dispatch_slot_restricted (insn)
15939 && reload_completed
15940 && current_sched_info->sched_max_insns_priority
15941 && rs6000_sched_restricted_insns_priority)
15944 /* Prioritize insns that can be dispatched only in the first
15946 if (rs6000_sched_restricted_insns_priority == 1)
15947 /* Attach highest priority to insn. This means that in
15948 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15949 precede 'priority' (critical path) considerations. */
15950 return current_sched_info->sched_max_insns_priority;
15951 else if (rs6000_sched_restricted_insns_priority == 2)
15952 /* Increase priority of insn by a minimal amount. This means that in
15953 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15954 considerations precede dispatch-slot restriction considerations. */
15955 return (priority + 1);
15961 /* Return how many instructions the machine can issue per cycle. */
15964 rs6000_issue_rate (void)
15966 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15967 if (!reload_completed)
15970 switch (rs6000_cpu_attr) {
15971 case CPU_RIOS1: /* ? */
15973 case CPU_PPC601: /* ? */
15996 /* Return how many instructions to look ahead for better insn
16000 rs6000_use_sched_lookahead (void)
16002 if (rs6000_cpu_attr == CPU_PPC8540)
16007 /* Determine is PAT refers to memory. */
16010 is_mem_ref (rtx pat)
16016 if (GET_CODE (pat) == MEM)
16019 /* Recursively process the pattern. */
16020 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16022 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16025 ret |= is_mem_ref (XEXP (pat, i));
16026 else if (fmt[i] == 'E')
16027 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16028 ret |= is_mem_ref (XVECEXP (pat, i, j));
16034 /* Determine if PAT is a PATTERN of a load insn. */
16037 is_load_insn1 (rtx pat)
16039 if (!pat || pat == NULL_RTX)
16042 if (GET_CODE (pat) == SET)
16043 return is_mem_ref (SET_SRC (pat));
16045 if (GET_CODE (pat) == PARALLEL)
16049 for (i = 0; i < XVECLEN (pat, 0); i++)
16050 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16057 /* Determine if INSN loads from memory. */
16060 is_load_insn (rtx insn)
16062 if (!insn || !INSN_P (insn))
16065 if (GET_CODE (insn) == CALL_INSN)
16068 return is_load_insn1 (PATTERN (insn));
16071 /* Determine if PAT is a PATTERN of a store insn. */
16074 is_store_insn1 (rtx pat)
16076 if (!pat || pat == NULL_RTX)
16079 if (GET_CODE (pat) == SET)
16080 return is_mem_ref (SET_DEST (pat));
16082 if (GET_CODE (pat) == PARALLEL)
16086 for (i = 0; i < XVECLEN (pat, 0); i++)
16087 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16094 /* Determine if INSN stores to memory. */
16097 is_store_insn (rtx insn)
16099 if (!insn || !INSN_P (insn))
16102 return is_store_insn1 (PATTERN (insn));
16105 /* Returns whether the dependence between INSN and NEXT is considered
16106 costly by the given target. */
16109 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16112 /* If the flag is not enbled - no dependence is considered costly;
16113 allow all dependent insns in the same group.
16114 This is the most aggressive option. */
16115 if (rs6000_sched_costly_dep == no_dep_costly)
16118 /* If the flag is set to 1 - a dependence is always considered costly;
16119 do not allow dependent instructions in the same group.
16120 This is the most conservative option. */
16121 if (rs6000_sched_costly_dep == all_deps_costly)
16124 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16125 && is_load_insn (next)
16126 && is_store_insn (insn))
16127 /* Prevent load after store in the same group. */
16130 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16131 && is_load_insn (next)
16132 && is_store_insn (insn)
16133 && (!link || (int) REG_NOTE_KIND (link) == 0))
16134 /* Prevent load after store in the same group if it is a true
16138 /* The flag is set to X; dependences with latency >= X are considered costly,
16139 and will not be scheduled in the same group. */
16140 if (rs6000_sched_costly_dep <= max_dep_latency
16141 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16147 /* Return the next insn after INSN that is found before TAIL is reached,
16148 skipping any "non-active" insns - insns that will not actually occupy
16149 an issue slot. Return NULL_RTX if such an insn is not found. */
16152 get_next_active_insn (rtx insn, rtx tail)
16156 if (!insn || insn == tail)
16159 next_insn = NEXT_INSN (insn);
16162 && next_insn != tail
16163 && (GET_CODE(next_insn) == NOTE
16164 || GET_CODE (PATTERN (next_insn)) == USE
16165 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16167 next_insn = NEXT_INSN (next_insn);
16170 if (!next_insn || next_insn == tail)
16176 /* Return whether the presence of INSN causes a dispatch group termination
16177 of group WHICH_GROUP.
16179 If WHICH_GROUP == current_group, this function will return true if INSN
16180 causes the termination of the current group (i.e, the dispatch group to
16181 which INSN belongs). This means that INSN will be the last insn in the
16182 group it belongs to.
16184 If WHICH_GROUP == previous_group, this function will return true if INSN
16185 causes the termination of the previous group (i.e, the dispatch group that
16186 precedes the group to which INSN belongs). This means that INSN will be
16187 the first insn in the group it belongs to). */
16190 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16192 enum attr_type type;
16197 type = get_attr_type (insn);
16199 if (is_microcoded_insn (insn))
16202 if (which_group == current_group)
16204 if (is_branch_slot_insn (insn))
16208 else if (which_group == previous_group)
16210 if (is_dispatch_slot_restricted (insn))
16218 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16219 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16222 is_costly_group (rtx *group_insns, rtx next_insn)
16227 int issue_rate = rs6000_issue_rate ();
16229 for (i = 0; i < issue_rate; i++)
16231 rtx insn = group_insns[i];
16234 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16236 rtx next = XEXP (link, 0);
16237 if (next == next_insn)
16239 cost = insn_cost (insn, link, next_insn);
16240 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16249 /* Utility of the function redefine_groups.
16250 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16251 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16252 to keep it "far" (in a separate group) from GROUP_INSNS, following
16253 one of the following schemes, depending on the value of the flag
16254 -minsert_sched_nops = X:
16255 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16256 in order to force NEXT_INSN into a separate group.
16257 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16258 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16259 insertion (has a group just ended, how many vacant issue slots remain in the
16260 last group, and how many dispatch groups were encountered so far). */
16263 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16264 rtx next_insn, bool *group_end, int can_issue_more,
16269 int issue_rate = rs6000_issue_rate ();
16270 bool end = *group_end;
16273 if (next_insn == NULL_RTX)
16274 return can_issue_more;
16276 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16277 return can_issue_more;
16279 force = is_costly_group (group_insns, next_insn);
16281 return can_issue_more;
16283 if (sched_verbose > 6)
16284 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16285 *group_count ,can_issue_more);
16287 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16290 can_issue_more = 0;
16292 /* Since only a branch can be issued in the last issue_slot, it is
16293 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16294 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16295 in this case the last nop will start a new group and the branch
16296 will be forced to the new group. */
16297 if (can_issue_more && !is_branch_slot_insn (next_insn))
16300 while (can_issue_more > 0)
16303 emit_insn_before (nop, next_insn);
16311 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16313 int n_nops = rs6000_sched_insert_nops;
16315 /* Nops can't be issued from the branch slot, so the effective
16316 issue_rate for nops is 'issue_rate - 1'. */
16317 if (can_issue_more == 0)
16318 can_issue_more = issue_rate;
16320 if (can_issue_more == 0)
16322 can_issue_more = issue_rate - 1;
16325 for (i = 0; i < issue_rate; i++)
16327 group_insns[i] = 0;
16334 emit_insn_before (nop, next_insn);
16335 if (can_issue_more == issue_rate - 1) /* new group begins */
16338 if (can_issue_more == 0)
16340 can_issue_more = issue_rate - 1;
16343 for (i = 0; i < issue_rate; i++)
16345 group_insns[i] = 0;
16351 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16354 /* Is next_insn going to start a new group? */
16357 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16358 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16359 || (can_issue_more < issue_rate &&
16360 insn_terminates_group_p (next_insn, previous_group)));
16361 if (*group_end && end)
16364 if (sched_verbose > 6)
16365 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16366 *group_count, can_issue_more);
16367 return can_issue_more;
16370 return can_issue_more;
16373 /* This function tries to synch the dispatch groups that the compiler "sees"
16374 with the dispatch groups that the processor dispatcher is expected to
16375 form in practice. It tries to achieve this synchronization by forcing the
16376 estimated processor grouping on the compiler (as opposed to the function
16377 'pad_goups' which tries to force the scheduler's grouping on the processor).
16379 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16380 examines the (estimated) dispatch groups that will be formed by the processor
16381 dispatcher. It marks these group boundaries to reflect the estimated
16382 processor grouping, overriding the grouping that the scheduler had marked.
16383 Depending on the value of the flag '-minsert-sched-nops' this function can
16384 force certain insns into separate groups or force a certain distance between
16385 them by inserting nops, for example, if there exists a "costly dependence"
16388 The function estimates the group boundaries that the processor will form as
16389 folllows: It keeps track of how many vacant issue slots are available after
16390 each insn. A subsequent insn will start a new group if one of the following
16392 - no more vacant issue slots remain in the current dispatch group.
16393 - only the last issue slot, which is the branch slot, is vacant, but the next
16394 insn is not a branch.
16395 - only the last 2 or less issue slots, including the branch slot, are vacant,
16396 which means that a cracked insn (which occupies two issue slots) can't be
16397 issued in this group.
16398 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16399 start a new group. */
16402 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16404 rtx insn, next_insn;
16406 int can_issue_more;
16409 int group_count = 0;
16413 issue_rate = rs6000_issue_rate ();
16414 group_insns = alloca (issue_rate * sizeof (rtx));
16415 for (i = 0; i < issue_rate; i++)
16417 group_insns[i] = 0;
16419 can_issue_more = issue_rate;
16421 insn = get_next_active_insn (prev_head_insn, tail);
16424 while (insn != NULL_RTX)
16426 slot = (issue_rate - can_issue_more);
16427 group_insns[slot] = insn;
16429 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16430 if (insn_terminates_group_p (insn, current_group))
16431 can_issue_more = 0;
16433 next_insn = get_next_active_insn (insn, tail);
16434 if (next_insn == NULL_RTX)
16435 return group_count + 1;
16437 /* Is next_insn going to start a new group? */
16439 = (can_issue_more == 0
16440 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16441 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16442 || (can_issue_more < issue_rate &&
16443 insn_terminates_group_p (next_insn, previous_group)));
16445 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16446 next_insn, &group_end, can_issue_more,
16452 can_issue_more = 0;
16453 for (i = 0; i < issue_rate; i++)
16455 group_insns[i] = 0;
16459 if (GET_MODE (next_insn) == TImode && can_issue_more)
16460 PUT_MODE(next_insn, VOIDmode);
16461 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16462 PUT_MODE (next_insn, TImode);
16465 if (can_issue_more == 0)
16466 can_issue_more = issue_rate;
16469 return group_count;
16472 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16473 dispatch group boundaries that the scheduler had marked. Pad with nops
16474 any dispatch groups which have vacant issue slots, in order to force the
16475 scheduler's grouping on the processor dispatcher. The function
16476 returns the number of dispatch groups found. */
16479 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16481 rtx insn, next_insn;
16484 int can_issue_more;
16486 int group_count = 0;
16488 /* Initialize issue_rate. */
16489 issue_rate = rs6000_issue_rate ();
16490 can_issue_more = issue_rate;
16492 insn = get_next_active_insn (prev_head_insn, tail);
16493 next_insn = get_next_active_insn (insn, tail);
16495 while (insn != NULL_RTX)
16498 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16500 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16502 if (next_insn == NULL_RTX)
16507 /* If the scheduler had marked group termination at this location
16508 (between insn and next_indn), and neither insn nor next_insn will
16509 force group termination, pad the group with nops to force group
16512 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16513 && !insn_terminates_group_p (insn, current_group)
16514 && !insn_terminates_group_p (next_insn, previous_group))
16516 if (!is_branch_slot_insn(next_insn))
16519 while (can_issue_more)
16522 emit_insn_before (nop, next_insn);
16527 can_issue_more = issue_rate;
16532 next_insn = get_next_active_insn (insn, tail);
16535 return group_count;
16538 /* The following function is called at the end of scheduling BB.
16539 After reload, it inserts nops at insn group bundling. */
16542 rs6000_sched_finish (FILE *dump, int sched_verbose)
16547 fprintf (dump, "=== Finishing schedule.\n");
16549 if (reload_completed && rs6000_sched_groups)
16551 if (rs6000_sched_insert_nops == sched_finish_none)
16554 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
16555 n_groups = pad_groups (dump, sched_verbose,
16556 current_sched_info->prev_head,
16557 current_sched_info->next_tail);
16559 n_groups = redefine_groups (dump, sched_verbose,
16560 current_sched_info->prev_head,
16561 current_sched_info->next_tail);
16563 if (sched_verbose >= 6)
16565 fprintf (dump, "ngroups = %d\n", n_groups);
16566 print_rtl (dump, current_sched_info->prev_head);
16567 fprintf (dump, "Done finish_sched\n");
16572 /* Length in units of the trampoline for entering a nested function. */
16575 rs6000_trampoline_size (void)
16579 switch (DEFAULT_ABI)
16585 ret = (TARGET_32BIT) ? 12 : 24;
16590 ret = (TARGET_32BIT) ? 40 : 48;
16597 /* Emit RTL insns to initialize the variable parts of a trampoline.
16598 FNADDR is an RTX for the address of the function's pure code.
16599 CXT is an RTX for the static chain value for the function. */
16602 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
16604 enum machine_mode pmode = Pmode;
16605 int regsize = (TARGET_32BIT) ? 4 : 8;
16606 rtx ctx_reg = force_reg (pmode, cxt);
16608 switch (DEFAULT_ABI)
16613 /* Macros to shorten the code expansions below. */
16614 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16615 #define MEM_PLUS(addr,offset) \
16616 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16618 /* Under AIX, just build the 3 word function descriptor */
16621 rtx fn_reg = gen_reg_rtx (pmode);
16622 rtx toc_reg = gen_reg_rtx (pmode);
16623 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
16624 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
16625 emit_move_insn (MEM_DEREF (addr), fn_reg);
16626 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16627 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16631 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16634 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
16635 FALSE, VOIDmode, 4,
16637 GEN_INT (rs6000_trampoline_size ()), SImode,
16647 /* Table of valid machine attributes. */
16649 const struct attribute_spec rs6000_attribute_table[] =
16651 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
16652 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
16653 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16654 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16655 #ifdef SUBTARGET_ATTRIBUTE_TABLE
16656 SUBTARGET_ATTRIBUTE_TABLE,
16658 { NULL, 0, 0, false, false, false, NULL }
16661 /* Handle the "altivec" attribute. The attribute may have
16662 arguments as follows:
16664 __attribute__((altivec(vector__)))
16665 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16666 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16668 and may appear more than once (e.g., 'vector bool char') in a
16669 given declaration. */
16672 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
16673 int flags ATTRIBUTE_UNUSED,
16674 bool *no_add_attrs)
16676 tree type = *node, result = NULL_TREE;
16677 enum machine_mode mode;
16680 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
16681 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
16682 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
16685 while (POINTER_TYPE_P (type)
16686 || TREE_CODE (type) == FUNCTION_TYPE
16687 || TREE_CODE (type) == METHOD_TYPE
16688 || TREE_CODE (type) == ARRAY_TYPE)
16689 type = TREE_TYPE (type);
16691 mode = TYPE_MODE (type);
16693 if (rs6000_warn_altivec_long
16694 && (type == long_unsigned_type_node || type == long_integer_type_node))
16695 warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
16697 switch (altivec_type)
16700 unsigned_p = TYPE_UNSIGNED (type);
16704 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
16707 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
16710 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
16712 case SFmode: result = V4SF_type_node; break;
16713 /* If the user says 'vector int bool', we may be handed the 'bool'
16714 attribute _before_ the 'vector' attribute, and so select the
16715 proper type in the 'b' case below. */
16716 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
16724 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
16725 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
16726 case QImode: case V16QImode: result = bool_V16QI_type_node;
16733 case V8HImode: result = pixel_V8HI_type_node;
16739 if (result && result != type && TYPE_READONLY (type))
16740 result = build_qualified_type (result, TYPE_QUAL_CONST);
16742 *no_add_attrs = true; /* No need to hang on to the attribute. */
16745 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
16747 *node = reconstruct_complex_type (*node, result);
16752 /* AltiVec defines four built-in scalar types that serve as vector
16753 elements; we must teach the compiler how to mangle them. */
16755 static const char *
16756 rs6000_mangle_fundamental_type (tree type)
16758 if (type == bool_char_type_node) return "U6__boolc";
16759 if (type == bool_short_type_node) return "U6__bools";
16760 if (type == pixel_type_node) return "u7__pixel";
16761 if (type == bool_int_type_node) return "U6__booli";
16763 /* For all other types, use normal C++ mangling. */
16767 /* Handle a "longcall" or "shortcall" attribute; arguments as in
16768 struct attribute_spec.handler. */
16771 rs6000_handle_longcall_attribute (tree *node, tree name,
16772 tree args ATTRIBUTE_UNUSED,
16773 int flags ATTRIBUTE_UNUSED,
16774 bool *no_add_attrs)
16776 if (TREE_CODE (*node) != FUNCTION_TYPE
16777 && TREE_CODE (*node) != FIELD_DECL
16778 && TREE_CODE (*node) != TYPE_DECL)
16780 warning ("`%s' attribute only applies to functions",
16781 IDENTIFIER_POINTER (name));
16782 *no_add_attrs = true;
16788 /* Set longcall attributes on all functions declared when
16789 rs6000_default_long_calls is true. */
16791 rs6000_set_default_type_attributes (tree type)
16793 if (rs6000_default_long_calls
16794 && (TREE_CODE (type) == FUNCTION_TYPE
16795 || TREE_CODE (type) == METHOD_TYPE))
16796 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
16798 TYPE_ATTRIBUTES (type));
16801 /* Return a reference suitable for calling a function with the
16802 longcall attribute. */
16805 rs6000_longcall_ref (rtx call_ref)
16807 const char *call_name;
16810 if (GET_CODE (call_ref) != SYMBOL_REF)
16813 /* System V adds '.' to the internal name, so skip them. */
16814 call_name = XSTR (call_ref, 0);
16815 if (*call_name == '.')
16817 while (*call_name == '.')
16820 node = get_identifier (call_name);
16821 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
16824 return force_reg (Pmode, call_ref);
16827 #ifdef USING_ELFOS_H
16829 /* A C statement or statements to switch to the appropriate section
16830 for output of RTX in mode MODE. You can assume that RTX is some
16831 kind of constant in RTL. The argument MODE is redundant except in
16832 the case of a `const_int' rtx. Select the section by calling
16833 `text_section' or one of the alternatives for other sections.
16835 Do not define this macro if you put all constants in the read-only
16839 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
16840 unsigned HOST_WIDE_INT align)
16842 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16845 default_elf_select_rtx_section (mode, x, align);
16848 /* A C statement or statements to switch to the appropriate
16849 section for output of DECL. DECL is either a `VAR_DECL' node
16850 or a constant of some sort. RELOC indicates whether forming
16851 the initial value of DECL requires link-time relocations. */
16854 rs6000_elf_select_section (tree decl, int reloc,
16855 unsigned HOST_WIDE_INT align)
16857 /* Pretend that we're always building for a shared library when
16858 ABI_AIX, because otherwise we end up with dynamic relocations
16859 in read-only sections. This happens for function pointers,
16860 references to vtables in typeinfo, and probably other cases. */
16861 default_elf_select_section_1 (decl, reloc, align,
16862 flag_pic || DEFAULT_ABI == ABI_AIX);
16865 /* A C statement to build up a unique section name, expressed as a
16866 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16867 RELOC indicates whether the initial value of EXP requires
16868 link-time relocations. If you do not define this macro, GCC will use
16869 the symbol name prefixed by `.' as the section name. Note - this
16870 macro can now be called for uninitialized data items as well as
16871 initialized data and functions. */
16874 rs6000_elf_unique_section (tree decl, int reloc)
16876 /* As above, pretend that we're always building for a shared library
16877 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16878 default_unique_section_1 (decl, reloc,
16879 flag_pic || DEFAULT_ABI == ABI_AIX);
16882 /* For a SYMBOL_REF, set generic flags and then perform some
16883 target-specific processing.
16885 When the AIX ABI is requested on a non-AIX system, replace the
16886 function name with the real name (with a leading .) rather than the
16887 function descriptor name. This saves a lot of overriding code to
16888 read the prefixes. */
16891 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16893 default_encode_section_info (decl, rtl, first);
16896 && TREE_CODE (decl) == FUNCTION_DECL
16898 && DEFAULT_ABI == ABI_AIX)
16900 rtx sym_ref = XEXP (rtl, 0);
16901 size_t len = strlen (XSTR (sym_ref, 0));
16902 char *str = alloca (len + 2);
16904 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16905 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16910 rs6000_elf_in_small_data_p (tree decl)
16912 if (rs6000_sdata == SDATA_NONE)
16915 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16917 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16918 if (strcmp (section, ".sdata") == 0
16919 || strcmp (section, ".sdata2") == 0
16920 || strcmp (section, ".sbss") == 0
16921 || strcmp (section, ".sbss2") == 0
16922 || strcmp (section, ".PPC.EMB.sdata0") == 0
16923 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16928 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16931 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16932 /* If it's not public, and we're not going to reference it there,
16933 there's no need to put it in the small data section. */
16934 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16941 #endif /* USING_ELFOS_H */
16944 /* Return a REG that occurs in ADDR with coefficient 1.
16945 ADDR can be effectively incremented by incrementing REG.
16947 r0 is special and we must not select it as an address
16948 register by this routine since our caller will try to
16949 increment the returned register via an "la" instruction. */
16952 find_addr_reg (rtx addr)
16954 while (GET_CODE (addr) == PLUS)
16956 if (GET_CODE (XEXP (addr, 0)) == REG
16957 && REGNO (XEXP (addr, 0)) != 0)
16958 addr = XEXP (addr, 0);
16959 else if (GET_CODE (XEXP (addr, 1)) == REG
16960 && REGNO (XEXP (addr, 1)) != 0)
16961 addr = XEXP (addr, 1);
16962 else if (CONSTANT_P (XEXP (addr, 0)))
16963 addr = XEXP (addr, 1);
16964 else if (CONSTANT_P (XEXP (addr, 1)))
16965 addr = XEXP (addr, 0);
16969 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
16975 rs6000_fatal_bad_address (rtx op)
16977 fatal_insn ("bad address", op);
16982 static tree branch_island_list = 0;
16984 /* Remember to generate a branch island for far calls to the given
16988 add_compiler_branch_island (tree label_name, tree function_name,
16991 tree branch_island = build_tree_list (function_name, label_name);
16992 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
16993 TREE_CHAIN (branch_island) = branch_island_list;
16994 branch_island_list = branch_island;
16997 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16998 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16999 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17000 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17002 /* Generate far-jump branch islands for everything on the
17003 branch_island_list. Invoked immediately after the last instruction
17004 of the epilogue has been emitted; the branch-islands must be
17005 appended to, and contiguous with, the function body. Mach-O stubs
17006 are generated in machopic_output_stub(). */
17009 macho_branch_islands (void)
17012 tree branch_island;
17014 for (branch_island = branch_island_list;
17016 branch_island = TREE_CHAIN (branch_island))
17018 const char *label =
17019 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17021 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17022 char name_buf[512];
17023 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17024 if (name[0] == '*' || name[0] == '&')
17025 strcpy (name_buf, name+1);
17029 strcpy (name_buf+1, name);
17031 strcpy (tmp_buf, "\n");
17032 strcat (tmp_buf, label);
17033 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17034 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17035 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17036 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17039 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17040 strcat (tmp_buf, label);
17041 strcat (tmp_buf, "_pic\n");
17042 strcat (tmp_buf, label);
17043 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17045 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17046 strcat (tmp_buf, name_buf);
17047 strcat (tmp_buf, " - ");
17048 strcat (tmp_buf, label);
17049 strcat (tmp_buf, "_pic)\n");
17051 strcat (tmp_buf, "\tmtlr r0\n");
17053 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17054 strcat (tmp_buf, name_buf);
17055 strcat (tmp_buf, " - ");
17056 strcat (tmp_buf, label);
17057 strcat (tmp_buf, "_pic)\n");
17059 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17063 strcat (tmp_buf, ":\nlis r12,hi16(");
17064 strcat (tmp_buf, name_buf);
17065 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17066 strcat (tmp_buf, name_buf);
17067 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17069 output_asm_insn (tmp_buf, 0);
17070 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17071 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17072 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17073 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17076 branch_island_list = 0;
17079 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17080 already there or not. */
17083 no_previous_def (tree function_name)
17085 tree branch_island;
17086 for (branch_island = branch_island_list;
17088 branch_island = TREE_CHAIN (branch_island))
17089 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17094 /* GET_PREV_LABEL gets the label name from the previous definition of
17098 get_prev_label (tree function_name)
17100 tree branch_island;
17101 for (branch_island = branch_island_list;
17103 branch_island = TREE_CHAIN (branch_island))
17104 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17105 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17109 /* INSN is either a function call or a millicode call. It may have an
17110 unconditional jump in its delay slot.
17112 CALL_DEST is the routine we are calling. */
17115 output_call (rtx insn, rtx *operands, int dest_operand_number,
17116 int cookie_operand_number)
17118 static char buf[256];
17119 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17120 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17123 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17125 if (no_previous_def (funname))
17127 int line_number = 0;
17128 rtx label_rtx = gen_label_rtx ();
17129 char *label_buf, temp_buf[256];
17130 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17131 CODE_LABEL_NUMBER (label_rtx));
17132 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17133 labelname = get_identifier (label_buf);
17134 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17136 line_number = NOTE_LINE_NUMBER (insn);
17137 add_compiler_branch_island (labelname, funname, line_number);
17140 labelname = get_prev_label (funname);
17142 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17143 instruction will reach 'foo', otherwise link as 'bl L42'".
17144 "L42" should be a 'branch island', that will do a far jump to
17145 'foo'. Branch islands are generated in
17146 macho_branch_islands(). */
17147 sprintf (buf, "jbsr %%z%d,%.246s",
17148 dest_operand_number, IDENTIFIER_POINTER (labelname));
17151 sprintf (buf, "bl %%z%d", dest_operand_number);
17155 /* Generate PIC and indirect symbol stubs. */
17158 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17160 unsigned int length;
17161 char *symbol_name, *lazy_ptr_name;
17162 char *local_label_0;
17163 static int label = 0;
17165 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17166 symb = (*targetm.strip_name_encoding) (symb);
17169 length = strlen (symb);
17170 symbol_name = alloca (length + 32);
17171 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17173 lazy_ptr_name = alloca (length + 32);
17174 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17177 machopic_picsymbol_stub1_section ();
17179 machopic_symbol_stub1_section ();
17183 fprintf (file, "\t.align 5\n");
17185 fprintf (file, "%s:\n", stub);
17186 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17189 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
17190 sprintf (local_label_0, "\"L%011d$spb\"", label);
17192 fprintf (file, "\tmflr r0\n");
17193 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17194 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17195 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17196 lazy_ptr_name, local_label_0);
17197 fprintf (file, "\tmtlr r0\n");
17198 fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
17199 lazy_ptr_name, local_label_0);
17200 fprintf (file, "\tmtctr r12\n");
17201 fprintf (file, "\tbctr\n");
17205 fprintf (file, "\t.align 4\n");
17207 fprintf (file, "%s:\n", stub);
17208 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17210 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17211 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
17212 fprintf (file, "\tmtctr r12\n");
17213 fprintf (file, "\tbctr\n");
17216 machopic_lazy_symbol_ptr_section ();
17217 fprintf (file, "%s:\n", lazy_ptr_name);
17218 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17219 fprintf (file, "%sdyld_stub_binding_helper\n",
17220 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17223 /* Legitimize PIC addresses. If the address is already
17224 position-independent, we return ORIG. Newly generated
17225 position-independent addresses go into a reg. This is REG if non
17226 zero, otherwise we allocate register(s) as necessary. */
17228 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17231 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17236 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17237 reg = gen_reg_rtx (Pmode);
17239 if (GET_CODE (orig) == CONST)
17241 if (GET_CODE (XEXP (orig, 0)) == PLUS
17242 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17245 if (GET_CODE (XEXP (orig, 0)) == PLUS)
17247 /* Use a different reg for the intermediate value, as
17248 it will be marked UNCHANGING. */
17249 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17252 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17255 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17261 if (GET_CODE (offset) == CONST_INT)
17263 if (SMALL_INT (offset))
17264 return plus_constant (base, INTVAL (offset));
17265 else if (! reload_in_progress && ! reload_completed)
17266 offset = force_reg (Pmode, offset);
17269 rtx mem = force_const_mem (Pmode, orig);
17270 return machopic_legitimize_pic_address (mem, Pmode, reg);
17273 return gen_rtx_PLUS (Pmode, base, offset);
17276 /* Fall back on generic machopic code. */
17277 return machopic_legitimize_pic_address (orig, mode, reg);
17280 /* This is just a placeholder to make linking work without having to
17281 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17282 ever needed for Darwin (not too likely!) this would have to get a
17283 real definition. */
17290 /* Output a .machine directive for the Darwin assembler, and call
17291 the generic start_file routine. */
17294 rs6000_darwin_file_start (void)
17296 static const struct
17302 { "ppc64", "ppc64", MASK_64BIT },
17303 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17304 { "power4", "ppc970", 0 },
17305 { "G5", "ppc970", 0 },
17306 { "7450", "ppc7450", 0 },
17307 { "7400", "ppc7400", MASK_ALTIVEC },
17308 { "G4", "ppc7400", 0 },
17309 { "750", "ppc750", 0 },
17310 { "740", "ppc750", 0 },
17311 { "G3", "ppc750", 0 },
17312 { "604e", "ppc604e", 0 },
17313 { "604", "ppc604", 0 },
17314 { "603e", "ppc603", 0 },
17315 { "603", "ppc603", 0 },
17316 { "601", "ppc601", 0 },
17317 { NULL, "ppc", 0 } };
17318 const char *cpu_id = "";
17321 rs6000_file_start();
17323 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17324 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17325 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17326 && rs6000_select[i].string[0] != '\0')
17327 cpu_id = rs6000_select[i].string;
17329 /* Look through the mapping array. Pick the first name that either
17330 matches the argument, has a bit set in IF_SET that is also set
17331 in the target flags, or has a NULL name. */
17334 while (mapping[i].arg != NULL
17335 && strcmp (mapping[i].arg, cpu_id) != 0
17336 && (mapping[i].if_set & target_flags) == 0)
17339 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17342 #endif /* TARGET_MACHO */
17345 static unsigned int
17346 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17348 return default_section_type_flags_1 (decl, name, reloc,
17349 flag_pic || DEFAULT_ABI == ABI_AIX);
17352 /* Record an element in the table of global constructors. SYMBOL is
17353 a SYMBOL_REF of the function to be called; PRIORITY is a number
17354 between 0 and MAX_INIT_PRIORITY.
17356 This differs from default_named_section_asm_out_constructor in
17357 that we have special handling for -mrelocatable. */
17360 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17362 const char *section = ".ctors";
17365 if (priority != DEFAULT_INIT_PRIORITY)
17367 sprintf (buf, ".ctors.%.5u",
17368 /* Invert the numbering so the linker puts us in the proper
17369 order; constructors are run from right to left, and the
17370 linker sorts in increasing order. */
17371 MAX_INIT_PRIORITY - priority);
17375 named_section_flags (section, SECTION_WRITE);
17376 assemble_align (POINTER_SIZE);
17378 if (TARGET_RELOCATABLE)
17380 fputs ("\t.long (", asm_out_file);
17381 output_addr_const (asm_out_file, symbol);
17382 fputs (")@fixup\n", asm_out_file);
17385 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17389 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17391 const char *section = ".dtors";
17394 if (priority != DEFAULT_INIT_PRIORITY)
17396 sprintf (buf, ".dtors.%.5u",
17397 /* Invert the numbering so the linker puts us in the proper
17398 order; constructors are run from right to left, and the
17399 linker sorts in increasing order. */
17400 MAX_INIT_PRIORITY - priority);
17404 named_section_flags (section, SECTION_WRITE);
17405 assemble_align (POINTER_SIZE);
17407 if (TARGET_RELOCATABLE)
17409 fputs ("\t.long (", asm_out_file);
17410 output_addr_const (asm_out_file, symbol);
17411 fputs (")@fixup\n", asm_out_file);
17414 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17418 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17422 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17423 ASM_OUTPUT_LABEL (file, name);
17424 fputs (DOUBLE_INT_ASM_OP, file);
17425 rs6000_output_function_entry (file, name);
17426 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17429 fputs ("\t.size\t", file);
17430 assemble_name (file, name);
17431 fputs (",24\n\t.type\t.", file);
17432 assemble_name (file, name);
17433 fputs (",@function\n", file);
17434 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17436 fputs ("\t.globl\t.", file);
17437 assemble_name (file, name);
17442 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17443 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17444 rs6000_output_function_entry (file, name);
17445 fputs (":\n", file);
17449 if (TARGET_RELOCATABLE
17450 && (get_pool_size () != 0 || current_function_profile)
17455 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17457 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17458 fprintf (file, "\t.long ");
17459 assemble_name (file, buf);
17461 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17462 assemble_name (file, buf);
17466 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17467 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17469 if (DEFAULT_ABI == ABI_AIX)
17471 const char *desc_name, *orig_name;
17473 orig_name = (*targetm.strip_name_encoding) (name);
17474 desc_name = orig_name;
17475 while (*desc_name == '.')
17478 if (TREE_PUBLIC (decl))
17479 fprintf (file, "\t.globl %s\n", desc_name);
17481 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17482 fprintf (file, "%s:\n", desc_name);
17483 fprintf (file, "\t.long %s\n", orig_name);
17484 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17485 if (DEFAULT_ABI == ABI_AIX)
17486 fputs ("\t.long 0\n", file);
17487 fprintf (file, "\t.previous\n");
17489 ASM_OUTPUT_LABEL (file, name);
17495 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
17497 fputs (GLOBAL_ASM_OP, stream);
17498 RS6000_OUTPUT_BASENAME (stream, name);
17499 putc ('\n', stream);
17503 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17504 tree decl ATTRIBUTE_UNUSED)
17507 static const char * const suffix[3] = { "PR", "RO", "RW" };
17509 if (flags & SECTION_CODE)
17511 else if (flags & SECTION_WRITE)
17516 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
17517 (flags & SECTION_CODE) ? "." : "",
17518 name, suffix[smclass], flags & SECTION_ENTSIZE);
17522 rs6000_xcoff_select_section (tree decl, int reloc,
17523 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17525 if (decl_readonly_section_1 (decl, reloc, 1))
17527 if (TREE_PUBLIC (decl))
17528 read_only_data_section ();
17530 read_only_private_data_section ();
17534 if (TREE_PUBLIC (decl))
17537 private_data_section ();
17542 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
17546 /* Use select_section for private and uninitialized data. */
17547 if (!TREE_PUBLIC (decl)
17548 || DECL_COMMON (decl)
17549 || DECL_INITIAL (decl) == NULL_TREE
17550 || DECL_INITIAL (decl) == error_mark_node
17551 || (flag_zero_initialized_in_bss
17552 && initializer_zerop (DECL_INITIAL (decl))))
17555 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17556 name = (*targetm.strip_name_encoding) (name);
17557 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
17560 /* Select section for constant in constant pool.
17562 On RS/6000, all constants are in the private read-only data area.
17563 However, if this is being placed in the TOC it must be output as a
17567 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
17568 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17570 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17573 read_only_private_data_section ();
17576 /* Remove any trailing [DS] or the like from the symbol name. */
17578 static const char *
17579 rs6000_xcoff_strip_name_encoding (const char *name)
17584 len = strlen (name);
17585 if (name[len - 1] == ']')
17586 return ggc_alloc_string (name, len - 4);
17591 /* Section attributes. AIX is always PIC. */
17593 static unsigned int
17594 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
17596 unsigned int align;
17597 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17599 /* Align to at least UNIT size. */
17600 if (flags & SECTION_CODE)
17601 align = MIN_UNITS_PER_WORD;
17603 /* Increase alignment of large objects if not already stricter. */
17604 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17605 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17606 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17608 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
17611 /* Output at beginning of assembler file.
17613 Initialize the section names for the RS/6000 at this point.
17615 Specify filename, including full path, to assembler.
17617 We want to go into the TOC section so at least one .toc will be emitted.
17618 Also, in order to output proper .bs/.es pairs, we need at least one static
17619 [RW] section emitted.
17621 Finally, declare mcount when profiling to make the assembler happy. */
17624 rs6000_xcoff_file_start (void)
17626 rs6000_gen_section_name (&xcoff_bss_section_name,
17627 main_input_filename, ".bss_");
17628 rs6000_gen_section_name (&xcoff_private_data_section_name,
17629 main_input_filename, ".rw_");
17630 rs6000_gen_section_name (&xcoff_read_only_section_name,
17631 main_input_filename, ".ro_");
17633 fputs ("\t.file\t", asm_out_file);
17634 output_quoted_string (asm_out_file, main_input_filename);
17635 fputc ('\n', asm_out_file);
17637 if (write_symbols != NO_DEBUG)
17638 private_data_section ();
17641 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17642 rs6000_file_start ();
17645 /* Output at end of assembler file.
17646 On the RS/6000, referencing data should automatically pull in text. */
17649 rs6000_xcoff_file_end (void)
17652 fputs ("_section_.text:\n", asm_out_file);
17654 fputs (TARGET_32BIT
17655 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17658 #endif /* TARGET_XCOFF */
17661 /* Cross-module name binding. Darwin does not support overriding
17662 functions at dynamic-link time. */
17665 rs6000_binds_local_p (tree decl)
17667 return default_binds_local_p_1 (decl, 0);
17671 /* Compute a (partial) cost for rtx X. Return true if the complete
17672 cost has been computed, and false if subexpressions should be
17673 scanned. In either case, *TOTAL contains the cost result. */
17676 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
17678 enum machine_mode mode = GET_MODE (x);
17682 /* On the RS/6000, if it is valid in the insn, it is free. */
17684 if (((outer_code == SET
17685 || outer_code == PLUS
17686 || outer_code == MINUS)
17687 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17688 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
17689 || ((outer_code == IOR || outer_code == XOR)
17690 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17691 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
17692 || ((outer_code == DIV || outer_code == UDIV
17693 || outer_code == MOD || outer_code == UMOD)
17694 && exact_log2 (INTVAL (x)) >= 0)
17695 || (outer_code == AND
17696 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17697 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
17698 || mask_operand (x, VOIDmode)))
17699 || outer_code == ASHIFT
17700 || outer_code == ASHIFTRT
17701 || outer_code == LSHIFTRT
17702 || outer_code == ROTATE
17703 || outer_code == ROTATERT
17704 || outer_code == ZERO_EXTRACT
17705 || (outer_code == MULT
17706 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17707 || (outer_code == COMPARE
17708 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17709 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))))
17714 else if ((outer_code == PLUS
17715 && reg_or_add_cint64_operand (x, VOIDmode))
17716 || (outer_code == MINUS
17717 && reg_or_sub_cint64_operand (x, VOIDmode))
17718 || ((outer_code == SET
17719 || outer_code == IOR
17720 || outer_code == XOR)
17722 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
17724 *total = COSTS_N_INSNS (1);
17731 && ((outer_code == AND
17732 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17733 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
17734 || mask64_operand (x, DImode)))
17735 || ((outer_code == IOR || outer_code == XOR)
17736 && CONST_DOUBLE_HIGH (x) == 0
17737 && (CONST_DOUBLE_LOW (x)
17738 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
17743 else if (mode == DImode
17744 && (outer_code == SET
17745 || outer_code == IOR
17746 || outer_code == XOR)
17747 && CONST_DOUBLE_HIGH (x) == 0)
17749 *total = COSTS_N_INSNS (1);
17758 /* When optimizing for size, MEM should be slightly more expensive
17759 than generating address, e.g., (plus (reg) (const)).
17760 L1 cache latency is about two instructions. */
17761 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
17769 if (mode == DFmode)
17771 if (GET_CODE (XEXP (x, 0)) == MULT)
17773 /* FNMA accounted in outer NEG. */
17774 if (outer_code == NEG)
17775 *total = rs6000_cost->dmul - rs6000_cost->fp;
17777 *total = rs6000_cost->dmul;
17780 *total = rs6000_cost->fp;
17782 else if (mode == SFmode)
17784 /* FNMA accounted in outer NEG. */
17785 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17788 *total = rs6000_cost->fp;
17790 else if (GET_CODE (XEXP (x, 0)) == MULT)
17792 /* The rs6000 doesn't have shift-and-add instructions. */
17793 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
17794 *total += COSTS_N_INSNS (1);
17797 *total = COSTS_N_INSNS (1);
17801 if (mode == DFmode)
17803 if (GET_CODE (XEXP (x, 0)) == MULT)
17805 /* FNMA accounted in outer NEG. */
17806 if (outer_code == NEG)
17809 *total = rs6000_cost->dmul;
17812 *total = rs6000_cost->fp;
17814 else if (mode == SFmode)
17816 /* FNMA accounted in outer NEG. */
17817 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17820 *total = rs6000_cost->fp;
17822 else if (GET_CODE (XEXP (x, 0)) == MULT)
17824 /* The rs6000 doesn't have shift-and-sub instructions. */
17825 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17826 *total += COSTS_N_INSNS (1);
17829 *total = COSTS_N_INSNS (1);
17833 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
17835 if (INTVAL (XEXP (x, 1)) >= -256
17836 && INTVAL (XEXP (x, 1)) <= 255)
17837 *total = rs6000_cost->mulsi_const9;
17839 *total = rs6000_cost->mulsi_const;
17841 /* FMA accounted in outer PLUS/MINUS. */
17842 else if ((mode == DFmode || mode == SFmode)
17843 && (outer_code == PLUS || outer_code == MINUS))
17845 else if (mode == DFmode)
17846 *total = rs6000_cost->dmul;
17847 else if (mode == SFmode)
17848 *total = rs6000_cost->fp;
17849 else if (mode == DImode)
17850 *total = rs6000_cost->muldi;
17852 *total = rs6000_cost->mulsi;
17857 if (FLOAT_MODE_P (mode))
17859 *total = mode == DFmode ? rs6000_cost->ddiv
17860 : rs6000_cost->sdiv;
17867 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17868 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17870 if (code == DIV || code == MOD)
17872 *total = COSTS_N_INSNS (2);
17875 *total = COSTS_N_INSNS (1);
17879 if (GET_MODE (XEXP (x, 1)) == DImode)
17880 *total = rs6000_cost->divdi;
17882 *total = rs6000_cost->divsi;
17884 /* Add in shift and subtract for MOD. */
17885 if (code == MOD || code == UMOD)
17886 *total += COSTS_N_INSNS (2);
17890 *total = COSTS_N_INSNS (4);
17894 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17905 *total = COSTS_N_INSNS (1);
17913 /* Handle mul_highpart. */
17914 if (outer_code == TRUNCATE
17915 && GET_CODE (XEXP (x, 0)) == MULT)
17917 if (mode == DImode)
17918 *total = rs6000_cost->muldi;
17920 *total = rs6000_cost->mulsi;
17923 else if (outer_code == AND)
17926 *total = COSTS_N_INSNS (1);
17931 if (GET_CODE (XEXP (x, 0)) == MEM)
17934 *total = COSTS_N_INSNS (1);
17940 if (!FLOAT_MODE_P (mode))
17942 *total = COSTS_N_INSNS (1);
17948 case UNSIGNED_FLOAT:
17952 case FLOAT_TRUNCATE:
17953 *total = rs6000_cost->fp;
17957 switch (XINT (x, 1))
17960 *total = rs6000_cost->fp;
17972 *total = COSTS_N_INSNS (1);
17975 else if (FLOAT_MODE_P (mode)
17976 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17978 *total = rs6000_cost->fp;
17991 /* A C expression returning the cost of moving data from a register of class
17992 CLASS1 to one of CLASS2. */
17995 rs6000_register_move_cost (enum machine_mode mode,
17996 enum reg_class from, enum reg_class to)
17998 /* Moves from/to GENERAL_REGS. */
17999 if (reg_classes_intersect_p (to, GENERAL_REGS)
18000 || reg_classes_intersect_p (from, GENERAL_REGS))
18002 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18005 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18006 return (rs6000_memory_move_cost (mode, from, 0)
18007 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18009 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18011 else if (from == CR_REGS)
18015 /* A move will cost one instruction per GPR moved. */
18016 return 2 * HARD_REGNO_NREGS (0, mode);
18019 /* Moving between two similar registers is just one instruction. */
18020 else if (reg_classes_intersect_p (to, from))
18021 return mode == TFmode ? 4 : 2;
18023 /* Everything else has to go through GENERAL_REGS. */
18025 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18026 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18029 /* A C expressions returning the cost of moving data of MODE from a register to
18033 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18034 int in ATTRIBUTE_UNUSED)
18036 if (reg_classes_intersect_p (class, GENERAL_REGS))
18037 return 4 * HARD_REGNO_NREGS (0, mode);
18038 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18039 return 4 * HARD_REGNO_NREGS (32, mode);
18040 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18041 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
18043 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18046 /* Return an RTX representing where to find the function value of a
18047 function returning MODE. */
18049 rs6000_complex_function_value (enum machine_mode mode)
18051 unsigned int regno;
18053 enum machine_mode inner = GET_MODE_INNER (mode);
18054 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18056 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18057 regno = FP_ARG_RETURN;
18060 regno = GP_ARG_RETURN;
18062 /* 32-bit is OK since it'll go in r3/r4. */
18063 if (TARGET_32BIT && inner_bytes >= 4)
18064 return gen_rtx_REG (mode, regno);
18067 if (inner_bytes >= 8)
18068 return gen_rtx_REG (mode, regno);
18070 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18072 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18073 GEN_INT (inner_bytes));
18074 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18077 /* Define how to find the value returned by a function.
18078 VALTYPE is the data type of the value (as a tree).
18079 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18080 otherwise, FUNC is 0.
18082 On the SPE, both FPs and vectors are returned in r3.
18084 On RS/6000 an integer value is in r3 and a floating-point value is in
18085 fp1, unless -msoft-float. */
18088 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18090 enum machine_mode mode;
18091 unsigned int regno;
18093 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18095 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18096 return gen_rtx_PARALLEL (DImode,
18098 gen_rtx_EXPR_LIST (VOIDmode,
18099 gen_rtx_REG (SImode, GP_ARG_RETURN),
18101 gen_rtx_EXPR_LIST (VOIDmode,
18102 gen_rtx_REG (SImode,
18103 GP_ARG_RETURN + 1),
18107 if ((INTEGRAL_TYPE_P (valtype)
18108 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18109 || POINTER_TYPE_P (valtype))
18110 mode = TARGET_32BIT ? SImode : DImode;
18112 mode = TYPE_MODE (valtype);
18114 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18115 regno = FP_ARG_RETURN;
18116 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18117 && targetm.calls.split_complex_arg)
18118 return rs6000_complex_function_value (mode);
18119 else if (TREE_CODE (valtype) == VECTOR_TYPE
18120 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18121 && ALTIVEC_VECTOR_MODE(mode))
18122 regno = ALTIVEC_ARG_RETURN;
18123 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && mode == DFmode)
18124 return spe_build_register_parallel (DFmode, GP_ARG_RETURN);
18126 regno = GP_ARG_RETURN;
18128 return gen_rtx_REG (mode, regno);
18131 /* Define how to find the value returned by a library function
18132 assuming the value has mode MODE. */
18134 rs6000_libcall_value (enum machine_mode mode)
18136 unsigned int regno;
18138 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18140 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18141 return gen_rtx_PARALLEL (DImode,
18143 gen_rtx_EXPR_LIST (VOIDmode,
18144 gen_rtx_REG (SImode, GP_ARG_RETURN),
18146 gen_rtx_EXPR_LIST (VOIDmode,
18147 gen_rtx_REG (SImode,
18148 GP_ARG_RETURN + 1),
18152 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18153 && TARGET_HARD_FLOAT && TARGET_FPRS)
18154 regno = FP_ARG_RETURN;
18155 else if (ALTIVEC_VECTOR_MODE (mode)
18156 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18157 regno = ALTIVEC_ARG_RETURN;
18158 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18159 return rs6000_complex_function_value (mode);
18160 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && mode == DFmode)
18161 return spe_build_register_parallel (DFmode, GP_ARG_RETURN);
18163 regno = GP_ARG_RETURN;
18165 return gen_rtx_REG (mode, regno);
18168 /* Define the offset between two registers, FROM to be eliminated and its
18169 replacement TO, at the start of a routine. */
18171 rs6000_initial_elimination_offset (int from, int to)
18173 rs6000_stack_t *info = rs6000_stack_info ();
18174 HOST_WIDE_INT offset;
18176 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18177 offset = info->push_p ? 0 : -info->total_size;
18178 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
18179 offset = info->total_size;
18180 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18181 offset = info->push_p ? info->total_size : 0;
18182 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18190 /* Return true if TYPE is of type __ev64_opaque__. */
18193 is_ev64_opaque_type (tree type)
18196 && (type == opaque_V2SI_type_node
18197 || type == opaque_V2SF_type_node
18198 || type == opaque_p_V2SI_type_node));
18202 rs6000_dwarf_register_span (rtx reg)
18207 && (SPE_VECTOR_MODE (GET_MODE (reg))
18208 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18213 regno = REGNO (reg);
18215 /* The duality of the SPE register size wreaks all kinds of havoc.
18216 This is a way of distinguishing r0 in 32-bits from r0 in
18219 gen_rtx_PARALLEL (VOIDmode,
18222 gen_rtx_REG (SImode, regno + 1200),
18223 gen_rtx_REG (SImode, regno))
18225 gen_rtx_REG (SImode, regno),
18226 gen_rtx_REG (SImode, regno + 1200)));
18229 /* Map internal gcc register numbers to DWARF2 register numbers. */
18232 rs6000_dbx_register_number (unsigned int regno)
18234 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18236 if (regno == MQ_REGNO)
18238 if (regno == LINK_REGISTER_REGNUM)
18240 if (regno == COUNT_REGISTER_REGNUM)
18242 if (CR_REGNO_P (regno))
18243 return regno - CR0_REGNO + 86;
18244 if (regno == XER_REGNO)
18246 if (ALTIVEC_REGNO_P (regno))
18247 return regno - FIRST_ALTIVEC_REGNO + 1124;
18248 if (regno == VRSAVE_REGNO)
18250 if (regno == VSCR_REGNO)
18252 if (regno == SPE_ACC_REGNO)
18254 if (regno == SPEFSCR_REGNO)
18256 /* SPE high reg number. We get these values of regno from
18257 rs6000_dwarf_register_span. */
18258 if (regno >= 1200 && regno < 1232)
18264 /* target hook eh_return_filter_mode */
18265 static enum machine_mode
18266 rs6000_eh_return_filter_mode (void)
18268 return TARGET_32BIT ? SImode : word_mode;
18271 /* Target hook for vector_mode_supported_p. */
18273 rs6000_vector_mode_supported_p (enum machine_mode mode)
18276 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18279 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18286 #include "gt-rs6000.h"