1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu;
138 struct rs6000_cpu_select rs6000_select[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 static GTY(()) bool rs6000_cell_dont_microcode;
148 /* Always emit branch hint bits. */
149 static GTY(()) bool rs6000_always_hint;
151 /* Schedule instructions for group formation. */
152 static GTY(()) bool rs6000_sched_groups;
154 /* Align branch targets. */
155 static GTY(()) bool rs6000_align_branch_targets;
157 /* Support for -msched-costly-dep option. */
158 const char *rs6000_sched_costly_dep_str;
159 enum rs6000_dependence_cost rs6000_sched_costly_dep;
161 /* Support for -minsert-sched-nops option. */
162 const char *rs6000_sched_insert_nops_str;
163 enum rs6000_nop_insertion rs6000_sched_insert_nops;
165 /* Support targetm.vectorize.builtin_mask_for_load. */
166 static GTY(()) tree altivec_builtin_mask_for_load;
168 /* Size of long double. */
169 int rs6000_long_double_type_size;
171 /* IEEE quad extended precision long double. */
174 /* Nonzero to use AltiVec ABI. */
175 int rs6000_altivec_abi;
177 /* Nonzero if we want SPE SIMD instructions. */
180 /* Nonzero if we want SPE ABI extensions. */
183 /* Nonzero to use isel instructions. */
186 /* Nonzero if floating point operations are done in the GPRs. */
187 int rs6000_float_gprs = 0;
189 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
190 int rs6000_darwin64_abi;
192 /* Set to nonzero once AIX common-mode calls have been defined. */
193 static GTY(()) int common_mode_defined;
195 /* Save information from a "cmpxx" operation until the branch or scc is
197 rtx rs6000_compare_op0, rs6000_compare_op1;
198 int rs6000_compare_fp_p;
200 /* Label number of label created for -mrelocatable, to call to so we can
201 get the address of the GOT section */
202 int rs6000_pic_labelno;
205 /* Which abi to adhere to */
206 const char *rs6000_abi_name;
208 /* Semantics of the small data area */
209 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
211 /* Which small data model to use */
212 const char *rs6000_sdata_name = (char *)0;
214 /* Counter for labels which are to be placed in .fixup. */
215 int fixuplabelno = 0;
218 /* Bit size of immediate TLS offsets and string from which it is decoded. */
219 int rs6000_tls_size = 32;
220 const char *rs6000_tls_size_string;
222 /* ABI enumeration available for subtarget to use. */
223 enum rs6000_abi rs6000_current_abi;
225 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
229 const char *rs6000_debug_name;
230 int rs6000_debug_stack; /* debug stack applications */
231 int rs6000_debug_arg; /* debug argument handling */
233 /* Value is TRUE if register/mode pair is acceptable. */
234 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
236 /* Built in types. */
238 tree rs6000_builtin_types[RS6000_BTI_MAX];
239 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
241 const char *rs6000_traceback_name;
243 traceback_default = 0,
249 /* Flag to say the TOC is initialized */
251 char toc_label_name[10];
253 /* Cached value of rs6000_variable_issue. This is cached in
254 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
255 static short cached_can_issue_more;
257 static GTY(()) section *read_only_data_section;
258 static GTY(()) section *private_data_section;
259 static GTY(()) section *read_only_private_data_section;
260 static GTY(()) section *sdata2_section;
261 static GTY(()) section *toc_section;
263 /* Control alignment for fields within structures. */
264 /* String from -malign-XXXXX. */
265 int rs6000_alignment_flags;
267 /* True for any options that were explicitly set. */
269 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
270 bool alignment; /* True if -malign- was used. */
271 bool spe_abi; /* True if -mabi=spe/no-spe was used. */
272 bool altivec_abi; /* True if -mabi=altivec/no-altivec used. */
273 bool spe; /* True if -mspe= was used. */
274 bool float_gprs; /* True if -mfloat-gprs= was used. */
275 bool isel; /* True if -misel was used. */
276 bool long_double; /* True if -mlong-double- was used. */
277 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
278 bool vrsave; /* True if -mvrsave was used. */
279 } rs6000_explicit_options;
281 struct builtin_description
283 /* mask is not const because we're going to alter it below. This
284 nonsense will go away when we rewrite the -march infrastructure
285 to give us more target flag bits. */
287 const enum insn_code icode;
288 const char *const name;
289 const enum rs6000_builtins code;
292 /* Target cpu costs. */
294 struct processor_costs {
295 const int mulsi; /* cost of SImode multiplication. */
296 const int mulsi_const; /* cost of SImode multiplication by constant. */
297 const int mulsi_const9; /* cost of SImode mult by short constant. */
298 const int muldi; /* cost of DImode multiplication. */
299 const int divsi; /* cost of SImode division. */
300 const int divdi; /* cost of DImode division. */
301 const int fp; /* cost of simple SFmode and DFmode insns. */
302 const int dmul; /* cost of DFmode multiplication (and fmadd). */
303 const int sdiv; /* cost of SFmode division (fdivs). */
304 const int ddiv; /* cost of DFmode division (fdiv). */
305 const int cache_line_size; /* cache line size in bytes. */
306 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
307 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
308 const int simultaneous_prefetches; /* number of parallel prefetch
312 const struct processor_costs *rs6000_cost;
314 /* Processor costs (relative to an add) */
316 /* Instruction size costs on 32bit processors. */
318 struct processor_costs size32_cost = {
319 COSTS_N_INSNS (1), /* mulsi */
320 COSTS_N_INSNS (1), /* mulsi_const */
321 COSTS_N_INSNS (1), /* mulsi_const9 */
322 COSTS_N_INSNS (1), /* muldi */
323 COSTS_N_INSNS (1), /* divsi */
324 COSTS_N_INSNS (1), /* divdi */
325 COSTS_N_INSNS (1), /* fp */
326 COSTS_N_INSNS (1), /* dmul */
327 COSTS_N_INSNS (1), /* sdiv */
328 COSTS_N_INSNS (1), /* ddiv */
335 /* Instruction size costs on 64bit processors. */
337 struct processor_costs size64_cost = {
338 COSTS_N_INSNS (1), /* mulsi */
339 COSTS_N_INSNS (1), /* mulsi_const */
340 COSTS_N_INSNS (1), /* mulsi_const9 */
341 COSTS_N_INSNS (1), /* muldi */
342 COSTS_N_INSNS (1), /* divsi */
343 COSTS_N_INSNS (1), /* divdi */
344 COSTS_N_INSNS (1), /* fp */
345 COSTS_N_INSNS (1), /* dmul */
346 COSTS_N_INSNS (1), /* sdiv */
347 COSTS_N_INSNS (1), /* ddiv */
354 /* Instruction costs on RIOS1 processors. */
356 struct processor_costs rios1_cost = {
357 COSTS_N_INSNS (5), /* mulsi */
358 COSTS_N_INSNS (4), /* mulsi_const */
359 COSTS_N_INSNS (3), /* mulsi_const9 */
360 COSTS_N_INSNS (5), /* muldi */
361 COSTS_N_INSNS (19), /* divsi */
362 COSTS_N_INSNS (19), /* divdi */
363 COSTS_N_INSNS (2), /* fp */
364 COSTS_N_INSNS (2), /* dmul */
365 COSTS_N_INSNS (19), /* sdiv */
366 COSTS_N_INSNS (19), /* ddiv */
367 128, /* cache line size */
373 /* Instruction costs on RIOS2 processors. */
375 struct processor_costs rios2_cost = {
376 COSTS_N_INSNS (2), /* mulsi */
377 COSTS_N_INSNS (2), /* mulsi_const */
378 COSTS_N_INSNS (2), /* mulsi_const9 */
379 COSTS_N_INSNS (2), /* muldi */
380 COSTS_N_INSNS (13), /* divsi */
381 COSTS_N_INSNS (13), /* divdi */
382 COSTS_N_INSNS (2), /* fp */
383 COSTS_N_INSNS (2), /* dmul */
384 COSTS_N_INSNS (17), /* sdiv */
385 COSTS_N_INSNS (17), /* ddiv */
386 256, /* cache line size */
392 /* Instruction costs on RS64A processors. */
394 struct processor_costs rs64a_cost = {
395 COSTS_N_INSNS (20), /* mulsi */
396 COSTS_N_INSNS (12), /* mulsi_const */
397 COSTS_N_INSNS (8), /* mulsi_const9 */
398 COSTS_N_INSNS (34), /* muldi */
399 COSTS_N_INSNS (65), /* divsi */
400 COSTS_N_INSNS (67), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (4), /* dmul */
403 COSTS_N_INSNS (31), /* sdiv */
404 COSTS_N_INSNS (31), /* ddiv */
405 128, /* cache line size */
411 /* Instruction costs on MPCCORE processors. */
413 struct processor_costs mpccore_cost = {
414 COSTS_N_INSNS (2), /* mulsi */
415 COSTS_N_INSNS (2), /* mulsi_const */
416 COSTS_N_INSNS (2), /* mulsi_const9 */
417 COSTS_N_INSNS (2), /* muldi */
418 COSTS_N_INSNS (6), /* divsi */
419 COSTS_N_INSNS (6), /* divdi */
420 COSTS_N_INSNS (4), /* fp */
421 COSTS_N_INSNS (5), /* dmul */
422 COSTS_N_INSNS (10), /* sdiv */
423 COSTS_N_INSNS (17), /* ddiv */
424 32, /* cache line size */
430 /* Instruction costs on PPC403 processors. */
432 struct processor_costs ppc403_cost = {
433 COSTS_N_INSNS (4), /* mulsi */
434 COSTS_N_INSNS (4), /* mulsi_const */
435 COSTS_N_INSNS (4), /* mulsi_const9 */
436 COSTS_N_INSNS (4), /* muldi */
437 COSTS_N_INSNS (33), /* divsi */
438 COSTS_N_INSNS (33), /* divdi */
439 COSTS_N_INSNS (11), /* fp */
440 COSTS_N_INSNS (11), /* dmul */
441 COSTS_N_INSNS (11), /* sdiv */
442 COSTS_N_INSNS (11), /* ddiv */
443 32, /* cache line size */
449 /* Instruction costs on PPC405 processors. */
451 struct processor_costs ppc405_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (3), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (35), /* divsi */
457 COSTS_N_INSNS (35), /* divdi */
458 COSTS_N_INSNS (11), /* fp */
459 COSTS_N_INSNS (11), /* dmul */
460 COSTS_N_INSNS (11), /* sdiv */
461 COSTS_N_INSNS (11), /* ddiv */
462 32, /* cache line size */
468 /* Instruction costs on PPC440 processors. */
470 struct processor_costs ppc440_cost = {
471 COSTS_N_INSNS (3), /* mulsi */
472 COSTS_N_INSNS (2), /* mulsi_const */
473 COSTS_N_INSNS (2), /* mulsi_const9 */
474 COSTS_N_INSNS (3), /* muldi */
475 COSTS_N_INSNS (34), /* divsi */
476 COSTS_N_INSNS (34), /* divdi */
477 COSTS_N_INSNS (5), /* fp */
478 COSTS_N_INSNS (5), /* dmul */
479 COSTS_N_INSNS (19), /* sdiv */
480 COSTS_N_INSNS (33), /* ddiv */
481 32, /* cache line size */
487 /* Instruction costs on PPC601 processors. */
489 struct processor_costs ppc601_cost = {
490 COSTS_N_INSNS (5), /* mulsi */
491 COSTS_N_INSNS (5), /* mulsi_const */
492 COSTS_N_INSNS (5), /* mulsi_const9 */
493 COSTS_N_INSNS (5), /* muldi */
494 COSTS_N_INSNS (36), /* divsi */
495 COSTS_N_INSNS (36), /* divdi */
496 COSTS_N_INSNS (4), /* fp */
497 COSTS_N_INSNS (5), /* dmul */
498 COSTS_N_INSNS (17), /* sdiv */
499 COSTS_N_INSNS (31), /* ddiv */
500 32, /* cache line size */
506 /* Instruction costs on PPC603 processors. */
508 struct processor_costs ppc603_cost = {
509 COSTS_N_INSNS (5), /* mulsi */
510 COSTS_N_INSNS (3), /* mulsi_const */
511 COSTS_N_INSNS (2), /* mulsi_const9 */
512 COSTS_N_INSNS (5), /* muldi */
513 COSTS_N_INSNS (37), /* divsi */
514 COSTS_N_INSNS (37), /* divdi */
515 COSTS_N_INSNS (3), /* fp */
516 COSTS_N_INSNS (4), /* dmul */
517 COSTS_N_INSNS (18), /* sdiv */
518 COSTS_N_INSNS (33), /* ddiv */
519 32, /* cache line size */
525 /* Instruction costs on PPC604 processors. */
527 struct processor_costs ppc604_cost = {
528 COSTS_N_INSNS (4), /* mulsi */
529 COSTS_N_INSNS (4), /* mulsi_const */
530 COSTS_N_INSNS (4), /* mulsi_const9 */
531 COSTS_N_INSNS (4), /* muldi */
532 COSTS_N_INSNS (20), /* divsi */
533 COSTS_N_INSNS (20), /* divdi */
534 COSTS_N_INSNS (3), /* fp */
535 COSTS_N_INSNS (3), /* dmul */
536 COSTS_N_INSNS (18), /* sdiv */
537 COSTS_N_INSNS (32), /* ddiv */
538 32, /* cache line size */
544 /* Instruction costs on PPC604e processors. */
546 struct processor_costs ppc604e_cost = {
547 COSTS_N_INSNS (2), /* mulsi */
548 COSTS_N_INSNS (2), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (2), /* muldi */
551 COSTS_N_INSNS (20), /* divsi */
552 COSTS_N_INSNS (20), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (18), /* sdiv */
556 COSTS_N_INSNS (32), /* ddiv */
557 32, /* cache line size */
563 /* Instruction costs on PPC620 processors. */
565 struct processor_costs ppc620_cost = {
566 COSTS_N_INSNS (5), /* mulsi */
567 COSTS_N_INSNS (4), /* mulsi_const */
568 COSTS_N_INSNS (3), /* mulsi_const9 */
569 COSTS_N_INSNS (7), /* muldi */
570 COSTS_N_INSNS (21), /* divsi */
571 COSTS_N_INSNS (37), /* divdi */
572 COSTS_N_INSNS (3), /* fp */
573 COSTS_N_INSNS (3), /* dmul */
574 COSTS_N_INSNS (18), /* sdiv */
575 COSTS_N_INSNS (32), /* ddiv */
576 128, /* cache line size */
582 /* Instruction costs on PPC630 processors. */
584 struct processor_costs ppc630_cost = {
585 COSTS_N_INSNS (5), /* mulsi */
586 COSTS_N_INSNS (4), /* mulsi_const */
587 COSTS_N_INSNS (3), /* mulsi_const9 */
588 COSTS_N_INSNS (7), /* muldi */
589 COSTS_N_INSNS (21), /* divsi */
590 COSTS_N_INSNS (37), /* divdi */
591 COSTS_N_INSNS (3), /* fp */
592 COSTS_N_INSNS (3), /* dmul */
593 COSTS_N_INSNS (17), /* sdiv */
594 COSTS_N_INSNS (21), /* ddiv */
595 128, /* cache line size */
601 /* Instruction costs on Cell processor. */
602 /* COSTS_N_INSNS (1) ~ one add. */
604 struct processor_costs ppccell_cost = {
605 COSTS_N_INSNS (9/2)+2, /* mulsi */
606 COSTS_N_INSNS (6/2), /* mulsi_const */
607 COSTS_N_INSNS (6/2), /* mulsi_const9 */
608 COSTS_N_INSNS (15/2)+2, /* muldi */
609 COSTS_N_INSNS (38/2), /* divsi */
610 COSTS_N_INSNS (70/2), /* divdi */
611 COSTS_N_INSNS (10/2), /* fp */
612 COSTS_N_INSNS (10/2), /* dmul */
613 COSTS_N_INSNS (74/2), /* sdiv */
614 COSTS_N_INSNS (74/2), /* ddiv */
615 128, /* cache line size */
621 /* Instruction costs on PPC750 and PPC7400 processors. */
623 struct processor_costs ppc750_cost = {
624 COSTS_N_INSNS (5), /* mulsi */
625 COSTS_N_INSNS (3), /* mulsi_const */
626 COSTS_N_INSNS (2), /* mulsi_const9 */
627 COSTS_N_INSNS (5), /* muldi */
628 COSTS_N_INSNS (17), /* divsi */
629 COSTS_N_INSNS (17), /* divdi */
630 COSTS_N_INSNS (3), /* fp */
631 COSTS_N_INSNS (3), /* dmul */
632 COSTS_N_INSNS (17), /* sdiv */
633 COSTS_N_INSNS (31), /* ddiv */
634 32, /* cache line size */
640 /* Instruction costs on PPC7450 processors. */
642 struct processor_costs ppc7450_cost = {
643 COSTS_N_INSNS (4), /* mulsi */
644 COSTS_N_INSNS (3), /* mulsi_const */
645 COSTS_N_INSNS (3), /* mulsi_const9 */
646 COSTS_N_INSNS (4), /* muldi */
647 COSTS_N_INSNS (23), /* divsi */
648 COSTS_N_INSNS (23), /* divdi */
649 COSTS_N_INSNS (5), /* fp */
650 COSTS_N_INSNS (5), /* dmul */
651 COSTS_N_INSNS (21), /* sdiv */
652 COSTS_N_INSNS (35), /* ddiv */
653 32, /* cache line size */
659 /* Instruction costs on PPC8540 processors. */
661 struct processor_costs ppc8540_cost = {
662 COSTS_N_INSNS (4), /* mulsi */
663 COSTS_N_INSNS (4), /* mulsi_const */
664 COSTS_N_INSNS (4), /* mulsi_const9 */
665 COSTS_N_INSNS (4), /* muldi */
666 COSTS_N_INSNS (19), /* divsi */
667 COSTS_N_INSNS (19), /* divdi */
668 COSTS_N_INSNS (4), /* fp */
669 COSTS_N_INSNS (4), /* dmul */
670 COSTS_N_INSNS (29), /* sdiv */
671 COSTS_N_INSNS (29), /* ddiv */
672 32, /* cache line size */
675 1, /* prefetch streams /*/
678 /* Instruction costs on E300C2 and E300C3 cores. */
680 struct processor_costs ppce300c2c3_cost = {
681 COSTS_N_INSNS (4), /* mulsi */
682 COSTS_N_INSNS (4), /* mulsi_const */
683 COSTS_N_INSNS (4), /* mulsi_const9 */
684 COSTS_N_INSNS (4), /* muldi */
685 COSTS_N_INSNS (19), /* divsi */
686 COSTS_N_INSNS (19), /* divdi */
687 COSTS_N_INSNS (3), /* fp */
688 COSTS_N_INSNS (4), /* dmul */
689 COSTS_N_INSNS (18), /* sdiv */
690 COSTS_N_INSNS (33), /* ddiv */
694 1, /* prefetch streams /*/
697 /* Instruction costs on PPCE500MC processors. */
699 struct processor_costs ppce500mc_cost = {
700 COSTS_N_INSNS (4), /* mulsi */
701 COSTS_N_INSNS (4), /* mulsi_const */
702 COSTS_N_INSNS (4), /* mulsi_const9 */
703 COSTS_N_INSNS (4), /* muldi */
704 COSTS_N_INSNS (14), /* divsi */
705 COSTS_N_INSNS (14), /* divdi */
706 COSTS_N_INSNS (8), /* fp */
707 COSTS_N_INSNS (10), /* dmul */
708 COSTS_N_INSNS (36), /* sdiv */
709 COSTS_N_INSNS (66), /* ddiv */
710 64, /* cache line size */
713 1, /* prefetch streams /*/
716 /* Instruction costs on POWER4 and POWER5 processors. */
718 struct processor_costs power4_cost = {
719 COSTS_N_INSNS (3), /* mulsi */
720 COSTS_N_INSNS (2), /* mulsi_const */
721 COSTS_N_INSNS (2), /* mulsi_const9 */
722 COSTS_N_INSNS (4), /* muldi */
723 COSTS_N_INSNS (18), /* divsi */
724 COSTS_N_INSNS (34), /* divdi */
725 COSTS_N_INSNS (3), /* fp */
726 COSTS_N_INSNS (3), /* dmul */
727 COSTS_N_INSNS (17), /* sdiv */
728 COSTS_N_INSNS (17), /* ddiv */
729 128, /* cache line size */
732 8, /* prefetch streams /*/
735 /* Instruction costs on POWER6 processors. */
737 struct processor_costs power6_cost = {
738 COSTS_N_INSNS (8), /* mulsi */
739 COSTS_N_INSNS (8), /* mulsi_const */
740 COSTS_N_INSNS (8), /* mulsi_const9 */
741 COSTS_N_INSNS (8), /* muldi */
742 COSTS_N_INSNS (22), /* divsi */
743 COSTS_N_INSNS (28), /* divdi */
744 COSTS_N_INSNS (3), /* fp */
745 COSTS_N_INSNS (3), /* dmul */
746 COSTS_N_INSNS (13), /* sdiv */
747 COSTS_N_INSNS (16), /* ddiv */
748 128, /* cache line size */
751 16, /* prefetch streams */
755 static bool rs6000_function_ok_for_sibcall (tree, tree);
756 static const char *rs6000_invalid_within_doloop (const_rtx);
757 static rtx rs6000_generate_compare (enum rtx_code);
758 static void rs6000_emit_stack_tie (void);
759 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
760 static bool spe_func_has_64bit_regs_p (void);
761 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
763 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
764 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int, int);
765 static unsigned rs6000_hash_constant (rtx);
766 static unsigned toc_hash_function (const void *);
767 static int toc_hash_eq (const void *, const void *);
768 static int constant_pool_expr_1 (rtx, int *, int *);
769 static bool constant_pool_expr_p (rtx);
770 static bool legitimate_small_data_p (enum machine_mode, rtx);
771 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
772 static struct machine_function * rs6000_init_machine_status (void);
773 static bool rs6000_assemble_integer (rtx, unsigned int, int);
774 static bool no_global_regs_above (int, bool);
775 #ifdef HAVE_GAS_HIDDEN
776 static void rs6000_assemble_visibility (tree, int);
778 static int rs6000_ra_ever_killed (void);
779 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
780 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
781 static bool rs6000_ms_bitfield_layout_p (const_tree);
782 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
783 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
784 static const char *rs6000_mangle_type (const_tree);
785 extern const struct attribute_spec rs6000_attribute_table[];
786 static void rs6000_set_default_type_attributes (tree);
787 static rtx rs6000_savres_routine_sym (rs6000_stack_t *, bool, bool, bool);
788 static void rs6000_emit_stack_reset (rs6000_stack_t *, rtx, rtx, int, bool);
789 static rtx rs6000_make_savres_rtx (rs6000_stack_t *, rtx, int,
790 enum machine_mode, bool, bool, bool);
791 static bool rs6000_reg_live_or_pic_offset_p (int);
792 static int rs6000_savres_strategy (rs6000_stack_t *, bool, int, int);
793 static void rs6000_restore_saved_cr (rtx, int);
794 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
795 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
796 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
798 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
799 static bool rs6000_return_in_memory (const_tree, const_tree);
800 static void rs6000_file_start (void);
802 static int rs6000_elf_reloc_rw_mask (void);
803 static void rs6000_elf_asm_out_constructor (rtx, int);
804 static void rs6000_elf_asm_out_destructor (rtx, int);
805 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
806 static void rs6000_elf_asm_init_sections (void);
807 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
808 unsigned HOST_WIDE_INT);
809 static void rs6000_elf_encode_section_info (tree, rtx, int)
812 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
813 static void rs6000_alloc_sdmode_stack_slot (void);
814 static void rs6000_instantiate_decls (void);
816 static void rs6000_xcoff_asm_output_anchor (rtx);
817 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
818 static void rs6000_xcoff_asm_init_sections (void);
819 static int rs6000_xcoff_reloc_rw_mask (void);
820 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
821 static section *rs6000_xcoff_select_section (tree, int,
822 unsigned HOST_WIDE_INT);
823 static void rs6000_xcoff_unique_section (tree, int);
824 static section *rs6000_xcoff_select_rtx_section
825 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
826 static const char * rs6000_xcoff_strip_name_encoding (const char *);
827 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
828 static void rs6000_xcoff_file_start (void);
829 static void rs6000_xcoff_file_end (void);
831 static int rs6000_variable_issue (FILE *, int, rtx, int);
832 static bool rs6000_rtx_costs (rtx, int, int, int *);
833 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
834 static void rs6000_sched_init (FILE *, int, int);
835 static bool is_microcoded_insn (rtx);
836 static bool is_nonpipeline_insn (rtx);
837 static bool is_cracked_insn (rtx);
838 static bool is_branch_slot_insn (rtx);
839 static bool is_load_insn (rtx);
840 static rtx get_store_dest (rtx pat);
841 static bool is_store_insn (rtx);
842 static bool set_to_load_agen (rtx,rtx);
843 static bool adjacent_mem_locations (rtx,rtx);
844 static int rs6000_adjust_priority (rtx, int);
845 static int rs6000_issue_rate (void);
846 static bool rs6000_is_costly_dependence (dep_t, int, int);
847 static rtx get_next_active_insn (rtx, rtx);
848 static bool insn_terminates_group_p (rtx , enum group_termination);
849 static bool insn_must_be_first_in_group (rtx);
850 static bool insn_must_be_last_in_group (rtx);
851 static bool is_costly_group (rtx *, rtx);
852 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
853 static int redefine_groups (FILE *, int, rtx, rtx);
854 static int pad_groups (FILE *, int, rtx, rtx);
855 static void rs6000_sched_finish (FILE *, int);
856 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
857 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
858 static int rs6000_use_sched_lookahead (void);
859 static int rs6000_use_sched_lookahead_guard (rtx);
860 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
861 static tree rs6000_builtin_mask_for_load (void);
862 static tree rs6000_builtin_mul_widen_even (tree);
863 static tree rs6000_builtin_mul_widen_odd (tree);
864 static tree rs6000_builtin_conversion (enum tree_code, tree);
866 static void def_builtin (int, const char *, tree, int);
867 static bool rs6000_vector_alignment_reachable (const_tree, bool);
868 static void rs6000_init_builtins (void);
869 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
870 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
871 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
872 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
873 static void altivec_init_builtins (void);
874 static void rs6000_common_init_builtins (void);
875 static void rs6000_init_libfuncs (void);
877 static void paired_init_builtins (void);
878 static rtx paired_expand_builtin (tree, rtx, bool *);
879 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
880 static rtx paired_expand_stv_builtin (enum insn_code, tree);
881 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
883 static void enable_mask_for_builtins (struct builtin_description *, int,
884 enum rs6000_builtins,
885 enum rs6000_builtins);
886 static tree build_opaque_vector_type (tree, int);
887 static void spe_init_builtins (void);
888 static rtx spe_expand_builtin (tree, rtx, bool *);
889 static rtx spe_expand_stv_builtin (enum insn_code, tree);
890 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
891 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
892 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
893 static rs6000_stack_t *rs6000_stack_info (void);
894 static void debug_stack_info (rs6000_stack_t *);
896 static rtx altivec_expand_builtin (tree, rtx, bool *);
897 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
898 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
899 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
900 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
901 static rtx altivec_expand_predicate_builtin (enum insn_code,
902 const char *, tree, rtx);
903 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
904 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
905 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
906 static rtx altivec_expand_vec_set_builtin (tree);
907 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
908 static int get_element_number (tree, tree);
909 static bool rs6000_handle_option (size_t, const char *, int);
910 static void rs6000_parse_tls_size_option (void);
911 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
912 static int first_altivec_reg_to_save (void);
913 static unsigned int compute_vrsave_mask (void);
914 static void compute_save_world_info (rs6000_stack_t *info_ptr);
915 static void is_altivec_return_reg (rtx, void *);
916 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
917 int easy_vector_constant (rtx, enum machine_mode);
918 static bool rs6000_is_opaque_type (const_tree);
919 static rtx rs6000_dwarf_register_span (rtx);
920 static void rs6000_init_dwarf_reg_sizes_extra (tree);
921 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
922 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
923 static rtx rs6000_tls_get_addr (void);
924 static rtx rs6000_got_sym (void);
925 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
926 static const char *rs6000_get_some_local_dynamic_name (void);
927 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
928 static rtx rs6000_complex_function_value (enum machine_mode);
929 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
930 enum machine_mode, tree);
931 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
933 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
934 tree, HOST_WIDE_INT);
935 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
938 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
939 const_tree, HOST_WIDE_INT,
941 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool);
942 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
943 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
944 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
945 enum machine_mode, tree,
947 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
949 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
951 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
953 static void macho_branch_islands (void);
954 static int no_previous_def (tree function_name);
955 static tree get_prev_label (tree function_name);
956 static void rs6000_darwin_file_start (void);
959 static tree rs6000_build_builtin_va_list (void);
960 static void rs6000_va_start (tree, rtx);
961 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
962 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
963 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
964 static bool rs6000_vector_mode_supported_p (enum machine_mode);
965 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
967 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
969 static int get_vsel_insn (enum machine_mode);
970 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
971 static tree rs6000_stack_protect_fail (void);
973 const int INSN_NOT_AVAILABLE = -1;
974 static enum machine_mode rs6000_eh_return_filter_mode (void);
976 /* Hash table stuff for keeping track of TOC entries. */
978 struct toc_hash_struct GTY(())
980 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
981 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
983 enum machine_mode key_mode;
987 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
989 /* Default register names. */
990 char rs6000_reg_names[][8] =
992 "0", "1", "2", "3", "4", "5", "6", "7",
993 "8", "9", "10", "11", "12", "13", "14", "15",
994 "16", "17", "18", "19", "20", "21", "22", "23",
995 "24", "25", "26", "27", "28", "29", "30", "31",
996 "0", "1", "2", "3", "4", "5", "6", "7",
997 "8", "9", "10", "11", "12", "13", "14", "15",
998 "16", "17", "18", "19", "20", "21", "22", "23",
999 "24", "25", "26", "27", "28", "29", "30", "31",
1000 "mq", "lr", "ctr","ap",
1001 "0", "1", "2", "3", "4", "5", "6", "7",
1003 /* AltiVec registers. */
1004 "0", "1", "2", "3", "4", "5", "6", "7",
1005 "8", "9", "10", "11", "12", "13", "14", "15",
1006 "16", "17", "18", "19", "20", "21", "22", "23",
1007 "24", "25", "26", "27", "28", "29", "30", "31",
1009 /* SPE registers. */
1010 "spe_acc", "spefscr",
1011 /* Soft frame pointer. */
1015 #ifdef TARGET_REGNAMES
1016 static const char alt_reg_names[][8] =
1018 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1019 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1020 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1021 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1022 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1023 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1024 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1025 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1026 "mq", "lr", "ctr", "ap",
1027 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1029 /* AltiVec registers. */
1030 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1031 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1032 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1033 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1035 /* SPE registers. */
1036 "spe_acc", "spefscr",
1037 /* Soft frame pointer. */
1042 #ifndef MASK_STRICT_ALIGN
1043 #define MASK_STRICT_ALIGN 0
1045 #ifndef TARGET_PROFILE_KERNEL
1046 #define TARGET_PROFILE_KERNEL 0
1049 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1050 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1052 /* Initialize the GCC target structure. */
1053 #undef TARGET_ATTRIBUTE_TABLE
1054 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1055 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1056 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1058 #undef TARGET_ASM_ALIGNED_DI_OP
1059 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1061 /* Default unaligned ops are only provided for ELF. Find the ops needed
1062 for non-ELF systems. */
1063 #ifndef OBJECT_FORMAT_ELF
1065 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1067 #undef TARGET_ASM_UNALIGNED_HI_OP
1068 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1069 #undef TARGET_ASM_UNALIGNED_SI_OP
1070 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1071 #undef TARGET_ASM_UNALIGNED_DI_OP
1072 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1075 #undef TARGET_ASM_UNALIGNED_HI_OP
1076 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1077 #undef TARGET_ASM_UNALIGNED_SI_OP
1078 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1079 #undef TARGET_ASM_UNALIGNED_DI_OP
1080 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1081 #undef TARGET_ASM_ALIGNED_DI_OP
1082 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1086 /* This hook deals with fixups for relocatable code and DI-mode objects
1088 #undef TARGET_ASM_INTEGER
1089 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1091 #ifdef HAVE_GAS_HIDDEN
1092 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1093 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1096 #undef TARGET_HAVE_TLS
1097 #define TARGET_HAVE_TLS HAVE_AS_TLS
1099 #undef TARGET_CANNOT_FORCE_CONST_MEM
1100 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1102 #undef TARGET_ASM_FUNCTION_PROLOGUE
1103 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1104 #undef TARGET_ASM_FUNCTION_EPILOGUE
1105 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1107 #undef TARGET_SCHED_VARIABLE_ISSUE
1108 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1110 #undef TARGET_SCHED_ISSUE_RATE
1111 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1112 #undef TARGET_SCHED_ADJUST_COST
1113 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1114 #undef TARGET_SCHED_ADJUST_PRIORITY
1115 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1116 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1117 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1118 #undef TARGET_SCHED_INIT
1119 #define TARGET_SCHED_INIT rs6000_sched_init
1120 #undef TARGET_SCHED_FINISH
1121 #define TARGET_SCHED_FINISH rs6000_sched_finish
1122 #undef TARGET_SCHED_REORDER
1123 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1124 #undef TARGET_SCHED_REORDER2
1125 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1127 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1128 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1130 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1131 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1133 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1134 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1135 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1136 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1137 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1138 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1139 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1140 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1142 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1143 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1145 #undef TARGET_INIT_BUILTINS
1146 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1148 #undef TARGET_EXPAND_BUILTIN
1149 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1151 #undef TARGET_MANGLE_TYPE
1152 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1154 #undef TARGET_INIT_LIBFUNCS
1155 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1158 #undef TARGET_BINDS_LOCAL_P
1159 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1162 #undef TARGET_MS_BITFIELD_LAYOUT_P
1163 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1165 #undef TARGET_ASM_OUTPUT_MI_THUNK
1166 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1168 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1169 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1171 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1172 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1174 #undef TARGET_INVALID_WITHIN_DOLOOP
1175 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1177 #undef TARGET_RTX_COSTS
1178 #define TARGET_RTX_COSTS rs6000_rtx_costs
1179 #undef TARGET_ADDRESS_COST
1180 #define TARGET_ADDRESS_COST hook_int_rtx_0
1182 #undef TARGET_VECTOR_OPAQUE_P
1183 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1185 #undef TARGET_DWARF_REGISTER_SPAN
1186 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1188 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1189 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1191 /* On rs6000, function arguments are promoted, as are function return
1193 #undef TARGET_PROMOTE_FUNCTION_ARGS
1194 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1195 #undef TARGET_PROMOTE_FUNCTION_RETURN
1196 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1198 #undef TARGET_RETURN_IN_MEMORY
1199 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1201 #undef TARGET_SETUP_INCOMING_VARARGS
1202 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1204 /* Always strict argument naming on rs6000. */
1205 #undef TARGET_STRICT_ARGUMENT_NAMING
1206 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1207 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1208 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1209 #undef TARGET_SPLIT_COMPLEX_ARG
1210 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1211 #undef TARGET_MUST_PASS_IN_STACK
1212 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1213 #undef TARGET_PASS_BY_REFERENCE
1214 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1215 #undef TARGET_ARG_PARTIAL_BYTES
1216 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1218 #undef TARGET_BUILD_BUILTIN_VA_LIST
1219 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1221 #undef TARGET_EXPAND_BUILTIN_VA_START
1222 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1224 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1225 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1227 #undef TARGET_EH_RETURN_FILTER_MODE
1228 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1230 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1231 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1233 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1234 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1236 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1237 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1239 #undef TARGET_HANDLE_OPTION
1240 #define TARGET_HANDLE_OPTION rs6000_handle_option
1242 #undef TARGET_DEFAULT_TARGET_FLAGS
1243 #define TARGET_DEFAULT_TARGET_FLAGS \
1246 #undef TARGET_STACK_PROTECT_FAIL
1247 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1249 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1250 The PowerPC architecture requires only weak consistency among
1251 processors--that is, memory accesses between processors need not be
1252 sequentially consistent and memory accesses among processors can occur
1253 in any order. The ability to order memory accesses weakly provides
1254 opportunities for more efficient use of the system bus. Unless a
1255 dependency exists, the 604e allows read operations to precede store
1257 #undef TARGET_RELAXED_ORDERING
1258 #define TARGET_RELAXED_ORDERING true
1261 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1262 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1265 /* Use a 32-bit anchor range. This leads to sequences like:
1267 addis tmp,anchor,high
1270 where tmp itself acts as an anchor, and can be shared between
1271 accesses to the same 64k page. */
1272 #undef TARGET_MIN_ANCHOR_OFFSET
1273 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1274 #undef TARGET_MAX_ANCHOR_OFFSET
1275 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1276 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1277 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1279 #undef TARGET_BUILTIN_RECIPROCAL
1280 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1282 #undef TARGET_EXPAND_TO_RTL_HOOK
1283 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1285 #undef TARGET_INSTANTIATE_DECLS
1286 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1288 struct gcc_target targetm = TARGET_INITIALIZER;
1291 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1294 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1296 /* The GPRs can hold any mode, but values bigger than one register
1297 cannot go past R31. */
1298 if (INT_REGNO_P (regno))
1299 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1301 /* The float registers can only hold floating modes and DImode.
1302 This excludes the 32-bit decimal float mode for now. */
1303 if (FP_REGNO_P (regno))
1305 ((SCALAR_FLOAT_MODE_P (mode)
1306 && (mode != TDmode || (regno % 2) == 0)
1307 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1308 || (GET_MODE_CLASS (mode) == MODE_INT
1309 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1310 || (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1311 && PAIRED_VECTOR_MODE (mode)));
1313 /* The CR register can only hold CC modes. */
1314 if (CR_REGNO_P (regno))
1315 return GET_MODE_CLASS (mode) == MODE_CC;
1317 if (XER_REGNO_P (regno))
1318 return mode == PSImode;
1320 /* AltiVec only in AldyVec registers. */
1321 if (ALTIVEC_REGNO_P (regno))
1322 return ALTIVEC_VECTOR_MODE (mode);
1324 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1325 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1328 /* We cannot put TImode anywhere except general register and it must be
1329 able to fit within the register set. */
1331 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1334 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1336 rs6000_init_hard_regno_mode_ok (void)
1340 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1341 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1342 if (rs6000_hard_regno_mode_ok (r, m))
1343 rs6000_hard_regno_mode_ok_p[m][r] = true;
1347 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1350 darwin_rs6000_override_options (void)
1352 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1354 rs6000_altivec_abi = 1;
1355 TARGET_ALTIVEC_VRSAVE = 1;
1356 if (DEFAULT_ABI == ABI_DARWIN)
1358 if (MACHO_DYNAMIC_NO_PIC_P)
1361 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1364 else if (flag_pic == 1)
1369 if (TARGET_64BIT && ! TARGET_POWERPC64)
1371 target_flags |= MASK_POWERPC64;
1372 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1376 rs6000_default_long_calls = 1;
1377 target_flags |= MASK_SOFT_FLOAT;
1380 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1382 if (!flag_mkernel && !flag_apple_kext
1384 && ! (target_flags_explicit & MASK_ALTIVEC))
1385 target_flags |= MASK_ALTIVEC;
1387 /* Unless the user (not the configurer) has explicitly overridden
1388 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1389 G4 unless targetting the kernel. */
1392 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1393 && ! (target_flags_explicit & MASK_ALTIVEC)
1394 && ! rs6000_select[1].string)
1396 target_flags |= MASK_ALTIVEC;
1401 /* If not otherwise specified by a target, make 'long double' equivalent to
1404 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1405 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1408 /* Override command line options. Mostly we process the processor
1409 type and sometimes adjust other TARGET_ options. */
1412 rs6000_override_options (const char *default_cpu)
1415 struct rs6000_cpu_select *ptr;
1418 /* Simplifications for entries below. */
1421 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1422 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1425 /* This table occasionally claims that a processor does not support
1426 a particular feature even though it does, but the feature is slower
1427 than the alternative. Thus, it shouldn't be relied on as a
1428 complete description of the processor's support.
1430 Please keep this list in order, and don't forget to update the
1431 documentation in invoke.texi when adding a new processor or
1435 const char *const name; /* Canonical processor name. */
1436 const enum processor_type processor; /* Processor type enum value. */
1437 const int target_enable; /* Target flags to enable. */
1438 } const processor_target_table[]
1439 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1440 {"403", PROCESSOR_PPC403,
1441 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1442 {"405", PROCESSOR_PPC405,
1443 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1444 {"405fp", PROCESSOR_PPC405,
1445 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1446 {"440", PROCESSOR_PPC440,
1447 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1448 {"440fp", PROCESSOR_PPC440,
1449 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1450 {"464", PROCESSOR_PPC440,
1451 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1452 {"464fp", PROCESSOR_PPC440,
1453 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1454 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1455 {"601", PROCESSOR_PPC601,
1456 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1457 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1458 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1459 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1460 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1461 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1462 {"620", PROCESSOR_PPC620,
1463 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1464 {"630", PROCESSOR_PPC630,
1465 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1466 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1467 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1468 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1469 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1470 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1471 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1472 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1473 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1474 /* 8548 has a dummy entry for now. */
1475 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1476 {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1477 {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
1478 {"e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1479 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1480 {"970", PROCESSOR_POWER4,
1481 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1482 {"cell", PROCESSOR_CELL,
1483 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1484 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1485 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1486 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1487 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1488 {"G5", PROCESSOR_POWER4,
1489 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1490 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1491 {"power2", PROCESSOR_POWER,
1492 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1493 {"power3", PROCESSOR_PPC630,
1494 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1495 {"power4", PROCESSOR_POWER4,
1496 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1497 {"power5", PROCESSOR_POWER5,
1498 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1499 | MASK_MFCRF | MASK_POPCNTB},
1500 {"power5+", PROCESSOR_POWER5,
1501 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1502 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1503 {"power6", PROCESSOR_POWER6,
1504 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1505 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1506 {"power6x", PROCESSOR_POWER6,
1507 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1508 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1509 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1510 {"powerpc64", PROCESSOR_POWERPC64,
1511 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1512 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1513 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1514 {"rios2", PROCESSOR_RIOS2,
1515 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1516 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1517 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1518 {"rs64", PROCESSOR_RS64A,
1519 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1522 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1524 /* Some OSs don't support saving the high part of 64-bit registers on
1525 context switch. Other OSs don't support saving Altivec registers.
1526 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1527 settings; if the user wants either, the user must explicitly specify
1528 them and we won't interfere with the user's specification. */
1531 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1532 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1533 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1534 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1535 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1538 rs6000_init_hard_regno_mode_ok ();
1540 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1541 #ifdef OS_MISSING_POWERPC64
1542 if (OS_MISSING_POWERPC64)
1543 set_masks &= ~MASK_POWERPC64;
1545 #ifdef OS_MISSING_ALTIVEC
1546 if (OS_MISSING_ALTIVEC)
1547 set_masks &= ~MASK_ALTIVEC;
1550 /* Don't override by the processor default if given explicitly. */
1551 set_masks &= ~target_flags_explicit;
1553 /* Identify the processor type. */
1554 rs6000_select[0].string = default_cpu;
1555 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1557 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1559 ptr = &rs6000_select[i];
1560 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1562 for (j = 0; j < ptt_size; j++)
1563 if (! strcmp (ptr->string, processor_target_table[j].name))
1565 if (ptr->set_tune_p)
1566 rs6000_cpu = processor_target_table[j].processor;
1568 if (ptr->set_arch_p)
1570 target_flags &= ~set_masks;
1571 target_flags |= (processor_target_table[j].target_enable
1578 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1582 if ((TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
1583 && !rs6000_explicit_options.isel)
1586 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
1587 || rs6000_cpu == PROCESSOR_PPCE500MC)
1590 error ("AltiVec not supported in this target");
1592 error ("Spe not supported in this target");
1595 /* If we are optimizing big endian systems for space, use the load/store
1596 multiple and string instructions. */
1597 if (BYTES_BIG_ENDIAN && optimize_size)
1598 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1600 /* Don't allow -mmultiple or -mstring on little endian systems
1601 unless the cpu is a 750, because the hardware doesn't support the
1602 instructions used in little endian mode, and causes an alignment
1603 trap. The 750 does not cause an alignment trap (except when the
1604 target is unaligned). */
1606 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1608 if (TARGET_MULTIPLE)
1610 target_flags &= ~MASK_MULTIPLE;
1611 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1612 warning (0, "-mmultiple is not supported on little endian systems");
1617 target_flags &= ~MASK_STRING;
1618 if ((target_flags_explicit & MASK_STRING) != 0)
1619 warning (0, "-mstring is not supported on little endian systems");
1623 /* Set debug flags */
1624 if (rs6000_debug_name)
1626 if (! strcmp (rs6000_debug_name, "all"))
1627 rs6000_debug_stack = rs6000_debug_arg = 1;
1628 else if (! strcmp (rs6000_debug_name, "stack"))
1629 rs6000_debug_stack = 1;
1630 else if (! strcmp (rs6000_debug_name, "arg"))
1631 rs6000_debug_arg = 1;
1633 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1636 if (rs6000_traceback_name)
1638 if (! strncmp (rs6000_traceback_name, "full", 4))
1639 rs6000_traceback = traceback_full;
1640 else if (! strncmp (rs6000_traceback_name, "part", 4))
1641 rs6000_traceback = traceback_part;
1642 else if (! strncmp (rs6000_traceback_name, "no", 2))
1643 rs6000_traceback = traceback_none;
1645 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1646 rs6000_traceback_name);
1649 if (!rs6000_explicit_options.long_double)
1650 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1652 #ifndef POWERPC_LINUX
1653 if (!rs6000_explicit_options.ieee)
1654 rs6000_ieeequad = 1;
1657 /* Enable Altivec ABI for AIX -maltivec. */
1658 if (TARGET_XCOFF && TARGET_ALTIVEC)
1659 rs6000_altivec_abi = 1;
1661 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1662 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1663 be explicitly overridden in either case. */
1666 if (!rs6000_explicit_options.altivec_abi
1667 && (TARGET_64BIT || TARGET_ALTIVEC))
1668 rs6000_altivec_abi = 1;
1670 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1671 if (!rs6000_explicit_options.vrsave)
1672 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
1675 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1676 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1678 rs6000_darwin64_abi = 1;
1680 darwin_one_byte_bool = 1;
1682 /* Default to natural alignment, for better performance. */
1683 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1686 /* Place FP constants in the constant pool instead of TOC
1687 if section anchors enabled. */
1688 if (flag_section_anchors)
1689 TARGET_NO_FP_IN_TOC = 1;
1691 /* Handle -mtls-size option. */
1692 rs6000_parse_tls_size_option ();
1694 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1695 SUBTARGET_OVERRIDE_OPTIONS;
1697 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1698 SUBSUBTARGET_OVERRIDE_OPTIONS;
1700 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1701 SUB3TARGET_OVERRIDE_OPTIONS;
1704 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
1706 /* The e500 and e500mc do not have string instructions, and we set
1707 MASK_STRING above when optimizing for size. */
1708 if ((target_flags & MASK_STRING) != 0)
1709 target_flags = target_flags & ~MASK_STRING;
1711 else if (rs6000_select[1].string != NULL)
1713 /* For the powerpc-eabispe configuration, we set all these by
1714 default, so let's unset them if we manually set another
1715 CPU that is not the E500. */
1716 if (!rs6000_explicit_options.spe_abi)
1718 if (!rs6000_explicit_options.spe)
1720 if (!rs6000_explicit_options.float_gprs)
1721 rs6000_float_gprs = 0;
1722 if (!rs6000_explicit_options.isel)
1726 /* Detect invalid option combinations with E500. */
1729 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1730 && rs6000_cpu != PROCESSOR_POWER5
1731 && rs6000_cpu != PROCESSOR_POWER6
1732 && rs6000_cpu != PROCESSOR_CELL);
1733 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1734 || rs6000_cpu == PROCESSOR_POWER5);
1735 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1736 || rs6000_cpu == PROCESSOR_POWER5
1737 || rs6000_cpu == PROCESSOR_POWER6);
1739 rs6000_sched_restricted_insns_priority
1740 = (rs6000_sched_groups ? 1 : 0);
1742 /* Handle -msched-costly-dep option. */
1743 rs6000_sched_costly_dep
1744 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1746 if (rs6000_sched_costly_dep_str)
1748 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1749 rs6000_sched_costly_dep = no_dep_costly;
1750 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1751 rs6000_sched_costly_dep = all_deps_costly;
1752 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1753 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1754 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1755 rs6000_sched_costly_dep = store_to_load_dep_costly;
1757 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1760 /* Handle -minsert-sched-nops option. */
1761 rs6000_sched_insert_nops
1762 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1764 if (rs6000_sched_insert_nops_str)
1766 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1767 rs6000_sched_insert_nops = sched_finish_none;
1768 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1769 rs6000_sched_insert_nops = sched_finish_pad_groups;
1770 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1771 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1773 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1776 #ifdef TARGET_REGNAMES
1777 /* If the user desires alternate register names, copy in the
1778 alternate names now. */
1779 if (TARGET_REGNAMES)
1780 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1783 /* Set aix_struct_return last, after the ABI is determined.
1784 If -maix-struct-return or -msvr4-struct-return was explicitly
1785 used, don't override with the ABI default. */
1786 if (!rs6000_explicit_options.aix_struct_ret)
1787 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1789 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1790 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1793 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1795 /* We can only guarantee the availability of DI pseudo-ops when
1796 assembling for 64-bit targets. */
1799 targetm.asm_out.aligned_op.di = NULL;
1800 targetm.asm_out.unaligned_op.di = NULL;
1803 /* Set branch target alignment, if not optimizing for size. */
1806 /* Cell wants to be aligned 8byte for dual issue. */
1807 if (rs6000_cpu == PROCESSOR_CELL)
1809 if (align_functions <= 0)
1810 align_functions = 8;
1811 if (align_jumps <= 0)
1813 if (align_loops <= 0)
1816 if (rs6000_align_branch_targets)
1818 if (align_functions <= 0)
1819 align_functions = 16;
1820 if (align_jumps <= 0)
1822 if (align_loops <= 0)
1825 if (align_jumps_max_skip <= 0)
1826 align_jumps_max_skip = 15;
1827 if (align_loops_max_skip <= 0)
1828 align_loops_max_skip = 15;
1831 /* Arrange to save and restore machine status around nested functions. */
1832 init_machine_status = rs6000_init_machine_status;
1834 /* We should always be splitting complex arguments, but we can't break
1835 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1836 if (DEFAULT_ABI != ABI_AIX)
1837 targetm.calls.split_complex_arg = NULL;
1839 /* Initialize rs6000_cost with the appropriate target costs. */
1841 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1845 case PROCESSOR_RIOS1:
1846 rs6000_cost = &rios1_cost;
1849 case PROCESSOR_RIOS2:
1850 rs6000_cost = &rios2_cost;
1853 case PROCESSOR_RS64A:
1854 rs6000_cost = &rs64a_cost;
1857 case PROCESSOR_MPCCORE:
1858 rs6000_cost = &mpccore_cost;
1861 case PROCESSOR_PPC403:
1862 rs6000_cost = &ppc403_cost;
1865 case PROCESSOR_PPC405:
1866 rs6000_cost = &ppc405_cost;
1869 case PROCESSOR_PPC440:
1870 rs6000_cost = &ppc440_cost;
1873 case PROCESSOR_PPC601:
1874 rs6000_cost = &ppc601_cost;
1877 case PROCESSOR_PPC603:
1878 rs6000_cost = &ppc603_cost;
1881 case PROCESSOR_PPC604:
1882 rs6000_cost = &ppc604_cost;
1885 case PROCESSOR_PPC604e:
1886 rs6000_cost = &ppc604e_cost;
1889 case PROCESSOR_PPC620:
1890 rs6000_cost = &ppc620_cost;
1893 case PROCESSOR_PPC630:
1894 rs6000_cost = &ppc630_cost;
1897 case PROCESSOR_CELL:
1898 rs6000_cost = &ppccell_cost;
1901 case PROCESSOR_PPC750:
1902 case PROCESSOR_PPC7400:
1903 rs6000_cost = &ppc750_cost;
1906 case PROCESSOR_PPC7450:
1907 rs6000_cost = &ppc7450_cost;
1910 case PROCESSOR_PPC8540:
1911 rs6000_cost = &ppc8540_cost;
1914 case PROCESSOR_PPCE300C2:
1915 case PROCESSOR_PPCE300C3:
1916 rs6000_cost = &ppce300c2c3_cost;
1919 case PROCESSOR_PPCE500MC:
1920 rs6000_cost = &ppce500mc_cost;
1923 case PROCESSOR_POWER4:
1924 case PROCESSOR_POWER5:
1925 rs6000_cost = &power4_cost;
1928 case PROCESSOR_POWER6:
1929 rs6000_cost = &power6_cost;
1936 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1937 set_param_value ("simultaneous-prefetches",
1938 rs6000_cost->simultaneous_prefetches);
1939 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1940 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1941 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1942 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1943 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1944 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1946 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1947 can be optimized to ap = __builtin_next_arg (0). */
1948 if (DEFAULT_ABI != ABI_V4)
1949 targetm.expand_builtin_va_start = NULL;
1952 /* Implement targetm.vectorize.builtin_mask_for_load. */
1954 rs6000_builtin_mask_for_load (void)
1957 return altivec_builtin_mask_for_load;
1962 /* Implement targetm.vectorize.builtin_conversion. */
1964 rs6000_builtin_conversion (enum tree_code code, tree type)
1966 if (!TARGET_ALTIVEC)
1972 switch (TYPE_MODE (type))
1975 return TYPE_UNSIGNED (type) ?
1976 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1977 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1986 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1988 rs6000_builtin_mul_widen_even (tree type)
1990 if (!TARGET_ALTIVEC)
1993 switch (TYPE_MODE (type))
1996 return TYPE_UNSIGNED (type) ?
1997 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1998 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
2001 return TYPE_UNSIGNED (type) ?
2002 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
2003 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
2009 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
2011 rs6000_builtin_mul_widen_odd (tree type)
2013 if (!TARGET_ALTIVEC)
2016 switch (TYPE_MODE (type))
2019 return TYPE_UNSIGNED (type) ?
2020 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
2021 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
2024 return TYPE_UNSIGNED (type) ?
2025 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
2026 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
2033 /* Return true iff, data reference of TYPE can reach vector alignment (16)
2034 after applying N number of iterations. This routine does not determine
2035 how may iterations are required to reach desired alignment. */
2038 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
2045 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
2048 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
2058 /* Assuming that all other types are naturally aligned. CHECKME! */
2063 /* Handle generic options of the form -mfoo=yes/no.
2064 NAME is the option name.
2065 VALUE is the option value.
2066 FLAG is the pointer to the flag where to store a 1 or 0, depending on
2067 whether the option value is 'yes' or 'no' respectively. */
2069 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
2073 else if (!strcmp (value, "yes"))
2075 else if (!strcmp (value, "no"))
2078 error ("unknown -m%s= option specified: '%s'", name, value);
2081 /* Validate and record the size specified with the -mtls-size option. */
2084 rs6000_parse_tls_size_option (void)
2086 if (rs6000_tls_size_string == 0)
2088 else if (strcmp (rs6000_tls_size_string, "16") == 0)
2089 rs6000_tls_size = 16;
2090 else if (strcmp (rs6000_tls_size_string, "32") == 0)
2091 rs6000_tls_size = 32;
2092 else if (strcmp (rs6000_tls_size_string, "64") == 0)
2093 rs6000_tls_size = 64;
2095 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
2099 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
2101 if (DEFAULT_ABI == ABI_DARWIN)
2102 /* The Darwin libraries never set errno, so we might as well
2103 avoid calling them when that's the only reason we would. */
2104 flag_errno_math = 0;
2106 /* Double growth factor to counter reduced min jump length. */
2107 set_param_value ("max-grow-copy-bb-insns", 16);
2109 /* Enable section anchors by default.
2110 Skip section anchors for Objective C and Objective C++
2111 until front-ends fixed. */
2112 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
2113 flag_section_anchors = 1;
2116 /* Implement TARGET_HANDLE_OPTION. */
2119 rs6000_handle_option (size_t code, const char *arg, int value)
2124 target_flags &= ~(MASK_POWER | MASK_POWER2
2125 | MASK_MULTIPLE | MASK_STRING);
2126 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2127 | MASK_MULTIPLE | MASK_STRING);
2129 case OPT_mno_powerpc:
2130 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2131 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2132 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2133 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2136 target_flags &= ~MASK_MINIMAL_TOC;
2137 TARGET_NO_FP_IN_TOC = 0;
2138 TARGET_NO_SUM_IN_TOC = 0;
2139 target_flags_explicit |= MASK_MINIMAL_TOC;
2140 #ifdef TARGET_USES_SYSV4_OPT
2141 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2142 just the same as -mminimal-toc. */
2143 target_flags |= MASK_MINIMAL_TOC;
2144 target_flags_explicit |= MASK_MINIMAL_TOC;
2148 #ifdef TARGET_USES_SYSV4_OPT
2150 /* Make -mtoc behave like -mminimal-toc. */
2151 target_flags |= MASK_MINIMAL_TOC;
2152 target_flags_explicit |= MASK_MINIMAL_TOC;
2156 #ifdef TARGET_USES_AIX64_OPT
2161 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2162 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2163 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2166 #ifdef TARGET_USES_AIX64_OPT
2171 target_flags &= ~MASK_POWERPC64;
2172 target_flags_explicit |= MASK_POWERPC64;
2175 case OPT_minsert_sched_nops_:
2176 rs6000_sched_insert_nops_str = arg;
2179 case OPT_mminimal_toc:
2182 TARGET_NO_FP_IN_TOC = 0;
2183 TARGET_NO_SUM_IN_TOC = 0;
2190 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2191 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2198 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2199 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2203 case OPT_mpowerpc_gpopt:
2204 case OPT_mpowerpc_gfxopt:
2207 target_flags |= MASK_POWERPC;
2208 target_flags_explicit |= MASK_POWERPC;
2212 case OPT_maix_struct_return:
2213 case OPT_msvr4_struct_return:
2214 rs6000_explicit_options.aix_struct_ret = true;
2218 rs6000_explicit_options.vrsave = true;
2219 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2223 rs6000_explicit_options.isel = true;
2224 rs6000_isel = value;
2228 rs6000_explicit_options.isel = true;
2229 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2233 rs6000_explicit_options.spe = true;
2238 rs6000_explicit_options.spe = true;
2239 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2243 rs6000_debug_name = arg;
2246 #ifdef TARGET_USES_SYSV4_OPT
2248 rs6000_abi_name = arg;
2252 rs6000_sdata_name = arg;
2255 case OPT_mtls_size_:
2256 rs6000_tls_size_string = arg;
2259 case OPT_mrelocatable:
2262 target_flags |= MASK_MINIMAL_TOC;
2263 target_flags_explicit |= MASK_MINIMAL_TOC;
2264 TARGET_NO_FP_IN_TOC = 1;
2268 case OPT_mrelocatable_lib:
2271 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2272 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2273 TARGET_NO_FP_IN_TOC = 1;
2277 target_flags &= ~MASK_RELOCATABLE;
2278 target_flags_explicit |= MASK_RELOCATABLE;
2284 if (!strcmp (arg, "altivec"))
2286 rs6000_explicit_options.altivec_abi = true;
2287 rs6000_altivec_abi = 1;
2289 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2292 else if (! strcmp (arg, "no-altivec"))
2294 rs6000_explicit_options.altivec_abi = true;
2295 rs6000_altivec_abi = 0;
2297 else if (! strcmp (arg, "spe"))
2299 rs6000_explicit_options.spe_abi = true;
2301 rs6000_altivec_abi = 0;
2302 if (!TARGET_SPE_ABI)
2303 error ("not configured for ABI: '%s'", arg);
2305 else if (! strcmp (arg, "no-spe"))
2307 rs6000_explicit_options.spe_abi = true;
2311 /* These are here for testing during development only, do not
2312 document in the manual please. */
2313 else if (! strcmp (arg, "d64"))
2315 rs6000_darwin64_abi = 1;
2316 warning (0, "Using darwin64 ABI");
2318 else if (! strcmp (arg, "d32"))
2320 rs6000_darwin64_abi = 0;
2321 warning (0, "Using old darwin ABI");
2324 else if (! strcmp (arg, "ibmlongdouble"))
2326 rs6000_explicit_options.ieee = true;
2327 rs6000_ieeequad = 0;
2328 warning (0, "Using IBM extended precision long double");
2330 else if (! strcmp (arg, "ieeelongdouble"))
2332 rs6000_explicit_options.ieee = true;
2333 rs6000_ieeequad = 1;
2334 warning (0, "Using IEEE extended precision long double");
2339 error ("unknown ABI specified: '%s'", arg);
2345 rs6000_select[1].string = arg;
2349 rs6000_select[2].string = arg;
2352 case OPT_mtraceback_:
2353 rs6000_traceback_name = arg;
2356 case OPT_mfloat_gprs_:
2357 rs6000_explicit_options.float_gprs = true;
2358 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2359 rs6000_float_gprs = 1;
2360 else if (! strcmp (arg, "double"))
2361 rs6000_float_gprs = 2;
2362 else if (! strcmp (arg, "no"))
2363 rs6000_float_gprs = 0;
2366 error ("invalid option for -mfloat-gprs: '%s'", arg);
2371 case OPT_mlong_double_:
2372 rs6000_explicit_options.long_double = true;
2373 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2374 if (value != 64 && value != 128)
2376 error ("Unknown switch -mlong-double-%s", arg);
2377 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2381 rs6000_long_double_type_size = value;
2384 case OPT_msched_costly_dep_:
2385 rs6000_sched_costly_dep_str = arg;
2389 rs6000_explicit_options.alignment = true;
2390 if (! strcmp (arg, "power"))
2392 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2393 some C library functions, so warn about it. The flag may be
2394 useful for performance studies from time to time though, so
2395 don't disable it entirely. */
2396 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2397 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2398 " it is incompatible with the installed C and C++ libraries");
2399 rs6000_alignment_flags = MASK_ALIGN_POWER;
2401 else if (! strcmp (arg, "natural"))
2402 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2405 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2413 /* Do anything needed at the start of the asm file. */
2416 rs6000_file_start (void)
2420 const char *start = buffer;
2421 struct rs6000_cpu_select *ptr;
2422 const char *default_cpu = TARGET_CPU_DEFAULT;
2423 FILE *file = asm_out_file;
2425 default_file_start ();
2427 #ifdef TARGET_BI_ARCH
2428 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2432 if (flag_verbose_asm)
2434 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2435 rs6000_select[0].string = default_cpu;
2437 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2439 ptr = &rs6000_select[i];
2440 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2442 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2447 if (PPC405_ERRATUM77)
2449 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2453 #ifdef USING_ELFOS_H
2454 switch (rs6000_sdata)
2456 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2457 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2458 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2459 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2462 if (rs6000_sdata && g_switch_value)
2464 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2474 #ifdef HAVE_AS_GNU_ATTRIBUTE
2475 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2477 fprintf (file, "\t.gnu_attribute 4, %d\n",
2478 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2479 fprintf (file, "\t.gnu_attribute 8, %d\n",
2480 (TARGET_ALTIVEC_ABI ? 2
2481 : TARGET_SPE_ABI ? 3
2486 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2488 switch_to_section (toc_section);
2489 switch_to_section (text_section);
2494 /* Return nonzero if this function is known to have a null epilogue. */
2497 direct_return (void)
2499 if (reload_completed)
2501 rs6000_stack_t *info = rs6000_stack_info ();
2503 if (info->first_gp_reg_save == 32
2504 && info->first_fp_reg_save == 64
2505 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2506 && ! info->lr_save_p
2507 && ! info->cr_save_p
2508 && info->vrsave_mask == 0
2516 /* Return the number of instructions it takes to form a constant in an
2517 integer register. */
2520 num_insns_constant_wide (HOST_WIDE_INT value)
2522 /* signed constant loadable with {cal|addi} */
2523 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2526 /* constant loadable with {cau|addis} */
2527 else if ((value & 0xffff) == 0
2528 && (value >> 31 == -1 || value >> 31 == 0))
2531 #if HOST_BITS_PER_WIDE_INT == 64
2532 else if (TARGET_POWERPC64)
2534 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2535 HOST_WIDE_INT high = value >> 31;
2537 if (high == 0 || high == -1)
2543 return num_insns_constant_wide (high) + 1;
2545 return (num_insns_constant_wide (high)
2546 + num_insns_constant_wide (low) + 1);
2555 num_insns_constant (rtx op, enum machine_mode mode)
2557 HOST_WIDE_INT low, high;
2559 switch (GET_CODE (op))
2562 #if HOST_BITS_PER_WIDE_INT == 64
2563 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2564 && mask64_operand (op, mode))
2568 return num_insns_constant_wide (INTVAL (op));
2571 if (mode == SFmode || mode == SDmode)
2576 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2577 if (DECIMAL_FLOAT_MODE_P (mode))
2578 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
2580 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2581 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2584 if (mode == VOIDmode || mode == DImode)
2586 high = CONST_DOUBLE_HIGH (op);
2587 low = CONST_DOUBLE_LOW (op);
2594 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2595 if (DECIMAL_FLOAT_MODE_P (mode))
2596 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2598 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2599 high = l[WORDS_BIG_ENDIAN == 0];
2600 low = l[WORDS_BIG_ENDIAN != 0];
2604 return (num_insns_constant_wide (low)
2605 + num_insns_constant_wide (high));
2608 if ((high == 0 && low >= 0)
2609 || (high == -1 && low < 0))
2610 return num_insns_constant_wide (low);
2612 else if (mask64_operand (op, mode))
2616 return num_insns_constant_wide (high) + 1;
2619 return (num_insns_constant_wide (high)
2620 + num_insns_constant_wide (low) + 1);
2628 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2629 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2630 corresponding element of the vector, but for V4SFmode and V2SFmode,
2631 the corresponding "float" is interpreted as an SImode integer. */
2633 static HOST_WIDE_INT
2634 const_vector_elt_as_int (rtx op, unsigned int elt)
2636 rtx tmp = CONST_VECTOR_ELT (op, elt);
2637 if (GET_MODE (op) == V4SFmode
2638 || GET_MODE (op) == V2SFmode)
2639 tmp = gen_lowpart (SImode, tmp);
2640 return INTVAL (tmp);
2643 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2644 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2645 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2646 all items are set to the same value and contain COPIES replicas of the
2647 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2648 operand and the others are set to the value of the operand's msb. */
2651 vspltis_constant (rtx op, unsigned step, unsigned copies)
2653 enum machine_mode mode = GET_MODE (op);
2654 enum machine_mode inner = GET_MODE_INNER (mode);
2657 unsigned nunits = GET_MODE_NUNITS (mode);
2658 unsigned bitsize = GET_MODE_BITSIZE (inner);
2659 unsigned mask = GET_MODE_MASK (inner);
2661 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2662 HOST_WIDE_INT splat_val = val;
2663 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2665 /* Construct the value to be splatted, if possible. If not, return 0. */
2666 for (i = 2; i <= copies; i *= 2)
2668 HOST_WIDE_INT small_val;
2670 small_val = splat_val >> bitsize;
2672 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2674 splat_val = small_val;
2677 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2678 if (EASY_VECTOR_15 (splat_val))
2681 /* Also check if we can splat, and then add the result to itself. Do so if
2682 the value is positive, of if the splat instruction is using OP's mode;
2683 for splat_val < 0, the splat and the add should use the same mode. */
2684 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2685 && (splat_val >= 0 || (step == 1 && copies == 1)))
2691 /* Check if VAL is present in every STEP-th element, and the
2692 other elements are filled with its most significant bit. */
2693 for (i = 0; i < nunits - 1; ++i)
2695 HOST_WIDE_INT desired_val;
2696 if (((i + 1) & (step - 1)) == 0)
2699 desired_val = msb_val;
2701 if (desired_val != const_vector_elt_as_int (op, i))
2709 /* Return true if OP is of the given MODE and can be synthesized
2710 with a vspltisb, vspltish or vspltisw. */
2713 easy_altivec_constant (rtx op, enum machine_mode mode)
2715 unsigned step, copies;
2717 if (mode == VOIDmode)
2718 mode = GET_MODE (op);
2719 else if (mode != GET_MODE (op))
2722 /* Start with a vspltisw. */
2723 step = GET_MODE_NUNITS (mode) / 4;
2726 if (vspltis_constant (op, step, copies))
2729 /* Then try with a vspltish. */
2735 if (vspltis_constant (op, step, copies))
2738 /* And finally a vspltisb. */
2744 if (vspltis_constant (op, step, copies))
2750 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2751 result is OP. Abort if it is not possible. */
2754 gen_easy_altivec_constant (rtx op)
2756 enum machine_mode mode = GET_MODE (op);
2757 int nunits = GET_MODE_NUNITS (mode);
2758 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2759 unsigned step = nunits / 4;
2760 unsigned copies = 1;
2762 /* Start with a vspltisw. */
2763 if (vspltis_constant (op, step, copies))
2764 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2766 /* Then try with a vspltish. */
2772 if (vspltis_constant (op, step, copies))
2773 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2775 /* And finally a vspltisb. */
2781 if (vspltis_constant (op, step, copies))
2782 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2788 output_vec_const_move (rtx *operands)
2791 enum machine_mode mode;
2796 mode = GET_MODE (dest);
2801 if (zero_constant (vec, mode))
2802 return "vxor %0,%0,%0";
2804 splat_vec = gen_easy_altivec_constant (vec);
2805 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2806 operands[1] = XEXP (splat_vec, 0);
2807 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2810 switch (GET_MODE (splat_vec))
2813 return "vspltisw %0,%1";
2816 return "vspltish %0,%1";
2819 return "vspltisb %0,%1";
2826 gcc_assert (TARGET_SPE);
2828 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2829 pattern of V1DI, V4HI, and V2SF.
2831 FIXME: We should probably return # and add post reload
2832 splitters for these, but this way is so easy ;-). */
2833 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2834 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2835 operands[1] = CONST_VECTOR_ELT (vec, 0);
2836 operands[2] = CONST_VECTOR_ELT (vec, 1);
2838 return "li %0,%1\n\tevmergelo %0,%0,%0";
2840 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2843 /* Initialize TARGET of vector PAIRED to VALS. */
2846 paired_expand_vector_init (rtx target, rtx vals)
2848 enum machine_mode mode = GET_MODE (target);
2849 int n_elts = GET_MODE_NUNITS (mode);
2851 rtx x, new, tmp, constant_op, op1, op2;
2854 for (i = 0; i < n_elts; ++i)
2856 x = XVECEXP (vals, 0, i);
2857 if (!CONSTANT_P (x))
2862 /* Load from constant pool. */
2863 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2869 /* The vector is initialized only with non-constants. */
2870 new = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
2871 XVECEXP (vals, 0, 1));
2873 emit_move_insn (target, new);
2877 /* One field is non-constant and the other one is a constant. Load the
2878 constant from the constant pool and use ps_merge instruction to
2879 construct the whole vector. */
2880 op1 = XVECEXP (vals, 0, 0);
2881 op2 = XVECEXP (vals, 0, 1);
2883 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
2885 tmp = gen_reg_rtx (GET_MODE (constant_op));
2886 emit_move_insn (tmp, constant_op);
2888 if (CONSTANT_P (op1))
2889 new = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
2891 new = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
2893 emit_move_insn (target, new);
2897 paired_expand_vector_move (rtx operands[])
2899 rtx op0 = operands[0], op1 = operands[1];
2901 emit_move_insn (op0, op1);
2904 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
2905 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
2906 operands for the relation operation COND. This is a recursive
2910 paired_emit_vector_compare (enum rtx_code rcode,
2911 rtx dest, rtx op0, rtx op1,
2912 rtx cc_op0, rtx cc_op1)
2914 rtx tmp = gen_reg_rtx (V2SFmode);
2915 rtx tmp1, max, min, equal_zero;
2917 gcc_assert (TARGET_PAIRED_FLOAT);
2918 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
2924 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
2928 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
2929 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
2933 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
2936 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
2939 tmp1 = gen_reg_rtx (V2SFmode);
2940 max = gen_reg_rtx (V2SFmode);
2941 min = gen_reg_rtx (V2SFmode);
2942 equal_zero = gen_reg_rtx (V2SFmode);
2944 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
2945 emit_insn (gen_selv2sf4
2946 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
2947 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
2948 emit_insn (gen_selv2sf4
2949 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
2950 emit_insn (gen_subv2sf3 (tmp1, min, max));
2951 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
2954 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
2957 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
2960 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
2963 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
2966 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
2975 /* Emit vector conditional expression.
2976 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
2977 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
2980 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
2981 rtx cond, rtx cc_op0, rtx cc_op1)
2983 enum rtx_code rcode = GET_CODE (cond);
2985 if (!TARGET_PAIRED_FLOAT)
2988 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
2993 /* Initialize vector TARGET to VALS. */
2996 rs6000_expand_vector_init (rtx target, rtx vals)
2998 enum machine_mode mode = GET_MODE (target);
2999 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3000 int n_elts = GET_MODE_NUNITS (mode);
3001 int n_var = 0, one_var = -1;
3002 bool all_same = true, all_const_zero = true;
3006 for (i = 0; i < n_elts; ++i)
3008 x = XVECEXP (vals, 0, i);
3009 if (!CONSTANT_P (x))
3010 ++n_var, one_var = i;
3011 else if (x != CONST0_RTX (inner_mode))
3012 all_const_zero = false;
3014 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
3020 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
3021 if (mode != V4SFmode && all_const_zero)
3023 /* Zero register. */
3024 emit_insn (gen_rtx_SET (VOIDmode, target,
3025 gen_rtx_XOR (mode, target, target)));
3028 else if (mode != V4SFmode && easy_vector_constant (const_vec, mode))
3030 /* Splat immediate. */
3031 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
3035 ; /* Splat vector element. */
3038 /* Load from constant pool. */
3039 emit_move_insn (target, const_vec);
3044 /* Store value to stack temp. Load vector element. Splat. */
3047 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
3048 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
3049 XVECEXP (vals, 0, 0));
3050 x = gen_rtx_UNSPEC (VOIDmode,
3051 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3052 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3054 gen_rtx_SET (VOIDmode,
3057 x = gen_rtx_VEC_SELECT (inner_mode, target,
3058 gen_rtx_PARALLEL (VOIDmode,
3059 gen_rtvec (1, const0_rtx)));
3060 emit_insn (gen_rtx_SET (VOIDmode, target,
3061 gen_rtx_VEC_DUPLICATE (mode, x)));
3065 /* One field is non-constant. Load constant then overwrite
3069 rtx copy = copy_rtx (vals);
3071 /* Load constant part of vector, substitute neighboring value for
3073 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
3074 rs6000_expand_vector_init (target, copy);
3076 /* Insert variable. */
3077 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
3081 /* Construct the vector in memory one field at a time
3082 and load the whole vector. */
3083 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3084 for (i = 0; i < n_elts; i++)
3085 emit_move_insn (adjust_address_nv (mem, inner_mode,
3086 i * GET_MODE_SIZE (inner_mode)),
3087 XVECEXP (vals, 0, i));
3088 emit_move_insn (target, mem);
3091 /* Set field ELT of TARGET to VAL. */
3094 rs6000_expand_vector_set (rtx target, rtx val, int elt)
3096 enum machine_mode mode = GET_MODE (target);
3097 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3098 rtx reg = gen_reg_rtx (mode);
3100 int width = GET_MODE_SIZE (inner_mode);
3103 /* Load single variable value. */
3104 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
3105 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
3106 x = gen_rtx_UNSPEC (VOIDmode,
3107 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3108 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3110 gen_rtx_SET (VOIDmode,
3114 /* Linear sequence. */
3115 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
3116 for (i = 0; i < 16; ++i)
3117 XVECEXP (mask, 0, i) = GEN_INT (i);
3119 /* Set permute mask to insert element into target. */
3120 for (i = 0; i < width; ++i)
3121 XVECEXP (mask, 0, elt*width + i)
3122 = GEN_INT (i + 0x10);
3123 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
3124 x = gen_rtx_UNSPEC (mode,
3125 gen_rtvec (3, target, reg,
3126 force_reg (V16QImode, x)),
3128 emit_insn (gen_rtx_SET (VOIDmode, target, x));
3131 /* Extract field ELT from VEC into TARGET. */
3134 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
3136 enum machine_mode mode = GET_MODE (vec);
3137 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3140 /* Allocate mode-sized buffer. */
3141 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3143 /* Add offset to field within buffer matching vector element. */
3144 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
3146 /* Store single field into mode-sized buffer. */
3147 x = gen_rtx_UNSPEC (VOIDmode,
3148 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
3149 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3151 gen_rtx_SET (VOIDmode,
3154 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
3157 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3158 implement ANDing by the mask IN. */
3160 build_mask64_2_operands (rtx in, rtx *out)
3162 #if HOST_BITS_PER_WIDE_INT >= 64
3163 unsigned HOST_WIDE_INT c, lsb, m1, m2;
3166 gcc_assert (GET_CODE (in) == CONST_INT);
3171 /* Assume c initially something like 0x00fff000000fffff. The idea
3172 is to rotate the word so that the middle ^^^^^^ group of zeros
3173 is at the MS end and can be cleared with an rldicl mask. We then
3174 rotate back and clear off the MS ^^ group of zeros with a
3176 c = ~c; /* c == 0xff000ffffff00000 */
3177 lsb = c & -c; /* lsb == 0x0000000000100000 */
3178 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
3179 c = ~c; /* c == 0x00fff000000fffff */
3180 c &= -lsb; /* c == 0x00fff00000000000 */
3181 lsb = c & -c; /* lsb == 0x0000100000000000 */
3182 c = ~c; /* c == 0xff000fffffffffff */
3183 c &= -lsb; /* c == 0xff00000000000000 */
3185 while ((lsb >>= 1) != 0)
3186 shift++; /* shift == 44 on exit from loop */
3187 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
3188 m1 = ~m1; /* m1 == 0x000000ffffffffff */
3189 m2 = ~c; /* m2 == 0x00ffffffffffffff */
3193 /* Assume c initially something like 0xff000f0000000000. The idea
3194 is to rotate the word so that the ^^^ middle group of zeros
3195 is at the LS end and can be cleared with an rldicr mask. We then
3196 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3198 lsb = c & -c; /* lsb == 0x0000010000000000 */
3199 m2 = -lsb; /* m2 == 0xffffff0000000000 */
3200 c = ~c; /* c == 0x00fff0ffffffffff */
3201 c &= -lsb; /* c == 0x00fff00000000000 */
3202 lsb = c & -c; /* lsb == 0x0000100000000000 */
3203 c = ~c; /* c == 0xff000fffffffffff */
3204 c &= -lsb; /* c == 0xff00000000000000 */
3206 while ((lsb >>= 1) != 0)
3207 shift++; /* shift == 44 on exit from loop */
3208 m1 = ~c; /* m1 == 0x00ffffffffffffff */
3209 m1 >>= shift; /* m1 == 0x0000000000000fff */
3210 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
3213 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3214 masks will be all 1's. We are guaranteed more than one transition. */
3215 out[0] = GEN_INT (64 - shift);
3216 out[1] = GEN_INT (m1);
3217 out[2] = GEN_INT (shift);
3218 out[3] = GEN_INT (m2);
3226 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3229 invalid_e500_subreg (rtx op, enum machine_mode mode)
3231 if (TARGET_E500_DOUBLE)
3233 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3234 subreg:TI and reg:TF. Decimal float modes are like integer
3235 modes (only low part of each register used) for this
3237 if (GET_CODE (op) == SUBREG
3238 && (mode == SImode || mode == DImode || mode == TImode
3239 || mode == DDmode || mode == TDmode)
3240 && REG_P (SUBREG_REG (op))
3241 && (GET_MODE (SUBREG_REG (op)) == DFmode
3242 || GET_MODE (SUBREG_REG (op)) == TFmode))
3245 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3247 if (GET_CODE (op) == SUBREG
3248 && (mode == DFmode || mode == TFmode)
3249 && REG_P (SUBREG_REG (op))
3250 && (GET_MODE (SUBREG_REG (op)) == DImode
3251 || GET_MODE (SUBREG_REG (op)) == TImode
3252 || GET_MODE (SUBREG_REG (op)) == DDmode
3253 || GET_MODE (SUBREG_REG (op)) == TDmode))
3258 && GET_CODE (op) == SUBREG
3260 && REG_P (SUBREG_REG (op))
3261 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
3267 /* AIX increases natural record alignment to doubleword if the first
3268 field is an FP double while the FP fields remain word aligned. */
3271 rs6000_special_round_type_align (tree type, unsigned int computed,
3272 unsigned int specified)
3274 unsigned int align = MAX (computed, specified);
3275 tree field = TYPE_FIELDS (type);
3277 /* Skip all non field decls */
3278 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3279 field = TREE_CHAIN (field);
3281 if (field != NULL && field != type)
3283 type = TREE_TYPE (field);
3284 while (TREE_CODE (type) == ARRAY_TYPE)
3285 type = TREE_TYPE (type);
3287 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
3288 align = MAX (align, 64);
3294 /* Darwin increases record alignment to the natural alignment of
3298 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3299 unsigned int specified)
3301 unsigned int align = MAX (computed, specified);
3303 if (TYPE_PACKED (type))
3306 /* Find the first field, looking down into aggregates. */
3308 tree field = TYPE_FIELDS (type);
3309 /* Skip all non field decls */
3310 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3311 field = TREE_CHAIN (field);
3314 type = TREE_TYPE (field);
3315 while (TREE_CODE (type) == ARRAY_TYPE)
3316 type = TREE_TYPE (type);
3317 } while (AGGREGATE_TYPE_P (type));
3319 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3320 align = MAX (align, TYPE_ALIGN (type));
3325 /* Return 1 for an operand in small memory on V.4/eabi. */
3328 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3329 enum machine_mode mode ATTRIBUTE_UNUSED)
3334 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3337 if (DEFAULT_ABI != ABI_V4)
3340 /* Vector and float memory instructions have a limited offset on the
3341 SPE, so using a vector or float variable directly as an operand is
3344 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
3347 if (GET_CODE (op) == SYMBOL_REF)
3350 else if (GET_CODE (op) != CONST
3351 || GET_CODE (XEXP (op, 0)) != PLUS
3352 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3353 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3358 rtx sum = XEXP (op, 0);
3359 HOST_WIDE_INT summand;
3361 /* We have to be careful here, because it is the referenced address
3362 that must be 32k from _SDA_BASE_, not just the symbol. */
3363 summand = INTVAL (XEXP (sum, 1));
3364 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3367 sym_ref = XEXP (sum, 0);
3370 return SYMBOL_REF_SMALL_P (sym_ref);
3376 /* Return true if either operand is a general purpose register. */
3379 gpr_or_gpr_p (rtx op0, rtx op1)
3381 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3382 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3386 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3389 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3391 switch (GET_CODE (op))
3394 if (RS6000_SYMBOL_REF_TLS_P (op))
3396 else if (CONSTANT_POOL_ADDRESS_P (op))
3398 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3406 else if (! strcmp (XSTR (op, 0), toc_label_name))
3415 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3416 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3418 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3427 constant_pool_expr_p (rtx op)
3431 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3435 toc_relative_expr_p (rtx op)
3439 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3443 legitimate_constant_pool_address_p (rtx x)
3446 && GET_CODE (x) == PLUS
3447 && GET_CODE (XEXP (x, 0)) == REG
3448 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3449 && constant_pool_expr_p (XEXP (x, 1)));
3453 legitimate_small_data_p (enum machine_mode mode, rtx x)
3455 return (DEFAULT_ABI == ABI_V4
3456 && !flag_pic && !TARGET_TOC
3457 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3458 && small_data_operand (x, mode));
3461 /* SPE offset addressing is limited to 5-bits worth of double words. */
3462 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3465 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3467 unsigned HOST_WIDE_INT offset, extra;
3469 if (GET_CODE (x) != PLUS)
3471 if (GET_CODE (XEXP (x, 0)) != REG)
3473 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3475 if (legitimate_constant_pool_address_p (x))
3477 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3480 offset = INTVAL (XEXP (x, 1));
3488 /* AltiVec vector modes. Only reg+reg addressing is valid and
3489 constant offset zero should not occur due to canonicalization. */
3496 /* Paired vector modes. Only reg+reg addressing is valid and
3497 constant offset zero should not occur due to canonicalization. */
3498 if (TARGET_PAIRED_FLOAT)
3500 /* SPE vector modes. */
3501 return SPE_CONST_OFFSET_OK (offset);
3504 if (TARGET_E500_DOUBLE)
3505 return SPE_CONST_OFFSET_OK (offset);
3509 /* On e500v2, we may have:
3511 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3513 Which gets addressed with evldd instructions. */
3514 if (TARGET_E500_DOUBLE)
3515 return SPE_CONST_OFFSET_OK (offset);
3517 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3519 else if (offset & 3)
3524 if (TARGET_E500_DOUBLE)
3525 return (SPE_CONST_OFFSET_OK (offset)
3526 && SPE_CONST_OFFSET_OK (offset + 8));
3530 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3532 else if (offset & 3)
3543 return (offset < 0x10000) && (offset + extra < 0x10000);
3547 legitimate_indexed_address_p (rtx x, int strict)
3551 if (GET_CODE (x) != PLUS)
3557 /* Recognize the rtl generated by reload which we know will later be
3558 replaced with proper base and index regs. */
3560 && reload_in_progress
3561 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3565 return (REG_P (op0) && REG_P (op1)
3566 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3567 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3568 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3569 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3573 legitimate_indirect_address_p (rtx x, int strict)
3575 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3579 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3581 if (!TARGET_MACHO || !flag_pic
3582 || mode != SImode || GET_CODE (x) != MEM)
3586 if (GET_CODE (x) != LO_SUM)
3588 if (GET_CODE (XEXP (x, 0)) != REG)
3590 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3594 return CONSTANT_P (x);
3598 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3600 if (GET_CODE (x) != LO_SUM)
3602 if (GET_CODE (XEXP (x, 0)) != REG)
3604 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3606 /* Restrict addressing for DI because of our SUBREG hackery. */
3607 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3608 || mode == DDmode || mode == TDmode
3613 if (TARGET_ELF || TARGET_MACHO)
3615 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3619 if (GET_MODE_NUNITS (mode) != 1)
3621 if (GET_MODE_BITSIZE (mode) > 64
3622 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3623 && !(TARGET_HARD_FLOAT && TARGET_FPRS
3624 && (mode == DFmode || mode == DDmode))))
3627 return CONSTANT_P (x);
3634 /* Try machine-dependent ways of modifying an illegitimate address
3635 to be legitimate. If we find one, return the new, valid address.
3636 This is used from only one place: `memory_address' in explow.c.
3638 OLDX is the address as it was before break_out_memory_refs was
3639 called. In some cases it is useful to look at this to decide what
3642 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3644 It is always safe for this function to do nothing. It exists to
3645 recognize opportunities to optimize the output.
3647 On RS/6000, first check for the sum of a register with a constant
3648 integer that is out of range. If so, generate code to add the
3649 constant with the low-order 16 bits masked to the register and force
3650 this result into another register (this can be done with `cau').
3651 Then generate an address of REG+(CONST&0xffff), allowing for the
3652 possibility of bit 16 being a one.
3654 Then check for the sum of a register and something not constant, try to
3655 load the other things into a register and return the sum. */
3658 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3659 enum machine_mode mode)
3661 if (GET_CODE (x) == SYMBOL_REF)
3663 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3665 return rs6000_legitimize_tls_address (x, model);
3668 if (GET_CODE (x) == PLUS
3669 && GET_CODE (XEXP (x, 0)) == REG
3670 && GET_CODE (XEXP (x, 1)) == CONST_INT
3671 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
3672 && !(SPE_VECTOR_MODE (mode)
3673 || ALTIVEC_VECTOR_MODE (mode)
3674 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3675 || mode == DImode || mode == DDmode
3676 || mode == TDmode))))
3678 HOST_WIDE_INT high_int, low_int;
3680 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3681 high_int = INTVAL (XEXP (x, 1)) - low_int;
3682 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3683 GEN_INT (high_int)), 0);
3684 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3686 else if (GET_CODE (x) == PLUS
3687 && GET_CODE (XEXP (x, 0)) == REG
3688 && GET_CODE (XEXP (x, 1)) != CONST_INT
3689 && GET_MODE_NUNITS (mode) == 1
3690 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3692 || ((mode != DImode && mode != DFmode && mode != DDmode)
3693 || (TARGET_E500_DOUBLE && mode != DDmode)))
3694 && (TARGET_POWERPC64 || mode != DImode)
3699 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3700 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3702 else if (ALTIVEC_VECTOR_MODE (mode))
3706 /* Make sure both operands are registers. */
3707 if (GET_CODE (x) == PLUS)
3708 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3709 force_reg (Pmode, XEXP (x, 1)));
3711 reg = force_reg (Pmode, x);
3714 else if (SPE_VECTOR_MODE (mode)
3715 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3716 || mode == DDmode || mode == TDmode
3717 || mode == DImode)))
3721 /* We accept [reg + reg] and [reg + OFFSET]. */
3723 if (GET_CODE (x) == PLUS)
3725 rtx op1 = XEXP (x, 0);
3726 rtx op2 = XEXP (x, 1);
3729 op1 = force_reg (Pmode, op1);
3731 if (GET_CODE (op2) != REG
3732 && (GET_CODE (op2) != CONST_INT
3733 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
3734 || (GET_MODE_SIZE (mode) > 8
3735 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
3736 op2 = force_reg (Pmode, op2);
3738 /* We can't always do [reg + reg] for these, because [reg +
3739 reg + offset] is not a legitimate addressing mode. */
3740 y = gen_rtx_PLUS (Pmode, op1, op2);
3742 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
3743 return force_reg (Pmode, y);
3748 return force_reg (Pmode, x);
3754 && GET_CODE (x) != CONST_INT
3755 && GET_CODE (x) != CONST_DOUBLE
3757 && GET_MODE_NUNITS (mode) == 1
3758 && (GET_MODE_BITSIZE (mode) <= 32
3759 || ((TARGET_HARD_FLOAT && TARGET_FPRS)
3760 && (mode == DFmode || mode == DDmode))))
3762 rtx reg = gen_reg_rtx (Pmode);
3763 emit_insn (gen_elf_high (reg, x));
3764 return gen_rtx_LO_SUM (Pmode, reg, x);
3766 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3769 && ! MACHO_DYNAMIC_NO_PIC_P
3771 && GET_CODE (x) != CONST_INT
3772 && GET_CODE (x) != CONST_DOUBLE
3774 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3775 || (mode != DFmode && mode != DDmode))
3779 rtx reg = gen_reg_rtx (Pmode);
3780 emit_insn (gen_macho_high (reg, x));
3781 return gen_rtx_LO_SUM (Pmode, reg, x);
3784 && GET_CODE (x) == SYMBOL_REF
3785 && constant_pool_expr_p (x)
3786 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3788 return create_TOC_reference (x);
3794 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3795 We need to emit DTP-relative relocations. */
3798 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3803 fputs ("\t.long\t", file);
3806 fputs (DOUBLE_INT_ASM_OP, file);
3811 output_addr_const (file, x);
3812 fputs ("@dtprel+0x8000", file);
3815 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3817 static GTY(()) rtx rs6000_tls_symbol;
3819 rs6000_tls_get_addr (void)
3821 if (!rs6000_tls_symbol)
3822 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3824 return rs6000_tls_symbol;
3827 /* Construct the SYMBOL_REF for TLS GOT references. */
3829 static GTY(()) rtx rs6000_got_symbol;
3831 rs6000_got_sym (void)
3833 if (!rs6000_got_symbol)
3835 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3836 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3837 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3840 return rs6000_got_symbol;
3843 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3844 this (thread-local) address. */
3847 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3851 dest = gen_reg_rtx (Pmode);
3852 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3858 tlsreg = gen_rtx_REG (Pmode, 13);
3859 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3863 tlsreg = gen_rtx_REG (Pmode, 2);
3864 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3868 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3872 tmp = gen_reg_rtx (Pmode);
3875 tlsreg = gen_rtx_REG (Pmode, 13);
3876 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3880 tlsreg = gen_rtx_REG (Pmode, 2);
3881 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3885 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3887 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3892 rtx r3, got, tga, tmp1, tmp2, eqv;
3894 /* We currently use relocations like @got@tlsgd for tls, which
3895 means the linker will handle allocation of tls entries, placing
3896 them in the .got section. So use a pointer to the .got section,
3897 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3898 or to secondary GOT sections used by 32-bit -fPIC. */
3900 got = gen_rtx_REG (Pmode, 2);
3904 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3907 rtx gsym = rs6000_got_sym ();
3908 got = gen_reg_rtx (Pmode);
3910 rs6000_emit_move (got, gsym, Pmode);
3916 tmp1 = gen_reg_rtx (Pmode);
3917 tmp2 = gen_reg_rtx (Pmode);
3918 tmp3 = gen_reg_rtx (Pmode);
3919 mem = gen_const_mem (Pmode, tmp1);
3921 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3922 emit_move_insn (tmp1,
3923 gen_rtx_REG (Pmode, LR_REGNO));
3924 emit_move_insn (tmp2, mem);
3925 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3926 last = emit_move_insn (got, tmp3);
3927 set_unique_reg_note (last, REG_EQUAL, gsym);
3932 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3934 r3 = gen_rtx_REG (Pmode, 3);
3935 tga = rs6000_tls_get_addr ();
3937 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
3938 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
3939 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
3940 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
3941 else if (DEFAULT_ABI == ABI_V4)
3942 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
3947 insn = emit_call_insn (insn);
3948 RTL_CONST_CALL_P (insn) = 1;
3949 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3950 insn = get_insns ();
3952 emit_libcall_block (insn, dest, r3, addr);
3954 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3956 r3 = gen_rtx_REG (Pmode, 3);
3957 tga = rs6000_tls_get_addr ();
3959 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
3960 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
3961 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
3962 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
3963 else if (DEFAULT_ABI == ABI_V4)
3964 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
3969 insn = emit_call_insn (insn);
3970 RTL_CONST_CALL_P (insn) = 1;
3971 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3972 insn = get_insns ();
3974 tmp1 = gen_reg_rtx (Pmode);
3975 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3977 emit_libcall_block (insn, tmp1, r3, eqv);
3978 if (rs6000_tls_size == 16)
3981 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3983 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3985 else if (rs6000_tls_size == 32)
3987 tmp2 = gen_reg_rtx (Pmode);
3989 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3991 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3994 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3996 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
4000 tmp2 = gen_reg_rtx (Pmode);
4002 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
4004 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
4006 insn = gen_rtx_SET (Pmode, dest,
4007 gen_rtx_PLUS (Pmode, tmp2, tmp1));
4013 /* IE, or 64-bit offset LE. */
4014 tmp2 = gen_reg_rtx (Pmode);
4016 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
4018 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
4021 insn = gen_tls_tls_64 (dest, tmp2, addr);
4023 insn = gen_tls_tls_32 (dest, tmp2, addr);
4031 /* Return 1 if X contains a thread-local symbol. */
4034 rs6000_tls_referenced_p (rtx x)
4036 if (! TARGET_HAVE_TLS)
4039 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
4042 /* Return 1 if *X is a thread-local symbol. This is the same as
4043 rs6000_tls_symbol_ref except for the type of the unused argument. */
4046 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4048 return RS6000_SYMBOL_REF_TLS_P (*x);
4051 /* The convention appears to be to define this wherever it is used.
4052 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
4053 is now used here. */
4054 #ifndef REG_MODE_OK_FOR_BASE_P
4055 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
4058 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4059 replace the input X, or the original X if no replacement is called for.
4060 The output parameter *WIN is 1 if the calling macro should goto WIN,
4063 For RS/6000, we wish to handle large displacements off a base
4064 register by splitting the addend across an addiu/addis and the mem insn.
4065 This cuts number of extra insns needed from 3 to 1.
4067 On Darwin, we use this to generate code for floating point constants.
4068 A movsf_low is generated so we wind up with 2 instructions rather than 3.
4069 The Darwin code is inside #if TARGET_MACHO because only then is
4070 machopic_function_base_name() defined. */
4072 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
4073 int opnum, int type,
4074 int ind_levels ATTRIBUTE_UNUSED, int *win)
4076 /* We must recognize output that we have already generated ourselves. */
4077 if (GET_CODE (x) == PLUS
4078 && GET_CODE (XEXP (x, 0)) == PLUS
4079 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4080 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4081 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4083 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4084 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4085 opnum, (enum reload_type)type);
4091 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
4092 && GET_CODE (x) == LO_SUM
4093 && GET_CODE (XEXP (x, 0)) == PLUS
4094 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
4095 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
4096 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
4097 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
4098 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
4099 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
4100 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
4102 /* Result of previous invocation of this function on Darwin
4103 floating point constant. */
4104 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4105 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4106 opnum, (enum reload_type)type);
4112 /* Force ld/std non-word aligned offset into base register by wrapping
4114 if (GET_CODE (x) == PLUS
4115 && GET_CODE (XEXP (x, 0)) == REG
4116 && REGNO (XEXP (x, 0)) < 32
4117 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4118 && GET_CODE (XEXP (x, 1)) == CONST_INT
4119 && (INTVAL (XEXP (x, 1)) & 3) != 0
4120 && !ALTIVEC_VECTOR_MODE (mode)
4121 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
4122 && TARGET_POWERPC64)
4124 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
4125 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4126 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4127 opnum, (enum reload_type) type);
4132 if (GET_CODE (x) == PLUS
4133 && GET_CODE (XEXP (x, 0)) == REG
4134 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
4135 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4136 && GET_CODE (XEXP (x, 1)) == CONST_INT
4137 && !SPE_VECTOR_MODE (mode)
4138 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
4139 || mode == DDmode || mode == TDmode
4141 && !ALTIVEC_VECTOR_MODE (mode))
4143 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
4144 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
4146 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4148 /* Check for 32-bit overflow. */
4149 if (high + low != val)
4155 /* Reload the high part into a base reg; leave the low part
4156 in the mem directly. */
4158 x = gen_rtx_PLUS (GET_MODE (x),
4159 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
4163 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4164 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4165 opnum, (enum reload_type)type);
4170 if (GET_CODE (x) == SYMBOL_REF
4171 && !ALTIVEC_VECTOR_MODE (mode)
4172 && !SPE_VECTOR_MODE (mode)
4174 && DEFAULT_ABI == ABI_DARWIN
4175 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
4177 && DEFAULT_ABI == ABI_V4
4180 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4181 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4185 && (mode != DImode || TARGET_POWERPC64)
4186 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
4187 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
4192 rtx offset = gen_rtx_CONST (Pmode,
4193 gen_rtx_MINUS (Pmode, x,
4194 machopic_function_base_sym ()));
4195 x = gen_rtx_LO_SUM (GET_MODE (x),
4196 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
4197 gen_rtx_HIGH (Pmode, offset)), offset);
4201 x = gen_rtx_LO_SUM (GET_MODE (x),
4202 gen_rtx_HIGH (Pmode, x), x);
4204 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4205 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4206 opnum, (enum reload_type)type);
4211 /* Reload an offset address wrapped by an AND that represents the
4212 masking of the lower bits. Strip the outer AND and let reload
4213 convert the offset address into an indirect address. */
4215 && ALTIVEC_VECTOR_MODE (mode)
4216 && GET_CODE (x) == AND
4217 && GET_CODE (XEXP (x, 0)) == PLUS
4218 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4219 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4220 && GET_CODE (XEXP (x, 1)) == CONST_INT
4221 && INTVAL (XEXP (x, 1)) == -16)
4229 && GET_CODE (x) == SYMBOL_REF
4230 && constant_pool_expr_p (x)
4231 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
4233 x = create_TOC_reference (x);
4241 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4242 that is a valid memory address for an instruction.
4243 The MODE argument is the machine mode for the MEM expression
4244 that wants to use this address.
4246 On the RS/6000, there are four valid address: a SYMBOL_REF that
4247 refers to a constant pool entry of an address (or the sum of it
4248 plus a constant), a short (16-bit signed) constant plus a register,
4249 the sum of two registers, or a register indirect, possibly with an
4250 auto-increment. For DFmode, DDmode and DImode with a constant plus
4251 register, we must ensure that both words are addressable or PowerPC64
4252 with offset word aligned.
4254 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4255 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4256 because adjacent memory cells are accessed by adding word-sized offsets
4257 during assembly output. */
4259 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
4261 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4263 && ALTIVEC_VECTOR_MODE (mode)
4264 && GET_CODE (x) == AND
4265 && GET_CODE (XEXP (x, 1)) == CONST_INT
4266 && INTVAL (XEXP (x, 1)) == -16)
4269 if (RS6000_SYMBOL_REF_TLS_P (x))
4271 if (legitimate_indirect_address_p (x, reg_ok_strict))
4273 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
4274 && !ALTIVEC_VECTOR_MODE (mode)
4275 && !SPE_VECTOR_MODE (mode)
4278 /* Restrict addressing for DI because of our SUBREG hackery. */
4279 && !(TARGET_E500_DOUBLE
4280 && (mode == DFmode || mode == DDmode || mode == DImode))
4282 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
4284 if (legitimate_small_data_p (mode, x))
4286 if (legitimate_constant_pool_address_p (x))
4288 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4290 && GET_CODE (x) == PLUS
4291 && GET_CODE (XEXP (x, 0)) == REG
4292 && (XEXP (x, 0) == virtual_stack_vars_rtx
4293 || XEXP (x, 0) == arg_pointer_rtx)
4294 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4296 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
4301 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4303 || (mode != DFmode && mode != DDmode)
4304 || (TARGET_E500_DOUBLE && mode != DDmode))
4305 && (TARGET_POWERPC64 || mode != DImode)
4306 && legitimate_indexed_address_p (x, reg_ok_strict))
4308 if (GET_CODE (x) == PRE_MODIFY
4312 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4314 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
4315 && (TARGET_POWERPC64 || mode != DImode)
4316 && !ALTIVEC_VECTOR_MODE (mode)
4317 && !SPE_VECTOR_MODE (mode)
4318 /* Restrict addressing for DI because of our SUBREG hackery. */
4319 && !(TARGET_E500_DOUBLE
4320 && (mode == DFmode || mode == DDmode || mode == DImode))
4322 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
4323 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
4324 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
4325 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4327 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
4332 /* Go to LABEL if ADDR (a legitimate address expression)
4333 has an effect that depends on the machine mode it is used for.
4335 On the RS/6000 this is true of all integral offsets (since AltiVec
4336 modes don't allow them) or is a pre-increment or decrement.
4338 ??? Except that due to conceptual problems in offsettable_address_p
4339 we can't really report the problems of integral offsets. So leave
4340 this assuming that the adjustable offset must be valid for the
4341 sub-words of a TFmode operand, which is what we had before. */
4344 rs6000_mode_dependent_address (rtx addr)
4346 switch (GET_CODE (addr))
4349 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4351 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4352 return val + 12 + 0x8000 >= 0x10000;
4359 /* Auto-increment cases are now treated generically in recog.c. */
4361 return TARGET_UPDATE;
4370 /* More elaborate version of recog's offsettable_memref_p predicate
4371 that works around the ??? note of rs6000_mode_dependent_address.
4372 In particular it accepts
4374 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4376 in 32-bit mode, that the recog predicate rejects. */
4379 rs6000_offsettable_memref_p (rtx op)
4384 /* First mimic offsettable_memref_p. */
4385 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4388 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4389 the latter predicate knows nothing about the mode of the memory
4390 reference and, therefore, assumes that it is the largest supported
4391 mode (TFmode). As a consequence, legitimate offsettable memory
4392 references are rejected. rs6000_legitimate_offset_address_p contains
4393 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4394 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4397 /* Return number of consecutive hard regs needed starting at reg REGNO
4398 to hold something of mode MODE.
4399 This is ordinarily the length in words of a value of mode MODE
4400 but can be less for certain modes in special long registers.
4402 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4403 scalar instructions. The upper 32 bits are only available to the
4406 POWER and PowerPC GPRs hold 32 bits worth;
4407 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4410 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4412 if (FP_REGNO_P (regno))
4413 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4415 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4416 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4418 if (ALTIVEC_REGNO_P (regno))
4420 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4422 /* The value returned for SCmode in the E500 double case is 2 for
4423 ABI compatibility; storing an SCmode value in a single register
4424 would require function_arg and rs6000_spe_function_arg to handle
4425 SCmode so as to pass the value correctly in a pair of
4427 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
4428 && !DECIMAL_FLOAT_MODE_P (mode))
4429 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4431 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4434 /* Change register usage conditional on target flags. */
4436 rs6000_conditional_register_usage (void)
4440 /* Set MQ register fixed (already call_used) if not POWER
4441 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4446 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4448 fixed_regs[13] = call_used_regs[13]
4449 = call_really_used_regs[13] = 1;
4451 /* Conditionally disable FPRs. */
4452 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4453 for (i = 32; i < 64; i++)
4454 fixed_regs[i] = call_used_regs[i]
4455 = call_really_used_regs[i] = 1;
4457 /* The TOC register is not killed across calls in a way that is
4458 visible to the compiler. */
4459 if (DEFAULT_ABI == ABI_AIX)
4460 call_really_used_regs[2] = 0;
4462 if (DEFAULT_ABI == ABI_V4
4463 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4465 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4467 if (DEFAULT_ABI == ABI_V4
4468 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4470 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4471 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4472 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4474 if (DEFAULT_ABI == ABI_DARWIN
4475 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4476 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4477 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4478 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4480 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4481 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4482 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4486 global_regs[SPEFSCR_REGNO] = 1;
4487 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4488 registers in prologues and epilogues. We no longer use r14
4489 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4490 pool for link-compatibility with older versions of GCC. Once
4491 "old" code has died out, we can return r14 to the allocation
4494 = call_used_regs[14]
4495 = call_really_used_regs[14] = 1;
4498 if (!TARGET_ALTIVEC)
4500 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4501 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4502 call_really_used_regs[VRSAVE_REGNO] = 1;
4506 global_regs[VSCR_REGNO] = 1;
4508 if (TARGET_ALTIVEC_ABI)
4510 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4511 call_used_regs[i] = call_really_used_regs[i] = 1;
4513 /* AIX reserves VR20:31 in non-extended ABI mode. */
4515 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
4516 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4520 /* Try to output insns to set TARGET equal to the constant C if it can
4521 be done in less than N insns. Do all computations in MODE.
4522 Returns the place where the output has been placed if it can be
4523 done and the insns have been emitted. If it would take more than N
4524 insns, zero is returned and no insns and emitted. */
4527 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4528 rtx source, int n ATTRIBUTE_UNUSED)
4530 rtx result, insn, set;
4531 HOST_WIDE_INT c0, c1;
4538 dest = gen_reg_rtx (mode);
4539 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4543 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4545 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4546 GEN_INT (INTVAL (source)
4547 & (~ (HOST_WIDE_INT) 0xffff))));
4548 emit_insn (gen_rtx_SET (VOIDmode, dest,
4549 gen_rtx_IOR (SImode, copy_rtx (result),
4550 GEN_INT (INTVAL (source) & 0xffff))));
4555 switch (GET_CODE (source))
4558 c0 = INTVAL (source);
4563 #if HOST_BITS_PER_WIDE_INT >= 64
4564 c0 = CONST_DOUBLE_LOW (source);
4567 c0 = CONST_DOUBLE_LOW (source);
4568 c1 = CONST_DOUBLE_HIGH (source);
4576 result = rs6000_emit_set_long_const (dest, c0, c1);
4583 insn = get_last_insn ();
4584 set = single_set (insn);
4585 if (! CONSTANT_P (SET_SRC (set)))
4586 set_unique_reg_note (insn, REG_EQUAL, source);
4591 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4592 fall back to a straight forward decomposition. We do this to avoid
4593 exponential run times encountered when looking for longer sequences
4594 with rs6000_emit_set_const. */
4596 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4598 if (!TARGET_POWERPC64)
4600 rtx operand1, operand2;
4602 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4604 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4606 emit_move_insn (operand1, GEN_INT (c1));
4607 emit_move_insn (operand2, GEN_INT (c2));
4611 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4614 ud2 = (c1 & 0xffff0000) >> 16;
4615 #if HOST_BITS_PER_WIDE_INT >= 64
4619 ud4 = (c2 & 0xffff0000) >> 16;
4621 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4622 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4625 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4627 emit_move_insn (dest, GEN_INT (ud1));
4630 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4631 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4634 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4637 emit_move_insn (dest, GEN_INT (ud2 << 16));
4639 emit_move_insn (copy_rtx (dest),
4640 gen_rtx_IOR (DImode, copy_rtx (dest),
4643 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4644 || (ud4 == 0 && ! (ud3 & 0x8000)))
4647 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4650 emit_move_insn (dest, GEN_INT (ud3 << 16));
4653 emit_move_insn (copy_rtx (dest),
4654 gen_rtx_IOR (DImode, copy_rtx (dest),
4656 emit_move_insn (copy_rtx (dest),
4657 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4660 emit_move_insn (copy_rtx (dest),
4661 gen_rtx_IOR (DImode, copy_rtx (dest),
4667 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4670 emit_move_insn (dest, GEN_INT (ud4 << 16));
4673 emit_move_insn (copy_rtx (dest),
4674 gen_rtx_IOR (DImode, copy_rtx (dest),
4677 emit_move_insn (copy_rtx (dest),
4678 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4681 emit_move_insn (copy_rtx (dest),
4682 gen_rtx_IOR (DImode, copy_rtx (dest),
4683 GEN_INT (ud2 << 16)));
4685 emit_move_insn (copy_rtx (dest),
4686 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4692 /* Helper for the following. Get rid of [r+r] memory refs
4693 in cases where it won't work (TImode, TFmode, TDmode). */
4696 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4698 if (GET_CODE (operands[0]) == MEM
4699 && GET_CODE (XEXP (operands[0], 0)) != REG
4700 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4701 && ! reload_in_progress)
4703 = replace_equiv_address (operands[0],
4704 copy_addr_to_reg (XEXP (operands[0], 0)));
4706 if (GET_CODE (operands[1]) == MEM
4707 && GET_CODE (XEXP (operands[1], 0)) != REG
4708 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4709 && ! reload_in_progress)
4711 = replace_equiv_address (operands[1],
4712 copy_addr_to_reg (XEXP (operands[1], 0)));
4715 /* Emit a move from SOURCE to DEST in mode MODE. */
4717 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4721 operands[1] = source;
4723 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4724 if (GET_CODE (operands[1]) == CONST_DOUBLE
4725 && ! FLOAT_MODE_P (mode)
4726 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4728 /* FIXME. This should never happen. */
4729 /* Since it seems that it does, do the safe thing and convert
4731 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4733 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4734 || FLOAT_MODE_P (mode)
4735 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4736 || CONST_DOUBLE_LOW (operands[1]) < 0)
4737 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4738 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4740 /* Check if GCC is setting up a block move that will end up using FP
4741 registers as temporaries. We must make sure this is acceptable. */
4742 if (GET_CODE (operands[0]) == MEM
4743 && GET_CODE (operands[1]) == MEM
4745 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4746 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4747 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4748 ? 32 : MEM_ALIGN (operands[0])))
4749 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4751 : MEM_ALIGN (operands[1]))))
4752 && ! MEM_VOLATILE_P (operands [0])
4753 && ! MEM_VOLATILE_P (operands [1]))
4755 emit_move_insn (adjust_address (operands[0], SImode, 0),
4756 adjust_address (operands[1], SImode, 0));
4757 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4758 adjust_address (copy_rtx (operands[1]), SImode, 4));
4762 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4763 && !gpc_reg_operand (operands[1], mode))
4764 operands[1] = force_reg (mode, operands[1]);
4766 if (mode == SFmode && ! TARGET_POWERPC
4767 && TARGET_HARD_FLOAT && TARGET_FPRS
4768 && GET_CODE (operands[0]) == MEM)
4772 if (reload_in_progress || reload_completed)
4773 regnum = true_regnum (operands[1]);
4774 else if (GET_CODE (operands[1]) == REG)
4775 regnum = REGNO (operands[1]);
4779 /* If operands[1] is a register, on POWER it may have
4780 double-precision data in it, so truncate it to single
4782 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4785 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4786 : gen_reg_rtx (mode));
4787 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4788 operands[1] = newreg;
4792 /* Recognize the case where operand[1] is a reference to thread-local
4793 data and load its address to a register. */
4794 if (rs6000_tls_referenced_p (operands[1]))
4796 enum tls_model model;
4797 rtx tmp = operands[1];
4800 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4802 addend = XEXP (XEXP (tmp, 0), 1);
4803 tmp = XEXP (XEXP (tmp, 0), 0);
4806 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4807 model = SYMBOL_REF_TLS_MODEL (tmp);
4808 gcc_assert (model != 0);
4810 tmp = rs6000_legitimize_tls_address (tmp, model);
4813 tmp = gen_rtx_PLUS (mode, tmp, addend);
4814 tmp = force_operand (tmp, operands[0]);
4819 /* Handle the case where reload calls us with an invalid address. */
4820 if (reload_in_progress && mode == Pmode
4821 && (! general_operand (operands[1], mode)
4822 || ! nonimmediate_operand (operands[0], mode)))
4825 /* 128-bit constant floating-point values on Darwin should really be
4826 loaded as two parts. */
4827 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4828 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4830 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4831 know how to get a DFmode SUBREG of a TFmode. */
4832 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4833 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4834 simplify_gen_subreg (imode, operands[1], mode, 0),
4836 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4837 GET_MODE_SIZE (imode)),
4838 simplify_gen_subreg (imode, operands[1], mode,
4839 GET_MODE_SIZE (imode)),
4844 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
4845 cfun->machine->sdmode_stack_slot =
4846 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
4848 if (reload_in_progress
4850 && MEM_P (operands[0])
4851 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
4852 && REG_P (operands[1]))
4854 if (FP_REGNO_P (REGNO (operands[1])))
4856 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
4857 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4858 emit_insn (gen_movsd_store (mem, operands[1]));
4860 else if (INT_REGNO_P (REGNO (operands[1])))
4862 rtx mem = adjust_address_nv (operands[0], mode, 4);
4863 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4864 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
4870 if (reload_in_progress
4872 && REG_P (operands[0])
4873 && MEM_P (operands[1])
4874 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
4876 if (FP_REGNO_P (REGNO (operands[0])))
4878 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
4879 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4880 emit_insn (gen_movsd_load (operands[0], mem));
4882 else if (INT_REGNO_P (REGNO (operands[0])))
4884 rtx mem = adjust_address_nv (operands[1], mode, 4);
4885 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4886 emit_insn (gen_movsd_hardfloat (operands[0], mem));
4893 /* FIXME: In the long term, this switch statement should go away
4894 and be replaced by a sequence of tests based on things like
4900 if (CONSTANT_P (operands[1])
4901 && GET_CODE (operands[1]) != CONST_INT)
4902 operands[1] = force_const_mem (mode, operands[1]);
4907 rs6000_eliminate_indexed_memrefs (operands);
4914 if (CONSTANT_P (operands[1])
4915 && ! easy_fp_constant (operands[1], mode))
4916 operands[1] = force_const_mem (mode, operands[1]);
4927 if (CONSTANT_P (operands[1])
4928 && !easy_vector_constant (operands[1], mode))
4929 operands[1] = force_const_mem (mode, operands[1]);
4934 /* Use default pattern for address of ELF small data */
4937 && DEFAULT_ABI == ABI_V4
4938 && (GET_CODE (operands[1]) == SYMBOL_REF
4939 || GET_CODE (operands[1]) == CONST)
4940 && small_data_operand (operands[1], mode))
4942 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4946 if (DEFAULT_ABI == ABI_V4
4947 && mode == Pmode && mode == SImode
4948 && flag_pic == 1 && got_operand (operands[1], mode))
4950 emit_insn (gen_movsi_got (operands[0], operands[1]));
4954 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4958 && CONSTANT_P (operands[1])
4959 && GET_CODE (operands[1]) != HIGH
4960 && GET_CODE (operands[1]) != CONST_INT)
4962 rtx target = (!can_create_pseudo_p ()
4964 : gen_reg_rtx (mode));
4966 /* If this is a function address on -mcall-aixdesc,
4967 convert it to the address of the descriptor. */
4968 if (DEFAULT_ABI == ABI_AIX
4969 && GET_CODE (operands[1]) == SYMBOL_REF
4970 && XSTR (operands[1], 0)[0] == '.')
4972 const char *name = XSTR (operands[1], 0);
4974 while (*name == '.')
4976 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4977 CONSTANT_POOL_ADDRESS_P (new_ref)
4978 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4979 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4980 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4981 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4982 operands[1] = new_ref;
4985 if (DEFAULT_ABI == ABI_DARWIN)
4988 if (MACHO_DYNAMIC_NO_PIC_P)
4990 /* Take care of any required data indirection. */
4991 operands[1] = rs6000_machopic_legitimize_pic_address (
4992 operands[1], mode, operands[0]);
4993 if (operands[0] != operands[1])
4994 emit_insn (gen_rtx_SET (VOIDmode,
4995 operands[0], operands[1]));
4999 emit_insn (gen_macho_high (target, operands[1]));
5000 emit_insn (gen_macho_low (operands[0], target, operands[1]));
5004 emit_insn (gen_elf_high (target, operands[1]));
5005 emit_insn (gen_elf_low (operands[0], target, operands[1]));
5009 /* If this is a SYMBOL_REF that refers to a constant pool entry,
5010 and we have put it in the TOC, we just need to make a TOC-relative
5013 && GET_CODE (operands[1]) == SYMBOL_REF
5014 && constant_pool_expr_p (operands[1])
5015 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
5016 get_pool_mode (operands[1])))
5018 operands[1] = create_TOC_reference (operands[1]);
5020 else if (mode == Pmode
5021 && CONSTANT_P (operands[1])
5022 && ((GET_CODE (operands[1]) != CONST_INT
5023 && ! easy_fp_constant (operands[1], mode))
5024 || (GET_CODE (operands[1]) == CONST_INT
5025 && num_insns_constant (operands[1], mode) > 2)
5026 || (GET_CODE (operands[0]) == REG
5027 && FP_REGNO_P (REGNO (operands[0]))))
5028 && GET_CODE (operands[1]) != HIGH
5029 && ! legitimate_constant_pool_address_p (operands[1])
5030 && ! toc_relative_expr_p (operands[1]))
5032 /* Emit a USE operation so that the constant isn't deleted if
5033 expensive optimizations are turned on because nobody
5034 references it. This should only be done for operands that
5035 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5036 This should not be done for operands that contain LABEL_REFs.
5037 For now, we just handle the obvious case. */
5038 if (GET_CODE (operands[1]) != LABEL_REF)
5039 emit_use (operands[1]);
5042 /* Darwin uses a special PIC legitimizer. */
5043 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
5046 rs6000_machopic_legitimize_pic_address (operands[1], mode,
5048 if (operands[0] != operands[1])
5049 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5054 /* If we are to limit the number of things we put in the TOC and
5055 this is a symbol plus a constant we can add in one insn,
5056 just put the symbol in the TOC and add the constant. Don't do
5057 this if reload is in progress. */
5058 if (GET_CODE (operands[1]) == CONST
5059 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5060 && GET_CODE (XEXP (operands[1], 0)) == PLUS
5061 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
5062 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
5063 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
5064 && ! side_effects_p (operands[0]))
5067 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
5068 rtx other = XEXP (XEXP (operands[1], 0), 1);
5070 sym = force_reg (mode, sym);
5072 emit_insn (gen_addsi3 (operands[0], sym, other));
5074 emit_insn (gen_adddi3 (operands[0], sym, other));
5078 operands[1] = force_const_mem (mode, operands[1]);
5081 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
5082 && constant_pool_expr_p (XEXP (operands[1], 0))
5083 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
5084 get_pool_constant (XEXP (operands[1], 0)),
5085 get_pool_mode (XEXP (operands[1], 0))))
5088 = gen_const_mem (mode,
5089 create_TOC_reference (XEXP (operands[1], 0)));
5090 set_mem_alias_set (operands[1], get_TOC_alias_set ());
5096 rs6000_eliminate_indexed_memrefs (operands);
5100 emit_insn (gen_rtx_PARALLEL (VOIDmode,
5102 gen_rtx_SET (VOIDmode,
5103 operands[0], operands[1]),
5104 gen_rtx_CLOBBER (VOIDmode,
5105 gen_rtx_SCRATCH (SImode)))));
5114 /* Above, we may have called force_const_mem which may have returned
5115 an invalid address. If we can, fix this up; otherwise, reload will
5116 have to deal with it. */
5117 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
5118 operands[1] = validize_mem (operands[1]);
5121 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5124 /* Nonzero if we can use a floating-point register to pass this arg. */
5125 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5126 (SCALAR_FLOAT_MODE_P (MODE) \
5127 && (CUM)->fregno <= FP_ARG_MAX_REG \
5128 && TARGET_HARD_FLOAT && TARGET_FPRS)
5130 /* Nonzero if we can use an AltiVec register to pass this arg. */
5131 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5132 (ALTIVEC_VECTOR_MODE (MODE) \
5133 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5134 && TARGET_ALTIVEC_ABI \
5137 /* Return a nonzero value to say to return the function value in
5138 memory, just as large structures are always returned. TYPE will be
5139 the data type of the value, and FNTYPE will be the type of the
5140 function doing the returning, or @code{NULL} for libcalls.
5142 The AIX ABI for the RS/6000 specifies that all structures are
5143 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5144 specifies that structures <= 8 bytes are returned in r3/r4, but a
5145 draft put them in memory, and GCC used to implement the draft
5146 instead of the final standard. Therefore, aix_struct_return
5147 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5148 compatibility can change DRAFT_V4_STRUCT_RET to override the
5149 default, and -m switches get the final word. See
5150 rs6000_override_options for more details.
5152 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5153 long double support is enabled. These values are returned in memory.
5155 int_size_in_bytes returns -1 for variable size objects, which go in
5156 memory always. The cast to unsigned makes -1 > 8. */
5159 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5161 /* In the darwin64 abi, try to use registers for larger structs
5163 if (rs6000_darwin64_abi
5164 && TREE_CODE (type) == RECORD_TYPE
5165 && int_size_in_bytes (type) > 0)
5167 CUMULATIVE_ARGS valcum;
5171 valcum.fregno = FP_ARG_MIN_REG;
5172 valcum.vregno = ALTIVEC_ARG_MIN_REG;
5173 /* Do a trial code generation as if this were going to be passed
5174 as an argument; if any part goes in memory, we return NULL. */
5175 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
5178 /* Otherwise fall through to more conventional ABI rules. */
5181 if (AGGREGATE_TYPE_P (type)
5182 && (aix_struct_return
5183 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
5186 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5187 modes only exist for GCC vector types if -maltivec. */
5188 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
5189 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5192 /* Return synthetic vectors in memory. */
5193 if (TREE_CODE (type) == VECTOR_TYPE
5194 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5196 static bool warned_for_return_big_vectors = false;
5197 if (!warned_for_return_big_vectors)
5199 warning (0, "GCC vector returned by reference: "
5200 "non-standard ABI extension with no compatibility guarantee");
5201 warned_for_return_big_vectors = true;
5206 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
5212 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5213 for a call to a function whose data type is FNTYPE.
5214 For a library call, FNTYPE is 0.
5216 For incoming args we set the number of arguments in the prototype large
5217 so we never return a PARALLEL. */
5220 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
5221 rtx libname ATTRIBUTE_UNUSED, int incoming,
5222 int libcall, int n_named_args)
5224 static CUMULATIVE_ARGS zero_cumulative;
5226 *cum = zero_cumulative;
5228 cum->fregno = FP_ARG_MIN_REG;
5229 cum->vregno = ALTIVEC_ARG_MIN_REG;
5230 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
5231 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
5232 ? CALL_LIBCALL : CALL_NORMAL);
5233 cum->sysv_gregno = GP_ARG_MIN_REG;
5234 cum->stdarg = fntype
5235 && (TYPE_ARG_TYPES (fntype) != 0
5236 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5237 != void_type_node));
5239 cum->nargs_prototype = 0;
5240 if (incoming || cum->prototype)
5241 cum->nargs_prototype = n_named_args;
5243 /* Check for a longcall attribute. */
5244 if ((!fntype && rs6000_default_long_calls)
5246 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
5247 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
5248 cum->call_cookie |= CALL_LONG;
5250 if (TARGET_DEBUG_ARG)
5252 fprintf (stderr, "\ninit_cumulative_args:");
5255 tree ret_type = TREE_TYPE (fntype);
5256 fprintf (stderr, " ret code = %s,",
5257 tree_code_name[ (int)TREE_CODE (ret_type) ]);
5260 if (cum->call_cookie & CALL_LONG)
5261 fprintf (stderr, " longcall,");
5263 fprintf (stderr, " proto = %d, nargs = %d\n",
5264 cum->prototype, cum->nargs_prototype);
5269 && TARGET_ALTIVEC_ABI
5270 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
5272 error ("cannot return value in vector register because"
5273 " altivec instructions are disabled, use -maltivec"
5278 /* Return true if TYPE must be passed on the stack and not in registers. */
5281 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
5283 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
5284 return must_pass_in_stack_var_size (mode, type);
5286 return must_pass_in_stack_var_size_or_pad (mode, type);
5289 /* If defined, a C expression which determines whether, and in which
5290 direction, to pad out an argument with extra space. The value
5291 should be of type `enum direction': either `upward' to pad above
5292 the argument, `downward' to pad below, or `none' to inhibit
5295 For the AIX ABI structs are always stored left shifted in their
5299 function_arg_padding (enum machine_mode mode, const_tree type)
5301 #ifndef AGGREGATE_PADDING_FIXED
5302 #define AGGREGATE_PADDING_FIXED 0
5304 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5305 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5308 if (!AGGREGATE_PADDING_FIXED)
5310 /* GCC used to pass structures of the same size as integer types as
5311 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5312 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5313 passed padded downward, except that -mstrict-align further
5314 muddied the water in that multi-component structures of 2 and 4
5315 bytes in size were passed padded upward.
5317 The following arranges for best compatibility with previous
5318 versions of gcc, but removes the -mstrict-align dependency. */
5319 if (BYTES_BIG_ENDIAN)
5321 HOST_WIDE_INT size = 0;
5323 if (mode == BLKmode)
5325 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5326 size = int_size_in_bytes (type);
5329 size = GET_MODE_SIZE (mode);
5331 if (size == 1 || size == 2 || size == 4)
5337 if (AGGREGATES_PAD_UPWARD_ALWAYS)
5339 if (type != 0 && AGGREGATE_TYPE_P (type))
5343 /* Fall back to the default. */
5344 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5347 /* If defined, a C expression that gives the alignment boundary, in bits,
5348 of an argument with the specified mode and type. If it is not defined,
5349 PARM_BOUNDARY is used for all arguments.
5351 V.4 wants long longs and doubles to be double word aligned. Just
5352 testing the mode size is a boneheaded way to do this as it means
5353 that other types such as complex int are also double word aligned.
5354 However, we're stuck with this because changing the ABI might break
5355 existing library interfaces.
5357 Doubleword align SPE vectors.
5358 Quadword align Altivec vectors.
5359 Quadword align large synthetic vector types. */
5362 function_arg_boundary (enum machine_mode mode, tree type)
5364 if (DEFAULT_ABI == ABI_V4
5365 && (GET_MODE_SIZE (mode) == 8
5366 || (TARGET_HARD_FLOAT
5368 && (mode == TFmode || mode == TDmode))))
5370 else if (SPE_VECTOR_MODE (mode)
5371 || (type && TREE_CODE (type) == VECTOR_TYPE
5372 && int_size_in_bytes (type) >= 8
5373 && int_size_in_bytes (type) < 16))
5375 else if (ALTIVEC_VECTOR_MODE (mode)
5376 || (type && TREE_CODE (type) == VECTOR_TYPE
5377 && int_size_in_bytes (type) >= 16))
5379 else if (rs6000_darwin64_abi && mode == BLKmode
5380 && type && TYPE_ALIGN (type) > 64)
5383 return PARM_BOUNDARY;
5386 /* For a function parm of MODE and TYPE, return the starting word in
5387 the parameter area. NWORDS of the parameter area are already used. */
5390 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
5393 unsigned int parm_offset;
5395 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5396 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5397 return nwords + (-(parm_offset + nwords) & align);
5400 /* Compute the size (in words) of a function argument. */
5402 static unsigned long
5403 rs6000_arg_size (enum machine_mode mode, tree type)
5407 if (mode != BLKmode)
5408 size = GET_MODE_SIZE (mode);
5410 size = int_size_in_bytes (type);
5413 return (size + 3) >> 2;
5415 return (size + 7) >> 3;
5418 /* Use this to flush pending int fields. */
5421 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5422 HOST_WIDE_INT bitpos)
5424 unsigned int startbit, endbit;
5425 int intregs, intoffset;
5426 enum machine_mode mode;
5428 if (cum->intoffset == -1)
5431 intoffset = cum->intoffset;
5432 cum->intoffset = -1;
5434 if (intoffset % BITS_PER_WORD != 0)
5436 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5438 if (mode == BLKmode)
5440 /* We couldn't find an appropriate mode, which happens,
5441 e.g., in packed structs when there are 3 bytes to load.
5442 Back intoffset back to the beginning of the word in this
5444 intoffset = intoffset & -BITS_PER_WORD;
5448 startbit = intoffset & -BITS_PER_WORD;
5449 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5450 intregs = (endbit - startbit) / BITS_PER_WORD;
5451 cum->words += intregs;
5454 /* The darwin64 ABI calls for us to recurse down through structs,
5455 looking for elements passed in registers. Unfortunately, we have
5456 to track int register count here also because of misalignments
5457 in powerpc alignment mode. */
5460 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5462 HOST_WIDE_INT startbitpos)
5466 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5467 if (TREE_CODE (f) == FIELD_DECL)
5469 HOST_WIDE_INT bitpos = startbitpos;
5470 tree ftype = TREE_TYPE (f);
5471 enum machine_mode mode;
5472 if (ftype == error_mark_node)
5474 mode = TYPE_MODE (ftype);
5476 if (DECL_SIZE (f) != 0
5477 && host_integerp (bit_position (f), 1))
5478 bitpos += int_bit_position (f);
5480 /* ??? FIXME: else assume zero offset. */
5482 if (TREE_CODE (ftype) == RECORD_TYPE)
5483 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5484 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5486 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5487 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5488 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5490 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5492 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5496 else if (cum->intoffset == -1)
5497 cum->intoffset = bitpos;
5501 /* Update the data in CUM to advance over an argument
5502 of mode MODE and data type TYPE.
5503 (TYPE is null for libcalls where that information may not be available.)
5505 Note that for args passed by reference, function_arg will be called
5506 with MODE and TYPE set to that of the pointer to the arg, not the arg
5510 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5511 tree type, int named, int depth)
5515 /* Only tick off an argument if we're not recursing. */
5517 cum->nargs_prototype--;
5519 if (TARGET_ALTIVEC_ABI
5520 && (ALTIVEC_VECTOR_MODE (mode)
5521 || (type && TREE_CODE (type) == VECTOR_TYPE
5522 && int_size_in_bytes (type) == 16)))
5526 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5529 if (!TARGET_ALTIVEC)
5530 error ("cannot pass argument in vector register because"
5531 " altivec instructions are disabled, use -maltivec"
5534 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5535 even if it is going to be passed in a vector register.
5536 Darwin does the same for variable-argument functions. */
5537 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5538 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5548 /* Vector parameters must be 16-byte aligned. This places
5549 them at 2 mod 4 in terms of words in 32-bit mode, since
5550 the parameter save area starts at offset 24 from the
5551 stack. In 64-bit mode, they just have to start on an
5552 even word, since the parameter save area is 16-byte
5553 aligned. Space for GPRs is reserved even if the argument
5554 will be passed in memory. */
5556 align = (2 - cum->words) & 3;
5558 align = cum->words & 1;
5559 cum->words += align + rs6000_arg_size (mode, type);
5561 if (TARGET_DEBUG_ARG)
5563 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5565 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5566 cum->nargs_prototype, cum->prototype,
5567 GET_MODE_NAME (mode));
5571 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5573 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5576 else if (rs6000_darwin64_abi
5578 && TREE_CODE (type) == RECORD_TYPE
5579 && (size = int_size_in_bytes (type)) > 0)
5581 /* Variable sized types have size == -1 and are
5582 treated as if consisting entirely of ints.
5583 Pad to 16 byte boundary if needed. */
5584 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5585 && (cum->words % 2) != 0)
5587 /* For varargs, we can just go up by the size of the struct. */
5589 cum->words += (size + 7) / 8;
5592 /* It is tempting to say int register count just goes up by
5593 sizeof(type)/8, but this is wrong in a case such as
5594 { int; double; int; } [powerpc alignment]. We have to
5595 grovel through the fields for these too. */
5597 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5598 rs6000_darwin64_record_arg_advance_flush (cum,
5599 size * BITS_PER_UNIT);
5602 else if (DEFAULT_ABI == ABI_V4)
5604 if (TARGET_HARD_FLOAT && TARGET_FPRS
5605 && (mode == SFmode || mode == DFmode
5606 || mode == SDmode || mode == DDmode || mode == TDmode
5607 || (mode == TFmode && !TARGET_IEEEQUAD)))
5609 /* _Decimal128 must use an even/odd register pair. This assumes
5610 that the register number is odd when fregno is odd. */
5611 if (mode == TDmode && (cum->fregno % 2) == 1)
5614 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5615 <= FP_ARG_V4_MAX_REG)
5616 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5619 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5620 if (mode == DFmode || mode == TFmode
5621 || mode == DDmode || mode == TDmode)
5622 cum->words += cum->words & 1;
5623 cum->words += rs6000_arg_size (mode, type);
5628 int n_words = rs6000_arg_size (mode, type);
5629 int gregno = cum->sysv_gregno;
5631 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5632 (r7,r8) or (r9,r10). As does any other 2 word item such
5633 as complex int due to a historical mistake. */
5635 gregno += (1 - gregno) & 1;
5637 /* Multi-reg args are not split between registers and stack. */
5638 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5640 /* Long long and SPE vectors are aligned on the stack.
5641 So are other 2 word items such as complex int due to
5642 a historical mistake. */
5644 cum->words += cum->words & 1;
5645 cum->words += n_words;
5648 /* Note: continuing to accumulate gregno past when we've started
5649 spilling to the stack indicates the fact that we've started
5650 spilling to the stack to expand_builtin_saveregs. */
5651 cum->sysv_gregno = gregno + n_words;
5654 if (TARGET_DEBUG_ARG)
5656 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5657 cum->words, cum->fregno);
5658 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5659 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5660 fprintf (stderr, "mode = %4s, named = %d\n",
5661 GET_MODE_NAME (mode), named);
5666 int n_words = rs6000_arg_size (mode, type);
5667 int start_words = cum->words;
5668 int align_words = rs6000_parm_start (mode, type, start_words);
5670 cum->words = align_words + n_words;
5672 if (SCALAR_FLOAT_MODE_P (mode)
5673 && TARGET_HARD_FLOAT && TARGET_FPRS)
5675 /* _Decimal128 must be passed in an even/odd float register pair.
5676 This assumes that the register number is odd when fregno is
5678 if (mode == TDmode && (cum->fregno % 2) == 1)
5680 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5683 if (TARGET_DEBUG_ARG)
5685 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5686 cum->words, cum->fregno);
5687 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5688 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5689 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5690 named, align_words - start_words, depth);
5696 spe_build_register_parallel (enum machine_mode mode, int gregno)
5703 r1 = gen_rtx_REG (DImode, gregno);
5704 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5705 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5709 r1 = gen_rtx_REG (DImode, gregno);
5710 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5711 r3 = gen_rtx_REG (DImode, gregno + 2);
5712 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5713 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5716 r1 = gen_rtx_REG (DImode, gregno);
5717 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5718 r3 = gen_rtx_REG (DImode, gregno + 2);
5719 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5720 r5 = gen_rtx_REG (DImode, gregno + 4);
5721 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5722 r7 = gen_rtx_REG (DImode, gregno + 6);
5723 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5724 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5731 /* Determine where to put a SIMD argument on the SPE. */
5733 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5736 int gregno = cum->sysv_gregno;
5738 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5739 are passed and returned in a pair of GPRs for ABI compatibility. */
5740 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5741 || mode == DCmode || mode == TCmode))
5743 int n_words = rs6000_arg_size (mode, type);
5745 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5747 gregno += (1 - gregno) & 1;
5749 /* Multi-reg args are not split between registers and stack. */
5750 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5753 return spe_build_register_parallel (mode, gregno);
5757 int n_words = rs6000_arg_size (mode, type);
5759 /* SPE vectors are put in odd registers. */
5760 if (n_words == 2 && (gregno & 1) == 0)
5763 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5766 enum machine_mode m = SImode;
5768 r1 = gen_rtx_REG (m, gregno);
5769 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5770 r2 = gen_rtx_REG (m, gregno + 1);
5771 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5772 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5779 if (gregno <= GP_ARG_MAX_REG)
5780 return gen_rtx_REG (mode, gregno);
5786 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5787 structure between cum->intoffset and bitpos to integer registers. */
5790 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5791 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5793 enum machine_mode mode;
5795 unsigned int startbit, endbit;
5796 int this_regno, intregs, intoffset;
5799 if (cum->intoffset == -1)
5802 intoffset = cum->intoffset;
5803 cum->intoffset = -1;
5805 /* If this is the trailing part of a word, try to only load that
5806 much into the register. Otherwise load the whole register. Note
5807 that in the latter case we may pick up unwanted bits. It's not a
5808 problem at the moment but may wish to revisit. */
5810 if (intoffset % BITS_PER_WORD != 0)
5812 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5814 if (mode == BLKmode)
5816 /* We couldn't find an appropriate mode, which happens,
5817 e.g., in packed structs when there are 3 bytes to load.
5818 Back intoffset back to the beginning of the word in this
5820 intoffset = intoffset & -BITS_PER_WORD;
5827 startbit = intoffset & -BITS_PER_WORD;
5828 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5829 intregs = (endbit - startbit) / BITS_PER_WORD;
5830 this_regno = cum->words + intoffset / BITS_PER_WORD;
5832 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5835 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5839 intoffset /= BITS_PER_UNIT;
5842 regno = GP_ARG_MIN_REG + this_regno;
5843 reg = gen_rtx_REG (mode, regno);
5845 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5848 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5852 while (intregs > 0);
5855 /* Recursive workhorse for the following. */
5858 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
5859 HOST_WIDE_INT startbitpos, rtx rvec[],
5864 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5865 if (TREE_CODE (f) == FIELD_DECL)
5867 HOST_WIDE_INT bitpos = startbitpos;
5868 tree ftype = TREE_TYPE (f);
5869 enum machine_mode mode;
5870 if (ftype == error_mark_node)
5872 mode = TYPE_MODE (ftype);
5874 if (DECL_SIZE (f) != 0
5875 && host_integerp (bit_position (f), 1))
5876 bitpos += int_bit_position (f);
5878 /* ??? FIXME: else assume zero offset. */
5880 if (TREE_CODE (ftype) == RECORD_TYPE)
5881 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5882 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5887 case SCmode: mode = SFmode; break;
5888 case DCmode: mode = DFmode; break;
5889 case TCmode: mode = TFmode; break;
5893 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5895 = gen_rtx_EXPR_LIST (VOIDmode,
5896 gen_rtx_REG (mode, cum->fregno++),
5897 GEN_INT (bitpos / BITS_PER_UNIT));
5898 if (mode == TFmode || mode == TDmode)
5901 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5903 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5905 = gen_rtx_EXPR_LIST (VOIDmode,
5906 gen_rtx_REG (mode, cum->vregno++),
5907 GEN_INT (bitpos / BITS_PER_UNIT));
5909 else if (cum->intoffset == -1)
5910 cum->intoffset = bitpos;
5914 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5915 the register(s) to be used for each field and subfield of a struct
5916 being passed by value, along with the offset of where the
5917 register's value may be found in the block. FP fields go in FP
5918 register, vector fields go in vector registers, and everything
5919 else goes in int registers, packed as in memory.
5921 This code is also used for function return values. RETVAL indicates
5922 whether this is the case.
5924 Much of this is taken from the SPARC V9 port, which has a similar
5925 calling convention. */
5928 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
5929 int named, bool retval)
5931 rtx rvec[FIRST_PSEUDO_REGISTER];
5932 int k = 1, kbase = 1;
5933 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5934 /* This is a copy; modifications are not visible to our caller. */
5935 CUMULATIVE_ARGS copy_cum = *orig_cum;
5936 CUMULATIVE_ARGS *cum = ©_cum;
5938 /* Pad to 16 byte boundary if needed. */
5939 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5940 && (cum->words % 2) != 0)
5947 /* Put entries into rvec[] for individual FP and vector fields, and
5948 for the chunks of memory that go in int regs. Note we start at
5949 element 1; 0 is reserved for an indication of using memory, and
5950 may or may not be filled in below. */
5951 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5952 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5954 /* If any part of the struct went on the stack put all of it there.
5955 This hack is because the generic code for
5956 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5957 parts of the struct are not at the beginning. */
5961 return NULL_RTX; /* doesn't go in registers at all */
5963 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5965 if (k > 1 || cum->use_stack)
5966 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5971 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5974 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5978 rtx rvec[GP_ARG_NUM_REG + 1];
5980 if (align_words >= GP_ARG_NUM_REG)
5983 n_units = rs6000_arg_size (mode, type);
5985 /* Optimize the simple case where the arg fits in one gpr, except in
5986 the case of BLKmode due to assign_parms assuming that registers are
5987 BITS_PER_WORD wide. */
5989 || (n_units == 1 && mode != BLKmode))
5990 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5993 if (align_words + n_units > GP_ARG_NUM_REG)
5994 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5995 using a magic NULL_RTX component.
5996 This is not strictly correct. Only some of the arg belongs in
5997 memory, not all of it. However, the normal scheme using
5998 function_arg_partial_nregs can result in unusual subregs, eg.
5999 (subreg:SI (reg:DF) 4), which are not handled well. The code to
6000 store the whole arg to memory is often more efficient than code
6001 to store pieces, and we know that space is available in the right
6002 place for the whole arg. */
6003 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6008 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
6009 rtx off = GEN_INT (i++ * 4);
6010 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6012 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
6014 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6017 /* Determine where to put an argument to a function.
6018 Value is zero to push the argument on the stack,
6019 or a hard register in which to store the argument.
6021 MODE is the argument's machine mode.
6022 TYPE is the data type of the argument (as a tree).
6023 This is null for libcalls where that information may
6025 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6026 the preceding args and about the function being called. It is
6027 not modified in this routine.
6028 NAMED is nonzero if this argument is a named parameter
6029 (otherwise it is an extra parameter matching an ellipsis).
6031 On RS/6000 the first eight words of non-FP are normally in registers
6032 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
6033 Under V.4, the first 8 FP args are in registers.
6035 If this is floating-point and no prototype is specified, we use
6036 both an FP and integer register (or possibly FP reg and stack). Library
6037 functions (when CALL_LIBCALL is set) always have the proper types for args,
6038 so we can pass the FP value just in one register. emit_library_function
6039 doesn't support PARALLEL anyway.
6041 Note that for args passed by reference, function_arg will be called
6042 with MODE and TYPE set to that of the pointer to the arg, not the arg
6046 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6047 tree type, int named)
6049 enum rs6000_abi abi = DEFAULT_ABI;
6051 /* Return a marker to indicate whether CR1 needs to set or clear the
6052 bit that V.4 uses to say fp args were passed in registers.
6053 Assume that we don't need the marker for software floating point,
6054 or compiler generated library calls. */
6055 if (mode == VOIDmode)
6058 && (cum->call_cookie & CALL_LIBCALL) == 0
6060 || (cum->nargs_prototype < 0
6061 && (cum->prototype || TARGET_NO_PROTOTYPE))))
6063 /* For the SPE, we need to crxor CR6 always. */
6065 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
6066 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
6067 return GEN_INT (cum->call_cookie
6068 | ((cum->fregno == FP_ARG_MIN_REG)
6069 ? CALL_V4_SET_FP_ARGS
6070 : CALL_V4_CLEAR_FP_ARGS));
6073 return GEN_INT (cum->call_cookie);
6076 if (rs6000_darwin64_abi && mode == BLKmode
6077 && TREE_CODE (type) == RECORD_TYPE)
6079 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
6080 if (rslt != NULL_RTX)
6082 /* Else fall through to usual handling. */
6085 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
6086 if (TARGET_64BIT && ! cum->prototype)
6088 /* Vector parameters get passed in vector register
6089 and also in GPRs or memory, in absence of prototype. */
6092 align_words = (cum->words + 1) & ~1;
6094 if (align_words >= GP_ARG_NUM_REG)
6100 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6102 return gen_rtx_PARALLEL (mode,
6104 gen_rtx_EXPR_LIST (VOIDmode,
6106 gen_rtx_EXPR_LIST (VOIDmode,
6107 gen_rtx_REG (mode, cum->vregno),
6111 return gen_rtx_REG (mode, cum->vregno);
6112 else if (TARGET_ALTIVEC_ABI
6113 && (ALTIVEC_VECTOR_MODE (mode)
6114 || (type && TREE_CODE (type) == VECTOR_TYPE
6115 && int_size_in_bytes (type) == 16)))
6117 if (named || abi == ABI_V4)
6121 /* Vector parameters to varargs functions under AIX or Darwin
6122 get passed in memory and possibly also in GPRs. */
6123 int align, align_words, n_words;
6124 enum machine_mode part_mode;
6126 /* Vector parameters must be 16-byte aligned. This places them at
6127 2 mod 4 in terms of words in 32-bit mode, since the parameter
6128 save area starts at offset 24 from the stack. In 64-bit mode,
6129 they just have to start on an even word, since the parameter
6130 save area is 16-byte aligned. */
6132 align = (2 - cum->words) & 3;
6134 align = cum->words & 1;
6135 align_words = cum->words + align;
6137 /* Out of registers? Memory, then. */
6138 if (align_words >= GP_ARG_NUM_REG)
6141 if (TARGET_32BIT && TARGET_POWERPC64)
6142 return rs6000_mixed_function_arg (mode, type, align_words);
6144 /* The vector value goes in GPRs. Only the part of the
6145 value in GPRs is reported here. */
6147 n_words = rs6000_arg_size (mode, type);
6148 if (align_words + n_words > GP_ARG_NUM_REG)
6149 /* Fortunately, there are only two possibilities, the value
6150 is either wholly in GPRs or half in GPRs and half not. */
6153 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
6156 else if (TARGET_SPE_ABI && TARGET_SPE
6157 && (SPE_VECTOR_MODE (mode)
6158 || (TARGET_E500_DOUBLE && (mode == DFmode
6161 || mode == TCmode))))
6162 return rs6000_spe_function_arg (cum, mode, type);
6164 else if (abi == ABI_V4)
6166 if (TARGET_HARD_FLOAT && TARGET_FPRS
6167 && (mode == SFmode || mode == DFmode
6168 || (mode == TFmode && !TARGET_IEEEQUAD)
6169 || mode == SDmode || mode == DDmode || mode == TDmode))
6171 /* _Decimal128 must use an even/odd register pair. This assumes
6172 that the register number is odd when fregno is odd. */
6173 if (mode == TDmode && (cum->fregno % 2) == 1)
6176 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
6177 <= FP_ARG_V4_MAX_REG)
6178 return gen_rtx_REG (mode, cum->fregno);
6184 int n_words = rs6000_arg_size (mode, type);
6185 int gregno = cum->sysv_gregno;
6187 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6188 (r7,r8) or (r9,r10). As does any other 2 word item such
6189 as complex int due to a historical mistake. */
6191 gregno += (1 - gregno) & 1;
6193 /* Multi-reg args are not split between registers and stack. */
6194 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
6197 if (TARGET_32BIT && TARGET_POWERPC64)
6198 return rs6000_mixed_function_arg (mode, type,
6199 gregno - GP_ARG_MIN_REG);
6200 return gen_rtx_REG (mode, gregno);
6205 int align_words = rs6000_parm_start (mode, type, cum->words);
6207 /* _Decimal128 must be passed in an even/odd float register pair.
6208 This assumes that the register number is odd when fregno is odd. */
6209 if (mode == TDmode && (cum->fregno % 2) == 1)
6212 if (USE_FP_FOR_ARG_P (cum, mode, type))
6214 rtx rvec[GP_ARG_NUM_REG + 1];
6218 enum machine_mode fmode = mode;
6219 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
6221 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
6223 /* Currently, we only ever need one reg here because complex
6224 doubles are split. */
6225 gcc_assert (cum->fregno == FP_ARG_MAX_REG
6226 && (fmode == TFmode || fmode == TDmode));
6228 /* Long double or _Decimal128 split over regs and memory. */
6229 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
6232 /* Do we also need to pass this arg in the parameter save
6235 && (cum->nargs_prototype <= 0
6236 || (DEFAULT_ABI == ABI_AIX
6238 && align_words >= GP_ARG_NUM_REG)));
6240 if (!needs_psave && mode == fmode)
6241 return gen_rtx_REG (fmode, cum->fregno);
6246 /* Describe the part that goes in gprs or the stack.
6247 This piece must come first, before the fprs. */
6248 if (align_words < GP_ARG_NUM_REG)
6250 unsigned long n_words = rs6000_arg_size (mode, type);
6252 if (align_words + n_words > GP_ARG_NUM_REG
6253 || (TARGET_32BIT && TARGET_POWERPC64))
6255 /* If this is partially on the stack, then we only
6256 include the portion actually in registers here. */
6257 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
6260 if (align_words + n_words > GP_ARG_NUM_REG)
6261 /* Not all of the arg fits in gprs. Say that it
6262 goes in memory too, using a magic NULL_RTX
6263 component. Also see comment in
6264 rs6000_mixed_function_arg for why the normal
6265 function_arg_partial_nregs scheme doesn't work
6267 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
6271 r = gen_rtx_REG (rmode,
6272 GP_ARG_MIN_REG + align_words);
6273 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
6274 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6276 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
6280 /* The whole arg fits in gprs. */
6281 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6282 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6286 /* It's entirely in memory. */
6287 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6290 /* Describe where this piece goes in the fprs. */
6291 r = gen_rtx_REG (fmode, cum->fregno);
6292 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6294 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6296 else if (align_words < GP_ARG_NUM_REG)
6298 if (TARGET_32BIT && TARGET_POWERPC64)
6299 return rs6000_mixed_function_arg (mode, type, align_words);
6301 if (mode == BLKmode)
6304 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6311 /* For an arg passed partly in registers and partly in memory, this is
6312 the number of bytes passed in registers. For args passed entirely in
6313 registers or entirely in memory, zero. When an arg is described by a
6314 PARALLEL, perhaps using more than one register type, this function
6315 returns the number of bytes used by the first element of the PARALLEL. */
6318 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6319 tree type, bool named)
6324 if (DEFAULT_ABI == ABI_V4)
6327 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
6328 && cum->nargs_prototype >= 0)
6331 /* In this complicated case we just disable the partial_nregs code. */
6332 if (rs6000_darwin64_abi && mode == BLKmode
6333 && TREE_CODE (type) == RECORD_TYPE
6334 && int_size_in_bytes (type) > 0)
6337 align_words = rs6000_parm_start (mode, type, cum->words);
6339 if (USE_FP_FOR_ARG_P (cum, mode, type))
6341 /* If we are passing this arg in the fixed parameter save area
6342 (gprs or memory) as well as fprs, then this function should
6343 return the number of partial bytes passed in the parameter
6344 save area rather than partial bytes passed in fprs. */
6346 && (cum->nargs_prototype <= 0
6347 || (DEFAULT_ABI == ABI_AIX
6349 && align_words >= GP_ARG_NUM_REG)))
6351 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
6352 > FP_ARG_MAX_REG + 1)
6353 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
6354 else if (cum->nargs_prototype >= 0)
6358 if (align_words < GP_ARG_NUM_REG
6359 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
6360 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
6362 if (ret != 0 && TARGET_DEBUG_ARG)
6363 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
6368 /* A C expression that indicates when an argument must be passed by
6369 reference. If nonzero for an argument, a copy of that argument is
6370 made in memory and a pointer to the argument is passed instead of
6371 the argument itself. The pointer is passed in whatever way is
6372 appropriate for passing a pointer to that type.
6374 Under V.4, aggregates and long double are passed by reference.
6376 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6377 reference unless the AltiVec vector extension ABI is in force.
6379 As an extension to all ABIs, variable sized types are passed by
6383 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6384 enum machine_mode mode, const_tree type,
6385 bool named ATTRIBUTE_UNUSED)
6387 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
6389 if (TARGET_DEBUG_ARG)
6390 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6397 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6399 if (TARGET_DEBUG_ARG)
6400 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6404 if (int_size_in_bytes (type) < 0)
6406 if (TARGET_DEBUG_ARG)
6407 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6411 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6412 modes only exist for GCC vector types if -maltivec. */
6413 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6415 if (TARGET_DEBUG_ARG)
6416 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6420 /* Pass synthetic vectors in memory. */
6421 if (TREE_CODE (type) == VECTOR_TYPE
6422 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6424 static bool warned_for_pass_big_vectors = false;
6425 if (TARGET_DEBUG_ARG)
6426 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6427 if (!warned_for_pass_big_vectors)
6429 warning (0, "GCC vector passed by reference: "
6430 "non-standard ABI extension with no compatibility guarantee");
6431 warned_for_pass_big_vectors = true;
6440 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6443 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6448 for (i = 0; i < nregs; i++)
6450 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6451 if (reload_completed)
6453 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6456 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6457 i * GET_MODE_SIZE (reg_mode));
6460 tem = replace_equiv_address (tem, XEXP (tem, 0));
6464 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6468 /* Perform any needed actions needed for a function that is receiving a
6469 variable number of arguments.
6473 MODE and TYPE are the mode and type of the current parameter.
6475 PRETEND_SIZE is a variable that should be set to the amount of stack
6476 that must be pushed by the prolog to pretend that our caller pushed
6479 Normally, this macro will push all remaining incoming registers on the
6480 stack and set PRETEND_SIZE to the length of the registers pushed. */
6483 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6484 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6487 CUMULATIVE_ARGS next_cum;
6488 int reg_size = TARGET_32BIT ? 4 : 8;
6489 rtx save_area = NULL_RTX, mem;
6490 int first_reg_offset;
6493 /* Skip the last named argument. */
6495 function_arg_advance (&next_cum, mode, type, 1, 0);
6497 if (DEFAULT_ABI == ABI_V4)
6499 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6503 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6504 HOST_WIDE_INT offset = 0;
6506 /* Try to optimize the size of the varargs save area.
6507 The ABI requires that ap.reg_save_area is doubleword
6508 aligned, but we don't need to allocate space for all
6509 the bytes, only those to which we actually will save
6511 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6512 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6513 if (TARGET_HARD_FLOAT && TARGET_FPRS
6514 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6515 && cfun->va_list_fpr_size)
6518 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6519 * UNITS_PER_FP_WORD;
6520 if (cfun->va_list_fpr_size
6521 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6522 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6524 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6525 * UNITS_PER_FP_WORD;
6529 offset = -((first_reg_offset * reg_size) & ~7);
6530 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6532 gpr_reg_num = cfun->va_list_gpr_size;
6533 if (reg_size == 4 && (first_reg_offset & 1))
6536 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6539 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6541 - (int) (GP_ARG_NUM_REG * reg_size);
6543 if (gpr_size + fpr_size)
6546 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6547 gcc_assert (GET_CODE (reg_save_area) == MEM);
6548 reg_save_area = XEXP (reg_save_area, 0);
6549 if (GET_CODE (reg_save_area) == PLUS)
6551 gcc_assert (XEXP (reg_save_area, 0)
6552 == virtual_stack_vars_rtx);
6553 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6554 offset += INTVAL (XEXP (reg_save_area, 1));
6557 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6560 cfun->machine->varargs_save_offset = offset;
6561 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6566 first_reg_offset = next_cum.words;
6567 save_area = virtual_incoming_args_rtx;
6569 if (targetm.calls.must_pass_in_stack (mode, type))
6570 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6573 set = get_varargs_alias_set ();
6574 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6575 && cfun->va_list_gpr_size)
6577 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6579 if (va_list_gpr_counter_field)
6581 /* V4 va_list_gpr_size counts number of registers needed. */
6582 if (nregs > cfun->va_list_gpr_size)
6583 nregs = cfun->va_list_gpr_size;
6587 /* char * va_list instead counts number of bytes needed. */
6588 if (nregs > cfun->va_list_gpr_size / reg_size)
6589 nregs = cfun->va_list_gpr_size / reg_size;
6592 mem = gen_rtx_MEM (BLKmode,
6593 plus_constant (save_area,
6594 first_reg_offset * reg_size));
6595 MEM_NOTRAP_P (mem) = 1;
6596 set_mem_alias_set (mem, set);
6597 set_mem_align (mem, BITS_PER_WORD);
6599 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6603 /* Save FP registers if needed. */
6604 if (DEFAULT_ABI == ABI_V4
6605 && TARGET_HARD_FLOAT && TARGET_FPRS
6607 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6608 && cfun->va_list_fpr_size)
6610 int fregno = next_cum.fregno, nregs;
6611 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6612 rtx lab = gen_label_rtx ();
6613 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6614 * UNITS_PER_FP_WORD);
6617 (gen_rtx_SET (VOIDmode,
6619 gen_rtx_IF_THEN_ELSE (VOIDmode,
6620 gen_rtx_NE (VOIDmode, cr1,
6622 gen_rtx_LABEL_REF (VOIDmode, lab),
6626 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6627 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6629 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6630 MEM_NOTRAP_P (mem) = 1;
6631 set_mem_alias_set (mem, set);
6632 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6633 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6640 /* Create the va_list data type. */
6643 rs6000_build_builtin_va_list (void)
6645 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6647 /* For AIX, prefer 'char *' because that's what the system
6648 header files like. */
6649 if (DEFAULT_ABI != ABI_V4)
6650 return build_pointer_type (char_type_node);
6652 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6653 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6655 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6656 unsigned_char_type_node);
6657 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6658 unsigned_char_type_node);
6659 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6661 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6662 short_unsigned_type_node);
6663 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6665 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6668 va_list_gpr_counter_field = f_gpr;
6669 va_list_fpr_counter_field = f_fpr;
6671 DECL_FIELD_CONTEXT (f_gpr) = record;
6672 DECL_FIELD_CONTEXT (f_fpr) = record;
6673 DECL_FIELD_CONTEXT (f_res) = record;
6674 DECL_FIELD_CONTEXT (f_ovf) = record;
6675 DECL_FIELD_CONTEXT (f_sav) = record;
6677 TREE_CHAIN (record) = type_decl;
6678 TYPE_NAME (record) = type_decl;
6679 TYPE_FIELDS (record) = f_gpr;
6680 TREE_CHAIN (f_gpr) = f_fpr;
6681 TREE_CHAIN (f_fpr) = f_res;
6682 TREE_CHAIN (f_res) = f_ovf;
6683 TREE_CHAIN (f_ovf) = f_sav;
6685 layout_type (record);
6687 /* The correct type is an array type of one element. */
6688 return build_array_type (record, build_index_type (size_zero_node));
6691 /* Implement va_start. */
6694 rs6000_va_start (tree valist, rtx nextarg)
6696 HOST_WIDE_INT words, n_gpr, n_fpr;
6697 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6698 tree gpr, fpr, ovf, sav, t;
6700 /* Only SVR4 needs something special. */
6701 if (DEFAULT_ABI != ABI_V4)
6703 std_expand_builtin_va_start (valist, nextarg);
6707 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6708 f_fpr = TREE_CHAIN (f_gpr);
6709 f_res = TREE_CHAIN (f_fpr);
6710 f_ovf = TREE_CHAIN (f_res);
6711 f_sav = TREE_CHAIN (f_ovf);
6713 valist = build_va_arg_indirect_ref (valist);
6714 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6715 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6716 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6717 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6719 /* Count number of gp and fp argument registers used. */
6720 words = crtl->args.info.words;
6721 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
6723 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
6726 if (TARGET_DEBUG_ARG)
6727 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6728 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6729 words, n_gpr, n_fpr);
6731 if (cfun->va_list_gpr_size)
6733 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6734 build_int_cst (NULL_TREE, n_gpr));
6735 TREE_SIDE_EFFECTS (t) = 1;
6736 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6739 if (cfun->va_list_fpr_size)
6741 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6742 build_int_cst (NULL_TREE, n_fpr));
6743 TREE_SIDE_EFFECTS (t) = 1;
6744 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6747 /* Find the overflow area. */
6748 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6750 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6751 size_int (words * UNITS_PER_WORD));
6752 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6753 TREE_SIDE_EFFECTS (t) = 1;
6754 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6756 /* If there were no va_arg invocations, don't set up the register
6758 if (!cfun->va_list_gpr_size
6759 && !cfun->va_list_fpr_size
6760 && n_gpr < GP_ARG_NUM_REG
6761 && n_fpr < FP_ARG_V4_MAX_REG)
6764 /* Find the register save area. */
6765 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6766 if (cfun->machine->varargs_save_offset)
6767 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6768 size_int (cfun->machine->varargs_save_offset));
6769 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6770 TREE_SIDE_EFFECTS (t) = 1;
6771 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6774 /* Implement va_arg. */
6777 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6779 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6780 tree gpr, fpr, ovf, sav, reg, t, u;
6781 int size, rsize, n_reg, sav_ofs, sav_scale;
6782 tree lab_false, lab_over, addr;
6784 tree ptrtype = build_pointer_type (type);
6787 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6789 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6790 return build_va_arg_indirect_ref (t);
6793 if (DEFAULT_ABI != ABI_V4)
6795 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6797 tree elem_type = TREE_TYPE (type);
6798 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6799 int elem_size = GET_MODE_SIZE (elem_mode);
6801 if (elem_size < UNITS_PER_WORD)
6803 tree real_part, imag_part;
6804 tree post = NULL_TREE;
6806 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6808 /* Copy the value into a temporary, lest the formal temporary
6809 be reused out from under us. */
6810 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6811 append_to_statement_list (post, pre_p);
6813 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6816 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6820 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6823 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6824 f_fpr = TREE_CHAIN (f_gpr);
6825 f_res = TREE_CHAIN (f_fpr);
6826 f_ovf = TREE_CHAIN (f_res);
6827 f_sav = TREE_CHAIN (f_ovf);
6829 valist = build_va_arg_indirect_ref (valist);
6830 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6831 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6832 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6833 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6835 size = int_size_in_bytes (type);
6836 rsize = (size + 3) / 4;
6839 if (TARGET_HARD_FLOAT && TARGET_FPRS
6840 && (TYPE_MODE (type) == SFmode
6841 || TYPE_MODE (type) == DFmode
6842 || TYPE_MODE (type) == TFmode
6843 || TYPE_MODE (type) == SDmode
6844 || TYPE_MODE (type) == DDmode
6845 || TYPE_MODE (type) == TDmode))
6847 /* FP args go in FP registers, if present. */
6849 n_reg = (size + 7) / 8;
6852 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
6857 /* Otherwise into GP registers. */
6866 /* Pull the value out of the saved registers.... */
6869 addr = create_tmp_var (ptr_type_node, "addr");
6870 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6872 /* AltiVec vectors never go in registers when -mabi=altivec. */
6873 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6877 lab_false = create_artificial_label ();
6878 lab_over = create_artificial_label ();
6880 /* Long long and SPE vectors are aligned in the registers.
6881 As are any other 2 gpr item such as complex int due to a
6882 historical mistake. */
6884 if (n_reg == 2 && reg == gpr)
6887 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6888 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6889 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6891 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6892 reg number is 0 for f1, so we want to make it odd. */
6893 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6896 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg,
6897 build_int_cst (TREE_TYPE (reg), 1));
6898 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6901 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6902 t = build2 (GE_EXPR, boolean_type_node, u, t);
6903 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6904 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6905 gimplify_and_add (t, pre_p);
6909 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6911 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
6912 build_int_cst (TREE_TYPE (reg), n_reg));
6913 u = fold_convert (sizetype, u);
6914 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6915 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6917 /* _Decimal32 varargs are located in the second word of the 64-bit
6918 FP register for 32-bit binaries. */
6919 if (!TARGET_POWERPC64
6920 && TARGET_HARD_FLOAT && TARGET_FPRS
6921 && TYPE_MODE (type) == SDmode)
6922 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6924 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6925 gimplify_and_add (t, pre_p);
6927 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6928 gimplify_and_add (t, pre_p);
6930 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6931 append_to_statement_list (t, pre_p);
6933 if ((n_reg == 2 && !regalign) || n_reg > 2)
6935 /* Ensure that we don't find any more args in regs.
6936 Alignment has taken care of for special cases. */
6937 t = build_gimple_modify_stmt (reg,
6938 build_int_cst (TREE_TYPE (reg), 8));
6939 gimplify_and_add (t, pre_p);
6943 /* ... otherwise out of the overflow area. */
6945 /* Care for on-stack alignment if needed. */
6949 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6950 t = fold_convert (sizetype, t);
6951 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6953 t = fold_convert (TREE_TYPE (ovf), t);
6955 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6957 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6958 gimplify_and_add (u, pre_p);
6960 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6961 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6962 gimplify_and_add (t, pre_p);
6966 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6967 append_to_statement_list (t, pre_p);
6970 if (STRICT_ALIGNMENT
6971 && (TYPE_ALIGN (type)
6972 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6974 /* The value (of type complex double, for example) may not be
6975 aligned in memory in the saved registers, so copy via a
6976 temporary. (This is the same code as used for SPARC.) */
6977 tree tmp = create_tmp_var (type, "va_arg_tmp");
6978 tree dest_addr = build_fold_addr_expr (tmp);
6980 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6981 3, dest_addr, addr, size_int (rsize * 4));
6983 gimplify_and_add (copy, pre_p);
6987 addr = fold_convert (ptrtype, addr);
6988 return build_va_arg_indirect_ref (addr);
6994 def_builtin (int mask, const char *name, tree type, int code)
6996 if ((mask & target_flags) || TARGET_PAIRED_FLOAT)
6998 if (rs6000_builtin_decls[code])
7001 rs6000_builtin_decls[code] =
7002 add_builtin_function (name, type, code, BUILT_IN_MD,
7007 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
7009 static const struct builtin_description bdesc_3arg[] =
7011 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
7012 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
7013 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
7014 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
7015 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
7016 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
7017 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
7018 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
7019 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
7020 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
7021 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
7022 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
7023 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
7024 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
7025 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
7026 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
7027 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
7028 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
7029 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
7030 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
7031 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
7032 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
7033 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
7035 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
7036 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
7037 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
7038 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
7039 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
7040 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
7041 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
7042 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
7043 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
7044 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
7045 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
7046 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
7047 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
7048 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
7049 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
7051 { 0, CODE_FOR_paired_msub, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB },
7052 { 0, CODE_FOR_paired_madd, "__builtin_paired_madd", PAIRED_BUILTIN_MADD },
7053 { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 },
7054 { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 },
7055 { 0, CODE_FOR_paired_nmsub, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB },
7056 { 0, CODE_FOR_paired_nmadd, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD },
7057 { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 },
7058 { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 },
7059 { 0, CODE_FOR_selv2sf4, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4 },
7062 /* DST operations: void foo (void *, const int, const char). */
7064 static const struct builtin_description bdesc_dst[] =
7066 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
7067 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
7068 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
7069 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
7071 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
7072 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
7073 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
7074 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
7077 /* Simple binary operations: VECc = foo (VECa, VECb). */
7079 static struct builtin_description bdesc_2arg[] =
7081 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
7082 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
7083 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
7084 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
7085 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
7086 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
7087 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
7088 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
7089 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
7090 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
7091 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
7092 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
7093 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
7094 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
7095 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
7096 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
7097 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
7098 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
7099 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
7100 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
7101 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
7102 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
7103 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
7104 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
7105 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
7106 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
7107 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
7108 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
7109 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
7110 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
7111 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
7112 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
7113 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
7114 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
7115 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
7116 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
7117 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
7118 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
7119 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
7120 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
7121 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
7122 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
7123 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
7124 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
7125 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
7126 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
7127 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
7128 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
7129 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
7130 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
7131 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
7132 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
7133 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
7134 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
7135 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
7136 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
7137 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
7138 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
7139 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
7140 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
7141 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
7142 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
7143 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
7144 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
7145 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
7146 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
7147 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
7148 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
7149 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
7150 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
7151 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
7152 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
7153 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
7154 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
7155 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
7156 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
7157 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
7158 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
7159 { MASK_ALTIVEC, CODE_FOR_vashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
7160 { MASK_ALTIVEC, CODE_FOR_vashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
7161 { MASK_ALTIVEC, CODE_FOR_vashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
7162 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
7163 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
7164 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
7165 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
7166 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
7167 { MASK_ALTIVEC, CODE_FOR_vlshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
7168 { MASK_ALTIVEC, CODE_FOR_vlshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
7169 { MASK_ALTIVEC, CODE_FOR_vlshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
7170 { MASK_ALTIVEC, CODE_FOR_vashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
7171 { MASK_ALTIVEC, CODE_FOR_vashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
7172 { MASK_ALTIVEC, CODE_FOR_vashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
7173 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
7174 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
7175 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
7176 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
7177 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
7178 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
7179 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
7180 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
7181 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
7182 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
7183 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
7184 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
7185 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
7186 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
7187 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
7188 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
7189 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
7190 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
7191 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
7193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
7194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
7195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
7196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
7197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
7198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
7199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
7200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
7201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
7202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
7203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
7204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
7205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
7206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
7207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
7208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
7209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
7210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
7211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
7212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
7213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
7214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
7215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
7216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
7217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
7218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
7219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
7220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
7221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
7222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
7223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
7224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
7225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
7226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
7227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
7228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
7229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
7230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
7231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
7232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
7233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
7234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
7235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
7236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
7237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
7238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
7239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
7240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
7241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
7242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
7243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
7244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
7245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
7246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
7247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
7248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
7249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
7250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
7251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
7252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
7253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
7254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
7255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
7256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
7257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
7258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
7259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
7260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
7261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
7262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
7263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
7264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
7265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
7266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
7267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
7268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
7269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
7270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
7271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
7272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
7273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
7274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
7275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
7276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
7277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
7278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
7279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
7280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
7281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
7282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
7283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
7284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
7285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
7286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
7287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
7288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
7289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
7290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
7291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
7292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
7293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
7294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
7295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
7296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
7297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
7298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
7299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
7300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
7301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
7302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
7303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
7304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
7305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
7306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
7307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
7308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
7309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
7310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
7311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
7312 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
7313 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
7314 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
7315 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
7316 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
7317 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
7318 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
7319 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
7321 { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
7322 { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
7323 { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
7324 { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
7325 { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
7326 { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
7327 { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
7328 { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 },
7329 { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 },
7330 { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
7332 /* Place holder, leave as first spe builtin. */
7333 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
7334 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
7335 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
7336 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
7337 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
7338 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
7339 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
7340 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
7341 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
7342 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
7343 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
7344 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
7345 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
7346 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
7347 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
7348 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
7349 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
7350 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
7351 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
7352 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
7353 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
7354 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
7355 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
7356 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
7357 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
7358 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
7359 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
7360 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
7361 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
7362 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
7363 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
7364 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
7365 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
7366 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
7367 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
7368 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
7369 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
7370 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
7371 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
7372 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
7373 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
7374 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
7375 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
7376 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
7377 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
7378 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
7379 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
7380 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
7381 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
7382 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
7383 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
7384 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
7385 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
7386 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
7387 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
7388 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
7389 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
7390 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
7391 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
7392 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
7393 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
7394 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
7395 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
7396 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
7397 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
7398 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
7399 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
7400 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
7401 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
7402 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
7403 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
7404 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
7405 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
7406 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
7407 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
7408 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
7409 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
7410 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
7411 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
7412 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
7413 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
7414 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
7415 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
7416 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
7417 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
7418 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
7419 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
7420 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
7421 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
7422 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
7423 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
7424 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
7425 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7426 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7427 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7428 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7429 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7430 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7431 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7432 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7433 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7434 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7435 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7436 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7437 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7438 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7439 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7440 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7441 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7443 /* SPE binary operations expecting a 5-bit unsigned literal. */
7444 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7446 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7447 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7448 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7449 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7450 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7451 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7452 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7453 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7454 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7455 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7456 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7457 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7458 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7459 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7460 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7461 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7462 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7463 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7464 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7465 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7466 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7467 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7468 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7469 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7470 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7471 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7473 /* Place-holder. Leave as last binary SPE builtin. */
7474 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7477 /* AltiVec predicates. */
7479 struct builtin_description_predicates
7481 const unsigned int mask;
7482 const enum insn_code icode;
7484 const char *const name;
7485 const enum rs6000_builtins code;
7488 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7490 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7491 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7492 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7493 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7494 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7495 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7496 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7497 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7498 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7499 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7500 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7501 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7502 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7504 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7505 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7506 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7509 /* SPE predicates. */
7510 static struct builtin_description bdesc_spe_predicates[] =
7512 /* Place-holder. Leave as first. */
7513 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7514 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7515 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7516 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7517 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7518 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7519 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7520 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7521 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7522 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7523 /* Place-holder. Leave as last. */
7524 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7527 /* SPE evsel predicates. */
7528 static struct builtin_description bdesc_spe_evsel[] =
7530 /* Place-holder. Leave as first. */
7531 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7532 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7533 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7534 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7535 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7536 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7537 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7538 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7539 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7540 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7541 /* Place-holder. Leave as last. */
7542 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7545 /* PAIRED predicates. */
7546 static const struct builtin_description bdesc_paired_preds[] =
7548 /* Place-holder. Leave as first. */
7549 { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 },
7550 /* Place-holder. Leave as last. */
7551 { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 },
7554 /* ABS* operations. */
7556 static const struct builtin_description bdesc_abs[] =
7558 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7559 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7560 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7561 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7562 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7563 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7564 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7567 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7570 static struct builtin_description bdesc_1arg[] =
7572 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7573 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7574 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7575 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7576 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7577 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7578 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7579 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7580 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7581 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7582 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7583 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7584 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7585 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7586 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7587 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7588 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7590 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7591 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7592 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7593 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7594 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7595 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7596 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7597 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7598 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7599 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7600 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7601 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7602 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7603 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7604 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7605 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7606 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7607 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7608 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7610 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7611 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7612 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7613 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7614 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7615 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7616 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7617 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7618 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7619 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7620 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7621 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7622 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7623 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7624 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7625 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7626 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7627 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7628 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7629 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7630 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7631 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7632 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7633 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7634 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7635 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7636 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7637 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7638 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7639 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7641 /* Place-holder. Leave as last unary SPE builtin. */
7642 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
7644 { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
7645 { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
7646 { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
7647 { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
7648 { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
7652 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7655 tree arg0 = CALL_EXPR_ARG (exp, 0);
7656 rtx op0 = expand_normal (arg0);
7657 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7658 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7660 if (icode == CODE_FOR_nothing)
7661 /* Builtin not supported on this processor. */
7664 /* If we got invalid arguments bail out before generating bad rtl. */
7665 if (arg0 == error_mark_node)
7668 if (icode == CODE_FOR_altivec_vspltisb
7669 || icode == CODE_FOR_altivec_vspltish
7670 || icode == CODE_FOR_altivec_vspltisw
7671 || icode == CODE_FOR_spe_evsplatfi
7672 || icode == CODE_FOR_spe_evsplati)
7674 /* Only allow 5-bit *signed* literals. */
7675 if (GET_CODE (op0) != CONST_INT
7676 || INTVAL (op0) > 15
7677 || INTVAL (op0) < -16)
7679 error ("argument 1 must be a 5-bit signed literal");
7685 || GET_MODE (target) != tmode
7686 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7687 target = gen_reg_rtx (tmode);
7689 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7690 op0 = copy_to_mode_reg (mode0, op0);
7692 pat = GEN_FCN (icode) (target, op0);
7701 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7703 rtx pat, scratch1, scratch2;
7704 tree arg0 = CALL_EXPR_ARG (exp, 0);
7705 rtx op0 = expand_normal (arg0);
7706 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7707 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7709 /* If we have invalid arguments, bail out before generating bad rtl. */
7710 if (arg0 == error_mark_node)
7714 || GET_MODE (target) != tmode
7715 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7716 target = gen_reg_rtx (tmode);
7718 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7719 op0 = copy_to_mode_reg (mode0, op0);
7721 scratch1 = gen_reg_rtx (mode0);
7722 scratch2 = gen_reg_rtx (mode0);
7724 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7733 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7736 tree arg0 = CALL_EXPR_ARG (exp, 0);
7737 tree arg1 = CALL_EXPR_ARG (exp, 1);
7738 rtx op0 = expand_normal (arg0);
7739 rtx op1 = expand_normal (arg1);
7740 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7741 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7742 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7744 if (icode == CODE_FOR_nothing)
7745 /* Builtin not supported on this processor. */
7748 /* If we got invalid arguments bail out before generating bad rtl. */
7749 if (arg0 == error_mark_node || arg1 == error_mark_node)
7752 if (icode == CODE_FOR_altivec_vcfux
7753 || icode == CODE_FOR_altivec_vcfsx
7754 || icode == CODE_FOR_altivec_vctsxs
7755 || icode == CODE_FOR_altivec_vctuxs
7756 || icode == CODE_FOR_altivec_vspltb
7757 || icode == CODE_FOR_altivec_vsplth
7758 || icode == CODE_FOR_altivec_vspltw
7759 || icode == CODE_FOR_spe_evaddiw
7760 || icode == CODE_FOR_spe_evldd
7761 || icode == CODE_FOR_spe_evldh
7762 || icode == CODE_FOR_spe_evldw
7763 || icode == CODE_FOR_spe_evlhhesplat
7764 || icode == CODE_FOR_spe_evlhhossplat
7765 || icode == CODE_FOR_spe_evlhhousplat
7766 || icode == CODE_FOR_spe_evlwhe
7767 || icode == CODE_FOR_spe_evlwhos
7768 || icode == CODE_FOR_spe_evlwhou
7769 || icode == CODE_FOR_spe_evlwhsplat
7770 || icode == CODE_FOR_spe_evlwwsplat
7771 || icode == CODE_FOR_spe_evrlwi
7772 || icode == CODE_FOR_spe_evslwi
7773 || icode == CODE_FOR_spe_evsrwis
7774 || icode == CODE_FOR_spe_evsubifw
7775 || icode == CODE_FOR_spe_evsrwiu)
7777 /* Only allow 5-bit unsigned literals. */
7779 if (TREE_CODE (arg1) != INTEGER_CST
7780 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7782 error ("argument 2 must be a 5-bit unsigned literal");
7788 || GET_MODE (target) != tmode
7789 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7790 target = gen_reg_rtx (tmode);
7792 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7793 op0 = copy_to_mode_reg (mode0, op0);
7794 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7795 op1 = copy_to_mode_reg (mode1, op1);
7797 pat = GEN_FCN (icode) (target, op0, op1);
7806 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7807 tree exp, rtx target)
7810 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7811 tree arg0 = CALL_EXPR_ARG (exp, 1);
7812 tree arg1 = CALL_EXPR_ARG (exp, 2);
7813 rtx op0 = expand_normal (arg0);
7814 rtx op1 = expand_normal (arg1);
7815 enum machine_mode tmode = SImode;
7816 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7817 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7820 if (TREE_CODE (cr6_form) != INTEGER_CST)
7822 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7826 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7828 gcc_assert (mode0 == mode1);
7830 /* If we have invalid arguments, bail out before generating bad rtl. */
7831 if (arg0 == error_mark_node || arg1 == error_mark_node)
7835 || GET_MODE (target) != tmode
7836 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7837 target = gen_reg_rtx (tmode);
7839 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7840 op0 = copy_to_mode_reg (mode0, op0);
7841 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7842 op1 = copy_to_mode_reg (mode1, op1);
7844 scratch = gen_reg_rtx (mode0);
7846 pat = GEN_FCN (icode) (scratch, op0, op1,
7847 gen_rtx_SYMBOL_REF (Pmode, opcode));
7852 /* The vec_any* and vec_all* predicates use the same opcodes for two
7853 different operations, but the bits in CR6 will be different
7854 depending on what information we want. So we have to play tricks
7855 with CR6 to get the right bits out.
7857 If you think this is disgusting, look at the specs for the
7858 AltiVec predicates. */
7860 switch (cr6_form_int)
7863 emit_insn (gen_cr6_test_for_zero (target));
7866 emit_insn (gen_cr6_test_for_zero_reverse (target));
7869 emit_insn (gen_cr6_test_for_lt (target));
7872 emit_insn (gen_cr6_test_for_lt_reverse (target));
7875 error ("argument 1 of __builtin_altivec_predicate is out of range");
7883 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7886 tree arg0 = CALL_EXPR_ARG (exp, 0);
7887 tree arg1 = CALL_EXPR_ARG (exp, 1);
7888 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7889 enum machine_mode mode0 = Pmode;
7890 enum machine_mode mode1 = Pmode;
7891 rtx op0 = expand_normal (arg0);
7892 rtx op1 = expand_normal (arg1);
7894 if (icode == CODE_FOR_nothing)
7895 /* Builtin not supported on this processor. */
7898 /* If we got invalid arguments bail out before generating bad rtl. */
7899 if (arg0 == error_mark_node || arg1 == error_mark_node)
7903 || GET_MODE (target) != tmode
7904 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7905 target = gen_reg_rtx (tmode);
7907 op1 = copy_to_mode_reg (mode1, op1);
7909 if (op0 == const0_rtx)
7911 addr = gen_rtx_MEM (tmode, op1);
7915 op0 = copy_to_mode_reg (mode0, op0);
7916 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7919 pat = GEN_FCN (icode) (target, addr);
7929 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7932 tree arg0 = CALL_EXPR_ARG (exp, 0);
7933 tree arg1 = CALL_EXPR_ARG (exp, 1);
7934 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7935 enum machine_mode mode0 = Pmode;
7936 enum machine_mode mode1 = Pmode;
7937 rtx op0 = expand_normal (arg0);
7938 rtx op1 = expand_normal (arg1);
7940 if (icode == CODE_FOR_nothing)
7941 /* Builtin not supported on this processor. */
7944 /* If we got invalid arguments bail out before generating bad rtl. */
7945 if (arg0 == error_mark_node || arg1 == error_mark_node)
7949 || GET_MODE (target) != tmode
7950 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7951 target = gen_reg_rtx (tmode);
7953 op1 = copy_to_mode_reg (mode1, op1);
7955 if (op0 == const0_rtx)
7957 addr = gen_rtx_MEM (tmode, op1);
7961 op0 = copy_to_mode_reg (mode0, op0);
7962 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7965 pat = GEN_FCN (icode) (target, addr);
7975 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7977 tree arg0 = CALL_EXPR_ARG (exp, 0);
7978 tree arg1 = CALL_EXPR_ARG (exp, 1);
7979 tree arg2 = CALL_EXPR_ARG (exp, 2);
7980 rtx op0 = expand_normal (arg0);
7981 rtx op1 = expand_normal (arg1);
7982 rtx op2 = expand_normal (arg2);
7984 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7985 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7986 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7988 /* Invalid arguments. Bail before doing anything stoopid! */
7989 if (arg0 == error_mark_node
7990 || arg1 == error_mark_node
7991 || arg2 == error_mark_node)
7994 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7995 op0 = copy_to_mode_reg (mode2, op0);
7996 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7997 op1 = copy_to_mode_reg (mode0, op1);
7998 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7999 op2 = copy_to_mode_reg (mode1, op2);
8001 pat = GEN_FCN (icode) (op1, op2, op0);
8008 paired_expand_stv_builtin (enum insn_code icode, tree exp)
8010 tree arg0 = CALL_EXPR_ARG (exp, 0);
8011 tree arg1 = CALL_EXPR_ARG (exp, 1);
8012 tree arg2 = CALL_EXPR_ARG (exp, 2);
8013 rtx op0 = expand_normal (arg0);
8014 rtx op1 = expand_normal (arg1);
8015 rtx op2 = expand_normal (arg2);
8017 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8018 enum machine_mode mode1 = Pmode;
8019 enum machine_mode mode2 = Pmode;
8021 /* Invalid arguments. Bail before doing anything stoopid! */
8022 if (arg0 == error_mark_node
8023 || arg1 == error_mark_node
8024 || arg2 == error_mark_node)
8027 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
8028 op0 = copy_to_mode_reg (tmode, op0);
8030 op2 = copy_to_mode_reg (mode2, op2);
8032 if (op1 == const0_rtx)
8034 addr = gen_rtx_MEM (tmode, op2);
8038 op1 = copy_to_mode_reg (mode1, op1);
8039 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
8042 pat = GEN_FCN (icode) (addr, op0);
8049 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
8051 tree arg0 = CALL_EXPR_ARG (exp, 0);
8052 tree arg1 = CALL_EXPR_ARG (exp, 1);
8053 tree arg2 = CALL_EXPR_ARG (exp, 2);
8054 rtx op0 = expand_normal (arg0);
8055 rtx op1 = expand_normal (arg1);
8056 rtx op2 = expand_normal (arg2);
8058 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8059 enum machine_mode mode1 = Pmode;
8060 enum machine_mode mode2 = Pmode;
8062 /* Invalid arguments. Bail before doing anything stoopid! */
8063 if (arg0 == error_mark_node
8064 || arg1 == error_mark_node
8065 || arg2 == error_mark_node)
8068 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
8069 op0 = copy_to_mode_reg (tmode, op0);
8071 op2 = copy_to_mode_reg (mode2, op2);
8073 if (op1 == const0_rtx)
8075 addr = gen_rtx_MEM (tmode, op2);
8079 op1 = copy_to_mode_reg (mode1, op1);
8080 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
8083 pat = GEN_FCN (icode) (addr, op0);
8090 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
8093 tree arg0 = CALL_EXPR_ARG (exp, 0);
8094 tree arg1 = CALL_EXPR_ARG (exp, 1);
8095 tree arg2 = CALL_EXPR_ARG (exp, 2);
8096 rtx op0 = expand_normal (arg0);
8097 rtx op1 = expand_normal (arg1);
8098 rtx op2 = expand_normal (arg2);
8099 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8100 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8101 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8102 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
8104 if (icode == CODE_FOR_nothing)
8105 /* Builtin not supported on this processor. */
8108 /* If we got invalid arguments bail out before generating bad rtl. */
8109 if (arg0 == error_mark_node
8110 || arg1 == error_mark_node
8111 || arg2 == error_mark_node)
8114 if (icode == CODE_FOR_altivec_vsldoi_v4sf
8115 || icode == CODE_FOR_altivec_vsldoi_v4si
8116 || icode == CODE_FOR_altivec_vsldoi_v8hi
8117 || icode == CODE_FOR_altivec_vsldoi_v16qi)
8119 /* Only allow 4-bit unsigned literals. */
8121 if (TREE_CODE (arg2) != INTEGER_CST
8122 || TREE_INT_CST_LOW (arg2) & ~0xf)
8124 error ("argument 3 must be a 4-bit unsigned literal");
8130 || GET_MODE (target) != tmode
8131 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8132 target = gen_reg_rtx (tmode);
8134 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8135 op0 = copy_to_mode_reg (mode0, op0);
8136 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8137 op1 = copy_to_mode_reg (mode1, op1);
8138 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
8139 op2 = copy_to_mode_reg (mode2, op2);
8141 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
8142 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
8144 pat = GEN_FCN (icode) (target, op0, op1, op2);
8152 /* Expand the lvx builtins. */
8154 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
8156 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8157 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8159 enum machine_mode tmode, mode0;
8161 enum insn_code icode;
8165 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
8166 icode = CODE_FOR_altivec_lvx_v16qi;
8168 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
8169 icode = CODE_FOR_altivec_lvx_v8hi;
8171 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
8172 icode = CODE_FOR_altivec_lvx_v4si;
8174 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
8175 icode = CODE_FOR_altivec_lvx_v4sf;
8184 arg0 = CALL_EXPR_ARG (exp, 0);
8185 op0 = expand_normal (arg0);
8186 tmode = insn_data[icode].operand[0].mode;
8187 mode0 = insn_data[icode].operand[1].mode;
8190 || GET_MODE (target) != tmode
8191 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8192 target = gen_reg_rtx (tmode);
8194 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8195 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8197 pat = GEN_FCN (icode) (target, op0);
8204 /* Expand the stvx builtins. */
8206 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8209 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8210 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8212 enum machine_mode mode0, mode1;
8214 enum insn_code icode;
8218 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
8219 icode = CODE_FOR_altivec_stvx_v16qi;
8221 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
8222 icode = CODE_FOR_altivec_stvx_v8hi;
8224 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
8225 icode = CODE_FOR_altivec_stvx_v4si;
8227 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
8228 icode = CODE_FOR_altivec_stvx_v4sf;
8235 arg0 = CALL_EXPR_ARG (exp, 0);
8236 arg1 = CALL_EXPR_ARG (exp, 1);
8237 op0 = expand_normal (arg0);
8238 op1 = expand_normal (arg1);
8239 mode0 = insn_data[icode].operand[0].mode;
8240 mode1 = insn_data[icode].operand[1].mode;
8242 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8243 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8244 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8245 op1 = copy_to_mode_reg (mode1, op1);
8247 pat = GEN_FCN (icode) (op0, op1);
8255 /* Expand the dst builtins. */
8257 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8260 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8261 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8262 tree arg0, arg1, arg2;
8263 enum machine_mode mode0, mode1, mode2;
8264 rtx pat, op0, op1, op2;
8265 const struct builtin_description *d;
8270 /* Handle DST variants. */
8272 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8273 if (d->code == fcode)
8275 arg0 = CALL_EXPR_ARG (exp, 0);
8276 arg1 = CALL_EXPR_ARG (exp, 1);
8277 arg2 = CALL_EXPR_ARG (exp, 2);
8278 op0 = expand_normal (arg0);
8279 op1 = expand_normal (arg1);
8280 op2 = expand_normal (arg2);
8281 mode0 = insn_data[d->icode].operand[0].mode;
8282 mode1 = insn_data[d->icode].operand[1].mode;
8283 mode2 = insn_data[d->icode].operand[2].mode;
8285 /* Invalid arguments, bail out before generating bad rtl. */
8286 if (arg0 == error_mark_node
8287 || arg1 == error_mark_node
8288 || arg2 == error_mark_node)
8293 if (TREE_CODE (arg2) != INTEGER_CST
8294 || TREE_INT_CST_LOW (arg2) & ~0x3)
8296 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
8300 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
8301 op0 = copy_to_mode_reg (Pmode, op0);
8302 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
8303 op1 = copy_to_mode_reg (mode1, op1);
8305 pat = GEN_FCN (d->icode) (op0, op1, op2);
8315 /* Expand vec_init builtin. */
8317 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
8319 enum machine_mode tmode = TYPE_MODE (type);
8320 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
8321 int i, n_elt = GET_MODE_NUNITS (tmode);
8322 rtvec v = rtvec_alloc (n_elt);
8324 gcc_assert (VECTOR_MODE_P (tmode));
8325 gcc_assert (n_elt == call_expr_nargs (exp));
8327 for (i = 0; i < n_elt; ++i)
8329 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
8330 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
8333 if (!target || !register_operand (target, tmode))
8334 target = gen_reg_rtx (tmode);
8336 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
8340 /* Return the integer constant in ARG. Constrain it to be in the range
8341 of the subparts of VEC_TYPE; issue an error if not. */
8344 get_element_number (tree vec_type, tree arg)
8346 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
8348 if (!host_integerp (arg, 1)
8349 || (elt = tree_low_cst (arg, 1), elt > max))
8351 error ("selector must be an integer constant in the range 0..%wi", max);
8358 /* Expand vec_set builtin. */
8360 altivec_expand_vec_set_builtin (tree exp)
8362 enum machine_mode tmode, mode1;
8363 tree arg0, arg1, arg2;
8367 arg0 = CALL_EXPR_ARG (exp, 0);
8368 arg1 = CALL_EXPR_ARG (exp, 1);
8369 arg2 = CALL_EXPR_ARG (exp, 2);
8371 tmode = TYPE_MODE (TREE_TYPE (arg0));
8372 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8373 gcc_assert (VECTOR_MODE_P (tmode));
8375 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
8376 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
8377 elt = get_element_number (TREE_TYPE (arg0), arg2);
8379 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
8380 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
8382 op0 = force_reg (tmode, op0);
8383 op1 = force_reg (mode1, op1);
8385 rs6000_expand_vector_set (op0, op1, elt);
8390 /* Expand vec_ext builtin. */
8392 altivec_expand_vec_ext_builtin (tree exp, rtx target)
8394 enum machine_mode tmode, mode0;
8399 arg0 = CALL_EXPR_ARG (exp, 0);
8400 arg1 = CALL_EXPR_ARG (exp, 1);
8402 op0 = expand_normal (arg0);
8403 elt = get_element_number (TREE_TYPE (arg0), arg1);
8405 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8406 mode0 = TYPE_MODE (TREE_TYPE (arg0));
8407 gcc_assert (VECTOR_MODE_P (mode0));
8409 op0 = force_reg (mode0, op0);
8411 if (optimize || !target || !register_operand (target, tmode))
8412 target = gen_reg_rtx (tmode);
8414 rs6000_expand_vector_extract (target, op0, elt);
8419 /* Expand the builtin in EXP and store the result in TARGET. Store
8420 true in *EXPANDEDP if we found a builtin to expand. */
8422 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
8424 const struct builtin_description *d;
8425 const struct builtin_description_predicates *dp;
8427 enum insn_code icode;
8428 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8431 enum machine_mode tmode, mode0;
8432 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8434 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8435 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
8438 error ("unresolved overload for Altivec builtin %qF", fndecl);
8442 target = altivec_expand_ld_builtin (exp, target, expandedp);
8446 target = altivec_expand_st_builtin (exp, target, expandedp);
8450 target = altivec_expand_dst_builtin (exp, target, expandedp);
8458 case ALTIVEC_BUILTIN_STVX:
8459 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
8460 case ALTIVEC_BUILTIN_STVEBX:
8461 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
8462 case ALTIVEC_BUILTIN_STVEHX:
8463 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
8464 case ALTIVEC_BUILTIN_STVEWX:
8465 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
8466 case ALTIVEC_BUILTIN_STVXL:
8467 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
8469 case ALTIVEC_BUILTIN_MFVSCR:
8470 icode = CODE_FOR_altivec_mfvscr;
8471 tmode = insn_data[icode].operand[0].mode;
8474 || GET_MODE (target) != tmode
8475 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8476 target = gen_reg_rtx (tmode);
8478 pat = GEN_FCN (icode) (target);
8484 case ALTIVEC_BUILTIN_MTVSCR:
8485 icode = CODE_FOR_altivec_mtvscr;
8486 arg0 = CALL_EXPR_ARG (exp, 0);
8487 op0 = expand_normal (arg0);
8488 mode0 = insn_data[icode].operand[0].mode;
8490 /* If we got invalid arguments bail out before generating bad rtl. */
8491 if (arg0 == error_mark_node)
8494 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8495 op0 = copy_to_mode_reg (mode0, op0);
8497 pat = GEN_FCN (icode) (op0);
8502 case ALTIVEC_BUILTIN_DSSALL:
8503 emit_insn (gen_altivec_dssall ());
8506 case ALTIVEC_BUILTIN_DSS:
8507 icode = CODE_FOR_altivec_dss;
8508 arg0 = CALL_EXPR_ARG (exp, 0);
8510 op0 = expand_normal (arg0);
8511 mode0 = insn_data[icode].operand[0].mode;
8513 /* If we got invalid arguments bail out before generating bad rtl. */
8514 if (arg0 == error_mark_node)
8517 if (TREE_CODE (arg0) != INTEGER_CST
8518 || TREE_INT_CST_LOW (arg0) & ~0x3)
8520 error ("argument to dss must be a 2-bit unsigned literal");
8524 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8525 op0 = copy_to_mode_reg (mode0, op0);
8527 emit_insn (gen_altivec_dss (op0));
8530 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8531 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8532 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8533 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8534 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8536 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8537 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8538 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8539 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8540 return altivec_expand_vec_set_builtin (exp);
8542 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8543 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8544 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8545 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8546 return altivec_expand_vec_ext_builtin (exp, target);
8553 /* Expand abs* operations. */
8555 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8556 if (d->code == fcode)
8557 return altivec_expand_abs_builtin (d->icode, exp, target);
8559 /* Expand the AltiVec predicates. */
8560 dp = bdesc_altivec_preds;
8561 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8562 if (dp->code == fcode)
8563 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8566 /* LV* are funky. We initialized them differently. */
8569 case ALTIVEC_BUILTIN_LVSL:
8570 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8572 case ALTIVEC_BUILTIN_LVSR:
8573 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8575 case ALTIVEC_BUILTIN_LVEBX:
8576 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8578 case ALTIVEC_BUILTIN_LVEHX:
8579 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8581 case ALTIVEC_BUILTIN_LVEWX:
8582 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8584 case ALTIVEC_BUILTIN_LVXL:
8585 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8587 case ALTIVEC_BUILTIN_LVX:
8588 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8599 /* Expand the builtin in EXP and store the result in TARGET. Store
8600 true in *EXPANDEDP if we found a builtin to expand. */
8602 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
8604 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8605 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8606 const struct builtin_description *d;
8613 case PAIRED_BUILTIN_STX:
8614 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
8615 case PAIRED_BUILTIN_LX:
8616 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
8622 /* Expand the paired predicates. */
8623 d = bdesc_paired_preds;
8624 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
8625 if (d->code == fcode)
8626 return paired_expand_predicate_builtin (d->icode, exp, target);
8632 /* Binops that need to be initialized manually, but can be expanded
8633 automagically by rs6000_expand_binop_builtin. */
8634 static struct builtin_description bdesc_2arg_spe[] =
8636 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8637 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8638 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8639 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8640 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8641 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8642 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8643 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8644 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8645 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8646 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8647 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8648 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8649 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8650 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8651 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8652 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8653 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8654 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8655 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8656 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8657 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8660 /* Expand the builtin in EXP and store the result in TARGET. Store
8661 true in *EXPANDEDP if we found a builtin to expand.
8663 This expands the SPE builtins that are not simple unary and binary
8666 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8668 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8670 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8671 enum insn_code icode;
8672 enum machine_mode tmode, mode0;
8674 struct builtin_description *d;
8679 /* Syntax check for a 5-bit unsigned immediate. */
8682 case SPE_BUILTIN_EVSTDD:
8683 case SPE_BUILTIN_EVSTDH:
8684 case SPE_BUILTIN_EVSTDW:
8685 case SPE_BUILTIN_EVSTWHE:
8686 case SPE_BUILTIN_EVSTWHO:
8687 case SPE_BUILTIN_EVSTWWE:
8688 case SPE_BUILTIN_EVSTWWO:
8689 arg1 = CALL_EXPR_ARG (exp, 2);
8690 if (TREE_CODE (arg1) != INTEGER_CST
8691 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8693 error ("argument 2 must be a 5-bit unsigned literal");
8701 /* The evsplat*i instructions are not quite generic. */
8704 case SPE_BUILTIN_EVSPLATFI:
8705 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8707 case SPE_BUILTIN_EVSPLATI:
8708 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8714 d = (struct builtin_description *) bdesc_2arg_spe;
8715 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8716 if (d->code == fcode)
8717 return rs6000_expand_binop_builtin (d->icode, exp, target);
8719 d = (struct builtin_description *) bdesc_spe_predicates;
8720 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8721 if (d->code == fcode)
8722 return spe_expand_predicate_builtin (d->icode, exp, target);
8724 d = (struct builtin_description *) bdesc_spe_evsel;
8725 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8726 if (d->code == fcode)
8727 return spe_expand_evsel_builtin (d->icode, exp, target);
8731 case SPE_BUILTIN_EVSTDDX:
8732 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8733 case SPE_BUILTIN_EVSTDHX:
8734 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8735 case SPE_BUILTIN_EVSTDWX:
8736 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8737 case SPE_BUILTIN_EVSTWHEX:
8738 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8739 case SPE_BUILTIN_EVSTWHOX:
8740 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8741 case SPE_BUILTIN_EVSTWWEX:
8742 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8743 case SPE_BUILTIN_EVSTWWOX:
8744 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8745 case SPE_BUILTIN_EVSTDD:
8746 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8747 case SPE_BUILTIN_EVSTDH:
8748 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8749 case SPE_BUILTIN_EVSTDW:
8750 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8751 case SPE_BUILTIN_EVSTWHE:
8752 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8753 case SPE_BUILTIN_EVSTWHO:
8754 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8755 case SPE_BUILTIN_EVSTWWE:
8756 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8757 case SPE_BUILTIN_EVSTWWO:
8758 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8759 case SPE_BUILTIN_MFSPEFSCR:
8760 icode = CODE_FOR_spe_mfspefscr;
8761 tmode = insn_data[icode].operand[0].mode;
8764 || GET_MODE (target) != tmode
8765 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8766 target = gen_reg_rtx (tmode);
8768 pat = GEN_FCN (icode) (target);
8773 case SPE_BUILTIN_MTSPEFSCR:
8774 icode = CODE_FOR_spe_mtspefscr;
8775 arg0 = CALL_EXPR_ARG (exp, 0);
8776 op0 = expand_normal (arg0);
8777 mode0 = insn_data[icode].operand[0].mode;
8779 if (arg0 == error_mark_node)
8782 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8783 op0 = copy_to_mode_reg (mode0, op0);
8785 pat = GEN_FCN (icode) (op0);
8798 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8800 rtx pat, scratch, tmp;
8801 tree form = CALL_EXPR_ARG (exp, 0);
8802 tree arg0 = CALL_EXPR_ARG (exp, 1);
8803 tree arg1 = CALL_EXPR_ARG (exp, 2);
8804 rtx op0 = expand_normal (arg0);
8805 rtx op1 = expand_normal (arg1);
8806 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8807 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8811 if (TREE_CODE (form) != INTEGER_CST)
8813 error ("argument 1 of __builtin_paired_predicate must be a constant");
8817 form_int = TREE_INT_CST_LOW (form);
8819 gcc_assert (mode0 == mode1);
8821 if (arg0 == error_mark_node || arg1 == error_mark_node)
8825 || GET_MODE (target) != SImode
8826 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
8827 target = gen_reg_rtx (SImode);
8828 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
8829 op0 = copy_to_mode_reg (mode0, op0);
8830 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
8831 op1 = copy_to_mode_reg (mode1, op1);
8833 scratch = gen_reg_rtx (CCFPmode);
8835 pat = GEN_FCN (icode) (scratch, op0, op1);
8857 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8860 error ("argument 1 of __builtin_paired_predicate is out of range");
8864 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8865 emit_move_insn (target, tmp);
8870 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8872 rtx pat, scratch, tmp;
8873 tree form = CALL_EXPR_ARG (exp, 0);
8874 tree arg0 = CALL_EXPR_ARG (exp, 1);
8875 tree arg1 = CALL_EXPR_ARG (exp, 2);
8876 rtx op0 = expand_normal (arg0);
8877 rtx op1 = expand_normal (arg1);
8878 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8879 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8883 if (TREE_CODE (form) != INTEGER_CST)
8885 error ("argument 1 of __builtin_spe_predicate must be a constant");
8889 form_int = TREE_INT_CST_LOW (form);
8891 gcc_assert (mode0 == mode1);
8893 if (arg0 == error_mark_node || arg1 == error_mark_node)
8897 || GET_MODE (target) != SImode
8898 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8899 target = gen_reg_rtx (SImode);
8901 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8902 op0 = copy_to_mode_reg (mode0, op0);
8903 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8904 op1 = copy_to_mode_reg (mode1, op1);
8906 scratch = gen_reg_rtx (CCmode);
8908 pat = GEN_FCN (icode) (scratch, op0, op1);
8913 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8914 _lower_. We use one compare, but look in different bits of the
8915 CR for each variant.
8917 There are 2 elements in each SPE simd type (upper/lower). The CR
8918 bits are set as follows:
8920 BIT0 | BIT 1 | BIT 2 | BIT 3
8921 U | L | (U | L) | (U & L)
8923 So, for an "all" relationship, BIT 3 would be set.
8924 For an "any" relationship, BIT 2 would be set. Etc.
8926 Following traditional nomenclature, these bits map to:
8928 BIT0 | BIT 1 | BIT 2 | BIT 3
8931 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8936 /* All variant. OV bit. */
8938 /* We need to get to the OV bit, which is the ORDERED bit. We
8939 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8940 that's ugly and will make validate_condition_mode die.
8941 So let's just use another pattern. */
8942 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8944 /* Any variant. EQ bit. */
8948 /* Upper variant. LT bit. */
8952 /* Lower variant. GT bit. */
8957 error ("argument 1 of __builtin_spe_predicate is out of range");
8961 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8962 emit_move_insn (target, tmp);
8967 /* The evsel builtins look like this:
8969 e = __builtin_spe_evsel_OP (a, b, c, d);
8973 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8974 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8978 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8981 tree arg0 = CALL_EXPR_ARG (exp, 0);
8982 tree arg1 = CALL_EXPR_ARG (exp, 1);
8983 tree arg2 = CALL_EXPR_ARG (exp, 2);
8984 tree arg3 = CALL_EXPR_ARG (exp, 3);
8985 rtx op0 = expand_normal (arg0);
8986 rtx op1 = expand_normal (arg1);
8987 rtx op2 = expand_normal (arg2);
8988 rtx op3 = expand_normal (arg3);
8989 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8990 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8992 gcc_assert (mode0 == mode1);
8994 if (arg0 == error_mark_node || arg1 == error_mark_node
8995 || arg2 == error_mark_node || arg3 == error_mark_node)
8999 || GET_MODE (target) != mode0
9000 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
9001 target = gen_reg_rtx (mode0);
9003 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9004 op0 = copy_to_mode_reg (mode0, op0);
9005 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
9006 op1 = copy_to_mode_reg (mode0, op1);
9007 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
9008 op2 = copy_to_mode_reg (mode0, op2);
9009 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
9010 op3 = copy_to_mode_reg (mode0, op3);
9012 /* Generate the compare. */
9013 scratch = gen_reg_rtx (CCmode);
9014 pat = GEN_FCN (icode) (scratch, op0, op1);
9019 if (mode0 == V2SImode)
9020 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
9022 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
9027 /* Expand an expression EXP that calls a built-in function,
9028 with result going to TARGET if that's convenient
9029 (and in mode MODE if that's convenient).
9030 SUBTARGET may be used as the target for computing one of EXP's operands.
9031 IGNORE is nonzero if the value is to be ignored. */
9034 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9035 enum machine_mode mode ATTRIBUTE_UNUSED,
9036 int ignore ATTRIBUTE_UNUSED)
9038 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9039 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9040 const struct builtin_description *d;
9045 if (fcode == RS6000_BUILTIN_RECIP)
9046 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
9048 if (fcode == RS6000_BUILTIN_RECIPF)
9049 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
9051 if (fcode == RS6000_BUILTIN_RSQRTF)
9052 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
9054 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
9055 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
9057 int icode = (int) CODE_FOR_altivec_lvsr;
9058 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9059 enum machine_mode mode = insn_data[icode].operand[1].mode;
9063 gcc_assert (TARGET_ALTIVEC);
9065 arg = CALL_EXPR_ARG (exp, 0);
9066 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
9067 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
9068 addr = memory_address (mode, op);
9069 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
9073 /* For the load case need to negate the address. */
9074 op = gen_reg_rtx (GET_MODE (addr));
9075 emit_insn (gen_rtx_SET (VOIDmode, op,
9076 gen_rtx_NEG (GET_MODE (addr), addr)));
9078 op = gen_rtx_MEM (mode, op);
9081 || GET_MODE (target) != tmode
9082 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9083 target = gen_reg_rtx (tmode);
9085 /*pat = gen_altivec_lvsr (target, op);*/
9086 pat = GEN_FCN (icode) (target, op);
9094 /* FIXME: There's got to be a nicer way to handle this case than
9095 constructing a new CALL_EXPR. */
9096 if (fcode == ALTIVEC_BUILTIN_VCFUX
9097 || fcode == ALTIVEC_BUILTIN_VCFSX)
9099 if (call_expr_nargs (exp) == 1)
9100 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
9101 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
9106 ret = altivec_expand_builtin (exp, target, &success);
9113 ret = spe_expand_builtin (exp, target, &success);
9118 if (TARGET_PAIRED_FLOAT)
9120 ret = paired_expand_builtin (exp, target, &success);
9126 gcc_assert (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT);
9128 /* Handle simple unary operations. */
9129 d = (struct builtin_description *) bdesc_1arg;
9130 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9131 if (d->code == fcode)
9132 return rs6000_expand_unop_builtin (d->icode, exp, target);
9134 /* Handle simple binary operations. */
9135 d = (struct builtin_description *) bdesc_2arg;
9136 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9137 if (d->code == fcode)
9138 return rs6000_expand_binop_builtin (d->icode, exp, target);
9140 /* Handle simple ternary operations. */
9142 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9143 if (d->code == fcode)
9144 return rs6000_expand_ternop_builtin (d->icode, exp, target);
9150 build_opaque_vector_type (tree node, int nunits)
9152 node = copy_node (node);
9153 TYPE_MAIN_VARIANT (node) = node;
9154 TYPE_CANONICAL (node) = node;
9155 return build_vector_type (node, nunits);
9159 rs6000_init_builtins (void)
9161 V2SI_type_node = build_vector_type (intSI_type_node, 2);
9162 V2SF_type_node = build_vector_type (float_type_node, 2);
9163 V4HI_type_node = build_vector_type (intHI_type_node, 4);
9164 V4SI_type_node = build_vector_type (intSI_type_node, 4);
9165 V4SF_type_node = build_vector_type (float_type_node, 4);
9166 V8HI_type_node = build_vector_type (intHI_type_node, 8);
9167 V16QI_type_node = build_vector_type (intQI_type_node, 16);
9169 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
9170 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
9171 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
9173 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
9174 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
9175 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
9176 opaque_V4SI_type_node = copy_node (V4SI_type_node);
9178 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9179 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9180 'vector unsigned short'. */
9182 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
9183 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9184 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
9185 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9187 long_integer_type_internal_node = long_integer_type_node;
9188 long_unsigned_type_internal_node = long_unsigned_type_node;
9189 intQI_type_internal_node = intQI_type_node;
9190 uintQI_type_internal_node = unsigned_intQI_type_node;
9191 intHI_type_internal_node = intHI_type_node;
9192 uintHI_type_internal_node = unsigned_intHI_type_node;
9193 intSI_type_internal_node = intSI_type_node;
9194 uintSI_type_internal_node = unsigned_intSI_type_node;
9195 float_type_internal_node = float_type_node;
9196 void_type_internal_node = void_type_node;
9198 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9199 get_identifier ("__bool char"),
9200 bool_char_type_node));
9201 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9202 get_identifier ("__bool short"),
9203 bool_short_type_node));
9204 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9205 get_identifier ("__bool int"),
9206 bool_int_type_node));
9207 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9208 get_identifier ("__pixel"),
9211 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
9212 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
9213 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
9214 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
9216 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9217 get_identifier ("__vector unsigned char"),
9218 unsigned_V16QI_type_node));
9219 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9220 get_identifier ("__vector signed char"),
9222 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9223 get_identifier ("__vector __bool char"),
9224 bool_V16QI_type_node));
9226 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9227 get_identifier ("__vector unsigned short"),
9228 unsigned_V8HI_type_node));
9229 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9230 get_identifier ("__vector signed short"),
9232 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9233 get_identifier ("__vector __bool short"),
9234 bool_V8HI_type_node));
9236 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9237 get_identifier ("__vector unsigned int"),
9238 unsigned_V4SI_type_node));
9239 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9240 get_identifier ("__vector signed int"),
9242 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9243 get_identifier ("__vector __bool int"),
9244 bool_V4SI_type_node));
9246 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9247 get_identifier ("__vector float"),
9249 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9250 get_identifier ("__vector __pixel"),
9251 pixel_V8HI_type_node));
9253 if (TARGET_PAIRED_FLOAT)
9254 paired_init_builtins ();
9256 spe_init_builtins ();
9258 altivec_init_builtins ();
9259 if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT)
9260 rs6000_common_init_builtins ();
9261 if (TARGET_PPC_GFXOPT)
9263 tree ftype = build_function_type_list (float_type_node,
9267 def_builtin (MASK_PPC_GFXOPT, "__builtin_recipdivf", ftype,
9268 RS6000_BUILTIN_RECIPF);
9270 ftype = build_function_type_list (float_type_node,
9273 def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrtf", ftype,
9274 RS6000_BUILTIN_RSQRTF);
9278 tree ftype = build_function_type_list (double_type_node,
9282 def_builtin (MASK_POPCNTB, "__builtin_recipdiv", ftype,
9283 RS6000_BUILTIN_RECIP);
9288 /* AIX libm provides clog as __clog. */
9289 if (built_in_decls [BUILT_IN_CLOG])
9290 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
9293 #ifdef SUBTARGET_INIT_BUILTINS
9294 SUBTARGET_INIT_BUILTINS;
9298 /* Search through a set of builtins and enable the mask bits.
9299 DESC is an array of builtins.
9300 SIZE is the total number of builtins.
9301 START is the builtin enum at which to start.
9302 END is the builtin enum at which to end. */
9304 enable_mask_for_builtins (struct builtin_description *desc, int size,
9305 enum rs6000_builtins start,
9306 enum rs6000_builtins end)
9310 for (i = 0; i < size; ++i)
9311 if (desc[i].code == start)
9317 for (; i < size; ++i)
9319 /* Flip all the bits on. */
9320 desc[i].mask = target_flags;
9321 if (desc[i].code == end)
9327 spe_init_builtins (void)
9329 tree endlink = void_list_node;
9330 tree puint_type_node = build_pointer_type (unsigned_type_node);
9331 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
9332 struct builtin_description *d;
9335 tree v2si_ftype_4_v2si
9336 = build_function_type
9337 (opaque_V2SI_type_node,
9338 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9339 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9340 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9341 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9344 tree v2sf_ftype_4_v2sf
9345 = build_function_type
9346 (opaque_V2SF_type_node,
9347 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9348 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9349 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9350 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9353 tree int_ftype_int_v2si_v2si
9354 = build_function_type
9356 tree_cons (NULL_TREE, integer_type_node,
9357 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9358 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9361 tree int_ftype_int_v2sf_v2sf
9362 = build_function_type
9364 tree_cons (NULL_TREE, integer_type_node,
9365 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9366 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9369 tree void_ftype_v2si_puint_int
9370 = build_function_type (void_type_node,
9371 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9372 tree_cons (NULL_TREE, puint_type_node,
9373 tree_cons (NULL_TREE,
9377 tree void_ftype_v2si_puint_char
9378 = build_function_type (void_type_node,
9379 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9380 tree_cons (NULL_TREE, puint_type_node,
9381 tree_cons (NULL_TREE,
9385 tree void_ftype_v2si_pv2si_int
9386 = build_function_type (void_type_node,
9387 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9388 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9389 tree_cons (NULL_TREE,
9393 tree void_ftype_v2si_pv2si_char
9394 = build_function_type (void_type_node,
9395 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9396 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9397 tree_cons (NULL_TREE,
9402 = build_function_type (void_type_node,
9403 tree_cons (NULL_TREE, integer_type_node, endlink));
9406 = build_function_type (integer_type_node, endlink);
9408 tree v2si_ftype_pv2si_int
9409 = build_function_type (opaque_V2SI_type_node,
9410 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9411 tree_cons (NULL_TREE, integer_type_node,
9414 tree v2si_ftype_puint_int
9415 = build_function_type (opaque_V2SI_type_node,
9416 tree_cons (NULL_TREE, puint_type_node,
9417 tree_cons (NULL_TREE, integer_type_node,
9420 tree v2si_ftype_pushort_int
9421 = build_function_type (opaque_V2SI_type_node,
9422 tree_cons (NULL_TREE, pushort_type_node,
9423 tree_cons (NULL_TREE, integer_type_node,
9426 tree v2si_ftype_signed_char
9427 = build_function_type (opaque_V2SI_type_node,
9428 tree_cons (NULL_TREE, signed_char_type_node,
9431 /* The initialization of the simple binary and unary builtins is
9432 done in rs6000_common_init_builtins, but we have to enable the
9433 mask bits here manually because we have run out of `target_flags'
9434 bits. We really need to redesign this mask business. */
9436 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
9437 ARRAY_SIZE (bdesc_2arg),
9440 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
9441 ARRAY_SIZE (bdesc_1arg),
9443 SPE_BUILTIN_EVSUBFUSIAAW);
9444 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
9445 ARRAY_SIZE (bdesc_spe_predicates),
9446 SPE_BUILTIN_EVCMPEQ,
9447 SPE_BUILTIN_EVFSTSTLT);
9448 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
9449 ARRAY_SIZE (bdesc_spe_evsel),
9450 SPE_BUILTIN_EVSEL_CMPGTS,
9451 SPE_BUILTIN_EVSEL_FSTSTEQ);
9453 (*lang_hooks.decls.pushdecl)
9454 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
9455 opaque_V2SI_type_node));
9457 /* Initialize irregular SPE builtins. */
9459 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
9460 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
9461 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
9462 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
9463 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
9464 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
9465 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
9466 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
9467 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
9468 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
9469 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
9470 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
9471 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
9472 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
9473 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
9474 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
9475 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
9476 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
9479 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
9480 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
9481 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
9482 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
9483 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
9484 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
9485 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
9486 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
9487 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
9488 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
9489 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
9490 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
9491 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
9492 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
9493 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
9494 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
9495 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
9496 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
9497 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
9498 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
9499 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
9500 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
9503 d = (struct builtin_description *) bdesc_spe_predicates;
9504 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
9508 switch (insn_data[d->icode].operand[1].mode)
9511 type = int_ftype_int_v2si_v2si;
9514 type = int_ftype_int_v2sf_v2sf;
9520 def_builtin (d->mask, d->name, type, d->code);
9523 /* Evsel predicates. */
9524 d = (struct builtin_description *) bdesc_spe_evsel;
9525 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
9529 switch (insn_data[d->icode].operand[1].mode)
9532 type = v2si_ftype_4_v2si;
9535 type = v2sf_ftype_4_v2sf;
9541 def_builtin (d->mask, d->name, type, d->code);
9546 paired_init_builtins (void)
9548 const struct builtin_description *d;
9550 tree endlink = void_list_node;
9552 tree int_ftype_int_v2sf_v2sf
9553 = build_function_type
9555 tree_cons (NULL_TREE, integer_type_node,
9556 tree_cons (NULL_TREE, V2SF_type_node,
9557 tree_cons (NULL_TREE, V2SF_type_node,
9559 tree pcfloat_type_node =
9560 build_pointer_type (build_qualified_type
9561 (float_type_node, TYPE_QUAL_CONST));
9563 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
9564 long_integer_type_node,
9567 tree void_ftype_v2sf_long_pcfloat =
9568 build_function_type_list (void_type_node,
9570 long_integer_type_node,
9575 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat,
9579 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
9580 PAIRED_BUILTIN_STX);
9583 d = bdesc_paired_preds;
9584 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
9588 switch (insn_data[d->icode].operand[1].mode)
9591 type = int_ftype_int_v2sf_v2sf;
9597 def_builtin (d->mask, d->name, type, d->code);
9602 altivec_init_builtins (void)
9604 const struct builtin_description *d;
9605 const struct builtin_description_predicates *dp;
9609 tree pfloat_type_node = build_pointer_type (float_type_node);
9610 tree pint_type_node = build_pointer_type (integer_type_node);
9611 tree pshort_type_node = build_pointer_type (short_integer_type_node);
9612 tree pchar_type_node = build_pointer_type (char_type_node);
9614 tree pvoid_type_node = build_pointer_type (void_type_node);
9616 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
9617 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
9618 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
9619 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
9621 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
9623 tree int_ftype_opaque
9624 = build_function_type_list (integer_type_node,
9625 opaque_V4SI_type_node, NULL_TREE);
9627 tree opaque_ftype_opaque_int
9628 = build_function_type_list (opaque_V4SI_type_node,
9629 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
9630 tree opaque_ftype_opaque_opaque_int
9631 = build_function_type_list (opaque_V4SI_type_node,
9632 opaque_V4SI_type_node, opaque_V4SI_type_node,
9633 integer_type_node, NULL_TREE);
9634 tree int_ftype_int_opaque_opaque
9635 = build_function_type_list (integer_type_node,
9636 integer_type_node, opaque_V4SI_type_node,
9637 opaque_V4SI_type_node, NULL_TREE);
9638 tree int_ftype_int_v4si_v4si
9639 = build_function_type_list (integer_type_node,
9640 integer_type_node, V4SI_type_node,
9641 V4SI_type_node, NULL_TREE);
9642 tree v4sf_ftype_pcfloat
9643 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
9644 tree void_ftype_pfloat_v4sf
9645 = build_function_type_list (void_type_node,
9646 pfloat_type_node, V4SF_type_node, NULL_TREE);
9647 tree v4si_ftype_pcint
9648 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
9649 tree void_ftype_pint_v4si
9650 = build_function_type_list (void_type_node,
9651 pint_type_node, V4SI_type_node, NULL_TREE);
9652 tree v8hi_ftype_pcshort
9653 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
9654 tree void_ftype_pshort_v8hi
9655 = build_function_type_list (void_type_node,
9656 pshort_type_node, V8HI_type_node, NULL_TREE);
9657 tree v16qi_ftype_pcchar
9658 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
9659 tree void_ftype_pchar_v16qi
9660 = build_function_type_list (void_type_node,
9661 pchar_type_node, V16QI_type_node, NULL_TREE);
9662 tree void_ftype_v4si
9663 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
9664 tree v8hi_ftype_void
9665 = build_function_type (V8HI_type_node, void_list_node);
9666 tree void_ftype_void
9667 = build_function_type (void_type_node, void_list_node);
9669 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
9671 tree opaque_ftype_long_pcvoid
9672 = build_function_type_list (opaque_V4SI_type_node,
9673 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9674 tree v16qi_ftype_long_pcvoid
9675 = build_function_type_list (V16QI_type_node,
9676 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9677 tree v8hi_ftype_long_pcvoid
9678 = build_function_type_list (V8HI_type_node,
9679 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9680 tree v4si_ftype_long_pcvoid
9681 = build_function_type_list (V4SI_type_node,
9682 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9684 tree void_ftype_opaque_long_pvoid
9685 = build_function_type_list (void_type_node,
9686 opaque_V4SI_type_node, long_integer_type_node,
9687 pvoid_type_node, NULL_TREE);
9688 tree void_ftype_v4si_long_pvoid
9689 = build_function_type_list (void_type_node,
9690 V4SI_type_node, long_integer_type_node,
9691 pvoid_type_node, NULL_TREE);
9692 tree void_ftype_v16qi_long_pvoid
9693 = build_function_type_list (void_type_node,
9694 V16QI_type_node, long_integer_type_node,
9695 pvoid_type_node, NULL_TREE);
9696 tree void_ftype_v8hi_long_pvoid
9697 = build_function_type_list (void_type_node,
9698 V8HI_type_node, long_integer_type_node,
9699 pvoid_type_node, NULL_TREE);
9700 tree int_ftype_int_v8hi_v8hi
9701 = build_function_type_list (integer_type_node,
9702 integer_type_node, V8HI_type_node,
9703 V8HI_type_node, NULL_TREE);
9704 tree int_ftype_int_v16qi_v16qi
9705 = build_function_type_list (integer_type_node,
9706 integer_type_node, V16QI_type_node,
9707 V16QI_type_node, NULL_TREE);
9708 tree int_ftype_int_v4sf_v4sf
9709 = build_function_type_list (integer_type_node,
9710 integer_type_node, V4SF_type_node,
9711 V4SF_type_node, NULL_TREE);
9712 tree v4si_ftype_v4si
9713 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
9714 tree v8hi_ftype_v8hi
9715 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
9716 tree v16qi_ftype_v16qi
9717 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
9718 tree v4sf_ftype_v4sf
9719 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9720 tree void_ftype_pcvoid_int_int
9721 = build_function_type_list (void_type_node,
9722 pcvoid_type_node, integer_type_node,
9723 integer_type_node, NULL_TREE);
9725 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
9726 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
9727 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
9728 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
9729 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
9730 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
9731 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
9732 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
9733 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
9734 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
9735 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
9736 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
9737 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
9738 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
9739 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9740 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9741 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9742 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9743 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9744 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9745 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9746 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9747 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9748 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9749 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9750 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9751 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9752 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9753 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9754 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9755 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9756 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9757 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9758 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9759 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9760 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9761 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9762 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9763 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9764 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9765 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9766 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9767 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9768 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9769 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9770 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9772 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9774 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9775 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9776 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9777 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9778 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9779 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9780 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9781 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9782 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9783 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9785 /* Add the DST variants. */
9787 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9788 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9790 /* Initialize the predicates. */
9791 dp = bdesc_altivec_preds;
9792 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9794 enum machine_mode mode1;
9796 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9797 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9802 mode1 = insn_data[dp->icode].operand[1].mode;
9807 type = int_ftype_int_opaque_opaque;
9810 type = int_ftype_int_v4si_v4si;
9813 type = int_ftype_int_v8hi_v8hi;
9816 type = int_ftype_int_v16qi_v16qi;
9819 type = int_ftype_int_v4sf_v4sf;
9825 def_builtin (dp->mask, dp->name, type, dp->code);
9828 /* Initialize the abs* operators. */
9830 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9832 enum machine_mode mode0;
9835 mode0 = insn_data[d->icode].operand[0].mode;
9840 type = v4si_ftype_v4si;
9843 type = v8hi_ftype_v8hi;
9846 type = v16qi_ftype_v16qi;
9849 type = v4sf_ftype_v4sf;
9855 def_builtin (d->mask, d->name, type, d->code);
9862 /* Initialize target builtin that implements
9863 targetm.vectorize.builtin_mask_for_load. */
9865 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9866 v16qi_ftype_long_pcvoid,
9867 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9868 BUILT_IN_MD, NULL, NULL_TREE);
9869 TREE_READONLY (decl) = 1;
9870 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9871 altivec_builtin_mask_for_load = decl;
9874 /* Access to the vec_init patterns. */
9875 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9876 integer_type_node, integer_type_node,
9877 integer_type_node, NULL_TREE);
9878 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9879 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9881 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9882 short_integer_type_node,
9883 short_integer_type_node,
9884 short_integer_type_node,
9885 short_integer_type_node,
9886 short_integer_type_node,
9887 short_integer_type_node,
9888 short_integer_type_node, NULL_TREE);
9889 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9890 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9892 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9893 char_type_node, char_type_node,
9894 char_type_node, char_type_node,
9895 char_type_node, char_type_node,
9896 char_type_node, char_type_node,
9897 char_type_node, char_type_node,
9898 char_type_node, char_type_node,
9899 char_type_node, char_type_node,
9900 char_type_node, NULL_TREE);
9901 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9902 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9904 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9905 float_type_node, float_type_node,
9906 float_type_node, NULL_TREE);
9907 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9908 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9910 /* Access to the vec_set patterns. */
9911 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9913 integer_type_node, NULL_TREE);
9914 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9915 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9917 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9919 integer_type_node, NULL_TREE);
9920 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9921 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9923 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9925 integer_type_node, NULL_TREE);
9926 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9927 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9929 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9931 integer_type_node, NULL_TREE);
9932 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9933 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9935 /* Access to the vec_extract patterns. */
9936 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9937 integer_type_node, NULL_TREE);
9938 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9939 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9941 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9942 integer_type_node, NULL_TREE);
9943 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9944 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9946 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9947 integer_type_node, NULL_TREE);
9948 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9949 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9951 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9952 integer_type_node, NULL_TREE);
9953 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9954 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9958 rs6000_common_init_builtins (void)
9960 const struct builtin_description *d;
9963 tree v2sf_ftype_v2sf_v2sf_v2sf
9964 = build_function_type_list (V2SF_type_node,
9965 V2SF_type_node, V2SF_type_node,
9966 V2SF_type_node, NULL_TREE);
9968 tree v4sf_ftype_v4sf_v4sf_v16qi
9969 = build_function_type_list (V4SF_type_node,
9970 V4SF_type_node, V4SF_type_node,
9971 V16QI_type_node, NULL_TREE);
9972 tree v4si_ftype_v4si_v4si_v16qi
9973 = build_function_type_list (V4SI_type_node,
9974 V4SI_type_node, V4SI_type_node,
9975 V16QI_type_node, NULL_TREE);
9976 tree v8hi_ftype_v8hi_v8hi_v16qi
9977 = build_function_type_list (V8HI_type_node,
9978 V8HI_type_node, V8HI_type_node,
9979 V16QI_type_node, NULL_TREE);
9980 tree v16qi_ftype_v16qi_v16qi_v16qi
9981 = build_function_type_list (V16QI_type_node,
9982 V16QI_type_node, V16QI_type_node,
9983 V16QI_type_node, NULL_TREE);
9985 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9987 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9988 tree v16qi_ftype_int
9989 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9990 tree v8hi_ftype_v16qi
9991 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9992 tree v4sf_ftype_v4sf
9993 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9995 tree v2si_ftype_v2si_v2si
9996 = build_function_type_list (opaque_V2SI_type_node,
9997 opaque_V2SI_type_node,
9998 opaque_V2SI_type_node, NULL_TREE);
10000 tree v2sf_ftype_v2sf_v2sf_spe
10001 = build_function_type_list (opaque_V2SF_type_node,
10002 opaque_V2SF_type_node,
10003 opaque_V2SF_type_node, NULL_TREE);
10005 tree v2sf_ftype_v2sf_v2sf
10006 = build_function_type_list (V2SF_type_node,
10008 V2SF_type_node, NULL_TREE);
10011 tree v2si_ftype_int_int
10012 = build_function_type_list (opaque_V2SI_type_node,
10013 integer_type_node, integer_type_node,
10016 tree opaque_ftype_opaque
10017 = build_function_type_list (opaque_V4SI_type_node,
10018 opaque_V4SI_type_node, NULL_TREE);
10020 tree v2si_ftype_v2si
10021 = build_function_type_list (opaque_V2SI_type_node,
10022 opaque_V2SI_type_node, NULL_TREE);
10024 tree v2sf_ftype_v2sf_spe
10025 = build_function_type_list (opaque_V2SF_type_node,
10026 opaque_V2SF_type_node, NULL_TREE);
10028 tree v2sf_ftype_v2sf
10029 = build_function_type_list (V2SF_type_node,
10030 V2SF_type_node, NULL_TREE);
10032 tree v2sf_ftype_v2si
10033 = build_function_type_list (opaque_V2SF_type_node,
10034 opaque_V2SI_type_node, NULL_TREE);
10036 tree v2si_ftype_v2sf
10037 = build_function_type_list (opaque_V2SI_type_node,
10038 opaque_V2SF_type_node, NULL_TREE);
10040 tree v2si_ftype_v2si_char
10041 = build_function_type_list (opaque_V2SI_type_node,
10042 opaque_V2SI_type_node,
10043 char_type_node, NULL_TREE);
10045 tree v2si_ftype_int_char
10046 = build_function_type_list (opaque_V2SI_type_node,
10047 integer_type_node, char_type_node, NULL_TREE);
10049 tree v2si_ftype_char
10050 = build_function_type_list (opaque_V2SI_type_node,
10051 char_type_node, NULL_TREE);
10053 tree int_ftype_int_int
10054 = build_function_type_list (integer_type_node,
10055 integer_type_node, integer_type_node,
10058 tree opaque_ftype_opaque_opaque
10059 = build_function_type_list (opaque_V4SI_type_node,
10060 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
10061 tree v4si_ftype_v4si_v4si
10062 = build_function_type_list (V4SI_type_node,
10063 V4SI_type_node, V4SI_type_node, NULL_TREE);
10064 tree v4sf_ftype_v4si_int
10065 = build_function_type_list (V4SF_type_node,
10066 V4SI_type_node, integer_type_node, NULL_TREE);
10067 tree v4si_ftype_v4sf_int
10068 = build_function_type_list (V4SI_type_node,
10069 V4SF_type_node, integer_type_node, NULL_TREE);
10070 tree v4si_ftype_v4si_int
10071 = build_function_type_list (V4SI_type_node,
10072 V4SI_type_node, integer_type_node, NULL_TREE);
10073 tree v8hi_ftype_v8hi_int
10074 = build_function_type_list (V8HI_type_node,
10075 V8HI_type_node, integer_type_node, NULL_TREE);
10076 tree v16qi_ftype_v16qi_int
10077 = build_function_type_list (V16QI_type_node,
10078 V16QI_type_node, integer_type_node, NULL_TREE);
10079 tree v16qi_ftype_v16qi_v16qi_int
10080 = build_function_type_list (V16QI_type_node,
10081 V16QI_type_node, V16QI_type_node,
10082 integer_type_node, NULL_TREE);
10083 tree v8hi_ftype_v8hi_v8hi_int
10084 = build_function_type_list (V8HI_type_node,
10085 V8HI_type_node, V8HI_type_node,
10086 integer_type_node, NULL_TREE);
10087 tree v4si_ftype_v4si_v4si_int
10088 = build_function_type_list (V4SI_type_node,
10089 V4SI_type_node, V4SI_type_node,
10090 integer_type_node, NULL_TREE);
10091 tree v4sf_ftype_v4sf_v4sf_int
10092 = build_function_type_list (V4SF_type_node,
10093 V4SF_type_node, V4SF_type_node,
10094 integer_type_node, NULL_TREE);
10095 tree v4sf_ftype_v4sf_v4sf
10096 = build_function_type_list (V4SF_type_node,
10097 V4SF_type_node, V4SF_type_node, NULL_TREE);
10098 tree opaque_ftype_opaque_opaque_opaque
10099 = build_function_type_list (opaque_V4SI_type_node,
10100 opaque_V4SI_type_node, opaque_V4SI_type_node,
10101 opaque_V4SI_type_node, NULL_TREE);
10102 tree v4sf_ftype_v4sf_v4sf_v4si
10103 = build_function_type_list (V4SF_type_node,
10104 V4SF_type_node, V4SF_type_node,
10105 V4SI_type_node, NULL_TREE);
10106 tree v4sf_ftype_v4sf_v4sf_v4sf
10107 = build_function_type_list (V4SF_type_node,
10108 V4SF_type_node, V4SF_type_node,
10109 V4SF_type_node, NULL_TREE);
10110 tree v4si_ftype_v4si_v4si_v4si
10111 = build_function_type_list (V4SI_type_node,
10112 V4SI_type_node, V4SI_type_node,
10113 V4SI_type_node, NULL_TREE);
10114 tree v8hi_ftype_v8hi_v8hi
10115 = build_function_type_list (V8HI_type_node,
10116 V8HI_type_node, V8HI_type_node, NULL_TREE);
10117 tree v8hi_ftype_v8hi_v8hi_v8hi
10118 = build_function_type_list (V8HI_type_node,
10119 V8HI_type_node, V8HI_type_node,
10120 V8HI_type_node, NULL_TREE);
10121 tree v4si_ftype_v8hi_v8hi_v4si
10122 = build_function_type_list (V4SI_type_node,
10123 V8HI_type_node, V8HI_type_node,
10124 V4SI_type_node, NULL_TREE);
10125 tree v4si_ftype_v16qi_v16qi_v4si
10126 = build_function_type_list (V4SI_type_node,
10127 V16QI_type_node, V16QI_type_node,
10128 V4SI_type_node, NULL_TREE);
10129 tree v16qi_ftype_v16qi_v16qi
10130 = build_function_type_list (V16QI_type_node,
10131 V16QI_type_node, V16QI_type_node, NULL_TREE);
10132 tree v4si_ftype_v4sf_v4sf
10133 = build_function_type_list (V4SI_type_node,
10134 V4SF_type_node, V4SF_type_node, NULL_TREE);
10135 tree v8hi_ftype_v16qi_v16qi
10136 = build_function_type_list (V8HI_type_node,
10137 V16QI_type_node, V16QI_type_node, NULL_TREE);
10138 tree v4si_ftype_v8hi_v8hi
10139 = build_function_type_list (V4SI_type_node,
10140 V8HI_type_node, V8HI_type_node, NULL_TREE);
10141 tree v8hi_ftype_v4si_v4si
10142 = build_function_type_list (V8HI_type_node,
10143 V4SI_type_node, V4SI_type_node, NULL_TREE);
10144 tree v16qi_ftype_v8hi_v8hi
10145 = build_function_type_list (V16QI_type_node,
10146 V8HI_type_node, V8HI_type_node, NULL_TREE);
10147 tree v4si_ftype_v16qi_v4si
10148 = build_function_type_list (V4SI_type_node,
10149 V16QI_type_node, V4SI_type_node, NULL_TREE);
10150 tree v4si_ftype_v16qi_v16qi
10151 = build_function_type_list (V4SI_type_node,
10152 V16QI_type_node, V16QI_type_node, NULL_TREE);
10153 tree v4si_ftype_v8hi_v4si
10154 = build_function_type_list (V4SI_type_node,
10155 V8HI_type_node, V4SI_type_node, NULL_TREE);
10156 tree v4si_ftype_v8hi
10157 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
10158 tree int_ftype_v4si_v4si
10159 = build_function_type_list (integer_type_node,
10160 V4SI_type_node, V4SI_type_node, NULL_TREE);
10161 tree int_ftype_v4sf_v4sf
10162 = build_function_type_list (integer_type_node,
10163 V4SF_type_node, V4SF_type_node, NULL_TREE);
10164 tree int_ftype_v16qi_v16qi
10165 = build_function_type_list (integer_type_node,
10166 V16QI_type_node, V16QI_type_node, NULL_TREE);
10167 tree int_ftype_v8hi_v8hi
10168 = build_function_type_list (integer_type_node,
10169 V8HI_type_node, V8HI_type_node, NULL_TREE);
10171 /* Add the simple ternary operators. */
10173 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
10175 enum machine_mode mode0, mode1, mode2, mode3;
10177 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10178 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10189 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10192 mode0 = insn_data[d->icode].operand[0].mode;
10193 mode1 = insn_data[d->icode].operand[1].mode;
10194 mode2 = insn_data[d->icode].operand[2].mode;
10195 mode3 = insn_data[d->icode].operand[3].mode;
10198 /* When all four are of the same mode. */
10199 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
10204 type = opaque_ftype_opaque_opaque_opaque;
10207 type = v4si_ftype_v4si_v4si_v4si;
10210 type = v4sf_ftype_v4sf_v4sf_v4sf;
10213 type = v8hi_ftype_v8hi_v8hi_v8hi;
10216 type = v16qi_ftype_v16qi_v16qi_v16qi;
10219 type = v2sf_ftype_v2sf_v2sf_v2sf;
10222 gcc_unreachable ();
10225 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
10230 type = v4si_ftype_v4si_v4si_v16qi;
10233 type = v4sf_ftype_v4sf_v4sf_v16qi;
10236 type = v8hi_ftype_v8hi_v8hi_v16qi;
10239 type = v16qi_ftype_v16qi_v16qi_v16qi;
10242 gcc_unreachable ();
10245 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
10246 && mode3 == V4SImode)
10247 type = v4si_ftype_v16qi_v16qi_v4si;
10248 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
10249 && mode3 == V4SImode)
10250 type = v4si_ftype_v8hi_v8hi_v4si;
10251 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
10252 && mode3 == V4SImode)
10253 type = v4sf_ftype_v4sf_v4sf_v4si;
10255 /* vchar, vchar, vchar, 4-bit literal. */
10256 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
10257 && mode3 == QImode)
10258 type = v16qi_ftype_v16qi_v16qi_int;
10260 /* vshort, vshort, vshort, 4-bit literal. */
10261 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
10262 && mode3 == QImode)
10263 type = v8hi_ftype_v8hi_v8hi_int;
10265 /* vint, vint, vint, 4-bit literal. */
10266 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
10267 && mode3 == QImode)
10268 type = v4si_ftype_v4si_v4si_int;
10270 /* vfloat, vfloat, vfloat, 4-bit literal. */
10271 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
10272 && mode3 == QImode)
10273 type = v4sf_ftype_v4sf_v4sf_int;
10276 gcc_unreachable ();
10278 def_builtin (d->mask, d->name, type, d->code);
10281 /* Add the simple binary operators. */
10282 d = (struct builtin_description *) bdesc_2arg;
10283 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10285 enum machine_mode mode0, mode1, mode2;
10287 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10288 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10298 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10301 mode0 = insn_data[d->icode].operand[0].mode;
10302 mode1 = insn_data[d->icode].operand[1].mode;
10303 mode2 = insn_data[d->icode].operand[2].mode;
10306 /* When all three operands are of the same mode. */
10307 if (mode0 == mode1 && mode1 == mode2)
10312 type = opaque_ftype_opaque_opaque;
10315 type = v4sf_ftype_v4sf_v4sf;
10318 type = v4si_ftype_v4si_v4si;
10321 type = v16qi_ftype_v16qi_v16qi;
10324 type = v8hi_ftype_v8hi_v8hi;
10327 type = v2si_ftype_v2si_v2si;
10330 if (TARGET_PAIRED_FLOAT)
10331 type = v2sf_ftype_v2sf_v2sf;
10333 type = v2sf_ftype_v2sf_v2sf_spe;
10336 type = int_ftype_int_int;
10339 gcc_unreachable ();
10343 /* A few other combos we really don't want to do manually. */
10345 /* vint, vfloat, vfloat. */
10346 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
10347 type = v4si_ftype_v4sf_v4sf;
10349 /* vshort, vchar, vchar. */
10350 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
10351 type = v8hi_ftype_v16qi_v16qi;
10353 /* vint, vshort, vshort. */
10354 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
10355 type = v4si_ftype_v8hi_v8hi;
10357 /* vshort, vint, vint. */
10358 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
10359 type = v8hi_ftype_v4si_v4si;
10361 /* vchar, vshort, vshort. */
10362 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
10363 type = v16qi_ftype_v8hi_v8hi;
10365 /* vint, vchar, vint. */
10366 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
10367 type = v4si_ftype_v16qi_v4si;
10369 /* vint, vchar, vchar. */
10370 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
10371 type = v4si_ftype_v16qi_v16qi;
10373 /* vint, vshort, vint. */
10374 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
10375 type = v4si_ftype_v8hi_v4si;
10377 /* vint, vint, 5-bit literal. */
10378 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
10379 type = v4si_ftype_v4si_int;
10381 /* vshort, vshort, 5-bit literal. */
10382 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
10383 type = v8hi_ftype_v8hi_int;
10385 /* vchar, vchar, 5-bit literal. */
10386 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
10387 type = v16qi_ftype_v16qi_int;
10389 /* vfloat, vint, 5-bit literal. */
10390 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
10391 type = v4sf_ftype_v4si_int;
10393 /* vint, vfloat, 5-bit literal. */
10394 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
10395 type = v4si_ftype_v4sf_int;
10397 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
10398 type = v2si_ftype_int_int;
10400 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
10401 type = v2si_ftype_v2si_char;
10403 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
10404 type = v2si_ftype_int_char;
10409 gcc_assert (mode0 == SImode);
10413 type = int_ftype_v4si_v4si;
10416 type = int_ftype_v4sf_v4sf;
10419 type = int_ftype_v16qi_v16qi;
10422 type = int_ftype_v8hi_v8hi;
10425 gcc_unreachable ();
10429 def_builtin (d->mask, d->name, type, d->code);
10432 /* Add the simple unary operators. */
10433 d = (struct builtin_description *) bdesc_1arg;
10434 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10436 enum machine_mode mode0, mode1;
10438 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10439 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10448 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10451 mode0 = insn_data[d->icode].operand[0].mode;
10452 mode1 = insn_data[d->icode].operand[1].mode;
10455 if (mode0 == V4SImode && mode1 == QImode)
10456 type = v4si_ftype_int;
10457 else if (mode0 == V8HImode && mode1 == QImode)
10458 type = v8hi_ftype_int;
10459 else if (mode0 == V16QImode && mode1 == QImode)
10460 type = v16qi_ftype_int;
10461 else if (mode0 == VOIDmode && mode1 == VOIDmode)
10462 type = opaque_ftype_opaque;
10463 else if (mode0 == V4SFmode && mode1 == V4SFmode)
10464 type = v4sf_ftype_v4sf;
10465 else if (mode0 == V8HImode && mode1 == V16QImode)
10466 type = v8hi_ftype_v16qi;
10467 else if (mode0 == V4SImode && mode1 == V8HImode)
10468 type = v4si_ftype_v8hi;
10469 else if (mode0 == V2SImode && mode1 == V2SImode)
10470 type = v2si_ftype_v2si;
10471 else if (mode0 == V2SFmode && mode1 == V2SFmode)
10473 if (TARGET_PAIRED_FLOAT)
10474 type = v2sf_ftype_v2sf;
10476 type = v2sf_ftype_v2sf_spe;
10478 else if (mode0 == V2SFmode && mode1 == V2SImode)
10479 type = v2sf_ftype_v2si;
10480 else if (mode0 == V2SImode && mode1 == V2SFmode)
10481 type = v2si_ftype_v2sf;
10482 else if (mode0 == V2SImode && mode1 == QImode)
10483 type = v2si_ftype_char;
10485 gcc_unreachable ();
10487 def_builtin (d->mask, d->name, type, d->code);
10492 rs6000_init_libfuncs (void)
10494 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
10495 && !TARGET_POWER2 && !TARGET_POWERPC)
10497 /* AIX library routines for float->int conversion. */
10498 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
10499 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
10500 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
10501 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
10504 if (!TARGET_IEEEQUAD)
10505 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10506 if (!TARGET_XL_COMPAT)
10508 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
10509 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
10510 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
10511 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
10513 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
10515 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
10516 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
10517 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
10518 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
10519 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
10520 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
10521 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
10523 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
10524 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
10525 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
10526 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
10527 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
10528 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
10529 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
10530 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
10533 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
10534 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
10538 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
10539 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
10540 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
10541 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
10545 /* 32-bit SVR4 quad floating point routines. */
10547 set_optab_libfunc (add_optab, TFmode, "_q_add");
10548 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
10549 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
10550 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
10551 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
10552 if (TARGET_PPC_GPOPT || TARGET_POWER2)
10553 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
10555 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
10556 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
10557 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
10558 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
10559 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
10560 set_optab_libfunc (le_optab, TFmode, "_q_fle");
10562 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
10563 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
10564 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
10565 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
10566 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
10567 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
10568 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
10569 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
10574 /* Expand a block clear operation, and return 1 if successful. Return 0
10575 if we should let the compiler generate normal code.
10577 operands[0] is the destination
10578 operands[1] is the length
10579 operands[3] is the alignment */
10582 expand_block_clear (rtx operands[])
10584 rtx orig_dest = operands[0];
10585 rtx bytes_rtx = operands[1];
10586 rtx align_rtx = operands[3];
10587 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
10588 HOST_WIDE_INT align;
10589 HOST_WIDE_INT bytes;
10594 /* If this is not a fixed size move, just call memcpy */
10598 /* This must be a fixed size alignment */
10599 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10600 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10602 /* Anything to clear? */
10603 bytes = INTVAL (bytes_rtx);
10607 /* Use the builtin memset after a point, to avoid huge code bloat.
10608 When optimize_size, avoid any significant code bloat; calling
10609 memset is about 4 instructions, so allow for one instruction to
10610 load zero and three to do clearing. */
10611 if (TARGET_ALTIVEC && align >= 128)
10613 else if (TARGET_POWERPC64 && align >= 32)
10615 else if (TARGET_SPE && align >= 64)
10620 if (optimize_size && bytes > 3 * clear_step)
10622 if (! optimize_size && bytes > 8 * clear_step)
10625 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
10627 enum machine_mode mode = BLKmode;
10630 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
10635 else if (bytes >= 8 && TARGET_SPE && align >= 64)
10640 else if (bytes >= 8 && TARGET_POWERPC64
10641 /* 64-bit loads and stores require word-aligned
10643 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10648 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10649 { /* move 4 bytes */
10653 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10654 { /* move 2 bytes */
10658 else /* move 1 byte at a time */
10664 dest = adjust_address (orig_dest, mode, offset);
10666 emit_move_insn (dest, CONST0_RTX (mode));
10673 /* Expand a block move operation, and return 1 if successful. Return 0
10674 if we should let the compiler generate normal code.
10676 operands[0] is the destination
10677 operands[1] is the source
10678 operands[2] is the length
10679 operands[3] is the alignment */
10681 #define MAX_MOVE_REG 4
10684 expand_block_move (rtx operands[])
10686 rtx orig_dest = operands[0];
10687 rtx orig_src = operands[1];
10688 rtx bytes_rtx = operands[2];
10689 rtx align_rtx = operands[3];
10690 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
10695 rtx stores[MAX_MOVE_REG];
10698 /* If this is not a fixed size move, just call memcpy */
10702 /* This must be a fixed size alignment */
10703 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10704 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10706 /* Anything to move? */
10707 bytes = INTVAL (bytes_rtx);
10711 /* store_one_arg depends on expand_block_move to handle at least the size of
10712 reg_parm_stack_space. */
10713 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
10716 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
10719 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
10720 rtx (*mov) (rtx, rtx);
10722 enum machine_mode mode = BLKmode;
10725 /* Altivec first, since it will be faster than a string move
10726 when it applies, and usually not significantly larger. */
10727 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
10731 gen_func.mov = gen_movv4si;
10733 else if (TARGET_SPE && bytes >= 8 && align >= 64)
10737 gen_func.mov = gen_movv2si;
10739 else if (TARGET_STRING
10740 && bytes > 24 /* move up to 32 bytes at a time */
10746 && ! fixed_regs[10]
10747 && ! fixed_regs[11]
10748 && ! fixed_regs[12])
10750 move_bytes = (bytes > 32) ? 32 : bytes;
10751 gen_func.movmemsi = gen_movmemsi_8reg;
10753 else if (TARGET_STRING
10754 && bytes > 16 /* move up to 24 bytes at a time */
10760 && ! fixed_regs[10])
10762 move_bytes = (bytes > 24) ? 24 : bytes;
10763 gen_func.movmemsi = gen_movmemsi_6reg;
10765 else if (TARGET_STRING
10766 && bytes > 8 /* move up to 16 bytes at a time */
10770 && ! fixed_regs[8])
10772 move_bytes = (bytes > 16) ? 16 : bytes;
10773 gen_func.movmemsi = gen_movmemsi_4reg;
10775 else if (bytes >= 8 && TARGET_POWERPC64
10776 /* 64-bit loads and stores require word-aligned
10778 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10782 gen_func.mov = gen_movdi;
10784 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10785 { /* move up to 8 bytes at a time */
10786 move_bytes = (bytes > 8) ? 8 : bytes;
10787 gen_func.movmemsi = gen_movmemsi_2reg;
10789 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10790 { /* move 4 bytes */
10793 gen_func.mov = gen_movsi;
10795 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10796 { /* move 2 bytes */
10799 gen_func.mov = gen_movhi;
10801 else if (TARGET_STRING && bytes > 1)
10802 { /* move up to 4 bytes at a time */
10803 move_bytes = (bytes > 4) ? 4 : bytes;
10804 gen_func.movmemsi = gen_movmemsi_1reg;
10806 else /* move 1 byte at a time */
10810 gen_func.mov = gen_movqi;
10813 src = adjust_address (orig_src, mode, offset);
10814 dest = adjust_address (orig_dest, mode, offset);
10816 if (mode != BLKmode)
10818 rtx tmp_reg = gen_reg_rtx (mode);
10820 emit_insn ((*gen_func.mov) (tmp_reg, src));
10821 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10824 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10827 for (i = 0; i < num_reg; i++)
10828 emit_insn (stores[i]);
10832 if (mode == BLKmode)
10834 /* Move the address into scratch registers. The movmemsi
10835 patterns require zero offset. */
10836 if (!REG_P (XEXP (src, 0)))
10838 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10839 src = replace_equiv_address (src, src_reg);
10841 set_mem_size (src, GEN_INT (move_bytes));
10843 if (!REG_P (XEXP (dest, 0)))
10845 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10846 dest = replace_equiv_address (dest, dest_reg);
10848 set_mem_size (dest, GEN_INT (move_bytes));
10850 emit_insn ((*gen_func.movmemsi) (dest, src,
10851 GEN_INT (move_bytes & 31),
10860 /* Return a string to perform a load_multiple operation.
10861 operands[0] is the vector.
10862 operands[1] is the source address.
10863 operands[2] is the first destination register. */
10866 rs6000_output_load_multiple (rtx operands[3])
10868 /* We have to handle the case where the pseudo used to contain the address
10869 is assigned to one of the output registers. */
10871 int words = XVECLEN (operands[0], 0);
10874 if (XVECLEN (operands[0], 0) == 1)
10875 return "{l|lwz} %2,0(%1)";
10877 for (i = 0; i < words; i++)
10878 if (refers_to_regno_p (REGNO (operands[2]) + i,
10879 REGNO (operands[2]) + i + 1, operands[1], 0))
10883 xop[0] = GEN_INT (4 * (words-1));
10884 xop[1] = operands[1];
10885 xop[2] = operands[2];
10886 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10891 xop[0] = GEN_INT (4 * (words-1));
10892 xop[1] = operands[1];
10893 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10894 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10899 for (j = 0; j < words; j++)
10902 xop[0] = GEN_INT (j * 4);
10903 xop[1] = operands[1];
10904 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10905 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10907 xop[0] = GEN_INT (i * 4);
10908 xop[1] = operands[1];
10909 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10914 return "{lsi|lswi} %2,%1,%N0";
10918 /* A validation routine: say whether CODE, a condition code, and MODE
10919 match. The other alternatives either don't make sense or should
10920 never be generated. */
10923 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10925 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10926 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10927 && GET_MODE_CLASS (mode) == MODE_CC);
10929 /* These don't make sense. */
10930 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10931 || mode != CCUNSmode);
10933 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10934 || mode == CCUNSmode);
10936 gcc_assert (mode == CCFPmode
10937 || (code != ORDERED && code != UNORDERED
10938 && code != UNEQ && code != LTGT
10939 && code != UNGT && code != UNLT
10940 && code != UNGE && code != UNLE));
10942 /* These should never be generated except for
10943 flag_finite_math_only. */
10944 gcc_assert (mode != CCFPmode
10945 || flag_finite_math_only
10946 || (code != LE && code != GE
10947 && code != UNEQ && code != LTGT
10948 && code != UNGT && code != UNLT));
10950 /* These are invalid; the information is not there. */
10951 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10955 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10956 mask required to convert the result of a rotate insn into a shift
10957 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10960 includes_lshift_p (rtx shiftop, rtx andop)
10962 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10964 shift_mask <<= INTVAL (shiftop);
10966 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10969 /* Similar, but for right shift. */
10972 includes_rshift_p (rtx shiftop, rtx andop)
10974 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10976 shift_mask >>= INTVAL (shiftop);
10978 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10981 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10982 to perform a left shift. It must have exactly SHIFTOP least
10983 significant 0's, then one or more 1's, then zero or more 0's. */
10986 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10988 if (GET_CODE (andop) == CONST_INT)
10990 HOST_WIDE_INT c, lsb, shift_mask;
10992 c = INTVAL (andop);
10993 if (c == 0 || c == ~0)
10997 shift_mask <<= INTVAL (shiftop);
10999 /* Find the least significant one bit. */
11002 /* It must coincide with the LSB of the shift mask. */
11003 if (-lsb != shift_mask)
11006 /* Invert to look for the next transition (if any). */
11009 /* Remove the low group of ones (originally low group of zeros). */
11012 /* Again find the lsb, and check we have all 1's above. */
11016 else if (GET_CODE (andop) == CONST_DOUBLE
11017 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
11019 HOST_WIDE_INT low, high, lsb;
11020 HOST_WIDE_INT shift_mask_low, shift_mask_high;
11022 low = CONST_DOUBLE_LOW (andop);
11023 if (HOST_BITS_PER_WIDE_INT < 64)
11024 high = CONST_DOUBLE_HIGH (andop);
11026 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
11027 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
11030 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
11032 shift_mask_high = ~0;
11033 if (INTVAL (shiftop) > 32)
11034 shift_mask_high <<= INTVAL (shiftop) - 32;
11036 lsb = high & -high;
11038 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
11044 lsb = high & -high;
11045 return high == -lsb;
11048 shift_mask_low = ~0;
11049 shift_mask_low <<= INTVAL (shiftop);
11053 if (-lsb != shift_mask_low)
11056 if (HOST_BITS_PER_WIDE_INT < 64)
11061 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
11063 lsb = high & -high;
11064 return high == -lsb;
11068 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
11074 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
11075 to perform a left shift. It must have SHIFTOP or more least
11076 significant 0's, with the remainder of the word 1's. */
11079 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
11081 if (GET_CODE (andop) == CONST_INT)
11083 HOST_WIDE_INT c, lsb, shift_mask;
11086 shift_mask <<= INTVAL (shiftop);
11087 c = INTVAL (andop);
11089 /* Find the least significant one bit. */
11092 /* It must be covered by the shift mask.
11093 This test also rejects c == 0. */
11094 if ((lsb & shift_mask) == 0)
11097 /* Check we have all 1's above the transition, and reject all 1's. */
11098 return c == -lsb && lsb != 1;
11100 else if (GET_CODE (andop) == CONST_DOUBLE
11101 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
11103 HOST_WIDE_INT low, lsb, shift_mask_low;
11105 low = CONST_DOUBLE_LOW (andop);
11107 if (HOST_BITS_PER_WIDE_INT < 64)
11109 HOST_WIDE_INT high, shift_mask_high;
11111 high = CONST_DOUBLE_HIGH (andop);
11115 shift_mask_high = ~0;
11116 if (INTVAL (shiftop) > 32)
11117 shift_mask_high <<= INTVAL (shiftop) - 32;
11119 lsb = high & -high;
11121 if ((lsb & shift_mask_high) == 0)
11124 return high == -lsb;
11130 shift_mask_low = ~0;
11131 shift_mask_low <<= INTVAL (shiftop);
11135 if ((lsb & shift_mask_low) == 0)
11138 return low == -lsb && lsb != 1;
11144 /* Return 1 if operands will generate a valid arguments to rlwimi
11145 instruction for insert with right shift in 64-bit mode. The mask may
11146 not start on the first bit or stop on the last bit because wrap-around
11147 effects of instruction do not correspond to semantics of RTL insn. */
11150 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
11152 if (INTVAL (startop) > 32
11153 && INTVAL (startop) < 64
11154 && INTVAL (sizeop) > 1
11155 && INTVAL (sizeop) + INTVAL (startop) < 64
11156 && INTVAL (shiftop) > 0
11157 && INTVAL (sizeop) + INTVAL (shiftop) < 32
11158 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
11164 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11165 for lfq and stfq insns iff the registers are hard registers. */
11168 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
11170 /* We might have been passed a SUBREG. */
11171 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
11174 /* We might have been passed non floating point registers. */
11175 if (!FP_REGNO_P (REGNO (reg1))
11176 || !FP_REGNO_P (REGNO (reg2)))
11179 return (REGNO (reg1) == REGNO (reg2) - 1);
11182 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11183 addr1 and addr2 must be in consecutive memory locations
11184 (addr2 == addr1 + 8). */
11187 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
11190 unsigned int reg1, reg2;
11191 int offset1, offset2;
11193 /* The mems cannot be volatile. */
11194 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
11197 addr1 = XEXP (mem1, 0);
11198 addr2 = XEXP (mem2, 0);
11200 /* Extract an offset (if used) from the first addr. */
11201 if (GET_CODE (addr1) == PLUS)
11203 /* If not a REG, return zero. */
11204 if (GET_CODE (XEXP (addr1, 0)) != REG)
11208 reg1 = REGNO (XEXP (addr1, 0));
11209 /* The offset must be constant! */
11210 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
11212 offset1 = INTVAL (XEXP (addr1, 1));
11215 else if (GET_CODE (addr1) != REG)
11219 reg1 = REGNO (addr1);
11220 /* This was a simple (mem (reg)) expression. Offset is 0. */
11224 /* And now for the second addr. */
11225 if (GET_CODE (addr2) == PLUS)
11227 /* If not a REG, return zero. */
11228 if (GET_CODE (XEXP (addr2, 0)) != REG)
11232 reg2 = REGNO (XEXP (addr2, 0));
11233 /* The offset must be constant. */
11234 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
11236 offset2 = INTVAL (XEXP (addr2, 1));
11239 else if (GET_CODE (addr2) != REG)
11243 reg2 = REGNO (addr2);
11244 /* This was a simple (mem (reg)) expression. Offset is 0. */
11248 /* Both of these must have the same base register. */
11252 /* The offset for the second addr must be 8 more than the first addr. */
11253 if (offset2 != offset1 + 8)
11256 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11263 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
11265 static bool eliminated = false;
11266 if (mode != SDmode)
11267 return assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
11270 rtx mem = cfun->machine->sdmode_stack_slot;
11271 gcc_assert (mem != NULL_RTX);
11275 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
11276 cfun->machine->sdmode_stack_slot = mem;
11284 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
11286 /* Don't walk into types. */
11287 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
11289 *walk_subtrees = 0;
11293 switch (TREE_CODE (*tp))
11301 case ALIGN_INDIRECT_REF:
11302 case MISALIGNED_INDIRECT_REF:
11303 case VIEW_CONVERT_EXPR:
11304 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
11315 /* Allocate a 64-bit stack slot to be used for copying SDmode
11316 values through if this function has any SDmode references. */
11319 rs6000_alloc_sdmode_stack_slot (void)
11323 block_stmt_iterator bsi;
11325 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
11328 for (bsi = bsi_start (bb); !bsi_end_p (bsi); bsi_next (&bsi))
11330 tree ret = walk_tree_without_duplicates (bsi_stmt_ptr (bsi),
11331 rs6000_check_sdmode, NULL);
11334 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11335 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11341 /* Check for any SDmode parameters of the function. */
11342 for (t = DECL_ARGUMENTS (cfun->decl); t; t = TREE_CHAIN (t))
11344 if (TREE_TYPE (t) == error_mark_node)
11347 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
11348 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
11350 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11351 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11359 rs6000_instantiate_decls (void)
11361 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
11362 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
11365 /* Return the register class of a scratch register needed to copy IN into
11366 or out of a register in CLASS in MODE. If it can be done directly,
11367 NO_REGS is returned. */
11370 rs6000_secondary_reload_class (enum reg_class class,
11371 enum machine_mode mode ATTRIBUTE_UNUSED,
11376 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
11378 && MACHOPIC_INDIRECT
11382 /* We cannot copy a symbolic operand directly into anything
11383 other than BASE_REGS for TARGET_ELF. So indicate that a
11384 register from BASE_REGS is needed as an intermediate
11387 On Darwin, pic addresses require a load from memory, which
11388 needs a base register. */
11389 if (class != BASE_REGS
11390 && (GET_CODE (in) == SYMBOL_REF
11391 || GET_CODE (in) == HIGH
11392 || GET_CODE (in) == LABEL_REF
11393 || GET_CODE (in) == CONST))
11397 if (GET_CODE (in) == REG)
11399 regno = REGNO (in);
11400 if (regno >= FIRST_PSEUDO_REGISTER)
11402 regno = true_regnum (in);
11403 if (regno >= FIRST_PSEUDO_REGISTER)
11407 else if (GET_CODE (in) == SUBREG)
11409 regno = true_regnum (in);
11410 if (regno >= FIRST_PSEUDO_REGISTER)
11416 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11418 if (class == GENERAL_REGS || class == BASE_REGS
11419 || (regno >= 0 && INT_REGNO_P (regno)))
11422 /* Constants, memory, and FP registers can go into FP registers. */
11423 if ((regno == -1 || FP_REGNO_P (regno))
11424 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
11425 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
11427 /* Memory, and AltiVec registers can go into AltiVec registers. */
11428 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
11429 && class == ALTIVEC_REGS)
11432 /* We can copy among the CR registers. */
11433 if ((class == CR_REGS || class == CR0_REGS)
11434 && regno >= 0 && CR_REGNO_P (regno))
11437 /* Otherwise, we need GENERAL_REGS. */
11438 return GENERAL_REGS;
11441 /* Given a comparison operation, return the bit number in CCR to test. We
11442 know this is a valid comparison.
11444 SCC_P is 1 if this is for an scc. That means that %D will have been
11445 used instead of %C, so the bits will be in different places.
11447 Return -1 if OP isn't a valid comparison for some reason. */
11450 ccr_bit (rtx op, int scc_p)
11452 enum rtx_code code = GET_CODE (op);
11453 enum machine_mode cc_mode;
11458 if (!COMPARISON_P (op))
11461 reg = XEXP (op, 0);
11463 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
11465 cc_mode = GET_MODE (reg);
11466 cc_regnum = REGNO (reg);
11467 base_bit = 4 * (cc_regnum - CR0_REGNO);
11469 validate_condition_mode (code, cc_mode);
11471 /* When generating a sCOND operation, only positive conditions are
11474 || code == EQ || code == GT || code == LT || code == UNORDERED
11475 || code == GTU || code == LTU);
11480 return scc_p ? base_bit + 3 : base_bit + 2;
11482 return base_bit + 2;
11483 case GT: case GTU: case UNLE:
11484 return base_bit + 1;
11485 case LT: case LTU: case UNGE:
11487 case ORDERED: case UNORDERED:
11488 return base_bit + 3;
11491 /* If scc, we will have done a cror to put the bit in the
11492 unordered position. So test that bit. For integer, this is ! LT
11493 unless this is an scc insn. */
11494 return scc_p ? base_bit + 3 : base_bit;
11497 return scc_p ? base_bit + 3 : base_bit + 1;
11500 gcc_unreachable ();
11504 /* Return the GOT register. */
11507 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
11509 /* The second flow pass currently (June 1999) can't update
11510 regs_ever_live without disturbing other parts of the compiler, so
11511 update it here to make the prolog/epilogue code happy. */
11512 if (!can_create_pseudo_p ()
11513 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
11514 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
11516 crtl->uses_pic_offset_table = 1;
11518 return pic_offset_table_rtx;
11521 /* Function to init struct machine_function.
11522 This will be called, via a pointer variable,
11523 from push_function_context. */
11525 static struct machine_function *
11526 rs6000_init_machine_status (void)
11528 return ggc_alloc_cleared (sizeof (machine_function));
11531 /* These macros test for integers and extract the low-order bits. */
11533 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11534 && GET_MODE (X) == VOIDmode)
11536 #define INT_LOWPART(X) \
11537 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11540 extract_MB (rtx op)
11543 unsigned long val = INT_LOWPART (op);
11545 /* If the high bit is zero, the value is the first 1 bit we find
11547 if ((val & 0x80000000) == 0)
11549 gcc_assert (val & 0xffffffff);
11552 while (((val <<= 1) & 0x80000000) == 0)
11557 /* If the high bit is set and the low bit is not, or the mask is all
11558 1's, the value is zero. */
11559 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
11562 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11565 while (((val >>= 1) & 1) != 0)
11572 extract_ME (rtx op)
11575 unsigned long val = INT_LOWPART (op);
11577 /* If the low bit is zero, the value is the first 1 bit we find from
11579 if ((val & 1) == 0)
11581 gcc_assert (val & 0xffffffff);
11584 while (((val >>= 1) & 1) == 0)
11590 /* If the low bit is set and the high bit is not, or the mask is all
11591 1's, the value is 31. */
11592 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
11595 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11598 while (((val <<= 1) & 0x80000000) != 0)
11604 /* Locate some local-dynamic symbol still in use by this function
11605 so that we can print its name in some tls_ld pattern. */
11607 static const char *
11608 rs6000_get_some_local_dynamic_name (void)
11612 if (cfun->machine->some_ld_name)
11613 return cfun->machine->some_ld_name;
11615 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11617 && for_each_rtx (&PATTERN (insn),
11618 rs6000_get_some_local_dynamic_name_1, 0))
11619 return cfun->machine->some_ld_name;
11621 gcc_unreachable ();
11624 /* Helper function for rs6000_get_some_local_dynamic_name. */
11627 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11631 if (GET_CODE (x) == SYMBOL_REF)
11633 const char *str = XSTR (x, 0);
11634 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11636 cfun->machine->some_ld_name = str;
11644 /* Write out a function code label. */
11647 rs6000_output_function_entry (FILE *file, const char *fname)
11649 if (fname[0] != '.')
11651 switch (DEFAULT_ABI)
11654 gcc_unreachable ();
11660 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
11669 RS6000_OUTPUT_BASENAME (file, fname);
11671 assemble_name (file, fname);
11674 /* Print an operand. Recognize special options, documented below. */
11677 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11678 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11680 #define SMALL_DATA_RELOC "sda21"
11681 #define SMALL_DATA_REG 0
11685 print_operand (FILE *file, rtx x, int code)
11689 unsigned HOST_WIDE_INT uval;
11694 /* Write out an instruction after the call which may be replaced
11695 with glue code by the loader. This depends on the AIX version. */
11696 asm_fprintf (file, RS6000_CALL_GLUE);
11699 /* %a is output_address. */
11702 /* If X is a constant integer whose low-order 5 bits are zero,
11703 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11704 in the AIX assembler where "sri" with a zero shift count
11705 writes a trash instruction. */
11706 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
11713 /* If constant, low-order 16 bits of constant, unsigned.
11714 Otherwise, write normally. */
11716 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
11718 print_operand (file, x, 0);
11722 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11723 for 64-bit mask direction. */
11724 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
11727 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11731 /* X is a CR register. Print the number of the GT bit of the CR. */
11732 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11733 output_operand_lossage ("invalid %%E value");
11735 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
11739 /* Like 'J' but get to the GT bit only. */
11740 gcc_assert (GET_CODE (x) == REG);
11742 /* Bit 1 is GT bit. */
11743 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
11745 /* Add one for shift count in rlinm for scc. */
11746 fprintf (file, "%d", i + 1);
11750 /* X is a CR register. Print the number of the EQ bit of the CR */
11751 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11752 output_operand_lossage ("invalid %%E value");
11754 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
11758 /* X is a CR register. Print the shift count needed to move it
11759 to the high-order four bits. */
11760 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11761 output_operand_lossage ("invalid %%f value");
11763 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
11767 /* Similar, but print the count for the rotate in the opposite
11769 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11770 output_operand_lossage ("invalid %%F value");
11772 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
11776 /* X is a constant integer. If it is negative, print "m",
11777 otherwise print "z". This is to make an aze or ame insn. */
11778 if (GET_CODE (x) != CONST_INT)
11779 output_operand_lossage ("invalid %%G value");
11780 else if (INTVAL (x) >= 0)
11787 /* If constant, output low-order five bits. Otherwise, write
11790 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
11792 print_operand (file, x, 0);
11796 /* If constant, output low-order six bits. Otherwise, write
11799 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
11801 print_operand (file, x, 0);
11805 /* Print `i' if this is a constant, else nothing. */
11811 /* Write the bit number in CCR for jump. */
11812 i = ccr_bit (x, 0);
11814 output_operand_lossage ("invalid %%j code");
11816 fprintf (file, "%d", i);
11820 /* Similar, but add one for shift count in rlinm for scc and pass
11821 scc flag to `ccr_bit'. */
11822 i = ccr_bit (x, 1);
11824 output_operand_lossage ("invalid %%J code");
11826 /* If we want bit 31, write a shift count of zero, not 32. */
11827 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11831 /* X must be a constant. Write the 1's complement of the
11834 output_operand_lossage ("invalid %%k value");
11836 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
11840 /* X must be a symbolic constant on ELF. Write an
11841 expression suitable for an 'addi' that adds in the low 16
11842 bits of the MEM. */
11843 if (GET_CODE (x) != CONST)
11845 print_operand_address (file, x);
11846 fputs ("@l", file);
11850 if (GET_CODE (XEXP (x, 0)) != PLUS
11851 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
11852 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
11853 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
11854 output_operand_lossage ("invalid %%K value");
11855 print_operand_address (file, XEXP (XEXP (x, 0), 0));
11856 fputs ("@l", file);
11857 /* For GNU as, there must be a non-alphanumeric character
11858 between 'l' and the number. The '-' is added by
11859 print_operand() already. */
11860 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
11862 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
11866 /* %l is output_asm_label. */
11869 /* Write second word of DImode or DFmode reference. Works on register
11870 or non-indexed memory only. */
11871 if (GET_CODE (x) == REG)
11872 fputs (reg_names[REGNO (x) + 1], file);
11873 else if (GET_CODE (x) == MEM)
11875 /* Handle possible auto-increment. Since it is pre-increment and
11876 we have already done it, we can just use an offset of word. */
11877 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11878 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11879 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11881 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11882 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11885 output_address (XEXP (adjust_address_nv (x, SImode,
11889 if (small_data_operand (x, GET_MODE (x)))
11890 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11891 reg_names[SMALL_DATA_REG]);
11896 /* MB value for a mask operand. */
11897 if (! mask_operand (x, SImode))
11898 output_operand_lossage ("invalid %%m value");
11900 fprintf (file, "%d", extract_MB (x));
11904 /* ME value for a mask operand. */
11905 if (! mask_operand (x, SImode))
11906 output_operand_lossage ("invalid %%M value");
11908 fprintf (file, "%d", extract_ME (x));
11911 /* %n outputs the negative of its operand. */
11914 /* Write the number of elements in the vector times 4. */
11915 if (GET_CODE (x) != PARALLEL)
11916 output_operand_lossage ("invalid %%N value");
11918 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11922 /* Similar, but subtract 1 first. */
11923 if (GET_CODE (x) != PARALLEL)
11924 output_operand_lossage ("invalid %%O value");
11926 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11930 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11932 || INT_LOWPART (x) < 0
11933 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11934 output_operand_lossage ("invalid %%p value");
11936 fprintf (file, "%d", i);
11940 /* The operand must be an indirect memory reference. The result
11941 is the register name. */
11942 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11943 || REGNO (XEXP (x, 0)) >= 32)
11944 output_operand_lossage ("invalid %%P value");
11946 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11950 /* This outputs the logical code corresponding to a boolean
11951 expression. The expression may have one or both operands
11952 negated (if one, only the first one). For condition register
11953 logical operations, it will also treat the negated
11954 CR codes as NOTs, but not handle NOTs of them. */
11956 const char *const *t = 0;
11958 enum rtx_code code = GET_CODE (x);
11959 static const char * const tbl[3][3] = {
11960 { "and", "andc", "nor" },
11961 { "or", "orc", "nand" },
11962 { "xor", "eqv", "xor" } };
11966 else if (code == IOR)
11968 else if (code == XOR)
11971 output_operand_lossage ("invalid %%q value");
11973 if (GET_CODE (XEXP (x, 0)) != NOT)
11977 if (GET_CODE (XEXP (x, 1)) == NOT)
11995 /* X is a CR register. Print the mask for `mtcrf'. */
11996 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11997 output_operand_lossage ("invalid %%R value");
11999 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
12003 /* Low 5 bits of 32 - value */
12005 output_operand_lossage ("invalid %%s value");
12007 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
12011 /* PowerPC64 mask position. All 0's is excluded.
12012 CONST_INT 32-bit mask is considered sign-extended so any
12013 transition must occur within the CONST_INT, not on the boundary. */
12014 if (! mask64_operand (x, DImode))
12015 output_operand_lossage ("invalid %%S value");
12017 uval = INT_LOWPART (x);
12019 if (uval & 1) /* Clear Left */
12021 #if HOST_BITS_PER_WIDE_INT > 64
12022 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
12026 else /* Clear Right */
12029 #if HOST_BITS_PER_WIDE_INT > 64
12030 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
12036 gcc_assert (i >= 0);
12037 fprintf (file, "%d", i);
12041 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
12042 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
12044 /* Bit 3 is OV bit. */
12045 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
12047 /* If we want bit 31, write a shift count of zero, not 32. */
12048 fprintf (file, "%d", i == 31 ? 0 : i + 1);
12052 /* Print the symbolic name of a branch target register. */
12053 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
12054 && REGNO (x) != CTR_REGNO))
12055 output_operand_lossage ("invalid %%T value");
12056 else if (REGNO (x) == LR_REGNO)
12057 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
12059 fputs ("ctr", file);
12063 /* High-order 16 bits of constant for use in unsigned operand. */
12065 output_operand_lossage ("invalid %%u value");
12067 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
12068 (INT_LOWPART (x) >> 16) & 0xffff);
12072 /* High-order 16 bits of constant for use in signed operand. */
12074 output_operand_lossage ("invalid %%v value");
12076 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
12077 (INT_LOWPART (x) >> 16) & 0xffff);
12081 /* Print `u' if this has an auto-increment or auto-decrement. */
12082 if (GET_CODE (x) == MEM
12083 && (GET_CODE (XEXP (x, 0)) == PRE_INC
12084 || GET_CODE (XEXP (x, 0)) == PRE_DEC
12085 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
12090 /* Print the trap code for this operand. */
12091 switch (GET_CODE (x))
12094 fputs ("eq", file); /* 4 */
12097 fputs ("ne", file); /* 24 */
12100 fputs ("lt", file); /* 16 */
12103 fputs ("le", file); /* 20 */
12106 fputs ("gt", file); /* 8 */
12109 fputs ("ge", file); /* 12 */
12112 fputs ("llt", file); /* 2 */
12115 fputs ("lle", file); /* 6 */
12118 fputs ("lgt", file); /* 1 */
12121 fputs ("lge", file); /* 5 */
12124 gcc_unreachable ();
12129 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12132 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
12133 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
12135 print_operand (file, x, 0);
12139 /* MB value for a PowerPC64 rldic operand. */
12140 val = (GET_CODE (x) == CONST_INT
12141 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
12146 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
12147 if ((val <<= 1) < 0)
12150 #if HOST_BITS_PER_WIDE_INT == 32
12151 if (GET_CODE (x) == CONST_INT && i >= 0)
12152 i += 32; /* zero-extend high-part was all 0's */
12153 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
12155 val = CONST_DOUBLE_LOW (x);
12161 for ( ; i < 64; i++)
12162 if ((val <<= 1) < 0)
12167 fprintf (file, "%d", i + 1);
12171 if (GET_CODE (x) == MEM
12172 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
12173 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
12174 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
12179 /* Like 'L', for third word of TImode */
12180 if (GET_CODE (x) == REG)
12181 fputs (reg_names[REGNO (x) + 2], file);
12182 else if (GET_CODE (x) == MEM)
12184 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12185 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12186 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12187 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12188 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12190 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
12191 if (small_data_operand (x, GET_MODE (x)))
12192 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12193 reg_names[SMALL_DATA_REG]);
12198 /* X is a SYMBOL_REF. Write out the name preceded by a
12199 period and without any trailing data in brackets. Used for function
12200 names. If we are configured for System V (or the embedded ABI) on
12201 the PowerPC, do not emit the period, since those systems do not use
12202 TOCs and the like. */
12203 gcc_assert (GET_CODE (x) == SYMBOL_REF);
12205 /* Mark the decl as referenced so that cgraph will output the
12207 if (SYMBOL_REF_DECL (x))
12208 mark_decl_referenced (SYMBOL_REF_DECL (x));
12210 /* For macho, check to see if we need a stub. */
12213 const char *name = XSTR (x, 0);
12215 if (MACHOPIC_INDIRECT
12216 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
12217 name = machopic_indirection_name (x, /*stub_p=*/true);
12219 assemble_name (file, name);
12221 else if (!DOT_SYMBOLS)
12222 assemble_name (file, XSTR (x, 0));
12224 rs6000_output_function_entry (file, XSTR (x, 0));
12228 /* Like 'L', for last word of TImode. */
12229 if (GET_CODE (x) == REG)
12230 fputs (reg_names[REGNO (x) + 3], file);
12231 else if (GET_CODE (x) == MEM)
12233 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12234 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12235 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12236 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12237 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12239 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
12240 if (small_data_operand (x, GET_MODE (x)))
12241 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12242 reg_names[SMALL_DATA_REG]);
12246 /* Print AltiVec or SPE memory operand. */
12251 gcc_assert (GET_CODE (x) == MEM);
12255 /* Ugly hack because %y is overloaded. */
12256 if ((TARGET_SPE || TARGET_E500_DOUBLE)
12257 && (GET_MODE_SIZE (GET_MODE (x)) == 8
12258 || GET_MODE (x) == TFmode
12259 || GET_MODE (x) == TImode))
12261 /* Handle [reg]. */
12262 if (GET_CODE (tmp) == REG)
12264 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
12267 /* Handle [reg+UIMM]. */
12268 else if (GET_CODE (tmp) == PLUS &&
12269 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
12273 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
12275 x = INTVAL (XEXP (tmp, 1));
12276 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
12280 /* Fall through. Must be [reg+reg]. */
12283 && GET_CODE (tmp) == AND
12284 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
12285 && INTVAL (XEXP (tmp, 1)) == -16)
12286 tmp = XEXP (tmp, 0);
12287 if (GET_CODE (tmp) == REG)
12288 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
12291 gcc_assert (GET_CODE (tmp) == PLUS
12292 && REG_P (XEXP (tmp, 0))
12293 && REG_P (XEXP (tmp, 1)));
12295 if (REGNO (XEXP (tmp, 0)) == 0)
12296 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
12297 reg_names[ REGNO (XEXP (tmp, 0)) ]);
12299 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
12300 reg_names[ REGNO (XEXP (tmp, 1)) ]);
12306 if (GET_CODE (x) == REG)
12307 fprintf (file, "%s", reg_names[REGNO (x)]);
12308 else if (GET_CODE (x) == MEM)
12310 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12311 know the width from the mode. */
12312 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
12313 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
12314 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12315 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
12316 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
12317 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12318 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12319 output_address (XEXP (XEXP (x, 0), 1));
12321 output_address (XEXP (x, 0));
12324 output_addr_const (file, x);
12328 assemble_name (file, rs6000_get_some_local_dynamic_name ());
12332 output_operand_lossage ("invalid %%xn code");
12336 /* Print the address of an operand. */
12339 print_operand_address (FILE *file, rtx x)
12341 if (GET_CODE (x) == REG)
12342 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
12343 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
12344 || GET_CODE (x) == LABEL_REF)
12346 output_addr_const (file, x);
12347 if (small_data_operand (x, GET_MODE (x)))
12348 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12349 reg_names[SMALL_DATA_REG]);
12351 gcc_assert (!TARGET_TOC);
12353 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
12355 gcc_assert (REG_P (XEXP (x, 0)));
12356 if (REGNO (XEXP (x, 0)) == 0)
12357 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
12358 reg_names[ REGNO (XEXP (x, 0)) ]);
12360 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
12361 reg_names[ REGNO (XEXP (x, 1)) ]);
12363 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
12364 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
12365 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
12367 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12368 && CONSTANT_P (XEXP (x, 1)))
12370 output_addr_const (file, XEXP (x, 1));
12371 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12375 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12376 && CONSTANT_P (XEXP (x, 1)))
12378 fprintf (file, "lo16(");
12379 output_addr_const (file, XEXP (x, 1));
12380 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12383 else if (legitimate_constant_pool_address_p (x))
12385 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
12387 rtx contains_minus = XEXP (x, 1);
12391 /* Find the (minus (sym) (toc)) buried in X, and temporarily
12392 turn it into (sym) for output_addr_const. */
12393 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
12394 contains_minus = XEXP (contains_minus, 0);
12396 minus = XEXP (contains_minus, 0);
12397 symref = XEXP (minus, 0);
12398 gcc_assert (GET_CODE (XEXP (minus, 1)) == SYMBOL_REF);
12399 XEXP (contains_minus, 0) = symref;
12404 name = XSTR (symref, 0);
12405 newname = alloca (strlen (name) + sizeof ("@toc"));
12406 strcpy (newname, name);
12407 strcat (newname, "@toc");
12408 XSTR (symref, 0) = newname;
12410 output_addr_const (file, XEXP (x, 1));
12412 XSTR (symref, 0) = name;
12413 XEXP (contains_minus, 0) = minus;
12416 output_addr_const (file, XEXP (x, 1));
12418 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
12421 gcc_unreachable ();
12424 /* Target hook for assembling integer objects. The PowerPC version has
12425 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12426 is defined. It also needs to handle DI-mode objects on 64-bit
12430 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
12432 #ifdef RELOCATABLE_NEEDS_FIXUP
12433 /* Special handling for SI values. */
12434 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
12436 static int recurse = 0;
12438 /* For -mrelocatable, we mark all addresses that need to be fixed up
12439 in the .fixup section. */
12440 if (TARGET_RELOCATABLE
12441 && in_section != toc_section
12442 && in_section != text_section
12443 && !unlikely_text_section_p (in_section)
12445 && GET_CODE (x) != CONST_INT
12446 && GET_CODE (x) != CONST_DOUBLE
12452 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
12454 ASM_OUTPUT_LABEL (asm_out_file, buf);
12455 fprintf (asm_out_file, "\t.long\t(");
12456 output_addr_const (asm_out_file, x);
12457 fprintf (asm_out_file, ")@fixup\n");
12458 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
12459 ASM_OUTPUT_ALIGN (asm_out_file, 2);
12460 fprintf (asm_out_file, "\t.long\t");
12461 assemble_name (asm_out_file, buf);
12462 fprintf (asm_out_file, "\n\t.previous\n");
12466 /* Remove initial .'s to turn a -mcall-aixdesc function
12467 address into the address of the descriptor, not the function
12469 else if (GET_CODE (x) == SYMBOL_REF
12470 && XSTR (x, 0)[0] == '.'
12471 && DEFAULT_ABI == ABI_AIX)
12473 const char *name = XSTR (x, 0);
12474 while (*name == '.')
12477 fprintf (asm_out_file, "\t.long\t%s\n", name);
12481 #endif /* RELOCATABLE_NEEDS_FIXUP */
12482 return default_assemble_integer (x, size, aligned_p);
12485 #ifdef HAVE_GAS_HIDDEN
12486 /* Emit an assembler directive to set symbol visibility for DECL to
12487 VISIBILITY_TYPE. */
12490 rs6000_assemble_visibility (tree decl, int vis)
12492 /* Functions need to have their entry point symbol visibility set as
12493 well as their descriptor symbol visibility. */
12494 if (DEFAULT_ABI == ABI_AIX
12496 && TREE_CODE (decl) == FUNCTION_DECL)
12498 static const char * const visibility_types[] = {
12499 NULL, "internal", "hidden", "protected"
12502 const char *name, *type;
12504 name = ((* targetm.strip_name_encoding)
12505 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
12506 type = visibility_types[vis];
12508 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
12509 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
12512 default_assemble_visibility (decl, vis);
12517 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
12519 /* Reversal of FP compares takes care -- an ordered compare
12520 becomes an unordered compare and vice versa. */
12521 if (mode == CCFPmode
12522 && (!flag_finite_math_only
12523 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
12524 || code == UNEQ || code == LTGT))
12525 return reverse_condition_maybe_unordered (code);
12527 return reverse_condition (code);
12530 /* Generate a compare for CODE. Return a brand-new rtx that
12531 represents the result of the compare. */
12534 rs6000_generate_compare (enum rtx_code code)
12536 enum machine_mode comp_mode;
12537 rtx compare_result;
12539 if (rs6000_compare_fp_p)
12540 comp_mode = CCFPmode;
12541 else if (code == GTU || code == LTU
12542 || code == GEU || code == LEU)
12543 comp_mode = CCUNSmode;
12544 else if ((code == EQ || code == NE)
12545 && GET_CODE (rs6000_compare_op0) == SUBREG
12546 && GET_CODE (rs6000_compare_op1) == SUBREG
12547 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
12548 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
12549 /* These are unsigned values, perhaps there will be a later
12550 ordering compare that can be shared with this one.
12551 Unfortunately we cannot detect the signedness of the operands
12552 for non-subregs. */
12553 comp_mode = CCUNSmode;
12555 comp_mode = CCmode;
12557 /* First, the compare. */
12558 compare_result = gen_reg_rtx (comp_mode);
12560 /* E500 FP compare instructions on the GPRs. Yuck! */
12561 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
12562 && rs6000_compare_fp_p)
12564 rtx cmp, or_result, compare_result2;
12565 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
12567 if (op_mode == VOIDmode)
12568 op_mode = GET_MODE (rs6000_compare_op1);
12570 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12571 This explains the following mess. */
12575 case EQ: case UNEQ: case NE: case LTGT:
12579 cmp = flag_unsafe_math_optimizations
12580 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
12581 rs6000_compare_op1)
12582 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
12583 rs6000_compare_op1);
12587 cmp = flag_unsafe_math_optimizations
12588 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
12589 rs6000_compare_op1)
12590 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
12591 rs6000_compare_op1);
12595 cmp = flag_unsafe_math_optimizations
12596 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
12597 rs6000_compare_op1)
12598 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
12599 rs6000_compare_op1);
12603 gcc_unreachable ();
12607 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
12611 cmp = flag_unsafe_math_optimizations
12612 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
12613 rs6000_compare_op1)
12614 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
12615 rs6000_compare_op1);
12619 cmp = flag_unsafe_math_optimizations
12620 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
12621 rs6000_compare_op1)
12622 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
12623 rs6000_compare_op1);
12627 cmp = flag_unsafe_math_optimizations
12628 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
12629 rs6000_compare_op1)
12630 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
12631 rs6000_compare_op1);
12635 gcc_unreachable ();
12639 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
12643 cmp = flag_unsafe_math_optimizations
12644 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
12645 rs6000_compare_op1)
12646 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
12647 rs6000_compare_op1);
12651 cmp = flag_unsafe_math_optimizations
12652 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
12653 rs6000_compare_op1)
12654 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
12655 rs6000_compare_op1);
12659 cmp = flag_unsafe_math_optimizations
12660 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
12661 rs6000_compare_op1)
12662 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
12663 rs6000_compare_op1);
12667 gcc_unreachable ();
12671 gcc_unreachable ();
12674 /* Synthesize LE and GE from LT/GT || EQ. */
12675 if (code == LE || code == GE || code == LEU || code == GEU)
12681 case LE: code = LT; break;
12682 case GE: code = GT; break;
12683 case LEU: code = LT; break;
12684 case GEU: code = GT; break;
12685 default: gcc_unreachable ();
12688 compare_result2 = gen_reg_rtx (CCFPmode);
12694 cmp = flag_unsafe_math_optimizations
12695 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
12696 rs6000_compare_op1)
12697 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
12698 rs6000_compare_op1);
12702 cmp = flag_unsafe_math_optimizations
12703 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
12704 rs6000_compare_op1)
12705 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
12706 rs6000_compare_op1);
12710 cmp = flag_unsafe_math_optimizations
12711 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
12712 rs6000_compare_op1)
12713 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
12714 rs6000_compare_op1);
12718 gcc_unreachable ();
12722 /* OR them together. */
12723 or_result = gen_reg_rtx (CCFPmode);
12724 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
12726 compare_result = or_result;
12731 if (code == NE || code == LTGT)
12741 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12742 CLOBBERs to match cmptf_internal2 pattern. */
12743 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
12744 && GET_MODE (rs6000_compare_op0) == TFmode
12745 && !TARGET_IEEEQUAD
12746 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
12747 emit_insn (gen_rtx_PARALLEL (VOIDmode,
12749 gen_rtx_SET (VOIDmode,
12751 gen_rtx_COMPARE (comp_mode,
12752 rs6000_compare_op0,
12753 rs6000_compare_op1)),
12754 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12755 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12756 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12757 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12758 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12759 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12760 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12761 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
12762 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
12763 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
12765 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
12766 comp_mode = CCEQmode;
12767 compare_result = gen_reg_rtx (CCEQmode);
12769 emit_insn (gen_stack_protect_testdi (compare_result,
12770 rs6000_compare_op0, op1));
12772 emit_insn (gen_stack_protect_testsi (compare_result,
12773 rs6000_compare_op0, op1));
12776 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
12777 gen_rtx_COMPARE (comp_mode,
12778 rs6000_compare_op0,
12779 rs6000_compare_op1)));
12782 /* Some kinds of FP comparisons need an OR operation;
12783 under flag_finite_math_only we don't bother. */
12784 if (rs6000_compare_fp_p
12785 && !flag_finite_math_only
12786 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
12787 && (code == LE || code == GE
12788 || code == UNEQ || code == LTGT
12789 || code == UNGT || code == UNLT))
12791 enum rtx_code or1, or2;
12792 rtx or1_rtx, or2_rtx, compare2_rtx;
12793 rtx or_result = gen_reg_rtx (CCEQmode);
12797 case LE: or1 = LT; or2 = EQ; break;
12798 case GE: or1 = GT; or2 = EQ; break;
12799 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
12800 case LTGT: or1 = LT; or2 = GT; break;
12801 case UNGT: or1 = UNORDERED; or2 = GT; break;
12802 case UNLT: or1 = UNORDERED; or2 = LT; break;
12803 default: gcc_unreachable ();
12805 validate_condition_mode (or1, comp_mode);
12806 validate_condition_mode (or2, comp_mode);
12807 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
12808 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
12809 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
12810 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
12812 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
12814 compare_result = or_result;
12818 validate_condition_mode (code, GET_MODE (compare_result));
12820 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
12824 /* Emit the RTL for an sCOND pattern. */
12827 rs6000_emit_sCOND (enum rtx_code code, rtx result)
12830 enum machine_mode op_mode;
12831 enum rtx_code cond_code;
12833 condition_rtx = rs6000_generate_compare (code);
12834 cond_code = GET_CODE (condition_rtx);
12836 if (rs6000_compare_fp_p
12837 && !TARGET_FPRS && TARGET_HARD_FLOAT)
12841 PUT_MODE (condition_rtx, SImode);
12842 t = XEXP (condition_rtx, 0);
12844 gcc_assert (cond_code == NE || cond_code == EQ);
12846 if (cond_code == NE)
12847 emit_insn (gen_e500_flip_gt_bit (t, t));
12849 emit_insn (gen_move_from_CR_gt_bit (result, t));
12853 if (cond_code == NE
12854 || cond_code == GE || cond_code == LE
12855 || cond_code == GEU || cond_code == LEU
12856 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
12858 rtx not_result = gen_reg_rtx (CCEQmode);
12859 rtx not_op, rev_cond_rtx;
12860 enum machine_mode cc_mode;
12862 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
12864 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
12865 SImode, XEXP (condition_rtx, 0), const0_rtx);
12866 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
12867 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
12868 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
12871 op_mode = GET_MODE (rs6000_compare_op0);
12872 if (op_mode == VOIDmode)
12873 op_mode = GET_MODE (rs6000_compare_op1);
12875 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
12877 PUT_MODE (condition_rtx, DImode);
12878 convert_move (result, condition_rtx, 0);
12882 PUT_MODE (condition_rtx, SImode);
12883 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12887 /* Emit a branch of kind CODE to location LOC. */
12890 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12892 rtx condition_rtx, loc_ref;
12894 condition_rtx = rs6000_generate_compare (code);
12895 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12896 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12897 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12898 loc_ref, pc_rtx)));
12901 /* Return the string to output a conditional branch to LABEL, which is
12902 the operand number of the label, or -1 if the branch is really a
12903 conditional return.
12905 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12906 condition code register and its mode specifies what kind of
12907 comparison we made.
12909 REVERSED is nonzero if we should reverse the sense of the comparison.
12911 INSN is the insn. */
12914 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12916 static char string[64];
12917 enum rtx_code code = GET_CODE (op);
12918 rtx cc_reg = XEXP (op, 0);
12919 enum machine_mode mode = GET_MODE (cc_reg);
12920 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12921 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12922 int really_reversed = reversed ^ need_longbranch;
12928 validate_condition_mode (code, mode);
12930 /* Work out which way this really branches. We could use
12931 reverse_condition_maybe_unordered here always but this
12932 makes the resulting assembler clearer. */
12933 if (really_reversed)
12935 /* Reversal of FP compares takes care -- an ordered compare
12936 becomes an unordered compare and vice versa. */
12937 if (mode == CCFPmode)
12938 code = reverse_condition_maybe_unordered (code);
12940 code = reverse_condition (code);
12943 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12945 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12950 /* Opposite of GT. */
12959 gcc_unreachable ();
12965 /* Not all of these are actually distinct opcodes, but
12966 we distinguish them for clarity of the resulting assembler. */
12967 case NE: case LTGT:
12968 ccode = "ne"; break;
12969 case EQ: case UNEQ:
12970 ccode = "eq"; break;
12972 ccode = "ge"; break;
12973 case GT: case GTU: case UNGT:
12974 ccode = "gt"; break;
12976 ccode = "le"; break;
12977 case LT: case LTU: case UNLT:
12978 ccode = "lt"; break;
12979 case UNORDERED: ccode = "un"; break;
12980 case ORDERED: ccode = "nu"; break;
12981 case UNGE: ccode = "nl"; break;
12982 case UNLE: ccode = "ng"; break;
12984 gcc_unreachable ();
12987 /* Maybe we have a guess as to how likely the branch is.
12988 The old mnemonics don't have a way to specify this information. */
12990 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12991 if (note != NULL_RTX)
12993 /* PROB is the difference from 50%. */
12994 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12996 /* Only hint for highly probable/improbable branches on newer
12997 cpus as static prediction overrides processor dynamic
12998 prediction. For older cpus we may as well always hint, but
12999 assume not taken for branches that are very close to 50% as a
13000 mispredicted taken branch is more expensive than a
13001 mispredicted not-taken branch. */
13002 if (rs6000_always_hint
13003 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
13004 && br_prob_note_reliable_p (note)))
13006 if (abs (prob) > REG_BR_PROB_BASE / 20
13007 && ((prob > 0) ^ need_longbranch))
13015 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
13017 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
13019 /* We need to escape any '%' characters in the reg_names string.
13020 Assume they'd only be the first character.... */
13021 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
13023 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
13027 /* If the branch distance was too far, we may have to use an
13028 unconditional branch to go the distance. */
13029 if (need_longbranch)
13030 s += sprintf (s, ",$+8\n\tb %s", label);
13032 s += sprintf (s, ",%s", label);
13038 /* Return the string to flip the GT bit on a CR. */
13040 output_e500_flip_gt_bit (rtx dst, rtx src)
13042 static char string[64];
13045 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
13046 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
13049 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
13050 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
13052 sprintf (string, "crnot %d,%d", a, b);
13056 /* Return insn index for the vector compare instruction for given CODE,
13057 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
13061 get_vec_cmp_insn (enum rtx_code code,
13062 enum machine_mode dest_mode,
13063 enum machine_mode op_mode)
13065 if (!TARGET_ALTIVEC)
13066 return INSN_NOT_AVAILABLE;
13071 if (dest_mode == V16QImode && op_mode == V16QImode)
13072 return UNSPEC_VCMPEQUB;
13073 if (dest_mode == V8HImode && op_mode == V8HImode)
13074 return UNSPEC_VCMPEQUH;
13075 if (dest_mode == V4SImode && op_mode == V4SImode)
13076 return UNSPEC_VCMPEQUW;
13077 if (dest_mode == V4SImode && op_mode == V4SFmode)
13078 return UNSPEC_VCMPEQFP;
13081 if (dest_mode == V4SImode && op_mode == V4SFmode)
13082 return UNSPEC_VCMPGEFP;
13084 if (dest_mode == V16QImode && op_mode == V16QImode)
13085 return UNSPEC_VCMPGTSB;
13086 if (dest_mode == V8HImode && op_mode == V8HImode)
13087 return UNSPEC_VCMPGTSH;
13088 if (dest_mode == V4SImode && op_mode == V4SImode)
13089 return UNSPEC_VCMPGTSW;
13090 if (dest_mode == V4SImode && op_mode == V4SFmode)
13091 return UNSPEC_VCMPGTFP;
13094 if (dest_mode == V16QImode && op_mode == V16QImode)
13095 return UNSPEC_VCMPGTUB;
13096 if (dest_mode == V8HImode && op_mode == V8HImode)
13097 return UNSPEC_VCMPGTUH;
13098 if (dest_mode == V4SImode && op_mode == V4SImode)
13099 return UNSPEC_VCMPGTUW;
13104 return INSN_NOT_AVAILABLE;
13107 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
13108 DMODE is expected destination mode. This is a recursive function. */
13111 rs6000_emit_vector_compare (enum rtx_code rcode,
13113 enum machine_mode dmode)
13117 enum machine_mode dest_mode;
13118 enum machine_mode op_mode = GET_MODE (op1);
13120 gcc_assert (TARGET_ALTIVEC);
13121 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
13123 /* Floating point vector compare instructions uses destination V4SImode.
13124 Move destination to appropriate mode later. */
13125 if (dmode == V4SFmode)
13126 dest_mode = V4SImode;
13130 mask = gen_reg_rtx (dest_mode);
13131 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13133 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
13135 bool swap_operands = false;
13136 bool try_again = false;
13141 swap_operands = true;
13146 swap_operands = true;
13154 /* Invert condition and try again.
13155 e.g., A != B becomes ~(A==B). */
13157 enum rtx_code rev_code;
13158 enum insn_code nor_code;
13161 rev_code = reverse_condition_maybe_unordered (rcode);
13162 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
13165 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
13166 gcc_assert (nor_code != CODE_FOR_nothing);
13167 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
13169 if (dmode != dest_mode)
13171 rtx temp = gen_reg_rtx (dest_mode);
13172 convert_move (temp, mask, 0);
13182 /* Try GT/GTU/LT/LTU OR EQ */
13185 enum insn_code ior_code;
13186 enum rtx_code new_code;
13207 gcc_unreachable ();
13210 c_rtx = rs6000_emit_vector_compare (new_code,
13211 op0, op1, dest_mode);
13212 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
13215 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
13216 gcc_assert (ior_code != CODE_FOR_nothing);
13217 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
13218 if (dmode != dest_mode)
13220 rtx temp = gen_reg_rtx (dest_mode);
13221 convert_move (temp, mask, 0);
13228 gcc_unreachable ();
13233 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13234 /* You only get two chances. */
13235 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
13247 emit_insn (gen_rtx_SET (VOIDmode, mask,
13248 gen_rtx_UNSPEC (dest_mode,
13249 gen_rtvec (2, op0, op1),
13251 if (dmode != dest_mode)
13253 rtx temp = gen_reg_rtx (dest_mode);
13254 convert_move (temp, mask, 0);
13260 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13261 valid insn doesn exist for given mode. */
13264 get_vsel_insn (enum machine_mode mode)
13269 return UNSPEC_VSEL4SI;
13272 return UNSPEC_VSEL4SF;
13275 return UNSPEC_VSEL8HI;
13278 return UNSPEC_VSEL16QI;
13281 return INSN_NOT_AVAILABLE;
13284 return INSN_NOT_AVAILABLE;
13287 /* Emit vector select insn where DEST is destination using
13288 operands OP1, OP2 and MASK. */
13291 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
13294 enum machine_mode dest_mode = GET_MODE (dest);
13295 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
13297 temp = gen_reg_rtx (dest_mode);
13299 /* For each vector element, select op1 when mask is 1 otherwise
13301 t = gen_rtx_SET (VOIDmode, temp,
13302 gen_rtx_UNSPEC (dest_mode,
13303 gen_rtvec (3, op2, op1, mask),
13306 emit_move_insn (dest, temp);
13310 /* Emit vector conditional expression.
13311 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13312 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13315 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
13316 rtx cond, rtx cc_op0, rtx cc_op1)
13318 enum machine_mode dest_mode = GET_MODE (dest);
13319 enum rtx_code rcode = GET_CODE (cond);
13322 if (!TARGET_ALTIVEC)
13325 /* Get the vector mask for the given relational operations. */
13326 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
13328 rs6000_emit_vector_select (dest, op1, op2, mask);
13333 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13334 operands of the last comparison is nonzero/true, FALSE_COND if it
13335 is zero/false. Return 0 if the hardware has no such operation. */
13338 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13340 enum rtx_code code = GET_CODE (op);
13341 rtx op0 = rs6000_compare_op0;
13342 rtx op1 = rs6000_compare_op1;
13343 REAL_VALUE_TYPE c1;
13344 enum machine_mode compare_mode = GET_MODE (op0);
13345 enum machine_mode result_mode = GET_MODE (dest);
13347 bool is_against_zero;
13349 /* These modes should always match. */
13350 if (GET_MODE (op1) != compare_mode
13351 /* In the isel case however, we can use a compare immediate, so
13352 op1 may be a small constant. */
13353 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
13355 if (GET_MODE (true_cond) != result_mode)
13357 if (GET_MODE (false_cond) != result_mode)
13360 /* First, work out if the hardware can do this at all, or
13361 if it's too slow.... */
13362 if (! rs6000_compare_fp_p)
13365 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
13368 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
13369 && SCALAR_FLOAT_MODE_P (compare_mode))
13372 is_against_zero = op1 == CONST0_RTX (compare_mode);
13374 /* A floating-point subtract might overflow, underflow, or produce
13375 an inexact result, thus changing the floating-point flags, so it
13376 can't be generated if we care about that. It's safe if one side
13377 of the construct is zero, since then no subtract will be
13379 if (SCALAR_FLOAT_MODE_P (compare_mode)
13380 && flag_trapping_math && ! is_against_zero)
13383 /* Eliminate half of the comparisons by switching operands, this
13384 makes the remaining code simpler. */
13385 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
13386 || code == LTGT || code == LT || code == UNLE)
13388 code = reverse_condition_maybe_unordered (code);
13390 true_cond = false_cond;
13394 /* UNEQ and LTGT take four instructions for a comparison with zero,
13395 it'll probably be faster to use a branch here too. */
13396 if (code == UNEQ && HONOR_NANS (compare_mode))
13399 if (GET_CODE (op1) == CONST_DOUBLE)
13400 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
13402 /* We're going to try to implement comparisons by performing
13403 a subtract, then comparing against zero. Unfortunately,
13404 Inf - Inf is NaN which is not zero, and so if we don't
13405 know that the operand is finite and the comparison
13406 would treat EQ different to UNORDERED, we can't do it. */
13407 if (HONOR_INFINITIES (compare_mode)
13408 && code != GT && code != UNGE
13409 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
13410 /* Constructs of the form (a OP b ? a : b) are safe. */
13411 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
13412 || (! rtx_equal_p (op0, true_cond)
13413 && ! rtx_equal_p (op1, true_cond))))
13416 /* At this point we know we can use fsel. */
13418 /* Reduce the comparison to a comparison against zero. */
13419 if (! is_against_zero)
13421 temp = gen_reg_rtx (compare_mode);
13422 emit_insn (gen_rtx_SET (VOIDmode, temp,
13423 gen_rtx_MINUS (compare_mode, op0, op1)));
13425 op1 = CONST0_RTX (compare_mode);
13428 /* If we don't care about NaNs we can reduce some of the comparisons
13429 down to faster ones. */
13430 if (! HONOR_NANS (compare_mode))
13436 true_cond = false_cond;
13449 /* Now, reduce everything down to a GE. */
13456 temp = gen_reg_rtx (compare_mode);
13457 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13462 temp = gen_reg_rtx (compare_mode);
13463 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
13468 temp = gen_reg_rtx (compare_mode);
13469 emit_insn (gen_rtx_SET (VOIDmode, temp,
13470 gen_rtx_NEG (compare_mode,
13471 gen_rtx_ABS (compare_mode, op0))));
13476 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13477 temp = gen_reg_rtx (result_mode);
13478 emit_insn (gen_rtx_SET (VOIDmode, temp,
13479 gen_rtx_IF_THEN_ELSE (result_mode,
13480 gen_rtx_GE (VOIDmode,
13482 true_cond, false_cond)));
13483 false_cond = true_cond;
13486 temp = gen_reg_rtx (compare_mode);
13487 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13492 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13493 temp = gen_reg_rtx (result_mode);
13494 emit_insn (gen_rtx_SET (VOIDmode, temp,
13495 gen_rtx_IF_THEN_ELSE (result_mode,
13496 gen_rtx_GE (VOIDmode,
13498 true_cond, false_cond)));
13499 true_cond = false_cond;
13502 temp = gen_reg_rtx (compare_mode);
13503 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13508 gcc_unreachable ();
13511 emit_insn (gen_rtx_SET (VOIDmode, dest,
13512 gen_rtx_IF_THEN_ELSE (result_mode,
13513 gen_rtx_GE (VOIDmode,
13515 true_cond, false_cond)));
13519 /* Same as above, but for ints (isel). */
13522 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13524 rtx condition_rtx, cr;
13526 /* All isel implementations thus far are 32-bits. */
13527 if (GET_MODE (rs6000_compare_op0) != SImode)
13530 /* We still have to do the compare, because isel doesn't do a
13531 compare, it just looks at the CRx bits set by a previous compare
13533 condition_rtx = rs6000_generate_compare (GET_CODE (op));
13534 cr = XEXP (condition_rtx, 0);
13536 if (GET_MODE (cr) == CCmode)
13537 emit_insn (gen_isel_signed (dest, condition_rtx,
13538 true_cond, false_cond, cr));
13540 emit_insn (gen_isel_unsigned (dest, condition_rtx,
13541 true_cond, false_cond, cr));
13547 output_isel (rtx *operands)
13549 enum rtx_code code;
13551 code = GET_CODE (operands[1]);
13552 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
13554 PUT_CODE (operands[1], reverse_condition (code));
13555 return "isel %0,%3,%2,%j1";
13558 return "isel %0,%2,%3,%j1";
13562 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
13564 enum machine_mode mode = GET_MODE (op0);
13568 if (code == SMAX || code == SMIN)
13573 if (code == SMAX || code == UMAX)
13574 target = emit_conditional_move (dest, c, op0, op1, mode,
13575 op0, op1, mode, 0);
13577 target = emit_conditional_move (dest, c, op0, op1, mode,
13578 op1, op0, mode, 0);
13579 gcc_assert (target);
13580 if (target != dest)
13581 emit_move_insn (dest, target);
13584 /* Emit instructions to perform a load-reserved/store-conditional operation.
13585 The operation performed is an atomic
13586 (set M (CODE:MODE M OP))
13587 If not NULL, BEFORE is atomically set to M before the operation, and
13588 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13589 If SYNC_P then a memory barrier is emitted before the operation.
13590 Either OP or M may be wrapped in a NOT operation. */
13593 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
13594 rtx m, rtx op, rtx before_param, rtx after_param,
13597 enum machine_mode used_mode;
13598 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
13601 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13602 rtx shift = NULL_RTX;
13605 emit_insn (gen_memory_barrier ());
13607 if (GET_CODE (m) == NOT)
13608 used_m = XEXP (m, 0);
13612 /* If this is smaller than SImode, we'll have to use SImode with
13614 if (mode == QImode || mode == HImode)
13618 if (MEM_ALIGN (used_m) >= 32)
13621 if (BYTES_BIG_ENDIAN)
13622 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
13624 shift = GEN_INT (ishift);
13625 used_m = change_address (used_m, SImode, 0);
13629 rtx addrSI, aligned_addr;
13630 int shift_mask = mode == QImode ? 0x18 : 0x10;
13632 addrSI = gen_lowpart_common (SImode,
13633 force_reg (Pmode, XEXP (used_m, 0)));
13634 addrSI = force_reg (SImode, addrSI);
13635 shift = gen_reg_rtx (SImode);
13637 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13638 GEN_INT (shift_mask)));
13639 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13641 aligned_addr = expand_binop (Pmode, and_optab,
13643 GEN_INT (-4), NULL_RTX,
13644 1, OPTAB_LIB_WIDEN);
13645 used_m = change_address (used_m, SImode, aligned_addr);
13646 set_mem_align (used_m, 32);
13648 /* It's safe to keep the old alias set of USED_M, because
13649 the operation is atomic and only affects the original
13651 if (GET_CODE (m) == NOT)
13652 m = gen_rtx_NOT (SImode, used_m);
13656 if (GET_CODE (op) == NOT)
13658 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
13659 oldop = gen_rtx_NOT (SImode, oldop);
13662 oldop = lowpart_subreg (SImode, op, mode);
13668 newop = expand_binop (SImode, and_optab,
13669 oldop, GEN_INT (imask), NULL_RTX,
13670 1, OPTAB_LIB_WIDEN);
13671 emit_insn (gen_ashlsi3 (newop, newop, shift));
13675 newop = expand_binop (SImode, ior_optab,
13676 oldop, GEN_INT (~imask), NULL_RTX,
13677 1, OPTAB_LIB_WIDEN);
13678 emit_insn (gen_rotlsi3 (newop, newop, shift));
13686 newop = expand_binop (SImode, and_optab,
13687 oldop, GEN_INT (imask), NULL_RTX,
13688 1, OPTAB_LIB_WIDEN);
13689 emit_insn (gen_ashlsi3 (newop, newop, shift));
13691 mask = gen_reg_rtx (SImode);
13692 emit_move_insn (mask, GEN_INT (imask));
13693 emit_insn (gen_ashlsi3 (mask, mask, shift));
13696 newop = gen_rtx_PLUS (SImode, m, newop);
13698 newop = gen_rtx_MINUS (SImode, m, newop);
13699 newop = gen_rtx_AND (SImode, newop, mask);
13700 newop = gen_rtx_IOR (SImode, newop,
13701 gen_rtx_AND (SImode,
13702 gen_rtx_NOT (SImode, mask),
13708 gcc_unreachable ();
13711 if (GET_CODE (m) == NOT)
13715 mask = gen_reg_rtx (SImode);
13716 emit_move_insn (mask, GEN_INT (imask));
13717 emit_insn (gen_ashlsi3 (mask, mask, shift));
13719 xorm = gen_rtx_XOR (SImode, used_m, mask);
13720 /* Depending on the value of 'op', the XOR or the operation might
13721 be able to be simplified away. */
13722 newop = simplify_gen_binary (code, SImode, xorm, newop);
13725 used_mode = SImode;
13726 before = gen_reg_rtx (used_mode);
13727 after = gen_reg_rtx (used_mode);
13732 before = before_param;
13733 after = after_param;
13735 if (before == NULL_RTX)
13736 before = gen_reg_rtx (used_mode);
13737 if (after == NULL_RTX)
13738 after = gen_reg_rtx (used_mode);
13741 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
13742 && used_mode != mode)
13743 the_op = op; /* Computed above. */
13744 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
13745 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
13747 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
13749 set_after = gen_rtx_SET (VOIDmode, after, the_op);
13750 set_before = gen_rtx_SET (VOIDmode, before, used_m);
13751 set_atomic = gen_rtx_SET (VOIDmode, used_m,
13752 gen_rtx_UNSPEC (used_mode,
13753 gen_rtvec (1, the_op),
13755 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
13757 if ((code == PLUS || code == MINUS) && used_mode != mode)
13758 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
13759 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
13761 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
13762 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
13764 /* Shift and mask the return values properly. */
13765 if (used_mode != mode && before_param)
13767 emit_insn (gen_lshrsi3 (before, before, shift));
13768 convert_move (before_param, before, 1);
13771 if (used_mode != mode && after_param)
13773 emit_insn (gen_lshrsi3 (after, after, shift));
13774 convert_move (after_param, after, 1);
13777 /* The previous sequence will end with a branch that's dependent on
13778 the conditional store, so placing an isync will ensure that no
13779 other instructions (especially, no load or store instructions)
13780 can start before the atomic operation completes. */
13782 emit_insn (gen_isync ());
13785 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13786 COND is true. Mark the jump as unlikely to be taken. */
13789 emit_unlikely_jump (rtx cond, rtx label)
13791 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
13794 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
13795 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
13796 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
13799 /* A subroutine of the atomic operation splitters. Emit a load-locked
13800 instruction in MODE. */
13803 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
13805 rtx (*fn) (rtx, rtx) = NULL;
13806 if (mode == SImode)
13807 fn = gen_load_locked_si;
13808 else if (mode == DImode)
13809 fn = gen_load_locked_di;
13810 emit_insn (fn (reg, mem));
13813 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13814 instruction in MODE. */
13817 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
13819 rtx (*fn) (rtx, rtx, rtx) = NULL;
13820 if (mode == SImode)
13821 fn = gen_store_conditional_si;
13822 else if (mode == DImode)
13823 fn = gen_store_conditional_di;
13825 /* Emit sync before stwcx. to address PPC405 Erratum. */
13826 if (PPC405_ERRATUM77)
13827 emit_insn (gen_memory_barrier ());
13829 emit_insn (fn (res, mem, val));
13832 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13833 to perform. MEM is the memory on which to operate. VAL is the second
13834 operand of the binary operator. BEFORE and AFTER are optional locations to
13835 return the value of MEM either before of after the operation. SCRATCH is
13836 a scratch register. */
13839 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
13840 rtx before, rtx after, rtx scratch)
13842 enum machine_mode mode = GET_MODE (mem);
13843 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13845 emit_insn (gen_memory_barrier ());
13847 label = gen_label_rtx ();
13848 emit_label (label);
13849 label = gen_rtx_LABEL_REF (VOIDmode, label);
13851 if (before == NULL_RTX)
13853 emit_load_locked (mode, before, mem);
13856 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
13857 else if (code == AND)
13858 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
13860 x = gen_rtx_fmt_ee (code, mode, before, val);
13862 if (after != NULL_RTX)
13863 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
13864 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13866 emit_store_conditional (mode, cond, mem, scratch);
13868 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13869 emit_unlikely_jump (x, label);
13871 emit_insn (gen_isync ());
13874 /* Expand an atomic compare and swap operation. MEM is the memory on which
13875 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13876 value to be stored. SCRATCH is a scratch GPR. */
13879 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
13882 enum machine_mode mode = GET_MODE (mem);
13883 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13885 emit_insn (gen_memory_barrier ());
13887 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13888 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13889 emit_label (XEXP (label1, 0));
13891 emit_load_locked (mode, retval, mem);
13893 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13894 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13896 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13897 emit_unlikely_jump (x, label2);
13899 emit_move_insn (scratch, newval);
13900 emit_store_conditional (mode, cond, mem, scratch);
13902 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13903 emit_unlikely_jump (x, label1);
13905 emit_insn (gen_isync ());
13906 emit_label (XEXP (label2, 0));
13909 /* Expand an atomic test and set operation. MEM is the memory on which
13910 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13913 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13915 enum machine_mode mode = GET_MODE (mem);
13916 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13918 emit_insn (gen_memory_barrier ());
13920 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13921 emit_label (XEXP (label, 0));
13923 emit_load_locked (mode, retval, mem);
13924 emit_move_insn (scratch, val);
13925 emit_store_conditional (mode, cond, mem, scratch);
13927 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13928 emit_unlikely_jump (x, label);
13930 emit_insn (gen_isync ());
13934 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13936 enum machine_mode mode = GET_MODE (mem);
13937 rtx addrSI, align, wdst, shift, mask;
13938 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13939 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13941 /* Shift amount for subword relative to aligned word. */
13942 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13943 shift = gen_reg_rtx (SImode);
13944 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13945 GEN_INT (shift_mask)));
13946 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13948 /* Shift and mask old value into position within word. */
13949 oldval = convert_modes (SImode, mode, oldval, 1);
13950 oldval = expand_binop (SImode, and_optab,
13951 oldval, GEN_INT (imask), NULL_RTX,
13952 1, OPTAB_LIB_WIDEN);
13953 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13955 /* Shift and mask new value into position within word. */
13956 newval = convert_modes (SImode, mode, newval, 1);
13957 newval = expand_binop (SImode, and_optab,
13958 newval, GEN_INT (imask), NULL_RTX,
13959 1, OPTAB_LIB_WIDEN);
13960 emit_insn (gen_ashlsi3 (newval, newval, shift));
13962 /* Mask for insertion. */
13963 mask = gen_reg_rtx (SImode);
13964 emit_move_insn (mask, GEN_INT (imask));
13965 emit_insn (gen_ashlsi3 (mask, mask, shift));
13967 /* Address of aligned word containing subword. */
13968 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13969 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13970 mem = change_address (mem, SImode, align);
13971 set_mem_align (mem, 32);
13972 MEM_VOLATILE_P (mem) = 1;
13974 wdst = gen_reg_rtx (SImode);
13975 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13976 oldval, newval, mem));
13978 /* Shift the result back. */
13979 emit_insn (gen_lshrsi3 (wdst, wdst, shift));
13981 emit_move_insn (dst, gen_lowpart (mode, wdst));
13985 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13986 rtx oldval, rtx newval, rtx mem,
13989 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13991 emit_insn (gen_memory_barrier ());
13992 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13993 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13994 emit_label (XEXP (label1, 0));
13996 emit_load_locked (SImode, scratch, mem);
13998 /* Mask subword within loaded value for comparison with oldval.
13999 Use UNSPEC_AND to avoid clobber.*/
14000 emit_insn (gen_rtx_SET (SImode, dest,
14001 gen_rtx_UNSPEC (SImode,
14002 gen_rtvec (2, scratch, mask),
14005 x = gen_rtx_COMPARE (CCmode, dest, oldval);
14006 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
14008 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14009 emit_unlikely_jump (x, label2);
14011 /* Clear subword within loaded value for insertion of new value. */
14012 emit_insn (gen_rtx_SET (SImode, scratch,
14013 gen_rtx_AND (SImode,
14014 gen_rtx_NOT (SImode, mask), scratch)));
14015 emit_insn (gen_iorsi3 (scratch, scratch, newval));
14016 emit_store_conditional (SImode, cond, mem, scratch);
14018 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14019 emit_unlikely_jump (x, label1);
14021 emit_insn (gen_isync ());
14022 emit_label (XEXP (label2, 0));
14026 /* Emit instructions to move SRC to DST. Called by splitters for
14027 multi-register moves. It will emit at most one instruction for
14028 each register that is accessed; that is, it won't emit li/lis pairs
14029 (or equivalent for 64-bit code). One of SRC or DST must be a hard
14033 rs6000_split_multireg_move (rtx dst, rtx src)
14035 /* The register number of the first register being moved. */
14037 /* The mode that is to be moved. */
14038 enum machine_mode mode;
14039 /* The mode that the move is being done in, and its size. */
14040 enum machine_mode reg_mode;
14042 /* The number of registers that will be moved. */
14045 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
14046 mode = GET_MODE (dst);
14047 nregs = hard_regno_nregs[reg][mode];
14048 if (FP_REGNO_P (reg))
14049 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
14050 else if (ALTIVEC_REGNO_P (reg))
14051 reg_mode = V16QImode;
14052 else if (TARGET_E500_DOUBLE && mode == TFmode)
14055 reg_mode = word_mode;
14056 reg_mode_size = GET_MODE_SIZE (reg_mode);
14058 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
14060 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
14062 /* Move register range backwards, if we might have destructive
14065 for (i = nregs - 1; i >= 0; i--)
14066 emit_insn (gen_rtx_SET (VOIDmode,
14067 simplify_gen_subreg (reg_mode, dst, mode,
14068 i * reg_mode_size),
14069 simplify_gen_subreg (reg_mode, src, mode,
14070 i * reg_mode_size)));
14076 bool used_update = false;
14078 if (MEM_P (src) && INT_REGNO_P (reg))
14082 if (GET_CODE (XEXP (src, 0)) == PRE_INC
14083 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
14086 breg = XEXP (XEXP (src, 0), 0);
14087 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
14088 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
14089 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
14090 emit_insn (TARGET_32BIT
14091 ? gen_addsi3 (breg, breg, delta_rtx)
14092 : gen_adddi3 (breg, breg, delta_rtx));
14093 src = replace_equiv_address (src, breg);
14095 else if (! rs6000_offsettable_memref_p (src))
14098 basereg = gen_rtx_REG (Pmode, reg);
14099 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
14100 src = replace_equiv_address (src, basereg);
14103 breg = XEXP (src, 0);
14104 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
14105 breg = XEXP (breg, 0);
14107 /* If the base register we are using to address memory is
14108 also a destination reg, then change that register last. */
14110 && REGNO (breg) >= REGNO (dst)
14111 && REGNO (breg) < REGNO (dst) + nregs)
14112 j = REGNO (breg) - REGNO (dst);
14115 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
14119 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
14120 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
14123 breg = XEXP (XEXP (dst, 0), 0);
14124 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
14125 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
14126 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
14128 /* We have to update the breg before doing the store.
14129 Use store with update, if available. */
14133 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
14134 emit_insn (TARGET_32BIT
14135 ? (TARGET_POWERPC64
14136 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
14137 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
14138 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
14139 used_update = true;
14142 emit_insn (TARGET_32BIT
14143 ? gen_addsi3 (breg, breg, delta_rtx)
14144 : gen_adddi3 (breg, breg, delta_rtx));
14145 dst = replace_equiv_address (dst, breg);
14148 gcc_assert (rs6000_offsettable_memref_p (dst));
14151 for (i = 0; i < nregs; i++)
14153 /* Calculate index to next subword. */
14158 /* If compiler already emitted move of first word by
14159 store with update, no need to do anything. */
14160 if (j == 0 && used_update)
14163 emit_insn (gen_rtx_SET (VOIDmode,
14164 simplify_gen_subreg (reg_mode, dst, mode,
14165 j * reg_mode_size),
14166 simplify_gen_subreg (reg_mode, src, mode,
14167 j * reg_mode_size)));
14173 /* This page contains routines that are used to determine what the
14174 function prologue and epilogue code will do and write them out. */
14176 /* Return the first fixed-point register that is required to be
14177 saved. 32 if none. */
14180 first_reg_to_save (void)
14184 /* Find lowest numbered live register. */
14185 for (first_reg = 13; first_reg <= 31; first_reg++)
14186 if (df_regs_ever_live_p (first_reg)
14187 && (! call_used_regs[first_reg]
14188 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14189 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14190 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
14191 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
14196 && crtl->uses_pic_offset_table
14197 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
14198 return RS6000_PIC_OFFSET_TABLE_REGNUM;
14204 /* Similar, for FP regs. */
14207 first_fp_reg_to_save (void)
14211 /* Find lowest numbered live register. */
14212 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
14213 if (df_regs_ever_live_p (first_reg))
14219 /* Similar, for AltiVec regs. */
14222 first_altivec_reg_to_save (void)
14226 /* Stack frame remains as is unless we are in AltiVec ABI. */
14227 if (! TARGET_ALTIVEC_ABI)
14228 return LAST_ALTIVEC_REGNO + 1;
14230 /* On Darwin, the unwind routines are compiled without
14231 TARGET_ALTIVEC, and use save_world to save/restore the
14232 altivec registers when necessary. */
14233 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
14234 && ! TARGET_ALTIVEC)
14235 return FIRST_ALTIVEC_REGNO + 20;
14237 /* Find lowest numbered live register. */
14238 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
14239 if (df_regs_ever_live_p (i))
14245 /* Return a 32-bit mask of the AltiVec registers we need to set in
14246 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14247 the 32-bit word is 0. */
14249 static unsigned int
14250 compute_vrsave_mask (void)
14252 unsigned int i, mask = 0;
14254 /* On Darwin, the unwind routines are compiled without
14255 TARGET_ALTIVEC, and use save_world to save/restore the
14256 call-saved altivec registers when necessary. */
14257 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
14258 && ! TARGET_ALTIVEC)
14261 /* First, find out if we use _any_ altivec registers. */
14262 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14263 if (df_regs_ever_live_p (i))
14264 mask |= ALTIVEC_REG_BIT (i);
14269 /* Next, remove the argument registers from the set. These must
14270 be in the VRSAVE mask set by the caller, so we don't need to add
14271 them in again. More importantly, the mask we compute here is
14272 used to generate CLOBBERs in the set_vrsave insn, and we do not
14273 wish the argument registers to die. */
14274 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
14275 mask &= ~ALTIVEC_REG_BIT (i);
14277 /* Similarly, remove the return value from the set. */
14280 diddle_return_value (is_altivec_return_reg, &yes);
14282 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
14288 /* For a very restricted set of circumstances, we can cut down the
14289 size of prologues/epilogues by calling our own save/restore-the-world
14293 compute_save_world_info (rs6000_stack_t *info_ptr)
14295 info_ptr->world_save_p = 1;
14296 info_ptr->world_save_p
14297 = (WORLD_SAVE_P (info_ptr)
14298 && DEFAULT_ABI == ABI_DARWIN
14299 && ! (cfun->calls_setjmp && flag_exceptions)
14300 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
14301 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
14302 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
14303 && info_ptr->cr_save_p);
14305 /* This will not work in conjunction with sibcalls. Make sure there
14306 are none. (This check is expensive, but seldom executed.) */
14307 if (WORLD_SAVE_P (info_ptr))
14310 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
14311 if ( GET_CODE (insn) == CALL_INSN
14312 && SIBLING_CALL_P (insn))
14314 info_ptr->world_save_p = 0;
14319 if (WORLD_SAVE_P (info_ptr))
14321 /* Even if we're not touching VRsave, make sure there's room on the
14322 stack for it, if it looks like we're calling SAVE_WORLD, which
14323 will attempt to save it. */
14324 info_ptr->vrsave_size = 4;
14326 /* If we are going to save the world, we need to save the link register too. */
14327 info_ptr->lr_save_p = 1;
14329 /* "Save" the VRsave register too if we're saving the world. */
14330 if (info_ptr->vrsave_mask == 0)
14331 info_ptr->vrsave_mask = compute_vrsave_mask ();
14333 /* Because the Darwin register save/restore routines only handle
14334 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14336 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
14337 && (info_ptr->first_altivec_reg_save
14338 >= FIRST_SAVED_ALTIVEC_REGNO));
14345 is_altivec_return_reg (rtx reg, void *xyes)
14347 bool *yes = (bool *) xyes;
14348 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
14353 /* Calculate the stack information for the current function. This is
14354 complicated by having two separate calling sequences, the AIX calling
14355 sequence and the V.4 calling sequence.
14357 AIX (and Darwin/Mac OS X) stack frames look like:
14359 SP----> +---------------------------------------+
14360 | back chain to caller | 0 0
14361 +---------------------------------------+
14362 | saved CR | 4 8 (8-11)
14363 +---------------------------------------+
14365 +---------------------------------------+
14366 | reserved for compilers | 12 24
14367 +---------------------------------------+
14368 | reserved for binders | 16 32
14369 +---------------------------------------+
14370 | saved TOC pointer | 20 40
14371 +---------------------------------------+
14372 | Parameter save area (P) | 24 48
14373 +---------------------------------------+
14374 | Alloca space (A) | 24+P etc.
14375 +---------------------------------------+
14376 | Local variable space (L) | 24+P+A
14377 +---------------------------------------+
14378 | Float/int conversion temporary (X) | 24+P+A+L
14379 +---------------------------------------+
14380 | Save area for AltiVec registers (W) | 24+P+A+L+X
14381 +---------------------------------------+
14382 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14383 +---------------------------------------+
14384 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14385 +---------------------------------------+
14386 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14387 +---------------------------------------+
14388 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14389 +---------------------------------------+
14390 old SP->| back chain to caller's caller |
14391 +---------------------------------------+
14393 The required alignment for AIX configurations is two words (i.e., 8
14397 V.4 stack frames look like:
14399 SP----> +---------------------------------------+
14400 | back chain to caller | 0
14401 +---------------------------------------+
14402 | caller's saved LR | 4
14403 +---------------------------------------+
14404 | Parameter save area (P) | 8
14405 +---------------------------------------+
14406 | Alloca space (A) | 8+P
14407 +---------------------------------------+
14408 | Varargs save area (V) | 8+P+A
14409 +---------------------------------------+
14410 | Local variable space (L) | 8+P+A+V
14411 +---------------------------------------+
14412 | Float/int conversion temporary (X) | 8+P+A+V+L
14413 +---------------------------------------+
14414 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14415 +---------------------------------------+
14416 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14417 +---------------------------------------+
14418 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14419 +---------------------------------------+
14420 | SPE: area for 64-bit GP registers |
14421 +---------------------------------------+
14422 | SPE alignment padding |
14423 +---------------------------------------+
14424 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14425 +---------------------------------------+
14426 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14427 +---------------------------------------+
14428 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14429 +---------------------------------------+
14430 old SP->| back chain to caller's caller |
14431 +---------------------------------------+
14433 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14434 given. (But note below and in sysv4.h that we require only 8 and
14435 may round up the size of our stack frame anyways. The historical
14436 reason is early versions of powerpc-linux which didn't properly
14437 align the stack at program startup. A happy side-effect is that
14438 -mno-eabi libraries can be used with -meabi programs.)
14440 The EABI configuration defaults to the V.4 layout. However,
14441 the stack alignment requirements may differ. If -mno-eabi is not
14442 given, the required stack alignment is 8 bytes; if -mno-eabi is
14443 given, the required alignment is 16 bytes. (But see V.4 comment
14446 #ifndef ABI_STACK_BOUNDARY
14447 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14450 static rs6000_stack_t *
14451 rs6000_stack_info (void)
14453 static rs6000_stack_t info;
14454 rs6000_stack_t *info_ptr = &info;
14455 int reg_size = TARGET_32BIT ? 4 : 8;
14459 HOST_WIDE_INT non_fixed_size;
14461 memset (&info, 0, sizeof (info));
14465 /* Cache value so we don't rescan instruction chain over and over. */
14466 if (cfun->machine->insn_chain_scanned_p == 0)
14467 cfun->machine->insn_chain_scanned_p
14468 = spe_func_has_64bit_regs_p () + 1;
14469 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
14472 /* Select which calling sequence. */
14473 info_ptr->abi = DEFAULT_ABI;
14475 /* Calculate which registers need to be saved & save area size. */
14476 info_ptr->first_gp_reg_save = first_reg_to_save ();
14477 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14478 even if it currently looks like we won't. Reload may need it to
14479 get at a constant; if so, it will have already created a constant
14480 pool entry for it. */
14481 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
14482 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
14483 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
14484 && crtl->uses_const_pool
14485 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
14486 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
14488 first_gp = info_ptr->first_gp_reg_save;
14490 info_ptr->gp_size = reg_size * (32 - first_gp);
14492 /* For the SPE, we have an additional upper 32-bits on each GPR.
14493 Ideally we should save the entire 64-bits only when the upper
14494 half is used in SIMD instructions. Since we only record
14495 registers live (not the size they are used in), this proves
14496 difficult because we'd have to traverse the instruction chain at
14497 the right time, taking reload into account. This is a real pain,
14498 so we opt to save the GPRs in 64-bits always if but one register
14499 gets used in 64-bits. Otherwise, all the registers in the frame
14500 get saved in 32-bits.
14502 So... since when we save all GPRs (except the SP) in 64-bits, the
14503 traditional GP save area will be empty. */
14504 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14505 info_ptr->gp_size = 0;
14507 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
14508 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
14510 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
14511 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
14512 - info_ptr->first_altivec_reg_save);
14514 /* Does this function call anything? */
14515 info_ptr->calls_p = (! current_function_is_leaf
14516 || cfun->machine->ra_needs_full_frame);
14518 /* Determine if we need to save the link register. */
14519 if ((DEFAULT_ABI == ABI_AIX
14521 && !TARGET_PROFILE_KERNEL)
14522 #ifdef TARGET_RELOCATABLE
14523 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
14525 || (info_ptr->first_fp_reg_save != 64
14526 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
14527 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
14528 || info_ptr->calls_p
14529 || rs6000_ra_ever_killed ())
14531 info_ptr->lr_save_p = 1;
14532 df_set_regs_ever_live (LR_REGNO, true);
14535 /* Determine if we need to save the condition code registers. */
14536 if (df_regs_ever_live_p (CR2_REGNO)
14537 || df_regs_ever_live_p (CR3_REGNO)
14538 || df_regs_ever_live_p (CR4_REGNO))
14540 info_ptr->cr_save_p = 1;
14541 if (DEFAULT_ABI == ABI_V4)
14542 info_ptr->cr_size = reg_size;
14545 /* If the current function calls __builtin_eh_return, then we need
14546 to allocate stack space for registers that will hold data for
14547 the exception handler. */
14548 if (crtl->calls_eh_return)
14551 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
14554 /* SPE saves EH registers in 64-bits. */
14555 ehrd_size = i * (TARGET_SPE_ABI
14556 && info_ptr->spe_64bit_regs_used != 0
14557 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
14562 /* Determine various sizes. */
14563 info_ptr->reg_size = reg_size;
14564 info_ptr->fixed_size = RS6000_SAVE_AREA;
14565 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
14566 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
14567 TARGET_ALTIVEC ? 16 : 8);
14568 if (FRAME_GROWS_DOWNWARD)
14569 info_ptr->vars_size
14570 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
14571 + info_ptr->parm_size,
14572 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
14573 - (info_ptr->fixed_size + info_ptr->vars_size
14574 + info_ptr->parm_size);
14576 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14577 info_ptr->spe_gp_size = 8 * (32 - first_gp);
14579 info_ptr->spe_gp_size = 0;
14581 if (TARGET_ALTIVEC_ABI)
14582 info_ptr->vrsave_mask = compute_vrsave_mask ();
14584 info_ptr->vrsave_mask = 0;
14586 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
14587 info_ptr->vrsave_size = 4;
14589 info_ptr->vrsave_size = 0;
14591 compute_save_world_info (info_ptr);
14593 /* Calculate the offsets. */
14594 switch (DEFAULT_ABI)
14598 gcc_unreachable ();
14602 info_ptr->fp_save_offset = - info_ptr->fp_size;
14603 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14605 if (TARGET_ALTIVEC_ABI)
14607 info_ptr->vrsave_save_offset
14608 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
14610 /* Align stack so vector save area is on a quadword boundary.
14611 The padding goes above the vectors. */
14612 if (info_ptr->altivec_size != 0)
14613 info_ptr->altivec_padding_size
14614 = info_ptr->vrsave_save_offset & 0xF;
14616 info_ptr->altivec_padding_size = 0;
14618 info_ptr->altivec_save_offset
14619 = info_ptr->vrsave_save_offset
14620 - info_ptr->altivec_padding_size
14621 - info_ptr->altivec_size;
14622 gcc_assert (info_ptr->altivec_size == 0
14623 || info_ptr->altivec_save_offset % 16 == 0);
14625 /* Adjust for AltiVec case. */
14626 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
14629 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
14630 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
14631 info_ptr->lr_save_offset = 2*reg_size;
14635 info_ptr->fp_save_offset = - info_ptr->fp_size;
14636 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14637 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
14639 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14641 /* Align stack so SPE GPR save area is aligned on a
14642 double-word boundary. */
14643 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
14644 info_ptr->spe_padding_size
14645 = 8 - (-info_ptr->cr_save_offset % 8);
14647 info_ptr->spe_padding_size = 0;
14649 info_ptr->spe_gp_save_offset
14650 = info_ptr->cr_save_offset
14651 - info_ptr->spe_padding_size
14652 - info_ptr->spe_gp_size;
14654 /* Adjust for SPE case. */
14655 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
14657 else if (TARGET_ALTIVEC_ABI)
14659 info_ptr->vrsave_save_offset
14660 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
14662 /* Align stack so vector save area is on a quadword boundary. */
14663 if (info_ptr->altivec_size != 0)
14664 info_ptr->altivec_padding_size
14665 = 16 - (-info_ptr->vrsave_save_offset % 16);
14667 info_ptr->altivec_padding_size = 0;
14669 info_ptr->altivec_save_offset
14670 = info_ptr->vrsave_save_offset
14671 - info_ptr->altivec_padding_size
14672 - info_ptr->altivec_size;
14674 /* Adjust for AltiVec case. */
14675 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
14678 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
14679 info_ptr->ehrd_offset -= ehrd_size;
14680 info_ptr->lr_save_offset = reg_size;
14684 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
14685 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
14686 + info_ptr->gp_size
14687 + info_ptr->altivec_size
14688 + info_ptr->altivec_padding_size
14689 + info_ptr->spe_gp_size
14690 + info_ptr->spe_padding_size
14692 + info_ptr->cr_size
14693 + info_ptr->vrsave_size,
14696 non_fixed_size = (info_ptr->vars_size
14697 + info_ptr->parm_size
14698 + info_ptr->save_size);
14700 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
14701 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
14703 /* Determine if we need to allocate any stack frame:
14705 For AIX we need to push the stack if a frame pointer is needed
14706 (because the stack might be dynamically adjusted), if we are
14707 debugging, if we make calls, or if the sum of fp_save, gp_save,
14708 and local variables are more than the space needed to save all
14709 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14710 + 18*8 = 288 (GPR13 reserved).
14712 For V.4 we don't have the stack cushion that AIX uses, but assume
14713 that the debugger can handle stackless frames. */
14715 if (info_ptr->calls_p)
14716 info_ptr->push_p = 1;
14718 else if (DEFAULT_ABI == ABI_V4)
14719 info_ptr->push_p = non_fixed_size != 0;
14721 else if (frame_pointer_needed)
14722 info_ptr->push_p = 1;
14724 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
14725 info_ptr->push_p = 1;
14728 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
14730 /* Zero offsets if we're not saving those registers. */
14731 if (info_ptr->fp_size == 0)
14732 info_ptr->fp_save_offset = 0;
14734 if (info_ptr->gp_size == 0)
14735 info_ptr->gp_save_offset = 0;
14737 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
14738 info_ptr->altivec_save_offset = 0;
14740 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
14741 info_ptr->vrsave_save_offset = 0;
14743 if (! TARGET_SPE_ABI
14744 || info_ptr->spe_64bit_regs_used == 0
14745 || info_ptr->spe_gp_size == 0)
14746 info_ptr->spe_gp_save_offset = 0;
14748 if (! info_ptr->lr_save_p)
14749 info_ptr->lr_save_offset = 0;
14751 if (! info_ptr->cr_save_p)
14752 info_ptr->cr_save_offset = 0;
14757 /* Return true if the current function uses any GPRs in 64-bit SIMD
14761 spe_func_has_64bit_regs_p (void)
14765 /* Functions that save and restore all the call-saved registers will
14766 need to save/restore the registers in 64-bits. */
14767 if (crtl->calls_eh_return
14768 || cfun->calls_setjmp
14769 || crtl->has_nonlocal_goto)
14772 insns = get_insns ();
14774 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
14780 /* FIXME: This should be implemented with attributes...
14782 (set_attr "spe64" "true")....then,
14783 if (get_spe64(insn)) return true;
14785 It's the only reliable way to do the stuff below. */
14787 i = PATTERN (insn);
14788 if (GET_CODE (i) == SET)
14790 enum machine_mode mode = GET_MODE (SET_SRC (i));
14792 if (SPE_VECTOR_MODE (mode))
14794 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
14804 debug_stack_info (rs6000_stack_t *info)
14806 const char *abi_string;
14809 info = rs6000_stack_info ();
14811 fprintf (stderr, "\nStack information for function %s:\n",
14812 ((current_function_decl && DECL_NAME (current_function_decl))
14813 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
14818 default: abi_string = "Unknown"; break;
14819 case ABI_NONE: abi_string = "NONE"; break;
14820 case ABI_AIX: abi_string = "AIX"; break;
14821 case ABI_DARWIN: abi_string = "Darwin"; break;
14822 case ABI_V4: abi_string = "V.4"; break;
14825 fprintf (stderr, "\tABI = %5s\n", abi_string);
14827 if (TARGET_ALTIVEC_ABI)
14828 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
14830 if (TARGET_SPE_ABI)
14831 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
14833 if (info->first_gp_reg_save != 32)
14834 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
14836 if (info->first_fp_reg_save != 64)
14837 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
14839 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
14840 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
14841 info->first_altivec_reg_save);
14843 if (info->lr_save_p)
14844 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
14846 if (info->cr_save_p)
14847 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
14849 if (info->vrsave_mask)
14850 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
14853 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
14856 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
14858 if (info->gp_save_offset)
14859 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
14861 if (info->fp_save_offset)
14862 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
14864 if (info->altivec_save_offset)
14865 fprintf (stderr, "\taltivec_save_offset = %5d\n",
14866 info->altivec_save_offset);
14868 if (info->spe_gp_save_offset)
14869 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
14870 info->spe_gp_save_offset);
14872 if (info->vrsave_save_offset)
14873 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
14874 info->vrsave_save_offset);
14876 if (info->lr_save_offset)
14877 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
14879 if (info->cr_save_offset)
14880 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
14882 if (info->varargs_save_offset)
14883 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
14885 if (info->total_size)
14886 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14889 if (info->vars_size)
14890 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14893 if (info->parm_size)
14894 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
14896 if (info->fixed_size)
14897 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14900 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14902 if (info->spe_gp_size)
14903 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14906 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14908 if (info->altivec_size)
14909 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14911 if (info->vrsave_size)
14912 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14914 if (info->altivec_padding_size)
14915 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14916 info->altivec_padding_size);
14918 if (info->spe_padding_size)
14919 fprintf (stderr, "\tspe_padding_size = %5d\n",
14920 info->spe_padding_size);
14923 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14925 if (info->save_size)
14926 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14928 if (info->reg_size != 4)
14929 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14931 fprintf (stderr, "\n");
14935 rs6000_return_addr (int count, rtx frame)
14937 /* Currently we don't optimize very well between prolog and body
14938 code and for PIC code the code can be actually quite bad, so
14939 don't try to be too clever here. */
14940 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14942 cfun->machine->ra_needs_full_frame = 1;
14949 plus_constant (copy_to_reg
14950 (gen_rtx_MEM (Pmode,
14951 memory_address (Pmode, frame))),
14952 RETURN_ADDRESS_OFFSET)));
14955 cfun->machine->ra_need_lr = 1;
14956 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14959 /* Say whether a function is a candidate for sibcall handling or not.
14960 We do not allow indirect calls to be optimized into sibling calls.
14961 Also, we can't do it if there are any vector parameters; there's
14962 nowhere to put the VRsave code so it works; note that functions with
14963 vector parameters are required to have a prototype, so the argument
14964 type info must be available here. (The tail recursion case can work
14965 with vector parameters, but there's no way to distinguish here.) */
14967 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14972 if (TARGET_ALTIVEC_VRSAVE)
14974 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14975 type; type = TREE_CHAIN (type))
14977 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14981 if (DEFAULT_ABI == ABI_DARWIN
14982 || ((*targetm.binds_local_p) (decl)
14983 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14985 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14987 if (!lookup_attribute ("longcall", attr_list)
14988 || lookup_attribute ("shortcall", attr_list))
14995 /* NULL if INSN insn is valid within a low-overhead loop.
14996 Otherwise return why doloop cannot be applied.
14997 PowerPC uses the COUNT register for branch on table instructions. */
14999 static const char *
15000 rs6000_invalid_within_doloop (const_rtx insn)
15003 return "Function call in the loop.";
15006 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
15007 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
15008 return "Computed branch in the loop.";
15014 rs6000_ra_ever_killed (void)
15020 if (crtl->is_thunk)
15023 /* regs_ever_live has LR marked as used if any sibcalls are present,
15024 but this should not force saving and restoring in the
15025 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
15026 clobbers LR, so that is inappropriate. */
15028 /* Also, the prologue can generate a store into LR that
15029 doesn't really count, like this:
15032 bcl to set PIC register
15036 When we're called from the epilogue, we need to avoid counting
15037 this as a store. */
15039 push_topmost_sequence ();
15040 top = get_insns ();
15041 pop_topmost_sequence ();
15042 reg = gen_rtx_REG (Pmode, LR_REGNO);
15044 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
15050 if (!SIBLING_CALL_P (insn))
15053 else if (find_regno_note (insn, REG_INC, LR_REGNO))
15055 else if (set_of (reg, insn) != NULL_RTX
15056 && !prologue_epilogue_contains (insn))
15063 /* Emit instructions needed to load the TOC register.
15064 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
15065 a constant pool; or for SVR4 -fpic. */
15068 rs6000_emit_load_toc_table (int fromprolog)
15071 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
15073 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
15076 rtx lab, tmp1, tmp2, got;
15078 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15079 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15081 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15083 got = rs6000_got_sym ();
15084 tmp1 = tmp2 = dest;
15087 tmp1 = gen_reg_rtx (Pmode);
15088 tmp2 = gen_reg_rtx (Pmode);
15090 emit_insn (gen_load_toc_v4_PIC_1 (lab));
15091 emit_move_insn (tmp1,
15092 gen_rtx_REG (Pmode, LR_REGNO));
15093 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
15094 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
15096 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
15098 emit_insn (gen_load_toc_v4_pic_si ());
15099 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
15101 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
15104 rtx temp0 = (fromprolog
15105 ? gen_rtx_REG (Pmode, 0)
15106 : gen_reg_rtx (Pmode));
15112 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15113 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15115 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
15116 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15118 emit_insn (gen_load_toc_v4_PIC_1 (symF));
15119 emit_move_insn (dest,
15120 gen_rtx_REG (Pmode, LR_REGNO));
15121 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
15127 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15128 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
15129 emit_move_insn (dest,
15130 gen_rtx_REG (Pmode, LR_REGNO));
15131 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
15133 emit_insn (gen_addsi3 (dest, temp0, dest));
15135 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
15137 /* This is for AIX code running in non-PIC ELF32. */
15140 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15141 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15143 emit_insn (gen_elf_high (dest, realsym));
15144 emit_insn (gen_elf_low (dest, dest, realsym));
15148 gcc_assert (DEFAULT_ABI == ABI_AIX);
15151 emit_insn (gen_load_toc_aix_si (dest));
15153 emit_insn (gen_load_toc_aix_di (dest));
15157 /* Emit instructions to restore the link register after determining where
15158 its value has been stored. */
15161 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
15163 rs6000_stack_t *info = rs6000_stack_info ();
15166 operands[0] = source;
15167 operands[1] = scratch;
15169 if (info->lr_save_p)
15171 rtx frame_rtx = stack_pointer_rtx;
15172 HOST_WIDE_INT sp_offset = 0;
15175 if (frame_pointer_needed
15176 || cfun->calls_alloca
15177 || info->total_size > 32767)
15179 tmp = gen_frame_mem (Pmode, frame_rtx);
15180 emit_move_insn (operands[1], tmp);
15181 frame_rtx = operands[1];
15183 else if (info->push_p)
15184 sp_offset = info->total_size;
15186 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
15187 tmp = gen_frame_mem (Pmode, tmp);
15188 emit_move_insn (tmp, operands[0]);
15191 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
15194 static GTY(()) alias_set_type set = -1;
15197 get_TOC_alias_set (void)
15200 set = new_alias_set ();
15204 /* This returns nonzero if the current function uses the TOC. This is
15205 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15206 is generated by the ABI_V4 load_toc_* patterns. */
15213 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15216 rtx pat = PATTERN (insn);
15219 if (GET_CODE (pat) == PARALLEL)
15220 for (i = 0; i < XVECLEN (pat, 0); i++)
15222 rtx sub = XVECEXP (pat, 0, i);
15223 if (GET_CODE (sub) == USE)
15225 sub = XEXP (sub, 0);
15226 if (GET_CODE (sub) == UNSPEC
15227 && XINT (sub, 1) == UNSPEC_TOC)
15237 create_TOC_reference (rtx symbol)
15239 if (!can_create_pseudo_p ())
15240 df_set_regs_ever_live (TOC_REGISTER, true);
15241 return gen_rtx_PLUS (Pmode,
15242 gen_rtx_REG (Pmode, TOC_REGISTER),
15243 gen_rtx_CONST (Pmode,
15244 gen_rtx_MINUS (Pmode, symbol,
15245 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
15248 /* If _Unwind_* has been called from within the same module,
15249 toc register is not guaranteed to be saved to 40(1) on function
15250 entry. Save it there in that case. */
15253 rs6000_aix_emit_builtin_unwind_init (void)
15256 rtx stack_top = gen_reg_rtx (Pmode);
15257 rtx opcode_addr = gen_reg_rtx (Pmode);
15258 rtx opcode = gen_reg_rtx (SImode);
15259 rtx tocompare = gen_reg_rtx (SImode);
15260 rtx no_toc_save_needed = gen_label_rtx ();
15262 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
15263 emit_move_insn (stack_top, mem);
15265 mem = gen_frame_mem (Pmode,
15266 gen_rtx_PLUS (Pmode, stack_top,
15267 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
15268 emit_move_insn (opcode_addr, mem);
15269 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
15270 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
15271 : 0xE8410028, SImode));
15273 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
15274 SImode, NULL_RTX, NULL_RTX,
15275 no_toc_save_needed);
15277 mem = gen_frame_mem (Pmode,
15278 gen_rtx_PLUS (Pmode, stack_top,
15279 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
15280 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
15281 emit_label (no_toc_save_needed);
15284 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15285 and the change to the stack pointer. */
15288 rs6000_emit_stack_tie (void)
15290 rtx mem = gen_frame_mem (BLKmode,
15291 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
15293 emit_insn (gen_stack_tie (mem));
15296 /* Emit the correct code for allocating stack space, as insns.
15297 If COPY_R12, make sure a copy of the old frame is left in r12.
15298 If COPY_R11, make sure a copy of the old frame is left in r11,
15299 in preference to r12 if COPY_R12.
15300 The generated code may use hard register 0 as a temporary. */
15303 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12, int copy_r11)
15306 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15307 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
15308 rtx todec = gen_int_mode (-size, Pmode);
15310 if (INTVAL (todec) != -size)
15312 warning (0, "stack frame too large");
15313 emit_insn (gen_trap ());
15317 if (crtl->limit_stack)
15319 if (REG_P (stack_limit_rtx)
15320 && REGNO (stack_limit_rtx) > 1
15321 && REGNO (stack_limit_rtx) <= 31)
15323 emit_insn (TARGET_32BIT
15324 ? gen_addsi3 (tmp_reg,
15327 : gen_adddi3 (tmp_reg,
15331 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15334 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
15336 && DEFAULT_ABI == ABI_V4)
15338 rtx toload = gen_rtx_CONST (VOIDmode,
15339 gen_rtx_PLUS (Pmode,
15343 emit_insn (gen_elf_high (tmp_reg, toload));
15344 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
15345 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15349 warning (0, "stack limit expression is not supported");
15352 if (copy_r12 || copy_r11 || ! TARGET_UPDATE)
15353 emit_move_insn (copy_r11
15354 ? gen_rtx_REG (Pmode, 11)
15355 : gen_rtx_REG (Pmode, 12),
15362 /* Need a note here so that try_split doesn't get confused. */
15363 if (get_last_insn () == NULL_RTX)
15364 emit_note (NOTE_INSN_DELETED);
15365 insn = emit_move_insn (tmp_reg, todec);
15366 try_split (PATTERN (insn), insn, 0);
15370 insn = emit_insn (TARGET_32BIT
15371 ? gen_movsi_update (stack_reg, stack_reg,
15373 : gen_movdi_di_update (stack_reg, stack_reg,
15374 todec, stack_reg));
15378 insn = emit_insn (TARGET_32BIT
15379 ? gen_addsi3 (stack_reg, stack_reg, todec)
15380 : gen_adddi3 (stack_reg, stack_reg, todec));
15381 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
15383 ? gen_rtx_REG (Pmode, 11)
15384 : gen_rtx_REG (Pmode, 12));
15387 RTX_FRAME_RELATED_P (insn) = 1;
15389 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15390 gen_rtx_SET (VOIDmode, stack_reg,
15391 gen_rtx_PLUS (Pmode, stack_reg,
15396 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15397 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15398 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15399 deduce these equivalences by itself so it wasn't necessary to hold
15400 its hand so much. */
15403 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
15404 rtx reg2, rtx rreg)
15408 /* copy_rtx will not make unique copies of registers, so we need to
15409 ensure we don't have unwanted sharing here. */
15411 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15414 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15416 real = copy_rtx (PATTERN (insn));
15418 if (reg2 != NULL_RTX)
15419 real = replace_rtx (real, reg2, rreg);
15421 real = replace_rtx (real, reg,
15422 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
15423 STACK_POINTER_REGNUM),
15426 /* We expect that 'real' is either a SET or a PARALLEL containing
15427 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15428 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15430 if (GET_CODE (real) == SET)
15434 temp = simplify_rtx (SET_SRC (set));
15436 SET_SRC (set) = temp;
15437 temp = simplify_rtx (SET_DEST (set));
15439 SET_DEST (set) = temp;
15440 if (GET_CODE (SET_DEST (set)) == MEM)
15442 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15444 XEXP (SET_DEST (set), 0) = temp;
15451 gcc_assert (GET_CODE (real) == PARALLEL);
15452 for (i = 0; i < XVECLEN (real, 0); i++)
15453 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
15455 rtx set = XVECEXP (real, 0, i);
15457 temp = simplify_rtx (SET_SRC (set));
15459 SET_SRC (set) = temp;
15460 temp = simplify_rtx (SET_DEST (set));
15462 SET_DEST (set) = temp;
15463 if (GET_CODE (SET_DEST (set)) == MEM)
15465 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15467 XEXP (SET_DEST (set), 0) = temp;
15469 RTX_FRAME_RELATED_P (set) = 1;
15473 RTX_FRAME_RELATED_P (insn) = 1;
15474 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15479 /* Returns an insn that has a vrsave set operation with the
15480 appropriate CLOBBERs. */
15483 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
15486 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
15487 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15490 = gen_rtx_SET (VOIDmode,
15492 gen_rtx_UNSPEC_VOLATILE (SImode,
15493 gen_rtvec (2, reg, vrsave),
15494 UNSPECV_SET_VRSAVE));
15498 /* We need to clobber the registers in the mask so the scheduler
15499 does not move sets to VRSAVE before sets of AltiVec registers.
15501 However, if the function receives nonlocal gotos, reload will set
15502 all call saved registers live. We will end up with:
15504 (set (reg 999) (mem))
15505 (parallel [ (set (reg vrsave) (unspec blah))
15506 (clobber (reg 999))])
15508 The clobber will cause the store into reg 999 to be dead, and
15509 flow will attempt to delete an epilogue insn. In this case, we
15510 need an unspec use/set of the register. */
15512 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
15513 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15515 if (!epiloguep || call_used_regs [i])
15516 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
15517 gen_rtx_REG (V4SImode, i));
15520 rtx reg = gen_rtx_REG (V4SImode, i);
15523 = gen_rtx_SET (VOIDmode,
15525 gen_rtx_UNSPEC (V4SImode,
15526 gen_rtvec (1, reg), 27));
15530 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
15532 for (i = 0; i < nclobs; ++i)
15533 XVECEXP (insn, 0, i) = clobs[i];
15538 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15539 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15542 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
15543 unsigned int regno, int offset, HOST_WIDE_INT total_size)
15545 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
15546 rtx replacea, replaceb;
15548 int_rtx = GEN_INT (offset);
15550 /* Some cases that need register indexed addressing. */
15551 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
15552 || (TARGET_E500_DOUBLE && mode == DFmode)
15554 && SPE_VECTOR_MODE (mode)
15555 && !SPE_CONST_OFFSET_OK (offset)))
15557 /* Whomever calls us must make sure r11 is available in the
15558 flow path of instructions in the prologue. */
15559 offset_rtx = gen_rtx_REG (Pmode, 11);
15560 emit_move_insn (offset_rtx, int_rtx);
15562 replacea = offset_rtx;
15563 replaceb = int_rtx;
15567 offset_rtx = int_rtx;
15568 replacea = NULL_RTX;
15569 replaceb = NULL_RTX;
15572 reg = gen_rtx_REG (mode, regno);
15573 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
15574 mem = gen_frame_mem (mode, addr);
15576 insn = emit_move_insn (mem, reg);
15578 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
15581 /* Emit an offset memory reference suitable for a frame store, while
15582 converting to a valid addressing mode. */
15585 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
15587 rtx int_rtx, offset_rtx;
15589 int_rtx = GEN_INT (offset);
15591 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
15592 || (TARGET_E500_DOUBLE && mode == DFmode))
15594 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15595 emit_move_insn (offset_rtx, int_rtx);
15598 offset_rtx = int_rtx;
15600 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
15603 /* Look for user-defined global regs. We should not save and restore these,
15604 and cannot use stmw/lmw if there are any in its range. */
15607 no_global_regs_above (int first, bool gpr)
15610 for (i = first; i < gpr ? 32 : 64 ; i++)
15611 if (global_regs[i])
15616 #ifndef TARGET_FIX_AND_CONTINUE
15617 #define TARGET_FIX_AND_CONTINUE 0
15620 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
15621 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
15622 #define LAST_SAVRES_REGISTER 31
15623 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
15625 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8];
15627 /* Return the symbol for an out-of-line register save/restore routine.
15628 We are saving/restoring GPRs if GPR is true. */
15631 rs6000_savres_routine_sym (rs6000_stack_t *info, bool savep, bool gpr, bool exitp)
15633 int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32);
15635 int select = ((savep ? 1 : 0) << 2
15637 /* On the SPE, we never have any FPRs, but we do have
15638 32/64-bit versions of the routines. */
15639 ? (TARGET_SPE_ABI && info->spe_64bit_regs_used ? 1 : 0)
15643 /* Don't generate bogus routine names. */
15644 gcc_assert (FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER);
15646 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
15651 const char *action;
15652 const char *regkind;
15653 const char *exit_suffix;
15655 action = savep ? "save" : "rest";
15657 /* SPE has slightly different names for its routines depending on
15658 whether we are saving 32-bit or 64-bit registers. */
15659 if (TARGET_SPE_ABI)
15661 /* No floating point saves on the SPE. */
15664 regkind = info->spe_64bit_regs_used ? "64gpr" : "32gpr";
15667 regkind = gpr ? "gpr" : "fpr";
15669 exit_suffix = exitp ? "_x" : "";
15671 sprintf (name, "_%s%s_%d%s", action, regkind, regno, exit_suffix);
15673 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
15674 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
15680 /* Emit a sequence of insns, including a stack tie if needed, for
15681 resetting the stack pointer. If SAVRES is true, then don't reset the
15682 stack pointer, but move the base of the frame into r11 for use by
15683 out-of-line register restore routines. */
15686 rs6000_emit_stack_reset (rs6000_stack_t *info,
15687 rtx sp_reg_rtx, rtx frame_reg_rtx,
15688 int sp_offset, bool savres)
15690 /* This blockage is needed so that sched doesn't decide to move
15691 the sp change before the register restores. */
15692 if (frame_reg_rtx != sp_reg_rtx
15694 && info->spe_64bit_regs_used != 0
15695 && info->first_gp_reg_save != 32))
15696 rs6000_emit_stack_tie ();
15698 if (frame_reg_rtx != sp_reg_rtx)
15700 rs6000_emit_stack_tie ();
15701 if (sp_offset != 0)
15702 emit_insn (gen_addsi3 (sp_reg_rtx, frame_reg_rtx,
15703 GEN_INT (sp_offset)));
15705 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15707 else if (sp_offset != 0)
15709 /* If we are restoring registers out-of-line, we will be using the
15710 "exit" variants of the restore routines, which will reset the
15711 stack for us. But we do need to point r11 into the right place
15712 for those routines. */
15713 rtx dest_reg = (savres
15714 ? gen_rtx_REG (Pmode, 11)
15717 emit_insn (TARGET_32BIT
15718 ? gen_addsi3 (dest_reg, sp_reg_rtx,
15719 GEN_INT (sp_offset))
15720 : gen_adddi3 (dest_reg, sp_reg_rtx,
15721 GEN_INT (sp_offset)));
15725 /* Construct a parallel rtx describing the effect of a call to an
15726 out-of-line register save/restore routine. */
15729 rs6000_make_savres_rtx (rs6000_stack_t *info,
15730 rtx frame_reg_rtx, int save_area_offset,
15731 enum machine_mode reg_mode,
15732 bool savep, bool gpr, bool exitp)
15735 int offset, start_reg, end_reg, n_regs;
15736 int reg_size = GET_MODE_SIZE (reg_mode);
15742 ? info->first_gp_reg_save
15743 : info->first_fp_reg_save);
15744 end_reg = gpr ? 32 : 64;
15745 n_regs = end_reg - start_reg;
15746 p = rtvec_alloc ((exitp ? 4 : 3) + n_regs);
15748 /* If we're saving registers, then we should never say we're exiting. */
15749 gcc_assert ((savep && !exitp) || !savep);
15752 RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode);
15754 RTVEC_ELT (p, offset++)
15755 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65));
15757 sym = rs6000_savres_routine_sym (info, savep, gpr, exitp);
15758 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
15759 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 11));
15761 for (i = 0; i < end_reg - start_reg; i++)
15763 rtx addr, reg, mem;
15764 reg = gen_rtx_REG (reg_mode, start_reg + i);
15765 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15766 GEN_INT (save_area_offset + reg_size*i));
15767 mem = gen_frame_mem (reg_mode, addr);
15769 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode,
15771 savep ? reg : mem);
15774 return gen_rtx_PARALLEL (VOIDmode, p);
15777 /* Determine whether the gp REG is really used. */
15780 rs6000_reg_live_or_pic_offset_p (int reg)
15782 return ((df_regs_ever_live_p (reg)
15783 && (!call_used_regs[reg]
15784 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15785 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15786 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15787 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15788 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
15792 SAVRES_MULTIPLE = 0x1,
15793 SAVRES_INLINE_FPRS = 0x2,
15794 SAVRES_INLINE_GPRS = 0x4
15797 /* Determine the strategy for savings/restoring registers. */
15800 rs6000_savres_strategy (rs6000_stack_t *info, bool savep,
15801 int using_static_chain_p, int sibcall)
15803 bool using_multiple_p;
15805 bool savres_fprs_inline;
15806 bool savres_gprs_inline;
15807 bool noclobber_global_gprs
15808 = no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true);
15810 using_multiple_p = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15811 && (!TARGET_SPE_ABI
15812 || info->spe_64bit_regs_used == 0)
15813 && info->first_gp_reg_save < 31
15814 && noclobber_global_gprs);
15815 /* Don't bother to try to save things out-of-line if r11 is occupied
15816 by the static chain. It would require too much fiddling and the
15817 static chain is rarely used anyway. */
15818 common = (using_static_chain_p
15820 || crtl->calls_eh_return
15821 || !info->lr_save_p
15822 || cfun->machine->ra_need_lr
15823 || info->total_size > 32767);
15824 savres_fprs_inline = (common
15825 || info->first_fp_reg_save == 64
15826 || !no_global_regs_above (info->first_fp_reg_save,
15828 || FP_SAVE_INLINE (info->first_fp_reg_save));
15829 savres_gprs_inline = (common
15830 /* Saving CR interferes with the exit routines
15831 used on the SPE, so just punt here. */
15834 && info->spe_64bit_regs_used != 0
15835 && info->cr_save_p != 0)
15836 || info->first_gp_reg_save == 32
15837 || !noclobber_global_gprs
15838 || GP_SAVE_INLINE (info->first_gp_reg_save));
15841 /* If we are going to use store multiple, then don't even bother
15842 with the out-of-line routines, since the store-multiple instruction
15843 will always be smaller. */
15844 savres_gprs_inline = savres_gprs_inline || using_multiple_p;
15847 /* The situation is more complicated with load multiple. We'd
15848 prefer to use the out-of-line routines for restores, since the
15849 "exit" out-of-line routines can handle the restore of LR and
15850 the frame teardown. But we can only use the out-of-line
15851 routines if we know that we've used store multiple or
15852 out-of-line routines in the prologue, i.e. if we've saved all
15853 the registers from first_gp_reg_save. Otherwise, we risk
15854 loading garbage from the stack. Furthermore, we can only use
15855 the "exit" out-of-line gpr restore if we haven't saved any
15857 bool saved_all = !savres_gprs_inline || using_multiple_p;
15859 if (saved_all && info->first_fp_reg_save != 64)
15860 /* We can't use the exit routine; use load multiple if it's
15862 savres_gprs_inline = savres_gprs_inline || using_multiple_p;
15865 return (using_multiple_p
15866 | (savres_fprs_inline << 1)
15867 | (savres_gprs_inline << 2));
15870 /* Emit function prologue as insns. */
15873 rs6000_emit_prologue (void)
15875 rs6000_stack_t *info = rs6000_stack_info ();
15876 enum machine_mode reg_mode = Pmode;
15877 int reg_size = TARGET_32BIT ? 4 : 8;
15878 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15879 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
15880 rtx frame_reg_rtx = sp_reg_rtx;
15881 rtx cr_save_rtx = NULL_RTX;
15884 int saving_FPRs_inline;
15885 int saving_GPRs_inline;
15886 int using_store_multiple;
15887 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15888 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15889 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15890 HOST_WIDE_INT sp_offset = 0;
15892 if (TARGET_FIX_AND_CONTINUE)
15894 /* gdb on darwin arranges to forward a function from the old
15895 address by modifying the first 5 instructions of the function
15896 to branch to the overriding function. This is necessary to
15897 permit function pointers that point to the old function to
15898 actually forward to the new function. */
15899 emit_insn (gen_nop ());
15900 emit_insn (gen_nop ());
15901 emit_insn (gen_nop ());
15902 emit_insn (gen_nop ());
15903 emit_insn (gen_nop ());
15906 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15908 reg_mode = V2SImode;
15912 strategy = rs6000_savres_strategy (info, /*savep=*/true,
15913 /*static_chain_p=*/using_static_chain_p,
15915 using_store_multiple = strategy & SAVRES_MULTIPLE;
15916 saving_FPRs_inline = strategy & SAVRES_INLINE_FPRS;
15917 saving_GPRs_inline = strategy & SAVRES_INLINE_GPRS;
15919 /* For V.4, update stack before we do any saving and set back pointer. */
15920 if (! WORLD_SAVE_P (info)
15922 && (DEFAULT_ABI == ABI_V4
15923 || crtl->calls_eh_return))
15925 bool need_r11 = (TARGET_SPE
15926 ? (!saving_GPRs_inline
15927 && info->spe_64bit_regs_used == 0)
15928 : (!saving_FPRs_inline || !saving_GPRs_inline));
15929 if (info->total_size < 32767)
15930 sp_offset = info->total_size;
15932 frame_reg_rtx = (need_r11
15933 ? gen_rtx_REG (Pmode, 11)
15935 rs6000_emit_allocate_stack (info->total_size,
15936 (frame_reg_rtx != sp_reg_rtx
15937 && (info->cr_save_p
15939 || info->first_fp_reg_save < 64
15940 || info->first_gp_reg_save < 32
15943 if (frame_reg_rtx != sp_reg_rtx)
15944 rs6000_emit_stack_tie ();
15947 /* Handle world saves specially here. */
15948 if (WORLD_SAVE_P (info))
15955 /* save_world expects lr in r0. */
15956 reg0 = gen_rtx_REG (Pmode, 0);
15957 if (info->lr_save_p)
15959 insn = emit_move_insn (reg0,
15960 gen_rtx_REG (Pmode, LR_REGNO));
15961 RTX_FRAME_RELATED_P (insn) = 1;
15964 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15965 assumptions about the offsets of various bits of the stack
15967 gcc_assert (info->gp_save_offset == -220
15968 && info->fp_save_offset == -144
15969 && info->lr_save_offset == 8
15970 && info->cr_save_offset == 4
15973 && (!crtl->calls_eh_return
15974 || info->ehrd_offset == -432)
15975 && info->vrsave_save_offset == -224
15976 && info->altivec_save_offset == -416);
15978 treg = gen_rtx_REG (SImode, 11);
15979 emit_move_insn (treg, GEN_INT (-info->total_size));
15981 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15982 in R11. It also clobbers R12, so beware! */
15984 /* Preserve CR2 for save_world prologues */
15986 sz += 32 - info->first_gp_reg_save;
15987 sz += 64 - info->first_fp_reg_save;
15988 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
15989 p = rtvec_alloc (sz);
15991 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
15992 gen_rtx_REG (SImode,
15994 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15995 gen_rtx_SYMBOL_REF (Pmode,
15997 /* We do floats first so that the instruction pattern matches
15999 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16001 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
16002 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16003 GEN_INT (info->fp_save_offset
16004 + sp_offset + 8 * i));
16005 rtx mem = gen_frame_mem (DFmode, addr);
16007 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16009 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16011 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16012 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16013 GEN_INT (info->altivec_save_offset
16014 + sp_offset + 16 * i));
16015 rtx mem = gen_frame_mem (V4SImode, addr);
16017 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16019 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16021 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16022 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16023 GEN_INT (info->gp_save_offset
16024 + sp_offset + reg_size * i));
16025 rtx mem = gen_frame_mem (reg_mode, addr);
16027 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16031 /* CR register traditionally saved as CR2. */
16032 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16033 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16034 GEN_INT (info->cr_save_offset
16036 rtx mem = gen_frame_mem (reg_mode, addr);
16038 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16040 /* Explain about use of R0. */
16041 if (info->lr_save_p)
16043 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16044 GEN_INT (info->lr_save_offset
16046 rtx mem = gen_frame_mem (reg_mode, addr);
16048 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
16050 /* Explain what happens to the stack pointer. */
16052 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
16053 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
16056 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16057 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16058 treg, GEN_INT (-info->total_size));
16059 sp_offset = info->total_size;
16062 /* If we use the link register, get it into r0. */
16063 if (!WORLD_SAVE_P (info) && info->lr_save_p)
16065 rtx addr, reg, mem;
16067 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
16068 gen_rtx_REG (Pmode, LR_REGNO));
16069 RTX_FRAME_RELATED_P (insn) = 1;
16071 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16072 GEN_INT (info->lr_save_offset + sp_offset));
16073 reg = gen_rtx_REG (Pmode, 0);
16074 mem = gen_rtx_MEM (Pmode, addr);
16075 /* This should not be of rs6000_sr_alias_set, because of
16076 __builtin_return_address. */
16078 insn = emit_move_insn (mem, reg);
16079 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16080 NULL_RTX, NULL_RTX);
16083 /* If we need to save CR, put it into r12. */
16084 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
16088 cr_save_rtx = gen_rtx_REG (SImode, 12);
16089 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
16090 RTX_FRAME_RELATED_P (insn) = 1;
16091 /* Now, there's no way that dwarf2out_frame_debug_expr is going
16092 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
16093 But that's OK. All we have to do is specify that _one_ condition
16094 code register is saved in this stack slot. The thrower's epilogue
16095 will then restore all the call-saved registers.
16096 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
16097 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
16098 gen_rtx_REG (SImode, CR2_REGNO));
16099 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
16104 /* Do any required saving of fpr's. If only one or two to save, do
16105 it ourselves. Otherwise, call function. */
16106 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
16109 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16110 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
16111 && ! call_used_regs[info->first_fp_reg_save+i]))
16112 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
16113 info->first_fp_reg_save + i,
16114 info->fp_save_offset + sp_offset + 8 * i,
16117 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
16121 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
16122 info->fp_save_offset + sp_offset,
16124 /*savep=*/true, /*gpr=*/false,
16126 insn = emit_insn (par);
16127 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16128 NULL_RTX, NULL_RTX);
16131 /* Save GPRs. This is done as a PARALLEL if we are using
16132 the store-multiple instructions. */
16133 if (!WORLD_SAVE_P (info)
16135 && info->spe_64bit_regs_used != 0
16136 && info->first_gp_reg_save != 32)
16139 rtx spe_save_area_ptr;
16141 /* Determine whether we can address all of the registers that need
16142 to be saved with an offset from the stack pointer that fits in
16143 the small const field for SPE memory instructions. */
16144 int spe_regs_addressable_via_sp
16145 = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
16146 + (32 - info->first_gp_reg_save - 1) * reg_size)
16147 && saving_GPRs_inline);
16150 if (spe_regs_addressable_via_sp)
16152 spe_save_area_ptr = frame_reg_rtx;
16153 spe_offset = info->spe_gp_save_offset + sp_offset;
16157 /* Make r11 point to the start of the SPE save area. We need
16158 to be careful here if r11 is holding the static chain. If
16159 it is, then temporarily save it in r0. We would use r0 as
16160 our base register here, but using r0 as a base register in
16161 loads and stores means something different from what we
16163 int ool_adjust = (saving_GPRs_inline
16165 : (info->first_gp_reg_save
16166 - (FIRST_SAVRES_REGISTER+1))*8);
16167 HOST_WIDE_INT offset = (info->spe_gp_save_offset
16168 + sp_offset - ool_adjust);
16170 if (using_static_chain_p)
16172 rtx r0 = gen_rtx_REG (Pmode, 0);
16173 gcc_assert (info->first_gp_reg_save > 11);
16175 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
16178 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
16179 insn = emit_insn (gen_addsi3 (spe_save_area_ptr,
16181 GEN_INT (offset)));
16182 /* We need to make sure the move to r11 gets noted for
16183 properly outputting unwind information. */
16184 if (!saving_GPRs_inline)
16185 rs6000_frame_related (insn, frame_reg_rtx, offset,
16186 NULL_RTX, NULL_RTX);
16190 if (saving_GPRs_inline)
16192 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16193 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16195 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16196 rtx offset, addr, mem;
16198 /* We're doing all this to ensure that the offset fits into
16199 the immediate offset of 'evstdd'. */
16200 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
16202 offset = GEN_INT (reg_size * i + spe_offset);
16203 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
16204 mem = gen_rtx_MEM (V2SImode, addr);
16206 insn = emit_move_insn (mem, reg);
16208 rs6000_frame_related (insn, spe_save_area_ptr,
16209 info->spe_gp_save_offset
16210 + sp_offset + reg_size * i,
16211 offset, const0_rtx);
16218 par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
16220 /*savep=*/true, /*gpr=*/true,
16222 insn = emit_insn (par);
16223 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16224 NULL_RTX, NULL_RTX);
16228 /* Move the static chain pointer back. */
16229 if (using_static_chain_p && !spe_regs_addressable_via_sp)
16230 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
16232 else if (!WORLD_SAVE_P (info) && !saving_GPRs_inline)
16236 /* Need to adjust r11 if we saved any FPRs. */
16237 if (info->first_fp_reg_save != 64)
16239 rtx r11 = gen_rtx_REG (reg_mode, 11);
16240 rtx offset = GEN_INT (info->total_size
16241 + (-8 * (64-info->first_fp_reg_save)));
16242 rtx ptr_reg = (sp_reg_rtx == frame_reg_rtx
16243 ? sp_reg_rtx : r11);
16245 emit_insn (TARGET_32BIT
16246 ? gen_addsi3 (r11, ptr_reg, offset)
16247 : gen_adddi3 (r11, ptr_reg, offset));
16250 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
16251 info->gp_save_offset + sp_offset,
16253 /*savep=*/true, /*gpr=*/true,
16255 insn = emit_insn (par);
16256 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16257 NULL_RTX, NULL_RTX);
16259 else if (!WORLD_SAVE_P (info) && using_store_multiple)
16263 p = rtvec_alloc (32 - info->first_gp_reg_save);
16264 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16266 rtx addr, reg, mem;
16267 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16268 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16269 GEN_INT (info->gp_save_offset
16272 mem = gen_frame_mem (reg_mode, addr);
16274 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
16276 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16277 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16278 NULL_RTX, NULL_RTX);
16280 else if (!WORLD_SAVE_P (info))
16283 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16284 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16286 rtx addr, reg, mem;
16287 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16289 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16290 GEN_INT (info->gp_save_offset
16293 mem = gen_frame_mem (reg_mode, addr);
16295 insn = emit_move_insn (mem, reg);
16296 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16297 NULL_RTX, NULL_RTX);
16301 /* ??? There's no need to emit actual instructions here, but it's the
16302 easiest way to get the frame unwind information emitted. */
16303 if (crtl->calls_eh_return)
16305 unsigned int i, regno;
16307 /* In AIX ABI we need to pretend we save r2 here. */
16310 rtx addr, reg, mem;
16312 reg = gen_rtx_REG (reg_mode, 2);
16313 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16314 GEN_INT (sp_offset + 5 * reg_size));
16315 mem = gen_frame_mem (reg_mode, addr);
16317 insn = emit_move_insn (mem, reg);
16318 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16319 NULL_RTX, NULL_RTX);
16320 PATTERN (insn) = gen_blockage ();
16325 regno = EH_RETURN_DATA_REGNO (i);
16326 if (regno == INVALID_REGNUM)
16329 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
16330 info->ehrd_offset + sp_offset
16331 + reg_size * (int) i,
16336 /* Save CR if we use any that must be preserved. */
16337 if (!WORLD_SAVE_P (info) && info->cr_save_p)
16339 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16340 GEN_INT (info->cr_save_offset + sp_offset));
16341 rtx mem = gen_frame_mem (SImode, addr);
16342 /* See the large comment above about why CR2_REGNO is used. */
16343 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
16345 /* If r12 was used to hold the original sp, copy cr into r0 now
16347 if (REGNO (frame_reg_rtx) == 12)
16351 cr_save_rtx = gen_rtx_REG (SImode, 0);
16352 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
16353 RTX_FRAME_RELATED_P (insn) = 1;
16354 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
16355 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
16360 insn = emit_move_insn (mem, cr_save_rtx);
16362 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16363 NULL_RTX, NULL_RTX);
16366 /* Update stack and set back pointer unless this is V.4,
16367 for which it was done previously. */
16368 if (!WORLD_SAVE_P (info) && info->push_p
16369 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
16371 if (info->total_size < 32767)
16372 sp_offset = info->total_size;
16374 frame_reg_rtx = frame_ptr_rtx;
16375 rs6000_emit_allocate_stack (info->total_size,
16376 (frame_reg_rtx != sp_reg_rtx
16377 && ((info->altivec_size != 0)
16378 || (info->vrsave_mask != 0)
16381 if (frame_reg_rtx != sp_reg_rtx)
16382 rs6000_emit_stack_tie ();
16385 /* Set frame pointer, if needed. */
16386 if (frame_pointer_needed)
16388 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
16390 RTX_FRAME_RELATED_P (insn) = 1;
16393 /* Save AltiVec registers if needed. Save here because the red zone does
16394 not include AltiVec registers. */
16395 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
16399 /* There should be a non inline version of this, for when we
16400 are saving lots of vector registers. */
16401 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16402 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16404 rtx areg, savereg, mem;
16407 offset = info->altivec_save_offset + sp_offset
16408 + 16 * (i - info->first_altivec_reg_save);
16410 savereg = gen_rtx_REG (V4SImode, i);
16412 areg = gen_rtx_REG (Pmode, 0);
16413 emit_move_insn (areg, GEN_INT (offset));
16415 /* AltiVec addressing mode is [reg+reg]. */
16416 mem = gen_frame_mem (V4SImode,
16417 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
16419 insn = emit_move_insn (mem, savereg);
16421 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16422 areg, GEN_INT (offset));
16426 /* VRSAVE is a bit vector representing which AltiVec registers
16427 are used. The OS uses this to determine which vector
16428 registers to save on a context switch. We need to save
16429 VRSAVE on the stack frame, add whatever AltiVec registers we
16430 used in this function, and do the corresponding magic in the
16433 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
16434 && info->vrsave_mask != 0)
16436 rtx reg, mem, vrsave;
16439 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16440 as frame_reg_rtx and r11 as the static chain pointer for
16441 nested functions. */
16442 reg = gen_rtx_REG (SImode, 0);
16443 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
16445 emit_insn (gen_get_vrsave_internal (reg));
16447 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
16449 if (!WORLD_SAVE_P (info))
16452 offset = info->vrsave_save_offset + sp_offset;
16453 mem = gen_frame_mem (SImode,
16454 gen_rtx_PLUS (Pmode, frame_reg_rtx,
16455 GEN_INT (offset)));
16456 insn = emit_move_insn (mem, reg);
16459 /* Include the registers in the mask. */
16460 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
16462 insn = emit_insn (generate_set_vrsave (reg, info, 0));
16465 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16466 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
16467 || (DEFAULT_ABI == ABI_V4
16468 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
16469 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
16471 /* If emit_load_toc_table will use the link register, we need to save
16472 it. We use R12 for this purpose because emit_load_toc_table
16473 can use register 0. This allows us to use a plain 'blr' to return
16474 from the procedure more often. */
16475 int save_LR_around_toc_setup = (TARGET_ELF
16476 && DEFAULT_ABI != ABI_AIX
16478 && ! info->lr_save_p
16479 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
16480 if (save_LR_around_toc_setup)
16482 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16484 insn = emit_move_insn (frame_ptr_rtx, lr);
16485 RTX_FRAME_RELATED_P (insn) = 1;
16487 rs6000_emit_load_toc_table (TRUE);
16489 insn = emit_move_insn (lr, frame_ptr_rtx);
16490 RTX_FRAME_RELATED_P (insn) = 1;
16493 rs6000_emit_load_toc_table (TRUE);
16497 if (DEFAULT_ABI == ABI_DARWIN
16498 && flag_pic && crtl->uses_pic_offset_table)
16500 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16501 rtx src = machopic_function_base_sym ();
16503 /* Save and restore LR locally around this call (in R0). */
16504 if (!info->lr_save_p)
16505 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
16507 emit_insn (gen_load_macho_picbase (src));
16509 emit_move_insn (gen_rtx_REG (Pmode,
16510 RS6000_PIC_OFFSET_TABLE_REGNUM),
16513 if (!info->lr_save_p)
16514 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
16519 /* Write function prologue. */
16522 rs6000_output_function_prologue (FILE *file,
16523 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
16525 rs6000_stack_t *info = rs6000_stack_info ();
16527 if (TARGET_DEBUG_STACK)
16528 debug_stack_info (info);
16530 /* Write .extern for any function we will call to save and restore
16532 if (info->first_fp_reg_save < 64
16533 && !FP_SAVE_INLINE (info->first_fp_reg_save))
16534 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16535 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
16536 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
16538 /* Write .extern for AIX common mode routines, if needed. */
16539 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
16541 fputs ("\t.extern __mulh\n", file);
16542 fputs ("\t.extern __mull\n", file);
16543 fputs ("\t.extern __divss\n", file);
16544 fputs ("\t.extern __divus\n", file);
16545 fputs ("\t.extern __quoss\n", file);
16546 fputs ("\t.extern __quous\n", file);
16547 common_mode_defined = 1;
16550 if (! HAVE_prologue)
16554 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16555 the "toplevel" insn chain. */
16556 emit_note (NOTE_INSN_DELETED);
16557 rs6000_emit_prologue ();
16558 emit_note (NOTE_INSN_DELETED);
16560 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16564 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16566 INSN_ADDRESSES_NEW (insn, addr);
16571 if (TARGET_DEBUG_STACK)
16572 debug_rtx_list (get_insns (), 100);
16573 final (get_insns (), file, FALSE);
16577 rs6000_pic_labelno++;
16580 /* Non-zero if vmx regs are restored before the frame pop, zero if
16581 we restore after the pop when possible. */
16582 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
16584 /* Reload CR from REG. */
16587 rs6000_restore_saved_cr (rtx reg, int using_mfcr_multiple)
16592 if (using_mfcr_multiple)
16594 for (i = 0; i < 8; i++)
16595 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16597 gcc_assert (count);
16600 if (using_mfcr_multiple && count > 1)
16605 p = rtvec_alloc (count);
16608 for (i = 0; i < 8; i++)
16609 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16611 rtvec r = rtvec_alloc (2);
16612 RTVEC_ELT (r, 0) = reg;
16613 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
16614 RTVEC_ELT (p, ndx) =
16615 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
16616 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
16619 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16620 gcc_assert (ndx == count);
16623 for (i = 0; i < 8; i++)
16624 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16626 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
16632 /* Emit function epilogue as insns.
16634 At present, dwarf2out_frame_debug_expr doesn't understand
16635 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16636 anywhere in the epilogue. Most of the insns below would in any case
16637 need special notes to explain where r11 is in relation to the stack. */
16640 rs6000_emit_epilogue (int sibcall)
16642 rs6000_stack_t *info;
16643 int restoring_GPRs_inline;
16644 int restoring_FPRs_inline;
16645 int using_load_multiple;
16646 int using_mtcr_multiple;
16647 int use_backchain_to_restore_sp;
16651 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
16652 rtx frame_reg_rtx = sp_reg_rtx;
16653 enum machine_mode reg_mode = Pmode;
16654 int reg_size = TARGET_32BIT ? 4 : 8;
16657 info = rs6000_stack_info ();
16659 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
16661 reg_mode = V2SImode;
16665 strategy = rs6000_savres_strategy (info, /*savep=*/false,
16666 /*static_chain_p=*/0, sibcall);
16667 using_load_multiple = strategy & SAVRES_MULTIPLE;
16668 restoring_FPRs_inline = strategy & SAVRES_INLINE_FPRS;
16669 restoring_GPRs_inline = strategy & SAVRES_INLINE_GPRS;
16670 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
16671 || rs6000_cpu == PROCESSOR_PPC603
16672 || rs6000_cpu == PROCESSOR_PPC750
16674 /* Restore via the backchain when we have a large frame, since this
16675 is more efficient than an addis, addi pair. The second condition
16676 here will not trigger at the moment; We don't actually need a
16677 frame pointer for alloca, but the generic parts of the compiler
16678 give us one anyway. */
16679 use_backchain_to_restore_sp = (info->total_size > 32767
16680 || info->total_size
16681 + (info->lr_save_p ? info->lr_save_offset : 0)
16683 || (cfun->calls_alloca
16684 && !frame_pointer_needed));
16685 restore_lr = (info->lr_save_p
16686 && restoring_GPRs_inline
16687 && restoring_FPRs_inline);
16689 if (WORLD_SAVE_P (info))
16693 const char *alloc_rname;
16696 /* eh_rest_world_r10 will return to the location saved in the LR
16697 stack slot (which is not likely to be our caller.)
16698 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16699 rest_world is similar, except any R10 parameter is ignored.
16700 The exception-handling stuff that was here in 2.95 is no
16701 longer necessary. */
16705 + 32 - info->first_gp_reg_save
16706 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
16707 + 63 + 1 - info->first_fp_reg_save);
16709 strcpy (rname, ((crtl->calls_eh_return) ?
16710 "*eh_rest_world_r10" : "*rest_world"));
16711 alloc_rname = ggc_strdup (rname);
16714 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
16715 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
16716 gen_rtx_REG (Pmode,
16719 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
16720 /* The instruction pattern requires a clobber here;
16721 it is shared with the restVEC helper. */
16723 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
16726 /* CR register traditionally saved as CR2. */
16727 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16728 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16729 GEN_INT (info->cr_save_offset));
16730 rtx mem = gen_frame_mem (reg_mode, addr);
16732 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16735 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16737 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16738 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16739 GEN_INT (info->gp_save_offset
16741 rtx mem = gen_frame_mem (reg_mode, addr);
16743 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16745 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16747 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16748 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16749 GEN_INT (info->altivec_save_offset
16751 rtx mem = gen_frame_mem (V4SImode, addr);
16753 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16755 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
16757 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
16758 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16759 GEN_INT (info->fp_save_offset
16761 rtx mem = gen_frame_mem (DFmode, addr);
16763 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16766 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
16768 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
16770 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
16772 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
16774 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
16775 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
16780 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
16782 sp_offset = info->total_size;
16784 /* Restore AltiVec registers if we must do so before adjusting the
16786 if (TARGET_ALTIVEC_ABI
16787 && info->altivec_size != 0
16788 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16789 || (DEFAULT_ABI != ABI_V4
16790 && info->altivec_save_offset < (TARGET_32BIT ? -220 : -288))))
16794 if (use_backchain_to_restore_sp)
16796 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16797 emit_move_insn (frame_reg_rtx,
16798 gen_rtx_MEM (Pmode, sp_reg_rtx));
16801 else if (frame_pointer_needed)
16802 frame_reg_rtx = hard_frame_pointer_rtx;
16804 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16805 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16807 rtx addr, areg, mem;
16809 areg = gen_rtx_REG (Pmode, 0);
16811 (areg, GEN_INT (info->altivec_save_offset
16813 + 16 * (i - info->first_altivec_reg_save)));
16815 /* AltiVec addressing mode is [reg+reg]. */
16816 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
16817 mem = gen_frame_mem (V4SImode, addr);
16819 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
16823 /* Restore VRSAVE if we must do so before adjusting the stack. */
16825 && TARGET_ALTIVEC_VRSAVE
16826 && info->vrsave_mask != 0
16827 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16828 || (DEFAULT_ABI != ABI_V4
16829 && info->vrsave_save_offset < (TARGET_32BIT ? -220 : -288))))
16831 rtx addr, mem, reg;
16833 if (frame_reg_rtx == sp_reg_rtx)
16835 if (use_backchain_to_restore_sp)
16837 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16838 emit_move_insn (frame_reg_rtx,
16839 gen_rtx_MEM (Pmode, sp_reg_rtx));
16842 else if (frame_pointer_needed)
16843 frame_reg_rtx = hard_frame_pointer_rtx;
16846 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16847 GEN_INT (info->vrsave_save_offset + sp_offset));
16848 mem = gen_frame_mem (SImode, addr);
16849 reg = gen_rtx_REG (SImode, 12);
16850 emit_move_insn (reg, mem);
16852 emit_insn (generate_set_vrsave (reg, info, 1));
16855 /* If we have a large stack frame, restore the old stack pointer
16856 using the backchain. */
16857 if (use_backchain_to_restore_sp)
16859 if (frame_reg_rtx == sp_reg_rtx)
16861 /* Under V.4, don't reset the stack pointer until after we're done
16862 loading the saved registers. */
16863 if (DEFAULT_ABI == ABI_V4)
16864 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16866 emit_move_insn (frame_reg_rtx,
16867 gen_rtx_MEM (Pmode, sp_reg_rtx));
16870 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16871 && DEFAULT_ABI == ABI_V4)
16872 /* frame_reg_rtx has been set up by the altivec restore. */
16876 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
16877 frame_reg_rtx = sp_reg_rtx;
16880 /* If we have a frame pointer, we can restore the old stack pointer
16882 else if (frame_pointer_needed)
16884 frame_reg_rtx = sp_reg_rtx;
16885 if (DEFAULT_ABI == ABI_V4)
16886 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16888 emit_insn (TARGET_32BIT
16889 ? gen_addsi3 (frame_reg_rtx, hard_frame_pointer_rtx,
16890 GEN_INT (info->total_size))
16891 : gen_adddi3 (frame_reg_rtx, hard_frame_pointer_rtx,
16892 GEN_INT (info->total_size)));
16895 else if (info->push_p
16896 && DEFAULT_ABI != ABI_V4
16897 && !crtl->calls_eh_return)
16899 emit_insn (TARGET_32BIT
16900 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16901 GEN_INT (info->total_size))
16902 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16903 GEN_INT (info->total_size)));
16907 /* Restore AltiVec registers if we have not done so already. */
16908 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16909 && TARGET_ALTIVEC_ABI
16910 && info->altivec_size != 0
16911 && (DEFAULT_ABI == ABI_V4
16912 || info->altivec_save_offset >= (TARGET_32BIT ? -220 : -288)))
16916 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16917 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16919 rtx addr, areg, mem;
16921 areg = gen_rtx_REG (Pmode, 0);
16923 (areg, GEN_INT (info->altivec_save_offset
16925 + 16 * (i - info->first_altivec_reg_save)));
16927 /* AltiVec addressing mode is [reg+reg]. */
16928 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
16929 mem = gen_frame_mem (V4SImode, addr);
16931 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
16935 /* Restore VRSAVE if we have not done so already. */
16936 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16938 && TARGET_ALTIVEC_VRSAVE
16939 && info->vrsave_mask != 0
16940 && (DEFAULT_ABI == ABI_V4
16941 || info->vrsave_save_offset >= (TARGET_32BIT ? -220 : -288)))
16943 rtx addr, mem, reg;
16945 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16946 GEN_INT (info->vrsave_save_offset + sp_offset));
16947 mem = gen_frame_mem (SImode, addr);
16948 reg = gen_rtx_REG (SImode, 12);
16949 emit_move_insn (reg, mem);
16951 emit_insn (generate_set_vrsave (reg, info, 1));
16954 /* Get the old lr if we saved it. If we are restoring registers
16955 out-of-line, then the out-of-line routines can do this for us. */
16958 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
16959 info->lr_save_offset + sp_offset);
16961 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
16964 /* Get the old cr if we saved it. */
16965 if (info->cr_save_p)
16967 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16968 GEN_INT (info->cr_save_offset + sp_offset));
16969 rtx mem = gen_frame_mem (SImode, addr);
16971 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
16974 /* Set LR here to try to overlap restores below. */
16976 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
16977 gen_rtx_REG (Pmode, 0));
16979 /* Load exception handler data registers, if needed. */
16980 if (crtl->calls_eh_return)
16982 unsigned int i, regno;
16986 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16987 GEN_INT (sp_offset + 5 * reg_size));
16988 rtx mem = gen_frame_mem (reg_mode, addr);
16990 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
16997 regno = EH_RETURN_DATA_REGNO (i);
16998 if (regno == INVALID_REGNUM)
17001 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
17002 info->ehrd_offset + sp_offset
17003 + reg_size * (int) i);
17005 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
17009 /* Restore GPRs. This is done as a PARALLEL if we are using
17010 the load-multiple instructions. */
17012 && info->spe_64bit_regs_used != 0
17013 && info->first_gp_reg_save != 32)
17015 /* Determine whether we can address all of the registers that need
17016 to be saved with an offset from the stack pointer that fits in
17017 the small const field for SPE memory instructions. */
17018 int spe_regs_addressable_via_sp
17019 = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
17020 + (32 - info->first_gp_reg_save - 1) * reg_size)
17021 && restoring_GPRs_inline);
17024 if (spe_regs_addressable_via_sp)
17025 spe_offset = info->spe_gp_save_offset + sp_offset;
17028 rtx old_frame_reg_rtx = frame_reg_rtx;
17029 /* Make r11 point to the start of the SPE save area. We worried about
17030 not clobbering it when we were saving registers in the prologue.
17031 There's no need to worry here because the static chain is passed
17032 anew to every function. */
17033 int ool_adjust = (restoring_GPRs_inline
17035 : (info->first_gp_reg_save
17036 - (FIRST_SAVRES_REGISTER+1))*8);
17038 if (frame_reg_rtx == sp_reg_rtx)
17039 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
17040 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
17041 GEN_INT (info->spe_gp_save_offset
17044 /* Keep the invariant that frame_reg_rtx + sp_offset points
17045 at the top of the stack frame. */
17046 sp_offset = -info->spe_gp_save_offset;
17051 if (restoring_GPRs_inline)
17053 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17054 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
17056 rtx offset, addr, mem;
17058 /* We're doing all this to ensure that the immediate offset
17059 fits into the immediate field of 'evldd'. */
17060 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
17062 offset = GEN_INT (spe_offset + reg_size * i);
17063 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
17064 mem = gen_rtx_MEM (V2SImode, addr);
17066 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
17074 par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
17076 /*savep=*/false, /*gpr=*/true,
17078 emit_jump_insn (par);
17080 /* We don't want anybody else emitting things after we jumped
17085 else if (!restoring_GPRs_inline)
17087 /* We are jumping to an out-of-line function. */
17088 bool can_use_exit = info->first_fp_reg_save == 64;
17091 /* Emit stack reset code if we need it. */
17093 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
17094 sp_offset, can_use_exit);
17096 emit_insn (gen_addsi3 (gen_rtx_REG (Pmode, 11),
17098 GEN_INT (sp_offset - info->fp_size)));
17100 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
17101 info->gp_save_offset, reg_mode,
17102 /*savep=*/false, /*gpr=*/true,
17103 /*exitp=*/can_use_exit);
17107 if (info->cr_save_p)
17108 rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12),
17109 using_mtcr_multiple);
17111 emit_jump_insn (par);
17113 /* We don't want anybody else emitting things after we jumped
17120 else if (using_load_multiple)
17123 p = rtvec_alloc (32 - info->first_gp_reg_save);
17124 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17126 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17127 GEN_INT (info->gp_save_offset
17130 rtx mem = gen_frame_mem (reg_mode, addr);
17133 gen_rtx_SET (VOIDmode,
17134 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
17137 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
17141 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17142 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
17144 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17145 GEN_INT (info->gp_save_offset
17148 rtx mem = gen_frame_mem (reg_mode, addr);
17150 emit_move_insn (gen_rtx_REG (reg_mode,
17151 info->first_gp_reg_save + i), mem);
17155 /* Restore fpr's if we need to do it without calling a function. */
17156 if (restoring_FPRs_inline)
17157 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
17158 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
17159 && ! call_used_regs[info->first_fp_reg_save+i]))
17162 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17163 GEN_INT (info->fp_save_offset
17166 mem = gen_frame_mem (DFmode, addr);
17168 emit_move_insn (gen_rtx_REG (DFmode,
17169 info->first_fp_reg_save + i),
17173 /* If we saved cr, restore it here. Just those that were used. */
17174 if (info->cr_save_p)
17175 rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12), using_mtcr_multiple);
17177 /* If this is V.4, unwind the stack pointer after all of the loads
17179 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
17180 sp_offset, !restoring_FPRs_inline);
17182 if (crtl->calls_eh_return)
17184 rtx sa = EH_RETURN_STACKADJ_RTX;
17185 emit_insn (TARGET_32BIT
17186 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
17187 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
17193 if (! restoring_FPRs_inline)
17194 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
17196 p = rtvec_alloc (2);
17198 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
17199 RTVEC_ELT (p, 1) = (restoring_FPRs_inline
17200 ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65))
17201 : gen_rtx_CLOBBER (VOIDmode,
17202 gen_rtx_REG (Pmode, 65)));
17204 /* If we have to restore more than two FP registers, branch to the
17205 restore function. It will return to our caller. */
17206 if (! restoring_FPRs_inline)
17211 sym = rs6000_savres_routine_sym (info,
17215 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
17216 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
17217 gen_rtx_REG (Pmode, 11));
17218 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
17221 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
17222 GEN_INT (info->fp_save_offset + 8*i));
17223 mem = gen_frame_mem (DFmode, addr);
17225 RTVEC_ELT (p, i+4) =
17226 gen_rtx_SET (VOIDmode,
17227 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
17232 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
17236 /* Write function epilogue. */
17239 rs6000_output_function_epilogue (FILE *file,
17240 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
17242 if (! HAVE_epilogue)
17244 rtx insn = get_last_insn ();
17245 /* If the last insn was a BARRIER, we don't have to write anything except
17246 the trace table. */
17247 if (GET_CODE (insn) == NOTE)
17248 insn = prev_nonnote_insn (insn);
17249 if (insn == 0 || GET_CODE (insn) != BARRIER)
17251 /* This is slightly ugly, but at least we don't have two
17252 copies of the epilogue-emitting code. */
17255 /* A NOTE_INSN_DELETED is supposed to be at the start
17256 and end of the "toplevel" insn chain. */
17257 emit_note (NOTE_INSN_DELETED);
17258 rs6000_emit_epilogue (FALSE);
17259 emit_note (NOTE_INSN_DELETED);
17261 /* Expand INSN_ADDRESSES so final() doesn't crash. */
17265 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
17267 INSN_ADDRESSES_NEW (insn, addr);
17272 if (TARGET_DEBUG_STACK)
17273 debug_rtx_list (get_insns (), 100);
17274 final (get_insns (), file, FALSE);
17280 macho_branch_islands ();
17281 /* Mach-O doesn't support labels at the end of objects, so if
17282 it looks like we might want one, insert a NOP. */
17284 rtx insn = get_last_insn ();
17287 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
17288 insn = PREV_INSN (insn);
17292 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
17293 fputs ("\tnop\n", file);
17297 /* Output a traceback table here. See /usr/include/sys/debug.h for info
17300 We don't output a traceback table if -finhibit-size-directive was
17301 used. The documentation for -finhibit-size-directive reads
17302 ``don't output a @code{.size} assembler directive, or anything
17303 else that would cause trouble if the function is split in the
17304 middle, and the two halves are placed at locations far apart in
17305 memory.'' The traceback table has this property, since it
17306 includes the offset from the start of the function to the
17307 traceback table itself.
17309 System V.4 Powerpc's (and the embedded ABI derived from it) use a
17310 different traceback table. */
17311 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
17312 && rs6000_traceback != traceback_none && !crtl->is_thunk)
17314 const char *fname = NULL;
17315 const char *language_string = lang_hooks.name;
17316 int fixed_parms = 0, float_parms = 0, parm_info = 0;
17318 int optional_tbtab;
17319 rs6000_stack_t *info = rs6000_stack_info ();
17321 if (rs6000_traceback == traceback_full)
17322 optional_tbtab = 1;
17323 else if (rs6000_traceback == traceback_part)
17324 optional_tbtab = 0;
17326 optional_tbtab = !optimize_size && !TARGET_ELF;
17328 if (optional_tbtab)
17330 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
17331 while (*fname == '.') /* V.4 encodes . in the name */
17334 /* Need label immediately before tbtab, so we can compute
17335 its offset from the function start. */
17336 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
17337 ASM_OUTPUT_LABEL (file, fname);
17340 /* The .tbtab pseudo-op can only be used for the first eight
17341 expressions, since it can't handle the possibly variable
17342 length fields that follow. However, if you omit the optional
17343 fields, the assembler outputs zeros for all optional fields
17344 anyways, giving each variable length field is minimum length
17345 (as defined in sys/debug.h). Thus we can not use the .tbtab
17346 pseudo-op at all. */
17348 /* An all-zero word flags the start of the tbtab, for debuggers
17349 that have to find it by searching forward from the entry
17350 point or from the current pc. */
17351 fputs ("\t.long 0\n", file);
17353 /* Tbtab format type. Use format type 0. */
17354 fputs ("\t.byte 0,", file);
17356 /* Language type. Unfortunately, there does not seem to be any
17357 official way to discover the language being compiled, so we
17358 use language_string.
17359 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
17360 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
17361 a number, so for now use 9. */
17362 if (! strcmp (language_string, "GNU C"))
17364 else if (! strcmp (language_string, "GNU F77")
17365 || ! strcmp (language_string, "GNU Fortran"))
17367 else if (! strcmp (language_string, "GNU Pascal"))
17369 else if (! strcmp (language_string, "GNU Ada"))
17371 else if (! strcmp (language_string, "GNU C++")
17372 || ! strcmp (language_string, "GNU Objective-C++"))
17374 else if (! strcmp (language_string, "GNU Java"))
17376 else if (! strcmp (language_string, "GNU Objective-C"))
17379 gcc_unreachable ();
17380 fprintf (file, "%d,", i);
17382 /* 8 single bit fields: global linkage (not set for C extern linkage,
17383 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
17384 from start of procedure stored in tbtab, internal function, function
17385 has controlled storage, function has no toc, function uses fp,
17386 function logs/aborts fp operations. */
17387 /* Assume that fp operations are used if any fp reg must be saved. */
17388 fprintf (file, "%d,",
17389 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
17391 /* 6 bitfields: function is interrupt handler, name present in
17392 proc table, function calls alloca, on condition directives
17393 (controls stack walks, 3 bits), saves condition reg, saves
17395 /* The `function calls alloca' bit seems to be set whenever reg 31 is
17396 set up as a frame pointer, even when there is no alloca call. */
17397 fprintf (file, "%d,",
17398 ((optional_tbtab << 6)
17399 | ((optional_tbtab & frame_pointer_needed) << 5)
17400 | (info->cr_save_p << 1)
17401 | (info->lr_save_p)));
17403 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
17405 fprintf (file, "%d,",
17406 (info->push_p << 7) | (64 - info->first_fp_reg_save));
17408 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
17409 fprintf (file, "%d,", (32 - first_reg_to_save ()));
17411 if (optional_tbtab)
17413 /* Compute the parameter info from the function decl argument
17416 int next_parm_info_bit = 31;
17418 for (decl = DECL_ARGUMENTS (current_function_decl);
17419 decl; decl = TREE_CHAIN (decl))
17421 rtx parameter = DECL_INCOMING_RTL (decl);
17422 enum machine_mode mode = GET_MODE (parameter);
17424 if (GET_CODE (parameter) == REG)
17426 if (SCALAR_FLOAT_MODE_P (mode))
17447 gcc_unreachable ();
17450 /* If only one bit will fit, don't or in this entry. */
17451 if (next_parm_info_bit > 0)
17452 parm_info |= (bits << (next_parm_info_bit - 1));
17453 next_parm_info_bit -= 2;
17457 fixed_parms += ((GET_MODE_SIZE (mode)
17458 + (UNITS_PER_WORD - 1))
17460 next_parm_info_bit -= 1;
17466 /* Number of fixed point parameters. */
17467 /* This is actually the number of words of fixed point parameters; thus
17468 an 8 byte struct counts as 2; and thus the maximum value is 8. */
17469 fprintf (file, "%d,", fixed_parms);
17471 /* 2 bitfields: number of floating point parameters (7 bits), parameters
17473 /* This is actually the number of fp registers that hold parameters;
17474 and thus the maximum value is 13. */
17475 /* Set parameters on stack bit if parameters are not in their original
17476 registers, regardless of whether they are on the stack? Xlc
17477 seems to set the bit when not optimizing. */
17478 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
17480 if (! optional_tbtab)
17483 /* Optional fields follow. Some are variable length. */
17485 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
17486 11 double float. */
17487 /* There is an entry for each parameter in a register, in the order that
17488 they occur in the parameter list. Any intervening arguments on the
17489 stack are ignored. If the list overflows a long (max possible length
17490 34 bits) then completely leave off all elements that don't fit. */
17491 /* Only emit this long if there was at least one parameter. */
17492 if (fixed_parms || float_parms)
17493 fprintf (file, "\t.long %d\n", parm_info);
17495 /* Offset from start of code to tb table. */
17496 fputs ("\t.long ", file);
17497 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
17499 RS6000_OUTPUT_BASENAME (file, fname);
17501 assemble_name (file, fname);
17503 rs6000_output_function_entry (file, fname);
17506 /* Interrupt handler mask. */
17507 /* Omit this long, since we never set the interrupt handler bit
17510 /* Number of CTL (controlled storage) anchors. */
17511 /* Omit this long, since the has_ctl bit is never set above. */
17513 /* Displacement into stack of each CTL anchor. */
17514 /* Omit this list of longs, because there are no CTL anchors. */
17516 /* Length of function name. */
17519 fprintf (file, "\t.short %d\n", (int) strlen (fname));
17521 /* Function name. */
17522 assemble_string (fname, strlen (fname));
17524 /* Register for alloca automatic storage; this is always reg 31.
17525 Only emit this if the alloca bit was set above. */
17526 if (frame_pointer_needed)
17527 fputs ("\t.byte 31\n", file);
17529 fputs ("\t.align 2\n", file);
17533 /* A C compound statement that outputs the assembler code for a thunk
17534 function, used to implement C++ virtual function calls with
17535 multiple inheritance. The thunk acts as a wrapper around a virtual
17536 function, adjusting the implicit object parameter before handing
17537 control off to the real function.
17539 First, emit code to add the integer DELTA to the location that
17540 contains the incoming first argument. Assume that this argument
17541 contains a pointer, and is the one used to pass the `this' pointer
17542 in C++. This is the incoming argument *before* the function
17543 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17544 values of all other incoming arguments.
17546 After the addition, emit code to jump to FUNCTION, which is a
17547 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17548 not touch the return address. Hence returning from FUNCTION will
17549 return to whoever called the current `thunk'.
17551 The effect must be as if FUNCTION had been called directly with the
17552 adjusted first argument. This macro is responsible for emitting
17553 all of the code for a thunk function; output_function_prologue()
17554 and output_function_epilogue() are not invoked.
17556 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17557 been extracted from it.) It might possibly be useful on some
17558 targets, but probably not.
17560 If you do not define this macro, the target-independent code in the
17561 C++ frontend will generate a less efficient heavyweight thunk that
17562 calls FUNCTION instead of jumping to it. The generic approach does
17563 not support varargs. */
17566 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
17567 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
17570 rtx this, insn, funexp;
17572 reload_completed = 1;
17573 epilogue_completed = 1;
17575 /* Mark the end of the (empty) prologue. */
17576 emit_note (NOTE_INSN_PROLOGUE_END);
17578 /* Find the "this" pointer. If the function returns a structure,
17579 the structure return pointer is in r3. */
17580 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
17581 this = gen_rtx_REG (Pmode, 4);
17583 this = gen_rtx_REG (Pmode, 3);
17585 /* Apply the constant offset, if required. */
17588 rtx delta_rtx = GEN_INT (delta);
17589 emit_insn (TARGET_32BIT
17590 ? gen_addsi3 (this, this, delta_rtx)
17591 : gen_adddi3 (this, this, delta_rtx));
17594 /* Apply the offset from the vtable, if required. */
17597 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
17598 rtx tmp = gen_rtx_REG (Pmode, 12);
17600 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
17601 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
17603 emit_insn (TARGET_32BIT
17604 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
17605 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
17606 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
17610 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
17612 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
17614 emit_insn (TARGET_32BIT
17615 ? gen_addsi3 (this, this, tmp)
17616 : gen_adddi3 (this, this, tmp));
17619 /* Generate a tail call to the target function. */
17620 if (!TREE_USED (function))
17622 assemble_external (function);
17623 TREE_USED (function) = 1;
17625 funexp = XEXP (DECL_RTL (function), 0);
17626 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
17629 if (MACHOPIC_INDIRECT)
17630 funexp = machopic_indirect_call_target (funexp);
17633 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17634 generate sibcall RTL explicitly. */
17635 insn = emit_call_insn (
17636 gen_rtx_PARALLEL (VOIDmode,
17638 gen_rtx_CALL (VOIDmode,
17639 funexp, const0_rtx),
17640 gen_rtx_USE (VOIDmode, const0_rtx),
17641 gen_rtx_USE (VOIDmode,
17642 gen_rtx_REG (SImode,
17644 gen_rtx_RETURN (VOIDmode))));
17645 SIBLING_CALL_P (insn) = 1;
17648 /* Run just enough of rest_of_compilation to get the insns emitted.
17649 There's not really enough bulk here to make other passes such as
17650 instruction scheduling worth while. Note that use_thunk calls
17651 assemble_start_function and assemble_end_function. */
17652 insn = get_insns ();
17653 insn_locators_alloc ();
17654 shorten_branches (insn);
17655 final_start_function (insn, file, 1);
17656 final (insn, file, 1);
17657 final_end_function ();
17658 free_after_compilation (cfun);
17660 reload_completed = 0;
17661 epilogue_completed = 0;
17664 /* A quick summary of the various types of 'constant-pool tables'
17667 Target Flags Name One table per
17668 AIX (none) AIX TOC object file
17669 AIX -mfull-toc AIX TOC object file
17670 AIX -mminimal-toc AIX minimal TOC translation unit
17671 SVR4/EABI (none) SVR4 SDATA object file
17672 SVR4/EABI -fpic SVR4 pic object file
17673 SVR4/EABI -fPIC SVR4 PIC translation unit
17674 SVR4/EABI -mrelocatable EABI TOC function
17675 SVR4/EABI -maix AIX TOC object file
17676 SVR4/EABI -maix -mminimal-toc
17677 AIX minimal TOC translation unit
17679 Name Reg. Set by entries contains:
17680 made by addrs? fp? sum?
17682 AIX TOC 2 crt0 as Y option option
17683 AIX minimal TOC 30 prolog gcc Y Y option
17684 SVR4 SDATA 13 crt0 gcc N Y N
17685 SVR4 pic 30 prolog ld Y not yet N
17686 SVR4 PIC 30 prolog gcc Y option option
17687 EABI TOC 30 prolog gcc Y option option
17691 /* Hash functions for the hash table. */
17694 rs6000_hash_constant (rtx k)
17696 enum rtx_code code = GET_CODE (k);
17697 enum machine_mode mode = GET_MODE (k);
17698 unsigned result = (code << 3) ^ mode;
17699 const char *format;
17702 format = GET_RTX_FORMAT (code);
17703 flen = strlen (format);
17709 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
17712 if (mode != VOIDmode)
17713 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
17725 for (; fidx < flen; fidx++)
17726 switch (format[fidx])
17731 const char *str = XSTR (k, fidx);
17732 len = strlen (str);
17733 result = result * 613 + len;
17734 for (i = 0; i < len; i++)
17735 result = result * 613 + (unsigned) str[i];
17740 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
17744 result = result * 613 + (unsigned) XINT (k, fidx);
17747 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
17748 result = result * 613 + (unsigned) XWINT (k, fidx);
17752 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
17753 result = result * 613 + (unsigned) (XWINT (k, fidx)
17760 gcc_unreachable ();
17767 toc_hash_function (const void *hash_entry)
17769 const struct toc_hash_struct *thc =
17770 (const struct toc_hash_struct *) hash_entry;
17771 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
17774 /* Compare H1 and H2 for equivalence. */
17777 toc_hash_eq (const void *h1, const void *h2)
17779 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
17780 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
17782 if (((const struct toc_hash_struct *) h1)->key_mode
17783 != ((const struct toc_hash_struct *) h2)->key_mode)
17786 return rtx_equal_p (r1, r2);
17789 /* These are the names given by the C++ front-end to vtables, and
17790 vtable-like objects. Ideally, this logic should not be here;
17791 instead, there should be some programmatic way of inquiring as
17792 to whether or not an object is a vtable. */
17794 #define VTABLE_NAME_P(NAME) \
17795 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
17796 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
17797 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
17798 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
17799 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
17802 rs6000_output_symbol_ref (FILE *file, rtx x)
17804 /* Currently C++ toc references to vtables can be emitted before it
17805 is decided whether the vtable is public or private. If this is
17806 the case, then the linker will eventually complain that there is
17807 a reference to an unknown section. Thus, for vtables only,
17808 we emit the TOC reference to reference the symbol and not the
17810 const char *name = XSTR (x, 0);
17812 if (VTABLE_NAME_P (name))
17814 RS6000_OUTPUT_BASENAME (file, name);
17817 assemble_name (file, name);
17820 /* Output a TOC entry. We derive the entry name from what is being
17824 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
17827 const char *name = buf;
17828 const char *real_name;
17830 HOST_WIDE_INT offset = 0;
17832 gcc_assert (!TARGET_NO_TOC);
17834 /* When the linker won't eliminate them, don't output duplicate
17835 TOC entries (this happens on AIX if there is any kind of TOC,
17836 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
17838 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
17840 struct toc_hash_struct *h;
17843 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
17844 time because GGC is not initialized at that point. */
17845 if (toc_hash_table == NULL)
17846 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17847 toc_hash_eq, NULL);
17849 h = ggc_alloc (sizeof (*h));
17851 h->key_mode = mode;
17852 h->labelno = labelno;
17854 found = htab_find_slot (toc_hash_table, h, 1);
17855 if (*found == NULL)
17857 else /* This is indeed a duplicate.
17858 Set this label equal to that label. */
17860 fputs ("\t.set ", file);
17861 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17862 fprintf (file, "%d,", labelno);
17863 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17864 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
17870 /* If we're going to put a double constant in the TOC, make sure it's
17871 aligned properly when strict alignment is on. */
17872 if (GET_CODE (x) == CONST_DOUBLE
17873 && STRICT_ALIGNMENT
17874 && GET_MODE_BITSIZE (mode) >= 64
17875 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
17876 ASM_OUTPUT_ALIGN (file, 3);
17879 (*targetm.asm_out.internal_label) (file, "LC", labelno);
17881 /* Handle FP constants specially. Note that if we have a minimal
17882 TOC, things we put here aren't actually in the TOC, so we can allow
17884 if (GET_CODE (x) == CONST_DOUBLE &&
17885 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
17887 REAL_VALUE_TYPE rv;
17890 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17891 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17892 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
17894 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
17898 if (TARGET_MINIMAL_TOC)
17899 fputs (DOUBLE_INT_ASM_OP, file);
17901 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17902 k[0] & 0xffffffff, k[1] & 0xffffffff,
17903 k[2] & 0xffffffff, k[3] & 0xffffffff);
17904 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
17905 k[0] & 0xffffffff, k[1] & 0xffffffff,
17906 k[2] & 0xffffffff, k[3] & 0xffffffff);
17911 if (TARGET_MINIMAL_TOC)
17912 fputs ("\t.long ", file);
17914 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17915 k[0] & 0xffffffff, k[1] & 0xffffffff,
17916 k[2] & 0xffffffff, k[3] & 0xffffffff);
17917 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17918 k[0] & 0xffffffff, k[1] & 0xffffffff,
17919 k[2] & 0xffffffff, k[3] & 0xffffffff);
17923 else if (GET_CODE (x) == CONST_DOUBLE &&
17924 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
17926 REAL_VALUE_TYPE rv;
17929 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17931 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17932 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
17934 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
17938 if (TARGET_MINIMAL_TOC)
17939 fputs (DOUBLE_INT_ASM_OP, file);
17941 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17942 k[0] & 0xffffffff, k[1] & 0xffffffff);
17943 fprintf (file, "0x%lx%08lx\n",
17944 k[0] & 0xffffffff, k[1] & 0xffffffff);
17949 if (TARGET_MINIMAL_TOC)
17950 fputs ("\t.long ", file);
17952 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17953 k[0] & 0xffffffff, k[1] & 0xffffffff);
17954 fprintf (file, "0x%lx,0x%lx\n",
17955 k[0] & 0xffffffff, k[1] & 0xffffffff);
17959 else if (GET_CODE (x) == CONST_DOUBLE &&
17960 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
17962 REAL_VALUE_TYPE rv;
17965 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17966 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17967 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
17969 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
17973 if (TARGET_MINIMAL_TOC)
17974 fputs (DOUBLE_INT_ASM_OP, file);
17976 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17977 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
17982 if (TARGET_MINIMAL_TOC)
17983 fputs ("\t.long ", file);
17985 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17986 fprintf (file, "0x%lx\n", l & 0xffffffff);
17990 else if (GET_MODE (x) == VOIDmode
17991 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
17993 unsigned HOST_WIDE_INT low;
17994 HOST_WIDE_INT high;
17996 if (GET_CODE (x) == CONST_DOUBLE)
17998 low = CONST_DOUBLE_LOW (x);
17999 high = CONST_DOUBLE_HIGH (x);
18002 #if HOST_BITS_PER_WIDE_INT == 32
18005 high = (low & 0x80000000) ? ~0 : 0;
18009 low = INTVAL (x) & 0xffffffff;
18010 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
18014 /* TOC entries are always Pmode-sized, but since this
18015 is a bigendian machine then if we're putting smaller
18016 integer constants in the TOC we have to pad them.
18017 (This is still a win over putting the constants in
18018 a separate constant pool, because then we'd have
18019 to have both a TOC entry _and_ the actual constant.)
18021 For a 32-bit target, CONST_INT values are loaded and shifted
18022 entirely within `low' and can be stored in one TOC entry. */
18024 /* It would be easy to make this work, but it doesn't now. */
18025 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
18027 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
18029 #if HOST_BITS_PER_WIDE_INT == 32
18030 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
18031 POINTER_SIZE, &low, &high, 0);
18034 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
18035 high = (HOST_WIDE_INT) low >> 32;
18042 if (TARGET_MINIMAL_TOC)
18043 fputs (DOUBLE_INT_ASM_OP, file);
18045 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
18046 (long) high & 0xffffffff, (long) low & 0xffffffff);
18047 fprintf (file, "0x%lx%08lx\n",
18048 (long) high & 0xffffffff, (long) low & 0xffffffff);
18053 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
18055 if (TARGET_MINIMAL_TOC)
18056 fputs ("\t.long ", file);
18058 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
18059 (long) high & 0xffffffff, (long) low & 0xffffffff);
18060 fprintf (file, "0x%lx,0x%lx\n",
18061 (long) high & 0xffffffff, (long) low & 0xffffffff);
18065 if (TARGET_MINIMAL_TOC)
18066 fputs ("\t.long ", file);
18068 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
18069 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
18075 if (GET_CODE (x) == CONST)
18077 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
18079 base = XEXP (XEXP (x, 0), 0);
18080 offset = INTVAL (XEXP (XEXP (x, 0), 1));
18083 switch (GET_CODE (base))
18086 name = XSTR (base, 0);
18090 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
18091 CODE_LABEL_NUMBER (XEXP (base, 0)));
18095 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
18099 gcc_unreachable ();
18102 real_name = (*targetm.strip_name_encoding) (name);
18103 if (TARGET_MINIMAL_TOC)
18104 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
18107 fprintf (file, "\t.tc %s", real_name);
18110 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
18112 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
18114 fputs ("[TC],", file);
18117 /* Currently C++ toc references to vtables can be emitted before it
18118 is decided whether the vtable is public or private. If this is
18119 the case, then the linker will eventually complain that there is
18120 a TOC reference to an unknown section. Thus, for vtables only,
18121 we emit the TOC reference to reference the symbol and not the
18123 if (VTABLE_NAME_P (name))
18125 RS6000_OUTPUT_BASENAME (file, name);
18127 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
18128 else if (offset > 0)
18129 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
18132 output_addr_const (file, x);
18136 /* Output an assembler pseudo-op to write an ASCII string of N characters
18137 starting at P to FILE.
18139 On the RS/6000, we have to do this using the .byte operation and
18140 write out special characters outside the quoted string.
18141 Also, the assembler is broken; very long strings are truncated,
18142 so we must artificially break them up early. */
18145 output_ascii (FILE *file, const char *p, int n)
18148 int i, count_string;
18149 const char *for_string = "\t.byte \"";
18150 const char *for_decimal = "\t.byte ";
18151 const char *to_close = NULL;
18154 for (i = 0; i < n; i++)
18157 if (c >= ' ' && c < 0177)
18160 fputs (for_string, file);
18163 /* Write two quotes to get one. */
18171 for_decimal = "\"\n\t.byte ";
18175 if (count_string >= 512)
18177 fputs (to_close, file);
18179 for_string = "\t.byte \"";
18180 for_decimal = "\t.byte ";
18188 fputs (for_decimal, file);
18189 fprintf (file, "%d", c);
18191 for_string = "\n\t.byte \"";
18192 for_decimal = ", ";
18198 /* Now close the string if we have written one. Then end the line. */
18200 fputs (to_close, file);
18203 /* Generate a unique section name for FILENAME for a section type
18204 represented by SECTION_DESC. Output goes into BUF.
18206 SECTION_DESC can be any string, as long as it is different for each
18207 possible section type.
18209 We name the section in the same manner as xlc. The name begins with an
18210 underscore followed by the filename (after stripping any leading directory
18211 names) with the last period replaced by the string SECTION_DESC. If
18212 FILENAME does not contain a period, SECTION_DESC is appended to the end of
18216 rs6000_gen_section_name (char **buf, const char *filename,
18217 const char *section_desc)
18219 const char *q, *after_last_slash, *last_period = 0;
18223 after_last_slash = filename;
18224 for (q = filename; *q; q++)
18227 after_last_slash = q + 1;
18228 else if (*q == '.')
18232 len = strlen (after_last_slash) + strlen (section_desc) + 2;
18233 *buf = (char *) xmalloc (len);
18238 for (q = after_last_slash; *q; q++)
18240 if (q == last_period)
18242 strcpy (p, section_desc);
18243 p += strlen (section_desc);
18247 else if (ISALNUM (*q))
18251 if (last_period == 0)
18252 strcpy (p, section_desc);
18257 /* Emit profile function. */
18260 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
18262 /* Non-standard profiling for kernels, which just saves LR then calls
18263 _mcount without worrying about arg saves. The idea is to change
18264 the function prologue as little as possible as it isn't easy to
18265 account for arg save/restore code added just for _mcount. */
18266 if (TARGET_PROFILE_KERNEL)
18269 if (DEFAULT_ABI == ABI_AIX)
18271 #ifndef NO_PROFILE_COUNTERS
18272 # define NO_PROFILE_COUNTERS 0
18274 if (NO_PROFILE_COUNTERS)
18275 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
18279 const char *label_name;
18282 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
18283 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
18284 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
18286 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
18290 else if (DEFAULT_ABI == ABI_DARWIN)
18292 const char *mcount_name = RS6000_MCOUNT;
18293 int caller_addr_regno = LR_REGNO;
18295 /* Be conservative and always set this, at least for now. */
18296 crtl->uses_pic_offset_table = 1;
18299 /* For PIC code, set up a stub and collect the caller's address
18300 from r0, which is where the prologue puts it. */
18301 if (MACHOPIC_INDIRECT
18302 && crtl->uses_pic_offset_table)
18303 caller_addr_regno = 0;
18305 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
18307 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
18311 /* Write function profiler code. */
18314 output_function_profiler (FILE *file, int labelno)
18318 switch (DEFAULT_ABI)
18321 gcc_unreachable ();
18326 warning (0, "no profiling of 64-bit code for this ABI");
18329 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
18330 fprintf (file, "\tmflr %s\n", reg_names[0]);
18331 if (NO_PROFILE_COUNTERS)
18333 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18334 reg_names[0], reg_names[1]);
18336 else if (TARGET_SECURE_PLT && flag_pic)
18338 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
18339 reg_names[0], reg_names[1]);
18340 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
18341 asm_fprintf (file, "\t{cau|addis} %s,%s,",
18342 reg_names[12], reg_names[12]);
18343 assemble_name (file, buf);
18344 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
18345 assemble_name (file, buf);
18346 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
18348 else if (flag_pic == 1)
18350 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
18351 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18352 reg_names[0], reg_names[1]);
18353 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
18354 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
18355 assemble_name (file, buf);
18356 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
18358 else if (flag_pic > 1)
18360 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18361 reg_names[0], reg_names[1]);
18362 /* Now, we need to get the address of the label. */
18363 fputs ("\tbcl 20,31,1f\n\t.long ", file);
18364 assemble_name (file, buf);
18365 fputs ("-.\n1:", file);
18366 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
18367 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
18368 reg_names[0], reg_names[11]);
18369 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
18370 reg_names[0], reg_names[0], reg_names[11]);
18374 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
18375 assemble_name (file, buf);
18376 fputs ("@ha\n", file);
18377 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18378 reg_names[0], reg_names[1]);
18379 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
18380 assemble_name (file, buf);
18381 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
18384 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
18385 fprintf (file, "\tbl %s%s\n",
18386 RS6000_MCOUNT, flag_pic ? "@plt" : "");
18391 if (!TARGET_PROFILE_KERNEL)
18393 /* Don't do anything, done in output_profile_hook (). */
18397 gcc_assert (!TARGET_32BIT);
18399 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
18400 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
18402 if (cfun->static_chain_decl != NULL)
18404 asm_fprintf (file, "\tstd %s,24(%s)\n",
18405 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
18406 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
18407 asm_fprintf (file, "\tld %s,24(%s)\n",
18408 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
18411 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
18419 /* The following variable value is the last issued insn. */
18421 static rtx last_scheduled_insn;
18423 /* The following variable helps to balance issuing of load and
18424 store instructions */
18426 static int load_store_pendulum;
18428 /* Power4 load update and store update instructions are cracked into a
18429 load or store and an integer insn which are executed in the same cycle.
18430 Branches have their own dispatch slot which does not count against the
18431 GCC issue rate, but it changes the program flow so there are no other
18432 instructions to issue in this cycle. */
18435 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
18436 int verbose ATTRIBUTE_UNUSED,
18437 rtx insn, int more)
18439 last_scheduled_insn = insn;
18440 if (GET_CODE (PATTERN (insn)) == USE
18441 || GET_CODE (PATTERN (insn)) == CLOBBER)
18443 cached_can_issue_more = more;
18444 return cached_can_issue_more;
18447 if (insn_terminates_group_p (insn, current_group))
18449 cached_can_issue_more = 0;
18450 return cached_can_issue_more;
18453 /* If no reservation, but reach here */
18454 if (recog_memoized (insn) < 0)
18457 if (rs6000_sched_groups)
18459 if (is_microcoded_insn (insn))
18460 cached_can_issue_more = 0;
18461 else if (is_cracked_insn (insn))
18462 cached_can_issue_more = more > 2 ? more - 2 : 0;
18464 cached_can_issue_more = more - 1;
18466 return cached_can_issue_more;
18469 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
18472 cached_can_issue_more = more - 1;
18473 return cached_can_issue_more;
18476 /* Adjust the cost of a scheduling dependency. Return the new cost of
18477 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
18480 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
18482 enum attr_type attr_type;
18484 if (! recog_memoized (insn))
18487 switch (REG_NOTE_KIND (link))
18491 /* Data dependency; DEP_INSN writes a register that INSN reads
18492 some cycles later. */
18494 /* Separate a load from a narrower, dependent store. */
18495 if (rs6000_sched_groups
18496 && GET_CODE (PATTERN (insn)) == SET
18497 && GET_CODE (PATTERN (dep_insn)) == SET
18498 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
18499 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
18500 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
18501 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
18504 attr_type = get_attr_type (insn);
18509 /* Tell the first scheduling pass about the latency between
18510 a mtctr and bctr (and mtlr and br/blr). The first
18511 scheduling pass will not know about this latency since
18512 the mtctr instruction, which has the latency associated
18513 to it, will be generated by reload. */
18514 return TARGET_POWER ? 5 : 4;
18516 /* Leave some extra cycles between a compare and its
18517 dependent branch, to inhibit expensive mispredicts. */
18518 if ((rs6000_cpu_attr == CPU_PPC603
18519 || rs6000_cpu_attr == CPU_PPC604
18520 || rs6000_cpu_attr == CPU_PPC604E
18521 || rs6000_cpu_attr == CPU_PPC620
18522 || rs6000_cpu_attr == CPU_PPC630
18523 || rs6000_cpu_attr == CPU_PPC750
18524 || rs6000_cpu_attr == CPU_PPC7400
18525 || rs6000_cpu_attr == CPU_PPC7450
18526 || rs6000_cpu_attr == CPU_POWER4
18527 || rs6000_cpu_attr == CPU_POWER5
18528 || rs6000_cpu_attr == CPU_CELL)
18529 && recog_memoized (dep_insn)
18530 && (INSN_CODE (dep_insn) >= 0))
18532 switch (get_attr_type (dep_insn))
18536 case TYPE_DELAYED_COMPARE:
18537 case TYPE_IMUL_COMPARE:
18538 case TYPE_LMUL_COMPARE:
18539 case TYPE_FPCOMPARE:
18540 case TYPE_CR_LOGICAL:
18541 case TYPE_DELAYED_CR:
18550 case TYPE_STORE_UX:
18552 case TYPE_FPSTORE_U:
18553 case TYPE_FPSTORE_UX:
18554 if ((rs6000_cpu == PROCESSOR_POWER6)
18555 && recog_memoized (dep_insn)
18556 && (INSN_CODE (dep_insn) >= 0))
18559 if (GET_CODE (PATTERN (insn)) != SET)
18560 /* If this happens, we have to extend this to schedule
18561 optimally. Return default for now. */
18564 /* Adjust the cost for the case where the value written
18565 by a fixed point operation is used as the address
18566 gen value on a store. */
18567 switch (get_attr_type (dep_insn))
18574 if (! store_data_bypass_p (dep_insn, insn))
18578 case TYPE_LOAD_EXT:
18579 case TYPE_LOAD_EXT_U:
18580 case TYPE_LOAD_EXT_UX:
18581 case TYPE_VAR_SHIFT_ROTATE:
18582 case TYPE_VAR_DELAYED_COMPARE:
18584 if (! store_data_bypass_p (dep_insn, insn))
18590 case TYPE_FAST_COMPARE:
18593 case TYPE_INSERT_WORD:
18594 case TYPE_INSERT_DWORD:
18595 case TYPE_FPLOAD_U:
18596 case TYPE_FPLOAD_UX:
18598 case TYPE_STORE_UX:
18599 case TYPE_FPSTORE_U:
18600 case TYPE_FPSTORE_UX:
18602 if (! store_data_bypass_p (dep_insn, insn))
18610 case TYPE_IMUL_COMPARE:
18611 case TYPE_LMUL_COMPARE:
18613 if (! store_data_bypass_p (dep_insn, insn))
18619 if (! store_data_bypass_p (dep_insn, insn))
18625 if (! store_data_bypass_p (dep_insn, insn))
18638 case TYPE_LOAD_EXT:
18639 case TYPE_LOAD_EXT_U:
18640 case TYPE_LOAD_EXT_UX:
18641 if ((rs6000_cpu == PROCESSOR_POWER6)
18642 && recog_memoized (dep_insn)
18643 && (INSN_CODE (dep_insn) >= 0))
18646 /* Adjust the cost for the case where the value written
18647 by a fixed point instruction is used within the address
18648 gen portion of a subsequent load(u)(x) */
18649 switch (get_attr_type (dep_insn))
18656 if (set_to_load_agen (dep_insn, insn))
18660 case TYPE_LOAD_EXT:
18661 case TYPE_LOAD_EXT_U:
18662 case TYPE_LOAD_EXT_UX:
18663 case TYPE_VAR_SHIFT_ROTATE:
18664 case TYPE_VAR_DELAYED_COMPARE:
18666 if (set_to_load_agen (dep_insn, insn))
18672 case TYPE_FAST_COMPARE:
18675 case TYPE_INSERT_WORD:
18676 case TYPE_INSERT_DWORD:
18677 case TYPE_FPLOAD_U:
18678 case TYPE_FPLOAD_UX:
18680 case TYPE_STORE_UX:
18681 case TYPE_FPSTORE_U:
18682 case TYPE_FPSTORE_UX:
18684 if (set_to_load_agen (dep_insn, insn))
18692 case TYPE_IMUL_COMPARE:
18693 case TYPE_LMUL_COMPARE:
18695 if (set_to_load_agen (dep_insn, insn))
18701 if (set_to_load_agen (dep_insn, insn))
18707 if (set_to_load_agen (dep_insn, insn))
18718 if ((rs6000_cpu == PROCESSOR_POWER6)
18719 && recog_memoized (dep_insn)
18720 && (INSN_CODE (dep_insn) >= 0)
18721 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
18728 /* Fall out to return default cost. */
18732 case REG_DEP_OUTPUT:
18733 /* Output dependency; DEP_INSN writes a register that INSN writes some
18735 if ((rs6000_cpu == PROCESSOR_POWER6)
18736 && recog_memoized (dep_insn)
18737 && (INSN_CODE (dep_insn) >= 0))
18739 attr_type = get_attr_type (insn);
18744 if (get_attr_type (dep_insn) == TYPE_FP)
18748 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
18756 /* Anti dependency; DEP_INSN reads a register that INSN writes some
18761 gcc_unreachable ();
18767 /* The function returns a true if INSN is microcoded.
18768 Return false otherwise. */
18771 is_microcoded_insn (rtx insn)
18773 if (!insn || !INSN_P (insn)
18774 || GET_CODE (PATTERN (insn)) == USE
18775 || GET_CODE (PATTERN (insn)) == CLOBBER)
18778 if (rs6000_cpu_attr == CPU_CELL)
18779 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
18781 if (rs6000_sched_groups)
18783 enum attr_type type = get_attr_type (insn);
18784 if (type == TYPE_LOAD_EXT_U
18785 || type == TYPE_LOAD_EXT_UX
18786 || type == TYPE_LOAD_UX
18787 || type == TYPE_STORE_UX
18788 || type == TYPE_MFCR)
18795 /* The function returns true if INSN is cracked into 2 instructions
18796 by the processor (and therefore occupies 2 issue slots). */
18799 is_cracked_insn (rtx insn)
18801 if (!insn || !INSN_P (insn)
18802 || GET_CODE (PATTERN (insn)) == USE
18803 || GET_CODE (PATTERN (insn)) == CLOBBER)
18806 if (rs6000_sched_groups)
18808 enum attr_type type = get_attr_type (insn);
18809 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
18810 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
18811 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
18812 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
18813 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
18814 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
18815 || type == TYPE_IDIV || type == TYPE_LDIV
18816 || type == TYPE_INSERT_WORD)
18823 /* The function returns true if INSN can be issued only from
18824 the branch slot. */
18827 is_branch_slot_insn (rtx insn)
18829 if (!insn || !INSN_P (insn)
18830 || GET_CODE (PATTERN (insn)) == USE
18831 || GET_CODE (PATTERN (insn)) == CLOBBER)
18834 if (rs6000_sched_groups)
18836 enum attr_type type = get_attr_type (insn);
18837 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
18845 /* The function returns true if out_inst sets a value that is
18846 used in the address generation computation of in_insn */
18848 set_to_load_agen (rtx out_insn, rtx in_insn)
18850 rtx out_set, in_set;
18852 /* For performance reasons, only handle the simple case where
18853 both loads are a single_set. */
18854 out_set = single_set (out_insn);
18857 in_set = single_set (in_insn);
18859 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
18865 /* The function returns true if the target storage location of
18866 out_insn is adjacent to the target storage location of in_insn */
18867 /* Return 1 if memory locations are adjacent. */
18870 adjacent_mem_locations (rtx insn1, rtx insn2)
18873 rtx a = get_store_dest (PATTERN (insn1));
18874 rtx b = get_store_dest (PATTERN (insn2));
18876 if ((GET_CODE (XEXP (a, 0)) == REG
18877 || (GET_CODE (XEXP (a, 0)) == PLUS
18878 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
18879 && (GET_CODE (XEXP (b, 0)) == REG
18880 || (GET_CODE (XEXP (b, 0)) == PLUS
18881 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
18883 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
18886 if (GET_CODE (XEXP (a, 0)) == PLUS)
18888 reg0 = XEXP (XEXP (a, 0), 0);
18889 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
18892 reg0 = XEXP (a, 0);
18894 if (GET_CODE (XEXP (b, 0)) == PLUS)
18896 reg1 = XEXP (XEXP (b, 0), 0);
18897 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
18900 reg1 = XEXP (b, 0);
18902 val_diff = val1 - val0;
18904 return ((REGNO (reg0) == REGNO (reg1))
18905 && ((MEM_SIZE (a) && val_diff == INTVAL (MEM_SIZE (a)))
18906 || (MEM_SIZE (b) && val_diff == -INTVAL (MEM_SIZE (b)))));
18912 /* A C statement (sans semicolon) to update the integer scheduling
18913 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18914 INSN earlier, reduce the priority to execute INSN later. Do not
18915 define this macro if you do not need to adjust the scheduling
18916 priorities of insns. */
18919 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
18921 /* On machines (like the 750) which have asymmetric integer units,
18922 where one integer unit can do multiply and divides and the other
18923 can't, reduce the priority of multiply/divide so it is scheduled
18924 before other integer operations. */
18927 if (! INSN_P (insn))
18930 if (GET_CODE (PATTERN (insn)) == USE)
18933 switch (rs6000_cpu_attr) {
18935 switch (get_attr_type (insn))
18942 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
18943 priority, priority);
18944 if (priority >= 0 && priority < 0x01000000)
18951 if (insn_must_be_first_in_group (insn)
18952 && reload_completed
18953 && current_sched_info->sched_max_insns_priority
18954 && rs6000_sched_restricted_insns_priority)
18957 /* Prioritize insns that can be dispatched only in the first
18959 if (rs6000_sched_restricted_insns_priority == 1)
18960 /* Attach highest priority to insn. This means that in
18961 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18962 precede 'priority' (critical path) considerations. */
18963 return current_sched_info->sched_max_insns_priority;
18964 else if (rs6000_sched_restricted_insns_priority == 2)
18965 /* Increase priority of insn by a minimal amount. This means that in
18966 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18967 considerations precede dispatch-slot restriction considerations. */
18968 return (priority + 1);
18971 if (rs6000_cpu == PROCESSOR_POWER6
18972 && ((load_store_pendulum == -2 && is_load_insn (insn))
18973 || (load_store_pendulum == 2 && is_store_insn (insn))))
18974 /* Attach highest priority to insn if the scheduler has just issued two
18975 stores and this instruction is a load, or two loads and this instruction
18976 is a store. Power6 wants loads and stores scheduled alternately
18978 return current_sched_info->sched_max_insns_priority;
18983 /* Return true if the instruction is nonpipelined on the Cell. */
18985 is_nonpipeline_insn (rtx insn)
18987 enum attr_type type;
18988 if (!insn || !INSN_P (insn)
18989 || GET_CODE (PATTERN (insn)) == USE
18990 || GET_CODE (PATTERN (insn)) == CLOBBER)
18993 type = get_attr_type (insn);
18994 if (type == TYPE_IMUL
18995 || type == TYPE_IMUL2
18996 || type == TYPE_IMUL3
18997 || type == TYPE_LMUL
18998 || type == TYPE_IDIV
18999 || type == TYPE_LDIV
19000 || type == TYPE_SDIV
19001 || type == TYPE_DDIV
19002 || type == TYPE_SSQRT
19003 || type == TYPE_DSQRT
19004 || type == TYPE_MFCR
19005 || type == TYPE_MFCRF
19006 || type == TYPE_MFJMPR)
19014 /* Return how many instructions the machine can issue per cycle. */
19017 rs6000_issue_rate (void)
19019 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
19020 if (!reload_completed)
19023 switch (rs6000_cpu_attr) {
19024 case CPU_RIOS1: /* ? */
19026 case CPU_PPC601: /* ? */
19035 case CPU_PPCE300C2:
19036 case CPU_PPCE300C3:
19037 case CPU_PPCE500MC:
19054 /* Return how many instructions to look ahead for better insn
19058 rs6000_use_sched_lookahead (void)
19060 if (rs6000_cpu_attr == CPU_PPC8540)
19062 if (rs6000_cpu_attr == CPU_CELL)
19063 return (reload_completed ? 8 : 0);
19067 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
19069 rs6000_use_sched_lookahead_guard (rtx insn)
19071 if (rs6000_cpu_attr != CPU_CELL)
19074 if (insn == NULL_RTX || !INSN_P (insn))
19077 if (!reload_completed
19078 || is_nonpipeline_insn (insn)
19079 || is_microcoded_insn (insn))
19085 /* Determine is PAT refers to memory. */
19088 is_mem_ref (rtx pat)
19094 /* stack_tie does not produce any real memory traffic. */
19095 if (GET_CODE (pat) == UNSPEC
19096 && XINT (pat, 1) == UNSPEC_TIE)
19099 if (GET_CODE (pat) == MEM)
19102 /* Recursively process the pattern. */
19103 fmt = GET_RTX_FORMAT (GET_CODE (pat));
19105 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
19108 ret |= is_mem_ref (XEXP (pat, i));
19109 else if (fmt[i] == 'E')
19110 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
19111 ret |= is_mem_ref (XVECEXP (pat, i, j));
19117 /* Determine if PAT is a PATTERN of a load insn. */
19120 is_load_insn1 (rtx pat)
19122 if (!pat || pat == NULL_RTX)
19125 if (GET_CODE (pat) == SET)
19126 return is_mem_ref (SET_SRC (pat));
19128 if (GET_CODE (pat) == PARALLEL)
19132 for (i = 0; i < XVECLEN (pat, 0); i++)
19133 if (is_load_insn1 (XVECEXP (pat, 0, i)))
19140 /* Determine if INSN loads from memory. */
19143 is_load_insn (rtx insn)
19145 if (!insn || !INSN_P (insn))
19148 if (GET_CODE (insn) == CALL_INSN)
19151 return is_load_insn1 (PATTERN (insn));
19154 /* Determine if PAT is a PATTERN of a store insn. */
19157 is_store_insn1 (rtx pat)
19159 if (!pat || pat == NULL_RTX)
19162 if (GET_CODE (pat) == SET)
19163 return is_mem_ref (SET_DEST (pat));
19165 if (GET_CODE (pat) == PARALLEL)
19169 for (i = 0; i < XVECLEN (pat, 0); i++)
19170 if (is_store_insn1 (XVECEXP (pat, 0, i)))
19177 /* Determine if INSN stores to memory. */
19180 is_store_insn (rtx insn)
19182 if (!insn || !INSN_P (insn))
19185 return is_store_insn1 (PATTERN (insn));
19188 /* Return the dest of a store insn. */
19191 get_store_dest (rtx pat)
19193 gcc_assert (is_store_insn1 (pat));
19195 if (GET_CODE (pat) == SET)
19196 return SET_DEST (pat);
19197 else if (GET_CODE (pat) == PARALLEL)
19201 for (i = 0; i < XVECLEN (pat, 0); i++)
19203 rtx inner_pat = XVECEXP (pat, 0, i);
19204 if (GET_CODE (inner_pat) == SET
19205 && is_mem_ref (SET_DEST (inner_pat)))
19209 /* We shouldn't get here, because we should have either a simple
19210 store insn or a store with update which are covered above. */
19214 /* Returns whether the dependence between INSN and NEXT is considered
19215 costly by the given target. */
19218 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
19223 /* If the flag is not enabled - no dependence is considered costly;
19224 allow all dependent insns in the same group.
19225 This is the most aggressive option. */
19226 if (rs6000_sched_costly_dep == no_dep_costly)
19229 /* If the flag is set to 1 - a dependence is always considered costly;
19230 do not allow dependent instructions in the same group.
19231 This is the most conservative option. */
19232 if (rs6000_sched_costly_dep == all_deps_costly)
19235 insn = DEP_PRO (dep);
19236 next = DEP_CON (dep);
19238 if (rs6000_sched_costly_dep == store_to_load_dep_costly
19239 && is_load_insn (next)
19240 && is_store_insn (insn))
19241 /* Prevent load after store in the same group. */
19244 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
19245 && is_load_insn (next)
19246 && is_store_insn (insn)
19247 && DEP_TYPE (dep) == REG_DEP_TRUE)
19248 /* Prevent load after store in the same group if it is a true
19252 /* The flag is set to X; dependences with latency >= X are considered costly,
19253 and will not be scheduled in the same group. */
19254 if (rs6000_sched_costly_dep <= max_dep_latency
19255 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
19261 /* Return the next insn after INSN that is found before TAIL is reached,
19262 skipping any "non-active" insns - insns that will not actually occupy
19263 an issue slot. Return NULL_RTX if such an insn is not found. */
19266 get_next_active_insn (rtx insn, rtx tail)
19268 if (insn == NULL_RTX || insn == tail)
19273 insn = NEXT_INSN (insn);
19274 if (insn == NULL_RTX || insn == tail)
19279 || (NONJUMP_INSN_P (insn)
19280 && GET_CODE (PATTERN (insn)) != USE
19281 && GET_CODE (PATTERN (insn)) != CLOBBER
19282 && INSN_CODE (insn) != CODE_FOR_stack_tie))
19288 /* We are about to begin issuing insns for this clock cycle. */
19291 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
19292 rtx *ready ATTRIBUTE_UNUSED,
19293 int *pn_ready ATTRIBUTE_UNUSED,
19294 int clock_var ATTRIBUTE_UNUSED)
19296 int n_ready = *pn_ready;
19299 fprintf (dump, "// rs6000_sched_reorder :\n");
19301 /* Reorder the ready list, if the second to last ready insn
19302 is a nonepipeline insn. */
19303 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
19305 if (is_nonpipeline_insn (ready[n_ready - 1])
19306 && (recog_memoized (ready[n_ready - 2]) > 0))
19307 /* Simply swap first two insns. */
19309 rtx tmp = ready[n_ready - 1];
19310 ready[n_ready - 1] = ready[n_ready - 2];
19311 ready[n_ready - 2] = tmp;
19315 if (rs6000_cpu == PROCESSOR_POWER6)
19316 load_store_pendulum = 0;
19318 return rs6000_issue_rate ();
19321 /* Like rs6000_sched_reorder, but called after issuing each insn. */
19324 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
19325 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
19328 fprintf (dump, "// rs6000_sched_reorder2 :\n");
19330 /* For Power6, we need to handle some special cases to try and keep the
19331 store queue from overflowing and triggering expensive flushes.
19333 This code monitors how load and store instructions are being issued
19334 and skews the ready list one way or the other to increase the likelihood
19335 that a desired instruction is issued at the proper time.
19337 A couple of things are done. First, we maintain a "load_store_pendulum"
19338 to track the current state of load/store issue.
19340 - If the pendulum is at zero, then no loads or stores have been
19341 issued in the current cycle so we do nothing.
19343 - If the pendulum is 1, then a single load has been issued in this
19344 cycle and we attempt to locate another load in the ready list to
19347 - If the pendulum is -2, then two stores have already been
19348 issued in this cycle, so we increase the priority of the first load
19349 in the ready list to increase it's likelihood of being chosen first
19352 - If the pendulum is -1, then a single store has been issued in this
19353 cycle and we attempt to locate another store in the ready list to
19354 issue with it, preferring a store to an adjacent memory location to
19355 facilitate store pairing in the store queue.
19357 - If the pendulum is 2, then two loads have already been
19358 issued in this cycle, so we increase the priority of the first store
19359 in the ready list to increase it's likelihood of being chosen first
19362 - If the pendulum < -2 or > 2, then do nothing.
19364 Note: This code covers the most common scenarios. There exist non
19365 load/store instructions which make use of the LSU and which
19366 would need to be accounted for to strictly model the behavior
19367 of the machine. Those instructions are currently unaccounted
19368 for to help minimize compile time overhead of this code.
19370 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
19376 if (is_store_insn (last_scheduled_insn))
19377 /* Issuing a store, swing the load_store_pendulum to the left */
19378 load_store_pendulum--;
19379 else if (is_load_insn (last_scheduled_insn))
19380 /* Issuing a load, swing the load_store_pendulum to the right */
19381 load_store_pendulum++;
19383 return cached_can_issue_more;
19385 /* If the pendulum is balanced, or there is only one instruction on
19386 the ready list, then all is well, so return. */
19387 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
19388 return cached_can_issue_more;
19390 if (load_store_pendulum == 1)
19392 /* A load has been issued in this cycle. Scan the ready list
19393 for another load to issue with it */
19398 if (is_load_insn (ready[pos]))
19400 /* Found a load. Move it to the head of the ready list,
19401 and adjust it's priority so that it is more likely to
19404 for (i=pos; i<*pn_ready-1; i++)
19405 ready[i] = ready[i + 1];
19406 ready[*pn_ready-1] = tmp;
19407 if INSN_PRIORITY_KNOWN (tmp)
19408 INSN_PRIORITY (tmp)++;
19414 else if (load_store_pendulum == -2)
19416 /* Two stores have been issued in this cycle. Increase the
19417 priority of the first load in the ready list to favor it for
19418 issuing in the next cycle. */
19423 if (is_load_insn (ready[pos])
19424 && INSN_PRIORITY_KNOWN (ready[pos]))
19426 INSN_PRIORITY (ready[pos])++;
19428 /* Adjust the pendulum to account for the fact that a load
19429 was found and increased in priority. This is to prevent
19430 increasing the priority of multiple loads */
19431 load_store_pendulum--;
19438 else if (load_store_pendulum == -1)
19440 /* A store has been issued in this cycle. Scan the ready list for
19441 another store to issue with it, preferring a store to an adjacent
19443 int first_store_pos = -1;
19449 if (is_store_insn (ready[pos]))
19451 /* Maintain the index of the first store found on the
19453 if (first_store_pos == -1)
19454 first_store_pos = pos;
19456 if (is_store_insn (last_scheduled_insn)
19457 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
19459 /* Found an adjacent store. Move it to the head of the
19460 ready list, and adjust it's priority so that it is
19461 more likely to stay there */
19463 for (i=pos; i<*pn_ready-1; i++)
19464 ready[i] = ready[i + 1];
19465 ready[*pn_ready-1] = tmp;
19466 if INSN_PRIORITY_KNOWN (tmp)
19467 INSN_PRIORITY (tmp)++;
19468 first_store_pos = -1;
19476 if (first_store_pos >= 0)
19478 /* An adjacent store wasn't found, but a non-adjacent store was,
19479 so move the non-adjacent store to the front of the ready
19480 list, and adjust its priority so that it is more likely to
19482 tmp = ready[first_store_pos];
19483 for (i=first_store_pos; i<*pn_ready-1; i++)
19484 ready[i] = ready[i + 1];
19485 ready[*pn_ready-1] = tmp;
19486 if INSN_PRIORITY_KNOWN (tmp)
19487 INSN_PRIORITY (tmp)++;
19490 else if (load_store_pendulum == 2)
19492 /* Two loads have been issued in this cycle. Increase the priority
19493 of the first store in the ready list to favor it for issuing in
19499 if (is_store_insn (ready[pos])
19500 && INSN_PRIORITY_KNOWN (ready[pos]))
19502 INSN_PRIORITY (ready[pos])++;
19504 /* Adjust the pendulum to account for the fact that a store
19505 was found and increased in priority. This is to prevent
19506 increasing the priority of multiple stores */
19507 load_store_pendulum++;
19516 return cached_can_issue_more;
19519 /* Return whether the presence of INSN causes a dispatch group termination
19520 of group WHICH_GROUP.
19522 If WHICH_GROUP == current_group, this function will return true if INSN
19523 causes the termination of the current group (i.e, the dispatch group to
19524 which INSN belongs). This means that INSN will be the last insn in the
19525 group it belongs to.
19527 If WHICH_GROUP == previous_group, this function will return true if INSN
19528 causes the termination of the previous group (i.e, the dispatch group that
19529 precedes the group to which INSN belongs). This means that INSN will be
19530 the first insn in the group it belongs to). */
19533 insn_terminates_group_p (rtx insn, enum group_termination which_group)
19540 first = insn_must_be_first_in_group (insn);
19541 last = insn_must_be_last_in_group (insn);
19546 if (which_group == current_group)
19548 else if (which_group == previous_group)
19556 insn_must_be_first_in_group (rtx insn)
19558 enum attr_type type;
19561 || insn == NULL_RTX
19562 || GET_CODE (insn) == NOTE
19563 || GET_CODE (PATTERN (insn)) == USE
19564 || GET_CODE (PATTERN (insn)) == CLOBBER)
19567 switch (rs6000_cpu)
19569 case PROCESSOR_POWER5:
19570 if (is_cracked_insn (insn))
19572 case PROCESSOR_POWER4:
19573 if (is_microcoded_insn (insn))
19576 if (!rs6000_sched_groups)
19579 type = get_attr_type (insn);
19586 case TYPE_DELAYED_CR:
19587 case TYPE_CR_LOGICAL:
19601 case PROCESSOR_POWER6:
19602 type = get_attr_type (insn);
19606 case TYPE_INSERT_DWORD:
19610 case TYPE_VAR_SHIFT_ROTATE:
19617 case TYPE_INSERT_WORD:
19618 case TYPE_DELAYED_COMPARE:
19619 case TYPE_IMUL_COMPARE:
19620 case TYPE_LMUL_COMPARE:
19621 case TYPE_FPCOMPARE:
19632 case TYPE_LOAD_EXT_UX:
19634 case TYPE_STORE_UX:
19635 case TYPE_FPLOAD_U:
19636 case TYPE_FPLOAD_UX:
19637 case TYPE_FPSTORE_U:
19638 case TYPE_FPSTORE_UX:
19652 insn_must_be_last_in_group (rtx insn)
19654 enum attr_type type;
19657 || insn == NULL_RTX
19658 || GET_CODE (insn) == NOTE
19659 || GET_CODE (PATTERN (insn)) == USE
19660 || GET_CODE (PATTERN (insn)) == CLOBBER)
19663 switch (rs6000_cpu) {
19664 case PROCESSOR_POWER4:
19665 case PROCESSOR_POWER5:
19666 if (is_microcoded_insn (insn))
19669 if (is_branch_slot_insn (insn))
19673 case PROCESSOR_POWER6:
19674 type = get_attr_type (insn);
19681 case TYPE_VAR_SHIFT_ROTATE:
19688 case TYPE_DELAYED_COMPARE:
19689 case TYPE_IMUL_COMPARE:
19690 case TYPE_LMUL_COMPARE:
19691 case TYPE_FPCOMPARE:
19712 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19713 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
19716 is_costly_group (rtx *group_insns, rtx next_insn)
19719 int issue_rate = rs6000_issue_rate ();
19721 for (i = 0; i < issue_rate; i++)
19723 sd_iterator_def sd_it;
19725 rtx insn = group_insns[i];
19730 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
19732 rtx next = DEP_CON (dep);
19734 if (next == next_insn
19735 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
19743 /* Utility of the function redefine_groups.
19744 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
19745 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
19746 to keep it "far" (in a separate group) from GROUP_INSNS, following
19747 one of the following schemes, depending on the value of the flag
19748 -minsert_sched_nops = X:
19749 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
19750 in order to force NEXT_INSN into a separate group.
19751 (2) X < sched_finish_regroup_exact: insert exactly X nops.
19752 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
19753 insertion (has a group just ended, how many vacant issue slots remain in the
19754 last group, and how many dispatch groups were encountered so far). */
19757 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
19758 rtx next_insn, bool *group_end, int can_issue_more,
19763 int issue_rate = rs6000_issue_rate ();
19764 bool end = *group_end;
19767 if (next_insn == NULL_RTX)
19768 return can_issue_more;
19770 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
19771 return can_issue_more;
19773 force = is_costly_group (group_insns, next_insn);
19775 return can_issue_more;
19777 if (sched_verbose > 6)
19778 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
19779 *group_count ,can_issue_more);
19781 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
19784 can_issue_more = 0;
19786 /* Since only a branch can be issued in the last issue_slot, it is
19787 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
19788 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
19789 in this case the last nop will start a new group and the branch
19790 will be forced to the new group. */
19791 if (can_issue_more && !is_branch_slot_insn (next_insn))
19794 while (can_issue_more > 0)
19797 emit_insn_before (nop, next_insn);
19805 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
19807 int n_nops = rs6000_sched_insert_nops;
19809 /* Nops can't be issued from the branch slot, so the effective
19810 issue_rate for nops is 'issue_rate - 1'. */
19811 if (can_issue_more == 0)
19812 can_issue_more = issue_rate;
19814 if (can_issue_more == 0)
19816 can_issue_more = issue_rate - 1;
19819 for (i = 0; i < issue_rate; i++)
19821 group_insns[i] = 0;
19828 emit_insn_before (nop, next_insn);
19829 if (can_issue_more == issue_rate - 1) /* new group begins */
19832 if (can_issue_more == 0)
19834 can_issue_more = issue_rate - 1;
19837 for (i = 0; i < issue_rate; i++)
19839 group_insns[i] = 0;
19845 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
19848 /* Is next_insn going to start a new group? */
19851 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19852 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19853 || (can_issue_more < issue_rate &&
19854 insn_terminates_group_p (next_insn, previous_group)));
19855 if (*group_end && end)
19858 if (sched_verbose > 6)
19859 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
19860 *group_count, can_issue_more);
19861 return can_issue_more;
19864 return can_issue_more;
19867 /* This function tries to synch the dispatch groups that the compiler "sees"
19868 with the dispatch groups that the processor dispatcher is expected to
19869 form in practice. It tries to achieve this synchronization by forcing the
19870 estimated processor grouping on the compiler (as opposed to the function
19871 'pad_goups' which tries to force the scheduler's grouping on the processor).
19873 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
19874 examines the (estimated) dispatch groups that will be formed by the processor
19875 dispatcher. It marks these group boundaries to reflect the estimated
19876 processor grouping, overriding the grouping that the scheduler had marked.
19877 Depending on the value of the flag '-minsert-sched-nops' this function can
19878 force certain insns into separate groups or force a certain distance between
19879 them by inserting nops, for example, if there exists a "costly dependence"
19882 The function estimates the group boundaries that the processor will form as
19883 follows: It keeps track of how many vacant issue slots are available after
19884 each insn. A subsequent insn will start a new group if one of the following
19886 - no more vacant issue slots remain in the current dispatch group.
19887 - only the last issue slot, which is the branch slot, is vacant, but the next
19888 insn is not a branch.
19889 - only the last 2 or less issue slots, including the branch slot, are vacant,
19890 which means that a cracked insn (which occupies two issue slots) can't be
19891 issued in this group.
19892 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19893 start a new group. */
19896 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19898 rtx insn, next_insn;
19900 int can_issue_more;
19903 int group_count = 0;
19907 issue_rate = rs6000_issue_rate ();
19908 group_insns = alloca (issue_rate * sizeof (rtx));
19909 for (i = 0; i < issue_rate; i++)
19911 group_insns[i] = 0;
19913 can_issue_more = issue_rate;
19915 insn = get_next_active_insn (prev_head_insn, tail);
19918 while (insn != NULL_RTX)
19920 slot = (issue_rate - can_issue_more);
19921 group_insns[slot] = insn;
19923 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19924 if (insn_terminates_group_p (insn, current_group))
19925 can_issue_more = 0;
19927 next_insn = get_next_active_insn (insn, tail);
19928 if (next_insn == NULL_RTX)
19929 return group_count + 1;
19931 /* Is next_insn going to start a new group? */
19933 = (can_issue_more == 0
19934 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19935 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19936 || (can_issue_more < issue_rate &&
19937 insn_terminates_group_p (next_insn, previous_group)));
19939 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
19940 next_insn, &group_end, can_issue_more,
19946 can_issue_more = 0;
19947 for (i = 0; i < issue_rate; i++)
19949 group_insns[i] = 0;
19953 if (GET_MODE (next_insn) == TImode && can_issue_more)
19954 PUT_MODE (next_insn, VOIDmode);
19955 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
19956 PUT_MODE (next_insn, TImode);
19959 if (can_issue_more == 0)
19960 can_issue_more = issue_rate;
19963 return group_count;
19966 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19967 dispatch group boundaries that the scheduler had marked. Pad with nops
19968 any dispatch groups which have vacant issue slots, in order to force the
19969 scheduler's grouping on the processor dispatcher. The function
19970 returns the number of dispatch groups found. */
19973 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19975 rtx insn, next_insn;
19978 int can_issue_more;
19980 int group_count = 0;
19982 /* Initialize issue_rate. */
19983 issue_rate = rs6000_issue_rate ();
19984 can_issue_more = issue_rate;
19986 insn = get_next_active_insn (prev_head_insn, tail);
19987 next_insn = get_next_active_insn (insn, tail);
19989 while (insn != NULL_RTX)
19992 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19994 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
19996 if (next_insn == NULL_RTX)
20001 /* If the scheduler had marked group termination at this location
20002 (between insn and next_indn), and neither insn nor next_insn will
20003 force group termination, pad the group with nops to force group
20006 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
20007 && !insn_terminates_group_p (insn, current_group)
20008 && !insn_terminates_group_p (next_insn, previous_group))
20010 if (!is_branch_slot_insn (next_insn))
20013 while (can_issue_more)
20016 emit_insn_before (nop, next_insn);
20021 can_issue_more = issue_rate;
20026 next_insn = get_next_active_insn (insn, tail);
20029 return group_count;
20032 /* We're beginning a new block. Initialize data structures as necessary. */
20035 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
20036 int sched_verbose ATTRIBUTE_UNUSED,
20037 int max_ready ATTRIBUTE_UNUSED)
20039 last_scheduled_insn = NULL_RTX;
20040 load_store_pendulum = 0;
20043 /* The following function is called at the end of scheduling BB.
20044 After reload, it inserts nops at insn group bundling. */
20047 rs6000_sched_finish (FILE *dump, int sched_verbose)
20052 fprintf (dump, "=== Finishing schedule.\n");
20054 if (reload_completed && rs6000_sched_groups)
20056 if (rs6000_sched_insert_nops == sched_finish_none)
20059 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
20060 n_groups = pad_groups (dump, sched_verbose,
20061 current_sched_info->prev_head,
20062 current_sched_info->next_tail);
20064 n_groups = redefine_groups (dump, sched_verbose,
20065 current_sched_info->prev_head,
20066 current_sched_info->next_tail);
20068 if (sched_verbose >= 6)
20070 fprintf (dump, "ngroups = %d\n", n_groups);
20071 print_rtl (dump, current_sched_info->prev_head);
20072 fprintf (dump, "Done finish_sched\n");
20077 /* Length in units of the trampoline for entering a nested function. */
20080 rs6000_trampoline_size (void)
20084 switch (DEFAULT_ABI)
20087 gcc_unreachable ();
20090 ret = (TARGET_32BIT) ? 12 : 24;
20095 ret = (TARGET_32BIT) ? 40 : 48;
20102 /* Emit RTL insns to initialize the variable parts of a trampoline.
20103 FNADDR is an RTX for the address of the function's pure code.
20104 CXT is an RTX for the static chain value for the function. */
20107 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
20109 int regsize = (TARGET_32BIT) ? 4 : 8;
20110 rtx ctx_reg = force_reg (Pmode, cxt);
20112 switch (DEFAULT_ABI)
20115 gcc_unreachable ();
20117 /* Macros to shorten the code expansions below. */
20118 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
20119 #define MEM_PLUS(addr,offset) \
20120 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
20122 /* Under AIX, just build the 3 word function descriptor */
20125 rtx fn_reg = gen_reg_rtx (Pmode);
20126 rtx toc_reg = gen_reg_rtx (Pmode);
20127 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
20128 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
20129 emit_move_insn (MEM_DEREF (addr), fn_reg);
20130 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
20131 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
20135 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
20138 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
20139 FALSE, VOIDmode, 4,
20141 GEN_INT (rs6000_trampoline_size ()), SImode,
20151 /* Table of valid machine attributes. */
20153 const struct attribute_spec rs6000_attribute_table[] =
20155 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
20156 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
20157 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
20158 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
20159 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
20160 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
20161 #ifdef SUBTARGET_ATTRIBUTE_TABLE
20162 SUBTARGET_ATTRIBUTE_TABLE,
20164 { NULL, 0, 0, false, false, false, NULL }
20167 /* Handle the "altivec" attribute. The attribute may have
20168 arguments as follows:
20170 __attribute__((altivec(vector__)))
20171 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
20172 __attribute__((altivec(bool__))) (always followed by 'unsigned')
20174 and may appear more than once (e.g., 'vector bool char') in a
20175 given declaration. */
20178 rs6000_handle_altivec_attribute (tree *node,
20179 tree name ATTRIBUTE_UNUSED,
20181 int flags ATTRIBUTE_UNUSED,
20182 bool *no_add_attrs)
20184 tree type = *node, result = NULL_TREE;
20185 enum machine_mode mode;
20188 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
20189 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
20190 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
20193 while (POINTER_TYPE_P (type)
20194 || TREE_CODE (type) == FUNCTION_TYPE
20195 || TREE_CODE (type) == METHOD_TYPE
20196 || TREE_CODE (type) == ARRAY_TYPE)
20197 type = TREE_TYPE (type);
20199 mode = TYPE_MODE (type);
20201 /* Check for invalid AltiVec type qualifiers. */
20202 if (type == long_unsigned_type_node || type == long_integer_type_node)
20205 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
20206 else if (rs6000_warn_altivec_long)
20207 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
20209 else if (type == long_long_unsigned_type_node
20210 || type == long_long_integer_type_node)
20211 error ("use of %<long long%> in AltiVec types is invalid");
20212 else if (type == double_type_node)
20213 error ("use of %<double%> in AltiVec types is invalid");
20214 else if (type == long_double_type_node)
20215 error ("use of %<long double%> in AltiVec types is invalid");
20216 else if (type == boolean_type_node)
20217 error ("use of boolean types in AltiVec types is invalid");
20218 else if (TREE_CODE (type) == COMPLEX_TYPE)
20219 error ("use of %<complex%> in AltiVec types is invalid");
20220 else if (DECIMAL_FLOAT_MODE_P (mode))
20221 error ("use of decimal floating point types in AltiVec types is invalid");
20223 switch (altivec_type)
20226 unsigned_p = TYPE_UNSIGNED (type);
20230 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
20233 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
20236 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
20238 case SFmode: result = V4SF_type_node; break;
20239 /* If the user says 'vector int bool', we may be handed the 'bool'
20240 attribute _before_ the 'vector' attribute, and so select the
20241 proper type in the 'b' case below. */
20242 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
20250 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
20251 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
20252 case QImode: case V16QImode: result = bool_V16QI_type_node;
20259 case V8HImode: result = pixel_V8HI_type_node;
20265 if (result && result != type && TYPE_READONLY (type))
20266 result = build_qualified_type (result, TYPE_QUAL_CONST);
20268 *no_add_attrs = true; /* No need to hang on to the attribute. */
20271 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
20276 /* AltiVec defines four built-in scalar types that serve as vector
20277 elements; we must teach the compiler how to mangle them. */
20279 static const char *
20280 rs6000_mangle_type (const_tree type)
20282 type = TYPE_MAIN_VARIANT (type);
20284 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
20285 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
20288 if (type == bool_char_type_node) return "U6__boolc";
20289 if (type == bool_short_type_node) return "U6__bools";
20290 if (type == pixel_type_node) return "u7__pixel";
20291 if (type == bool_int_type_node) return "U6__booli";
20293 /* Mangle IBM extended float long double as `g' (__float128) on
20294 powerpc*-linux where long-double-64 previously was the default. */
20295 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
20297 && TARGET_LONG_DOUBLE_128
20298 && !TARGET_IEEEQUAD)
20301 /* For all other types, use normal C++ mangling. */
20305 /* Handle a "longcall" or "shortcall" attribute; arguments as in
20306 struct attribute_spec.handler. */
20309 rs6000_handle_longcall_attribute (tree *node, tree name,
20310 tree args ATTRIBUTE_UNUSED,
20311 int flags ATTRIBUTE_UNUSED,
20312 bool *no_add_attrs)
20314 if (TREE_CODE (*node) != FUNCTION_TYPE
20315 && TREE_CODE (*node) != FIELD_DECL
20316 && TREE_CODE (*node) != TYPE_DECL)
20318 warning (OPT_Wattributes, "%qs attribute only applies to functions",
20319 IDENTIFIER_POINTER (name));
20320 *no_add_attrs = true;
20326 /* Set longcall attributes on all functions declared when
20327 rs6000_default_long_calls is true. */
20329 rs6000_set_default_type_attributes (tree type)
20331 if (rs6000_default_long_calls
20332 && (TREE_CODE (type) == FUNCTION_TYPE
20333 || TREE_CODE (type) == METHOD_TYPE))
20334 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
20336 TYPE_ATTRIBUTES (type));
20339 darwin_set_default_type_attributes (type);
20343 /* Return a reference suitable for calling a function with the
20344 longcall attribute. */
20347 rs6000_longcall_ref (rtx call_ref)
20349 const char *call_name;
20352 if (GET_CODE (call_ref) != SYMBOL_REF)
20355 /* System V adds '.' to the internal name, so skip them. */
20356 call_name = XSTR (call_ref, 0);
20357 if (*call_name == '.')
20359 while (*call_name == '.')
20362 node = get_identifier (call_name);
20363 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
20366 return force_reg (Pmode, call_ref);
20369 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
20370 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
20373 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20374 struct attribute_spec.handler. */
20376 rs6000_handle_struct_attribute (tree *node, tree name,
20377 tree args ATTRIBUTE_UNUSED,
20378 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
20381 if (DECL_P (*node))
20383 if (TREE_CODE (*node) == TYPE_DECL)
20384 type = &TREE_TYPE (*node);
20389 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
20390 || TREE_CODE (*type) == UNION_TYPE)))
20392 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
20393 *no_add_attrs = true;
20396 else if ((is_attribute_p ("ms_struct", name)
20397 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
20398 || ((is_attribute_p ("gcc_struct", name)
20399 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
20401 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
20402 IDENTIFIER_POINTER (name));
20403 *no_add_attrs = true;
20410 rs6000_ms_bitfield_layout_p (const_tree record_type)
20412 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
20413 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
20414 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
20417 #ifdef USING_ELFOS_H
20419 /* A get_unnamed_section callback, used for switching to toc_section. */
20422 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
20424 if (DEFAULT_ABI == ABI_AIX
20425 && TARGET_MINIMAL_TOC
20426 && !TARGET_RELOCATABLE)
20428 if (!toc_initialized)
20430 toc_initialized = 1;
20431 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
20432 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
20433 fprintf (asm_out_file, "\t.tc ");
20434 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
20435 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20436 fprintf (asm_out_file, "\n");
20438 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20439 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20440 fprintf (asm_out_file, " = .+32768\n");
20443 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20445 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
20446 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
20449 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20450 if (!toc_initialized)
20452 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20453 fprintf (asm_out_file, " = .+32768\n");
20454 toc_initialized = 1;
20459 /* Implement TARGET_ASM_INIT_SECTIONS. */
20462 rs6000_elf_asm_init_sections (void)
20465 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
20468 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
20469 SDATA2_SECTION_ASM_OP);
20472 /* Implement TARGET_SELECT_RTX_SECTION. */
20475 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
20476 unsigned HOST_WIDE_INT align)
20478 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20479 return toc_section;
20481 return default_elf_select_rtx_section (mode, x, align);
20484 /* For a SYMBOL_REF, set generic flags and then perform some
20485 target-specific processing.
20487 When the AIX ABI is requested on a non-AIX system, replace the
20488 function name with the real name (with a leading .) rather than the
20489 function descriptor name. This saves a lot of overriding code to
20490 read the prefixes. */
20493 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
20495 default_encode_section_info (decl, rtl, first);
20498 && TREE_CODE (decl) == FUNCTION_DECL
20500 && DEFAULT_ABI == ABI_AIX)
20502 rtx sym_ref = XEXP (rtl, 0);
20503 size_t len = strlen (XSTR (sym_ref, 0));
20504 char *str = alloca (len + 2);
20506 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
20507 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
20512 compare_section_name (const char *section, const char *template)
20516 len = strlen (template);
20517 return (strncmp (section, template, len) == 0
20518 && (section[len] == 0 || section[len] == '.'));
20522 rs6000_elf_in_small_data_p (const_tree decl)
20524 if (rs6000_sdata == SDATA_NONE)
20527 /* We want to merge strings, so we never consider them small data. */
20528 if (TREE_CODE (decl) == STRING_CST)
20531 /* Functions are never in the small data area. */
20532 if (TREE_CODE (decl) == FUNCTION_DECL)
20535 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
20537 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
20538 if (compare_section_name (section, ".sdata")
20539 || compare_section_name (section, ".sdata2")
20540 || compare_section_name (section, ".gnu.linkonce.s")
20541 || compare_section_name (section, ".sbss")
20542 || compare_section_name (section, ".sbss2")
20543 || compare_section_name (section, ".gnu.linkonce.sb")
20544 || strcmp (section, ".PPC.EMB.sdata0") == 0
20545 || strcmp (section, ".PPC.EMB.sbss0") == 0)
20550 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
20553 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20554 /* If it's not public, and we're not going to reference it there,
20555 there's no need to put it in the small data section. */
20556 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
20563 #endif /* USING_ELFOS_H */
20565 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20568 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
20570 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
20573 /* Return a REG that occurs in ADDR with coefficient 1.
20574 ADDR can be effectively incremented by incrementing REG.
20576 r0 is special and we must not select it as an address
20577 register by this routine since our caller will try to
20578 increment the returned register via an "la" instruction. */
20581 find_addr_reg (rtx addr)
20583 while (GET_CODE (addr) == PLUS)
20585 if (GET_CODE (XEXP (addr, 0)) == REG
20586 && REGNO (XEXP (addr, 0)) != 0)
20587 addr = XEXP (addr, 0);
20588 else if (GET_CODE (XEXP (addr, 1)) == REG
20589 && REGNO (XEXP (addr, 1)) != 0)
20590 addr = XEXP (addr, 1);
20591 else if (CONSTANT_P (XEXP (addr, 0)))
20592 addr = XEXP (addr, 1);
20593 else if (CONSTANT_P (XEXP (addr, 1)))
20594 addr = XEXP (addr, 0);
20596 gcc_unreachable ();
20598 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
20603 rs6000_fatal_bad_address (rtx op)
20605 fatal_insn ("bad address", op);
20610 static tree branch_island_list = 0;
20612 /* Remember to generate a branch island for far calls to the given
20616 add_compiler_branch_island (tree label_name, tree function_name,
20619 tree branch_island = build_tree_list (function_name, label_name);
20620 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
20621 TREE_CHAIN (branch_island) = branch_island_list;
20622 branch_island_list = branch_island;
20625 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20626 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20627 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20628 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20630 /* Generate far-jump branch islands for everything on the
20631 branch_island_list. Invoked immediately after the last instruction
20632 of the epilogue has been emitted; the branch-islands must be
20633 appended to, and contiguous with, the function body. Mach-O stubs
20634 are generated in machopic_output_stub(). */
20637 macho_branch_islands (void)
20640 tree branch_island;
20642 for (branch_island = branch_island_list;
20644 branch_island = TREE_CHAIN (branch_island))
20646 const char *label =
20647 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
20649 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
20650 char name_buf[512];
20651 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
20652 if (name[0] == '*' || name[0] == '&')
20653 strcpy (name_buf, name+1);
20657 strcpy (name_buf+1, name);
20659 strcpy (tmp_buf, "\n");
20660 strcat (tmp_buf, label);
20661 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20662 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
20663 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
20664 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20667 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
20668 strcat (tmp_buf, label);
20669 strcat (tmp_buf, "_pic\n");
20670 strcat (tmp_buf, label);
20671 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
20673 strcat (tmp_buf, "\taddis r11,r11,ha16(");
20674 strcat (tmp_buf, name_buf);
20675 strcat (tmp_buf, " - ");
20676 strcat (tmp_buf, label);
20677 strcat (tmp_buf, "_pic)\n");
20679 strcat (tmp_buf, "\tmtlr r0\n");
20681 strcat (tmp_buf, "\taddi r12,r11,lo16(");
20682 strcat (tmp_buf, name_buf);
20683 strcat (tmp_buf, " - ");
20684 strcat (tmp_buf, label);
20685 strcat (tmp_buf, "_pic)\n");
20687 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
20691 strcat (tmp_buf, ":\nlis r12,hi16(");
20692 strcat (tmp_buf, name_buf);
20693 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
20694 strcat (tmp_buf, name_buf);
20695 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
20697 output_asm_insn (tmp_buf, 0);
20698 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20699 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
20700 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
20701 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20704 branch_island_list = 0;
20707 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
20708 already there or not. */
20711 no_previous_def (tree function_name)
20713 tree branch_island;
20714 for (branch_island = branch_island_list;
20716 branch_island = TREE_CHAIN (branch_island))
20717 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
20722 /* GET_PREV_LABEL gets the label name from the previous definition of
20726 get_prev_label (tree function_name)
20728 tree branch_island;
20729 for (branch_island = branch_island_list;
20731 branch_island = TREE_CHAIN (branch_island))
20732 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
20733 return BRANCH_ISLAND_LABEL_NAME (branch_island);
20737 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
20738 #define DARWIN_LINKER_GENERATES_ISLANDS 0
20741 /* KEXTs still need branch islands. */
20742 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
20743 || flag_mkernel || flag_apple_kext)
20745 /* INSN is either a function call or a millicode call. It may have an
20746 unconditional jump in its delay slot.
20748 CALL_DEST is the routine we are calling. */
20751 output_call (rtx insn, rtx *operands, int dest_operand_number,
20752 int cookie_operand_number)
20754 static char buf[256];
20755 if (DARWIN_GENERATE_ISLANDS
20756 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
20757 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
20760 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
20762 if (no_previous_def (funname))
20764 rtx label_rtx = gen_label_rtx ();
20765 char *label_buf, temp_buf[256];
20766 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
20767 CODE_LABEL_NUMBER (label_rtx));
20768 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
20769 labelname = get_identifier (label_buf);
20770 add_compiler_branch_island (labelname, funname, insn_line (insn));
20773 labelname = get_prev_label (funname);
20775 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
20776 instruction will reach 'foo', otherwise link as 'bl L42'".
20777 "L42" should be a 'branch island', that will do a far jump to
20778 'foo'. Branch islands are generated in
20779 macho_branch_islands(). */
20780 sprintf (buf, "jbsr %%z%d,%.246s",
20781 dest_operand_number, IDENTIFIER_POINTER (labelname));
20784 sprintf (buf, "bl %%z%d", dest_operand_number);
20788 /* Generate PIC and indirect symbol stubs. */
20791 machopic_output_stub (FILE *file, const char *symb, const char *stub)
20793 unsigned int length;
20794 char *symbol_name, *lazy_ptr_name;
20795 char *local_label_0;
20796 static int label = 0;
20798 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20799 symb = (*targetm.strip_name_encoding) (symb);
20802 length = strlen (symb);
20803 symbol_name = alloca (length + 32);
20804 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
20806 lazy_ptr_name = alloca (length + 32);
20807 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
20810 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
20812 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
20816 fprintf (file, "\t.align 5\n");
20818 fprintf (file, "%s:\n", stub);
20819 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20822 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
20823 sprintf (local_label_0, "\"L%011d$spb\"", label);
20825 fprintf (file, "\tmflr r0\n");
20826 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
20827 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
20828 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
20829 lazy_ptr_name, local_label_0);
20830 fprintf (file, "\tmtlr r0\n");
20831 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
20832 (TARGET_64BIT ? "ldu" : "lwzu"),
20833 lazy_ptr_name, local_label_0);
20834 fprintf (file, "\tmtctr r12\n");
20835 fprintf (file, "\tbctr\n");
20839 fprintf (file, "\t.align 4\n");
20841 fprintf (file, "%s:\n", stub);
20842 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20844 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
20845 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
20846 (TARGET_64BIT ? "ldu" : "lwzu"),
20848 fprintf (file, "\tmtctr r12\n");
20849 fprintf (file, "\tbctr\n");
20852 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
20853 fprintf (file, "%s:\n", lazy_ptr_name);
20854 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20855 fprintf (file, "%sdyld_stub_binding_helper\n",
20856 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
20859 /* Legitimize PIC addresses. If the address is already
20860 position-independent, we return ORIG. Newly generated
20861 position-independent addresses go into a reg. This is REG if non
20862 zero, otherwise we allocate register(s) as necessary. */
20864 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
20867 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
20872 if (reg == NULL && ! reload_in_progress && ! reload_completed)
20873 reg = gen_reg_rtx (Pmode);
20875 if (GET_CODE (orig) == CONST)
20879 if (GET_CODE (XEXP (orig, 0)) == PLUS
20880 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
20883 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
20885 /* Use a different reg for the intermediate value, as
20886 it will be marked UNCHANGING. */
20887 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
20888 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
20891 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
20894 if (GET_CODE (offset) == CONST_INT)
20896 if (SMALL_INT (offset))
20897 return plus_constant (base, INTVAL (offset));
20898 else if (! reload_in_progress && ! reload_completed)
20899 offset = force_reg (Pmode, offset);
20902 rtx mem = force_const_mem (Pmode, orig);
20903 return machopic_legitimize_pic_address (mem, Pmode, reg);
20906 return gen_rtx_PLUS (Pmode, base, offset);
20909 /* Fall back on generic machopic code. */
20910 return machopic_legitimize_pic_address (orig, mode, reg);
20913 /* Output a .machine directive for the Darwin assembler, and call
20914 the generic start_file routine. */
20917 rs6000_darwin_file_start (void)
20919 static const struct
20925 { "ppc64", "ppc64", MASK_64BIT },
20926 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
20927 { "power4", "ppc970", 0 },
20928 { "G5", "ppc970", 0 },
20929 { "7450", "ppc7450", 0 },
20930 { "7400", "ppc7400", MASK_ALTIVEC },
20931 { "G4", "ppc7400", 0 },
20932 { "750", "ppc750", 0 },
20933 { "740", "ppc750", 0 },
20934 { "G3", "ppc750", 0 },
20935 { "604e", "ppc604e", 0 },
20936 { "604", "ppc604", 0 },
20937 { "603e", "ppc603", 0 },
20938 { "603", "ppc603", 0 },
20939 { "601", "ppc601", 0 },
20940 { NULL, "ppc", 0 } };
20941 const char *cpu_id = "";
20944 rs6000_file_start ();
20945 darwin_file_start ();
20947 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20948 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
20949 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
20950 && rs6000_select[i].string[0] != '\0')
20951 cpu_id = rs6000_select[i].string;
20953 /* Look through the mapping array. Pick the first name that either
20954 matches the argument, has a bit set in IF_SET that is also set
20955 in the target flags, or has a NULL name. */
20958 while (mapping[i].arg != NULL
20959 && strcmp (mapping[i].arg, cpu_id) != 0
20960 && (mapping[i].if_set & target_flags) == 0)
20963 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
20966 #endif /* TARGET_MACHO */
20970 rs6000_elf_reloc_rw_mask (void)
20974 else if (DEFAULT_ABI == ABI_AIX)
20980 /* Record an element in the table of global constructors. SYMBOL is
20981 a SYMBOL_REF of the function to be called; PRIORITY is a number
20982 between 0 and MAX_INIT_PRIORITY.
20984 This differs from default_named_section_asm_out_constructor in
20985 that we have special handling for -mrelocatable. */
20988 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
20990 const char *section = ".ctors";
20993 if (priority != DEFAULT_INIT_PRIORITY)
20995 sprintf (buf, ".ctors.%.5u",
20996 /* Invert the numbering so the linker puts us in the proper
20997 order; constructors are run from right to left, and the
20998 linker sorts in increasing order. */
20999 MAX_INIT_PRIORITY - priority);
21003 switch_to_section (get_section (section, SECTION_WRITE, NULL));
21004 assemble_align (POINTER_SIZE);
21006 if (TARGET_RELOCATABLE)
21008 fputs ("\t.long (", asm_out_file);
21009 output_addr_const (asm_out_file, symbol);
21010 fputs (")@fixup\n", asm_out_file);
21013 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
21017 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
21019 const char *section = ".dtors";
21022 if (priority != DEFAULT_INIT_PRIORITY)
21024 sprintf (buf, ".dtors.%.5u",
21025 /* Invert the numbering so the linker puts us in the proper
21026 order; constructors are run from right to left, and the
21027 linker sorts in increasing order. */
21028 MAX_INIT_PRIORITY - priority);
21032 switch_to_section (get_section (section, SECTION_WRITE, NULL));
21033 assemble_align (POINTER_SIZE);
21035 if (TARGET_RELOCATABLE)
21037 fputs ("\t.long (", asm_out_file);
21038 output_addr_const (asm_out_file, symbol);
21039 fputs (")@fixup\n", asm_out_file);
21042 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
21046 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
21050 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
21051 ASM_OUTPUT_LABEL (file, name);
21052 fputs (DOUBLE_INT_ASM_OP, file);
21053 rs6000_output_function_entry (file, name);
21054 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
21057 fputs ("\t.size\t", file);
21058 assemble_name (file, name);
21059 fputs (",24\n\t.type\t.", file);
21060 assemble_name (file, name);
21061 fputs (",@function\n", file);
21062 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
21064 fputs ("\t.globl\t.", file);
21065 assemble_name (file, name);
21070 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
21071 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
21072 rs6000_output_function_entry (file, name);
21073 fputs (":\n", file);
21077 if (TARGET_RELOCATABLE
21078 && !TARGET_SECURE_PLT
21079 && (get_pool_size () != 0 || crtl->profile)
21084 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
21086 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
21087 fprintf (file, "\t.long ");
21088 assemble_name (file, buf);
21090 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
21091 assemble_name (file, buf);
21095 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
21096 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
21098 if (DEFAULT_ABI == ABI_AIX)
21100 const char *desc_name, *orig_name;
21102 orig_name = (*targetm.strip_name_encoding) (name);
21103 desc_name = orig_name;
21104 while (*desc_name == '.')
21107 if (TREE_PUBLIC (decl))
21108 fprintf (file, "\t.globl %s\n", desc_name);
21110 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
21111 fprintf (file, "%s:\n", desc_name);
21112 fprintf (file, "\t.long %s\n", orig_name);
21113 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
21114 if (DEFAULT_ABI == ABI_AIX)
21115 fputs ("\t.long 0\n", file);
21116 fprintf (file, "\t.previous\n");
21118 ASM_OUTPUT_LABEL (file, name);
21122 rs6000_elf_end_indicate_exec_stack (void)
21125 file_end_indicate_exec_stack ();
21131 rs6000_xcoff_asm_output_anchor (rtx symbol)
21135 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
21136 SYMBOL_REF_BLOCK_OFFSET (symbol));
21137 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
21141 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
21143 fputs (GLOBAL_ASM_OP, stream);
21144 RS6000_OUTPUT_BASENAME (stream, name);
21145 putc ('\n', stream);
21148 /* A get_unnamed_decl callback, used for read-only sections. PTR
21149 points to the section string variable. */
21152 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
21154 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
21155 *(const char *const *) directive,
21156 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
21159 /* Likewise for read-write sections. */
21162 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
21164 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
21165 *(const char *const *) directive,
21166 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
21169 /* A get_unnamed_section callback, used for switching to toc_section. */
21172 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
21174 if (TARGET_MINIMAL_TOC)
21176 /* toc_section is always selected at least once from
21177 rs6000_xcoff_file_start, so this is guaranteed to
21178 always be defined once and only once in each file. */
21179 if (!toc_initialized)
21181 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
21182 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
21183 toc_initialized = 1;
21185 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
21186 (TARGET_32BIT ? "" : ",3"));
21189 fputs ("\t.toc\n", asm_out_file);
21192 /* Implement TARGET_ASM_INIT_SECTIONS. */
21195 rs6000_xcoff_asm_init_sections (void)
21197 read_only_data_section
21198 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
21199 &xcoff_read_only_section_name);
21201 private_data_section
21202 = get_unnamed_section (SECTION_WRITE,
21203 rs6000_xcoff_output_readwrite_section_asm_op,
21204 &xcoff_private_data_section_name);
21206 read_only_private_data_section
21207 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
21208 &xcoff_private_data_section_name);
21211 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
21213 readonly_data_section = read_only_data_section;
21214 exception_section = data_section;
21218 rs6000_xcoff_reloc_rw_mask (void)
21224 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
21225 tree decl ATTRIBUTE_UNUSED)
21228 static const char * const suffix[3] = { "PR", "RO", "RW" };
21230 if (flags & SECTION_CODE)
21232 else if (flags & SECTION_WRITE)
21237 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
21238 (flags & SECTION_CODE) ? "." : "",
21239 name, suffix[smclass], flags & SECTION_ENTSIZE);
21243 rs6000_xcoff_select_section (tree decl, int reloc,
21244 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
21246 if (decl_readonly_section (decl, reloc))
21248 if (TREE_PUBLIC (decl))
21249 return read_only_data_section;
21251 return read_only_private_data_section;
21255 if (TREE_PUBLIC (decl))
21256 return data_section;
21258 return private_data_section;
21263 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
21267 /* Use select_section for private and uninitialized data. */
21268 if (!TREE_PUBLIC (decl)
21269 || DECL_COMMON (decl)
21270 || DECL_INITIAL (decl) == NULL_TREE
21271 || DECL_INITIAL (decl) == error_mark_node
21272 || (flag_zero_initialized_in_bss
21273 && initializer_zerop (DECL_INITIAL (decl))))
21276 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
21277 name = (*targetm.strip_name_encoding) (name);
21278 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
21281 /* Select section for constant in constant pool.
21283 On RS/6000, all constants are in the private read-only data area.
21284 However, if this is being placed in the TOC it must be output as a
21288 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
21289 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
21291 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
21292 return toc_section;
21294 return read_only_private_data_section;
21297 /* Remove any trailing [DS] or the like from the symbol name. */
21299 static const char *
21300 rs6000_xcoff_strip_name_encoding (const char *name)
21305 len = strlen (name);
21306 if (name[len - 1] == ']')
21307 return ggc_alloc_string (name, len - 4);
21312 /* Section attributes. AIX is always PIC. */
21314 static unsigned int
21315 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
21317 unsigned int align;
21318 unsigned int flags = default_section_type_flags (decl, name, reloc);
21320 /* Align to at least UNIT size. */
21321 if (flags & SECTION_CODE)
21322 align = MIN_UNITS_PER_WORD;
21324 /* Increase alignment of large objects if not already stricter. */
21325 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
21326 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
21327 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
21329 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
21332 /* Output at beginning of assembler file.
21334 Initialize the section names for the RS/6000 at this point.
21336 Specify filename, including full path, to assembler.
21338 We want to go into the TOC section so at least one .toc will be emitted.
21339 Also, in order to output proper .bs/.es pairs, we need at least one static
21340 [RW] section emitted.
21342 Finally, declare mcount when profiling to make the assembler happy. */
21345 rs6000_xcoff_file_start (void)
21347 rs6000_gen_section_name (&xcoff_bss_section_name,
21348 main_input_filename, ".bss_");
21349 rs6000_gen_section_name (&xcoff_private_data_section_name,
21350 main_input_filename, ".rw_");
21351 rs6000_gen_section_name (&xcoff_read_only_section_name,
21352 main_input_filename, ".ro_");
21354 fputs ("\t.file\t", asm_out_file);
21355 output_quoted_string (asm_out_file, main_input_filename);
21356 fputc ('\n', asm_out_file);
21357 if (write_symbols != NO_DEBUG)
21358 switch_to_section (private_data_section);
21359 switch_to_section (text_section);
21361 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
21362 rs6000_file_start ();
21365 /* Output at end of assembler file.
21366 On the RS/6000, referencing data should automatically pull in text. */
21369 rs6000_xcoff_file_end (void)
21371 switch_to_section (text_section);
21372 fputs ("_section_.text:\n", asm_out_file);
21373 switch_to_section (data_section);
21374 fputs (TARGET_32BIT
21375 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
21378 #endif /* TARGET_XCOFF */
21380 /* Compute a (partial) cost for rtx X. Return true if the complete
21381 cost has been computed, and false if subexpressions should be
21382 scanned. In either case, *TOTAL contains the cost result. */
21385 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
21387 enum machine_mode mode = GET_MODE (x);
21391 /* On the RS/6000, if it is valid in the insn, it is free. */
21393 if (((outer_code == SET
21394 || outer_code == PLUS
21395 || outer_code == MINUS)
21396 && (satisfies_constraint_I (x)
21397 || satisfies_constraint_L (x)))
21398 || (outer_code == AND
21399 && (satisfies_constraint_K (x)
21401 ? satisfies_constraint_L (x)
21402 : satisfies_constraint_J (x))
21403 || mask_operand (x, mode)
21405 && mask64_operand (x, DImode))))
21406 || ((outer_code == IOR || outer_code == XOR)
21407 && (satisfies_constraint_K (x)
21409 ? satisfies_constraint_L (x)
21410 : satisfies_constraint_J (x))))
21411 || outer_code == ASHIFT
21412 || outer_code == ASHIFTRT
21413 || outer_code == LSHIFTRT
21414 || outer_code == ROTATE
21415 || outer_code == ROTATERT
21416 || outer_code == ZERO_EXTRACT
21417 || (outer_code == MULT
21418 && satisfies_constraint_I (x))
21419 || ((outer_code == DIV || outer_code == UDIV
21420 || outer_code == MOD || outer_code == UMOD)
21421 && exact_log2 (INTVAL (x)) >= 0)
21422 || (outer_code == COMPARE
21423 && (satisfies_constraint_I (x)
21424 || satisfies_constraint_K (x)))
21425 || (outer_code == EQ
21426 && (satisfies_constraint_I (x)
21427 || satisfies_constraint_K (x)
21429 ? satisfies_constraint_L (x)
21430 : satisfies_constraint_J (x))))
21431 || (outer_code == GTU
21432 && satisfies_constraint_I (x))
21433 || (outer_code == LTU
21434 && satisfies_constraint_P (x)))
21439 else if ((outer_code == PLUS
21440 && reg_or_add_cint_operand (x, VOIDmode))
21441 || (outer_code == MINUS
21442 && reg_or_sub_cint_operand (x, VOIDmode))
21443 || ((outer_code == SET
21444 || outer_code == IOR
21445 || outer_code == XOR)
21447 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
21449 *total = COSTS_N_INSNS (1);
21455 if (mode == DImode && code == CONST_DOUBLE)
21457 if ((outer_code == IOR || outer_code == XOR)
21458 && CONST_DOUBLE_HIGH (x) == 0
21459 && (CONST_DOUBLE_LOW (x)
21460 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
21465 else if ((outer_code == AND && and64_2_operand (x, DImode))
21466 || ((outer_code == SET
21467 || outer_code == IOR
21468 || outer_code == XOR)
21469 && CONST_DOUBLE_HIGH (x) == 0))
21471 *total = COSTS_N_INSNS (1);
21481 /* When optimizing for size, MEM should be slightly more expensive
21482 than generating address, e.g., (plus (reg) (const)).
21483 L1 cache latency is about two instructions. */
21484 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
21492 if (mode == DFmode)
21494 if (GET_CODE (XEXP (x, 0)) == MULT)
21496 /* FNMA accounted in outer NEG. */
21497 if (outer_code == NEG)
21498 *total = rs6000_cost->dmul - rs6000_cost->fp;
21500 *total = rs6000_cost->dmul;
21503 *total = rs6000_cost->fp;
21505 else if (mode == SFmode)
21507 /* FNMA accounted in outer NEG. */
21508 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21511 *total = rs6000_cost->fp;
21514 *total = COSTS_N_INSNS (1);
21518 if (mode == DFmode)
21520 if (GET_CODE (XEXP (x, 0)) == MULT
21521 || GET_CODE (XEXP (x, 1)) == MULT)
21523 /* FNMA accounted in outer NEG. */
21524 if (outer_code == NEG)
21525 *total = rs6000_cost->dmul - rs6000_cost->fp;
21527 *total = rs6000_cost->dmul;
21530 *total = rs6000_cost->fp;
21532 else if (mode == SFmode)
21534 /* FNMA accounted in outer NEG. */
21535 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21538 *total = rs6000_cost->fp;
21541 *total = COSTS_N_INSNS (1);
21545 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21546 && satisfies_constraint_I (XEXP (x, 1)))
21548 if (INTVAL (XEXP (x, 1)) >= -256
21549 && INTVAL (XEXP (x, 1)) <= 255)
21550 *total = rs6000_cost->mulsi_const9;
21552 *total = rs6000_cost->mulsi_const;
21554 /* FMA accounted in outer PLUS/MINUS. */
21555 else if ((mode == DFmode || mode == SFmode)
21556 && (outer_code == PLUS || outer_code == MINUS))
21558 else if (mode == DFmode)
21559 *total = rs6000_cost->dmul;
21560 else if (mode == SFmode)
21561 *total = rs6000_cost->fp;
21562 else if (mode == DImode)
21563 *total = rs6000_cost->muldi;
21565 *total = rs6000_cost->mulsi;
21570 if (FLOAT_MODE_P (mode))
21572 *total = mode == DFmode ? rs6000_cost->ddiv
21573 : rs6000_cost->sdiv;
21580 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21581 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
21583 if (code == DIV || code == MOD)
21585 *total = COSTS_N_INSNS (2);
21588 *total = COSTS_N_INSNS (1);
21592 if (GET_MODE (XEXP (x, 1)) == DImode)
21593 *total = rs6000_cost->divdi;
21595 *total = rs6000_cost->divsi;
21597 /* Add in shift and subtract for MOD. */
21598 if (code == MOD || code == UMOD)
21599 *total += COSTS_N_INSNS (2);
21604 *total = COSTS_N_INSNS (4);
21608 *total = COSTS_N_INSNS (6);
21612 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
21624 *total = COSTS_N_INSNS (1);
21632 /* Handle mul_highpart. */
21633 if (outer_code == TRUNCATE
21634 && GET_CODE (XEXP (x, 0)) == MULT)
21636 if (mode == DImode)
21637 *total = rs6000_cost->muldi;
21639 *total = rs6000_cost->mulsi;
21642 else if (outer_code == AND)
21645 *total = COSTS_N_INSNS (1);
21650 if (GET_CODE (XEXP (x, 0)) == MEM)
21653 *total = COSTS_N_INSNS (1);
21659 if (!FLOAT_MODE_P (mode))
21661 *total = COSTS_N_INSNS (1);
21667 case UNSIGNED_FLOAT:
21670 case FLOAT_TRUNCATE:
21671 *total = rs6000_cost->fp;
21675 if (mode == DFmode)
21678 *total = rs6000_cost->fp;
21682 switch (XINT (x, 1))
21685 *total = rs6000_cost->fp;
21697 *total = COSTS_N_INSNS (1);
21700 else if (FLOAT_MODE_P (mode)
21701 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
21703 *total = rs6000_cost->fp;
21711 /* Carry bit requires mode == Pmode.
21712 NEG or PLUS already counted so only add one. */
21714 && (outer_code == NEG || outer_code == PLUS))
21716 *total = COSTS_N_INSNS (1);
21719 if (outer_code == SET)
21721 if (XEXP (x, 1) == const0_rtx)
21723 *total = COSTS_N_INSNS (2);
21726 else if (mode == Pmode)
21728 *total = COSTS_N_INSNS (3);
21737 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
21739 *total = COSTS_N_INSNS (2);
21743 if (outer_code == COMPARE)
21757 /* A C expression returning the cost of moving data from a register of class
21758 CLASS1 to one of CLASS2. */
21761 rs6000_register_move_cost (enum machine_mode mode,
21762 enum reg_class from, enum reg_class to)
21764 /* Moves from/to GENERAL_REGS. */
21765 if (reg_classes_intersect_p (to, GENERAL_REGS)
21766 || reg_classes_intersect_p (from, GENERAL_REGS))
21768 if (! reg_classes_intersect_p (to, GENERAL_REGS))
21771 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
21772 return (rs6000_memory_move_cost (mode, from, 0)
21773 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
21775 /* It's more expensive to move CR_REGS than CR0_REGS because of the
21777 else if (from == CR_REGS)
21780 /* Power6 has slower LR/CTR moves so make them more expensive than
21781 memory in order to bias spills to memory .*/
21782 else if (rs6000_cpu == PROCESSOR_POWER6
21783 && reg_classes_intersect_p (from, LINK_OR_CTR_REGS))
21784 return 6 * hard_regno_nregs[0][mode];
21787 /* A move will cost one instruction per GPR moved. */
21788 return 2 * hard_regno_nregs[0][mode];
21791 /* Moving between two similar registers is just one instruction. */
21792 else if (reg_classes_intersect_p (to, from))
21793 return (mode == TFmode || mode == TDmode) ? 4 : 2;
21795 /* Everything else has to go through GENERAL_REGS. */
21797 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
21798 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
21801 /* A C expressions returning the cost of moving data of MODE from a register to
21805 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
21806 int in ATTRIBUTE_UNUSED)
21808 if (reg_classes_intersect_p (class, GENERAL_REGS))
21809 return 4 * hard_regno_nregs[0][mode];
21810 else if (reg_classes_intersect_p (class, FLOAT_REGS))
21811 return 4 * hard_regno_nregs[32][mode];
21812 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
21813 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
21815 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
21818 /* Returns a code for a target-specific builtin that implements
21819 reciprocal of the function, or NULL_TREE if not available. */
21822 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
21823 bool sqrt ATTRIBUTE_UNUSED)
21825 if (! (TARGET_RECIP && TARGET_PPC_GFXOPT && !optimize_size
21826 && flag_finite_math_only && !flag_trapping_math
21827 && flag_unsafe_math_optimizations))
21835 case BUILT_IN_SQRTF:
21836 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
21843 /* Newton-Raphson approximation of single-precision floating point divide n/d.
21844 Assumes no trapping math and finite arguments. */
21847 rs6000_emit_swdivsf (rtx dst, rtx n, rtx d)
21849 rtx x0, e0, e1, y1, u0, v0, one;
21851 x0 = gen_reg_rtx (SFmode);
21852 e0 = gen_reg_rtx (SFmode);
21853 e1 = gen_reg_rtx (SFmode);
21854 y1 = gen_reg_rtx (SFmode);
21855 u0 = gen_reg_rtx (SFmode);
21856 v0 = gen_reg_rtx (SFmode);
21857 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21859 /* x0 = 1./d estimate */
21860 emit_insn (gen_rtx_SET (VOIDmode, x0,
21861 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
21863 /* e0 = 1. - d * x0 */
21864 emit_insn (gen_rtx_SET (VOIDmode, e0,
21865 gen_rtx_MINUS (SFmode, one,
21866 gen_rtx_MULT (SFmode, d, x0))));
21867 /* e1 = e0 + e0 * e0 */
21868 emit_insn (gen_rtx_SET (VOIDmode, e1,
21869 gen_rtx_PLUS (SFmode,
21870 gen_rtx_MULT (SFmode, e0, e0), e0)));
21871 /* y1 = x0 + e1 * x0 */
21872 emit_insn (gen_rtx_SET (VOIDmode, y1,
21873 gen_rtx_PLUS (SFmode,
21874 gen_rtx_MULT (SFmode, e1, x0), x0)));
21876 emit_insn (gen_rtx_SET (VOIDmode, u0,
21877 gen_rtx_MULT (SFmode, n, y1)));
21878 /* v0 = n - d * u0 */
21879 emit_insn (gen_rtx_SET (VOIDmode, v0,
21880 gen_rtx_MINUS (SFmode, n,
21881 gen_rtx_MULT (SFmode, d, u0))));
21882 /* dst = u0 + v0 * y1 */
21883 emit_insn (gen_rtx_SET (VOIDmode, dst,
21884 gen_rtx_PLUS (SFmode,
21885 gen_rtx_MULT (SFmode, v0, y1), u0)));
21888 /* Newton-Raphson approximation of double-precision floating point divide n/d.
21889 Assumes no trapping math and finite arguments. */
21892 rs6000_emit_swdivdf (rtx dst, rtx n, rtx d)
21894 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
21896 x0 = gen_reg_rtx (DFmode);
21897 e0 = gen_reg_rtx (DFmode);
21898 e1 = gen_reg_rtx (DFmode);
21899 e2 = gen_reg_rtx (DFmode);
21900 y1 = gen_reg_rtx (DFmode);
21901 y2 = gen_reg_rtx (DFmode);
21902 y3 = gen_reg_rtx (DFmode);
21903 u0 = gen_reg_rtx (DFmode);
21904 v0 = gen_reg_rtx (DFmode);
21905 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
21907 /* x0 = 1./d estimate */
21908 emit_insn (gen_rtx_SET (VOIDmode, x0,
21909 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
21911 /* e0 = 1. - d * x0 */
21912 emit_insn (gen_rtx_SET (VOIDmode, e0,
21913 gen_rtx_MINUS (DFmode, one,
21914 gen_rtx_MULT (SFmode, d, x0))));
21915 /* y1 = x0 + e0 * x0 */
21916 emit_insn (gen_rtx_SET (VOIDmode, y1,
21917 gen_rtx_PLUS (DFmode,
21918 gen_rtx_MULT (DFmode, e0, x0), x0)));
21920 emit_insn (gen_rtx_SET (VOIDmode, e1,
21921 gen_rtx_MULT (DFmode, e0, e0)));
21922 /* y2 = y1 + e1 * y1 */
21923 emit_insn (gen_rtx_SET (VOIDmode, y2,
21924 gen_rtx_PLUS (DFmode,
21925 gen_rtx_MULT (DFmode, e1, y1), y1)));
21927 emit_insn (gen_rtx_SET (VOIDmode, e2,
21928 gen_rtx_MULT (DFmode, e1, e1)));
21929 /* y3 = y2 + e2 * y2 */
21930 emit_insn (gen_rtx_SET (VOIDmode, y3,
21931 gen_rtx_PLUS (DFmode,
21932 gen_rtx_MULT (DFmode, e2, y2), y2)));
21934 emit_insn (gen_rtx_SET (VOIDmode, u0,
21935 gen_rtx_MULT (DFmode, n, y3)));
21936 /* v0 = n - d * u0 */
21937 emit_insn (gen_rtx_SET (VOIDmode, v0,
21938 gen_rtx_MINUS (DFmode, n,
21939 gen_rtx_MULT (DFmode, d, u0))));
21940 /* dst = u0 + v0 * y3 */
21941 emit_insn (gen_rtx_SET (VOIDmode, dst,
21942 gen_rtx_PLUS (DFmode,
21943 gen_rtx_MULT (DFmode, v0, y3), u0)));
21947 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21948 Assumes no trapping math and finite arguments. */
21951 rs6000_emit_swrsqrtsf (rtx dst, rtx src)
21953 rtx x0, x1, x2, y1, u0, u1, u2, v0, v1, v2, t0,
21954 half, one, halfthree, c1, cond, label;
21956 x0 = gen_reg_rtx (SFmode);
21957 x1 = gen_reg_rtx (SFmode);
21958 x2 = gen_reg_rtx (SFmode);
21959 y1 = gen_reg_rtx (SFmode);
21960 u0 = gen_reg_rtx (SFmode);
21961 u1 = gen_reg_rtx (SFmode);
21962 u2 = gen_reg_rtx (SFmode);
21963 v0 = gen_reg_rtx (SFmode);
21964 v1 = gen_reg_rtx (SFmode);
21965 v2 = gen_reg_rtx (SFmode);
21966 t0 = gen_reg_rtx (SFmode);
21967 halfthree = gen_reg_rtx (SFmode);
21968 cond = gen_rtx_REG (CCFPmode, CR1_REGNO);
21969 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
21971 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
21972 emit_insn (gen_rtx_SET (VOIDmode, t0,
21973 gen_rtx_MULT (SFmode, src, src)));
21975 emit_insn (gen_rtx_SET (VOIDmode, cond,
21976 gen_rtx_COMPARE (CCFPmode, t0, src)));
21977 c1 = gen_rtx_EQ (VOIDmode, cond, const0_rtx);
21978 emit_unlikely_jump (c1, label);
21980 half = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode));
21981 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21983 /* halfthree = 1.5 = 1.0 + 0.5 */
21984 emit_insn (gen_rtx_SET (VOIDmode, halfthree,
21985 gen_rtx_PLUS (SFmode, one, half)));
21987 /* x0 = rsqrt estimate */
21988 emit_insn (gen_rtx_SET (VOIDmode, x0,
21989 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, src),
21992 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
21993 emit_insn (gen_rtx_SET (VOIDmode, y1,
21994 gen_rtx_MINUS (SFmode,
21995 gen_rtx_MULT (SFmode, src, halfthree),
21998 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
21999 emit_insn (gen_rtx_SET (VOIDmode, u0,
22000 gen_rtx_MULT (SFmode, x0, x0)));
22001 emit_insn (gen_rtx_SET (VOIDmode, v0,
22002 gen_rtx_MINUS (SFmode,
22004 gen_rtx_MULT (SFmode, y1, u0))));
22005 emit_insn (gen_rtx_SET (VOIDmode, x1,
22006 gen_rtx_MULT (SFmode, x0, v0)));
22008 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
22009 emit_insn (gen_rtx_SET (VOIDmode, u1,
22010 gen_rtx_MULT (SFmode, x1, x1)));
22011 emit_insn (gen_rtx_SET (VOIDmode, v1,
22012 gen_rtx_MINUS (SFmode,
22014 gen_rtx_MULT (SFmode, y1, u1))));
22015 emit_insn (gen_rtx_SET (VOIDmode, x2,
22016 gen_rtx_MULT (SFmode, x1, v1)));
22018 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
22019 emit_insn (gen_rtx_SET (VOIDmode, u2,
22020 gen_rtx_MULT (SFmode, x2, x2)));
22021 emit_insn (gen_rtx_SET (VOIDmode, v2,
22022 gen_rtx_MINUS (SFmode,
22024 gen_rtx_MULT (SFmode, y1, u2))));
22025 emit_insn (gen_rtx_SET (VOIDmode, dst,
22026 gen_rtx_MULT (SFmode, x2, v2)));
22028 emit_label (XEXP (label, 0));
22031 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
22032 target, and SRC is the argument operand. */
22035 rs6000_emit_popcount (rtx dst, rtx src)
22037 enum machine_mode mode = GET_MODE (dst);
22040 tmp1 = gen_reg_rtx (mode);
22042 if (mode == SImode)
22044 emit_insn (gen_popcntbsi2 (tmp1, src));
22045 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
22047 tmp2 = force_reg (SImode, tmp2);
22048 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
22052 emit_insn (gen_popcntbdi2 (tmp1, src));
22053 tmp2 = expand_mult (DImode, tmp1,
22054 GEN_INT ((HOST_WIDE_INT)
22055 0x01010101 << 32 | 0x01010101),
22057 tmp2 = force_reg (DImode, tmp2);
22058 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
22063 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
22064 target, and SRC is the argument operand. */
22067 rs6000_emit_parity (rtx dst, rtx src)
22069 enum machine_mode mode = GET_MODE (dst);
22072 tmp = gen_reg_rtx (mode);
22073 if (mode == SImode)
22075 /* Is mult+shift >= shift+xor+shift+xor? */
22076 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
22078 rtx tmp1, tmp2, tmp3, tmp4;
22080 tmp1 = gen_reg_rtx (SImode);
22081 emit_insn (gen_popcntbsi2 (tmp1, src));
22083 tmp2 = gen_reg_rtx (SImode);
22084 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
22085 tmp3 = gen_reg_rtx (SImode);
22086 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
22088 tmp4 = gen_reg_rtx (SImode);
22089 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
22090 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
22093 rs6000_emit_popcount (tmp, src);
22094 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
22098 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
22099 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
22101 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
22103 tmp1 = gen_reg_rtx (DImode);
22104 emit_insn (gen_popcntbdi2 (tmp1, src));
22106 tmp2 = gen_reg_rtx (DImode);
22107 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
22108 tmp3 = gen_reg_rtx (DImode);
22109 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
22111 tmp4 = gen_reg_rtx (DImode);
22112 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
22113 tmp5 = gen_reg_rtx (DImode);
22114 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
22116 tmp6 = gen_reg_rtx (DImode);
22117 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
22118 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
22121 rs6000_emit_popcount (tmp, src);
22122 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
22126 /* Return an RTX representing where to find the function value of a
22127 function returning MODE. */
22129 rs6000_complex_function_value (enum machine_mode mode)
22131 unsigned int regno;
22133 enum machine_mode inner = GET_MODE_INNER (mode);
22134 unsigned int inner_bytes = GET_MODE_SIZE (inner);
22136 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22137 regno = FP_ARG_RETURN;
22140 regno = GP_ARG_RETURN;
22142 /* 32-bit is OK since it'll go in r3/r4. */
22143 if (TARGET_32BIT && inner_bytes >= 4)
22144 return gen_rtx_REG (mode, regno);
22147 if (inner_bytes >= 8)
22148 return gen_rtx_REG (mode, regno);
22150 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
22152 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
22153 GEN_INT (inner_bytes));
22154 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
22157 /* Define how to find the value returned by a function.
22158 VALTYPE is the data type of the value (as a tree).
22159 If the precise function being called is known, FUNC is its FUNCTION_DECL;
22160 otherwise, FUNC is 0.
22162 On the SPE, both FPs and vectors are returned in r3.
22164 On RS/6000 an integer value is in r3 and a floating-point value is in
22165 fp1, unless -msoft-float. */
22168 rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
22170 enum machine_mode mode;
22171 unsigned int regno;
22173 /* Special handling for structs in darwin64. */
22174 if (rs6000_darwin64_abi
22175 && TYPE_MODE (valtype) == BLKmode
22176 && TREE_CODE (valtype) == RECORD_TYPE
22177 && int_size_in_bytes (valtype) > 0)
22179 CUMULATIVE_ARGS valcum;
22183 valcum.fregno = FP_ARG_MIN_REG;
22184 valcum.vregno = ALTIVEC_ARG_MIN_REG;
22185 /* Do a trial code generation as if this were going to be passed as
22186 an argument; if any part goes in memory, we return NULL. */
22187 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
22190 /* Otherwise fall through to standard ABI rules. */
22193 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
22195 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22196 return gen_rtx_PARALLEL (DImode,
22198 gen_rtx_EXPR_LIST (VOIDmode,
22199 gen_rtx_REG (SImode, GP_ARG_RETURN),
22201 gen_rtx_EXPR_LIST (VOIDmode,
22202 gen_rtx_REG (SImode,
22203 GP_ARG_RETURN + 1),
22206 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
22208 return gen_rtx_PARALLEL (DCmode,
22210 gen_rtx_EXPR_LIST (VOIDmode,
22211 gen_rtx_REG (SImode, GP_ARG_RETURN),
22213 gen_rtx_EXPR_LIST (VOIDmode,
22214 gen_rtx_REG (SImode,
22215 GP_ARG_RETURN + 1),
22217 gen_rtx_EXPR_LIST (VOIDmode,
22218 gen_rtx_REG (SImode,
22219 GP_ARG_RETURN + 2),
22221 gen_rtx_EXPR_LIST (VOIDmode,
22222 gen_rtx_REG (SImode,
22223 GP_ARG_RETURN + 3),
22227 mode = TYPE_MODE (valtype);
22228 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
22229 || POINTER_TYPE_P (valtype))
22230 mode = TARGET_32BIT ? SImode : DImode;
22232 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22233 /* _Decimal128 must use an even/odd register pair. */
22234 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
22235 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
22236 regno = FP_ARG_RETURN;
22237 else if (TREE_CODE (valtype) == COMPLEX_TYPE
22238 && targetm.calls.split_complex_arg)
22239 return rs6000_complex_function_value (mode);
22240 else if (TREE_CODE (valtype) == VECTOR_TYPE
22241 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
22242 && ALTIVEC_VECTOR_MODE (mode))
22243 regno = ALTIVEC_ARG_RETURN;
22244 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
22245 && (mode == DFmode || mode == DCmode
22246 || mode == TFmode || mode == TCmode))
22247 return spe_build_register_parallel (mode, GP_ARG_RETURN);
22249 regno = GP_ARG_RETURN;
22251 return gen_rtx_REG (mode, regno);
22254 /* Define how to find the value returned by a library function
22255 assuming the value has mode MODE. */
22257 rs6000_libcall_value (enum machine_mode mode)
22259 unsigned int regno;
22261 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
22263 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22264 return gen_rtx_PARALLEL (DImode,
22266 gen_rtx_EXPR_LIST (VOIDmode,
22267 gen_rtx_REG (SImode, GP_ARG_RETURN),
22269 gen_rtx_EXPR_LIST (VOIDmode,
22270 gen_rtx_REG (SImode,
22271 GP_ARG_RETURN + 1),
22275 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22276 /* _Decimal128 must use an even/odd register pair. */
22277 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
22278 else if (SCALAR_FLOAT_MODE_P (mode)
22279 && TARGET_HARD_FLOAT && TARGET_FPRS)
22280 regno = FP_ARG_RETURN;
22281 else if (ALTIVEC_VECTOR_MODE (mode)
22282 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
22283 regno = ALTIVEC_ARG_RETURN;
22284 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
22285 return rs6000_complex_function_value (mode);
22286 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
22287 && (mode == DFmode || mode == DCmode
22288 || mode == TFmode || mode == TCmode))
22289 return spe_build_register_parallel (mode, GP_ARG_RETURN);
22291 regno = GP_ARG_RETURN;
22293 return gen_rtx_REG (mode, regno);
22296 /* Define the offset between two registers, FROM to be eliminated and its
22297 replacement TO, at the start of a routine. */
22299 rs6000_initial_elimination_offset (int from, int to)
22301 rs6000_stack_t *info = rs6000_stack_info ();
22302 HOST_WIDE_INT offset;
22304 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22305 offset = info->push_p ? 0 : -info->total_size;
22306 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22308 offset = info->push_p ? 0 : -info->total_size;
22309 if (FRAME_GROWS_DOWNWARD)
22310 offset += info->fixed_size + info->vars_size + info->parm_size;
22312 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
22313 offset = FRAME_GROWS_DOWNWARD
22314 ? info->fixed_size + info->vars_size + info->parm_size
22316 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
22317 offset = info->total_size;
22318 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22319 offset = info->push_p ? info->total_size : 0;
22320 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
22323 gcc_unreachable ();
22328 /* Return true if TYPE is a SPE or AltiVec opaque type. */
22331 rs6000_is_opaque_type (const_tree type)
22333 return (type == opaque_V2SI_type_node
22334 || type == opaque_V2SF_type_node
22335 || type == opaque_p_V2SI_type_node
22336 || type == opaque_V4SI_type_node);
22340 rs6000_dwarf_register_span (rtx reg)
22345 && (SPE_VECTOR_MODE (GET_MODE (reg))
22346 || (TARGET_E500_DOUBLE
22347 && (GET_MODE (reg) == DFmode || GET_MODE (reg) == DDmode))))
22352 regno = REGNO (reg);
22354 /* The duality of the SPE register size wreaks all kinds of havoc.
22355 This is a way of distinguishing r0 in 32-bits from r0 in
22358 gen_rtx_PARALLEL (VOIDmode,
22361 gen_rtx_REG (SImode, regno + 1200),
22362 gen_rtx_REG (SImode, regno))
22364 gen_rtx_REG (SImode, regno),
22365 gen_rtx_REG (SImode, regno + 1200)));
22368 /* Fill in sizes for SPE register high parts in table used by unwinder. */
22371 rs6000_init_dwarf_reg_sizes_extra (tree address)
22376 enum machine_mode mode = TYPE_MODE (char_type_node);
22377 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
22378 rtx mem = gen_rtx_MEM (BLKmode, addr);
22379 rtx value = gen_int_mode (4, mode);
22381 for (i = 1201; i < 1232; i++)
22383 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
22384 HOST_WIDE_INT offset
22385 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
22387 emit_move_insn (adjust_address (mem, mode, offset), value);
22392 /* Map internal gcc register numbers to DWARF2 register numbers. */
22395 rs6000_dbx_register_number (unsigned int regno)
22397 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
22399 if (regno == MQ_REGNO)
22401 if (regno == LR_REGNO)
22403 if (regno == CTR_REGNO)
22405 if (CR_REGNO_P (regno))
22406 return regno - CR0_REGNO + 86;
22407 if (regno == XER_REGNO)
22409 if (ALTIVEC_REGNO_P (regno))
22410 return regno - FIRST_ALTIVEC_REGNO + 1124;
22411 if (regno == VRSAVE_REGNO)
22413 if (regno == VSCR_REGNO)
22415 if (regno == SPE_ACC_REGNO)
22417 if (regno == SPEFSCR_REGNO)
22419 /* SPE high reg number. We get these values of regno from
22420 rs6000_dwarf_register_span. */
22421 gcc_assert (regno >= 1200 && regno < 1232);
22425 /* target hook eh_return_filter_mode */
22426 static enum machine_mode
22427 rs6000_eh_return_filter_mode (void)
22429 return TARGET_32BIT ? SImode : word_mode;
22432 /* Target hook for scalar_mode_supported_p. */
22434 rs6000_scalar_mode_supported_p (enum machine_mode mode)
22436 if (DECIMAL_FLOAT_MODE_P (mode))
22439 return default_scalar_mode_supported_p (mode);
22442 /* Target hook for vector_mode_supported_p. */
22444 rs6000_vector_mode_supported_p (enum machine_mode mode)
22447 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
22450 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
22453 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
22460 /* Target hook for invalid_arg_for_unprototyped_fn. */
22461 static const char *
22462 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
22464 return (!rs6000_darwin64_abi
22466 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
22467 && (funcdecl == NULL_TREE
22468 || (TREE_CODE (funcdecl) == FUNCTION_DECL
22469 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
22470 ? N_("AltiVec argument passed to unprototyped function")
22474 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
22475 setup by using __stack_chk_fail_local hidden function instead of
22476 calling __stack_chk_fail directly. Otherwise it is better to call
22477 __stack_chk_fail directly. */
22480 rs6000_stack_protect_fail (void)
22482 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
22483 ? default_hidden_stack_protect_fail ()
22484 : default_external_stack_protect_fail ();
22487 #include "gt-rs6000.h"