1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 /* Always emit branch hint bits. */
142 static GTY(()) bool rs6000_always_hint;
144 /* Schedule instructions for group formation. */
145 static GTY(()) bool rs6000_sched_groups;
147 /* Support for -msched-costly-dep option. */
148 const char *rs6000_sched_costly_dep_str;
149 enum rs6000_dependence_cost rs6000_sched_costly_dep;
151 /* Support for -minsert-sched-nops option. */
152 const char *rs6000_sched_insert_nops_str;
153 enum rs6000_nop_insertion rs6000_sched_insert_nops;
155 /* Support targetm.vectorize.builtin_mask_for_load. */
156 static GTY(()) tree altivec_builtin_mask_for_load;
158 /* Size of long double. */
159 int rs6000_long_double_type_size;
161 /* IEEE quad extended precision long double. */
164 /* Whether -mabi=altivec has appeared. */
165 int rs6000_altivec_abi;
167 /* Nonzero if we want SPE ABI extensions. */
170 /* Nonzero if floating point operations are done in the GPRs. */
171 int rs6000_float_gprs = 0;
173 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
174 int rs6000_darwin64_abi;
176 /* Set to nonzero once AIX common-mode calls have been defined. */
177 static GTY(()) int common_mode_defined;
179 /* Save information from a "cmpxx" operation until the branch or scc is
181 rtx rs6000_compare_op0, rs6000_compare_op1;
182 int rs6000_compare_fp_p;
184 /* Label number of label created for -mrelocatable, to call to so we can
185 get the address of the GOT section */
186 int rs6000_pic_labelno;
189 /* Which abi to adhere to */
190 const char *rs6000_abi_name;
192 /* Semantics of the small data area */
193 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
195 /* Which small data model to use */
196 const char *rs6000_sdata_name = (char *)0;
198 /* Counter for labels which are to be placed in .fixup. */
199 int fixuplabelno = 0;
202 /* Bit size of immediate TLS offsets and string from which it is decoded. */
203 int rs6000_tls_size = 32;
204 const char *rs6000_tls_size_string;
206 /* ABI enumeration available for subtarget to use. */
207 enum rs6000_abi rs6000_current_abi;
209 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
213 const char *rs6000_debug_name;
214 int rs6000_debug_stack; /* debug stack applications */
215 int rs6000_debug_arg; /* debug argument handling */
217 /* Value is TRUE if register/mode pair is acceptable. */
218 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
220 /* Built in types. */
222 tree rs6000_builtin_types[RS6000_BTI_MAX];
223 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
225 const char *rs6000_traceback_name;
227 traceback_default = 0,
233 /* Flag to say the TOC is initialized */
235 char toc_label_name[10];
237 static GTY(()) section *read_only_data_section;
238 static GTY(()) section *private_data_section;
239 static GTY(()) section *read_only_private_data_section;
240 static GTY(()) section *sdata2_section;
241 static GTY(()) section *toc_section;
243 /* Control alignment for fields within structures. */
244 /* String from -malign-XXXXX. */
245 int rs6000_alignment_flags;
247 /* True for any options that were explicitly set. */
249 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
250 bool alignment; /* True if -malign- was used. */
251 bool abi; /* True if -mabi= was used. */
252 bool spe; /* True if -mspe= was used. */
253 bool float_gprs; /* True if -mfloat-gprs= was used. */
254 bool isel; /* True if -misel was used. */
255 bool long_double; /* True if -mlong-double- was used. */
256 } rs6000_explicit_options;
258 struct builtin_description
260 /* mask is not const because we're going to alter it below. This
261 nonsense will go away when we rewrite the -march infrastructure
262 to give us more target flag bits. */
264 const enum insn_code icode;
265 const char *const name;
266 const enum rs6000_builtins code;
269 /* Target cpu costs. */
271 struct processor_costs {
272 const int mulsi; /* cost of SImode multiplication. */
273 const int mulsi_const; /* cost of SImode multiplication by constant. */
274 const int mulsi_const9; /* cost of SImode mult by short constant. */
275 const int muldi; /* cost of DImode multiplication. */
276 const int divsi; /* cost of SImode division. */
277 const int divdi; /* cost of DImode division. */
278 const int fp; /* cost of simple SFmode and DFmode insns. */
279 const int dmul; /* cost of DFmode multiplication (and fmadd). */
280 const int sdiv; /* cost of SFmode division (fdivs). */
281 const int ddiv; /* cost of DFmode division (fdiv). */
284 const struct processor_costs *rs6000_cost;
286 /* Processor costs (relative to an add) */
288 /* Instruction size costs on 32bit processors. */
290 struct processor_costs size32_cost = {
291 COSTS_N_INSNS (1), /* mulsi */
292 COSTS_N_INSNS (1), /* mulsi_const */
293 COSTS_N_INSNS (1), /* mulsi_const9 */
294 COSTS_N_INSNS (1), /* muldi */
295 COSTS_N_INSNS (1), /* divsi */
296 COSTS_N_INSNS (1), /* divdi */
297 COSTS_N_INSNS (1), /* fp */
298 COSTS_N_INSNS (1), /* dmul */
299 COSTS_N_INSNS (1), /* sdiv */
300 COSTS_N_INSNS (1), /* ddiv */
303 /* Instruction size costs on 64bit processors. */
305 struct processor_costs size64_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
318 /* Instruction costs on RIOS1 processors. */
320 struct processor_costs rios1_cost = {
321 COSTS_N_INSNS (5), /* mulsi */
322 COSTS_N_INSNS (4), /* mulsi_const */
323 COSTS_N_INSNS (3), /* mulsi_const9 */
324 COSTS_N_INSNS (5), /* muldi */
325 COSTS_N_INSNS (19), /* divsi */
326 COSTS_N_INSNS (19), /* divdi */
327 COSTS_N_INSNS (2), /* fp */
328 COSTS_N_INSNS (2), /* dmul */
329 COSTS_N_INSNS (19), /* sdiv */
330 COSTS_N_INSNS (19), /* ddiv */
333 /* Instruction costs on RIOS2 processors. */
335 struct processor_costs rios2_cost = {
336 COSTS_N_INSNS (2), /* mulsi */
337 COSTS_N_INSNS (2), /* mulsi_const */
338 COSTS_N_INSNS (2), /* mulsi_const9 */
339 COSTS_N_INSNS (2), /* muldi */
340 COSTS_N_INSNS (13), /* divsi */
341 COSTS_N_INSNS (13), /* divdi */
342 COSTS_N_INSNS (2), /* fp */
343 COSTS_N_INSNS (2), /* dmul */
344 COSTS_N_INSNS (17), /* sdiv */
345 COSTS_N_INSNS (17), /* ddiv */
348 /* Instruction costs on RS64A processors. */
350 struct processor_costs rs64a_cost = {
351 COSTS_N_INSNS (20), /* mulsi */
352 COSTS_N_INSNS (12), /* mulsi_const */
353 COSTS_N_INSNS (8), /* mulsi_const9 */
354 COSTS_N_INSNS (34), /* muldi */
355 COSTS_N_INSNS (65), /* divsi */
356 COSTS_N_INSNS (67), /* divdi */
357 COSTS_N_INSNS (4), /* fp */
358 COSTS_N_INSNS (4), /* dmul */
359 COSTS_N_INSNS (31), /* sdiv */
360 COSTS_N_INSNS (31), /* ddiv */
363 /* Instruction costs on MPCCORE processors. */
365 struct processor_costs mpccore_cost = {
366 COSTS_N_INSNS (2), /* mulsi */
367 COSTS_N_INSNS (2), /* mulsi_const */
368 COSTS_N_INSNS (2), /* mulsi_const9 */
369 COSTS_N_INSNS (2), /* muldi */
370 COSTS_N_INSNS (6), /* divsi */
371 COSTS_N_INSNS (6), /* divdi */
372 COSTS_N_INSNS (4), /* fp */
373 COSTS_N_INSNS (5), /* dmul */
374 COSTS_N_INSNS (10), /* sdiv */
375 COSTS_N_INSNS (17), /* ddiv */
378 /* Instruction costs on PPC403 processors. */
380 struct processor_costs ppc403_cost = {
381 COSTS_N_INSNS (4), /* mulsi */
382 COSTS_N_INSNS (4), /* mulsi_const */
383 COSTS_N_INSNS (4), /* mulsi_const9 */
384 COSTS_N_INSNS (4), /* muldi */
385 COSTS_N_INSNS (33), /* divsi */
386 COSTS_N_INSNS (33), /* divdi */
387 COSTS_N_INSNS (11), /* fp */
388 COSTS_N_INSNS (11), /* dmul */
389 COSTS_N_INSNS (11), /* sdiv */
390 COSTS_N_INSNS (11), /* ddiv */
393 /* Instruction costs on PPC405 processors. */
395 struct processor_costs ppc405_cost = {
396 COSTS_N_INSNS (5), /* mulsi */
397 COSTS_N_INSNS (4), /* mulsi_const */
398 COSTS_N_INSNS (3), /* mulsi_const9 */
399 COSTS_N_INSNS (5), /* muldi */
400 COSTS_N_INSNS (35), /* divsi */
401 COSTS_N_INSNS (35), /* divdi */
402 COSTS_N_INSNS (11), /* fp */
403 COSTS_N_INSNS (11), /* dmul */
404 COSTS_N_INSNS (11), /* sdiv */
405 COSTS_N_INSNS (11), /* ddiv */
408 /* Instruction costs on PPC440 processors. */
410 struct processor_costs ppc440_cost = {
411 COSTS_N_INSNS (3), /* mulsi */
412 COSTS_N_INSNS (2), /* mulsi_const */
413 COSTS_N_INSNS (2), /* mulsi_const9 */
414 COSTS_N_INSNS (3), /* muldi */
415 COSTS_N_INSNS (34), /* divsi */
416 COSTS_N_INSNS (34), /* divdi */
417 COSTS_N_INSNS (5), /* fp */
418 COSTS_N_INSNS (5), /* dmul */
419 COSTS_N_INSNS (19), /* sdiv */
420 COSTS_N_INSNS (33), /* ddiv */
423 /* Instruction costs on PPC601 processors. */
425 struct processor_costs ppc601_cost = {
426 COSTS_N_INSNS (5), /* mulsi */
427 COSTS_N_INSNS (5), /* mulsi_const */
428 COSTS_N_INSNS (5), /* mulsi_const9 */
429 COSTS_N_INSNS (5), /* muldi */
430 COSTS_N_INSNS (36), /* divsi */
431 COSTS_N_INSNS (36), /* divdi */
432 COSTS_N_INSNS (4), /* fp */
433 COSTS_N_INSNS (5), /* dmul */
434 COSTS_N_INSNS (17), /* sdiv */
435 COSTS_N_INSNS (31), /* ddiv */
438 /* Instruction costs on PPC603 processors. */
440 struct processor_costs ppc603_cost = {
441 COSTS_N_INSNS (5), /* mulsi */
442 COSTS_N_INSNS (3), /* mulsi_const */
443 COSTS_N_INSNS (2), /* mulsi_const9 */
444 COSTS_N_INSNS (5), /* muldi */
445 COSTS_N_INSNS (37), /* divsi */
446 COSTS_N_INSNS (37), /* divdi */
447 COSTS_N_INSNS (3), /* fp */
448 COSTS_N_INSNS (4), /* dmul */
449 COSTS_N_INSNS (18), /* sdiv */
450 COSTS_N_INSNS (33), /* ddiv */
453 /* Instruction costs on PPC604 processors. */
455 struct processor_costs ppc604_cost = {
456 COSTS_N_INSNS (4), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (4), /* mulsi_const9 */
459 COSTS_N_INSNS (4), /* muldi */
460 COSTS_N_INSNS (20), /* divsi */
461 COSTS_N_INSNS (20), /* divdi */
462 COSTS_N_INSNS (3), /* fp */
463 COSTS_N_INSNS (3), /* dmul */
464 COSTS_N_INSNS (18), /* sdiv */
465 COSTS_N_INSNS (32), /* ddiv */
468 /* Instruction costs on PPC604e processors. */
470 struct processor_costs ppc604e_cost = {
471 COSTS_N_INSNS (2), /* mulsi */
472 COSTS_N_INSNS (2), /* mulsi_const */
473 COSTS_N_INSNS (2), /* mulsi_const9 */
474 COSTS_N_INSNS (2), /* muldi */
475 COSTS_N_INSNS (20), /* divsi */
476 COSTS_N_INSNS (20), /* divdi */
477 COSTS_N_INSNS (3), /* fp */
478 COSTS_N_INSNS (3), /* dmul */
479 COSTS_N_INSNS (18), /* sdiv */
480 COSTS_N_INSNS (32), /* ddiv */
483 /* Instruction costs on PPC620 processors. */
485 struct processor_costs ppc620_cost = {
486 COSTS_N_INSNS (5), /* mulsi */
487 COSTS_N_INSNS (4), /* mulsi_const */
488 COSTS_N_INSNS (3), /* mulsi_const9 */
489 COSTS_N_INSNS (7), /* muldi */
490 COSTS_N_INSNS (21), /* divsi */
491 COSTS_N_INSNS (37), /* divdi */
492 COSTS_N_INSNS (3), /* fp */
493 COSTS_N_INSNS (3), /* dmul */
494 COSTS_N_INSNS (18), /* sdiv */
495 COSTS_N_INSNS (32), /* ddiv */
498 /* Instruction costs on PPC630 processors. */
500 struct processor_costs ppc630_cost = {
501 COSTS_N_INSNS (5), /* mulsi */
502 COSTS_N_INSNS (4), /* mulsi_const */
503 COSTS_N_INSNS (3), /* mulsi_const9 */
504 COSTS_N_INSNS (7), /* muldi */
505 COSTS_N_INSNS (21), /* divsi */
506 COSTS_N_INSNS (37), /* divdi */
507 COSTS_N_INSNS (3), /* fp */
508 COSTS_N_INSNS (3), /* dmul */
509 COSTS_N_INSNS (17), /* sdiv */
510 COSTS_N_INSNS (21), /* ddiv */
513 /* Instruction costs on PPC750 and PPC7400 processors. */
515 struct processor_costs ppc750_cost = {
516 COSTS_N_INSNS (5), /* mulsi */
517 COSTS_N_INSNS (3), /* mulsi_const */
518 COSTS_N_INSNS (2), /* mulsi_const9 */
519 COSTS_N_INSNS (5), /* muldi */
520 COSTS_N_INSNS (17), /* divsi */
521 COSTS_N_INSNS (17), /* divdi */
522 COSTS_N_INSNS (3), /* fp */
523 COSTS_N_INSNS (3), /* dmul */
524 COSTS_N_INSNS (17), /* sdiv */
525 COSTS_N_INSNS (31), /* ddiv */
528 /* Instruction costs on PPC7450 processors. */
530 struct processor_costs ppc7450_cost = {
531 COSTS_N_INSNS (4), /* mulsi */
532 COSTS_N_INSNS (3), /* mulsi_const */
533 COSTS_N_INSNS (3), /* mulsi_const9 */
534 COSTS_N_INSNS (4), /* muldi */
535 COSTS_N_INSNS (23), /* divsi */
536 COSTS_N_INSNS (23), /* divdi */
537 COSTS_N_INSNS (5), /* fp */
538 COSTS_N_INSNS (5), /* dmul */
539 COSTS_N_INSNS (21), /* sdiv */
540 COSTS_N_INSNS (35), /* ddiv */
543 /* Instruction costs on PPC8540 processors. */
545 struct processor_costs ppc8540_cost = {
546 COSTS_N_INSNS (4), /* mulsi */
547 COSTS_N_INSNS (4), /* mulsi_const */
548 COSTS_N_INSNS (4), /* mulsi_const9 */
549 COSTS_N_INSNS (4), /* muldi */
550 COSTS_N_INSNS (19), /* divsi */
551 COSTS_N_INSNS (19), /* divdi */
552 COSTS_N_INSNS (4), /* fp */
553 COSTS_N_INSNS (4), /* dmul */
554 COSTS_N_INSNS (29), /* sdiv */
555 COSTS_N_INSNS (29), /* ddiv */
558 /* Instruction costs on POWER4 and POWER5 processors. */
560 struct processor_costs power4_cost = {
561 COSTS_N_INSNS (3), /* mulsi */
562 COSTS_N_INSNS (2), /* mulsi_const */
563 COSTS_N_INSNS (2), /* mulsi_const9 */
564 COSTS_N_INSNS (4), /* muldi */
565 COSTS_N_INSNS (18), /* divsi */
566 COSTS_N_INSNS (34), /* divdi */
567 COSTS_N_INSNS (3), /* fp */
568 COSTS_N_INSNS (3), /* dmul */
569 COSTS_N_INSNS (17), /* sdiv */
570 COSTS_N_INSNS (17), /* ddiv */
574 static bool rs6000_function_ok_for_sibcall (tree, tree);
575 static const char *rs6000_invalid_within_doloop (rtx);
576 static rtx rs6000_generate_compare (enum rtx_code);
577 static void rs6000_maybe_dead (rtx);
578 static void rs6000_emit_stack_tie (void);
579 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
580 static rtx spe_synthesize_frame_save (rtx);
581 static bool spe_func_has_64bit_regs_p (void);
582 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
584 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
585 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
586 static unsigned rs6000_hash_constant (rtx);
587 static unsigned toc_hash_function (const void *);
588 static int toc_hash_eq (const void *, const void *);
589 static int constant_pool_expr_1 (rtx, int *, int *);
590 static bool constant_pool_expr_p (rtx);
591 static bool legitimate_indexed_address_p (rtx, int);
592 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
593 static struct machine_function * rs6000_init_machine_status (void);
594 static bool rs6000_assemble_integer (rtx, unsigned int, int);
595 static bool no_global_regs_above (int);
596 #ifdef HAVE_GAS_HIDDEN
597 static void rs6000_assemble_visibility (tree, int);
599 static int rs6000_ra_ever_killed (void);
600 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
601 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
602 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
603 static const char *rs6000_mangle_fundamental_type (tree);
604 extern const struct attribute_spec rs6000_attribute_table[];
605 static void rs6000_set_default_type_attributes (tree);
606 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
607 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
608 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
610 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
611 static bool rs6000_return_in_memory (tree, tree);
612 static void rs6000_file_start (void);
614 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
615 static void rs6000_elf_asm_out_constructor (rtx, int);
616 static void rs6000_elf_asm_out_destructor (rtx, int);
617 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
618 static void rs6000_elf_asm_init_sections (void);
619 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
620 static void rs6000_elf_unique_section (tree, int);
621 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
622 unsigned HOST_WIDE_INT);
623 static void rs6000_elf_encode_section_info (tree, rtx, int)
626 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
628 static void rs6000_xcoff_asm_output_anchor (rtx);
629 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
630 static void rs6000_xcoff_asm_init_sections (void);
631 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
632 static section *rs6000_xcoff_select_section (tree, int,
633 unsigned HOST_WIDE_INT);
634 static void rs6000_xcoff_unique_section (tree, int);
635 static section *rs6000_xcoff_select_rtx_section
636 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
637 static const char * rs6000_xcoff_strip_name_encoding (const char *);
638 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
639 static void rs6000_xcoff_file_start (void);
640 static void rs6000_xcoff_file_end (void);
642 static int rs6000_variable_issue (FILE *, int, rtx, int);
643 static bool rs6000_rtx_costs (rtx, int, int, int *);
644 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
645 static bool is_microcoded_insn (rtx);
646 static int is_dispatch_slot_restricted (rtx);
647 static bool is_cracked_insn (rtx);
648 static bool is_branch_slot_insn (rtx);
649 static int rs6000_adjust_priority (rtx, int);
650 static int rs6000_issue_rate (void);
651 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
652 static rtx get_next_active_insn (rtx, rtx);
653 static bool insn_terminates_group_p (rtx , enum group_termination);
654 static bool is_costly_group (rtx *, rtx);
655 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
656 static int redefine_groups (FILE *, int, rtx, rtx);
657 static int pad_groups (FILE *, int, rtx, rtx);
658 static void rs6000_sched_finish (FILE *, int);
659 static int rs6000_use_sched_lookahead (void);
660 static tree rs6000_builtin_mask_for_load (void);
662 static void def_builtin (int, const char *, tree, int);
663 static void rs6000_init_builtins (void);
664 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
665 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
666 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
667 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
668 static void altivec_init_builtins (void);
669 static void rs6000_common_init_builtins (void);
670 static void rs6000_init_libfuncs (void);
672 static void enable_mask_for_builtins (struct builtin_description *, int,
673 enum rs6000_builtins,
674 enum rs6000_builtins);
675 static tree build_opaque_vector_type (tree, int);
676 static void spe_init_builtins (void);
677 static rtx spe_expand_builtin (tree, rtx, bool *);
678 static rtx spe_expand_stv_builtin (enum insn_code, tree);
679 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
680 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
681 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
682 static rs6000_stack_t *rs6000_stack_info (void);
683 static void debug_stack_info (rs6000_stack_t *);
685 static rtx altivec_expand_builtin (tree, rtx, bool *);
686 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
687 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
688 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
689 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
690 static rtx altivec_expand_predicate_builtin (enum insn_code,
691 const char *, tree, rtx);
692 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
693 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
694 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
695 static rtx altivec_expand_vec_set_builtin (tree);
696 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
697 static int get_element_number (tree, tree);
698 static bool rs6000_handle_option (size_t, const char *, int);
699 static void rs6000_parse_tls_size_option (void);
700 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
701 static int first_altivec_reg_to_save (void);
702 static unsigned int compute_vrsave_mask (void);
703 static void compute_save_world_info (rs6000_stack_t *info_ptr);
704 static void is_altivec_return_reg (rtx, void *);
705 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
706 int easy_vector_constant (rtx, enum machine_mode);
707 static bool rs6000_is_opaque_type (tree);
708 static rtx rs6000_dwarf_register_span (rtx);
709 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
710 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
711 static rtx rs6000_tls_get_addr (void);
712 static rtx rs6000_got_sym (void);
713 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
714 static const char *rs6000_get_some_local_dynamic_name (void);
715 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
716 static rtx rs6000_complex_function_value (enum machine_mode);
717 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
718 enum machine_mode, tree);
719 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
721 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
722 tree, HOST_WIDE_INT);
723 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
726 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
729 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
730 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
731 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
732 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
733 enum machine_mode, tree,
735 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
737 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
739 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
741 static void macho_branch_islands (void);
742 static void add_compiler_branch_island (tree, tree, int);
743 static int no_previous_def (tree function_name);
744 static tree get_prev_label (tree function_name);
745 static void rs6000_darwin_file_start (void);
748 static tree rs6000_build_builtin_va_list (void);
749 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
750 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
751 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
752 static bool rs6000_vector_mode_supported_p (enum machine_mode);
753 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
755 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
757 static int get_vsel_insn (enum machine_mode);
758 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
759 static tree rs6000_stack_protect_fail (void);
761 const int INSN_NOT_AVAILABLE = -1;
762 static enum machine_mode rs6000_eh_return_filter_mode (void);
764 /* Hash table stuff for keeping track of TOC entries. */
766 struct toc_hash_struct GTY(())
768 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
769 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
771 enum machine_mode key_mode;
775 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
777 /* Default register names. */
778 char rs6000_reg_names[][8] =
780 "0", "1", "2", "3", "4", "5", "6", "7",
781 "8", "9", "10", "11", "12", "13", "14", "15",
782 "16", "17", "18", "19", "20", "21", "22", "23",
783 "24", "25", "26", "27", "28", "29", "30", "31",
784 "0", "1", "2", "3", "4", "5", "6", "7",
785 "8", "9", "10", "11", "12", "13", "14", "15",
786 "16", "17", "18", "19", "20", "21", "22", "23",
787 "24", "25", "26", "27", "28", "29", "30", "31",
788 "mq", "lr", "ctr","ap",
789 "0", "1", "2", "3", "4", "5", "6", "7",
791 /* AltiVec registers. */
792 "0", "1", "2", "3", "4", "5", "6", "7",
793 "8", "9", "10", "11", "12", "13", "14", "15",
794 "16", "17", "18", "19", "20", "21", "22", "23",
795 "24", "25", "26", "27", "28", "29", "30", "31",
798 "spe_acc", "spefscr",
799 /* Soft frame pointer. */
803 #ifdef TARGET_REGNAMES
804 static const char alt_reg_names[][8] =
806 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
807 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
808 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
809 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
810 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
811 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
812 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
813 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
814 "mq", "lr", "ctr", "ap",
815 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
817 /* AltiVec registers. */
818 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
819 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
820 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
821 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
824 "spe_acc", "spefscr",
825 /* Soft frame pointer. */
830 #ifndef MASK_STRICT_ALIGN
831 #define MASK_STRICT_ALIGN 0
833 #ifndef TARGET_PROFILE_KERNEL
834 #define TARGET_PROFILE_KERNEL 0
837 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
838 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
840 /* Initialize the GCC target structure. */
841 #undef TARGET_ATTRIBUTE_TABLE
842 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
843 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
844 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
846 #undef TARGET_ASM_ALIGNED_DI_OP
847 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
849 /* Default unaligned ops are only provided for ELF. Find the ops needed
850 for non-ELF systems. */
851 #ifndef OBJECT_FORMAT_ELF
853 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
855 #undef TARGET_ASM_UNALIGNED_HI_OP
856 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
857 #undef TARGET_ASM_UNALIGNED_SI_OP
858 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
859 #undef TARGET_ASM_UNALIGNED_DI_OP
860 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
863 #undef TARGET_ASM_UNALIGNED_HI_OP
864 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
865 #undef TARGET_ASM_UNALIGNED_SI_OP
866 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
867 #undef TARGET_ASM_UNALIGNED_DI_OP
868 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
869 #undef TARGET_ASM_ALIGNED_DI_OP
870 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
874 /* This hook deals with fixups for relocatable code and DI-mode objects
876 #undef TARGET_ASM_INTEGER
877 #define TARGET_ASM_INTEGER rs6000_assemble_integer
879 #ifdef HAVE_GAS_HIDDEN
880 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
881 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
884 #undef TARGET_HAVE_TLS
885 #define TARGET_HAVE_TLS HAVE_AS_TLS
887 #undef TARGET_CANNOT_FORCE_CONST_MEM
888 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
890 #undef TARGET_ASM_FUNCTION_PROLOGUE
891 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
892 #undef TARGET_ASM_FUNCTION_EPILOGUE
893 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
895 #undef TARGET_SCHED_VARIABLE_ISSUE
896 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
898 #undef TARGET_SCHED_ISSUE_RATE
899 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
900 #undef TARGET_SCHED_ADJUST_COST
901 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
902 #undef TARGET_SCHED_ADJUST_PRIORITY
903 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
904 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
905 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
906 #undef TARGET_SCHED_FINISH
907 #define TARGET_SCHED_FINISH rs6000_sched_finish
909 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
910 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
912 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
913 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
915 #undef TARGET_INIT_BUILTINS
916 #define TARGET_INIT_BUILTINS rs6000_init_builtins
918 #undef TARGET_EXPAND_BUILTIN
919 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
921 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
922 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
924 #undef TARGET_INIT_LIBFUNCS
925 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
928 #undef TARGET_BINDS_LOCAL_P
929 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
932 #undef TARGET_ASM_OUTPUT_MI_THUNK
933 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
935 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
936 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
938 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
939 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
941 #undef TARGET_INVALID_WITHIN_DOLOOP
942 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
944 #undef TARGET_RTX_COSTS
945 #define TARGET_RTX_COSTS rs6000_rtx_costs
946 #undef TARGET_ADDRESS_COST
947 #define TARGET_ADDRESS_COST hook_int_rtx_0
949 #undef TARGET_VECTOR_OPAQUE_P
950 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
952 #undef TARGET_DWARF_REGISTER_SPAN
953 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
955 /* On rs6000, function arguments are promoted, as are function return
957 #undef TARGET_PROMOTE_FUNCTION_ARGS
958 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
959 #undef TARGET_PROMOTE_FUNCTION_RETURN
960 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
962 #undef TARGET_RETURN_IN_MEMORY
963 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
965 #undef TARGET_SETUP_INCOMING_VARARGS
966 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
968 /* Always strict argument naming on rs6000. */
969 #undef TARGET_STRICT_ARGUMENT_NAMING
970 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
971 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
972 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
973 #undef TARGET_SPLIT_COMPLEX_ARG
974 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
975 #undef TARGET_MUST_PASS_IN_STACK
976 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
977 #undef TARGET_PASS_BY_REFERENCE
978 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
979 #undef TARGET_ARG_PARTIAL_BYTES
980 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
982 #undef TARGET_BUILD_BUILTIN_VA_LIST
983 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
985 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
986 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
988 #undef TARGET_EH_RETURN_FILTER_MODE
989 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
991 #undef TARGET_SCALAR_MODE_SUPPORTED_P
992 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
994 #undef TARGET_VECTOR_MODE_SUPPORTED_P
995 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
997 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
998 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1000 #undef TARGET_HANDLE_OPTION
1001 #define TARGET_HANDLE_OPTION rs6000_handle_option
1003 #undef TARGET_DEFAULT_TARGET_FLAGS
1004 #define TARGET_DEFAULT_TARGET_FLAGS \
1005 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
1007 #undef TARGET_STACK_PROTECT_FAIL
1008 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1010 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1011 The PowerPC architecture requires only weak consistency among
1012 processors--that is, memory accesses between processors need not be
1013 sequentially consistent and memory accesses among processors can occur
1014 in any order. The ability to order memory accesses weakly provides
1015 opportunities for more efficient use of the system bus. Unless a
1016 dependency exists, the 604e allows read operations to precede store
1018 #undef TARGET_RELAXED_ORDERING
1019 #define TARGET_RELAXED_ORDERING true
1022 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1023 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1026 /* Use a 32-bit anchor range. This leads to sequences like:
1028 addis tmp,anchor,high
1031 where tmp itself acts as an anchor, and can be shared between
1032 accesses to the same 64k page. */
1033 #undef TARGET_MIN_ANCHOR_OFFSET
1034 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1035 #undef TARGET_MAX_ANCHOR_OFFSET
1036 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1037 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1038 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1040 struct gcc_target targetm = TARGET_INITIALIZER;
1043 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1046 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1048 /* The GPRs can hold any mode, but values bigger than one register
1049 cannot go past R31. */
1050 if (INT_REGNO_P (regno))
1051 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1053 /* The float registers can only hold floating modes and DImode.
1054 This also excludes decimal float modes. */
1055 if (FP_REGNO_P (regno))
1057 (SCALAR_FLOAT_MODE_P (mode)
1058 && !DECIMAL_FLOAT_MODE_P (mode)
1059 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1060 || (GET_MODE_CLASS (mode) == MODE_INT
1061 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1063 /* The CR register can only hold CC modes. */
1064 if (CR_REGNO_P (regno))
1065 return GET_MODE_CLASS (mode) == MODE_CC;
1067 if (XER_REGNO_P (regno))
1068 return mode == PSImode;
1070 /* AltiVec only in AldyVec registers. */
1071 if (ALTIVEC_REGNO_P (regno))
1072 return ALTIVEC_VECTOR_MODE (mode);
1074 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1075 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1078 /* We cannot put TImode anywhere except general register and it must be
1079 able to fit within the register set. */
1081 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1084 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1086 rs6000_init_hard_regno_mode_ok (void)
1090 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1091 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1092 if (rs6000_hard_regno_mode_ok (r, m))
1093 rs6000_hard_regno_mode_ok_p[m][r] = true;
1096 /* If not otherwise specified by a target, make 'long double' equivalent to
1099 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1100 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1103 /* Override command line options. Mostly we process the processor
1104 type and sometimes adjust other TARGET_ options. */
1107 rs6000_override_options (const char *default_cpu)
1110 struct rs6000_cpu_select *ptr;
1113 /* Simplifications for entries below. */
1116 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1117 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1120 /* This table occasionally claims that a processor does not support
1121 a particular feature even though it does, but the feature is slower
1122 than the alternative. Thus, it shouldn't be relied on as a
1123 complete description of the processor's support.
1125 Please keep this list in order, and don't forget to update the
1126 documentation in invoke.texi when adding a new processor or
1130 const char *const name; /* Canonical processor name. */
1131 const enum processor_type processor; /* Processor type enum value. */
1132 const int target_enable; /* Target flags to enable. */
1133 } const processor_target_table[]
1134 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1135 {"403", PROCESSOR_PPC403,
1136 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1137 {"405", PROCESSOR_PPC405,
1138 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1139 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_MULHW},
1140 {"440", PROCESSOR_PPC440,
1141 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1142 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_MULHW},
1143 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1144 {"601", PROCESSOR_PPC601,
1145 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1146 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1147 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1148 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1150 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1151 {"620", PROCESSOR_PPC620,
1152 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1153 {"630", PROCESSOR_PPC630,
1154 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1155 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1156 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1157 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1158 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1159 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1160 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1161 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1162 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1163 /* 8548 has a dummy entry for now. */
1164 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1165 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1166 {"970", PROCESSOR_POWER4,
1167 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1168 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1169 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1170 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1171 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1172 {"G5", PROCESSOR_POWER4,
1173 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1174 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1175 {"power2", PROCESSOR_POWER,
1176 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1177 {"power3", PROCESSOR_PPC630,
1178 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1179 {"power4", PROCESSOR_POWER4,
1180 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1181 {"power5", PROCESSOR_POWER5,
1182 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1183 | MASK_MFCRF | MASK_POPCNTB},
1184 {"power5+", PROCESSOR_POWER5,
1185 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1186 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1187 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1188 {"powerpc64", PROCESSOR_POWERPC64,
1189 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1190 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1191 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1192 {"rios2", PROCESSOR_RIOS2,
1193 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1194 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1195 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1196 {"rs64", PROCESSOR_RS64A,
1197 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1200 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1202 /* Some OSs don't support saving the high part of 64-bit registers on
1203 context switch. Other OSs don't support saving Altivec registers.
1204 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1205 settings; if the user wants either, the user must explicitly specify
1206 them and we won't interfere with the user's specification. */
1209 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1210 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1211 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1212 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW)
1215 rs6000_init_hard_regno_mode_ok ();
1217 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1218 #ifdef OS_MISSING_POWERPC64
1219 if (OS_MISSING_POWERPC64)
1220 set_masks &= ~MASK_POWERPC64;
1222 #ifdef OS_MISSING_ALTIVEC
1223 if (OS_MISSING_ALTIVEC)
1224 set_masks &= ~MASK_ALTIVEC;
1227 /* Don't override by the processor default if given explicitly. */
1228 set_masks &= ~target_flags_explicit;
1230 /* Identify the processor type. */
1231 rs6000_select[0].string = default_cpu;
1232 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1234 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1236 ptr = &rs6000_select[i];
1237 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1239 for (j = 0; j < ptt_size; j++)
1240 if (! strcmp (ptr->string, processor_target_table[j].name))
1242 if (ptr->set_tune_p)
1243 rs6000_cpu = processor_target_table[j].processor;
1245 if (ptr->set_arch_p)
1247 target_flags &= ~set_masks;
1248 target_flags |= (processor_target_table[j].target_enable
1255 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1262 /* If we are optimizing big endian systems for space, use the load/store
1263 multiple and string instructions. */
1264 if (BYTES_BIG_ENDIAN && optimize_size)
1265 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1267 /* Don't allow -mmultiple or -mstring on little endian systems
1268 unless the cpu is a 750, because the hardware doesn't support the
1269 instructions used in little endian mode, and causes an alignment
1270 trap. The 750 does not cause an alignment trap (except when the
1271 target is unaligned). */
1273 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1275 if (TARGET_MULTIPLE)
1277 target_flags &= ~MASK_MULTIPLE;
1278 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1279 warning (0, "-mmultiple is not supported on little endian systems");
1284 target_flags &= ~MASK_STRING;
1285 if ((target_flags_explicit & MASK_STRING) != 0)
1286 warning (0, "-mstring is not supported on little endian systems");
1290 /* Set debug flags */
1291 if (rs6000_debug_name)
1293 if (! strcmp (rs6000_debug_name, "all"))
1294 rs6000_debug_stack = rs6000_debug_arg = 1;
1295 else if (! strcmp (rs6000_debug_name, "stack"))
1296 rs6000_debug_stack = 1;
1297 else if (! strcmp (rs6000_debug_name, "arg"))
1298 rs6000_debug_arg = 1;
1300 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1303 if (rs6000_traceback_name)
1305 if (! strncmp (rs6000_traceback_name, "full", 4))
1306 rs6000_traceback = traceback_full;
1307 else if (! strncmp (rs6000_traceback_name, "part", 4))
1308 rs6000_traceback = traceback_part;
1309 else if (! strncmp (rs6000_traceback_name, "no", 2))
1310 rs6000_traceback = traceback_none;
1312 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1313 rs6000_traceback_name);
1316 if (!rs6000_explicit_options.long_double)
1317 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1319 #ifndef POWERPC_LINUX
1320 if (!rs6000_explicit_options.abi)
1321 rs6000_ieeequad = 1;
1324 /* Set Altivec ABI as default for powerpc64 linux. */
1325 if (TARGET_ELF && TARGET_64BIT)
1327 rs6000_altivec_abi = 1;
1328 TARGET_ALTIVEC_VRSAVE = 1;
1331 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1332 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1334 rs6000_darwin64_abi = 1;
1336 darwin_one_byte_bool = 1;
1338 /* Default to natural alignment, for better performance. */
1339 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1342 /* Handle -mtls-size option. */
1343 rs6000_parse_tls_size_option ();
1345 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1346 SUBTARGET_OVERRIDE_OPTIONS;
1348 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1349 SUBSUBTARGET_OVERRIDE_OPTIONS;
1351 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1352 SUB3TARGET_OVERRIDE_OPTIONS;
1358 error ("AltiVec and E500 instructions cannot coexist");
1360 /* The e500 does not have string instructions, and we set
1361 MASK_STRING above when optimizing for size. */
1362 if ((target_flags & MASK_STRING) != 0)
1363 target_flags = target_flags & ~MASK_STRING;
1365 else if (rs6000_select[1].string != NULL)
1367 /* For the powerpc-eabispe configuration, we set all these by
1368 default, so let's unset them if we manually set another
1369 CPU that is not the E500. */
1370 if (!rs6000_explicit_options.abi)
1372 if (!rs6000_explicit_options.spe)
1374 if (!rs6000_explicit_options.float_gprs)
1375 rs6000_float_gprs = 0;
1376 if (!rs6000_explicit_options.isel)
1378 if (!rs6000_explicit_options.long_double)
1379 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1382 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1383 && rs6000_cpu != PROCESSOR_POWER5);
1384 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1385 || rs6000_cpu == PROCESSOR_POWER5);
1387 rs6000_sched_restricted_insns_priority
1388 = (rs6000_sched_groups ? 1 : 0);
1390 /* Handle -msched-costly-dep option. */
1391 rs6000_sched_costly_dep
1392 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1394 if (rs6000_sched_costly_dep_str)
1396 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1397 rs6000_sched_costly_dep = no_dep_costly;
1398 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1399 rs6000_sched_costly_dep = all_deps_costly;
1400 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1401 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1402 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1403 rs6000_sched_costly_dep = store_to_load_dep_costly;
1405 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1408 /* Handle -minsert-sched-nops option. */
1409 rs6000_sched_insert_nops
1410 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1412 if (rs6000_sched_insert_nops_str)
1414 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1415 rs6000_sched_insert_nops = sched_finish_none;
1416 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1417 rs6000_sched_insert_nops = sched_finish_pad_groups;
1418 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1419 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1421 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1424 #ifdef TARGET_REGNAMES
1425 /* If the user desires alternate register names, copy in the
1426 alternate names now. */
1427 if (TARGET_REGNAMES)
1428 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1431 /* Set aix_struct_return last, after the ABI is determined.
1432 If -maix-struct-return or -msvr4-struct-return was explicitly
1433 used, don't override with the ABI default. */
1434 if (!rs6000_explicit_options.aix_struct_ret)
1435 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1437 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1438 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1441 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1443 /* We can only guarantee the availability of DI pseudo-ops when
1444 assembling for 64-bit targets. */
1447 targetm.asm_out.aligned_op.di = NULL;
1448 targetm.asm_out.unaligned_op.di = NULL;
1451 /* Set branch target alignment, if not optimizing for size. */
1454 if (rs6000_sched_groups)
1456 if (align_functions <= 0)
1457 align_functions = 16;
1458 if (align_jumps <= 0)
1460 if (align_loops <= 0)
1463 if (align_jumps_max_skip <= 0)
1464 align_jumps_max_skip = 15;
1465 if (align_loops_max_skip <= 0)
1466 align_loops_max_skip = 15;
1469 /* Arrange to save and restore machine status around nested functions. */
1470 init_machine_status = rs6000_init_machine_status;
1472 /* We should always be splitting complex arguments, but we can't break
1473 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1474 if (DEFAULT_ABI != ABI_AIX)
1475 targetm.calls.split_complex_arg = NULL;
1477 /* Initialize rs6000_cost with the appropriate target costs. */
1479 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1483 case PROCESSOR_RIOS1:
1484 rs6000_cost = &rios1_cost;
1487 case PROCESSOR_RIOS2:
1488 rs6000_cost = &rios2_cost;
1491 case PROCESSOR_RS64A:
1492 rs6000_cost = &rs64a_cost;
1495 case PROCESSOR_MPCCORE:
1496 rs6000_cost = &mpccore_cost;
1499 case PROCESSOR_PPC403:
1500 rs6000_cost = &ppc403_cost;
1503 case PROCESSOR_PPC405:
1504 rs6000_cost = &ppc405_cost;
1507 case PROCESSOR_PPC440:
1508 rs6000_cost = &ppc440_cost;
1511 case PROCESSOR_PPC601:
1512 rs6000_cost = &ppc601_cost;
1515 case PROCESSOR_PPC603:
1516 rs6000_cost = &ppc603_cost;
1519 case PROCESSOR_PPC604:
1520 rs6000_cost = &ppc604_cost;
1523 case PROCESSOR_PPC604e:
1524 rs6000_cost = &ppc604e_cost;
1527 case PROCESSOR_PPC620:
1528 rs6000_cost = &ppc620_cost;
1531 case PROCESSOR_PPC630:
1532 rs6000_cost = &ppc630_cost;
1535 case PROCESSOR_PPC750:
1536 case PROCESSOR_PPC7400:
1537 rs6000_cost = &ppc750_cost;
1540 case PROCESSOR_PPC7450:
1541 rs6000_cost = &ppc7450_cost;
1544 case PROCESSOR_PPC8540:
1545 rs6000_cost = &ppc8540_cost;
1548 case PROCESSOR_POWER4:
1549 case PROCESSOR_POWER5:
1550 rs6000_cost = &power4_cost;
1558 /* Implement targetm.vectorize.builtin_mask_for_load. */
1560 rs6000_builtin_mask_for_load (void)
1563 return altivec_builtin_mask_for_load;
1568 /* Handle generic options of the form -mfoo=yes/no.
1569 NAME is the option name.
1570 VALUE is the option value.
1571 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1572 whether the option value is 'yes' or 'no' respectively. */
1574 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1578 else if (!strcmp (value, "yes"))
1580 else if (!strcmp (value, "no"))
1583 error ("unknown -m%s= option specified: '%s'", name, value);
1586 /* Validate and record the size specified with the -mtls-size option. */
1589 rs6000_parse_tls_size_option (void)
1591 if (rs6000_tls_size_string == 0)
1593 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1594 rs6000_tls_size = 16;
1595 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1596 rs6000_tls_size = 32;
1597 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1598 rs6000_tls_size = 64;
1600 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1604 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1606 if (DEFAULT_ABI == ABI_DARWIN)
1607 /* The Darwin libraries never set errno, so we might as well
1608 avoid calling them when that's the only reason we would. */
1609 flag_errno_math = 0;
1611 /* Double growth factor to counter reduced min jump length. */
1612 set_param_value ("max-grow-copy-bb-insns", 16);
1615 /* Implement TARGET_HANDLE_OPTION. */
1618 rs6000_handle_option (size_t code, const char *arg, int value)
1623 target_flags &= ~(MASK_POWER | MASK_POWER2
1624 | MASK_MULTIPLE | MASK_STRING);
1625 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1626 | MASK_MULTIPLE | MASK_STRING);
1628 case OPT_mno_powerpc:
1629 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1630 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1631 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1632 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1635 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1636 | MASK_NO_SUM_IN_TOC);
1637 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1638 | MASK_NO_SUM_IN_TOC);
1639 #ifdef TARGET_USES_SYSV4_OPT
1640 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1641 just the same as -mminimal-toc. */
1642 target_flags |= MASK_MINIMAL_TOC;
1643 target_flags_explicit |= MASK_MINIMAL_TOC;
1647 #ifdef TARGET_USES_SYSV4_OPT
1649 /* Make -mtoc behave like -mminimal-toc. */
1650 target_flags |= MASK_MINIMAL_TOC;
1651 target_flags_explicit |= MASK_MINIMAL_TOC;
1655 #ifdef TARGET_USES_AIX64_OPT
1660 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1661 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1662 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1665 #ifdef TARGET_USES_AIX64_OPT
1670 target_flags &= ~MASK_POWERPC64;
1671 target_flags_explicit |= MASK_POWERPC64;
1674 case OPT_minsert_sched_nops_:
1675 rs6000_sched_insert_nops_str = arg;
1678 case OPT_mminimal_toc:
1681 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1682 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1689 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1690 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1697 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1698 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1702 case OPT_mpowerpc_gpopt:
1703 case OPT_mpowerpc_gfxopt:
1706 target_flags |= MASK_POWERPC;
1707 target_flags_explicit |= MASK_POWERPC;
1711 case OPT_maix_struct_return:
1712 case OPT_msvr4_struct_return:
1713 rs6000_explicit_options.aix_struct_ret = true;
1717 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1721 rs6000_explicit_options.isel = true;
1722 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1726 rs6000_explicit_options.spe = true;
1727 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1728 /* No SPE means 64-bit long doubles, even if an E500. */
1730 rs6000_long_double_type_size = 64;
1734 rs6000_debug_name = arg;
1737 #ifdef TARGET_USES_SYSV4_OPT
1739 rs6000_abi_name = arg;
1743 rs6000_sdata_name = arg;
1746 case OPT_mtls_size_:
1747 rs6000_tls_size_string = arg;
1750 case OPT_mrelocatable:
1753 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1754 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1758 case OPT_mrelocatable_lib:
1761 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1762 | MASK_NO_FP_IN_TOC;
1763 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1764 | MASK_NO_FP_IN_TOC;
1768 target_flags &= ~MASK_RELOCATABLE;
1769 target_flags_explicit |= MASK_RELOCATABLE;
1775 rs6000_explicit_options.abi = true;
1776 if (!strcmp (arg, "altivec"))
1778 rs6000_altivec_abi = 1;
1781 else if (! strcmp (arg, "no-altivec"))
1782 rs6000_altivec_abi = 0;
1783 else if (! strcmp (arg, "spe"))
1786 rs6000_altivec_abi = 0;
1787 if (!TARGET_SPE_ABI)
1788 error ("not configured for ABI: '%s'", arg);
1790 else if (! strcmp (arg, "no-spe"))
1793 /* These are here for testing during development only, do not
1794 document in the manual please. */
1795 else if (! strcmp (arg, "d64"))
1797 rs6000_darwin64_abi = 1;
1798 warning (0, "Using darwin64 ABI");
1800 else if (! strcmp (arg, "d32"))
1802 rs6000_darwin64_abi = 0;
1803 warning (0, "Using old darwin ABI");
1806 else if (! strcmp (arg, "ibmlongdouble"))
1808 rs6000_ieeequad = 0;
1809 warning (0, "Using IBM extended precision long double");
1811 else if (! strcmp (arg, "ieeelongdouble"))
1813 rs6000_ieeequad = 1;
1814 warning (0, "Using IEEE extended precision long double");
1819 error ("unknown ABI specified: '%s'", arg);
1825 rs6000_select[1].string = arg;
1829 rs6000_select[2].string = arg;
1832 case OPT_mtraceback_:
1833 rs6000_traceback_name = arg;
1836 case OPT_mfloat_gprs_:
1837 rs6000_explicit_options.float_gprs = true;
1838 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1839 rs6000_float_gprs = 1;
1840 else if (! strcmp (arg, "double"))
1841 rs6000_float_gprs = 2;
1842 else if (! strcmp (arg, "no"))
1843 rs6000_float_gprs = 0;
1846 error ("invalid option for -mfloat-gprs: '%s'", arg);
1851 case OPT_mlong_double_:
1852 rs6000_explicit_options.long_double = true;
1853 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1854 if (value != 64 && value != 128)
1856 error ("Unknown switch -mlong-double-%s", arg);
1857 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1861 rs6000_long_double_type_size = value;
1864 case OPT_msched_costly_dep_:
1865 rs6000_sched_costly_dep_str = arg;
1869 rs6000_explicit_options.alignment = true;
1870 if (! strcmp (arg, "power"))
1872 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1873 some C library functions, so warn about it. The flag may be
1874 useful for performance studies from time to time though, so
1875 don't disable it entirely. */
1876 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1877 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1878 " it is incompatible with the installed C and C++ libraries");
1879 rs6000_alignment_flags = MASK_ALIGN_POWER;
1881 else if (! strcmp (arg, "natural"))
1882 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1885 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1893 /* Do anything needed at the start of the asm file. */
1896 rs6000_file_start (void)
1900 const char *start = buffer;
1901 struct rs6000_cpu_select *ptr;
1902 const char *default_cpu = TARGET_CPU_DEFAULT;
1903 FILE *file = asm_out_file;
1905 default_file_start ();
1907 #ifdef TARGET_BI_ARCH
1908 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1912 if (flag_verbose_asm)
1914 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1915 rs6000_select[0].string = default_cpu;
1917 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1919 ptr = &rs6000_select[i];
1920 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1922 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1927 if (PPC405_ERRATUM77)
1929 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1933 #ifdef USING_ELFOS_H
1934 switch (rs6000_sdata)
1936 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1937 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1938 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1939 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1942 if (rs6000_sdata && g_switch_value)
1944 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1954 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1956 switch_to_section (toc_section);
1957 switch_to_section (text_section);
1962 /* Return nonzero if this function is known to have a null epilogue. */
1965 direct_return (void)
1967 if (reload_completed)
1969 rs6000_stack_t *info = rs6000_stack_info ();
1971 if (info->first_gp_reg_save == 32
1972 && info->first_fp_reg_save == 64
1973 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1974 && ! info->lr_save_p
1975 && ! info->cr_save_p
1976 && info->vrsave_mask == 0
1984 /* Return the number of instructions it takes to form a constant in an
1985 integer register. */
1988 num_insns_constant_wide (HOST_WIDE_INT value)
1990 /* signed constant loadable with {cal|addi} */
1991 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1994 /* constant loadable with {cau|addis} */
1995 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1998 #if HOST_BITS_PER_WIDE_INT == 64
1999 else if (TARGET_POWERPC64)
2001 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2002 HOST_WIDE_INT high = value >> 31;
2004 if (high == 0 || high == -1)
2010 return num_insns_constant_wide (high) + 1;
2012 return (num_insns_constant_wide (high)
2013 + num_insns_constant_wide (low) + 1);
2022 num_insns_constant (rtx op, enum machine_mode mode)
2024 HOST_WIDE_INT low, high;
2026 switch (GET_CODE (op))
2029 #if HOST_BITS_PER_WIDE_INT == 64
2030 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2031 && mask64_operand (op, mode))
2035 return num_insns_constant_wide (INTVAL (op));
2043 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2044 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2045 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2048 if (mode == VOIDmode || mode == DImode)
2050 high = CONST_DOUBLE_HIGH (op);
2051 low = CONST_DOUBLE_LOW (op);
2058 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2059 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2060 high = l[WORDS_BIG_ENDIAN == 0];
2061 low = l[WORDS_BIG_ENDIAN != 0];
2065 return (num_insns_constant_wide (low)
2066 + num_insns_constant_wide (high));
2069 if ((high == 0 && low >= 0)
2070 || (high == -1 && low < 0))
2071 return num_insns_constant_wide (low);
2073 else if (mask64_operand (op, mode))
2077 return num_insns_constant_wide (high) + 1;
2080 return (num_insns_constant_wide (high)
2081 + num_insns_constant_wide (low) + 1);
2090 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2091 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2092 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2093 all items are set to the same value and contain COPIES replicas of the
2094 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2095 operand and the others are set to the value of the operand's msb. */
2098 vspltis_constant (rtx op, unsigned step, unsigned copies)
2100 enum machine_mode mode = GET_MODE (op);
2101 enum machine_mode inner = GET_MODE_INNER (mode);
2104 unsigned nunits = GET_MODE_NUNITS (mode);
2105 unsigned bitsize = GET_MODE_BITSIZE (inner);
2106 unsigned mask = GET_MODE_MASK (inner);
2108 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2109 HOST_WIDE_INT val = INTVAL (last);
2110 HOST_WIDE_INT splat_val = val;
2111 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2113 /* Construct the value to be splatted, if possible. If not, return 0. */
2114 for (i = 2; i <= copies; i *= 2)
2116 HOST_WIDE_INT small_val;
2118 small_val = splat_val >> bitsize;
2120 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2122 splat_val = small_val;
2125 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2126 if (EASY_VECTOR_15 (splat_val))
2129 /* Also check if we can splat, and then add the result to itself. Do so if
2130 the value is positive, of if the splat instruction is using OP's mode;
2131 for splat_val < 0, the splat and the add should use the same mode. */
2132 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2133 && (splat_val >= 0 || (step == 1 && copies == 1)))
2139 /* Check if VAL is present in every STEP-th element, and the
2140 other elements are filled with its most significant bit. */
2141 for (i = 0; i < nunits - 1; ++i)
2143 HOST_WIDE_INT desired_val;
2144 if (((i + 1) & (step - 1)) == 0)
2147 desired_val = msb_val;
2149 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2157 /* Return true if OP is of the given MODE and can be synthesized
2158 with a vspltisb, vspltish or vspltisw. */
2161 easy_altivec_constant (rtx op, enum machine_mode mode)
2163 unsigned step, copies;
2165 if (mode == VOIDmode)
2166 mode = GET_MODE (op);
2167 else if (mode != GET_MODE (op))
2170 /* Start with a vspltisw. */
2171 step = GET_MODE_NUNITS (mode) / 4;
2174 if (vspltis_constant (op, step, copies))
2177 /* Then try with a vspltish. */
2183 if (vspltis_constant (op, step, copies))
2186 /* And finally a vspltisb. */
2192 if (vspltis_constant (op, step, copies))
2198 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2199 result is OP. Abort if it is not possible. */
2202 gen_easy_altivec_constant (rtx op)
2204 enum machine_mode mode = GET_MODE (op);
2205 int nunits = GET_MODE_NUNITS (mode);
2206 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2207 unsigned step = nunits / 4;
2208 unsigned copies = 1;
2210 /* Start with a vspltisw. */
2211 if (vspltis_constant (op, step, copies))
2212 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2214 /* Then try with a vspltish. */
2220 if (vspltis_constant (op, step, copies))
2221 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2223 /* And finally a vspltisb. */
2229 if (vspltis_constant (op, step, copies))
2230 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2236 output_vec_const_move (rtx *operands)
2239 enum machine_mode mode;
2244 mode = GET_MODE (dest);
2249 if (zero_constant (vec, mode))
2250 return "vxor %0,%0,%0";
2252 splat_vec = gen_easy_altivec_constant (vec);
2253 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2254 operands[1] = XEXP (splat_vec, 0);
2255 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2258 switch (GET_MODE (splat_vec))
2261 return "vspltisw %0,%1";
2264 return "vspltish %0,%1";
2267 return "vspltisb %0,%1";
2274 gcc_assert (TARGET_SPE);
2276 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2277 pattern of V1DI, V4HI, and V2SF.
2279 FIXME: We should probably return # and add post reload
2280 splitters for these, but this way is so easy ;-). */
2281 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2282 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2283 operands[1] = CONST_VECTOR_ELT (vec, 0);
2284 operands[2] = CONST_VECTOR_ELT (vec, 1);
2286 return "li %0,%1\n\tevmergelo %0,%0,%0";
2288 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2291 /* Initialize vector TARGET to VALS. */
2294 rs6000_expand_vector_init (rtx target, rtx vals)
2296 enum machine_mode mode = GET_MODE (target);
2297 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2298 int n_elts = GET_MODE_NUNITS (mode);
2299 int n_var = 0, one_var = -1;
2300 bool all_same = true, all_const_zero = true;
2304 for (i = 0; i < n_elts; ++i)
2306 x = XVECEXP (vals, 0, i);
2307 if (!CONSTANT_P (x))
2308 ++n_var, one_var = i;
2309 else if (x != CONST0_RTX (inner_mode))
2310 all_const_zero = false;
2312 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2318 if (mode != V4SFmode && all_const_zero)
2320 /* Zero register. */
2321 emit_insn (gen_rtx_SET (VOIDmode, target,
2322 gen_rtx_XOR (mode, target, target)));
2325 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2327 /* Splat immediate. */
2328 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2332 ; /* Splat vector element. */
2335 /* Load from constant pool. */
2336 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2341 /* Store value to stack temp. Load vector element. Splat. */
2344 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2345 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2346 XVECEXP (vals, 0, 0));
2347 x = gen_rtx_UNSPEC (VOIDmode,
2348 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2349 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2351 gen_rtx_SET (VOIDmode,
2354 x = gen_rtx_VEC_SELECT (inner_mode, target,
2355 gen_rtx_PARALLEL (VOIDmode,
2356 gen_rtvec (1, const0_rtx)));
2357 emit_insn (gen_rtx_SET (VOIDmode, target,
2358 gen_rtx_VEC_DUPLICATE (mode, x)));
2362 /* One field is non-constant. Load constant then overwrite
2366 rtx copy = copy_rtx (vals);
2368 /* Load constant part of vector, substitute neighboring value for
2370 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2371 rs6000_expand_vector_init (target, copy);
2373 /* Insert variable. */
2374 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2378 /* Construct the vector in memory one field at a time
2379 and load the whole vector. */
2380 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2381 for (i = 0; i < n_elts; i++)
2382 emit_move_insn (adjust_address_nv (mem, inner_mode,
2383 i * GET_MODE_SIZE (inner_mode)),
2384 XVECEXP (vals, 0, i));
2385 emit_move_insn (target, mem);
2388 /* Set field ELT of TARGET to VAL. */
2391 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2393 enum machine_mode mode = GET_MODE (target);
2394 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2395 rtx reg = gen_reg_rtx (mode);
2397 int width = GET_MODE_SIZE (inner_mode);
2400 /* Load single variable value. */
2401 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2402 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2403 x = gen_rtx_UNSPEC (VOIDmode,
2404 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2405 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2407 gen_rtx_SET (VOIDmode,
2411 /* Linear sequence. */
2412 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2413 for (i = 0; i < 16; ++i)
2414 XVECEXP (mask, 0, i) = GEN_INT (i);
2416 /* Set permute mask to insert element into target. */
2417 for (i = 0; i < width; ++i)
2418 XVECEXP (mask, 0, elt*width + i)
2419 = GEN_INT (i + 0x10);
2420 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2421 x = gen_rtx_UNSPEC (mode,
2422 gen_rtvec (3, target, reg,
2423 force_reg (V16QImode, x)),
2425 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2428 /* Extract field ELT from VEC into TARGET. */
2431 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2433 enum machine_mode mode = GET_MODE (vec);
2434 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2437 /* Allocate mode-sized buffer. */
2438 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2440 /* Add offset to field within buffer matching vector element. */
2441 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2443 /* Store single field into mode-sized buffer. */
2444 x = gen_rtx_UNSPEC (VOIDmode,
2445 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2446 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2448 gen_rtx_SET (VOIDmode,
2451 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2454 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2455 implement ANDing by the mask IN. */
2457 build_mask64_2_operands (rtx in, rtx *out)
2459 #if HOST_BITS_PER_WIDE_INT >= 64
2460 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2463 gcc_assert (GET_CODE (in) == CONST_INT);
2468 /* Assume c initially something like 0x00fff000000fffff. The idea
2469 is to rotate the word so that the middle ^^^^^^ group of zeros
2470 is at the MS end and can be cleared with an rldicl mask. We then
2471 rotate back and clear off the MS ^^ group of zeros with a
2473 c = ~c; /* c == 0xff000ffffff00000 */
2474 lsb = c & -c; /* lsb == 0x0000000000100000 */
2475 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2476 c = ~c; /* c == 0x00fff000000fffff */
2477 c &= -lsb; /* c == 0x00fff00000000000 */
2478 lsb = c & -c; /* lsb == 0x0000100000000000 */
2479 c = ~c; /* c == 0xff000fffffffffff */
2480 c &= -lsb; /* c == 0xff00000000000000 */
2482 while ((lsb >>= 1) != 0)
2483 shift++; /* shift == 44 on exit from loop */
2484 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2485 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2486 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2490 /* Assume c initially something like 0xff000f0000000000. The idea
2491 is to rotate the word so that the ^^^ middle group of zeros
2492 is at the LS end and can be cleared with an rldicr mask. We then
2493 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2495 lsb = c & -c; /* lsb == 0x0000010000000000 */
2496 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2497 c = ~c; /* c == 0x00fff0ffffffffff */
2498 c &= -lsb; /* c == 0x00fff00000000000 */
2499 lsb = c & -c; /* lsb == 0x0000100000000000 */
2500 c = ~c; /* c == 0xff000fffffffffff */
2501 c &= -lsb; /* c == 0xff00000000000000 */
2503 while ((lsb >>= 1) != 0)
2504 shift++; /* shift == 44 on exit from loop */
2505 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2506 m1 >>= shift; /* m1 == 0x0000000000000fff */
2507 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2510 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2511 masks will be all 1's. We are guaranteed more than one transition. */
2512 out[0] = GEN_INT (64 - shift);
2513 out[1] = GEN_INT (m1);
2514 out[2] = GEN_INT (shift);
2515 out[3] = GEN_INT (m2);
2523 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2526 invalid_e500_subreg (rtx op, enum machine_mode mode)
2528 /* Reject (subreg:SI (reg:DF)). */
2529 if (GET_CODE (op) == SUBREG
2531 && REG_P (SUBREG_REG (op))
2532 && GET_MODE (SUBREG_REG (op)) == DFmode)
2535 /* Reject (subreg:DF (reg:DI)). */
2536 if (GET_CODE (op) == SUBREG
2538 && REG_P (SUBREG_REG (op))
2539 && GET_MODE (SUBREG_REG (op)) == DImode)
2545 /* Darwin, AIX increases natural record alignment to doubleword if the first
2546 field is an FP double while the FP fields remain word aligned. */
2549 rs6000_special_round_type_align (tree type, unsigned int computed,
2550 unsigned int specified)
2552 unsigned int align = MAX (computed, specified);
2553 tree field = TYPE_FIELDS (type);
2555 /* Skip all non field decls */
2556 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2557 field = TREE_CHAIN (field);
2559 if (field != NULL && field != type)
2561 type = TREE_TYPE (field);
2562 while (TREE_CODE (type) == ARRAY_TYPE)
2563 type = TREE_TYPE (type);
2565 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2566 align = MAX (align, 64);
2572 /* Return 1 for an operand in small memory on V.4/eabi. */
2575 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2576 enum machine_mode mode ATTRIBUTE_UNUSED)
2581 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2584 if (DEFAULT_ABI != ABI_V4)
2587 if (GET_CODE (op) == SYMBOL_REF)
2590 else if (GET_CODE (op) != CONST
2591 || GET_CODE (XEXP (op, 0)) != PLUS
2592 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2593 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2598 rtx sum = XEXP (op, 0);
2599 HOST_WIDE_INT summand;
2601 /* We have to be careful here, because it is the referenced address
2602 that must be 32k from _SDA_BASE_, not just the symbol. */
2603 summand = INTVAL (XEXP (sum, 1));
2604 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2607 sym_ref = XEXP (sum, 0);
2610 return SYMBOL_REF_SMALL_P (sym_ref);
2616 /* Return true if either operand is a general purpose register. */
2619 gpr_or_gpr_p (rtx op0, rtx op1)
2621 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2622 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2626 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2629 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2631 switch (GET_CODE (op))
2634 if (RS6000_SYMBOL_REF_TLS_P (op))
2636 else if (CONSTANT_POOL_ADDRESS_P (op))
2638 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2646 else if (! strcmp (XSTR (op, 0), toc_label_name))
2655 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2656 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2658 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2667 constant_pool_expr_p (rtx op)
2671 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2675 toc_relative_expr_p (rtx op)
2679 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2683 legitimate_constant_pool_address_p (rtx x)
2686 && GET_CODE (x) == PLUS
2687 && GET_CODE (XEXP (x, 0)) == REG
2688 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2689 && constant_pool_expr_p (XEXP (x, 1)));
2693 rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x)
2695 return (DEFAULT_ABI == ABI_V4
2696 && !flag_pic && !TARGET_TOC
2697 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2698 && small_data_operand (x, mode));
2701 /* SPE offset addressing is limited to 5-bits worth of double words. */
2702 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2705 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2707 unsigned HOST_WIDE_INT offset, extra;
2709 if (GET_CODE (x) != PLUS)
2711 if (GET_CODE (XEXP (x, 0)) != REG)
2713 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2715 if (legitimate_constant_pool_address_p (x))
2717 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2720 offset = INTVAL (XEXP (x, 1));
2728 /* AltiVec vector modes. Only reg+reg addressing is valid and
2729 constant offset zero should not occur due to canonicalization.
2730 Allow any offset when not strict before reload. */
2737 /* SPE vector modes. */
2738 return SPE_CONST_OFFSET_OK (offset);
2741 if (TARGET_E500_DOUBLE)
2742 return SPE_CONST_OFFSET_OK (offset);
2745 /* On e500v2, we may have:
2747 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2749 Which gets addressed with evldd instructions. */
2750 if (TARGET_E500_DOUBLE)
2751 return SPE_CONST_OFFSET_OK (offset);
2753 if (mode == DFmode || !TARGET_POWERPC64)
2755 else if (offset & 3)
2761 if (mode == TFmode || !TARGET_POWERPC64)
2763 else if (offset & 3)
2774 return (offset < 0x10000) && (offset + extra < 0x10000);
2778 legitimate_indexed_address_p (rtx x, int strict)
2782 if (GET_CODE (x) != PLUS)
2788 /* Recognize the rtl generated by reload which we know will later be
2789 replaced with proper base and index regs. */
2791 && reload_in_progress
2792 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2796 return (REG_P (op0) && REG_P (op1)
2797 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2798 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2799 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2800 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2804 legitimate_indirect_address_p (rtx x, int strict)
2806 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2810 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2812 if (!TARGET_MACHO || !flag_pic
2813 || mode != SImode || GET_CODE (x) != MEM)
2817 if (GET_CODE (x) != LO_SUM)
2819 if (GET_CODE (XEXP (x, 0)) != REG)
2821 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2825 return CONSTANT_P (x);
2829 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2831 if (GET_CODE (x) != LO_SUM)
2833 if (GET_CODE (XEXP (x, 0)) != REG)
2835 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2837 /* Restrict addressing for DI because of our SUBREG hackery. */
2838 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2842 if (TARGET_ELF || TARGET_MACHO)
2844 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2848 if (GET_MODE_NUNITS (mode) != 1)
2850 if (GET_MODE_BITSIZE (mode) > 64
2851 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2852 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2855 return CONSTANT_P (x);
2862 /* Try machine-dependent ways of modifying an illegitimate address
2863 to be legitimate. If we find one, return the new, valid address.
2864 This is used from only one place: `memory_address' in explow.c.
2866 OLDX is the address as it was before break_out_memory_refs was
2867 called. In some cases it is useful to look at this to decide what
2870 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2872 It is always safe for this function to do nothing. It exists to
2873 recognize opportunities to optimize the output.
2875 On RS/6000, first check for the sum of a register with a constant
2876 integer that is out of range. If so, generate code to add the
2877 constant with the low-order 16 bits masked to the register and force
2878 this result into another register (this can be done with `cau').
2879 Then generate an address of REG+(CONST&0xffff), allowing for the
2880 possibility of bit 16 being a one.
2882 Then check for the sum of a register and something not constant, try to
2883 load the other things into a register and return the sum. */
2886 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2887 enum machine_mode mode)
2889 if (GET_CODE (x) == SYMBOL_REF)
2891 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2893 return rs6000_legitimize_tls_address (x, model);
2896 if (GET_CODE (x) == PLUS
2897 && GET_CODE (XEXP (x, 0)) == REG
2898 && GET_CODE (XEXP (x, 1)) == CONST_INT
2899 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2901 HOST_WIDE_INT high_int, low_int;
2903 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2904 high_int = INTVAL (XEXP (x, 1)) - low_int;
2905 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2906 GEN_INT (high_int)), 0);
2907 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2909 else if (GET_CODE (x) == PLUS
2910 && GET_CODE (XEXP (x, 0)) == REG
2911 && GET_CODE (XEXP (x, 1)) != CONST_INT
2912 && GET_MODE_NUNITS (mode) == 1
2913 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2915 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2917 && (TARGET_POWERPC64 || mode != DImode)
2920 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2921 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2923 else if (ALTIVEC_VECTOR_MODE (mode))
2927 /* Make sure both operands are registers. */
2928 if (GET_CODE (x) == PLUS)
2929 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2930 force_reg (Pmode, XEXP (x, 1)));
2932 reg = force_reg (Pmode, x);
2935 else if (SPE_VECTOR_MODE (mode)
2936 || (TARGET_E500_DOUBLE && (mode == DFmode
2937 || mode == DImode)))
2941 /* We accept [reg + reg] and [reg + OFFSET]. */
2943 if (GET_CODE (x) == PLUS)
2945 rtx op1 = XEXP (x, 0);
2946 rtx op2 = XEXP (x, 1);
2948 op1 = force_reg (Pmode, op1);
2950 if (GET_CODE (op2) != REG
2951 && (GET_CODE (op2) != CONST_INT
2952 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2953 op2 = force_reg (Pmode, op2);
2955 return gen_rtx_PLUS (Pmode, op1, op2);
2958 return force_reg (Pmode, x);
2964 && GET_CODE (x) != CONST_INT
2965 && GET_CODE (x) != CONST_DOUBLE
2967 && GET_MODE_NUNITS (mode) == 1
2968 && (GET_MODE_BITSIZE (mode) <= 32
2969 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2971 rtx reg = gen_reg_rtx (Pmode);
2972 emit_insn (gen_elf_high (reg, x));
2973 return gen_rtx_LO_SUM (Pmode, reg, x);
2975 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2978 && ! MACHO_DYNAMIC_NO_PIC_P
2980 && GET_CODE (x) != CONST_INT
2981 && GET_CODE (x) != CONST_DOUBLE
2983 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2987 rtx reg = gen_reg_rtx (Pmode);
2988 emit_insn (gen_macho_high (reg, x));
2989 return gen_rtx_LO_SUM (Pmode, reg, x);
2992 && constant_pool_expr_p (x)
2993 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2995 return create_TOC_reference (x);
3001 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3002 We need to emit DTP-relative relocations. */
3005 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3010 fputs ("\t.long\t", file);
3013 fputs (DOUBLE_INT_ASM_OP, file);
3018 output_addr_const (file, x);
3019 fputs ("@dtprel+0x8000", file);
3022 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3024 static GTY(()) rtx rs6000_tls_symbol;
3026 rs6000_tls_get_addr (void)
3028 if (!rs6000_tls_symbol)
3029 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3031 return rs6000_tls_symbol;
3034 /* Construct the SYMBOL_REF for TLS GOT references. */
3036 static GTY(()) rtx rs6000_got_symbol;
3038 rs6000_got_sym (void)
3040 if (!rs6000_got_symbol)
3042 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3043 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3044 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3047 return rs6000_got_symbol;
3050 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3051 this (thread-local) address. */
3054 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3058 dest = gen_reg_rtx (Pmode);
3059 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3065 tlsreg = gen_rtx_REG (Pmode, 13);
3066 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3070 tlsreg = gen_rtx_REG (Pmode, 2);
3071 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3075 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3079 tmp = gen_reg_rtx (Pmode);
3082 tlsreg = gen_rtx_REG (Pmode, 13);
3083 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3087 tlsreg = gen_rtx_REG (Pmode, 2);
3088 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3092 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3094 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3099 rtx r3, got, tga, tmp1, tmp2, eqv;
3101 /* We currently use relocations like @got@tlsgd for tls, which
3102 means the linker will handle allocation of tls entries, placing
3103 them in the .got section. So use a pointer to the .got section,
3104 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3105 or to secondary GOT sections used by 32-bit -fPIC. */
3107 got = gen_rtx_REG (Pmode, 2);
3111 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3114 rtx gsym = rs6000_got_sym ();
3115 got = gen_reg_rtx (Pmode);
3117 rs6000_emit_move (got, gsym, Pmode);
3120 rtx tempLR, tmp3, mem;
3123 tempLR = gen_reg_rtx (Pmode);
3124 tmp1 = gen_reg_rtx (Pmode);
3125 tmp2 = gen_reg_rtx (Pmode);
3126 tmp3 = gen_reg_rtx (Pmode);
3127 mem = gen_const_mem (Pmode, tmp1);
3129 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3130 emit_move_insn (tmp1, tempLR);
3131 emit_move_insn (tmp2, mem);
3132 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3133 last = emit_move_insn (got, tmp3);
3134 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3136 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3138 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3144 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3146 r3 = gen_rtx_REG (Pmode, 3);
3148 insn = gen_tls_gd_64 (r3, got, addr);
3150 insn = gen_tls_gd_32 (r3, got, addr);
3153 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3154 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3155 insn = emit_call_insn (insn);
3156 CONST_OR_PURE_CALL_P (insn) = 1;
3157 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3158 insn = get_insns ();
3160 emit_libcall_block (insn, dest, r3, addr);
3162 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3164 r3 = gen_rtx_REG (Pmode, 3);
3166 insn = gen_tls_ld_64 (r3, got);
3168 insn = gen_tls_ld_32 (r3, got);
3171 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3172 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3173 insn = emit_call_insn (insn);
3174 CONST_OR_PURE_CALL_P (insn) = 1;
3175 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3176 insn = get_insns ();
3178 tmp1 = gen_reg_rtx (Pmode);
3179 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3181 emit_libcall_block (insn, tmp1, r3, eqv);
3182 if (rs6000_tls_size == 16)
3185 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3187 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3189 else if (rs6000_tls_size == 32)
3191 tmp2 = gen_reg_rtx (Pmode);
3193 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3195 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3198 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3200 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3204 tmp2 = gen_reg_rtx (Pmode);
3206 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3208 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3210 insn = gen_rtx_SET (Pmode, dest,
3211 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3217 /* IE, or 64 bit offset LE. */
3218 tmp2 = gen_reg_rtx (Pmode);
3220 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3222 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3225 insn = gen_tls_tls_64 (dest, tmp2, addr);
3227 insn = gen_tls_tls_32 (dest, tmp2, addr);
3235 /* Return 1 if X contains a thread-local symbol. */
3238 rs6000_tls_referenced_p (rtx x)
3240 if (! TARGET_HAVE_TLS)
3243 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3246 /* Return 1 if *X is a thread-local symbol. This is the same as
3247 rs6000_tls_symbol_ref except for the type of the unused argument. */
3250 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3252 return RS6000_SYMBOL_REF_TLS_P (*x);
3255 /* The convention appears to be to define this wherever it is used.
3256 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3257 is now used here. */
3258 #ifndef REG_MODE_OK_FOR_BASE_P
3259 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3262 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3263 replace the input X, or the original X if no replacement is called for.
3264 The output parameter *WIN is 1 if the calling macro should goto WIN,
3267 For RS/6000, we wish to handle large displacements off a base
3268 register by splitting the addend across an addiu/addis and the mem insn.
3269 This cuts number of extra insns needed from 3 to 1.
3271 On Darwin, we use this to generate code for floating point constants.
3272 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3273 The Darwin code is inside #if TARGET_MACHO because only then is
3274 machopic_function_base_name() defined. */
3276 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3277 int opnum, int type,
3278 int ind_levels ATTRIBUTE_UNUSED, int *win)
3280 /* We must recognize output that we have already generated ourselves. */
3281 if (GET_CODE (x) == PLUS
3282 && GET_CODE (XEXP (x, 0)) == PLUS
3283 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3284 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3285 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3287 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3288 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3289 opnum, (enum reload_type)type);
3295 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3296 && GET_CODE (x) == LO_SUM
3297 && GET_CODE (XEXP (x, 0)) == PLUS
3298 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3299 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3300 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3301 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3302 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3303 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3304 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3306 /* Result of previous invocation of this function on Darwin
3307 floating point constant. */
3308 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3309 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3310 opnum, (enum reload_type)type);
3316 /* Force ld/std non-word aligned offset into base register by wrapping
3318 if (GET_CODE (x) == PLUS
3319 && GET_CODE (XEXP (x, 0)) == REG
3320 && REGNO (XEXP (x, 0)) < 32
3321 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3322 && GET_CODE (XEXP (x, 1)) == CONST_INT
3323 && (INTVAL (XEXP (x, 1)) & 3) != 0
3324 && !ALTIVEC_VECTOR_MODE (mode)
3325 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3326 && TARGET_POWERPC64)
3328 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3329 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3330 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3331 opnum, (enum reload_type) type);
3336 if (GET_CODE (x) == PLUS
3337 && GET_CODE (XEXP (x, 0)) == REG
3338 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3339 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3340 && GET_CODE (XEXP (x, 1)) == CONST_INT
3341 && !SPE_VECTOR_MODE (mode)
3342 && !(TARGET_E500_DOUBLE && (mode == DFmode
3344 && !ALTIVEC_VECTOR_MODE (mode))
3346 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3347 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3349 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3351 /* Check for 32-bit overflow. */
3352 if (high + low != val)
3358 /* Reload the high part into a base reg; leave the low part
3359 in the mem directly. */
3361 x = gen_rtx_PLUS (GET_MODE (x),
3362 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3366 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3367 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3368 opnum, (enum reload_type)type);
3373 if (GET_CODE (x) == SYMBOL_REF
3374 && !ALTIVEC_VECTOR_MODE (mode)
3376 && DEFAULT_ABI == ABI_DARWIN
3377 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3379 && DEFAULT_ABI == ABI_V4
3382 /* Don't do this for TFmode, since the result isn't offsettable.
3383 The same goes for DImode without 64-bit gprs. */
3385 && (mode != DImode || TARGET_POWERPC64))
3390 rtx offset = gen_rtx_CONST (Pmode,
3391 gen_rtx_MINUS (Pmode, x,
3392 machopic_function_base_sym ()));
3393 x = gen_rtx_LO_SUM (GET_MODE (x),
3394 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3395 gen_rtx_HIGH (Pmode, offset)), offset);
3399 x = gen_rtx_LO_SUM (GET_MODE (x),
3400 gen_rtx_HIGH (Pmode, x), x);
3402 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3403 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3404 opnum, (enum reload_type)type);
3409 /* Reload an offset address wrapped by an AND that represents the
3410 masking of the lower bits. Strip the outer AND and let reload
3411 convert the offset address into an indirect address. */
3413 && ALTIVEC_VECTOR_MODE (mode)
3414 && GET_CODE (x) == AND
3415 && GET_CODE (XEXP (x, 0)) == PLUS
3416 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3417 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3418 && GET_CODE (XEXP (x, 1)) == CONST_INT
3419 && INTVAL (XEXP (x, 1)) == -16)
3427 && constant_pool_expr_p (x)
3428 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3430 (x) = create_TOC_reference (x);
3438 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3439 that is a valid memory address for an instruction.
3440 The MODE argument is the machine mode for the MEM expression
3441 that wants to use this address.
3443 On the RS/6000, there are four valid address: a SYMBOL_REF that
3444 refers to a constant pool entry of an address (or the sum of it
3445 plus a constant), a short (16-bit signed) constant plus a register,
3446 the sum of two registers, or a register indirect, possibly with an
3447 auto-increment. For DFmode and DImode with a constant plus register,
3448 we must ensure that both words are addressable or PowerPC64 with offset
3451 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3452 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3453 adjacent memory cells are accessed by adding word-sized offsets
3454 during assembly output. */
3456 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3458 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3460 && ALTIVEC_VECTOR_MODE (mode)
3461 && GET_CODE (x) == AND
3462 && GET_CODE (XEXP (x, 1)) == CONST_INT
3463 && INTVAL (XEXP (x, 1)) == -16)
3466 if (RS6000_SYMBOL_REF_TLS_P (x))
3468 if (legitimate_indirect_address_p (x, reg_ok_strict))
3470 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3471 && !ALTIVEC_VECTOR_MODE (mode)
3472 && !SPE_VECTOR_MODE (mode)
3473 /* Restrict addressing for DI because of our SUBREG hackery. */
3474 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3476 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3478 if (rs6000_legitimate_small_data_p (mode, x))
3480 if (legitimate_constant_pool_address_p (x))
3482 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3484 && GET_CODE (x) == PLUS
3485 && GET_CODE (XEXP (x, 0)) == REG
3486 && (XEXP (x, 0) == virtual_stack_vars_rtx
3487 || XEXP (x, 0) == arg_pointer_rtx)
3488 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3490 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3494 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3496 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3497 && (TARGET_POWERPC64 || mode != DImode)
3498 && legitimate_indexed_address_p (x, reg_ok_strict))
3500 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3505 /* Go to LABEL if ADDR (a legitimate address expression)
3506 has an effect that depends on the machine mode it is used for.
3508 On the RS/6000 this is true of all integral offsets (since AltiVec
3509 modes don't allow them) or is a pre-increment or decrement.
3511 ??? Except that due to conceptual problems in offsettable_address_p
3512 we can't really report the problems of integral offsets. So leave
3513 this assuming that the adjustable offset must be valid for the
3514 sub-words of a TFmode operand, which is what we had before. */
3517 rs6000_mode_dependent_address (rtx addr)
3519 switch (GET_CODE (addr))
3522 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3524 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3525 return val + 12 + 0x8000 >= 0x10000;
3534 return TARGET_UPDATE;
3543 /* Return number of consecutive hard regs needed starting at reg REGNO
3544 to hold something of mode MODE.
3545 This is ordinarily the length in words of a value of mode MODE
3546 but can be less for certain modes in special long registers.
3548 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3549 scalar instructions. The upper 32 bits are only available to the
3552 POWER and PowerPC GPRs hold 32 bits worth;
3553 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3556 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3558 if (FP_REGNO_P (regno))
3559 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3561 if (TARGET_E500_DOUBLE && mode == DFmode)
3564 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3565 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3567 if (ALTIVEC_REGNO_P (regno))
3569 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3571 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3574 /* Change register usage conditional on target flags. */
3576 rs6000_conditional_register_usage (void)
3580 /* Set MQ register fixed (already call_used) if not POWER
3581 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3586 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3588 fixed_regs[13] = call_used_regs[13]
3589 = call_really_used_regs[13] = 1;
3591 /* Conditionally disable FPRs. */
3592 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3593 for (i = 32; i < 64; i++)
3594 fixed_regs[i] = call_used_regs[i]
3595 = call_really_used_regs[i] = 1;
3597 /* The TOC register is not killed across calls in a way that is
3598 visible to the compiler. */
3599 if (DEFAULT_ABI == ABI_AIX)
3600 call_really_used_regs[2] = 0;
3602 if (DEFAULT_ABI == ABI_V4
3603 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3605 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3607 if (DEFAULT_ABI == ABI_V4
3608 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3610 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3611 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3612 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3614 if (DEFAULT_ABI == ABI_DARWIN
3615 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3616 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3617 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3618 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3620 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3621 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3622 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3625 global_regs[VSCR_REGNO] = 1;
3629 global_regs[SPEFSCR_REGNO] = 1;
3630 fixed_regs[FIXED_SCRATCH]
3631 = call_used_regs[FIXED_SCRATCH]
3632 = call_really_used_regs[FIXED_SCRATCH] = 1;
3635 if (! TARGET_ALTIVEC)
3637 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3638 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3639 call_really_used_regs[VRSAVE_REGNO] = 1;
3642 if (TARGET_ALTIVEC_ABI)
3643 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3644 call_used_regs[i] = call_really_used_regs[i] = 1;
3647 /* Try to output insns to set TARGET equal to the constant C if it can
3648 be done in less than N insns. Do all computations in MODE.
3649 Returns the place where the output has been placed if it can be
3650 done and the insns have been emitted. If it would take more than N
3651 insns, zero is returned and no insns and emitted. */
3654 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3655 rtx source, int n ATTRIBUTE_UNUSED)
3657 rtx result, insn, set;
3658 HOST_WIDE_INT c0, c1;
3665 dest = gen_reg_rtx (mode);
3666 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3670 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3672 emit_insn (gen_rtx_SET (VOIDmode, result,
3673 GEN_INT (INTVAL (source)
3674 & (~ (HOST_WIDE_INT) 0xffff))));
3675 emit_insn (gen_rtx_SET (VOIDmode, dest,
3676 gen_rtx_IOR (SImode, result,
3677 GEN_INT (INTVAL (source) & 0xffff))));
3682 switch (GET_CODE (source))
3685 c0 = INTVAL (source);
3690 #if HOST_BITS_PER_WIDE_INT >= 64
3691 c0 = CONST_DOUBLE_LOW (source);
3694 c0 = CONST_DOUBLE_LOW (source);
3695 c1 = CONST_DOUBLE_HIGH (source);
3703 result = rs6000_emit_set_long_const (dest, c0, c1);
3710 insn = get_last_insn ();
3711 set = single_set (insn);
3712 if (! CONSTANT_P (SET_SRC (set)))
3713 set_unique_reg_note (insn, REG_EQUAL, source);
3718 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3719 fall back to a straight forward decomposition. We do this to avoid
3720 exponential run times encountered when looking for longer sequences
3721 with rs6000_emit_set_const. */
3723 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3725 if (!TARGET_POWERPC64)
3727 rtx operand1, operand2;
3729 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3731 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3733 emit_move_insn (operand1, GEN_INT (c1));
3734 emit_move_insn (operand2, GEN_INT (c2));
3738 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3741 ud2 = (c1 & 0xffff0000) >> 16;
3742 #if HOST_BITS_PER_WIDE_INT >= 64
3746 ud4 = (c2 & 0xffff0000) >> 16;
3748 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3749 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3752 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3754 emit_move_insn (dest, GEN_INT (ud1));
3757 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3758 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3761 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3764 emit_move_insn (dest, GEN_INT (ud2 << 16));
3766 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3768 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3769 || (ud4 == 0 && ! (ud3 & 0x8000)))
3772 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3775 emit_move_insn (dest, GEN_INT (ud3 << 16));
3778 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3779 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3781 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3786 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3789 emit_move_insn (dest, GEN_INT (ud4 << 16));
3792 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3794 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3796 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3797 GEN_INT (ud2 << 16)));
3799 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3805 /* Helper for the following. Get rid of [r+r] memory refs
3806 in cases where it won't work (TImode, TFmode). */
3809 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3811 if (GET_CODE (operands[0]) == MEM
3812 && GET_CODE (XEXP (operands[0], 0)) != REG
3813 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3814 && ! reload_in_progress)
3816 = replace_equiv_address (operands[0],
3817 copy_addr_to_reg (XEXP (operands[0], 0)));
3819 if (GET_CODE (operands[1]) == MEM
3820 && GET_CODE (XEXP (operands[1], 0)) != REG
3821 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3822 && ! reload_in_progress)
3824 = replace_equiv_address (operands[1],
3825 copy_addr_to_reg (XEXP (operands[1], 0)));
3828 /* Emit a move from SOURCE to DEST in mode MODE. */
3830 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3834 operands[1] = source;
3836 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3837 if (GET_CODE (operands[1]) == CONST_DOUBLE
3838 && ! FLOAT_MODE_P (mode)
3839 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3841 /* FIXME. This should never happen. */
3842 /* Since it seems that it does, do the safe thing and convert
3844 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3846 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3847 || FLOAT_MODE_P (mode)
3848 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3849 || CONST_DOUBLE_LOW (operands[1]) < 0)
3850 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3851 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3853 /* Check if GCC is setting up a block move that will end up using FP
3854 registers as temporaries. We must make sure this is acceptable. */
3855 if (GET_CODE (operands[0]) == MEM
3856 && GET_CODE (operands[1]) == MEM
3858 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3859 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3860 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3861 ? 32 : MEM_ALIGN (operands[0])))
3862 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3864 : MEM_ALIGN (operands[1]))))
3865 && ! MEM_VOLATILE_P (operands [0])
3866 && ! MEM_VOLATILE_P (operands [1]))
3868 emit_move_insn (adjust_address (operands[0], SImode, 0),
3869 adjust_address (operands[1], SImode, 0));
3870 emit_move_insn (adjust_address (operands[0], SImode, 4),
3871 adjust_address (operands[1], SImode, 4));
3875 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3876 && !gpc_reg_operand (operands[1], mode))
3877 operands[1] = force_reg (mode, operands[1]);
3879 if (mode == SFmode && ! TARGET_POWERPC
3880 && TARGET_HARD_FLOAT && TARGET_FPRS
3881 && GET_CODE (operands[0]) == MEM)
3885 if (reload_in_progress || reload_completed)
3886 regnum = true_regnum (operands[1]);
3887 else if (GET_CODE (operands[1]) == REG)
3888 regnum = REGNO (operands[1]);
3892 /* If operands[1] is a register, on POWER it may have
3893 double-precision data in it, so truncate it to single
3895 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3898 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3899 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3900 operands[1] = newreg;
3904 /* Recognize the case where operand[1] is a reference to thread-local
3905 data and load its address to a register. */
3906 if (rs6000_tls_referenced_p (operands[1]))
3908 enum tls_model model;
3909 rtx tmp = operands[1];
3912 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3914 addend = XEXP (XEXP (tmp, 0), 1);
3915 tmp = XEXP (XEXP (tmp, 0), 0);
3918 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3919 model = SYMBOL_REF_TLS_MODEL (tmp);
3920 gcc_assert (model != 0);
3922 tmp = rs6000_legitimize_tls_address (tmp, model);
3925 tmp = gen_rtx_PLUS (mode, tmp, addend);
3926 tmp = force_operand (tmp, operands[0]);
3931 /* Handle the case where reload calls us with an invalid address. */
3932 if (reload_in_progress && mode == Pmode
3933 && (! general_operand (operands[1], mode)
3934 || ! nonimmediate_operand (operands[0], mode)))
3937 /* 128-bit constant floating-point values on Darwin should really be
3938 loaded as two parts. */
3939 if (!TARGET_IEEEQUAD
3940 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3941 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3943 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3944 know how to get a DFmode SUBREG of a TFmode. */
3945 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3946 simplify_gen_subreg (DImode, operands[1], mode, 0),
3948 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3949 GET_MODE_SIZE (DImode)),
3950 simplify_gen_subreg (DImode, operands[1], mode,
3951 GET_MODE_SIZE (DImode)),
3956 /* FIXME: In the long term, this switch statement should go away
3957 and be replaced by a sequence of tests based on things like
3963 if (CONSTANT_P (operands[1])
3964 && GET_CODE (operands[1]) != CONST_INT)
3965 operands[1] = force_const_mem (mode, operands[1]);
3969 rs6000_eliminate_indexed_memrefs (operands);
3974 if (CONSTANT_P (operands[1])
3975 && ! easy_fp_constant (operands[1], mode))
3976 operands[1] = force_const_mem (mode, operands[1]);
3987 if (CONSTANT_P (operands[1])
3988 && !easy_vector_constant (operands[1], mode))
3989 operands[1] = force_const_mem (mode, operands[1]);
3994 /* Use default pattern for address of ELF small data */
3997 && DEFAULT_ABI == ABI_V4
3998 && (GET_CODE (operands[1]) == SYMBOL_REF
3999 || GET_CODE (operands[1]) == CONST)
4000 && small_data_operand (operands[1], mode))
4002 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4006 if (DEFAULT_ABI == ABI_V4
4007 && mode == Pmode && mode == SImode
4008 && flag_pic == 1 && got_operand (operands[1], mode))
4010 emit_insn (gen_movsi_got (operands[0], operands[1]));
4014 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4018 && CONSTANT_P (operands[1])
4019 && GET_CODE (operands[1]) != HIGH
4020 && GET_CODE (operands[1]) != CONST_INT)
4022 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4024 /* If this is a function address on -mcall-aixdesc,
4025 convert it to the address of the descriptor. */
4026 if (DEFAULT_ABI == ABI_AIX
4027 && GET_CODE (operands[1]) == SYMBOL_REF
4028 && XSTR (operands[1], 0)[0] == '.')
4030 const char *name = XSTR (operands[1], 0);
4032 while (*name == '.')
4034 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4035 CONSTANT_POOL_ADDRESS_P (new_ref)
4036 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4037 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4038 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4039 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4040 operands[1] = new_ref;
4043 if (DEFAULT_ABI == ABI_DARWIN)
4046 if (MACHO_DYNAMIC_NO_PIC_P)
4048 /* Take care of any required data indirection. */
4049 operands[1] = rs6000_machopic_legitimize_pic_address (
4050 operands[1], mode, operands[0]);
4051 if (operands[0] != operands[1])
4052 emit_insn (gen_rtx_SET (VOIDmode,
4053 operands[0], operands[1]));
4057 emit_insn (gen_macho_high (target, operands[1]));
4058 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4062 emit_insn (gen_elf_high (target, operands[1]));
4063 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4067 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4068 and we have put it in the TOC, we just need to make a TOC-relative
4071 && GET_CODE (operands[1]) == SYMBOL_REF
4072 && constant_pool_expr_p (operands[1])
4073 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4074 get_pool_mode (operands[1])))
4076 operands[1] = create_TOC_reference (operands[1]);
4078 else if (mode == Pmode
4079 && CONSTANT_P (operands[1])
4080 && ((GET_CODE (operands[1]) != CONST_INT
4081 && ! easy_fp_constant (operands[1], mode))
4082 || (GET_CODE (operands[1]) == CONST_INT
4083 && num_insns_constant (operands[1], mode) > 2)
4084 || (GET_CODE (operands[0]) == REG
4085 && FP_REGNO_P (REGNO (operands[0]))))
4086 && GET_CODE (operands[1]) != HIGH
4087 && ! legitimate_constant_pool_address_p (operands[1])
4088 && ! toc_relative_expr_p (operands[1]))
4090 /* Emit a USE operation so that the constant isn't deleted if
4091 expensive optimizations are turned on because nobody
4092 references it. This should only be done for operands that
4093 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4094 This should not be done for operands that contain LABEL_REFs.
4095 For now, we just handle the obvious case. */
4096 if (GET_CODE (operands[1]) != LABEL_REF)
4097 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4100 /* Darwin uses a special PIC legitimizer. */
4101 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4104 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4106 if (operands[0] != operands[1])
4107 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4112 /* If we are to limit the number of things we put in the TOC and
4113 this is a symbol plus a constant we can add in one insn,
4114 just put the symbol in the TOC and add the constant. Don't do
4115 this if reload is in progress. */
4116 if (GET_CODE (operands[1]) == CONST
4117 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4118 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4119 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4120 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4121 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4122 && ! side_effects_p (operands[0]))
4125 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4126 rtx other = XEXP (XEXP (operands[1], 0), 1);
4128 sym = force_reg (mode, sym);
4130 emit_insn (gen_addsi3 (operands[0], sym, other));
4132 emit_insn (gen_adddi3 (operands[0], sym, other));
4136 operands[1] = force_const_mem (mode, operands[1]);
4139 && constant_pool_expr_p (XEXP (operands[1], 0))
4140 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4141 get_pool_constant (XEXP (operands[1], 0)),
4142 get_pool_mode (XEXP (operands[1], 0))))
4145 = gen_const_mem (mode,
4146 create_TOC_reference (XEXP (operands[1], 0)));
4147 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4153 rs6000_eliminate_indexed_memrefs (operands);
4157 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4159 gen_rtx_SET (VOIDmode,
4160 operands[0], operands[1]),
4161 gen_rtx_CLOBBER (VOIDmode,
4162 gen_rtx_SCRATCH (SImode)))));
4171 /* Above, we may have called force_const_mem which may have returned
4172 an invalid address. If we can, fix this up; otherwise, reload will
4173 have to deal with it. */
4174 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4175 operands[1] = validize_mem (operands[1]);
4178 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4181 /* Nonzero if we can use a floating-point register to pass this arg. */
4182 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4183 (SCALAR_FLOAT_MODE_P (MODE) \
4184 && !DECIMAL_FLOAT_MODE_P (MODE) \
4185 && (CUM)->fregno <= FP_ARG_MAX_REG \
4186 && TARGET_HARD_FLOAT && TARGET_FPRS)
4188 /* Nonzero if we can use an AltiVec register to pass this arg. */
4189 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4190 (ALTIVEC_VECTOR_MODE (MODE) \
4191 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4192 && TARGET_ALTIVEC_ABI \
4195 /* Return a nonzero value to say to return the function value in
4196 memory, just as large structures are always returned. TYPE will be
4197 the data type of the value, and FNTYPE will be the type of the
4198 function doing the returning, or @code{NULL} for libcalls.
4200 The AIX ABI for the RS/6000 specifies that all structures are
4201 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4202 specifies that structures <= 8 bytes are returned in r3/r4, but a
4203 draft put them in memory, and GCC used to implement the draft
4204 instead of the final standard. Therefore, aix_struct_return
4205 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4206 compatibility can change DRAFT_V4_STRUCT_RET to override the
4207 default, and -m switches get the final word. See
4208 rs6000_override_options for more details.
4210 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4211 long double support is enabled. These values are returned in memory.
4213 int_size_in_bytes returns -1 for variable size objects, which go in
4214 memory always. The cast to unsigned makes -1 > 8. */
4217 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4219 /* In the darwin64 abi, try to use registers for larger structs
4221 if (rs6000_darwin64_abi
4222 && TREE_CODE (type) == RECORD_TYPE
4223 && int_size_in_bytes (type) > 0)
4225 CUMULATIVE_ARGS valcum;
4229 valcum.fregno = FP_ARG_MIN_REG;
4230 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4231 /* Do a trial code generation as if this were going to be passed
4232 as an argument; if any part goes in memory, we return NULL. */
4233 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4236 /* Otherwise fall through to more conventional ABI rules. */
4239 if (AGGREGATE_TYPE_P (type)
4240 && (aix_struct_return
4241 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4244 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4245 modes only exist for GCC vector types if -maltivec. */
4246 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4247 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4250 /* Return synthetic vectors in memory. */
4251 if (TREE_CODE (type) == VECTOR_TYPE
4252 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4254 static bool warned_for_return_big_vectors = false;
4255 if (!warned_for_return_big_vectors)
4257 warning (0, "GCC vector returned by reference: "
4258 "non-standard ABI extension with no compatibility guarantee");
4259 warned_for_return_big_vectors = true;
4264 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4270 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4271 for a call to a function whose data type is FNTYPE.
4272 For a library call, FNTYPE is 0.
4274 For incoming args we set the number of arguments in the prototype large
4275 so we never return a PARALLEL. */
4278 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4279 rtx libname ATTRIBUTE_UNUSED, int incoming,
4280 int libcall, int n_named_args)
4282 static CUMULATIVE_ARGS zero_cumulative;
4284 *cum = zero_cumulative;
4286 cum->fregno = FP_ARG_MIN_REG;
4287 cum->vregno = ALTIVEC_ARG_MIN_REG;
4288 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4289 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4290 ? CALL_LIBCALL : CALL_NORMAL);
4291 cum->sysv_gregno = GP_ARG_MIN_REG;
4292 cum->stdarg = fntype
4293 && (TYPE_ARG_TYPES (fntype) != 0
4294 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4295 != void_type_node));
4297 cum->nargs_prototype = 0;
4298 if (incoming || cum->prototype)
4299 cum->nargs_prototype = n_named_args;
4301 /* Check for a longcall attribute. */
4302 if ((!fntype && rs6000_default_long_calls)
4304 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4305 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4306 cum->call_cookie |= CALL_LONG;
4308 if (TARGET_DEBUG_ARG)
4310 fprintf (stderr, "\ninit_cumulative_args:");
4313 tree ret_type = TREE_TYPE (fntype);
4314 fprintf (stderr, " ret code = %s,",
4315 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4318 if (cum->call_cookie & CALL_LONG)
4319 fprintf (stderr, " longcall,");
4321 fprintf (stderr, " proto = %d, nargs = %d\n",
4322 cum->prototype, cum->nargs_prototype);
4327 && TARGET_ALTIVEC_ABI
4328 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4330 error ("cannot return value in vector register because"
4331 " altivec instructions are disabled, use -maltivec"
4336 /* Return true if TYPE must be passed on the stack and not in registers. */
4339 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4341 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4342 return must_pass_in_stack_var_size (mode, type);
4344 return must_pass_in_stack_var_size_or_pad (mode, type);
4347 /* If defined, a C expression which determines whether, and in which
4348 direction, to pad out an argument with extra space. The value
4349 should be of type `enum direction': either `upward' to pad above
4350 the argument, `downward' to pad below, or `none' to inhibit
4353 For the AIX ABI structs are always stored left shifted in their
4357 function_arg_padding (enum machine_mode mode, tree type)
4359 #ifndef AGGREGATE_PADDING_FIXED
4360 #define AGGREGATE_PADDING_FIXED 0
4362 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4363 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4366 if (!AGGREGATE_PADDING_FIXED)
4368 /* GCC used to pass structures of the same size as integer types as
4369 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4370 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4371 passed padded downward, except that -mstrict-align further
4372 muddied the water in that multi-component structures of 2 and 4
4373 bytes in size were passed padded upward.
4375 The following arranges for best compatibility with previous
4376 versions of gcc, but removes the -mstrict-align dependency. */
4377 if (BYTES_BIG_ENDIAN)
4379 HOST_WIDE_INT size = 0;
4381 if (mode == BLKmode)
4383 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4384 size = int_size_in_bytes (type);
4387 size = GET_MODE_SIZE (mode);
4389 if (size == 1 || size == 2 || size == 4)
4395 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4397 if (type != 0 && AGGREGATE_TYPE_P (type))
4401 /* Fall back to the default. */
4402 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4405 /* If defined, a C expression that gives the alignment boundary, in bits,
4406 of an argument with the specified mode and type. If it is not defined,
4407 PARM_BOUNDARY is used for all arguments.
4409 V.4 wants long longs to be double word aligned.
4410 Doubleword align SPE vectors.
4411 Quadword align Altivec vectors.
4412 Quadword align large synthetic vector types. */
4415 function_arg_boundary (enum machine_mode mode, tree type)
4417 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4419 else if (SPE_VECTOR_MODE (mode)
4420 || (type && TREE_CODE (type) == VECTOR_TYPE
4421 && int_size_in_bytes (type) >= 8
4422 && int_size_in_bytes (type) < 16))
4424 else if (ALTIVEC_VECTOR_MODE (mode)
4425 || (type && TREE_CODE (type) == VECTOR_TYPE
4426 && int_size_in_bytes (type) >= 16))
4428 else if (rs6000_darwin64_abi && mode == BLKmode
4429 && type && TYPE_ALIGN (type) > 64)
4432 return PARM_BOUNDARY;
4435 /* For a function parm of MODE and TYPE, return the starting word in
4436 the parameter area. NWORDS of the parameter area are already used. */
4439 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4442 unsigned int parm_offset;
4444 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4445 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4446 return nwords + (-(parm_offset + nwords) & align);
4449 /* Compute the size (in words) of a function argument. */
4451 static unsigned long
4452 rs6000_arg_size (enum machine_mode mode, tree type)
4456 if (mode != BLKmode)
4457 size = GET_MODE_SIZE (mode);
4459 size = int_size_in_bytes (type);
4462 return (size + 3) >> 2;
4464 return (size + 7) >> 3;
4467 /* Use this to flush pending int fields. */
4470 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4471 HOST_WIDE_INT bitpos)
4473 unsigned int startbit, endbit;
4474 int intregs, intoffset;
4475 enum machine_mode mode;
4477 if (cum->intoffset == -1)
4480 intoffset = cum->intoffset;
4481 cum->intoffset = -1;
4483 if (intoffset % BITS_PER_WORD != 0)
4485 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4487 if (mode == BLKmode)
4489 /* We couldn't find an appropriate mode, which happens,
4490 e.g., in packed structs when there are 3 bytes to load.
4491 Back intoffset back to the beginning of the word in this
4493 intoffset = intoffset & -BITS_PER_WORD;
4497 startbit = intoffset & -BITS_PER_WORD;
4498 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4499 intregs = (endbit - startbit) / BITS_PER_WORD;
4500 cum->words += intregs;
4503 /* The darwin64 ABI calls for us to recurse down through structs,
4504 looking for elements passed in registers. Unfortunately, we have
4505 to track int register count here also because of misalignments
4506 in powerpc alignment mode. */
4509 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4511 HOST_WIDE_INT startbitpos)
4515 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4516 if (TREE_CODE (f) == FIELD_DECL)
4518 HOST_WIDE_INT bitpos = startbitpos;
4519 tree ftype = TREE_TYPE (f);
4520 enum machine_mode mode = TYPE_MODE (ftype);
4522 if (DECL_SIZE (f) != 0
4523 && host_integerp (bit_position (f), 1))
4524 bitpos += int_bit_position (f);
4526 /* ??? FIXME: else assume zero offset. */
4528 if (TREE_CODE (ftype) == RECORD_TYPE)
4529 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4530 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4532 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4533 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4534 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4536 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4538 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4542 else if (cum->intoffset == -1)
4543 cum->intoffset = bitpos;
4547 /* Update the data in CUM to advance over an argument
4548 of mode MODE and data type TYPE.
4549 (TYPE is null for libcalls where that information may not be available.)
4551 Note that for args passed by reference, function_arg will be called
4552 with MODE and TYPE set to that of the pointer to the arg, not the arg
4556 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4557 tree type, int named, int depth)
4561 /* Only tick off an argument if we're not recursing. */
4563 cum->nargs_prototype--;
4565 if (TARGET_ALTIVEC_ABI
4566 && (ALTIVEC_VECTOR_MODE (mode)
4567 || (type && TREE_CODE (type) == VECTOR_TYPE
4568 && int_size_in_bytes (type) == 16)))
4572 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4575 if (!TARGET_ALTIVEC)
4576 error ("cannot pass argument in vector register because"
4577 " altivec instructions are disabled, use -maltivec"
4580 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4581 even if it is going to be passed in a vector register.
4582 Darwin does the same for variable-argument functions. */
4583 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4584 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4594 /* Vector parameters must be 16-byte aligned. This places
4595 them at 2 mod 4 in terms of words in 32-bit mode, since
4596 the parameter save area starts at offset 24 from the
4597 stack. In 64-bit mode, they just have to start on an
4598 even word, since the parameter save area is 16-byte
4599 aligned. Space for GPRs is reserved even if the argument
4600 will be passed in memory. */
4602 align = (2 - cum->words) & 3;
4604 align = cum->words & 1;
4605 cum->words += align + rs6000_arg_size (mode, type);
4607 if (TARGET_DEBUG_ARG)
4609 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4611 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4612 cum->nargs_prototype, cum->prototype,
4613 GET_MODE_NAME (mode));
4617 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4619 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4622 else if (rs6000_darwin64_abi
4624 && TREE_CODE (type) == RECORD_TYPE
4625 && (size = int_size_in_bytes (type)) > 0)
4627 /* Variable sized types have size == -1 and are
4628 treated as if consisting entirely of ints.
4629 Pad to 16 byte boundary if needed. */
4630 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4631 && (cum->words % 2) != 0)
4633 /* For varargs, we can just go up by the size of the struct. */
4635 cum->words += (size + 7) / 8;
4638 /* It is tempting to say int register count just goes up by
4639 sizeof(type)/8, but this is wrong in a case such as
4640 { int; double; int; } [powerpc alignment]. We have to
4641 grovel through the fields for these too. */
4643 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4644 rs6000_darwin64_record_arg_advance_flush (cum,
4645 size * BITS_PER_UNIT);
4648 else if (DEFAULT_ABI == ABI_V4)
4650 if (TARGET_HARD_FLOAT && TARGET_FPRS
4651 && (mode == SFmode || mode == DFmode
4652 || (mode == TFmode && !TARGET_IEEEQUAD)))
4654 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4655 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4658 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4659 if (mode == DFmode || mode == TFmode)
4660 cum->words += cum->words & 1;
4661 cum->words += rs6000_arg_size (mode, type);
4666 int n_words = rs6000_arg_size (mode, type);
4667 int gregno = cum->sysv_gregno;
4669 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4670 (r7,r8) or (r9,r10). As does any other 2 word item such
4671 as complex int due to a historical mistake. */
4673 gregno += (1 - gregno) & 1;
4675 /* Multi-reg args are not split between registers and stack. */
4676 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4678 /* Long long and SPE vectors are aligned on the stack.
4679 So are other 2 word items such as complex int due to
4680 a historical mistake. */
4682 cum->words += cum->words & 1;
4683 cum->words += n_words;
4686 /* Note: continuing to accumulate gregno past when we've started
4687 spilling to the stack indicates the fact that we've started
4688 spilling to the stack to expand_builtin_saveregs. */
4689 cum->sysv_gregno = gregno + n_words;
4692 if (TARGET_DEBUG_ARG)
4694 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4695 cum->words, cum->fregno);
4696 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4697 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4698 fprintf (stderr, "mode = %4s, named = %d\n",
4699 GET_MODE_NAME (mode), named);
4704 int n_words = rs6000_arg_size (mode, type);
4705 int start_words = cum->words;
4706 int align_words = rs6000_parm_start (mode, type, start_words);
4708 cum->words = align_words + n_words;
4710 if (SCALAR_FLOAT_MODE_P (mode)
4711 && !DECIMAL_FLOAT_MODE_P (mode)
4712 && TARGET_HARD_FLOAT && TARGET_FPRS)
4713 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4715 if (TARGET_DEBUG_ARG)
4717 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4718 cum->words, cum->fregno);
4719 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4720 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4721 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4722 named, align_words - start_words, depth);
4728 spe_build_register_parallel (enum machine_mode mode, int gregno)
4735 r1 = gen_rtx_REG (DImode, gregno);
4736 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4737 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4740 r1 = gen_rtx_REG (DImode, gregno);
4741 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4742 r3 = gen_rtx_REG (DImode, gregno + 2);
4743 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4744 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4751 /* Determine where to put a SIMD argument on the SPE. */
4753 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4756 int gregno = cum->sysv_gregno;
4758 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4759 are passed and returned in a pair of GPRs for ABI compatibility. */
4760 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4762 int n_words = rs6000_arg_size (mode, type);
4764 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4766 gregno += (1 - gregno) & 1;
4768 /* Multi-reg args are not split between registers and stack. */
4769 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4772 return spe_build_register_parallel (mode, gregno);
4776 int n_words = rs6000_arg_size (mode, type);
4778 /* SPE vectors are put in odd registers. */
4779 if (n_words == 2 && (gregno & 1) == 0)
4782 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4785 enum machine_mode m = SImode;
4787 r1 = gen_rtx_REG (m, gregno);
4788 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4789 r2 = gen_rtx_REG (m, gregno + 1);
4790 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4791 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4798 if (gregno <= GP_ARG_MAX_REG)
4799 return gen_rtx_REG (mode, gregno);
4805 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4806 structure between cum->intoffset and bitpos to integer registers. */
4809 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4810 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4812 enum machine_mode mode;
4814 unsigned int startbit, endbit;
4815 int this_regno, intregs, intoffset;
4818 if (cum->intoffset == -1)
4821 intoffset = cum->intoffset;
4822 cum->intoffset = -1;
4824 /* If this is the trailing part of a word, try to only load that
4825 much into the register. Otherwise load the whole register. Note
4826 that in the latter case we may pick up unwanted bits. It's not a
4827 problem at the moment but may wish to revisit. */
4829 if (intoffset % BITS_PER_WORD != 0)
4831 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4833 if (mode == BLKmode)
4835 /* We couldn't find an appropriate mode, which happens,
4836 e.g., in packed structs when there are 3 bytes to load.
4837 Back intoffset back to the beginning of the word in this
4839 intoffset = intoffset & -BITS_PER_WORD;
4846 startbit = intoffset & -BITS_PER_WORD;
4847 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4848 intregs = (endbit - startbit) / BITS_PER_WORD;
4849 this_regno = cum->words + intoffset / BITS_PER_WORD;
4851 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4854 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4858 intoffset /= BITS_PER_UNIT;
4861 regno = GP_ARG_MIN_REG + this_regno;
4862 reg = gen_rtx_REG (mode, regno);
4864 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4867 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4871 while (intregs > 0);
4874 /* Recursive workhorse for the following. */
4877 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4878 HOST_WIDE_INT startbitpos, rtx rvec[],
4883 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4884 if (TREE_CODE (f) == FIELD_DECL)
4886 HOST_WIDE_INT bitpos = startbitpos;
4887 tree ftype = TREE_TYPE (f);
4888 enum machine_mode mode = TYPE_MODE (ftype);
4890 if (DECL_SIZE (f) != 0
4891 && host_integerp (bit_position (f), 1))
4892 bitpos += int_bit_position (f);
4894 /* ??? FIXME: else assume zero offset. */
4896 if (TREE_CODE (ftype) == RECORD_TYPE)
4897 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4898 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4903 case SCmode: mode = SFmode; break;
4904 case DCmode: mode = DFmode; break;
4905 case TCmode: mode = TFmode; break;
4909 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4911 = gen_rtx_EXPR_LIST (VOIDmode,
4912 gen_rtx_REG (mode, cum->fregno++),
4913 GEN_INT (bitpos / BITS_PER_UNIT));
4917 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4919 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4921 = gen_rtx_EXPR_LIST (VOIDmode,
4922 gen_rtx_REG (mode, cum->vregno++),
4923 GEN_INT (bitpos / BITS_PER_UNIT));
4925 else if (cum->intoffset == -1)
4926 cum->intoffset = bitpos;
4930 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4931 the register(s) to be used for each field and subfield of a struct
4932 being passed by value, along with the offset of where the
4933 register's value may be found in the block. FP fields go in FP
4934 register, vector fields go in vector registers, and everything
4935 else goes in int registers, packed as in memory.
4937 This code is also used for function return values. RETVAL indicates
4938 whether this is the case.
4940 Much of this is taken from the SPARC V9 port, which has a similar
4941 calling convention. */
4944 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4945 int named, bool retval)
4947 rtx rvec[FIRST_PSEUDO_REGISTER];
4948 int k = 1, kbase = 1;
4949 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4950 /* This is a copy; modifications are not visible to our caller. */
4951 CUMULATIVE_ARGS copy_cum = *orig_cum;
4952 CUMULATIVE_ARGS *cum = ©_cum;
4954 /* Pad to 16 byte boundary if needed. */
4955 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4956 && (cum->words % 2) != 0)
4963 /* Put entries into rvec[] for individual FP and vector fields, and
4964 for the chunks of memory that go in int regs. Note we start at
4965 element 1; 0 is reserved for an indication of using memory, and
4966 may or may not be filled in below. */
4967 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4968 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4970 /* If any part of the struct went on the stack put all of it there.
4971 This hack is because the generic code for
4972 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4973 parts of the struct are not at the beginning. */
4977 return NULL_RTX; /* doesn't go in registers at all */
4979 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4981 if (k > 1 || cum->use_stack)
4982 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4987 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4990 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4994 rtx rvec[GP_ARG_NUM_REG + 1];
4996 if (align_words >= GP_ARG_NUM_REG)
4999 n_units = rs6000_arg_size (mode, type);
5001 /* Optimize the simple case where the arg fits in one gpr, except in
5002 the case of BLKmode due to assign_parms assuming that registers are
5003 BITS_PER_WORD wide. */
5005 || (n_units == 1 && mode != BLKmode))
5006 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5009 if (align_words + n_units > GP_ARG_NUM_REG)
5010 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5011 using a magic NULL_RTX component.
5012 FIXME: This is not strictly correct. Only some of the arg
5013 belongs in memory, not all of it. However, there isn't any way
5014 to do this currently, apart from building rtx descriptions for
5015 the pieces of memory we want stored. Due to bugs in the generic
5016 code we can't use the normal function_arg_partial_nregs scheme
5017 with the PARALLEL arg description we emit here.
5018 In any case, the code to store the whole arg to memory is often
5019 more efficient than code to store pieces, and we know that space
5020 is available in the right place for the whole arg. */
5021 /* FIXME: This should be fixed since the conversion to
5022 TARGET_ARG_PARTIAL_BYTES. */
5023 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5028 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5029 rtx off = GEN_INT (i++ * 4);
5030 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5032 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5034 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5037 /* Determine where to put an argument to a function.
5038 Value is zero to push the argument on the stack,
5039 or a hard register in which to store the argument.
5041 MODE is the argument's machine mode.
5042 TYPE is the data type of the argument (as a tree).
5043 This is null for libcalls where that information may
5045 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5046 the preceding args and about the function being called. It is
5047 not modified in this routine.
5048 NAMED is nonzero if this argument is a named parameter
5049 (otherwise it is an extra parameter matching an ellipsis).
5051 On RS/6000 the first eight words of non-FP are normally in registers
5052 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5053 Under V.4, the first 8 FP args are in registers.
5055 If this is floating-point and no prototype is specified, we use
5056 both an FP and integer register (or possibly FP reg and stack). Library
5057 functions (when CALL_LIBCALL is set) always have the proper types for args,
5058 so we can pass the FP value just in one register. emit_library_function
5059 doesn't support PARALLEL anyway.
5061 Note that for args passed by reference, function_arg will be called
5062 with MODE and TYPE set to that of the pointer to the arg, not the arg
5066 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5067 tree type, int named)
5069 enum rs6000_abi abi = DEFAULT_ABI;
5071 /* Return a marker to indicate whether CR1 needs to set or clear the
5072 bit that V.4 uses to say fp args were passed in registers.
5073 Assume that we don't need the marker for software floating point,
5074 or compiler generated library calls. */
5075 if (mode == VOIDmode)
5078 && (cum->call_cookie & CALL_LIBCALL) == 0
5080 || (cum->nargs_prototype < 0
5081 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5083 /* For the SPE, we need to crxor CR6 always. */
5085 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5086 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5087 return GEN_INT (cum->call_cookie
5088 | ((cum->fregno == FP_ARG_MIN_REG)
5089 ? CALL_V4_SET_FP_ARGS
5090 : CALL_V4_CLEAR_FP_ARGS));
5093 return GEN_INT (cum->call_cookie);
5096 if (rs6000_darwin64_abi && mode == BLKmode
5097 && TREE_CODE (type) == RECORD_TYPE)
5099 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5100 if (rslt != NULL_RTX)
5102 /* Else fall through to usual handling. */
5105 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5106 if (TARGET_64BIT && ! cum->prototype)
5108 /* Vector parameters get passed in vector register
5109 and also in GPRs or memory, in absence of prototype. */
5112 align_words = (cum->words + 1) & ~1;
5114 if (align_words >= GP_ARG_NUM_REG)
5120 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5122 return gen_rtx_PARALLEL (mode,
5124 gen_rtx_EXPR_LIST (VOIDmode,
5126 gen_rtx_EXPR_LIST (VOIDmode,
5127 gen_rtx_REG (mode, cum->vregno),
5131 return gen_rtx_REG (mode, cum->vregno);
5132 else if (TARGET_ALTIVEC_ABI
5133 && (ALTIVEC_VECTOR_MODE (mode)
5134 || (type && TREE_CODE (type) == VECTOR_TYPE
5135 && int_size_in_bytes (type) == 16)))
5137 if (named || abi == ABI_V4)
5141 /* Vector parameters to varargs functions under AIX or Darwin
5142 get passed in memory and possibly also in GPRs. */
5143 int align, align_words, n_words;
5144 enum machine_mode part_mode;
5146 /* Vector parameters must be 16-byte aligned. This places them at
5147 2 mod 4 in terms of words in 32-bit mode, since the parameter
5148 save area starts at offset 24 from the stack. In 64-bit mode,
5149 they just have to start on an even word, since the parameter
5150 save area is 16-byte aligned. */
5152 align = (2 - cum->words) & 3;
5154 align = cum->words & 1;
5155 align_words = cum->words + align;
5157 /* Out of registers? Memory, then. */
5158 if (align_words >= GP_ARG_NUM_REG)
5161 if (TARGET_32BIT && TARGET_POWERPC64)
5162 return rs6000_mixed_function_arg (mode, type, align_words);
5164 /* The vector value goes in GPRs. Only the part of the
5165 value in GPRs is reported here. */
5167 n_words = rs6000_arg_size (mode, type);
5168 if (align_words + n_words > GP_ARG_NUM_REG)
5169 /* Fortunately, there are only two possibilities, the value
5170 is either wholly in GPRs or half in GPRs and half not. */
5173 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5176 else if (TARGET_SPE_ABI && TARGET_SPE
5177 && (SPE_VECTOR_MODE (mode)
5178 || (TARGET_E500_DOUBLE && (mode == DFmode
5179 || mode == DCmode))))
5180 return rs6000_spe_function_arg (cum, mode, type);
5182 else if (abi == ABI_V4)
5184 if (TARGET_HARD_FLOAT && TARGET_FPRS
5185 && (mode == SFmode || mode == DFmode
5186 || (mode == TFmode && !TARGET_IEEEQUAD)))
5188 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5189 return gen_rtx_REG (mode, cum->fregno);
5195 int n_words = rs6000_arg_size (mode, type);
5196 int gregno = cum->sysv_gregno;
5198 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5199 (r7,r8) or (r9,r10). As does any other 2 word item such
5200 as complex int due to a historical mistake. */
5202 gregno += (1 - gregno) & 1;
5204 /* Multi-reg args are not split between registers and stack. */
5205 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5208 if (TARGET_32BIT && TARGET_POWERPC64)
5209 return rs6000_mixed_function_arg (mode, type,
5210 gregno - GP_ARG_MIN_REG);
5211 return gen_rtx_REG (mode, gregno);
5216 int align_words = rs6000_parm_start (mode, type, cum->words);
5218 if (USE_FP_FOR_ARG_P (cum, mode, type))
5220 rtx rvec[GP_ARG_NUM_REG + 1];
5224 enum machine_mode fmode = mode;
5225 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5227 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5229 /* Currently, we only ever need one reg here because complex
5230 doubles are split. */
5231 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5233 /* Long double split over regs and memory. */
5237 /* Do we also need to pass this arg in the parameter save
5240 && (cum->nargs_prototype <= 0
5241 || (DEFAULT_ABI == ABI_AIX
5243 && align_words >= GP_ARG_NUM_REG)));
5245 if (!needs_psave && mode == fmode)
5246 return gen_rtx_REG (fmode, cum->fregno);
5251 /* Describe the part that goes in gprs or the stack.
5252 This piece must come first, before the fprs. */
5253 if (align_words < GP_ARG_NUM_REG)
5255 unsigned long n_words = rs6000_arg_size (mode, type);
5257 if (align_words + n_words > GP_ARG_NUM_REG
5258 || (TARGET_32BIT && TARGET_POWERPC64))
5260 /* If this is partially on the stack, then we only
5261 include the portion actually in registers here. */
5262 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5265 if (align_words + n_words > GP_ARG_NUM_REG
5266 && (TARGET_32BIT && TARGET_POWERPC64))
5267 /* Not all of the arg fits in gprs. Say that it
5268 goes in memory too, using a magic NULL_RTX
5269 component. Also see comment in
5270 rs6000_mixed_function_arg for why the normal
5271 function_arg_partial_nregs scheme doesn't work
5273 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5277 r = gen_rtx_REG (rmode,
5278 GP_ARG_MIN_REG + align_words);
5279 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5280 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5282 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5286 /* The whole arg fits in gprs. */
5287 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5288 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5292 /* It's entirely in memory. */
5293 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5296 /* Describe where this piece goes in the fprs. */
5297 r = gen_rtx_REG (fmode, cum->fregno);
5298 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5300 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5302 else if (align_words < GP_ARG_NUM_REG)
5304 if (TARGET_32BIT && TARGET_POWERPC64)
5305 return rs6000_mixed_function_arg (mode, type, align_words);
5307 if (mode == BLKmode)
5310 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5317 /* For an arg passed partly in registers and partly in memory, this is
5318 the number of bytes passed in registers. For args passed entirely in
5319 registers or entirely in memory, zero. When an arg is described by a
5320 PARALLEL, perhaps using more than one register type, this function
5321 returns the number of bytes used by the first element of the PARALLEL. */
5324 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5325 tree type, bool named)
5330 if (DEFAULT_ABI == ABI_V4)
5333 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5334 && cum->nargs_prototype >= 0)
5337 /* In this complicated case we just disable the partial_nregs code. */
5338 if (rs6000_darwin64_abi && mode == BLKmode
5339 && TREE_CODE (type) == RECORD_TYPE
5340 && int_size_in_bytes (type) > 0)
5343 align_words = rs6000_parm_start (mode, type, cum->words);
5345 if (USE_FP_FOR_ARG_P (cum, mode, type)
5346 /* If we are passing this arg in the fixed parameter save area
5347 (gprs or memory) as well as fprs, then this function should
5348 return the number of bytes passed in the parameter save area
5349 rather than bytes passed in fprs. */
5351 && (cum->nargs_prototype <= 0
5352 || (DEFAULT_ABI == ABI_AIX
5354 && align_words >= GP_ARG_NUM_REG))))
5356 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5357 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5358 else if (cum->nargs_prototype >= 0)
5362 if (align_words < GP_ARG_NUM_REG
5363 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5364 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5366 if (ret != 0 && TARGET_DEBUG_ARG)
5367 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5372 /* A C expression that indicates when an argument must be passed by
5373 reference. If nonzero for an argument, a copy of that argument is
5374 made in memory and a pointer to the argument is passed instead of
5375 the argument itself. The pointer is passed in whatever way is
5376 appropriate for passing a pointer to that type.
5378 Under V.4, aggregates and long double are passed by reference.
5380 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5381 reference unless the AltiVec vector extension ABI is in force.
5383 As an extension to all ABIs, variable sized types are passed by
5387 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5388 enum machine_mode mode, tree type,
5389 bool named ATTRIBUTE_UNUSED)
5391 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5393 if (TARGET_DEBUG_ARG)
5394 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5401 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5403 if (TARGET_DEBUG_ARG)
5404 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5408 if (int_size_in_bytes (type) < 0)
5410 if (TARGET_DEBUG_ARG)
5411 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5415 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5416 modes only exist for GCC vector types if -maltivec. */
5417 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5419 if (TARGET_DEBUG_ARG)
5420 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5424 /* Pass synthetic vectors in memory. */
5425 if (TREE_CODE (type) == VECTOR_TYPE
5426 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5428 static bool warned_for_pass_big_vectors = false;
5429 if (TARGET_DEBUG_ARG)
5430 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5431 if (!warned_for_pass_big_vectors)
5433 warning (0, "GCC vector passed by reference: "
5434 "non-standard ABI extension with no compatibility guarantee");
5435 warned_for_pass_big_vectors = true;
5444 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5447 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5452 for (i = 0; i < nregs; i++)
5454 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5455 if (reload_completed)
5457 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5460 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5461 i * GET_MODE_SIZE (reg_mode));
5464 tem = replace_equiv_address (tem, XEXP (tem, 0));
5468 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5472 /* Perform any needed actions needed for a function that is receiving a
5473 variable number of arguments.
5477 MODE and TYPE are the mode and type of the current parameter.
5479 PRETEND_SIZE is a variable that should be set to the amount of stack
5480 that must be pushed by the prolog to pretend that our caller pushed
5483 Normally, this macro will push all remaining incoming registers on the
5484 stack and set PRETEND_SIZE to the length of the registers pushed. */
5487 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5488 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5491 CUMULATIVE_ARGS next_cum;
5492 int reg_size = TARGET_32BIT ? 4 : 8;
5493 rtx save_area = NULL_RTX, mem;
5494 int first_reg_offset, set;
5496 /* Skip the last named argument. */
5498 function_arg_advance (&next_cum, mode, type, 1, 0);
5500 if (DEFAULT_ABI == ABI_V4)
5502 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5506 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5507 HOST_WIDE_INT offset = 0;
5509 /* Try to optimize the size of the varargs save area.
5510 The ABI requires that ap.reg_save_area is doubleword
5511 aligned, but we don't need to allocate space for all
5512 the bytes, only those to which we actually will save
5514 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5515 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5516 if (TARGET_HARD_FLOAT && TARGET_FPRS
5517 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5518 && cfun->va_list_fpr_size)
5521 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5522 * UNITS_PER_FP_WORD;
5523 if (cfun->va_list_fpr_size
5524 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5525 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5527 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5528 * UNITS_PER_FP_WORD;
5532 offset = -((first_reg_offset * reg_size) & ~7);
5533 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5535 gpr_reg_num = cfun->va_list_gpr_size;
5536 if (reg_size == 4 && (first_reg_offset & 1))
5539 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5542 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5544 - (int) (GP_ARG_NUM_REG * reg_size);
5546 if (gpr_size + fpr_size)
5549 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5550 gcc_assert (GET_CODE (reg_save_area) == MEM);
5551 reg_save_area = XEXP (reg_save_area, 0);
5552 if (GET_CODE (reg_save_area) == PLUS)
5554 gcc_assert (XEXP (reg_save_area, 0)
5555 == virtual_stack_vars_rtx);
5556 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5557 offset += INTVAL (XEXP (reg_save_area, 1));
5560 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5563 cfun->machine->varargs_save_offset = offset;
5564 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5569 first_reg_offset = next_cum.words;
5570 save_area = virtual_incoming_args_rtx;
5572 if (targetm.calls.must_pass_in_stack (mode, type))
5573 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5576 set = get_varargs_alias_set ();
5577 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5578 && cfun->va_list_gpr_size)
5580 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5582 if (va_list_gpr_counter_field)
5584 /* V4 va_list_gpr_size counts number of registers needed. */
5585 if (nregs > cfun->va_list_gpr_size)
5586 nregs = cfun->va_list_gpr_size;
5590 /* char * va_list instead counts number of bytes needed. */
5591 if (nregs > cfun->va_list_gpr_size / reg_size)
5592 nregs = cfun->va_list_gpr_size / reg_size;
5595 mem = gen_rtx_MEM (BLKmode,
5596 plus_constant (save_area,
5597 first_reg_offset * reg_size));
5598 MEM_NOTRAP_P (mem) = 1;
5599 set_mem_alias_set (mem, set);
5600 set_mem_align (mem, BITS_PER_WORD);
5602 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5606 /* Save FP registers if needed. */
5607 if (DEFAULT_ABI == ABI_V4
5608 && TARGET_HARD_FLOAT && TARGET_FPRS
5610 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5611 && cfun->va_list_fpr_size)
5613 int fregno = next_cum.fregno, nregs;
5614 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5615 rtx lab = gen_label_rtx ();
5616 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5617 * UNITS_PER_FP_WORD);
5620 (gen_rtx_SET (VOIDmode,
5622 gen_rtx_IF_THEN_ELSE (VOIDmode,
5623 gen_rtx_NE (VOIDmode, cr1,
5625 gen_rtx_LABEL_REF (VOIDmode, lab),
5629 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5630 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5632 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5633 MEM_NOTRAP_P (mem) = 1;
5634 set_mem_alias_set (mem, set);
5635 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5636 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5643 /* Create the va_list data type. */
5646 rs6000_build_builtin_va_list (void)
5648 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5650 /* For AIX, prefer 'char *' because that's what the system
5651 header files like. */
5652 if (DEFAULT_ABI != ABI_V4)
5653 return build_pointer_type (char_type_node);
5655 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5656 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5658 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5659 unsigned_char_type_node);
5660 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5661 unsigned_char_type_node);
5662 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5664 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5665 short_unsigned_type_node);
5666 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5668 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5671 va_list_gpr_counter_field = f_gpr;
5672 va_list_fpr_counter_field = f_fpr;
5674 DECL_FIELD_CONTEXT (f_gpr) = record;
5675 DECL_FIELD_CONTEXT (f_fpr) = record;
5676 DECL_FIELD_CONTEXT (f_res) = record;
5677 DECL_FIELD_CONTEXT (f_ovf) = record;
5678 DECL_FIELD_CONTEXT (f_sav) = record;
5680 TREE_CHAIN (record) = type_decl;
5681 TYPE_NAME (record) = type_decl;
5682 TYPE_FIELDS (record) = f_gpr;
5683 TREE_CHAIN (f_gpr) = f_fpr;
5684 TREE_CHAIN (f_fpr) = f_res;
5685 TREE_CHAIN (f_res) = f_ovf;
5686 TREE_CHAIN (f_ovf) = f_sav;
5688 layout_type (record);
5690 /* The correct type is an array type of one element. */
5691 return build_array_type (record, build_index_type (size_zero_node));
5694 /* Implement va_start. */
5697 rs6000_va_start (tree valist, rtx nextarg)
5699 HOST_WIDE_INT words, n_gpr, n_fpr;
5700 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5701 tree gpr, fpr, ovf, sav, t;
5703 /* Only SVR4 needs something special. */
5704 if (DEFAULT_ABI != ABI_V4)
5706 std_expand_builtin_va_start (valist, nextarg);
5710 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5711 f_fpr = TREE_CHAIN (f_gpr);
5712 f_res = TREE_CHAIN (f_fpr);
5713 f_ovf = TREE_CHAIN (f_res);
5714 f_sav = TREE_CHAIN (f_ovf);
5716 valist = build_va_arg_indirect_ref (valist);
5717 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5718 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5719 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5720 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5722 /* Count number of gp and fp argument registers used. */
5723 words = current_function_args_info.words;
5724 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5726 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5729 if (TARGET_DEBUG_ARG)
5730 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5731 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5732 words, n_gpr, n_fpr);
5734 if (cfun->va_list_gpr_size)
5736 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5737 build_int_cst (NULL_TREE, n_gpr));
5738 TREE_SIDE_EFFECTS (t) = 1;
5739 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5742 if (cfun->va_list_fpr_size)
5744 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5745 build_int_cst (NULL_TREE, n_fpr));
5746 TREE_SIDE_EFFECTS (t) = 1;
5747 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5750 /* Find the overflow area. */
5751 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5753 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5754 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5755 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5756 TREE_SIDE_EFFECTS (t) = 1;
5757 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5759 /* If there were no va_arg invocations, don't set up the register
5761 if (!cfun->va_list_gpr_size
5762 && !cfun->va_list_fpr_size
5763 && n_gpr < GP_ARG_NUM_REG
5764 && n_fpr < FP_ARG_V4_MAX_REG)
5767 /* Find the register save area. */
5768 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5769 if (cfun->machine->varargs_save_offset)
5770 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5771 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5772 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5773 TREE_SIDE_EFFECTS (t) = 1;
5774 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5777 /* Implement va_arg. */
5780 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5782 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5783 tree gpr, fpr, ovf, sav, reg, t, u;
5784 int size, rsize, n_reg, sav_ofs, sav_scale;
5785 tree lab_false, lab_over, addr;
5787 tree ptrtype = build_pointer_type (type);
5789 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5791 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5792 return build_va_arg_indirect_ref (t);
5795 if (DEFAULT_ABI != ABI_V4)
5797 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5799 tree elem_type = TREE_TYPE (type);
5800 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5801 int elem_size = GET_MODE_SIZE (elem_mode);
5803 if (elem_size < UNITS_PER_WORD)
5805 tree real_part, imag_part;
5806 tree post = NULL_TREE;
5808 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5810 /* Copy the value into a temporary, lest the formal temporary
5811 be reused out from under us. */
5812 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5813 append_to_statement_list (post, pre_p);
5815 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5818 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5822 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5825 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5826 f_fpr = TREE_CHAIN (f_gpr);
5827 f_res = TREE_CHAIN (f_fpr);
5828 f_ovf = TREE_CHAIN (f_res);
5829 f_sav = TREE_CHAIN (f_ovf);
5831 valist = build_va_arg_indirect_ref (valist);
5832 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5833 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5834 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5835 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5837 size = int_size_in_bytes (type);
5838 rsize = (size + 3) / 4;
5841 if (TARGET_HARD_FLOAT && TARGET_FPRS
5842 && (TYPE_MODE (type) == SFmode
5843 || TYPE_MODE (type) == DFmode
5844 || TYPE_MODE (type) == TFmode))
5846 /* FP args go in FP registers, if present. */
5848 n_reg = (size + 7) / 8;
5851 if (TYPE_MODE (type) != SFmode)
5856 /* Otherwise into GP registers. */
5865 /* Pull the value out of the saved registers.... */
5868 addr = create_tmp_var (ptr_type_node, "addr");
5869 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5871 /* AltiVec vectors never go in registers when -mabi=altivec. */
5872 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5876 lab_false = create_artificial_label ();
5877 lab_over = create_artificial_label ();
5879 /* Long long and SPE vectors are aligned in the registers.
5880 As are any other 2 gpr item such as complex int due to a
5881 historical mistake. */
5883 if (n_reg == 2 && reg == gpr)
5885 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5886 size_int (n_reg - 1));
5887 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5890 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5891 t = build2 (GE_EXPR, boolean_type_node, u, t);
5892 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5893 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5894 gimplify_and_add (t, pre_p);
5898 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5900 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5901 u = build1 (CONVERT_EXPR, integer_type_node, u);
5902 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5903 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5905 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5906 gimplify_and_add (t, pre_p);
5908 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5909 gimplify_and_add (t, pre_p);
5911 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5912 append_to_statement_list (t, pre_p);
5916 /* Ensure that we don't find any more args in regs.
5917 Alignment has taken care of the n_reg == 2 case. */
5918 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5919 gimplify_and_add (t, pre_p);
5923 /* ... otherwise out of the overflow area. */
5925 /* Care for on-stack alignment if needed. */
5929 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5930 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5931 build_int_cst (NULL_TREE, -align));
5933 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5935 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5936 gimplify_and_add (u, pre_p);
5938 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5939 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5940 gimplify_and_add (t, pre_p);
5944 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5945 append_to_statement_list (t, pre_p);
5948 addr = fold_convert (ptrtype, addr);
5949 return build_va_arg_indirect_ref (addr);
5955 def_builtin (int mask, const char *name, tree type, int code)
5957 if (mask & target_flags)
5959 if (rs6000_builtin_decls[code])
5962 rs6000_builtin_decls[code] =
5963 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5968 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5970 static const struct builtin_description bdesc_3arg[] =
5972 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5973 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5974 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5975 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5976 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5977 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5978 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5979 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5980 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5981 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5982 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5983 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5984 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5985 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5986 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5987 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5988 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5989 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5990 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5991 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5992 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5993 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5994 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5996 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5997 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5998 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5999 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6000 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6001 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6002 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6003 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6004 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6005 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6006 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6007 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6008 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6009 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6010 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6013 /* DST operations: void foo (void *, const int, const char). */
6015 static const struct builtin_description bdesc_dst[] =
6017 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6019 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6020 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6022 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6023 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6024 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6025 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6028 /* Simple binary operations: VECc = foo (VECa, VECb). */
6030 static struct builtin_description bdesc_2arg[] =
6032 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6033 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6034 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6035 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6036 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6037 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6038 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6039 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6040 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6041 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6042 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6043 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6044 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6045 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6046 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6047 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6048 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6049 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6050 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6053 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6054 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6055 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6056 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6057 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6058 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6059 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6060 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6061 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6062 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6063 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6064 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6065 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6066 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6067 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6068 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6069 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6070 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6071 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6072 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6073 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6074 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6075 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6076 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6077 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6078 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6079 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6080 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6081 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6082 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6083 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6084 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6085 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6086 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6087 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6088 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6094 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6096 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6097 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6099 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6100 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6101 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6102 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6103 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6104 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6105 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6106 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6107 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6108 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6109 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6110 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6111 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6112 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6113 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6114 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6115 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6116 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6117 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6118 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6119 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6120 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6121 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6122 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6123 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6124 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6125 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6126 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6127 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6128 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6129 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6130 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6131 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6132 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6133 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6134 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6136 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6140 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6142 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6146 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6149 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6272 /* Place holder, leave as first spe builtin. */
6273 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6274 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6275 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6276 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6277 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6278 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6279 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6280 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6281 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6282 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6283 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6284 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6285 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6286 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6287 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6288 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6289 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6290 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6291 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6292 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6293 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6294 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6295 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6296 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6297 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6298 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6299 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6300 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6301 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6302 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6303 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6304 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6305 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6306 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6307 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6308 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6309 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6310 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6311 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6312 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6313 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6314 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6315 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6316 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6317 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6318 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6319 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6320 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6321 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6322 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6323 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6324 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6325 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6326 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6327 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6328 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6329 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6330 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6331 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6332 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6333 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6334 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6335 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6336 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6337 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6338 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6339 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6340 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6341 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6342 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6343 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6344 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6345 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6346 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6347 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6348 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6349 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6350 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6351 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6352 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6353 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6354 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6355 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6356 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6357 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6358 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6359 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6360 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6361 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6362 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6363 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6364 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6365 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6366 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6367 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6368 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6369 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6370 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6371 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6372 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6373 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6374 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6375 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6376 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6377 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6378 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6379 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6380 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6381 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6383 /* SPE binary operations expecting a 5-bit unsigned literal. */
6384 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6386 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6387 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6388 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6389 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6390 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6391 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6392 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6393 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6394 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6395 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6396 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6397 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6398 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6399 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6400 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6401 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6402 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6403 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6404 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6405 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6406 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6407 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6408 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6409 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6410 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6411 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6413 /* Place-holder. Leave as last binary SPE builtin. */
6414 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6417 /* AltiVec predicates. */
6419 struct builtin_description_predicates
6421 const unsigned int mask;
6422 const enum insn_code icode;
6424 const char *const name;
6425 const enum rs6000_builtins code;
6428 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6430 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6431 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6432 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6433 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6434 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6435 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6436 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6437 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6438 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6439 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6440 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6441 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6442 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6444 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6445 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6446 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6449 /* SPE predicates. */
6450 static struct builtin_description bdesc_spe_predicates[] =
6452 /* Place-holder. Leave as first. */
6453 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6454 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6455 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6456 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6457 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6458 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6459 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6460 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6461 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6462 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6463 /* Place-holder. Leave as last. */
6464 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6467 /* SPE evsel predicates. */
6468 static struct builtin_description bdesc_spe_evsel[] =
6470 /* Place-holder. Leave as first. */
6471 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6472 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6473 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6474 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6475 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6476 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6477 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6478 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6479 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6480 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6481 /* Place-holder. Leave as last. */
6482 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6485 /* ABS* operations. */
6487 static const struct builtin_description bdesc_abs[] =
6489 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6490 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6491 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6492 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6493 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6494 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6495 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6498 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6501 static struct builtin_description bdesc_1arg[] =
6503 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6504 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6505 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6506 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6507 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6508 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6509 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6510 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6511 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6512 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6513 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6514 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6515 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6516 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6521 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6522 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6523 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6524 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6525 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6526 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6527 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6528 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6529 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6530 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6531 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6532 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6533 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6534 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6535 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6536 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6537 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6538 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6539 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6541 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6542 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6543 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6544 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6545 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6546 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6547 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6548 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6549 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6550 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6551 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6552 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6553 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6554 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6555 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6556 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6557 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6558 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6559 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6560 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6561 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6562 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6563 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6564 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6565 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6566 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6567 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6568 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6569 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6570 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6572 /* Place-holder. Leave as last unary SPE builtin. */
6573 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6577 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6580 tree arg0 = TREE_VALUE (arglist);
6581 rtx op0 = expand_normal (arg0);
6582 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6583 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6585 if (icode == CODE_FOR_nothing)
6586 /* Builtin not supported on this processor. */
6589 /* If we got invalid arguments bail out before generating bad rtl. */
6590 if (arg0 == error_mark_node)
6593 if (icode == CODE_FOR_altivec_vspltisb
6594 || icode == CODE_FOR_altivec_vspltish
6595 || icode == CODE_FOR_altivec_vspltisw
6596 || icode == CODE_FOR_spe_evsplatfi
6597 || icode == CODE_FOR_spe_evsplati)
6599 /* Only allow 5-bit *signed* literals. */
6600 if (GET_CODE (op0) != CONST_INT
6601 || INTVAL (op0) > 15
6602 || INTVAL (op0) < -16)
6604 error ("argument 1 must be a 5-bit signed literal");
6610 || GET_MODE (target) != tmode
6611 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6612 target = gen_reg_rtx (tmode);
6614 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6615 op0 = copy_to_mode_reg (mode0, op0);
6617 pat = GEN_FCN (icode) (target, op0);
6626 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6628 rtx pat, scratch1, scratch2;
6629 tree arg0 = TREE_VALUE (arglist);
6630 rtx op0 = expand_normal (arg0);
6631 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6632 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6634 /* If we have invalid arguments, bail out before generating bad rtl. */
6635 if (arg0 == error_mark_node)
6639 || GET_MODE (target) != tmode
6640 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6641 target = gen_reg_rtx (tmode);
6643 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6644 op0 = copy_to_mode_reg (mode0, op0);
6646 scratch1 = gen_reg_rtx (mode0);
6647 scratch2 = gen_reg_rtx (mode0);
6649 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6658 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6661 tree arg0 = TREE_VALUE (arglist);
6662 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6663 rtx op0 = expand_normal (arg0);
6664 rtx op1 = expand_normal (arg1);
6665 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6666 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6667 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6669 if (icode == CODE_FOR_nothing)
6670 /* Builtin not supported on this processor. */
6673 /* If we got invalid arguments bail out before generating bad rtl. */
6674 if (arg0 == error_mark_node || arg1 == error_mark_node)
6677 if (icode == CODE_FOR_altivec_vcfux
6678 || icode == CODE_FOR_altivec_vcfsx
6679 || icode == CODE_FOR_altivec_vctsxs
6680 || icode == CODE_FOR_altivec_vctuxs
6681 || icode == CODE_FOR_altivec_vspltb
6682 || icode == CODE_FOR_altivec_vsplth
6683 || icode == CODE_FOR_altivec_vspltw
6684 || icode == CODE_FOR_spe_evaddiw
6685 || icode == CODE_FOR_spe_evldd
6686 || icode == CODE_FOR_spe_evldh
6687 || icode == CODE_FOR_spe_evldw
6688 || icode == CODE_FOR_spe_evlhhesplat
6689 || icode == CODE_FOR_spe_evlhhossplat
6690 || icode == CODE_FOR_spe_evlhhousplat
6691 || icode == CODE_FOR_spe_evlwhe
6692 || icode == CODE_FOR_spe_evlwhos
6693 || icode == CODE_FOR_spe_evlwhou
6694 || icode == CODE_FOR_spe_evlwhsplat
6695 || icode == CODE_FOR_spe_evlwwsplat
6696 || icode == CODE_FOR_spe_evrlwi
6697 || icode == CODE_FOR_spe_evslwi
6698 || icode == CODE_FOR_spe_evsrwis
6699 || icode == CODE_FOR_spe_evsubifw
6700 || icode == CODE_FOR_spe_evsrwiu)
6702 /* Only allow 5-bit unsigned literals. */
6704 if (TREE_CODE (arg1) != INTEGER_CST
6705 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6707 error ("argument 2 must be a 5-bit unsigned literal");
6713 || GET_MODE (target) != tmode
6714 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6715 target = gen_reg_rtx (tmode);
6717 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6718 op0 = copy_to_mode_reg (mode0, op0);
6719 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6720 op1 = copy_to_mode_reg (mode1, op1);
6722 pat = GEN_FCN (icode) (target, op0, op1);
6731 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6732 tree arglist, rtx target)
6735 tree cr6_form = TREE_VALUE (arglist);
6736 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6737 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6738 rtx op0 = expand_normal (arg0);
6739 rtx op1 = expand_normal (arg1);
6740 enum machine_mode tmode = SImode;
6741 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6742 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6745 if (TREE_CODE (cr6_form) != INTEGER_CST)
6747 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6751 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6753 gcc_assert (mode0 == mode1);
6755 /* If we have invalid arguments, bail out before generating bad rtl. */
6756 if (arg0 == error_mark_node || arg1 == error_mark_node)
6760 || GET_MODE (target) != tmode
6761 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6762 target = gen_reg_rtx (tmode);
6764 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6765 op0 = copy_to_mode_reg (mode0, op0);
6766 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6767 op1 = copy_to_mode_reg (mode1, op1);
6769 scratch = gen_reg_rtx (mode0);
6771 pat = GEN_FCN (icode) (scratch, op0, op1,
6772 gen_rtx_SYMBOL_REF (Pmode, opcode));
6777 /* The vec_any* and vec_all* predicates use the same opcodes for two
6778 different operations, but the bits in CR6 will be different
6779 depending on what information we want. So we have to play tricks
6780 with CR6 to get the right bits out.
6782 If you think this is disgusting, look at the specs for the
6783 AltiVec predicates. */
6785 switch (cr6_form_int)
6788 emit_insn (gen_cr6_test_for_zero (target));
6791 emit_insn (gen_cr6_test_for_zero_reverse (target));
6794 emit_insn (gen_cr6_test_for_lt (target));
6797 emit_insn (gen_cr6_test_for_lt_reverse (target));
6800 error ("argument 1 of __builtin_altivec_predicate is out of range");
6808 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6811 tree arg0 = TREE_VALUE (arglist);
6812 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6813 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6814 enum machine_mode mode0 = Pmode;
6815 enum machine_mode mode1 = Pmode;
6816 rtx op0 = expand_normal (arg0);
6817 rtx op1 = expand_normal (arg1);
6819 if (icode == CODE_FOR_nothing)
6820 /* Builtin not supported on this processor. */
6823 /* If we got invalid arguments bail out before generating bad rtl. */
6824 if (arg0 == error_mark_node || arg1 == error_mark_node)
6828 || GET_MODE (target) != tmode
6829 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6830 target = gen_reg_rtx (tmode);
6832 op1 = copy_to_mode_reg (mode1, op1);
6834 if (op0 == const0_rtx)
6836 addr = gen_rtx_MEM (tmode, op1);
6840 op0 = copy_to_mode_reg (mode0, op0);
6841 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6844 pat = GEN_FCN (icode) (target, addr);
6854 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6856 tree arg0 = TREE_VALUE (arglist);
6857 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6858 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6859 rtx op0 = expand_normal (arg0);
6860 rtx op1 = expand_normal (arg1);
6861 rtx op2 = expand_normal (arg2);
6863 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6864 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6865 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6867 /* Invalid arguments. Bail before doing anything stoopid! */
6868 if (arg0 == error_mark_node
6869 || arg1 == error_mark_node
6870 || arg2 == error_mark_node)
6873 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6874 op0 = copy_to_mode_reg (mode2, op0);
6875 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6876 op1 = copy_to_mode_reg (mode0, op1);
6877 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6878 op2 = copy_to_mode_reg (mode1, op2);
6880 pat = GEN_FCN (icode) (op1, op2, op0);
6887 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6889 tree arg0 = TREE_VALUE (arglist);
6890 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6891 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6892 rtx op0 = expand_normal (arg0);
6893 rtx op1 = expand_normal (arg1);
6894 rtx op2 = expand_normal (arg2);
6896 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6897 enum machine_mode mode1 = Pmode;
6898 enum machine_mode mode2 = Pmode;
6900 /* Invalid arguments. Bail before doing anything stoopid! */
6901 if (arg0 == error_mark_node
6902 || arg1 == error_mark_node
6903 || arg2 == error_mark_node)
6906 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6907 op0 = copy_to_mode_reg (tmode, op0);
6909 op2 = copy_to_mode_reg (mode2, op2);
6911 if (op1 == const0_rtx)
6913 addr = gen_rtx_MEM (tmode, op2);
6917 op1 = copy_to_mode_reg (mode1, op1);
6918 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6921 pat = GEN_FCN (icode) (addr, op0);
6928 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6931 tree arg0 = TREE_VALUE (arglist);
6932 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6933 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6934 rtx op0 = expand_normal (arg0);
6935 rtx op1 = expand_normal (arg1);
6936 rtx op2 = expand_normal (arg2);
6937 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6938 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6939 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6940 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6942 if (icode == CODE_FOR_nothing)
6943 /* Builtin not supported on this processor. */
6946 /* If we got invalid arguments bail out before generating bad rtl. */
6947 if (arg0 == error_mark_node
6948 || arg1 == error_mark_node
6949 || arg2 == error_mark_node)
6952 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6953 || icode == CODE_FOR_altivec_vsldoi_v4si
6954 || icode == CODE_FOR_altivec_vsldoi_v8hi
6955 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6957 /* Only allow 4-bit unsigned literals. */
6959 if (TREE_CODE (arg2) != INTEGER_CST
6960 || TREE_INT_CST_LOW (arg2) & ~0xf)
6962 error ("argument 3 must be a 4-bit unsigned literal");
6968 || GET_MODE (target) != tmode
6969 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6970 target = gen_reg_rtx (tmode);
6972 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6973 op0 = copy_to_mode_reg (mode0, op0);
6974 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6975 op1 = copy_to_mode_reg (mode1, op1);
6976 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6977 op2 = copy_to_mode_reg (mode2, op2);
6979 pat = GEN_FCN (icode) (target, op0, op1, op2);
6987 /* Expand the lvx builtins. */
6989 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6991 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6992 tree arglist = TREE_OPERAND (exp, 1);
6993 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6995 enum machine_mode tmode, mode0;
6997 enum insn_code icode;
7001 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7002 icode = CODE_FOR_altivec_lvx_v16qi;
7004 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7005 icode = CODE_FOR_altivec_lvx_v8hi;
7007 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7008 icode = CODE_FOR_altivec_lvx_v4si;
7010 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7011 icode = CODE_FOR_altivec_lvx_v4sf;
7020 arg0 = TREE_VALUE (arglist);
7021 op0 = expand_normal (arg0);
7022 tmode = insn_data[icode].operand[0].mode;
7023 mode0 = insn_data[icode].operand[1].mode;
7026 || GET_MODE (target) != tmode
7027 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7028 target = gen_reg_rtx (tmode);
7030 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7031 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7033 pat = GEN_FCN (icode) (target, op0);
7040 /* Expand the stvx builtins. */
7042 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7045 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7046 tree arglist = TREE_OPERAND (exp, 1);
7047 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7049 enum machine_mode mode0, mode1;
7051 enum insn_code icode;
7055 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7056 icode = CODE_FOR_altivec_stvx_v16qi;
7058 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7059 icode = CODE_FOR_altivec_stvx_v8hi;
7061 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7062 icode = CODE_FOR_altivec_stvx_v4si;
7064 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7065 icode = CODE_FOR_altivec_stvx_v4sf;
7072 arg0 = TREE_VALUE (arglist);
7073 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7074 op0 = expand_normal (arg0);
7075 op1 = expand_normal (arg1);
7076 mode0 = insn_data[icode].operand[0].mode;
7077 mode1 = insn_data[icode].operand[1].mode;
7079 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7080 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7081 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7082 op1 = copy_to_mode_reg (mode1, op1);
7084 pat = GEN_FCN (icode) (op0, op1);
7092 /* Expand the dst builtins. */
7094 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7097 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7098 tree arglist = TREE_OPERAND (exp, 1);
7099 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7100 tree arg0, arg1, arg2;
7101 enum machine_mode mode0, mode1, mode2;
7102 rtx pat, op0, op1, op2;
7103 struct builtin_description *d;
7108 /* Handle DST variants. */
7109 d = (struct builtin_description *) bdesc_dst;
7110 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7111 if (d->code == fcode)
7113 arg0 = TREE_VALUE (arglist);
7114 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7115 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7116 op0 = expand_normal (arg0);
7117 op1 = expand_normal (arg1);
7118 op2 = expand_normal (arg2);
7119 mode0 = insn_data[d->icode].operand[0].mode;
7120 mode1 = insn_data[d->icode].operand[1].mode;
7121 mode2 = insn_data[d->icode].operand[2].mode;
7123 /* Invalid arguments, bail out before generating bad rtl. */
7124 if (arg0 == error_mark_node
7125 || arg1 == error_mark_node
7126 || arg2 == error_mark_node)
7131 if (TREE_CODE (arg2) != INTEGER_CST
7132 || TREE_INT_CST_LOW (arg2) & ~0x3)
7134 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7138 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7139 op0 = copy_to_mode_reg (Pmode, op0);
7140 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7141 op1 = copy_to_mode_reg (mode1, op1);
7143 pat = GEN_FCN (d->icode) (op0, op1, op2);
7153 /* Expand vec_init builtin. */
7155 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7157 enum machine_mode tmode = TYPE_MODE (type);
7158 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7159 int i, n_elt = GET_MODE_NUNITS (tmode);
7160 rtvec v = rtvec_alloc (n_elt);
7162 gcc_assert (VECTOR_MODE_P (tmode));
7164 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7166 rtx x = expand_normal (TREE_VALUE (arglist));
7167 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7170 gcc_assert (arglist == NULL);
7172 if (!target || !register_operand (target, tmode))
7173 target = gen_reg_rtx (tmode);
7175 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7179 /* Return the integer constant in ARG. Constrain it to be in the range
7180 of the subparts of VEC_TYPE; issue an error if not. */
7183 get_element_number (tree vec_type, tree arg)
7185 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7187 if (!host_integerp (arg, 1)
7188 || (elt = tree_low_cst (arg, 1), elt > max))
7190 error ("selector must be an integer constant in the range 0..%wi", max);
7197 /* Expand vec_set builtin. */
7199 altivec_expand_vec_set_builtin (tree arglist)
7201 enum machine_mode tmode, mode1;
7202 tree arg0, arg1, arg2;
7206 arg0 = TREE_VALUE (arglist);
7207 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7208 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7210 tmode = TYPE_MODE (TREE_TYPE (arg0));
7211 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7212 gcc_assert (VECTOR_MODE_P (tmode));
7214 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7215 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7216 elt = get_element_number (TREE_TYPE (arg0), arg2);
7218 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7219 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7221 op0 = force_reg (tmode, op0);
7222 op1 = force_reg (mode1, op1);
7224 rs6000_expand_vector_set (op0, op1, elt);
7229 /* Expand vec_ext builtin. */
7231 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7233 enum machine_mode tmode, mode0;
7238 arg0 = TREE_VALUE (arglist);
7239 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7241 op0 = expand_normal (arg0);
7242 elt = get_element_number (TREE_TYPE (arg0), arg1);
7244 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7245 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7246 gcc_assert (VECTOR_MODE_P (mode0));
7248 op0 = force_reg (mode0, op0);
7250 if (optimize || !target || !register_operand (target, tmode))
7251 target = gen_reg_rtx (tmode);
7253 rs6000_expand_vector_extract (target, op0, elt);
7258 /* Expand the builtin in EXP and store the result in TARGET. Store
7259 true in *EXPANDEDP if we found a builtin to expand. */
7261 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7263 struct builtin_description *d;
7264 struct builtin_description_predicates *dp;
7266 enum insn_code icode;
7267 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7268 tree arglist = TREE_OPERAND (exp, 1);
7271 enum machine_mode tmode, mode0;
7272 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7274 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7275 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7278 error ("unresolved overload for Altivec builtin %qF", fndecl);
7282 target = altivec_expand_ld_builtin (exp, target, expandedp);
7286 target = altivec_expand_st_builtin (exp, target, expandedp);
7290 target = altivec_expand_dst_builtin (exp, target, expandedp);
7298 case ALTIVEC_BUILTIN_STVX:
7299 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7300 case ALTIVEC_BUILTIN_STVEBX:
7301 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7302 case ALTIVEC_BUILTIN_STVEHX:
7303 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7304 case ALTIVEC_BUILTIN_STVEWX:
7305 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7306 case ALTIVEC_BUILTIN_STVXL:
7307 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7309 case ALTIVEC_BUILTIN_MFVSCR:
7310 icode = CODE_FOR_altivec_mfvscr;
7311 tmode = insn_data[icode].operand[0].mode;
7314 || GET_MODE (target) != tmode
7315 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7316 target = gen_reg_rtx (tmode);
7318 pat = GEN_FCN (icode) (target);
7324 case ALTIVEC_BUILTIN_MTVSCR:
7325 icode = CODE_FOR_altivec_mtvscr;
7326 arg0 = TREE_VALUE (arglist);
7327 op0 = expand_normal (arg0);
7328 mode0 = insn_data[icode].operand[0].mode;
7330 /* If we got invalid arguments bail out before generating bad rtl. */
7331 if (arg0 == error_mark_node)
7334 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7335 op0 = copy_to_mode_reg (mode0, op0);
7337 pat = GEN_FCN (icode) (op0);
7342 case ALTIVEC_BUILTIN_DSSALL:
7343 emit_insn (gen_altivec_dssall ());
7346 case ALTIVEC_BUILTIN_DSS:
7347 icode = CODE_FOR_altivec_dss;
7348 arg0 = TREE_VALUE (arglist);
7350 op0 = expand_normal (arg0);
7351 mode0 = insn_data[icode].operand[0].mode;
7353 /* If we got invalid arguments bail out before generating bad rtl. */
7354 if (arg0 == error_mark_node)
7357 if (TREE_CODE (arg0) != INTEGER_CST
7358 || TREE_INT_CST_LOW (arg0) & ~0x3)
7360 error ("argument to dss must be a 2-bit unsigned literal");
7364 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7365 op0 = copy_to_mode_reg (mode0, op0);
7367 emit_insn (gen_altivec_dss (op0));
7370 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7371 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7372 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7373 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7374 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7376 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7377 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7378 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7379 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7380 return altivec_expand_vec_set_builtin (arglist);
7382 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7383 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7384 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7385 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7386 return altivec_expand_vec_ext_builtin (arglist, target);
7393 /* Expand abs* operations. */
7394 d = (struct builtin_description *) bdesc_abs;
7395 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7396 if (d->code == fcode)
7397 return altivec_expand_abs_builtin (d->icode, arglist, target);
7399 /* Expand the AltiVec predicates. */
7400 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7401 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7402 if (dp->code == fcode)
7403 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7406 /* LV* are funky. We initialized them differently. */
7409 case ALTIVEC_BUILTIN_LVSL:
7410 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7412 case ALTIVEC_BUILTIN_LVSR:
7413 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7415 case ALTIVEC_BUILTIN_LVEBX:
7416 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7418 case ALTIVEC_BUILTIN_LVEHX:
7419 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7421 case ALTIVEC_BUILTIN_LVEWX:
7422 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7424 case ALTIVEC_BUILTIN_LVXL:
7425 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7427 case ALTIVEC_BUILTIN_LVX:
7428 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7439 /* Binops that need to be initialized manually, but can be expanded
7440 automagically by rs6000_expand_binop_builtin. */
7441 static struct builtin_description bdesc_2arg_spe[] =
7443 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7444 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7445 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7446 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7447 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7448 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7449 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7450 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7451 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7452 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7453 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7454 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7455 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7456 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7457 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7458 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7459 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7460 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7461 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7462 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7463 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7464 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7467 /* Expand the builtin in EXP and store the result in TARGET. Store
7468 true in *EXPANDEDP if we found a builtin to expand.
7470 This expands the SPE builtins that are not simple unary and binary
7473 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7475 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7476 tree arglist = TREE_OPERAND (exp, 1);
7478 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7479 enum insn_code icode;
7480 enum machine_mode tmode, mode0;
7482 struct builtin_description *d;
7487 /* Syntax check for a 5-bit unsigned immediate. */
7490 case SPE_BUILTIN_EVSTDD:
7491 case SPE_BUILTIN_EVSTDH:
7492 case SPE_BUILTIN_EVSTDW:
7493 case SPE_BUILTIN_EVSTWHE:
7494 case SPE_BUILTIN_EVSTWHO:
7495 case SPE_BUILTIN_EVSTWWE:
7496 case SPE_BUILTIN_EVSTWWO:
7497 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7498 if (TREE_CODE (arg1) != INTEGER_CST
7499 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7501 error ("argument 2 must be a 5-bit unsigned literal");
7509 /* The evsplat*i instructions are not quite generic. */
7512 case SPE_BUILTIN_EVSPLATFI:
7513 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7515 case SPE_BUILTIN_EVSPLATI:
7516 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7522 d = (struct builtin_description *) bdesc_2arg_spe;
7523 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7524 if (d->code == fcode)
7525 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7527 d = (struct builtin_description *) bdesc_spe_predicates;
7528 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7529 if (d->code == fcode)
7530 return spe_expand_predicate_builtin (d->icode, arglist, target);
7532 d = (struct builtin_description *) bdesc_spe_evsel;
7533 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7534 if (d->code == fcode)
7535 return spe_expand_evsel_builtin (d->icode, arglist, target);
7539 case SPE_BUILTIN_EVSTDDX:
7540 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7541 case SPE_BUILTIN_EVSTDHX:
7542 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7543 case SPE_BUILTIN_EVSTDWX:
7544 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7545 case SPE_BUILTIN_EVSTWHEX:
7546 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7547 case SPE_BUILTIN_EVSTWHOX:
7548 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7549 case SPE_BUILTIN_EVSTWWEX:
7550 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7551 case SPE_BUILTIN_EVSTWWOX:
7552 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7553 case SPE_BUILTIN_EVSTDD:
7554 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7555 case SPE_BUILTIN_EVSTDH:
7556 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7557 case SPE_BUILTIN_EVSTDW:
7558 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7559 case SPE_BUILTIN_EVSTWHE:
7560 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7561 case SPE_BUILTIN_EVSTWHO:
7562 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7563 case SPE_BUILTIN_EVSTWWE:
7564 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7565 case SPE_BUILTIN_EVSTWWO:
7566 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7567 case SPE_BUILTIN_MFSPEFSCR:
7568 icode = CODE_FOR_spe_mfspefscr;
7569 tmode = insn_data[icode].operand[0].mode;
7572 || GET_MODE (target) != tmode
7573 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7574 target = gen_reg_rtx (tmode);
7576 pat = GEN_FCN (icode) (target);
7581 case SPE_BUILTIN_MTSPEFSCR:
7582 icode = CODE_FOR_spe_mtspefscr;
7583 arg0 = TREE_VALUE (arglist);
7584 op0 = expand_normal (arg0);
7585 mode0 = insn_data[icode].operand[0].mode;
7587 if (arg0 == error_mark_node)
7590 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7591 op0 = copy_to_mode_reg (mode0, op0);
7593 pat = GEN_FCN (icode) (op0);
7606 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7608 rtx pat, scratch, tmp;
7609 tree form = TREE_VALUE (arglist);
7610 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7611 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7612 rtx op0 = expand_normal (arg0);
7613 rtx op1 = expand_normal (arg1);
7614 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7615 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7619 if (TREE_CODE (form) != INTEGER_CST)
7621 error ("argument 1 of __builtin_spe_predicate must be a constant");
7625 form_int = TREE_INT_CST_LOW (form);
7627 gcc_assert (mode0 == mode1);
7629 if (arg0 == error_mark_node || arg1 == error_mark_node)
7633 || GET_MODE (target) != SImode
7634 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7635 target = gen_reg_rtx (SImode);
7637 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7638 op0 = copy_to_mode_reg (mode0, op0);
7639 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7640 op1 = copy_to_mode_reg (mode1, op1);
7642 scratch = gen_reg_rtx (CCmode);
7644 pat = GEN_FCN (icode) (scratch, op0, op1);
7649 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7650 _lower_. We use one compare, but look in different bits of the
7651 CR for each variant.
7653 There are 2 elements in each SPE simd type (upper/lower). The CR
7654 bits are set as follows:
7656 BIT0 | BIT 1 | BIT 2 | BIT 3
7657 U | L | (U | L) | (U & L)
7659 So, for an "all" relationship, BIT 3 would be set.
7660 For an "any" relationship, BIT 2 would be set. Etc.
7662 Following traditional nomenclature, these bits map to:
7664 BIT0 | BIT 1 | BIT 2 | BIT 3
7667 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7672 /* All variant. OV bit. */
7674 /* We need to get to the OV bit, which is the ORDERED bit. We
7675 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7676 that's ugly and will make validate_condition_mode die.
7677 So let's just use another pattern. */
7678 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7680 /* Any variant. EQ bit. */
7684 /* Upper variant. LT bit. */
7688 /* Lower variant. GT bit. */
7693 error ("argument 1 of __builtin_spe_predicate is out of range");
7697 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7698 emit_move_insn (target, tmp);
7703 /* The evsel builtins look like this:
7705 e = __builtin_spe_evsel_OP (a, b, c, d);
7709 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7710 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7714 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7717 tree arg0 = TREE_VALUE (arglist);
7718 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7719 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7720 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7721 rtx op0 = expand_normal (arg0);
7722 rtx op1 = expand_normal (arg1);
7723 rtx op2 = expand_normal (arg2);
7724 rtx op3 = expand_normal (arg3);
7725 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7726 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7728 gcc_assert (mode0 == mode1);
7730 if (arg0 == error_mark_node || arg1 == error_mark_node
7731 || arg2 == error_mark_node || arg3 == error_mark_node)
7735 || GET_MODE (target) != mode0
7736 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7737 target = gen_reg_rtx (mode0);
7739 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7740 op0 = copy_to_mode_reg (mode0, op0);
7741 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7742 op1 = copy_to_mode_reg (mode0, op1);
7743 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7744 op2 = copy_to_mode_reg (mode0, op2);
7745 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7746 op3 = copy_to_mode_reg (mode0, op3);
7748 /* Generate the compare. */
7749 scratch = gen_reg_rtx (CCmode);
7750 pat = GEN_FCN (icode) (scratch, op0, op1);
7755 if (mode0 == V2SImode)
7756 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7758 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7763 /* Expand an expression EXP that calls a built-in function,
7764 with result going to TARGET if that's convenient
7765 (and in mode MODE if that's convenient).
7766 SUBTARGET may be used as the target for computing one of EXP's operands.
7767 IGNORE is nonzero if the value is to be ignored. */
7770 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7771 enum machine_mode mode ATTRIBUTE_UNUSED,
7772 int ignore ATTRIBUTE_UNUSED)
7774 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7775 tree arglist = TREE_OPERAND (exp, 1);
7776 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7777 struct builtin_description *d;
7782 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7783 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7785 int icode = (int) CODE_FOR_altivec_lvsr;
7786 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7787 enum machine_mode mode = insn_data[icode].operand[1].mode;
7791 gcc_assert (TARGET_ALTIVEC);
7793 arg = TREE_VALUE (arglist);
7794 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7795 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7796 addr = memory_address (mode, op);
7797 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7801 /* For the load case need to negate the address. */
7802 op = gen_reg_rtx (GET_MODE (addr));
7803 emit_insn (gen_rtx_SET (VOIDmode, op,
7804 gen_rtx_NEG (GET_MODE (addr), addr)));
7806 op = gen_rtx_MEM (mode, op);
7809 || GET_MODE (target) != tmode
7810 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7811 target = gen_reg_rtx (tmode);
7813 /*pat = gen_altivec_lvsr (target, op);*/
7814 pat = GEN_FCN (icode) (target, op);
7824 ret = altivec_expand_builtin (exp, target, &success);
7831 ret = spe_expand_builtin (exp, target, &success);
7837 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7839 /* Handle simple unary operations. */
7840 d = (struct builtin_description *) bdesc_1arg;
7841 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7842 if (d->code == fcode)
7843 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7845 /* Handle simple binary operations. */
7846 d = (struct builtin_description *) bdesc_2arg;
7847 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7848 if (d->code == fcode)
7849 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7851 /* Handle simple ternary operations. */
7852 d = (struct builtin_description *) bdesc_3arg;
7853 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7854 if (d->code == fcode)
7855 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7861 build_opaque_vector_type (tree node, int nunits)
7863 node = copy_node (node);
7864 TYPE_MAIN_VARIANT (node) = node;
7865 return build_vector_type (node, nunits);
7869 rs6000_init_builtins (void)
7871 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7872 V2SF_type_node = build_vector_type (float_type_node, 2);
7873 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7874 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7875 V4SF_type_node = build_vector_type (float_type_node, 4);
7876 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7877 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7879 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7880 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7881 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7883 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7884 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7885 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7886 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7888 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7889 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7890 'vector unsigned short'. */
7892 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7893 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7894 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7895 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7897 long_integer_type_internal_node = long_integer_type_node;
7898 long_unsigned_type_internal_node = long_unsigned_type_node;
7899 intQI_type_internal_node = intQI_type_node;
7900 uintQI_type_internal_node = unsigned_intQI_type_node;
7901 intHI_type_internal_node = intHI_type_node;
7902 uintHI_type_internal_node = unsigned_intHI_type_node;
7903 intSI_type_internal_node = intSI_type_node;
7904 uintSI_type_internal_node = unsigned_intSI_type_node;
7905 float_type_internal_node = float_type_node;
7906 void_type_internal_node = void_type_node;
7908 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7909 get_identifier ("__bool char"),
7910 bool_char_type_node));
7911 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7912 get_identifier ("__bool short"),
7913 bool_short_type_node));
7914 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7915 get_identifier ("__bool int"),
7916 bool_int_type_node));
7917 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7918 get_identifier ("__pixel"),
7921 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7922 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7923 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7924 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7926 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7927 get_identifier ("__vector unsigned char"),
7928 unsigned_V16QI_type_node));
7929 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7930 get_identifier ("__vector signed char"),
7932 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7933 get_identifier ("__vector __bool char"),
7934 bool_V16QI_type_node));
7936 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7937 get_identifier ("__vector unsigned short"),
7938 unsigned_V8HI_type_node));
7939 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7940 get_identifier ("__vector signed short"),
7942 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7943 get_identifier ("__vector __bool short"),
7944 bool_V8HI_type_node));
7946 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7947 get_identifier ("__vector unsigned int"),
7948 unsigned_V4SI_type_node));
7949 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7950 get_identifier ("__vector signed int"),
7952 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7953 get_identifier ("__vector __bool int"),
7954 bool_V4SI_type_node));
7956 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7957 get_identifier ("__vector float"),
7959 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7960 get_identifier ("__vector __pixel"),
7961 pixel_V8HI_type_node));
7964 spe_init_builtins ();
7966 altivec_init_builtins ();
7967 if (TARGET_ALTIVEC || TARGET_SPE)
7968 rs6000_common_init_builtins ();
7971 /* Search through a set of builtins and enable the mask bits.
7972 DESC is an array of builtins.
7973 SIZE is the total number of builtins.
7974 START is the builtin enum at which to start.
7975 END is the builtin enum at which to end. */
7977 enable_mask_for_builtins (struct builtin_description *desc, int size,
7978 enum rs6000_builtins start,
7979 enum rs6000_builtins end)
7983 for (i = 0; i < size; ++i)
7984 if (desc[i].code == start)
7990 for (; i < size; ++i)
7992 /* Flip all the bits on. */
7993 desc[i].mask = target_flags;
7994 if (desc[i].code == end)
8000 spe_init_builtins (void)
8002 tree endlink = void_list_node;
8003 tree puint_type_node = build_pointer_type (unsigned_type_node);
8004 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8005 struct builtin_description *d;
8008 tree v2si_ftype_4_v2si
8009 = build_function_type
8010 (opaque_V2SI_type_node,
8011 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8012 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8013 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8014 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8017 tree v2sf_ftype_4_v2sf
8018 = build_function_type
8019 (opaque_V2SF_type_node,
8020 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8021 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8022 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8023 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8026 tree int_ftype_int_v2si_v2si
8027 = build_function_type
8029 tree_cons (NULL_TREE, integer_type_node,
8030 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8031 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8034 tree int_ftype_int_v2sf_v2sf
8035 = build_function_type
8037 tree_cons (NULL_TREE, integer_type_node,
8038 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8039 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8042 tree void_ftype_v2si_puint_int
8043 = build_function_type (void_type_node,
8044 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8045 tree_cons (NULL_TREE, puint_type_node,
8046 tree_cons (NULL_TREE,
8050 tree void_ftype_v2si_puint_char
8051 = build_function_type (void_type_node,
8052 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8053 tree_cons (NULL_TREE, puint_type_node,
8054 tree_cons (NULL_TREE,
8058 tree void_ftype_v2si_pv2si_int
8059 = build_function_type (void_type_node,
8060 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8061 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8062 tree_cons (NULL_TREE,
8066 tree void_ftype_v2si_pv2si_char
8067 = build_function_type (void_type_node,
8068 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8069 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8070 tree_cons (NULL_TREE,
8075 = build_function_type (void_type_node,
8076 tree_cons (NULL_TREE, integer_type_node, endlink));
8079 = build_function_type (integer_type_node, endlink);
8081 tree v2si_ftype_pv2si_int
8082 = build_function_type (opaque_V2SI_type_node,
8083 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8084 tree_cons (NULL_TREE, integer_type_node,
8087 tree v2si_ftype_puint_int
8088 = build_function_type (opaque_V2SI_type_node,
8089 tree_cons (NULL_TREE, puint_type_node,
8090 tree_cons (NULL_TREE, integer_type_node,
8093 tree v2si_ftype_pushort_int
8094 = build_function_type (opaque_V2SI_type_node,
8095 tree_cons (NULL_TREE, pushort_type_node,
8096 tree_cons (NULL_TREE, integer_type_node,
8099 tree v2si_ftype_signed_char
8100 = build_function_type (opaque_V2SI_type_node,
8101 tree_cons (NULL_TREE, signed_char_type_node,
8104 /* The initialization of the simple binary and unary builtins is
8105 done in rs6000_common_init_builtins, but we have to enable the
8106 mask bits here manually because we have run out of `target_flags'
8107 bits. We really need to redesign this mask business. */
8109 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8110 ARRAY_SIZE (bdesc_2arg),
8113 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8114 ARRAY_SIZE (bdesc_1arg),
8116 SPE_BUILTIN_EVSUBFUSIAAW);
8117 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8118 ARRAY_SIZE (bdesc_spe_predicates),
8119 SPE_BUILTIN_EVCMPEQ,
8120 SPE_BUILTIN_EVFSTSTLT);
8121 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8122 ARRAY_SIZE (bdesc_spe_evsel),
8123 SPE_BUILTIN_EVSEL_CMPGTS,
8124 SPE_BUILTIN_EVSEL_FSTSTEQ);
8126 (*lang_hooks.decls.pushdecl)
8127 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8128 opaque_V2SI_type_node));
8130 /* Initialize irregular SPE builtins. */
8132 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8133 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8134 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8135 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8136 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8137 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8138 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8139 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8140 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8141 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8142 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8143 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8144 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8145 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8146 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8147 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8148 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8149 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8152 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8153 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8154 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8155 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8156 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8157 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8158 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8159 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8160 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8161 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8162 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8163 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8164 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8165 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8166 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8167 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8168 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8169 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8170 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8171 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8172 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8173 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8176 d = (struct builtin_description *) bdesc_spe_predicates;
8177 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8181 switch (insn_data[d->icode].operand[1].mode)
8184 type = int_ftype_int_v2si_v2si;
8187 type = int_ftype_int_v2sf_v2sf;
8193 def_builtin (d->mask, d->name, type, d->code);
8196 /* Evsel predicates. */
8197 d = (struct builtin_description *) bdesc_spe_evsel;
8198 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8202 switch (insn_data[d->icode].operand[1].mode)
8205 type = v2si_ftype_4_v2si;
8208 type = v2sf_ftype_4_v2sf;
8214 def_builtin (d->mask, d->name, type, d->code);
8219 altivec_init_builtins (void)
8221 struct builtin_description *d;
8222 struct builtin_description_predicates *dp;
8226 tree pfloat_type_node = build_pointer_type (float_type_node);
8227 tree pint_type_node = build_pointer_type (integer_type_node);
8228 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8229 tree pchar_type_node = build_pointer_type (char_type_node);
8231 tree pvoid_type_node = build_pointer_type (void_type_node);
8233 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8234 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8235 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8236 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8238 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8240 tree int_ftype_opaque
8241 = build_function_type_list (integer_type_node,
8242 opaque_V4SI_type_node, NULL_TREE);
8244 tree opaque_ftype_opaque_int
8245 = build_function_type_list (opaque_V4SI_type_node,
8246 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8247 tree opaque_ftype_opaque_opaque_int
8248 = build_function_type_list (opaque_V4SI_type_node,
8249 opaque_V4SI_type_node, opaque_V4SI_type_node,
8250 integer_type_node, NULL_TREE);
8251 tree int_ftype_int_opaque_opaque
8252 = build_function_type_list (integer_type_node,
8253 integer_type_node, opaque_V4SI_type_node,
8254 opaque_V4SI_type_node, NULL_TREE);
8255 tree int_ftype_int_v4si_v4si
8256 = build_function_type_list (integer_type_node,
8257 integer_type_node, V4SI_type_node,
8258 V4SI_type_node, NULL_TREE);
8259 tree v4sf_ftype_pcfloat
8260 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8261 tree void_ftype_pfloat_v4sf
8262 = build_function_type_list (void_type_node,
8263 pfloat_type_node, V4SF_type_node, NULL_TREE);
8264 tree v4si_ftype_pcint
8265 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8266 tree void_ftype_pint_v4si
8267 = build_function_type_list (void_type_node,
8268 pint_type_node, V4SI_type_node, NULL_TREE);
8269 tree v8hi_ftype_pcshort
8270 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8271 tree void_ftype_pshort_v8hi
8272 = build_function_type_list (void_type_node,
8273 pshort_type_node, V8HI_type_node, NULL_TREE);
8274 tree v16qi_ftype_pcchar
8275 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8276 tree void_ftype_pchar_v16qi
8277 = build_function_type_list (void_type_node,
8278 pchar_type_node, V16QI_type_node, NULL_TREE);
8279 tree void_ftype_v4si
8280 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8281 tree v8hi_ftype_void
8282 = build_function_type (V8HI_type_node, void_list_node);
8283 tree void_ftype_void
8284 = build_function_type (void_type_node, void_list_node);
8286 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8288 tree opaque_ftype_long_pcvoid
8289 = build_function_type_list (opaque_V4SI_type_node,
8290 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8291 tree v16qi_ftype_long_pcvoid
8292 = build_function_type_list (V16QI_type_node,
8293 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8294 tree v8hi_ftype_long_pcvoid
8295 = build_function_type_list (V8HI_type_node,
8296 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8297 tree v4si_ftype_long_pcvoid
8298 = build_function_type_list (V4SI_type_node,
8299 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8301 tree void_ftype_opaque_long_pvoid
8302 = build_function_type_list (void_type_node,
8303 opaque_V4SI_type_node, long_integer_type_node,
8304 pvoid_type_node, NULL_TREE);
8305 tree void_ftype_v4si_long_pvoid
8306 = build_function_type_list (void_type_node,
8307 V4SI_type_node, long_integer_type_node,
8308 pvoid_type_node, NULL_TREE);
8309 tree void_ftype_v16qi_long_pvoid
8310 = build_function_type_list (void_type_node,
8311 V16QI_type_node, long_integer_type_node,
8312 pvoid_type_node, NULL_TREE);
8313 tree void_ftype_v8hi_long_pvoid
8314 = build_function_type_list (void_type_node,
8315 V8HI_type_node, long_integer_type_node,
8316 pvoid_type_node, NULL_TREE);
8317 tree int_ftype_int_v8hi_v8hi
8318 = build_function_type_list (integer_type_node,
8319 integer_type_node, V8HI_type_node,
8320 V8HI_type_node, NULL_TREE);
8321 tree int_ftype_int_v16qi_v16qi
8322 = build_function_type_list (integer_type_node,
8323 integer_type_node, V16QI_type_node,
8324 V16QI_type_node, NULL_TREE);
8325 tree int_ftype_int_v4sf_v4sf
8326 = build_function_type_list (integer_type_node,
8327 integer_type_node, V4SF_type_node,
8328 V4SF_type_node, NULL_TREE);
8329 tree v4si_ftype_v4si
8330 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8331 tree v8hi_ftype_v8hi
8332 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8333 tree v16qi_ftype_v16qi
8334 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8335 tree v4sf_ftype_v4sf
8336 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8337 tree void_ftype_pcvoid_int_int
8338 = build_function_type_list (void_type_node,
8339 pcvoid_type_node, integer_type_node,
8340 integer_type_node, NULL_TREE);
8342 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8343 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8344 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8345 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8346 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8347 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8348 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8349 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8350 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8351 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8352 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8353 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8354 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8355 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8356 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8357 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8358 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8359 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8360 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8361 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8362 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8363 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8364 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8365 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8366 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8367 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8368 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8369 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8370 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8371 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8372 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8373 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8374 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8375 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8376 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8377 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8378 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8379 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8380 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8381 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8382 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8383 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8384 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8385 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8386 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8387 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8389 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8391 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8392 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8393 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8394 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8395 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8396 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8397 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8398 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8399 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8400 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8402 /* Add the DST variants. */
8403 d = (struct builtin_description *) bdesc_dst;
8404 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8405 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8407 /* Initialize the predicates. */
8408 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8409 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8411 enum machine_mode mode1;
8413 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8414 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8419 mode1 = insn_data[dp->icode].operand[1].mode;
8424 type = int_ftype_int_opaque_opaque;
8427 type = int_ftype_int_v4si_v4si;
8430 type = int_ftype_int_v8hi_v8hi;
8433 type = int_ftype_int_v16qi_v16qi;
8436 type = int_ftype_int_v4sf_v4sf;
8442 def_builtin (dp->mask, dp->name, type, dp->code);
8445 /* Initialize the abs* operators. */
8446 d = (struct builtin_description *) bdesc_abs;
8447 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8449 enum machine_mode mode0;
8452 mode0 = insn_data[d->icode].operand[0].mode;
8457 type = v4si_ftype_v4si;
8460 type = v8hi_ftype_v8hi;
8463 type = v16qi_ftype_v16qi;
8466 type = v4sf_ftype_v4sf;
8472 def_builtin (d->mask, d->name, type, d->code);
8479 /* Initialize target builtin that implements
8480 targetm.vectorize.builtin_mask_for_load. */
8482 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8483 v16qi_ftype_long_pcvoid,
8484 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8486 tree_cons (get_identifier ("const"),
8487 NULL_TREE, NULL_TREE));
8488 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8489 altivec_builtin_mask_for_load = decl;
8492 /* Access to the vec_init patterns. */
8493 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8494 integer_type_node, integer_type_node,
8495 integer_type_node, NULL_TREE);
8496 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8497 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8499 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8500 short_integer_type_node,
8501 short_integer_type_node,
8502 short_integer_type_node,
8503 short_integer_type_node,
8504 short_integer_type_node,
8505 short_integer_type_node,
8506 short_integer_type_node, NULL_TREE);
8507 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8508 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8510 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8511 char_type_node, char_type_node,
8512 char_type_node, char_type_node,
8513 char_type_node, char_type_node,
8514 char_type_node, char_type_node,
8515 char_type_node, char_type_node,
8516 char_type_node, char_type_node,
8517 char_type_node, char_type_node,
8518 char_type_node, NULL_TREE);
8519 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8520 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8522 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8523 float_type_node, float_type_node,
8524 float_type_node, NULL_TREE);
8525 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8526 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8528 /* Access to the vec_set patterns. */
8529 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8531 integer_type_node, NULL_TREE);
8532 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8533 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8535 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8537 integer_type_node, NULL_TREE);
8538 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8539 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8541 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8543 integer_type_node, NULL_TREE);
8544 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8545 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8547 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8549 integer_type_node, NULL_TREE);
8550 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8551 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8553 /* Access to the vec_extract patterns. */
8554 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8555 integer_type_node, NULL_TREE);
8556 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8557 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8559 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8560 integer_type_node, NULL_TREE);
8561 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8562 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8564 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8565 integer_type_node, NULL_TREE);
8566 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8567 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8569 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8570 integer_type_node, NULL_TREE);
8571 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8572 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8576 rs6000_common_init_builtins (void)
8578 struct builtin_description *d;
8581 tree v4sf_ftype_v4sf_v4sf_v16qi
8582 = build_function_type_list (V4SF_type_node,
8583 V4SF_type_node, V4SF_type_node,
8584 V16QI_type_node, NULL_TREE);
8585 tree v4si_ftype_v4si_v4si_v16qi
8586 = build_function_type_list (V4SI_type_node,
8587 V4SI_type_node, V4SI_type_node,
8588 V16QI_type_node, NULL_TREE);
8589 tree v8hi_ftype_v8hi_v8hi_v16qi
8590 = build_function_type_list (V8HI_type_node,
8591 V8HI_type_node, V8HI_type_node,
8592 V16QI_type_node, NULL_TREE);
8593 tree v16qi_ftype_v16qi_v16qi_v16qi
8594 = build_function_type_list (V16QI_type_node,
8595 V16QI_type_node, V16QI_type_node,
8596 V16QI_type_node, NULL_TREE);
8598 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8600 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8601 tree v16qi_ftype_int
8602 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8603 tree v8hi_ftype_v16qi
8604 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8605 tree v4sf_ftype_v4sf
8606 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8608 tree v2si_ftype_v2si_v2si
8609 = build_function_type_list (opaque_V2SI_type_node,
8610 opaque_V2SI_type_node,
8611 opaque_V2SI_type_node, NULL_TREE);
8613 tree v2sf_ftype_v2sf_v2sf
8614 = build_function_type_list (opaque_V2SF_type_node,
8615 opaque_V2SF_type_node,
8616 opaque_V2SF_type_node, NULL_TREE);
8618 tree v2si_ftype_int_int
8619 = build_function_type_list (opaque_V2SI_type_node,
8620 integer_type_node, integer_type_node,
8623 tree opaque_ftype_opaque
8624 = build_function_type_list (opaque_V4SI_type_node,
8625 opaque_V4SI_type_node, NULL_TREE);
8627 tree v2si_ftype_v2si
8628 = build_function_type_list (opaque_V2SI_type_node,
8629 opaque_V2SI_type_node, NULL_TREE);
8631 tree v2sf_ftype_v2sf
8632 = build_function_type_list (opaque_V2SF_type_node,
8633 opaque_V2SF_type_node, NULL_TREE);
8635 tree v2sf_ftype_v2si
8636 = build_function_type_list (opaque_V2SF_type_node,
8637 opaque_V2SI_type_node, NULL_TREE);
8639 tree v2si_ftype_v2sf
8640 = build_function_type_list (opaque_V2SI_type_node,
8641 opaque_V2SF_type_node, NULL_TREE);
8643 tree v2si_ftype_v2si_char
8644 = build_function_type_list (opaque_V2SI_type_node,
8645 opaque_V2SI_type_node,
8646 char_type_node, NULL_TREE);
8648 tree v2si_ftype_int_char
8649 = build_function_type_list (opaque_V2SI_type_node,
8650 integer_type_node, char_type_node, NULL_TREE);
8652 tree v2si_ftype_char
8653 = build_function_type_list (opaque_V2SI_type_node,
8654 char_type_node, NULL_TREE);
8656 tree int_ftype_int_int
8657 = build_function_type_list (integer_type_node,
8658 integer_type_node, integer_type_node,
8661 tree opaque_ftype_opaque_opaque
8662 = build_function_type_list (opaque_V4SI_type_node,
8663 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8664 tree v4si_ftype_v4si_v4si
8665 = build_function_type_list (V4SI_type_node,
8666 V4SI_type_node, V4SI_type_node, NULL_TREE);
8667 tree v4sf_ftype_v4si_int
8668 = build_function_type_list (V4SF_type_node,
8669 V4SI_type_node, integer_type_node, NULL_TREE);
8670 tree v4si_ftype_v4sf_int
8671 = build_function_type_list (V4SI_type_node,
8672 V4SF_type_node, integer_type_node, NULL_TREE);
8673 tree v4si_ftype_v4si_int
8674 = build_function_type_list (V4SI_type_node,
8675 V4SI_type_node, integer_type_node, NULL_TREE);
8676 tree v8hi_ftype_v8hi_int
8677 = build_function_type_list (V8HI_type_node,
8678 V8HI_type_node, integer_type_node, NULL_TREE);
8679 tree v16qi_ftype_v16qi_int
8680 = build_function_type_list (V16QI_type_node,
8681 V16QI_type_node, integer_type_node, NULL_TREE);
8682 tree v16qi_ftype_v16qi_v16qi_int
8683 = build_function_type_list (V16QI_type_node,
8684 V16QI_type_node, V16QI_type_node,
8685 integer_type_node, NULL_TREE);
8686 tree v8hi_ftype_v8hi_v8hi_int
8687 = build_function_type_list (V8HI_type_node,
8688 V8HI_type_node, V8HI_type_node,
8689 integer_type_node, NULL_TREE);
8690 tree v4si_ftype_v4si_v4si_int
8691 = build_function_type_list (V4SI_type_node,
8692 V4SI_type_node, V4SI_type_node,
8693 integer_type_node, NULL_TREE);
8694 tree v4sf_ftype_v4sf_v4sf_int
8695 = build_function_type_list (V4SF_type_node,
8696 V4SF_type_node, V4SF_type_node,
8697 integer_type_node, NULL_TREE);
8698 tree v4sf_ftype_v4sf_v4sf
8699 = build_function_type_list (V4SF_type_node,
8700 V4SF_type_node, V4SF_type_node, NULL_TREE);
8701 tree opaque_ftype_opaque_opaque_opaque
8702 = build_function_type_list (opaque_V4SI_type_node,
8703 opaque_V4SI_type_node, opaque_V4SI_type_node,
8704 opaque_V4SI_type_node, NULL_TREE);
8705 tree v4sf_ftype_v4sf_v4sf_v4si
8706 = build_function_type_list (V4SF_type_node,
8707 V4SF_type_node, V4SF_type_node,
8708 V4SI_type_node, NULL_TREE);
8709 tree v4sf_ftype_v4sf_v4sf_v4sf
8710 = build_function_type_list (V4SF_type_node,
8711 V4SF_type_node, V4SF_type_node,
8712 V4SF_type_node, NULL_TREE);
8713 tree v4si_ftype_v4si_v4si_v4si
8714 = build_function_type_list (V4SI_type_node,
8715 V4SI_type_node, V4SI_type_node,
8716 V4SI_type_node, NULL_TREE);
8717 tree v8hi_ftype_v8hi_v8hi
8718 = build_function_type_list (V8HI_type_node,
8719 V8HI_type_node, V8HI_type_node, NULL_TREE);
8720 tree v8hi_ftype_v8hi_v8hi_v8hi
8721 = build_function_type_list (V8HI_type_node,
8722 V8HI_type_node, V8HI_type_node,
8723 V8HI_type_node, NULL_TREE);
8724 tree v4si_ftype_v8hi_v8hi_v4si
8725 = build_function_type_list (V4SI_type_node,
8726 V8HI_type_node, V8HI_type_node,
8727 V4SI_type_node, NULL_TREE);
8728 tree v4si_ftype_v16qi_v16qi_v4si
8729 = build_function_type_list (V4SI_type_node,
8730 V16QI_type_node, V16QI_type_node,
8731 V4SI_type_node, NULL_TREE);
8732 tree v16qi_ftype_v16qi_v16qi
8733 = build_function_type_list (V16QI_type_node,
8734 V16QI_type_node, V16QI_type_node, NULL_TREE);
8735 tree v4si_ftype_v4sf_v4sf
8736 = build_function_type_list (V4SI_type_node,
8737 V4SF_type_node, V4SF_type_node, NULL_TREE);
8738 tree v8hi_ftype_v16qi_v16qi
8739 = build_function_type_list (V8HI_type_node,
8740 V16QI_type_node, V16QI_type_node, NULL_TREE);
8741 tree v4si_ftype_v8hi_v8hi
8742 = build_function_type_list (V4SI_type_node,
8743 V8HI_type_node, V8HI_type_node, NULL_TREE);
8744 tree v8hi_ftype_v4si_v4si
8745 = build_function_type_list (V8HI_type_node,
8746 V4SI_type_node, V4SI_type_node, NULL_TREE);
8747 tree v16qi_ftype_v8hi_v8hi
8748 = build_function_type_list (V16QI_type_node,
8749 V8HI_type_node, V8HI_type_node, NULL_TREE);
8750 tree v4si_ftype_v16qi_v4si
8751 = build_function_type_list (V4SI_type_node,
8752 V16QI_type_node, V4SI_type_node, NULL_TREE);
8753 tree v4si_ftype_v16qi_v16qi
8754 = build_function_type_list (V4SI_type_node,
8755 V16QI_type_node, V16QI_type_node, NULL_TREE);
8756 tree v4si_ftype_v8hi_v4si
8757 = build_function_type_list (V4SI_type_node,
8758 V8HI_type_node, V4SI_type_node, NULL_TREE);
8759 tree v4si_ftype_v8hi
8760 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8761 tree int_ftype_v4si_v4si
8762 = build_function_type_list (integer_type_node,
8763 V4SI_type_node, V4SI_type_node, NULL_TREE);
8764 tree int_ftype_v4sf_v4sf
8765 = build_function_type_list (integer_type_node,
8766 V4SF_type_node, V4SF_type_node, NULL_TREE);
8767 tree int_ftype_v16qi_v16qi
8768 = build_function_type_list (integer_type_node,
8769 V16QI_type_node, V16QI_type_node, NULL_TREE);
8770 tree int_ftype_v8hi_v8hi
8771 = build_function_type_list (integer_type_node,
8772 V8HI_type_node, V8HI_type_node, NULL_TREE);
8774 /* Add the simple ternary operators. */
8775 d = (struct builtin_description *) bdesc_3arg;
8776 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8778 enum machine_mode mode0, mode1, mode2, mode3;
8780 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8781 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8792 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8795 mode0 = insn_data[d->icode].operand[0].mode;
8796 mode1 = insn_data[d->icode].operand[1].mode;
8797 mode2 = insn_data[d->icode].operand[2].mode;
8798 mode3 = insn_data[d->icode].operand[3].mode;
8801 /* When all four are of the same mode. */
8802 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8807 type = opaque_ftype_opaque_opaque_opaque;
8810 type = v4si_ftype_v4si_v4si_v4si;
8813 type = v4sf_ftype_v4sf_v4sf_v4sf;
8816 type = v8hi_ftype_v8hi_v8hi_v8hi;
8819 type = v16qi_ftype_v16qi_v16qi_v16qi;
8825 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8830 type = v4si_ftype_v4si_v4si_v16qi;
8833 type = v4sf_ftype_v4sf_v4sf_v16qi;
8836 type = v8hi_ftype_v8hi_v8hi_v16qi;
8839 type = v16qi_ftype_v16qi_v16qi_v16qi;
8845 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8846 && mode3 == V4SImode)
8847 type = v4si_ftype_v16qi_v16qi_v4si;
8848 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8849 && mode3 == V4SImode)
8850 type = v4si_ftype_v8hi_v8hi_v4si;
8851 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8852 && mode3 == V4SImode)
8853 type = v4sf_ftype_v4sf_v4sf_v4si;
8855 /* vchar, vchar, vchar, 4 bit literal. */
8856 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8858 type = v16qi_ftype_v16qi_v16qi_int;
8860 /* vshort, vshort, vshort, 4 bit literal. */
8861 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8863 type = v8hi_ftype_v8hi_v8hi_int;
8865 /* vint, vint, vint, 4 bit literal. */
8866 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8868 type = v4si_ftype_v4si_v4si_int;
8870 /* vfloat, vfloat, vfloat, 4 bit literal. */
8871 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8873 type = v4sf_ftype_v4sf_v4sf_int;
8878 def_builtin (d->mask, d->name, type, d->code);
8881 /* Add the simple binary operators. */
8882 d = (struct builtin_description *) bdesc_2arg;
8883 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8885 enum machine_mode mode0, mode1, mode2;
8887 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8888 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8898 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8901 mode0 = insn_data[d->icode].operand[0].mode;
8902 mode1 = insn_data[d->icode].operand[1].mode;
8903 mode2 = insn_data[d->icode].operand[2].mode;
8906 /* When all three operands are of the same mode. */
8907 if (mode0 == mode1 && mode1 == mode2)
8912 type = opaque_ftype_opaque_opaque;
8915 type = v4sf_ftype_v4sf_v4sf;
8918 type = v4si_ftype_v4si_v4si;
8921 type = v16qi_ftype_v16qi_v16qi;
8924 type = v8hi_ftype_v8hi_v8hi;
8927 type = v2si_ftype_v2si_v2si;
8930 type = v2sf_ftype_v2sf_v2sf;
8933 type = int_ftype_int_int;
8940 /* A few other combos we really don't want to do manually. */
8942 /* vint, vfloat, vfloat. */
8943 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8944 type = v4si_ftype_v4sf_v4sf;
8946 /* vshort, vchar, vchar. */
8947 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8948 type = v8hi_ftype_v16qi_v16qi;
8950 /* vint, vshort, vshort. */
8951 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8952 type = v4si_ftype_v8hi_v8hi;
8954 /* vshort, vint, vint. */
8955 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8956 type = v8hi_ftype_v4si_v4si;
8958 /* vchar, vshort, vshort. */
8959 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8960 type = v16qi_ftype_v8hi_v8hi;
8962 /* vint, vchar, vint. */
8963 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8964 type = v4si_ftype_v16qi_v4si;
8966 /* vint, vchar, vchar. */
8967 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8968 type = v4si_ftype_v16qi_v16qi;
8970 /* vint, vshort, vint. */
8971 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8972 type = v4si_ftype_v8hi_v4si;
8974 /* vint, vint, 5 bit literal. */
8975 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8976 type = v4si_ftype_v4si_int;
8978 /* vshort, vshort, 5 bit literal. */
8979 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8980 type = v8hi_ftype_v8hi_int;
8982 /* vchar, vchar, 5 bit literal. */
8983 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8984 type = v16qi_ftype_v16qi_int;
8986 /* vfloat, vint, 5 bit literal. */
8987 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8988 type = v4sf_ftype_v4si_int;
8990 /* vint, vfloat, 5 bit literal. */
8991 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8992 type = v4si_ftype_v4sf_int;
8994 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8995 type = v2si_ftype_int_int;
8997 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8998 type = v2si_ftype_v2si_char;
9000 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9001 type = v2si_ftype_int_char;
9006 gcc_assert (mode0 == SImode);
9010 type = int_ftype_v4si_v4si;
9013 type = int_ftype_v4sf_v4sf;
9016 type = int_ftype_v16qi_v16qi;
9019 type = int_ftype_v8hi_v8hi;
9026 def_builtin (d->mask, d->name, type, d->code);
9029 /* Add the simple unary operators. */
9030 d = (struct builtin_description *) bdesc_1arg;
9031 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9033 enum machine_mode mode0, mode1;
9035 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9036 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9045 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9048 mode0 = insn_data[d->icode].operand[0].mode;
9049 mode1 = insn_data[d->icode].operand[1].mode;
9052 if (mode0 == V4SImode && mode1 == QImode)
9053 type = v4si_ftype_int;
9054 else if (mode0 == V8HImode && mode1 == QImode)
9055 type = v8hi_ftype_int;
9056 else if (mode0 == V16QImode && mode1 == QImode)
9057 type = v16qi_ftype_int;
9058 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9059 type = opaque_ftype_opaque;
9060 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9061 type = v4sf_ftype_v4sf;
9062 else if (mode0 == V8HImode && mode1 == V16QImode)
9063 type = v8hi_ftype_v16qi;
9064 else if (mode0 == V4SImode && mode1 == V8HImode)
9065 type = v4si_ftype_v8hi;
9066 else if (mode0 == V2SImode && mode1 == V2SImode)
9067 type = v2si_ftype_v2si;
9068 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9069 type = v2sf_ftype_v2sf;
9070 else if (mode0 == V2SFmode && mode1 == V2SImode)
9071 type = v2sf_ftype_v2si;
9072 else if (mode0 == V2SImode && mode1 == V2SFmode)
9073 type = v2si_ftype_v2sf;
9074 else if (mode0 == V2SImode && mode1 == QImode)
9075 type = v2si_ftype_char;
9079 def_builtin (d->mask, d->name, type, d->code);
9084 rs6000_init_libfuncs (void)
9086 if (!TARGET_HARD_FLOAT)
9089 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9090 && !TARGET_POWER2 && !TARGET_POWERPC)
9092 /* AIX library routines for float->int conversion. */
9093 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9094 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9095 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9096 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9099 if (!TARGET_IEEEQUAD)
9100 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9101 if (!TARGET_XL_COMPAT)
9103 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9104 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9105 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9106 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9110 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9111 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9112 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9113 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9117 /* 32-bit SVR4 quad floating point routines. */
9119 set_optab_libfunc (add_optab, TFmode, "_q_add");
9120 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9121 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9122 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9123 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9124 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9125 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9127 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9128 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9129 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9130 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9131 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9132 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9134 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9135 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9136 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9137 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9138 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9139 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9140 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9141 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9146 /* Expand a block clear operation, and return 1 if successful. Return 0
9147 if we should let the compiler generate normal code.
9149 operands[0] is the destination
9150 operands[1] is the length
9151 operands[3] is the alignment */
9154 expand_block_clear (rtx operands[])
9156 rtx orig_dest = operands[0];
9157 rtx bytes_rtx = operands[1];
9158 rtx align_rtx = operands[3];
9159 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9160 HOST_WIDE_INT align;
9161 HOST_WIDE_INT bytes;
9166 /* If this is not a fixed size move, just call memcpy */
9170 /* This must be a fixed size alignment */
9171 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9172 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9174 /* Anything to clear? */
9175 bytes = INTVAL (bytes_rtx);
9179 /* Use the builtin memset after a point, to avoid huge code bloat.
9180 When optimize_size, avoid any significant code bloat; calling
9181 memset is about 4 instructions, so allow for one instruction to
9182 load zero and three to do clearing. */
9183 if (TARGET_ALTIVEC && align >= 128)
9185 else if (TARGET_POWERPC64 && align >= 32)
9190 if (optimize_size && bytes > 3 * clear_step)
9192 if (! optimize_size && bytes > 8 * clear_step)
9195 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9197 enum machine_mode mode = BLKmode;
9200 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9205 else if (bytes >= 8 && TARGET_POWERPC64
9206 /* 64-bit loads and stores require word-aligned
9208 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9213 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9214 { /* move 4 bytes */
9218 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9219 { /* move 2 bytes */
9223 else /* move 1 byte at a time */
9229 dest = adjust_address (orig_dest, mode, offset);
9231 emit_move_insn (dest, CONST0_RTX (mode));
9238 /* Expand a block move operation, and return 1 if successful. Return 0
9239 if we should let the compiler generate normal code.
9241 operands[0] is the destination
9242 operands[1] is the source
9243 operands[2] is the length
9244 operands[3] is the alignment */
9246 #define MAX_MOVE_REG 4
9249 expand_block_move (rtx operands[])
9251 rtx orig_dest = operands[0];
9252 rtx orig_src = operands[1];
9253 rtx bytes_rtx = operands[2];
9254 rtx align_rtx = operands[3];
9255 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9260 rtx stores[MAX_MOVE_REG];
9263 /* If this is not a fixed size move, just call memcpy */
9267 /* This must be a fixed size alignment */
9268 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9269 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9271 /* Anything to move? */
9272 bytes = INTVAL (bytes_rtx);
9276 /* store_one_arg depends on expand_block_move to handle at least the size of
9277 reg_parm_stack_space. */
9278 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9281 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9284 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9285 rtx (*mov) (rtx, rtx);
9287 enum machine_mode mode = BLKmode;
9290 /* Altivec first, since it will be faster than a string move
9291 when it applies, and usually not significantly larger. */
9292 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9296 gen_func.mov = gen_movv4si;
9298 else if (TARGET_STRING
9299 && bytes > 24 /* move up to 32 bytes at a time */
9307 && ! fixed_regs[12])
9309 move_bytes = (bytes > 32) ? 32 : bytes;
9310 gen_func.movmemsi = gen_movmemsi_8reg;
9312 else if (TARGET_STRING
9313 && bytes > 16 /* move up to 24 bytes at a time */
9319 && ! fixed_regs[10])
9321 move_bytes = (bytes > 24) ? 24 : bytes;
9322 gen_func.movmemsi = gen_movmemsi_6reg;
9324 else if (TARGET_STRING
9325 && bytes > 8 /* move up to 16 bytes at a time */
9331 move_bytes = (bytes > 16) ? 16 : bytes;
9332 gen_func.movmemsi = gen_movmemsi_4reg;
9334 else if (bytes >= 8 && TARGET_POWERPC64
9335 /* 64-bit loads and stores require word-aligned
9337 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9341 gen_func.mov = gen_movdi;
9343 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9344 { /* move up to 8 bytes at a time */
9345 move_bytes = (bytes > 8) ? 8 : bytes;
9346 gen_func.movmemsi = gen_movmemsi_2reg;
9348 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9349 { /* move 4 bytes */
9352 gen_func.mov = gen_movsi;
9354 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9355 { /* move 2 bytes */
9358 gen_func.mov = gen_movhi;
9360 else if (TARGET_STRING && bytes > 1)
9361 { /* move up to 4 bytes at a time */
9362 move_bytes = (bytes > 4) ? 4 : bytes;
9363 gen_func.movmemsi = gen_movmemsi_1reg;
9365 else /* move 1 byte at a time */
9369 gen_func.mov = gen_movqi;
9372 src = adjust_address (orig_src, mode, offset);
9373 dest = adjust_address (orig_dest, mode, offset);
9375 if (mode != BLKmode)
9377 rtx tmp_reg = gen_reg_rtx (mode);
9379 emit_insn ((*gen_func.mov) (tmp_reg, src));
9380 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9383 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9386 for (i = 0; i < num_reg; i++)
9387 emit_insn (stores[i]);
9391 if (mode == BLKmode)
9393 /* Move the address into scratch registers. The movmemsi
9394 patterns require zero offset. */
9395 if (!REG_P (XEXP (src, 0)))
9397 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9398 src = replace_equiv_address (src, src_reg);
9400 set_mem_size (src, GEN_INT (move_bytes));
9402 if (!REG_P (XEXP (dest, 0)))
9404 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9405 dest = replace_equiv_address (dest, dest_reg);
9407 set_mem_size (dest, GEN_INT (move_bytes));
9409 emit_insn ((*gen_func.movmemsi) (dest, src,
9410 GEN_INT (move_bytes & 31),
9419 /* Return a string to perform a load_multiple operation.
9420 operands[0] is the vector.
9421 operands[1] is the source address.
9422 operands[2] is the first destination register. */
9425 rs6000_output_load_multiple (rtx operands[3])
9427 /* We have to handle the case where the pseudo used to contain the address
9428 is assigned to one of the output registers. */
9430 int words = XVECLEN (operands[0], 0);
9433 if (XVECLEN (operands[0], 0) == 1)
9434 return "{l|lwz} %2,0(%1)";
9436 for (i = 0; i < words; i++)
9437 if (refers_to_regno_p (REGNO (operands[2]) + i,
9438 REGNO (operands[2]) + i + 1, operands[1], 0))
9442 xop[0] = GEN_INT (4 * (words-1));
9443 xop[1] = operands[1];
9444 xop[2] = operands[2];
9445 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9450 xop[0] = GEN_INT (4 * (words-1));
9451 xop[1] = operands[1];
9452 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9453 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9458 for (j = 0; j < words; j++)
9461 xop[0] = GEN_INT (j * 4);
9462 xop[1] = operands[1];
9463 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9464 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9466 xop[0] = GEN_INT (i * 4);
9467 xop[1] = operands[1];
9468 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9473 return "{lsi|lswi} %2,%1,%N0";
9477 /* A validation routine: say whether CODE, a condition code, and MODE
9478 match. The other alternatives either don't make sense or should
9479 never be generated. */
9482 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9484 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9485 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9486 && GET_MODE_CLASS (mode) == MODE_CC);
9488 /* These don't make sense. */
9489 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9490 || mode != CCUNSmode);
9492 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9493 || mode == CCUNSmode);
9495 gcc_assert (mode == CCFPmode
9496 || (code != ORDERED && code != UNORDERED
9497 && code != UNEQ && code != LTGT
9498 && code != UNGT && code != UNLT
9499 && code != UNGE && code != UNLE));
9501 /* These should never be generated except for
9502 flag_finite_math_only. */
9503 gcc_assert (mode != CCFPmode
9504 || flag_finite_math_only
9505 || (code != LE && code != GE
9506 && code != UNEQ && code != LTGT
9507 && code != UNGT && code != UNLT));
9509 /* These are invalid; the information is not there. */
9510 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9514 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9515 mask required to convert the result of a rotate insn into a shift
9516 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9519 includes_lshift_p (rtx shiftop, rtx andop)
9521 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9523 shift_mask <<= INTVAL (shiftop);
9525 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9528 /* Similar, but for right shift. */
9531 includes_rshift_p (rtx shiftop, rtx andop)
9533 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9535 shift_mask >>= INTVAL (shiftop);
9537 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9540 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9541 to perform a left shift. It must have exactly SHIFTOP least
9542 significant 0's, then one or more 1's, then zero or more 0's. */
9545 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9547 if (GET_CODE (andop) == CONST_INT)
9549 HOST_WIDE_INT c, lsb, shift_mask;
9552 if (c == 0 || c == ~0)
9556 shift_mask <<= INTVAL (shiftop);
9558 /* Find the least significant one bit. */
9561 /* It must coincide with the LSB of the shift mask. */
9562 if (-lsb != shift_mask)
9565 /* Invert to look for the next transition (if any). */
9568 /* Remove the low group of ones (originally low group of zeros). */
9571 /* Again find the lsb, and check we have all 1's above. */
9575 else if (GET_CODE (andop) == CONST_DOUBLE
9576 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9578 HOST_WIDE_INT low, high, lsb;
9579 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9581 low = CONST_DOUBLE_LOW (andop);
9582 if (HOST_BITS_PER_WIDE_INT < 64)
9583 high = CONST_DOUBLE_HIGH (andop);
9585 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9586 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9589 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9591 shift_mask_high = ~0;
9592 if (INTVAL (shiftop) > 32)
9593 shift_mask_high <<= INTVAL (shiftop) - 32;
9597 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9604 return high == -lsb;
9607 shift_mask_low = ~0;
9608 shift_mask_low <<= INTVAL (shiftop);
9612 if (-lsb != shift_mask_low)
9615 if (HOST_BITS_PER_WIDE_INT < 64)
9620 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9623 return high == -lsb;
9627 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9633 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9634 to perform a left shift. It must have SHIFTOP or more least
9635 significant 0's, with the remainder of the word 1's. */
9638 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9640 if (GET_CODE (andop) == CONST_INT)
9642 HOST_WIDE_INT c, lsb, shift_mask;
9645 shift_mask <<= INTVAL (shiftop);
9648 /* Find the least significant one bit. */
9651 /* It must be covered by the shift mask.
9652 This test also rejects c == 0. */
9653 if ((lsb & shift_mask) == 0)
9656 /* Check we have all 1's above the transition, and reject all 1's. */
9657 return c == -lsb && lsb != 1;
9659 else if (GET_CODE (andop) == CONST_DOUBLE
9660 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9662 HOST_WIDE_INT low, lsb, shift_mask_low;
9664 low = CONST_DOUBLE_LOW (andop);
9666 if (HOST_BITS_PER_WIDE_INT < 64)
9668 HOST_WIDE_INT high, shift_mask_high;
9670 high = CONST_DOUBLE_HIGH (andop);
9674 shift_mask_high = ~0;
9675 if (INTVAL (shiftop) > 32)
9676 shift_mask_high <<= INTVAL (shiftop) - 32;
9680 if ((lsb & shift_mask_high) == 0)
9683 return high == -lsb;
9689 shift_mask_low = ~0;
9690 shift_mask_low <<= INTVAL (shiftop);
9694 if ((lsb & shift_mask_low) == 0)
9697 return low == -lsb && lsb != 1;
9703 /* Return 1 if operands will generate a valid arguments to rlwimi
9704 instruction for insert with right shift in 64-bit mode. The mask may
9705 not start on the first bit or stop on the last bit because wrap-around
9706 effects of instruction do not correspond to semantics of RTL insn. */
9709 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9711 if (INTVAL (startop) < 64
9712 && INTVAL (startop) > 32
9713 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9714 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9715 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9716 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9717 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9723 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9724 for lfq and stfq insns iff the registers are hard registers. */
9727 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9729 /* We might have been passed a SUBREG. */
9730 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9733 /* We might have been passed non floating point registers. */
9734 if (!FP_REGNO_P (REGNO (reg1))
9735 || !FP_REGNO_P (REGNO (reg2)))
9738 return (REGNO (reg1) == REGNO (reg2) - 1);
9741 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9742 addr1 and addr2 must be in consecutive memory locations
9743 (addr2 == addr1 + 8). */
9746 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9749 unsigned int reg1, reg2;
9750 int offset1, offset2;
9752 /* The mems cannot be volatile. */
9753 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9756 addr1 = XEXP (mem1, 0);
9757 addr2 = XEXP (mem2, 0);
9759 /* Extract an offset (if used) from the first addr. */
9760 if (GET_CODE (addr1) == PLUS)
9762 /* If not a REG, return zero. */
9763 if (GET_CODE (XEXP (addr1, 0)) != REG)
9767 reg1 = REGNO (XEXP (addr1, 0));
9768 /* The offset must be constant! */
9769 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9771 offset1 = INTVAL (XEXP (addr1, 1));
9774 else if (GET_CODE (addr1) != REG)
9778 reg1 = REGNO (addr1);
9779 /* This was a simple (mem (reg)) expression. Offset is 0. */
9783 /* And now for the second addr. */
9784 if (GET_CODE (addr2) == PLUS)
9786 /* If not a REG, return zero. */
9787 if (GET_CODE (XEXP (addr2, 0)) != REG)
9791 reg2 = REGNO (XEXP (addr2, 0));
9792 /* The offset must be constant. */
9793 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9795 offset2 = INTVAL (XEXP (addr2, 1));
9798 else if (GET_CODE (addr2) != REG)
9802 reg2 = REGNO (addr2);
9803 /* This was a simple (mem (reg)) expression. Offset is 0. */
9807 /* Both of these must have the same base register. */
9811 /* The offset for the second addr must be 8 more than the first addr. */
9812 if (offset2 != offset1 + 8)
9815 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9820 /* Return the register class of a scratch register needed to copy IN into
9821 or out of a register in CLASS in MODE. If it can be done directly,
9822 NO_REGS is returned. */
9825 rs6000_secondary_reload_class (enum reg_class class,
9826 enum machine_mode mode ATTRIBUTE_UNUSED,
9831 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9833 && MACHOPIC_INDIRECT
9837 /* We cannot copy a symbolic operand directly into anything
9838 other than BASE_REGS for TARGET_ELF. So indicate that a
9839 register from BASE_REGS is needed as an intermediate
9842 On Darwin, pic addresses require a load from memory, which
9843 needs a base register. */
9844 if (class != BASE_REGS
9845 && (GET_CODE (in) == SYMBOL_REF
9846 || GET_CODE (in) == HIGH
9847 || GET_CODE (in) == LABEL_REF
9848 || GET_CODE (in) == CONST))
9852 if (GET_CODE (in) == REG)
9855 if (regno >= FIRST_PSEUDO_REGISTER)
9857 regno = true_regnum (in);
9858 if (regno >= FIRST_PSEUDO_REGISTER)
9862 else if (GET_CODE (in) == SUBREG)
9864 regno = true_regnum (in);
9865 if (regno >= FIRST_PSEUDO_REGISTER)
9871 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9873 if (class == GENERAL_REGS || class == BASE_REGS
9874 || (regno >= 0 && INT_REGNO_P (regno)))
9877 /* Constants, memory, and FP registers can go into FP registers. */
9878 if ((regno == -1 || FP_REGNO_P (regno))
9879 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9882 /* Memory, and AltiVec registers can go into AltiVec registers. */
9883 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9884 && class == ALTIVEC_REGS)
9887 /* We can copy among the CR registers. */
9888 if ((class == CR_REGS || class == CR0_REGS)
9889 && regno >= 0 && CR_REGNO_P (regno))
9892 /* Otherwise, we need GENERAL_REGS. */
9893 return GENERAL_REGS;
9896 /* Given a comparison operation, return the bit number in CCR to test. We
9897 know this is a valid comparison.
9899 SCC_P is 1 if this is for an scc. That means that %D will have been
9900 used instead of %C, so the bits will be in different places.
9902 Return -1 if OP isn't a valid comparison for some reason. */
9905 ccr_bit (rtx op, int scc_p)
9907 enum rtx_code code = GET_CODE (op);
9908 enum machine_mode cc_mode;
9913 if (!COMPARISON_P (op))
9918 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9920 cc_mode = GET_MODE (reg);
9921 cc_regnum = REGNO (reg);
9922 base_bit = 4 * (cc_regnum - CR0_REGNO);
9924 validate_condition_mode (code, cc_mode);
9926 /* When generating a sCOND operation, only positive conditions are
9929 || code == EQ || code == GT || code == LT || code == UNORDERED
9930 || code == GTU || code == LTU);
9935 return scc_p ? base_bit + 3 : base_bit + 2;
9937 return base_bit + 2;
9938 case GT: case GTU: case UNLE:
9939 return base_bit + 1;
9940 case LT: case LTU: case UNGE:
9942 case ORDERED: case UNORDERED:
9943 return base_bit + 3;
9946 /* If scc, we will have done a cror to put the bit in the
9947 unordered position. So test that bit. For integer, this is ! LT
9948 unless this is an scc insn. */
9949 return scc_p ? base_bit + 3 : base_bit;
9952 return scc_p ? base_bit + 3 : base_bit + 1;
9959 /* Return the GOT register. */
9962 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9964 /* The second flow pass currently (June 1999) can't update
9965 regs_ever_live without disturbing other parts of the compiler, so
9966 update it here to make the prolog/epilogue code happy. */
9967 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9968 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9970 current_function_uses_pic_offset_table = 1;
9972 return pic_offset_table_rtx;
9975 /* Function to init struct machine_function.
9976 This will be called, via a pointer variable,
9977 from push_function_context. */
9979 static struct machine_function *
9980 rs6000_init_machine_status (void)
9982 return ggc_alloc_cleared (sizeof (machine_function));
9985 /* These macros test for integers and extract the low-order bits. */
9987 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9988 && GET_MODE (X) == VOIDmode)
9990 #define INT_LOWPART(X) \
9991 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9997 unsigned long val = INT_LOWPART (op);
9999 /* If the high bit is zero, the value is the first 1 bit we find
10001 if ((val & 0x80000000) == 0)
10003 gcc_assert (val & 0xffffffff);
10006 while (((val <<= 1) & 0x80000000) == 0)
10011 /* If the high bit is set and the low bit is not, or the mask is all
10012 1's, the value is zero. */
10013 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10016 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10019 while (((val >>= 1) & 1) != 0)
10026 extract_ME (rtx op)
10029 unsigned long val = INT_LOWPART (op);
10031 /* If the low bit is zero, the value is the first 1 bit we find from
10033 if ((val & 1) == 0)
10035 gcc_assert (val & 0xffffffff);
10038 while (((val >>= 1) & 1) == 0)
10044 /* If the low bit is set and the high bit is not, or the mask is all
10045 1's, the value is 31. */
10046 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10049 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10052 while (((val <<= 1) & 0x80000000) != 0)
10058 /* Locate some local-dynamic symbol still in use by this function
10059 so that we can print its name in some tls_ld pattern. */
10061 static const char *
10062 rs6000_get_some_local_dynamic_name (void)
10066 if (cfun->machine->some_ld_name)
10067 return cfun->machine->some_ld_name;
10069 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10071 && for_each_rtx (&PATTERN (insn),
10072 rs6000_get_some_local_dynamic_name_1, 0))
10073 return cfun->machine->some_ld_name;
10075 gcc_unreachable ();
10078 /* Helper function for rs6000_get_some_local_dynamic_name. */
10081 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10085 if (GET_CODE (x) == SYMBOL_REF)
10087 const char *str = XSTR (x, 0);
10088 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10090 cfun->machine->some_ld_name = str;
10098 /* Write out a function code label. */
10101 rs6000_output_function_entry (FILE *file, const char *fname)
10103 if (fname[0] != '.')
10105 switch (DEFAULT_ABI)
10108 gcc_unreachable ();
10114 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10123 RS6000_OUTPUT_BASENAME (file, fname);
10125 assemble_name (file, fname);
10128 /* Print an operand. Recognize special options, documented below. */
10131 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10132 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10134 #define SMALL_DATA_RELOC "sda21"
10135 #define SMALL_DATA_REG 0
10139 print_operand (FILE *file, rtx x, int code)
10143 unsigned HOST_WIDE_INT uval;
10148 /* Write out an instruction after the call which may be replaced
10149 with glue code by the loader. This depends on the AIX version. */
10150 asm_fprintf (file, RS6000_CALL_GLUE);
10153 /* %a is output_address. */
10156 /* If X is a constant integer whose low-order 5 bits are zero,
10157 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10158 in the AIX assembler where "sri" with a zero shift count
10159 writes a trash instruction. */
10160 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10167 /* If constant, low-order 16 bits of constant, unsigned.
10168 Otherwise, write normally. */
10170 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10172 print_operand (file, x, 0);
10176 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10177 for 64-bit mask direction. */
10178 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10181 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10185 /* X is a CR register. Print the number of the GT bit of the CR. */
10186 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10187 output_operand_lossage ("invalid %%E value");
10189 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10193 /* Like 'J' but get to the EQ bit. */
10194 gcc_assert (GET_CODE (x) == REG);
10196 /* Bit 1 is EQ bit. */
10197 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10199 fprintf (file, "%d", i);
10203 /* X is a CR register. Print the number of the EQ bit of the CR */
10204 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10205 output_operand_lossage ("invalid %%E value");
10207 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10211 /* X is a CR register. Print the shift count needed to move it
10212 to the high-order four bits. */
10213 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10214 output_operand_lossage ("invalid %%f value");
10216 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10220 /* Similar, but print the count for the rotate in the opposite
10222 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10223 output_operand_lossage ("invalid %%F value");
10225 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10229 /* X is a constant integer. If it is negative, print "m",
10230 otherwise print "z". This is to make an aze or ame insn. */
10231 if (GET_CODE (x) != CONST_INT)
10232 output_operand_lossage ("invalid %%G value");
10233 else if (INTVAL (x) >= 0)
10240 /* If constant, output low-order five bits. Otherwise, write
10243 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10245 print_operand (file, x, 0);
10249 /* If constant, output low-order six bits. Otherwise, write
10252 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10254 print_operand (file, x, 0);
10258 /* Print `i' if this is a constant, else nothing. */
10264 /* Write the bit number in CCR for jump. */
10265 i = ccr_bit (x, 0);
10267 output_operand_lossage ("invalid %%j code");
10269 fprintf (file, "%d", i);
10273 /* Similar, but add one for shift count in rlinm for scc and pass
10274 scc flag to `ccr_bit'. */
10275 i = ccr_bit (x, 1);
10277 output_operand_lossage ("invalid %%J code");
10279 /* If we want bit 31, write a shift count of zero, not 32. */
10280 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10284 /* X must be a constant. Write the 1's complement of the
10287 output_operand_lossage ("invalid %%k value");
10289 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10293 /* X must be a symbolic constant on ELF. Write an
10294 expression suitable for an 'addi' that adds in the low 16
10295 bits of the MEM. */
10296 if (GET_CODE (x) != CONST)
10298 print_operand_address (file, x);
10299 fputs ("@l", file);
10303 if (GET_CODE (XEXP (x, 0)) != PLUS
10304 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10305 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10306 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10307 output_operand_lossage ("invalid %%K value");
10308 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10309 fputs ("@l", file);
10310 /* For GNU as, there must be a non-alphanumeric character
10311 between 'l' and the number. The '-' is added by
10312 print_operand() already. */
10313 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10315 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10319 /* %l is output_asm_label. */
10322 /* Write second word of DImode or DFmode reference. Works on register
10323 or non-indexed memory only. */
10324 if (GET_CODE (x) == REG)
10325 fputs (reg_names[REGNO (x) + 1], file);
10326 else if (GET_CODE (x) == MEM)
10328 /* Handle possible auto-increment. Since it is pre-increment and
10329 we have already done it, we can just use an offset of word. */
10330 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10331 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10332 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10335 output_address (XEXP (adjust_address_nv (x, SImode,
10339 if (small_data_operand (x, GET_MODE (x)))
10340 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10341 reg_names[SMALL_DATA_REG]);
10346 /* MB value for a mask operand. */
10347 if (! mask_operand (x, SImode))
10348 output_operand_lossage ("invalid %%m value");
10350 fprintf (file, "%d", extract_MB (x));
10354 /* ME value for a mask operand. */
10355 if (! mask_operand (x, SImode))
10356 output_operand_lossage ("invalid %%M value");
10358 fprintf (file, "%d", extract_ME (x));
10361 /* %n outputs the negative of its operand. */
10364 /* Write the number of elements in the vector times 4. */
10365 if (GET_CODE (x) != PARALLEL)
10366 output_operand_lossage ("invalid %%N value");
10368 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10372 /* Similar, but subtract 1 first. */
10373 if (GET_CODE (x) != PARALLEL)
10374 output_operand_lossage ("invalid %%O value");
10376 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10380 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10382 || INT_LOWPART (x) < 0
10383 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10384 output_operand_lossage ("invalid %%p value");
10386 fprintf (file, "%d", i);
10390 /* The operand must be an indirect memory reference. The result
10391 is the register name. */
10392 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10393 || REGNO (XEXP (x, 0)) >= 32)
10394 output_operand_lossage ("invalid %%P value");
10396 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10400 /* This outputs the logical code corresponding to a boolean
10401 expression. The expression may have one or both operands
10402 negated (if one, only the first one). For condition register
10403 logical operations, it will also treat the negated
10404 CR codes as NOTs, but not handle NOTs of them. */
10406 const char *const *t = 0;
10408 enum rtx_code code = GET_CODE (x);
10409 static const char * const tbl[3][3] = {
10410 { "and", "andc", "nor" },
10411 { "or", "orc", "nand" },
10412 { "xor", "eqv", "xor" } };
10416 else if (code == IOR)
10418 else if (code == XOR)
10421 output_operand_lossage ("invalid %%q value");
10423 if (GET_CODE (XEXP (x, 0)) != NOT)
10427 if (GET_CODE (XEXP (x, 1)) == NOT)
10445 /* X is a CR register. Print the mask for `mtcrf'. */
10446 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10447 output_operand_lossage ("invalid %%R value");
10449 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10453 /* Low 5 bits of 32 - value */
10455 output_operand_lossage ("invalid %%s value");
10457 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10461 /* PowerPC64 mask position. All 0's is excluded.
10462 CONST_INT 32-bit mask is considered sign-extended so any
10463 transition must occur within the CONST_INT, not on the boundary. */
10464 if (! mask64_operand (x, DImode))
10465 output_operand_lossage ("invalid %%S value");
10467 uval = INT_LOWPART (x);
10469 if (uval & 1) /* Clear Left */
10471 #if HOST_BITS_PER_WIDE_INT > 64
10472 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10476 else /* Clear Right */
10479 #if HOST_BITS_PER_WIDE_INT > 64
10480 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10486 gcc_assert (i >= 0);
10487 fprintf (file, "%d", i);
10491 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10492 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10494 /* Bit 3 is OV bit. */
10495 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10497 /* If we want bit 31, write a shift count of zero, not 32. */
10498 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10502 /* Print the symbolic name of a branch target register. */
10503 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10504 && REGNO (x) != COUNT_REGISTER_REGNUM))
10505 output_operand_lossage ("invalid %%T value");
10506 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10507 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10509 fputs ("ctr", file);
10513 /* High-order 16 bits of constant for use in unsigned operand. */
10515 output_operand_lossage ("invalid %%u value");
10517 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10518 (INT_LOWPART (x) >> 16) & 0xffff);
10522 /* High-order 16 bits of constant for use in signed operand. */
10524 output_operand_lossage ("invalid %%v value");
10526 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10527 (INT_LOWPART (x) >> 16) & 0xffff);
10531 /* Print `u' if this has an auto-increment or auto-decrement. */
10532 if (GET_CODE (x) == MEM
10533 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10534 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10539 /* Print the trap code for this operand. */
10540 switch (GET_CODE (x))
10543 fputs ("eq", file); /* 4 */
10546 fputs ("ne", file); /* 24 */
10549 fputs ("lt", file); /* 16 */
10552 fputs ("le", file); /* 20 */
10555 fputs ("gt", file); /* 8 */
10558 fputs ("ge", file); /* 12 */
10561 fputs ("llt", file); /* 2 */
10564 fputs ("lle", file); /* 6 */
10567 fputs ("lgt", file); /* 1 */
10570 fputs ("lge", file); /* 5 */
10573 gcc_unreachable ();
10578 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10581 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10582 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10584 print_operand (file, x, 0);
10588 /* MB value for a PowerPC64 rldic operand. */
10589 val = (GET_CODE (x) == CONST_INT
10590 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10595 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10596 if ((val <<= 1) < 0)
10599 #if HOST_BITS_PER_WIDE_INT == 32
10600 if (GET_CODE (x) == CONST_INT && i >= 0)
10601 i += 32; /* zero-extend high-part was all 0's */
10602 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10604 val = CONST_DOUBLE_LOW (x);
10610 for ( ; i < 64; i++)
10611 if ((val <<= 1) < 0)
10616 fprintf (file, "%d", i + 1);
10620 if (GET_CODE (x) == MEM
10621 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10626 /* Like 'L', for third word of TImode */
10627 if (GET_CODE (x) == REG)
10628 fputs (reg_names[REGNO (x) + 2], file);
10629 else if (GET_CODE (x) == MEM)
10631 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10632 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10633 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10635 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10636 if (small_data_operand (x, GET_MODE (x)))
10637 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10638 reg_names[SMALL_DATA_REG]);
10643 /* X is a SYMBOL_REF. Write out the name preceded by a
10644 period and without any trailing data in brackets. Used for function
10645 names. If we are configured for System V (or the embedded ABI) on
10646 the PowerPC, do not emit the period, since those systems do not use
10647 TOCs and the like. */
10648 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10650 /* Mark the decl as referenced so that cgraph will output the
10652 if (SYMBOL_REF_DECL (x))
10653 mark_decl_referenced (SYMBOL_REF_DECL (x));
10655 /* For macho, check to see if we need a stub. */
10658 const char *name = XSTR (x, 0);
10660 if (MACHOPIC_INDIRECT
10661 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10662 name = machopic_indirection_name (x, /*stub_p=*/true);
10664 assemble_name (file, name);
10666 else if (!DOT_SYMBOLS)
10667 assemble_name (file, XSTR (x, 0));
10669 rs6000_output_function_entry (file, XSTR (x, 0));
10673 /* Like 'L', for last word of TImode. */
10674 if (GET_CODE (x) == REG)
10675 fputs (reg_names[REGNO (x) + 3], file);
10676 else if (GET_CODE (x) == MEM)
10678 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10679 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10680 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10682 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10683 if (small_data_operand (x, GET_MODE (x)))
10684 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10685 reg_names[SMALL_DATA_REG]);
10689 /* Print AltiVec or SPE memory operand. */
10694 gcc_assert (GET_CODE (x) == MEM);
10700 /* Handle [reg]. */
10701 if (GET_CODE (tmp) == REG)
10703 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10706 /* Handle [reg+UIMM]. */
10707 else if (GET_CODE (tmp) == PLUS &&
10708 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10712 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10714 x = INTVAL (XEXP (tmp, 1));
10715 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10719 /* Fall through. Must be [reg+reg]. */
10722 && GET_CODE (tmp) == AND
10723 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10724 && INTVAL (XEXP (tmp, 1)) == -16)
10725 tmp = XEXP (tmp, 0);
10726 if (GET_CODE (tmp) == REG)
10727 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10730 gcc_assert (GET_CODE (tmp) == PLUS
10731 && REG_P (XEXP (tmp, 0))
10732 && REG_P (XEXP (tmp, 1)));
10734 if (REGNO (XEXP (tmp, 0)) == 0)
10735 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10736 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10738 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10739 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10745 if (GET_CODE (x) == REG)
10746 fprintf (file, "%s", reg_names[REGNO (x)]);
10747 else if (GET_CODE (x) == MEM)
10749 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10750 know the width from the mode. */
10751 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10752 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10753 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10754 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10755 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10756 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10758 output_address (XEXP (x, 0));
10761 output_addr_const (file, x);
10765 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10769 output_operand_lossage ("invalid %%xn code");
10773 /* Print the address of an operand. */
10776 print_operand_address (FILE *file, rtx x)
10778 if (GET_CODE (x) == REG)
10779 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10780 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10781 || GET_CODE (x) == LABEL_REF)
10783 output_addr_const (file, x);
10784 if (small_data_operand (x, GET_MODE (x)))
10785 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10786 reg_names[SMALL_DATA_REG]);
10788 gcc_assert (!TARGET_TOC);
10790 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10792 gcc_assert (REG_P (XEXP (x, 0)));
10793 if (REGNO (XEXP (x, 0)) == 0)
10794 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10795 reg_names[ REGNO (XEXP (x, 0)) ]);
10797 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10798 reg_names[ REGNO (XEXP (x, 1)) ]);
10800 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10801 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10802 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10804 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10805 && CONSTANT_P (XEXP (x, 1)))
10807 output_addr_const (file, XEXP (x, 1));
10808 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10812 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10813 && CONSTANT_P (XEXP (x, 1)))
10815 fprintf (file, "lo16(");
10816 output_addr_const (file, XEXP (x, 1));
10817 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10820 else if (legitimate_constant_pool_address_p (x))
10822 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10824 rtx contains_minus = XEXP (x, 1);
10828 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10829 turn it into (sym) for output_addr_const. */
10830 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10831 contains_minus = XEXP (contains_minus, 0);
10833 minus = XEXP (contains_minus, 0);
10834 symref = XEXP (minus, 0);
10835 XEXP (contains_minus, 0) = symref;
10840 name = XSTR (symref, 0);
10841 newname = alloca (strlen (name) + sizeof ("@toc"));
10842 strcpy (newname, name);
10843 strcat (newname, "@toc");
10844 XSTR (symref, 0) = newname;
10846 output_addr_const (file, XEXP (x, 1));
10848 XSTR (symref, 0) = name;
10849 XEXP (contains_minus, 0) = minus;
10852 output_addr_const (file, XEXP (x, 1));
10854 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10857 gcc_unreachable ();
10860 /* Target hook for assembling integer objects. The PowerPC version has
10861 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10862 is defined. It also needs to handle DI-mode objects on 64-bit
10866 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10868 #ifdef RELOCATABLE_NEEDS_FIXUP
10869 /* Special handling for SI values. */
10870 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10872 static int recurse = 0;
10874 /* For -mrelocatable, we mark all addresses that need to be fixed up
10875 in the .fixup section. */
10876 if (TARGET_RELOCATABLE
10877 && in_section != toc_section
10878 && in_section != text_section
10879 && !unlikely_text_section_p (in_section)
10881 && GET_CODE (x) != CONST_INT
10882 && GET_CODE (x) != CONST_DOUBLE
10888 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10890 ASM_OUTPUT_LABEL (asm_out_file, buf);
10891 fprintf (asm_out_file, "\t.long\t(");
10892 output_addr_const (asm_out_file, x);
10893 fprintf (asm_out_file, ")@fixup\n");
10894 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10895 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10896 fprintf (asm_out_file, "\t.long\t");
10897 assemble_name (asm_out_file, buf);
10898 fprintf (asm_out_file, "\n\t.previous\n");
10902 /* Remove initial .'s to turn a -mcall-aixdesc function
10903 address into the address of the descriptor, not the function
10905 else if (GET_CODE (x) == SYMBOL_REF
10906 && XSTR (x, 0)[0] == '.'
10907 && DEFAULT_ABI == ABI_AIX)
10909 const char *name = XSTR (x, 0);
10910 while (*name == '.')
10913 fprintf (asm_out_file, "\t.long\t%s\n", name);
10917 #endif /* RELOCATABLE_NEEDS_FIXUP */
10918 return default_assemble_integer (x, size, aligned_p);
10921 #ifdef HAVE_GAS_HIDDEN
10922 /* Emit an assembler directive to set symbol visibility for DECL to
10923 VISIBILITY_TYPE. */
10926 rs6000_assemble_visibility (tree decl, int vis)
10928 /* Functions need to have their entry point symbol visibility set as
10929 well as their descriptor symbol visibility. */
10930 if (DEFAULT_ABI == ABI_AIX
10932 && TREE_CODE (decl) == FUNCTION_DECL)
10934 static const char * const visibility_types[] = {
10935 NULL, "internal", "hidden", "protected"
10938 const char *name, *type;
10940 name = ((* targetm.strip_name_encoding)
10941 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10942 type = visibility_types[vis];
10944 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10945 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10948 default_assemble_visibility (decl, vis);
10953 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10955 /* Reversal of FP compares takes care -- an ordered compare
10956 becomes an unordered compare and vice versa. */
10957 if (mode == CCFPmode
10958 && (!flag_finite_math_only
10959 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10960 || code == UNEQ || code == LTGT))
10961 return reverse_condition_maybe_unordered (code);
10963 return reverse_condition (code);
10966 /* Generate a compare for CODE. Return a brand-new rtx that
10967 represents the result of the compare. */
10970 rs6000_generate_compare (enum rtx_code code)
10972 enum machine_mode comp_mode;
10973 rtx compare_result;
10975 if (rs6000_compare_fp_p)
10976 comp_mode = CCFPmode;
10977 else if (code == GTU || code == LTU
10978 || code == GEU || code == LEU)
10979 comp_mode = CCUNSmode;
10980 else if ((code == EQ || code == NE)
10981 && GET_CODE (rs6000_compare_op0) == SUBREG
10982 && GET_CODE (rs6000_compare_op1) == SUBREG
10983 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10984 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10985 /* These are unsigned values, perhaps there will be a later
10986 ordering compare that can be shared with this one.
10987 Unfortunately we cannot detect the signedness of the operands
10988 for non-subregs. */
10989 comp_mode = CCUNSmode;
10991 comp_mode = CCmode;
10993 /* First, the compare. */
10994 compare_result = gen_reg_rtx (comp_mode);
10996 /* SPE FP compare instructions on the GPRs. Yuck! */
10997 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10998 && rs6000_compare_fp_p)
11000 rtx cmp, or_result, compare_result2;
11001 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11003 if (op_mode == VOIDmode)
11004 op_mode = GET_MODE (rs6000_compare_op1);
11006 /* Note: The E500 comparison instructions set the GT bit (x +
11007 1), on success. This explains the mess. */
11011 case EQ: case UNEQ: case NE: case LTGT:
11015 cmp = flag_unsafe_math_optimizations
11016 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11017 rs6000_compare_op1)
11018 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11019 rs6000_compare_op1);
11023 cmp = flag_unsafe_math_optimizations
11024 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11025 rs6000_compare_op1)
11026 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11027 rs6000_compare_op1);
11031 gcc_unreachable ();
11035 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11039 cmp = flag_unsafe_math_optimizations
11040 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11041 rs6000_compare_op1)
11042 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11043 rs6000_compare_op1);
11047 cmp = flag_unsafe_math_optimizations
11048 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11049 rs6000_compare_op1)
11050 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11051 rs6000_compare_op1);
11055 gcc_unreachable ();
11059 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11063 cmp = flag_unsafe_math_optimizations
11064 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11065 rs6000_compare_op1)
11066 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11067 rs6000_compare_op1);
11071 cmp = flag_unsafe_math_optimizations
11072 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11073 rs6000_compare_op1)
11074 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11075 rs6000_compare_op1);
11079 gcc_unreachable ();
11083 gcc_unreachable ();
11086 /* Synthesize LE and GE from LT/GT || EQ. */
11087 if (code == LE || code == GE || code == LEU || code == GEU)
11093 case LE: code = LT; break;
11094 case GE: code = GT; break;
11095 case LEU: code = LT; break;
11096 case GEU: code = GT; break;
11097 default: gcc_unreachable ();
11100 compare_result2 = gen_reg_rtx (CCFPmode);
11106 cmp = flag_unsafe_math_optimizations
11107 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11108 rs6000_compare_op1)
11109 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11110 rs6000_compare_op1);
11114 cmp = flag_unsafe_math_optimizations
11115 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11116 rs6000_compare_op1)
11117 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11118 rs6000_compare_op1);
11122 gcc_unreachable ();
11126 /* OR them together. */
11127 or_result = gen_reg_rtx (CCFPmode);
11128 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11130 compare_result = or_result;
11135 if (code == NE || code == LTGT)
11145 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11146 CLOBBERs to match cmptf_internal2 pattern. */
11147 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11148 && GET_MODE (rs6000_compare_op0) == TFmode
11149 && !TARGET_IEEEQUAD
11150 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11151 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11153 gen_rtx_SET (VOIDmode,
11155 gen_rtx_COMPARE (comp_mode,
11156 rs6000_compare_op0,
11157 rs6000_compare_op1)),
11158 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11159 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11160 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11161 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11162 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11163 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11164 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11165 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11166 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11167 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11169 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11170 comp_mode = CCEQmode;
11171 compare_result = gen_reg_rtx (CCEQmode);
11173 emit_insn (gen_stack_protect_testdi (compare_result,
11174 rs6000_compare_op0, op1));
11176 emit_insn (gen_stack_protect_testsi (compare_result,
11177 rs6000_compare_op0, op1));
11180 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11181 gen_rtx_COMPARE (comp_mode,
11182 rs6000_compare_op0,
11183 rs6000_compare_op1)));
11186 /* Some kinds of FP comparisons need an OR operation;
11187 under flag_finite_math_only we don't bother. */
11188 if (rs6000_compare_fp_p
11189 && !flag_finite_math_only
11190 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11191 && (code == LE || code == GE
11192 || code == UNEQ || code == LTGT
11193 || code == UNGT || code == UNLT))
11195 enum rtx_code or1, or2;
11196 rtx or1_rtx, or2_rtx, compare2_rtx;
11197 rtx or_result = gen_reg_rtx (CCEQmode);
11201 case LE: or1 = LT; or2 = EQ; break;
11202 case GE: or1 = GT; or2 = EQ; break;
11203 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11204 case LTGT: or1 = LT; or2 = GT; break;
11205 case UNGT: or1 = UNORDERED; or2 = GT; break;
11206 case UNLT: or1 = UNORDERED; or2 = LT; break;
11207 default: gcc_unreachable ();
11209 validate_condition_mode (or1, comp_mode);
11210 validate_condition_mode (or2, comp_mode);
11211 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11212 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11213 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11214 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11216 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11218 compare_result = or_result;
11222 validate_condition_mode (code, GET_MODE (compare_result));
11224 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11228 /* Emit the RTL for an sCOND pattern. */
11231 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11234 enum machine_mode op_mode;
11235 enum rtx_code cond_code;
11237 condition_rtx = rs6000_generate_compare (code);
11238 cond_code = GET_CODE (condition_rtx);
11240 if (TARGET_E500 && rs6000_compare_fp_p
11241 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11245 PUT_MODE (condition_rtx, SImode);
11246 t = XEXP (condition_rtx, 0);
11248 gcc_assert (cond_code == NE || cond_code == EQ);
11250 if (cond_code == NE)
11251 emit_insn (gen_e500_flip_gt_bit (t, t));
11253 emit_insn (gen_move_from_CR_gt_bit (result, t));
11257 if (cond_code == NE
11258 || cond_code == GE || cond_code == LE
11259 || cond_code == GEU || cond_code == LEU
11260 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11262 rtx not_result = gen_reg_rtx (CCEQmode);
11263 rtx not_op, rev_cond_rtx;
11264 enum machine_mode cc_mode;
11266 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11268 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11269 SImode, XEXP (condition_rtx, 0), const0_rtx);
11270 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11271 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11272 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11275 op_mode = GET_MODE (rs6000_compare_op0);
11276 if (op_mode == VOIDmode)
11277 op_mode = GET_MODE (rs6000_compare_op1);
11279 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11281 PUT_MODE (condition_rtx, DImode);
11282 convert_move (result, condition_rtx, 0);
11286 PUT_MODE (condition_rtx, SImode);
11287 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11291 /* Emit a branch of kind CODE to location LOC. */
11294 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11296 rtx condition_rtx, loc_ref;
11298 condition_rtx = rs6000_generate_compare (code);
11299 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11300 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11301 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11302 loc_ref, pc_rtx)));
11305 /* Return the string to output a conditional branch to LABEL, which is
11306 the operand number of the label, or -1 if the branch is really a
11307 conditional return.
11309 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11310 condition code register and its mode specifies what kind of
11311 comparison we made.
11313 REVERSED is nonzero if we should reverse the sense of the comparison.
11315 INSN is the insn. */
11318 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11320 static char string[64];
11321 enum rtx_code code = GET_CODE (op);
11322 rtx cc_reg = XEXP (op, 0);
11323 enum machine_mode mode = GET_MODE (cc_reg);
11324 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11325 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11326 int really_reversed = reversed ^ need_longbranch;
11332 validate_condition_mode (code, mode);
11334 /* Work out which way this really branches. We could use
11335 reverse_condition_maybe_unordered here always but this
11336 makes the resulting assembler clearer. */
11337 if (really_reversed)
11339 /* Reversal of FP compares takes care -- an ordered compare
11340 becomes an unordered compare and vice versa. */
11341 if (mode == CCFPmode)
11342 code = reverse_condition_maybe_unordered (code);
11344 code = reverse_condition (code);
11347 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11349 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11354 /* Opposite of GT. */
11363 gcc_unreachable ();
11369 /* Not all of these are actually distinct opcodes, but
11370 we distinguish them for clarity of the resulting assembler. */
11371 case NE: case LTGT:
11372 ccode = "ne"; break;
11373 case EQ: case UNEQ:
11374 ccode = "eq"; break;
11376 ccode = "ge"; break;
11377 case GT: case GTU: case UNGT:
11378 ccode = "gt"; break;
11380 ccode = "le"; break;
11381 case LT: case LTU: case UNLT:
11382 ccode = "lt"; break;
11383 case UNORDERED: ccode = "un"; break;
11384 case ORDERED: ccode = "nu"; break;
11385 case UNGE: ccode = "nl"; break;
11386 case UNLE: ccode = "ng"; break;
11388 gcc_unreachable ();
11391 /* Maybe we have a guess as to how likely the branch is.
11392 The old mnemonics don't have a way to specify this information. */
11394 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11395 if (note != NULL_RTX)
11397 /* PROB is the difference from 50%. */
11398 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11400 /* Only hint for highly probable/improbable branches on newer
11401 cpus as static prediction overrides processor dynamic
11402 prediction. For older cpus we may as well always hint, but
11403 assume not taken for branches that are very close to 50% as a
11404 mispredicted taken branch is more expensive than a
11405 mispredicted not-taken branch. */
11406 if (rs6000_always_hint
11407 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11409 if (abs (prob) > REG_BR_PROB_BASE / 20
11410 && ((prob > 0) ^ need_longbranch))
11418 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11420 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11422 /* We need to escape any '%' characters in the reg_names string.
11423 Assume they'd only be the first character.... */
11424 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11426 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11430 /* If the branch distance was too far, we may have to use an
11431 unconditional branch to go the distance. */
11432 if (need_longbranch)
11433 s += sprintf (s, ",$+8\n\tb %s", label);
11435 s += sprintf (s, ",%s", label);
11441 /* Return the string to flip the GT bit on a CR. */
11443 output_e500_flip_gt_bit (rtx dst, rtx src)
11445 static char string[64];
11448 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11449 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11452 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11453 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11455 sprintf (string, "crnot %d,%d", a, b);
11459 /* Return insn index for the vector compare instruction for given CODE,
11460 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11464 get_vec_cmp_insn (enum rtx_code code,
11465 enum machine_mode dest_mode,
11466 enum machine_mode op_mode)
11468 if (!TARGET_ALTIVEC)
11469 return INSN_NOT_AVAILABLE;
11474 if (dest_mode == V16QImode && op_mode == V16QImode)
11475 return UNSPEC_VCMPEQUB;
11476 if (dest_mode == V8HImode && op_mode == V8HImode)
11477 return UNSPEC_VCMPEQUH;
11478 if (dest_mode == V4SImode && op_mode == V4SImode)
11479 return UNSPEC_VCMPEQUW;
11480 if (dest_mode == V4SImode && op_mode == V4SFmode)
11481 return UNSPEC_VCMPEQFP;
11484 if (dest_mode == V4SImode && op_mode == V4SFmode)
11485 return UNSPEC_VCMPGEFP;
11487 if (dest_mode == V16QImode && op_mode == V16QImode)
11488 return UNSPEC_VCMPGTSB;
11489 if (dest_mode == V8HImode && op_mode == V8HImode)
11490 return UNSPEC_VCMPGTSH;
11491 if (dest_mode == V4SImode && op_mode == V4SImode)
11492 return UNSPEC_VCMPGTSW;
11493 if (dest_mode == V4SImode && op_mode == V4SFmode)
11494 return UNSPEC_VCMPGTFP;
11497 if (dest_mode == V16QImode && op_mode == V16QImode)
11498 return UNSPEC_VCMPGTUB;
11499 if (dest_mode == V8HImode && op_mode == V8HImode)
11500 return UNSPEC_VCMPGTUH;
11501 if (dest_mode == V4SImode && op_mode == V4SImode)
11502 return UNSPEC_VCMPGTUW;
11507 return INSN_NOT_AVAILABLE;
11510 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11511 DMODE is expected destination mode. This is a recursive function. */
11514 rs6000_emit_vector_compare (enum rtx_code rcode,
11516 enum machine_mode dmode)
11520 enum machine_mode dest_mode;
11521 enum machine_mode op_mode = GET_MODE (op1);
11523 gcc_assert (TARGET_ALTIVEC);
11524 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11526 /* Floating point vector compare instructions uses destination V4SImode.
11527 Move destination to appropriate mode later. */
11528 if (dmode == V4SFmode)
11529 dest_mode = V4SImode;
11533 mask = gen_reg_rtx (dest_mode);
11534 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11536 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11538 bool swap_operands = false;
11539 bool try_again = false;
11544 swap_operands = true;
11549 swap_operands = true;
11553 /* Treat A != B as ~(A==B). */
11555 enum insn_code nor_code;
11556 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11559 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11560 gcc_assert (nor_code != CODE_FOR_nothing);
11561 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11563 if (dmode != dest_mode)
11565 rtx temp = gen_reg_rtx (dest_mode);
11566 convert_move (temp, mask, 0);
11576 /* Try GT/GTU/LT/LTU OR EQ */
11579 enum insn_code ior_code;
11580 enum rtx_code new_code;
11601 gcc_unreachable ();
11604 c_rtx = rs6000_emit_vector_compare (new_code,
11605 op0, op1, dest_mode);
11606 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11609 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11610 gcc_assert (ior_code != CODE_FOR_nothing);
11611 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11612 if (dmode != dest_mode)
11614 rtx temp = gen_reg_rtx (dest_mode);
11615 convert_move (temp, mask, 0);
11622 gcc_unreachable ();
11627 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11628 /* You only get two chances. */
11629 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11641 emit_insn (gen_rtx_SET (VOIDmode, mask,
11642 gen_rtx_UNSPEC (dest_mode,
11643 gen_rtvec (2, op0, op1),
11645 if (dmode != dest_mode)
11647 rtx temp = gen_reg_rtx (dest_mode);
11648 convert_move (temp, mask, 0);
11654 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11655 valid insn doesn exist for given mode. */
11658 get_vsel_insn (enum machine_mode mode)
11663 return UNSPEC_VSEL4SI;
11666 return UNSPEC_VSEL4SF;
11669 return UNSPEC_VSEL8HI;
11672 return UNSPEC_VSEL16QI;
11675 return INSN_NOT_AVAILABLE;
11678 return INSN_NOT_AVAILABLE;
11681 /* Emit vector select insn where DEST is destination using
11682 operands OP1, OP2 and MASK. */
11685 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11688 enum machine_mode dest_mode = GET_MODE (dest);
11689 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11691 temp = gen_reg_rtx (dest_mode);
11693 /* For each vector element, select op1 when mask is 1 otherwise
11695 t = gen_rtx_SET (VOIDmode, temp,
11696 gen_rtx_UNSPEC (dest_mode,
11697 gen_rtvec (3, op2, op1, mask),
11700 emit_move_insn (dest, temp);
11704 /* Emit vector conditional expression.
11705 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11706 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11709 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11710 rtx cond, rtx cc_op0, rtx cc_op1)
11712 enum machine_mode dest_mode = GET_MODE (dest);
11713 enum rtx_code rcode = GET_CODE (cond);
11716 if (!TARGET_ALTIVEC)
11719 /* Get the vector mask for the given relational operations. */
11720 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11722 rs6000_emit_vector_select (dest, op1, op2, mask);
11727 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11728 operands of the last comparison is nonzero/true, FALSE_COND if it
11729 is zero/false. Return 0 if the hardware has no such operation. */
11732 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11734 enum rtx_code code = GET_CODE (op);
11735 rtx op0 = rs6000_compare_op0;
11736 rtx op1 = rs6000_compare_op1;
11737 REAL_VALUE_TYPE c1;
11738 enum machine_mode compare_mode = GET_MODE (op0);
11739 enum machine_mode result_mode = GET_MODE (dest);
11741 bool is_against_zero;
11743 /* These modes should always match. */
11744 if (GET_MODE (op1) != compare_mode
11745 /* In the isel case however, we can use a compare immediate, so
11746 op1 may be a small constant. */
11747 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11749 if (GET_MODE (true_cond) != result_mode)
11751 if (GET_MODE (false_cond) != result_mode)
11754 /* First, work out if the hardware can do this at all, or
11755 if it's too slow.... */
11756 if (! rs6000_compare_fp_p)
11759 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11762 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11763 && SCALAR_FLOAT_MODE_P (compare_mode))
11766 is_against_zero = op1 == CONST0_RTX (compare_mode);
11768 /* A floating-point subtract might overflow, underflow, or produce
11769 an inexact result, thus changing the floating-point flags, so it
11770 can't be generated if we care about that. It's safe if one side
11771 of the construct is zero, since then no subtract will be
11773 if (SCALAR_FLOAT_MODE_P (compare_mode)
11774 && flag_trapping_math && ! is_against_zero)
11777 /* Eliminate half of the comparisons by switching operands, this
11778 makes the remaining code simpler. */
11779 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11780 || code == LTGT || code == LT || code == UNLE)
11782 code = reverse_condition_maybe_unordered (code);
11784 true_cond = false_cond;
11788 /* UNEQ and LTGT take four instructions for a comparison with zero,
11789 it'll probably be faster to use a branch here too. */
11790 if (code == UNEQ && HONOR_NANS (compare_mode))
11793 if (GET_CODE (op1) == CONST_DOUBLE)
11794 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11796 /* We're going to try to implement comparisons by performing
11797 a subtract, then comparing against zero. Unfortunately,
11798 Inf - Inf is NaN which is not zero, and so if we don't
11799 know that the operand is finite and the comparison
11800 would treat EQ different to UNORDERED, we can't do it. */
11801 if (HONOR_INFINITIES (compare_mode)
11802 && code != GT && code != UNGE
11803 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11804 /* Constructs of the form (a OP b ? a : b) are safe. */
11805 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11806 || (! rtx_equal_p (op0, true_cond)
11807 && ! rtx_equal_p (op1, true_cond))))
11810 /* At this point we know we can use fsel. */
11812 /* Reduce the comparison to a comparison against zero. */
11813 if (! is_against_zero)
11815 temp = gen_reg_rtx (compare_mode);
11816 emit_insn (gen_rtx_SET (VOIDmode, temp,
11817 gen_rtx_MINUS (compare_mode, op0, op1)));
11819 op1 = CONST0_RTX (compare_mode);
11822 /* If we don't care about NaNs we can reduce some of the comparisons
11823 down to faster ones. */
11824 if (! HONOR_NANS (compare_mode))
11830 true_cond = false_cond;
11843 /* Now, reduce everything down to a GE. */
11850 temp = gen_reg_rtx (compare_mode);
11851 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11856 temp = gen_reg_rtx (compare_mode);
11857 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11862 temp = gen_reg_rtx (compare_mode);
11863 emit_insn (gen_rtx_SET (VOIDmode, temp,
11864 gen_rtx_NEG (compare_mode,
11865 gen_rtx_ABS (compare_mode, op0))));
11870 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11871 temp = gen_reg_rtx (result_mode);
11872 emit_insn (gen_rtx_SET (VOIDmode, temp,
11873 gen_rtx_IF_THEN_ELSE (result_mode,
11874 gen_rtx_GE (VOIDmode,
11876 true_cond, false_cond)));
11877 false_cond = true_cond;
11880 temp = gen_reg_rtx (compare_mode);
11881 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11886 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11887 temp = gen_reg_rtx (result_mode);
11888 emit_insn (gen_rtx_SET (VOIDmode, temp,
11889 gen_rtx_IF_THEN_ELSE (result_mode,
11890 gen_rtx_GE (VOIDmode,
11892 true_cond, false_cond)));
11893 true_cond = false_cond;
11896 temp = gen_reg_rtx (compare_mode);
11897 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11902 gcc_unreachable ();
11905 emit_insn (gen_rtx_SET (VOIDmode, dest,
11906 gen_rtx_IF_THEN_ELSE (result_mode,
11907 gen_rtx_GE (VOIDmode,
11909 true_cond, false_cond)));
11913 /* Same as above, but for ints (isel). */
11916 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11918 rtx condition_rtx, cr;
11920 /* All isel implementations thus far are 32-bits. */
11921 if (GET_MODE (rs6000_compare_op0) != SImode)
11924 /* We still have to do the compare, because isel doesn't do a
11925 compare, it just looks at the CRx bits set by a previous compare
11927 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11928 cr = XEXP (condition_rtx, 0);
11930 if (GET_MODE (cr) == CCmode)
11931 emit_insn (gen_isel_signed (dest, condition_rtx,
11932 true_cond, false_cond, cr));
11934 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11935 true_cond, false_cond, cr));
11941 output_isel (rtx *operands)
11943 enum rtx_code code;
11945 code = GET_CODE (operands[1]);
11946 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11948 PUT_CODE (operands[1], reverse_condition (code));
11949 return "isel %0,%3,%2,%j1";
11952 return "isel %0,%2,%3,%j1";
11956 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11958 enum machine_mode mode = GET_MODE (op0);
11962 if (code == SMAX || code == SMIN)
11967 if (code == SMAX || code == UMAX)
11968 target = emit_conditional_move (dest, c, op0, op1, mode,
11969 op0, op1, mode, 0);
11971 target = emit_conditional_move (dest, c, op0, op1, mode,
11972 op1, op0, mode, 0);
11973 gcc_assert (target);
11974 if (target != dest)
11975 emit_move_insn (dest, target);
11978 /* Emit instructions to perform a load-reserved/store-conditional operation.
11979 The operation performed is an atomic
11980 (set M (CODE:MODE M OP))
11981 If not NULL, BEFORE is atomically set to M before the operation, and
11982 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11983 If SYNC_P then a memory barrier is emitted before the operation.
11984 Either OP or M may be wrapped in a NOT operation. */
11987 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11988 rtx m, rtx op, rtx before_param, rtx after_param,
11991 enum machine_mode used_mode;
11992 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11995 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11996 rtx shift = NULL_RTX;
11999 emit_insn (gen_memory_barrier ());
12001 if (GET_CODE (m) == NOT)
12002 used_m = XEXP (m, 0);
12006 /* If this is smaller than SImode, we'll have to use SImode with
12008 if (mode == QImode || mode == HImode)
12012 if (MEM_ALIGN (used_m) >= 32)
12015 if (BYTES_BIG_ENDIAN)
12016 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12018 shift = GEN_INT (ishift);
12022 rtx addrSI, aligned_addr;
12023 int shift_mask = mode == QImode ? 0x18 : 0x10;
12025 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12026 XEXP (used_m, 0)));
12027 shift = gen_reg_rtx (SImode);
12029 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12030 GEN_INT (shift_mask)));
12031 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12033 aligned_addr = expand_binop (Pmode, and_optab,
12035 GEN_INT (-4), NULL_RTX,
12036 1, OPTAB_LIB_WIDEN);
12037 used_m = change_address (used_m, SImode, aligned_addr);
12038 set_mem_align (used_m, 32);
12039 /* It's safe to keep the old alias set of USED_M, because
12040 the operation is atomic and only affects the original
12042 if (GET_CODE (m) == NOT)
12043 m = gen_rtx_NOT (SImode, used_m);
12048 if (GET_CODE (op) == NOT)
12050 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12051 oldop = gen_rtx_NOT (SImode, oldop);
12054 oldop = lowpart_subreg (SImode, op, mode);
12060 newop = expand_binop (SImode, and_optab,
12061 oldop, GEN_INT (imask), NULL_RTX,
12062 1, OPTAB_LIB_WIDEN);
12063 emit_insn (gen_ashlsi3 (newop, newop, shift));
12067 newop = expand_binop (SImode, ior_optab,
12068 oldop, GEN_INT (~imask), NULL_RTX,
12069 1, OPTAB_LIB_WIDEN);
12070 emit_insn (gen_rotlsi3 (newop, newop, shift));
12078 newop = expand_binop (SImode, and_optab,
12079 oldop, GEN_INT (imask), NULL_RTX,
12080 1, OPTAB_LIB_WIDEN);
12081 emit_insn (gen_ashlsi3 (newop, newop, shift));
12083 mask = gen_reg_rtx (SImode);
12084 emit_move_insn (mask, GEN_INT (imask));
12085 emit_insn (gen_ashlsi3 (mask, mask, shift));
12088 newop = gen_rtx_PLUS (SImode, m, newop);
12090 newop = gen_rtx_MINUS (SImode, m, newop);
12091 newop = gen_rtx_AND (SImode, newop, mask);
12092 newop = gen_rtx_IOR (SImode, newop,
12093 gen_rtx_AND (SImode,
12094 gen_rtx_NOT (SImode, mask),
12100 gcc_unreachable ();
12103 if (GET_CODE (m) == NOT)
12107 mask = gen_reg_rtx (SImode);
12108 emit_move_insn (mask, GEN_INT (imask));
12109 emit_insn (gen_ashlsi3 (mask, mask, shift));
12111 xorm = gen_rtx_XOR (SImode, used_m, mask);
12112 /* Depending on the value of 'op', the XOR or the operation might
12113 be able to be simplified away. */
12114 newop = simplify_gen_binary (code, SImode, xorm, newop);
12117 used_mode = SImode;
12118 before = gen_reg_rtx (used_mode);
12119 after = gen_reg_rtx (used_mode);
12124 before = before_param;
12125 after = after_param;
12127 if (before == NULL_RTX)
12128 before = gen_reg_rtx (used_mode);
12129 if (after == NULL_RTX)
12130 after = gen_reg_rtx (used_mode);
12133 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12134 && used_mode != mode)
12135 the_op = op; /* Computed above. */
12136 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12137 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12139 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12141 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12142 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12143 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12144 gen_rtx_UNSPEC (used_mode,
12145 gen_rtvec (1, the_op),
12147 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12149 if ((code == PLUS || code == MINUS) && used_mode != mode)
12150 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12151 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12153 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12154 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12156 /* Shift and mask the return values properly. */
12157 if (used_mode != mode && before_param)
12159 emit_insn (gen_lshrsi3 (before, before, shift));
12160 convert_move (before_param, before, 1);
12163 if (used_mode != mode && after_param)
12165 emit_insn (gen_lshrsi3 (after, after, shift));
12166 convert_move (after_param, after, 1);
12169 /* The previous sequence will end with a branch that's dependent on
12170 the conditional store, so placing an isync will ensure that no
12171 other instructions (especially, no load or store instructions)
12172 can start before the atomic operation completes. */
12174 emit_insn (gen_isync ());
12177 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12178 COND is true. Mark the jump as unlikely to be taken. */
12181 emit_unlikely_jump (rtx cond, rtx label)
12183 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12186 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12187 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12188 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12191 /* A subroutine of the atomic operation splitters. Emit a load-locked
12192 instruction in MODE. */
12195 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12197 rtx (*fn) (rtx, rtx) = NULL;
12198 if (mode == SImode)
12199 fn = gen_load_locked_si;
12200 else if (mode == DImode)
12201 fn = gen_load_locked_di;
12202 emit_insn (fn (reg, mem));
12205 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12206 instruction in MODE. */
12209 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12211 rtx (*fn) (rtx, rtx, rtx) = NULL;
12212 if (mode == SImode)
12213 fn = gen_store_conditional_si;
12214 else if (mode == DImode)
12215 fn = gen_store_conditional_di;
12217 /* Emit sync before stwcx. to address PPC405 Erratum. */
12218 if (PPC405_ERRATUM77)
12219 emit_insn (gen_memory_barrier ());
12221 emit_insn (fn (res, mem, val));
12224 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12225 to perform. MEM is the memory on which to operate. VAL is the second
12226 operand of the binary operator. BEFORE and AFTER are optional locations to
12227 return the value of MEM either before of after the operation. SCRATCH is
12228 a scratch register. */
12231 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12232 rtx before, rtx after, rtx scratch)
12234 enum machine_mode mode = GET_MODE (mem);
12235 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12237 emit_insn (gen_memory_barrier ());
12239 label = gen_label_rtx ();
12240 emit_label (label);
12241 label = gen_rtx_LABEL_REF (VOIDmode, label);
12243 if (before == NULL_RTX)
12245 emit_load_locked (mode, before, mem);
12248 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12249 else if (code == AND)
12250 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12252 x = gen_rtx_fmt_ee (code, mode, before, val);
12254 if (after != NULL_RTX)
12255 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12256 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12258 emit_store_conditional (mode, cond, mem, scratch);
12260 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12261 emit_unlikely_jump (x, label);
12263 emit_insn (gen_isync ());
12266 /* Expand an atomic compare and swap operation. MEM is the memory on which
12267 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12268 value to be stored. SCRATCH is a scratch GPR. */
12271 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12274 enum machine_mode mode = GET_MODE (mem);
12275 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12277 emit_insn (gen_memory_barrier ());
12279 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12280 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12281 emit_label (XEXP (label1, 0));
12283 emit_load_locked (mode, retval, mem);
12285 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12286 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12288 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12289 emit_unlikely_jump (x, label2);
12291 emit_move_insn (scratch, newval);
12292 emit_store_conditional (mode, cond, mem, scratch);
12294 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12295 emit_unlikely_jump (x, label1);
12297 emit_insn (gen_isync ());
12298 emit_label (XEXP (label2, 0));
12301 /* Expand an atomic test and set operation. MEM is the memory on which
12302 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12305 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12307 enum machine_mode mode = GET_MODE (mem);
12308 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12310 emit_insn (gen_memory_barrier ());
12312 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12313 emit_label (XEXP (label, 0));
12315 emit_load_locked (mode, retval, mem);
12316 emit_move_insn (scratch, val);
12317 emit_store_conditional (mode, cond, mem, scratch);
12319 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12320 emit_unlikely_jump (x, label);
12322 emit_insn (gen_isync ());
12326 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12328 enum machine_mode mode = GET_MODE (mem);
12329 rtx addrSI, align, wdst, shift, mask;
12330 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12331 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12333 /* Shift amount for subword relative to aligned word. */
12334 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12335 shift = gen_reg_rtx (SImode);
12336 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12337 GEN_INT (shift_mask)));
12338 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12340 /* Shift and mask old value into position within word. */
12341 oldval = convert_modes (SImode, mode, oldval, 1);
12342 oldval = expand_binop (SImode, and_optab,
12343 oldval, GEN_INT (imask), NULL_RTX,
12344 1, OPTAB_LIB_WIDEN);
12345 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12347 /* Shift and mask new value into position within word. */
12348 newval = convert_modes (SImode, mode, newval, 1);
12349 newval = expand_binop (SImode, and_optab,
12350 newval, GEN_INT (imask), NULL_RTX,
12351 1, OPTAB_LIB_WIDEN);
12352 emit_insn (gen_ashlsi3 (newval, newval, shift));
12354 /* Mask for insertion. */
12355 mask = gen_reg_rtx (SImode);
12356 emit_move_insn (mask, GEN_INT (imask));
12357 emit_insn (gen_ashlsi3 (mask, mask, shift));
12359 /* Address of aligned word containing subword. */
12360 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12361 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12362 mem = change_address (mem, SImode, align);
12363 set_mem_align (mem, 32);
12364 MEM_VOLATILE_P (mem) = 1;
12366 wdst = gen_reg_rtx (SImode);
12367 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12368 oldval, newval, mem));
12370 emit_move_insn (dst, gen_lowpart (mode, wdst));
12374 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12375 rtx oldval, rtx newval, rtx mem,
12378 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12380 emit_insn (gen_memory_barrier ());
12381 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12382 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12383 emit_label (XEXP (label1, 0));
12385 emit_load_locked (SImode, scratch, mem);
12387 /* Mask subword within loaded value for comparison with oldval.
12388 Use UNSPEC_AND to avoid clobber.*/
12389 emit_insn (gen_rtx_SET (SImode, dest,
12390 gen_rtx_UNSPEC (SImode,
12391 gen_rtvec (2, scratch, mask),
12394 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12395 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12397 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12398 emit_unlikely_jump (x, label2);
12400 /* Clear subword within loaded value for insertion of new value. */
12401 emit_insn (gen_rtx_SET (SImode, scratch,
12402 gen_rtx_AND (SImode,
12403 gen_rtx_NOT (SImode, mask), scratch)));
12404 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12405 emit_store_conditional (SImode, cond, mem, scratch);
12407 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12408 emit_unlikely_jump (x, label1);
12410 emit_insn (gen_isync ());
12411 emit_label (XEXP (label2, 0));
12415 /* Emit instructions to move SRC to DST. Called by splitters for
12416 multi-register moves. It will emit at most one instruction for
12417 each register that is accessed; that is, it won't emit li/lis pairs
12418 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12422 rs6000_split_multireg_move (rtx dst, rtx src)
12424 /* The register number of the first register being moved. */
12426 /* The mode that is to be moved. */
12427 enum machine_mode mode;
12428 /* The mode that the move is being done in, and its size. */
12429 enum machine_mode reg_mode;
12431 /* The number of registers that will be moved. */
12434 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12435 mode = GET_MODE (dst);
12436 nregs = hard_regno_nregs[reg][mode];
12437 if (FP_REGNO_P (reg))
12439 else if (ALTIVEC_REGNO_P (reg))
12440 reg_mode = V16QImode;
12442 reg_mode = word_mode;
12443 reg_mode_size = GET_MODE_SIZE (reg_mode);
12445 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12447 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12449 /* Move register range backwards, if we might have destructive
12452 for (i = nregs - 1; i >= 0; i--)
12453 emit_insn (gen_rtx_SET (VOIDmode,
12454 simplify_gen_subreg (reg_mode, dst, mode,
12455 i * reg_mode_size),
12456 simplify_gen_subreg (reg_mode, src, mode,
12457 i * reg_mode_size)));
12463 bool used_update = false;
12465 if (MEM_P (src) && INT_REGNO_P (reg))
12469 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12470 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12473 breg = XEXP (XEXP (src, 0), 0);
12474 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12475 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12476 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12477 emit_insn (TARGET_32BIT
12478 ? gen_addsi3 (breg, breg, delta_rtx)
12479 : gen_adddi3 (breg, breg, delta_rtx));
12480 src = replace_equiv_address (src, breg);
12482 else if (! offsettable_memref_p (src))
12485 basereg = gen_rtx_REG (Pmode, reg);
12486 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12487 src = replace_equiv_address (src, basereg);
12490 breg = XEXP (src, 0);
12491 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12492 breg = XEXP (breg, 0);
12494 /* If the base register we are using to address memory is
12495 also a destination reg, then change that register last. */
12497 && REGNO (breg) >= REGNO (dst)
12498 && REGNO (breg) < REGNO (dst) + nregs)
12499 j = REGNO (breg) - REGNO (dst);
12502 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12506 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12507 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12510 breg = XEXP (XEXP (dst, 0), 0);
12511 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12512 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12513 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12515 /* We have to update the breg before doing the store.
12516 Use store with update, if available. */
12520 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12521 emit_insn (TARGET_32BIT
12522 ? (TARGET_POWERPC64
12523 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12524 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12525 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12526 used_update = true;
12529 emit_insn (TARGET_32BIT
12530 ? gen_addsi3 (breg, breg, delta_rtx)
12531 : gen_adddi3 (breg, breg, delta_rtx));
12532 dst = replace_equiv_address (dst, breg);
12535 gcc_assert (offsettable_memref_p (dst));
12538 for (i = 0; i < nregs; i++)
12540 /* Calculate index to next subword. */
12545 /* If compiler already emitted move of first word by
12546 store with update, no need to do anything. */
12547 if (j == 0 && used_update)
12550 emit_insn (gen_rtx_SET (VOIDmode,
12551 simplify_gen_subreg (reg_mode, dst, mode,
12552 j * reg_mode_size),
12553 simplify_gen_subreg (reg_mode, src, mode,
12554 j * reg_mode_size)));
12560 /* This page contains routines that are used to determine what the
12561 function prologue and epilogue code will do and write them out. */
12563 /* Return the first fixed-point register that is required to be
12564 saved. 32 if none. */
12567 first_reg_to_save (void)
12571 /* Find lowest numbered live register. */
12572 for (first_reg = 13; first_reg <= 31; first_reg++)
12573 if (regs_ever_live[first_reg]
12574 && (! call_used_regs[first_reg]
12575 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12576 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12577 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12578 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12583 && current_function_uses_pic_offset_table
12584 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12585 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12591 /* Similar, for FP regs. */
12594 first_fp_reg_to_save (void)
12598 /* Find lowest numbered live register. */
12599 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12600 if (regs_ever_live[first_reg])
12606 /* Similar, for AltiVec regs. */
12609 first_altivec_reg_to_save (void)
12613 /* Stack frame remains as is unless we are in AltiVec ABI. */
12614 if (! TARGET_ALTIVEC_ABI)
12615 return LAST_ALTIVEC_REGNO + 1;
12617 /* Find lowest numbered live register. */
12618 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12619 if (regs_ever_live[i])
12625 /* Return a 32-bit mask of the AltiVec registers we need to set in
12626 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12627 the 32-bit word is 0. */
12629 static unsigned int
12630 compute_vrsave_mask (void)
12632 unsigned int i, mask = 0;
12634 /* First, find out if we use _any_ altivec registers. */
12635 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12636 if (regs_ever_live[i])
12637 mask |= ALTIVEC_REG_BIT (i);
12642 /* Next, remove the argument registers from the set. These must
12643 be in the VRSAVE mask set by the caller, so we don't need to add
12644 them in again. More importantly, the mask we compute here is
12645 used to generate CLOBBERs in the set_vrsave insn, and we do not
12646 wish the argument registers to die. */
12647 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12648 mask &= ~ALTIVEC_REG_BIT (i);
12650 /* Similarly, remove the return value from the set. */
12653 diddle_return_value (is_altivec_return_reg, &yes);
12655 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12661 /* For a very restricted set of circumstances, we can cut down the
12662 size of prologues/epilogues by calling our own save/restore-the-world
12666 compute_save_world_info (rs6000_stack_t *info_ptr)
12668 info_ptr->world_save_p = 1;
12669 info_ptr->world_save_p
12670 = (WORLD_SAVE_P (info_ptr)
12671 && DEFAULT_ABI == ABI_DARWIN
12672 && ! (current_function_calls_setjmp && flag_exceptions)
12673 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12674 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12675 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12676 && info_ptr->cr_save_p);
12678 /* This will not work in conjunction with sibcalls. Make sure there
12679 are none. (This check is expensive, but seldom executed.) */
12680 if (WORLD_SAVE_P (info_ptr))
12683 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12684 if ( GET_CODE (insn) == CALL_INSN
12685 && SIBLING_CALL_P (insn))
12687 info_ptr->world_save_p = 0;
12692 if (WORLD_SAVE_P (info_ptr))
12694 /* Even if we're not touching VRsave, make sure there's room on the
12695 stack for it, if it looks like we're calling SAVE_WORLD, which
12696 will attempt to save it. */
12697 info_ptr->vrsave_size = 4;
12699 /* "Save" the VRsave register too if we're saving the world. */
12700 if (info_ptr->vrsave_mask == 0)
12701 info_ptr->vrsave_mask = compute_vrsave_mask ();
12703 /* Because the Darwin register save/restore routines only handle
12704 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12706 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12707 && (info_ptr->first_altivec_reg_save
12708 >= FIRST_SAVED_ALTIVEC_REGNO));
12715 is_altivec_return_reg (rtx reg, void *xyes)
12717 bool *yes = (bool *) xyes;
12718 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12723 /* Calculate the stack information for the current function. This is
12724 complicated by having two separate calling sequences, the AIX calling
12725 sequence and the V.4 calling sequence.
12727 AIX (and Darwin/Mac OS X) stack frames look like:
12729 SP----> +---------------------------------------+
12730 | back chain to caller | 0 0
12731 +---------------------------------------+
12732 | saved CR | 4 8 (8-11)
12733 +---------------------------------------+
12735 +---------------------------------------+
12736 | reserved for compilers | 12 24
12737 +---------------------------------------+
12738 | reserved for binders | 16 32
12739 +---------------------------------------+
12740 | saved TOC pointer | 20 40
12741 +---------------------------------------+
12742 | Parameter save area (P) | 24 48
12743 +---------------------------------------+
12744 | Alloca space (A) | 24+P etc.
12745 +---------------------------------------+
12746 | Local variable space (L) | 24+P+A
12747 +---------------------------------------+
12748 | Float/int conversion temporary (X) | 24+P+A+L
12749 +---------------------------------------+
12750 | Save area for AltiVec registers (W) | 24+P+A+L+X
12751 +---------------------------------------+
12752 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12753 +---------------------------------------+
12754 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12755 +---------------------------------------+
12756 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12757 +---------------------------------------+
12758 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12759 +---------------------------------------+
12760 old SP->| back chain to caller's caller |
12761 +---------------------------------------+
12763 The required alignment for AIX configurations is two words (i.e., 8
12767 V.4 stack frames look like:
12769 SP----> +---------------------------------------+
12770 | back chain to caller | 0
12771 +---------------------------------------+
12772 | caller's saved LR | 4
12773 +---------------------------------------+
12774 | Parameter save area (P) | 8
12775 +---------------------------------------+
12776 | Alloca space (A) | 8+P
12777 +---------------------------------------+
12778 | Varargs save area (V) | 8+P+A
12779 +---------------------------------------+
12780 | Local variable space (L) | 8+P+A+V
12781 +---------------------------------------+
12782 | Float/int conversion temporary (X) | 8+P+A+V+L
12783 +---------------------------------------+
12784 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12785 +---------------------------------------+
12786 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12787 +---------------------------------------+
12788 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12789 +---------------------------------------+
12790 | SPE: area for 64-bit GP registers |
12791 +---------------------------------------+
12792 | SPE alignment padding |
12793 +---------------------------------------+
12794 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12795 +---------------------------------------+
12796 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12797 +---------------------------------------+
12798 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12799 +---------------------------------------+
12800 old SP->| back chain to caller's caller |
12801 +---------------------------------------+
12803 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12804 given. (But note below and in sysv4.h that we require only 8 and
12805 may round up the size of our stack frame anyways. The historical
12806 reason is early versions of powerpc-linux which didn't properly
12807 align the stack at program startup. A happy side-effect is that
12808 -mno-eabi libraries can be used with -meabi programs.)
12810 The EABI configuration defaults to the V.4 layout. However,
12811 the stack alignment requirements may differ. If -mno-eabi is not
12812 given, the required stack alignment is 8 bytes; if -mno-eabi is
12813 given, the required alignment is 16 bytes. (But see V.4 comment
12816 #ifndef ABI_STACK_BOUNDARY
12817 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12820 static rs6000_stack_t *
12821 rs6000_stack_info (void)
12823 static rs6000_stack_t info;
12824 rs6000_stack_t *info_ptr = &info;
12825 int reg_size = TARGET_32BIT ? 4 : 8;
12828 HOST_WIDE_INT non_fixed_size;
12830 memset (&info, 0, sizeof (info));
12834 /* Cache value so we don't rescan instruction chain over and over. */
12835 if (cfun->machine->insn_chain_scanned_p == 0)
12836 cfun->machine->insn_chain_scanned_p
12837 = spe_func_has_64bit_regs_p () + 1;
12838 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12841 /* Select which calling sequence. */
12842 info_ptr->abi = DEFAULT_ABI;
12844 /* Calculate which registers need to be saved & save area size. */
12845 info_ptr->first_gp_reg_save = first_reg_to_save ();
12846 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12847 even if it currently looks like we won't. */
12848 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12849 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12850 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12851 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12852 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12854 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12856 /* For the SPE, we have an additional upper 32-bits on each GPR.
12857 Ideally we should save the entire 64-bits only when the upper
12858 half is used in SIMD instructions. Since we only record
12859 registers live (not the size they are used in), this proves
12860 difficult because we'd have to traverse the instruction chain at
12861 the right time, taking reload into account. This is a real pain,
12862 so we opt to save the GPRs in 64-bits always if but one register
12863 gets used in 64-bits. Otherwise, all the registers in the frame
12864 get saved in 32-bits.
12866 So... since when we save all GPRs (except the SP) in 64-bits, the
12867 traditional GP save area will be empty. */
12868 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12869 info_ptr->gp_size = 0;
12871 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12872 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12874 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12875 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12876 - info_ptr->first_altivec_reg_save);
12878 /* Does this function call anything? */
12879 info_ptr->calls_p = (! current_function_is_leaf
12880 || cfun->machine->ra_needs_full_frame);
12882 /* Determine if we need to save the link register. */
12883 if ((DEFAULT_ABI == ABI_AIX
12884 && current_function_profile
12885 && !TARGET_PROFILE_KERNEL)
12886 #ifdef TARGET_RELOCATABLE
12887 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12889 || (info_ptr->first_fp_reg_save != 64
12890 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12891 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12892 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12893 || info_ptr->calls_p
12894 || rs6000_ra_ever_killed ())
12896 info_ptr->lr_save_p = 1;
12897 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12900 /* Determine if we need to save the condition code registers. */
12901 if (regs_ever_live[CR2_REGNO]
12902 || regs_ever_live[CR3_REGNO]
12903 || regs_ever_live[CR4_REGNO])
12905 info_ptr->cr_save_p = 1;
12906 if (DEFAULT_ABI == ABI_V4)
12907 info_ptr->cr_size = reg_size;
12910 /* If the current function calls __builtin_eh_return, then we need
12911 to allocate stack space for registers that will hold data for
12912 the exception handler. */
12913 if (current_function_calls_eh_return)
12916 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12919 /* SPE saves EH registers in 64-bits. */
12920 ehrd_size = i * (TARGET_SPE_ABI
12921 && info_ptr->spe_64bit_regs_used != 0
12922 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12927 /* Determine various sizes. */
12928 info_ptr->reg_size = reg_size;
12929 info_ptr->fixed_size = RS6000_SAVE_AREA;
12930 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12931 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12932 TARGET_ALTIVEC ? 16 : 8);
12933 if (FRAME_GROWS_DOWNWARD)
12934 info_ptr->vars_size
12935 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12936 + info_ptr->parm_size,
12937 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12938 - (info_ptr->fixed_size + info_ptr->vars_size
12939 + info_ptr->parm_size);
12941 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12942 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12944 info_ptr->spe_gp_size = 0;
12946 if (TARGET_ALTIVEC_ABI)
12947 info_ptr->vrsave_mask = compute_vrsave_mask ();
12949 info_ptr->vrsave_mask = 0;
12951 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12952 info_ptr->vrsave_size = 4;
12954 info_ptr->vrsave_size = 0;
12956 compute_save_world_info (info_ptr);
12958 /* Calculate the offsets. */
12959 switch (DEFAULT_ABI)
12963 gcc_unreachable ();
12967 info_ptr->fp_save_offset = - info_ptr->fp_size;
12968 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12970 if (TARGET_ALTIVEC_ABI)
12972 info_ptr->vrsave_save_offset
12973 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12975 /* Align stack so vector save area is on a quadword boundary. */
12976 if (info_ptr->altivec_size != 0)
12977 info_ptr->altivec_padding_size
12978 = 16 - (-info_ptr->vrsave_save_offset % 16);
12980 info_ptr->altivec_padding_size = 0;
12982 info_ptr->altivec_save_offset
12983 = info_ptr->vrsave_save_offset
12984 - info_ptr->altivec_padding_size
12985 - info_ptr->altivec_size;
12987 /* Adjust for AltiVec case. */
12988 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12991 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12992 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12993 info_ptr->lr_save_offset = 2*reg_size;
12997 info_ptr->fp_save_offset = - info_ptr->fp_size;
12998 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12999 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13001 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13003 /* Align stack so SPE GPR save area is aligned on a
13004 double-word boundary. */
13005 if (info_ptr->spe_gp_size != 0)
13006 info_ptr->spe_padding_size
13007 = 8 - (-info_ptr->cr_save_offset % 8);
13009 info_ptr->spe_padding_size = 0;
13011 info_ptr->spe_gp_save_offset
13012 = info_ptr->cr_save_offset
13013 - info_ptr->spe_padding_size
13014 - info_ptr->spe_gp_size;
13016 /* Adjust for SPE case. */
13017 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13019 else if (TARGET_ALTIVEC_ABI)
13021 info_ptr->vrsave_save_offset
13022 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13024 /* Align stack so vector save area is on a quadword boundary. */
13025 if (info_ptr->altivec_size != 0)
13026 info_ptr->altivec_padding_size
13027 = 16 - (-info_ptr->vrsave_save_offset % 16);
13029 info_ptr->altivec_padding_size = 0;
13031 info_ptr->altivec_save_offset
13032 = info_ptr->vrsave_save_offset
13033 - info_ptr->altivec_padding_size
13034 - info_ptr->altivec_size;
13036 /* Adjust for AltiVec case. */
13037 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13040 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13041 info_ptr->ehrd_offset -= ehrd_size;
13042 info_ptr->lr_save_offset = reg_size;
13046 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13047 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13048 + info_ptr->gp_size
13049 + info_ptr->altivec_size
13050 + info_ptr->altivec_padding_size
13051 + info_ptr->spe_gp_size
13052 + info_ptr->spe_padding_size
13054 + info_ptr->cr_size
13055 + info_ptr->vrsave_size,
13058 non_fixed_size = (info_ptr->vars_size
13059 + info_ptr->parm_size
13060 + info_ptr->save_size);
13062 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13063 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13065 /* Determine if we need to allocate any stack frame:
13067 For AIX we need to push the stack if a frame pointer is needed
13068 (because the stack might be dynamically adjusted), if we are
13069 debugging, if we make calls, or if the sum of fp_save, gp_save,
13070 and local variables are more than the space needed to save all
13071 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13072 + 18*8 = 288 (GPR13 reserved).
13074 For V.4 we don't have the stack cushion that AIX uses, but assume
13075 that the debugger can handle stackless frames. */
13077 if (info_ptr->calls_p)
13078 info_ptr->push_p = 1;
13080 else if (DEFAULT_ABI == ABI_V4)
13081 info_ptr->push_p = non_fixed_size != 0;
13083 else if (frame_pointer_needed)
13084 info_ptr->push_p = 1;
13086 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13087 info_ptr->push_p = 1;
13090 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13092 /* Zero offsets if we're not saving those registers. */
13093 if (info_ptr->fp_size == 0)
13094 info_ptr->fp_save_offset = 0;
13096 if (info_ptr->gp_size == 0)
13097 info_ptr->gp_save_offset = 0;
13099 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13100 info_ptr->altivec_save_offset = 0;
13102 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13103 info_ptr->vrsave_save_offset = 0;
13105 if (! TARGET_SPE_ABI
13106 || info_ptr->spe_64bit_regs_used == 0
13107 || info_ptr->spe_gp_size == 0)
13108 info_ptr->spe_gp_save_offset = 0;
13110 if (! info_ptr->lr_save_p)
13111 info_ptr->lr_save_offset = 0;
13113 if (! info_ptr->cr_save_p)
13114 info_ptr->cr_save_offset = 0;
13119 /* Return true if the current function uses any GPRs in 64-bit SIMD
13123 spe_func_has_64bit_regs_p (void)
13127 /* Functions that save and restore all the call-saved registers will
13128 need to save/restore the registers in 64-bits. */
13129 if (current_function_calls_eh_return
13130 || current_function_calls_setjmp
13131 || current_function_has_nonlocal_goto)
13134 insns = get_insns ();
13136 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13142 /* FIXME: This should be implemented with attributes...
13144 (set_attr "spe64" "true")....then,
13145 if (get_spe64(insn)) return true;
13147 It's the only reliable way to do the stuff below. */
13149 i = PATTERN (insn);
13150 if (GET_CODE (i) == SET)
13152 enum machine_mode mode = GET_MODE (SET_SRC (i));
13154 if (SPE_VECTOR_MODE (mode))
13156 if (TARGET_E500_DOUBLE && mode == DFmode)
13166 debug_stack_info (rs6000_stack_t *info)
13168 const char *abi_string;
13171 info = rs6000_stack_info ();
13173 fprintf (stderr, "\nStack information for function %s:\n",
13174 ((current_function_decl && DECL_NAME (current_function_decl))
13175 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13180 default: abi_string = "Unknown"; break;
13181 case ABI_NONE: abi_string = "NONE"; break;
13182 case ABI_AIX: abi_string = "AIX"; break;
13183 case ABI_DARWIN: abi_string = "Darwin"; break;
13184 case ABI_V4: abi_string = "V.4"; break;
13187 fprintf (stderr, "\tABI = %5s\n", abi_string);
13189 if (TARGET_ALTIVEC_ABI)
13190 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13192 if (TARGET_SPE_ABI)
13193 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13195 if (info->first_gp_reg_save != 32)
13196 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13198 if (info->first_fp_reg_save != 64)
13199 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13201 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13202 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13203 info->first_altivec_reg_save);
13205 if (info->lr_save_p)
13206 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13208 if (info->cr_save_p)
13209 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13211 if (info->vrsave_mask)
13212 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13215 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13218 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13220 if (info->gp_save_offset)
13221 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13223 if (info->fp_save_offset)
13224 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13226 if (info->altivec_save_offset)
13227 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13228 info->altivec_save_offset);
13230 if (info->spe_gp_save_offset)
13231 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13232 info->spe_gp_save_offset);
13234 if (info->vrsave_save_offset)
13235 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13236 info->vrsave_save_offset);
13238 if (info->lr_save_offset)
13239 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13241 if (info->cr_save_offset)
13242 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13244 if (info->varargs_save_offset)
13245 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13247 if (info->total_size)
13248 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13251 if (info->vars_size)
13252 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13255 if (info->parm_size)
13256 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13258 if (info->fixed_size)
13259 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13262 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13264 if (info->spe_gp_size)
13265 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13268 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13270 if (info->altivec_size)
13271 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13273 if (info->vrsave_size)
13274 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13276 if (info->altivec_padding_size)
13277 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13278 info->altivec_padding_size);
13280 if (info->spe_padding_size)
13281 fprintf (stderr, "\tspe_padding_size = %5d\n",
13282 info->spe_padding_size);
13285 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13287 if (info->save_size)
13288 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13290 if (info->reg_size != 4)
13291 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13293 fprintf (stderr, "\n");
13297 rs6000_return_addr (int count, rtx frame)
13299 /* Currently we don't optimize very well between prolog and body
13300 code and for PIC code the code can be actually quite bad, so
13301 don't try to be too clever here. */
13302 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13304 cfun->machine->ra_needs_full_frame = 1;
13311 plus_constant (copy_to_reg
13312 (gen_rtx_MEM (Pmode,
13313 memory_address (Pmode, frame))),
13314 RETURN_ADDRESS_OFFSET)));
13317 cfun->machine->ra_need_lr = 1;
13318 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13321 /* Say whether a function is a candidate for sibcall handling or not.
13322 We do not allow indirect calls to be optimized into sibling calls.
13323 Also, we can't do it if there are any vector parameters; there's
13324 nowhere to put the VRsave code so it works; note that functions with
13325 vector parameters are required to have a prototype, so the argument
13326 type info must be available here. (The tail recursion case can work
13327 with vector parameters, but there's no way to distinguish here.) */
13329 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13334 if (TARGET_ALTIVEC_VRSAVE)
13336 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13337 type; type = TREE_CHAIN (type))
13339 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13343 if (DEFAULT_ABI == ABI_DARWIN
13344 || (*targetm.binds_local_p) (decl))
13346 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13348 if (!lookup_attribute ("longcall", attr_list)
13349 || lookup_attribute ("shortcall", attr_list))
13356 /* NULL if INSN insn is valid within a low-overhead loop.
13357 Otherwise return why doloop cannot be applied.
13358 PowerPC uses the COUNT register for branch on table instructions. */
13360 static const char *
13361 rs6000_invalid_within_doloop (rtx insn)
13364 return "Function call in the loop.";
13367 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13368 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13369 return "Computed branch in the loop.";
13375 rs6000_ra_ever_killed (void)
13381 if (current_function_is_thunk)
13384 /* regs_ever_live has LR marked as used if any sibcalls are present,
13385 but this should not force saving and restoring in the
13386 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13387 clobbers LR, so that is inappropriate. */
13389 /* Also, the prologue can generate a store into LR that
13390 doesn't really count, like this:
13393 bcl to set PIC register
13397 When we're called from the epilogue, we need to avoid counting
13398 this as a store. */
13400 push_topmost_sequence ();
13401 top = get_insns ();
13402 pop_topmost_sequence ();
13403 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13405 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13411 if (!SIBLING_CALL_P (insn))
13414 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13416 else if (set_of (reg, insn) != NULL_RTX
13417 && !prologue_epilogue_contains (insn))
13424 /* Add a REG_MAYBE_DEAD note to the insn. */
13426 rs6000_maybe_dead (rtx insn)
13428 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13433 /* Emit instructions needed to load the TOC register.
13434 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13435 a constant pool; or for SVR4 -fpic. */
13438 rs6000_emit_load_toc_table (int fromprolog)
13441 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13443 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13446 rtx lab, tmp1, tmp2, got, tempLR;
13448 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13449 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13451 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13453 got = rs6000_got_sym ();
13454 tmp1 = tmp2 = dest;
13457 tmp1 = gen_reg_rtx (Pmode);
13458 tmp2 = gen_reg_rtx (Pmode);
13460 tempLR = (fromprolog
13461 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13462 : gen_reg_rtx (Pmode));
13463 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13465 rs6000_maybe_dead (insn);
13466 insn = emit_move_insn (tmp1, tempLR);
13468 rs6000_maybe_dead (insn);
13469 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13471 rs6000_maybe_dead (insn);
13472 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13474 rs6000_maybe_dead (insn);
13476 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13478 rtx tempLR = (fromprolog
13479 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13480 : gen_reg_rtx (Pmode));
13482 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13484 rs6000_maybe_dead (insn);
13485 insn = emit_move_insn (dest, tempLR);
13487 rs6000_maybe_dead (insn);
13489 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13492 rtx tempLR = (fromprolog
13493 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13494 : gen_reg_rtx (Pmode));
13495 rtx temp0 = (fromprolog
13496 ? gen_rtx_REG (Pmode, 0)
13497 : gen_reg_rtx (Pmode));
13503 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13504 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13506 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13507 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13509 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13511 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13512 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13520 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13521 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13522 emit_move_insn (dest, tempLR);
13523 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13525 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13527 rs6000_maybe_dead (insn);
13529 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13531 /* This is for AIX code running in non-PIC ELF32. */
13534 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13535 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13537 insn = emit_insn (gen_elf_high (dest, realsym));
13539 rs6000_maybe_dead (insn);
13540 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13542 rs6000_maybe_dead (insn);
13546 gcc_assert (DEFAULT_ABI == ABI_AIX);
13549 insn = emit_insn (gen_load_toc_aix_si (dest));
13551 insn = emit_insn (gen_load_toc_aix_di (dest));
13553 rs6000_maybe_dead (insn);
13557 /* Emit instructions to restore the link register after determining where
13558 its value has been stored. */
13561 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13563 rs6000_stack_t *info = rs6000_stack_info ();
13566 operands[0] = source;
13567 operands[1] = scratch;
13569 if (info->lr_save_p)
13571 rtx frame_rtx = stack_pointer_rtx;
13572 HOST_WIDE_INT sp_offset = 0;
13575 if (frame_pointer_needed
13576 || current_function_calls_alloca
13577 || info->total_size > 32767)
13579 tmp = gen_frame_mem (Pmode, frame_rtx);
13580 emit_move_insn (operands[1], tmp);
13581 frame_rtx = operands[1];
13583 else if (info->push_p)
13584 sp_offset = info->total_size;
13586 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13587 tmp = gen_frame_mem (Pmode, tmp);
13588 emit_move_insn (tmp, operands[0]);
13591 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13594 static GTY(()) int set = -1;
13597 get_TOC_alias_set (void)
13600 set = new_alias_set ();
13604 /* This returns nonzero if the current function uses the TOC. This is
13605 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13606 is generated by the ABI_V4 load_toc_* patterns. */
13613 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13616 rtx pat = PATTERN (insn);
13619 if (GET_CODE (pat) == PARALLEL)
13620 for (i = 0; i < XVECLEN (pat, 0); i++)
13622 rtx sub = XVECEXP (pat, 0, i);
13623 if (GET_CODE (sub) == USE)
13625 sub = XEXP (sub, 0);
13626 if (GET_CODE (sub) == UNSPEC
13627 && XINT (sub, 1) == UNSPEC_TOC)
13637 create_TOC_reference (rtx symbol)
13639 if (no_new_pseudos)
13640 regs_ever_live[TOC_REGISTER] = 1;
13641 return gen_rtx_PLUS (Pmode,
13642 gen_rtx_REG (Pmode, TOC_REGISTER),
13643 gen_rtx_CONST (Pmode,
13644 gen_rtx_MINUS (Pmode, symbol,
13645 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13648 /* If _Unwind_* has been called from within the same module,
13649 toc register is not guaranteed to be saved to 40(1) on function
13650 entry. Save it there in that case. */
13653 rs6000_aix_emit_builtin_unwind_init (void)
13656 rtx stack_top = gen_reg_rtx (Pmode);
13657 rtx opcode_addr = gen_reg_rtx (Pmode);
13658 rtx opcode = gen_reg_rtx (SImode);
13659 rtx tocompare = gen_reg_rtx (SImode);
13660 rtx no_toc_save_needed = gen_label_rtx ();
13662 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13663 emit_move_insn (stack_top, mem);
13665 mem = gen_frame_mem (Pmode,
13666 gen_rtx_PLUS (Pmode, stack_top,
13667 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13668 emit_move_insn (opcode_addr, mem);
13669 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13670 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13671 : 0xE8410028, SImode));
13673 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13674 SImode, NULL_RTX, NULL_RTX,
13675 no_toc_save_needed);
13677 mem = gen_frame_mem (Pmode,
13678 gen_rtx_PLUS (Pmode, stack_top,
13679 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13680 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13681 emit_label (no_toc_save_needed);
13684 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13685 and the change to the stack pointer. */
13688 rs6000_emit_stack_tie (void)
13690 rtx mem = gen_frame_mem (BLKmode,
13691 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13693 emit_insn (gen_stack_tie (mem));
13696 /* Emit the correct code for allocating stack space, as insns.
13697 If COPY_R12, make sure a copy of the old frame is left in r12.
13698 The generated code may use hard register 0 as a temporary. */
13701 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13704 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13705 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13706 rtx todec = gen_int_mode (-size, Pmode);
13708 if (INTVAL (todec) != -size)
13710 warning (0, "stack frame too large");
13711 emit_insn (gen_trap ());
13715 if (current_function_limit_stack)
13717 if (REG_P (stack_limit_rtx)
13718 && REGNO (stack_limit_rtx) > 1
13719 && REGNO (stack_limit_rtx) <= 31)
13721 emit_insn (TARGET_32BIT
13722 ? gen_addsi3 (tmp_reg,
13725 : gen_adddi3 (tmp_reg,
13729 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13732 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13734 && DEFAULT_ABI == ABI_V4)
13736 rtx toload = gen_rtx_CONST (VOIDmode,
13737 gen_rtx_PLUS (Pmode,
13741 emit_insn (gen_elf_high (tmp_reg, toload));
13742 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13743 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13747 warning (0, "stack limit expression is not supported");
13750 if (copy_r12 || ! TARGET_UPDATE)
13751 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13757 /* Need a note here so that try_split doesn't get confused. */
13758 if (get_last_insn () == NULL_RTX)
13759 emit_note (NOTE_INSN_DELETED);
13760 insn = emit_move_insn (tmp_reg, todec);
13761 try_split (PATTERN (insn), insn, 0);
13765 insn = emit_insn (TARGET_32BIT
13766 ? gen_movsi_update (stack_reg, stack_reg,
13768 : gen_movdi_di_update (stack_reg, stack_reg,
13769 todec, stack_reg));
13773 insn = emit_insn (TARGET_32BIT
13774 ? gen_addsi3 (stack_reg, stack_reg, todec)
13775 : gen_adddi3 (stack_reg, stack_reg, todec));
13776 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13777 gen_rtx_REG (Pmode, 12));
13780 RTX_FRAME_RELATED_P (insn) = 1;
13782 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13783 gen_rtx_SET (VOIDmode, stack_reg,
13784 gen_rtx_PLUS (Pmode, stack_reg,
13789 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13790 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13791 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13792 deduce these equivalences by itself so it wasn't necessary to hold
13793 its hand so much. */
13796 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13797 rtx reg2, rtx rreg)
13801 /* copy_rtx will not make unique copies of registers, so we need to
13802 ensure we don't have unwanted sharing here. */
13804 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13807 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13809 real = copy_rtx (PATTERN (insn));
13811 if (reg2 != NULL_RTX)
13812 real = replace_rtx (real, reg2, rreg);
13814 real = replace_rtx (real, reg,
13815 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13816 STACK_POINTER_REGNUM),
13819 /* We expect that 'real' is either a SET or a PARALLEL containing
13820 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13821 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13823 if (GET_CODE (real) == SET)
13827 temp = simplify_rtx (SET_SRC (set));
13829 SET_SRC (set) = temp;
13830 temp = simplify_rtx (SET_DEST (set));
13832 SET_DEST (set) = temp;
13833 if (GET_CODE (SET_DEST (set)) == MEM)
13835 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13837 XEXP (SET_DEST (set), 0) = temp;
13844 gcc_assert (GET_CODE (real) == PARALLEL);
13845 for (i = 0; i < XVECLEN (real, 0); i++)
13846 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13848 rtx set = XVECEXP (real, 0, i);
13850 temp = simplify_rtx (SET_SRC (set));
13852 SET_SRC (set) = temp;
13853 temp = simplify_rtx (SET_DEST (set));
13855 SET_DEST (set) = temp;
13856 if (GET_CODE (SET_DEST (set)) == MEM)
13858 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13860 XEXP (SET_DEST (set), 0) = temp;
13862 RTX_FRAME_RELATED_P (set) = 1;
13867 real = spe_synthesize_frame_save (real);
13869 RTX_FRAME_RELATED_P (insn) = 1;
13870 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13875 /* Given an SPE frame note, return a PARALLEL of SETs with the
13876 original note, plus a synthetic register save. */
13879 spe_synthesize_frame_save (rtx real)
13881 rtx synth, offset, reg, real2;
13883 if (GET_CODE (real) != SET
13884 || GET_MODE (SET_SRC (real)) != V2SImode)
13887 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13888 frame related note. The parallel contains a set of the register
13889 being saved, and another set to a synthetic register (n+1200).
13890 This is so we can differentiate between 64-bit and 32-bit saves.
13891 Words cannot describe this nastiness. */
13893 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13894 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13895 && GET_CODE (SET_SRC (real)) == REG);
13898 (set (mem (plus (reg x) (const y)))
13901 (set (mem (plus (reg x) (const y+4)))
13905 real2 = copy_rtx (real);
13906 PUT_MODE (SET_DEST (real2), SImode);
13907 reg = SET_SRC (real2);
13908 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13909 synth = copy_rtx (real2);
13911 if (BYTES_BIG_ENDIAN)
13913 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13914 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13917 reg = SET_SRC (synth);
13919 synth = replace_rtx (synth, reg,
13920 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13922 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13923 synth = replace_rtx (synth, offset,
13924 GEN_INT (INTVAL (offset)
13925 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13927 RTX_FRAME_RELATED_P (synth) = 1;
13928 RTX_FRAME_RELATED_P (real2) = 1;
13929 if (BYTES_BIG_ENDIAN)
13930 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13932 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13937 /* Returns an insn that has a vrsave set operation with the
13938 appropriate CLOBBERs. */
13941 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13944 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13945 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13948 = gen_rtx_SET (VOIDmode,
13950 gen_rtx_UNSPEC_VOLATILE (SImode,
13951 gen_rtvec (2, reg, vrsave),
13952 UNSPECV_SET_VRSAVE));
13956 /* We need to clobber the registers in the mask so the scheduler
13957 does not move sets to VRSAVE before sets of AltiVec registers.
13959 However, if the function receives nonlocal gotos, reload will set
13960 all call saved registers live. We will end up with:
13962 (set (reg 999) (mem))
13963 (parallel [ (set (reg vrsave) (unspec blah))
13964 (clobber (reg 999))])
13966 The clobber will cause the store into reg 999 to be dead, and
13967 flow will attempt to delete an epilogue insn. In this case, we
13968 need an unspec use/set of the register. */
13970 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13971 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13973 if (!epiloguep || call_used_regs [i])
13974 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13975 gen_rtx_REG (V4SImode, i));
13978 rtx reg = gen_rtx_REG (V4SImode, i);
13981 = gen_rtx_SET (VOIDmode,
13983 gen_rtx_UNSPEC (V4SImode,
13984 gen_rtvec (1, reg), 27));
13988 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13990 for (i = 0; i < nclobs; ++i)
13991 XVECEXP (insn, 0, i) = clobs[i];
13996 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13997 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14000 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14001 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14003 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14004 rtx replacea, replaceb;
14006 int_rtx = GEN_INT (offset);
14008 /* Some cases that need register indexed addressing. */
14009 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14010 || (TARGET_E500_DOUBLE && mode == DFmode)
14012 && SPE_VECTOR_MODE (mode)
14013 && !SPE_CONST_OFFSET_OK (offset)))
14015 /* Whomever calls us must make sure r11 is available in the
14016 flow path of instructions in the prologue. */
14017 offset_rtx = gen_rtx_REG (Pmode, 11);
14018 emit_move_insn (offset_rtx, int_rtx);
14020 replacea = offset_rtx;
14021 replaceb = int_rtx;
14025 offset_rtx = int_rtx;
14026 replacea = NULL_RTX;
14027 replaceb = NULL_RTX;
14030 reg = gen_rtx_REG (mode, regno);
14031 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14032 mem = gen_frame_mem (mode, addr);
14034 insn = emit_move_insn (mem, reg);
14036 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14039 /* Emit an offset memory reference suitable for a frame store, while
14040 converting to a valid addressing mode. */
14043 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14045 rtx int_rtx, offset_rtx;
14047 int_rtx = GEN_INT (offset);
14049 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14050 || (TARGET_E500_DOUBLE && mode == DFmode))
14052 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14053 emit_move_insn (offset_rtx, int_rtx);
14056 offset_rtx = int_rtx;
14058 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14061 /* Look for user-defined global regs. We should not save and restore these,
14062 and cannot use stmw/lmw if there are any in its range. */
14065 no_global_regs_above (int first_greg)
14068 for (i = 0; i < 32 - first_greg; i++)
14069 if (global_regs[first_greg + i])
14074 #ifndef TARGET_FIX_AND_CONTINUE
14075 #define TARGET_FIX_AND_CONTINUE 0
14078 /* Emit function prologue as insns. */
14081 rs6000_emit_prologue (void)
14083 rs6000_stack_t *info = rs6000_stack_info ();
14084 enum machine_mode reg_mode = Pmode;
14085 int reg_size = TARGET_32BIT ? 4 : 8;
14086 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14087 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14088 rtx frame_reg_rtx = sp_reg_rtx;
14089 rtx cr_save_rtx = NULL_RTX;
14091 int saving_FPRs_inline;
14092 int using_store_multiple;
14093 HOST_WIDE_INT sp_offset = 0;
14095 if (TARGET_FIX_AND_CONTINUE)
14097 /* gdb on darwin arranges to forward a function from the old
14098 address by modifying the first 5 instructions of the function
14099 to branch to the overriding function. This is necessary to
14100 permit function pointers that point to the old function to
14101 actually forward to the new function. */
14102 emit_insn (gen_nop ());
14103 emit_insn (gen_nop ());
14104 emit_insn (gen_nop ());
14105 emit_insn (gen_nop ());
14106 emit_insn (gen_nop ());
14109 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14111 reg_mode = V2SImode;
14115 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14116 && (!TARGET_SPE_ABI
14117 || info->spe_64bit_regs_used == 0)
14118 && info->first_gp_reg_save < 31
14119 && no_global_regs_above (info->first_gp_reg_save));
14120 saving_FPRs_inline = (info->first_fp_reg_save == 64
14121 || FP_SAVE_INLINE (info->first_fp_reg_save)
14122 || current_function_calls_eh_return
14123 || cfun->machine->ra_need_lr);
14125 /* For V.4, update stack before we do any saving and set back pointer. */
14127 && (DEFAULT_ABI == ABI_V4
14128 || current_function_calls_eh_return))
14130 if (info->total_size < 32767)
14131 sp_offset = info->total_size;
14133 frame_reg_rtx = frame_ptr_rtx;
14134 rs6000_emit_allocate_stack (info->total_size,
14135 (frame_reg_rtx != sp_reg_rtx
14136 && (info->cr_save_p
14138 || info->first_fp_reg_save < 64
14139 || info->first_gp_reg_save < 32
14141 if (frame_reg_rtx != sp_reg_rtx)
14142 rs6000_emit_stack_tie ();
14145 /* Handle world saves specially here. */
14146 if (WORLD_SAVE_P (info))
14152 /* save_world expects lr in r0. */
14153 if (info->lr_save_p)
14155 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14156 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14157 RTX_FRAME_RELATED_P (insn) = 1;
14160 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14161 assumptions about the offsets of various bits of the stack
14163 gcc_assert (info->gp_save_offset == -220
14164 && info->fp_save_offset == -144
14165 && info->lr_save_offset == 8
14166 && info->cr_save_offset == 4
14169 && (!current_function_calls_eh_return
14170 || info->ehrd_offset == -432)
14171 && info->vrsave_save_offset == -224
14172 && info->altivec_save_offset == (-224 -16 -192));
14174 treg = gen_rtx_REG (SImode, 11);
14175 emit_move_insn (treg, GEN_INT (-info->total_size));
14177 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14178 in R11. It also clobbers R12, so beware! */
14180 /* Preserve CR2 for save_world prologues */
14182 sz += 32 - info->first_gp_reg_save;
14183 sz += 64 - info->first_fp_reg_save;
14184 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14185 p = rtvec_alloc (sz);
14187 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14188 gen_rtx_REG (Pmode,
14189 LINK_REGISTER_REGNUM));
14190 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14191 gen_rtx_SYMBOL_REF (Pmode,
14193 /* We do floats first so that the instruction pattern matches
14195 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14197 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14198 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14199 GEN_INT (info->fp_save_offset
14200 + sp_offset + 8 * i));
14201 rtx mem = gen_frame_mem (DFmode, addr);
14203 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14205 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14207 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14208 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14209 GEN_INT (info->altivec_save_offset
14210 + sp_offset + 16 * i));
14211 rtx mem = gen_frame_mem (V4SImode, addr);
14213 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14215 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14217 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14218 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14219 GEN_INT (info->gp_save_offset
14220 + sp_offset + reg_size * i));
14221 rtx mem = gen_frame_mem (reg_mode, addr);
14223 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14227 /* CR register traditionally saved as CR2. */
14228 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14229 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14230 GEN_INT (info->cr_save_offset
14232 rtx mem = gen_frame_mem (reg_mode, addr);
14234 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14236 /* Prevent any attempt to delete the setting of r0 and treg! */
14237 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14238 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14239 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14241 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14242 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14243 NULL_RTX, NULL_RTX);
14245 if (current_function_calls_eh_return)
14250 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14251 if (regno == INVALID_REGNUM)
14253 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14254 info->ehrd_offset + sp_offset
14255 + reg_size * (int) i,
14261 /* Save AltiVec registers if needed. */
14262 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14266 /* There should be a non inline version of this, for when we
14267 are saving lots of vector registers. */
14268 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14269 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14271 rtx areg, savereg, mem;
14274 offset = info->altivec_save_offset + sp_offset
14275 + 16 * (i - info->first_altivec_reg_save);
14277 savereg = gen_rtx_REG (V4SImode, i);
14279 areg = gen_rtx_REG (Pmode, 0);
14280 emit_move_insn (areg, GEN_INT (offset));
14282 /* AltiVec addressing mode is [reg+reg]. */
14283 mem = gen_frame_mem (V4SImode,
14284 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14286 insn = emit_move_insn (mem, savereg);
14288 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14289 areg, GEN_INT (offset));
14293 /* VRSAVE is a bit vector representing which AltiVec registers
14294 are used. The OS uses this to determine which vector
14295 registers to save on a context switch. We need to save
14296 VRSAVE on the stack frame, add whatever AltiVec registers we
14297 used in this function, and do the corresponding magic in the
14300 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14301 && info->vrsave_mask != 0)
14303 rtx reg, mem, vrsave;
14306 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14307 as frame_reg_rtx and r11 as the static chain pointer for
14308 nested functions. */
14309 reg = gen_rtx_REG (SImode, 0);
14310 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14312 emit_insn (gen_get_vrsave_internal (reg));
14314 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14316 if (!WORLD_SAVE_P (info))
14319 offset = info->vrsave_save_offset + sp_offset;
14320 mem = gen_frame_mem (SImode,
14321 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14322 GEN_INT (offset)));
14323 insn = emit_move_insn (mem, reg);
14326 /* Include the registers in the mask. */
14327 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14329 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14332 /* If we use the link register, get it into r0. */
14333 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14335 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14336 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14337 RTX_FRAME_RELATED_P (insn) = 1;
14340 /* If we need to save CR, put it into r12. */
14341 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14345 cr_save_rtx = gen_rtx_REG (SImode, 12);
14346 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14347 RTX_FRAME_RELATED_P (insn) = 1;
14348 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14349 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14350 But that's OK. All we have to do is specify that _one_ condition
14351 code register is saved in this stack slot. The thrower's epilogue
14352 will then restore all the call-saved registers.
14353 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14354 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14355 gen_rtx_REG (SImode, CR2_REGNO));
14356 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14361 /* Do any required saving of fpr's. If only one or two to save, do
14362 it ourselves. Otherwise, call function. */
14363 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14366 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14367 if ((regs_ever_live[info->first_fp_reg_save+i]
14368 && ! call_used_regs[info->first_fp_reg_save+i]))
14369 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14370 info->first_fp_reg_save + i,
14371 info->fp_save_offset + sp_offset + 8 * i,
14374 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14378 const char *alloc_rname;
14380 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14382 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14383 gen_rtx_REG (Pmode,
14384 LINK_REGISTER_REGNUM));
14385 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14386 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14387 alloc_rname = ggc_strdup (rname);
14388 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14389 gen_rtx_SYMBOL_REF (Pmode,
14391 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14393 rtx addr, reg, mem;
14394 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14395 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14396 GEN_INT (info->fp_save_offset
14397 + sp_offset + 8*i));
14398 mem = gen_frame_mem (DFmode, addr);
14400 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14402 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14403 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14404 NULL_RTX, NULL_RTX);
14407 /* Save GPRs. This is done as a PARALLEL if we are using
14408 the store-multiple instructions. */
14409 if (!WORLD_SAVE_P (info) && using_store_multiple)
14413 p = rtvec_alloc (32 - info->first_gp_reg_save);
14414 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14416 rtx addr, reg, mem;
14417 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14418 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14419 GEN_INT (info->gp_save_offset
14422 mem = gen_frame_mem (reg_mode, addr);
14424 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14426 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14427 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14428 NULL_RTX, NULL_RTX);
14430 else if (!WORLD_SAVE_P (info))
14433 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14434 if ((regs_ever_live[info->first_gp_reg_save + i]
14435 && (!call_used_regs[info->first_gp_reg_save + i]
14436 || (i + info->first_gp_reg_save
14437 == RS6000_PIC_OFFSET_TABLE_REGNUM
14438 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14439 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14440 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14441 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14443 rtx addr, reg, mem;
14444 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14446 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14448 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14451 if (!SPE_CONST_OFFSET_OK (offset))
14453 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14454 emit_move_insn (b, GEN_INT (offset));
14457 b = GEN_INT (offset);
14459 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14460 mem = gen_frame_mem (V2SImode, addr);
14461 insn = emit_move_insn (mem, reg);
14463 if (GET_CODE (b) == CONST_INT)
14464 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14465 NULL_RTX, NULL_RTX);
14467 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14468 b, GEN_INT (offset));
14472 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14473 GEN_INT (info->gp_save_offset
14476 mem = gen_frame_mem (reg_mode, addr);
14478 insn = emit_move_insn (mem, reg);
14479 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14480 NULL_RTX, NULL_RTX);
14485 /* ??? There's no need to emit actual instructions here, but it's the
14486 easiest way to get the frame unwind information emitted. */
14487 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14489 unsigned int i, regno;
14491 /* In AIX ABI we need to pretend we save r2 here. */
14494 rtx addr, reg, mem;
14496 reg = gen_rtx_REG (reg_mode, 2);
14497 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14498 GEN_INT (sp_offset + 5 * reg_size));
14499 mem = gen_frame_mem (reg_mode, addr);
14501 insn = emit_move_insn (mem, reg);
14502 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14503 NULL_RTX, NULL_RTX);
14504 PATTERN (insn) = gen_blockage ();
14509 regno = EH_RETURN_DATA_REGNO (i);
14510 if (regno == INVALID_REGNUM)
14513 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14514 info->ehrd_offset + sp_offset
14515 + reg_size * (int) i,
14520 /* Save lr if we used it. */
14521 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14523 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14524 GEN_INT (info->lr_save_offset + sp_offset));
14525 rtx reg = gen_rtx_REG (Pmode, 0);
14526 rtx mem = gen_rtx_MEM (Pmode, addr);
14527 /* This should not be of frame_alias_set, because of
14528 __builtin_return_address. */
14530 insn = emit_move_insn (mem, reg);
14531 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14532 NULL_RTX, NULL_RTX);
14535 /* Save CR if we use any that must be preserved. */
14536 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14538 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14539 GEN_INT (info->cr_save_offset + sp_offset));
14540 rtx mem = gen_frame_mem (SImode, addr);
14541 /* See the large comment above about why CR2_REGNO is used. */
14542 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14544 /* If r12 was used to hold the original sp, copy cr into r0 now
14546 if (REGNO (frame_reg_rtx) == 12)
14550 cr_save_rtx = gen_rtx_REG (SImode, 0);
14551 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14552 RTX_FRAME_RELATED_P (insn) = 1;
14553 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14554 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14559 insn = emit_move_insn (mem, cr_save_rtx);
14561 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14562 NULL_RTX, NULL_RTX);
14565 /* Update stack and set back pointer unless this is V.4,
14566 for which it was done previously. */
14567 if (!WORLD_SAVE_P (info) && info->push_p
14568 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14569 rs6000_emit_allocate_stack (info->total_size, FALSE);
14571 /* Set frame pointer, if needed. */
14572 if (frame_pointer_needed)
14574 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14576 RTX_FRAME_RELATED_P (insn) = 1;
14579 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14580 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14581 || (DEFAULT_ABI == ABI_V4
14582 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14583 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14585 /* If emit_load_toc_table will use the link register, we need to save
14586 it. We use R12 for this purpose because emit_load_toc_table
14587 can use register 0. This allows us to use a plain 'blr' to return
14588 from the procedure more often. */
14589 int save_LR_around_toc_setup = (TARGET_ELF
14590 && DEFAULT_ABI != ABI_AIX
14592 && ! info->lr_save_p
14593 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14594 if (save_LR_around_toc_setup)
14596 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14598 insn = emit_move_insn (frame_ptr_rtx, lr);
14599 rs6000_maybe_dead (insn);
14600 RTX_FRAME_RELATED_P (insn) = 1;
14602 rs6000_emit_load_toc_table (TRUE);
14604 insn = emit_move_insn (lr, frame_ptr_rtx);
14605 rs6000_maybe_dead (insn);
14606 RTX_FRAME_RELATED_P (insn) = 1;
14609 rs6000_emit_load_toc_table (TRUE);
14613 if (DEFAULT_ABI == ABI_DARWIN
14614 && flag_pic && current_function_uses_pic_offset_table)
14616 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14617 rtx src = machopic_function_base_sym ();
14619 /* Save and restore LR locally around this call (in R0). */
14620 if (!info->lr_save_p)
14621 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14623 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14625 insn = emit_move_insn (gen_rtx_REG (Pmode,
14626 RS6000_PIC_OFFSET_TABLE_REGNUM),
14628 rs6000_maybe_dead (insn);
14630 if (!info->lr_save_p)
14631 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14636 /* Write function prologue. */
14639 rs6000_output_function_prologue (FILE *file,
14640 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14642 rs6000_stack_t *info = rs6000_stack_info ();
14644 if (TARGET_DEBUG_STACK)
14645 debug_stack_info (info);
14647 /* Write .extern for any function we will call to save and restore
14649 if (info->first_fp_reg_save < 64
14650 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14651 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14652 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14653 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14654 RESTORE_FP_SUFFIX);
14656 /* Write .extern for AIX common mode routines, if needed. */
14657 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14659 fputs ("\t.extern __mulh\n", file);
14660 fputs ("\t.extern __mull\n", file);
14661 fputs ("\t.extern __divss\n", file);
14662 fputs ("\t.extern __divus\n", file);
14663 fputs ("\t.extern __quoss\n", file);
14664 fputs ("\t.extern __quous\n", file);
14665 common_mode_defined = 1;
14668 if (! HAVE_prologue)
14672 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14673 the "toplevel" insn chain. */
14674 emit_note (NOTE_INSN_DELETED);
14675 rs6000_emit_prologue ();
14676 emit_note (NOTE_INSN_DELETED);
14678 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14682 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14684 INSN_ADDRESSES_NEW (insn, addr);
14689 if (TARGET_DEBUG_STACK)
14690 debug_rtx_list (get_insns (), 100);
14691 final (get_insns (), file, FALSE);
14695 rs6000_pic_labelno++;
14698 /* Emit function epilogue as insns.
14700 At present, dwarf2out_frame_debug_expr doesn't understand
14701 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14702 anywhere in the epilogue. Most of the insns below would in any case
14703 need special notes to explain where r11 is in relation to the stack. */
14706 rs6000_emit_epilogue (int sibcall)
14708 rs6000_stack_t *info;
14709 int restoring_FPRs_inline;
14710 int using_load_multiple;
14711 int using_mfcr_multiple;
14712 int use_backchain_to_restore_sp;
14714 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14715 rtx frame_reg_rtx = sp_reg_rtx;
14716 enum machine_mode reg_mode = Pmode;
14717 int reg_size = TARGET_32BIT ? 4 : 8;
14720 info = rs6000_stack_info ();
14722 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14724 reg_mode = V2SImode;
14728 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14729 && (!TARGET_SPE_ABI
14730 || info->spe_64bit_regs_used == 0)
14731 && info->first_gp_reg_save < 31
14732 && no_global_regs_above (info->first_gp_reg_save));
14733 restoring_FPRs_inline = (sibcall
14734 || current_function_calls_eh_return
14735 || info->first_fp_reg_save == 64
14736 || FP_SAVE_INLINE (info->first_fp_reg_save));
14737 use_backchain_to_restore_sp = (frame_pointer_needed
14738 || current_function_calls_alloca
14739 || info->total_size > 32767);
14740 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14741 || rs6000_cpu == PROCESSOR_PPC603
14742 || rs6000_cpu == PROCESSOR_PPC750
14745 if (WORLD_SAVE_P (info))
14749 const char *alloc_rname;
14752 /* eh_rest_world_r10 will return to the location saved in the LR
14753 stack slot (which is not likely to be our caller.)
14754 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14755 rest_world is similar, except any R10 parameter is ignored.
14756 The exception-handling stuff that was here in 2.95 is no
14757 longer necessary. */
14761 + 32 - info->first_gp_reg_save
14762 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14763 + 63 + 1 - info->first_fp_reg_save);
14765 strcpy (rname, ((current_function_calls_eh_return) ?
14766 "*eh_rest_world_r10" : "*rest_world"));
14767 alloc_rname = ggc_strdup (rname);
14770 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14771 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14772 gen_rtx_REG (Pmode,
14773 LINK_REGISTER_REGNUM));
14775 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14776 /* The instruction pattern requires a clobber here;
14777 it is shared with the restVEC helper. */
14779 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14782 /* CR register traditionally saved as CR2. */
14783 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14784 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14785 GEN_INT (info->cr_save_offset));
14786 rtx mem = gen_frame_mem (reg_mode, addr);
14788 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14791 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14793 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14794 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14795 GEN_INT (info->gp_save_offset
14797 rtx mem = gen_frame_mem (reg_mode, addr);
14799 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14801 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14803 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14804 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14805 GEN_INT (info->altivec_save_offset
14807 rtx mem = gen_frame_mem (V4SImode, addr);
14809 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14811 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14813 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14814 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14815 GEN_INT (info->fp_save_offset
14817 rtx mem = gen_frame_mem (DFmode, addr);
14819 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14822 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14824 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14826 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14828 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14830 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14831 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14836 /* If we have a frame pointer, a call to alloca, or a large stack
14837 frame, restore the old stack pointer using the backchain. Otherwise,
14838 we know what size to update it with. */
14839 if (use_backchain_to_restore_sp)
14841 /* Under V.4, don't reset the stack pointer until after we're done
14842 loading the saved registers. */
14843 if (DEFAULT_ABI == ABI_V4)
14844 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14846 emit_move_insn (frame_reg_rtx,
14847 gen_rtx_MEM (Pmode, sp_reg_rtx));
14849 else if (info->push_p)
14851 if (DEFAULT_ABI == ABI_V4
14852 || current_function_calls_eh_return)
14853 sp_offset = info->total_size;
14856 emit_insn (TARGET_32BIT
14857 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14858 GEN_INT (info->total_size))
14859 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14860 GEN_INT (info->total_size)));
14864 /* Restore AltiVec registers if needed. */
14865 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14869 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14870 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14872 rtx addr, areg, mem;
14874 areg = gen_rtx_REG (Pmode, 0);
14876 (areg, GEN_INT (info->altivec_save_offset
14878 + 16 * (i - info->first_altivec_reg_save)));
14880 /* AltiVec addressing mode is [reg+reg]. */
14881 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14882 mem = gen_frame_mem (V4SImode, addr);
14884 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14888 /* Restore VRSAVE if needed. */
14889 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14890 && info->vrsave_mask != 0)
14892 rtx addr, mem, reg;
14894 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14895 GEN_INT (info->vrsave_save_offset + sp_offset));
14896 mem = gen_frame_mem (SImode, addr);
14897 reg = gen_rtx_REG (SImode, 12);
14898 emit_move_insn (reg, mem);
14900 emit_insn (generate_set_vrsave (reg, info, 1));
14903 /* Get the old lr if we saved it. */
14904 if (info->lr_save_p)
14906 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14907 info->lr_save_offset + sp_offset);
14909 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14912 /* Get the old cr if we saved it. */
14913 if (info->cr_save_p)
14915 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14916 GEN_INT (info->cr_save_offset + sp_offset));
14917 rtx mem = gen_frame_mem (SImode, addr);
14919 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14922 /* Set LR here to try to overlap restores below. */
14923 if (info->lr_save_p)
14924 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14925 gen_rtx_REG (Pmode, 0));
14927 /* Load exception handler data registers, if needed. */
14928 if (current_function_calls_eh_return)
14930 unsigned int i, regno;
14934 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14935 GEN_INT (sp_offset + 5 * reg_size));
14936 rtx mem = gen_frame_mem (reg_mode, addr);
14938 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14945 regno = EH_RETURN_DATA_REGNO (i);
14946 if (regno == INVALID_REGNUM)
14949 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14950 info->ehrd_offset + sp_offset
14951 + reg_size * (int) i);
14953 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14957 /* Restore GPRs. This is done as a PARALLEL if we are using
14958 the load-multiple instructions. */
14959 if (using_load_multiple)
14962 p = rtvec_alloc (32 - info->first_gp_reg_save);
14963 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14965 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14966 GEN_INT (info->gp_save_offset
14969 rtx mem = gen_frame_mem (reg_mode, addr);
14972 gen_rtx_SET (VOIDmode,
14973 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14976 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14979 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14980 if ((regs_ever_live[info->first_gp_reg_save + i]
14981 && (!call_used_regs[info->first_gp_reg_save + i]
14982 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14983 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14984 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14985 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14986 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14988 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14989 GEN_INT (info->gp_save_offset
14992 rtx mem = gen_frame_mem (reg_mode, addr);
14994 /* Restore 64-bit quantities for SPE. */
14995 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14997 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15000 if (!SPE_CONST_OFFSET_OK (offset))
15002 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15003 emit_move_insn (b, GEN_INT (offset));
15006 b = GEN_INT (offset);
15008 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15009 mem = gen_frame_mem (V2SImode, addr);
15012 emit_move_insn (gen_rtx_REG (reg_mode,
15013 info->first_gp_reg_save + i), mem);
15016 /* Restore fpr's if we need to do it without calling a function. */
15017 if (restoring_FPRs_inline)
15018 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15019 if ((regs_ever_live[info->first_fp_reg_save+i]
15020 && ! call_used_regs[info->first_fp_reg_save+i]))
15023 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15024 GEN_INT (info->fp_save_offset
15027 mem = gen_frame_mem (DFmode, addr);
15029 emit_move_insn (gen_rtx_REG (DFmode,
15030 info->first_fp_reg_save + i),
15034 /* If we saved cr, restore it here. Just those that were used. */
15035 if (info->cr_save_p)
15037 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15040 if (using_mfcr_multiple)
15042 for (i = 0; i < 8; i++)
15043 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15045 gcc_assert (count);
15048 if (using_mfcr_multiple && count > 1)
15053 p = rtvec_alloc (count);
15056 for (i = 0; i < 8; i++)
15057 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15059 rtvec r = rtvec_alloc (2);
15060 RTVEC_ELT (r, 0) = r12_rtx;
15061 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15062 RTVEC_ELT (p, ndx) =
15063 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15064 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15067 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15068 gcc_assert (ndx == count);
15071 for (i = 0; i < 8; i++)
15072 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15074 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15080 /* If this is V.4, unwind the stack pointer after all of the loads
15082 if (frame_reg_rtx != sp_reg_rtx)
15084 /* This blockage is needed so that sched doesn't decide to move
15085 the sp change before the register restores. */
15086 rs6000_emit_stack_tie ();
15087 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15089 else if (sp_offset != 0)
15090 emit_insn (TARGET_32BIT
15091 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15092 GEN_INT (sp_offset))
15093 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15094 GEN_INT (sp_offset)));
15096 if (current_function_calls_eh_return)
15098 rtx sa = EH_RETURN_STACKADJ_RTX;
15099 emit_insn (TARGET_32BIT
15100 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15101 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15107 if (! restoring_FPRs_inline)
15108 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15110 p = rtvec_alloc (2);
15112 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15113 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15114 gen_rtx_REG (Pmode,
15115 LINK_REGISTER_REGNUM));
15117 /* If we have to restore more than two FP registers, branch to the
15118 restore function. It will return to our caller. */
15119 if (! restoring_FPRs_inline)
15123 const char *alloc_rname;
15125 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15126 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15127 alloc_rname = ggc_strdup (rname);
15128 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15129 gen_rtx_SYMBOL_REF (Pmode,
15132 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15135 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15136 GEN_INT (info->fp_save_offset + 8*i));
15137 mem = gen_frame_mem (DFmode, addr);
15139 RTVEC_ELT (p, i+3) =
15140 gen_rtx_SET (VOIDmode,
15141 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15146 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15150 /* Write function epilogue. */
15153 rs6000_output_function_epilogue (FILE *file,
15154 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15156 if (! HAVE_epilogue)
15158 rtx insn = get_last_insn ();
15159 /* If the last insn was a BARRIER, we don't have to write anything except
15160 the trace table. */
15161 if (GET_CODE (insn) == NOTE)
15162 insn = prev_nonnote_insn (insn);
15163 if (insn == 0 || GET_CODE (insn) != BARRIER)
15165 /* This is slightly ugly, but at least we don't have two
15166 copies of the epilogue-emitting code. */
15169 /* A NOTE_INSN_DELETED is supposed to be at the start
15170 and end of the "toplevel" insn chain. */
15171 emit_note (NOTE_INSN_DELETED);
15172 rs6000_emit_epilogue (FALSE);
15173 emit_note (NOTE_INSN_DELETED);
15175 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15179 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15181 INSN_ADDRESSES_NEW (insn, addr);
15186 if (TARGET_DEBUG_STACK)
15187 debug_rtx_list (get_insns (), 100);
15188 final (get_insns (), file, FALSE);
15194 macho_branch_islands ();
15195 /* Mach-O doesn't support labels at the end of objects, so if
15196 it looks like we might want one, insert a NOP. */
15198 rtx insn = get_last_insn ();
15201 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15202 insn = PREV_INSN (insn);
15206 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15207 fputs ("\tnop\n", file);
15211 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15214 We don't output a traceback table if -finhibit-size-directive was
15215 used. The documentation for -finhibit-size-directive reads
15216 ``don't output a @code{.size} assembler directive, or anything
15217 else that would cause trouble if the function is split in the
15218 middle, and the two halves are placed at locations far apart in
15219 memory.'' The traceback table has this property, since it
15220 includes the offset from the start of the function to the
15221 traceback table itself.
15223 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15224 different traceback table. */
15225 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15226 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15228 const char *fname = NULL;
15229 const char *language_string = lang_hooks.name;
15230 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15232 int optional_tbtab;
15233 rs6000_stack_t *info = rs6000_stack_info ();
15235 if (rs6000_traceback == traceback_full)
15236 optional_tbtab = 1;
15237 else if (rs6000_traceback == traceback_part)
15238 optional_tbtab = 0;
15240 optional_tbtab = !optimize_size && !TARGET_ELF;
15242 if (optional_tbtab)
15244 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15245 while (*fname == '.') /* V.4 encodes . in the name */
15248 /* Need label immediately before tbtab, so we can compute
15249 its offset from the function start. */
15250 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15251 ASM_OUTPUT_LABEL (file, fname);
15254 /* The .tbtab pseudo-op can only be used for the first eight
15255 expressions, since it can't handle the possibly variable
15256 length fields that follow. However, if you omit the optional
15257 fields, the assembler outputs zeros for all optional fields
15258 anyways, giving each variable length field is minimum length
15259 (as defined in sys/debug.h). Thus we can not use the .tbtab
15260 pseudo-op at all. */
15262 /* An all-zero word flags the start of the tbtab, for debuggers
15263 that have to find it by searching forward from the entry
15264 point or from the current pc. */
15265 fputs ("\t.long 0\n", file);
15267 /* Tbtab format type. Use format type 0. */
15268 fputs ("\t.byte 0,", file);
15270 /* Language type. Unfortunately, there does not seem to be any
15271 official way to discover the language being compiled, so we
15272 use language_string.
15273 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15274 Java is 13. Objective-C is 14. */
15275 if (! strcmp (language_string, "GNU C"))
15277 else if (! strcmp (language_string, "GNU F77")
15278 || ! strcmp (language_string, "GNU F95"))
15280 else if (! strcmp (language_string, "GNU Pascal"))
15282 else if (! strcmp (language_string, "GNU Ada"))
15284 else if (! strcmp (language_string, "GNU C++"))
15286 else if (! strcmp (language_string, "GNU Java"))
15288 else if (! strcmp (language_string, "GNU Objective-C"))
15291 gcc_unreachable ();
15292 fprintf (file, "%d,", i);
15294 /* 8 single bit fields: global linkage (not set for C extern linkage,
15295 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15296 from start of procedure stored in tbtab, internal function, function
15297 has controlled storage, function has no toc, function uses fp,
15298 function logs/aborts fp operations. */
15299 /* Assume that fp operations are used if any fp reg must be saved. */
15300 fprintf (file, "%d,",
15301 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15303 /* 6 bitfields: function is interrupt handler, name present in
15304 proc table, function calls alloca, on condition directives
15305 (controls stack walks, 3 bits), saves condition reg, saves
15307 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15308 set up as a frame pointer, even when there is no alloca call. */
15309 fprintf (file, "%d,",
15310 ((optional_tbtab << 6)
15311 | ((optional_tbtab & frame_pointer_needed) << 5)
15312 | (info->cr_save_p << 1)
15313 | (info->lr_save_p)));
15315 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15317 fprintf (file, "%d,",
15318 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15320 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15321 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15323 if (optional_tbtab)
15325 /* Compute the parameter info from the function decl argument
15328 int next_parm_info_bit = 31;
15330 for (decl = DECL_ARGUMENTS (current_function_decl);
15331 decl; decl = TREE_CHAIN (decl))
15333 rtx parameter = DECL_INCOMING_RTL (decl);
15334 enum machine_mode mode = GET_MODE (parameter);
15336 if (GET_CODE (parameter) == REG)
15338 if (SCALAR_FLOAT_MODE_P (mode))
15356 gcc_unreachable ();
15359 /* If only one bit will fit, don't or in this entry. */
15360 if (next_parm_info_bit > 0)
15361 parm_info |= (bits << (next_parm_info_bit - 1));
15362 next_parm_info_bit -= 2;
15366 fixed_parms += ((GET_MODE_SIZE (mode)
15367 + (UNITS_PER_WORD - 1))
15369 next_parm_info_bit -= 1;
15375 /* Number of fixed point parameters. */
15376 /* This is actually the number of words of fixed point parameters; thus
15377 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15378 fprintf (file, "%d,", fixed_parms);
15380 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15382 /* This is actually the number of fp registers that hold parameters;
15383 and thus the maximum value is 13. */
15384 /* Set parameters on stack bit if parameters are not in their original
15385 registers, regardless of whether they are on the stack? Xlc
15386 seems to set the bit when not optimizing. */
15387 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15389 if (! optional_tbtab)
15392 /* Optional fields follow. Some are variable length. */
15394 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15395 11 double float. */
15396 /* There is an entry for each parameter in a register, in the order that
15397 they occur in the parameter list. Any intervening arguments on the
15398 stack are ignored. If the list overflows a long (max possible length
15399 34 bits) then completely leave off all elements that don't fit. */
15400 /* Only emit this long if there was at least one parameter. */
15401 if (fixed_parms || float_parms)
15402 fprintf (file, "\t.long %d\n", parm_info);
15404 /* Offset from start of code to tb table. */
15405 fputs ("\t.long ", file);
15406 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15408 RS6000_OUTPUT_BASENAME (file, fname);
15410 assemble_name (file, fname);
15412 rs6000_output_function_entry (file, fname);
15415 /* Interrupt handler mask. */
15416 /* Omit this long, since we never set the interrupt handler bit
15419 /* Number of CTL (controlled storage) anchors. */
15420 /* Omit this long, since the has_ctl bit is never set above. */
15422 /* Displacement into stack of each CTL anchor. */
15423 /* Omit this list of longs, because there are no CTL anchors. */
15425 /* Length of function name. */
15428 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15430 /* Function name. */
15431 assemble_string (fname, strlen (fname));
15433 /* Register for alloca automatic storage; this is always reg 31.
15434 Only emit this if the alloca bit was set above. */
15435 if (frame_pointer_needed)
15436 fputs ("\t.byte 31\n", file);
15438 fputs ("\t.align 2\n", file);
15442 /* A C compound statement that outputs the assembler code for a thunk
15443 function, used to implement C++ virtual function calls with
15444 multiple inheritance. The thunk acts as a wrapper around a virtual
15445 function, adjusting the implicit object parameter before handing
15446 control off to the real function.
15448 First, emit code to add the integer DELTA to the location that
15449 contains the incoming first argument. Assume that this argument
15450 contains a pointer, and is the one used to pass the `this' pointer
15451 in C++. This is the incoming argument *before* the function
15452 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15453 values of all other incoming arguments.
15455 After the addition, emit code to jump to FUNCTION, which is a
15456 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15457 not touch the return address. Hence returning from FUNCTION will
15458 return to whoever called the current `thunk'.
15460 The effect must be as if FUNCTION had been called directly with the
15461 adjusted first argument. This macro is responsible for emitting
15462 all of the code for a thunk function; output_function_prologue()
15463 and output_function_epilogue() are not invoked.
15465 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15466 been extracted from it.) It might possibly be useful on some
15467 targets, but probably not.
15469 If you do not define this macro, the target-independent code in the
15470 C++ frontend will generate a less efficient heavyweight thunk that
15471 calls FUNCTION instead of jumping to it. The generic approach does
15472 not support varargs. */
15475 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15476 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15479 rtx this, insn, funexp;
15481 reload_completed = 1;
15482 epilogue_completed = 1;
15483 no_new_pseudos = 1;
15484 reset_block_changes ();
15486 /* Mark the end of the (empty) prologue. */
15487 emit_note (NOTE_INSN_PROLOGUE_END);
15489 /* Find the "this" pointer. If the function returns a structure,
15490 the structure return pointer is in r3. */
15491 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15492 this = gen_rtx_REG (Pmode, 4);
15494 this = gen_rtx_REG (Pmode, 3);
15496 /* Apply the constant offset, if required. */
15499 rtx delta_rtx = GEN_INT (delta);
15500 emit_insn (TARGET_32BIT
15501 ? gen_addsi3 (this, this, delta_rtx)
15502 : gen_adddi3 (this, this, delta_rtx));
15505 /* Apply the offset from the vtable, if required. */
15508 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15509 rtx tmp = gen_rtx_REG (Pmode, 12);
15511 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15512 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15514 emit_insn (TARGET_32BIT
15515 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15516 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15517 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15521 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15523 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15525 emit_insn (TARGET_32BIT
15526 ? gen_addsi3 (this, this, tmp)
15527 : gen_adddi3 (this, this, tmp));
15530 /* Generate a tail call to the target function. */
15531 if (!TREE_USED (function))
15533 assemble_external (function);
15534 TREE_USED (function) = 1;
15536 funexp = XEXP (DECL_RTL (function), 0);
15537 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15540 if (MACHOPIC_INDIRECT)
15541 funexp = machopic_indirect_call_target (funexp);
15544 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15545 generate sibcall RTL explicitly. */
15546 insn = emit_call_insn (
15547 gen_rtx_PARALLEL (VOIDmode,
15549 gen_rtx_CALL (VOIDmode,
15550 funexp, const0_rtx),
15551 gen_rtx_USE (VOIDmode, const0_rtx),
15552 gen_rtx_USE (VOIDmode,
15553 gen_rtx_REG (SImode,
15554 LINK_REGISTER_REGNUM)),
15555 gen_rtx_RETURN (VOIDmode))));
15556 SIBLING_CALL_P (insn) = 1;
15559 /* Run just enough of rest_of_compilation to get the insns emitted.
15560 There's not really enough bulk here to make other passes such as
15561 instruction scheduling worth while. Note that use_thunk calls
15562 assemble_start_function and assemble_end_function. */
15563 insn = get_insns ();
15564 insn_locators_initialize ();
15565 shorten_branches (insn);
15566 final_start_function (insn, file, 1);
15567 final (insn, file, 1);
15568 final_end_function ();
15570 reload_completed = 0;
15571 epilogue_completed = 0;
15572 no_new_pseudos = 0;
15575 /* A quick summary of the various types of 'constant-pool tables'
15578 Target Flags Name One table per
15579 AIX (none) AIX TOC object file
15580 AIX -mfull-toc AIX TOC object file
15581 AIX -mminimal-toc AIX minimal TOC translation unit
15582 SVR4/EABI (none) SVR4 SDATA object file
15583 SVR4/EABI -fpic SVR4 pic object file
15584 SVR4/EABI -fPIC SVR4 PIC translation unit
15585 SVR4/EABI -mrelocatable EABI TOC function
15586 SVR4/EABI -maix AIX TOC object file
15587 SVR4/EABI -maix -mminimal-toc
15588 AIX minimal TOC translation unit
15590 Name Reg. Set by entries contains:
15591 made by addrs? fp? sum?
15593 AIX TOC 2 crt0 as Y option option
15594 AIX minimal TOC 30 prolog gcc Y Y option
15595 SVR4 SDATA 13 crt0 gcc N Y N
15596 SVR4 pic 30 prolog ld Y not yet N
15597 SVR4 PIC 30 prolog gcc Y option option
15598 EABI TOC 30 prolog gcc Y option option
15602 /* Hash functions for the hash table. */
15605 rs6000_hash_constant (rtx k)
15607 enum rtx_code code = GET_CODE (k);
15608 enum machine_mode mode = GET_MODE (k);
15609 unsigned result = (code << 3) ^ mode;
15610 const char *format;
15613 format = GET_RTX_FORMAT (code);
15614 flen = strlen (format);
15620 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15623 if (mode != VOIDmode)
15624 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15636 for (; fidx < flen; fidx++)
15637 switch (format[fidx])
15642 const char *str = XSTR (k, fidx);
15643 len = strlen (str);
15644 result = result * 613 + len;
15645 for (i = 0; i < len; i++)
15646 result = result * 613 + (unsigned) str[i];
15651 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15655 result = result * 613 + (unsigned) XINT (k, fidx);
15658 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15659 result = result * 613 + (unsigned) XWINT (k, fidx);
15663 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15664 result = result * 613 + (unsigned) (XWINT (k, fidx)
15671 gcc_unreachable ();
15678 toc_hash_function (const void *hash_entry)
15680 const struct toc_hash_struct *thc =
15681 (const struct toc_hash_struct *) hash_entry;
15682 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15685 /* Compare H1 and H2 for equivalence. */
15688 toc_hash_eq (const void *h1, const void *h2)
15690 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15691 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15693 if (((const struct toc_hash_struct *) h1)->key_mode
15694 != ((const struct toc_hash_struct *) h2)->key_mode)
15697 return rtx_equal_p (r1, r2);
15700 /* These are the names given by the C++ front-end to vtables, and
15701 vtable-like objects. Ideally, this logic should not be here;
15702 instead, there should be some programmatic way of inquiring as
15703 to whether or not an object is a vtable. */
15705 #define VTABLE_NAME_P(NAME) \
15706 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15707 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15708 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15709 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15710 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15713 rs6000_output_symbol_ref (FILE *file, rtx x)
15715 /* Currently C++ toc references to vtables can be emitted before it
15716 is decided whether the vtable is public or private. If this is
15717 the case, then the linker will eventually complain that there is
15718 a reference to an unknown section. Thus, for vtables only,
15719 we emit the TOC reference to reference the symbol and not the
15721 const char *name = XSTR (x, 0);
15723 if (VTABLE_NAME_P (name))
15725 RS6000_OUTPUT_BASENAME (file, name);
15728 assemble_name (file, name);
15731 /* Output a TOC entry. We derive the entry name from what is being
15735 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15738 const char *name = buf;
15739 const char *real_name;
15741 HOST_WIDE_INT offset = 0;
15743 gcc_assert (!TARGET_NO_TOC);
15745 /* When the linker won't eliminate them, don't output duplicate
15746 TOC entries (this happens on AIX if there is any kind of TOC,
15747 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15749 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15751 struct toc_hash_struct *h;
15754 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15755 time because GGC is not initialized at that point. */
15756 if (toc_hash_table == NULL)
15757 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15758 toc_hash_eq, NULL);
15760 h = ggc_alloc (sizeof (*h));
15762 h->key_mode = mode;
15763 h->labelno = labelno;
15765 found = htab_find_slot (toc_hash_table, h, 1);
15766 if (*found == NULL)
15768 else /* This is indeed a duplicate.
15769 Set this label equal to that label. */
15771 fputs ("\t.set ", file);
15772 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15773 fprintf (file, "%d,", labelno);
15774 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15775 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15781 /* If we're going to put a double constant in the TOC, make sure it's
15782 aligned properly when strict alignment is on. */
15783 if (GET_CODE (x) == CONST_DOUBLE
15784 && STRICT_ALIGNMENT
15785 && GET_MODE_BITSIZE (mode) >= 64
15786 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15787 ASM_OUTPUT_ALIGN (file, 3);
15790 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15792 /* Handle FP constants specially. Note that if we have a minimal
15793 TOC, things we put here aren't actually in the TOC, so we can allow
15795 if (GET_CODE (x) == CONST_DOUBLE &&
15796 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15798 REAL_VALUE_TYPE rv;
15801 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15802 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15803 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15805 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15809 if (TARGET_MINIMAL_TOC)
15810 fputs (DOUBLE_INT_ASM_OP, file);
15812 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15813 k[0] & 0xffffffff, k[1] & 0xffffffff,
15814 k[2] & 0xffffffff, k[3] & 0xffffffff);
15815 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15816 k[0] & 0xffffffff, k[1] & 0xffffffff,
15817 k[2] & 0xffffffff, k[3] & 0xffffffff);
15822 if (TARGET_MINIMAL_TOC)
15823 fputs ("\t.long ", file);
15825 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15826 k[0] & 0xffffffff, k[1] & 0xffffffff,
15827 k[2] & 0xffffffff, k[3] & 0xffffffff);
15828 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15829 k[0] & 0xffffffff, k[1] & 0xffffffff,
15830 k[2] & 0xffffffff, k[3] & 0xffffffff);
15834 else if (GET_CODE (x) == CONST_DOUBLE &&
15835 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
15837 REAL_VALUE_TYPE rv;
15840 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15842 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15843 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
15845 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15849 if (TARGET_MINIMAL_TOC)
15850 fputs (DOUBLE_INT_ASM_OP, file);
15852 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15853 k[0] & 0xffffffff, k[1] & 0xffffffff);
15854 fprintf (file, "0x%lx%08lx\n",
15855 k[0] & 0xffffffff, k[1] & 0xffffffff);
15860 if (TARGET_MINIMAL_TOC)
15861 fputs ("\t.long ", file);
15863 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15864 k[0] & 0xffffffff, k[1] & 0xffffffff);
15865 fprintf (file, "0x%lx,0x%lx\n",
15866 k[0] & 0xffffffff, k[1] & 0xffffffff);
15870 else if (GET_CODE (x) == CONST_DOUBLE &&
15871 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
15873 REAL_VALUE_TYPE rv;
15876 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15877 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15878 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
15880 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15884 if (TARGET_MINIMAL_TOC)
15885 fputs (DOUBLE_INT_ASM_OP, file);
15887 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15888 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15893 if (TARGET_MINIMAL_TOC)
15894 fputs ("\t.long ", file);
15896 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15897 fprintf (file, "0x%lx\n", l & 0xffffffff);
15901 else if (GET_MODE (x) == VOIDmode
15902 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15904 unsigned HOST_WIDE_INT low;
15905 HOST_WIDE_INT high;
15907 if (GET_CODE (x) == CONST_DOUBLE)
15909 low = CONST_DOUBLE_LOW (x);
15910 high = CONST_DOUBLE_HIGH (x);
15913 #if HOST_BITS_PER_WIDE_INT == 32
15916 high = (low & 0x80000000) ? ~0 : 0;
15920 low = INTVAL (x) & 0xffffffff;
15921 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15925 /* TOC entries are always Pmode-sized, but since this
15926 is a bigendian machine then if we're putting smaller
15927 integer constants in the TOC we have to pad them.
15928 (This is still a win over putting the constants in
15929 a separate constant pool, because then we'd have
15930 to have both a TOC entry _and_ the actual constant.)
15932 For a 32-bit target, CONST_INT values are loaded and shifted
15933 entirely within `low' and can be stored in one TOC entry. */
15935 /* It would be easy to make this work, but it doesn't now. */
15936 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15938 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15940 #if HOST_BITS_PER_WIDE_INT == 32
15941 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15942 POINTER_SIZE, &low, &high, 0);
15945 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15946 high = (HOST_WIDE_INT) low >> 32;
15953 if (TARGET_MINIMAL_TOC)
15954 fputs (DOUBLE_INT_ASM_OP, file);
15956 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15957 (long) high & 0xffffffff, (long) low & 0xffffffff);
15958 fprintf (file, "0x%lx%08lx\n",
15959 (long) high & 0xffffffff, (long) low & 0xffffffff);
15964 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15966 if (TARGET_MINIMAL_TOC)
15967 fputs ("\t.long ", file);
15969 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15970 (long) high & 0xffffffff, (long) low & 0xffffffff);
15971 fprintf (file, "0x%lx,0x%lx\n",
15972 (long) high & 0xffffffff, (long) low & 0xffffffff);
15976 if (TARGET_MINIMAL_TOC)
15977 fputs ("\t.long ", file);
15979 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15980 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15986 if (GET_CODE (x) == CONST)
15988 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15990 base = XEXP (XEXP (x, 0), 0);
15991 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15994 switch (GET_CODE (base))
15997 name = XSTR (base, 0);
16001 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16002 CODE_LABEL_NUMBER (XEXP (base, 0)));
16006 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16010 gcc_unreachable ();
16013 real_name = (*targetm.strip_name_encoding) (name);
16014 if (TARGET_MINIMAL_TOC)
16015 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16018 fprintf (file, "\t.tc %s", real_name);
16021 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16023 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16025 fputs ("[TC],", file);
16028 /* Currently C++ toc references to vtables can be emitted before it
16029 is decided whether the vtable is public or private. If this is
16030 the case, then the linker will eventually complain that there is
16031 a TOC reference to an unknown section. Thus, for vtables only,
16032 we emit the TOC reference to reference the symbol and not the
16034 if (VTABLE_NAME_P (name))
16036 RS6000_OUTPUT_BASENAME (file, name);
16038 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16039 else if (offset > 0)
16040 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16043 output_addr_const (file, x);
16047 /* Output an assembler pseudo-op to write an ASCII string of N characters
16048 starting at P to FILE.
16050 On the RS/6000, we have to do this using the .byte operation and
16051 write out special characters outside the quoted string.
16052 Also, the assembler is broken; very long strings are truncated,
16053 so we must artificially break them up early. */
16056 output_ascii (FILE *file, const char *p, int n)
16059 int i, count_string;
16060 const char *for_string = "\t.byte \"";
16061 const char *for_decimal = "\t.byte ";
16062 const char *to_close = NULL;
16065 for (i = 0; i < n; i++)
16068 if (c >= ' ' && c < 0177)
16071 fputs (for_string, file);
16074 /* Write two quotes to get one. */
16082 for_decimal = "\"\n\t.byte ";
16086 if (count_string >= 512)
16088 fputs (to_close, file);
16090 for_string = "\t.byte \"";
16091 for_decimal = "\t.byte ";
16099 fputs (for_decimal, file);
16100 fprintf (file, "%d", c);
16102 for_string = "\n\t.byte \"";
16103 for_decimal = ", ";
16109 /* Now close the string if we have written one. Then end the line. */
16111 fputs (to_close, file);
16114 /* Generate a unique section name for FILENAME for a section type
16115 represented by SECTION_DESC. Output goes into BUF.
16117 SECTION_DESC can be any string, as long as it is different for each
16118 possible section type.
16120 We name the section in the same manner as xlc. The name begins with an
16121 underscore followed by the filename (after stripping any leading directory
16122 names) with the last period replaced by the string SECTION_DESC. If
16123 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16127 rs6000_gen_section_name (char **buf, const char *filename,
16128 const char *section_desc)
16130 const char *q, *after_last_slash, *last_period = 0;
16134 after_last_slash = filename;
16135 for (q = filename; *q; q++)
16138 after_last_slash = q + 1;
16139 else if (*q == '.')
16143 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16144 *buf = (char *) xmalloc (len);
16149 for (q = after_last_slash; *q; q++)
16151 if (q == last_period)
16153 strcpy (p, section_desc);
16154 p += strlen (section_desc);
16158 else if (ISALNUM (*q))
16162 if (last_period == 0)
16163 strcpy (p, section_desc);
16168 /* Emit profile function. */
16171 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16173 /* Non-standard profiling for kernels, which just saves LR then calls
16174 _mcount without worrying about arg saves. The idea is to change
16175 the function prologue as little as possible as it isn't easy to
16176 account for arg save/restore code added just for _mcount. */
16177 if (TARGET_PROFILE_KERNEL)
16180 if (DEFAULT_ABI == ABI_AIX)
16182 #ifndef NO_PROFILE_COUNTERS
16183 # define NO_PROFILE_COUNTERS 0
16185 if (NO_PROFILE_COUNTERS)
16186 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16190 const char *label_name;
16193 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16194 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16195 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16197 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16201 else if (DEFAULT_ABI == ABI_DARWIN)
16203 const char *mcount_name = RS6000_MCOUNT;
16204 int caller_addr_regno = LINK_REGISTER_REGNUM;
16206 /* Be conservative and always set this, at least for now. */
16207 current_function_uses_pic_offset_table = 1;
16210 /* For PIC code, set up a stub and collect the caller's address
16211 from r0, which is where the prologue puts it. */
16212 if (MACHOPIC_INDIRECT
16213 && current_function_uses_pic_offset_table)
16214 caller_addr_regno = 0;
16216 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16218 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16222 /* Write function profiler code. */
16225 output_function_profiler (FILE *file, int labelno)
16229 switch (DEFAULT_ABI)
16232 gcc_unreachable ();
16237 warning (0, "no profiling of 64-bit code for this ABI");
16240 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16241 fprintf (file, "\tmflr %s\n", reg_names[0]);
16242 if (NO_PROFILE_COUNTERS)
16244 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16245 reg_names[0], reg_names[1]);
16247 else if (TARGET_SECURE_PLT && flag_pic)
16249 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16250 reg_names[0], reg_names[1]);
16251 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16252 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16253 reg_names[12], reg_names[12]);
16254 assemble_name (file, buf);
16255 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16256 assemble_name (file, buf);
16257 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16259 else if (flag_pic == 1)
16261 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16262 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16263 reg_names[0], reg_names[1]);
16264 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16265 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16266 assemble_name (file, buf);
16267 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16269 else if (flag_pic > 1)
16271 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16272 reg_names[0], reg_names[1]);
16273 /* Now, we need to get the address of the label. */
16274 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16275 assemble_name (file, buf);
16276 fputs ("-.\n1:", file);
16277 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16278 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16279 reg_names[0], reg_names[11]);
16280 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16281 reg_names[0], reg_names[0], reg_names[11]);
16285 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16286 assemble_name (file, buf);
16287 fputs ("@ha\n", file);
16288 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16289 reg_names[0], reg_names[1]);
16290 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16291 assemble_name (file, buf);
16292 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16295 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16296 fprintf (file, "\tbl %s%s\n",
16297 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16302 if (!TARGET_PROFILE_KERNEL)
16304 /* Don't do anything, done in output_profile_hook (). */
16308 gcc_assert (!TARGET_32BIT);
16310 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16311 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16313 if (cfun->static_chain_decl != NULL)
16315 asm_fprintf (file, "\tstd %s,24(%s)\n",
16316 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16317 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16318 asm_fprintf (file, "\tld %s,24(%s)\n",
16319 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16322 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16329 /* Power4 load update and store update instructions are cracked into a
16330 load or store and an integer insn which are executed in the same cycle.
16331 Branches have their own dispatch slot which does not count against the
16332 GCC issue rate, but it changes the program flow so there are no other
16333 instructions to issue in this cycle. */
16336 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16337 int verbose ATTRIBUTE_UNUSED,
16338 rtx insn, int more)
16340 if (GET_CODE (PATTERN (insn)) == USE
16341 || GET_CODE (PATTERN (insn)) == CLOBBER)
16344 if (rs6000_sched_groups)
16346 if (is_microcoded_insn (insn))
16348 else if (is_cracked_insn (insn))
16349 return more > 2 ? more - 2 : 0;
16355 /* Adjust the cost of a scheduling dependency. Return the new cost of
16356 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16359 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16361 if (! recog_memoized (insn))
16364 if (REG_NOTE_KIND (link) != 0)
16367 if (REG_NOTE_KIND (link) == 0)
16369 /* Data dependency; DEP_INSN writes a register that INSN reads
16370 some cycles later. */
16372 /* Separate a load from a narrower, dependent store. */
16373 if (rs6000_sched_groups
16374 && GET_CODE (PATTERN (insn)) == SET
16375 && GET_CODE (PATTERN (dep_insn)) == SET
16376 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16377 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16378 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16379 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16382 switch (get_attr_type (insn))
16385 /* Tell the first scheduling pass about the latency between
16386 a mtctr and bctr (and mtlr and br/blr). The first
16387 scheduling pass will not know about this latency since
16388 the mtctr instruction, which has the latency associated
16389 to it, will be generated by reload. */
16390 return TARGET_POWER ? 5 : 4;
16392 /* Leave some extra cycles between a compare and its
16393 dependent branch, to inhibit expensive mispredicts. */
16394 if ((rs6000_cpu_attr == CPU_PPC603
16395 || rs6000_cpu_attr == CPU_PPC604
16396 || rs6000_cpu_attr == CPU_PPC604E
16397 || rs6000_cpu_attr == CPU_PPC620
16398 || rs6000_cpu_attr == CPU_PPC630
16399 || rs6000_cpu_attr == CPU_PPC750
16400 || rs6000_cpu_attr == CPU_PPC7400
16401 || rs6000_cpu_attr == CPU_PPC7450
16402 || rs6000_cpu_attr == CPU_POWER4
16403 || rs6000_cpu_attr == CPU_POWER5)
16404 && recog_memoized (dep_insn)
16405 && (INSN_CODE (dep_insn) >= 0)
16406 && (get_attr_type (dep_insn) == TYPE_CMP
16407 || get_attr_type (dep_insn) == TYPE_COMPARE
16408 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16409 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16410 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16411 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16412 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16413 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16418 /* Fall out to return default cost. */
16424 /* The function returns a true if INSN is microcoded.
16425 Return false otherwise. */
16428 is_microcoded_insn (rtx insn)
16430 if (!insn || !INSN_P (insn)
16431 || GET_CODE (PATTERN (insn)) == USE
16432 || GET_CODE (PATTERN (insn)) == CLOBBER)
16435 if (rs6000_sched_groups)
16437 enum attr_type type = get_attr_type (insn);
16438 if (type == TYPE_LOAD_EXT_U
16439 || type == TYPE_LOAD_EXT_UX
16440 || type == TYPE_LOAD_UX
16441 || type == TYPE_STORE_UX
16442 || type == TYPE_MFCR)
16449 /* The function returns a nonzero value if INSN can be scheduled only
16450 as the first insn in a dispatch group ("dispatch-slot restricted").
16451 In this case, the returned value indicates how many dispatch slots
16452 the insn occupies (at the beginning of the group).
16453 Return 0 otherwise. */
16456 is_dispatch_slot_restricted (rtx insn)
16458 enum attr_type type;
16460 if (!rs6000_sched_groups)
16464 || insn == NULL_RTX
16465 || GET_CODE (insn) == NOTE
16466 || GET_CODE (PATTERN (insn)) == USE
16467 || GET_CODE (PATTERN (insn)) == CLOBBER)
16470 type = get_attr_type (insn);
16477 case TYPE_DELAYED_CR:
16478 case TYPE_CR_LOGICAL:
16491 if (rs6000_cpu == PROCESSOR_POWER5
16492 && is_cracked_insn (insn))
16498 /* The function returns true if INSN is cracked into 2 instructions
16499 by the processor (and therefore occupies 2 issue slots). */
16502 is_cracked_insn (rtx insn)
16504 if (!insn || !INSN_P (insn)
16505 || GET_CODE (PATTERN (insn)) == USE
16506 || GET_CODE (PATTERN (insn)) == CLOBBER)
16509 if (rs6000_sched_groups)
16511 enum attr_type type = get_attr_type (insn);
16512 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16513 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16514 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16515 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16516 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16517 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16518 || type == TYPE_IDIV || type == TYPE_LDIV
16519 || type == TYPE_INSERT_WORD)
16526 /* The function returns true if INSN can be issued only from
16527 the branch slot. */
16530 is_branch_slot_insn (rtx insn)
16532 if (!insn || !INSN_P (insn)
16533 || GET_CODE (PATTERN (insn)) == USE
16534 || GET_CODE (PATTERN (insn)) == CLOBBER)
16537 if (rs6000_sched_groups)
16539 enum attr_type type = get_attr_type (insn);
16540 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16548 /* A C statement (sans semicolon) to update the integer scheduling
16549 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16550 INSN earlier, reduce the priority to execute INSN later. Do not
16551 define this macro if you do not need to adjust the scheduling
16552 priorities of insns. */
16555 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16557 /* On machines (like the 750) which have asymmetric integer units,
16558 where one integer unit can do multiply and divides and the other
16559 can't, reduce the priority of multiply/divide so it is scheduled
16560 before other integer operations. */
16563 if (! INSN_P (insn))
16566 if (GET_CODE (PATTERN (insn)) == USE)
16569 switch (rs6000_cpu_attr) {
16571 switch (get_attr_type (insn))
16578 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16579 priority, priority);
16580 if (priority >= 0 && priority < 0x01000000)
16587 if (is_dispatch_slot_restricted (insn)
16588 && reload_completed
16589 && current_sched_info->sched_max_insns_priority
16590 && rs6000_sched_restricted_insns_priority)
16593 /* Prioritize insns that can be dispatched only in the first
16595 if (rs6000_sched_restricted_insns_priority == 1)
16596 /* Attach highest priority to insn. This means that in
16597 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16598 precede 'priority' (critical path) considerations. */
16599 return current_sched_info->sched_max_insns_priority;
16600 else if (rs6000_sched_restricted_insns_priority == 2)
16601 /* Increase priority of insn by a minimal amount. This means that in
16602 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16603 considerations precede dispatch-slot restriction considerations. */
16604 return (priority + 1);
16610 /* Return how many instructions the machine can issue per cycle. */
16613 rs6000_issue_rate (void)
16615 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16616 if (!reload_completed)
16619 switch (rs6000_cpu_attr) {
16620 case CPU_RIOS1: /* ? */
16622 case CPU_PPC601: /* ? */
16645 /* Return how many instructions to look ahead for better insn
16649 rs6000_use_sched_lookahead (void)
16651 if (rs6000_cpu_attr == CPU_PPC8540)
16656 /* Determine is PAT refers to memory. */
16659 is_mem_ref (rtx pat)
16665 if (GET_CODE (pat) == MEM)
16668 /* Recursively process the pattern. */
16669 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16671 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16674 ret |= is_mem_ref (XEXP (pat, i));
16675 else if (fmt[i] == 'E')
16676 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16677 ret |= is_mem_ref (XVECEXP (pat, i, j));
16683 /* Determine if PAT is a PATTERN of a load insn. */
16686 is_load_insn1 (rtx pat)
16688 if (!pat || pat == NULL_RTX)
16691 if (GET_CODE (pat) == SET)
16692 return is_mem_ref (SET_SRC (pat));
16694 if (GET_CODE (pat) == PARALLEL)
16698 for (i = 0; i < XVECLEN (pat, 0); i++)
16699 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16706 /* Determine if INSN loads from memory. */
16709 is_load_insn (rtx insn)
16711 if (!insn || !INSN_P (insn))
16714 if (GET_CODE (insn) == CALL_INSN)
16717 return is_load_insn1 (PATTERN (insn));
16720 /* Determine if PAT is a PATTERN of a store insn. */
16723 is_store_insn1 (rtx pat)
16725 if (!pat || pat == NULL_RTX)
16728 if (GET_CODE (pat) == SET)
16729 return is_mem_ref (SET_DEST (pat));
16731 if (GET_CODE (pat) == PARALLEL)
16735 for (i = 0; i < XVECLEN (pat, 0); i++)
16736 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16743 /* Determine if INSN stores to memory. */
16746 is_store_insn (rtx insn)
16748 if (!insn || !INSN_P (insn))
16751 return is_store_insn1 (PATTERN (insn));
16754 /* Returns whether the dependence between INSN and NEXT is considered
16755 costly by the given target. */
16758 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16761 /* If the flag is not enabled - no dependence is considered costly;
16762 allow all dependent insns in the same group.
16763 This is the most aggressive option. */
16764 if (rs6000_sched_costly_dep == no_dep_costly)
16767 /* If the flag is set to 1 - a dependence is always considered costly;
16768 do not allow dependent instructions in the same group.
16769 This is the most conservative option. */
16770 if (rs6000_sched_costly_dep == all_deps_costly)
16773 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16774 && is_load_insn (next)
16775 && is_store_insn (insn))
16776 /* Prevent load after store in the same group. */
16779 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16780 && is_load_insn (next)
16781 && is_store_insn (insn)
16782 && (!link || (int) REG_NOTE_KIND (link) == 0))
16783 /* Prevent load after store in the same group if it is a true
16787 /* The flag is set to X; dependences with latency >= X are considered costly,
16788 and will not be scheduled in the same group. */
16789 if (rs6000_sched_costly_dep <= max_dep_latency
16790 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16796 /* Return the next insn after INSN that is found before TAIL is reached,
16797 skipping any "non-active" insns - insns that will not actually occupy
16798 an issue slot. Return NULL_RTX if such an insn is not found. */
16801 get_next_active_insn (rtx insn, rtx tail)
16803 if (insn == NULL_RTX || insn == tail)
16808 insn = NEXT_INSN (insn);
16809 if (insn == NULL_RTX || insn == tail)
16814 || (NONJUMP_INSN_P (insn)
16815 && GET_CODE (PATTERN (insn)) != USE
16816 && GET_CODE (PATTERN (insn)) != CLOBBER
16817 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16823 /* Return whether the presence of INSN causes a dispatch group termination
16824 of group WHICH_GROUP.
16826 If WHICH_GROUP == current_group, this function will return true if INSN
16827 causes the termination of the current group (i.e, the dispatch group to
16828 which INSN belongs). This means that INSN will be the last insn in the
16829 group it belongs to.
16831 If WHICH_GROUP == previous_group, this function will return true if INSN
16832 causes the termination of the previous group (i.e, the dispatch group that
16833 precedes the group to which INSN belongs). This means that INSN will be
16834 the first insn in the group it belongs to). */
16837 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16839 enum attr_type type;
16844 type = get_attr_type (insn);
16846 if (is_microcoded_insn (insn))
16849 if (which_group == current_group)
16851 if (is_branch_slot_insn (insn))
16855 else if (which_group == previous_group)
16857 if (is_dispatch_slot_restricted (insn))
16865 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16866 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16869 is_costly_group (rtx *group_insns, rtx next_insn)
16874 int issue_rate = rs6000_issue_rate ();
16876 for (i = 0; i < issue_rate; i++)
16878 rtx insn = group_insns[i];
16881 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16883 rtx next = XEXP (link, 0);
16884 if (next == next_insn)
16886 cost = insn_cost (insn, link, next_insn);
16887 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16896 /* Utility of the function redefine_groups.
16897 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16898 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16899 to keep it "far" (in a separate group) from GROUP_INSNS, following
16900 one of the following schemes, depending on the value of the flag
16901 -minsert_sched_nops = X:
16902 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16903 in order to force NEXT_INSN into a separate group.
16904 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16905 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16906 insertion (has a group just ended, how many vacant issue slots remain in the
16907 last group, and how many dispatch groups were encountered so far). */
16910 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16911 rtx next_insn, bool *group_end, int can_issue_more,
16916 int issue_rate = rs6000_issue_rate ();
16917 bool end = *group_end;
16920 if (next_insn == NULL_RTX)
16921 return can_issue_more;
16923 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16924 return can_issue_more;
16926 force = is_costly_group (group_insns, next_insn);
16928 return can_issue_more;
16930 if (sched_verbose > 6)
16931 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16932 *group_count ,can_issue_more);
16934 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16937 can_issue_more = 0;
16939 /* Since only a branch can be issued in the last issue_slot, it is
16940 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16941 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16942 in this case the last nop will start a new group and the branch
16943 will be forced to the new group. */
16944 if (can_issue_more && !is_branch_slot_insn (next_insn))
16947 while (can_issue_more > 0)
16950 emit_insn_before (nop, next_insn);
16958 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16960 int n_nops = rs6000_sched_insert_nops;
16962 /* Nops can't be issued from the branch slot, so the effective
16963 issue_rate for nops is 'issue_rate - 1'. */
16964 if (can_issue_more == 0)
16965 can_issue_more = issue_rate;
16967 if (can_issue_more == 0)
16969 can_issue_more = issue_rate - 1;
16972 for (i = 0; i < issue_rate; i++)
16974 group_insns[i] = 0;
16981 emit_insn_before (nop, next_insn);
16982 if (can_issue_more == issue_rate - 1) /* new group begins */
16985 if (can_issue_more == 0)
16987 can_issue_more = issue_rate - 1;
16990 for (i = 0; i < issue_rate; i++)
16992 group_insns[i] = 0;
16998 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
17001 /* Is next_insn going to start a new group? */
17004 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17005 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17006 || (can_issue_more < issue_rate &&
17007 insn_terminates_group_p (next_insn, previous_group)));
17008 if (*group_end && end)
17011 if (sched_verbose > 6)
17012 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
17013 *group_count, can_issue_more);
17014 return can_issue_more;
17017 return can_issue_more;
17020 /* This function tries to synch the dispatch groups that the compiler "sees"
17021 with the dispatch groups that the processor dispatcher is expected to
17022 form in practice. It tries to achieve this synchronization by forcing the
17023 estimated processor grouping on the compiler (as opposed to the function
17024 'pad_goups' which tries to force the scheduler's grouping on the processor).
17026 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
17027 examines the (estimated) dispatch groups that will be formed by the processor
17028 dispatcher. It marks these group boundaries to reflect the estimated
17029 processor grouping, overriding the grouping that the scheduler had marked.
17030 Depending on the value of the flag '-minsert-sched-nops' this function can
17031 force certain insns into separate groups or force a certain distance between
17032 them by inserting nops, for example, if there exists a "costly dependence"
17035 The function estimates the group boundaries that the processor will form as
17036 follows: It keeps track of how many vacant issue slots are available after
17037 each insn. A subsequent insn will start a new group if one of the following
17039 - no more vacant issue slots remain in the current dispatch group.
17040 - only the last issue slot, which is the branch slot, is vacant, but the next
17041 insn is not a branch.
17042 - only the last 2 or less issue slots, including the branch slot, are vacant,
17043 which means that a cracked insn (which occupies two issue slots) can't be
17044 issued in this group.
17045 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17046 start a new group. */
17049 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17051 rtx insn, next_insn;
17053 int can_issue_more;
17056 int group_count = 0;
17060 issue_rate = rs6000_issue_rate ();
17061 group_insns = alloca (issue_rate * sizeof (rtx));
17062 for (i = 0; i < issue_rate; i++)
17064 group_insns[i] = 0;
17066 can_issue_more = issue_rate;
17068 insn = get_next_active_insn (prev_head_insn, tail);
17071 while (insn != NULL_RTX)
17073 slot = (issue_rate - can_issue_more);
17074 group_insns[slot] = insn;
17076 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17077 if (insn_terminates_group_p (insn, current_group))
17078 can_issue_more = 0;
17080 next_insn = get_next_active_insn (insn, tail);
17081 if (next_insn == NULL_RTX)
17082 return group_count + 1;
17084 /* Is next_insn going to start a new group? */
17086 = (can_issue_more == 0
17087 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17088 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17089 || (can_issue_more < issue_rate &&
17090 insn_terminates_group_p (next_insn, previous_group)));
17092 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17093 next_insn, &group_end, can_issue_more,
17099 can_issue_more = 0;
17100 for (i = 0; i < issue_rate; i++)
17102 group_insns[i] = 0;
17106 if (GET_MODE (next_insn) == TImode && can_issue_more)
17107 PUT_MODE (next_insn, VOIDmode);
17108 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17109 PUT_MODE (next_insn, TImode);
17112 if (can_issue_more == 0)
17113 can_issue_more = issue_rate;
17116 return group_count;
17119 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17120 dispatch group boundaries that the scheduler had marked. Pad with nops
17121 any dispatch groups which have vacant issue slots, in order to force the
17122 scheduler's grouping on the processor dispatcher. The function
17123 returns the number of dispatch groups found. */
17126 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17128 rtx insn, next_insn;
17131 int can_issue_more;
17133 int group_count = 0;
17135 /* Initialize issue_rate. */
17136 issue_rate = rs6000_issue_rate ();
17137 can_issue_more = issue_rate;
17139 insn = get_next_active_insn (prev_head_insn, tail);
17140 next_insn = get_next_active_insn (insn, tail);
17142 while (insn != NULL_RTX)
17145 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17147 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17149 if (next_insn == NULL_RTX)
17154 /* If the scheduler had marked group termination at this location
17155 (between insn and next_indn), and neither insn nor next_insn will
17156 force group termination, pad the group with nops to force group
17159 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17160 && !insn_terminates_group_p (insn, current_group)
17161 && !insn_terminates_group_p (next_insn, previous_group))
17163 if (!is_branch_slot_insn (next_insn))
17166 while (can_issue_more)
17169 emit_insn_before (nop, next_insn);
17174 can_issue_more = issue_rate;
17179 next_insn = get_next_active_insn (insn, tail);
17182 return group_count;
17185 /* The following function is called at the end of scheduling BB.
17186 After reload, it inserts nops at insn group bundling. */
17189 rs6000_sched_finish (FILE *dump, int sched_verbose)
17194 fprintf (dump, "=== Finishing schedule.\n");
17196 if (reload_completed && rs6000_sched_groups)
17198 if (rs6000_sched_insert_nops == sched_finish_none)
17201 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17202 n_groups = pad_groups (dump, sched_verbose,
17203 current_sched_info->prev_head,
17204 current_sched_info->next_tail);
17206 n_groups = redefine_groups (dump, sched_verbose,
17207 current_sched_info->prev_head,
17208 current_sched_info->next_tail);
17210 if (sched_verbose >= 6)
17212 fprintf (dump, "ngroups = %d\n", n_groups);
17213 print_rtl (dump, current_sched_info->prev_head);
17214 fprintf (dump, "Done finish_sched\n");
17219 /* Length in units of the trampoline for entering a nested function. */
17222 rs6000_trampoline_size (void)
17226 switch (DEFAULT_ABI)
17229 gcc_unreachable ();
17232 ret = (TARGET_32BIT) ? 12 : 24;
17237 ret = (TARGET_32BIT) ? 40 : 48;
17244 /* Emit RTL insns to initialize the variable parts of a trampoline.
17245 FNADDR is an RTX for the address of the function's pure code.
17246 CXT is an RTX for the static chain value for the function. */
17249 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17251 enum machine_mode pmode = Pmode;
17252 int regsize = (TARGET_32BIT) ? 4 : 8;
17253 rtx ctx_reg = force_reg (pmode, cxt);
17255 switch (DEFAULT_ABI)
17258 gcc_unreachable ();
17260 /* Macros to shorten the code expansions below. */
17261 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17262 #define MEM_PLUS(addr,offset) \
17263 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17265 /* Under AIX, just build the 3 word function descriptor */
17268 rtx fn_reg = gen_reg_rtx (pmode);
17269 rtx toc_reg = gen_reg_rtx (pmode);
17270 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17271 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17272 emit_move_insn (MEM_DEREF (addr), fn_reg);
17273 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17274 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17278 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17281 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17282 FALSE, VOIDmode, 4,
17284 GEN_INT (rs6000_trampoline_size ()), SImode,
17294 /* Table of valid machine attributes. */
17296 const struct attribute_spec rs6000_attribute_table[] =
17298 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17299 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17300 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17301 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17302 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17303 SUBTARGET_ATTRIBUTE_TABLE,
17305 { NULL, 0, 0, false, false, false, NULL }
17308 /* Handle the "altivec" attribute. The attribute may have
17309 arguments as follows:
17311 __attribute__((altivec(vector__)))
17312 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17313 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17315 and may appear more than once (e.g., 'vector bool char') in a
17316 given declaration. */
17319 rs6000_handle_altivec_attribute (tree *node,
17320 tree name ATTRIBUTE_UNUSED,
17322 int flags ATTRIBUTE_UNUSED,
17323 bool *no_add_attrs)
17325 tree type = *node, result = NULL_TREE;
17326 enum machine_mode mode;
17329 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17330 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17331 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17334 while (POINTER_TYPE_P (type)
17335 || TREE_CODE (type) == FUNCTION_TYPE
17336 || TREE_CODE (type) == METHOD_TYPE
17337 || TREE_CODE (type) == ARRAY_TYPE)
17338 type = TREE_TYPE (type);
17340 mode = TYPE_MODE (type);
17342 /* Check for invalid AltiVec type qualifiers. */
17343 if (type == long_unsigned_type_node || type == long_integer_type_node)
17346 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17347 else if (rs6000_warn_altivec_long)
17348 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17350 else if (type == long_long_unsigned_type_node
17351 || type == long_long_integer_type_node)
17352 error ("use of %<long long%> in AltiVec types is invalid");
17353 else if (type == double_type_node)
17354 error ("use of %<double%> in AltiVec types is invalid");
17355 else if (type == long_double_type_node)
17356 error ("use of %<long double%> in AltiVec types is invalid");
17357 else if (type == boolean_type_node)
17358 error ("use of boolean types in AltiVec types is invalid");
17359 else if (TREE_CODE (type) == COMPLEX_TYPE)
17360 error ("use of %<complex%> in AltiVec types is invalid");
17361 else if (DECIMAL_FLOAT_MODE_P (mode))
17362 error ("use of decimal floating point types in AltiVec types is invalid");
17364 switch (altivec_type)
17367 unsigned_p = TYPE_UNSIGNED (type);
17371 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17374 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17377 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17379 case SFmode: result = V4SF_type_node; break;
17380 /* If the user says 'vector int bool', we may be handed the 'bool'
17381 attribute _before_ the 'vector' attribute, and so select the
17382 proper type in the 'b' case below. */
17383 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17391 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17392 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17393 case QImode: case V16QImode: result = bool_V16QI_type_node;
17400 case V8HImode: result = pixel_V8HI_type_node;
17406 if (result && result != type && TYPE_READONLY (type))
17407 result = build_qualified_type (result, TYPE_QUAL_CONST);
17409 *no_add_attrs = true; /* No need to hang on to the attribute. */
17412 *node = reconstruct_complex_type (*node, result);
17417 /* AltiVec defines four built-in scalar types that serve as vector
17418 elements; we must teach the compiler how to mangle them. */
17420 static const char *
17421 rs6000_mangle_fundamental_type (tree type)
17423 if (type == bool_char_type_node) return "U6__boolc";
17424 if (type == bool_short_type_node) return "U6__bools";
17425 if (type == pixel_type_node) return "u7__pixel";
17426 if (type == bool_int_type_node) return "U6__booli";
17428 /* Mangle IBM extended float long double as `g' (__float128) on
17429 powerpc*-linux where long-double-64 previously was the default. */
17430 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
17432 && TARGET_LONG_DOUBLE_128
17433 && !TARGET_IEEEQUAD)
17436 /* For all other types, use normal C++ mangling. */
17440 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17441 struct attribute_spec.handler. */
17444 rs6000_handle_longcall_attribute (tree *node, tree name,
17445 tree args ATTRIBUTE_UNUSED,
17446 int flags ATTRIBUTE_UNUSED,
17447 bool *no_add_attrs)
17449 if (TREE_CODE (*node) != FUNCTION_TYPE
17450 && TREE_CODE (*node) != FIELD_DECL
17451 && TREE_CODE (*node) != TYPE_DECL)
17453 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17454 IDENTIFIER_POINTER (name));
17455 *no_add_attrs = true;
17461 /* Set longcall attributes on all functions declared when
17462 rs6000_default_long_calls is true. */
17464 rs6000_set_default_type_attributes (tree type)
17466 if (rs6000_default_long_calls
17467 && (TREE_CODE (type) == FUNCTION_TYPE
17468 || TREE_CODE (type) == METHOD_TYPE))
17469 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17471 TYPE_ATTRIBUTES (type));
17474 /* Return a reference suitable for calling a function with the
17475 longcall attribute. */
17478 rs6000_longcall_ref (rtx call_ref)
17480 const char *call_name;
17483 if (GET_CODE (call_ref) != SYMBOL_REF)
17486 /* System V adds '.' to the internal name, so skip them. */
17487 call_name = XSTR (call_ref, 0);
17488 if (*call_name == '.')
17490 while (*call_name == '.')
17493 node = get_identifier (call_name);
17494 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17497 return force_reg (Pmode, call_ref);
17500 #ifdef USING_ELFOS_H
17502 /* A get_unnamed_section callback, used for switching to toc_section. */
17505 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17507 if (DEFAULT_ABI == ABI_AIX
17508 && TARGET_MINIMAL_TOC
17509 && !TARGET_RELOCATABLE)
17511 if (!toc_initialized)
17513 toc_initialized = 1;
17514 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17515 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17516 fprintf (asm_out_file, "\t.tc ");
17517 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17518 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17519 fprintf (asm_out_file, "\n");
17521 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17522 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17523 fprintf (asm_out_file, " = .+32768\n");
17526 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17528 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17529 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17532 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17533 if (!toc_initialized)
17535 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17536 fprintf (asm_out_file, " = .+32768\n");
17537 toc_initialized = 1;
17542 /* Implement TARGET_ASM_INIT_SECTIONS. */
17545 rs6000_elf_asm_init_sections (void)
17548 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17551 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17552 SDATA2_SECTION_ASM_OP);
17555 /* Implement TARGET_SELECT_RTX_SECTION. */
17558 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17559 unsigned HOST_WIDE_INT align)
17561 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17562 return toc_section;
17564 return default_elf_select_rtx_section (mode, x, align);
17567 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17570 rs6000_elf_select_section (tree decl, int reloc,
17571 unsigned HOST_WIDE_INT align)
17573 /* Pretend that we're always building for a shared library when
17574 ABI_AIX, because otherwise we end up with dynamic relocations
17575 in read-only sections. This happens for function pointers,
17576 references to vtables in typeinfo, and probably other cases. */
17577 return default_elf_select_section_1 (decl, reloc, align,
17578 flag_pic || DEFAULT_ABI == ABI_AIX);
17581 /* A C statement to build up a unique section name, expressed as a
17582 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17583 RELOC indicates whether the initial value of EXP requires
17584 link-time relocations. If you do not define this macro, GCC will use
17585 the symbol name prefixed by `.' as the section name. Note - this
17586 macro can now be called for uninitialized data items as well as
17587 initialized data and functions. */
17590 rs6000_elf_unique_section (tree decl, int reloc)
17592 /* As above, pretend that we're always building for a shared library
17593 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17594 default_unique_section_1 (decl, reloc,
17595 flag_pic || DEFAULT_ABI == ABI_AIX);
17598 /* For a SYMBOL_REF, set generic flags and then perform some
17599 target-specific processing.
17601 When the AIX ABI is requested on a non-AIX system, replace the
17602 function name with the real name (with a leading .) rather than the
17603 function descriptor name. This saves a lot of overriding code to
17604 read the prefixes. */
17607 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17609 default_encode_section_info (decl, rtl, first);
17612 && TREE_CODE (decl) == FUNCTION_DECL
17614 && DEFAULT_ABI == ABI_AIX)
17616 rtx sym_ref = XEXP (rtl, 0);
17617 size_t len = strlen (XSTR (sym_ref, 0));
17618 char *str = alloca (len + 2);
17620 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17621 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17626 rs6000_elf_in_small_data_p (tree decl)
17628 if (rs6000_sdata == SDATA_NONE)
17631 /* We want to merge strings, so we never consider them small data. */
17632 if (TREE_CODE (decl) == STRING_CST)
17635 /* Functions are never in the small data area. */
17636 if (TREE_CODE (decl) == FUNCTION_DECL)
17639 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17641 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17642 if (strcmp (section, ".sdata") == 0
17643 || strcmp (section, ".sdata2") == 0
17644 || strcmp (section, ".sbss") == 0
17645 || strcmp (section, ".sbss2") == 0
17646 || strcmp (section, ".PPC.EMB.sdata0") == 0
17647 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17652 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17655 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17656 /* If it's not public, and we're not going to reference it there,
17657 there's no need to put it in the small data section. */
17658 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17665 #endif /* USING_ELFOS_H */
17667 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
17670 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
17672 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
17675 /* Return a REG that occurs in ADDR with coefficient 1.
17676 ADDR can be effectively incremented by incrementing REG.
17678 r0 is special and we must not select it as an address
17679 register by this routine since our caller will try to
17680 increment the returned register via an "la" instruction. */
17683 find_addr_reg (rtx addr)
17685 while (GET_CODE (addr) == PLUS)
17687 if (GET_CODE (XEXP (addr, 0)) == REG
17688 && REGNO (XEXP (addr, 0)) != 0)
17689 addr = XEXP (addr, 0);
17690 else if (GET_CODE (XEXP (addr, 1)) == REG
17691 && REGNO (XEXP (addr, 1)) != 0)
17692 addr = XEXP (addr, 1);
17693 else if (CONSTANT_P (XEXP (addr, 0)))
17694 addr = XEXP (addr, 1);
17695 else if (CONSTANT_P (XEXP (addr, 1)))
17696 addr = XEXP (addr, 0);
17698 gcc_unreachable ();
17700 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17705 rs6000_fatal_bad_address (rtx op)
17707 fatal_insn ("bad address", op);
17712 static tree branch_island_list = 0;
17714 /* Remember to generate a branch island for far calls to the given
17718 add_compiler_branch_island (tree label_name, tree function_name,
17721 tree branch_island = build_tree_list (function_name, label_name);
17722 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17723 TREE_CHAIN (branch_island) = branch_island_list;
17724 branch_island_list = branch_island;
17727 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17728 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17729 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17730 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17732 /* Generate far-jump branch islands for everything on the
17733 branch_island_list. Invoked immediately after the last instruction
17734 of the epilogue has been emitted; the branch-islands must be
17735 appended to, and contiguous with, the function body. Mach-O stubs
17736 are generated in machopic_output_stub(). */
17739 macho_branch_islands (void)
17742 tree branch_island;
17744 for (branch_island = branch_island_list;
17746 branch_island = TREE_CHAIN (branch_island))
17748 const char *label =
17749 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17751 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17752 char name_buf[512];
17753 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17754 if (name[0] == '*' || name[0] == '&')
17755 strcpy (name_buf, name+1);
17759 strcpy (name_buf+1, name);
17761 strcpy (tmp_buf, "\n");
17762 strcat (tmp_buf, label);
17763 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17764 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17765 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17766 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17769 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17770 strcat (tmp_buf, label);
17771 strcat (tmp_buf, "_pic\n");
17772 strcat (tmp_buf, label);
17773 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17775 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17776 strcat (tmp_buf, name_buf);
17777 strcat (tmp_buf, " - ");
17778 strcat (tmp_buf, label);
17779 strcat (tmp_buf, "_pic)\n");
17781 strcat (tmp_buf, "\tmtlr r0\n");
17783 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17784 strcat (tmp_buf, name_buf);
17785 strcat (tmp_buf, " - ");
17786 strcat (tmp_buf, label);
17787 strcat (tmp_buf, "_pic)\n");
17789 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17793 strcat (tmp_buf, ":\nlis r12,hi16(");
17794 strcat (tmp_buf, name_buf);
17795 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17796 strcat (tmp_buf, name_buf);
17797 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17799 output_asm_insn (tmp_buf, 0);
17800 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17801 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17802 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17803 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17806 branch_island_list = 0;
17809 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17810 already there or not. */
17813 no_previous_def (tree function_name)
17815 tree branch_island;
17816 for (branch_island = branch_island_list;
17818 branch_island = TREE_CHAIN (branch_island))
17819 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17824 /* GET_PREV_LABEL gets the label name from the previous definition of
17828 get_prev_label (tree function_name)
17830 tree branch_island;
17831 for (branch_island = branch_island_list;
17833 branch_island = TREE_CHAIN (branch_island))
17834 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17835 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17839 /* INSN is either a function call or a millicode call. It may have an
17840 unconditional jump in its delay slot.
17842 CALL_DEST is the routine we are calling. */
17845 output_call (rtx insn, rtx *operands, int dest_operand_number,
17846 int cookie_operand_number)
17848 static char buf[256];
17849 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17850 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17853 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17855 if (no_previous_def (funname))
17857 int line_number = 0;
17858 rtx label_rtx = gen_label_rtx ();
17859 char *label_buf, temp_buf[256];
17860 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17861 CODE_LABEL_NUMBER (label_rtx));
17862 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17863 labelname = get_identifier (label_buf);
17864 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17866 line_number = NOTE_LINE_NUMBER (insn);
17867 add_compiler_branch_island (labelname, funname, line_number);
17870 labelname = get_prev_label (funname);
17872 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17873 instruction will reach 'foo', otherwise link as 'bl L42'".
17874 "L42" should be a 'branch island', that will do a far jump to
17875 'foo'. Branch islands are generated in
17876 macho_branch_islands(). */
17877 sprintf (buf, "jbsr %%z%d,%.246s",
17878 dest_operand_number, IDENTIFIER_POINTER (labelname));
17881 sprintf (buf, "bl %%z%d", dest_operand_number);
17885 /* Generate PIC and indirect symbol stubs. */
17888 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17890 unsigned int length;
17891 char *symbol_name, *lazy_ptr_name;
17892 char *local_label_0;
17893 static int label = 0;
17895 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17896 symb = (*targetm.strip_name_encoding) (symb);
17899 length = strlen (symb);
17900 symbol_name = alloca (length + 32);
17901 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17903 lazy_ptr_name = alloca (length + 32);
17904 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17907 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
17909 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
17913 fprintf (file, "\t.align 5\n");
17915 fprintf (file, "%s:\n", stub);
17916 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17919 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17920 sprintf (local_label_0, "\"L%011d$spb\"", label);
17922 fprintf (file, "\tmflr r0\n");
17923 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17924 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17925 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17926 lazy_ptr_name, local_label_0);
17927 fprintf (file, "\tmtlr r0\n");
17928 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17929 (TARGET_64BIT ? "ldu" : "lwzu"),
17930 lazy_ptr_name, local_label_0);
17931 fprintf (file, "\tmtctr r12\n");
17932 fprintf (file, "\tbctr\n");
17936 fprintf (file, "\t.align 4\n");
17938 fprintf (file, "%s:\n", stub);
17939 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17941 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17942 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17943 (TARGET_64BIT ? "ldu" : "lwzu"),
17945 fprintf (file, "\tmtctr r12\n");
17946 fprintf (file, "\tbctr\n");
17949 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
17950 fprintf (file, "%s:\n", lazy_ptr_name);
17951 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17952 fprintf (file, "%sdyld_stub_binding_helper\n",
17953 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17956 /* Legitimize PIC addresses. If the address is already
17957 position-independent, we return ORIG. Newly generated
17958 position-independent addresses go into a reg. This is REG if non
17959 zero, otherwise we allocate register(s) as necessary. */
17961 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17964 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17969 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17970 reg = gen_reg_rtx (Pmode);
17972 if (GET_CODE (orig) == CONST)
17976 if (GET_CODE (XEXP (orig, 0)) == PLUS
17977 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17980 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17982 /* Use a different reg for the intermediate value, as
17983 it will be marked UNCHANGING. */
17984 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17985 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17988 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17991 if (GET_CODE (offset) == CONST_INT)
17993 if (SMALL_INT (offset))
17994 return plus_constant (base, INTVAL (offset));
17995 else if (! reload_in_progress && ! reload_completed)
17996 offset = force_reg (Pmode, offset);
17999 rtx mem = force_const_mem (Pmode, orig);
18000 return machopic_legitimize_pic_address (mem, Pmode, reg);
18003 return gen_rtx_PLUS (Pmode, base, offset);
18006 /* Fall back on generic machopic code. */
18007 return machopic_legitimize_pic_address (orig, mode, reg);
18010 /* Output a .machine directive for the Darwin assembler, and call
18011 the generic start_file routine. */
18014 rs6000_darwin_file_start (void)
18016 static const struct
18022 { "ppc64", "ppc64", MASK_64BIT },
18023 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
18024 { "power4", "ppc970", 0 },
18025 { "G5", "ppc970", 0 },
18026 { "7450", "ppc7450", 0 },
18027 { "7400", "ppc7400", MASK_ALTIVEC },
18028 { "G4", "ppc7400", 0 },
18029 { "750", "ppc750", 0 },
18030 { "740", "ppc750", 0 },
18031 { "G3", "ppc750", 0 },
18032 { "604e", "ppc604e", 0 },
18033 { "604", "ppc604", 0 },
18034 { "603e", "ppc603", 0 },
18035 { "603", "ppc603", 0 },
18036 { "601", "ppc601", 0 },
18037 { NULL, "ppc", 0 } };
18038 const char *cpu_id = "";
18041 rs6000_file_start ();
18043 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
18044 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
18045 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
18046 && rs6000_select[i].string[0] != '\0')
18047 cpu_id = rs6000_select[i].string;
18049 /* Look through the mapping array. Pick the first name that either
18050 matches the argument, has a bit set in IF_SET that is also set
18051 in the target flags, or has a NULL name. */
18054 while (mapping[i].arg != NULL
18055 && strcmp (mapping[i].arg, cpu_id) != 0
18056 && (mapping[i].if_set & target_flags) == 0)
18059 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18062 #endif /* TARGET_MACHO */
18065 static unsigned int
18066 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
18068 return default_section_type_flags_1 (decl, name, reloc,
18069 flag_pic || DEFAULT_ABI == ABI_AIX);
18072 /* Record an element in the table of global constructors. SYMBOL is
18073 a SYMBOL_REF of the function to be called; PRIORITY is a number
18074 between 0 and MAX_INIT_PRIORITY.
18076 This differs from default_named_section_asm_out_constructor in
18077 that we have special handling for -mrelocatable. */
18080 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18082 const char *section = ".ctors";
18085 if (priority != DEFAULT_INIT_PRIORITY)
18087 sprintf (buf, ".ctors.%.5u",
18088 /* Invert the numbering so the linker puts us in the proper
18089 order; constructors are run from right to left, and the
18090 linker sorts in increasing order. */
18091 MAX_INIT_PRIORITY - priority);
18095 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18096 assemble_align (POINTER_SIZE);
18098 if (TARGET_RELOCATABLE)
18100 fputs ("\t.long (", asm_out_file);
18101 output_addr_const (asm_out_file, symbol);
18102 fputs (")@fixup\n", asm_out_file);
18105 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18109 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18111 const char *section = ".dtors";
18114 if (priority != DEFAULT_INIT_PRIORITY)
18116 sprintf (buf, ".dtors.%.5u",
18117 /* Invert the numbering so the linker puts us in the proper
18118 order; constructors are run from right to left, and the
18119 linker sorts in increasing order. */
18120 MAX_INIT_PRIORITY - priority);
18124 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18125 assemble_align (POINTER_SIZE);
18127 if (TARGET_RELOCATABLE)
18129 fputs ("\t.long (", asm_out_file);
18130 output_addr_const (asm_out_file, symbol);
18131 fputs (")@fixup\n", asm_out_file);
18134 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18138 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18142 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18143 ASM_OUTPUT_LABEL (file, name);
18144 fputs (DOUBLE_INT_ASM_OP, file);
18145 rs6000_output_function_entry (file, name);
18146 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18149 fputs ("\t.size\t", file);
18150 assemble_name (file, name);
18151 fputs (",24\n\t.type\t.", file);
18152 assemble_name (file, name);
18153 fputs (",@function\n", file);
18154 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18156 fputs ("\t.globl\t.", file);
18157 assemble_name (file, name);
18162 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18163 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18164 rs6000_output_function_entry (file, name);
18165 fputs (":\n", file);
18169 if (TARGET_RELOCATABLE
18170 && !TARGET_SECURE_PLT
18171 && (get_pool_size () != 0 || current_function_profile)
18176 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18178 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18179 fprintf (file, "\t.long ");
18180 assemble_name (file, buf);
18182 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18183 assemble_name (file, buf);
18187 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18188 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18190 if (DEFAULT_ABI == ABI_AIX)
18192 const char *desc_name, *orig_name;
18194 orig_name = (*targetm.strip_name_encoding) (name);
18195 desc_name = orig_name;
18196 while (*desc_name == '.')
18199 if (TREE_PUBLIC (decl))
18200 fprintf (file, "\t.globl %s\n", desc_name);
18202 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18203 fprintf (file, "%s:\n", desc_name);
18204 fprintf (file, "\t.long %s\n", orig_name);
18205 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18206 if (DEFAULT_ABI == ABI_AIX)
18207 fputs ("\t.long 0\n", file);
18208 fprintf (file, "\t.previous\n");
18210 ASM_OUTPUT_LABEL (file, name);
18214 rs6000_elf_end_indicate_exec_stack (void)
18217 file_end_indicate_exec_stack ();
18223 rs6000_xcoff_asm_output_anchor (rtx symbol)
18227 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
18228 SYMBOL_REF_BLOCK_OFFSET (symbol));
18229 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
18233 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18235 fputs (GLOBAL_ASM_OP, stream);
18236 RS6000_OUTPUT_BASENAME (stream, name);
18237 putc ('\n', stream);
18240 /* A get_unnamed_decl callback, used for read-only sections. PTR
18241 points to the section string variable. */
18244 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18246 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18247 *(const char *const *) directive);
18250 /* Likewise for read-write sections. */
18253 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18255 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18256 *(const char *const *) directive);
18259 /* A get_unnamed_section callback, used for switching to toc_section. */
18262 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18264 if (TARGET_MINIMAL_TOC)
18266 /* toc_section is always selected at least once from
18267 rs6000_xcoff_file_start, so this is guaranteed to
18268 always be defined once and only once in each file. */
18269 if (!toc_initialized)
18271 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18272 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18273 toc_initialized = 1;
18275 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18276 (TARGET_32BIT ? "" : ",3"));
18279 fputs ("\t.toc\n", asm_out_file);
18282 /* Implement TARGET_ASM_INIT_SECTIONS. */
18285 rs6000_xcoff_asm_init_sections (void)
18287 read_only_data_section
18288 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18289 &xcoff_read_only_section_name);
18291 private_data_section
18292 = get_unnamed_section (SECTION_WRITE,
18293 rs6000_xcoff_output_readwrite_section_asm_op,
18294 &xcoff_private_data_section_name);
18296 read_only_private_data_section
18297 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18298 &xcoff_private_data_section_name);
18301 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18303 readonly_data_section = read_only_data_section;
18304 exception_section = data_section;
18308 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18309 tree decl ATTRIBUTE_UNUSED)
18312 static const char * const suffix[3] = { "PR", "RO", "RW" };
18314 if (flags & SECTION_CODE)
18316 else if (flags & SECTION_WRITE)
18321 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18322 (flags & SECTION_CODE) ? "." : "",
18323 name, suffix[smclass], flags & SECTION_ENTSIZE);
18327 rs6000_xcoff_select_section (tree decl, int reloc,
18328 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18330 if (decl_readonly_section_1 (decl, reloc, 1))
18332 if (TREE_PUBLIC (decl))
18333 return read_only_data_section;
18335 return read_only_private_data_section;
18339 if (TREE_PUBLIC (decl))
18340 return data_section;
18342 return private_data_section;
18347 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18351 /* Use select_section for private and uninitialized data. */
18352 if (!TREE_PUBLIC (decl)
18353 || DECL_COMMON (decl)
18354 || DECL_INITIAL (decl) == NULL_TREE
18355 || DECL_INITIAL (decl) == error_mark_node
18356 || (flag_zero_initialized_in_bss
18357 && initializer_zerop (DECL_INITIAL (decl))))
18360 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18361 name = (*targetm.strip_name_encoding) (name);
18362 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18365 /* Select section for constant in constant pool.
18367 On RS/6000, all constants are in the private read-only data area.
18368 However, if this is being placed in the TOC it must be output as a
18372 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18373 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18375 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18376 return toc_section;
18378 return read_only_private_data_section;
18381 /* Remove any trailing [DS] or the like from the symbol name. */
18383 static const char *
18384 rs6000_xcoff_strip_name_encoding (const char *name)
18389 len = strlen (name);
18390 if (name[len - 1] == ']')
18391 return ggc_alloc_string (name, len - 4);
18396 /* Section attributes. AIX is always PIC. */
18398 static unsigned int
18399 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18401 unsigned int align;
18402 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18404 /* Align to at least UNIT size. */
18405 if (flags & SECTION_CODE)
18406 align = MIN_UNITS_PER_WORD;
18408 /* Increase alignment of large objects if not already stricter. */
18409 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18410 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18411 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18413 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18416 /* Output at beginning of assembler file.
18418 Initialize the section names for the RS/6000 at this point.
18420 Specify filename, including full path, to assembler.
18422 We want to go into the TOC section so at least one .toc will be emitted.
18423 Also, in order to output proper .bs/.es pairs, we need at least one static
18424 [RW] section emitted.
18426 Finally, declare mcount when profiling to make the assembler happy. */
18429 rs6000_xcoff_file_start (void)
18431 rs6000_gen_section_name (&xcoff_bss_section_name,
18432 main_input_filename, ".bss_");
18433 rs6000_gen_section_name (&xcoff_private_data_section_name,
18434 main_input_filename, ".rw_");
18435 rs6000_gen_section_name (&xcoff_read_only_section_name,
18436 main_input_filename, ".ro_");
18438 fputs ("\t.file\t", asm_out_file);
18439 output_quoted_string (asm_out_file, main_input_filename);
18440 fputc ('\n', asm_out_file);
18441 if (write_symbols != NO_DEBUG)
18442 switch_to_section (private_data_section);
18443 switch_to_section (text_section);
18445 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18446 rs6000_file_start ();
18449 /* Output at end of assembler file.
18450 On the RS/6000, referencing data should automatically pull in text. */
18453 rs6000_xcoff_file_end (void)
18455 switch_to_section (text_section);
18456 fputs ("_section_.text:\n", asm_out_file);
18457 switch_to_section (data_section);
18458 fputs (TARGET_32BIT
18459 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18462 #endif /* TARGET_XCOFF */
18464 /* Compute a (partial) cost for rtx X. Return true if the complete
18465 cost has been computed, and false if subexpressions should be
18466 scanned. In either case, *TOTAL contains the cost result. */
18469 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18471 enum machine_mode mode = GET_MODE (x);
18475 /* On the RS/6000, if it is valid in the insn, it is free. */
18477 if (((outer_code == SET
18478 || outer_code == PLUS
18479 || outer_code == MINUS)
18480 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18481 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18482 || (outer_code == AND
18483 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18484 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18485 mode == SImode ? 'L' : 'J'))
18486 || mask_operand (x, mode)
18488 && mask64_operand (x, DImode))))
18489 || ((outer_code == IOR || outer_code == XOR)
18490 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18491 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18492 mode == SImode ? 'L' : 'J'))))
18493 || outer_code == ASHIFT
18494 || outer_code == ASHIFTRT
18495 || outer_code == LSHIFTRT
18496 || outer_code == ROTATE
18497 || outer_code == ROTATERT
18498 || outer_code == ZERO_EXTRACT
18499 || (outer_code == MULT
18500 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18501 || ((outer_code == DIV || outer_code == UDIV
18502 || outer_code == MOD || outer_code == UMOD)
18503 && exact_log2 (INTVAL (x)) >= 0)
18504 || (outer_code == COMPARE
18505 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18506 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18507 || (outer_code == EQ
18508 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18509 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18510 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18511 mode == SImode ? 'L' : 'J'))))
18512 || (outer_code == GTU
18513 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18514 || (outer_code == LTU
18515 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18520 else if ((outer_code == PLUS
18521 && reg_or_add_cint_operand (x, VOIDmode))
18522 || (outer_code == MINUS
18523 && reg_or_sub_cint_operand (x, VOIDmode))
18524 || ((outer_code == SET
18525 || outer_code == IOR
18526 || outer_code == XOR)
18528 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18530 *total = COSTS_N_INSNS (1);
18537 && ((outer_code == AND
18538 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18539 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18540 || mask_operand (x, DImode)
18541 || mask64_operand (x, DImode)))
18542 || ((outer_code == IOR || outer_code == XOR)
18543 && CONST_DOUBLE_HIGH (x) == 0
18544 && (CONST_DOUBLE_LOW (x)
18545 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18550 else if (mode == DImode
18551 && (outer_code == SET
18552 || outer_code == IOR
18553 || outer_code == XOR)
18554 && CONST_DOUBLE_HIGH (x) == 0)
18556 *total = COSTS_N_INSNS (1);
18565 /* When optimizing for size, MEM should be slightly more expensive
18566 than generating address, e.g., (plus (reg) (const)).
18567 L1 cache latency is about two instructions. */
18568 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18576 if (mode == DFmode)
18578 if (GET_CODE (XEXP (x, 0)) == MULT)
18580 /* FNMA accounted in outer NEG. */
18581 if (outer_code == NEG)
18582 *total = rs6000_cost->dmul - rs6000_cost->fp;
18584 *total = rs6000_cost->dmul;
18587 *total = rs6000_cost->fp;
18589 else if (mode == SFmode)
18591 /* FNMA accounted in outer NEG. */
18592 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18595 *total = rs6000_cost->fp;
18598 *total = COSTS_N_INSNS (1);
18602 if (mode == DFmode)
18604 if (GET_CODE (XEXP (x, 0)) == MULT)
18606 /* FNMA accounted in outer NEG. */
18607 if (outer_code == NEG)
18610 *total = rs6000_cost->dmul;
18613 *total = rs6000_cost->fp;
18615 else if (mode == SFmode)
18617 /* FNMA accounted in outer NEG. */
18618 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18621 *total = rs6000_cost->fp;
18624 *total = COSTS_N_INSNS (1);
18628 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18629 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18631 if (INTVAL (XEXP (x, 1)) >= -256
18632 && INTVAL (XEXP (x, 1)) <= 255)
18633 *total = rs6000_cost->mulsi_const9;
18635 *total = rs6000_cost->mulsi_const;
18637 /* FMA accounted in outer PLUS/MINUS. */
18638 else if ((mode == DFmode || mode == SFmode)
18639 && (outer_code == PLUS || outer_code == MINUS))
18641 else if (mode == DFmode)
18642 *total = rs6000_cost->dmul;
18643 else if (mode == SFmode)
18644 *total = rs6000_cost->fp;
18645 else if (mode == DImode)
18646 *total = rs6000_cost->muldi;
18648 *total = rs6000_cost->mulsi;
18653 if (FLOAT_MODE_P (mode))
18655 *total = mode == DFmode ? rs6000_cost->ddiv
18656 : rs6000_cost->sdiv;
18663 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18664 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18666 if (code == DIV || code == MOD)
18668 *total = COSTS_N_INSNS (2);
18671 *total = COSTS_N_INSNS (1);
18675 if (GET_MODE (XEXP (x, 1)) == DImode)
18676 *total = rs6000_cost->divdi;
18678 *total = rs6000_cost->divsi;
18680 /* Add in shift and subtract for MOD. */
18681 if (code == MOD || code == UMOD)
18682 *total += COSTS_N_INSNS (2);
18686 *total = COSTS_N_INSNS (4);
18690 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18701 *total = COSTS_N_INSNS (1);
18709 /* Handle mul_highpart. */
18710 if (outer_code == TRUNCATE
18711 && GET_CODE (XEXP (x, 0)) == MULT)
18713 if (mode == DImode)
18714 *total = rs6000_cost->muldi;
18716 *total = rs6000_cost->mulsi;
18719 else if (outer_code == AND)
18722 *total = COSTS_N_INSNS (1);
18727 if (GET_CODE (XEXP (x, 0)) == MEM)
18730 *total = COSTS_N_INSNS (1);
18736 if (!FLOAT_MODE_P (mode))
18738 *total = COSTS_N_INSNS (1);
18744 case UNSIGNED_FLOAT:
18747 case FLOAT_TRUNCATE:
18748 *total = rs6000_cost->fp;
18752 if (mode == DFmode)
18755 *total = rs6000_cost->fp;
18759 switch (XINT (x, 1))
18762 *total = rs6000_cost->fp;
18774 *total = COSTS_N_INSNS (1);
18777 else if (FLOAT_MODE_P (mode)
18778 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18780 *total = rs6000_cost->fp;
18788 /* Carry bit requires mode == Pmode.
18789 NEG or PLUS already counted so only add one. */
18791 && (outer_code == NEG || outer_code == PLUS))
18793 *total = COSTS_N_INSNS (1);
18796 if (outer_code == SET)
18798 if (XEXP (x, 1) == const0_rtx)
18800 *total = COSTS_N_INSNS (2);
18803 else if (mode == Pmode)
18805 *total = COSTS_N_INSNS (3);
18814 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18816 *total = COSTS_N_INSNS (2);
18820 if (outer_code == COMPARE)
18834 /* A C expression returning the cost of moving data from a register of class
18835 CLASS1 to one of CLASS2. */
18838 rs6000_register_move_cost (enum machine_mode mode,
18839 enum reg_class from, enum reg_class to)
18841 /* Moves from/to GENERAL_REGS. */
18842 if (reg_classes_intersect_p (to, GENERAL_REGS)
18843 || reg_classes_intersect_p (from, GENERAL_REGS))
18845 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18848 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18849 return (rs6000_memory_move_cost (mode, from, 0)
18850 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18852 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18854 else if (from == CR_REGS)
18858 /* A move will cost one instruction per GPR moved. */
18859 return 2 * hard_regno_nregs[0][mode];
18862 /* Moving between two similar registers is just one instruction. */
18863 else if (reg_classes_intersect_p (to, from))
18864 return mode == TFmode ? 4 : 2;
18866 /* Everything else has to go through GENERAL_REGS. */
18868 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18869 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18872 /* A C expressions returning the cost of moving data of MODE from a register to
18876 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18877 int in ATTRIBUTE_UNUSED)
18879 if (reg_classes_intersect_p (class, GENERAL_REGS))
18880 return 4 * hard_regno_nregs[0][mode];
18881 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18882 return 4 * hard_regno_nregs[32][mode];
18883 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18884 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18886 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18889 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18890 Assumes no trapping math and finite arguments. */
18893 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18895 rtx x0, e0, e1, y1, u0, v0, one;
18897 x0 = gen_reg_rtx (SFmode);
18898 e0 = gen_reg_rtx (SFmode);
18899 e1 = gen_reg_rtx (SFmode);
18900 y1 = gen_reg_rtx (SFmode);
18901 u0 = gen_reg_rtx (SFmode);
18902 v0 = gen_reg_rtx (SFmode);
18903 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18905 /* x0 = 1./d estimate */
18906 emit_insn (gen_rtx_SET (VOIDmode, x0,
18907 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18909 /* e0 = 1. - d * x0 */
18910 emit_insn (gen_rtx_SET (VOIDmode, e0,
18911 gen_rtx_MINUS (SFmode, one,
18912 gen_rtx_MULT (SFmode, d, x0))));
18913 /* e1 = e0 + e0 * e0 */
18914 emit_insn (gen_rtx_SET (VOIDmode, e1,
18915 gen_rtx_PLUS (SFmode,
18916 gen_rtx_MULT (SFmode, e0, e0), e0)));
18917 /* y1 = x0 + e1 * x0 */
18918 emit_insn (gen_rtx_SET (VOIDmode, y1,
18919 gen_rtx_PLUS (SFmode,
18920 gen_rtx_MULT (SFmode, e1, x0), x0)));
18922 emit_insn (gen_rtx_SET (VOIDmode, u0,
18923 gen_rtx_MULT (SFmode, n, y1)));
18924 /* v0 = n - d * u0 */
18925 emit_insn (gen_rtx_SET (VOIDmode, v0,
18926 gen_rtx_MINUS (SFmode, n,
18927 gen_rtx_MULT (SFmode, d, u0))));
18928 /* res = u0 + v0 * y1 */
18929 emit_insn (gen_rtx_SET (VOIDmode, res,
18930 gen_rtx_PLUS (SFmode,
18931 gen_rtx_MULT (SFmode, v0, y1), u0)));
18934 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18935 Assumes no trapping math and finite arguments. */
18938 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18940 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18942 x0 = gen_reg_rtx (DFmode);
18943 e0 = gen_reg_rtx (DFmode);
18944 e1 = gen_reg_rtx (DFmode);
18945 e2 = gen_reg_rtx (DFmode);
18946 y1 = gen_reg_rtx (DFmode);
18947 y2 = gen_reg_rtx (DFmode);
18948 y3 = gen_reg_rtx (DFmode);
18949 u0 = gen_reg_rtx (DFmode);
18950 v0 = gen_reg_rtx (DFmode);
18951 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18953 /* x0 = 1./d estimate */
18954 emit_insn (gen_rtx_SET (VOIDmode, x0,
18955 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18957 /* e0 = 1. - d * x0 */
18958 emit_insn (gen_rtx_SET (VOIDmode, e0,
18959 gen_rtx_MINUS (DFmode, one,
18960 gen_rtx_MULT (SFmode, d, x0))));
18961 /* y1 = x0 + e0 * x0 */
18962 emit_insn (gen_rtx_SET (VOIDmode, y1,
18963 gen_rtx_PLUS (DFmode,
18964 gen_rtx_MULT (DFmode, e0, x0), x0)));
18966 emit_insn (gen_rtx_SET (VOIDmode, e1,
18967 gen_rtx_MULT (DFmode, e0, e0)));
18968 /* y2 = y1 + e1 * y1 */
18969 emit_insn (gen_rtx_SET (VOIDmode, y2,
18970 gen_rtx_PLUS (DFmode,
18971 gen_rtx_MULT (DFmode, e1, y1), y1)));
18973 emit_insn (gen_rtx_SET (VOIDmode, e2,
18974 gen_rtx_MULT (DFmode, e1, e1)));
18975 /* y3 = y2 + e2 * y2 */
18976 emit_insn (gen_rtx_SET (VOIDmode, y3,
18977 gen_rtx_PLUS (DFmode,
18978 gen_rtx_MULT (DFmode, e2, y2), y2)));
18980 emit_insn (gen_rtx_SET (VOIDmode, u0,
18981 gen_rtx_MULT (DFmode, n, y3)));
18982 /* v0 = n - d * u0 */
18983 emit_insn (gen_rtx_SET (VOIDmode, v0,
18984 gen_rtx_MINUS (DFmode, n,
18985 gen_rtx_MULT (DFmode, d, u0))));
18986 /* res = u0 + v0 * y3 */
18987 emit_insn (gen_rtx_SET (VOIDmode, res,
18988 gen_rtx_PLUS (DFmode,
18989 gen_rtx_MULT (DFmode, v0, y3), u0)));
18992 /* Return an RTX representing where to find the function value of a
18993 function returning MODE. */
18995 rs6000_complex_function_value (enum machine_mode mode)
18997 unsigned int regno;
18999 enum machine_mode inner = GET_MODE_INNER (mode);
19000 unsigned int inner_bytes = GET_MODE_SIZE (inner);
19002 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
19003 regno = FP_ARG_RETURN;
19006 regno = GP_ARG_RETURN;
19008 /* 32-bit is OK since it'll go in r3/r4. */
19009 if (TARGET_32BIT && inner_bytes >= 4)
19010 return gen_rtx_REG (mode, regno);
19013 if (inner_bytes >= 8)
19014 return gen_rtx_REG (mode, regno);
19016 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
19018 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
19019 GEN_INT (inner_bytes));
19020 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
19023 /* Define how to find the value returned by a function.
19024 VALTYPE is the data type of the value (as a tree).
19025 If the precise function being called is known, FUNC is its FUNCTION_DECL;
19026 otherwise, FUNC is 0.
19028 On the SPE, both FPs and vectors are returned in r3.
19030 On RS/6000 an integer value is in r3 and a floating-point value is in
19031 fp1, unless -msoft-float. */
19034 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
19036 enum machine_mode mode;
19037 unsigned int regno;
19039 /* Special handling for structs in darwin64. */
19040 if (rs6000_darwin64_abi
19041 && TYPE_MODE (valtype) == BLKmode
19042 && TREE_CODE (valtype) == RECORD_TYPE
19043 && int_size_in_bytes (valtype) > 0)
19045 CUMULATIVE_ARGS valcum;
19049 valcum.fregno = FP_ARG_MIN_REG;
19050 valcum.vregno = ALTIVEC_ARG_MIN_REG;
19051 /* Do a trial code generation as if this were going to be passed as
19052 an argument; if any part goes in memory, we return NULL. */
19053 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
19056 /* Otherwise fall through to standard ABI rules. */
19059 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
19061 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19062 return gen_rtx_PARALLEL (DImode,
19064 gen_rtx_EXPR_LIST (VOIDmode,
19065 gen_rtx_REG (SImode, GP_ARG_RETURN),
19067 gen_rtx_EXPR_LIST (VOIDmode,
19068 gen_rtx_REG (SImode,
19069 GP_ARG_RETURN + 1),
19072 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19074 return gen_rtx_PARALLEL (DCmode,
19076 gen_rtx_EXPR_LIST (VOIDmode,
19077 gen_rtx_REG (SImode, GP_ARG_RETURN),
19079 gen_rtx_EXPR_LIST (VOIDmode,
19080 gen_rtx_REG (SImode,
19081 GP_ARG_RETURN + 1),
19083 gen_rtx_EXPR_LIST (VOIDmode,
19084 gen_rtx_REG (SImode,
19085 GP_ARG_RETURN + 2),
19087 gen_rtx_EXPR_LIST (VOIDmode,
19088 gen_rtx_REG (SImode,
19089 GP_ARG_RETURN + 3),
19093 if ((INTEGRAL_TYPE_P (valtype)
19094 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
19095 || POINTER_TYPE_P (valtype))
19096 mode = TARGET_32BIT ? SImode : DImode;
19098 mode = TYPE_MODE (valtype);
19100 if (DECIMAL_FLOAT_MODE_P (mode))
19101 regno = GP_ARG_RETURN;
19102 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19103 regno = FP_ARG_RETURN;
19104 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19105 && targetm.calls.split_complex_arg)
19106 return rs6000_complex_function_value (mode);
19107 else if (TREE_CODE (valtype) == VECTOR_TYPE
19108 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19109 && ALTIVEC_VECTOR_MODE (mode))
19110 regno = ALTIVEC_ARG_RETURN;
19111 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19112 && (mode == DFmode || mode == DCmode))
19113 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19115 regno = GP_ARG_RETURN;
19117 return gen_rtx_REG (mode, regno);
19120 /* Define how to find the value returned by a library function
19121 assuming the value has mode MODE. */
19123 rs6000_libcall_value (enum machine_mode mode)
19125 unsigned int regno;
19127 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19129 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19130 return gen_rtx_PARALLEL (DImode,
19132 gen_rtx_EXPR_LIST (VOIDmode,
19133 gen_rtx_REG (SImode, GP_ARG_RETURN),
19135 gen_rtx_EXPR_LIST (VOIDmode,
19136 gen_rtx_REG (SImode,
19137 GP_ARG_RETURN + 1),
19141 if (DECIMAL_FLOAT_MODE_P (mode))
19142 regno = GP_ARG_RETURN;
19143 else if (SCALAR_FLOAT_MODE_P (mode)
19144 && TARGET_HARD_FLOAT && TARGET_FPRS)
19145 regno = FP_ARG_RETURN;
19146 else if (ALTIVEC_VECTOR_MODE (mode)
19147 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19148 regno = ALTIVEC_ARG_RETURN;
19149 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19150 return rs6000_complex_function_value (mode);
19151 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19152 && (mode == DFmode || mode == DCmode))
19153 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19155 regno = GP_ARG_RETURN;
19157 return gen_rtx_REG (mode, regno);
19160 /* Define the offset between two registers, FROM to be eliminated and its
19161 replacement TO, at the start of a routine. */
19163 rs6000_initial_elimination_offset (int from, int to)
19165 rs6000_stack_t *info = rs6000_stack_info ();
19166 HOST_WIDE_INT offset;
19168 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19169 offset = info->push_p ? 0 : -info->total_size;
19170 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19172 offset = info->push_p ? 0 : -info->total_size;
19173 if (FRAME_GROWS_DOWNWARD)
19174 offset += info->fixed_size + info->vars_size + info->parm_size;
19176 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19177 offset = FRAME_GROWS_DOWNWARD
19178 ? info->fixed_size + info->vars_size + info->parm_size
19180 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19181 offset = info->total_size;
19182 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19183 offset = info->push_p ? info->total_size : 0;
19184 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19187 gcc_unreachable ();
19192 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19195 rs6000_is_opaque_type (tree type)
19197 return (type == opaque_V2SI_type_node
19198 || type == opaque_V2SF_type_node
19199 || type == opaque_p_V2SI_type_node
19200 || type == opaque_V4SI_type_node);
19204 rs6000_dwarf_register_span (rtx reg)
19209 && (SPE_VECTOR_MODE (GET_MODE (reg))
19210 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19215 regno = REGNO (reg);
19217 /* The duality of the SPE register size wreaks all kinds of havoc.
19218 This is a way of distinguishing r0 in 32-bits from r0 in
19221 gen_rtx_PARALLEL (VOIDmode,
19224 gen_rtx_REG (SImode, regno + 1200),
19225 gen_rtx_REG (SImode, regno))
19227 gen_rtx_REG (SImode, regno),
19228 gen_rtx_REG (SImode, regno + 1200)));
19231 /* Map internal gcc register numbers to DWARF2 register numbers. */
19234 rs6000_dbx_register_number (unsigned int regno)
19236 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19238 if (regno == MQ_REGNO)
19240 if (regno == LINK_REGISTER_REGNUM)
19242 if (regno == COUNT_REGISTER_REGNUM)
19244 if (CR_REGNO_P (regno))
19245 return regno - CR0_REGNO + 86;
19246 if (regno == XER_REGNO)
19248 if (ALTIVEC_REGNO_P (regno))
19249 return regno - FIRST_ALTIVEC_REGNO + 1124;
19250 if (regno == VRSAVE_REGNO)
19252 if (regno == VSCR_REGNO)
19254 if (regno == SPE_ACC_REGNO)
19256 if (regno == SPEFSCR_REGNO)
19258 /* SPE high reg number. We get these values of regno from
19259 rs6000_dwarf_register_span. */
19260 gcc_assert (regno >= 1200 && regno < 1232);
19264 /* target hook eh_return_filter_mode */
19265 static enum machine_mode
19266 rs6000_eh_return_filter_mode (void)
19268 return TARGET_32BIT ? SImode : word_mode;
19271 /* Target hook for scalar_mode_supported_p. */
19273 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19275 if (DECIMAL_FLOAT_MODE_P (mode))
19278 return default_scalar_mode_supported_p (mode);
19281 /* Target hook for vector_mode_supported_p. */
19283 rs6000_vector_mode_supported_p (enum machine_mode mode)
19286 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19289 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19296 /* Target hook for invalid_arg_for_unprototyped_fn. */
19297 static const char *
19298 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19300 return (!rs6000_darwin64_abi
19302 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19303 && (funcdecl == NULL_TREE
19304 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19305 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19306 ? N_("AltiVec argument passed to unprototyped function")
19310 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19311 setup by using __stack_chk_fail_local hidden function instead of
19312 calling __stack_chk_fail directly. Otherwise it is better to call
19313 __stack_chk_fail directly. */
19316 rs6000_stack_protect_fail (void)
19318 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19319 ? default_hidden_stack_protect_fail ()
19320 : default_external_stack_protect_fail ();
19323 #include "gt-rs6000.h"