1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int toc_save_offset; /* offset to save the TOC pointer */
95 int varargs_save_offset; /* offset to save the varargs registers */
96 int ehrd_offset; /* offset to EH return data */
97 int reg_size; /* register size (4 or 8) */
98 int varargs_size; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size; /* variable save area size */
100 int parm_size; /* outgoing parameter size */
101 int save_size; /* save area size */
102 int fixed_size; /* fixed size of stack frame */
103 int gp_size; /* size of saved GP registers */
104 int fp_size; /* size of saved FP registers */
105 int altivec_size; /* size of saved AltiVec registers */
106 int cr_size; /* size to hold CR if not in save_size */
107 int lr_size; /* size to hold LR if not in save_size */
108 int vrsave_size; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size; /* size of altivec alignment padding if
111 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size;
113 int toc_size; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu;
121 struct rs6000_cpu_select rs6000_select[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str;
138 int rs6000_sched_restricted_insns_priority;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load;
151 /* Size of long double */
152 const char *rs6000_long_double_size_string;
153 int rs6000_long_double_type_size;
155 /* Whether -mabi=altivec has appeared */
156 int rs6000_altivec_abi;
158 /* Whether VRSAVE instructions should be generated. */
159 int rs6000_altivec_vrsave;
161 /* String from -mvrsave= option. */
162 const char *rs6000_altivec_vrsave_string;
164 /* Nonzero if we want SPE ABI extensions. */
167 /* Whether isel instructions should be generated. */
170 /* Whether SPE simd instructions should be generated. */
173 /* Nonzero if floating point operations are done in the GPRs. */
174 int rs6000_float_gprs = 0;
176 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
177 int rs6000_darwin64_abi;
179 /* String from -mfloat-gprs=. */
180 const char *rs6000_float_gprs_string;
182 /* String from -misel=. */
183 const char *rs6000_isel_string;
185 /* String from -mspe=. */
186 const char *rs6000_spe_string;
188 /* Set to nonzero once AIX common-mode calls have been defined. */
189 static GTY(()) int common_mode_defined;
191 /* Save information from a "cmpxx" operation until the branch or scc is
193 rtx rs6000_compare_op0, rs6000_compare_op1;
194 int rs6000_compare_fp_p;
196 /* Label number of label created for -mrelocatable, to call to so we can
197 get the address of the GOT section */
198 int rs6000_pic_labelno;
201 /* Which abi to adhere to */
202 const char *rs6000_abi_name;
204 /* Semantics of the small data area */
205 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
207 /* Which small data model to use */
208 const char *rs6000_sdata_name = (char *)0;
210 /* Counter for labels which are to be placed in .fixup. */
211 int fixuplabelno = 0;
214 /* Bit size of immediate TLS offsets and string from which it is decoded. */
215 int rs6000_tls_size = 32;
216 const char *rs6000_tls_size_string;
218 /* ABI enumeration available for subtarget to use. */
219 enum rs6000_abi rs6000_current_abi;
221 /* ABI string from -mabi= option. */
222 const char *rs6000_abi_string;
224 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
228 const char *rs6000_debug_name;
229 int rs6000_debug_stack; /* debug stack applications */
230 int rs6000_debug_arg; /* debug argument handling */
232 /* Value is TRUE if register/mode pair is accepatable. */
233 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
236 static GTY(()) tree opaque_V2SI_type_node;
237 static GTY(()) tree opaque_V2SF_type_node;
238 static GTY(()) tree opaque_p_V2SI_type_node;
239 static GTY(()) tree V16QI_type_node;
240 static GTY(()) tree V2SI_type_node;
241 static GTY(()) tree V2SF_type_node;
242 static GTY(()) tree V4HI_type_node;
243 static GTY(()) tree V4SI_type_node;
244 static GTY(()) tree V4SF_type_node;
245 static GTY(()) tree V8HI_type_node;
246 static GTY(()) tree unsigned_V16QI_type_node;
247 static GTY(()) tree unsigned_V8HI_type_node;
248 static GTY(()) tree unsigned_V4SI_type_node;
249 static GTY(()) tree bool_char_type_node; /* __bool char */
250 static GTY(()) tree bool_short_type_node; /* __bool short */
251 static GTY(()) tree bool_int_type_node; /* __bool int */
252 static GTY(()) tree pixel_type_node; /* __pixel */
253 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
254 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
255 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
256 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
258 int rs6000_warn_altivec_long = 1; /* On by default. */
259 const char *rs6000_warn_altivec_long_switch;
261 const char *rs6000_traceback_name;
263 traceback_default = 0,
269 /* Flag to say the TOC is initialized */
271 char toc_label_name[10];
273 /* Alias set for saves and restores from the rs6000 stack. */
274 static GTY(()) int rs6000_sr_alias_set;
276 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
277 The only place that looks at this is rs6000_set_default_type_attributes;
278 everywhere else should rely on the presence or absence of a longcall
279 attribute on the function declaration. Exception: init_cumulative_args
280 looks at it too, for libcalls. */
281 int rs6000_default_long_calls;
282 const char *rs6000_longcall_switch;
284 /* Control alignment for fields within structures. */
285 /* String from -malign-XXXXX. */
286 const char *rs6000_alignment_string;
287 int rs6000_alignment_flags;
289 struct builtin_description
291 /* mask is not const because we're going to alter it below. This
292 nonsense will go away when we rewrite the -march infrastructure
293 to give us more target flag bits. */
295 const enum insn_code icode;
296 const char *const name;
297 const enum rs6000_builtins code;
300 /* Target cpu costs. */
302 struct processor_costs {
303 const int mulsi; /* cost of SImode multiplication. */
304 const int mulsi_const; /* cost of SImode multiplication by constant. */
305 const int mulsi_const9; /* cost of SImode mult by short constant. */
306 const int muldi; /* cost of DImode multiplication. */
307 const int divsi; /* cost of SImode division. */
308 const int divdi; /* cost of DImode division. */
309 const int fp; /* cost of simple SFmode and DFmode insns. */
310 const int dmul; /* cost of DFmode multiplication (and fmadd). */
311 const int sdiv; /* cost of SFmode division (fdivs). */
312 const int ddiv; /* cost of DFmode division (fdiv). */
315 const struct processor_costs *rs6000_cost;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost = {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
334 /* Instruction size costs on 64bit processors. */
336 struct processor_costs size64_cost = {
337 COSTS_N_INSNS (1), /* mulsi */
338 COSTS_N_INSNS (1), /* mulsi_const */
339 COSTS_N_INSNS (1), /* mulsi_const9 */
340 COSTS_N_INSNS (1), /* muldi */
341 COSTS_N_INSNS (1), /* divsi */
342 COSTS_N_INSNS (1), /* divdi */
343 COSTS_N_INSNS (1), /* fp */
344 COSTS_N_INSNS (1), /* dmul */
345 COSTS_N_INSNS (1), /* sdiv */
346 COSTS_N_INSNS (1), /* ddiv */
349 /* Instruction costs on RIOS1 processors. */
351 struct processor_costs rios1_cost = {
352 COSTS_N_INSNS (5), /* mulsi */
353 COSTS_N_INSNS (4), /* mulsi_const */
354 COSTS_N_INSNS (3), /* mulsi_const9 */
355 COSTS_N_INSNS (5), /* muldi */
356 COSTS_N_INSNS (19), /* divsi */
357 COSTS_N_INSNS (19), /* divdi */
358 COSTS_N_INSNS (2), /* fp */
359 COSTS_N_INSNS (2), /* dmul */
360 COSTS_N_INSNS (19), /* sdiv */
361 COSTS_N_INSNS (19), /* ddiv */
364 /* Instruction costs on RIOS2 processors. */
366 struct processor_costs rios2_cost = {
367 COSTS_N_INSNS (2), /* mulsi */
368 COSTS_N_INSNS (2), /* mulsi_const */
369 COSTS_N_INSNS (2), /* mulsi_const9 */
370 COSTS_N_INSNS (2), /* muldi */
371 COSTS_N_INSNS (13), /* divsi */
372 COSTS_N_INSNS (13), /* divdi */
373 COSTS_N_INSNS (2), /* fp */
374 COSTS_N_INSNS (2), /* dmul */
375 COSTS_N_INSNS (17), /* sdiv */
376 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
394 /* Instruction costs on MPCCORE processors. */
396 struct processor_costs mpccore_cost = {
397 COSTS_N_INSNS (2), /* mulsi */
398 COSTS_N_INSNS (2), /* mulsi_const */
399 COSTS_N_INSNS (2), /* mulsi_const9 */
400 COSTS_N_INSNS (2), /* muldi */
401 COSTS_N_INSNS (6), /* divsi */
402 COSTS_N_INSNS (6), /* divdi */
403 COSTS_N_INSNS (4), /* fp */
404 COSTS_N_INSNS (5), /* dmul */
405 COSTS_N_INSNS (10), /* sdiv */
406 COSTS_N_INSNS (17), /* ddiv */
409 /* Instruction costs on PPC403 processors. */
411 struct processor_costs ppc403_cost = {
412 COSTS_N_INSNS (4), /* mulsi */
413 COSTS_N_INSNS (4), /* mulsi_const */
414 COSTS_N_INSNS (4), /* mulsi_const9 */
415 COSTS_N_INSNS (4), /* muldi */
416 COSTS_N_INSNS (33), /* divsi */
417 COSTS_N_INSNS (33), /* divdi */
418 COSTS_N_INSNS (11), /* fp */
419 COSTS_N_INSNS (11), /* dmul */
420 COSTS_N_INSNS (11), /* sdiv */
421 COSTS_N_INSNS (11), /* ddiv */
424 /* Instruction costs on PPC405 processors. */
426 struct processor_costs ppc405_cost = {
427 COSTS_N_INSNS (5), /* mulsi */
428 COSTS_N_INSNS (4), /* mulsi_const */
429 COSTS_N_INSNS (3), /* mulsi_const9 */
430 COSTS_N_INSNS (5), /* muldi */
431 COSTS_N_INSNS (35), /* divsi */
432 COSTS_N_INSNS (35), /* divdi */
433 COSTS_N_INSNS (11), /* fp */
434 COSTS_N_INSNS (11), /* dmul */
435 COSTS_N_INSNS (11), /* sdiv */
436 COSTS_N_INSNS (11), /* ddiv */
439 /* Instruction costs on PPC440 processors. */
441 struct processor_costs ppc440_cost = {
442 COSTS_N_INSNS (3), /* mulsi */
443 COSTS_N_INSNS (2), /* mulsi_const */
444 COSTS_N_INSNS (2), /* mulsi_const9 */
445 COSTS_N_INSNS (3), /* muldi */
446 COSTS_N_INSNS (34), /* divsi */
447 COSTS_N_INSNS (34), /* divdi */
448 COSTS_N_INSNS (5), /* fp */
449 COSTS_N_INSNS (5), /* dmul */
450 COSTS_N_INSNS (19), /* sdiv */
451 COSTS_N_INSNS (33), /* ddiv */
454 /* Instruction costs on PPC601 processors. */
456 struct processor_costs ppc601_cost = {
457 COSTS_N_INSNS (5), /* mulsi */
458 COSTS_N_INSNS (5), /* mulsi_const */
459 COSTS_N_INSNS (5), /* mulsi_const9 */
460 COSTS_N_INSNS (5), /* muldi */
461 COSTS_N_INSNS (36), /* divsi */
462 COSTS_N_INSNS (36), /* divdi */
463 COSTS_N_INSNS (4), /* fp */
464 COSTS_N_INSNS (5), /* dmul */
465 COSTS_N_INSNS (17), /* sdiv */
466 COSTS_N_INSNS (31), /* ddiv */
469 /* Instruction costs on PPC603 processors. */
471 struct processor_costs ppc603_cost = {
472 COSTS_N_INSNS (5), /* mulsi */
473 COSTS_N_INSNS (3), /* mulsi_const */
474 COSTS_N_INSNS (2), /* mulsi_const9 */
475 COSTS_N_INSNS (5), /* muldi */
476 COSTS_N_INSNS (37), /* divsi */
477 COSTS_N_INSNS (37), /* divdi */
478 COSTS_N_INSNS (3), /* fp */
479 COSTS_N_INSNS (4), /* dmul */
480 COSTS_N_INSNS (18), /* sdiv */
481 COSTS_N_INSNS (33), /* ddiv */
484 /* Instruction costs on PPC604 processors. */
486 struct processor_costs ppc604_cost = {
487 COSTS_N_INSNS (4), /* mulsi */
488 COSTS_N_INSNS (4), /* mulsi_const */
489 COSTS_N_INSNS (4), /* mulsi_const9 */
490 COSTS_N_INSNS (4), /* muldi */
491 COSTS_N_INSNS (20), /* divsi */
492 COSTS_N_INSNS (20), /* divdi */
493 COSTS_N_INSNS (3), /* fp */
494 COSTS_N_INSNS (3), /* dmul */
495 COSTS_N_INSNS (18), /* sdiv */
496 COSTS_N_INSNS (32), /* ddiv */
499 /* Instruction costs on PPC604e processors. */
501 struct processor_costs ppc604e_cost = {
502 COSTS_N_INSNS (2), /* mulsi */
503 COSTS_N_INSNS (2), /* mulsi_const */
504 COSTS_N_INSNS (2), /* mulsi_const9 */
505 COSTS_N_INSNS (2), /* muldi */
506 COSTS_N_INSNS (20), /* divsi */
507 COSTS_N_INSNS (20), /* divdi */
508 COSTS_N_INSNS (3), /* fp */
509 COSTS_N_INSNS (3), /* dmul */
510 COSTS_N_INSNS (18), /* sdiv */
511 COSTS_N_INSNS (32), /* ddiv */
514 /* Instruction costs on PPC620 processors. */
516 struct processor_costs ppc620_cost = {
517 COSTS_N_INSNS (5), /* mulsi */
518 COSTS_N_INSNS (4), /* mulsi_const */
519 COSTS_N_INSNS (3), /* mulsi_const9 */
520 COSTS_N_INSNS (7), /* muldi */
521 COSTS_N_INSNS (21), /* divsi */
522 COSTS_N_INSNS (37), /* divdi */
523 COSTS_N_INSNS (3), /* fp */
524 COSTS_N_INSNS (3), /* dmul */
525 COSTS_N_INSNS (18), /* sdiv */
526 COSTS_N_INSNS (32), /* ddiv */
529 /* Instruction costs on PPC630 processors. */
531 struct processor_costs ppc630_cost = {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (4), /* mulsi_const */
534 COSTS_N_INSNS (3), /* mulsi_const9 */
535 COSTS_N_INSNS (7), /* muldi */
536 COSTS_N_INSNS (21), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (3), /* dmul */
540 COSTS_N_INSNS (17), /* sdiv */
541 COSTS_N_INSNS (21), /* ddiv */
544 /* Instruction costs on PPC750 and PPC7400 processors. */
546 struct processor_costs ppc750_cost = {
547 COSTS_N_INSNS (5), /* mulsi */
548 COSTS_N_INSNS (3), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (5), /* muldi */
551 COSTS_N_INSNS (17), /* divsi */
552 COSTS_N_INSNS (17), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (17), /* sdiv */
556 COSTS_N_INSNS (31), /* ddiv */
559 /* Instruction costs on PPC7450 processors. */
561 struct processor_costs ppc7450_cost = {
562 COSTS_N_INSNS (4), /* mulsi */
563 COSTS_N_INSNS (3), /* mulsi_const */
564 COSTS_N_INSNS (3), /* mulsi_const9 */
565 COSTS_N_INSNS (4), /* muldi */
566 COSTS_N_INSNS (23), /* divsi */
567 COSTS_N_INSNS (23), /* divdi */
568 COSTS_N_INSNS (5), /* fp */
569 COSTS_N_INSNS (5), /* dmul */
570 COSTS_N_INSNS (21), /* sdiv */
571 COSTS_N_INSNS (35), /* ddiv */
574 /* Instruction costs on PPC8540 processors. */
576 struct processor_costs ppc8540_cost = {
577 COSTS_N_INSNS (4), /* mulsi */
578 COSTS_N_INSNS (4), /* mulsi_const */
579 COSTS_N_INSNS (4), /* mulsi_const9 */
580 COSTS_N_INSNS (4), /* muldi */
581 COSTS_N_INSNS (19), /* divsi */
582 COSTS_N_INSNS (19), /* divdi */
583 COSTS_N_INSNS (4), /* fp */
584 COSTS_N_INSNS (4), /* dmul */
585 COSTS_N_INSNS (29), /* sdiv */
586 COSTS_N_INSNS (29), /* ddiv */
589 /* Instruction costs on POWER4 and POWER5 processors. */
591 struct processor_costs power4_cost = {
592 COSTS_N_INSNS (3), /* mulsi */
593 COSTS_N_INSNS (2), /* mulsi_const */
594 COSTS_N_INSNS (2), /* mulsi_const9 */
595 COSTS_N_INSNS (4), /* muldi */
596 COSTS_N_INSNS (18), /* divsi */
597 COSTS_N_INSNS (34), /* divdi */
598 COSTS_N_INSNS (3), /* fp */
599 COSTS_N_INSNS (3), /* dmul */
600 COSTS_N_INSNS (17), /* sdiv */
601 COSTS_N_INSNS (17), /* ddiv */
605 static bool rs6000_function_ok_for_sibcall (tree, tree);
606 static int num_insns_constant_wide (HOST_WIDE_INT);
607 static void validate_condition_mode (enum rtx_code, enum machine_mode);
608 static rtx rs6000_generate_compare (enum rtx_code);
609 static void rs6000_maybe_dead (rtx);
610 static void rs6000_emit_stack_tie (void);
611 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
612 static rtx spe_synthesize_frame_save (rtx);
613 static bool spe_func_has_64bit_regs_p (void);
614 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
616 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
617 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
618 static unsigned rs6000_hash_constant (rtx);
619 static unsigned toc_hash_function (const void *);
620 static int toc_hash_eq (const void *, const void *);
621 static int constant_pool_expr_1 (rtx, int *, int *);
622 static bool constant_pool_expr_p (rtx);
623 static bool toc_relative_expr_p (rtx);
624 static bool legitimate_small_data_p (enum machine_mode, rtx);
625 static bool legitimate_indexed_address_p (rtx, int);
626 static bool legitimate_indirect_address_p (rtx, int);
627 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
628 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
629 static struct machine_function * rs6000_init_machine_status (void);
630 static bool rs6000_assemble_integer (rtx, unsigned int, int);
631 #ifdef HAVE_GAS_HIDDEN
632 static void rs6000_assemble_visibility (tree, int);
634 static int rs6000_ra_ever_killed (void);
635 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
636 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
637 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
638 static const char *rs6000_mangle_fundamental_type (tree);
639 extern const struct attribute_spec rs6000_attribute_table[];
640 static void rs6000_set_default_type_attributes (tree);
641 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
642 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
643 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
645 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
646 static bool rs6000_return_in_memory (tree, tree);
647 static void rs6000_file_start (void);
649 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
650 static void rs6000_elf_asm_out_constructor (rtx, int);
651 static void rs6000_elf_asm_out_destructor (rtx, int);
652 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
653 static void rs6000_elf_unique_section (tree, int);
654 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
655 unsigned HOST_WIDE_INT);
656 static void rs6000_elf_encode_section_info (tree, rtx, int)
658 static bool rs6000_elf_in_small_data_p (tree);
661 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
662 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
663 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
664 static void rs6000_xcoff_unique_section (tree, int);
665 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
666 unsigned HOST_WIDE_INT);
667 static const char * rs6000_xcoff_strip_name_encoding (const char *);
668 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
669 static void rs6000_xcoff_file_start (void);
670 static void rs6000_xcoff_file_end (void);
673 static bool rs6000_binds_local_p (tree);
675 static int rs6000_variable_issue (FILE *, int, rtx, int);
676 static bool rs6000_rtx_costs (rtx, int, int, int *);
677 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
678 static bool is_microcoded_insn (rtx);
679 static int is_dispatch_slot_restricted (rtx);
680 static bool is_cracked_insn (rtx);
681 static bool is_branch_slot_insn (rtx);
682 static int rs6000_adjust_priority (rtx, int);
683 static int rs6000_issue_rate (void);
684 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
685 static rtx get_next_active_insn (rtx, rtx);
686 static bool insn_terminates_group_p (rtx , enum group_termination);
687 static bool is_costly_group (rtx *, rtx);
688 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
689 static int redefine_groups (FILE *, int, rtx, rtx);
690 static int pad_groups (FILE *, int, rtx, rtx);
691 static void rs6000_sched_finish (FILE *, int);
692 static int rs6000_use_sched_lookahead (void);
693 static tree rs6000_builtin_mask_for_load (void);
695 static void rs6000_init_builtins (void);
696 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
697 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
698 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
699 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
700 static void altivec_init_builtins (void);
701 static void rs6000_common_init_builtins (void);
702 static void rs6000_init_libfuncs (void);
704 static void enable_mask_for_builtins (struct builtin_description *, int,
705 enum rs6000_builtins,
706 enum rs6000_builtins);
707 static tree build_opaque_vector_type (tree, int);
708 static void spe_init_builtins (void);
709 static rtx spe_expand_builtin (tree, rtx, bool *);
710 static rtx spe_expand_stv_builtin (enum insn_code, tree);
711 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
712 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
713 static bool invalid_e500_subreg (rtx, enum machine_mode);
714 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
715 static rs6000_stack_t *rs6000_stack_info (void);
716 static void debug_stack_info (rs6000_stack_t *);
718 static rtx altivec_expand_builtin (tree, rtx, bool *);
719 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
720 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
721 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
722 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
723 static rtx altivec_expand_predicate_builtin (enum insn_code,
724 const char *, tree, rtx);
725 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
726 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
727 static void rs6000_parse_abi_options (void);
728 static void rs6000_parse_alignment_option (void);
729 static void rs6000_parse_tls_size_option (void);
730 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
731 static void rs6000_parse_float_gprs_option (void);
732 static int first_altivec_reg_to_save (void);
733 static unsigned int compute_vrsave_mask (void);
734 static void compute_save_world_info(rs6000_stack_t *info_ptr);
735 static void is_altivec_return_reg (rtx, void *);
736 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
737 int easy_vector_constant (rtx, enum machine_mode);
738 static int easy_vector_same (rtx, enum machine_mode);
739 static int easy_vector_splat_const (int, enum machine_mode);
740 static bool is_ev64_opaque_type (tree);
741 static rtx rs6000_dwarf_register_span (rtx);
742 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
743 static rtx rs6000_tls_get_addr (void);
744 static rtx rs6000_got_sym (void);
745 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
746 static const char *rs6000_get_some_local_dynamic_name (void);
747 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
748 static rtx rs6000_complex_function_value (enum machine_mode);
749 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
750 enum machine_mode, tree);
751 static rtx rs6000_darwin64_function_arg (CUMULATIVE_ARGS *,
752 enum machine_mode, tree, int);
753 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
754 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
755 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
756 enum machine_mode, tree,
758 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
760 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
763 static void macho_branch_islands (void);
764 static void add_compiler_branch_island (tree, tree, int);
765 static int no_previous_def (tree function_name);
766 static tree get_prev_label (tree function_name);
767 static void rs6000_darwin_file_start (void);
770 static tree rs6000_build_builtin_va_list (void);
771 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
772 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
773 static bool rs6000_vector_mode_supported_p (enum machine_mode);
774 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
776 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
778 static int get_vsel_insn (enum machine_mode);
779 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
782 const int INSN_NOT_AVAILABLE = -1;
783 static enum machine_mode rs6000_eh_return_filter_mode (void);
785 /* Hash table stuff for keeping track of TOC entries. */
787 struct toc_hash_struct GTY(())
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
792 enum machine_mode key_mode;
796 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
798 /* Default register names. */
799 char rs6000_reg_names[][8] =
801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
812 /* AltiVec registers. */
813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
822 #ifdef TARGET_REGNAMES
823 static const char alt_reg_names[][8] =
825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
836 /* AltiVec registers. */
837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
847 #ifndef MASK_STRICT_ALIGN
848 #define MASK_STRICT_ALIGN 0
850 #ifndef TARGET_PROFILE_KERNEL
851 #define TARGET_PROFILE_KERNEL 0
854 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
857 /* Return 1 for a symbol ref for a thread-local storage symbol. */
858 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
859 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
861 /* Initialize the GCC target structure. */
862 #undef TARGET_ATTRIBUTE_TABLE
863 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
864 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
865 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
867 #undef TARGET_ASM_ALIGNED_DI_OP
868 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
870 /* Default unaligned ops are only provided for ELF. Find the ops needed
871 for non-ELF systems. */
872 #ifndef OBJECT_FORMAT_ELF
874 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
876 #undef TARGET_ASM_UNALIGNED_HI_OP
877 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
878 #undef TARGET_ASM_UNALIGNED_SI_OP
879 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
880 #undef TARGET_ASM_UNALIGNED_DI_OP
881 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
884 #undef TARGET_ASM_UNALIGNED_HI_OP
885 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
886 #undef TARGET_ASM_UNALIGNED_SI_OP
887 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
888 #undef TARGET_ASM_UNALIGNED_DI_OP
889 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
890 #undef TARGET_ASM_ALIGNED_DI_OP
891 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
895 /* This hook deals with fixups for relocatable code and DI-mode objects
897 #undef TARGET_ASM_INTEGER
898 #define TARGET_ASM_INTEGER rs6000_assemble_integer
900 #ifdef HAVE_GAS_HIDDEN
901 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
902 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
905 #undef TARGET_HAVE_TLS
906 #define TARGET_HAVE_TLS HAVE_AS_TLS
908 #undef TARGET_CANNOT_FORCE_CONST_MEM
909 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
911 #undef TARGET_ASM_FUNCTION_PROLOGUE
912 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
913 #undef TARGET_ASM_FUNCTION_EPILOGUE
914 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
916 #undef TARGET_SCHED_VARIABLE_ISSUE
917 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
919 #undef TARGET_SCHED_ISSUE_RATE
920 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
921 #undef TARGET_SCHED_ADJUST_COST
922 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
923 #undef TARGET_SCHED_ADJUST_PRIORITY
924 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
925 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
926 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
927 #undef TARGET_SCHED_FINISH
928 #define TARGET_SCHED_FINISH rs6000_sched_finish
930 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
931 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
933 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
934 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
936 #undef TARGET_INIT_BUILTINS
937 #define TARGET_INIT_BUILTINS rs6000_init_builtins
939 #undef TARGET_EXPAND_BUILTIN
940 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
942 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
943 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
945 #undef TARGET_INIT_LIBFUNCS
946 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
949 #undef TARGET_BINDS_LOCAL_P
950 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
953 #undef TARGET_ASM_OUTPUT_MI_THUNK
954 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
956 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
957 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
959 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
960 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
962 #undef TARGET_RTX_COSTS
963 #define TARGET_RTX_COSTS rs6000_rtx_costs
964 #undef TARGET_ADDRESS_COST
965 #define TARGET_ADDRESS_COST hook_int_rtx_0
967 #undef TARGET_VECTOR_OPAQUE_P
968 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
970 #undef TARGET_DWARF_REGISTER_SPAN
971 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
973 /* On rs6000, function arguments are promoted, as are function return
975 #undef TARGET_PROMOTE_FUNCTION_ARGS
976 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
977 #undef TARGET_PROMOTE_FUNCTION_RETURN
978 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
980 #undef TARGET_RETURN_IN_MEMORY
981 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
983 #undef TARGET_SETUP_INCOMING_VARARGS
984 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
986 /* Always strict argument naming on rs6000. */
987 #undef TARGET_STRICT_ARGUMENT_NAMING
988 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
989 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
990 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
991 #undef TARGET_SPLIT_COMPLEX_ARG
992 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
993 #undef TARGET_MUST_PASS_IN_STACK
994 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
995 #undef TARGET_PASS_BY_REFERENCE
996 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
997 #undef TARGET_ARG_PARTIAL_BYTES
998 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1000 #undef TARGET_BUILD_BUILTIN_VA_LIST
1001 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1003 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1004 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1006 #undef TARGET_EH_RETURN_FILTER_MODE
1007 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1009 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1010 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1012 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1013 The PowerPC architecture requires only weak consistency among
1014 processors--that is, memory accesses between processors need not be
1015 sequentially consistent and memory accesses among processors can occur
1016 in any order. The ability to order memory accesses weakly provides
1017 opportunities for more efficient use of the system bus. Unless a
1018 dependency exists, the 604e allows read operations to precede store
1020 #undef TARGET_RELAXED_ORDERING
1021 #define TARGET_RELAXED_ORDERING true
1023 struct gcc_target targetm = TARGET_INITIALIZER;
1026 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1029 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1031 /* The GPRs can hold any mode, but values bigger than one register
1032 cannot go past R31. */
1033 if (INT_REGNO_P (regno))
1034 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1036 /* The float registers can only hold floating modes and DImode. */
1037 if (FP_REGNO_P (regno))
1039 (GET_MODE_CLASS (mode) == MODE_FLOAT
1040 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1041 || (GET_MODE_CLASS (mode) == MODE_INT
1042 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1044 /* The CR register can only hold CC modes. */
1045 if (CR_REGNO_P (regno))
1046 return GET_MODE_CLASS (mode) == MODE_CC;
1048 if (XER_REGNO_P (regno))
1049 return mode == PSImode;
1051 /* AltiVec only in AldyVec registers. */
1052 if (ALTIVEC_REGNO_P (regno))
1053 return ALTIVEC_VECTOR_MODE (mode);
1055 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1056 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1059 /* We cannot put TImode anywhere except general register and it must be
1060 able to fit within the register set. */
1062 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1065 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1067 rs6000_init_hard_regno_mode_ok (void)
1071 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1072 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1073 if (rs6000_hard_regno_mode_ok (r, m))
1074 rs6000_hard_regno_mode_ok_p[m][r] = true;
1077 /* If not otherwise specified by a target, make 'long double' equivalent to
1080 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1081 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1084 /* Override command line options. Mostly we process the processor
1085 type and sometimes adjust other TARGET_ options. */
1088 rs6000_override_options (const char *default_cpu)
1091 struct rs6000_cpu_select *ptr;
1094 /* Simplifications for entries below. */
1097 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1098 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1101 /* This table occasionally claims that a processor does not support
1102 a particular feature even though it does, but the feature is slower
1103 than the alternative. Thus, it shouldn't be relied on as a
1104 complete description of the processor's support.
1106 Please keep this list in order, and don't forget to update the
1107 documentation in invoke.texi when adding a new processor or
1111 const char *const name; /* Canonical processor name. */
1112 const enum processor_type processor; /* Processor type enum value. */
1113 const int target_enable; /* Target flags to enable. */
1114 } const processor_target_table[]
1115 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1116 {"403", PROCESSOR_PPC403,
1117 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1118 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1119 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1120 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1121 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1122 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1123 {"601", PROCESSOR_PPC601,
1124 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1125 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1130 {"620", PROCESSOR_PPC620,
1131 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1132 {"630", PROCESSOR_PPC630,
1133 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1134 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1135 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1136 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1137 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1138 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1141 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1142 /* 8548 has a dummy entry for now. */
1143 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1144 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1145 {"970", PROCESSOR_POWER4,
1146 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1147 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1148 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1149 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1150 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1151 {"G5", PROCESSOR_POWER4,
1152 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1153 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1154 {"power2", PROCESSOR_POWER,
1155 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1156 {"power3", PROCESSOR_PPC630,
1157 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1158 {"power4", PROCESSOR_POWER4,
1159 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1160 {"power5", PROCESSOR_POWER5,
1161 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1162 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1163 {"powerpc64", PROCESSOR_POWERPC64,
1164 POWERPC_BASE_MASK | MASK_POWERPC64},
1165 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1167 {"rios2", PROCESSOR_RIOS2,
1168 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1170 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1171 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1174 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1176 /* Some OSs don't support saving the high part of 64-bit registers on
1177 context switch. Other OSs don't support saving Altivec registers.
1178 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1179 settings; if the user wants either, the user must explicitly specify
1180 them and we won't interfere with the user's specification. */
1183 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1184 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1185 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1189 rs6000_init_hard_regno_mode_ok ();
1191 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1192 #ifdef OS_MISSING_POWERPC64
1193 if (OS_MISSING_POWERPC64)
1194 set_masks &= ~MASK_POWERPC64;
1196 #ifdef OS_MISSING_ALTIVEC
1197 if (OS_MISSING_ALTIVEC)
1198 set_masks &= ~MASK_ALTIVEC;
1201 /* Don't override these by the processor default if given explicitly. */
1202 set_masks &= ~(target_flags_explicit
1203 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
1205 /* Identify the processor type. */
1206 rs6000_select[0].string = default_cpu;
1207 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1209 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1211 ptr = &rs6000_select[i];
1212 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1214 for (j = 0; j < ptt_size; j++)
1215 if (! strcmp (ptr->string, processor_target_table[j].name))
1217 if (ptr->set_tune_p)
1218 rs6000_cpu = processor_target_table[j].processor;
1220 if (ptr->set_arch_p)
1222 target_flags &= ~set_masks;
1223 target_flags |= (processor_target_table[j].target_enable
1230 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1237 /* If we are optimizing big endian systems for space, use the load/store
1238 multiple and string instructions. */
1239 if (BYTES_BIG_ENDIAN && optimize_size)
1240 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1242 /* Don't allow -mmultiple or -mstring on little endian systems
1243 unless the cpu is a 750, because the hardware doesn't support the
1244 instructions used in little endian mode, and causes an alignment
1245 trap. The 750 does not cause an alignment trap (except when the
1246 target is unaligned). */
1248 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1250 if (TARGET_MULTIPLE)
1252 target_flags &= ~MASK_MULTIPLE;
1253 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1254 warning ("-mmultiple is not supported on little endian systems");
1259 target_flags &= ~MASK_STRING;
1260 if ((target_flags_explicit & MASK_STRING) != 0)
1261 warning ("-mstring is not supported on little endian systems");
1265 /* Set debug flags */
1266 if (rs6000_debug_name)
1268 if (! strcmp (rs6000_debug_name, "all"))
1269 rs6000_debug_stack = rs6000_debug_arg = 1;
1270 else if (! strcmp (rs6000_debug_name, "stack"))
1271 rs6000_debug_stack = 1;
1272 else if (! strcmp (rs6000_debug_name, "arg"))
1273 rs6000_debug_arg = 1;
1275 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1278 if (rs6000_traceback_name)
1280 if (! strncmp (rs6000_traceback_name, "full", 4))
1281 rs6000_traceback = traceback_full;
1282 else if (! strncmp (rs6000_traceback_name, "part", 4))
1283 rs6000_traceback = traceback_part;
1284 else if (! strncmp (rs6000_traceback_name, "no", 2))
1285 rs6000_traceback = traceback_none;
1287 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1288 rs6000_traceback_name);
1291 /* Set size of long double */
1292 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1293 if (rs6000_long_double_size_string)
1296 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1297 if (*tail != '\0' || (size != 64 && size != 128))
1298 error ("Unknown switch -mlong-double-%s",
1299 rs6000_long_double_size_string);
1301 rs6000_long_double_type_size = size;
1304 /* Set Altivec ABI as default for powerpc64 linux. */
1305 if (TARGET_ELF && TARGET_64BIT)
1307 rs6000_altivec_abi = 1;
1308 rs6000_altivec_vrsave = 1;
1311 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1312 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1314 rs6000_darwin64_abi = 1;
1315 /* Setting to empty string is same as "-mone-byte-bool". */
1317 darwin_one_byte_bool = "";
1321 /* Handle -mabi= options. */
1322 rs6000_parse_abi_options ();
1324 /* Handle -malign-XXXXX option. */
1325 rs6000_parse_alignment_option ();
1327 rs6000_parse_float_gprs_option ();
1329 /* Handle generic -mFOO=YES/NO options. */
1330 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1331 &rs6000_altivec_vrsave);
1332 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1334 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1336 /* Handle -mtls-size option. */
1337 rs6000_parse_tls_size_option ();
1339 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1340 SUBTARGET_OVERRIDE_OPTIONS;
1342 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1343 SUBSUBTARGET_OVERRIDE_OPTIONS;
1345 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1346 SUB3TARGET_OVERRIDE_OPTIONS;
1352 error ("AltiVec and E500 instructions cannot coexist");
1354 /* The e500 does not have string instructions, and we set
1355 MASK_STRING above when optimizing for size. */
1356 if ((target_flags & MASK_STRING) != 0)
1357 target_flags = target_flags & ~MASK_STRING;
1359 /* No SPE means 64-bit long doubles, even if an E500. */
1360 if (rs6000_spe_string != 0
1361 && !strcmp (rs6000_spe_string, "no"))
1362 rs6000_long_double_type_size = 64;
1364 else if (rs6000_select[1].string != NULL)
1366 /* For the powerpc-eabispe configuration, we set all these by
1367 default, so let's unset them if we manually set another
1368 CPU that is not the E500. */
1369 if (rs6000_abi_string == 0)
1371 if (rs6000_spe_string == 0)
1373 if (rs6000_float_gprs_string == 0)
1374 rs6000_float_gprs = 0;
1375 if (rs6000_isel_string == 0)
1377 if (rs6000_long_double_size_string == 0)
1378 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1381 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1382 && rs6000_cpu != PROCESSOR_POWER5);
1383 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1384 || rs6000_cpu == PROCESSOR_POWER5);
1386 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1387 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1388 bits in target_flags so TARGET_SWITCHES cannot be used.
1389 Assumption here is that rs6000_longcall_switch points into the
1390 text of the complete option, rather than being a copy, so we can
1391 scan back for the presence or absence of the no- modifier. */
1392 if (rs6000_longcall_switch)
1394 const char *base = rs6000_longcall_switch;
1395 while (base[-1] != 'm') base--;
1397 if (*rs6000_longcall_switch != '\0')
1398 error ("invalid option %qs", base);
1399 rs6000_default_long_calls = (base[0] != 'n');
1402 /* Handle -m(no-)warn-altivec-long similarly. */
1403 if (rs6000_warn_altivec_long_switch)
1405 const char *base = rs6000_warn_altivec_long_switch;
1406 while (base[-1] != 'm') base--;
1408 if (*rs6000_warn_altivec_long_switch != '\0')
1409 error ("invalid option %qs", base);
1410 rs6000_warn_altivec_long = (base[0] != 'n');
1413 /* Handle -mprioritize-restricted-insns option. */
1414 rs6000_sched_restricted_insns_priority
1415 = (rs6000_sched_groups ? 1 : 0);
1416 if (rs6000_sched_restricted_insns_priority_str)
1417 rs6000_sched_restricted_insns_priority =
1418 atoi (rs6000_sched_restricted_insns_priority_str);
1420 /* Handle -msched-costly-dep option. */
1421 rs6000_sched_costly_dep
1422 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1423 if (rs6000_sched_costly_dep_str)
1425 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1426 rs6000_sched_costly_dep = no_dep_costly;
1427 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1428 rs6000_sched_costly_dep = all_deps_costly;
1429 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1430 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1431 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1432 rs6000_sched_costly_dep = store_to_load_dep_costly;
1434 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1437 /* Handle -minsert-sched-nops option. */
1438 rs6000_sched_insert_nops
1439 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1440 if (rs6000_sched_insert_nops_str)
1442 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1443 rs6000_sched_insert_nops = sched_finish_none;
1444 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1445 rs6000_sched_insert_nops = sched_finish_pad_groups;
1446 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1447 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1449 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1452 #ifdef TARGET_REGNAMES
1453 /* If the user desires alternate register names, copy in the
1454 alternate names now. */
1455 if (TARGET_REGNAMES)
1456 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1459 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1460 If -maix-struct-return or -msvr4-struct-return was explicitly
1461 used, don't override with the ABI default. */
1462 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1464 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1465 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1467 target_flags |= MASK_AIX_STRUCT_RET;
1470 if (TARGET_LONG_DOUBLE_128
1471 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1472 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1474 /* Allocate an alias set for register saves & restores from stack. */
1475 rs6000_sr_alias_set = new_alias_set ();
1478 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1480 /* We can only guarantee the availability of DI pseudo-ops when
1481 assembling for 64-bit targets. */
1484 targetm.asm_out.aligned_op.di = NULL;
1485 targetm.asm_out.unaligned_op.di = NULL;
1488 /* Set branch target alignment, if not optimizing for size. */
1491 if (rs6000_sched_groups)
1493 if (align_functions <= 0)
1494 align_functions = 16;
1495 if (align_jumps <= 0)
1497 if (align_loops <= 0)
1500 if (align_jumps_max_skip <= 0)
1501 align_jumps_max_skip = 15;
1502 if (align_loops_max_skip <= 0)
1503 align_loops_max_skip = 15;
1506 /* Arrange to save and restore machine status around nested functions. */
1507 init_machine_status = rs6000_init_machine_status;
1509 /* We should always be splitting complex arguments, but we can't break
1510 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1511 if (DEFAULT_ABI != ABI_AIX)
1512 targetm.calls.split_complex_arg = NULL;
1514 /* Initialize rs6000_cost with the appropriate target costs. */
1516 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1520 case PROCESSOR_RIOS1:
1521 rs6000_cost = &rios1_cost;
1524 case PROCESSOR_RIOS2:
1525 rs6000_cost = &rios2_cost;
1528 case PROCESSOR_RS64A:
1529 rs6000_cost = &rs64a_cost;
1532 case PROCESSOR_MPCCORE:
1533 rs6000_cost = &mpccore_cost;
1536 case PROCESSOR_PPC403:
1537 rs6000_cost = &ppc403_cost;
1540 case PROCESSOR_PPC405:
1541 rs6000_cost = &ppc405_cost;
1544 case PROCESSOR_PPC440:
1545 rs6000_cost = &ppc440_cost;
1548 case PROCESSOR_PPC601:
1549 rs6000_cost = &ppc601_cost;
1552 case PROCESSOR_PPC603:
1553 rs6000_cost = &ppc603_cost;
1556 case PROCESSOR_PPC604:
1557 rs6000_cost = &ppc604_cost;
1560 case PROCESSOR_PPC604e:
1561 rs6000_cost = &ppc604e_cost;
1564 case PROCESSOR_PPC620:
1565 rs6000_cost = &ppc620_cost;
1568 case PROCESSOR_PPC630:
1569 rs6000_cost = &ppc630_cost;
1572 case PROCESSOR_PPC750:
1573 case PROCESSOR_PPC7400:
1574 rs6000_cost = &ppc750_cost;
1577 case PROCESSOR_PPC7450:
1578 rs6000_cost = &ppc7450_cost;
1581 case PROCESSOR_PPC8540:
1582 rs6000_cost = &ppc8540_cost;
1585 case PROCESSOR_POWER4:
1586 case PROCESSOR_POWER5:
1587 rs6000_cost = &power4_cost;
1595 /* Implement targetm.vectorize.builtin_mask_for_load. */
1597 rs6000_builtin_mask_for_load (void)
1600 return altivec_builtin_mask_for_load;
1605 /* Handle generic options of the form -mfoo=yes/no.
1606 NAME is the option name.
1607 VALUE is the option value.
1608 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1609 whether the option value is 'yes' or 'no' respectively. */
1611 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1615 else if (!strcmp (value, "yes"))
1617 else if (!strcmp (value, "no"))
1620 error ("unknown -m%s= option specified: '%s'", name, value);
1623 /* Handle -mabi= options. */
1625 rs6000_parse_abi_options (void)
1627 if (rs6000_abi_string == 0)
1629 else if (! strcmp (rs6000_abi_string, "altivec"))
1631 rs6000_altivec_abi = 1;
1634 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1635 rs6000_altivec_abi = 0;
1636 else if (! strcmp (rs6000_abi_string, "spe"))
1639 rs6000_altivec_abi = 0;
1640 if (!TARGET_SPE_ABI)
1641 error ("not configured for ABI: '%s'", rs6000_abi_string);
1644 /* These are here for testing during development only, do not
1645 document in the manual please. */
1646 else if (! strcmp (rs6000_abi_string, "d64"))
1648 rs6000_darwin64_abi = 1;
1649 warning ("Using darwin64 ABI");
1651 else if (! strcmp (rs6000_abi_string, "d32"))
1653 rs6000_darwin64_abi = 0;
1654 warning ("Using old darwin ABI");
1657 else if (! strcmp (rs6000_abi_string, "no-spe"))
1660 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1663 /* Handle -mfloat-gprs= options. */
1665 rs6000_parse_float_gprs_option (void)
1667 if (rs6000_float_gprs_string == 0)
1669 else if (! strcmp (rs6000_float_gprs_string, "yes")
1670 || ! strcmp (rs6000_float_gprs_string, "single"))
1671 rs6000_float_gprs = 1;
1672 else if (! strcmp (rs6000_float_gprs_string, "double"))
1673 rs6000_float_gprs = 2;
1674 else if (! strcmp (rs6000_float_gprs_string, "no"))
1675 rs6000_float_gprs = 0;
1677 error ("invalid option for -mfloat-gprs");
1680 /* Handle -malign-XXXXXX options. */
1682 rs6000_parse_alignment_option (void)
1684 if (rs6000_alignment_string == 0)
1686 else if (! strcmp (rs6000_alignment_string, "power"))
1687 rs6000_alignment_flags = MASK_ALIGN_POWER;
1688 else if (! strcmp (rs6000_alignment_string, "natural"))
1689 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1691 error ("unknown -malign-XXXXX option specified: '%s'",
1692 rs6000_alignment_string);
1695 /* Validate and record the size specified with the -mtls-size option. */
1698 rs6000_parse_tls_size_option (void)
1700 if (rs6000_tls_size_string == 0)
1702 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1703 rs6000_tls_size = 16;
1704 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1705 rs6000_tls_size = 32;
1706 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1707 rs6000_tls_size = 64;
1709 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1713 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1717 /* Do anything needed at the start of the asm file. */
1720 rs6000_file_start (void)
1724 const char *start = buffer;
1725 struct rs6000_cpu_select *ptr;
1726 const char *default_cpu = TARGET_CPU_DEFAULT;
1727 FILE *file = asm_out_file;
1729 default_file_start ();
1731 #ifdef TARGET_BI_ARCH
1732 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1736 if (flag_verbose_asm)
1738 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1739 rs6000_select[0].string = default_cpu;
1741 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1743 ptr = &rs6000_select[i];
1744 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1746 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1751 #ifdef USING_ELFOS_H
1752 switch (rs6000_sdata)
1754 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1755 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1756 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1757 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1760 if (rs6000_sdata && g_switch_value)
1762 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1772 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1780 /* Return nonzero if this function is known to have a null epilogue. */
1783 direct_return (void)
1785 if (reload_completed)
1787 rs6000_stack_t *info = rs6000_stack_info ();
1789 if (info->first_gp_reg_save == 32
1790 && info->first_fp_reg_save == 64
1791 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1792 && ! info->lr_save_p
1793 && ! info->cr_save_p
1794 && info->vrsave_mask == 0
1802 /* Returns 1 always. */
1805 any_operand (rtx op ATTRIBUTE_UNUSED,
1806 enum machine_mode mode ATTRIBUTE_UNUSED)
1811 /* Returns 1 always. */
1814 any_parallel_operand (rtx op ATTRIBUTE_UNUSED,
1815 enum machine_mode mode ATTRIBUTE_UNUSED)
1820 /* Returns 1 if op is the count register. */
1823 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1825 if (GET_CODE (op) != REG)
1828 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1831 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1837 /* Returns 1 if op is an altivec register. */
1840 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1842 return (register_operand (op, mode)
1843 && (GET_CODE (op) != REG
1844 || REGNO (op) > FIRST_PSEUDO_REGISTER
1845 || ALTIVEC_REGNO_P (REGNO (op))));
1849 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1851 if (GET_CODE (op) != REG)
1854 if (XER_REGNO_P (REGNO (op)))
1860 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1861 by such constants completes more quickly. */
1864 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1866 return (GET_CODE (op) == CONST_INT
1867 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1870 /* Return 1 if OP is a constant that can fit in a D field. */
1873 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1875 return (GET_CODE (op) == CONST_INT
1876 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1879 /* Similar for an unsigned D field. */
1882 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1884 return (GET_CODE (op) == CONST_INT
1885 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1888 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1891 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1893 return (GET_CODE (op) == CONST_INT
1894 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1897 /* Returns 1 if OP is a CONST_INT that is a positive value
1898 and an exact power of 2. */
1901 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1903 return (GET_CODE (op) == CONST_INT
1905 && exact_log2 (INTVAL (op)) >= 0);
1908 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1912 gpc_reg_operand (rtx op, enum machine_mode mode)
1914 return (register_operand (op, mode)
1915 && (GET_CODE (op) != REG
1916 || (REGNO (op) >= ARG_POINTER_REGNUM
1917 && !XER_REGNO_P (REGNO (op)))
1918 || REGNO (op) < MQ_REGNO));
1921 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1925 cc_reg_operand (rtx op, enum machine_mode mode)
1927 return (register_operand (op, mode)
1928 && (GET_CODE (op) != REG
1929 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1930 || CR_REGNO_P (REGNO (op))));
1933 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1934 CR field that isn't CR0. */
1937 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1939 return (register_operand (op, mode)
1940 && (GET_CODE (op) != REG
1941 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1942 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1945 /* Returns 1 if OP is either a constant integer valid for a D-field or
1946 a non-special register. If a register, it must be in the proper
1947 mode unless MODE is VOIDmode. */
1950 reg_or_short_operand (rtx op, enum machine_mode mode)
1952 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1955 /* Similar, except check if the negation of the constant would be
1956 valid for a D-field. Don't allow a constant zero, since all the
1957 patterns that call this predicate use "addic r1,r2,-constant" on
1958 a constant value to set a carry when r2 is greater or equal to
1959 "constant". That doesn't work for zero. */
1962 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1964 if (GET_CODE (op) == CONST_INT)
1965 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
1967 return gpc_reg_operand (op, mode);
1970 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1971 a non-special register. If a register, it must be in the proper
1972 mode unless MODE is VOIDmode. */
1975 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1977 if (gpc_reg_operand (op, mode))
1979 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1986 /* Return 1 if the operand is either a register or an integer whose
1987 high-order 16 bits are zero. */
1990 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1992 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1995 /* Return 1 is the operand is either a non-special register or ANY
1996 constant integer. */
1999 reg_or_cint_operand (rtx op, enum machine_mode mode)
2001 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
2004 /* Return 1 is the operand is either a non-special register or ANY
2005 32-bit signed constant integer. */
2008 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
2010 return (gpc_reg_operand (op, mode)
2011 || (GET_CODE (op) == CONST_INT
2012 #if HOST_BITS_PER_WIDE_INT != 32
2013 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
2014 < (unsigned HOST_WIDE_INT) 0x100000000ll)
2019 /* Return 1 is the operand is either a non-special register or a 32-bit
2020 signed constant integer valid for 64-bit addition. */
2023 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
2025 return (gpc_reg_operand (op, mode)
2026 || (GET_CODE (op) == CONST_INT
2027 #if HOST_BITS_PER_WIDE_INT == 32
2028 && INTVAL (op) < 0x7fff8000
2030 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
2036 /* Return 1 is the operand is either a non-special register or a 32-bit
2037 signed constant integer valid for 64-bit subtraction. */
2040 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
2042 return (gpc_reg_operand (op, mode)
2043 || (GET_CODE (op) == CONST_INT
2044 #if HOST_BITS_PER_WIDE_INT == 32
2045 && (- INTVAL (op)) < 0x7fff8000
2047 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
2053 /* Return 1 is the operand is either a non-special register or ANY
2054 32-bit unsigned constant integer. */
2057 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
2059 if (GET_CODE (op) == CONST_INT)
2061 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
2063 if (GET_MODE_BITSIZE (mode) <= 32)
2066 if (INTVAL (op) < 0)
2070 return ((INTVAL (op) & GET_MODE_MASK (mode)
2071 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
2073 else if (GET_CODE (op) == CONST_DOUBLE)
2075 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2079 return CONST_DOUBLE_HIGH (op) == 0;
2082 return gpc_reg_operand (op, mode);
2085 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2088 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2090 return (GET_CODE (op) == SYMBOL_REF
2091 || GET_CODE (op) == CONST
2092 || GET_CODE (op) == LABEL_REF);
2095 /* Return 1 if the operand is a simple references that can be loaded via
2096 the GOT (labels involving addition aren't allowed). */
2099 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2101 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
2104 /* Return the number of instructions it takes to form a constant in an
2105 integer register. */
2108 num_insns_constant_wide (HOST_WIDE_INT value)
2110 /* signed constant loadable with {cal|addi} */
2111 if (CONST_OK_FOR_LETTER_P (value, 'I'))
2114 /* constant loadable with {cau|addis} */
2115 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2118 #if HOST_BITS_PER_WIDE_INT == 64
2119 else if (TARGET_POWERPC64)
2121 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2122 HOST_WIDE_INT high = value >> 31;
2124 if (high == 0 || high == -1)
2130 return num_insns_constant_wide (high) + 1;
2132 return (num_insns_constant_wide (high)
2133 + num_insns_constant_wide (low) + 1);
2142 num_insns_constant (rtx op, enum machine_mode mode)
2144 if (GET_CODE (op) == CONST_INT)
2146 #if HOST_BITS_PER_WIDE_INT == 64
2147 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2148 && mask64_operand (op, mode))
2152 return num_insns_constant_wide (INTVAL (op));
2155 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
2160 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2161 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2162 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2165 else if (GET_CODE (op) == CONST_DOUBLE)
2171 int endian = (WORDS_BIG_ENDIAN == 0);
2173 if (mode == VOIDmode || mode == DImode)
2175 high = CONST_DOUBLE_HIGH (op);
2176 low = CONST_DOUBLE_LOW (op);
2180 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2181 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2183 low = l[1 - endian];
2187 return (num_insns_constant_wide (low)
2188 + num_insns_constant_wide (high));
2192 if (high == 0 && low >= 0)
2193 return num_insns_constant_wide (low);
2195 else if (high == -1 && low < 0)
2196 return num_insns_constant_wide (low);
2198 else if (mask64_operand (op, mode))
2202 return num_insns_constant_wide (high) + 1;
2205 return (num_insns_constant_wide (high)
2206 + num_insns_constant_wide (low) + 1);
2214 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2215 register with one instruction per word. We only do this if we can
2216 safely read CONST_DOUBLE_{LOW,HIGH}. */
2219 easy_fp_constant (rtx op, enum machine_mode mode)
2221 if (GET_CODE (op) != CONST_DOUBLE
2222 || GET_MODE (op) != mode
2223 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
2226 /* Consider all constants with -msoft-float to be easy. */
2227 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
2231 /* If we are using V.4 style PIC, consider all constants to be hard. */
2232 if (flag_pic && DEFAULT_ABI == ABI_V4)
2235 #ifdef TARGET_RELOCATABLE
2236 /* Similarly if we are using -mrelocatable, consider all constants
2238 if (TARGET_RELOCATABLE)
2247 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2248 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
2250 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2251 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
2252 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
2253 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
2256 else if (mode == DFmode)
2261 if (TARGET_E500_DOUBLE)
2264 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2265 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
2267 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2268 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
2271 else if (mode == SFmode)
2276 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2277 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2279 return num_insns_constant_wide (l) == 1;
2282 else if (mode == DImode)
2283 return ((TARGET_POWERPC64
2284 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
2285 || (num_insns_constant (op, DImode) <= 2));
2287 else if (mode == SImode)
2293 /* Returns the constant for the splat instruction, if exists. */
2296 easy_vector_splat_const (int cst, enum machine_mode mode)
2301 if (EASY_VECTOR_15 (cst)
2302 || EASY_VECTOR_15_ADD_SELF (cst))
2304 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2310 if (EASY_VECTOR_15 (cst)
2311 || EASY_VECTOR_15_ADD_SELF (cst))
2313 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2319 if (EASY_VECTOR_15 (cst)
2320 || EASY_VECTOR_15_ADD_SELF (cst))
2329 /* Return nonzero if all elements of a vector have the same value. */
2332 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2336 units = CONST_VECTOR_NUNITS (op);
2338 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2339 for (i = 1; i < units; ++i)
2340 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2342 if (i == units && easy_vector_splat_const (cst, mode))
2347 /* Return 1 if the operand is a CONST_INT and can be put into a
2348 register without using memory. */
2351 easy_vector_constant (rtx op, enum machine_mode mode)
2355 if (GET_CODE (op) != CONST_VECTOR
2360 if (zero_constant (op, mode)
2361 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
2362 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
2365 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2368 if (TARGET_SPE && mode == V1DImode)
2371 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2372 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
2374 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2376 evmergelo r0, r0, r0
2379 I don't know how efficient it would be to allow bigger constants,
2380 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2381 instructions is better than a 64-bit memory load, but I don't
2382 have the e500 timing specs. */
2383 if (TARGET_SPE && mode == V2SImode
2384 && cst >= -0x7fff && cst <= 0x7fff
2385 && cst2 >= -0x7fff && cst2 <= 0x7fff)
2389 && easy_vector_same (op, mode))
2391 cst = easy_vector_splat_const (cst, mode);
2392 if (EASY_VECTOR_15_ADD_SELF (cst)
2393 || EASY_VECTOR_15 (cst))
2399 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2402 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
2406 && GET_CODE (op) == CONST_VECTOR
2407 && easy_vector_same (op, mode))
2409 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
2410 if (EASY_VECTOR_15_ADD_SELF (cst))
2416 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2419 gen_easy_vector_constant_add_self (rtx op)
2423 units = GET_MODE_NUNITS (GET_MODE (op));
2424 v = rtvec_alloc (units);
2426 for (i = 0; i < units; i++)
2428 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2429 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2433 output_vec_const_move (rtx *operands)
2436 enum machine_mode mode;
2442 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2443 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2444 mode = GET_MODE (dest);
2448 if (zero_constant (vec, mode))
2449 return "vxor %0,%0,%0";
2450 else if (easy_vector_constant (vec, mode))
2452 operands[1] = GEN_INT (cst);
2456 if (EASY_VECTOR_15 (cst))
2458 operands[1] = GEN_INT (cst);
2459 return "vspltisw %0,%1";
2461 else if (EASY_VECTOR_15_ADD_SELF (cst))
2467 if (EASY_VECTOR_15 (cst))
2469 operands[1] = GEN_INT (cst);
2470 return "vspltish %0,%1";
2472 else if (EASY_VECTOR_15_ADD_SELF (cst))
2478 if (EASY_VECTOR_15 (cst))
2480 operands[1] = GEN_INT (cst);
2481 return "vspltisb %0,%1";
2483 else if (EASY_VECTOR_15_ADD_SELF (cst))
2496 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2497 pattern of V1DI, V4HI, and V2SF.
2499 FIXME: We should probably return # and add post reload
2500 splitters for these, but this way is so easy ;-). */
2501 operands[1] = GEN_INT (cst);
2502 operands[2] = GEN_INT (cst2);
2504 return "li %0,%1\n\tevmergelo %0,%0,%0";
2506 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2512 /* Return 1 if the operand is the constant 0. This works for scalars
2513 as well as vectors. */
2515 zero_constant (rtx op, enum machine_mode mode)
2517 return op == CONST0_RTX (mode);
2520 /* Return 1 if the operand is 0.0. */
2522 zero_fp_constant (rtx op, enum machine_mode mode)
2524 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
2527 /* Return 1 if the operand is in volatile memory. Note that during
2528 the RTL generation phase, memory_operand does not return TRUE for
2529 volatile memory references. So this function allows us to
2530 recognize volatile references where its safe. */
2533 volatile_mem_operand (rtx op, enum machine_mode mode)
2535 if (GET_CODE (op) != MEM)
2538 if (!MEM_VOLATILE_P (op))
2541 if (mode != GET_MODE (op))
2544 if (reload_completed)
2545 return memory_operand (op, mode);
2547 if (reload_in_progress)
2548 return strict_memory_address_p (mode, XEXP (op, 0));
2550 return memory_address_p (mode, XEXP (op, 0));
2553 /* Return 1 if the operand is an offsettable memory operand. */
2556 offsettable_mem_operand (rtx op, enum machine_mode mode)
2558 return ((GET_CODE (op) == MEM)
2559 && offsettable_address_p (reload_completed || reload_in_progress,
2560 mode, XEXP (op, 0)));
2563 /* Return 1 if the operand is either an easy FP constant (see above) or
2567 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
2569 return memory_operand (op, mode) || easy_fp_constant (op, mode);
2572 /* Return 1 if the operand is either a non-special register or an item
2573 that can be used as the operand of a `mode' add insn. */
2576 add_operand (rtx op, enum machine_mode mode)
2578 if (GET_CODE (op) == CONST_INT)
2579 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2580 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2582 return gpc_reg_operand (op, mode);
2585 /* Return 1 if OP is a constant but not a valid add_operand. */
2588 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2590 return (GET_CODE (op) == CONST_INT
2591 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2592 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2595 /* Return 1 if the operand is a non-special register or a constant that
2596 can be used as the operand of an OR or XOR insn on the RS/6000. */
2599 logical_operand (rtx op, enum machine_mode mode)
2601 HOST_WIDE_INT opl, oph;
2603 if (gpc_reg_operand (op, mode))
2606 if (GET_CODE (op) == CONST_INT)
2608 opl = INTVAL (op) & GET_MODE_MASK (mode);
2610 #if HOST_BITS_PER_WIDE_INT <= 32
2611 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
2615 else if (GET_CODE (op) == CONST_DOUBLE)
2617 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2620 opl = CONST_DOUBLE_LOW (op);
2621 oph = CONST_DOUBLE_HIGH (op);
2628 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2629 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2632 /* Return 1 if C is a constant that is not a logical operand (as
2633 above), but could be split into one. */
2636 non_logical_cint_operand (rtx op, enum machine_mode mode)
2638 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2639 && ! logical_operand (op, mode)
2640 && reg_or_logical_cint_operand (op, mode));
2643 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2644 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2645 Reject all ones and all zeros, since these should have been optimized
2646 away and confuse the making of MB and ME. */
2649 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2651 HOST_WIDE_INT c, lsb;
2653 if (GET_CODE (op) != CONST_INT)
2658 /* Fail in 64-bit mode if the mask wraps around because the upper
2659 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2660 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2663 /* We don't change the number of transitions by inverting,
2664 so make sure we start with the LS bit zero. */
2668 /* Reject all zeros or all ones. */
2672 /* Find the first transition. */
2675 /* Invert to look for a second transition. */
2678 /* Erase first transition. */
2681 /* Find the second transition (if any). */
2684 /* Match if all the bits above are 1's (or c is zero). */
2688 /* Return 1 for the PowerPC64 rlwinm corner case. */
2691 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2693 HOST_WIDE_INT c, lsb;
2695 if (GET_CODE (op) != CONST_INT)
2700 if ((c & 0x80000001) != 0x80000001)
2714 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2715 It is if there are no more than one 1->0 or 0->1 transitions.
2716 Reject all zeros, since zero should have been optimized away and
2717 confuses the making of MB and ME. */
2720 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2722 if (GET_CODE (op) == CONST_INT)
2724 HOST_WIDE_INT c, lsb;
2728 /* Reject all zeros. */
2732 /* We don't change the number of transitions by inverting,
2733 so make sure we start with the LS bit zero. */
2737 /* Find the transition, and check that all bits above are 1's. */
2740 /* Match if all the bits above are 1's (or c is zero). */
2747 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2750 if (GET_CODE (op) == CONST_INT)
2752 HOST_WIDE_INT c, lsb;
2757 /* Disallow all zeros. */
2761 /* We can use a single rlwinm insn if no upper bits of C are set
2762 AND there are zero, one or two transitions in the _whole_ of
2764 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2766 /* We don't change the number of transitions by inverting,
2767 so make sure we start with the LS bit zero. */
2771 /* Find the first transition. */
2774 /* Invert to look for a second transition. */
2777 /* Erase first transition. */
2780 /* Find the second transition. */
2783 /* Invert to look for a third transition. */
2786 /* Erase second transition. */
2789 if (one_ok && !(allow_one || c))
2792 /* Find the third transition (if any). */
2795 /* Match if all the bits above are 1's (or c is zero). */
2801 /* Like mask64_operand, but allow up to three transitions. This
2802 predicate is used by insn patterns that generate two rldicl or
2803 rldicr machine insns. */
2804 int mask64_2_operand (rtx op, enum machine_mode mode)
2806 return mask64_1or2_operand (op, mode, false);
2809 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2810 implement ANDing by the mask IN. */
2812 build_mask64_2_operands (rtx in, rtx *out)
2814 #if HOST_BITS_PER_WIDE_INT >= 64
2815 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2818 if (GET_CODE (in) != CONST_INT)
2824 /* Assume c initially something like 0x00fff000000fffff. The idea
2825 is to rotate the word so that the middle ^^^^^^ group of zeros
2826 is at the MS end and can be cleared with an rldicl mask. We then
2827 rotate back and clear off the MS ^^ group of zeros with a
2829 c = ~c; /* c == 0xff000ffffff00000 */
2830 lsb = c & -c; /* lsb == 0x0000000000100000 */
2831 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2832 c = ~c; /* c == 0x00fff000000fffff */
2833 c &= -lsb; /* c == 0x00fff00000000000 */
2834 lsb = c & -c; /* lsb == 0x0000100000000000 */
2835 c = ~c; /* c == 0xff000fffffffffff */
2836 c &= -lsb; /* c == 0xff00000000000000 */
2838 while ((lsb >>= 1) != 0)
2839 shift++; /* shift == 44 on exit from loop */
2840 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2841 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2842 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2846 /* Assume c initially something like 0xff000f0000000000. The idea
2847 is to rotate the word so that the ^^^ middle group of zeros
2848 is at the LS end and can be cleared with an rldicr mask. We then
2849 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2851 lsb = c & -c; /* lsb == 0x0000010000000000 */
2852 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2853 c = ~c; /* c == 0x00fff0ffffffffff */
2854 c &= -lsb; /* c == 0x00fff00000000000 */
2855 lsb = c & -c; /* lsb == 0x0000100000000000 */
2856 c = ~c; /* c == 0xff000fffffffffff */
2857 c &= -lsb; /* c == 0xff00000000000000 */
2859 while ((lsb >>= 1) != 0)
2860 shift++; /* shift == 44 on exit from loop */
2861 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2862 m1 >>= shift; /* m1 == 0x0000000000000fff */
2863 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2866 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2867 masks will be all 1's. We are guaranteed more than one transition. */
2868 out[0] = GEN_INT (64 - shift);
2869 out[1] = GEN_INT (m1);
2870 out[2] = GEN_INT (shift);
2871 out[3] = GEN_INT (m2);
2879 /* Return 1 if the operand is either a non-special register or a constant
2880 that can be used as the operand of a PowerPC64 logical AND insn. */
2883 and64_operand (rtx op, enum machine_mode mode)
2885 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2886 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2888 return (logical_operand (op, mode) || mask64_operand (op, mode));
2891 /* Like the above, but also match constants that can be implemented
2892 with two rldicl or rldicr insns. */
2895 and64_2_operand (rtx op, enum machine_mode mode)
2897 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2898 return gpc_reg_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2900 return logical_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2903 /* Return 1 if the operand is either a non-special register or a
2904 constant that can be used as the operand of an RS/6000 logical AND insn. */
2907 and_operand (rtx op, enum machine_mode mode)
2909 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2910 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2912 return (logical_operand (op, mode) || mask_operand (op, mode));
2915 /* Return 1 if the operand is a general register or memory operand. */
2918 reg_or_mem_operand (rtx op, enum machine_mode mode)
2920 return (gpc_reg_operand (op, mode)
2921 || memory_operand (op, mode)
2922 || macho_lo_sum_memory_operand (op, mode)
2923 || volatile_mem_operand (op, mode));
2926 /* Return 1 if the operand is a general register or memory operand without
2927 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2931 lwa_operand (rtx op, enum machine_mode mode)
2935 if (reload_completed && GET_CODE (inner) == SUBREG)
2936 inner = SUBREG_REG (inner);
2938 return gpc_reg_operand (inner, mode)
2939 || (memory_operand (inner, mode)
2940 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2941 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2942 && (GET_CODE (XEXP (inner, 0)) != PLUS
2943 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2944 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2947 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2950 symbol_ref_operand (rtx op, enum machine_mode mode)
2952 if (mode != VOIDmode && GET_MODE (op) != mode)
2955 return (GET_CODE (op) == SYMBOL_REF
2956 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2959 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2960 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2963 call_operand (rtx op, enum machine_mode mode)
2965 if (mode != VOIDmode && GET_MODE (op) != mode)
2968 return (GET_CODE (op) == SYMBOL_REF
2969 || (GET_CODE (op) == REG
2970 && (REGNO (op) == LINK_REGISTER_REGNUM
2971 || REGNO (op) == COUNT_REGISTER_REGNUM
2972 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2975 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2979 current_file_function_operand (rtx op,
2980 enum machine_mode mode ATTRIBUTE_UNUSED)
2982 return (GET_CODE (op) == SYMBOL_REF
2983 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2984 && (SYMBOL_REF_LOCAL_P (op)
2985 || (DECL_RTL_SET_P (current_function_decl)
2986 && op == XEXP (DECL_RTL (current_function_decl), 0))));
2989 /* Return 1 if this operand is a valid input for a move insn. */
2992 input_operand (rtx op, enum machine_mode mode)
2994 /* Memory is always valid. */
2995 if (memory_operand (op, mode))
2998 /* For floating-point, easy constants are valid. */
2999 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3001 && easy_fp_constant (op, mode))
3004 /* Allow any integer constant. */
3005 if (GET_MODE_CLASS (mode) == MODE_INT
3006 && (GET_CODE (op) == CONST_INT
3007 || GET_CODE (op) == CONST_DOUBLE))
3010 /* Allow easy vector constants. */
3011 if (GET_CODE (op) == CONST_VECTOR
3012 && easy_vector_constant (op, mode))
3015 /* For floating-point or multi-word mode, the only remaining valid type
3017 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3018 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3019 return register_operand (op, mode);
3021 /* The only cases left are integral modes one word or smaller (we
3022 do not get called for MODE_CC values). These can be in any
3024 if (register_operand (op, mode))
3027 /* A SYMBOL_REF referring to the TOC is valid. */
3028 if (legitimate_constant_pool_address_p (op))
3031 /* A constant pool expression (relative to the TOC) is valid */
3032 if (toc_relative_expr_p (op))
3035 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
3037 if (DEFAULT_ABI == ABI_V4
3038 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
3039 && small_data_operand (op, Pmode))
3045 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3047 invalid_e500_subreg (rtx op, enum machine_mode mode)
3049 /* Reject (subreg:SI (reg:DF)). */
3050 if (GET_CODE (op) == SUBREG
3052 && REG_P (SUBREG_REG (op))
3053 && GET_MODE (SUBREG_REG (op)) == DFmode)
3056 /* Reject (subreg:DF (reg:DI)). */
3057 if (GET_CODE (op) == SUBREG
3059 && REG_P (SUBREG_REG (op))
3060 && GET_MODE (SUBREG_REG (op)) == DImode)
3066 /* Just like nonimmediate_operand, but return 0 for invalid SUBREG's
3069 rs6000_nonimmediate_operand (rtx op, enum machine_mode mode)
3071 if (TARGET_E500_DOUBLE
3072 && GET_CODE (op) == SUBREG
3073 && invalid_e500_subreg (op, mode))
3076 return nonimmediate_operand (op, mode);
3079 /* Darwin, AIX increases natural record alignment to doubleword if the first
3080 field is an FP double while the FP fields remain word aligned. */
3083 rs6000_special_round_type_align (tree type, int computed, int specified)
3085 tree field = TYPE_FIELDS (type);
3087 /* Skip all non field decls */
3088 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3089 field = TREE_CHAIN (field);
3091 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
3092 return MAX (computed, specified);
3094 return MAX (MAX (computed, specified), 64);
3097 /* Return 1 for an operand in small memory on V.4/eabi. */
3100 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3101 enum machine_mode mode ATTRIBUTE_UNUSED)
3106 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3109 if (DEFAULT_ABI != ABI_V4)
3112 if (GET_CODE (op) == SYMBOL_REF)
3115 else if (GET_CODE (op) != CONST
3116 || GET_CODE (XEXP (op, 0)) != PLUS
3117 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3118 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3123 rtx sum = XEXP (op, 0);
3124 HOST_WIDE_INT summand;
3126 /* We have to be careful here, because it is the referenced address
3127 that must be 32k from _SDA_BASE_, not just the symbol. */
3128 summand = INTVAL (XEXP (sum, 1));
3129 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3132 sym_ref = XEXP (sum, 0);
3135 return SYMBOL_REF_SMALL_P (sym_ref);
3141 /* Return true, if operand is a memory operand and has a
3142 displacement divisible by 4. */
3145 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3150 if (!memory_operand (op, mode))
3153 addr = XEXP (op, 0);
3154 if (GET_CODE (addr) == PLUS
3155 && GET_CODE (XEXP (addr, 0)) == REG
3156 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3157 off = INTVAL (XEXP (addr, 1));
3159 return (off % 4) == 0;
3162 /* Return true if either operand is a general purpose register. */
3165 gpr_or_gpr_p (rtx op0, rtx op1)
3167 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3168 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3172 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3175 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3177 switch (GET_CODE(op))
3180 if (RS6000_SYMBOL_REF_TLS_P (op))
3182 else if (CONSTANT_POOL_ADDRESS_P (op))
3184 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3192 else if (! strcmp (XSTR (op, 0), toc_label_name))
3201 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3202 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3204 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3213 constant_pool_expr_p (rtx op)
3217 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3221 toc_relative_expr_p (rtx op)
3225 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3229 legitimate_constant_pool_address_p (rtx x)
3232 && GET_CODE (x) == PLUS
3233 && GET_CODE (XEXP (x, 0)) == REG
3234 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3235 && constant_pool_expr_p (XEXP (x, 1)));
3239 legitimate_small_data_p (enum machine_mode mode, rtx x)
3241 return (DEFAULT_ABI == ABI_V4
3242 && !flag_pic && !TARGET_TOC
3243 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3244 && small_data_operand (x, mode));
3247 /* SPE offset addressing is limited to 5-bits worth of double words. */
3248 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3251 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3253 unsigned HOST_WIDE_INT offset, extra;
3255 if (GET_CODE (x) != PLUS)
3257 if (GET_CODE (XEXP (x, 0)) != REG)
3259 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3261 if (legitimate_constant_pool_address_p (x))
3263 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3266 offset = INTVAL (XEXP (x, 1));
3274 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3275 which leaves the only valid constant offset of zero, which by
3276 canonicalization rules is also invalid. */
3283 /* SPE vector modes. */
3284 return SPE_CONST_OFFSET_OK (offset);
3287 if (TARGET_E500_DOUBLE)
3288 return SPE_CONST_OFFSET_OK (offset);
3291 /* On e500v2, we may have:
3293 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3295 Which gets addressed with evldd instructions. */
3296 if (TARGET_E500_DOUBLE)
3297 return SPE_CONST_OFFSET_OK (offset);
3299 if (mode == DFmode || !TARGET_POWERPC64)
3301 else if (offset & 3)
3307 if (mode == TFmode || !TARGET_POWERPC64)
3309 else if (offset & 3)
3320 return (offset < 0x10000) && (offset + extra < 0x10000);
3324 legitimate_indexed_address_p (rtx x, int strict)
3328 if (GET_CODE (x) != PLUS)
3334 if (!REG_P (op0) || !REG_P (op1))
3337 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
3338 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3339 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3340 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
3344 legitimate_indirect_address_p (rtx x, int strict)
3346 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3350 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3352 if (!TARGET_MACHO || !flag_pic
3353 || mode != SImode || GET_CODE(x) != MEM)
3357 if (GET_CODE (x) != LO_SUM)
3359 if (GET_CODE (XEXP (x, 0)) != REG)
3361 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3365 return CONSTANT_P (x);
3369 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3371 if (GET_CODE (x) != LO_SUM)
3373 if (GET_CODE (XEXP (x, 0)) != REG)
3375 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3377 /* Restrict addressing for DI because of our SUBREG hackery. */
3378 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3382 if (TARGET_ELF || TARGET_MACHO)
3384 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3388 if (GET_MODE_NUNITS (mode) != 1)
3390 if (GET_MODE_BITSIZE (mode) > 64
3391 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3392 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3395 return CONSTANT_P (x);
3402 /* Try machine-dependent ways of modifying an illegitimate address
3403 to be legitimate. If we find one, return the new, valid address.
3404 This is used from only one place: `memory_address' in explow.c.
3406 OLDX is the address as it was before break_out_memory_refs was
3407 called. In some cases it is useful to look at this to decide what
3410 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3412 It is always safe for this function to do nothing. It exists to
3413 recognize opportunities to optimize the output.
3415 On RS/6000, first check for the sum of a register with a constant
3416 integer that is out of range. If so, generate code to add the
3417 constant with the low-order 16 bits masked to the register and force
3418 this result into another register (this can be done with `cau').
3419 Then generate an address of REG+(CONST&0xffff), allowing for the
3420 possibility of bit 16 being a one.
3422 Then check for the sum of a register and something not constant, try to
3423 load the other things into a register and return the sum. */
3426 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3427 enum machine_mode mode)
3429 if (GET_CODE (x) == SYMBOL_REF)
3431 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3433 return rs6000_legitimize_tls_address (x, model);
3436 if (GET_CODE (x) == PLUS
3437 && GET_CODE (XEXP (x, 0)) == REG
3438 && GET_CODE (XEXP (x, 1)) == CONST_INT
3439 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3441 HOST_WIDE_INT high_int, low_int;
3443 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3444 high_int = INTVAL (XEXP (x, 1)) - low_int;
3445 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3446 GEN_INT (high_int)), 0);
3447 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3449 else if (GET_CODE (x) == PLUS
3450 && GET_CODE (XEXP (x, 0)) == REG
3451 && GET_CODE (XEXP (x, 1)) != CONST_INT
3452 && GET_MODE_NUNITS (mode) == 1
3453 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3455 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
3457 && (TARGET_POWERPC64 || mode != DImode)
3460 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3461 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3463 else if (ALTIVEC_VECTOR_MODE (mode))
3467 /* Make sure both operands are registers. */
3468 if (GET_CODE (x) == PLUS)
3469 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3470 force_reg (Pmode, XEXP (x, 1)));
3472 reg = force_reg (Pmode, x);
3475 else if (SPE_VECTOR_MODE (mode)
3476 || (TARGET_E500_DOUBLE && (mode == DFmode
3477 || mode == DImode)))
3481 /* We accept [reg + reg] and [reg + OFFSET]. */
3483 if (GET_CODE (x) == PLUS)
3485 rtx op1 = XEXP (x, 0);
3486 rtx op2 = XEXP (x, 1);
3488 op1 = force_reg (Pmode, op1);
3490 if (GET_CODE (op2) != REG
3491 && (GET_CODE (op2) != CONST_INT
3492 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3493 op2 = force_reg (Pmode, op2);
3495 return gen_rtx_PLUS (Pmode, op1, op2);
3498 return force_reg (Pmode, x);
3504 && GET_CODE (x) != CONST_INT
3505 && GET_CODE (x) != CONST_DOUBLE
3507 && GET_MODE_NUNITS (mode) == 1
3508 && (GET_MODE_BITSIZE (mode) <= 32
3509 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3511 rtx reg = gen_reg_rtx (Pmode);
3512 emit_insn (gen_elf_high (reg, x));
3513 return gen_rtx_LO_SUM (Pmode, reg, x);
3515 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3518 && ! MACHO_DYNAMIC_NO_PIC_P
3520 && GET_CODE (x) != CONST_INT
3521 && GET_CODE (x) != CONST_DOUBLE
3523 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3527 rtx reg = gen_reg_rtx (Pmode);
3528 emit_insn (gen_macho_high (reg, x));
3529 return gen_rtx_LO_SUM (Pmode, reg, x);
3532 && constant_pool_expr_p (x)
3533 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3535 return create_TOC_reference (x);
3541 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3542 We need to emit DTP-relative relocations. */
3545 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3550 fputs ("\t.long\t", file);
3553 fputs (DOUBLE_INT_ASM_OP, file);
3558 output_addr_const (file, x);
3559 fputs ("@dtprel+0x8000", file);
3562 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3564 static GTY(()) rtx rs6000_tls_symbol;
3566 rs6000_tls_get_addr (void)
3568 if (!rs6000_tls_symbol)
3569 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3571 return rs6000_tls_symbol;
3574 /* Construct the SYMBOL_REF for TLS GOT references. */
3576 static GTY(()) rtx rs6000_got_symbol;
3578 rs6000_got_sym (void)
3580 if (!rs6000_got_symbol)
3582 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3583 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3584 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3587 return rs6000_got_symbol;
3590 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3591 this (thread-local) address. */
3594 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3598 dest = gen_reg_rtx (Pmode);
3599 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3605 tlsreg = gen_rtx_REG (Pmode, 13);
3606 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3610 tlsreg = gen_rtx_REG (Pmode, 2);
3611 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3615 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3619 tmp = gen_reg_rtx (Pmode);
3622 tlsreg = gen_rtx_REG (Pmode, 13);
3623 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3627 tlsreg = gen_rtx_REG (Pmode, 2);
3628 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3632 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3634 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3639 rtx r3, got, tga, tmp1, tmp2, eqv;
3642 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3646 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3649 rtx gsym = rs6000_got_sym ();
3650 got = gen_reg_rtx (Pmode);
3652 rs6000_emit_move (got, gsym, Pmode);
3656 static int tls_got_labelno = 0;
3657 rtx tempLR, lab, tmp3, mem;
3660 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
3661 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
3662 tempLR = gen_reg_rtx (Pmode);
3663 tmp1 = gen_reg_rtx (Pmode);
3664 tmp2 = gen_reg_rtx (Pmode);
3665 tmp3 = gen_reg_rtx (Pmode);
3666 mem = gen_const_mem (Pmode, tmp1);
3668 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
3670 emit_move_insn (tmp1, tempLR);
3671 emit_move_insn (tmp2, mem);
3672 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3673 last = emit_move_insn (got, tmp3);
3674 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3676 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3678 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3684 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3686 r3 = gen_rtx_REG (Pmode, 3);
3688 insn = gen_tls_gd_64 (r3, got, addr);
3690 insn = gen_tls_gd_32 (r3, got, addr);
3693 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3694 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3695 insn = emit_call_insn (insn);
3696 CONST_OR_PURE_CALL_P (insn) = 1;
3697 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3698 insn = get_insns ();
3700 emit_libcall_block (insn, dest, r3, addr);
3702 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3704 r3 = gen_rtx_REG (Pmode, 3);
3706 insn = gen_tls_ld_64 (r3, got);
3708 insn = gen_tls_ld_32 (r3, got);
3711 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3712 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3713 insn = emit_call_insn (insn);
3714 CONST_OR_PURE_CALL_P (insn) = 1;
3715 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3716 insn = get_insns ();
3718 tmp1 = gen_reg_rtx (Pmode);
3719 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3721 emit_libcall_block (insn, tmp1, r3, eqv);
3722 if (rs6000_tls_size == 16)
3725 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3727 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3729 else if (rs6000_tls_size == 32)
3731 tmp2 = gen_reg_rtx (Pmode);
3733 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3735 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3738 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3740 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3744 tmp2 = gen_reg_rtx (Pmode);
3746 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3748 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3750 insn = gen_rtx_SET (Pmode, dest,
3751 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3757 /* IE, or 64 bit offset LE. */
3758 tmp2 = gen_reg_rtx (Pmode);
3760 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3762 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3765 insn = gen_tls_tls_64 (dest, tmp2, addr);
3767 insn = gen_tls_tls_32 (dest, tmp2, addr);
3775 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3776 instruction definitions. */
3779 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3781 return RS6000_SYMBOL_REF_TLS_P (x);
3784 /* Return 1 if X contains a thread-local symbol. */
3787 rs6000_tls_referenced_p (rtx x)
3789 if (! TARGET_HAVE_TLS)
3792 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3795 /* Return 1 if *X is a thread-local symbol. This is the same as
3796 rs6000_tls_symbol_ref except for the type of the unused argument. */
3799 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3801 return RS6000_SYMBOL_REF_TLS_P (*x);
3804 /* The convention appears to be to define this wherever it is used.
3805 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3806 is now used here. */
3807 #ifndef REG_MODE_OK_FOR_BASE_P
3808 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3811 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3812 replace the input X, or the original X if no replacement is called for.
3813 The output parameter *WIN is 1 if the calling macro should goto WIN,
3816 For RS/6000, we wish to handle large displacements off a base
3817 register by splitting the addend across an addiu/addis and the mem insn.
3818 This cuts number of extra insns needed from 3 to 1.
3820 On Darwin, we use this to generate code for floating point constants.
3821 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3822 The Darwin code is inside #if TARGET_MACHO because only then is
3823 machopic_function_base_name() defined. */
3825 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3826 int opnum, int type,
3827 int ind_levels ATTRIBUTE_UNUSED, int *win)
3829 /* We must recognize output that we have already generated ourselves. */
3830 if (GET_CODE (x) == PLUS
3831 && GET_CODE (XEXP (x, 0)) == PLUS
3832 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3833 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3834 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3836 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3837 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3838 opnum, (enum reload_type)type);
3844 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3845 && GET_CODE (x) == LO_SUM
3846 && GET_CODE (XEXP (x, 0)) == PLUS
3847 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3848 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3849 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3850 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3851 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3852 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3853 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3855 /* Result of previous invocation of this function on Darwin
3856 floating point constant. */
3857 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3858 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3859 opnum, (enum reload_type)type);
3865 /* Force ld/std non-word aligned offset into base register by wrapping
3867 if (GET_CODE (x) == PLUS
3868 && GET_CODE (XEXP (x, 0)) == REG
3869 && REGNO (XEXP (x, 0)) < 32
3870 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3871 && GET_CODE (XEXP (x, 1)) == CONST_INT
3872 && (INTVAL (XEXP (x, 1)) & 3) != 0
3873 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3874 && TARGET_POWERPC64)
3876 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3877 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3878 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3879 opnum, (enum reload_type) type);
3884 if (GET_CODE (x) == PLUS
3885 && GET_CODE (XEXP (x, 0)) == REG
3886 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3887 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3888 && GET_CODE (XEXP (x, 1)) == CONST_INT
3889 && !SPE_VECTOR_MODE (mode)
3890 && !(TARGET_E500_DOUBLE && (mode == DFmode
3892 && !ALTIVEC_VECTOR_MODE (mode))
3894 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3895 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3897 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3899 /* Check for 32-bit overflow. */
3900 if (high + low != val)
3906 /* Reload the high part into a base reg; leave the low part
3907 in the mem directly. */
3909 x = gen_rtx_PLUS (GET_MODE (x),
3910 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3914 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3915 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3916 opnum, (enum reload_type)type);
3922 if (GET_CODE (x) == SYMBOL_REF
3923 && DEFAULT_ABI == ABI_DARWIN
3924 && !ALTIVEC_VECTOR_MODE (mode)
3925 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3926 /* Don't do this for TFmode, since the result isn't offsettable.
3927 The same goes for DImode without 64-bit gprs. */
3929 && (mode != DImode || TARGET_POWERPC64))
3933 rtx offset = gen_rtx_CONST (Pmode,
3934 gen_rtx_MINUS (Pmode, x,
3935 machopic_function_base_sym ()));
3936 x = gen_rtx_LO_SUM (GET_MODE (x),
3937 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3938 gen_rtx_HIGH (Pmode, offset)), offset);
3941 x = gen_rtx_LO_SUM (GET_MODE (x),
3942 gen_rtx_HIGH (Pmode, x), x);
3944 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3945 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3946 opnum, (enum reload_type)type);
3953 && constant_pool_expr_p (x)
3954 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3956 (x) = create_TOC_reference (x);
3964 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3965 that is a valid memory address for an instruction.
3966 The MODE argument is the machine mode for the MEM expression
3967 that wants to use this address.
3969 On the RS/6000, there are four valid address: a SYMBOL_REF that
3970 refers to a constant pool entry of an address (or the sum of it
3971 plus a constant), a short (16-bit signed) constant plus a register,
3972 the sum of two registers, or a register indirect, possibly with an
3973 auto-increment. For DFmode and DImode with a constant plus register,
3974 we must ensure that both words are addressable or PowerPC64 with offset
3977 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3978 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3979 adjacent memory cells are accessed by adding word-sized offsets
3980 during assembly output. */
3982 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3984 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3986 && ALTIVEC_VECTOR_MODE (mode)
3987 && GET_CODE (x) == AND
3988 && GET_CODE (XEXP (x, 1)) == CONST_INT
3989 && INTVAL (XEXP (x, 1)) == -16)
3992 if (RS6000_SYMBOL_REF_TLS_P (x))
3994 if (legitimate_indirect_address_p (x, reg_ok_strict))
3996 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3997 && !ALTIVEC_VECTOR_MODE (mode)
3998 && !SPE_VECTOR_MODE (mode)
3999 /* Restrict addressing for DI because of our SUBREG hackery. */
4000 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
4002 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
4004 if (legitimate_small_data_p (mode, x))
4006 if (legitimate_constant_pool_address_p (x))
4008 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4010 && GET_CODE (x) == PLUS
4011 && GET_CODE (XEXP (x, 0)) == REG
4012 && (XEXP (x, 0) == virtual_stack_vars_rtx
4013 || XEXP (x, 0) == arg_pointer_rtx)
4014 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4016 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
4020 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4022 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
4023 && (TARGET_POWERPC64 || mode != DImode)
4024 && legitimate_indexed_address_p (x, reg_ok_strict))
4026 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
4031 /* Go to LABEL if ADDR (a legitimate address expression)
4032 has an effect that depends on the machine mode it is used for.
4034 On the RS/6000 this is true of all integral offsets (since AltiVec
4035 modes don't allow them) or is a pre-increment or decrement.
4037 ??? Except that due to conceptual problems in offsettable_address_p
4038 we can't really report the problems of integral offsets. So leave
4039 this assuming that the adjustable offset must be valid for the
4040 sub-words of a TFmode operand, which is what we had before. */
4043 rs6000_mode_dependent_address (rtx addr)
4045 switch (GET_CODE (addr))
4048 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4050 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4051 return val + 12 + 0x8000 >= 0x10000;
4060 return TARGET_UPDATE;
4069 /* Return number of consecutive hard regs needed starting at reg REGNO
4070 to hold something of mode MODE.
4071 This is ordinarily the length in words of a value of mode MODE
4072 but can be less for certain modes in special long registers.
4074 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4075 scalar instructions. The upper 32 bits are only available to the
4078 POWER and PowerPC GPRs hold 32 bits worth;
4079 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4082 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4084 if (FP_REGNO_P (regno))
4085 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4087 if (TARGET_E500_DOUBLE && mode == DFmode)
4090 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4091 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4093 if (ALTIVEC_REGNO_P (regno))
4095 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4097 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4100 /* Change register usage conditional on target flags. */
4102 rs6000_conditional_register_usage (void)
4106 /* Set MQ register fixed (already call_used) if not POWER
4107 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4112 /* 64-bit AIX reserves GPR13 for thread-private data. */
4114 fixed_regs[13] = call_used_regs[13]
4115 = call_really_used_regs[13] = 1;
4117 /* Conditionally disable FPRs. */
4118 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4119 for (i = 32; i < 64; i++)
4120 fixed_regs[i] = call_used_regs[i]
4121 = call_really_used_regs[i] = 1;
4123 if (DEFAULT_ABI == ABI_V4
4124 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4126 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4128 if (DEFAULT_ABI == ABI_V4
4129 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4131 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4132 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4133 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4135 if (DEFAULT_ABI == ABI_DARWIN
4136 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4137 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4138 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4139 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4140 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4142 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4143 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4144 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4147 global_regs[VSCR_REGNO] = 1;
4151 global_regs[SPEFSCR_REGNO] = 1;
4152 fixed_regs[FIXED_SCRATCH]
4153 = call_used_regs[FIXED_SCRATCH]
4154 = call_really_used_regs[FIXED_SCRATCH] = 1;
4157 if (! TARGET_ALTIVEC)
4159 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4160 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4161 call_really_used_regs[VRSAVE_REGNO] = 1;
4164 if (TARGET_ALTIVEC_ABI)
4165 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4166 call_used_regs[i] = call_really_used_regs[i] = 1;
4169 /* Try to output insns to set TARGET equal to the constant C if it can
4170 be done in less than N insns. Do all computations in MODE.
4171 Returns the place where the output has been placed if it can be
4172 done and the insns have been emitted. If it would take more than N
4173 insns, zero is returned and no insns and emitted. */
4176 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4177 rtx source, int n ATTRIBUTE_UNUSED)
4179 rtx result, insn, set;
4180 HOST_WIDE_INT c0, c1;
4182 if (mode == QImode || mode == HImode)
4185 dest = gen_reg_rtx (mode);
4186 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4189 else if (mode == SImode)
4191 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4193 emit_insn (gen_rtx_SET (VOIDmode, result,
4194 GEN_INT (INTVAL (source)
4195 & (~ (HOST_WIDE_INT) 0xffff))));
4196 emit_insn (gen_rtx_SET (VOIDmode, dest,
4197 gen_rtx_IOR (SImode, result,
4198 GEN_INT (INTVAL (source) & 0xffff))));
4201 else if (mode == DImode)
4203 if (GET_CODE (source) == CONST_INT)
4205 c0 = INTVAL (source);
4208 else if (GET_CODE (source) == CONST_DOUBLE)
4210 #if HOST_BITS_PER_WIDE_INT >= 64
4211 c0 = CONST_DOUBLE_LOW (source);
4214 c0 = CONST_DOUBLE_LOW (source);
4215 c1 = CONST_DOUBLE_HIGH (source);
4221 result = rs6000_emit_set_long_const (dest, c0, c1);
4226 insn = get_last_insn ();
4227 set = single_set (insn);
4228 if (! CONSTANT_P (SET_SRC (set)))
4229 set_unique_reg_note (insn, REG_EQUAL, source);
4234 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4235 fall back to a straight forward decomposition. We do this to avoid
4236 exponential run times encountered when looking for longer sequences
4237 with rs6000_emit_set_const. */
4239 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4241 if (!TARGET_POWERPC64)
4243 rtx operand1, operand2;
4245 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4247 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4249 emit_move_insn (operand1, GEN_INT (c1));
4250 emit_move_insn (operand2, GEN_INT (c2));
4254 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4257 ud2 = (c1 & 0xffff0000) >> 16;
4258 #if HOST_BITS_PER_WIDE_INT >= 64
4262 ud4 = (c2 & 0xffff0000) >> 16;
4264 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4265 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4268 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4270 emit_move_insn (dest, GEN_INT (ud1));
4273 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4274 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4277 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4280 emit_move_insn (dest, GEN_INT (ud2 << 16));
4282 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4284 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4285 || (ud4 == 0 && ! (ud3 & 0x8000)))
4288 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4291 emit_move_insn (dest, GEN_INT (ud3 << 16));
4294 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4295 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4297 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4302 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4305 emit_move_insn (dest, GEN_INT (ud4 << 16));
4308 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4310 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4312 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4313 GEN_INT (ud2 << 16)));
4315 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4321 /* Helper for the following. Get rid of [r+r] memory refs
4322 in cases where it won't work (TImode, TFmode). */
4325 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4327 if (GET_CODE (operands[0]) == MEM
4328 && GET_CODE (XEXP (operands[0], 0)) != REG
4329 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4330 && ! reload_in_progress)
4332 = replace_equiv_address (operands[0],
4333 copy_addr_to_reg (XEXP (operands[0], 0)));
4335 if (GET_CODE (operands[1]) == MEM
4336 && GET_CODE (XEXP (operands[1], 0)) != REG
4337 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4338 && ! reload_in_progress)
4340 = replace_equiv_address (operands[1],
4341 copy_addr_to_reg (XEXP (operands[1], 0)));
4344 /* Emit a move from SOURCE to DEST in mode MODE. */
4346 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4350 operands[1] = source;
4352 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4353 if (GET_CODE (operands[1]) == CONST_DOUBLE
4354 && ! FLOAT_MODE_P (mode)
4355 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4357 /* FIXME. This should never happen. */
4358 /* Since it seems that it does, do the safe thing and convert
4360 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4362 if (GET_CODE (operands[1]) == CONST_DOUBLE
4363 && ! FLOAT_MODE_P (mode)
4364 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
4365 && CONST_DOUBLE_LOW (operands[1]) >= 0)
4366 || (CONST_DOUBLE_HIGH (operands[1]) == -1
4367 && CONST_DOUBLE_LOW (operands[1]) < 0)))
4370 /* Check if GCC is setting up a block move that will end up using FP
4371 registers as temporaries. We must make sure this is acceptable. */
4372 if (GET_CODE (operands[0]) == MEM
4373 && GET_CODE (operands[1]) == MEM
4375 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4376 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4377 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4378 ? 32 : MEM_ALIGN (operands[0])))
4379 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4381 : MEM_ALIGN (operands[1]))))
4382 && ! MEM_VOLATILE_P (operands [0])
4383 && ! MEM_VOLATILE_P (operands [1]))
4385 emit_move_insn (adjust_address (operands[0], SImode, 0),
4386 adjust_address (operands[1], SImode, 0));
4387 emit_move_insn (adjust_address (operands[0], SImode, 4),
4388 adjust_address (operands[1], SImode, 4));
4392 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
4393 && !gpc_reg_operand (operands[1], mode))
4394 operands[1] = force_reg (mode, operands[1]);
4396 if (mode == SFmode && ! TARGET_POWERPC
4397 && TARGET_HARD_FLOAT && TARGET_FPRS
4398 && GET_CODE (operands[0]) == MEM)
4402 if (reload_in_progress || reload_completed)
4403 regnum = true_regnum (operands[1]);
4404 else if (GET_CODE (operands[1]) == REG)
4405 regnum = REGNO (operands[1]);
4409 /* If operands[1] is a register, on POWER it may have
4410 double-precision data in it, so truncate it to single
4412 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4415 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4416 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4417 operands[1] = newreg;
4421 /* Recognize the case where operand[1] is a reference to thread-local
4422 data and load its address to a register. */
4423 if (GET_CODE (operands[1]) == SYMBOL_REF)
4425 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
4427 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
4430 /* Handle the case where reload calls us with an invalid address. */
4431 if (reload_in_progress && mode == Pmode
4432 && (! general_operand (operands[1], mode)
4433 || ! nonimmediate_operand (operands[0], mode)))
4436 /* 128-bit constant floating-point values on Darwin should really be
4437 loaded as two parts. */
4438 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
4439 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4440 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4442 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4443 know how to get a DFmode SUBREG of a TFmode. */
4444 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4445 simplify_gen_subreg (DImode, operands[1], mode, 0),
4447 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4448 GET_MODE_SIZE (DImode)),
4449 simplify_gen_subreg (DImode, operands[1], mode,
4450 GET_MODE_SIZE (DImode)),
4455 /* FIXME: In the long term, this switch statement should go away
4456 and be replaced by a sequence of tests based on things like
4462 if (CONSTANT_P (operands[1])
4463 && GET_CODE (operands[1]) != CONST_INT)
4464 operands[1] = force_const_mem (mode, operands[1]);
4468 rs6000_eliminate_indexed_memrefs (operands);
4473 if (CONSTANT_P (operands[1])
4474 && ! easy_fp_constant (operands[1], mode))
4475 operands[1] = force_const_mem (mode, operands[1]);
4486 if (CONSTANT_P (operands[1])
4487 && !easy_vector_constant (operands[1], mode))
4488 operands[1] = force_const_mem (mode, operands[1]);
4493 /* Use default pattern for address of ELF small data */
4496 && DEFAULT_ABI == ABI_V4
4497 && (GET_CODE (operands[1]) == SYMBOL_REF
4498 || GET_CODE (operands[1]) == CONST)
4499 && small_data_operand (operands[1], mode))
4501 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4505 if (DEFAULT_ABI == ABI_V4
4506 && mode == Pmode && mode == SImode
4507 && flag_pic == 1 && got_operand (operands[1], mode))
4509 emit_insn (gen_movsi_got (operands[0], operands[1]));
4513 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4517 && CONSTANT_P (operands[1])
4518 && GET_CODE (operands[1]) != HIGH
4519 && GET_CODE (operands[1]) != CONST_INT)
4521 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4523 /* If this is a function address on -mcall-aixdesc,
4524 convert it to the address of the descriptor. */
4525 if (DEFAULT_ABI == ABI_AIX
4526 && GET_CODE (operands[1]) == SYMBOL_REF
4527 && XSTR (operands[1], 0)[0] == '.')
4529 const char *name = XSTR (operands[1], 0);
4531 while (*name == '.')
4533 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4534 CONSTANT_POOL_ADDRESS_P (new_ref)
4535 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4536 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4537 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4538 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
4539 operands[1] = new_ref;
4542 if (DEFAULT_ABI == ABI_DARWIN)
4545 if (MACHO_DYNAMIC_NO_PIC_P)
4547 /* Take care of any required data indirection. */
4548 operands[1] = rs6000_machopic_legitimize_pic_address (
4549 operands[1], mode, operands[0]);
4550 if (operands[0] != operands[1])
4551 emit_insn (gen_rtx_SET (VOIDmode,
4552 operands[0], operands[1]));
4556 emit_insn (gen_macho_high (target, operands[1]));
4557 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4561 emit_insn (gen_elf_high (target, operands[1]));
4562 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4566 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4567 and we have put it in the TOC, we just need to make a TOC-relative
4570 && GET_CODE (operands[1]) == SYMBOL_REF
4571 && constant_pool_expr_p (operands[1])
4572 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4573 get_pool_mode (operands[1])))
4575 operands[1] = create_TOC_reference (operands[1]);
4577 else if (mode == Pmode
4578 && CONSTANT_P (operands[1])
4579 && ((GET_CODE (operands[1]) != CONST_INT
4580 && ! easy_fp_constant (operands[1], mode))
4581 || (GET_CODE (operands[1]) == CONST_INT
4582 && num_insns_constant (operands[1], mode) > 2)
4583 || (GET_CODE (operands[0]) == REG
4584 && FP_REGNO_P (REGNO (operands[0]))))
4585 && GET_CODE (operands[1]) != HIGH
4586 && ! legitimate_constant_pool_address_p (operands[1])
4587 && ! toc_relative_expr_p (operands[1]))
4589 /* Emit a USE operation so that the constant isn't deleted if
4590 expensive optimizations are turned on because nobody
4591 references it. This should only be done for operands that
4592 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4593 This should not be done for operands that contain LABEL_REFs.
4594 For now, we just handle the obvious case. */
4595 if (GET_CODE (operands[1]) != LABEL_REF)
4596 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4599 /* Darwin uses a special PIC legitimizer. */
4600 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4603 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4605 if (operands[0] != operands[1])
4606 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4611 /* If we are to limit the number of things we put in the TOC and
4612 this is a symbol plus a constant we can add in one insn,
4613 just put the symbol in the TOC and add the constant. Don't do
4614 this if reload is in progress. */
4615 if (GET_CODE (operands[1]) == CONST
4616 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4617 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4618 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4619 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4620 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4621 && ! side_effects_p (operands[0]))
4624 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4625 rtx other = XEXP (XEXP (operands[1], 0), 1);
4627 sym = force_reg (mode, sym);
4629 emit_insn (gen_addsi3 (operands[0], sym, other));
4631 emit_insn (gen_adddi3 (operands[0], sym, other));
4635 operands[1] = force_const_mem (mode, operands[1]);
4638 && constant_pool_expr_p (XEXP (operands[1], 0))
4639 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4640 get_pool_constant (XEXP (operands[1], 0)),
4641 get_pool_mode (XEXP (operands[1], 0))))
4644 = gen_const_mem (mode,
4645 create_TOC_reference (XEXP (operands[1], 0)));
4646 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4652 rs6000_eliminate_indexed_memrefs (operands);
4656 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4658 gen_rtx_SET (VOIDmode,
4659 operands[0], operands[1]),
4660 gen_rtx_CLOBBER (VOIDmode,
4661 gen_rtx_SCRATCH (SImode)))));
4670 /* Above, we may have called force_const_mem which may have returned
4671 an invalid address. If we can, fix this up; otherwise, reload will
4672 have to deal with it. */
4673 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4674 operands[1] = validize_mem (operands[1]);
4677 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4680 /* Nonzero if we can use a floating-point register to pass this arg. */
4681 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4682 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4683 && (CUM)->fregno <= FP_ARG_MAX_REG \
4684 && TARGET_HARD_FLOAT && TARGET_FPRS)
4686 /* Nonzero if we can use an AltiVec register to pass this arg. */
4687 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4688 (ALTIVEC_VECTOR_MODE (MODE) \
4689 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4690 && TARGET_ALTIVEC_ABI \
4693 /* Return a nonzero value to say to return the function value in
4694 memory, just as large structures are always returned. TYPE will be
4695 the data type of the value, and FNTYPE will be the type of the
4696 function doing the returning, or @code{NULL} for libcalls.
4698 The AIX ABI for the RS/6000 specifies that all structures are
4699 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4700 specifies that structures <= 8 bytes are returned in r3/r4, but a
4701 draft put them in memory, and GCC used to implement the draft
4702 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4703 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4704 compatibility can change DRAFT_V4_STRUCT_RET to override the
4705 default, and -m switches get the final word. See
4706 rs6000_override_options for more details.
4708 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4709 long double support is enabled. These values are returned in memory.
4711 int_size_in_bytes returns -1 for variable size objects, which go in
4712 memory always. The cast to unsigned makes -1 > 8. */
4715 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4717 /* In the darwin64 abi, try to use registers for larger structs
4719 if (AGGREGATE_TYPE_P (type)
4720 && rs6000_darwin64_abi
4721 && TREE_CODE (type) == RECORD_TYPE
4722 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 32)
4723 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 0))
4726 if (AGGREGATE_TYPE_P (type)
4727 && (TARGET_AIX_STRUCT_RET
4728 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4731 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4732 modes only exist for GCC vector types if -maltivec. */
4733 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4734 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4737 /* Return synthetic vectors in memory. */
4738 if (TREE_CODE (type) == VECTOR_TYPE
4739 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4741 static bool warned_for_return_big_vectors = false;
4742 if (!warned_for_return_big_vectors)
4744 warning ("GCC vector returned by reference: "
4745 "non-standard ABI extension with no compatibility guarantee");
4746 warned_for_return_big_vectors = true;
4751 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4757 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4758 for a call to a function whose data type is FNTYPE.
4759 For a library call, FNTYPE is 0.
4761 For incoming args we set the number of arguments in the prototype large
4762 so we never return a PARALLEL. */
4765 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4766 rtx libname ATTRIBUTE_UNUSED, int incoming,
4767 int libcall, int n_named_args)
4769 static CUMULATIVE_ARGS zero_cumulative;
4771 *cum = zero_cumulative;
4773 cum->fregno = FP_ARG_MIN_REG;
4774 cum->vregno = ALTIVEC_ARG_MIN_REG;
4775 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4776 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4777 ? CALL_LIBCALL : CALL_NORMAL);
4778 cum->sysv_gregno = GP_ARG_MIN_REG;
4779 cum->stdarg = fntype
4780 && (TYPE_ARG_TYPES (fntype) != 0
4781 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4782 != void_type_node));
4784 cum->nargs_prototype = 0;
4785 if (incoming || cum->prototype)
4786 cum->nargs_prototype = n_named_args;
4788 /* Check for a longcall attribute. */
4789 if ((!fntype && rs6000_default_long_calls)
4791 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4792 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4793 cum->call_cookie |= CALL_LONG;
4795 if (TARGET_DEBUG_ARG)
4797 fprintf (stderr, "\ninit_cumulative_args:");
4800 tree ret_type = TREE_TYPE (fntype);
4801 fprintf (stderr, " ret code = %s,",
4802 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4805 if (cum->call_cookie & CALL_LONG)
4806 fprintf (stderr, " longcall,");
4808 fprintf (stderr, " proto = %d, nargs = %d\n",
4809 cum->prototype, cum->nargs_prototype);
4814 && TARGET_ALTIVEC_ABI
4815 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4817 error ("Cannot return value in vector register because"
4818 " altivec instructions are disabled, use -maltivec"
4819 " to enable them.");
4823 /* Return true if TYPE must be passed on the stack and not in registers. */
4826 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4828 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4829 return must_pass_in_stack_var_size (mode, type);
4831 return must_pass_in_stack_var_size_or_pad (mode, type);
4834 /* If defined, a C expression which determines whether, and in which
4835 direction, to pad out an argument with extra space. The value
4836 should be of type `enum direction': either `upward' to pad above
4837 the argument, `downward' to pad below, or `none' to inhibit
4840 For the AIX ABI structs are always stored left shifted in their
4844 function_arg_padding (enum machine_mode mode, tree type)
4846 #ifndef AGGREGATE_PADDING_FIXED
4847 #define AGGREGATE_PADDING_FIXED 0
4849 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4850 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4853 if (!AGGREGATE_PADDING_FIXED)
4855 /* GCC used to pass structures of the same size as integer types as
4856 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4857 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4858 passed padded downward, except that -mstrict-align further
4859 muddied the water in that multi-component structures of 2 and 4
4860 bytes in size were passed padded upward.
4862 The following arranges for best compatibility with previous
4863 versions of gcc, but removes the -mstrict-align dependency. */
4864 if (BYTES_BIG_ENDIAN)
4866 HOST_WIDE_INT size = 0;
4868 if (mode == BLKmode)
4870 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4871 size = int_size_in_bytes (type);
4874 size = GET_MODE_SIZE (mode);
4876 if (size == 1 || size == 2 || size == 4)
4882 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4884 if (type != 0 && AGGREGATE_TYPE_P (type))
4888 /* Fall back to the default. */
4889 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4892 /* If defined, a C expression that gives the alignment boundary, in bits,
4893 of an argument with the specified mode and type. If it is not defined,
4894 PARM_BOUNDARY is used for all arguments.
4896 V.4 wants long longs to be double word aligned.
4897 Doubleword align SPE vectors.
4898 Quadword align Altivec vectors.
4899 Quadword align large synthetic vector types. */
4902 function_arg_boundary (enum machine_mode mode, tree type)
4904 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4906 else if (SPE_VECTOR_MODE (mode)
4907 || (type && TREE_CODE (type) == VECTOR_TYPE
4908 && int_size_in_bytes (type) >= 8
4909 && int_size_in_bytes (type) < 16))
4911 else if (ALTIVEC_VECTOR_MODE (mode)
4912 || (type && TREE_CODE (type) == VECTOR_TYPE
4913 && int_size_in_bytes (type) >= 16))
4916 return PARM_BOUNDARY;
4919 /* Compute the size (in words) of a function argument. */
4921 static unsigned long
4922 rs6000_arg_size (enum machine_mode mode, tree type)
4926 if (mode != BLKmode)
4927 size = GET_MODE_SIZE (mode);
4929 size = int_size_in_bytes (type);
4932 return (size + 3) >> 2;
4934 return (size + 7) >> 3;
4937 /* The darwin64 ABI calls for us to recurse down through structs,
4938 applying the same rules to struct elements as if a reference to
4939 each were being passed directly. */
4942 darwin64_function_arg_advance (CUMULATIVE_ARGS *cum, tree type,
4943 int named, int depth)
4948 switch (TREE_CODE (type))
4951 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4952 if (TREE_CODE (f) == FIELD_DECL)
4954 ftype = TREE_TYPE (f);
4955 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4961 tot = int_size_in_bytes (type);
4964 ftype = TREE_TYPE (type);
4965 tot /= int_size_in_bytes (ftype);
4967 for (i = 0; i < tot; ++i)
4969 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4979 /* Update the data in CUM to advance over an argument
4980 of mode MODE and data type TYPE.
4981 (TYPE is null for libcalls where that information may not be available.)
4983 Note that for args passed by reference, function_arg will be called
4984 with MODE and TYPE set to that of the pointer to the arg, not the arg
4988 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4989 tree type, int named, int depth)
4991 /* Only tick off an argument if we're not recursing. */
4993 cum->nargs_prototype--;
4995 if (TARGET_ALTIVEC_ABI
4996 && (ALTIVEC_VECTOR_MODE (mode)
4997 || (type && TREE_CODE (type) == VECTOR_TYPE
4998 && int_size_in_bytes (type) == 16)))
5002 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5005 if (!TARGET_ALTIVEC)
5006 error ("Cannot pass argument in vector register because"
5007 " altivec instructions are disabled, use -maltivec"
5008 " to enable them.");
5010 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5011 even if it is going to be passed in a vector register.
5012 Darwin does the same for variable-argument functions. */
5013 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5014 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5024 /* Vector parameters must be 16-byte aligned. This places
5025 them at 2 mod 4 in terms of words in 32-bit mode, since
5026 the parameter save area starts at offset 24 from the
5027 stack. In 64-bit mode, they just have to start on an
5028 even word, since the parameter save area is 16-byte
5029 aligned. Space for GPRs is reserved even if the argument
5030 will be passed in memory. */
5032 align = (2 - cum->words) & 3;
5034 align = cum->words & 1;
5035 cum->words += align + rs6000_arg_size (mode, type);
5037 if (TARGET_DEBUG_ARG)
5039 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5041 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5042 cum->nargs_prototype, cum->prototype,
5043 GET_MODE_NAME (mode));
5047 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5049 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5052 else if (rs6000_darwin64_abi
5054 && (TREE_CODE (type) == RECORD_TYPE
5055 || TREE_CODE (type) == ARRAY_TYPE))
5056 darwin64_function_arg_advance (cum, type, named, depth);
5058 else if (DEFAULT_ABI == ABI_V4)
5060 if (TARGET_HARD_FLOAT && TARGET_FPRS
5061 && (mode == SFmode || mode == DFmode))
5063 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5068 cum->words += cum->words & 1;
5069 cum->words += rs6000_arg_size (mode, type);
5074 int n_words = rs6000_arg_size (mode, type);
5075 int gregno = cum->sysv_gregno;
5077 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5078 (r7,r8) or (r9,r10). As does any other 2 word item such
5079 as complex int due to a historical mistake. */
5081 gregno += (1 - gregno) & 1;
5083 /* Multi-reg args are not split between registers and stack. */
5084 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5086 /* Long long and SPE vectors are aligned on the stack.
5087 So are other 2 word items such as complex int due to
5088 a historical mistake. */
5090 cum->words += cum->words & 1;
5091 cum->words += n_words;
5094 /* Note: continuing to accumulate gregno past when we've started
5095 spilling to the stack indicates the fact that we've started
5096 spilling to the stack to expand_builtin_saveregs. */
5097 cum->sysv_gregno = gregno + n_words;
5100 if (TARGET_DEBUG_ARG)
5102 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5103 cum->words, cum->fregno);
5104 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5105 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5106 fprintf (stderr, "mode = %4s, named = %d\n",
5107 GET_MODE_NAME (mode), named);
5112 int n_words = rs6000_arg_size (mode, type);
5113 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5115 /* The simple alignment calculation here works because
5116 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
5117 If we ever want to handle alignments larger than 8 bytes for
5118 32-bit or 16 bytes for 64-bit, then we'll need to take into
5119 account the offset to the start of the parm save area. */
5120 align &= cum->words;
5121 cum->words += align + n_words;
5123 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5124 && TARGET_HARD_FLOAT && TARGET_FPRS)
5125 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5127 if (TARGET_DEBUG_ARG)
5129 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5130 cum->words, cum->fregno);
5131 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5132 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5133 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5134 named, align, depth);
5140 spe_build_register_parallel (enum machine_mode mode, int gregno)
5146 r1 = gen_rtx_REG (DImode, gregno);
5147 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5148 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5150 else if (mode == DCmode)
5152 r1 = gen_rtx_REG (DImode, gregno);
5153 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5154 r3 = gen_rtx_REG (DImode, gregno + 2);
5155 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5156 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5162 /* Determine where to put a SIMD argument on the SPE. */
5164 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5167 int gregno = cum->sysv_gregno;
5169 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5170 are passed and returned in a pair of GPRs for ABI compatibility. */
5171 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
5173 int n_words = rs6000_arg_size (mode, type);
5175 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5177 gregno += (1 - gregno) & 1;
5179 /* Multi-reg args are not split between registers and stack. */
5180 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5183 return spe_build_register_parallel (mode, gregno);
5187 int n_words = rs6000_arg_size (mode, type);
5189 /* SPE vectors are put in odd registers. */
5190 if (n_words == 2 && (gregno & 1) == 0)
5193 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5196 enum machine_mode m = SImode;
5198 r1 = gen_rtx_REG (m, gregno);
5199 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5200 r2 = gen_rtx_REG (m, gregno + 1);
5201 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5202 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5209 if (gregno <= GP_ARG_MAX_REG)
5210 return gen_rtx_REG (mode, gregno);
5216 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5217 the register(s) to be used for each field and subfield of a struct
5218 being passed by value, along with the offset of where the
5219 register's value may be found in the block. */
5222 rs6000_darwin64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5223 tree type, int named)
5225 tree f, ftype, offset;
5226 rtx rvec[FIRST_PSEUDO_REGISTER], sub, suboff, roffset;
5227 int k = 0, i, j, bytepos, subbytepos, tot;
5228 CUMULATIVE_ARGS saved_cum = *cum;
5229 enum machine_mode submode;
5231 switch (TREE_CODE (type))
5234 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5235 if (TREE_CODE (f) == FIELD_DECL)
5237 ftype = TREE_TYPE (f);
5238 offset = DECL_FIELD_OFFSET (f);
5239 bytepos = int_bit_position (f) / BITS_PER_UNIT;
5240 /* Force substructs to be handled as BLKmode even if
5241 they're small enough to be recorded as DImode, so we
5242 drill through to non-record fields. */
5243 submode = TYPE_MODE (ftype);
5244 if (TREE_CODE (ftype) == RECORD_TYPE)
5246 sub = function_arg (cum, submode, ftype, named);
5247 if (sub == NULL_RTX)
5249 if (GET_CODE (sub) == PARALLEL)
5251 for (i = 0; i < XVECLEN (sub, 0); i++)
5253 rtx subsub = XVECEXP (sub, 0, i);
5254 suboff = XEXP (subsub, 1);
5255 subbytepos = INTVAL (suboff);
5256 subbytepos += bytepos;
5257 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5258 subsub = XEXP (subsub, 0);
5259 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5264 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5265 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5267 /* Now do an arg advance to get all the cumulative arg
5268 stuff set correctly for the next subfield. Note that it
5269 has no lasting effect, because it is being done on a
5270 temporary copy of the cumulative arg data. */
5271 function_arg_advance (cum, submode, ftype, named, 1);
5276 tot = rs6000_arg_size (mode, type);
5281 for (j = 0; j < tot; ++j)
5283 sub = gen_rtx_REG ((TARGET_64BIT ? DImode : SImode), GP_ARG_MIN_REG + cum->words++);
5284 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5285 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5286 if (cum->words >= GP_ARG_NUM_REG)
5288 bytepos += (TARGET_64BIT ? 8 : 4);
5293 tot = int_size_in_bytes (type);
5296 ftype = TREE_TYPE (type);
5297 tot /= int_size_in_bytes (ftype);
5300 for (j = 0; j < tot; ++j)
5302 /* Force substructs to be handled as BLKmode even if
5303 they're small enough to be recorded as DImode, so we
5304 drill through to non-record fields. */
5305 submode = TYPE_MODE (ftype);
5306 if (TREE_CODE (ftype) == RECORD_TYPE)
5308 sub = function_arg (cum, submode, ftype, named);
5309 if (sub == NULL_RTX)
5311 if (GET_CODE (sub) == PARALLEL)
5313 for (i = 0; i < XVECLEN (sub, 0); i++)
5315 rtx subsub = XVECEXP (sub, 0, i);
5317 suboff = XEXP (subsub, 1);
5318 subbytepos = INTVAL (suboff);
5319 subbytepos += bytepos;
5320 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5321 subsub = XEXP (subsub, 0);
5322 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5327 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5328 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5330 /* Now do an arg advance to get all the cumulative arg
5331 stuff set correctly for the next subfield. Note that it
5332 has no lasting effect, because it is being done on a
5333 temporary copy of the cumulative arg data. */
5334 function_arg_advance (cum, submode, ftype, named, 1);
5335 bytepos += int_size_in_bytes (ftype);
5345 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5350 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5353 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5357 rtx rvec[GP_ARG_NUM_REG + 1];
5359 if (align_words >= GP_ARG_NUM_REG)
5362 n_units = rs6000_arg_size (mode, type);
5364 /* Optimize the simple case where the arg fits in one gpr, except in
5365 the case of BLKmode due to assign_parms assuming that registers are
5366 BITS_PER_WORD wide. */
5368 || (n_units == 1 && mode != BLKmode))
5369 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5372 if (align_words + n_units > GP_ARG_NUM_REG)
5373 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5374 using a magic NULL_RTX component.
5375 FIXME: This is not strictly correct. Only some of the arg
5376 belongs in memory, not all of it. However, there isn't any way
5377 to do this currently, apart from building rtx descriptions for
5378 the pieces of memory we want stored. Due to bugs in the generic
5379 code we can't use the normal function_arg_partial_nregs scheme
5380 with the PARALLEL arg description we emit here.
5381 In any case, the code to store the whole arg to memory is often
5382 more efficient than code to store pieces, and we know that space
5383 is available in the right place for the whole arg. */
5384 /* FIXME: This should be fixed since the conversion to
5385 TARGET_ARG_PARTIAL_BYTES. */
5386 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5391 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5392 rtx off = GEN_INT (i++ * 4);
5393 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5395 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5397 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5400 /* Determine where to put an argument to a function.
5401 Value is zero to push the argument on the stack,
5402 or a hard register in which to store the argument.
5404 MODE is the argument's machine mode.
5405 TYPE is the data type of the argument (as a tree).
5406 This is null for libcalls where that information may
5408 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5409 the preceding args and about the function being called.
5410 NAMED is nonzero if this argument is a named parameter
5411 (otherwise it is an extra parameter matching an ellipsis).
5413 On RS/6000 the first eight words of non-FP are normally in registers
5414 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5415 Under V.4, the first 8 FP args are in registers.
5417 If this is floating-point and no prototype is specified, we use
5418 both an FP and integer register (or possibly FP reg and stack). Library
5419 functions (when CALL_LIBCALL is set) always have the proper types for args,
5420 so we can pass the FP value just in one register. emit_library_function
5421 doesn't support PARALLEL anyway.
5423 Note that for args passed by reference, function_arg will be called
5424 with MODE and TYPE set to that of the pointer to the arg, not the arg
5428 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5429 tree type, int named)
5431 enum rs6000_abi abi = DEFAULT_ABI;
5433 /* Return a marker to indicate whether CR1 needs to set or clear the
5434 bit that V.4 uses to say fp args were passed in registers.
5435 Assume that we don't need the marker for software floating point,
5436 or compiler generated library calls. */
5437 if (mode == VOIDmode)
5440 && cum->nargs_prototype < 0
5441 && (cum->call_cookie & CALL_LIBCALL) == 0
5442 && (cum->prototype || TARGET_NO_PROTOTYPE))
5444 /* For the SPE, we need to crxor CR6 always. */
5446 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5447 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5448 return GEN_INT (cum->call_cookie
5449 | ((cum->fregno == FP_ARG_MIN_REG)
5450 ? CALL_V4_SET_FP_ARGS
5451 : CALL_V4_CLEAR_FP_ARGS));
5454 return GEN_INT (cum->call_cookie);
5458 && rs6000_darwin64_abi
5459 && (TREE_CODE (type) == RECORD_TYPE
5460 || TREE_CODE (type) == UNION_TYPE
5461 || TREE_CODE (type) == ARRAY_TYPE))
5463 rtx rslt = rs6000_darwin64_function_arg (cum, mode, type, named);
5464 if (rslt != NULL_RTX)
5466 /* Else fall through to usual handling. */
5469 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5470 if (TARGET_64BIT && ! cum->prototype)
5472 /* Vector parameters get passed in vector register
5473 and also in GPRs or memory, in absence of prototype. */
5476 align_words = (cum->words + 1) & ~1;
5478 if (align_words >= GP_ARG_NUM_REG)
5484 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5486 return gen_rtx_PARALLEL (mode,
5488 gen_rtx_EXPR_LIST (VOIDmode,
5490 gen_rtx_EXPR_LIST (VOIDmode,
5491 gen_rtx_REG (mode, cum->vregno),
5495 return gen_rtx_REG (mode, cum->vregno);
5496 else if (TARGET_ALTIVEC_ABI
5497 && (ALTIVEC_VECTOR_MODE (mode)
5498 || (type && TREE_CODE (type) == VECTOR_TYPE
5499 && int_size_in_bytes (type) == 16)))
5501 if (named || abi == ABI_V4)
5505 /* Vector parameters to varargs functions under AIX or Darwin
5506 get passed in memory and possibly also in GPRs. */
5507 int align, align_words, n_words;
5508 enum machine_mode part_mode;
5510 /* Vector parameters must be 16-byte aligned. This places them at
5511 2 mod 4 in terms of words in 32-bit mode, since the parameter
5512 save area starts at offset 24 from the stack. In 64-bit mode,
5513 they just have to start on an even word, since the parameter
5514 save area is 16-byte aligned. */
5516 align = (2 - cum->words) & 3;
5518 align = cum->words & 1;
5519 align_words = cum->words + align;
5521 /* Out of registers? Memory, then. */
5522 if (align_words >= GP_ARG_NUM_REG)
5525 if (TARGET_32BIT && TARGET_POWERPC64)
5526 return rs6000_mixed_function_arg (mode, type, align_words);
5528 /* The vector value goes in GPRs. Only the part of the
5529 value in GPRs is reported here. */
5531 n_words = rs6000_arg_size (mode, type);
5532 if (align_words + n_words > GP_ARG_NUM_REG)
5533 /* Fortunately, there are only two possibilities, the value
5534 is either wholly in GPRs or half in GPRs and half not. */
5537 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5540 else if (TARGET_SPE_ABI && TARGET_SPE
5541 && (SPE_VECTOR_MODE (mode)
5542 || (TARGET_E500_DOUBLE && (mode == DFmode
5543 || mode == DCmode))))
5544 return rs6000_spe_function_arg (cum, mode, type);
5546 else if (abi == ABI_V4)
5548 if (TARGET_HARD_FLOAT && TARGET_FPRS
5549 && (mode == SFmode || mode == DFmode))
5551 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5552 return gen_rtx_REG (mode, cum->fregno);
5558 int n_words = rs6000_arg_size (mode, type);
5559 int gregno = cum->sysv_gregno;
5561 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5562 (r7,r8) or (r9,r10). As does any other 2 word item such
5563 as complex int due to a historical mistake. */
5565 gregno += (1 - gregno) & 1;
5567 /* Multi-reg args are not split between registers and stack. */
5568 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5571 if (TARGET_32BIT && TARGET_POWERPC64)
5572 return rs6000_mixed_function_arg (mode, type,
5573 gregno - GP_ARG_MIN_REG);
5574 return gen_rtx_REG (mode, gregno);
5579 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5580 int align_words = cum->words + (cum->words & align);
5582 if (USE_FP_FOR_ARG_P (cum, mode, type))
5584 rtx rvec[GP_ARG_NUM_REG + 1];
5588 enum machine_mode fmode = mode;
5589 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5591 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5593 /* Currently, we only ever need one reg here because complex
5594 doubles are split. */
5595 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
5598 /* Long double split over regs and memory. */
5602 /* Do we also need to pass this arg in the parameter save
5605 && (cum->nargs_prototype <= 0
5606 || (DEFAULT_ABI == ABI_AIX
5608 && align_words >= GP_ARG_NUM_REG)));
5610 if (!needs_psave && mode == fmode)
5611 return gen_rtx_REG (fmode, cum->fregno);
5616 /* Describe the part that goes in gprs or the stack.
5617 This piece must come first, before the fprs. */
5618 if (align_words < GP_ARG_NUM_REG)
5620 unsigned long n_words = rs6000_arg_size (mode, type);
5622 if (align_words + n_words > GP_ARG_NUM_REG
5623 || (TARGET_32BIT && TARGET_POWERPC64))
5625 /* If this is partially on the stack, then we only
5626 include the portion actually in registers here. */
5627 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5630 if (align_words + n_words > GP_ARG_NUM_REG
5631 && (TARGET_32BIT && TARGET_POWERPC64))
5632 /* Not all of the arg fits in gprs. Say that it
5633 goes in memory too, using a magic NULL_RTX
5634 component. Also see comment in
5635 rs6000_mixed_function_arg for why the normal
5636 function_arg_partial_nregs scheme doesn't work
5638 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5642 r = gen_rtx_REG (rmode,
5643 GP_ARG_MIN_REG + align_words);
5644 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5645 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5647 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5651 /* The whole arg fits in gprs. */
5652 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5653 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5657 /* It's entirely in memory. */
5658 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5661 /* Describe where this piece goes in the fprs. */
5662 r = gen_rtx_REG (fmode, cum->fregno);
5663 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5665 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5667 else if (align_words < GP_ARG_NUM_REG)
5669 if (TARGET_32BIT && TARGET_POWERPC64)
5670 return rs6000_mixed_function_arg (mode, type, align_words);
5672 if (mode == BLKmode)
5675 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5682 /* For an arg passed partly in registers and partly in memory, this is
5683 the number of registers used. For args passed entirely in registers
5684 or entirely in memory, zero. When an arg is described by a PARALLEL,
5685 perhaps using more than one register type, this function returns the
5686 number of bytes of registers used by the PARALLEL. */
5689 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5690 tree type, bool named)
5697 if (DEFAULT_ABI == ABI_V4)
5700 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5701 && cum->nargs_prototype >= 0)
5704 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5705 parm_offset = TARGET_32BIT ? 2 : 0;
5706 align_words = cum->words + ((parm_offset - cum->words) & align);
5708 if (USE_FP_FOR_ARG_P (cum, mode, type)
5709 /* If we are passing this arg in gprs as well, then this function
5710 should return the number of gprs (or memory) partially passed,
5711 *not* the number of fprs. */
5713 && (cum->nargs_prototype <= 0
5714 || (DEFAULT_ABI == ABI_AIX
5716 && align_words >= GP_ARG_NUM_REG))))
5718 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5719 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
5720 else if (cum->nargs_prototype >= 0)
5724 if (align_words < GP_ARG_NUM_REG
5725 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5726 ret = GP_ARG_NUM_REG - align_words;
5728 ret *= (TARGET_32BIT ? 4 : 8);
5730 if (ret != 0 && TARGET_DEBUG_ARG)
5731 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5736 /* A C expression that indicates when an argument must be passed by
5737 reference. If nonzero for an argument, a copy of that argument is
5738 made in memory and a pointer to the argument is passed instead of
5739 the argument itself. The pointer is passed in whatever way is
5740 appropriate for passing a pointer to that type.
5742 Under V.4, aggregates and long double are passed by reference.
5744 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5745 reference unless the AltiVec vector extension ABI is in force.
5747 As an extension to all ABIs, variable sized types are passed by
5751 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5752 enum machine_mode mode, tree type,
5753 bool named ATTRIBUTE_UNUSED)
5755 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5757 if (TARGET_DEBUG_ARG)
5758 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5765 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5767 if (TARGET_DEBUG_ARG)
5768 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5772 if (int_size_in_bytes (type) < 0)
5774 if (TARGET_DEBUG_ARG)
5775 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5779 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5780 modes only exist for GCC vector types if -maltivec. */
5781 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5783 if (TARGET_DEBUG_ARG)
5784 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5788 /* Pass synthetic vectors in memory. */
5789 if (TREE_CODE (type) == VECTOR_TYPE
5790 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5792 static bool warned_for_pass_big_vectors = false;
5793 if (TARGET_DEBUG_ARG)
5794 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5795 if (!warned_for_pass_big_vectors)
5797 warning ("GCC vector passed by reference: "
5798 "non-standard ABI extension with no compatibility guarantee");
5799 warned_for_pass_big_vectors = true;
5808 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5811 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5816 for (i = 0; i < nregs; i++)
5818 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5819 if (reload_completed)
5821 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5824 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5825 i * GET_MODE_SIZE(reg_mode));
5828 tem = replace_equiv_address (tem, XEXP (tem, 0));
5830 if (tem == NULL_RTX)
5833 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5837 /* Perform any needed actions needed for a function that is receiving a
5838 variable number of arguments.
5842 MODE and TYPE are the mode and type of the current parameter.
5844 PRETEND_SIZE is a variable that should be set to the amount of stack
5845 that must be pushed by the prolog to pretend that our caller pushed
5848 Normally, this macro will push all remaining incoming registers on the
5849 stack and set PRETEND_SIZE to the length of the registers pushed. */
5852 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5853 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5856 CUMULATIVE_ARGS next_cum;
5857 int reg_size = TARGET_32BIT ? 4 : 8;
5858 rtx save_area = NULL_RTX, mem;
5859 int first_reg_offset, set;
5861 /* Skip the last named argument. */
5863 function_arg_advance (&next_cum, mode, type, 1, 0);
5865 if (DEFAULT_ABI == ABI_V4)
5868 save_area = plus_constant (virtual_stack_vars_rtx,
5869 - RS6000_VARARGS_SIZE);
5871 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5875 first_reg_offset = next_cum.words;
5876 save_area = virtual_incoming_args_rtx;
5878 if (targetm.calls.must_pass_in_stack (mode, type))
5879 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5882 set = get_varargs_alias_set ();
5883 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5885 mem = gen_rtx_MEM (BLKmode,
5886 plus_constant (save_area,
5887 first_reg_offset * reg_size)),
5888 set_mem_alias_set (mem, set);
5889 set_mem_align (mem, BITS_PER_WORD);
5891 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5892 GP_ARG_NUM_REG - first_reg_offset);
5895 /* Save FP registers if needed. */
5896 if (DEFAULT_ABI == ABI_V4
5897 && TARGET_HARD_FLOAT && TARGET_FPRS
5899 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5901 int fregno = next_cum.fregno;
5902 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5903 rtx lab = gen_label_rtx ();
5904 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5907 (gen_rtx_SET (VOIDmode,
5909 gen_rtx_IF_THEN_ELSE (VOIDmode,
5910 gen_rtx_NE (VOIDmode, cr1,
5912 gen_rtx_LABEL_REF (VOIDmode, lab),
5915 while (fregno <= FP_ARG_V4_MAX_REG)
5917 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5918 set_mem_alias_set (mem, set);
5919 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5920 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5929 /* Create the va_list data type. */
5932 rs6000_build_builtin_va_list (void)
5934 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5936 /* For AIX, prefer 'char *' because that's what the system
5937 header files like. */
5938 if (DEFAULT_ABI != ABI_V4)
5939 return build_pointer_type (char_type_node);
5941 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5942 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5944 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5945 unsigned_char_type_node);
5946 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5947 unsigned_char_type_node);
5948 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5950 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5951 short_unsigned_type_node);
5952 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5954 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5957 DECL_FIELD_CONTEXT (f_gpr) = record;
5958 DECL_FIELD_CONTEXT (f_fpr) = record;
5959 DECL_FIELD_CONTEXT (f_res) = record;
5960 DECL_FIELD_CONTEXT (f_ovf) = record;
5961 DECL_FIELD_CONTEXT (f_sav) = record;
5963 TREE_CHAIN (record) = type_decl;
5964 TYPE_NAME (record) = type_decl;
5965 TYPE_FIELDS (record) = f_gpr;
5966 TREE_CHAIN (f_gpr) = f_fpr;
5967 TREE_CHAIN (f_fpr) = f_res;
5968 TREE_CHAIN (f_res) = f_ovf;
5969 TREE_CHAIN (f_ovf) = f_sav;
5971 layout_type (record);
5973 /* The correct type is an array type of one element. */
5974 return build_array_type (record, build_index_type (size_zero_node));
5977 /* Implement va_start. */
5980 rs6000_va_start (tree valist, rtx nextarg)
5982 HOST_WIDE_INT words, n_gpr, n_fpr;
5983 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5984 tree gpr, fpr, ovf, sav, t;
5986 /* Only SVR4 needs something special. */
5987 if (DEFAULT_ABI != ABI_V4)
5989 std_expand_builtin_va_start (valist, nextarg);
5993 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5994 f_fpr = TREE_CHAIN (f_gpr);
5995 f_res = TREE_CHAIN (f_fpr);
5996 f_ovf = TREE_CHAIN (f_res);
5997 f_sav = TREE_CHAIN (f_ovf);
5999 valist = build_va_arg_indirect_ref (valist);
6000 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6001 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6002 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6003 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6005 /* Count number of gp and fp argument registers used. */
6006 words = current_function_args_info.words;
6007 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6009 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6012 if (TARGET_DEBUG_ARG)
6013 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6014 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6015 words, n_gpr, n_fpr);
6017 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
6018 build_int_cst (NULL_TREE, n_gpr));
6019 TREE_SIDE_EFFECTS (t) = 1;
6020 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6022 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
6023 build_int_cst (NULL_TREE, n_fpr));
6024 TREE_SIDE_EFFECTS (t) = 1;
6025 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6027 /* Find the overflow area. */
6028 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6030 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
6031 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
6032 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6033 TREE_SIDE_EFFECTS (t) = 1;
6034 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6036 /* Find the register save area. */
6037 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6038 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
6039 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
6040 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
6041 TREE_SIDE_EFFECTS (t) = 1;
6042 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6045 /* Implement va_arg. */
6048 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6050 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6051 tree gpr, fpr, ovf, sav, reg, t, u;
6052 int size, rsize, n_reg, sav_ofs, sav_scale;
6053 tree lab_false, lab_over, addr;
6055 tree ptrtype = build_pointer_type (type);
6057 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6059 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6060 return build_va_arg_indirect_ref (t);
6063 if (DEFAULT_ABI != ABI_V4)
6065 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6067 tree elem_type = TREE_TYPE (type);
6068 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6069 int elem_size = GET_MODE_SIZE (elem_mode);
6071 if (elem_size < UNITS_PER_WORD)
6073 tree real_part, imag_part;
6074 tree post = NULL_TREE;
6076 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6078 /* Copy the value into a temporary, lest the formal temporary
6079 be reused out from under us. */
6080 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6081 append_to_statement_list (post, pre_p);
6083 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6086 return build (COMPLEX_EXPR, type, real_part, imag_part);
6090 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6093 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6094 f_fpr = TREE_CHAIN (f_gpr);
6095 f_res = TREE_CHAIN (f_fpr);
6096 f_ovf = TREE_CHAIN (f_res);
6097 f_sav = TREE_CHAIN (f_ovf);
6099 valist = build_va_arg_indirect_ref (valist);
6100 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6101 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6102 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6103 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6105 size = int_size_in_bytes (type);
6106 rsize = (size + 3) / 4;
6109 if (TARGET_HARD_FLOAT && TARGET_FPRS
6110 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
6112 /* FP args go in FP registers, if present. */
6117 if (TYPE_MODE (type) == DFmode)
6122 /* Otherwise into GP registers. */
6131 /* Pull the value out of the saved registers.... */
6134 addr = create_tmp_var (ptr_type_node, "addr");
6135 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6137 /* AltiVec vectors never go in registers when -mabi=altivec. */
6138 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6142 lab_false = create_artificial_label ();
6143 lab_over = create_artificial_label ();
6145 /* Long long and SPE vectors are aligned in the registers.
6146 As are any other 2 gpr item such as complex int due to a
6147 historical mistake. */
6151 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6152 size_int (n_reg - 1));
6153 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6156 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6157 t = build2 (GE_EXPR, boolean_type_node, u, t);
6158 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6159 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6160 gimplify_and_add (t, pre_p);
6164 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6166 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6167 u = build1 (CONVERT_EXPR, integer_type_node, u);
6168 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6169 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6171 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
6172 gimplify_and_add (t, pre_p);
6174 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6175 gimplify_and_add (t, pre_p);
6177 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6178 append_to_statement_list (t, pre_p);
6182 /* Ensure that we don't find any more args in regs.
6183 Alignment has taken care of the n_reg == 2 case. */
6184 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
6185 gimplify_and_add (t, pre_p);
6189 /* ... otherwise out of the overflow area. */
6191 /* Care for on-stack alignment if needed. */
6195 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6196 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6197 build_int_cst (NULL_TREE, -align));
6199 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6201 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
6202 gimplify_and_add (u, pre_p);
6204 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6205 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6206 gimplify_and_add (t, pre_p);
6210 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6211 append_to_statement_list (t, pre_p);
6214 addr = fold_convert (ptrtype, addr);
6215 return build_va_arg_indirect_ref (addr);
6220 #define def_builtin(MASK, NAME, TYPE, CODE) \
6222 if ((MASK) & target_flags) \
6223 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
6227 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6229 static const struct builtin_description bdesc_3arg[] =
6231 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6232 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6233 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6234 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6235 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6236 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6237 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6238 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6239 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6240 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6241 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6242 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6243 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6244 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6245 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6246 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6247 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6248 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6249 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6250 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6251 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6252 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6253 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6256 /* DST operations: void foo (void *, const int, const char). */
6258 static const struct builtin_description bdesc_dst[] =
6260 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6261 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6262 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6263 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
6266 /* Simple binary operations: VECc = foo (VECa, VECb). */
6268 static struct builtin_description bdesc_2arg[] =
6270 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6271 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6272 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6273 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6274 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6275 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6276 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6277 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6278 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6279 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6280 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6281 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6282 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6283 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6284 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6285 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6286 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6287 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6288 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6289 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6290 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6291 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6292 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6293 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6294 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6295 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6296 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6297 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6298 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6299 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6300 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6301 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6302 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6303 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6304 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6305 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6306 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6307 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6308 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6309 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6310 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6311 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6312 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6313 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6314 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6315 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6316 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6317 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6318 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6319 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6320 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6321 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6322 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6323 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6324 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6325 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6326 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6327 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6328 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6329 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6330 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6331 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6332 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6333 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6334 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6335 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6336 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6337 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6338 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6339 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
6340 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6341 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
6342 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6343 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6344 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6345 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6346 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6347 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6348 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6349 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6350 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6351 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6352 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6353 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6354 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6355 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6356 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6357 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6358 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6359 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6360 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6361 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6362 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6363 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6364 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6365 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6366 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6367 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6368 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6369 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6370 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6371 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6372 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6373 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6374 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6375 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6376 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6377 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6378 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6379 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6380 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6381 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6382 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6384 /* Place holder, leave as first spe builtin. */
6385 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6386 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6387 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6388 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6389 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6390 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6391 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6392 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6393 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6394 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6395 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6396 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6397 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6398 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6399 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6400 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6401 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6402 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6403 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6404 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6405 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6406 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6407 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6408 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6409 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6410 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6411 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6412 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6413 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6414 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6415 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6416 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6417 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6418 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6419 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6420 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6421 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6422 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6423 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6424 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6425 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6426 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6427 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6428 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6429 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6430 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6431 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6432 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6433 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6434 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6435 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6436 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6437 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6438 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6439 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6440 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6441 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6442 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6443 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6444 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6445 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6446 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6447 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6448 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6449 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6450 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6451 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6452 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6453 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6454 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6455 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6456 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6457 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6458 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6459 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6460 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6461 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6462 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6463 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6464 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6465 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6466 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6467 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6468 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6469 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6470 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6471 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6472 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6473 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6474 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6475 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6476 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6477 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6478 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6479 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6480 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6481 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6482 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6483 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6484 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6485 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6486 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6487 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6488 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6489 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6490 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6491 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6492 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6493 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6495 /* SPE binary operations expecting a 5-bit unsigned literal. */
6496 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6498 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6499 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6500 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6501 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6502 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6503 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6504 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6505 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6506 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6507 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6508 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6509 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6510 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6511 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6512 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6513 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6514 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6515 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6516 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6517 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6518 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6519 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6520 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6521 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6522 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6523 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6525 /* Place-holder. Leave as last binary SPE builtin. */
6526 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
6529 /* AltiVec predicates. */
6531 struct builtin_description_predicates
6533 const unsigned int mask;
6534 const enum insn_code icode;
6536 const char *const name;
6537 const enum rs6000_builtins code;
6540 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6542 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6543 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6544 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6545 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6546 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6547 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6548 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6549 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6550 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6551 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6552 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6553 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6554 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
6557 /* SPE predicates. */
6558 static struct builtin_description bdesc_spe_predicates[] =
6560 /* Place-holder. Leave as first. */
6561 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6562 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6563 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6564 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6565 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6566 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6567 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6568 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6569 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6570 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6571 /* Place-holder. Leave as last. */
6572 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6575 /* SPE evsel predicates. */
6576 static struct builtin_description bdesc_spe_evsel[] =
6578 /* Place-holder. Leave as first. */
6579 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6580 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6581 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6582 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6583 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6584 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6585 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6586 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6587 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6588 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6589 /* Place-holder. Leave as last. */
6590 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6593 /* ABS* operations. */
6595 static const struct builtin_description bdesc_abs[] =
6597 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6598 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6599 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6600 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6601 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6602 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6603 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6606 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6609 static struct builtin_description bdesc_1arg[] =
6611 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6613 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6614 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6615 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6616 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6617 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6618 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6619 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6620 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6621 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6622 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6624 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6625 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6626 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6627 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6629 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6630 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6631 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6632 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6633 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6634 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6635 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6636 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6637 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6638 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6639 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6640 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6641 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6642 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6643 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6644 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6645 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6646 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6647 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6648 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6649 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6650 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6651 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6652 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6653 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6654 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6655 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6656 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6657 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6658 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6660 /* Place-holder. Leave as last unary SPE builtin. */
6661 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
6665 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6668 tree arg0 = TREE_VALUE (arglist);
6669 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6670 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6671 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6673 if (icode == CODE_FOR_nothing)
6674 /* Builtin not supported on this processor. */
6677 /* If we got invalid arguments bail out before generating bad rtl. */
6678 if (arg0 == error_mark_node)
6681 if (icode == CODE_FOR_altivec_vspltisb
6682 || icode == CODE_FOR_altivec_vspltish
6683 || icode == CODE_FOR_altivec_vspltisw
6684 || icode == CODE_FOR_spe_evsplatfi
6685 || icode == CODE_FOR_spe_evsplati)
6687 /* Only allow 5-bit *signed* literals. */
6688 if (GET_CODE (op0) != CONST_INT
6689 || INTVAL (op0) > 0x1f
6690 || INTVAL (op0) < -0x1f)
6692 error ("argument 1 must be a 5-bit signed literal");
6698 || GET_MODE (target) != tmode
6699 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6700 target = gen_reg_rtx (tmode);
6702 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6703 op0 = copy_to_mode_reg (mode0, op0);
6705 pat = GEN_FCN (icode) (target, op0);
6714 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6716 rtx pat, scratch1, scratch2;
6717 tree arg0 = TREE_VALUE (arglist);
6718 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6719 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6720 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6722 /* If we have invalid arguments, bail out before generating bad rtl. */
6723 if (arg0 == error_mark_node)
6727 || GET_MODE (target) != tmode
6728 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6729 target = gen_reg_rtx (tmode);
6731 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6732 op0 = copy_to_mode_reg (mode0, op0);
6734 scratch1 = gen_reg_rtx (mode0);
6735 scratch2 = gen_reg_rtx (mode0);
6737 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6746 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6749 tree arg0 = TREE_VALUE (arglist);
6750 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6751 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6752 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6753 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6754 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6755 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6757 if (icode == CODE_FOR_nothing)
6758 /* Builtin not supported on this processor. */
6761 /* If we got invalid arguments bail out before generating bad rtl. */
6762 if (arg0 == error_mark_node || arg1 == error_mark_node)
6765 if (icode == CODE_FOR_altivec_vcfux
6766 || icode == CODE_FOR_altivec_vcfsx
6767 || icode == CODE_FOR_altivec_vctsxs
6768 || icode == CODE_FOR_altivec_vctuxs
6769 || icode == CODE_FOR_altivec_vspltb
6770 || icode == CODE_FOR_altivec_vsplth
6771 || icode == CODE_FOR_altivec_vspltw
6772 || icode == CODE_FOR_spe_evaddiw
6773 || icode == CODE_FOR_spe_evldd
6774 || icode == CODE_FOR_spe_evldh
6775 || icode == CODE_FOR_spe_evldw
6776 || icode == CODE_FOR_spe_evlhhesplat
6777 || icode == CODE_FOR_spe_evlhhossplat
6778 || icode == CODE_FOR_spe_evlhhousplat
6779 || icode == CODE_FOR_spe_evlwhe
6780 || icode == CODE_FOR_spe_evlwhos
6781 || icode == CODE_FOR_spe_evlwhou
6782 || icode == CODE_FOR_spe_evlwhsplat
6783 || icode == CODE_FOR_spe_evlwwsplat
6784 || icode == CODE_FOR_spe_evrlwi
6785 || icode == CODE_FOR_spe_evslwi
6786 || icode == CODE_FOR_spe_evsrwis
6787 || icode == CODE_FOR_spe_evsubifw
6788 || icode == CODE_FOR_spe_evsrwiu)
6790 /* Only allow 5-bit unsigned literals. */
6792 if (TREE_CODE (arg1) != INTEGER_CST
6793 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6795 error ("argument 2 must be a 5-bit unsigned literal");
6801 || GET_MODE (target) != tmode
6802 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6803 target = gen_reg_rtx (tmode);
6805 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6806 op0 = copy_to_mode_reg (mode0, op0);
6807 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6808 op1 = copy_to_mode_reg (mode1, op1);
6810 pat = GEN_FCN (icode) (target, op0, op1);
6819 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6820 tree arglist, rtx target)
6823 tree cr6_form = TREE_VALUE (arglist);
6824 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6825 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6826 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6827 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6828 enum machine_mode tmode = SImode;
6829 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6830 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6833 if (TREE_CODE (cr6_form) != INTEGER_CST)
6835 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6839 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6844 /* If we have invalid arguments, bail out before generating bad rtl. */
6845 if (arg0 == error_mark_node || arg1 == error_mark_node)
6849 || GET_MODE (target) != tmode
6850 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6851 target = gen_reg_rtx (tmode);
6853 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6854 op0 = copy_to_mode_reg (mode0, op0);
6855 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6856 op1 = copy_to_mode_reg (mode1, op1);
6858 scratch = gen_reg_rtx (mode0);
6860 pat = GEN_FCN (icode) (scratch, op0, op1,
6861 gen_rtx_SYMBOL_REF (Pmode, opcode));
6866 /* The vec_any* and vec_all* predicates use the same opcodes for two
6867 different operations, but the bits in CR6 will be different
6868 depending on what information we want. So we have to play tricks
6869 with CR6 to get the right bits out.
6871 If you think this is disgusting, look at the specs for the
6872 AltiVec predicates. */
6874 switch (cr6_form_int)
6877 emit_insn (gen_cr6_test_for_zero (target));
6880 emit_insn (gen_cr6_test_for_zero_reverse (target));
6883 emit_insn (gen_cr6_test_for_lt (target));
6886 emit_insn (gen_cr6_test_for_lt_reverse (target));
6889 error ("argument 1 of __builtin_altivec_predicate is out of range");
6897 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6900 tree arg0 = TREE_VALUE (arglist);
6901 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6902 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6903 enum machine_mode mode0 = Pmode;
6904 enum machine_mode mode1 = Pmode;
6905 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6906 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6908 if (icode == CODE_FOR_nothing)
6909 /* Builtin not supported on this processor. */
6912 /* If we got invalid arguments bail out before generating bad rtl. */
6913 if (arg0 == error_mark_node || arg1 == error_mark_node)
6917 || GET_MODE (target) != tmode
6918 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6919 target = gen_reg_rtx (tmode);
6921 op1 = copy_to_mode_reg (mode1, op1);
6923 if (op0 == const0_rtx)
6925 addr = gen_rtx_MEM (tmode, op1);
6929 op0 = copy_to_mode_reg (mode0, op0);
6930 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6933 pat = GEN_FCN (icode) (target, addr);
6943 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6945 tree arg0 = TREE_VALUE (arglist);
6946 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6947 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6948 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6949 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6950 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6952 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6953 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6954 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6956 /* Invalid arguments. Bail before doing anything stoopid! */
6957 if (arg0 == error_mark_node
6958 || arg1 == error_mark_node
6959 || arg2 == error_mark_node)
6962 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6963 op0 = copy_to_mode_reg (mode2, op0);
6964 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6965 op1 = copy_to_mode_reg (mode0, op1);
6966 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6967 op2 = copy_to_mode_reg (mode1, op2);
6969 pat = GEN_FCN (icode) (op1, op2, op0);
6976 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6978 tree arg0 = TREE_VALUE (arglist);
6979 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6980 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6981 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6982 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6983 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6985 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6986 enum machine_mode mode1 = Pmode;
6987 enum machine_mode mode2 = Pmode;
6989 /* Invalid arguments. Bail before doing anything stoopid! */
6990 if (arg0 == error_mark_node
6991 || arg1 == error_mark_node
6992 || arg2 == error_mark_node)
6995 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6996 op0 = copy_to_mode_reg (tmode, op0);
6998 op2 = copy_to_mode_reg (mode2, op2);
7000 if (op1 == const0_rtx)
7002 addr = gen_rtx_MEM (tmode, op2);
7006 op1 = copy_to_mode_reg (mode1, op1);
7007 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7010 pat = GEN_FCN (icode) (addr, op0);
7017 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
7020 tree arg0 = TREE_VALUE (arglist);
7021 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7022 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7023 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7024 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7025 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7026 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7027 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7028 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7029 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7031 if (icode == CODE_FOR_nothing)
7032 /* Builtin not supported on this processor. */
7035 /* If we got invalid arguments bail out before generating bad rtl. */
7036 if (arg0 == error_mark_node
7037 || arg1 == error_mark_node
7038 || arg2 == error_mark_node)
7041 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7042 || icode == CODE_FOR_altivec_vsldoi_v4si
7043 || icode == CODE_FOR_altivec_vsldoi_v8hi
7044 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7046 /* Only allow 4-bit unsigned literals. */
7048 if (TREE_CODE (arg2) != INTEGER_CST
7049 || TREE_INT_CST_LOW (arg2) & ~0xf)
7051 error ("argument 3 must be a 4-bit unsigned literal");
7057 || GET_MODE (target) != tmode
7058 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7059 target = gen_reg_rtx (tmode);
7061 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7062 op0 = copy_to_mode_reg (mode0, op0);
7063 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7064 op1 = copy_to_mode_reg (mode1, op1);
7065 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7066 op2 = copy_to_mode_reg (mode2, op2);
7068 pat = GEN_FCN (icode) (target, op0, op1, op2);
7076 /* Expand the lvx builtins. */
7078 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7080 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7081 tree arglist = TREE_OPERAND (exp, 1);
7082 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7084 enum machine_mode tmode, mode0;
7086 enum insn_code icode;
7090 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7091 icode = CODE_FOR_altivec_lvx_v16qi;
7093 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7094 icode = CODE_FOR_altivec_lvx_v8hi;
7096 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7097 icode = CODE_FOR_altivec_lvx_v4si;
7099 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7100 icode = CODE_FOR_altivec_lvx_v4sf;
7109 arg0 = TREE_VALUE (arglist);
7110 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7111 tmode = insn_data[icode].operand[0].mode;
7112 mode0 = insn_data[icode].operand[1].mode;
7115 || GET_MODE (target) != tmode
7116 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7117 target = gen_reg_rtx (tmode);
7119 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7120 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7122 pat = GEN_FCN (icode) (target, op0);
7129 /* Expand the stvx builtins. */
7131 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7134 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7135 tree arglist = TREE_OPERAND (exp, 1);
7136 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7138 enum machine_mode mode0, mode1;
7140 enum insn_code icode;
7144 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7145 icode = CODE_FOR_altivec_stvx_v16qi;
7147 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7148 icode = CODE_FOR_altivec_stvx_v8hi;
7150 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7151 icode = CODE_FOR_altivec_stvx_v4si;
7153 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7154 icode = CODE_FOR_altivec_stvx_v4sf;
7161 arg0 = TREE_VALUE (arglist);
7162 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7163 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7164 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7165 mode0 = insn_data[icode].operand[0].mode;
7166 mode1 = insn_data[icode].operand[1].mode;
7168 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7169 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7170 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7171 op1 = copy_to_mode_reg (mode1, op1);
7173 pat = GEN_FCN (icode) (op0, op1);
7181 /* Expand the dst builtins. */
7183 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7186 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7187 tree arglist = TREE_OPERAND (exp, 1);
7188 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7189 tree arg0, arg1, arg2;
7190 enum machine_mode mode0, mode1, mode2;
7191 rtx pat, op0, op1, op2;
7192 struct builtin_description *d;
7197 /* Handle DST variants. */
7198 d = (struct builtin_description *) bdesc_dst;
7199 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7200 if (d->code == fcode)
7202 arg0 = TREE_VALUE (arglist);
7203 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7204 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7205 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7206 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7207 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7208 mode0 = insn_data[d->icode].operand[0].mode;
7209 mode1 = insn_data[d->icode].operand[1].mode;
7210 mode2 = insn_data[d->icode].operand[2].mode;
7212 /* Invalid arguments, bail out before generating bad rtl. */
7213 if (arg0 == error_mark_node
7214 || arg1 == error_mark_node
7215 || arg2 == error_mark_node)
7220 if (TREE_CODE (arg2) != INTEGER_CST
7221 || TREE_INT_CST_LOW (arg2) & ~0x3)
7223 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7227 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7228 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7229 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7230 op1 = copy_to_mode_reg (mode1, op1);
7232 pat = GEN_FCN (d->icode) (op0, op1, op2);
7242 /* Expand the builtin in EXP and store the result in TARGET. Store
7243 true in *EXPANDEDP if we found a builtin to expand. */
7245 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7247 struct builtin_description *d;
7248 struct builtin_description_predicates *dp;
7250 enum insn_code icode;
7251 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7252 tree arglist = TREE_OPERAND (exp, 1);
7255 enum machine_mode tmode, mode0;
7256 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7258 target = altivec_expand_ld_builtin (exp, target, expandedp);
7262 target = altivec_expand_st_builtin (exp, target, expandedp);
7266 target = altivec_expand_dst_builtin (exp, target, expandedp);
7274 case ALTIVEC_BUILTIN_STVX:
7275 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7276 case ALTIVEC_BUILTIN_STVEBX:
7277 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7278 case ALTIVEC_BUILTIN_STVEHX:
7279 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7280 case ALTIVEC_BUILTIN_STVEWX:
7281 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7282 case ALTIVEC_BUILTIN_STVXL:
7283 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7285 case ALTIVEC_BUILTIN_MFVSCR:
7286 icode = CODE_FOR_altivec_mfvscr;
7287 tmode = insn_data[icode].operand[0].mode;
7290 || GET_MODE (target) != tmode
7291 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7292 target = gen_reg_rtx (tmode);
7294 pat = GEN_FCN (icode) (target);
7300 case ALTIVEC_BUILTIN_MTVSCR:
7301 icode = CODE_FOR_altivec_mtvscr;
7302 arg0 = TREE_VALUE (arglist);
7303 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7304 mode0 = insn_data[icode].operand[0].mode;
7306 /* If we got invalid arguments bail out before generating bad rtl. */
7307 if (arg0 == error_mark_node)
7310 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7311 op0 = copy_to_mode_reg (mode0, op0);
7313 pat = GEN_FCN (icode) (op0);
7318 case ALTIVEC_BUILTIN_DSSALL:
7319 emit_insn (gen_altivec_dssall ());
7322 case ALTIVEC_BUILTIN_DSS:
7323 icode = CODE_FOR_altivec_dss;
7324 arg0 = TREE_VALUE (arglist);
7326 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7327 mode0 = insn_data[icode].operand[0].mode;
7329 /* If we got invalid arguments bail out before generating bad rtl. */
7330 if (arg0 == error_mark_node)
7333 if (TREE_CODE (arg0) != INTEGER_CST
7334 || TREE_INT_CST_LOW (arg0) & ~0x3)
7336 error ("argument to dss must be a 2-bit unsigned literal");
7340 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7341 op0 = copy_to_mode_reg (mode0, op0);
7343 emit_insn (gen_altivec_dss (op0));
7346 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
7347 arg0 = TREE_VALUE (arglist);
7348 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
7349 || TREE_CODE (arg0) == ARRAY_REF)
7350 arg0 = TREE_OPERAND (arg0, 0);
7351 error ("invalid parameter combination for %qs AltiVec intrinsic",
7352 TREE_STRING_POINTER (arg0));
7357 /* Expand abs* operations. */
7358 d = (struct builtin_description *) bdesc_abs;
7359 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7360 if (d->code == fcode)
7361 return altivec_expand_abs_builtin (d->icode, arglist, target);
7363 /* Expand the AltiVec predicates. */
7364 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7365 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7366 if (dp->code == fcode)
7367 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7370 /* LV* are funky. We initialized them differently. */
7373 case ALTIVEC_BUILTIN_LVSL:
7374 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7376 case ALTIVEC_BUILTIN_LVSR:
7377 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7379 case ALTIVEC_BUILTIN_LVEBX:
7380 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7382 case ALTIVEC_BUILTIN_LVEHX:
7383 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7385 case ALTIVEC_BUILTIN_LVEWX:
7386 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7388 case ALTIVEC_BUILTIN_LVXL:
7389 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7391 case ALTIVEC_BUILTIN_LVX:
7392 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7403 /* Binops that need to be initialized manually, but can be expanded
7404 automagically by rs6000_expand_binop_builtin. */
7405 static struct builtin_description bdesc_2arg_spe[] =
7407 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7408 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7409 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7410 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7411 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7412 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7413 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7414 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7415 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7416 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7417 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7418 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7419 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7420 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7421 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7422 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7423 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7424 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7425 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7426 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7427 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7428 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7431 /* Expand the builtin in EXP and store the result in TARGET. Store
7432 true in *EXPANDEDP if we found a builtin to expand.
7434 This expands the SPE builtins that are not simple unary and binary
7437 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7439 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7440 tree arglist = TREE_OPERAND (exp, 1);
7442 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7443 enum insn_code icode;
7444 enum machine_mode tmode, mode0;
7446 struct builtin_description *d;
7451 /* Syntax check for a 5-bit unsigned immediate. */
7454 case SPE_BUILTIN_EVSTDD:
7455 case SPE_BUILTIN_EVSTDH:
7456 case SPE_BUILTIN_EVSTDW:
7457 case SPE_BUILTIN_EVSTWHE:
7458 case SPE_BUILTIN_EVSTWHO:
7459 case SPE_BUILTIN_EVSTWWE:
7460 case SPE_BUILTIN_EVSTWWO:
7461 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7462 if (TREE_CODE (arg1) != INTEGER_CST
7463 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7465 error ("argument 2 must be a 5-bit unsigned literal");
7473 /* The evsplat*i instructions are not quite generic. */
7476 case SPE_BUILTIN_EVSPLATFI:
7477 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7479 case SPE_BUILTIN_EVSPLATI:
7480 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7486 d = (struct builtin_description *) bdesc_2arg_spe;
7487 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7488 if (d->code == fcode)
7489 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7491 d = (struct builtin_description *) bdesc_spe_predicates;
7492 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7493 if (d->code == fcode)
7494 return spe_expand_predicate_builtin (d->icode, arglist, target);
7496 d = (struct builtin_description *) bdesc_spe_evsel;
7497 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7498 if (d->code == fcode)
7499 return spe_expand_evsel_builtin (d->icode, arglist, target);
7503 case SPE_BUILTIN_EVSTDDX:
7504 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7505 case SPE_BUILTIN_EVSTDHX:
7506 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7507 case SPE_BUILTIN_EVSTDWX:
7508 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7509 case SPE_BUILTIN_EVSTWHEX:
7510 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7511 case SPE_BUILTIN_EVSTWHOX:
7512 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7513 case SPE_BUILTIN_EVSTWWEX:
7514 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7515 case SPE_BUILTIN_EVSTWWOX:
7516 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7517 case SPE_BUILTIN_EVSTDD:
7518 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7519 case SPE_BUILTIN_EVSTDH:
7520 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7521 case SPE_BUILTIN_EVSTDW:
7522 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7523 case SPE_BUILTIN_EVSTWHE:
7524 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7525 case SPE_BUILTIN_EVSTWHO:
7526 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7527 case SPE_BUILTIN_EVSTWWE:
7528 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7529 case SPE_BUILTIN_EVSTWWO:
7530 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7531 case SPE_BUILTIN_MFSPEFSCR:
7532 icode = CODE_FOR_spe_mfspefscr;
7533 tmode = insn_data[icode].operand[0].mode;
7536 || GET_MODE (target) != tmode
7537 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7538 target = gen_reg_rtx (tmode);
7540 pat = GEN_FCN (icode) (target);
7545 case SPE_BUILTIN_MTSPEFSCR:
7546 icode = CODE_FOR_spe_mtspefscr;
7547 arg0 = TREE_VALUE (arglist);
7548 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7549 mode0 = insn_data[icode].operand[0].mode;
7551 if (arg0 == error_mark_node)
7554 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7555 op0 = copy_to_mode_reg (mode0, op0);
7557 pat = GEN_FCN (icode) (op0);
7570 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7572 rtx pat, scratch, tmp;
7573 tree form = TREE_VALUE (arglist);
7574 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7575 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7576 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7577 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7578 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7579 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7583 if (TREE_CODE (form) != INTEGER_CST)
7585 error ("argument 1 of __builtin_spe_predicate must be a constant");
7589 form_int = TREE_INT_CST_LOW (form);
7594 if (arg0 == error_mark_node || arg1 == error_mark_node)
7598 || GET_MODE (target) != SImode
7599 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7600 target = gen_reg_rtx (SImode);
7602 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7603 op0 = copy_to_mode_reg (mode0, op0);
7604 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7605 op1 = copy_to_mode_reg (mode1, op1);
7607 scratch = gen_reg_rtx (CCmode);
7609 pat = GEN_FCN (icode) (scratch, op0, op1);
7614 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7615 _lower_. We use one compare, but look in different bits of the
7616 CR for each variant.
7618 There are 2 elements in each SPE simd type (upper/lower). The CR
7619 bits are set as follows:
7621 BIT0 | BIT 1 | BIT 2 | BIT 3
7622 U | L | (U | L) | (U & L)
7624 So, for an "all" relationship, BIT 3 would be set.
7625 For an "any" relationship, BIT 2 would be set. Etc.
7627 Following traditional nomenclature, these bits map to:
7629 BIT0 | BIT 1 | BIT 2 | BIT 3
7632 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7637 /* All variant. OV bit. */
7639 /* We need to get to the OV bit, which is the ORDERED bit. We
7640 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7641 that's ugly and will trigger a validate_condition_mode abort.
7642 So let's just use another pattern. */
7643 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7645 /* Any variant. EQ bit. */
7649 /* Upper variant. LT bit. */
7653 /* Lower variant. GT bit. */
7658 error ("argument 1 of __builtin_spe_predicate is out of range");
7662 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7663 emit_move_insn (target, tmp);
7668 /* The evsel builtins look like this:
7670 e = __builtin_spe_evsel_OP (a, b, c, d);
7674 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7675 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7679 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7682 tree arg0 = TREE_VALUE (arglist);
7683 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7684 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7685 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7686 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7687 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7688 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7689 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7690 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7691 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7696 if (arg0 == error_mark_node || arg1 == error_mark_node
7697 || arg2 == error_mark_node || arg3 == error_mark_node)
7701 || GET_MODE (target) != mode0
7702 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7703 target = gen_reg_rtx (mode0);
7705 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7706 op0 = copy_to_mode_reg (mode0, op0);
7707 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7708 op1 = copy_to_mode_reg (mode0, op1);
7709 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7710 op2 = copy_to_mode_reg (mode0, op2);
7711 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7712 op3 = copy_to_mode_reg (mode0, op3);
7714 /* Generate the compare. */
7715 scratch = gen_reg_rtx (CCmode);
7716 pat = GEN_FCN (icode) (scratch, op0, op1);
7721 if (mode0 == V2SImode)
7722 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7724 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7729 /* Expand an expression EXP that calls a built-in function,
7730 with result going to TARGET if that's convenient
7731 (and in mode MODE if that's convenient).
7732 SUBTARGET may be used as the target for computing one of EXP's operands.
7733 IGNORE is nonzero if the value is to be ignored. */
7736 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7737 enum machine_mode mode ATTRIBUTE_UNUSED,
7738 int ignore ATTRIBUTE_UNUSED)
7740 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7741 tree arglist = TREE_OPERAND (exp, 1);
7742 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7743 struct builtin_description *d;
7748 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7749 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7751 int icode = (int) CODE_FOR_altivec_lvsr;
7752 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7753 enum machine_mode mode = insn_data[icode].operand[1].mode;
7757 if (!TARGET_ALTIVEC)
7760 arg = TREE_VALUE (arglist);
7761 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7763 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7764 addr = memory_address (mode, op);
7765 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7769 /* For the load case need to negate the address. */
7770 op = gen_reg_rtx (GET_MODE (addr));
7771 emit_insn (gen_rtx_SET (VOIDmode, op,
7772 gen_rtx_NEG (GET_MODE (addr), addr)));
7774 op = gen_rtx_MEM (mode, op);
7777 || GET_MODE (target) != tmode
7778 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7779 target = gen_reg_rtx (tmode);
7781 /*pat = gen_altivec_lvsr (target, op);*/
7782 pat = GEN_FCN (icode) (target, op);
7792 ret = altivec_expand_builtin (exp, target, &success);
7799 ret = spe_expand_builtin (exp, target, &success);
7805 if (TARGET_ALTIVEC || TARGET_SPE)
7807 /* Handle simple unary operations. */
7808 d = (struct builtin_description *) bdesc_1arg;
7809 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7810 if (d->code == fcode)
7811 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7813 /* Handle simple binary operations. */
7814 d = (struct builtin_description *) bdesc_2arg;
7815 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7816 if (d->code == fcode)
7817 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7819 /* Handle simple ternary operations. */
7820 d = (struct builtin_description *) bdesc_3arg;
7821 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7822 if (d->code == fcode)
7823 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7831 build_opaque_vector_type (tree node, int nunits)
7833 node = copy_node (node);
7834 TYPE_MAIN_VARIANT (node) = node;
7835 return build_vector_type (node, nunits);
7839 rs6000_init_builtins (void)
7841 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7842 V2SF_type_node = build_vector_type (float_type_node, 2);
7843 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7844 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7845 V4SF_type_node = build_vector_type (float_type_node, 4);
7846 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7847 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7849 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7850 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7851 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7853 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7854 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7855 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7857 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7858 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7859 'vector unsigned short'. */
7861 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7862 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7863 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7864 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7866 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7867 get_identifier ("__bool char"),
7868 bool_char_type_node));
7869 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7870 get_identifier ("__bool short"),
7871 bool_short_type_node));
7872 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7873 get_identifier ("__bool int"),
7874 bool_int_type_node));
7875 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7876 get_identifier ("__pixel"),
7879 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7880 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7881 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7882 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7884 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7885 get_identifier ("__vector unsigned char"),
7886 unsigned_V16QI_type_node));
7887 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7888 get_identifier ("__vector signed char"),
7890 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7891 get_identifier ("__vector __bool char"),
7892 bool_V16QI_type_node));
7894 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7895 get_identifier ("__vector unsigned short"),
7896 unsigned_V8HI_type_node));
7897 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7898 get_identifier ("__vector signed short"),
7900 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7901 get_identifier ("__vector __bool short"),
7902 bool_V8HI_type_node));
7904 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7905 get_identifier ("__vector unsigned int"),
7906 unsigned_V4SI_type_node));
7907 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7908 get_identifier ("__vector signed int"),
7910 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7911 get_identifier ("__vector __bool int"),
7912 bool_V4SI_type_node));
7914 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7915 get_identifier ("__vector float"),
7917 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7918 get_identifier ("__vector __pixel"),
7919 pixel_V8HI_type_node));
7922 spe_init_builtins ();
7924 altivec_init_builtins ();
7925 if (TARGET_ALTIVEC || TARGET_SPE)
7926 rs6000_common_init_builtins ();
7929 /* Search through a set of builtins and enable the mask bits.
7930 DESC is an array of builtins.
7931 SIZE is the total number of builtins.
7932 START is the builtin enum at which to start.
7933 END is the builtin enum at which to end. */
7935 enable_mask_for_builtins (struct builtin_description *desc, int size,
7936 enum rs6000_builtins start,
7937 enum rs6000_builtins end)
7941 for (i = 0; i < size; ++i)
7942 if (desc[i].code == start)
7948 for (; i < size; ++i)
7950 /* Flip all the bits on. */
7951 desc[i].mask = target_flags;
7952 if (desc[i].code == end)
7958 spe_init_builtins (void)
7960 tree endlink = void_list_node;
7961 tree puint_type_node = build_pointer_type (unsigned_type_node);
7962 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7963 struct builtin_description *d;
7966 tree v2si_ftype_4_v2si
7967 = build_function_type
7968 (opaque_V2SI_type_node,
7969 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7970 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7971 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7972 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7975 tree v2sf_ftype_4_v2sf
7976 = build_function_type
7977 (opaque_V2SF_type_node,
7978 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7979 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7980 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7981 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7984 tree int_ftype_int_v2si_v2si
7985 = build_function_type
7987 tree_cons (NULL_TREE, integer_type_node,
7988 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7989 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7992 tree int_ftype_int_v2sf_v2sf
7993 = build_function_type
7995 tree_cons (NULL_TREE, integer_type_node,
7996 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7997 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8000 tree void_ftype_v2si_puint_int
8001 = build_function_type (void_type_node,
8002 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8003 tree_cons (NULL_TREE, puint_type_node,
8004 tree_cons (NULL_TREE,
8008 tree void_ftype_v2si_puint_char
8009 = build_function_type (void_type_node,
8010 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8011 tree_cons (NULL_TREE, puint_type_node,
8012 tree_cons (NULL_TREE,
8016 tree void_ftype_v2si_pv2si_int
8017 = build_function_type (void_type_node,
8018 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8019 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8020 tree_cons (NULL_TREE,
8024 tree void_ftype_v2si_pv2si_char
8025 = build_function_type (void_type_node,
8026 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8027 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8028 tree_cons (NULL_TREE,
8033 = build_function_type (void_type_node,
8034 tree_cons (NULL_TREE, integer_type_node, endlink));
8037 = build_function_type (integer_type_node, endlink);
8039 tree v2si_ftype_pv2si_int
8040 = build_function_type (opaque_V2SI_type_node,
8041 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8042 tree_cons (NULL_TREE, integer_type_node,
8045 tree v2si_ftype_puint_int
8046 = build_function_type (opaque_V2SI_type_node,
8047 tree_cons (NULL_TREE, puint_type_node,
8048 tree_cons (NULL_TREE, integer_type_node,
8051 tree v2si_ftype_pushort_int
8052 = build_function_type (opaque_V2SI_type_node,
8053 tree_cons (NULL_TREE, pushort_type_node,
8054 tree_cons (NULL_TREE, integer_type_node,
8057 tree v2si_ftype_signed_char
8058 = build_function_type (opaque_V2SI_type_node,
8059 tree_cons (NULL_TREE, signed_char_type_node,
8062 /* The initialization of the simple binary and unary builtins is
8063 done in rs6000_common_init_builtins, but we have to enable the
8064 mask bits here manually because we have run out of `target_flags'
8065 bits. We really need to redesign this mask business. */
8067 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8068 ARRAY_SIZE (bdesc_2arg),
8071 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8072 ARRAY_SIZE (bdesc_1arg),
8074 SPE_BUILTIN_EVSUBFUSIAAW);
8075 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8076 ARRAY_SIZE (bdesc_spe_predicates),
8077 SPE_BUILTIN_EVCMPEQ,
8078 SPE_BUILTIN_EVFSTSTLT);
8079 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8080 ARRAY_SIZE (bdesc_spe_evsel),
8081 SPE_BUILTIN_EVSEL_CMPGTS,
8082 SPE_BUILTIN_EVSEL_FSTSTEQ);
8084 (*lang_hooks.decls.pushdecl)
8085 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8086 opaque_V2SI_type_node));
8088 /* Initialize irregular SPE builtins. */
8090 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8091 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8092 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8093 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8094 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8095 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8096 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8097 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8098 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8099 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8100 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8101 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8102 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8103 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8104 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8105 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8106 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8107 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8110 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8111 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8112 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8113 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8114 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8115 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8116 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8117 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8118 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8119 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8120 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8121 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8122 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8123 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8124 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8125 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8126 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8127 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8128 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8129 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8130 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8131 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8134 d = (struct builtin_description *) bdesc_spe_predicates;
8135 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8139 switch (insn_data[d->icode].operand[1].mode)
8142 type = int_ftype_int_v2si_v2si;
8145 type = int_ftype_int_v2sf_v2sf;
8151 def_builtin (d->mask, d->name, type, d->code);
8154 /* Evsel predicates. */
8155 d = (struct builtin_description *) bdesc_spe_evsel;
8156 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8160 switch (insn_data[d->icode].operand[1].mode)
8163 type = v2si_ftype_4_v2si;
8166 type = v2sf_ftype_4_v2sf;
8172 def_builtin (d->mask, d->name, type, d->code);
8177 altivec_init_builtins (void)
8179 struct builtin_description *d;
8180 struct builtin_description_predicates *dp;
8182 tree pfloat_type_node = build_pointer_type (float_type_node);
8183 tree pint_type_node = build_pointer_type (integer_type_node);
8184 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8185 tree pchar_type_node = build_pointer_type (char_type_node);
8187 tree pvoid_type_node = build_pointer_type (void_type_node);
8189 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8190 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8191 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8192 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8194 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8196 tree int_ftype_int_v4si_v4si
8197 = build_function_type_list (integer_type_node,
8198 integer_type_node, V4SI_type_node,
8199 V4SI_type_node, NULL_TREE);
8200 tree v4sf_ftype_pcfloat
8201 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8202 tree void_ftype_pfloat_v4sf
8203 = build_function_type_list (void_type_node,
8204 pfloat_type_node, V4SF_type_node, NULL_TREE);
8205 tree v4si_ftype_pcint
8206 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8207 tree void_ftype_pint_v4si
8208 = build_function_type_list (void_type_node,
8209 pint_type_node, V4SI_type_node, NULL_TREE);
8210 tree v8hi_ftype_pcshort
8211 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8212 tree void_ftype_pshort_v8hi
8213 = build_function_type_list (void_type_node,
8214 pshort_type_node, V8HI_type_node, NULL_TREE);
8215 tree v16qi_ftype_pcchar
8216 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8217 tree void_ftype_pchar_v16qi
8218 = build_function_type_list (void_type_node,
8219 pchar_type_node, V16QI_type_node, NULL_TREE);
8220 tree void_ftype_v4si
8221 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8222 tree v8hi_ftype_void
8223 = build_function_type (V8HI_type_node, void_list_node);
8224 tree void_ftype_void
8225 = build_function_type (void_type_node, void_list_node);
8227 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8229 tree v16qi_ftype_long_pcvoid
8230 = build_function_type_list (V16QI_type_node,
8231 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8232 tree v8hi_ftype_long_pcvoid
8233 = build_function_type_list (V8HI_type_node,
8234 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8235 tree v4si_ftype_long_pcvoid
8236 = build_function_type_list (V4SI_type_node,
8237 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8239 tree void_ftype_v4si_long_pvoid
8240 = build_function_type_list (void_type_node,
8241 V4SI_type_node, long_integer_type_node,
8242 pvoid_type_node, NULL_TREE);
8243 tree void_ftype_v16qi_long_pvoid
8244 = build_function_type_list (void_type_node,
8245 V16QI_type_node, long_integer_type_node,
8246 pvoid_type_node, NULL_TREE);
8247 tree void_ftype_v8hi_long_pvoid
8248 = build_function_type_list (void_type_node,
8249 V8HI_type_node, long_integer_type_node,
8250 pvoid_type_node, NULL_TREE);
8251 tree int_ftype_int_v8hi_v8hi
8252 = build_function_type_list (integer_type_node,
8253 integer_type_node, V8HI_type_node,
8254 V8HI_type_node, NULL_TREE);
8255 tree int_ftype_int_v16qi_v16qi
8256 = build_function_type_list (integer_type_node,
8257 integer_type_node, V16QI_type_node,
8258 V16QI_type_node, NULL_TREE);
8259 tree int_ftype_int_v4sf_v4sf
8260 = build_function_type_list (integer_type_node,
8261 integer_type_node, V4SF_type_node,
8262 V4SF_type_node, NULL_TREE);
8263 tree v4si_ftype_v4si
8264 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8265 tree v8hi_ftype_v8hi
8266 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8267 tree v16qi_ftype_v16qi
8268 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8269 tree v4sf_ftype_v4sf
8270 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8271 tree void_ftype_pcvoid_int_int
8272 = build_function_type_list (void_type_node,
8273 pcvoid_type_node, integer_type_node,
8274 integer_type_node, NULL_TREE);
8275 tree int_ftype_pcchar
8276 = build_function_type_list (integer_type_node,
8277 pcchar_type_node, NULL_TREE);
8279 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8280 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8281 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8282 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8283 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8284 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8285 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8286 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8287 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8288 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8289 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8290 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8291 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8292 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8293 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8294 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8295 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8296 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8297 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8298 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8299 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8300 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8301 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8302 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8303 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8304 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8305 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8306 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8307 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8308 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8309 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8310 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8312 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
8313 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
8314 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
8316 /* Add the DST variants. */
8317 d = (struct builtin_description *) bdesc_dst;
8318 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8319 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8321 /* Initialize the predicates. */
8322 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8323 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8325 enum machine_mode mode1;
8328 mode1 = insn_data[dp->icode].operand[1].mode;
8333 type = int_ftype_int_v4si_v4si;
8336 type = int_ftype_int_v8hi_v8hi;
8339 type = int_ftype_int_v16qi_v16qi;
8342 type = int_ftype_int_v4sf_v4sf;
8348 def_builtin (dp->mask, dp->name, type, dp->code);
8351 /* Initialize the abs* operators. */
8352 d = (struct builtin_description *) bdesc_abs;
8353 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8355 enum machine_mode mode0;
8358 mode0 = insn_data[d->icode].operand[0].mode;
8363 type = v4si_ftype_v4si;
8366 type = v8hi_ftype_v8hi;
8369 type = v16qi_ftype_v16qi;
8372 type = v4sf_ftype_v4sf;
8378 def_builtin (d->mask, d->name, type, d->code);
8385 /* Initialize target builtin that implements
8386 targetm.vectorize.builtin_mask_for_load. */
8388 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8389 v16qi_ftype_long_pcvoid,
8390 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8391 BUILT_IN_MD, NULL, NULL_TREE);
8392 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8393 altivec_builtin_mask_for_load = decl;
8398 rs6000_common_init_builtins (void)
8400 struct builtin_description *d;
8403 tree v4sf_ftype_v4sf_v4sf_v16qi
8404 = build_function_type_list (V4SF_type_node,
8405 V4SF_type_node, V4SF_type_node,
8406 V16QI_type_node, NULL_TREE);
8407 tree v4si_ftype_v4si_v4si_v16qi
8408 = build_function_type_list (V4SI_type_node,
8409 V4SI_type_node, V4SI_type_node,
8410 V16QI_type_node, NULL_TREE);
8411 tree v8hi_ftype_v8hi_v8hi_v16qi
8412 = build_function_type_list (V8HI_type_node,
8413 V8HI_type_node, V8HI_type_node,
8414 V16QI_type_node, NULL_TREE);
8415 tree v16qi_ftype_v16qi_v16qi_v16qi
8416 = build_function_type_list (V16QI_type_node,
8417 V16QI_type_node, V16QI_type_node,
8418 V16QI_type_node, NULL_TREE);
8420 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8422 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8423 tree v16qi_ftype_int
8424 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8425 tree v8hi_ftype_v16qi
8426 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8427 tree v4sf_ftype_v4sf
8428 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8430 tree v2si_ftype_v2si_v2si
8431 = build_function_type_list (opaque_V2SI_type_node,
8432 opaque_V2SI_type_node,
8433 opaque_V2SI_type_node, NULL_TREE);
8435 tree v2sf_ftype_v2sf_v2sf
8436 = build_function_type_list (opaque_V2SF_type_node,
8437 opaque_V2SF_type_node,
8438 opaque_V2SF_type_node, NULL_TREE);
8440 tree v2si_ftype_int_int
8441 = build_function_type_list (opaque_V2SI_type_node,
8442 integer_type_node, integer_type_node,
8445 tree v2si_ftype_v2si
8446 = build_function_type_list (opaque_V2SI_type_node,
8447 opaque_V2SI_type_node, NULL_TREE);
8449 tree v2sf_ftype_v2sf
8450 = build_function_type_list (opaque_V2SF_type_node,
8451 opaque_V2SF_type_node, NULL_TREE);
8453 tree v2sf_ftype_v2si
8454 = build_function_type_list (opaque_V2SF_type_node,
8455 opaque_V2SI_type_node, NULL_TREE);
8457 tree v2si_ftype_v2sf
8458 = build_function_type_list (opaque_V2SI_type_node,
8459 opaque_V2SF_type_node, NULL_TREE);
8461 tree v2si_ftype_v2si_char
8462 = build_function_type_list (opaque_V2SI_type_node,
8463 opaque_V2SI_type_node,
8464 char_type_node, NULL_TREE);
8466 tree v2si_ftype_int_char
8467 = build_function_type_list (opaque_V2SI_type_node,
8468 integer_type_node, char_type_node, NULL_TREE);
8470 tree v2si_ftype_char
8471 = build_function_type_list (opaque_V2SI_type_node,
8472 char_type_node, NULL_TREE);
8474 tree int_ftype_int_int
8475 = build_function_type_list (integer_type_node,
8476 integer_type_node, integer_type_node,
8479 tree v4si_ftype_v4si_v4si
8480 = build_function_type_list (V4SI_type_node,
8481 V4SI_type_node, V4SI_type_node, NULL_TREE);
8482 tree v4sf_ftype_v4si_int
8483 = build_function_type_list (V4SF_type_node,
8484 V4SI_type_node, integer_type_node, NULL_TREE);
8485 tree v4si_ftype_v4sf_int
8486 = build_function_type_list (V4SI_type_node,
8487 V4SF_type_node, integer_type_node, NULL_TREE);
8488 tree v4si_ftype_v4si_int
8489 = build_function_type_list (V4SI_type_node,
8490 V4SI_type_node, integer_type_node, NULL_TREE);
8491 tree v8hi_ftype_v8hi_int
8492 = build_function_type_list (V8HI_type_node,
8493 V8HI_type_node, integer_type_node, NULL_TREE);
8494 tree v16qi_ftype_v16qi_int
8495 = build_function_type_list (V16QI_type_node,
8496 V16QI_type_node, integer_type_node, NULL_TREE);
8497 tree v16qi_ftype_v16qi_v16qi_int
8498 = build_function_type_list (V16QI_type_node,
8499 V16QI_type_node, V16QI_type_node,
8500 integer_type_node, NULL_TREE);
8501 tree v8hi_ftype_v8hi_v8hi_int
8502 = build_function_type_list (V8HI_type_node,
8503 V8HI_type_node, V8HI_type_node,
8504 integer_type_node, NULL_TREE);
8505 tree v4si_ftype_v4si_v4si_int
8506 = build_function_type_list (V4SI_type_node,
8507 V4SI_type_node, V4SI_type_node,
8508 integer_type_node, NULL_TREE);
8509 tree v4sf_ftype_v4sf_v4sf_int
8510 = build_function_type_list (V4SF_type_node,
8511 V4SF_type_node, V4SF_type_node,
8512 integer_type_node, NULL_TREE);
8513 tree v4sf_ftype_v4sf_v4sf
8514 = build_function_type_list (V4SF_type_node,
8515 V4SF_type_node, V4SF_type_node, NULL_TREE);
8516 tree v4sf_ftype_v4sf_v4sf_v4si
8517 = build_function_type_list (V4SF_type_node,
8518 V4SF_type_node, V4SF_type_node,
8519 V4SI_type_node, NULL_TREE);
8520 tree v4sf_ftype_v4sf_v4sf_v4sf
8521 = build_function_type_list (V4SF_type_node,
8522 V4SF_type_node, V4SF_type_node,
8523 V4SF_type_node, NULL_TREE);
8524 tree v4si_ftype_v4si_v4si_v4si
8525 = build_function_type_list (V4SI_type_node,
8526 V4SI_type_node, V4SI_type_node,
8527 V4SI_type_node, NULL_TREE);
8528 tree v8hi_ftype_v8hi_v8hi
8529 = build_function_type_list (V8HI_type_node,
8530 V8HI_type_node, V8HI_type_node, NULL_TREE);
8531 tree v8hi_ftype_v8hi_v8hi_v8hi
8532 = build_function_type_list (V8HI_type_node,
8533 V8HI_type_node, V8HI_type_node,
8534 V8HI_type_node, NULL_TREE);
8535 tree v4si_ftype_v8hi_v8hi_v4si
8536 = build_function_type_list (V4SI_type_node,
8537 V8HI_type_node, V8HI_type_node,
8538 V4SI_type_node, NULL_TREE);
8539 tree v4si_ftype_v16qi_v16qi_v4si
8540 = build_function_type_list (V4SI_type_node,
8541 V16QI_type_node, V16QI_type_node,
8542 V4SI_type_node, NULL_TREE);
8543 tree v16qi_ftype_v16qi_v16qi
8544 = build_function_type_list (V16QI_type_node,
8545 V16QI_type_node, V16QI_type_node, NULL_TREE);
8546 tree v4si_ftype_v4sf_v4sf
8547 = build_function_type_list (V4SI_type_node,
8548 V4SF_type_node, V4SF_type_node, NULL_TREE);
8549 tree v8hi_ftype_v16qi_v16qi
8550 = build_function_type_list (V8HI_type_node,
8551 V16QI_type_node, V16QI_type_node, NULL_TREE);
8552 tree v4si_ftype_v8hi_v8hi
8553 = build_function_type_list (V4SI_type_node,
8554 V8HI_type_node, V8HI_type_node, NULL_TREE);
8555 tree v8hi_ftype_v4si_v4si
8556 = build_function_type_list (V8HI_type_node,
8557 V4SI_type_node, V4SI_type_node, NULL_TREE);
8558 tree v16qi_ftype_v8hi_v8hi
8559 = build_function_type_list (V16QI_type_node,
8560 V8HI_type_node, V8HI_type_node, NULL_TREE);
8561 tree v4si_ftype_v16qi_v4si
8562 = build_function_type_list (V4SI_type_node,
8563 V16QI_type_node, V4SI_type_node, NULL_TREE);
8564 tree v4si_ftype_v16qi_v16qi
8565 = build_function_type_list (V4SI_type_node,
8566 V16QI_type_node, V16QI_type_node, NULL_TREE);
8567 tree v4si_ftype_v8hi_v4si
8568 = build_function_type_list (V4SI_type_node,
8569 V8HI_type_node, V4SI_type_node, NULL_TREE);
8570 tree v4si_ftype_v8hi
8571 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8572 tree int_ftype_v4si_v4si
8573 = build_function_type_list (integer_type_node,
8574 V4SI_type_node, V4SI_type_node, NULL_TREE);
8575 tree int_ftype_v4sf_v4sf
8576 = build_function_type_list (integer_type_node,
8577 V4SF_type_node, V4SF_type_node, NULL_TREE);
8578 tree int_ftype_v16qi_v16qi
8579 = build_function_type_list (integer_type_node,
8580 V16QI_type_node, V16QI_type_node, NULL_TREE);
8581 tree int_ftype_v8hi_v8hi
8582 = build_function_type_list (integer_type_node,
8583 V8HI_type_node, V8HI_type_node, NULL_TREE);
8585 /* Add the simple ternary operators. */
8586 d = (struct builtin_description *) bdesc_3arg;
8587 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8590 enum machine_mode mode0, mode1, mode2, mode3;
8593 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8596 mode0 = insn_data[d->icode].operand[0].mode;
8597 mode1 = insn_data[d->icode].operand[1].mode;
8598 mode2 = insn_data[d->icode].operand[2].mode;
8599 mode3 = insn_data[d->icode].operand[3].mode;
8601 /* When all four are of the same mode. */
8602 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8607 type = v4si_ftype_v4si_v4si_v4si;
8610 type = v4sf_ftype_v4sf_v4sf_v4sf;
8613 type = v8hi_ftype_v8hi_v8hi_v8hi;
8616 type = v16qi_ftype_v16qi_v16qi_v16qi;
8622 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8627 type = v4si_ftype_v4si_v4si_v16qi;
8630 type = v4sf_ftype_v4sf_v4sf_v16qi;
8633 type = v8hi_ftype_v8hi_v8hi_v16qi;
8636 type = v16qi_ftype_v16qi_v16qi_v16qi;
8642 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8643 && mode3 == V4SImode)
8644 type = v4si_ftype_v16qi_v16qi_v4si;
8645 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8646 && mode3 == V4SImode)
8647 type = v4si_ftype_v8hi_v8hi_v4si;
8648 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8649 && mode3 == V4SImode)
8650 type = v4sf_ftype_v4sf_v4sf_v4si;
8652 /* vchar, vchar, vchar, 4 bit literal. */
8653 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8655 type = v16qi_ftype_v16qi_v16qi_int;
8657 /* vshort, vshort, vshort, 4 bit literal. */
8658 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8660 type = v8hi_ftype_v8hi_v8hi_int;
8662 /* vint, vint, vint, 4 bit literal. */
8663 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8665 type = v4si_ftype_v4si_v4si_int;
8667 /* vfloat, vfloat, vfloat, 4 bit literal. */
8668 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8670 type = v4sf_ftype_v4sf_v4sf_int;
8675 def_builtin (d->mask, d->name, type, d->code);
8678 /* Add the simple binary operators. */
8679 d = (struct builtin_description *) bdesc_2arg;
8680 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8682 enum machine_mode mode0, mode1, mode2;
8685 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8688 mode0 = insn_data[d->icode].operand[0].mode;
8689 mode1 = insn_data[d->icode].operand[1].mode;
8690 mode2 = insn_data[d->icode].operand[2].mode;
8692 /* When all three operands are of the same mode. */
8693 if (mode0 == mode1 && mode1 == mode2)
8698 type = v4sf_ftype_v4sf_v4sf;
8701 type = v4si_ftype_v4si_v4si;
8704 type = v16qi_ftype_v16qi_v16qi;
8707 type = v8hi_ftype_v8hi_v8hi;
8710 type = v2si_ftype_v2si_v2si;
8713 type = v2sf_ftype_v2sf_v2sf;
8716 type = int_ftype_int_int;
8723 /* A few other combos we really don't want to do manually. */
8725 /* vint, vfloat, vfloat. */
8726 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8727 type = v4si_ftype_v4sf_v4sf;
8729 /* vshort, vchar, vchar. */
8730 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8731 type = v8hi_ftype_v16qi_v16qi;
8733 /* vint, vshort, vshort. */
8734 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8735 type = v4si_ftype_v8hi_v8hi;
8737 /* vshort, vint, vint. */
8738 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8739 type = v8hi_ftype_v4si_v4si;
8741 /* vchar, vshort, vshort. */
8742 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8743 type = v16qi_ftype_v8hi_v8hi;
8745 /* vint, vchar, vint. */
8746 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8747 type = v4si_ftype_v16qi_v4si;
8749 /* vint, vchar, vchar. */
8750 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8751 type = v4si_ftype_v16qi_v16qi;
8753 /* vint, vshort, vint. */
8754 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8755 type = v4si_ftype_v8hi_v4si;
8757 /* vint, vint, 5 bit literal. */
8758 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8759 type = v4si_ftype_v4si_int;
8761 /* vshort, vshort, 5 bit literal. */
8762 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8763 type = v8hi_ftype_v8hi_int;
8765 /* vchar, vchar, 5 bit literal. */
8766 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8767 type = v16qi_ftype_v16qi_int;
8769 /* vfloat, vint, 5 bit literal. */
8770 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8771 type = v4sf_ftype_v4si_int;
8773 /* vint, vfloat, 5 bit literal. */
8774 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8775 type = v4si_ftype_v4sf_int;
8777 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8778 type = v2si_ftype_int_int;
8780 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8781 type = v2si_ftype_v2si_char;
8783 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8784 type = v2si_ftype_int_char;
8787 else if (mode0 == SImode)
8792 type = int_ftype_v4si_v4si;
8795 type = int_ftype_v4sf_v4sf;
8798 type = int_ftype_v16qi_v16qi;
8801 type = int_ftype_v8hi_v8hi;
8811 def_builtin (d->mask, d->name, type, d->code);
8814 /* Add the simple unary operators. */
8815 d = (struct builtin_description *) bdesc_1arg;
8816 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8818 enum machine_mode mode0, mode1;
8821 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8824 mode0 = insn_data[d->icode].operand[0].mode;
8825 mode1 = insn_data[d->icode].operand[1].mode;
8827 if (mode0 == V4SImode && mode1 == QImode)
8828 type = v4si_ftype_int;
8829 else if (mode0 == V8HImode && mode1 == QImode)
8830 type = v8hi_ftype_int;
8831 else if (mode0 == V16QImode && mode1 == QImode)
8832 type = v16qi_ftype_int;
8833 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8834 type = v4sf_ftype_v4sf;
8835 else if (mode0 == V8HImode && mode1 == V16QImode)
8836 type = v8hi_ftype_v16qi;
8837 else if (mode0 == V4SImode && mode1 == V8HImode)
8838 type = v4si_ftype_v8hi;
8839 else if (mode0 == V2SImode && mode1 == V2SImode)
8840 type = v2si_ftype_v2si;
8841 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8842 type = v2sf_ftype_v2sf;
8843 else if (mode0 == V2SFmode && mode1 == V2SImode)
8844 type = v2sf_ftype_v2si;
8845 else if (mode0 == V2SImode && mode1 == V2SFmode)
8846 type = v2si_ftype_v2sf;
8847 else if (mode0 == V2SImode && mode1 == QImode)
8848 type = v2si_ftype_char;
8852 def_builtin (d->mask, d->name, type, d->code);
8857 rs6000_init_libfuncs (void)
8859 if (!TARGET_HARD_FLOAT)
8862 if (DEFAULT_ABI != ABI_V4)
8864 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8866 /* AIX library routines for float->int conversion. */
8867 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8868 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8869 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8870 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8873 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8874 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8875 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8876 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8877 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8881 /* 32-bit SVR4 quad floating point routines. */
8883 set_optab_libfunc (add_optab, TFmode, "_q_add");
8884 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8885 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8886 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8887 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8888 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8889 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8891 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8892 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8893 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8894 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8895 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8896 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8898 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8899 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8900 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8901 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8902 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8903 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8904 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8909 /* Expand a block clear operation, and return 1 if successful. Return 0
8910 if we should let the compiler generate normal code.
8912 operands[0] is the destination
8913 operands[1] is the length
8914 operands[2] is the alignment */
8917 expand_block_clear (rtx operands[])
8919 rtx orig_dest = operands[0];
8920 rtx bytes_rtx = operands[1];
8921 rtx align_rtx = operands[2];
8922 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8923 HOST_WIDE_INT align;
8924 HOST_WIDE_INT bytes;
8929 /* If this is not a fixed size move, just call memcpy */
8933 /* If this is not a fixed size alignment, abort */
8934 if (GET_CODE (align_rtx) != CONST_INT)
8936 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8938 /* Anything to clear? */
8939 bytes = INTVAL (bytes_rtx);
8943 /* Use the builtin memset after a point, to avoid huge code bloat.
8944 When optimize_size, avoid any significant code bloat; calling
8945 memset is about 4 instructions, so allow for one instruction to
8946 load zero and three to do clearing. */
8947 if (TARGET_ALTIVEC && align >= 128)
8949 else if (TARGET_POWERPC64 && align >= 32)
8954 if (optimize_size && bytes > 3 * clear_step)
8956 if (! optimize_size && bytes > 8 * clear_step)
8959 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8961 enum machine_mode mode = BLKmode;
8964 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8969 else if (bytes >= 8 && TARGET_POWERPC64
8970 /* 64-bit loads and stores require word-aligned
8972 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8977 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8978 { /* move 4 bytes */
8982 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8983 { /* move 2 bytes */
8987 else /* move 1 byte at a time */
8993 dest = adjust_address (orig_dest, mode, offset);
8995 emit_move_insn (dest, CONST0_RTX (mode));
9002 /* Expand a block move operation, and return 1 if successful. Return 0
9003 if we should let the compiler generate normal code.
9005 operands[0] is the destination
9006 operands[1] is the source
9007 operands[2] is the length
9008 operands[3] is the alignment */
9010 #define MAX_MOVE_REG 4
9013 expand_block_move (rtx operands[])
9015 rtx orig_dest = operands[0];
9016 rtx orig_src = operands[1];
9017 rtx bytes_rtx = operands[2];
9018 rtx align_rtx = operands[3];
9019 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9024 rtx stores[MAX_MOVE_REG];
9027 /* If this is not a fixed size move, just call memcpy */
9031 /* If this is not a fixed size alignment, abort */
9032 if (GET_CODE (align_rtx) != CONST_INT)
9034 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9036 /* Anything to move? */
9037 bytes = INTVAL (bytes_rtx);
9041 /* store_one_arg depends on expand_block_move to handle at least the size of
9042 reg_parm_stack_space. */
9043 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9046 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9049 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9050 rtx (*mov) (rtx, rtx);
9052 enum machine_mode mode = BLKmode;
9055 /* Altivec first, since it will be faster than a string move
9056 when it applies, and usually not significantly larger. */
9057 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9061 gen_func.mov = gen_movv4si;
9063 else if (TARGET_STRING
9064 && bytes > 24 /* move up to 32 bytes at a time */
9072 && ! fixed_regs[12])
9074 move_bytes = (bytes > 32) ? 32 : bytes;
9075 gen_func.movmemsi = gen_movmemsi_8reg;
9077 else if (TARGET_STRING
9078 && bytes > 16 /* move up to 24 bytes at a time */
9084 && ! fixed_regs[10])
9086 move_bytes = (bytes > 24) ? 24 : bytes;
9087 gen_func.movmemsi = gen_movmemsi_6reg;
9089 else if (TARGET_STRING
9090 && bytes > 8 /* move up to 16 bytes at a time */
9096 move_bytes = (bytes > 16) ? 16 : bytes;
9097 gen_func.movmemsi = gen_movmemsi_4reg;
9099 else if (bytes >= 8 && TARGET_POWERPC64
9100 /* 64-bit loads and stores require word-aligned
9102 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9106 gen_func.mov = gen_movdi;
9108 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9109 { /* move up to 8 bytes at a time */
9110 move_bytes = (bytes > 8) ? 8 : bytes;
9111 gen_func.movmemsi = gen_movmemsi_2reg;
9113 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9114 { /* move 4 bytes */
9117 gen_func.mov = gen_movsi;
9119 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
9120 { /* move 2 bytes */
9123 gen_func.mov = gen_movhi;
9125 else if (TARGET_STRING && bytes > 1)
9126 { /* move up to 4 bytes at a time */
9127 move_bytes = (bytes > 4) ? 4 : bytes;
9128 gen_func.movmemsi = gen_movmemsi_1reg;
9130 else /* move 1 byte at a time */
9134 gen_func.mov = gen_movqi;
9137 src = adjust_address (orig_src, mode, offset);
9138 dest = adjust_address (orig_dest, mode, offset);
9140 if (mode != BLKmode)
9142 rtx tmp_reg = gen_reg_rtx (mode);
9144 emit_insn ((*gen_func.mov) (tmp_reg, src));
9145 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9148 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9151 for (i = 0; i < num_reg; i++)
9152 emit_insn (stores[i]);
9156 if (mode == BLKmode)
9158 /* Move the address into scratch registers. The movmemsi
9159 patterns require zero offset. */
9160 if (!REG_P (XEXP (src, 0)))
9162 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9163 src = replace_equiv_address (src, src_reg);
9165 set_mem_size (src, GEN_INT (move_bytes));
9167 if (!REG_P (XEXP (dest, 0)))
9169 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9170 dest = replace_equiv_address (dest, dest_reg);
9172 set_mem_size (dest, GEN_INT (move_bytes));
9174 emit_insn ((*gen_func.movmemsi) (dest, src,
9175 GEN_INT (move_bytes & 31),
9184 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9185 known to be a PARALLEL. */
9187 save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9192 int count = XVECLEN (op, 0);
9198 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9199 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9202 for (i=1; i <= 18; i++)
9204 elt = XVECEXP (op, 0, index++);
9205 if (GET_CODE (elt) != SET
9206 || GET_CODE (SET_DEST (elt)) != MEM
9207 || ! memory_operand (SET_DEST (elt), DFmode)
9208 || GET_CODE (SET_SRC (elt)) != REG
9209 || GET_MODE (SET_SRC (elt)) != DFmode)
9213 for (i=1; i <= 12; i++)
9215 elt = XVECEXP (op, 0, index++);
9216 if (GET_CODE (elt) != SET
9217 || GET_CODE (SET_DEST (elt)) != MEM
9218 || GET_CODE (SET_SRC (elt)) != REG
9219 || GET_MODE (SET_SRC (elt)) != V4SImode)
9223 for (i=1; i <= 19; i++)
9225 elt = XVECEXP (op, 0, index++);
9226 if (GET_CODE (elt) != SET
9227 || GET_CODE (SET_DEST (elt)) != MEM
9228 || ! memory_operand (SET_DEST (elt), Pmode)
9229 || GET_CODE (SET_SRC (elt)) != REG
9230 || GET_MODE (SET_SRC (elt)) != Pmode)
9234 elt = XVECEXP (op, 0, index++);
9235 if (GET_CODE (elt) != SET
9236 || GET_CODE (SET_DEST (elt)) != MEM
9237 || ! memory_operand (SET_DEST (elt), Pmode)
9238 || GET_CODE (SET_SRC (elt)) != REG
9239 || REGNO (SET_SRC (elt)) != CR2_REGNO
9240 || GET_MODE (SET_SRC (elt)) != Pmode)
9243 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
9244 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9245 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9250 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9251 known to be a PARALLEL. */
9253 restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9258 int count = XVECLEN (op, 0);
9264 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
9265 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9266 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9267 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9270 elt = XVECEXP (op, 0, index++);
9271 if (GET_CODE (elt) != SET
9272 || GET_CODE (SET_SRC (elt)) != MEM
9273 || ! memory_operand (SET_SRC (elt), Pmode)
9274 || GET_CODE (SET_DEST (elt)) != REG
9275 || REGNO (SET_DEST (elt)) != CR2_REGNO
9276 || GET_MODE (SET_DEST (elt)) != Pmode)
9279 for (i=1; i <= 19; i++)
9281 elt = XVECEXP (op, 0, index++);
9282 if (GET_CODE (elt) != SET
9283 || GET_CODE (SET_SRC (elt)) != MEM
9284 || ! memory_operand (SET_SRC (elt), Pmode)
9285 || GET_CODE (SET_DEST (elt)) != REG
9286 || GET_MODE (SET_DEST (elt)) != Pmode)
9290 for (i=1; i <= 12; i++)
9292 elt = XVECEXP (op, 0, index++);
9293 if (GET_CODE (elt) != SET
9294 || GET_CODE (SET_SRC (elt)) != MEM
9295 || GET_CODE (SET_DEST (elt)) != REG
9296 || GET_MODE (SET_DEST (elt)) != V4SImode)
9300 for (i=1; i <= 18; i++)
9302 elt = XVECEXP (op, 0, index++);
9303 if (GET_CODE (elt) != SET
9304 || GET_CODE (SET_SRC (elt)) != MEM
9305 || ! memory_operand (SET_SRC (elt), DFmode)
9306 || GET_CODE (SET_DEST (elt)) != REG
9307 || GET_MODE (SET_DEST (elt)) != DFmode)
9311 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9312 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9313 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9314 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9315 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9321 /* Return 1 if OP is a load multiple operation. It is known to be a
9322 PARALLEL and the first section will be tested. */
9325 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9327 int count = XVECLEN (op, 0);
9328 unsigned int dest_regno;
9332 /* Perform a quick check so we don't blow up below. */
9334 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9335 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9336 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9339 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9340 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9342 for (i = 1; i < count; i++)
9344 rtx elt = XVECEXP (op, 0, i);
9346 if (GET_CODE (elt) != SET
9347 || GET_CODE (SET_DEST (elt)) != REG
9348 || GET_MODE (SET_DEST (elt)) != SImode
9349 || REGNO (SET_DEST (elt)) != dest_regno + i
9350 || GET_CODE (SET_SRC (elt)) != MEM
9351 || GET_MODE (SET_SRC (elt)) != SImode
9352 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
9353 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
9354 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
9355 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
9362 /* Similar, but tests for store multiple. Here, the second vector element
9363 is a CLOBBER. It will be tested later. */
9366 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9368 int count = XVECLEN (op, 0) - 1;
9369 unsigned int src_regno;
9373 /* Perform a quick check so we don't blow up below. */
9375 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9376 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9377 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9380 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9381 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9383 for (i = 1; i < count; i++)
9385 rtx elt = XVECEXP (op, 0, i + 1);
9387 if (GET_CODE (elt) != SET
9388 || GET_CODE (SET_SRC (elt)) != REG
9389 || GET_MODE (SET_SRC (elt)) != SImode
9390 || REGNO (SET_SRC (elt)) != src_regno + i
9391 || GET_CODE (SET_DEST (elt)) != MEM
9392 || GET_MODE (SET_DEST (elt)) != SImode
9393 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
9394 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
9395 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
9396 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
9403 /* Return a string to perform a load_multiple operation.
9404 operands[0] is the vector.
9405 operands[1] is the source address.
9406 operands[2] is the first destination register. */
9409 rs6000_output_load_multiple (rtx operands[3])
9411 /* We have to handle the case where the pseudo used to contain the address
9412 is assigned to one of the output registers. */
9414 int words = XVECLEN (operands[0], 0);
9417 if (XVECLEN (operands[0], 0) == 1)
9418 return "{l|lwz} %2,0(%1)";
9420 for (i = 0; i < words; i++)
9421 if (refers_to_regno_p (REGNO (operands[2]) + i,
9422 REGNO (operands[2]) + i + 1, operands[1], 0))
9426 xop[0] = GEN_INT (4 * (words-1));
9427 xop[1] = operands[1];
9428 xop[2] = operands[2];
9429 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9434 xop[0] = GEN_INT (4 * (words-1));
9435 xop[1] = operands[1];
9436 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9437 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9442 for (j = 0; j < words; j++)
9445 xop[0] = GEN_INT (j * 4);
9446 xop[1] = operands[1];
9447 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9448 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9450 xop[0] = GEN_INT (i * 4);
9451 xop[1] = operands[1];
9452 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9457 return "{lsi|lswi} %2,%1,%N0";
9460 /* Return 1 for a parallel vrsave operation. */
9463 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9465 int count = XVECLEN (op, 0);
9466 unsigned int dest_regno, src_regno;
9470 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9471 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9472 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
9475 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9476 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9478 if (dest_regno != VRSAVE_REGNO
9479 && src_regno != VRSAVE_REGNO)
9482 for (i = 1; i < count; i++)
9484 rtx elt = XVECEXP (op, 0, i);
9486 if (GET_CODE (elt) != CLOBBER
9487 && GET_CODE (elt) != SET)
9494 /* Return 1 for an PARALLEL suitable for mfcr. */
9497 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9499 int count = XVECLEN (op, 0);
9502 /* Perform a quick check so we don't blow up below. */
9504 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9505 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9506 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9509 for (i = 0; i < count; i++)
9511 rtx exp = XVECEXP (op, 0, i);
9516 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
9518 if (GET_CODE (src_reg) != REG
9519 || GET_MODE (src_reg) != CCmode
9520 || ! CR_REGNO_P (REGNO (src_reg)))
9523 if (GET_CODE (exp) != SET
9524 || GET_CODE (SET_DEST (exp)) != REG
9525 || GET_MODE (SET_DEST (exp)) != SImode
9526 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
9528 unspec = SET_SRC (exp);
9529 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
9531 if (GET_CODE (unspec) != UNSPEC
9532 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
9533 || XVECLEN (unspec, 0) != 2
9534 || XVECEXP (unspec, 0, 0) != src_reg
9535 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9536 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9542 /* Return 1 for an PARALLEL suitable for mtcrf. */
9545 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9547 int count = XVECLEN (op, 0);
9551 /* Perform a quick check so we don't blow up below. */
9553 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9554 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9555 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9557 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
9559 if (GET_CODE (src_reg) != REG
9560 || GET_MODE (src_reg) != SImode
9561 || ! INT_REGNO_P (REGNO (src_reg)))
9564 for (i = 0; i < count; i++)
9566 rtx exp = XVECEXP (op, 0, i);
9570 if (GET_CODE (exp) != SET
9571 || GET_CODE (SET_DEST (exp)) != REG
9572 || GET_MODE (SET_DEST (exp)) != CCmode
9573 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
9575 unspec = SET_SRC (exp);
9576 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
9578 if (GET_CODE (unspec) != UNSPEC
9579 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
9580 || XVECLEN (unspec, 0) != 2
9581 || XVECEXP (unspec, 0, 0) != src_reg
9582 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9583 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9589 /* Return 1 for an PARALLEL suitable for lmw. */
9592 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9594 int count = XVECLEN (op, 0);
9595 unsigned int dest_regno;
9597 unsigned int base_regno;
9598 HOST_WIDE_INT offset;
9601 /* Perform a quick check so we don't blow up below. */
9603 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9604 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9605 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9608 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9609 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9612 || count != 32 - (int) dest_regno)
9615 if (legitimate_indirect_address_p (src_addr, 0))
9618 base_regno = REGNO (src_addr);
9619 if (base_regno == 0)
9622 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
9624 offset = INTVAL (XEXP (src_addr, 1));
9625 base_regno = REGNO (XEXP (src_addr, 0));
9630 for (i = 0; i < count; i++)
9632 rtx elt = XVECEXP (op, 0, i);
9635 HOST_WIDE_INT newoffset;
9637 if (GET_CODE (elt) != SET
9638 || GET_CODE (SET_DEST (elt)) != REG
9639 || GET_MODE (SET_DEST (elt)) != SImode
9640 || REGNO (SET_DEST (elt)) != dest_regno + i
9641 || GET_CODE (SET_SRC (elt)) != MEM
9642 || GET_MODE (SET_SRC (elt)) != SImode)
9644 newaddr = XEXP (SET_SRC (elt), 0);
9645 if (legitimate_indirect_address_p (newaddr, 0))
9650 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9652 addr_reg = XEXP (newaddr, 0);
9653 newoffset = INTVAL (XEXP (newaddr, 1));
9657 if (REGNO (addr_reg) != base_regno
9658 || newoffset != offset + 4 * i)
9665 /* Return 1 for an PARALLEL suitable for stmw. */
9668 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9670 int count = XVECLEN (op, 0);
9671 unsigned int src_regno;
9673 unsigned int base_regno;
9674 HOST_WIDE_INT offset;
9677 /* Perform a quick check so we don't blow up below. */
9679 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9680 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9681 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9684 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9685 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9688 || count != 32 - (int) src_regno)
9691 if (legitimate_indirect_address_p (dest_addr, 0))
9694 base_regno = REGNO (dest_addr);
9695 if (base_regno == 0)
9698 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
9700 offset = INTVAL (XEXP (dest_addr, 1));
9701 base_regno = REGNO (XEXP (dest_addr, 0));
9706 for (i = 0; i < count; i++)
9708 rtx elt = XVECEXP (op, 0, i);
9711 HOST_WIDE_INT newoffset;
9713 if (GET_CODE (elt) != SET
9714 || GET_CODE (SET_SRC (elt)) != REG
9715 || GET_MODE (SET_SRC (elt)) != SImode
9716 || REGNO (SET_SRC (elt)) != src_regno + i
9717 || GET_CODE (SET_DEST (elt)) != MEM
9718 || GET_MODE (SET_DEST (elt)) != SImode)
9720 newaddr = XEXP (SET_DEST (elt), 0);
9721 if (legitimate_indirect_address_p (newaddr, 0))
9726 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9728 addr_reg = XEXP (newaddr, 0);
9729 newoffset = INTVAL (XEXP (newaddr, 1));
9733 if (REGNO (addr_reg) != base_regno
9734 || newoffset != offset + 4 * i)
9741 /* A validation routine: say whether CODE, a condition code, and MODE
9742 match. The other alternatives either don't make sense or should
9743 never be generated. */
9746 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9748 if ((GET_RTX_CLASS (code) != RTX_COMPARE
9749 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
9750 || GET_MODE_CLASS (mode) != MODE_CC)
9753 /* These don't make sense. */
9754 if ((code == GT || code == LT || code == GE || code == LE)
9755 && mode == CCUNSmode)
9758 if ((code == GTU || code == LTU || code == GEU || code == LEU)
9759 && mode != CCUNSmode)
9762 if (mode != CCFPmode
9763 && (code == ORDERED || code == UNORDERED
9764 || code == UNEQ || code == LTGT
9765 || code == UNGT || code == UNLT
9766 || code == UNGE || code == UNLE))
9769 /* These should never be generated except for
9770 flag_finite_math_only. */
9771 if (mode == CCFPmode
9772 && ! flag_finite_math_only
9773 && (code == LE || code == GE
9774 || code == UNEQ || code == LTGT
9775 || code == UNGT || code == UNLT))
9778 /* These are invalid; the information is not there. */
9779 if (mode == CCEQmode
9780 && code != EQ && code != NE)
9784 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9785 We only check the opcode against the mode of the CC value here. */
9788 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9790 enum rtx_code code = GET_CODE (op);
9791 enum machine_mode cc_mode;
9793 if (!COMPARISON_P (op))
9796 cc_mode = GET_MODE (XEXP (op, 0));
9797 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
9800 validate_condition_mode (code, cc_mode);
9805 /* Return 1 if OP is a comparison operation that is valid for a branch
9806 insn and which is true if the corresponding bit in the CC register
9810 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
9814 if (! branch_comparison_operator (op, mode))
9817 code = GET_CODE (op);
9818 return (code == EQ || code == LT || code == GT
9819 || code == LTU || code == GTU
9820 || code == UNORDERED);
9823 /* Return 1 if OP is a comparison operation that is valid for an scc
9824 insn: it must be a positive comparison. */
9827 scc_comparison_operator (rtx op, enum machine_mode mode)
9829 return branch_positive_comparison_operator (op, mode);
9833 trap_comparison_operator (rtx op, enum machine_mode mode)
9835 if (mode != VOIDmode && mode != GET_MODE (op))
9837 return COMPARISON_P (op);
9841 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9843 enum rtx_code code = GET_CODE (op);
9844 return (code == AND || code == IOR || code == XOR);
9848 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9850 enum rtx_code code = GET_CODE (op);
9851 return (code == IOR || code == XOR);
9855 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9857 enum rtx_code code = GET_CODE (op);
9858 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
9861 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9862 mask required to convert the result of a rotate insn into a shift
9863 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9866 includes_lshift_p (rtx shiftop, rtx andop)
9868 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9870 shift_mask <<= INTVAL (shiftop);
9872 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9875 /* Similar, but for right shift. */
9878 includes_rshift_p (rtx shiftop, rtx andop)
9880 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9882 shift_mask >>= INTVAL (shiftop);
9884 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9887 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9888 to perform a left shift. It must have exactly SHIFTOP least
9889 significant 0's, then one or more 1's, then zero or more 0's. */
9892 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9894 if (GET_CODE (andop) == CONST_INT)
9896 HOST_WIDE_INT c, lsb, shift_mask;
9899 if (c == 0 || c == ~0)
9903 shift_mask <<= INTVAL (shiftop);
9905 /* Find the least significant one bit. */
9908 /* It must coincide with the LSB of the shift mask. */
9909 if (-lsb != shift_mask)
9912 /* Invert to look for the next transition (if any). */
9915 /* Remove the low group of ones (originally low group of zeros). */
9918 /* Again find the lsb, and check we have all 1's above. */
9922 else if (GET_CODE (andop) == CONST_DOUBLE
9923 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9925 HOST_WIDE_INT low, high, lsb;
9926 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9928 low = CONST_DOUBLE_LOW (andop);
9929 if (HOST_BITS_PER_WIDE_INT < 64)
9930 high = CONST_DOUBLE_HIGH (andop);
9932 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9933 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9936 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9938 shift_mask_high = ~0;
9939 if (INTVAL (shiftop) > 32)
9940 shift_mask_high <<= INTVAL (shiftop) - 32;
9944 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9951 return high == -lsb;
9954 shift_mask_low = ~0;
9955 shift_mask_low <<= INTVAL (shiftop);
9959 if (-lsb != shift_mask_low)
9962 if (HOST_BITS_PER_WIDE_INT < 64)
9967 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9970 return high == -lsb;
9974 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9980 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9981 to perform a left shift. It must have SHIFTOP or more least
9982 significant 0's, with the remainder of the word 1's. */
9985 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9987 if (GET_CODE (andop) == CONST_INT)
9989 HOST_WIDE_INT c, lsb, shift_mask;
9992 shift_mask <<= INTVAL (shiftop);
9995 /* Find the least significant one bit. */
9998 /* It must be covered by the shift mask.
9999 This test also rejects c == 0. */
10000 if ((lsb & shift_mask) == 0)
10003 /* Check we have all 1's above the transition, and reject all 1's. */
10004 return c == -lsb && lsb != 1;
10006 else if (GET_CODE (andop) == CONST_DOUBLE
10007 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10009 HOST_WIDE_INT low, lsb, shift_mask_low;
10011 low = CONST_DOUBLE_LOW (andop);
10013 if (HOST_BITS_PER_WIDE_INT < 64)
10015 HOST_WIDE_INT high, shift_mask_high;
10017 high = CONST_DOUBLE_HIGH (andop);
10021 shift_mask_high = ~0;
10022 if (INTVAL (shiftop) > 32)
10023 shift_mask_high <<= INTVAL (shiftop) - 32;
10025 lsb = high & -high;
10027 if ((lsb & shift_mask_high) == 0)
10030 return high == -lsb;
10036 shift_mask_low = ~0;
10037 shift_mask_low <<= INTVAL (shiftop);
10041 if ((lsb & shift_mask_low) == 0)
10044 return low == -lsb && lsb != 1;
10050 /* Return 1 if operands will generate a valid arguments to rlwimi
10051 instruction for insert with right shift in 64-bit mode. The mask may
10052 not start on the first bit or stop on the last bit because wrap-around
10053 effects of instruction do not correspond to semantics of RTL insn. */
10056 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10058 if (INTVAL (startop) < 64
10059 && INTVAL (startop) > 32
10060 && (INTVAL (sizeop) + INTVAL (startop) < 64)
10061 && (INTVAL (sizeop) + INTVAL (startop) > 33)
10062 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
10063 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
10064 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10070 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10071 for lfq and stfq insns iff the registers are hard registers. */
10074 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10076 /* We might have been passed a SUBREG. */
10077 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10080 /* We might have been passed non floating point registers. */
10081 if (!FP_REGNO_P (REGNO (reg1))
10082 || !FP_REGNO_P (REGNO (reg2)))
10085 return (REGNO (reg1) == REGNO (reg2) - 1);
10088 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10089 addr1 and addr2 must be in consecutive memory locations
10090 (addr2 == addr1 + 8). */
10093 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10099 /* The mems cannot be volatile. */
10100 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10103 addr1 = XEXP (mem1, 0);
10104 addr2 = XEXP (mem2, 0);
10106 /* Extract an offset (if used) from the first addr. */
10107 if (GET_CODE (addr1) == PLUS)
10109 /* If not a REG, return zero. */
10110 if (GET_CODE (XEXP (addr1, 0)) != REG)
10114 reg1 = REGNO (XEXP (addr1, 0));
10115 /* The offset must be constant! */
10116 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10118 offset1 = INTVAL (XEXP (addr1, 1));
10121 else if (GET_CODE (addr1) != REG)
10125 reg1 = REGNO (addr1);
10126 /* This was a simple (mem (reg)) expression. Offset is 0. */
10130 /* Make sure the second address is a (mem (plus (reg) (const_int)))
10131 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
10132 register as addr1. */
10133 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
10135 if (GET_CODE (addr2) != PLUS)
10138 if (GET_CODE (XEXP (addr2, 0)) != REG
10139 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10142 if (reg1 != REGNO (XEXP (addr2, 0)))
10145 /* The offset for the second addr must be 8 more than the first addr. */
10146 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
10149 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10154 /* Return the register class of a scratch register needed to copy IN into
10155 or out of a register in CLASS in MODE. If it can be done directly,
10156 NO_REGS is returned. */
10159 secondary_reload_class (enum reg_class class,
10160 enum machine_mode mode ATTRIBUTE_UNUSED,
10165 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10167 && MACHOPIC_INDIRECT
10171 /* We cannot copy a symbolic operand directly into anything
10172 other than BASE_REGS for TARGET_ELF. So indicate that a
10173 register from BASE_REGS is needed as an intermediate
10176 On Darwin, pic addresses require a load from memory, which
10177 needs a base register. */
10178 if (class != BASE_REGS
10179 && (GET_CODE (in) == SYMBOL_REF
10180 || GET_CODE (in) == HIGH
10181 || GET_CODE (in) == LABEL_REF
10182 || GET_CODE (in) == CONST))
10186 if (GET_CODE (in) == REG)
10188 regno = REGNO (in);
10189 if (regno >= FIRST_PSEUDO_REGISTER)
10191 regno = true_regnum (in);
10192 if (regno >= FIRST_PSEUDO_REGISTER)
10196 else if (GET_CODE (in) == SUBREG)
10198 regno = true_regnum (in);
10199 if (regno >= FIRST_PSEUDO_REGISTER)
10205 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10207 if (class == GENERAL_REGS || class == BASE_REGS
10208 || (regno >= 0 && INT_REGNO_P (regno)))
10211 /* Constants, memory, and FP registers can go into FP registers. */
10212 if ((regno == -1 || FP_REGNO_P (regno))
10213 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10216 /* Memory, and AltiVec registers can go into AltiVec registers. */
10217 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10218 && class == ALTIVEC_REGS)
10221 /* We can copy among the CR registers. */
10222 if ((class == CR_REGS || class == CR0_REGS)
10223 && regno >= 0 && CR_REGNO_P (regno))
10226 /* Otherwise, we need GENERAL_REGS. */
10227 return GENERAL_REGS;
10230 /* Given a comparison operation, return the bit number in CCR to test. We
10231 know this is a valid comparison.
10233 SCC_P is 1 if this is for an scc. That means that %D will have been
10234 used instead of %C, so the bits will be in different places.
10236 Return -1 if OP isn't a valid comparison for some reason. */
10239 ccr_bit (rtx op, int scc_p)
10241 enum rtx_code code = GET_CODE (op);
10242 enum machine_mode cc_mode;
10247 if (!COMPARISON_P (op))
10250 reg = XEXP (op, 0);
10252 if (GET_CODE (reg) != REG
10253 || ! CR_REGNO_P (REGNO (reg)))
10256 cc_mode = GET_MODE (reg);
10257 cc_regnum = REGNO (reg);
10258 base_bit = 4 * (cc_regnum - CR0_REGNO);
10260 validate_condition_mode (code, cc_mode);
10262 /* When generating a sCOND operation, only positive conditions are
10264 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
10265 && code != GTU && code != LTU)
10271 return scc_p ? base_bit + 3 : base_bit + 2;
10273 return base_bit + 2;
10274 case GT: case GTU: case UNLE:
10275 return base_bit + 1;
10276 case LT: case LTU: case UNGE:
10278 case ORDERED: case UNORDERED:
10279 return base_bit + 3;
10282 /* If scc, we will have done a cror to put the bit in the
10283 unordered position. So test that bit. For integer, this is ! LT
10284 unless this is an scc insn. */
10285 return scc_p ? base_bit + 3 : base_bit;
10288 return scc_p ? base_bit + 3 : base_bit + 1;
10295 /* Return the GOT register. */
10298 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10300 /* The second flow pass currently (June 1999) can't update
10301 regs_ever_live without disturbing other parts of the compiler, so
10302 update it here to make the prolog/epilogue code happy. */
10303 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10304 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10306 current_function_uses_pic_offset_table = 1;
10308 return pic_offset_table_rtx;
10311 /* Function to init struct machine_function.
10312 This will be called, via a pointer variable,
10313 from push_function_context. */
10315 static struct machine_function *
10316 rs6000_init_machine_status (void)
10318 return ggc_alloc_cleared (sizeof (machine_function));
10321 /* These macros test for integers and extract the low-order bits. */
10323 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10324 && GET_MODE (X) == VOIDmode)
10326 #define INT_LOWPART(X) \
10327 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10330 extract_MB (rtx op)
10333 unsigned long val = INT_LOWPART (op);
10335 /* If the high bit is zero, the value is the first 1 bit we find
10337 if ((val & 0x80000000) == 0)
10339 if ((val & 0xffffffff) == 0)
10343 while (((val <<= 1) & 0x80000000) == 0)
10348 /* If the high bit is set and the low bit is not, or the mask is all
10349 1's, the value is zero. */
10350 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10353 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10356 while (((val >>= 1) & 1) != 0)
10363 extract_ME (rtx op)
10366 unsigned long val = INT_LOWPART (op);
10368 /* If the low bit is zero, the value is the first 1 bit we find from
10370 if ((val & 1) == 0)
10372 if ((val & 0xffffffff) == 0)
10376 while (((val >>= 1) & 1) == 0)
10382 /* If the low bit is set and the high bit is not, or the mask is all
10383 1's, the value is 31. */
10384 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10387 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10390 while (((val <<= 1) & 0x80000000) != 0)
10396 /* Locate some local-dynamic symbol still in use by this function
10397 so that we can print its name in some tls_ld pattern. */
10399 static const char *
10400 rs6000_get_some_local_dynamic_name (void)
10404 if (cfun->machine->some_ld_name)
10405 return cfun->machine->some_ld_name;
10407 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10409 && for_each_rtx (&PATTERN (insn),
10410 rs6000_get_some_local_dynamic_name_1, 0))
10411 return cfun->machine->some_ld_name;
10416 /* Helper function for rs6000_get_some_local_dynamic_name. */
10419 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10423 if (GET_CODE (x) == SYMBOL_REF)
10425 const char *str = XSTR (x, 0);
10426 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10428 cfun->machine->some_ld_name = str;
10436 /* Write out a function code label. */
10439 rs6000_output_function_entry (FILE *file, const char *fname)
10441 if (fname[0] != '.')
10443 switch (DEFAULT_ABI)
10452 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10461 RS6000_OUTPUT_BASENAME (file, fname);
10463 assemble_name (file, fname);
10466 /* Print an operand. Recognize special options, documented below. */
10469 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10470 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10472 #define SMALL_DATA_RELOC "sda21"
10473 #define SMALL_DATA_REG 0
10477 print_operand (FILE *file, rtx x, int code)
10481 unsigned HOST_WIDE_INT uval;
10486 /* Write out an instruction after the call which may be replaced
10487 with glue code by the loader. This depends on the AIX version. */
10488 asm_fprintf (file, RS6000_CALL_GLUE);
10491 /* %a is output_address. */
10494 /* If X is a constant integer whose low-order 5 bits are zero,
10495 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10496 in the AIX assembler where "sri" with a zero shift count
10497 writes a trash instruction. */
10498 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10505 /* If constant, low-order 16 bits of constant, unsigned.
10506 Otherwise, write normally. */
10508 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10510 print_operand (file, x, 0);
10514 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10515 for 64-bit mask direction. */
10516 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
10519 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10523 /* X is a CR register. Print the number of the GT bit of the CR. */
10524 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10525 output_operand_lossage ("invalid %%E value");
10527 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10531 /* Like 'J' but get to the EQ bit. */
10532 if (GET_CODE (x) != REG)
10535 /* Bit 1 is EQ bit. */
10536 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10538 /* If we want bit 31, write a shift count of zero, not 32. */
10539 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10543 /* X is a CR register. Print the number of the EQ bit of the CR */
10544 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10545 output_operand_lossage ("invalid %%E value");
10547 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10551 /* X is a CR register. Print the shift count needed to move it
10552 to the high-order four bits. */
10553 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10554 output_operand_lossage ("invalid %%f value");
10556 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10560 /* Similar, but print the count for the rotate in the opposite
10562 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10563 output_operand_lossage ("invalid %%F value");
10565 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10569 /* X is a constant integer. If it is negative, print "m",
10570 otherwise print "z". This is to make an aze or ame insn. */
10571 if (GET_CODE (x) != CONST_INT)
10572 output_operand_lossage ("invalid %%G value");
10573 else if (INTVAL (x) >= 0)
10580 /* If constant, output low-order five bits. Otherwise, write
10583 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10585 print_operand (file, x, 0);
10589 /* If constant, output low-order six bits. Otherwise, write
10592 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10594 print_operand (file, x, 0);
10598 /* Print `i' if this is a constant, else nothing. */
10604 /* Write the bit number in CCR for jump. */
10605 i = ccr_bit (x, 0);
10607 output_operand_lossage ("invalid %%j code");
10609 fprintf (file, "%d", i);
10613 /* Similar, but add one for shift count in rlinm for scc and pass
10614 scc flag to `ccr_bit'. */
10615 i = ccr_bit (x, 1);
10617 output_operand_lossage ("invalid %%J code");
10619 /* If we want bit 31, write a shift count of zero, not 32. */
10620 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10624 /* X must be a constant. Write the 1's complement of the
10627 output_operand_lossage ("invalid %%k value");
10629 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10633 /* X must be a symbolic constant on ELF. Write an
10634 expression suitable for an 'addi' that adds in the low 16
10635 bits of the MEM. */
10636 if (GET_CODE (x) != CONST)
10638 print_operand_address (file, x);
10639 fputs ("@l", file);
10643 if (GET_CODE (XEXP (x, 0)) != PLUS
10644 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10645 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10646 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10647 output_operand_lossage ("invalid %%K value");
10648 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10649 fputs ("@l", file);
10650 /* For GNU as, there must be a non-alphanumeric character
10651 between 'l' and the number. The '-' is added by
10652 print_operand() already. */
10653 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10655 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10659 /* %l is output_asm_label. */
10662 /* Write second word of DImode or DFmode reference. Works on register
10663 or non-indexed memory only. */
10664 if (GET_CODE (x) == REG)
10665 fputs (reg_names[REGNO (x) + 1], file);
10666 else if (GET_CODE (x) == MEM)
10668 /* Handle possible auto-increment. Since it is pre-increment and
10669 we have already done it, we can just use an offset of word. */
10670 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10671 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10672 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10675 output_address (XEXP (adjust_address_nv (x, SImode,
10679 if (small_data_operand (x, GET_MODE (x)))
10680 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10681 reg_names[SMALL_DATA_REG]);
10686 /* MB value for a mask operand. */
10687 if (! mask_operand (x, SImode))
10688 output_operand_lossage ("invalid %%m value");
10690 fprintf (file, "%d", extract_MB (x));
10694 /* ME value for a mask operand. */
10695 if (! mask_operand (x, SImode))
10696 output_operand_lossage ("invalid %%M value");
10698 fprintf (file, "%d", extract_ME (x));
10701 /* %n outputs the negative of its operand. */
10704 /* Write the number of elements in the vector times 4. */
10705 if (GET_CODE (x) != PARALLEL)
10706 output_operand_lossage ("invalid %%N value");
10708 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10712 /* Similar, but subtract 1 first. */
10713 if (GET_CODE (x) != PARALLEL)
10714 output_operand_lossage ("invalid %%O value");
10716 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10720 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10722 || INT_LOWPART (x) < 0
10723 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10724 output_operand_lossage ("invalid %%p value");
10726 fprintf (file, "%d", i);
10730 /* The operand must be an indirect memory reference. The result
10731 is the register name. */
10732 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10733 || REGNO (XEXP (x, 0)) >= 32)
10734 output_operand_lossage ("invalid %%P value");
10736 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10740 /* This outputs the logical code corresponding to a boolean
10741 expression. The expression may have one or both operands
10742 negated (if one, only the first one). For condition register
10743 logical operations, it will also treat the negated
10744 CR codes as NOTs, but not handle NOTs of them. */
10746 const char *const *t = 0;
10748 enum rtx_code code = GET_CODE (x);
10749 static const char * const tbl[3][3] = {
10750 { "and", "andc", "nor" },
10751 { "or", "orc", "nand" },
10752 { "xor", "eqv", "xor" } };
10756 else if (code == IOR)
10758 else if (code == XOR)
10761 output_operand_lossage ("invalid %%q value");
10763 if (GET_CODE (XEXP (x, 0)) != NOT)
10767 if (GET_CODE (XEXP (x, 1)) == NOT)
10785 /* X is a CR register. Print the mask for `mtcrf'. */
10786 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10787 output_operand_lossage ("invalid %%R value");
10789 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10793 /* Low 5 bits of 32 - value */
10795 output_operand_lossage ("invalid %%s value");
10797 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10801 /* PowerPC64 mask position. All 0's is excluded.
10802 CONST_INT 32-bit mask is considered sign-extended so any
10803 transition must occur within the CONST_INT, not on the boundary. */
10804 if (! mask64_operand (x, DImode))
10805 output_operand_lossage ("invalid %%S value");
10807 uval = INT_LOWPART (x);
10809 if (uval & 1) /* Clear Left */
10811 #if HOST_BITS_PER_WIDE_INT > 64
10812 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10816 else /* Clear Right */
10819 #if HOST_BITS_PER_WIDE_INT > 64
10820 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10828 fprintf (file, "%d", i);
10832 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10833 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
10836 /* Bit 3 is OV bit. */
10837 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10839 /* If we want bit 31, write a shift count of zero, not 32. */
10840 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10844 /* Print the symbolic name of a branch target register. */
10845 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10846 && REGNO (x) != COUNT_REGISTER_REGNUM))
10847 output_operand_lossage ("invalid %%T value");
10848 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10849 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10851 fputs ("ctr", file);
10855 /* High-order 16 bits of constant for use in unsigned operand. */
10857 output_operand_lossage ("invalid %%u value");
10859 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10860 (INT_LOWPART (x) >> 16) & 0xffff);
10864 /* High-order 16 bits of constant for use in signed operand. */
10866 output_operand_lossage ("invalid %%v value");
10868 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10869 (INT_LOWPART (x) >> 16) & 0xffff);
10873 /* Print `u' if this has an auto-increment or auto-decrement. */
10874 if (GET_CODE (x) == MEM
10875 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10876 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10881 /* Print the trap code for this operand. */
10882 switch (GET_CODE (x))
10885 fputs ("eq", file); /* 4 */
10888 fputs ("ne", file); /* 24 */
10891 fputs ("lt", file); /* 16 */
10894 fputs ("le", file); /* 20 */
10897 fputs ("gt", file); /* 8 */
10900 fputs ("ge", file); /* 12 */
10903 fputs ("llt", file); /* 2 */
10906 fputs ("lle", file); /* 6 */
10909 fputs ("lgt", file); /* 1 */
10912 fputs ("lge", file); /* 5 */
10920 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10923 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10924 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10926 print_operand (file, x, 0);
10930 /* MB value for a PowerPC64 rldic operand. */
10931 val = (GET_CODE (x) == CONST_INT
10932 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10937 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10938 if ((val <<= 1) < 0)
10941 #if HOST_BITS_PER_WIDE_INT == 32
10942 if (GET_CODE (x) == CONST_INT && i >= 0)
10943 i += 32; /* zero-extend high-part was all 0's */
10944 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10946 val = CONST_DOUBLE_LOW (x);
10953 for ( ; i < 64; i++)
10954 if ((val <<= 1) < 0)
10959 fprintf (file, "%d", i + 1);
10963 if (GET_CODE (x) == MEM
10964 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10969 /* Like 'L', for third word of TImode */
10970 if (GET_CODE (x) == REG)
10971 fputs (reg_names[REGNO (x) + 2], file);
10972 else if (GET_CODE (x) == MEM)
10974 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10975 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10976 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10978 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10979 if (small_data_operand (x, GET_MODE (x)))
10980 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10981 reg_names[SMALL_DATA_REG]);
10986 /* X is a SYMBOL_REF. Write out the name preceded by a
10987 period and without any trailing data in brackets. Used for function
10988 names. If we are configured for System V (or the embedded ABI) on
10989 the PowerPC, do not emit the period, since those systems do not use
10990 TOCs and the like. */
10991 if (GET_CODE (x) != SYMBOL_REF)
10994 /* Mark the decl as referenced so that cgraph will output the
10996 if (SYMBOL_REF_DECL (x))
10997 mark_decl_referenced (SYMBOL_REF_DECL (x));
10999 /* For macho, check to see if we need a stub. */
11002 const char *name = XSTR (x, 0);
11004 if (MACHOPIC_INDIRECT
11005 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11006 name = machopic_indirection_name (x, /*stub_p=*/true);
11008 assemble_name (file, name);
11010 else if (!DOT_SYMBOLS)
11011 assemble_name (file, XSTR (x, 0));
11013 rs6000_output_function_entry (file, XSTR (x, 0));
11017 /* Like 'L', for last word of TImode. */
11018 if (GET_CODE (x) == REG)
11019 fputs (reg_names[REGNO (x) + 3], file);
11020 else if (GET_CODE (x) == MEM)
11022 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11023 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11024 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11026 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11027 if (small_data_operand (x, GET_MODE (x)))
11028 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11029 reg_names[SMALL_DATA_REG]);
11033 /* Print AltiVec or SPE memory operand. */
11038 if (GET_CODE (x) != MEM)
11045 /* Handle [reg]. */
11046 if (GET_CODE (tmp) == REG)
11048 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11051 /* Handle [reg+UIMM]. */
11052 else if (GET_CODE (tmp) == PLUS &&
11053 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11057 if (GET_CODE (XEXP (tmp, 0)) != REG)
11060 x = INTVAL (XEXP (tmp, 1));
11061 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11065 /* Fall through. Must be [reg+reg]. */
11068 && GET_CODE (tmp) == AND
11069 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11070 && INTVAL (XEXP (tmp, 1)) == -16)
11071 tmp = XEXP (tmp, 0);
11072 if (GET_CODE (tmp) == REG)
11073 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11074 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
11076 if (REGNO (XEXP (tmp, 0)) == 0)
11077 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11078 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11080 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11081 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11089 if (GET_CODE (x) == REG)
11090 fprintf (file, "%s", reg_names[REGNO (x)]);
11091 else if (GET_CODE (x) == MEM)
11093 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11094 know the width from the mode. */
11095 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11096 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11097 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11098 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11099 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11100 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11102 output_address (XEXP (x, 0));
11105 output_addr_const (file, x);
11109 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11113 output_operand_lossage ("invalid %%xn code");
11117 /* Print the address of an operand. */
11120 print_operand_address (FILE *file, rtx x)
11122 if (GET_CODE (x) == REG)
11123 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11124 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11125 || GET_CODE (x) == LABEL_REF)
11127 output_addr_const (file, x);
11128 if (small_data_operand (x, GET_MODE (x)))
11129 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11130 reg_names[SMALL_DATA_REG]);
11131 else if (TARGET_TOC)
11134 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11136 if (REGNO (XEXP (x, 0)) == 0)
11137 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11138 reg_names[ REGNO (XEXP (x, 0)) ]);
11140 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11141 reg_names[ REGNO (XEXP (x, 1)) ]);
11143 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11144 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11145 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11147 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11148 && CONSTANT_P (XEXP (x, 1)))
11150 output_addr_const (file, XEXP (x, 1));
11151 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11155 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11156 && CONSTANT_P (XEXP (x, 1)))
11158 fprintf (file, "lo16(");
11159 output_addr_const (file, XEXP (x, 1));
11160 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11163 else if (legitimate_constant_pool_address_p (x))
11165 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11167 rtx contains_minus = XEXP (x, 1);
11171 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11172 turn it into (sym) for output_addr_const. */
11173 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11174 contains_minus = XEXP (contains_minus, 0);
11176 minus = XEXP (contains_minus, 0);
11177 symref = XEXP (minus, 0);
11178 XEXP (contains_minus, 0) = symref;
11183 name = XSTR (symref, 0);
11184 newname = alloca (strlen (name) + sizeof ("@toc"));
11185 strcpy (newname, name);
11186 strcat (newname, "@toc");
11187 XSTR (symref, 0) = newname;
11189 output_addr_const (file, XEXP (x, 1));
11191 XSTR (symref, 0) = name;
11192 XEXP (contains_minus, 0) = minus;
11195 output_addr_const (file, XEXP (x, 1));
11197 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11203 /* Target hook for assembling integer objects. The PowerPC version has
11204 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11205 is defined. It also needs to handle DI-mode objects on 64-bit
11209 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11211 #ifdef RELOCATABLE_NEEDS_FIXUP
11212 /* Special handling for SI values. */
11213 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11215 extern int in_toc_section (void);
11216 static int recurse = 0;
11218 /* For -mrelocatable, we mark all addresses that need to be fixed up
11219 in the .fixup section. */
11220 if (TARGET_RELOCATABLE
11221 && !in_toc_section ()
11222 && !in_text_section ()
11223 && !in_unlikely_text_section ()
11225 && GET_CODE (x) != CONST_INT
11226 && GET_CODE (x) != CONST_DOUBLE
11232 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11234 ASM_OUTPUT_LABEL (asm_out_file, buf);
11235 fprintf (asm_out_file, "\t.long\t(");
11236 output_addr_const (asm_out_file, x);
11237 fprintf (asm_out_file, ")@fixup\n");
11238 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11239 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11240 fprintf (asm_out_file, "\t.long\t");
11241 assemble_name (asm_out_file, buf);
11242 fprintf (asm_out_file, "\n\t.previous\n");
11246 /* Remove initial .'s to turn a -mcall-aixdesc function
11247 address into the address of the descriptor, not the function
11249 else if (GET_CODE (x) == SYMBOL_REF
11250 && XSTR (x, 0)[0] == '.'
11251 && DEFAULT_ABI == ABI_AIX)
11253 const char *name = XSTR (x, 0);
11254 while (*name == '.')
11257 fprintf (asm_out_file, "\t.long\t%s\n", name);
11261 #endif /* RELOCATABLE_NEEDS_FIXUP */
11262 return default_assemble_integer (x, size, aligned_p);
11265 #ifdef HAVE_GAS_HIDDEN
11266 /* Emit an assembler directive to set symbol visibility for DECL to
11267 VISIBILITY_TYPE. */
11270 rs6000_assemble_visibility (tree decl, int vis)
11272 /* Functions need to have their entry point symbol visibility set as
11273 well as their descriptor symbol visibility. */
11274 if (DEFAULT_ABI == ABI_AIX
11276 && TREE_CODE (decl) == FUNCTION_DECL)
11278 static const char * const visibility_types[] = {
11279 NULL, "internal", "hidden", "protected"
11282 const char *name, *type;
11284 name = ((* targetm.strip_name_encoding)
11285 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11286 type = visibility_types[vis];
11288 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11289 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11292 default_assemble_visibility (decl, vis);
11297 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11299 /* Reversal of FP compares takes care -- an ordered compare
11300 becomes an unordered compare and vice versa. */
11301 if (mode == CCFPmode
11302 && (!flag_finite_math_only
11303 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11304 || code == UNEQ || code == LTGT))
11305 return reverse_condition_maybe_unordered (code);
11307 return reverse_condition (code);
11310 /* Generate a compare for CODE. Return a brand-new rtx that
11311 represents the result of the compare. */
11314 rs6000_generate_compare (enum rtx_code code)
11316 enum machine_mode comp_mode;
11317 rtx compare_result;
11319 if (rs6000_compare_fp_p)
11320 comp_mode = CCFPmode;
11321 else if (code == GTU || code == LTU
11322 || code == GEU || code == LEU)
11323 comp_mode = CCUNSmode;
11324 else if ((code == EQ || code == NE)
11325 && GET_CODE (rs6000_compare_op0) == SUBREG
11326 && GET_CODE (rs6000_compare_op1) == SUBREG
11327 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11328 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11329 /* These are unsigned values, perhaps there will be a later
11330 ordering compare that can be shared with this one.
11331 Unfortunately we cannot detect the signedness of the operands
11332 for non-subregs. */
11333 comp_mode = CCUNSmode;
11335 comp_mode = CCmode;
11337 /* First, the compare. */
11338 compare_result = gen_reg_rtx (comp_mode);
11340 /* SPE FP compare instructions on the GPRs. Yuck! */
11341 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11342 && rs6000_compare_fp_p)
11344 rtx cmp, or1, or2, or_result, compare_result2;
11345 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11347 if (op_mode == VOIDmode)
11348 op_mode = GET_MODE (rs6000_compare_op1);
11350 /* Note: The E500 comparison instructions set the GT bit (x +
11351 1), on success. This explains the mess. */
11355 case EQ: case UNEQ: case NE: case LTGT:
11356 if (op_mode == SFmode)
11357 cmp = flag_unsafe_math_optimizations
11358 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11359 rs6000_compare_op1)
11360 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11361 rs6000_compare_op1);
11362 else if (op_mode == DFmode)
11363 cmp = flag_unsafe_math_optimizations
11364 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11365 rs6000_compare_op1)
11366 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11367 rs6000_compare_op1);
11370 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11371 if (op_mode == SFmode)
11372 cmp = flag_unsafe_math_optimizations
11373 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11374 rs6000_compare_op1)
11375 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11376 rs6000_compare_op1);
11377 else if (op_mode == DFmode)
11378 cmp = flag_unsafe_math_optimizations
11379 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11380 rs6000_compare_op1)
11381 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11382 rs6000_compare_op1);
11385 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11386 if (op_mode == SFmode)
11387 cmp = flag_unsafe_math_optimizations
11388 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11389 rs6000_compare_op1)
11390 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11391 rs6000_compare_op1);
11392 else if (op_mode == DFmode)
11393 cmp = flag_unsafe_math_optimizations
11394 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11395 rs6000_compare_op1)
11396 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11397 rs6000_compare_op1);
11404 /* Synthesize LE and GE from LT/GT || EQ. */
11405 if (code == LE || code == GE || code == LEU || code == GEU)
11411 case LE: code = LT; break;
11412 case GE: code = GT; break;
11413 case LEU: code = LT; break;
11414 case GEU: code = GT; break;
11418 or1 = gen_reg_rtx (SImode);
11419 or2 = gen_reg_rtx (SImode);
11420 or_result = gen_reg_rtx (CCEQmode);
11421 compare_result2 = gen_reg_rtx (CCFPmode);
11424 if (op_mode == SFmode)
11425 cmp = flag_unsafe_math_optimizations
11426 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11427 rs6000_compare_op1)
11428 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11429 rs6000_compare_op1);
11430 else if (op_mode == DFmode)
11431 cmp = flag_unsafe_math_optimizations
11432 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11433 rs6000_compare_op1)
11434 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11435 rs6000_compare_op1);
11439 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
11440 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
11442 /* OR them together. */
11443 cmp = gen_rtx_SET (VOIDmode, or_result,
11444 gen_rtx_COMPARE (CCEQmode,
11445 gen_rtx_IOR (SImode, or1, or2),
11447 compare_result = or_result;
11452 if (code == NE || code == LTGT)
11461 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11462 gen_rtx_COMPARE (comp_mode,
11463 rs6000_compare_op0,
11464 rs6000_compare_op1)));
11466 /* Some kinds of FP comparisons need an OR operation;
11467 under flag_unsafe_math_optimizations we don't bother. */
11468 if (rs6000_compare_fp_p
11469 && ! flag_unsafe_math_optimizations
11470 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11471 && (code == LE || code == GE
11472 || code == UNEQ || code == LTGT
11473 || code == UNGT || code == UNLT))
11475 enum rtx_code or1, or2;
11476 rtx or1_rtx, or2_rtx, compare2_rtx;
11477 rtx or_result = gen_reg_rtx (CCEQmode);
11481 case LE: or1 = LT; or2 = EQ; break;
11482 case GE: or1 = GT; or2 = EQ; break;
11483 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11484 case LTGT: or1 = LT; or2 = GT; break;
11485 case UNGT: or1 = UNORDERED; or2 = GT; break;
11486 case UNLT: or1 = UNORDERED; or2 = LT; break;
11489 validate_condition_mode (or1, comp_mode);
11490 validate_condition_mode (or2, comp_mode);
11491 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11492 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11493 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11494 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11496 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11498 compare_result = or_result;
11502 validate_condition_mode (code, GET_MODE (compare_result));
11504 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11508 /* Emit the RTL for an sCOND pattern. */
11511 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11514 enum machine_mode op_mode;
11515 enum rtx_code cond_code;
11517 condition_rtx = rs6000_generate_compare (code);
11518 cond_code = GET_CODE (condition_rtx);
11520 if (TARGET_E500 && rs6000_compare_fp_p
11521 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11525 PUT_MODE (condition_rtx, SImode);
11526 t = XEXP (condition_rtx, 0);
11528 if (cond_code != NE && cond_code != EQ)
11531 if (cond_code == NE)
11532 emit_insn (gen_e500_flip_eq_bit (t, t));
11534 emit_insn (gen_move_from_CR_eq_bit (result, t));
11538 if (cond_code == NE
11539 || cond_code == GE || cond_code == LE
11540 || cond_code == GEU || cond_code == LEU
11541 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11543 rtx not_result = gen_reg_rtx (CCEQmode);
11544 rtx not_op, rev_cond_rtx;
11545 enum machine_mode cc_mode;
11547 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11549 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11550 SImode, XEXP (condition_rtx, 0), const0_rtx);
11551 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11552 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11553 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11556 op_mode = GET_MODE (rs6000_compare_op0);
11557 if (op_mode == VOIDmode)
11558 op_mode = GET_MODE (rs6000_compare_op1);
11560 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11562 PUT_MODE (condition_rtx, DImode);
11563 convert_move (result, condition_rtx, 0);
11567 PUT_MODE (condition_rtx, SImode);
11568 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11572 /* Emit a branch of kind CODE to location LOC. */
11575 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11577 rtx condition_rtx, loc_ref;
11579 condition_rtx = rs6000_generate_compare (code);
11580 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11581 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11582 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11583 loc_ref, pc_rtx)));
11586 /* Return the string to output a conditional branch to LABEL, which is
11587 the operand number of the label, or -1 if the branch is really a
11588 conditional return.
11590 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11591 condition code register and its mode specifies what kind of
11592 comparison we made.
11594 REVERSED is nonzero if we should reverse the sense of the comparison.
11596 INSN is the insn. */
11599 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11601 static char string[64];
11602 enum rtx_code code = GET_CODE (op);
11603 rtx cc_reg = XEXP (op, 0);
11604 enum machine_mode mode = GET_MODE (cc_reg);
11605 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11606 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11607 int really_reversed = reversed ^ need_longbranch;
11613 validate_condition_mode (code, mode);
11615 /* Work out which way this really branches. We could use
11616 reverse_condition_maybe_unordered here always but this
11617 makes the resulting assembler clearer. */
11618 if (really_reversed)
11620 /* Reversal of FP compares takes care -- an ordered compare
11621 becomes an unordered compare and vice versa. */
11622 if (mode == CCFPmode)
11623 code = reverse_condition_maybe_unordered (code);
11625 code = reverse_condition (code);
11628 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11630 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11633 /* Opposite of GT. */
11635 else if (code == NE)
11643 /* Not all of these are actually distinct opcodes, but
11644 we distinguish them for clarity of the resulting assembler. */
11645 case NE: case LTGT:
11646 ccode = "ne"; break;
11647 case EQ: case UNEQ:
11648 ccode = "eq"; break;
11650 ccode = "ge"; break;
11651 case GT: case GTU: case UNGT:
11652 ccode = "gt"; break;
11654 ccode = "le"; break;
11655 case LT: case LTU: case UNLT:
11656 ccode = "lt"; break;
11657 case UNORDERED: ccode = "un"; break;
11658 case ORDERED: ccode = "nu"; break;
11659 case UNGE: ccode = "nl"; break;
11660 case UNLE: ccode = "ng"; break;
11665 /* Maybe we have a guess as to how likely the branch is.
11666 The old mnemonics don't have a way to specify this information. */
11668 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11669 if (note != NULL_RTX)
11671 /* PROB is the difference from 50%. */
11672 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11674 /* Only hint for highly probable/improbable branches on newer
11675 cpus as static prediction overrides processor dynamic
11676 prediction. For older cpus we may as well always hint, but
11677 assume not taken for branches that are very close to 50% as a
11678 mispredicted taken branch is more expensive than a
11679 mispredicted not-taken branch. */
11680 if (rs6000_always_hint
11681 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11683 if (abs (prob) > REG_BR_PROB_BASE / 20
11684 && ((prob > 0) ^ need_longbranch))
11692 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11694 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11696 /* We need to escape any '%' characters in the reg_names string.
11697 Assume they'd only be the first character.... */
11698 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11700 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11704 /* If the branch distance was too far, we may have to use an
11705 unconditional branch to go the distance. */
11706 if (need_longbranch)
11707 s += sprintf (s, ",$+8\n\tb %s", label);
11709 s += sprintf (s, ",%s", label);
11715 /* Return the string to flip the EQ bit on a CR. */
11717 output_e500_flip_eq_bit (rtx dst, rtx src)
11719 static char string[64];
11722 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
11723 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
11727 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
11728 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
11730 sprintf (string, "crnot %d,%d", a, b);
11734 /* Return insn index for the vector compare instruction for given CODE,
11735 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11739 get_vec_cmp_insn (enum rtx_code code,
11740 enum machine_mode dest_mode,
11741 enum machine_mode op_mode)
11743 if (!TARGET_ALTIVEC)
11744 return INSN_NOT_AVAILABLE;
11749 if (dest_mode == V16QImode && op_mode == V16QImode)
11750 return UNSPEC_VCMPEQUB;
11751 if (dest_mode == V8HImode && op_mode == V8HImode)
11752 return UNSPEC_VCMPEQUH;
11753 if (dest_mode == V4SImode && op_mode == V4SImode)
11754 return UNSPEC_VCMPEQUW;
11755 if (dest_mode == V4SImode && op_mode == V4SFmode)
11756 return UNSPEC_VCMPEQFP;
11759 if (dest_mode == V4SImode && op_mode == V4SFmode)
11760 return UNSPEC_VCMPGEFP;
11762 if (dest_mode == V16QImode && op_mode == V16QImode)
11763 return UNSPEC_VCMPGTSB;
11764 if (dest_mode == V8HImode && op_mode == V8HImode)
11765 return UNSPEC_VCMPGTSH;
11766 if (dest_mode == V4SImode && op_mode == V4SImode)
11767 return UNSPEC_VCMPGTSW;
11768 if (dest_mode == V4SImode && op_mode == V4SFmode)
11769 return UNSPEC_VCMPGTFP;
11772 if (dest_mode == V16QImode && op_mode == V16QImode)
11773 return UNSPEC_VCMPGTUB;
11774 if (dest_mode == V8HImode && op_mode == V8HImode)
11775 return UNSPEC_VCMPGTUH;
11776 if (dest_mode == V4SImode && op_mode == V4SImode)
11777 return UNSPEC_VCMPGTUW;
11782 return INSN_NOT_AVAILABLE;
11785 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11786 DMODE is expected destination mode. This is a recursive function. */
11789 rs6000_emit_vector_compare (enum rtx_code rcode,
11791 enum machine_mode dmode)
11795 enum machine_mode dest_mode;
11796 enum machine_mode op_mode = GET_MODE (op1);
11798 #ifdef ENABLE_CHECKING
11799 if (!TARGET_ALTIVEC)
11802 if (GET_MODE (op0) != GET_MODE (op1))
11806 /* Floating point vector compare instructions uses destination V4SImode.
11807 Move destination to appropriate mode later. */
11808 if (dmode == V4SFmode)
11809 dest_mode = V4SImode;
11813 mask = gen_reg_rtx (dest_mode);
11814 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11816 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11818 bool swap_operands = false;
11819 bool try_again = false;
11824 swap_operands = true;
11829 swap_operands = true;
11833 /* Treat A != B as ~(A==B). */
11835 enum insn_code nor_code;
11836 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11839 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11840 if (nor_code == CODE_FOR_nothing)
11842 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11844 if (dmode != dest_mode)
11846 rtx temp = gen_reg_rtx (dest_mode);
11847 convert_move (temp, mask, 0);
11857 /* Try GT/GTU/LT/LTU OR EQ */
11860 enum insn_code ior_code;
11861 enum rtx_code new_code;
11865 else if (rcode == GEU)
11867 else if (rcode == LE)
11869 else if (rcode == LEU)
11874 c_rtx = rs6000_emit_vector_compare (new_code,
11875 op0, op1, dest_mode);
11876 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11879 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11880 if (ior_code == CODE_FOR_nothing)
11882 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11883 if (dmode != dest_mode)
11885 rtx temp = gen_reg_rtx (dest_mode);
11886 convert_move (temp, mask, 0);
11898 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11899 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11900 /* You only get two chances. */
11913 emit_insn (gen_rtx_fmt_ee (SET,
11916 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11917 gen_rtvec (2, op0, op1),
11919 if (dmode != dest_mode)
11921 rtx temp = gen_reg_rtx (dest_mode);
11922 convert_move (temp, mask, 0);
11928 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11929 valid insn doesn exist for given mode. */
11932 get_vsel_insn (enum machine_mode mode)
11937 return UNSPEC_VSEL4SI;
11940 return UNSPEC_VSEL4SF;
11943 return UNSPEC_VSEL8HI;
11946 return UNSPEC_VSEL16QI;
11949 return INSN_NOT_AVAILABLE;
11952 return INSN_NOT_AVAILABLE;
11955 /* Emit vector select insn where DEST is destination using
11956 operands OP1, OP2 and MASK. */
11959 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11962 enum machine_mode dest_mode = GET_MODE (dest);
11963 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11965 temp = gen_reg_rtx (dest_mode);
11967 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
11968 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11969 gen_rtvec (3, op1, op2, mask),
11972 emit_move_insn (dest, temp);
11976 /* Emit vector conditional expression.
11977 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11978 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11981 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11982 rtx cond, rtx cc_op0, rtx cc_op1)
11984 enum machine_mode dest_mode = GET_MODE (dest);
11985 enum rtx_code rcode = GET_CODE (cond);
11988 if (!TARGET_ALTIVEC)
11991 /* Get the vector mask for the given relational operations. */
11992 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11994 rs6000_emit_vector_select (dest, op1, op2, mask);
11999 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12000 operands of the last comparison is nonzero/true, FALSE_COND if it
12001 is zero/false. Return 0 if the hardware has no such operation. */
12004 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12006 enum rtx_code code = GET_CODE (op);
12007 rtx op0 = rs6000_compare_op0;
12008 rtx op1 = rs6000_compare_op1;
12009 REAL_VALUE_TYPE c1;
12010 enum machine_mode compare_mode = GET_MODE (op0);
12011 enum machine_mode result_mode = GET_MODE (dest);
12013 bool is_against_zero;
12015 /* These modes should always match. */
12016 if (GET_MODE (op1) != compare_mode
12017 /* In the isel case however, we can use a compare immediate, so
12018 op1 may be a small constant. */
12019 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12021 if (GET_MODE (true_cond) != result_mode)
12023 if (GET_MODE (false_cond) != result_mode)
12026 /* First, work out if the hardware can do this at all, or
12027 if it's too slow.... */
12028 if (! rs6000_compare_fp_p)
12031 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12034 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
12035 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
12038 is_against_zero = op1 == CONST0_RTX (compare_mode);
12040 /* A floating-point subtract might overflow, underflow, or produce
12041 an inexact result, thus changing the floating-point flags, so it
12042 can't be generated if we care about that. It's safe if one side
12043 of the construct is zero, since then no subtract will be
12045 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
12046 && flag_trapping_math && ! is_against_zero)
12049 /* Eliminate half of the comparisons by switching operands, this
12050 makes the remaining code simpler. */
12051 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12052 || code == LTGT || code == LT || code == UNLE)
12054 code = reverse_condition_maybe_unordered (code);
12056 true_cond = false_cond;
12060 /* UNEQ and LTGT take four instructions for a comparison with zero,
12061 it'll probably be faster to use a branch here too. */
12062 if (code == UNEQ && HONOR_NANS (compare_mode))
12065 if (GET_CODE (op1) == CONST_DOUBLE)
12066 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12068 /* We're going to try to implement comparisons by performing
12069 a subtract, then comparing against zero. Unfortunately,
12070 Inf - Inf is NaN which is not zero, and so if we don't
12071 know that the operand is finite and the comparison
12072 would treat EQ different to UNORDERED, we can't do it. */
12073 if (HONOR_INFINITIES (compare_mode)
12074 && code != GT && code != UNGE
12075 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12076 /* Constructs of the form (a OP b ? a : b) are safe. */
12077 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12078 || (! rtx_equal_p (op0, true_cond)
12079 && ! rtx_equal_p (op1, true_cond))))
12082 /* At this point we know we can use fsel. */
12084 /* Reduce the comparison to a comparison against zero. */
12085 if (! is_against_zero)
12087 temp = gen_reg_rtx (compare_mode);
12088 emit_insn (gen_rtx_SET (VOIDmode, temp,
12089 gen_rtx_MINUS (compare_mode, op0, op1)));
12091 op1 = CONST0_RTX (compare_mode);
12094 /* If we don't care about NaNs we can reduce some of the comparisons
12095 down to faster ones. */
12096 if (! HONOR_NANS (compare_mode))
12102 true_cond = false_cond;
12115 /* Now, reduce everything down to a GE. */
12122 temp = gen_reg_rtx (compare_mode);
12123 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12128 temp = gen_reg_rtx (compare_mode);
12129 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12134 temp = gen_reg_rtx (compare_mode);
12135 emit_insn (gen_rtx_SET (VOIDmode, temp,
12136 gen_rtx_NEG (compare_mode,
12137 gen_rtx_ABS (compare_mode, op0))));
12142 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12143 temp = gen_reg_rtx (result_mode);
12144 emit_insn (gen_rtx_SET (VOIDmode, temp,
12145 gen_rtx_IF_THEN_ELSE (result_mode,
12146 gen_rtx_GE (VOIDmode,
12148 true_cond, false_cond)));
12149 false_cond = true_cond;
12152 temp = gen_reg_rtx (compare_mode);
12153 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12158 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12159 temp = gen_reg_rtx (result_mode);
12160 emit_insn (gen_rtx_SET (VOIDmode, temp,
12161 gen_rtx_IF_THEN_ELSE (result_mode,
12162 gen_rtx_GE (VOIDmode,
12164 true_cond, false_cond)));
12165 true_cond = false_cond;
12168 temp = gen_reg_rtx (compare_mode);
12169 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12177 emit_insn (gen_rtx_SET (VOIDmode, dest,
12178 gen_rtx_IF_THEN_ELSE (result_mode,
12179 gen_rtx_GE (VOIDmode,
12181 true_cond, false_cond)));
12185 /* Same as above, but for ints (isel). */
12188 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12190 rtx condition_rtx, cr;
12192 /* All isel implementations thus far are 32-bits. */
12193 if (GET_MODE (rs6000_compare_op0) != SImode)
12196 /* We still have to do the compare, because isel doesn't do a
12197 compare, it just looks at the CRx bits set by a previous compare
12199 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12200 cr = XEXP (condition_rtx, 0);
12202 if (GET_MODE (cr) == CCmode)
12203 emit_insn (gen_isel_signed (dest, condition_rtx,
12204 true_cond, false_cond, cr));
12206 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12207 true_cond, false_cond, cr));
12213 output_isel (rtx *operands)
12215 enum rtx_code code;
12217 code = GET_CODE (operands[1]);
12218 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12220 PUT_CODE (operands[1], reverse_condition (code));
12221 return "isel %0,%3,%2,%j1";
12224 return "isel %0,%2,%3,%j1";
12228 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12230 enum machine_mode mode = GET_MODE (op0);
12234 if (code == SMAX || code == SMIN)
12239 if (code == SMAX || code == UMAX)
12240 target = emit_conditional_move (dest, c, op0, op1, mode,
12241 op0, op1, mode, 0);
12243 target = emit_conditional_move (dest, c, op0, op1, mode,
12244 op1, op0, mode, 0);
12245 if (target == NULL_RTX)
12247 if (target != dest)
12248 emit_move_insn (dest, target);
12251 /* Emit instructions to move SRC to DST. Called by splitters for
12252 multi-register moves. It will emit at most one instruction for
12253 each register that is accessed; that is, it won't emit li/lis pairs
12254 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12258 rs6000_split_multireg_move (rtx dst, rtx src)
12260 /* The register number of the first register being moved. */
12262 /* The mode that is to be moved. */
12263 enum machine_mode mode;
12264 /* The mode that the move is being done in, and its size. */
12265 enum machine_mode reg_mode;
12267 /* The number of registers that will be moved. */
12270 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12271 mode = GET_MODE (dst);
12272 nregs = HARD_REGNO_NREGS (reg, mode);
12273 if (FP_REGNO_P (reg))
12275 else if (ALTIVEC_REGNO_P (reg))
12276 reg_mode = V16QImode;
12278 reg_mode = word_mode;
12279 reg_mode_size = GET_MODE_SIZE (reg_mode);
12281 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
12284 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12286 /* Move register range backwards, if we might have destructive
12289 for (i = nregs - 1; i >= 0; i--)
12290 emit_insn (gen_rtx_SET (VOIDmode,
12291 simplify_gen_subreg (reg_mode, dst, mode,
12292 i * reg_mode_size),
12293 simplify_gen_subreg (reg_mode, src, mode,
12294 i * reg_mode_size)));
12300 bool used_update = false;
12302 if (MEM_P (src) && INT_REGNO_P (reg))
12306 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12307 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12310 breg = XEXP (XEXP (src, 0), 0);
12311 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12312 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12313 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12314 emit_insn (TARGET_32BIT
12315 ? gen_addsi3 (breg, breg, delta_rtx)
12316 : gen_adddi3 (breg, breg, delta_rtx));
12317 src = gen_rtx_MEM (mode, breg);
12319 else if (! offsettable_memref_p (src))
12321 rtx newsrc, basereg;
12322 basereg = gen_rtx_REG (Pmode, reg);
12323 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12324 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
12325 MEM_COPY_ATTRIBUTES (newsrc, src);
12329 breg = XEXP (src, 0);
12330 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12331 breg = XEXP (breg, 0);
12333 /* If the base register we are using to address memory is
12334 also a destination reg, then change that register last. */
12336 && REGNO (breg) >= REGNO (dst)
12337 && REGNO (breg) < REGNO (dst) + nregs)
12338 j = REGNO (breg) - REGNO (dst);
12341 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12345 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12346 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12349 breg = XEXP (XEXP (dst, 0), 0);
12350 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12351 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12352 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12354 /* We have to update the breg before doing the store.
12355 Use store with update, if available. */
12359 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12360 emit_insn (TARGET_32BIT
12361 ? (TARGET_POWERPC64
12362 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12363 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12364 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12365 used_update = true;
12368 emit_insn (TARGET_32BIT
12369 ? gen_addsi3 (breg, breg, delta_rtx)
12370 : gen_adddi3 (breg, breg, delta_rtx));
12371 dst = gen_rtx_MEM (mode, breg);
12373 else if (! offsettable_memref_p (dst))
12377 for (i = 0; i < nregs; i++)
12379 /* Calculate index to next subword. */
12384 /* If compiler already emitted move of first word by
12385 store with update, no need to do anything. */
12386 if (j == 0 && used_update)
12389 emit_insn (gen_rtx_SET (VOIDmode,
12390 simplify_gen_subreg (reg_mode, dst, mode,
12391 j * reg_mode_size),
12392 simplify_gen_subreg (reg_mode, src, mode,
12393 j * reg_mode_size)));
12399 /* This page contains routines that are used to determine what the
12400 function prologue and epilogue code will do and write them out. */
12402 /* Return the first fixed-point register that is required to be
12403 saved. 32 if none. */
12406 first_reg_to_save (void)
12410 /* Find lowest numbered live register. */
12411 for (first_reg = 13; first_reg <= 31; first_reg++)
12412 if (regs_ever_live[first_reg]
12413 && (! call_used_regs[first_reg]
12414 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12415 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12416 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12417 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12422 && current_function_uses_pic_offset_table
12423 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12424 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12430 /* Similar, for FP regs. */
12433 first_fp_reg_to_save (void)
12437 /* Find lowest numbered live register. */
12438 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12439 if (regs_ever_live[first_reg])
12445 /* Similar, for AltiVec regs. */
12448 first_altivec_reg_to_save (void)
12452 /* Stack frame remains as is unless we are in AltiVec ABI. */
12453 if (! TARGET_ALTIVEC_ABI)
12454 return LAST_ALTIVEC_REGNO + 1;
12456 /* Find lowest numbered live register. */
12457 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12458 if (regs_ever_live[i])
12464 /* Return a 32-bit mask of the AltiVec registers we need to set in
12465 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12466 the 32-bit word is 0. */
12468 static unsigned int
12469 compute_vrsave_mask (void)
12471 unsigned int i, mask = 0;
12473 /* First, find out if we use _any_ altivec registers. */
12474 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12475 if (regs_ever_live[i])
12476 mask |= ALTIVEC_REG_BIT (i);
12481 /* Next, remove the argument registers from the set. These must
12482 be in the VRSAVE mask set by the caller, so we don't need to add
12483 them in again. More importantly, the mask we compute here is
12484 used to generate CLOBBERs in the set_vrsave insn, and we do not
12485 wish the argument registers to die. */
12486 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12487 mask &= ~ALTIVEC_REG_BIT (i);
12489 /* Similarly, remove the return value from the set. */
12492 diddle_return_value (is_altivec_return_reg, &yes);
12494 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12500 /* For a very restricted set of circumstances, we can cut down the
12501 size of prologues/epilogues by calling our own save/restore-the-world
12505 compute_save_world_info (rs6000_stack_t *info_ptr)
12507 info_ptr->world_save_p = 1;
12508 info_ptr->world_save_p
12509 = (WORLD_SAVE_P (info_ptr)
12510 && DEFAULT_ABI == ABI_DARWIN
12511 && ! (current_function_calls_setjmp && flag_exceptions)
12512 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12513 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12514 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12515 && info_ptr->cr_save_p);
12517 /* This will not work in conjunction with sibcalls. Make sure there
12518 are none. (This check is expensive, but seldom executed.) */
12519 if (WORLD_SAVE_P (info_ptr))
12522 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12523 if ( GET_CODE (insn) == CALL_INSN
12524 && SIBLING_CALL_P (insn))
12526 info_ptr->world_save_p = 0;
12531 if (WORLD_SAVE_P (info_ptr))
12533 /* Even if we're not touching VRsave, make sure there's room on the
12534 stack for it, if it looks like we're calling SAVE_WORLD, which
12535 will attempt to save it. */
12536 info_ptr->vrsave_size = 4;
12538 /* "Save" the VRsave register too if we're saving the world. */
12539 if (info_ptr->vrsave_mask == 0)
12540 info_ptr->vrsave_mask = compute_vrsave_mask ();
12542 /* Because the Darwin register save/restore routines only handle
12543 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12544 check and abort if there's something worng. */
12545 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
12546 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
12554 is_altivec_return_reg (rtx reg, void *xyes)
12556 bool *yes = (bool *) xyes;
12557 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12562 /* Calculate the stack information for the current function. This is
12563 complicated by having two separate calling sequences, the AIX calling
12564 sequence and the V.4 calling sequence.
12566 AIX (and Darwin/Mac OS X) stack frames look like:
12568 SP----> +---------------------------------------+
12569 | back chain to caller | 0 0
12570 +---------------------------------------+
12571 | saved CR | 4 8 (8-11)
12572 +---------------------------------------+
12574 +---------------------------------------+
12575 | reserved for compilers | 12 24
12576 +---------------------------------------+
12577 | reserved for binders | 16 32
12578 +---------------------------------------+
12579 | saved TOC pointer | 20 40
12580 +---------------------------------------+
12581 | Parameter save area (P) | 24 48
12582 +---------------------------------------+
12583 | Alloca space (A) | 24+P etc.
12584 +---------------------------------------+
12585 | Local variable space (L) | 24+P+A
12586 +---------------------------------------+
12587 | Float/int conversion temporary (X) | 24+P+A+L
12588 +---------------------------------------+
12589 | Save area for AltiVec registers (W) | 24+P+A+L+X
12590 +---------------------------------------+
12591 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12592 +---------------------------------------+
12593 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12594 +---------------------------------------+
12595 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12596 +---------------------------------------+
12597 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12598 +---------------------------------------+
12599 old SP->| back chain to caller's caller |
12600 +---------------------------------------+
12602 The required alignment for AIX configurations is two words (i.e., 8
12606 V.4 stack frames look like:
12608 SP----> +---------------------------------------+
12609 | back chain to caller | 0
12610 +---------------------------------------+
12611 | caller's saved LR | 4
12612 +---------------------------------------+
12613 | Parameter save area (P) | 8
12614 +---------------------------------------+
12615 | Alloca space (A) | 8+P
12616 +---------------------------------------+
12617 | Varargs save area (V) | 8+P+A
12618 +---------------------------------------+
12619 | Local variable space (L) | 8+P+A+V
12620 +---------------------------------------+
12621 | Float/int conversion temporary (X) | 8+P+A+V+L
12622 +---------------------------------------+
12623 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12624 +---------------------------------------+
12625 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12626 +---------------------------------------+
12627 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12628 +---------------------------------------+
12629 | SPE: area for 64-bit GP registers |
12630 +---------------------------------------+
12631 | SPE alignment padding |
12632 +---------------------------------------+
12633 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12634 +---------------------------------------+
12635 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12636 +---------------------------------------+
12637 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12638 +---------------------------------------+
12639 old SP->| back chain to caller's caller |
12640 +---------------------------------------+
12642 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12643 given. (But note below and in sysv4.h that we require only 8 and
12644 may round up the size of our stack frame anyways. The historical
12645 reason is early versions of powerpc-linux which didn't properly
12646 align the stack at program startup. A happy side-effect is that
12647 -mno-eabi libraries can be used with -meabi programs.)
12649 The EABI configuration defaults to the V.4 layout. However,
12650 the stack alignment requirements may differ. If -mno-eabi is not
12651 given, the required stack alignment is 8 bytes; if -mno-eabi is
12652 given, the required alignment is 16 bytes. (But see V.4 comment
12655 #ifndef ABI_STACK_BOUNDARY
12656 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12659 static rs6000_stack_t *
12660 rs6000_stack_info (void)
12662 static rs6000_stack_t info, zero_info;
12663 rs6000_stack_t *info_ptr = &info;
12664 int reg_size = TARGET_32BIT ? 4 : 8;
12667 HOST_WIDE_INT non_fixed_size;
12669 /* Zero all fields portably. */
12674 /* Cache value so we don't rescan instruction chain over and over. */
12675 if (cfun->machine->insn_chain_scanned_p == 0)
12676 cfun->machine->insn_chain_scanned_p
12677 = spe_func_has_64bit_regs_p () + 1;
12678 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12681 /* Select which calling sequence. */
12682 info_ptr->abi = DEFAULT_ABI;
12684 /* Calculate which registers need to be saved & save area size. */
12685 info_ptr->first_gp_reg_save = first_reg_to_save ();
12686 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12687 even if it currently looks like we won't. */
12688 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12689 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12690 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12691 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12692 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12694 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12696 /* For the SPE, we have an additional upper 32-bits on each GPR.
12697 Ideally we should save the entire 64-bits only when the upper
12698 half is used in SIMD instructions. Since we only record
12699 registers live (not the size they are used in), this proves
12700 difficult because we'd have to traverse the instruction chain at
12701 the right time, taking reload into account. This is a real pain,
12702 so we opt to save the GPRs in 64-bits always if but one register
12703 gets used in 64-bits. Otherwise, all the registers in the frame
12704 get saved in 32-bits.
12706 So... since when we save all GPRs (except the SP) in 64-bits, the
12707 traditional GP save area will be empty. */
12708 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12709 info_ptr->gp_size = 0;
12711 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12712 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12714 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12715 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12716 - info_ptr->first_altivec_reg_save);
12718 /* Does this function call anything? */
12719 info_ptr->calls_p = (! current_function_is_leaf
12720 || cfun->machine->ra_needs_full_frame);
12722 /* Determine if we need to save the link register. */
12723 if (rs6000_ra_ever_killed ()
12724 || (DEFAULT_ABI == ABI_AIX
12725 && current_function_profile
12726 && !TARGET_PROFILE_KERNEL)
12727 #ifdef TARGET_RELOCATABLE
12728 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12730 || (info_ptr->first_fp_reg_save != 64
12731 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12732 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12733 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12734 || (DEFAULT_ABI == ABI_DARWIN
12736 && current_function_uses_pic_offset_table)
12737 || info_ptr->calls_p)
12739 info_ptr->lr_save_p = 1;
12740 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12743 /* Determine if we need to save the condition code registers. */
12744 if (regs_ever_live[CR2_REGNO]
12745 || regs_ever_live[CR3_REGNO]
12746 || regs_ever_live[CR4_REGNO])
12748 info_ptr->cr_save_p = 1;
12749 if (DEFAULT_ABI == ABI_V4)
12750 info_ptr->cr_size = reg_size;
12753 /* If the current function calls __builtin_eh_return, then we need
12754 to allocate stack space for registers that will hold data for
12755 the exception handler. */
12756 if (current_function_calls_eh_return)
12759 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12762 /* SPE saves EH registers in 64-bits. */
12763 ehrd_size = i * (TARGET_SPE_ABI
12764 && info_ptr->spe_64bit_regs_used != 0
12765 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12770 /* Determine various sizes. */
12771 info_ptr->reg_size = reg_size;
12772 info_ptr->fixed_size = RS6000_SAVE_AREA;
12773 info_ptr->varargs_size = RS6000_VARARGS_AREA;
12774 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12775 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12776 TARGET_ALTIVEC ? 16 : 8);
12778 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12779 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12781 info_ptr->spe_gp_size = 0;
12783 if (TARGET_ALTIVEC_ABI)
12784 info_ptr->vrsave_mask = compute_vrsave_mask ();
12786 info_ptr->vrsave_mask = 0;
12788 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12789 info_ptr->vrsave_size = 4;
12791 info_ptr->vrsave_size = 0;
12793 compute_save_world_info (info_ptr);
12795 /* Calculate the offsets. */
12796 switch (DEFAULT_ABI)
12804 info_ptr->fp_save_offset = - info_ptr->fp_size;
12805 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12807 if (TARGET_ALTIVEC_ABI)
12809 info_ptr->vrsave_save_offset
12810 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12812 /* Align stack so vector save area is on a quadword boundary. */
12813 if (info_ptr->altivec_size != 0)
12814 info_ptr->altivec_padding_size
12815 = 16 - (-info_ptr->vrsave_save_offset % 16);
12817 info_ptr->altivec_padding_size = 0;
12819 info_ptr->altivec_save_offset
12820 = info_ptr->vrsave_save_offset
12821 - info_ptr->altivec_padding_size
12822 - info_ptr->altivec_size;
12824 /* Adjust for AltiVec case. */
12825 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12828 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12829 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12830 info_ptr->lr_save_offset = 2*reg_size;
12834 info_ptr->fp_save_offset = - info_ptr->fp_size;
12835 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12836 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12838 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12840 /* Align stack so SPE GPR save area is aligned on a
12841 double-word boundary. */
12842 if (info_ptr->spe_gp_size != 0)
12843 info_ptr->spe_padding_size
12844 = 8 - (-info_ptr->cr_save_offset % 8);
12846 info_ptr->spe_padding_size = 0;
12848 info_ptr->spe_gp_save_offset
12849 = info_ptr->cr_save_offset
12850 - info_ptr->spe_padding_size
12851 - info_ptr->spe_gp_size;
12853 /* Adjust for SPE case. */
12854 info_ptr->toc_save_offset
12855 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12857 else if (TARGET_ALTIVEC_ABI)
12859 info_ptr->vrsave_save_offset
12860 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12862 /* Align stack so vector save area is on a quadword boundary. */
12863 if (info_ptr->altivec_size != 0)
12864 info_ptr->altivec_padding_size
12865 = 16 - (-info_ptr->vrsave_save_offset % 16);
12867 info_ptr->altivec_padding_size = 0;
12869 info_ptr->altivec_save_offset
12870 = info_ptr->vrsave_save_offset
12871 - info_ptr->altivec_padding_size
12872 - info_ptr->altivec_size;
12874 /* Adjust for AltiVec case. */
12875 info_ptr->toc_save_offset
12876 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12879 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12880 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12881 info_ptr->lr_save_offset = reg_size;
12885 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12886 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12887 + info_ptr->gp_size
12888 + info_ptr->altivec_size
12889 + info_ptr->altivec_padding_size
12890 + info_ptr->spe_gp_size
12891 + info_ptr->spe_padding_size
12893 + info_ptr->cr_size
12894 + info_ptr->lr_size
12895 + info_ptr->vrsave_size
12896 + info_ptr->toc_size,
12899 non_fixed_size = (info_ptr->vars_size
12900 + info_ptr->parm_size
12901 + info_ptr->save_size
12902 + info_ptr->varargs_size);
12904 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12905 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12907 /* Determine if we need to allocate any stack frame:
12909 For AIX we need to push the stack if a frame pointer is needed
12910 (because the stack might be dynamically adjusted), if we are
12911 debugging, if we make calls, or if the sum of fp_save, gp_save,
12912 and local variables are more than the space needed to save all
12913 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12914 + 18*8 = 288 (GPR13 reserved).
12916 For V.4 we don't have the stack cushion that AIX uses, but assume
12917 that the debugger can handle stackless frames. */
12919 if (info_ptr->calls_p)
12920 info_ptr->push_p = 1;
12922 else if (DEFAULT_ABI == ABI_V4)
12923 info_ptr->push_p = non_fixed_size != 0;
12925 else if (frame_pointer_needed)
12926 info_ptr->push_p = 1;
12928 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12929 info_ptr->push_p = 1;
12932 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12934 /* Zero offsets if we're not saving those registers. */
12935 if (info_ptr->fp_size == 0)
12936 info_ptr->fp_save_offset = 0;
12938 if (info_ptr->gp_size == 0)
12939 info_ptr->gp_save_offset = 0;
12941 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12942 info_ptr->altivec_save_offset = 0;
12944 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12945 info_ptr->vrsave_save_offset = 0;
12947 if (! TARGET_SPE_ABI
12948 || info_ptr->spe_64bit_regs_used == 0
12949 || info_ptr->spe_gp_size == 0)
12950 info_ptr->spe_gp_save_offset = 0;
12952 if (! info_ptr->lr_save_p)
12953 info_ptr->lr_save_offset = 0;
12955 if (! info_ptr->cr_save_p)
12956 info_ptr->cr_save_offset = 0;
12958 if (! info_ptr->toc_save_p)
12959 info_ptr->toc_save_offset = 0;
12964 /* Return true if the current function uses any GPRs in 64-bit SIMD
12968 spe_func_has_64bit_regs_p (void)
12972 /* Functions that save and restore all the call-saved registers will
12973 need to save/restore the registers in 64-bits. */
12974 if (current_function_calls_eh_return
12975 || current_function_calls_setjmp
12976 || current_function_has_nonlocal_goto)
12979 insns = get_insns ();
12981 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12987 /* FIXME: This should be implemented with attributes...
12989 (set_attr "spe64" "true")....then,
12990 if (get_spe64(insn)) return true;
12992 It's the only reliable way to do the stuff below. */
12994 i = PATTERN (insn);
12995 if (GET_CODE (i) == SET)
12997 enum machine_mode mode = GET_MODE (SET_SRC (i));
12999 if (SPE_VECTOR_MODE (mode))
13001 if (TARGET_E500_DOUBLE && mode == DFmode)
13011 debug_stack_info (rs6000_stack_t *info)
13013 const char *abi_string;
13016 info = rs6000_stack_info ();
13018 fprintf (stderr, "\nStack information for function %s:\n",
13019 ((current_function_decl && DECL_NAME (current_function_decl))
13020 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13025 default: abi_string = "Unknown"; break;
13026 case ABI_NONE: abi_string = "NONE"; break;
13027 case ABI_AIX: abi_string = "AIX"; break;
13028 case ABI_DARWIN: abi_string = "Darwin"; break;
13029 case ABI_V4: abi_string = "V.4"; break;
13032 fprintf (stderr, "\tABI = %5s\n", abi_string);
13034 if (TARGET_ALTIVEC_ABI)
13035 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13037 if (TARGET_SPE_ABI)
13038 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13040 if (info->first_gp_reg_save != 32)
13041 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13043 if (info->first_fp_reg_save != 64)
13044 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13046 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13047 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13048 info->first_altivec_reg_save);
13050 if (info->lr_save_p)
13051 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13053 if (info->cr_save_p)
13054 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13056 if (info->toc_save_p)
13057 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
13059 if (info->vrsave_mask)
13060 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13063 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13066 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13068 if (info->gp_save_offset)
13069 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13071 if (info->fp_save_offset)
13072 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13074 if (info->altivec_save_offset)
13075 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13076 info->altivec_save_offset);
13078 if (info->spe_gp_save_offset)
13079 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13080 info->spe_gp_save_offset);
13082 if (info->vrsave_save_offset)
13083 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13084 info->vrsave_save_offset);
13086 if (info->lr_save_offset)
13087 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13089 if (info->cr_save_offset)
13090 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13092 if (info->toc_save_offset)
13093 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
13095 if (info->varargs_save_offset)
13096 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13098 if (info->total_size)
13099 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13102 if (info->varargs_size)
13103 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
13105 if (info->vars_size)
13106 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13109 if (info->parm_size)
13110 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13112 if (info->fixed_size)
13113 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13116 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13118 if (info->spe_gp_size)
13119 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13122 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13124 if (info->altivec_size)
13125 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13127 if (info->vrsave_size)
13128 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13130 if (info->altivec_padding_size)
13131 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13132 info->altivec_padding_size);
13134 if (info->spe_padding_size)
13135 fprintf (stderr, "\tspe_padding_size = %5d\n",
13136 info->spe_padding_size);
13139 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
13142 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13144 if (info->toc_size)
13145 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
13147 if (info->save_size)
13148 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13150 if (info->reg_size != 4)
13151 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13153 fprintf (stderr, "\n");
13157 rs6000_return_addr (int count, rtx frame)
13159 /* Currently we don't optimize very well between prolog and body
13160 code and for PIC code the code can be actually quite bad, so
13161 don't try to be too clever here. */
13162 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13164 cfun->machine->ra_needs_full_frame = 1;
13171 plus_constant (copy_to_reg
13172 (gen_rtx_MEM (Pmode,
13173 memory_address (Pmode, frame))),
13174 RETURN_ADDRESS_OFFSET)));
13177 cfun->machine->ra_need_lr = 1;
13178 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13181 /* Say whether a function is a candidate for sibcall handling or not.
13182 We do not allow indirect calls to be optimized into sibling calls.
13183 Also, we can't do it if there are any vector parameters; there's
13184 nowhere to put the VRsave code so it works; note that functions with
13185 vector parameters are required to have a prototype, so the argument
13186 type info must be available here. (The tail recursion case can work
13187 with vector parameters, but there's no way to distinguish here.) */
13189 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13194 if (TARGET_ALTIVEC_VRSAVE)
13196 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13197 type; type = TREE_CHAIN (type))
13199 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13203 if (DEFAULT_ABI == ABI_DARWIN
13204 || (*targetm.binds_local_p) (decl))
13206 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13208 if (!lookup_attribute ("longcall", attr_list)
13209 || lookup_attribute ("shortcall", attr_list))
13217 rs6000_ra_ever_killed (void)
13223 if (current_function_is_thunk)
13226 /* regs_ever_live has LR marked as used if any sibcalls are present,
13227 but this should not force saving and restoring in the
13228 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13229 clobbers LR, so that is inappropriate. */
13231 /* Also, the prologue can generate a store into LR that
13232 doesn't really count, like this:
13235 bcl to set PIC register
13239 When we're called from the epilogue, we need to avoid counting
13240 this as a store. */
13242 push_topmost_sequence ();
13243 top = get_insns ();
13244 pop_topmost_sequence ();
13245 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13247 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13251 if (FIND_REG_INC_NOTE (insn, reg))
13253 else if (GET_CODE (insn) == CALL_INSN
13254 && !SIBLING_CALL_P (insn))
13256 else if (set_of (reg, insn) != NULL_RTX
13257 && !prologue_epilogue_contains (insn))
13264 /* Add a REG_MAYBE_DEAD note to the insn. */
13266 rs6000_maybe_dead (rtx insn)
13268 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13273 /* Emit instructions needed to load the TOC register.
13274 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13275 a constant pool; or for SVR4 -fpic. */
13278 rs6000_emit_load_toc_table (int fromprolog)
13281 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13283 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13285 rtx temp = (fromprolog
13286 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13287 : gen_reg_rtx (Pmode));
13288 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
13290 rs6000_maybe_dead (insn);
13291 insn = emit_move_insn (dest, temp);
13293 rs6000_maybe_dead (insn);
13295 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13298 rtx tempLR = (fromprolog
13299 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13300 : gen_reg_rtx (Pmode));
13301 rtx temp0 = (fromprolog
13302 ? gen_rtx_REG (Pmode, 0)
13303 : gen_reg_rtx (Pmode));
13310 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13311 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13313 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13314 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13316 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13318 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13319 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13326 static int reload_toc_labelno = 0;
13328 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13330 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
13331 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13333 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
13334 emit_move_insn (dest, tempLR);
13335 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13337 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13339 rs6000_maybe_dead (insn);
13341 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13343 /* This is for AIX code running in non-PIC ELF32. */
13346 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13347 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13349 insn = emit_insn (gen_elf_high (dest, realsym));
13351 rs6000_maybe_dead (insn);
13352 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13354 rs6000_maybe_dead (insn);
13356 else if (DEFAULT_ABI == ABI_AIX)
13359 insn = emit_insn (gen_load_toc_aix_si (dest));
13361 insn = emit_insn (gen_load_toc_aix_di (dest));
13363 rs6000_maybe_dead (insn);
13369 /* Emit instructions to restore the link register after determining where
13370 its value has been stored. */
13373 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13375 rs6000_stack_t *info = rs6000_stack_info ();
13378 operands[0] = source;
13379 operands[1] = scratch;
13381 if (info->lr_save_p)
13383 rtx frame_rtx = stack_pointer_rtx;
13384 HOST_WIDE_INT sp_offset = 0;
13387 if (frame_pointer_needed
13388 || current_function_calls_alloca
13389 || info->total_size > 32767)
13391 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13392 frame_rtx = operands[1];
13394 else if (info->push_p)
13395 sp_offset = info->total_size;
13397 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13398 tmp = gen_rtx_MEM (Pmode, tmp);
13399 emit_move_insn (tmp, operands[0]);
13402 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13405 static GTY(()) int set = -1;
13408 get_TOC_alias_set (void)
13411 set = new_alias_set ();
13415 /* This returns nonzero if the current function uses the TOC. This is
13416 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13417 is generated by the ABI_V4 load_toc_* patterns. */
13424 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13427 rtx pat = PATTERN (insn);
13430 if (GET_CODE (pat) == PARALLEL)
13431 for (i = 0; i < XVECLEN (pat, 0); i++)
13433 rtx sub = XVECEXP (pat, 0, i);
13434 if (GET_CODE (sub) == USE)
13436 sub = XEXP (sub, 0);
13437 if (GET_CODE (sub) == UNSPEC
13438 && XINT (sub, 1) == UNSPEC_TOC)
13448 create_TOC_reference (rtx symbol)
13450 return gen_rtx_PLUS (Pmode,
13451 gen_rtx_REG (Pmode, TOC_REGISTER),
13452 gen_rtx_CONST (Pmode,
13453 gen_rtx_MINUS (Pmode, symbol,
13454 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13457 /* If _Unwind_* has been called from within the same module,
13458 toc register is not guaranteed to be saved to 40(1) on function
13459 entry. Save it there in that case. */
13462 rs6000_aix_emit_builtin_unwind_init (void)
13465 rtx stack_top = gen_reg_rtx (Pmode);
13466 rtx opcode_addr = gen_reg_rtx (Pmode);
13467 rtx opcode = gen_reg_rtx (SImode);
13468 rtx tocompare = gen_reg_rtx (SImode);
13469 rtx no_toc_save_needed = gen_label_rtx ();
13471 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
13472 emit_move_insn (stack_top, mem);
13474 mem = gen_rtx_MEM (Pmode,
13475 gen_rtx_PLUS (Pmode, stack_top,
13476 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13477 emit_move_insn (opcode_addr, mem);
13478 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13479 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13480 : 0xE8410028, SImode));
13482 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13483 SImode, NULL_RTX, NULL_RTX,
13484 no_toc_save_needed);
13486 mem = gen_rtx_MEM (Pmode,
13487 gen_rtx_PLUS (Pmode, stack_top,
13488 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13489 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13490 emit_label (no_toc_save_needed);
13493 /* This ties together stack memory (MEM with an alias set of
13494 rs6000_sr_alias_set) and the change to the stack pointer. */
13497 rs6000_emit_stack_tie (void)
13499 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13501 set_mem_alias_set (mem, rs6000_sr_alias_set);
13502 emit_insn (gen_stack_tie (mem));
13505 /* Emit the correct code for allocating stack space, as insns.
13506 If COPY_R12, make sure a copy of the old frame is left in r12.
13507 The generated code may use hard register 0 as a temporary. */
13510 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13513 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13514 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13515 rtx todec = gen_int_mode (-size, Pmode);
13517 if (INTVAL (todec) != -size)
13519 warning("stack frame too large");
13520 emit_insn (gen_trap ());
13524 if (current_function_limit_stack)
13526 if (REG_P (stack_limit_rtx)
13527 && REGNO (stack_limit_rtx) > 1
13528 && REGNO (stack_limit_rtx) <= 31)
13530 emit_insn (TARGET_32BIT
13531 ? gen_addsi3 (tmp_reg,
13534 : gen_adddi3 (tmp_reg,
13538 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13541 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13543 && DEFAULT_ABI == ABI_V4)
13545 rtx toload = gen_rtx_CONST (VOIDmode,
13546 gen_rtx_PLUS (Pmode,
13550 emit_insn (gen_elf_high (tmp_reg, toload));
13551 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13552 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13556 warning ("stack limit expression is not supported");
13559 if (copy_r12 || ! TARGET_UPDATE)
13560 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13566 /* Need a note here so that try_split doesn't get confused. */
13567 if (get_last_insn() == NULL_RTX)
13568 emit_note (NOTE_INSN_DELETED);
13569 insn = emit_move_insn (tmp_reg, todec);
13570 try_split (PATTERN (insn), insn, 0);
13574 insn = emit_insn (TARGET_32BIT
13575 ? gen_movsi_update (stack_reg, stack_reg,
13577 : gen_movdi_di_update (stack_reg, stack_reg,
13578 todec, stack_reg));
13582 insn = emit_insn (TARGET_32BIT
13583 ? gen_addsi3 (stack_reg, stack_reg, todec)
13584 : gen_adddi3 (stack_reg, stack_reg, todec));
13585 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13586 gen_rtx_REG (Pmode, 12));
13589 RTX_FRAME_RELATED_P (insn) = 1;
13591 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13592 gen_rtx_SET (VOIDmode, stack_reg,
13593 gen_rtx_PLUS (Pmode, stack_reg,
13598 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13599 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13600 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13601 deduce these equivalences by itself so it wasn't necessary to hold
13602 its hand so much. */
13605 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13606 rtx reg2, rtx rreg)
13610 /* copy_rtx will not make unique copies of registers, so we need to
13611 ensure we don't have unwanted sharing here. */
13613 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13616 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13618 real = copy_rtx (PATTERN (insn));
13620 if (reg2 != NULL_RTX)
13621 real = replace_rtx (real, reg2, rreg);
13623 real = replace_rtx (real, reg,
13624 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13625 STACK_POINTER_REGNUM),
13628 /* We expect that 'real' is either a SET or a PARALLEL containing
13629 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13630 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13632 if (GET_CODE (real) == SET)
13636 temp = simplify_rtx (SET_SRC (set));
13638 SET_SRC (set) = temp;
13639 temp = simplify_rtx (SET_DEST (set));
13641 SET_DEST (set) = temp;
13642 if (GET_CODE (SET_DEST (set)) == MEM)
13644 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13646 XEXP (SET_DEST (set), 0) = temp;
13649 else if (GET_CODE (real) == PARALLEL)
13652 for (i = 0; i < XVECLEN (real, 0); i++)
13653 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13655 rtx set = XVECEXP (real, 0, i);
13657 temp = simplify_rtx (SET_SRC (set));
13659 SET_SRC (set) = temp;
13660 temp = simplify_rtx (SET_DEST (set));
13662 SET_DEST (set) = temp;
13663 if (GET_CODE (SET_DEST (set)) == MEM)
13665 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13667 XEXP (SET_DEST (set), 0) = temp;
13669 RTX_FRAME_RELATED_P (set) = 1;
13676 real = spe_synthesize_frame_save (real);
13678 RTX_FRAME_RELATED_P (insn) = 1;
13679 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13684 /* Given an SPE frame note, return a PARALLEL of SETs with the
13685 original note, plus a synthetic register save. */
13688 spe_synthesize_frame_save (rtx real)
13690 rtx synth, offset, reg, real2;
13692 if (GET_CODE (real) != SET
13693 || GET_MODE (SET_SRC (real)) != V2SImode)
13696 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13697 frame related note. The parallel contains a set of the register
13698 being saved, and another set to a synthetic register (n+1200).
13699 This is so we can differentiate between 64-bit and 32-bit saves.
13700 Words cannot describe this nastiness. */
13702 if (GET_CODE (SET_DEST (real)) != MEM
13703 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
13704 || GET_CODE (SET_SRC (real)) != REG)
13708 (set (mem (plus (reg x) (const y)))
13711 (set (mem (plus (reg x) (const y+4)))
13715 real2 = copy_rtx (real);
13716 PUT_MODE (SET_DEST (real2), SImode);
13717 reg = SET_SRC (real2);
13718 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13719 synth = copy_rtx (real2);
13721 if (BYTES_BIG_ENDIAN)
13723 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13724 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13727 reg = SET_SRC (synth);
13729 synth = replace_rtx (synth, reg,
13730 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13732 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13733 synth = replace_rtx (synth, offset,
13734 GEN_INT (INTVAL (offset)
13735 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13737 RTX_FRAME_RELATED_P (synth) = 1;
13738 RTX_FRAME_RELATED_P (real2) = 1;
13739 if (BYTES_BIG_ENDIAN)
13740 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13742 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13747 /* Returns an insn that has a vrsave set operation with the
13748 appropriate CLOBBERs. */
13751 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13754 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13755 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13758 = gen_rtx_SET (VOIDmode,
13760 gen_rtx_UNSPEC_VOLATILE (SImode,
13761 gen_rtvec (2, reg, vrsave),
13766 /* We need to clobber the registers in the mask so the scheduler
13767 does not move sets to VRSAVE before sets of AltiVec registers.
13769 However, if the function receives nonlocal gotos, reload will set
13770 all call saved registers live. We will end up with:
13772 (set (reg 999) (mem))
13773 (parallel [ (set (reg vrsave) (unspec blah))
13774 (clobber (reg 999))])
13776 The clobber will cause the store into reg 999 to be dead, and
13777 flow will attempt to delete an epilogue insn. In this case, we
13778 need an unspec use/set of the register. */
13780 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13781 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13783 if (!epiloguep || call_used_regs [i])
13784 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13785 gen_rtx_REG (V4SImode, i));
13788 rtx reg = gen_rtx_REG (V4SImode, i);
13791 = gen_rtx_SET (VOIDmode,
13793 gen_rtx_UNSPEC (V4SImode,
13794 gen_rtvec (1, reg), 27));
13798 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13800 for (i = 0; i < nclobs; ++i)
13801 XVECEXP (insn, 0, i) = clobs[i];
13806 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13807 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13810 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13811 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13813 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13814 rtx replacea, replaceb;
13816 int_rtx = GEN_INT (offset);
13818 /* Some cases that need register indexed addressing. */
13819 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13820 || (TARGET_E500_DOUBLE && mode == DFmode)
13822 && SPE_VECTOR_MODE (mode)
13823 && !SPE_CONST_OFFSET_OK (offset)))
13825 /* Whomever calls us must make sure r11 is available in the
13826 flow path of instructions in the prologue. */
13827 offset_rtx = gen_rtx_REG (Pmode, 11);
13828 emit_move_insn (offset_rtx, int_rtx);
13830 replacea = offset_rtx;
13831 replaceb = int_rtx;
13835 offset_rtx = int_rtx;
13836 replacea = NULL_RTX;
13837 replaceb = NULL_RTX;
13840 reg = gen_rtx_REG (mode, regno);
13841 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13842 mem = gen_rtx_MEM (mode, addr);
13843 set_mem_alias_set (mem, rs6000_sr_alias_set);
13845 insn = emit_move_insn (mem, reg);
13847 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13850 /* Emit an offset memory reference suitable for a frame store, while
13851 converting to a valid addressing mode. */
13854 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13856 rtx int_rtx, offset_rtx;
13858 int_rtx = GEN_INT (offset);
13860 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13861 || (TARGET_E500_DOUBLE && mode == DFmode))
13863 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13864 emit_move_insn (offset_rtx, int_rtx);
13867 offset_rtx = int_rtx;
13869 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13872 #ifndef TARGET_FIX_AND_CONTINUE
13873 #define TARGET_FIX_AND_CONTINUE 0
13876 /* Emit function prologue as insns. */
13879 rs6000_emit_prologue (void)
13881 rs6000_stack_t *info = rs6000_stack_info ();
13882 enum machine_mode reg_mode = Pmode;
13883 int reg_size = TARGET_32BIT ? 4 : 8;
13884 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13885 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13886 rtx frame_reg_rtx = sp_reg_rtx;
13887 rtx cr_save_rtx = NULL_RTX;
13889 int saving_FPRs_inline;
13890 int using_store_multiple;
13891 HOST_WIDE_INT sp_offset = 0;
13893 if (TARGET_FIX_AND_CONTINUE)
13895 /* gdb on darwin arranges to forward a function from the old
13896 address by modifying the first 4 instructions of the function
13897 to branch to the overriding function. This is necessary to
13898 permit function pointers that point to the old function to
13899 actually forward to the new function. */
13900 emit_insn (gen_nop ());
13901 emit_insn (gen_nop ());
13902 emit_insn (gen_nop ());
13903 emit_insn (gen_nop ());
13906 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13908 reg_mode = V2SImode;
13912 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13913 && (!TARGET_SPE_ABI
13914 || info->spe_64bit_regs_used == 0)
13915 && info->first_gp_reg_save < 31);
13916 saving_FPRs_inline = (info->first_fp_reg_save == 64
13917 || FP_SAVE_INLINE (info->first_fp_reg_save)
13918 || current_function_calls_eh_return
13919 || cfun->machine->ra_need_lr);
13921 /* For V.4, update stack before we do any saving and set back pointer. */
13923 && (DEFAULT_ABI == ABI_V4
13924 || current_function_calls_eh_return))
13926 if (info->total_size < 32767)
13927 sp_offset = info->total_size;
13929 frame_reg_rtx = frame_ptr_rtx;
13930 rs6000_emit_allocate_stack (info->total_size,
13931 (frame_reg_rtx != sp_reg_rtx
13932 && (info->cr_save_p
13934 || info->first_fp_reg_save < 64
13935 || info->first_gp_reg_save < 32
13937 if (frame_reg_rtx != sp_reg_rtx)
13938 rs6000_emit_stack_tie ();
13941 /* Handle world saves specially here. */
13942 if (WORLD_SAVE_P (info))
13948 /* save_world expects lr in r0. */
13949 if (info->lr_save_p)
13951 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13952 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13953 RTX_FRAME_RELATED_P (insn) = 1;
13956 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13957 assumptions about the offsets of various bits of the stack
13958 frame. Abort if things aren't what they should be. */
13959 if (info->gp_save_offset != -220
13960 || info->fp_save_offset != -144
13961 || info->lr_save_offset != 8
13962 || info->cr_save_offset != 4
13964 || !info->lr_save_p
13965 || (current_function_calls_eh_return && info->ehrd_offset != -432)
13966 || (info->vrsave_save_offset != -224
13967 || info->altivec_save_offset != (-224 -16 -192)))
13970 treg = gen_rtx_REG (SImode, 11);
13971 emit_move_insn (treg, GEN_INT (-info->total_size));
13973 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13974 in R11. It also clobbers R12, so beware! */
13976 /* Preserve CR2 for save_world prologues */
13978 sz += 32 - info->first_gp_reg_save;
13979 sz += 64 - info->first_fp_reg_save;
13980 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13981 p = rtvec_alloc (sz);
13983 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13984 gen_rtx_REG (Pmode,
13985 LINK_REGISTER_REGNUM));
13986 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13987 gen_rtx_SYMBOL_REF (Pmode,
13989 /* We do floats first so that the instruction pattern matches
13991 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13993 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13994 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13995 GEN_INT (info->fp_save_offset
13996 + sp_offset + 8 * i));
13997 rtx mem = gen_rtx_MEM (DFmode, addr);
13998 set_mem_alias_set (mem, rs6000_sr_alias_set);
14000 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14002 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14004 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14005 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14006 GEN_INT (info->altivec_save_offset
14007 + sp_offset + 16 * i));
14008 rtx mem = gen_rtx_MEM (V4SImode, addr);
14009 set_mem_alias_set (mem, rs6000_sr_alias_set);
14011 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14013 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14015 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14016 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14017 GEN_INT (info->gp_save_offset
14018 + sp_offset + reg_size * i));
14019 rtx mem = gen_rtx_MEM (reg_mode, addr);
14020 set_mem_alias_set (mem, rs6000_sr_alias_set);
14022 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14026 /* CR register traditionally saved as CR2. */
14027 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14028 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14029 GEN_INT (info->cr_save_offset
14031 rtx mem = gen_rtx_MEM (reg_mode, addr);
14032 set_mem_alias_set (mem, rs6000_sr_alias_set);
14034 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14036 /* Prevent any attempt to delete the setting of r0 and treg! */
14037 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14038 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14039 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14041 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14042 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14043 NULL_RTX, NULL_RTX);
14045 if (current_function_calls_eh_return)
14050 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14051 if (regno == INVALID_REGNUM)
14053 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14054 info->ehrd_offset + sp_offset
14055 + reg_size * (int) i,
14061 /* Save AltiVec registers if needed. */
14062 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14066 /* There should be a non inline version of this, for when we
14067 are saving lots of vector registers. */
14068 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14069 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14071 rtx areg, savereg, mem;
14074 offset = info->altivec_save_offset + sp_offset
14075 + 16 * (i - info->first_altivec_reg_save);
14077 savereg = gen_rtx_REG (V4SImode, i);
14079 areg = gen_rtx_REG (Pmode, 0);
14080 emit_move_insn (areg, GEN_INT (offset));
14082 /* AltiVec addressing mode is [reg+reg]. */
14083 mem = gen_rtx_MEM (V4SImode,
14084 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14086 set_mem_alias_set (mem, rs6000_sr_alias_set);
14088 insn = emit_move_insn (mem, savereg);
14090 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14091 areg, GEN_INT (offset));
14095 /* VRSAVE is a bit vector representing which AltiVec registers
14096 are used. The OS uses this to determine which vector
14097 registers to save on a context switch. We need to save
14098 VRSAVE on the stack frame, add whatever AltiVec registers we
14099 used in this function, and do the corresponding magic in the
14102 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14103 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
14105 rtx reg, mem, vrsave;
14108 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14109 as frame_reg_rtx and r11 as the static chain pointer for
14110 nested functions. */
14111 reg = gen_rtx_REG (SImode, 0);
14112 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14114 emit_insn (gen_get_vrsave_internal (reg));
14116 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14119 offset = info->vrsave_save_offset + sp_offset;
14121 = gen_rtx_MEM (SImode,
14122 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
14123 set_mem_alias_set (mem, rs6000_sr_alias_set);
14124 insn = emit_move_insn (mem, reg);
14126 /* Include the registers in the mask. */
14127 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14129 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14132 /* If we use the link register, get it into r0. */
14133 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14135 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14136 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14137 RTX_FRAME_RELATED_P (insn) = 1;
14140 /* If we need to save CR, put it into r12. */
14141 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14145 cr_save_rtx = gen_rtx_REG (SImode, 12);
14146 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14147 RTX_FRAME_RELATED_P (insn) = 1;
14148 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14149 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14150 But that's OK. All we have to do is specify that _one_ condition
14151 code register is saved in this stack slot. The thrower's epilogue
14152 will then restore all the call-saved registers.
14153 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14154 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14155 gen_rtx_REG (SImode, CR2_REGNO));
14156 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14161 /* Do any required saving of fpr's. If only one or two to save, do
14162 it ourselves. Otherwise, call function. */
14163 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14166 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14167 if ((regs_ever_live[info->first_fp_reg_save+i]
14168 && ! call_used_regs[info->first_fp_reg_save+i]))
14169 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14170 info->first_fp_reg_save + i,
14171 info->fp_save_offset + sp_offset + 8 * i,
14174 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14178 const char *alloc_rname;
14180 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14182 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14183 gen_rtx_REG (Pmode,
14184 LINK_REGISTER_REGNUM));
14185 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14186 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14187 alloc_rname = ggc_strdup (rname);
14188 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14189 gen_rtx_SYMBOL_REF (Pmode,
14191 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14193 rtx addr, reg, mem;
14194 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14195 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14196 GEN_INT (info->fp_save_offset
14197 + sp_offset + 8*i));
14198 mem = gen_rtx_MEM (DFmode, addr);
14199 set_mem_alias_set (mem, rs6000_sr_alias_set);
14201 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14203 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14204 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14205 NULL_RTX, NULL_RTX);
14208 /* Save GPRs. This is done as a PARALLEL if we are using
14209 the store-multiple instructions. */
14210 if (!WORLD_SAVE_P (info) && using_store_multiple)
14214 p = rtvec_alloc (32 - info->first_gp_reg_save);
14215 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14217 rtx addr, reg, mem;
14218 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14219 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14220 GEN_INT (info->gp_save_offset
14223 mem = gen_rtx_MEM (reg_mode, addr);
14224 set_mem_alias_set (mem, rs6000_sr_alias_set);
14226 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14228 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14229 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14230 NULL_RTX, NULL_RTX);
14232 else if (!WORLD_SAVE_P (info))
14235 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14236 if ((regs_ever_live[info->first_gp_reg_save+i]
14237 && (! call_used_regs[info->first_gp_reg_save+i]
14238 || (i+info->first_gp_reg_save
14239 == RS6000_PIC_OFFSET_TABLE_REGNUM
14240 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14241 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14242 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14243 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14245 rtx addr, reg, mem;
14246 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14248 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14250 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14253 if (!SPE_CONST_OFFSET_OK (offset))
14255 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14256 emit_move_insn (b, GEN_INT (offset));
14259 b = GEN_INT (offset);
14261 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14262 mem = gen_rtx_MEM (V2SImode, addr);
14263 set_mem_alias_set (mem, rs6000_sr_alias_set);
14264 insn = emit_move_insn (mem, reg);
14266 if (GET_CODE (b) == CONST_INT)
14267 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14268 NULL_RTX, NULL_RTX);
14270 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14271 b, GEN_INT (offset));
14275 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14276 GEN_INT (info->gp_save_offset
14279 mem = gen_rtx_MEM (reg_mode, addr);
14280 set_mem_alias_set (mem, rs6000_sr_alias_set);
14282 insn = emit_move_insn (mem, reg);
14283 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14284 NULL_RTX, NULL_RTX);
14289 /* ??? There's no need to emit actual instructions here, but it's the
14290 easiest way to get the frame unwind information emitted. */
14291 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14293 unsigned int i, regno;
14295 /* In AIX ABI we need to pretend we save r2 here. */
14298 rtx addr, reg, mem;
14300 reg = gen_rtx_REG (reg_mode, 2);
14301 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14302 GEN_INT (sp_offset + 5 * reg_size));
14303 mem = gen_rtx_MEM (reg_mode, addr);
14304 set_mem_alias_set (mem, rs6000_sr_alias_set);
14306 insn = emit_move_insn (mem, reg);
14307 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14308 NULL_RTX, NULL_RTX);
14309 PATTERN (insn) = gen_blockage ();
14314 regno = EH_RETURN_DATA_REGNO (i);
14315 if (regno == INVALID_REGNUM)
14318 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14319 info->ehrd_offset + sp_offset
14320 + reg_size * (int) i,
14325 /* Save lr if we used it. */
14326 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14328 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14329 GEN_INT (info->lr_save_offset + sp_offset));
14330 rtx reg = gen_rtx_REG (Pmode, 0);
14331 rtx mem = gen_rtx_MEM (Pmode, addr);
14332 /* This should not be of rs6000_sr_alias_set, because of
14333 __builtin_return_address. */
14335 insn = emit_move_insn (mem, reg);
14336 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14337 NULL_RTX, NULL_RTX);
14340 /* Save CR if we use any that must be preserved. */
14341 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14343 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14344 GEN_INT (info->cr_save_offset + sp_offset));
14345 rtx mem = gen_rtx_MEM (SImode, addr);
14346 /* See the large comment above about why CR2_REGNO is used. */
14347 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14349 set_mem_alias_set (mem, rs6000_sr_alias_set);
14351 /* If r12 was used to hold the original sp, copy cr into r0 now
14353 if (REGNO (frame_reg_rtx) == 12)
14357 cr_save_rtx = gen_rtx_REG (SImode, 0);
14358 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14359 RTX_FRAME_RELATED_P (insn) = 1;
14360 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14361 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14366 insn = emit_move_insn (mem, cr_save_rtx);
14368 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14369 NULL_RTX, NULL_RTX);
14372 /* Update stack and set back pointer unless this is V.4,
14373 for which it was done previously. */
14374 if (!WORLD_SAVE_P (info) && info->push_p
14375 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14376 rs6000_emit_allocate_stack (info->total_size, FALSE);
14378 /* Set frame pointer, if needed. */
14379 if (frame_pointer_needed)
14381 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
14383 RTX_FRAME_RELATED_P (insn) = 1;
14386 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14387 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14388 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
14389 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14391 /* If emit_load_toc_table will use the link register, we need to save
14392 it. We use R12 for this purpose because emit_load_toc_table
14393 can use register 0. This allows us to use a plain 'blr' to return
14394 from the procedure more often. */
14395 int save_LR_around_toc_setup = (TARGET_ELF
14396 && DEFAULT_ABI != ABI_AIX
14398 && ! info->lr_save_p
14399 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14400 if (save_LR_around_toc_setup)
14402 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14404 insn = emit_move_insn (frame_ptr_rtx, lr);
14405 rs6000_maybe_dead (insn);
14406 RTX_FRAME_RELATED_P (insn) = 1;
14408 rs6000_emit_load_toc_table (TRUE);
14410 insn = emit_move_insn (lr, frame_ptr_rtx);
14411 rs6000_maybe_dead (insn);
14412 RTX_FRAME_RELATED_P (insn) = 1;
14415 rs6000_emit_load_toc_table (TRUE);
14419 if (DEFAULT_ABI == ABI_DARWIN
14420 && flag_pic && current_function_uses_pic_offset_table)
14422 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14423 rtx src = machopic_function_base_sym ();
14425 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14427 insn = emit_move_insn (gen_rtx_REG (Pmode,
14428 RS6000_PIC_OFFSET_TABLE_REGNUM),
14430 rs6000_maybe_dead (insn);
14435 /* Write function prologue. */
14438 rs6000_output_function_prologue (FILE *file,
14439 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14441 rs6000_stack_t *info = rs6000_stack_info ();
14443 if (TARGET_DEBUG_STACK)
14444 debug_stack_info (info);
14446 /* Write .extern for any function we will call to save and restore
14448 if (info->first_fp_reg_save < 64
14449 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14450 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14451 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14452 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14453 RESTORE_FP_SUFFIX);
14455 /* Write .extern for AIX common mode routines, if needed. */
14456 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14458 fputs ("\t.extern __mulh\n", file);
14459 fputs ("\t.extern __mull\n", file);
14460 fputs ("\t.extern __divss\n", file);
14461 fputs ("\t.extern __divus\n", file);
14462 fputs ("\t.extern __quoss\n", file);
14463 fputs ("\t.extern __quous\n", file);
14464 common_mode_defined = 1;
14467 if (! HAVE_prologue)
14471 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14472 the "toplevel" insn chain. */
14473 emit_note (NOTE_INSN_DELETED);
14474 rs6000_emit_prologue ();
14475 emit_note (NOTE_INSN_DELETED);
14477 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14481 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14483 INSN_ADDRESSES_NEW (insn, addr);
14488 if (TARGET_DEBUG_STACK)
14489 debug_rtx_list (get_insns (), 100);
14490 final (get_insns (), file, FALSE, FALSE);
14494 rs6000_pic_labelno++;
14497 /* Emit function epilogue as insns.
14499 At present, dwarf2out_frame_debug_expr doesn't understand
14500 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14501 anywhere in the epilogue. Most of the insns below would in any case
14502 need special notes to explain where r11 is in relation to the stack. */
14505 rs6000_emit_epilogue (int sibcall)
14507 rs6000_stack_t *info;
14508 int restoring_FPRs_inline;
14509 int using_load_multiple;
14510 int using_mfcr_multiple;
14511 int use_backchain_to_restore_sp;
14513 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14514 rtx frame_reg_rtx = sp_reg_rtx;
14515 enum machine_mode reg_mode = Pmode;
14516 int reg_size = TARGET_32BIT ? 4 : 8;
14519 info = rs6000_stack_info ();
14521 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14523 reg_mode = V2SImode;
14527 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14528 && (!TARGET_SPE_ABI
14529 || info->spe_64bit_regs_used == 0)
14530 && info->first_gp_reg_save < 31);
14531 restoring_FPRs_inline = (sibcall
14532 || current_function_calls_eh_return
14533 || info->first_fp_reg_save == 64
14534 || FP_SAVE_INLINE (info->first_fp_reg_save));
14535 use_backchain_to_restore_sp = (frame_pointer_needed
14536 || current_function_calls_alloca
14537 || info->total_size > 32767);
14538 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14539 || rs6000_cpu == PROCESSOR_PPC603
14540 || rs6000_cpu == PROCESSOR_PPC750
14543 if (WORLD_SAVE_P (info))
14547 const char *alloc_rname;
14550 /* eh_rest_world_r10 will return to the location saved in the LR
14551 stack slot (which is not likely to be our caller.)
14552 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14553 rest_world is similar, except any R10 parameter is ignored.
14554 The exception-handling stuff that was here in 2.95 is no
14555 longer necessary. */
14559 + 32 - info->first_gp_reg_save
14560 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14561 + 63 + 1 - info->first_fp_reg_save);
14563 strcpy (rname, ((current_function_calls_eh_return) ?
14564 "*eh_rest_world_r10" : "*rest_world"));
14565 alloc_rname = ggc_strdup (rname);
14568 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14569 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14570 gen_rtx_REG (Pmode,
14571 LINK_REGISTER_REGNUM));
14573 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14574 /* The instruction pattern requires a clobber here;
14575 it is shared with the restVEC helper. */
14577 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14580 /* CR register traditionally saved as CR2. */
14581 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14582 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14583 GEN_INT (info->cr_save_offset));
14584 rtx mem = gen_rtx_MEM (reg_mode, addr);
14585 set_mem_alias_set (mem, rs6000_sr_alias_set);
14587 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14590 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14592 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14593 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14594 GEN_INT (info->gp_save_offset
14596 rtx mem = gen_rtx_MEM (reg_mode, addr);
14597 set_mem_alias_set (mem, rs6000_sr_alias_set);
14599 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14601 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14603 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14604 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14605 GEN_INT (info->altivec_save_offset
14607 rtx mem = gen_rtx_MEM (V4SImode, addr);
14608 set_mem_alias_set (mem, rs6000_sr_alias_set);
14610 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14612 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14614 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14615 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14616 GEN_INT (info->fp_save_offset
14618 rtx mem = gen_rtx_MEM (DFmode, addr);
14619 set_mem_alias_set (mem, rs6000_sr_alias_set);
14621 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14624 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14626 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14628 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14630 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14632 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14633 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14638 /* If we have a frame pointer, a call to alloca, or a large stack
14639 frame, restore the old stack pointer using the backchain. Otherwise,
14640 we know what size to update it with. */
14641 if (use_backchain_to_restore_sp)
14643 /* Under V.4, don't reset the stack pointer until after we're done
14644 loading the saved registers. */
14645 if (DEFAULT_ABI == ABI_V4)
14646 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14648 emit_move_insn (frame_reg_rtx,
14649 gen_rtx_MEM (Pmode, sp_reg_rtx));
14652 else if (info->push_p)
14654 if (DEFAULT_ABI == ABI_V4
14655 || current_function_calls_eh_return)
14656 sp_offset = info->total_size;
14659 emit_insn (TARGET_32BIT
14660 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14661 GEN_INT (info->total_size))
14662 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14663 GEN_INT (info->total_size)));
14667 /* Restore AltiVec registers if needed. */
14668 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14672 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14673 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14675 rtx addr, areg, mem;
14677 areg = gen_rtx_REG (Pmode, 0);
14679 (areg, GEN_INT (info->altivec_save_offset
14681 + 16 * (i - info->first_altivec_reg_save)));
14683 /* AltiVec addressing mode is [reg+reg]. */
14684 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14685 mem = gen_rtx_MEM (V4SImode, addr);
14686 set_mem_alias_set (mem, rs6000_sr_alias_set);
14688 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14692 /* Restore VRSAVE if needed. */
14693 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14694 && info->vrsave_mask != 0)
14696 rtx addr, mem, reg;
14698 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14699 GEN_INT (info->vrsave_save_offset + sp_offset));
14700 mem = gen_rtx_MEM (SImode, addr);
14701 set_mem_alias_set (mem, rs6000_sr_alias_set);
14702 reg = gen_rtx_REG (SImode, 12);
14703 emit_move_insn (reg, mem);
14705 emit_insn (generate_set_vrsave (reg, info, 1));
14708 /* Get the old lr if we saved it. */
14709 if (info->lr_save_p)
14711 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14712 info->lr_save_offset + sp_offset);
14714 set_mem_alias_set (mem, rs6000_sr_alias_set);
14716 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14719 /* Get the old cr if we saved it. */
14720 if (info->cr_save_p)
14722 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14723 GEN_INT (info->cr_save_offset + sp_offset));
14724 rtx mem = gen_rtx_MEM (SImode, addr);
14726 set_mem_alias_set (mem, rs6000_sr_alias_set);
14728 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14731 /* Set LR here to try to overlap restores below. */
14732 if (info->lr_save_p)
14733 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14734 gen_rtx_REG (Pmode, 0));
14736 /* Load exception handler data registers, if needed. */
14737 if (current_function_calls_eh_return)
14739 unsigned int i, regno;
14743 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14744 GEN_INT (sp_offset + 5 * reg_size));
14745 rtx mem = gen_rtx_MEM (reg_mode, addr);
14747 set_mem_alias_set (mem, rs6000_sr_alias_set);
14749 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14756 regno = EH_RETURN_DATA_REGNO (i);
14757 if (regno == INVALID_REGNUM)
14760 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14761 info->ehrd_offset + sp_offset
14762 + reg_size * (int) i);
14763 set_mem_alias_set (mem, rs6000_sr_alias_set);
14765 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14769 /* Restore GPRs. This is done as a PARALLEL if we are using
14770 the load-multiple instructions. */
14771 if (using_load_multiple)
14774 p = rtvec_alloc (32 - info->first_gp_reg_save);
14775 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14777 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14778 GEN_INT (info->gp_save_offset
14781 rtx mem = gen_rtx_MEM (reg_mode, addr);
14783 set_mem_alias_set (mem, rs6000_sr_alias_set);
14786 gen_rtx_SET (VOIDmode,
14787 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14790 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14793 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14794 if ((regs_ever_live[info->first_gp_reg_save+i]
14795 && (! call_used_regs[info->first_gp_reg_save+i]
14796 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14797 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14798 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14799 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14800 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14802 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14803 GEN_INT (info->gp_save_offset
14806 rtx mem = gen_rtx_MEM (reg_mode, addr);
14808 /* Restore 64-bit quantities for SPE. */
14809 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14811 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14814 if (!SPE_CONST_OFFSET_OK (offset))
14816 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14817 emit_move_insn (b, GEN_INT (offset));
14820 b = GEN_INT (offset);
14822 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14823 mem = gen_rtx_MEM (V2SImode, addr);
14826 set_mem_alias_set (mem, rs6000_sr_alias_set);
14828 emit_move_insn (gen_rtx_REG (reg_mode,
14829 info->first_gp_reg_save + i), mem);
14832 /* Restore fpr's if we need to do it without calling a function. */
14833 if (restoring_FPRs_inline)
14834 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14835 if ((regs_ever_live[info->first_fp_reg_save+i]
14836 && ! call_used_regs[info->first_fp_reg_save+i]))
14839 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14840 GEN_INT (info->fp_save_offset
14843 mem = gen_rtx_MEM (DFmode, addr);
14844 set_mem_alias_set (mem, rs6000_sr_alias_set);
14846 emit_move_insn (gen_rtx_REG (DFmode,
14847 info->first_fp_reg_save + i),
14851 /* If we saved cr, restore it here. Just those that were used. */
14852 if (info->cr_save_p)
14854 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14857 if (using_mfcr_multiple)
14859 for (i = 0; i < 8; i++)
14860 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14866 if (using_mfcr_multiple && count > 1)
14871 p = rtvec_alloc (count);
14874 for (i = 0; i < 8; i++)
14875 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14877 rtvec r = rtvec_alloc (2);
14878 RTVEC_ELT (r, 0) = r12_rtx;
14879 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14880 RTVEC_ELT (p, ndx) =
14881 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14882 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14885 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14890 for (i = 0; i < 8; i++)
14891 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14893 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14899 /* If this is V.4, unwind the stack pointer after all of the loads
14900 have been done. We need to emit a block here so that sched
14901 doesn't decide to move the sp change before the register restores
14902 (which may not have any obvious dependency on the stack). This
14903 doesn't hurt performance, because there is no scheduling that can
14904 be done after this point. */
14905 if (DEFAULT_ABI == ABI_V4
14906 || current_function_calls_eh_return)
14908 if (frame_reg_rtx != sp_reg_rtx)
14909 rs6000_emit_stack_tie ();
14911 if (use_backchain_to_restore_sp)
14913 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14915 else if (sp_offset != 0)
14917 emit_insn (TARGET_32BIT
14918 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14919 GEN_INT (sp_offset))
14920 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14921 GEN_INT (sp_offset)));
14925 if (current_function_calls_eh_return)
14927 rtx sa = EH_RETURN_STACKADJ_RTX;
14928 emit_insn (TARGET_32BIT
14929 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14930 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14936 if (! restoring_FPRs_inline)
14937 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14939 p = rtvec_alloc (2);
14941 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14942 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14943 gen_rtx_REG (Pmode,
14944 LINK_REGISTER_REGNUM));
14946 /* If we have to restore more than two FP registers, branch to the
14947 restore function. It will return to our caller. */
14948 if (! restoring_FPRs_inline)
14952 const char *alloc_rname;
14954 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14955 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14956 alloc_rname = ggc_strdup (rname);
14957 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14958 gen_rtx_SYMBOL_REF (Pmode,
14961 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14964 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14965 GEN_INT (info->fp_save_offset + 8*i));
14966 mem = gen_rtx_MEM (DFmode, addr);
14967 set_mem_alias_set (mem, rs6000_sr_alias_set);
14969 RTVEC_ELT (p, i+3) =
14970 gen_rtx_SET (VOIDmode,
14971 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14976 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14980 /* Write function epilogue. */
14983 rs6000_output_function_epilogue (FILE *file,
14984 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14986 rs6000_stack_t *info = rs6000_stack_info ();
14988 if (! HAVE_epilogue)
14990 rtx insn = get_last_insn ();
14991 /* If the last insn was a BARRIER, we don't have to write anything except
14992 the trace table. */
14993 if (GET_CODE (insn) == NOTE)
14994 insn = prev_nonnote_insn (insn);
14995 if (insn == 0 || GET_CODE (insn) != BARRIER)
14997 /* This is slightly ugly, but at least we don't have two
14998 copies of the epilogue-emitting code. */
15001 /* A NOTE_INSN_DELETED is supposed to be at the start
15002 and end of the "toplevel" insn chain. */
15003 emit_note (NOTE_INSN_DELETED);
15004 rs6000_emit_epilogue (FALSE);
15005 emit_note (NOTE_INSN_DELETED);
15007 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15011 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15013 INSN_ADDRESSES_NEW (insn, addr);
15018 if (TARGET_DEBUG_STACK)
15019 debug_rtx_list (get_insns (), 100);
15020 final (get_insns (), file, FALSE, FALSE);
15026 macho_branch_islands ();
15027 /* Mach-O doesn't support labels at the end of objects, so if
15028 it looks like we might want one, insert a NOP. */
15030 rtx insn = get_last_insn ();
15033 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15034 insn = PREV_INSN (insn);
15038 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15039 fputs ("\tnop\n", file);
15043 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15046 We don't output a traceback table if -finhibit-size-directive was
15047 used. The documentation for -finhibit-size-directive reads
15048 ``don't output a @code{.size} assembler directive, or anything
15049 else that would cause trouble if the function is split in the
15050 middle, and the two halves are placed at locations far apart in
15051 memory.'' The traceback table has this property, since it
15052 includes the offset from the start of the function to the
15053 traceback table itself.
15055 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15056 different traceback table. */
15057 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15058 && rs6000_traceback != traceback_none)
15060 const char *fname = NULL;
15061 const char *language_string = lang_hooks.name;
15062 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15064 int optional_tbtab;
15066 if (rs6000_traceback == traceback_full)
15067 optional_tbtab = 1;
15068 else if (rs6000_traceback == traceback_part)
15069 optional_tbtab = 0;
15071 optional_tbtab = !optimize_size && !TARGET_ELF;
15073 if (optional_tbtab)
15075 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15076 while (*fname == '.') /* V.4 encodes . in the name */
15079 /* Need label immediately before tbtab, so we can compute
15080 its offset from the function start. */
15081 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15082 ASM_OUTPUT_LABEL (file, fname);
15085 /* The .tbtab pseudo-op can only be used for the first eight
15086 expressions, since it can't handle the possibly variable
15087 length fields that follow. However, if you omit the optional
15088 fields, the assembler outputs zeros for all optional fields
15089 anyways, giving each variable length field is minimum length
15090 (as defined in sys/debug.h). Thus we can not use the .tbtab
15091 pseudo-op at all. */
15093 /* An all-zero word flags the start of the tbtab, for debuggers
15094 that have to find it by searching forward from the entry
15095 point or from the current pc. */
15096 fputs ("\t.long 0\n", file);
15098 /* Tbtab format type. Use format type 0. */
15099 fputs ("\t.byte 0,", file);
15101 /* Language type. Unfortunately, there does not seem to be any
15102 official way to discover the language being compiled, so we
15103 use language_string.
15104 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15105 Java is 13. Objective-C is 14. */
15106 if (! strcmp (language_string, "GNU C"))
15108 else if (! strcmp (language_string, "GNU F77")
15109 || ! strcmp (language_string, "GNU F95"))
15111 else if (! strcmp (language_string, "GNU Pascal"))
15113 else if (! strcmp (language_string, "GNU Ada"))
15115 else if (! strcmp (language_string, "GNU C++"))
15117 else if (! strcmp (language_string, "GNU Java"))
15119 else if (! strcmp (language_string, "GNU Objective-C"))
15123 fprintf (file, "%d,", i);
15125 /* 8 single bit fields: global linkage (not set for C extern linkage,
15126 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15127 from start of procedure stored in tbtab, internal function, function
15128 has controlled storage, function has no toc, function uses fp,
15129 function logs/aborts fp operations. */
15130 /* Assume that fp operations are used if any fp reg must be saved. */
15131 fprintf (file, "%d,",
15132 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15134 /* 6 bitfields: function is interrupt handler, name present in
15135 proc table, function calls alloca, on condition directives
15136 (controls stack walks, 3 bits), saves condition reg, saves
15138 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15139 set up as a frame pointer, even when there is no alloca call. */
15140 fprintf (file, "%d,",
15141 ((optional_tbtab << 6)
15142 | ((optional_tbtab & frame_pointer_needed) << 5)
15143 | (info->cr_save_p << 1)
15144 | (info->lr_save_p)));
15146 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15148 fprintf (file, "%d,",
15149 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15151 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15152 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15154 if (optional_tbtab)
15156 /* Compute the parameter info from the function decl argument
15159 int next_parm_info_bit = 31;
15161 for (decl = DECL_ARGUMENTS (current_function_decl);
15162 decl; decl = TREE_CHAIN (decl))
15164 rtx parameter = DECL_INCOMING_RTL (decl);
15165 enum machine_mode mode = GET_MODE (parameter);
15167 if (GET_CODE (parameter) == REG)
15169 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
15175 if (mode == SFmode)
15177 else if (mode == DFmode || mode == TFmode)
15182 /* If only one bit will fit, don't or in this entry. */
15183 if (next_parm_info_bit > 0)
15184 parm_info |= (bits << (next_parm_info_bit - 1));
15185 next_parm_info_bit -= 2;
15189 fixed_parms += ((GET_MODE_SIZE (mode)
15190 + (UNITS_PER_WORD - 1))
15192 next_parm_info_bit -= 1;
15198 /* Number of fixed point parameters. */
15199 /* This is actually the number of words of fixed point parameters; thus
15200 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15201 fprintf (file, "%d,", fixed_parms);
15203 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15205 /* This is actually the number of fp registers that hold parameters;
15206 and thus the maximum value is 13. */
15207 /* Set parameters on stack bit if parameters are not in their original
15208 registers, regardless of whether they are on the stack? Xlc
15209 seems to set the bit when not optimizing. */
15210 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15212 if (! optional_tbtab)
15215 /* Optional fields follow. Some are variable length. */
15217 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15218 11 double float. */
15219 /* There is an entry for each parameter in a register, in the order that
15220 they occur in the parameter list. Any intervening arguments on the
15221 stack are ignored. If the list overflows a long (max possible length
15222 34 bits) then completely leave off all elements that don't fit. */
15223 /* Only emit this long if there was at least one parameter. */
15224 if (fixed_parms || float_parms)
15225 fprintf (file, "\t.long %d\n", parm_info);
15227 /* Offset from start of code to tb table. */
15228 fputs ("\t.long ", file);
15229 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15231 RS6000_OUTPUT_BASENAME (file, fname);
15233 assemble_name (file, fname);
15235 rs6000_output_function_entry (file, fname);
15238 /* Interrupt handler mask. */
15239 /* Omit this long, since we never set the interrupt handler bit
15242 /* Number of CTL (controlled storage) anchors. */
15243 /* Omit this long, since the has_ctl bit is never set above. */
15245 /* Displacement into stack of each CTL anchor. */
15246 /* Omit this list of longs, because there are no CTL anchors. */
15248 /* Length of function name. */
15251 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15253 /* Function name. */
15254 assemble_string (fname, strlen (fname));
15256 /* Register for alloca automatic storage; this is always reg 31.
15257 Only emit this if the alloca bit was set above. */
15258 if (frame_pointer_needed)
15259 fputs ("\t.byte 31\n", file);
15261 fputs ("\t.align 2\n", file);
15265 /* A C compound statement that outputs the assembler code for a thunk
15266 function, used to implement C++ virtual function calls with
15267 multiple inheritance. The thunk acts as a wrapper around a virtual
15268 function, adjusting the implicit object parameter before handing
15269 control off to the real function.
15271 First, emit code to add the integer DELTA to the location that
15272 contains the incoming first argument. Assume that this argument
15273 contains a pointer, and is the one used to pass the `this' pointer
15274 in C++. This is the incoming argument *before* the function
15275 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15276 values of all other incoming arguments.
15278 After the addition, emit code to jump to FUNCTION, which is a
15279 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15280 not touch the return address. Hence returning from FUNCTION will
15281 return to whoever called the current `thunk'.
15283 The effect must be as if FUNCTION had been called directly with the
15284 adjusted first argument. This macro is responsible for emitting
15285 all of the code for a thunk function; output_function_prologue()
15286 and output_function_epilogue() are not invoked.
15288 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15289 been extracted from it.) It might possibly be useful on some
15290 targets, but probably not.
15292 If you do not define this macro, the target-independent code in the
15293 C++ frontend will generate a less efficient heavyweight thunk that
15294 calls FUNCTION instead of jumping to it. The generic approach does
15295 not support varargs. */
15298 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15299 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15302 rtx this, insn, funexp;
15304 reload_completed = 1;
15305 epilogue_completed = 1;
15306 no_new_pseudos = 1;
15307 reset_block_changes ();
15309 /* Mark the end of the (empty) prologue. */
15310 emit_note (NOTE_INSN_PROLOGUE_END);
15312 /* Find the "this" pointer. If the function returns a structure,
15313 the structure return pointer is in r3. */
15314 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15315 this = gen_rtx_REG (Pmode, 4);
15317 this = gen_rtx_REG (Pmode, 3);
15319 /* Apply the constant offset, if required. */
15322 rtx delta_rtx = GEN_INT (delta);
15323 emit_insn (TARGET_32BIT
15324 ? gen_addsi3 (this, this, delta_rtx)
15325 : gen_adddi3 (this, this, delta_rtx));
15328 /* Apply the offset from the vtable, if required. */
15331 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15332 rtx tmp = gen_rtx_REG (Pmode, 12);
15334 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15335 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15337 emit_insn (TARGET_32BIT
15338 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15339 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15340 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15344 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15346 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15348 emit_insn (TARGET_32BIT
15349 ? gen_addsi3 (this, this, tmp)
15350 : gen_adddi3 (this, this, tmp));
15353 /* Generate a tail call to the target function. */
15354 if (!TREE_USED (function))
15356 assemble_external (function);
15357 TREE_USED (function) = 1;
15359 funexp = XEXP (DECL_RTL (function), 0);
15360 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15363 if (MACHOPIC_INDIRECT)
15364 funexp = machopic_indirect_call_target (funexp);
15367 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15368 generate sibcall RTL explicitly to avoid constraint abort. */
15369 insn = emit_call_insn (
15370 gen_rtx_PARALLEL (VOIDmode,
15372 gen_rtx_CALL (VOIDmode,
15373 funexp, const0_rtx),
15374 gen_rtx_USE (VOIDmode, const0_rtx),
15375 gen_rtx_USE (VOIDmode,
15376 gen_rtx_REG (SImode,
15377 LINK_REGISTER_REGNUM)),
15378 gen_rtx_RETURN (VOIDmode))));
15379 SIBLING_CALL_P (insn) = 1;
15382 /* Run just enough of rest_of_compilation to get the insns emitted.
15383 There's not really enough bulk here to make other passes such as
15384 instruction scheduling worth while. Note that use_thunk calls
15385 assemble_start_function and assemble_end_function. */
15386 insn = get_insns ();
15387 insn_locators_initialize ();
15388 shorten_branches (insn);
15389 final_start_function (insn, file, 1);
15390 final (insn, file, 1, 0);
15391 final_end_function ();
15393 reload_completed = 0;
15394 epilogue_completed = 0;
15395 no_new_pseudos = 0;
15398 /* A quick summary of the various types of 'constant-pool tables'
15401 Target Flags Name One table per
15402 AIX (none) AIX TOC object file
15403 AIX -mfull-toc AIX TOC object file
15404 AIX -mminimal-toc AIX minimal TOC translation unit
15405 SVR4/EABI (none) SVR4 SDATA object file
15406 SVR4/EABI -fpic SVR4 pic object file
15407 SVR4/EABI -fPIC SVR4 PIC translation unit
15408 SVR4/EABI -mrelocatable EABI TOC function
15409 SVR4/EABI -maix AIX TOC object file
15410 SVR4/EABI -maix -mminimal-toc
15411 AIX minimal TOC translation unit
15413 Name Reg. Set by entries contains:
15414 made by addrs? fp? sum?
15416 AIX TOC 2 crt0 as Y option option
15417 AIX minimal TOC 30 prolog gcc Y Y option
15418 SVR4 SDATA 13 crt0 gcc N Y N
15419 SVR4 pic 30 prolog ld Y not yet N
15420 SVR4 PIC 30 prolog gcc Y option option
15421 EABI TOC 30 prolog gcc Y option option
15425 /* Hash functions for the hash table. */
15428 rs6000_hash_constant (rtx k)
15430 enum rtx_code code = GET_CODE (k);
15431 enum machine_mode mode = GET_MODE (k);
15432 unsigned result = (code << 3) ^ mode;
15433 const char *format;
15436 format = GET_RTX_FORMAT (code);
15437 flen = strlen (format);
15443 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15446 if (mode != VOIDmode)
15447 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15459 for (; fidx < flen; fidx++)
15460 switch (format[fidx])
15465 const char *str = XSTR (k, fidx);
15466 len = strlen (str);
15467 result = result * 613 + len;
15468 for (i = 0; i < len; i++)
15469 result = result * 613 + (unsigned) str[i];
15474 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15478 result = result * 613 + (unsigned) XINT (k, fidx);
15481 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15482 result = result * 613 + (unsigned) XWINT (k, fidx);
15486 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
15487 result = result * 613 + (unsigned) (XWINT (k, fidx)
15501 toc_hash_function (const void *hash_entry)
15503 const struct toc_hash_struct *thc =
15504 (const struct toc_hash_struct *) hash_entry;
15505 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15508 /* Compare H1 and H2 for equivalence. */
15511 toc_hash_eq (const void *h1, const void *h2)
15513 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15514 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15516 if (((const struct toc_hash_struct *) h1)->key_mode
15517 != ((const struct toc_hash_struct *) h2)->key_mode)
15520 return rtx_equal_p (r1, r2);
15523 /* These are the names given by the C++ front-end to vtables, and
15524 vtable-like objects. Ideally, this logic should not be here;
15525 instead, there should be some programmatic way of inquiring as
15526 to whether or not an object is a vtable. */
15528 #define VTABLE_NAME_P(NAME) \
15529 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15530 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15531 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15532 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15533 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15536 rs6000_output_symbol_ref (FILE *file, rtx x)
15538 /* Currently C++ toc references to vtables can be emitted before it
15539 is decided whether the vtable is public or private. If this is
15540 the case, then the linker will eventually complain that there is
15541 a reference to an unknown section. Thus, for vtables only,
15542 we emit the TOC reference to reference the symbol and not the
15544 const char *name = XSTR (x, 0);
15546 if (VTABLE_NAME_P (name))
15548 RS6000_OUTPUT_BASENAME (file, name);
15551 assemble_name (file, name);
15554 /* Output a TOC entry. We derive the entry name from what is being
15558 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15561 const char *name = buf;
15562 const char *real_name;
15569 /* When the linker won't eliminate them, don't output duplicate
15570 TOC entries (this happens on AIX if there is any kind of TOC,
15571 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15573 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15575 struct toc_hash_struct *h;
15578 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15579 time because GGC is not initialized at that point. */
15580 if (toc_hash_table == NULL)
15581 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15582 toc_hash_eq, NULL);
15584 h = ggc_alloc (sizeof (*h));
15586 h->key_mode = mode;
15587 h->labelno = labelno;
15589 found = htab_find_slot (toc_hash_table, h, 1);
15590 if (*found == NULL)
15592 else /* This is indeed a duplicate.
15593 Set this label equal to that label. */
15595 fputs ("\t.set ", file);
15596 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15597 fprintf (file, "%d,", labelno);
15598 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15599 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15605 /* If we're going to put a double constant in the TOC, make sure it's
15606 aligned properly when strict alignment is on. */
15607 if (GET_CODE (x) == CONST_DOUBLE
15608 && STRICT_ALIGNMENT
15609 && GET_MODE_BITSIZE (mode) >= 64
15610 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15611 ASM_OUTPUT_ALIGN (file, 3);
15614 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15616 /* Handle FP constants specially. Note that if we have a minimal
15617 TOC, things we put here aren't actually in the TOC, so we can allow
15619 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15621 REAL_VALUE_TYPE rv;
15624 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15625 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15629 if (TARGET_MINIMAL_TOC)
15630 fputs (DOUBLE_INT_ASM_OP, file);
15632 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15633 k[0] & 0xffffffff, k[1] & 0xffffffff,
15634 k[2] & 0xffffffff, k[3] & 0xffffffff);
15635 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15636 k[0] & 0xffffffff, k[1] & 0xffffffff,
15637 k[2] & 0xffffffff, k[3] & 0xffffffff);
15642 if (TARGET_MINIMAL_TOC)
15643 fputs ("\t.long ", file);
15645 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15646 k[0] & 0xffffffff, k[1] & 0xffffffff,
15647 k[2] & 0xffffffff, k[3] & 0xffffffff);
15648 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15649 k[0] & 0xffffffff, k[1] & 0xffffffff,
15650 k[2] & 0xffffffff, k[3] & 0xffffffff);
15654 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15656 REAL_VALUE_TYPE rv;
15659 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15660 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15664 if (TARGET_MINIMAL_TOC)
15665 fputs (DOUBLE_INT_ASM_OP, file);
15667 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15668 k[0] & 0xffffffff, k[1] & 0xffffffff);
15669 fprintf (file, "0x%lx%08lx\n",
15670 k[0] & 0xffffffff, k[1] & 0xffffffff);
15675 if (TARGET_MINIMAL_TOC)
15676 fputs ("\t.long ", file);
15678 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15679 k[0] & 0xffffffff, k[1] & 0xffffffff);
15680 fprintf (file, "0x%lx,0x%lx\n",
15681 k[0] & 0xffffffff, k[1] & 0xffffffff);
15685 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15687 REAL_VALUE_TYPE rv;
15690 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15691 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15695 if (TARGET_MINIMAL_TOC)
15696 fputs (DOUBLE_INT_ASM_OP, file);
15698 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15699 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15704 if (TARGET_MINIMAL_TOC)
15705 fputs ("\t.long ", file);
15707 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15708 fprintf (file, "0x%lx\n", l & 0xffffffff);
15712 else if (GET_MODE (x) == VOIDmode
15713 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15715 unsigned HOST_WIDE_INT low;
15716 HOST_WIDE_INT high;
15718 if (GET_CODE (x) == CONST_DOUBLE)
15720 low = CONST_DOUBLE_LOW (x);
15721 high = CONST_DOUBLE_HIGH (x);
15724 #if HOST_BITS_PER_WIDE_INT == 32
15727 high = (low & 0x80000000) ? ~0 : 0;
15731 low = INTVAL (x) & 0xffffffff;
15732 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15736 /* TOC entries are always Pmode-sized, but since this
15737 is a bigendian machine then if we're putting smaller
15738 integer constants in the TOC we have to pad them.
15739 (This is still a win over putting the constants in
15740 a separate constant pool, because then we'd have
15741 to have both a TOC entry _and_ the actual constant.)
15743 For a 32-bit target, CONST_INT values are loaded and shifted
15744 entirely within `low' and can be stored in one TOC entry. */
15746 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
15747 abort ();/* It would be easy to make this work, but it doesn't now. */
15749 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15751 #if HOST_BITS_PER_WIDE_INT == 32
15752 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15753 POINTER_SIZE, &low, &high, 0);
15756 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15757 high = (HOST_WIDE_INT) low >> 32;
15764 if (TARGET_MINIMAL_TOC)
15765 fputs (DOUBLE_INT_ASM_OP, file);
15767 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15768 (long) high & 0xffffffff, (long) low & 0xffffffff);
15769 fprintf (file, "0x%lx%08lx\n",
15770 (long) high & 0xffffffff, (long) low & 0xffffffff);
15775 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15777 if (TARGET_MINIMAL_TOC)
15778 fputs ("\t.long ", file);
15780 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15781 (long) high & 0xffffffff, (long) low & 0xffffffff);
15782 fprintf (file, "0x%lx,0x%lx\n",
15783 (long) high & 0xffffffff, (long) low & 0xffffffff);
15787 if (TARGET_MINIMAL_TOC)
15788 fputs ("\t.long ", file);
15790 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15791 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15797 if (GET_CODE (x) == CONST)
15799 if (GET_CODE (XEXP (x, 0)) != PLUS)
15802 base = XEXP (XEXP (x, 0), 0);
15803 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15806 if (GET_CODE (base) == SYMBOL_REF)
15807 name = XSTR (base, 0);
15808 else if (GET_CODE (base) == LABEL_REF)
15809 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
15810 else if (GET_CODE (base) == CODE_LABEL)
15811 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15815 real_name = (*targetm.strip_name_encoding) (name);
15816 if (TARGET_MINIMAL_TOC)
15817 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15820 fprintf (file, "\t.tc %s", real_name);
15823 fprintf (file, ".N%d", - offset);
15825 fprintf (file, ".P%d", offset);
15827 fputs ("[TC],", file);
15830 /* Currently C++ toc references to vtables can be emitted before it
15831 is decided whether the vtable is public or private. If this is
15832 the case, then the linker will eventually complain that there is
15833 a TOC reference to an unknown section. Thus, for vtables only,
15834 we emit the TOC reference to reference the symbol and not the
15836 if (VTABLE_NAME_P (name))
15838 RS6000_OUTPUT_BASENAME (file, name);
15840 fprintf (file, "%d", offset);
15841 else if (offset > 0)
15842 fprintf (file, "+%d", offset);
15845 output_addr_const (file, x);
15849 /* Output an assembler pseudo-op to write an ASCII string of N characters
15850 starting at P to FILE.
15852 On the RS/6000, we have to do this using the .byte operation and
15853 write out special characters outside the quoted string.
15854 Also, the assembler is broken; very long strings are truncated,
15855 so we must artificially break them up early. */
15858 output_ascii (FILE *file, const char *p, int n)
15861 int i, count_string;
15862 const char *for_string = "\t.byte \"";
15863 const char *for_decimal = "\t.byte ";
15864 const char *to_close = NULL;
15867 for (i = 0; i < n; i++)
15870 if (c >= ' ' && c < 0177)
15873 fputs (for_string, file);
15876 /* Write two quotes to get one. */
15884 for_decimal = "\"\n\t.byte ";
15888 if (count_string >= 512)
15890 fputs (to_close, file);
15892 for_string = "\t.byte \"";
15893 for_decimal = "\t.byte ";
15901 fputs (for_decimal, file);
15902 fprintf (file, "%d", c);
15904 for_string = "\n\t.byte \"";
15905 for_decimal = ", ";
15911 /* Now close the string if we have written one. Then end the line. */
15913 fputs (to_close, file);
15916 /* Generate a unique section name for FILENAME for a section type
15917 represented by SECTION_DESC. Output goes into BUF.
15919 SECTION_DESC can be any string, as long as it is different for each
15920 possible section type.
15922 We name the section in the same manner as xlc. The name begins with an
15923 underscore followed by the filename (after stripping any leading directory
15924 names) with the last period replaced by the string SECTION_DESC. If
15925 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15929 rs6000_gen_section_name (char **buf, const char *filename,
15930 const char *section_desc)
15932 const char *q, *after_last_slash, *last_period = 0;
15936 after_last_slash = filename;
15937 for (q = filename; *q; q++)
15940 after_last_slash = q + 1;
15941 else if (*q == '.')
15945 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15946 *buf = (char *) xmalloc (len);
15951 for (q = after_last_slash; *q; q++)
15953 if (q == last_period)
15955 strcpy (p, section_desc);
15956 p += strlen (section_desc);
15960 else if (ISALNUM (*q))
15964 if (last_period == 0)
15965 strcpy (p, section_desc);
15970 /* Emit profile function. */
15973 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
15975 if (TARGET_PROFILE_KERNEL)
15978 if (DEFAULT_ABI == ABI_AIX)
15980 #ifndef NO_PROFILE_COUNTERS
15981 # define NO_PROFILE_COUNTERS 0
15983 if (NO_PROFILE_COUNTERS)
15984 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15988 const char *label_name;
15991 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15992 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15993 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15995 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15999 else if (DEFAULT_ABI == ABI_DARWIN)
16001 const char *mcount_name = RS6000_MCOUNT;
16002 int caller_addr_regno = LINK_REGISTER_REGNUM;
16004 /* Be conservative and always set this, at least for now. */
16005 current_function_uses_pic_offset_table = 1;
16008 /* For PIC code, set up a stub and collect the caller's address
16009 from r0, which is where the prologue puts it. */
16010 if (MACHOPIC_INDIRECT
16011 && current_function_uses_pic_offset_table)
16012 caller_addr_regno = 0;
16014 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16016 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16020 /* Write function profiler code. */
16023 output_function_profiler (FILE *file, int labelno)
16028 switch (DEFAULT_ABI)
16037 warning ("no profiling of 64-bit code for this ABI");
16040 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16041 fprintf (file, "\tmflr %s\n", reg_names[0]);
16044 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16045 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
16046 reg_names[0], save_lr, reg_names[1]);
16047 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16048 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16049 assemble_name (file, buf);
16050 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16052 else if (flag_pic > 1)
16054 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
16055 reg_names[0], save_lr, reg_names[1]);
16056 /* Now, we need to get the address of the label. */
16057 fputs ("\tbl 1f\n\t.long ", file);
16058 assemble_name (file, buf);
16059 fputs ("-.\n1:", file);
16060 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16061 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16062 reg_names[0], reg_names[11]);
16063 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16064 reg_names[0], reg_names[0], reg_names[11]);
16068 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16069 assemble_name (file, buf);
16070 fputs ("@ha\n", file);
16071 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
16072 reg_names[0], save_lr, reg_names[1]);
16073 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16074 assemble_name (file, buf);
16075 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16078 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16079 fprintf (file, "\tbl %s%s\n",
16080 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16085 if (!TARGET_PROFILE_KERNEL)
16087 /* Don't do anything, done in output_profile_hook (). */
16094 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16095 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16097 if (cfun->static_chain_decl != NULL)
16099 asm_fprintf (file, "\tstd %s,24(%s)\n",
16100 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16101 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16102 asm_fprintf (file, "\tld %s,24(%s)\n",
16103 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16106 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16113 /* Power4 load update and store update instructions are cracked into a
16114 load or store and an integer insn which are executed in the same cycle.
16115 Branches have their own dispatch slot which does not count against the
16116 GCC issue rate, but it changes the program flow so there are no other
16117 instructions to issue in this cycle. */
16120 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16121 int verbose ATTRIBUTE_UNUSED,
16122 rtx insn, int more)
16124 if (GET_CODE (PATTERN (insn)) == USE
16125 || GET_CODE (PATTERN (insn)) == CLOBBER)
16128 if (rs6000_sched_groups)
16130 if (is_microcoded_insn (insn))
16132 else if (is_cracked_insn (insn))
16133 return more > 2 ? more - 2 : 0;
16139 /* Adjust the cost of a scheduling dependency. Return the new cost of
16140 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16143 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16145 if (! recog_memoized (insn))
16148 if (REG_NOTE_KIND (link) != 0)
16151 if (REG_NOTE_KIND (link) == 0)
16153 /* Data dependency; DEP_INSN writes a register that INSN reads
16154 some cycles later. */
16156 /* Separate a load from a narrower, dependent store. */
16157 if (rs6000_sched_groups
16158 && GET_CODE (PATTERN (insn)) == SET
16159 && GET_CODE (PATTERN (dep_insn)) == SET
16160 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16161 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16162 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16163 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16166 switch (get_attr_type (insn))
16169 /* Tell the first scheduling pass about the latency between
16170 a mtctr and bctr (and mtlr and br/blr). The first
16171 scheduling pass will not know about this latency since
16172 the mtctr instruction, which has the latency associated
16173 to it, will be generated by reload. */
16174 return TARGET_POWER ? 5 : 4;
16176 /* Leave some extra cycles between a compare and its
16177 dependent branch, to inhibit expensive mispredicts. */
16178 if ((rs6000_cpu_attr == CPU_PPC603
16179 || rs6000_cpu_attr == CPU_PPC604
16180 || rs6000_cpu_attr == CPU_PPC604E
16181 || rs6000_cpu_attr == CPU_PPC620
16182 || rs6000_cpu_attr == CPU_PPC630
16183 || rs6000_cpu_attr == CPU_PPC750
16184 || rs6000_cpu_attr == CPU_PPC7400
16185 || rs6000_cpu_attr == CPU_PPC7450
16186 || rs6000_cpu_attr == CPU_POWER4
16187 || rs6000_cpu_attr == CPU_POWER5)
16188 && recog_memoized (dep_insn)
16189 && (INSN_CODE (dep_insn) >= 0)
16190 && (get_attr_type (dep_insn) == TYPE_CMP
16191 || get_attr_type (dep_insn) == TYPE_COMPARE
16192 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16193 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16194 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16195 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16196 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16197 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16202 /* Fall out to return default cost. */
16208 /* The function returns a true if INSN is microcoded.
16209 Return false otherwise. */
16212 is_microcoded_insn (rtx insn)
16214 if (!insn || !INSN_P (insn)
16215 || GET_CODE (PATTERN (insn)) == USE
16216 || GET_CODE (PATTERN (insn)) == CLOBBER)
16219 if (rs6000_sched_groups)
16221 enum attr_type type = get_attr_type (insn);
16222 if (type == TYPE_LOAD_EXT_U
16223 || type == TYPE_LOAD_EXT_UX
16224 || type == TYPE_LOAD_UX
16225 || type == TYPE_STORE_UX
16226 || type == TYPE_MFCR)
16233 /* The function returns a nonzero value if INSN can be scheduled only
16234 as the first insn in a dispatch group ("dispatch-slot restricted").
16235 In this case, the returned value indicates how many dispatch slots
16236 the insn occupies (at the beginning of the group).
16237 Return 0 otherwise. */
16240 is_dispatch_slot_restricted (rtx insn)
16242 enum attr_type type;
16244 if (!rs6000_sched_groups)
16248 || insn == NULL_RTX
16249 || GET_CODE (insn) == NOTE
16250 || GET_CODE (PATTERN (insn)) == USE
16251 || GET_CODE (PATTERN (insn)) == CLOBBER)
16254 type = get_attr_type (insn);
16261 case TYPE_DELAYED_CR:
16262 case TYPE_CR_LOGICAL:
16270 if (rs6000_cpu == PROCESSOR_POWER5
16271 && is_cracked_insn (insn))
16277 /* The function returns true if INSN is cracked into 2 instructions
16278 by the processor (and therefore occupies 2 issue slots). */
16281 is_cracked_insn (rtx insn)
16283 if (!insn || !INSN_P (insn)
16284 || GET_CODE (PATTERN (insn)) == USE
16285 || GET_CODE (PATTERN (insn)) == CLOBBER)
16288 if (rs6000_sched_groups)
16290 enum attr_type type = get_attr_type (insn);
16291 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16292 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16293 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16294 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16295 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16296 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16297 || type == TYPE_IDIV || type == TYPE_LDIV
16298 || type == TYPE_INSERT_WORD)
16305 /* The function returns true if INSN can be issued only from
16306 the branch slot. */
16309 is_branch_slot_insn (rtx insn)
16311 if (!insn || !INSN_P (insn)
16312 || GET_CODE (PATTERN (insn)) == USE
16313 || GET_CODE (PATTERN (insn)) == CLOBBER)
16316 if (rs6000_sched_groups)
16318 enum attr_type type = get_attr_type (insn);
16319 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16327 /* A C statement (sans semicolon) to update the integer scheduling
16328 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16329 INSN earlier, reduce the priority to execute INSN later. Do not
16330 define this macro if you do not need to adjust the scheduling
16331 priorities of insns. */
16334 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16336 /* On machines (like the 750) which have asymmetric integer units,
16337 where one integer unit can do multiply and divides and the other
16338 can't, reduce the priority of multiply/divide so it is scheduled
16339 before other integer operations. */
16342 if (! INSN_P (insn))
16345 if (GET_CODE (PATTERN (insn)) == USE)
16348 switch (rs6000_cpu_attr) {
16350 switch (get_attr_type (insn))
16357 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16358 priority, priority);
16359 if (priority >= 0 && priority < 0x01000000)
16366 if (is_dispatch_slot_restricted (insn)
16367 && reload_completed
16368 && current_sched_info->sched_max_insns_priority
16369 && rs6000_sched_restricted_insns_priority)
16372 /* Prioritize insns that can be dispatched only in the first
16374 if (rs6000_sched_restricted_insns_priority == 1)
16375 /* Attach highest priority to insn. This means that in
16376 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16377 precede 'priority' (critical path) considerations. */
16378 return current_sched_info->sched_max_insns_priority;
16379 else if (rs6000_sched_restricted_insns_priority == 2)
16380 /* Increase priority of insn by a minimal amount. This means that in
16381 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16382 considerations precede dispatch-slot restriction considerations. */
16383 return (priority + 1);
16389 /* Return how many instructions the machine can issue per cycle. */
16392 rs6000_issue_rate (void)
16394 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16395 if (!reload_completed)
16398 switch (rs6000_cpu_attr) {
16399 case CPU_RIOS1: /* ? */
16401 case CPU_PPC601: /* ? */
16424 /* Return how many instructions to look ahead for better insn
16428 rs6000_use_sched_lookahead (void)
16430 if (rs6000_cpu_attr == CPU_PPC8540)
16435 /* Determine is PAT refers to memory. */
16438 is_mem_ref (rtx pat)
16444 if (GET_CODE (pat) == MEM)
16447 /* Recursively process the pattern. */
16448 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16450 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16453 ret |= is_mem_ref (XEXP (pat, i));
16454 else if (fmt[i] == 'E')
16455 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16456 ret |= is_mem_ref (XVECEXP (pat, i, j));
16462 /* Determine if PAT is a PATTERN of a load insn. */
16465 is_load_insn1 (rtx pat)
16467 if (!pat || pat == NULL_RTX)
16470 if (GET_CODE (pat) == SET)
16471 return is_mem_ref (SET_SRC (pat));
16473 if (GET_CODE (pat) == PARALLEL)
16477 for (i = 0; i < XVECLEN (pat, 0); i++)
16478 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16485 /* Determine if INSN loads from memory. */
16488 is_load_insn (rtx insn)
16490 if (!insn || !INSN_P (insn))
16493 if (GET_CODE (insn) == CALL_INSN)
16496 return is_load_insn1 (PATTERN (insn));
16499 /* Determine if PAT is a PATTERN of a store insn. */
16502 is_store_insn1 (rtx pat)
16504 if (!pat || pat == NULL_RTX)
16507 if (GET_CODE (pat) == SET)
16508 return is_mem_ref (SET_DEST (pat));
16510 if (GET_CODE (pat) == PARALLEL)
16514 for (i = 0; i < XVECLEN (pat, 0); i++)
16515 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16522 /* Determine if INSN stores to memory. */
16525 is_store_insn (rtx insn)
16527 if (!insn || !INSN_P (insn))
16530 return is_store_insn1 (PATTERN (insn));
16533 /* Returns whether the dependence between INSN and NEXT is considered
16534 costly by the given target. */
16537 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16540 /* If the flag is not enbled - no dependence is considered costly;
16541 allow all dependent insns in the same group.
16542 This is the most aggressive option. */
16543 if (rs6000_sched_costly_dep == no_dep_costly)
16546 /* If the flag is set to 1 - a dependence is always considered costly;
16547 do not allow dependent instructions in the same group.
16548 This is the most conservative option. */
16549 if (rs6000_sched_costly_dep == all_deps_costly)
16552 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16553 && is_load_insn (next)
16554 && is_store_insn (insn))
16555 /* Prevent load after store in the same group. */
16558 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16559 && is_load_insn (next)
16560 && is_store_insn (insn)
16561 && (!link || (int) REG_NOTE_KIND (link) == 0))
16562 /* Prevent load after store in the same group if it is a true
16566 /* The flag is set to X; dependences with latency >= X are considered costly,
16567 and will not be scheduled in the same group. */
16568 if (rs6000_sched_costly_dep <= max_dep_latency
16569 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16575 /* Return the next insn after INSN that is found before TAIL is reached,
16576 skipping any "non-active" insns - insns that will not actually occupy
16577 an issue slot. Return NULL_RTX if such an insn is not found. */
16580 get_next_active_insn (rtx insn, rtx tail)
16584 if (!insn || insn == tail)
16587 next_insn = NEXT_INSN (insn);
16590 && next_insn != tail
16591 && (GET_CODE(next_insn) == NOTE
16592 || GET_CODE (PATTERN (next_insn)) == USE
16593 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16595 next_insn = NEXT_INSN (next_insn);
16598 if (!next_insn || next_insn == tail)
16604 /* Return whether the presence of INSN causes a dispatch group termination
16605 of group WHICH_GROUP.
16607 If WHICH_GROUP == current_group, this function will return true if INSN
16608 causes the termination of the current group (i.e, the dispatch group to
16609 which INSN belongs). This means that INSN will be the last insn in the
16610 group it belongs to.
16612 If WHICH_GROUP == previous_group, this function will return true if INSN
16613 causes the termination of the previous group (i.e, the dispatch group that
16614 precedes the group to which INSN belongs). This means that INSN will be
16615 the first insn in the group it belongs to). */
16618 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16620 enum attr_type type;
16625 type = get_attr_type (insn);
16627 if (is_microcoded_insn (insn))
16630 if (which_group == current_group)
16632 if (is_branch_slot_insn (insn))
16636 else if (which_group == previous_group)
16638 if (is_dispatch_slot_restricted (insn))
16646 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16647 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16650 is_costly_group (rtx *group_insns, rtx next_insn)
16655 int issue_rate = rs6000_issue_rate ();
16657 for (i = 0; i < issue_rate; i++)
16659 rtx insn = group_insns[i];
16662 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16664 rtx next = XEXP (link, 0);
16665 if (next == next_insn)
16667 cost = insn_cost (insn, link, next_insn);
16668 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16677 /* Utility of the function redefine_groups.
16678 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16679 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16680 to keep it "far" (in a separate group) from GROUP_INSNS, following
16681 one of the following schemes, depending on the value of the flag
16682 -minsert_sched_nops = X:
16683 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16684 in order to force NEXT_INSN into a separate group.
16685 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16686 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16687 insertion (has a group just ended, how many vacant issue slots remain in the
16688 last group, and how many dispatch groups were encountered so far). */
16691 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16692 rtx next_insn, bool *group_end, int can_issue_more,
16697 int issue_rate = rs6000_issue_rate ();
16698 bool end = *group_end;
16701 if (next_insn == NULL_RTX)
16702 return can_issue_more;
16704 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16705 return can_issue_more;
16707 force = is_costly_group (group_insns, next_insn);
16709 return can_issue_more;
16711 if (sched_verbose > 6)
16712 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16713 *group_count ,can_issue_more);
16715 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16718 can_issue_more = 0;
16720 /* Since only a branch can be issued in the last issue_slot, it is
16721 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16722 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16723 in this case the last nop will start a new group and the branch
16724 will be forced to the new group. */
16725 if (can_issue_more && !is_branch_slot_insn (next_insn))
16728 while (can_issue_more > 0)
16731 emit_insn_before (nop, next_insn);
16739 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16741 int n_nops = rs6000_sched_insert_nops;
16743 /* Nops can't be issued from the branch slot, so the effective
16744 issue_rate for nops is 'issue_rate - 1'. */
16745 if (can_issue_more == 0)
16746 can_issue_more = issue_rate;
16748 if (can_issue_more == 0)
16750 can_issue_more = issue_rate - 1;
16753 for (i = 0; i < issue_rate; i++)
16755 group_insns[i] = 0;
16762 emit_insn_before (nop, next_insn);
16763 if (can_issue_more == issue_rate - 1) /* new group begins */
16766 if (can_issue_more == 0)
16768 can_issue_more = issue_rate - 1;
16771 for (i = 0; i < issue_rate; i++)
16773 group_insns[i] = 0;
16779 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16782 /* Is next_insn going to start a new group? */
16785 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16786 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16787 || (can_issue_more < issue_rate &&
16788 insn_terminates_group_p (next_insn, previous_group)));
16789 if (*group_end && end)
16792 if (sched_verbose > 6)
16793 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16794 *group_count, can_issue_more);
16795 return can_issue_more;
16798 return can_issue_more;
16801 /* This function tries to synch the dispatch groups that the compiler "sees"
16802 with the dispatch groups that the processor dispatcher is expected to
16803 form in practice. It tries to achieve this synchronization by forcing the
16804 estimated processor grouping on the compiler (as opposed to the function
16805 'pad_goups' which tries to force the scheduler's grouping on the processor).
16807 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16808 examines the (estimated) dispatch groups that will be formed by the processor
16809 dispatcher. It marks these group boundaries to reflect the estimated
16810 processor grouping, overriding the grouping that the scheduler had marked.
16811 Depending on the value of the flag '-minsert-sched-nops' this function can
16812 force certain insns into separate groups or force a certain distance between
16813 them by inserting nops, for example, if there exists a "costly dependence"
16816 The function estimates the group boundaries that the processor will form as
16817 folllows: It keeps track of how many vacant issue slots are available after
16818 each insn. A subsequent insn will start a new group if one of the following
16820 - no more vacant issue slots remain in the current dispatch group.
16821 - only the last issue slot, which is the branch slot, is vacant, but the next
16822 insn is not a branch.
16823 - only the last 2 or less issue slots, including the branch slot, are vacant,
16824 which means that a cracked insn (which occupies two issue slots) can't be
16825 issued in this group.
16826 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16827 start a new group. */
16830 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16832 rtx insn, next_insn;
16834 int can_issue_more;
16837 int group_count = 0;
16841 issue_rate = rs6000_issue_rate ();
16842 group_insns = alloca (issue_rate * sizeof (rtx));
16843 for (i = 0; i < issue_rate; i++)
16845 group_insns[i] = 0;
16847 can_issue_more = issue_rate;
16849 insn = get_next_active_insn (prev_head_insn, tail);
16852 while (insn != NULL_RTX)
16854 slot = (issue_rate - can_issue_more);
16855 group_insns[slot] = insn;
16857 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16858 if (insn_terminates_group_p (insn, current_group))
16859 can_issue_more = 0;
16861 next_insn = get_next_active_insn (insn, tail);
16862 if (next_insn == NULL_RTX)
16863 return group_count + 1;
16865 /* Is next_insn going to start a new group? */
16867 = (can_issue_more == 0
16868 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16869 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16870 || (can_issue_more < issue_rate &&
16871 insn_terminates_group_p (next_insn, previous_group)));
16873 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16874 next_insn, &group_end, can_issue_more,
16880 can_issue_more = 0;
16881 for (i = 0; i < issue_rate; i++)
16883 group_insns[i] = 0;
16887 if (GET_MODE (next_insn) == TImode && can_issue_more)
16888 PUT_MODE(next_insn, VOIDmode);
16889 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16890 PUT_MODE (next_insn, TImode);
16893 if (can_issue_more == 0)
16894 can_issue_more = issue_rate;
16897 return group_count;
16900 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16901 dispatch group boundaries that the scheduler had marked. Pad with nops
16902 any dispatch groups which have vacant issue slots, in order to force the
16903 scheduler's grouping on the processor dispatcher. The function
16904 returns the number of dispatch groups found. */
16907 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16909 rtx insn, next_insn;
16912 int can_issue_more;
16914 int group_count = 0;
16916 /* Initialize issue_rate. */
16917 issue_rate = rs6000_issue_rate ();
16918 can_issue_more = issue_rate;
16920 insn = get_next_active_insn (prev_head_insn, tail);
16921 next_insn = get_next_active_insn (insn, tail);
16923 while (insn != NULL_RTX)
16926 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16928 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16930 if (next_insn == NULL_RTX)
16935 /* If the scheduler had marked group termination at this location
16936 (between insn and next_indn), and neither insn nor next_insn will
16937 force group termination, pad the group with nops to force group
16940 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16941 && !insn_terminates_group_p (insn, current_group)
16942 && !insn_terminates_group_p (next_insn, previous_group))
16944 if (!is_branch_slot_insn(next_insn))
16947 while (can_issue_more)
16950 emit_insn_before (nop, next_insn);
16955 can_issue_more = issue_rate;
16960 next_insn = get_next_active_insn (insn, tail);
16963 return group_count;
16966 /* The following function is called at the end of scheduling BB.
16967 After reload, it inserts nops at insn group bundling. */
16970 rs6000_sched_finish (FILE *dump, int sched_verbose)
16975 fprintf (dump, "=== Finishing schedule.\n");
16977 if (reload_completed && rs6000_sched_groups)
16979 if (rs6000_sched_insert_nops == sched_finish_none)
16982 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
16983 n_groups = pad_groups (dump, sched_verbose,
16984 current_sched_info->prev_head,
16985 current_sched_info->next_tail);
16987 n_groups = redefine_groups (dump, sched_verbose,
16988 current_sched_info->prev_head,
16989 current_sched_info->next_tail);
16991 if (sched_verbose >= 6)
16993 fprintf (dump, "ngroups = %d\n", n_groups);
16994 print_rtl (dump, current_sched_info->prev_head);
16995 fprintf (dump, "Done finish_sched\n");
17000 /* Length in units of the trampoline for entering a nested function. */
17003 rs6000_trampoline_size (void)
17007 switch (DEFAULT_ABI)
17013 ret = (TARGET_32BIT) ? 12 : 24;
17018 ret = (TARGET_32BIT) ? 40 : 48;
17025 /* Emit RTL insns to initialize the variable parts of a trampoline.
17026 FNADDR is an RTX for the address of the function's pure code.
17027 CXT is an RTX for the static chain value for the function. */
17030 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17032 enum machine_mode pmode = Pmode;
17033 int regsize = (TARGET_32BIT) ? 4 : 8;
17034 rtx ctx_reg = force_reg (pmode, cxt);
17036 switch (DEFAULT_ABI)
17041 /* Macros to shorten the code expansions below. */
17042 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17043 #define MEM_PLUS(addr,offset) \
17044 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17046 /* Under AIX, just build the 3 word function descriptor */
17049 rtx fn_reg = gen_reg_rtx (pmode);
17050 rtx toc_reg = gen_reg_rtx (pmode);
17051 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17052 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17053 emit_move_insn (MEM_DEREF (addr), fn_reg);
17054 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17055 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17059 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17062 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17063 FALSE, VOIDmode, 4,
17065 GEN_INT (rs6000_trampoline_size ()), SImode,
17075 /* Table of valid machine attributes. */
17077 const struct attribute_spec rs6000_attribute_table[] =
17079 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17080 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17081 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17082 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17083 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17084 SUBTARGET_ATTRIBUTE_TABLE,
17086 { NULL, 0, 0, false, false, false, NULL }
17089 /* Handle the "altivec" attribute. The attribute may have
17090 arguments as follows:
17092 __attribute__((altivec(vector__)))
17093 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17094 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17096 and may appear more than once (e.g., 'vector bool char') in a
17097 given declaration. */
17100 rs6000_handle_altivec_attribute (tree *node,
17101 tree name ATTRIBUTE_UNUSED,
17103 int flags ATTRIBUTE_UNUSED,
17104 bool *no_add_attrs)
17106 tree type = *node, result = NULL_TREE;
17107 enum machine_mode mode;
17110 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17111 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17112 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17115 while (POINTER_TYPE_P (type)
17116 || TREE_CODE (type) == FUNCTION_TYPE
17117 || TREE_CODE (type) == METHOD_TYPE
17118 || TREE_CODE (type) == ARRAY_TYPE)
17119 type = TREE_TYPE (type);
17121 mode = TYPE_MODE (type);
17123 /* Check for invalid AltiVec type qualifiers. */
17124 if (type == long_unsigned_type_node || type == long_integer_type_node)
17127 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17128 else if (rs6000_warn_altivec_long)
17129 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
17131 else if (type == long_long_unsigned_type_node
17132 || type == long_long_integer_type_node)
17133 error ("use of %<long long%> in AltiVec types is invalid");
17134 else if (type == double_type_node)
17135 error ("use of %<double%> in AltiVec types is invalid");
17136 else if (type == long_double_type_node)
17137 error ("use of %<long double%> in AltiVec types is invalid");
17138 else if (type == boolean_type_node)
17139 error ("use of boolean types in AltiVec types is invalid");
17140 else if (TREE_CODE (type) == COMPLEX_TYPE)
17141 error ("use of %<complex%> in AltiVec types is invalid");
17143 switch (altivec_type)
17146 unsigned_p = TYPE_UNSIGNED (type);
17150 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17153 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17156 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17158 case SFmode: result = V4SF_type_node; break;
17159 /* If the user says 'vector int bool', we may be handed the 'bool'
17160 attribute _before_ the 'vector' attribute, and so select the
17161 proper type in the 'b' case below. */
17162 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17170 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17171 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17172 case QImode: case V16QImode: result = bool_V16QI_type_node;
17179 case V8HImode: result = pixel_V8HI_type_node;
17185 if (result && result != type && TYPE_READONLY (type))
17186 result = build_qualified_type (result, TYPE_QUAL_CONST);
17188 *no_add_attrs = true; /* No need to hang on to the attribute. */
17191 *node = reconstruct_complex_type (*node, result);
17196 /* AltiVec defines four built-in scalar types that serve as vector
17197 elements; we must teach the compiler how to mangle them. */
17199 static const char *
17200 rs6000_mangle_fundamental_type (tree type)
17202 if (type == bool_char_type_node) return "U6__boolc";
17203 if (type == bool_short_type_node) return "U6__bools";
17204 if (type == pixel_type_node) return "u7__pixel";
17205 if (type == bool_int_type_node) return "U6__booli";
17207 /* For all other types, use normal C++ mangling. */
17211 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17212 struct attribute_spec.handler. */
17215 rs6000_handle_longcall_attribute (tree *node, tree name,
17216 tree args ATTRIBUTE_UNUSED,
17217 int flags ATTRIBUTE_UNUSED,
17218 bool *no_add_attrs)
17220 if (TREE_CODE (*node) != FUNCTION_TYPE
17221 && TREE_CODE (*node) != FIELD_DECL
17222 && TREE_CODE (*node) != TYPE_DECL)
17224 warning ("%qs attribute only applies to functions",
17225 IDENTIFIER_POINTER (name));
17226 *no_add_attrs = true;
17232 /* Set longcall attributes on all functions declared when
17233 rs6000_default_long_calls is true. */
17235 rs6000_set_default_type_attributes (tree type)
17237 if (rs6000_default_long_calls
17238 && (TREE_CODE (type) == FUNCTION_TYPE
17239 || TREE_CODE (type) == METHOD_TYPE))
17240 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17242 TYPE_ATTRIBUTES (type));
17245 /* Return a reference suitable for calling a function with the
17246 longcall attribute. */
17249 rs6000_longcall_ref (rtx call_ref)
17251 const char *call_name;
17254 if (GET_CODE (call_ref) != SYMBOL_REF)
17257 /* System V adds '.' to the internal name, so skip them. */
17258 call_name = XSTR (call_ref, 0);
17259 if (*call_name == '.')
17261 while (*call_name == '.')
17264 node = get_identifier (call_name);
17265 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17268 return force_reg (Pmode, call_ref);
17271 #ifdef USING_ELFOS_H
17273 /* A C statement or statements to switch to the appropriate section
17274 for output of RTX in mode MODE. You can assume that RTX is some
17275 kind of constant in RTL. The argument MODE is redundant except in
17276 the case of a `const_int' rtx. Select the section by calling
17277 `text_section' or one of the alternatives for other sections.
17279 Do not define this macro if you put all constants in the read-only
17283 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17284 unsigned HOST_WIDE_INT align)
17286 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17289 default_elf_select_rtx_section (mode, x, align);
17292 /* A C statement or statements to switch to the appropriate
17293 section for output of DECL. DECL is either a `VAR_DECL' node
17294 or a constant of some sort. RELOC indicates whether forming
17295 the initial value of DECL requires link-time relocations. */
17298 rs6000_elf_select_section (tree decl, int reloc,
17299 unsigned HOST_WIDE_INT align)
17301 /* Pretend that we're always building for a shared library when
17302 ABI_AIX, because otherwise we end up with dynamic relocations
17303 in read-only sections. This happens for function pointers,
17304 references to vtables in typeinfo, and probably other cases. */
17305 default_elf_select_section_1 (decl, reloc, align,
17306 flag_pic || DEFAULT_ABI == ABI_AIX);
17309 /* A C statement to build up a unique section name, expressed as a
17310 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17311 RELOC indicates whether the initial value of EXP requires
17312 link-time relocations. If you do not define this macro, GCC will use
17313 the symbol name prefixed by `.' as the section name. Note - this
17314 macro can now be called for uninitialized data items as well as
17315 initialized data and functions. */
17318 rs6000_elf_unique_section (tree decl, int reloc)
17320 /* As above, pretend that we're always building for a shared library
17321 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17322 default_unique_section_1 (decl, reloc,
17323 flag_pic || DEFAULT_ABI == ABI_AIX);
17326 /* For a SYMBOL_REF, set generic flags and then perform some
17327 target-specific processing.
17329 When the AIX ABI is requested on a non-AIX system, replace the
17330 function name with the real name (with a leading .) rather than the
17331 function descriptor name. This saves a lot of overriding code to
17332 read the prefixes. */
17335 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17337 default_encode_section_info (decl, rtl, first);
17340 && TREE_CODE (decl) == FUNCTION_DECL
17342 && DEFAULT_ABI == ABI_AIX)
17344 rtx sym_ref = XEXP (rtl, 0);
17345 size_t len = strlen (XSTR (sym_ref, 0));
17346 char *str = alloca (len + 2);
17348 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17349 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17354 rs6000_elf_in_small_data_p (tree decl)
17356 if (rs6000_sdata == SDATA_NONE)
17359 /* We want to merge strings, so we never consider them small data. */
17360 if (TREE_CODE (decl) == STRING_CST)
17363 /* Functions are never in the small data area. */
17364 if (TREE_CODE (decl) == FUNCTION_DECL)
17367 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17369 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17370 if (strcmp (section, ".sdata") == 0
17371 || strcmp (section, ".sdata2") == 0
17372 || strcmp (section, ".sbss") == 0
17373 || strcmp (section, ".sbss2") == 0
17374 || strcmp (section, ".PPC.EMB.sdata0") == 0
17375 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17380 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17383 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17384 /* If it's not public, and we're not going to reference it there,
17385 there's no need to put it in the small data section. */
17386 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17393 #endif /* USING_ELFOS_H */
17396 /* Return a REG that occurs in ADDR with coefficient 1.
17397 ADDR can be effectively incremented by incrementing REG.
17399 r0 is special and we must not select it as an address
17400 register by this routine since our caller will try to
17401 increment the returned register via an "la" instruction. */
17404 find_addr_reg (rtx addr)
17406 while (GET_CODE (addr) == PLUS)
17408 if (GET_CODE (XEXP (addr, 0)) == REG
17409 && REGNO (XEXP (addr, 0)) != 0)
17410 addr = XEXP (addr, 0);
17411 else if (GET_CODE (XEXP (addr, 1)) == REG
17412 && REGNO (XEXP (addr, 1)) != 0)
17413 addr = XEXP (addr, 1);
17414 else if (CONSTANT_P (XEXP (addr, 0)))
17415 addr = XEXP (addr, 1);
17416 else if (CONSTANT_P (XEXP (addr, 1)))
17417 addr = XEXP (addr, 0);
17421 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
17427 rs6000_fatal_bad_address (rtx op)
17429 fatal_insn ("bad address", op);
17434 static tree branch_island_list = 0;
17436 /* Remember to generate a branch island for far calls to the given
17440 add_compiler_branch_island (tree label_name, tree function_name,
17443 tree branch_island = build_tree_list (function_name, label_name);
17444 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17445 TREE_CHAIN (branch_island) = branch_island_list;
17446 branch_island_list = branch_island;
17449 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17450 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17451 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17452 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17454 /* Generate far-jump branch islands for everything on the
17455 branch_island_list. Invoked immediately after the last instruction
17456 of the epilogue has been emitted; the branch-islands must be
17457 appended to, and contiguous with, the function body. Mach-O stubs
17458 are generated in machopic_output_stub(). */
17461 macho_branch_islands (void)
17464 tree branch_island;
17466 for (branch_island = branch_island_list;
17468 branch_island = TREE_CHAIN (branch_island))
17470 const char *label =
17471 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17473 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17474 char name_buf[512];
17475 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17476 if (name[0] == '*' || name[0] == '&')
17477 strcpy (name_buf, name+1);
17481 strcpy (name_buf+1, name);
17483 strcpy (tmp_buf, "\n");
17484 strcat (tmp_buf, label);
17485 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17486 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17487 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17488 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17491 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17492 strcat (tmp_buf, label);
17493 strcat (tmp_buf, "_pic\n");
17494 strcat (tmp_buf, label);
17495 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17497 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17498 strcat (tmp_buf, name_buf);
17499 strcat (tmp_buf, " - ");
17500 strcat (tmp_buf, label);
17501 strcat (tmp_buf, "_pic)\n");
17503 strcat (tmp_buf, "\tmtlr r0\n");
17505 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17506 strcat (tmp_buf, name_buf);
17507 strcat (tmp_buf, " - ");
17508 strcat (tmp_buf, label);
17509 strcat (tmp_buf, "_pic)\n");
17511 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17515 strcat (tmp_buf, ":\nlis r12,hi16(");
17516 strcat (tmp_buf, name_buf);
17517 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17518 strcat (tmp_buf, name_buf);
17519 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17521 output_asm_insn (tmp_buf, 0);
17522 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17523 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17524 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17525 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17528 branch_island_list = 0;
17531 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17532 already there or not. */
17535 no_previous_def (tree function_name)
17537 tree branch_island;
17538 for (branch_island = branch_island_list;
17540 branch_island = TREE_CHAIN (branch_island))
17541 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17546 /* GET_PREV_LABEL gets the label name from the previous definition of
17550 get_prev_label (tree function_name)
17552 tree branch_island;
17553 for (branch_island = branch_island_list;
17555 branch_island = TREE_CHAIN (branch_island))
17556 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17557 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17561 /* INSN is either a function call or a millicode call. It may have an
17562 unconditional jump in its delay slot.
17564 CALL_DEST is the routine we are calling. */
17567 output_call (rtx insn, rtx *operands, int dest_operand_number,
17568 int cookie_operand_number)
17570 static char buf[256];
17571 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17572 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17575 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17577 if (no_previous_def (funname))
17579 int line_number = 0;
17580 rtx label_rtx = gen_label_rtx ();
17581 char *label_buf, temp_buf[256];
17582 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17583 CODE_LABEL_NUMBER (label_rtx));
17584 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17585 labelname = get_identifier (label_buf);
17586 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17588 line_number = NOTE_LINE_NUMBER (insn);
17589 add_compiler_branch_island (labelname, funname, line_number);
17592 labelname = get_prev_label (funname);
17594 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17595 instruction will reach 'foo', otherwise link as 'bl L42'".
17596 "L42" should be a 'branch island', that will do a far jump to
17597 'foo'. Branch islands are generated in
17598 macho_branch_islands(). */
17599 sprintf (buf, "jbsr %%z%d,%.246s",
17600 dest_operand_number, IDENTIFIER_POINTER (labelname));
17603 sprintf (buf, "bl %%z%d", dest_operand_number);
17607 /* Generate PIC and indirect symbol stubs. */
17610 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17612 unsigned int length;
17613 char *symbol_name, *lazy_ptr_name;
17614 char *local_label_0;
17615 static int label = 0;
17617 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17618 symb = (*targetm.strip_name_encoding) (symb);
17621 length = strlen (symb);
17622 symbol_name = alloca (length + 32);
17623 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17625 lazy_ptr_name = alloca (length + 32);
17626 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17629 machopic_picsymbol_stub1_section ();
17631 machopic_symbol_stub1_section ();
17635 fprintf (file, "\t.align 5\n");
17637 fprintf (file, "%s:\n", stub);
17638 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17641 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
17642 sprintf (local_label_0, "\"L%011d$spb\"", label);
17644 fprintf (file, "\tmflr r0\n");
17645 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17646 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17647 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17648 lazy_ptr_name, local_label_0);
17649 fprintf (file, "\tmtlr r0\n");
17650 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17651 (TARGET_64BIT ? "ldu" : "lwzu"),
17652 lazy_ptr_name, local_label_0);
17653 fprintf (file, "\tmtctr r12\n");
17654 fprintf (file, "\tbctr\n");
17658 fprintf (file, "\t.align 4\n");
17660 fprintf (file, "%s:\n", stub);
17661 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17663 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17664 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17665 (TARGET_64BIT ? "ldu" : "lwzu"),
17667 fprintf (file, "\tmtctr r12\n");
17668 fprintf (file, "\tbctr\n");
17671 machopic_lazy_symbol_ptr_section ();
17672 fprintf (file, "%s:\n", lazy_ptr_name);
17673 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17674 fprintf (file, "%sdyld_stub_binding_helper\n",
17675 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17678 /* Legitimize PIC addresses. If the address is already
17679 position-independent, we return ORIG. Newly generated
17680 position-independent addresses go into a reg. This is REG if non
17681 zero, otherwise we allocate register(s) as necessary. */
17683 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17686 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17691 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17692 reg = gen_reg_rtx (Pmode);
17694 if (GET_CODE (orig) == CONST)
17696 if (GET_CODE (XEXP (orig, 0)) == PLUS
17697 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17700 if (GET_CODE (XEXP (orig, 0)) == PLUS)
17702 /* Use a different reg for the intermediate value, as
17703 it will be marked UNCHANGING. */
17704 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17707 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17710 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17716 if (GET_CODE (offset) == CONST_INT)
17718 if (SMALL_INT (offset))
17719 return plus_constant (base, INTVAL (offset));
17720 else if (! reload_in_progress && ! reload_completed)
17721 offset = force_reg (Pmode, offset);
17724 rtx mem = force_const_mem (Pmode, orig);
17725 return machopic_legitimize_pic_address (mem, Pmode, reg);
17728 return gen_rtx_PLUS (Pmode, base, offset);
17731 /* Fall back on generic machopic code. */
17732 return machopic_legitimize_pic_address (orig, mode, reg);
17735 /* This is just a placeholder to make linking work without having to
17736 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17737 ever needed for Darwin (not too likely!) this would have to get a
17738 real definition. */
17745 /* Output a .machine directive for the Darwin assembler, and call
17746 the generic start_file routine. */
17749 rs6000_darwin_file_start (void)
17751 static const struct
17757 { "ppc64", "ppc64", MASK_64BIT },
17758 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17759 { "power4", "ppc970", 0 },
17760 { "G5", "ppc970", 0 },
17761 { "7450", "ppc7450", 0 },
17762 { "7400", "ppc7400", MASK_ALTIVEC },
17763 { "G4", "ppc7400", 0 },
17764 { "750", "ppc750", 0 },
17765 { "740", "ppc750", 0 },
17766 { "G3", "ppc750", 0 },
17767 { "604e", "ppc604e", 0 },
17768 { "604", "ppc604", 0 },
17769 { "603e", "ppc603", 0 },
17770 { "603", "ppc603", 0 },
17771 { "601", "ppc601", 0 },
17772 { NULL, "ppc", 0 } };
17773 const char *cpu_id = "";
17776 rs6000_file_start();
17778 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17779 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17780 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17781 && rs6000_select[i].string[0] != '\0')
17782 cpu_id = rs6000_select[i].string;
17784 /* Look through the mapping array. Pick the first name that either
17785 matches the argument, has a bit set in IF_SET that is also set
17786 in the target flags, or has a NULL name. */
17789 while (mapping[i].arg != NULL
17790 && strcmp (mapping[i].arg, cpu_id) != 0
17791 && (mapping[i].if_set & target_flags) == 0)
17794 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17797 #endif /* TARGET_MACHO */
17800 static unsigned int
17801 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17803 return default_section_type_flags_1 (decl, name, reloc,
17804 flag_pic || DEFAULT_ABI == ABI_AIX);
17807 /* Record an element in the table of global constructors. SYMBOL is
17808 a SYMBOL_REF of the function to be called; PRIORITY is a number
17809 between 0 and MAX_INIT_PRIORITY.
17811 This differs from default_named_section_asm_out_constructor in
17812 that we have special handling for -mrelocatable. */
17815 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17817 const char *section = ".ctors";
17820 if (priority != DEFAULT_INIT_PRIORITY)
17822 sprintf (buf, ".ctors.%.5u",
17823 /* Invert the numbering so the linker puts us in the proper
17824 order; constructors are run from right to left, and the
17825 linker sorts in increasing order. */
17826 MAX_INIT_PRIORITY - priority);
17830 named_section_flags (section, SECTION_WRITE);
17831 assemble_align (POINTER_SIZE);
17833 if (TARGET_RELOCATABLE)
17835 fputs ("\t.long (", asm_out_file);
17836 output_addr_const (asm_out_file, symbol);
17837 fputs (")@fixup\n", asm_out_file);
17840 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17844 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17846 const char *section = ".dtors";
17849 if (priority != DEFAULT_INIT_PRIORITY)
17851 sprintf (buf, ".dtors.%.5u",
17852 /* Invert the numbering so the linker puts us in the proper
17853 order; constructors are run from right to left, and the
17854 linker sorts in increasing order. */
17855 MAX_INIT_PRIORITY - priority);
17859 named_section_flags (section, SECTION_WRITE);
17860 assemble_align (POINTER_SIZE);
17862 if (TARGET_RELOCATABLE)
17864 fputs ("\t.long (", asm_out_file);
17865 output_addr_const (asm_out_file, symbol);
17866 fputs (")@fixup\n", asm_out_file);
17869 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17873 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17877 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17878 ASM_OUTPUT_LABEL (file, name);
17879 fputs (DOUBLE_INT_ASM_OP, file);
17880 rs6000_output_function_entry (file, name);
17881 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17884 fputs ("\t.size\t", file);
17885 assemble_name (file, name);
17886 fputs (",24\n\t.type\t.", file);
17887 assemble_name (file, name);
17888 fputs (",@function\n", file);
17889 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17891 fputs ("\t.globl\t.", file);
17892 assemble_name (file, name);
17897 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17898 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17899 rs6000_output_function_entry (file, name);
17900 fputs (":\n", file);
17904 if (TARGET_RELOCATABLE
17905 && (get_pool_size () != 0 || current_function_profile)
17910 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17912 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17913 fprintf (file, "\t.long ");
17914 assemble_name (file, buf);
17916 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17917 assemble_name (file, buf);
17921 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17922 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17924 if (DEFAULT_ABI == ABI_AIX)
17926 const char *desc_name, *orig_name;
17928 orig_name = (*targetm.strip_name_encoding) (name);
17929 desc_name = orig_name;
17930 while (*desc_name == '.')
17933 if (TREE_PUBLIC (decl))
17934 fprintf (file, "\t.globl %s\n", desc_name);
17936 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17937 fprintf (file, "%s:\n", desc_name);
17938 fprintf (file, "\t.long %s\n", orig_name);
17939 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17940 if (DEFAULT_ABI == ABI_AIX)
17941 fputs ("\t.long 0\n", file);
17942 fprintf (file, "\t.previous\n");
17944 ASM_OUTPUT_LABEL (file, name);
17950 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
17952 fputs (GLOBAL_ASM_OP, stream);
17953 RS6000_OUTPUT_BASENAME (stream, name);
17954 putc ('\n', stream);
17958 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17959 tree decl ATTRIBUTE_UNUSED)
17962 static const char * const suffix[3] = { "PR", "RO", "RW" };
17964 if (flags & SECTION_CODE)
17966 else if (flags & SECTION_WRITE)
17971 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
17972 (flags & SECTION_CODE) ? "." : "",
17973 name, suffix[smclass], flags & SECTION_ENTSIZE);
17977 rs6000_xcoff_select_section (tree decl, int reloc,
17978 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17980 if (decl_readonly_section_1 (decl, reloc, 1))
17982 if (TREE_PUBLIC (decl))
17983 read_only_data_section ();
17985 read_only_private_data_section ();
17989 if (TREE_PUBLIC (decl))
17992 private_data_section ();
17997 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18001 /* Use select_section for private and uninitialized data. */
18002 if (!TREE_PUBLIC (decl)
18003 || DECL_COMMON (decl)
18004 || DECL_INITIAL (decl) == NULL_TREE
18005 || DECL_INITIAL (decl) == error_mark_node
18006 || (flag_zero_initialized_in_bss
18007 && initializer_zerop (DECL_INITIAL (decl))))
18010 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18011 name = (*targetm.strip_name_encoding) (name);
18012 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18015 /* Select section for constant in constant pool.
18017 On RS/6000, all constants are in the private read-only data area.
18018 However, if this is being placed in the TOC it must be output as a
18022 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18023 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18025 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18028 read_only_private_data_section ();
18031 /* Remove any trailing [DS] or the like from the symbol name. */
18033 static const char *
18034 rs6000_xcoff_strip_name_encoding (const char *name)
18039 len = strlen (name);
18040 if (name[len - 1] == ']')
18041 return ggc_alloc_string (name, len - 4);
18046 /* Section attributes. AIX is always PIC. */
18048 static unsigned int
18049 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18051 unsigned int align;
18052 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18054 /* Align to at least UNIT size. */
18055 if (flags & SECTION_CODE)
18056 align = MIN_UNITS_PER_WORD;
18058 /* Increase alignment of large objects if not already stricter. */
18059 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18060 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18061 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18063 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18066 /* Output at beginning of assembler file.
18068 Initialize the section names for the RS/6000 at this point.
18070 Specify filename, including full path, to assembler.
18072 We want to go into the TOC section so at least one .toc will be emitted.
18073 Also, in order to output proper .bs/.es pairs, we need at least one static
18074 [RW] section emitted.
18076 Finally, declare mcount when profiling to make the assembler happy. */
18079 rs6000_xcoff_file_start (void)
18081 rs6000_gen_section_name (&xcoff_bss_section_name,
18082 main_input_filename, ".bss_");
18083 rs6000_gen_section_name (&xcoff_private_data_section_name,
18084 main_input_filename, ".rw_");
18085 rs6000_gen_section_name (&xcoff_read_only_section_name,
18086 main_input_filename, ".ro_");
18088 fputs ("\t.file\t", asm_out_file);
18089 output_quoted_string (asm_out_file, main_input_filename);
18090 fputc ('\n', asm_out_file);
18091 if (write_symbols != NO_DEBUG)
18092 private_data_section ();
18095 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18096 rs6000_file_start ();
18099 /* Output at end of assembler file.
18100 On the RS/6000, referencing data should automatically pull in text. */
18103 rs6000_xcoff_file_end (void)
18106 fputs ("_section_.text:\n", asm_out_file);
18108 fputs (TARGET_32BIT
18109 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18112 #endif /* TARGET_XCOFF */
18115 /* Cross-module name binding. Darwin does not support overriding
18116 functions at dynamic-link time. */
18119 rs6000_binds_local_p (tree decl)
18121 return default_binds_local_p_1 (decl, 0);
18125 /* Compute a (partial) cost for rtx X. Return true if the complete
18126 cost has been computed, and false if subexpressions should be
18127 scanned. In either case, *TOTAL contains the cost result. */
18130 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18132 enum machine_mode mode = GET_MODE (x);
18136 /* On the RS/6000, if it is valid in the insn, it is free. */
18138 if (((outer_code == SET
18139 || outer_code == PLUS
18140 || outer_code == MINUS)
18141 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18142 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18143 || (outer_code == AND
18144 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18145 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18146 mode == SImode ? 'L' : 'J'))
18147 || mask_operand (x, VOIDmode)))
18148 || ((outer_code == IOR || outer_code == XOR)
18149 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18150 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18151 mode == SImode ? 'L' : 'J'))))
18152 || outer_code == ASHIFT
18153 || outer_code == ASHIFTRT
18154 || outer_code == LSHIFTRT
18155 || outer_code == ROTATE
18156 || outer_code == ROTATERT
18157 || outer_code == ZERO_EXTRACT
18158 || (outer_code == MULT
18159 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18160 || ((outer_code == DIV || outer_code == UDIV
18161 || outer_code == MOD || outer_code == UMOD)
18162 && exact_log2 (INTVAL (x)) >= 0)
18163 || (outer_code == COMPARE
18164 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18165 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18166 || (outer_code == EQ
18167 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18168 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18169 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18170 mode == SImode ? 'L' : 'J'))))
18171 || (outer_code == GTU
18172 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18173 || (outer_code == LTU
18174 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18179 else if ((outer_code == PLUS
18180 && reg_or_add_cint64_operand (x, VOIDmode))
18181 || (outer_code == MINUS
18182 && reg_or_sub_cint64_operand (x, VOIDmode))
18183 || ((outer_code == SET
18184 || outer_code == IOR
18185 || outer_code == XOR)
18187 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18189 *total = COSTS_N_INSNS (1);
18196 && ((outer_code == AND
18197 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18198 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18199 || mask64_operand (x, DImode)))
18200 || ((outer_code == IOR || outer_code == XOR)
18201 && CONST_DOUBLE_HIGH (x) == 0
18202 && (CONST_DOUBLE_LOW (x)
18203 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18208 else if (mode == DImode
18209 && (outer_code == SET
18210 || outer_code == IOR
18211 || outer_code == XOR)
18212 && CONST_DOUBLE_HIGH (x) == 0)
18214 *total = COSTS_N_INSNS (1);
18223 /* When optimizing for size, MEM should be slightly more expensive
18224 than generating address, e.g., (plus (reg) (const)).
18225 L1 cache latency is about two instructions. */
18226 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18234 if (mode == DFmode)
18236 if (GET_CODE (XEXP (x, 0)) == MULT)
18238 /* FNMA accounted in outer NEG. */
18239 if (outer_code == NEG)
18240 *total = rs6000_cost->dmul - rs6000_cost->fp;
18242 *total = rs6000_cost->dmul;
18245 *total = rs6000_cost->fp;
18247 else if (mode == SFmode)
18249 /* FNMA accounted in outer NEG. */
18250 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18253 *total = rs6000_cost->fp;
18255 else if (GET_CODE (XEXP (x, 0)) == MULT)
18257 /* The rs6000 doesn't have shift-and-add instructions. */
18258 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
18259 *total += COSTS_N_INSNS (1);
18262 *total = COSTS_N_INSNS (1);
18266 if (mode == DFmode)
18268 if (GET_CODE (XEXP (x, 0)) == MULT)
18270 /* FNMA accounted in outer NEG. */
18271 if (outer_code == NEG)
18274 *total = rs6000_cost->dmul;
18277 *total = rs6000_cost->fp;
18279 else if (mode == SFmode)
18281 /* FNMA accounted in outer NEG. */
18282 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18285 *total = rs6000_cost->fp;
18287 else if (GET_CODE (XEXP (x, 0)) == MULT)
18289 /* The rs6000 doesn't have shift-and-sub instructions. */
18290 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
18291 *total += COSTS_N_INSNS (1);
18294 *total = COSTS_N_INSNS (1);
18298 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18299 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18301 if (INTVAL (XEXP (x, 1)) >= -256
18302 && INTVAL (XEXP (x, 1)) <= 255)
18303 *total = rs6000_cost->mulsi_const9;
18305 *total = rs6000_cost->mulsi_const;
18307 /* FMA accounted in outer PLUS/MINUS. */
18308 else if ((mode == DFmode || mode == SFmode)
18309 && (outer_code == PLUS || outer_code == MINUS))
18311 else if (mode == DFmode)
18312 *total = rs6000_cost->dmul;
18313 else if (mode == SFmode)
18314 *total = rs6000_cost->fp;
18315 else if (mode == DImode)
18316 *total = rs6000_cost->muldi;
18318 *total = rs6000_cost->mulsi;
18323 if (FLOAT_MODE_P (mode))
18325 *total = mode == DFmode ? rs6000_cost->ddiv
18326 : rs6000_cost->sdiv;
18333 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18334 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18336 if (code == DIV || code == MOD)
18338 *total = COSTS_N_INSNS (2);
18341 *total = COSTS_N_INSNS (1);
18345 if (GET_MODE (XEXP (x, 1)) == DImode)
18346 *total = rs6000_cost->divdi;
18348 *total = rs6000_cost->divsi;
18350 /* Add in shift and subtract for MOD. */
18351 if (code == MOD || code == UMOD)
18352 *total += COSTS_N_INSNS (2);
18356 *total = COSTS_N_INSNS (4);
18360 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18371 *total = COSTS_N_INSNS (1);
18379 /* Handle mul_highpart. */
18380 if (outer_code == TRUNCATE
18381 && GET_CODE (XEXP (x, 0)) == MULT)
18383 if (mode == DImode)
18384 *total = rs6000_cost->muldi;
18386 *total = rs6000_cost->mulsi;
18389 else if (outer_code == AND)
18392 *total = COSTS_N_INSNS (1);
18397 if (GET_CODE (XEXP (x, 0)) == MEM)
18400 *total = COSTS_N_INSNS (1);
18406 if (!FLOAT_MODE_P (mode))
18408 *total = COSTS_N_INSNS (1);
18414 case UNSIGNED_FLOAT:
18418 case FLOAT_TRUNCATE:
18419 *total = rs6000_cost->fp;
18423 switch (XINT (x, 1))
18426 *total = rs6000_cost->fp;
18438 *total = COSTS_N_INSNS (1);
18441 else if (FLOAT_MODE_P (mode)
18442 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18444 *total = rs6000_cost->fp;
18452 /* Carry bit requires mode == Pmode.
18453 NEG or PLUS already counted so only add one. */
18455 && (outer_code == NEG || outer_code == PLUS))
18457 *total = COSTS_N_INSNS (1);
18460 if (outer_code == SET)
18462 if (XEXP (x, 1) == const0_rtx)
18464 *total = COSTS_N_INSNS (2);
18467 else if (mode == Pmode)
18469 *total = COSTS_N_INSNS (3);
18478 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18480 *total = COSTS_N_INSNS (2);
18484 if (outer_code == COMPARE)
18498 /* A C expression returning the cost of moving data from a register of class
18499 CLASS1 to one of CLASS2. */
18502 rs6000_register_move_cost (enum machine_mode mode,
18503 enum reg_class from, enum reg_class to)
18505 /* Moves from/to GENERAL_REGS. */
18506 if (reg_classes_intersect_p (to, GENERAL_REGS)
18507 || reg_classes_intersect_p (from, GENERAL_REGS))
18509 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18512 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18513 return (rs6000_memory_move_cost (mode, from, 0)
18514 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18516 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18518 else if (from == CR_REGS)
18522 /* A move will cost one instruction per GPR moved. */
18523 return 2 * HARD_REGNO_NREGS (0, mode);
18526 /* Moving between two similar registers is just one instruction. */
18527 else if (reg_classes_intersect_p (to, from))
18528 return mode == TFmode ? 4 : 2;
18530 /* Everything else has to go through GENERAL_REGS. */
18532 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18533 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18536 /* A C expressions returning the cost of moving data of MODE from a register to
18540 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18541 int in ATTRIBUTE_UNUSED)
18543 if (reg_classes_intersect_p (class, GENERAL_REGS))
18544 return 4 * HARD_REGNO_NREGS (0, mode);
18545 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18546 return 4 * HARD_REGNO_NREGS (32, mode);
18547 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18548 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
18550 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18553 /* Return an RTX representing where to find the function value of a
18554 function returning MODE. */
18556 rs6000_complex_function_value (enum machine_mode mode)
18558 unsigned int regno;
18560 enum machine_mode inner = GET_MODE_INNER (mode);
18561 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18563 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18564 regno = FP_ARG_RETURN;
18567 regno = GP_ARG_RETURN;
18569 /* 32-bit is OK since it'll go in r3/r4. */
18570 if (TARGET_32BIT && inner_bytes >= 4)
18571 return gen_rtx_REG (mode, regno);
18574 if (inner_bytes >= 8)
18575 return gen_rtx_REG (mode, regno);
18577 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18579 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18580 GEN_INT (inner_bytes));
18581 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18584 /* Compose a PARALLEL for a darwin64 struct being returned by
18588 rs6000_darwin64_function_value (CUMULATIVE_ARGS *cum, tree valtype)
18591 rtx rvec[FIRST_PSEUDO_REGISTER], sub, roffset, suboff;
18592 int k = 0, bytepos, tot, elt, i, subbytepos;
18593 enum machine_mode fmode;
18595 switch (TREE_CODE (valtype))
18598 for (f = TYPE_FIELDS (valtype); f ; f = TREE_CHAIN (f))
18599 if (TREE_CODE (f) == FIELD_DECL)
18601 ftype = TREE_TYPE (f);
18602 fmode = TYPE_MODE (ftype);
18603 bytepos = int_bit_position (f) / BITS_PER_UNIT;
18604 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18606 sub = gen_rtx_REG (fmode, cum->fregno++);
18607 cum->sysv_gregno++;
18609 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18611 sub = gen_rtx_REG (fmode, cum->vregno++);
18612 cum->sysv_gregno++;
18614 else if (fmode == BLKmode
18615 && (TREE_CODE (ftype) == RECORD_TYPE
18616 || TREE_CODE (ftype) == ARRAY_TYPE))
18617 sub = rs6000_darwin64_function_value (cum, ftype);
18619 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18620 if (sub == NULL_RTX)
18622 else if (GET_CODE (sub) == PARALLEL)
18624 for (i = 0; i < XVECLEN (sub, 0); i++)
18626 rtx subsub = XVECEXP (sub, 0, i);
18628 suboff = XEXP (subsub, 1);
18629 subbytepos = INTVAL (suboff);
18630 subbytepos += bytepos;
18631 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18632 subsub = XEXP (subsub, 0);
18633 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18638 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18639 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18643 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18648 /* If passing by value won't work, give up. */
18649 if (int_size_in_bytes (valtype) <= 0)
18651 ftype = TREE_TYPE (valtype);
18652 fmode = TYPE_MODE (ftype);
18653 tot = int_size_in_bytes (valtype) / int_size_in_bytes (ftype);
18655 for (elt = 0; elt < tot; ++elt)
18657 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18659 sub = gen_rtx_REG (fmode, cum->fregno++);
18660 cum->sysv_gregno++;
18662 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18664 sub = gen_rtx_REG (fmode, cum->vregno++);
18665 cum->sysv_gregno++;
18667 else if (fmode == BLKmode
18668 && (TREE_CODE (ftype) == RECORD_TYPE
18669 || TREE_CODE (ftype) == ARRAY_TYPE))
18670 sub = rs6000_darwin64_function_value (cum, ftype);
18672 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18673 if (sub == NULL_RTX)
18675 else if (GET_CODE (sub) == PARALLEL)
18677 for (i = 0; i < XVECLEN (sub, 0); i++)
18679 rtx subsub = XVECEXP (sub, 0, i);
18681 suboff = XEXP (subsub, 1);
18682 subbytepos = INTVAL (suboff);
18683 subbytepos += bytepos;
18684 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18685 subsub = XEXP (subsub, 0);
18686 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18691 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18692 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18694 bytepos += int_size_in_bytes (ftype);
18697 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18706 /* Define how to find the value returned by a function.
18707 VALTYPE is the data type of the value (as a tree).
18708 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18709 otherwise, FUNC is 0.
18711 On the SPE, both FPs and vectors are returned in r3.
18713 On RS/6000 an integer value is in r3 and a floating-point value is in
18714 fp1, unless -msoft-float. */
18717 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18719 enum machine_mode mode;
18720 unsigned int regno;
18722 /* Special handling for structs in darwin64. */
18723 if (rs6000_darwin64_abi
18724 && TYPE_MODE (valtype) == BLKmode
18725 && (TREE_CODE (valtype) == RECORD_TYPE
18726 || TREE_CODE (valtype) == ARRAY_TYPE))
18728 CUMULATIVE_ARGS valcum;
18731 valcum.sysv_gregno = GP_ARG_RETURN;
18732 valcum.fregno = FP_ARG_MIN_REG;
18733 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18734 valret = rs6000_darwin64_function_value (&valcum, valtype);
18737 /* Otherwise fall through to standard ABI rules. */
18740 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18742 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18743 return gen_rtx_PARALLEL (DImode,
18745 gen_rtx_EXPR_LIST (VOIDmode,
18746 gen_rtx_REG (SImode, GP_ARG_RETURN),
18748 gen_rtx_EXPR_LIST (VOIDmode,
18749 gen_rtx_REG (SImode,
18750 GP_ARG_RETURN + 1),
18754 if ((INTEGRAL_TYPE_P (valtype)
18755 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18756 || POINTER_TYPE_P (valtype))
18757 mode = TARGET_32BIT ? SImode : DImode;
18759 mode = TYPE_MODE (valtype);
18761 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18762 regno = FP_ARG_RETURN;
18763 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18764 && targetm.calls.split_complex_arg)
18765 return rs6000_complex_function_value (mode);
18766 else if (TREE_CODE (valtype) == VECTOR_TYPE
18767 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18768 && ALTIVEC_VECTOR_MODE (mode))
18769 regno = ALTIVEC_ARG_RETURN;
18770 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18771 && (mode == DFmode || mode == DCmode))
18772 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18774 regno = GP_ARG_RETURN;
18776 return gen_rtx_REG (mode, regno);
18779 /* Define how to find the value returned by a library function
18780 assuming the value has mode MODE. */
18782 rs6000_libcall_value (enum machine_mode mode)
18784 unsigned int regno;
18786 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18788 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18789 return gen_rtx_PARALLEL (DImode,
18791 gen_rtx_EXPR_LIST (VOIDmode,
18792 gen_rtx_REG (SImode, GP_ARG_RETURN),
18794 gen_rtx_EXPR_LIST (VOIDmode,
18795 gen_rtx_REG (SImode,
18796 GP_ARG_RETURN + 1),
18800 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18801 && TARGET_HARD_FLOAT && TARGET_FPRS)
18802 regno = FP_ARG_RETURN;
18803 else if (ALTIVEC_VECTOR_MODE (mode)
18804 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18805 regno = ALTIVEC_ARG_RETURN;
18806 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18807 return rs6000_complex_function_value (mode);
18808 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18809 && (mode == DFmode || mode == DCmode))
18810 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18812 regno = GP_ARG_RETURN;
18814 return gen_rtx_REG (mode, regno);
18817 /* Define the offset between two registers, FROM to be eliminated and its
18818 replacement TO, at the start of a routine. */
18820 rs6000_initial_elimination_offset (int from, int to)
18822 rs6000_stack_t *info = rs6000_stack_info ();
18823 HOST_WIDE_INT offset;
18825 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18826 offset = info->push_p ? 0 : -info->total_size;
18827 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
18828 offset = info->total_size;
18829 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18830 offset = info->push_p ? info->total_size : 0;
18831 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18839 /* Return true if TYPE is of type __ev64_opaque__. */
18842 is_ev64_opaque_type (tree type)
18845 && (type == opaque_V2SI_type_node
18846 || type == opaque_V2SF_type_node
18847 || type == opaque_p_V2SI_type_node));
18851 rs6000_dwarf_register_span (rtx reg)
18856 && (SPE_VECTOR_MODE (GET_MODE (reg))
18857 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18862 regno = REGNO (reg);
18864 /* The duality of the SPE register size wreaks all kinds of havoc.
18865 This is a way of distinguishing r0 in 32-bits from r0 in
18868 gen_rtx_PARALLEL (VOIDmode,
18871 gen_rtx_REG (SImode, regno + 1200),
18872 gen_rtx_REG (SImode, regno))
18874 gen_rtx_REG (SImode, regno),
18875 gen_rtx_REG (SImode, regno + 1200)));
18878 /* Map internal gcc register numbers to DWARF2 register numbers. */
18881 rs6000_dbx_register_number (unsigned int regno)
18883 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18885 if (regno == MQ_REGNO)
18887 if (regno == LINK_REGISTER_REGNUM)
18889 if (regno == COUNT_REGISTER_REGNUM)
18891 if (CR_REGNO_P (regno))
18892 return regno - CR0_REGNO + 86;
18893 if (regno == XER_REGNO)
18895 if (ALTIVEC_REGNO_P (regno))
18896 return regno - FIRST_ALTIVEC_REGNO + 1124;
18897 if (regno == VRSAVE_REGNO)
18899 if (regno == VSCR_REGNO)
18901 if (regno == SPE_ACC_REGNO)
18903 if (regno == SPEFSCR_REGNO)
18905 /* SPE high reg number. We get these values of regno from
18906 rs6000_dwarf_register_span. */
18907 if (regno >= 1200 && regno < 1232)
18913 /* target hook eh_return_filter_mode */
18914 static enum machine_mode
18915 rs6000_eh_return_filter_mode (void)
18917 return TARGET_32BIT ? SImode : word_mode;
18920 /* Target hook for vector_mode_supported_p. */
18922 rs6000_vector_mode_supported_p (enum machine_mode mode)
18925 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18928 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18935 #include "gt-rs6000.h"