1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu;
138 struct rs6000_cpu_select rs6000_select[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 static GTY(()) bool rs6000_cell_dont_microcode;
148 /* Always emit branch hint bits. */
149 static GTY(()) bool rs6000_always_hint;
151 /* Schedule instructions for group formation. */
152 static GTY(()) bool rs6000_sched_groups;
154 /* Align branch targets. */
155 static GTY(()) bool rs6000_align_branch_targets;
157 /* Support for -msched-costly-dep option. */
158 const char *rs6000_sched_costly_dep_str;
159 enum rs6000_dependence_cost rs6000_sched_costly_dep;
161 /* Support for -minsert-sched-nops option. */
162 const char *rs6000_sched_insert_nops_str;
163 enum rs6000_nop_insertion rs6000_sched_insert_nops;
165 /* Support targetm.vectorize.builtin_mask_for_load. */
166 static GTY(()) tree altivec_builtin_mask_for_load;
168 /* Size of long double. */
169 int rs6000_long_double_type_size;
171 /* IEEE quad extended precision long double. */
174 /* Nonzero to use AltiVec ABI. */
175 int rs6000_altivec_abi;
177 /* Nonzero if we want SPE ABI extensions. */
180 /* Nonzero if floating point operations are done in the GPRs. */
181 int rs6000_float_gprs = 0;
183 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
184 int rs6000_darwin64_abi;
186 /* Set to nonzero once AIX common-mode calls have been defined. */
187 static GTY(()) int common_mode_defined;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx rs6000_compare_op0, rs6000_compare_op1;
192 int rs6000_compare_fp_p;
194 /* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196 int rs6000_pic_labelno;
199 /* Which abi to adhere to */
200 const char *rs6000_abi_name;
202 /* Semantics of the small data area */
203 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
205 /* Which small data model to use */
206 const char *rs6000_sdata_name = (char *)0;
208 /* Counter for labels which are to be placed in .fixup. */
209 int fixuplabelno = 0;
212 /* Bit size of immediate TLS offsets and string from which it is decoded. */
213 int rs6000_tls_size = 32;
214 const char *rs6000_tls_size_string;
216 /* ABI enumeration available for subtarget to use. */
217 enum rs6000_abi rs6000_current_abi;
219 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
223 const char *rs6000_debug_name;
224 int rs6000_debug_stack; /* debug stack applications */
225 int rs6000_debug_arg; /* debug argument handling */
227 /* Value is TRUE if register/mode pair is acceptable. */
228 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
230 /* Built in types. */
232 tree rs6000_builtin_types[RS6000_BTI_MAX];
233 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
235 const char *rs6000_traceback_name;
237 traceback_default = 0,
243 /* Flag to say the TOC is initialized */
245 char toc_label_name[10];
247 /* Cached value of rs6000_variable_issue. This is cached in
248 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
249 static short cached_can_issue_more;
251 static GTY(()) section *read_only_data_section;
252 static GTY(()) section *private_data_section;
253 static GTY(()) section *read_only_private_data_section;
254 static GTY(()) section *sdata2_section;
255 static GTY(()) section *toc_section;
257 /* Control alignment for fields within structures. */
258 /* String from -malign-XXXXX. */
259 int rs6000_alignment_flags;
261 /* True for any options that were explicitly set. */
263 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
264 bool alignment; /* True if -malign- was used. */
265 bool spe_abi; /* True if -mabi=spe/no-spe was used. */
266 bool altivec_abi; /* True if -mabi=altivec/no-altivec used. */
267 bool spe; /* True if -mspe= was used. */
268 bool float_gprs; /* True if -mfloat-gprs= was used. */
269 bool isel; /* True if -misel was used. */
270 bool long_double; /* True if -mlong-double- was used. */
271 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
272 bool vrsave; /* True if -mvrsave was used. */
273 } rs6000_explicit_options;
275 struct builtin_description
277 /* mask is not const because we're going to alter it below. This
278 nonsense will go away when we rewrite the -march infrastructure
279 to give us more target flag bits. */
281 const enum insn_code icode;
282 const char *const name;
283 const enum rs6000_builtins code;
286 /* Target cpu costs. */
288 struct processor_costs {
289 const int mulsi; /* cost of SImode multiplication. */
290 const int mulsi_const; /* cost of SImode multiplication by constant. */
291 const int mulsi_const9; /* cost of SImode mult by short constant. */
292 const int muldi; /* cost of DImode multiplication. */
293 const int divsi; /* cost of SImode division. */
294 const int divdi; /* cost of DImode division. */
295 const int fp; /* cost of simple SFmode and DFmode insns. */
296 const int dmul; /* cost of DFmode multiplication (and fmadd). */
297 const int sdiv; /* cost of SFmode division (fdivs). */
298 const int ddiv; /* cost of DFmode division (fdiv). */
299 const int cache_line_size; /* cache line size in bytes. */
300 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
301 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
302 const int simultaneous_prefetches; /* number of parallel prefetch
306 const struct processor_costs *rs6000_cost;
308 /* Processor costs (relative to an add) */
310 /* Instruction size costs on 32bit processors. */
312 struct processor_costs size32_cost = {
313 COSTS_N_INSNS (1), /* mulsi */
314 COSTS_N_INSNS (1), /* mulsi_const */
315 COSTS_N_INSNS (1), /* mulsi_const9 */
316 COSTS_N_INSNS (1), /* muldi */
317 COSTS_N_INSNS (1), /* divsi */
318 COSTS_N_INSNS (1), /* divdi */
319 COSTS_N_INSNS (1), /* fp */
320 COSTS_N_INSNS (1), /* dmul */
321 COSTS_N_INSNS (1), /* sdiv */
322 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction size costs on 64bit processors. */
331 struct processor_costs size64_cost = {
332 COSTS_N_INSNS (1), /* mulsi */
333 COSTS_N_INSNS (1), /* mulsi_const */
334 COSTS_N_INSNS (1), /* mulsi_const9 */
335 COSTS_N_INSNS (1), /* muldi */
336 COSTS_N_INSNS (1), /* divsi */
337 COSTS_N_INSNS (1), /* divdi */
338 COSTS_N_INSNS (1), /* fp */
339 COSTS_N_INSNS (1), /* dmul */
340 COSTS_N_INSNS (1), /* sdiv */
341 COSTS_N_INSNS (1), /* ddiv */
348 /* Instruction costs on RIOS1 processors. */
350 struct processor_costs rios1_cost = {
351 COSTS_N_INSNS (5), /* mulsi */
352 COSTS_N_INSNS (4), /* mulsi_const */
353 COSTS_N_INSNS (3), /* mulsi_const9 */
354 COSTS_N_INSNS (5), /* muldi */
355 COSTS_N_INSNS (19), /* divsi */
356 COSTS_N_INSNS (19), /* divdi */
357 COSTS_N_INSNS (2), /* fp */
358 COSTS_N_INSNS (2), /* dmul */
359 COSTS_N_INSNS (19), /* sdiv */
360 COSTS_N_INSNS (19), /* ddiv */
367 /* Instruction costs on RIOS2 processors. */
369 struct processor_costs rios2_cost = {
370 COSTS_N_INSNS (2), /* mulsi */
371 COSTS_N_INSNS (2), /* mulsi_const */
372 COSTS_N_INSNS (2), /* mulsi_const9 */
373 COSTS_N_INSNS (2), /* muldi */
374 COSTS_N_INSNS (13), /* divsi */
375 COSTS_N_INSNS (13), /* divdi */
376 COSTS_N_INSNS (2), /* fp */
377 COSTS_N_INSNS (2), /* dmul */
378 COSTS_N_INSNS (17), /* sdiv */
379 COSTS_N_INSNS (17), /* ddiv */
386 /* Instruction costs on RS64A processors. */
388 struct processor_costs rs64a_cost = {
389 COSTS_N_INSNS (20), /* mulsi */
390 COSTS_N_INSNS (12), /* mulsi_const */
391 COSTS_N_INSNS (8), /* mulsi_const9 */
392 COSTS_N_INSNS (34), /* muldi */
393 COSTS_N_INSNS (65), /* divsi */
394 COSTS_N_INSNS (67), /* divdi */
395 COSTS_N_INSNS (4), /* fp */
396 COSTS_N_INSNS (4), /* dmul */
397 COSTS_N_INSNS (31), /* sdiv */
398 COSTS_N_INSNS (31), /* ddiv */
405 /* Instruction costs on MPCCORE processors. */
407 struct processor_costs mpccore_cost = {
408 COSTS_N_INSNS (2), /* mulsi */
409 COSTS_N_INSNS (2), /* mulsi_const */
410 COSTS_N_INSNS (2), /* mulsi_const9 */
411 COSTS_N_INSNS (2), /* muldi */
412 COSTS_N_INSNS (6), /* divsi */
413 COSTS_N_INSNS (6), /* divdi */
414 COSTS_N_INSNS (4), /* fp */
415 COSTS_N_INSNS (5), /* dmul */
416 COSTS_N_INSNS (10), /* sdiv */
417 COSTS_N_INSNS (17), /* ddiv */
424 /* Instruction costs on PPC403 processors. */
426 struct processor_costs ppc403_cost = {
427 COSTS_N_INSNS (4), /* mulsi */
428 COSTS_N_INSNS (4), /* mulsi_const */
429 COSTS_N_INSNS (4), /* mulsi_const9 */
430 COSTS_N_INSNS (4), /* muldi */
431 COSTS_N_INSNS (33), /* divsi */
432 COSTS_N_INSNS (33), /* divdi */
433 COSTS_N_INSNS (11), /* fp */
434 COSTS_N_INSNS (11), /* dmul */
435 COSTS_N_INSNS (11), /* sdiv */
436 COSTS_N_INSNS (11), /* ddiv */
443 /* Instruction costs on PPC405 processors. */
445 struct processor_costs ppc405_cost = {
446 COSTS_N_INSNS (5), /* mulsi */
447 COSTS_N_INSNS (4), /* mulsi_const */
448 COSTS_N_INSNS (3), /* mulsi_const9 */
449 COSTS_N_INSNS (5), /* muldi */
450 COSTS_N_INSNS (35), /* divsi */
451 COSTS_N_INSNS (35), /* divdi */
452 COSTS_N_INSNS (11), /* fp */
453 COSTS_N_INSNS (11), /* dmul */
454 COSTS_N_INSNS (11), /* sdiv */
455 COSTS_N_INSNS (11), /* ddiv */
462 /* Instruction costs on PPC440 processors. */
464 struct processor_costs ppc440_cost = {
465 COSTS_N_INSNS (3), /* mulsi */
466 COSTS_N_INSNS (2), /* mulsi_const */
467 COSTS_N_INSNS (2), /* mulsi_const9 */
468 COSTS_N_INSNS (3), /* muldi */
469 COSTS_N_INSNS (34), /* divsi */
470 COSTS_N_INSNS (34), /* divdi */
471 COSTS_N_INSNS (5), /* fp */
472 COSTS_N_INSNS (5), /* dmul */
473 COSTS_N_INSNS (19), /* sdiv */
474 COSTS_N_INSNS (33), /* ddiv */
481 /* Instruction costs on PPC601 processors. */
483 struct processor_costs ppc601_cost = {
484 COSTS_N_INSNS (5), /* mulsi */
485 COSTS_N_INSNS (5), /* mulsi_const */
486 COSTS_N_INSNS (5), /* mulsi_const9 */
487 COSTS_N_INSNS (5), /* muldi */
488 COSTS_N_INSNS (36), /* divsi */
489 COSTS_N_INSNS (36), /* divdi */
490 COSTS_N_INSNS (4), /* fp */
491 COSTS_N_INSNS (5), /* dmul */
492 COSTS_N_INSNS (17), /* sdiv */
493 COSTS_N_INSNS (31), /* ddiv */
500 /* Instruction costs on PPC603 processors. */
502 struct processor_costs ppc603_cost = {
503 COSTS_N_INSNS (5), /* mulsi */
504 COSTS_N_INSNS (3), /* mulsi_const */
505 COSTS_N_INSNS (2), /* mulsi_const9 */
506 COSTS_N_INSNS (5), /* muldi */
507 COSTS_N_INSNS (37), /* divsi */
508 COSTS_N_INSNS (37), /* divdi */
509 COSTS_N_INSNS (3), /* fp */
510 COSTS_N_INSNS (4), /* dmul */
511 COSTS_N_INSNS (18), /* sdiv */
512 COSTS_N_INSNS (33), /* ddiv */
519 /* Instruction costs on PPC604 processors. */
521 struct processor_costs ppc604_cost = {
522 COSTS_N_INSNS (4), /* mulsi */
523 COSTS_N_INSNS (4), /* mulsi_const */
524 COSTS_N_INSNS (4), /* mulsi_const9 */
525 COSTS_N_INSNS (4), /* muldi */
526 COSTS_N_INSNS (20), /* divsi */
527 COSTS_N_INSNS (20), /* divdi */
528 COSTS_N_INSNS (3), /* fp */
529 COSTS_N_INSNS (3), /* dmul */
530 COSTS_N_INSNS (18), /* sdiv */
531 COSTS_N_INSNS (32), /* ddiv */
538 /* Instruction costs on PPC604e processors. */
540 struct processor_costs ppc604e_cost = {
541 COSTS_N_INSNS (2), /* mulsi */
542 COSTS_N_INSNS (2), /* mulsi_const */
543 COSTS_N_INSNS (2), /* mulsi_const9 */
544 COSTS_N_INSNS (2), /* muldi */
545 COSTS_N_INSNS (20), /* divsi */
546 COSTS_N_INSNS (20), /* divdi */
547 COSTS_N_INSNS (3), /* fp */
548 COSTS_N_INSNS (3), /* dmul */
549 COSTS_N_INSNS (18), /* sdiv */
550 COSTS_N_INSNS (32), /* ddiv */
557 /* Instruction costs on PPC620 processors. */
559 struct processor_costs ppc620_cost = {
560 COSTS_N_INSNS (5), /* mulsi */
561 COSTS_N_INSNS (4), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (7), /* muldi */
564 COSTS_N_INSNS (21), /* divsi */
565 COSTS_N_INSNS (37), /* divdi */
566 COSTS_N_INSNS (3), /* fp */
567 COSTS_N_INSNS (3), /* dmul */
568 COSTS_N_INSNS (18), /* sdiv */
569 COSTS_N_INSNS (32), /* ddiv */
576 /* Instruction costs on PPC630 processors. */
578 struct processor_costs ppc630_cost = {
579 COSTS_N_INSNS (5), /* mulsi */
580 COSTS_N_INSNS (4), /* mulsi_const */
581 COSTS_N_INSNS (3), /* mulsi_const9 */
582 COSTS_N_INSNS (7), /* muldi */
583 COSTS_N_INSNS (21), /* divsi */
584 COSTS_N_INSNS (37), /* divdi */
585 COSTS_N_INSNS (3), /* fp */
586 COSTS_N_INSNS (3), /* dmul */
587 COSTS_N_INSNS (17), /* sdiv */
588 COSTS_N_INSNS (21), /* ddiv */
595 /* Instruction costs on Cell processor. */
596 /* COSTS_N_INSNS (1) ~ one add. */
598 struct processor_costs ppccell_cost = {
599 COSTS_N_INSNS (9/2)+2, /* mulsi */
600 COSTS_N_INSNS (6/2), /* mulsi_const */
601 COSTS_N_INSNS (6/2), /* mulsi_const9 */
602 COSTS_N_INSNS (15/2)+2, /* muldi */
603 COSTS_N_INSNS (38/2), /* divsi */
604 COSTS_N_INSNS (70/2), /* divdi */
605 COSTS_N_INSNS (10/2), /* fp */
606 COSTS_N_INSNS (10/2), /* dmul */
607 COSTS_N_INSNS (74/2), /* sdiv */
608 COSTS_N_INSNS (74/2), /* ddiv */
615 /* Instruction costs on PPC750 and PPC7400 processors. */
617 struct processor_costs ppc750_cost = {
618 COSTS_N_INSNS (5), /* mulsi */
619 COSTS_N_INSNS (3), /* mulsi_const */
620 COSTS_N_INSNS (2), /* mulsi_const9 */
621 COSTS_N_INSNS (5), /* muldi */
622 COSTS_N_INSNS (17), /* divsi */
623 COSTS_N_INSNS (17), /* divdi */
624 COSTS_N_INSNS (3), /* fp */
625 COSTS_N_INSNS (3), /* dmul */
626 COSTS_N_INSNS (17), /* sdiv */
627 COSTS_N_INSNS (31), /* ddiv */
634 /* Instruction costs on PPC7450 processors. */
636 struct processor_costs ppc7450_cost = {
637 COSTS_N_INSNS (4), /* mulsi */
638 COSTS_N_INSNS (3), /* mulsi_const */
639 COSTS_N_INSNS (3), /* mulsi_const9 */
640 COSTS_N_INSNS (4), /* muldi */
641 COSTS_N_INSNS (23), /* divsi */
642 COSTS_N_INSNS (23), /* divdi */
643 COSTS_N_INSNS (5), /* fp */
644 COSTS_N_INSNS (5), /* dmul */
645 COSTS_N_INSNS (21), /* sdiv */
646 COSTS_N_INSNS (35), /* ddiv */
653 /* Instruction costs on PPC8540 processors. */
655 struct processor_costs ppc8540_cost = {
656 COSTS_N_INSNS (4), /* mulsi */
657 COSTS_N_INSNS (4), /* mulsi_const */
658 COSTS_N_INSNS (4), /* mulsi_const9 */
659 COSTS_N_INSNS (4), /* muldi */
660 COSTS_N_INSNS (19), /* divsi */
661 COSTS_N_INSNS (19), /* divdi */
662 COSTS_N_INSNS (4), /* fp */
663 COSTS_N_INSNS (4), /* dmul */
664 COSTS_N_INSNS (29), /* sdiv */
665 COSTS_N_INSNS (29), /* ddiv */
669 1, /* prefetch streams /*/
672 /* Instruction costs on E300C2 and E300C3 cores. */
674 struct processor_costs ppce300c2c3_cost = {
675 COSTS_N_INSNS (4), /* mulsi */
676 COSTS_N_INSNS (4), /* mulsi_const */
677 COSTS_N_INSNS (4), /* mulsi_const9 */
678 COSTS_N_INSNS (4), /* muldi */
679 COSTS_N_INSNS (19), /* divsi */
680 COSTS_N_INSNS (19), /* divdi */
681 COSTS_N_INSNS (3), /* fp */
682 COSTS_N_INSNS (4), /* dmul */
683 COSTS_N_INSNS (18), /* sdiv */
684 COSTS_N_INSNS (33), /* ddiv */
688 1, /* prefetch streams /*/
691 /* Instruction costs on POWER4 and POWER5 processors. */
693 struct processor_costs power4_cost = {
694 COSTS_N_INSNS (3), /* mulsi */
695 COSTS_N_INSNS (2), /* mulsi_const */
696 COSTS_N_INSNS (2), /* mulsi_const9 */
697 COSTS_N_INSNS (4), /* muldi */
698 COSTS_N_INSNS (18), /* divsi */
699 COSTS_N_INSNS (34), /* divdi */
700 COSTS_N_INSNS (3), /* fp */
701 COSTS_N_INSNS (3), /* dmul */
702 COSTS_N_INSNS (17), /* sdiv */
703 COSTS_N_INSNS (17), /* ddiv */
707 8, /* prefetch streams /*/
710 /* Instruction costs on POWER6 processors. */
712 struct processor_costs power6_cost = {
713 COSTS_N_INSNS (8), /* mulsi */
714 COSTS_N_INSNS (8), /* mulsi_const */
715 COSTS_N_INSNS (8), /* mulsi_const9 */
716 COSTS_N_INSNS (8), /* muldi */
717 COSTS_N_INSNS (22), /* divsi */
718 COSTS_N_INSNS (28), /* divdi */
719 COSTS_N_INSNS (3), /* fp */
720 COSTS_N_INSNS (3), /* dmul */
721 COSTS_N_INSNS (13), /* sdiv */
722 COSTS_N_INSNS (16), /* ddiv */
726 16, /* prefetch streams */
730 static bool rs6000_function_ok_for_sibcall (tree, tree);
731 static const char *rs6000_invalid_within_doloop (const_rtx);
732 static rtx rs6000_generate_compare (enum rtx_code);
733 static void rs6000_emit_stack_tie (void);
734 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
735 static rtx spe_synthesize_frame_save (rtx);
736 static bool spe_func_has_64bit_regs_p (void);
737 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
739 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
740 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
741 static unsigned rs6000_hash_constant (rtx);
742 static unsigned toc_hash_function (const void *);
743 static int toc_hash_eq (const void *, const void *);
744 static int constant_pool_expr_1 (rtx, int *, int *);
745 static bool constant_pool_expr_p (rtx);
746 static bool legitimate_small_data_p (enum machine_mode, rtx);
747 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
748 static struct machine_function * rs6000_init_machine_status (void);
749 static bool rs6000_assemble_integer (rtx, unsigned int, int);
750 static bool no_global_regs_above (int);
751 #ifdef HAVE_GAS_HIDDEN
752 static void rs6000_assemble_visibility (tree, int);
754 static int rs6000_ra_ever_killed (void);
755 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
756 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
757 static bool rs6000_ms_bitfield_layout_p (const_tree);
758 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
759 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
760 static const char *rs6000_mangle_type (const_tree);
761 extern const struct attribute_spec rs6000_attribute_table[];
762 static void rs6000_set_default_type_attributes (tree);
763 static bool rs6000_reg_live_or_pic_offset_p (int);
764 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
765 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
766 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
768 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
769 static bool rs6000_return_in_memory (const_tree, const_tree);
770 static void rs6000_file_start (void);
772 static int rs6000_elf_reloc_rw_mask (void);
773 static void rs6000_elf_asm_out_constructor (rtx, int);
774 static void rs6000_elf_asm_out_destructor (rtx, int);
775 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
776 static void rs6000_elf_asm_init_sections (void);
777 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
778 unsigned HOST_WIDE_INT);
779 static void rs6000_elf_encode_section_info (tree, rtx, int)
782 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
783 static void rs6000_alloc_sdmode_stack_slot (void);
784 static void rs6000_instantiate_decls (void);
786 static void rs6000_xcoff_asm_output_anchor (rtx);
787 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
788 static void rs6000_xcoff_asm_init_sections (void);
789 static int rs6000_xcoff_reloc_rw_mask (void);
790 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
791 static section *rs6000_xcoff_select_section (tree, int,
792 unsigned HOST_WIDE_INT);
793 static void rs6000_xcoff_unique_section (tree, int);
794 static section *rs6000_xcoff_select_rtx_section
795 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
796 static const char * rs6000_xcoff_strip_name_encoding (const char *);
797 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
798 static void rs6000_xcoff_file_start (void);
799 static void rs6000_xcoff_file_end (void);
801 static int rs6000_variable_issue (FILE *, int, rtx, int);
802 static bool rs6000_rtx_costs (rtx, int, int, int *);
803 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
804 static void rs6000_sched_init (FILE *, int, int);
805 static bool is_microcoded_insn (rtx);
806 static bool is_nonpipeline_insn (rtx);
807 static bool is_cracked_insn (rtx);
808 static bool is_branch_slot_insn (rtx);
809 static bool is_load_insn (rtx);
810 static rtx get_store_dest (rtx pat);
811 static bool is_store_insn (rtx);
812 static bool set_to_load_agen (rtx,rtx);
813 static bool adjacent_mem_locations (rtx,rtx);
814 static int rs6000_adjust_priority (rtx, int);
815 static int rs6000_issue_rate (void);
816 static bool rs6000_is_costly_dependence (dep_t, int, int);
817 static rtx get_next_active_insn (rtx, rtx);
818 static bool insn_terminates_group_p (rtx , enum group_termination);
819 static bool insn_must_be_first_in_group (rtx);
820 static bool insn_must_be_last_in_group (rtx);
821 static bool is_costly_group (rtx *, rtx);
822 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
823 static int redefine_groups (FILE *, int, rtx, rtx);
824 static int pad_groups (FILE *, int, rtx, rtx);
825 static void rs6000_sched_finish (FILE *, int);
826 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
827 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
828 static int rs6000_use_sched_lookahead (void);
829 static int rs6000_use_sched_lookahead_guard (rtx);
830 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
831 static tree rs6000_builtin_mask_for_load (void);
832 static tree rs6000_builtin_mul_widen_even (tree);
833 static tree rs6000_builtin_mul_widen_odd (tree);
834 static tree rs6000_builtin_conversion (enum tree_code, tree);
836 static void def_builtin (int, const char *, tree, int);
837 static bool rs6000_vector_alignment_reachable (const_tree, bool);
838 static void rs6000_init_builtins (void);
839 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
840 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
841 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
842 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
843 static void altivec_init_builtins (void);
844 static void rs6000_common_init_builtins (void);
845 static void rs6000_init_libfuncs (void);
847 static void paired_init_builtins (void);
848 static rtx paired_expand_builtin (tree, rtx, bool *);
849 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
850 static rtx paired_expand_stv_builtin (enum insn_code, tree);
851 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
853 static void enable_mask_for_builtins (struct builtin_description *, int,
854 enum rs6000_builtins,
855 enum rs6000_builtins);
856 static tree build_opaque_vector_type (tree, int);
857 static void spe_init_builtins (void);
858 static rtx spe_expand_builtin (tree, rtx, bool *);
859 static rtx spe_expand_stv_builtin (enum insn_code, tree);
860 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
861 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
862 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
863 static rs6000_stack_t *rs6000_stack_info (void);
864 static void debug_stack_info (rs6000_stack_t *);
866 static rtx altivec_expand_builtin (tree, rtx, bool *);
867 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
868 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
869 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
870 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
871 static rtx altivec_expand_predicate_builtin (enum insn_code,
872 const char *, tree, rtx);
873 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
874 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
875 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
876 static rtx altivec_expand_vec_set_builtin (tree);
877 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
878 static int get_element_number (tree, tree);
879 static bool rs6000_handle_option (size_t, const char *, int);
880 static void rs6000_parse_tls_size_option (void);
881 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
882 static int first_altivec_reg_to_save (void);
883 static unsigned int compute_vrsave_mask (void);
884 static void compute_save_world_info (rs6000_stack_t *info_ptr);
885 static void is_altivec_return_reg (rtx, void *);
886 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
887 int easy_vector_constant (rtx, enum machine_mode);
888 static bool rs6000_is_opaque_type (const_tree);
889 static rtx rs6000_dwarf_register_span (rtx);
890 static void rs6000_init_dwarf_reg_sizes_extra (tree);
891 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
892 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
893 static rtx rs6000_tls_get_addr (void);
894 static rtx rs6000_got_sym (void);
895 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
896 static const char *rs6000_get_some_local_dynamic_name (void);
897 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
898 static rtx rs6000_complex_function_value (enum machine_mode);
899 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
900 enum machine_mode, tree);
901 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
903 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
904 tree, HOST_WIDE_INT);
905 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
908 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
909 const_tree, HOST_WIDE_INT,
911 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool);
912 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
913 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
914 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
915 enum machine_mode, tree,
917 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
919 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
921 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
923 static void macho_branch_islands (void);
924 static int no_previous_def (tree function_name);
925 static tree get_prev_label (tree function_name);
926 static void rs6000_darwin_file_start (void);
929 static tree rs6000_build_builtin_va_list (void);
930 static void rs6000_va_start (tree, rtx);
931 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
932 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
933 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
934 static bool rs6000_vector_mode_supported_p (enum machine_mode);
935 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
937 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
939 static int get_vsel_insn (enum machine_mode);
940 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
941 static tree rs6000_stack_protect_fail (void);
943 const int INSN_NOT_AVAILABLE = -1;
944 static enum machine_mode rs6000_eh_return_filter_mode (void);
946 /* Hash table stuff for keeping track of TOC entries. */
948 struct toc_hash_struct GTY(())
950 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
951 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
953 enum machine_mode key_mode;
957 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
959 /* Default register names. */
960 char rs6000_reg_names[][8] =
962 "0", "1", "2", "3", "4", "5", "6", "7",
963 "8", "9", "10", "11", "12", "13", "14", "15",
964 "16", "17", "18", "19", "20", "21", "22", "23",
965 "24", "25", "26", "27", "28", "29", "30", "31",
966 "0", "1", "2", "3", "4", "5", "6", "7",
967 "8", "9", "10", "11", "12", "13", "14", "15",
968 "16", "17", "18", "19", "20", "21", "22", "23",
969 "24", "25", "26", "27", "28", "29", "30", "31",
970 "mq", "lr", "ctr","ap",
971 "0", "1", "2", "3", "4", "5", "6", "7",
973 /* AltiVec registers. */
974 "0", "1", "2", "3", "4", "5", "6", "7",
975 "8", "9", "10", "11", "12", "13", "14", "15",
976 "16", "17", "18", "19", "20", "21", "22", "23",
977 "24", "25", "26", "27", "28", "29", "30", "31",
980 "spe_acc", "spefscr",
981 /* Soft frame pointer. */
985 #ifdef TARGET_REGNAMES
986 static const char alt_reg_names[][8] =
988 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
989 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
990 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
991 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
992 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
993 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
994 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
995 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
996 "mq", "lr", "ctr", "ap",
997 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
999 /* AltiVec registers. */
1000 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1001 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1002 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1003 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1005 /* SPE registers. */
1006 "spe_acc", "spefscr",
1007 /* Soft frame pointer. */
1012 #ifndef MASK_STRICT_ALIGN
1013 #define MASK_STRICT_ALIGN 0
1015 #ifndef TARGET_PROFILE_KERNEL
1016 #define TARGET_PROFILE_KERNEL 0
1019 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1020 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1022 /* Initialize the GCC target structure. */
1023 #undef TARGET_ATTRIBUTE_TABLE
1024 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1025 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1026 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1028 #undef TARGET_ASM_ALIGNED_DI_OP
1029 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1031 /* Default unaligned ops are only provided for ELF. Find the ops needed
1032 for non-ELF systems. */
1033 #ifndef OBJECT_FORMAT_ELF
1035 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1037 #undef TARGET_ASM_UNALIGNED_HI_OP
1038 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1039 #undef TARGET_ASM_UNALIGNED_SI_OP
1040 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1041 #undef TARGET_ASM_UNALIGNED_DI_OP
1042 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1045 #undef TARGET_ASM_UNALIGNED_HI_OP
1046 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1047 #undef TARGET_ASM_UNALIGNED_SI_OP
1048 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1049 #undef TARGET_ASM_UNALIGNED_DI_OP
1050 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1051 #undef TARGET_ASM_ALIGNED_DI_OP
1052 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1056 /* This hook deals with fixups for relocatable code and DI-mode objects
1058 #undef TARGET_ASM_INTEGER
1059 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1061 #ifdef HAVE_GAS_HIDDEN
1062 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1063 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1066 #undef TARGET_HAVE_TLS
1067 #define TARGET_HAVE_TLS HAVE_AS_TLS
1069 #undef TARGET_CANNOT_FORCE_CONST_MEM
1070 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1072 #undef TARGET_ASM_FUNCTION_PROLOGUE
1073 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1074 #undef TARGET_ASM_FUNCTION_EPILOGUE
1075 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1077 #undef TARGET_SCHED_VARIABLE_ISSUE
1078 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1080 #undef TARGET_SCHED_ISSUE_RATE
1081 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1082 #undef TARGET_SCHED_ADJUST_COST
1083 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1084 #undef TARGET_SCHED_ADJUST_PRIORITY
1085 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1086 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1087 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1088 #undef TARGET_SCHED_INIT
1089 #define TARGET_SCHED_INIT rs6000_sched_init
1090 #undef TARGET_SCHED_FINISH
1091 #define TARGET_SCHED_FINISH rs6000_sched_finish
1092 #undef TARGET_SCHED_REORDER
1093 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1094 #undef TARGET_SCHED_REORDER2
1095 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1097 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1098 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1100 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1101 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1103 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1104 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1105 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1106 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1107 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1108 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1109 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1110 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1112 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1113 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1115 #undef TARGET_INIT_BUILTINS
1116 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1118 #undef TARGET_EXPAND_BUILTIN
1119 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1121 #undef TARGET_MANGLE_TYPE
1122 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1124 #undef TARGET_INIT_LIBFUNCS
1125 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1128 #undef TARGET_BINDS_LOCAL_P
1129 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1132 #undef TARGET_MS_BITFIELD_LAYOUT_P
1133 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1135 #undef TARGET_ASM_OUTPUT_MI_THUNK
1136 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1138 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1139 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1141 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1142 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1144 #undef TARGET_INVALID_WITHIN_DOLOOP
1145 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1147 #undef TARGET_RTX_COSTS
1148 #define TARGET_RTX_COSTS rs6000_rtx_costs
1149 #undef TARGET_ADDRESS_COST
1150 #define TARGET_ADDRESS_COST hook_int_rtx_0
1152 #undef TARGET_VECTOR_OPAQUE_P
1153 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1155 #undef TARGET_DWARF_REGISTER_SPAN
1156 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1158 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1159 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1161 /* On rs6000, function arguments are promoted, as are function return
1163 #undef TARGET_PROMOTE_FUNCTION_ARGS
1164 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1165 #undef TARGET_PROMOTE_FUNCTION_RETURN
1166 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1168 #undef TARGET_RETURN_IN_MEMORY
1169 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1171 #undef TARGET_SETUP_INCOMING_VARARGS
1172 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1174 /* Always strict argument naming on rs6000. */
1175 #undef TARGET_STRICT_ARGUMENT_NAMING
1176 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1177 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1178 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1179 #undef TARGET_SPLIT_COMPLEX_ARG
1180 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1181 #undef TARGET_MUST_PASS_IN_STACK
1182 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1183 #undef TARGET_PASS_BY_REFERENCE
1184 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1185 #undef TARGET_ARG_PARTIAL_BYTES
1186 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1188 #undef TARGET_BUILD_BUILTIN_VA_LIST
1189 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1191 #undef TARGET_EXPAND_BUILTIN_VA_START
1192 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1194 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1195 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1197 #undef TARGET_EH_RETURN_FILTER_MODE
1198 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1200 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1201 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1203 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1204 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1206 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1207 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1209 #undef TARGET_HANDLE_OPTION
1210 #define TARGET_HANDLE_OPTION rs6000_handle_option
1212 #undef TARGET_DEFAULT_TARGET_FLAGS
1213 #define TARGET_DEFAULT_TARGET_FLAGS \
1216 #undef TARGET_STACK_PROTECT_FAIL
1217 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1219 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1220 The PowerPC architecture requires only weak consistency among
1221 processors--that is, memory accesses between processors need not be
1222 sequentially consistent and memory accesses among processors can occur
1223 in any order. The ability to order memory accesses weakly provides
1224 opportunities for more efficient use of the system bus. Unless a
1225 dependency exists, the 604e allows read operations to precede store
1227 #undef TARGET_RELAXED_ORDERING
1228 #define TARGET_RELAXED_ORDERING true
1231 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1232 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1235 /* Use a 32-bit anchor range. This leads to sequences like:
1237 addis tmp,anchor,high
1240 where tmp itself acts as an anchor, and can be shared between
1241 accesses to the same 64k page. */
1242 #undef TARGET_MIN_ANCHOR_OFFSET
1243 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1244 #undef TARGET_MAX_ANCHOR_OFFSET
1245 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1246 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1247 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1249 #undef TARGET_BUILTIN_RECIPROCAL
1250 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1252 #undef TARGET_EXPAND_TO_RTL_HOOK
1253 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1255 #undef TARGET_INSTANTIATE_DECLS
1256 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1258 struct gcc_target targetm = TARGET_INITIALIZER;
1261 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1264 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1266 /* The GPRs can hold any mode, but values bigger than one register
1267 cannot go past R31. */
1268 if (INT_REGNO_P (regno))
1269 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1271 /* The float registers can only hold floating modes and DImode.
1272 This excludes the 32-bit decimal float mode for now. */
1273 if (FP_REGNO_P (regno))
1275 ((SCALAR_FLOAT_MODE_P (mode)
1276 && (mode != TDmode || (regno % 2) == 0)
1277 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1278 || (GET_MODE_CLASS (mode) == MODE_INT
1279 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1280 || (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1281 && PAIRED_VECTOR_MODE (mode)));
1283 /* The CR register can only hold CC modes. */
1284 if (CR_REGNO_P (regno))
1285 return GET_MODE_CLASS (mode) == MODE_CC;
1287 if (XER_REGNO_P (regno))
1288 return mode == PSImode;
1290 /* AltiVec only in AldyVec registers. */
1291 if (ALTIVEC_REGNO_P (regno))
1292 return ALTIVEC_VECTOR_MODE (mode);
1294 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1295 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1298 /* We cannot put TImode anywhere except general register and it must be
1299 able to fit within the register set. */
1301 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1304 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1306 rs6000_init_hard_regno_mode_ok (void)
1310 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1311 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1312 if (rs6000_hard_regno_mode_ok (r, m))
1313 rs6000_hard_regno_mode_ok_p[m][r] = true;
1317 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1320 darwin_rs6000_override_options (void)
1322 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1324 rs6000_altivec_abi = 1;
1325 TARGET_ALTIVEC_VRSAVE = 1;
1326 if (DEFAULT_ABI == ABI_DARWIN)
1328 if (MACHO_DYNAMIC_NO_PIC_P)
1331 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1334 else if (flag_pic == 1)
1339 if (TARGET_64BIT && ! TARGET_POWERPC64)
1341 target_flags |= MASK_POWERPC64;
1342 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1346 rs6000_default_long_calls = 1;
1347 target_flags |= MASK_SOFT_FLOAT;
1350 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1352 if (!flag_mkernel && !flag_apple_kext
1354 && ! (target_flags_explicit & MASK_ALTIVEC))
1355 target_flags |= MASK_ALTIVEC;
1357 /* Unless the user (not the configurer) has explicitly overridden
1358 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1359 G4 unless targetting the kernel. */
1362 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1363 && ! (target_flags_explicit & MASK_ALTIVEC)
1364 && ! rs6000_select[1].string)
1366 target_flags |= MASK_ALTIVEC;
1371 /* If not otherwise specified by a target, make 'long double' equivalent to
1374 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1375 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1378 /* Override command line options. Mostly we process the processor
1379 type and sometimes adjust other TARGET_ options. */
1382 rs6000_override_options (const char *default_cpu)
1385 struct rs6000_cpu_select *ptr;
1388 /* Simplifications for entries below. */
1391 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1392 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1395 /* This table occasionally claims that a processor does not support
1396 a particular feature even though it does, but the feature is slower
1397 than the alternative. Thus, it shouldn't be relied on as a
1398 complete description of the processor's support.
1400 Please keep this list in order, and don't forget to update the
1401 documentation in invoke.texi when adding a new processor or
1405 const char *const name; /* Canonical processor name. */
1406 const enum processor_type processor; /* Processor type enum value. */
1407 const int target_enable; /* Target flags to enable. */
1408 } const processor_target_table[]
1409 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1410 {"403", PROCESSOR_PPC403,
1411 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1412 {"405", PROCESSOR_PPC405,
1413 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1414 {"405fp", PROCESSOR_PPC405,
1415 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1416 {"440", PROCESSOR_PPC440,
1417 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1418 {"440fp", PROCESSOR_PPC440,
1419 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1420 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1421 {"601", PROCESSOR_PPC601,
1422 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1423 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1424 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1425 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1426 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1427 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1428 {"620", PROCESSOR_PPC620,
1429 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1430 {"630", PROCESSOR_PPC630,
1431 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1432 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1433 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1434 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1435 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1436 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1437 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1438 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1439 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1440 /* 8548 has a dummy entry for now. */
1441 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1442 {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1443 {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
1444 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1445 {"970", PROCESSOR_POWER4,
1446 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1447 {"cell", PROCESSOR_CELL,
1448 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1449 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1450 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1451 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1452 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1453 {"G5", PROCESSOR_POWER4,
1454 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1455 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1456 {"power2", PROCESSOR_POWER,
1457 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1458 {"power3", PROCESSOR_PPC630,
1459 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1460 {"power4", PROCESSOR_POWER4,
1461 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1462 {"power5", PROCESSOR_POWER5,
1463 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1464 | MASK_MFCRF | MASK_POPCNTB},
1465 {"power5+", PROCESSOR_POWER5,
1466 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1467 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1468 {"power6", PROCESSOR_POWER6,
1469 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1470 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1471 {"power6x", PROCESSOR_POWER6,
1472 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1473 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1474 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1475 {"powerpc64", PROCESSOR_POWERPC64,
1476 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1477 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1478 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1479 {"rios2", PROCESSOR_RIOS2,
1480 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1481 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1482 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1483 {"rs64", PROCESSOR_RS64A,
1484 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1487 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1489 /* Some OSs don't support saving the high part of 64-bit registers on
1490 context switch. Other OSs don't support saving Altivec registers.
1491 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1492 settings; if the user wants either, the user must explicitly specify
1493 them and we won't interfere with the user's specification. */
1496 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1497 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1498 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1499 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1500 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1503 rs6000_init_hard_regno_mode_ok ();
1505 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1506 #ifdef OS_MISSING_POWERPC64
1507 if (OS_MISSING_POWERPC64)
1508 set_masks &= ~MASK_POWERPC64;
1510 #ifdef OS_MISSING_ALTIVEC
1511 if (OS_MISSING_ALTIVEC)
1512 set_masks &= ~MASK_ALTIVEC;
1515 /* Don't override by the processor default if given explicitly. */
1516 set_masks &= ~target_flags_explicit;
1518 /* Identify the processor type. */
1519 rs6000_select[0].string = default_cpu;
1520 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1522 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1524 ptr = &rs6000_select[i];
1525 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1527 for (j = 0; j < ptt_size; j++)
1528 if (! strcmp (ptr->string, processor_target_table[j].name))
1530 if (ptr->set_tune_p)
1531 rs6000_cpu = processor_target_table[j].processor;
1533 if (ptr->set_arch_p)
1535 target_flags &= ~set_masks;
1536 target_flags |= (processor_target_table[j].target_enable
1543 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1550 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3)
1553 error ("AltiVec not supported in this target");
1555 error ("Spe not supported in this target");
1558 /* If we are optimizing big endian systems for space, use the load/store
1559 multiple and string instructions. */
1560 if (BYTES_BIG_ENDIAN && optimize_size)
1561 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1563 /* Don't allow -mmultiple or -mstring on little endian systems
1564 unless the cpu is a 750, because the hardware doesn't support the
1565 instructions used in little endian mode, and causes an alignment
1566 trap. The 750 does not cause an alignment trap (except when the
1567 target is unaligned). */
1569 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1571 if (TARGET_MULTIPLE)
1573 target_flags &= ~MASK_MULTIPLE;
1574 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1575 warning (0, "-mmultiple is not supported on little endian systems");
1580 target_flags &= ~MASK_STRING;
1581 if ((target_flags_explicit & MASK_STRING) != 0)
1582 warning (0, "-mstring is not supported on little endian systems");
1586 /* Set debug flags */
1587 if (rs6000_debug_name)
1589 if (! strcmp (rs6000_debug_name, "all"))
1590 rs6000_debug_stack = rs6000_debug_arg = 1;
1591 else if (! strcmp (rs6000_debug_name, "stack"))
1592 rs6000_debug_stack = 1;
1593 else if (! strcmp (rs6000_debug_name, "arg"))
1594 rs6000_debug_arg = 1;
1596 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1599 if (rs6000_traceback_name)
1601 if (! strncmp (rs6000_traceback_name, "full", 4))
1602 rs6000_traceback = traceback_full;
1603 else if (! strncmp (rs6000_traceback_name, "part", 4))
1604 rs6000_traceback = traceback_part;
1605 else if (! strncmp (rs6000_traceback_name, "no", 2))
1606 rs6000_traceback = traceback_none;
1608 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1609 rs6000_traceback_name);
1612 if (!rs6000_explicit_options.long_double)
1613 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1615 #ifndef POWERPC_LINUX
1616 if (!rs6000_explicit_options.ieee)
1617 rs6000_ieeequad = 1;
1620 /* Enable Altivec ABI for AIX -maltivec. */
1621 if (TARGET_XCOFF && TARGET_ALTIVEC)
1622 rs6000_altivec_abi = 1;
1624 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1625 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1626 be explicitly overridden in either case. */
1629 if (!rs6000_explicit_options.altivec_abi
1630 && (TARGET_64BIT || TARGET_ALTIVEC))
1631 rs6000_altivec_abi = 1;
1633 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1634 if (!rs6000_explicit_options.vrsave)
1635 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
1638 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1639 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1641 rs6000_darwin64_abi = 1;
1643 darwin_one_byte_bool = 1;
1645 /* Default to natural alignment, for better performance. */
1646 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1649 /* Place FP constants in the constant pool instead of TOC
1650 if section anchors enabled. */
1651 if (flag_section_anchors)
1652 TARGET_NO_FP_IN_TOC = 1;
1654 /* Handle -mtls-size option. */
1655 rs6000_parse_tls_size_option ();
1657 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1658 SUBTARGET_OVERRIDE_OPTIONS;
1660 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1661 SUBSUBTARGET_OVERRIDE_OPTIONS;
1663 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1664 SUB3TARGET_OVERRIDE_OPTIONS;
1669 /* The e500 does not have string instructions, and we set
1670 MASK_STRING above when optimizing for size. */
1671 if ((target_flags & MASK_STRING) != 0)
1672 target_flags = target_flags & ~MASK_STRING;
1674 else if (rs6000_select[1].string != NULL)
1676 /* For the powerpc-eabispe configuration, we set all these by
1677 default, so let's unset them if we manually set another
1678 CPU that is not the E500. */
1679 if (!rs6000_explicit_options.spe_abi)
1681 if (!rs6000_explicit_options.spe)
1683 if (!rs6000_explicit_options.float_gprs)
1684 rs6000_float_gprs = 0;
1685 if (!rs6000_explicit_options.isel)
1689 /* Detect invalid option combinations with E500. */
1692 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1693 && rs6000_cpu != PROCESSOR_POWER5
1694 && rs6000_cpu != PROCESSOR_POWER6
1695 && rs6000_cpu != PROCESSOR_CELL);
1696 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1697 || rs6000_cpu == PROCESSOR_POWER5);
1698 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1699 || rs6000_cpu == PROCESSOR_POWER5
1700 || rs6000_cpu == PROCESSOR_POWER6);
1702 rs6000_sched_restricted_insns_priority
1703 = (rs6000_sched_groups ? 1 : 0);
1705 /* Handle -msched-costly-dep option. */
1706 rs6000_sched_costly_dep
1707 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1709 if (rs6000_sched_costly_dep_str)
1711 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1712 rs6000_sched_costly_dep = no_dep_costly;
1713 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1714 rs6000_sched_costly_dep = all_deps_costly;
1715 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1716 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1717 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1718 rs6000_sched_costly_dep = store_to_load_dep_costly;
1720 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1723 /* Handle -minsert-sched-nops option. */
1724 rs6000_sched_insert_nops
1725 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1727 if (rs6000_sched_insert_nops_str)
1729 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1730 rs6000_sched_insert_nops = sched_finish_none;
1731 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1732 rs6000_sched_insert_nops = sched_finish_pad_groups;
1733 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1734 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1736 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1739 #ifdef TARGET_REGNAMES
1740 /* If the user desires alternate register names, copy in the
1741 alternate names now. */
1742 if (TARGET_REGNAMES)
1743 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1746 /* Set aix_struct_return last, after the ABI is determined.
1747 If -maix-struct-return or -msvr4-struct-return was explicitly
1748 used, don't override with the ABI default. */
1749 if (!rs6000_explicit_options.aix_struct_ret)
1750 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1752 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1753 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1756 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1758 /* We can only guarantee the availability of DI pseudo-ops when
1759 assembling for 64-bit targets. */
1762 targetm.asm_out.aligned_op.di = NULL;
1763 targetm.asm_out.unaligned_op.di = NULL;
1766 /* Set branch target alignment, if not optimizing for size. */
1769 /* Cell wants to be aligned 8byte for dual issue. */
1770 if (rs6000_cpu == PROCESSOR_CELL)
1772 if (align_functions <= 0)
1773 align_functions = 8;
1774 if (align_jumps <= 0)
1776 if (align_loops <= 0)
1779 if (rs6000_align_branch_targets)
1781 if (align_functions <= 0)
1782 align_functions = 16;
1783 if (align_jumps <= 0)
1785 if (align_loops <= 0)
1788 if (align_jumps_max_skip <= 0)
1789 align_jumps_max_skip = 15;
1790 if (align_loops_max_skip <= 0)
1791 align_loops_max_skip = 15;
1794 /* Arrange to save and restore machine status around nested functions. */
1795 init_machine_status = rs6000_init_machine_status;
1797 /* We should always be splitting complex arguments, but we can't break
1798 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1799 if (DEFAULT_ABI != ABI_AIX)
1800 targetm.calls.split_complex_arg = NULL;
1802 /* Initialize rs6000_cost with the appropriate target costs. */
1804 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1808 case PROCESSOR_RIOS1:
1809 rs6000_cost = &rios1_cost;
1812 case PROCESSOR_RIOS2:
1813 rs6000_cost = &rios2_cost;
1816 case PROCESSOR_RS64A:
1817 rs6000_cost = &rs64a_cost;
1820 case PROCESSOR_MPCCORE:
1821 rs6000_cost = &mpccore_cost;
1824 case PROCESSOR_PPC403:
1825 rs6000_cost = &ppc403_cost;
1828 case PROCESSOR_PPC405:
1829 rs6000_cost = &ppc405_cost;
1832 case PROCESSOR_PPC440:
1833 rs6000_cost = &ppc440_cost;
1836 case PROCESSOR_PPC601:
1837 rs6000_cost = &ppc601_cost;
1840 case PROCESSOR_PPC603:
1841 rs6000_cost = &ppc603_cost;
1844 case PROCESSOR_PPC604:
1845 rs6000_cost = &ppc604_cost;
1848 case PROCESSOR_PPC604e:
1849 rs6000_cost = &ppc604e_cost;
1852 case PROCESSOR_PPC620:
1853 rs6000_cost = &ppc620_cost;
1856 case PROCESSOR_PPC630:
1857 rs6000_cost = &ppc630_cost;
1860 case PROCESSOR_CELL:
1861 rs6000_cost = &ppccell_cost;
1864 case PROCESSOR_PPC750:
1865 case PROCESSOR_PPC7400:
1866 rs6000_cost = &ppc750_cost;
1869 case PROCESSOR_PPC7450:
1870 rs6000_cost = &ppc7450_cost;
1873 case PROCESSOR_PPC8540:
1874 rs6000_cost = &ppc8540_cost;
1877 case PROCESSOR_PPCE300C2:
1878 case PROCESSOR_PPCE300C3:
1879 rs6000_cost = &ppce300c2c3_cost;
1882 case PROCESSOR_POWER4:
1883 case PROCESSOR_POWER5:
1884 rs6000_cost = &power4_cost;
1887 case PROCESSOR_POWER6:
1888 rs6000_cost = &power6_cost;
1895 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1896 set_param_value ("simultaneous-prefetches",
1897 rs6000_cost->simultaneous_prefetches);
1898 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1899 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1900 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1901 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1902 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1903 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1905 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1906 can be optimized to ap = __builtin_next_arg (0). */
1907 if (DEFAULT_ABI != ABI_V4)
1908 targetm.expand_builtin_va_start = NULL;
1911 /* Implement targetm.vectorize.builtin_mask_for_load. */
1913 rs6000_builtin_mask_for_load (void)
1916 return altivec_builtin_mask_for_load;
1921 /* Implement targetm.vectorize.builtin_conversion. */
1923 rs6000_builtin_conversion (enum tree_code code, tree type)
1925 if (!TARGET_ALTIVEC)
1931 switch (TYPE_MODE (type))
1934 return TYPE_UNSIGNED (type) ?
1935 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1936 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1945 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1947 rs6000_builtin_mul_widen_even (tree type)
1949 if (!TARGET_ALTIVEC)
1952 switch (TYPE_MODE (type))
1955 return TYPE_UNSIGNED (type) ?
1956 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1957 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1960 return TYPE_UNSIGNED (type) ?
1961 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1962 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1968 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1970 rs6000_builtin_mul_widen_odd (tree type)
1972 if (!TARGET_ALTIVEC)
1975 switch (TYPE_MODE (type))
1978 return TYPE_UNSIGNED (type) ?
1979 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1980 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1983 return TYPE_UNSIGNED (type) ?
1984 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1985 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1992 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1993 after applying N number of iterations. This routine does not determine
1994 how may iterations are required to reach desired alignment. */
1997 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
2004 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
2007 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
2017 /* Assuming that all other types are naturally aligned. CHECKME! */
2022 /* Handle generic options of the form -mfoo=yes/no.
2023 NAME is the option name.
2024 VALUE is the option value.
2025 FLAG is the pointer to the flag where to store a 1 or 0, depending on
2026 whether the option value is 'yes' or 'no' respectively. */
2028 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
2032 else if (!strcmp (value, "yes"))
2034 else if (!strcmp (value, "no"))
2037 error ("unknown -m%s= option specified: '%s'", name, value);
2040 /* Validate and record the size specified with the -mtls-size option. */
2043 rs6000_parse_tls_size_option (void)
2045 if (rs6000_tls_size_string == 0)
2047 else if (strcmp (rs6000_tls_size_string, "16") == 0)
2048 rs6000_tls_size = 16;
2049 else if (strcmp (rs6000_tls_size_string, "32") == 0)
2050 rs6000_tls_size = 32;
2051 else if (strcmp (rs6000_tls_size_string, "64") == 0)
2052 rs6000_tls_size = 64;
2054 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
2058 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
2060 if (DEFAULT_ABI == ABI_DARWIN)
2061 /* The Darwin libraries never set errno, so we might as well
2062 avoid calling them when that's the only reason we would. */
2063 flag_errno_math = 0;
2065 /* Double growth factor to counter reduced min jump length. */
2066 set_param_value ("max-grow-copy-bb-insns", 16);
2068 /* Enable section anchors by default.
2069 Skip section anchors for Objective C and Objective C++
2070 until front-ends fixed. */
2071 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
2072 flag_section_anchors = 1;
2075 /* Implement TARGET_HANDLE_OPTION. */
2078 rs6000_handle_option (size_t code, const char *arg, int value)
2083 target_flags &= ~(MASK_POWER | MASK_POWER2
2084 | MASK_MULTIPLE | MASK_STRING);
2085 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2086 | MASK_MULTIPLE | MASK_STRING);
2088 case OPT_mno_powerpc:
2089 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2090 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2091 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2092 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2095 target_flags &= ~MASK_MINIMAL_TOC;
2096 TARGET_NO_FP_IN_TOC = 0;
2097 TARGET_NO_SUM_IN_TOC = 0;
2098 target_flags_explicit |= MASK_MINIMAL_TOC;
2099 #ifdef TARGET_USES_SYSV4_OPT
2100 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2101 just the same as -mminimal-toc. */
2102 target_flags |= MASK_MINIMAL_TOC;
2103 target_flags_explicit |= MASK_MINIMAL_TOC;
2107 #ifdef TARGET_USES_SYSV4_OPT
2109 /* Make -mtoc behave like -mminimal-toc. */
2110 target_flags |= MASK_MINIMAL_TOC;
2111 target_flags_explicit |= MASK_MINIMAL_TOC;
2115 #ifdef TARGET_USES_AIX64_OPT
2120 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2121 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2122 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2125 #ifdef TARGET_USES_AIX64_OPT
2130 target_flags &= ~MASK_POWERPC64;
2131 target_flags_explicit |= MASK_POWERPC64;
2134 case OPT_minsert_sched_nops_:
2135 rs6000_sched_insert_nops_str = arg;
2138 case OPT_mminimal_toc:
2141 TARGET_NO_FP_IN_TOC = 0;
2142 TARGET_NO_SUM_IN_TOC = 0;
2149 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2150 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2157 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2158 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2162 case OPT_mpowerpc_gpopt:
2163 case OPT_mpowerpc_gfxopt:
2166 target_flags |= MASK_POWERPC;
2167 target_flags_explicit |= MASK_POWERPC;
2171 case OPT_maix_struct_return:
2172 case OPT_msvr4_struct_return:
2173 rs6000_explicit_options.aix_struct_ret = true;
2177 rs6000_explicit_options.vrsave = true;
2178 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2182 rs6000_explicit_options.isel = true;
2183 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2187 rs6000_explicit_options.spe = true;
2188 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2192 rs6000_debug_name = arg;
2195 #ifdef TARGET_USES_SYSV4_OPT
2197 rs6000_abi_name = arg;
2201 rs6000_sdata_name = arg;
2204 case OPT_mtls_size_:
2205 rs6000_tls_size_string = arg;
2208 case OPT_mrelocatable:
2211 target_flags |= MASK_MINIMAL_TOC;
2212 target_flags_explicit |= MASK_MINIMAL_TOC;
2213 TARGET_NO_FP_IN_TOC = 1;
2217 case OPT_mrelocatable_lib:
2220 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2221 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2222 TARGET_NO_FP_IN_TOC = 1;
2226 target_flags &= ~MASK_RELOCATABLE;
2227 target_flags_explicit |= MASK_RELOCATABLE;
2233 if (!strcmp (arg, "altivec"))
2235 rs6000_explicit_options.altivec_abi = true;
2236 rs6000_altivec_abi = 1;
2238 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2241 else if (! strcmp (arg, "no-altivec"))
2243 rs6000_explicit_options.altivec_abi = true;
2244 rs6000_altivec_abi = 0;
2246 else if (! strcmp (arg, "spe"))
2248 rs6000_explicit_options.spe_abi = true;
2250 rs6000_altivec_abi = 0;
2251 if (!TARGET_SPE_ABI)
2252 error ("not configured for ABI: '%s'", arg);
2254 else if (! strcmp (arg, "no-spe"))
2256 rs6000_explicit_options.spe_abi = true;
2260 /* These are here for testing during development only, do not
2261 document in the manual please. */
2262 else if (! strcmp (arg, "d64"))
2264 rs6000_darwin64_abi = 1;
2265 warning (0, "Using darwin64 ABI");
2267 else if (! strcmp (arg, "d32"))
2269 rs6000_darwin64_abi = 0;
2270 warning (0, "Using old darwin ABI");
2273 else if (! strcmp (arg, "ibmlongdouble"))
2275 rs6000_explicit_options.ieee = true;
2276 rs6000_ieeequad = 0;
2277 warning (0, "Using IBM extended precision long double");
2279 else if (! strcmp (arg, "ieeelongdouble"))
2281 rs6000_explicit_options.ieee = true;
2282 rs6000_ieeequad = 1;
2283 warning (0, "Using IEEE extended precision long double");
2288 error ("unknown ABI specified: '%s'", arg);
2294 rs6000_select[1].string = arg;
2298 rs6000_select[2].string = arg;
2301 case OPT_mtraceback_:
2302 rs6000_traceback_name = arg;
2305 case OPT_mfloat_gprs_:
2306 rs6000_explicit_options.float_gprs = true;
2307 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2308 rs6000_float_gprs = 1;
2309 else if (! strcmp (arg, "double"))
2310 rs6000_float_gprs = 2;
2311 else if (! strcmp (arg, "no"))
2312 rs6000_float_gprs = 0;
2315 error ("invalid option for -mfloat-gprs: '%s'", arg);
2320 case OPT_mlong_double_:
2321 rs6000_explicit_options.long_double = true;
2322 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2323 if (value != 64 && value != 128)
2325 error ("Unknown switch -mlong-double-%s", arg);
2326 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2330 rs6000_long_double_type_size = value;
2333 case OPT_msched_costly_dep_:
2334 rs6000_sched_costly_dep_str = arg;
2338 rs6000_explicit_options.alignment = true;
2339 if (! strcmp (arg, "power"))
2341 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2342 some C library functions, so warn about it. The flag may be
2343 useful for performance studies from time to time though, so
2344 don't disable it entirely. */
2345 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2346 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2347 " it is incompatible with the installed C and C++ libraries");
2348 rs6000_alignment_flags = MASK_ALIGN_POWER;
2350 else if (! strcmp (arg, "natural"))
2351 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2354 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2362 /* Do anything needed at the start of the asm file. */
2365 rs6000_file_start (void)
2369 const char *start = buffer;
2370 struct rs6000_cpu_select *ptr;
2371 const char *default_cpu = TARGET_CPU_DEFAULT;
2372 FILE *file = asm_out_file;
2374 default_file_start ();
2376 #ifdef TARGET_BI_ARCH
2377 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2381 if (flag_verbose_asm)
2383 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2384 rs6000_select[0].string = default_cpu;
2386 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2388 ptr = &rs6000_select[i];
2389 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2391 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2396 if (PPC405_ERRATUM77)
2398 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2402 #ifdef USING_ELFOS_H
2403 switch (rs6000_sdata)
2405 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2406 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2407 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2408 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2411 if (rs6000_sdata && g_switch_value)
2413 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2423 #ifdef HAVE_AS_GNU_ATTRIBUTE
2424 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2426 fprintf (file, "\t.gnu_attribute 4, %d\n",
2427 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2428 fprintf (file, "\t.gnu_attribute 8, %d\n",
2429 (TARGET_ALTIVEC_ABI ? 2
2430 : TARGET_SPE_ABI ? 3
2435 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2437 switch_to_section (toc_section);
2438 switch_to_section (text_section);
2443 /* Return nonzero if this function is known to have a null epilogue. */
2446 direct_return (void)
2448 if (reload_completed)
2450 rs6000_stack_t *info = rs6000_stack_info ();
2452 if (info->first_gp_reg_save == 32
2453 && info->first_fp_reg_save == 64
2454 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2455 && ! info->lr_save_p
2456 && ! info->cr_save_p
2457 && info->vrsave_mask == 0
2465 /* Return the number of instructions it takes to form a constant in an
2466 integer register. */
2469 num_insns_constant_wide (HOST_WIDE_INT value)
2471 /* signed constant loadable with {cal|addi} */
2472 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2475 /* constant loadable with {cau|addis} */
2476 else if ((value & 0xffff) == 0
2477 && (value >> 31 == -1 || value >> 31 == 0))
2480 #if HOST_BITS_PER_WIDE_INT == 64
2481 else if (TARGET_POWERPC64)
2483 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2484 HOST_WIDE_INT high = value >> 31;
2486 if (high == 0 || high == -1)
2492 return num_insns_constant_wide (high) + 1;
2494 return (num_insns_constant_wide (high)
2495 + num_insns_constant_wide (low) + 1);
2504 num_insns_constant (rtx op, enum machine_mode mode)
2506 HOST_WIDE_INT low, high;
2508 switch (GET_CODE (op))
2511 #if HOST_BITS_PER_WIDE_INT == 64
2512 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2513 && mask64_operand (op, mode))
2517 return num_insns_constant_wide (INTVAL (op));
2520 if (mode == SFmode || mode == SDmode)
2525 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2526 if (DECIMAL_FLOAT_MODE_P (mode))
2527 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
2529 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2530 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2533 if (mode == VOIDmode || mode == DImode)
2535 high = CONST_DOUBLE_HIGH (op);
2536 low = CONST_DOUBLE_LOW (op);
2543 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2544 if (DECIMAL_FLOAT_MODE_P (mode))
2545 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2547 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2548 high = l[WORDS_BIG_ENDIAN == 0];
2549 low = l[WORDS_BIG_ENDIAN != 0];
2553 return (num_insns_constant_wide (low)
2554 + num_insns_constant_wide (high));
2557 if ((high == 0 && low >= 0)
2558 || (high == -1 && low < 0))
2559 return num_insns_constant_wide (low);
2561 else if (mask64_operand (op, mode))
2565 return num_insns_constant_wide (high) + 1;
2568 return (num_insns_constant_wide (high)
2569 + num_insns_constant_wide (low) + 1);
2577 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2578 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2579 corresponding element of the vector, but for V4SFmode and V2SFmode,
2580 the corresponding "float" is interpreted as an SImode integer. */
2582 static HOST_WIDE_INT
2583 const_vector_elt_as_int (rtx op, unsigned int elt)
2585 rtx tmp = CONST_VECTOR_ELT (op, elt);
2586 if (GET_MODE (op) == V4SFmode
2587 || GET_MODE (op) == V2SFmode)
2588 tmp = gen_lowpart (SImode, tmp);
2589 return INTVAL (tmp);
2592 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2593 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2594 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2595 all items are set to the same value and contain COPIES replicas of the
2596 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2597 operand and the others are set to the value of the operand's msb. */
2600 vspltis_constant (rtx op, unsigned step, unsigned copies)
2602 enum machine_mode mode = GET_MODE (op);
2603 enum machine_mode inner = GET_MODE_INNER (mode);
2606 unsigned nunits = GET_MODE_NUNITS (mode);
2607 unsigned bitsize = GET_MODE_BITSIZE (inner);
2608 unsigned mask = GET_MODE_MASK (inner);
2610 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2611 HOST_WIDE_INT splat_val = val;
2612 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2614 /* Construct the value to be splatted, if possible. If not, return 0. */
2615 for (i = 2; i <= copies; i *= 2)
2617 HOST_WIDE_INT small_val;
2619 small_val = splat_val >> bitsize;
2621 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2623 splat_val = small_val;
2626 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2627 if (EASY_VECTOR_15 (splat_val))
2630 /* Also check if we can splat, and then add the result to itself. Do so if
2631 the value is positive, of if the splat instruction is using OP's mode;
2632 for splat_val < 0, the splat and the add should use the same mode. */
2633 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2634 && (splat_val >= 0 || (step == 1 && copies == 1)))
2640 /* Check if VAL is present in every STEP-th element, and the
2641 other elements are filled with its most significant bit. */
2642 for (i = 0; i < nunits - 1; ++i)
2644 HOST_WIDE_INT desired_val;
2645 if (((i + 1) & (step - 1)) == 0)
2648 desired_val = msb_val;
2650 if (desired_val != const_vector_elt_as_int (op, i))
2658 /* Return true if OP is of the given MODE and can be synthesized
2659 with a vspltisb, vspltish or vspltisw. */
2662 easy_altivec_constant (rtx op, enum machine_mode mode)
2664 unsigned step, copies;
2666 if (mode == VOIDmode)
2667 mode = GET_MODE (op);
2668 else if (mode != GET_MODE (op))
2671 /* Start with a vspltisw. */
2672 step = GET_MODE_NUNITS (mode) / 4;
2675 if (vspltis_constant (op, step, copies))
2678 /* Then try with a vspltish. */
2684 if (vspltis_constant (op, step, copies))
2687 /* And finally a vspltisb. */
2693 if (vspltis_constant (op, step, copies))
2699 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2700 result is OP. Abort if it is not possible. */
2703 gen_easy_altivec_constant (rtx op)
2705 enum machine_mode mode = GET_MODE (op);
2706 int nunits = GET_MODE_NUNITS (mode);
2707 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2708 unsigned step = nunits / 4;
2709 unsigned copies = 1;
2711 /* Start with a vspltisw. */
2712 if (vspltis_constant (op, step, copies))
2713 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2715 /* Then try with a vspltish. */
2721 if (vspltis_constant (op, step, copies))
2722 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2724 /* And finally a vspltisb. */
2730 if (vspltis_constant (op, step, copies))
2731 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2737 output_vec_const_move (rtx *operands)
2740 enum machine_mode mode;
2745 mode = GET_MODE (dest);
2750 if (zero_constant (vec, mode))
2751 return "vxor %0,%0,%0";
2753 splat_vec = gen_easy_altivec_constant (vec);
2754 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2755 operands[1] = XEXP (splat_vec, 0);
2756 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2759 switch (GET_MODE (splat_vec))
2762 return "vspltisw %0,%1";
2765 return "vspltish %0,%1";
2768 return "vspltisb %0,%1";
2775 gcc_assert (TARGET_SPE);
2777 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2778 pattern of V1DI, V4HI, and V2SF.
2780 FIXME: We should probably return # and add post reload
2781 splitters for these, but this way is so easy ;-). */
2782 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2783 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2784 operands[1] = CONST_VECTOR_ELT (vec, 0);
2785 operands[2] = CONST_VECTOR_ELT (vec, 1);
2787 return "li %0,%1\n\tevmergelo %0,%0,%0";
2789 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2792 /* Initialize TARGET of vector PAIRED to VALS. */
2795 paired_expand_vector_init (rtx target, rtx vals)
2797 enum machine_mode mode = GET_MODE (target);
2798 int n_elts = GET_MODE_NUNITS (mode);
2800 rtx x, new, tmp, constant_op, op1, op2;
2803 for (i = 0; i < n_elts; ++i)
2805 x = XVECEXP (vals, 0, i);
2806 if (!CONSTANT_P (x))
2811 /* Load from constant pool. */
2812 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2818 /* The vector is initialized only with non-constants. */
2819 new = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
2820 XVECEXP (vals, 0, 1));
2822 emit_move_insn (target, new);
2826 /* One field is non-constant and the other one is a constant. Load the
2827 constant from the constant pool and use ps_merge instruction to
2828 construct the whole vector. */
2829 op1 = XVECEXP (vals, 0, 0);
2830 op2 = XVECEXP (vals, 0, 1);
2832 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
2834 tmp = gen_reg_rtx (GET_MODE (constant_op));
2835 emit_move_insn (tmp, constant_op);
2837 if (CONSTANT_P (op1))
2838 new = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
2840 new = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
2842 emit_move_insn (target, new);
2846 paired_expand_vector_move (rtx operands[])
2848 rtx op0 = operands[0], op1 = operands[1];
2850 emit_move_insn (op0, op1);
2853 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
2854 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
2855 operands for the relation operation COND. This is a recursive
2859 paired_emit_vector_compare (enum rtx_code rcode,
2860 rtx dest, rtx op0, rtx op1,
2861 rtx cc_op0, rtx cc_op1)
2863 rtx tmp = gen_reg_rtx (V2SFmode);
2864 rtx tmp1, max, min, equal_zero;
2866 gcc_assert (TARGET_PAIRED_FLOAT);
2867 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
2873 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
2877 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
2878 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
2882 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
2885 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
2888 tmp1 = gen_reg_rtx (V2SFmode);
2889 max = gen_reg_rtx (V2SFmode);
2890 min = gen_reg_rtx (V2SFmode);
2891 equal_zero = gen_reg_rtx (V2SFmode);
2893 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
2894 emit_insn (gen_selv2sf4
2895 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
2896 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
2897 emit_insn (gen_selv2sf4
2898 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
2899 emit_insn (gen_subv2sf3 (tmp1, min, max));
2900 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
2903 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
2906 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
2909 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
2912 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
2915 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
2924 /* Emit vector conditional expression.
2925 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
2926 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
2929 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
2930 rtx cond, rtx cc_op0, rtx cc_op1)
2932 enum rtx_code rcode = GET_CODE (cond);
2934 if (!TARGET_PAIRED_FLOAT)
2937 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
2942 /* Initialize vector TARGET to VALS. */
2945 rs6000_expand_vector_init (rtx target, rtx vals)
2947 enum machine_mode mode = GET_MODE (target);
2948 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2949 int n_elts = GET_MODE_NUNITS (mode);
2950 int n_var = 0, one_var = -1;
2951 bool all_same = true, all_const_zero = true;
2955 for (i = 0; i < n_elts; ++i)
2957 x = XVECEXP (vals, 0, i);
2958 if (!CONSTANT_P (x))
2959 ++n_var, one_var = i;
2960 else if (x != CONST0_RTX (inner_mode))
2961 all_const_zero = false;
2963 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2969 if (mode != V4SFmode && all_const_zero)
2971 /* Zero register. */
2972 emit_insn (gen_rtx_SET (VOIDmode, target,
2973 gen_rtx_XOR (mode, target, target)));
2976 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2978 /* Splat immediate. */
2979 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2983 ; /* Splat vector element. */
2986 /* Load from constant pool. */
2987 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2992 /* Store value to stack temp. Load vector element. Splat. */
2995 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2996 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2997 XVECEXP (vals, 0, 0));
2998 x = gen_rtx_UNSPEC (VOIDmode,
2999 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3000 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3002 gen_rtx_SET (VOIDmode,
3005 x = gen_rtx_VEC_SELECT (inner_mode, target,
3006 gen_rtx_PARALLEL (VOIDmode,
3007 gen_rtvec (1, const0_rtx)));
3008 emit_insn (gen_rtx_SET (VOIDmode, target,
3009 gen_rtx_VEC_DUPLICATE (mode, x)));
3013 /* One field is non-constant. Load constant then overwrite
3017 rtx copy = copy_rtx (vals);
3019 /* Load constant part of vector, substitute neighboring value for
3021 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
3022 rs6000_expand_vector_init (target, copy);
3024 /* Insert variable. */
3025 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
3029 /* Construct the vector in memory one field at a time
3030 and load the whole vector. */
3031 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3032 for (i = 0; i < n_elts; i++)
3033 emit_move_insn (adjust_address_nv (mem, inner_mode,
3034 i * GET_MODE_SIZE (inner_mode)),
3035 XVECEXP (vals, 0, i));
3036 emit_move_insn (target, mem);
3039 /* Set field ELT of TARGET to VAL. */
3042 rs6000_expand_vector_set (rtx target, rtx val, int elt)
3044 enum machine_mode mode = GET_MODE (target);
3045 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3046 rtx reg = gen_reg_rtx (mode);
3048 int width = GET_MODE_SIZE (inner_mode);
3051 /* Load single variable value. */
3052 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
3053 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
3054 x = gen_rtx_UNSPEC (VOIDmode,
3055 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3056 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3058 gen_rtx_SET (VOIDmode,
3062 /* Linear sequence. */
3063 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
3064 for (i = 0; i < 16; ++i)
3065 XVECEXP (mask, 0, i) = GEN_INT (i);
3067 /* Set permute mask to insert element into target. */
3068 for (i = 0; i < width; ++i)
3069 XVECEXP (mask, 0, elt*width + i)
3070 = GEN_INT (i + 0x10);
3071 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
3072 x = gen_rtx_UNSPEC (mode,
3073 gen_rtvec (3, target, reg,
3074 force_reg (V16QImode, x)),
3076 emit_insn (gen_rtx_SET (VOIDmode, target, x));
3079 /* Extract field ELT from VEC into TARGET. */
3082 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
3084 enum machine_mode mode = GET_MODE (vec);
3085 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3088 /* Allocate mode-sized buffer. */
3089 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3091 /* Add offset to field within buffer matching vector element. */
3092 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
3094 /* Store single field into mode-sized buffer. */
3095 x = gen_rtx_UNSPEC (VOIDmode,
3096 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
3097 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3099 gen_rtx_SET (VOIDmode,
3102 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
3105 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3106 implement ANDing by the mask IN. */
3108 build_mask64_2_operands (rtx in, rtx *out)
3110 #if HOST_BITS_PER_WIDE_INT >= 64
3111 unsigned HOST_WIDE_INT c, lsb, m1, m2;
3114 gcc_assert (GET_CODE (in) == CONST_INT);
3119 /* Assume c initially something like 0x00fff000000fffff. The idea
3120 is to rotate the word so that the middle ^^^^^^ group of zeros
3121 is at the MS end and can be cleared with an rldicl mask. We then
3122 rotate back and clear off the MS ^^ group of zeros with a
3124 c = ~c; /* c == 0xff000ffffff00000 */
3125 lsb = c & -c; /* lsb == 0x0000000000100000 */
3126 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
3127 c = ~c; /* c == 0x00fff000000fffff */
3128 c &= -lsb; /* c == 0x00fff00000000000 */
3129 lsb = c & -c; /* lsb == 0x0000100000000000 */
3130 c = ~c; /* c == 0xff000fffffffffff */
3131 c &= -lsb; /* c == 0xff00000000000000 */
3133 while ((lsb >>= 1) != 0)
3134 shift++; /* shift == 44 on exit from loop */
3135 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
3136 m1 = ~m1; /* m1 == 0x000000ffffffffff */
3137 m2 = ~c; /* m2 == 0x00ffffffffffffff */
3141 /* Assume c initially something like 0xff000f0000000000. The idea
3142 is to rotate the word so that the ^^^ middle group of zeros
3143 is at the LS end and can be cleared with an rldicr mask. We then
3144 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3146 lsb = c & -c; /* lsb == 0x0000010000000000 */
3147 m2 = -lsb; /* m2 == 0xffffff0000000000 */
3148 c = ~c; /* c == 0x00fff0ffffffffff */
3149 c &= -lsb; /* c == 0x00fff00000000000 */
3150 lsb = c & -c; /* lsb == 0x0000100000000000 */
3151 c = ~c; /* c == 0xff000fffffffffff */
3152 c &= -lsb; /* c == 0xff00000000000000 */
3154 while ((lsb >>= 1) != 0)
3155 shift++; /* shift == 44 on exit from loop */
3156 m1 = ~c; /* m1 == 0x00ffffffffffffff */
3157 m1 >>= shift; /* m1 == 0x0000000000000fff */
3158 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
3161 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3162 masks will be all 1's. We are guaranteed more than one transition. */
3163 out[0] = GEN_INT (64 - shift);
3164 out[1] = GEN_INT (m1);
3165 out[2] = GEN_INT (shift);
3166 out[3] = GEN_INT (m2);
3174 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3177 invalid_e500_subreg (rtx op, enum machine_mode mode)
3179 if (TARGET_E500_DOUBLE)
3181 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3182 subreg:TI and reg:TF. */
3183 if (GET_CODE (op) == SUBREG
3184 && (mode == SImode || mode == DImode || mode == TImode)
3185 && REG_P (SUBREG_REG (op))
3186 && (GET_MODE (SUBREG_REG (op)) == DFmode
3187 || GET_MODE (SUBREG_REG (op)) == TFmode
3188 || GET_MODE (SUBREG_REG (op)) == DDmode
3189 || GET_MODE (SUBREG_REG (op)) == TDmode))
3192 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3194 if (GET_CODE (op) == SUBREG
3195 && (mode == DFmode || mode == TFmode
3196 || mode == DDmode || mode == TDmode)
3197 && REG_P (SUBREG_REG (op))
3198 && (GET_MODE (SUBREG_REG (op)) == DImode
3199 || GET_MODE (SUBREG_REG (op)) == TImode))
3204 && GET_CODE (op) == SUBREG
3206 && REG_P (SUBREG_REG (op))
3207 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
3213 /* AIX increases natural record alignment to doubleword if the first
3214 field is an FP double while the FP fields remain word aligned. */
3217 rs6000_special_round_type_align (tree type, unsigned int computed,
3218 unsigned int specified)
3220 unsigned int align = MAX (computed, specified);
3221 tree field = TYPE_FIELDS (type);
3223 /* Skip all non field decls */
3224 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3225 field = TREE_CHAIN (field);
3227 if (field != NULL && field != type)
3229 type = TREE_TYPE (field);
3230 while (TREE_CODE (type) == ARRAY_TYPE)
3231 type = TREE_TYPE (type);
3233 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
3234 align = MAX (align, 64);
3240 /* Darwin increases record alignment to the natural alignment of
3244 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3245 unsigned int specified)
3247 unsigned int align = MAX (computed, specified);
3249 if (TYPE_PACKED (type))
3252 /* Find the first field, looking down into aggregates. */
3254 tree field = TYPE_FIELDS (type);
3255 /* Skip all non field decls */
3256 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3257 field = TREE_CHAIN (field);
3260 type = TREE_TYPE (field);
3261 while (TREE_CODE (type) == ARRAY_TYPE)
3262 type = TREE_TYPE (type);
3263 } while (AGGREGATE_TYPE_P (type));
3265 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3266 align = MAX (align, TYPE_ALIGN (type));
3271 /* Return 1 for an operand in small memory on V.4/eabi. */
3274 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3275 enum machine_mode mode ATTRIBUTE_UNUSED)
3280 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3283 if (DEFAULT_ABI != ABI_V4)
3286 /* Vector and float memory instructions have a limited offset on the
3287 SPE, so using a vector or float variable directly as an operand is
3290 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
3293 if (GET_CODE (op) == SYMBOL_REF)
3296 else if (GET_CODE (op) != CONST
3297 || GET_CODE (XEXP (op, 0)) != PLUS
3298 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3299 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3304 rtx sum = XEXP (op, 0);
3305 HOST_WIDE_INT summand;
3307 /* We have to be careful here, because it is the referenced address
3308 that must be 32k from _SDA_BASE_, not just the symbol. */
3309 summand = INTVAL (XEXP (sum, 1));
3310 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3313 sym_ref = XEXP (sum, 0);
3316 return SYMBOL_REF_SMALL_P (sym_ref);
3322 /* Return true if either operand is a general purpose register. */
3325 gpr_or_gpr_p (rtx op0, rtx op1)
3327 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3328 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3332 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3335 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3337 switch (GET_CODE (op))
3340 if (RS6000_SYMBOL_REF_TLS_P (op))
3342 else if (CONSTANT_POOL_ADDRESS_P (op))
3344 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3352 else if (! strcmp (XSTR (op, 0), toc_label_name))
3361 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3362 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3364 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3373 constant_pool_expr_p (rtx op)
3377 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3381 toc_relative_expr_p (rtx op)
3385 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3389 legitimate_constant_pool_address_p (rtx x)
3392 && GET_CODE (x) == PLUS
3393 && GET_CODE (XEXP (x, 0)) == REG
3394 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3395 && constant_pool_expr_p (XEXP (x, 1)));
3399 legitimate_small_data_p (enum machine_mode mode, rtx x)
3401 return (DEFAULT_ABI == ABI_V4
3402 && !flag_pic && !TARGET_TOC
3403 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3404 && small_data_operand (x, mode));
3407 /* SPE offset addressing is limited to 5-bits worth of double words. */
3408 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3411 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3413 unsigned HOST_WIDE_INT offset, extra;
3415 if (GET_CODE (x) != PLUS)
3417 if (GET_CODE (XEXP (x, 0)) != REG)
3419 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3421 if (legitimate_constant_pool_address_p (x))
3423 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3426 offset = INTVAL (XEXP (x, 1));
3434 /* AltiVec vector modes. Only reg+reg addressing is valid and
3435 constant offset zero should not occur due to canonicalization. */
3442 /* Paired vector modes. Only reg+reg addressing is valid and
3443 constant offset zero should not occur due to canonicalization. */
3444 if (TARGET_PAIRED_FLOAT)
3446 /* SPE vector modes. */
3447 return SPE_CONST_OFFSET_OK (offset);
3451 if (TARGET_E500_DOUBLE)
3452 return SPE_CONST_OFFSET_OK (offset);
3455 /* On e500v2, we may have:
3457 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3459 Which gets addressed with evldd instructions. */
3460 if (TARGET_E500_DOUBLE)
3461 return SPE_CONST_OFFSET_OK (offset);
3463 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3465 else if (offset & 3)
3471 if (TARGET_E500_DOUBLE)
3472 return (SPE_CONST_OFFSET_OK (offset)
3473 && SPE_CONST_OFFSET_OK (offset + 8));
3476 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3478 else if (offset & 3)
3489 return (offset < 0x10000) && (offset + extra < 0x10000);
3493 legitimate_indexed_address_p (rtx x, int strict)
3497 if (GET_CODE (x) != PLUS)
3503 /* Recognize the rtl generated by reload which we know will later be
3504 replaced with proper base and index regs. */
3506 && reload_in_progress
3507 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3511 return (REG_P (op0) && REG_P (op1)
3512 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3513 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3514 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3515 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3519 legitimate_indirect_address_p (rtx x, int strict)
3521 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3525 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3527 if (!TARGET_MACHO || !flag_pic
3528 || mode != SImode || GET_CODE (x) != MEM)
3532 if (GET_CODE (x) != LO_SUM)
3534 if (GET_CODE (XEXP (x, 0)) != REG)
3536 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3540 return CONSTANT_P (x);
3544 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3546 if (GET_CODE (x) != LO_SUM)
3548 if (GET_CODE (XEXP (x, 0)) != REG)
3550 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3552 /* Restrict addressing for DI because of our SUBREG hackery. */
3553 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3554 || mode == DDmode || mode == TDmode
3559 if (TARGET_ELF || TARGET_MACHO)
3561 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3565 if (GET_MODE_NUNITS (mode) != 1)
3567 if (GET_MODE_BITSIZE (mode) > 64
3568 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3569 && !(TARGET_HARD_FLOAT && TARGET_FPRS
3570 && (mode == DFmode || mode == DDmode))))
3573 return CONSTANT_P (x);
3580 /* Try machine-dependent ways of modifying an illegitimate address
3581 to be legitimate. If we find one, return the new, valid address.
3582 This is used from only one place: `memory_address' in explow.c.
3584 OLDX is the address as it was before break_out_memory_refs was
3585 called. In some cases it is useful to look at this to decide what
3588 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3590 It is always safe for this function to do nothing. It exists to
3591 recognize opportunities to optimize the output.
3593 On RS/6000, first check for the sum of a register with a constant
3594 integer that is out of range. If so, generate code to add the
3595 constant with the low-order 16 bits masked to the register and force
3596 this result into another register (this can be done with `cau').
3597 Then generate an address of REG+(CONST&0xffff), allowing for the
3598 possibility of bit 16 being a one.
3600 Then check for the sum of a register and something not constant, try to
3601 load the other things into a register and return the sum. */
3604 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3605 enum machine_mode mode)
3607 if (GET_CODE (x) == SYMBOL_REF)
3609 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3611 return rs6000_legitimize_tls_address (x, model);
3614 if (GET_CODE (x) == PLUS
3615 && GET_CODE (XEXP (x, 0)) == REG
3616 && GET_CODE (XEXP (x, 1)) == CONST_INT
3617 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
3618 && !(SPE_VECTOR_MODE (mode)
3619 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3620 || mode == DImode))))
3622 HOST_WIDE_INT high_int, low_int;
3624 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3625 high_int = INTVAL (XEXP (x, 1)) - low_int;
3626 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3627 GEN_INT (high_int)), 0);
3628 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3630 else if (GET_CODE (x) == PLUS
3631 && GET_CODE (XEXP (x, 0)) == REG
3632 && GET_CODE (XEXP (x, 1)) != CONST_INT
3633 && GET_MODE_NUNITS (mode) == 1
3634 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3636 || (((mode != DImode && mode != DFmode && mode != DDmode)
3637 || TARGET_E500_DOUBLE)
3638 && mode != TFmode && mode != TDmode))
3639 && (TARGET_POWERPC64 || mode != DImode)
3642 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3643 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3645 else if (ALTIVEC_VECTOR_MODE (mode))
3649 /* Make sure both operands are registers. */
3650 if (GET_CODE (x) == PLUS)
3651 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3652 force_reg (Pmode, XEXP (x, 1)));
3654 reg = force_reg (Pmode, x);
3657 else if (SPE_VECTOR_MODE (mode)
3658 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3659 || mode == DDmode || mode == TDmode
3660 || mode == DImode)))
3664 /* We accept [reg + reg] and [reg + OFFSET]. */
3666 if (GET_CODE (x) == PLUS)
3668 rtx op1 = XEXP (x, 0);
3669 rtx op2 = XEXP (x, 1);
3672 op1 = force_reg (Pmode, op1);
3674 if (GET_CODE (op2) != REG
3675 && (GET_CODE (op2) != CONST_INT
3676 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
3677 || (GET_MODE_SIZE (mode) > 8
3678 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
3679 op2 = force_reg (Pmode, op2);
3681 /* We can't always do [reg + reg] for these, because [reg +
3682 reg + offset] is not a legitimate addressing mode. */
3683 y = gen_rtx_PLUS (Pmode, op1, op2);
3685 if (GET_MODE_SIZE (mode) > 8 && REG_P (op2))
3686 return force_reg (Pmode, y);
3691 return force_reg (Pmode, x);
3697 && GET_CODE (x) != CONST_INT
3698 && GET_CODE (x) != CONST_DOUBLE
3700 && GET_MODE_NUNITS (mode) == 1
3701 && (GET_MODE_BITSIZE (mode) <= 32
3702 || ((TARGET_HARD_FLOAT && TARGET_FPRS)
3703 && (mode == DFmode || mode == DDmode))))
3705 rtx reg = gen_reg_rtx (Pmode);
3706 emit_insn (gen_elf_high (reg, x));
3707 return gen_rtx_LO_SUM (Pmode, reg, x);
3709 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3712 && ! MACHO_DYNAMIC_NO_PIC_P
3714 && GET_CODE (x) != CONST_INT
3715 && GET_CODE (x) != CONST_DOUBLE
3717 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3718 || (mode != DFmode && mode != DDmode))
3722 rtx reg = gen_reg_rtx (Pmode);
3723 emit_insn (gen_macho_high (reg, x));
3724 return gen_rtx_LO_SUM (Pmode, reg, x);
3727 && constant_pool_expr_p (x)
3728 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3730 return create_TOC_reference (x);
3736 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3737 We need to emit DTP-relative relocations. */
3740 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3745 fputs ("\t.long\t", file);
3748 fputs (DOUBLE_INT_ASM_OP, file);
3753 output_addr_const (file, x);
3754 fputs ("@dtprel+0x8000", file);
3757 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3759 static GTY(()) rtx rs6000_tls_symbol;
3761 rs6000_tls_get_addr (void)
3763 if (!rs6000_tls_symbol)
3764 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3766 return rs6000_tls_symbol;
3769 /* Construct the SYMBOL_REF for TLS GOT references. */
3771 static GTY(()) rtx rs6000_got_symbol;
3773 rs6000_got_sym (void)
3775 if (!rs6000_got_symbol)
3777 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3778 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3779 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3782 return rs6000_got_symbol;
3785 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3786 this (thread-local) address. */
3789 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3793 dest = gen_reg_rtx (Pmode);
3794 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3800 tlsreg = gen_rtx_REG (Pmode, 13);
3801 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3805 tlsreg = gen_rtx_REG (Pmode, 2);
3806 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3810 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3814 tmp = gen_reg_rtx (Pmode);
3817 tlsreg = gen_rtx_REG (Pmode, 13);
3818 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3822 tlsreg = gen_rtx_REG (Pmode, 2);
3823 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3827 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3829 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3834 rtx r3, got, tga, tmp1, tmp2, eqv;
3836 /* We currently use relocations like @got@tlsgd for tls, which
3837 means the linker will handle allocation of tls entries, placing
3838 them in the .got section. So use a pointer to the .got section,
3839 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3840 or to secondary GOT sections used by 32-bit -fPIC. */
3842 got = gen_rtx_REG (Pmode, 2);
3846 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3849 rtx gsym = rs6000_got_sym ();
3850 got = gen_reg_rtx (Pmode);
3852 rs6000_emit_move (got, gsym, Pmode);
3858 tmp1 = gen_reg_rtx (Pmode);
3859 tmp2 = gen_reg_rtx (Pmode);
3860 tmp3 = gen_reg_rtx (Pmode);
3861 mem = gen_const_mem (Pmode, tmp1);
3863 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3864 emit_move_insn (tmp1,
3865 gen_rtx_REG (Pmode, LR_REGNO));
3866 emit_move_insn (tmp2, mem);
3867 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3868 last = emit_move_insn (got, tmp3);
3869 set_unique_reg_note (last, REG_EQUAL, gsym);
3870 maybe_encapsulate_block (first, last, gsym);
3875 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3877 r3 = gen_rtx_REG (Pmode, 3);
3879 insn = gen_tls_gd_64 (r3, got, addr);
3881 insn = gen_tls_gd_32 (r3, got, addr);
3884 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3885 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3886 insn = emit_call_insn (insn);
3887 CONST_OR_PURE_CALL_P (insn) = 1;
3888 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3889 insn = get_insns ();
3891 emit_libcall_block (insn, dest, r3, addr);
3893 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3895 r3 = gen_rtx_REG (Pmode, 3);
3897 insn = gen_tls_ld_64 (r3, got);
3899 insn = gen_tls_ld_32 (r3, got);
3902 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3903 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3904 insn = emit_call_insn (insn);
3905 CONST_OR_PURE_CALL_P (insn) = 1;
3906 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3907 insn = get_insns ();
3909 tmp1 = gen_reg_rtx (Pmode);
3910 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3912 emit_libcall_block (insn, tmp1, r3, eqv);
3913 if (rs6000_tls_size == 16)
3916 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3918 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3920 else if (rs6000_tls_size == 32)
3922 tmp2 = gen_reg_rtx (Pmode);
3924 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3926 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3929 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3931 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3935 tmp2 = gen_reg_rtx (Pmode);
3937 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3939 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3941 insn = gen_rtx_SET (Pmode, dest,
3942 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3948 /* IE, or 64-bit offset LE. */
3949 tmp2 = gen_reg_rtx (Pmode);
3951 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3953 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3956 insn = gen_tls_tls_64 (dest, tmp2, addr);
3958 insn = gen_tls_tls_32 (dest, tmp2, addr);
3966 /* Return 1 if X contains a thread-local symbol. */
3969 rs6000_tls_referenced_p (rtx x)
3971 if (! TARGET_HAVE_TLS)
3974 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3977 /* Return 1 if *X is a thread-local symbol. This is the same as
3978 rs6000_tls_symbol_ref except for the type of the unused argument. */
3981 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3983 return RS6000_SYMBOL_REF_TLS_P (*x);
3986 /* The convention appears to be to define this wherever it is used.
3987 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3988 is now used here. */
3989 #ifndef REG_MODE_OK_FOR_BASE_P
3990 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3993 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3994 replace the input X, or the original X if no replacement is called for.
3995 The output parameter *WIN is 1 if the calling macro should goto WIN,
3998 For RS/6000, we wish to handle large displacements off a base
3999 register by splitting the addend across an addiu/addis and the mem insn.
4000 This cuts number of extra insns needed from 3 to 1.
4002 On Darwin, we use this to generate code for floating point constants.
4003 A movsf_low is generated so we wind up with 2 instructions rather than 3.
4004 The Darwin code is inside #if TARGET_MACHO because only then is
4005 machopic_function_base_name() defined. */
4007 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
4008 int opnum, int type,
4009 int ind_levels ATTRIBUTE_UNUSED, int *win)
4011 /* We must recognize output that we have already generated ourselves. */
4012 if (GET_CODE (x) == PLUS
4013 && GET_CODE (XEXP (x, 0)) == PLUS
4014 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4015 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4016 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4018 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4019 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4020 opnum, (enum reload_type)type);
4026 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
4027 && GET_CODE (x) == LO_SUM
4028 && GET_CODE (XEXP (x, 0)) == PLUS
4029 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
4030 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
4031 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
4032 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
4033 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
4034 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
4035 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
4037 /* Result of previous invocation of this function on Darwin
4038 floating point constant. */
4039 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4040 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4041 opnum, (enum reload_type)type);
4047 /* Force ld/std non-word aligned offset into base register by wrapping
4049 if (GET_CODE (x) == PLUS
4050 && GET_CODE (XEXP (x, 0)) == REG
4051 && REGNO (XEXP (x, 0)) < 32
4052 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4053 && GET_CODE (XEXP (x, 1)) == CONST_INT
4054 && (INTVAL (XEXP (x, 1)) & 3) != 0
4055 && !ALTIVEC_VECTOR_MODE (mode)
4056 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
4057 && TARGET_POWERPC64)
4059 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
4060 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4061 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4062 opnum, (enum reload_type) type);
4067 if (GET_CODE (x) == PLUS
4068 && GET_CODE (XEXP (x, 0)) == REG
4069 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
4070 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4071 && GET_CODE (XEXP (x, 1)) == CONST_INT
4072 && !SPE_VECTOR_MODE (mode)
4073 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
4074 || mode == DDmode || mode == TDmode
4076 && !ALTIVEC_VECTOR_MODE (mode))
4078 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
4079 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
4081 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4083 /* Check for 32-bit overflow. */
4084 if (high + low != val)
4090 /* Reload the high part into a base reg; leave the low part
4091 in the mem directly. */
4093 x = gen_rtx_PLUS (GET_MODE (x),
4094 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
4098 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4099 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4100 opnum, (enum reload_type)type);
4105 if (GET_CODE (x) == SYMBOL_REF
4106 && !ALTIVEC_VECTOR_MODE (mode)
4107 && !SPE_VECTOR_MODE (mode)
4109 && DEFAULT_ABI == ABI_DARWIN
4110 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
4112 && DEFAULT_ABI == ABI_V4
4115 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4116 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4120 && (mode != DImode || TARGET_POWERPC64)
4121 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
4122 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
4127 rtx offset = gen_rtx_CONST (Pmode,
4128 gen_rtx_MINUS (Pmode, x,
4129 machopic_function_base_sym ()));
4130 x = gen_rtx_LO_SUM (GET_MODE (x),
4131 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
4132 gen_rtx_HIGH (Pmode, offset)), offset);
4136 x = gen_rtx_LO_SUM (GET_MODE (x),
4137 gen_rtx_HIGH (Pmode, x), x);
4139 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4140 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4141 opnum, (enum reload_type)type);
4146 /* Reload an offset address wrapped by an AND that represents the
4147 masking of the lower bits. Strip the outer AND and let reload
4148 convert the offset address into an indirect address. */
4150 && ALTIVEC_VECTOR_MODE (mode)
4151 && GET_CODE (x) == AND
4152 && GET_CODE (XEXP (x, 0)) == PLUS
4153 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4154 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4155 && GET_CODE (XEXP (x, 1)) == CONST_INT
4156 && INTVAL (XEXP (x, 1)) == -16)
4164 && constant_pool_expr_p (x)
4165 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
4167 x = create_TOC_reference (x);
4175 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4176 that is a valid memory address for an instruction.
4177 The MODE argument is the machine mode for the MEM expression
4178 that wants to use this address.
4180 On the RS/6000, there are four valid address: a SYMBOL_REF that
4181 refers to a constant pool entry of an address (or the sum of it
4182 plus a constant), a short (16-bit signed) constant plus a register,
4183 the sum of two registers, or a register indirect, possibly with an
4184 auto-increment. For DFmode, DDmode and DImode with a constant plus
4185 register, we must ensure that both words are addressable or PowerPC64
4186 with offset word aligned.
4188 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4189 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4190 because adjacent memory cells are accessed by adding word-sized offsets
4191 during assembly output. */
4193 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
4195 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4197 && ALTIVEC_VECTOR_MODE (mode)
4198 && GET_CODE (x) == AND
4199 && GET_CODE (XEXP (x, 1)) == CONST_INT
4200 && INTVAL (XEXP (x, 1)) == -16)
4203 if (RS6000_SYMBOL_REF_TLS_P (x))
4205 if (legitimate_indirect_address_p (x, reg_ok_strict))
4207 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
4208 && !ALTIVEC_VECTOR_MODE (mode)
4209 && !SPE_VECTOR_MODE (mode)
4212 /* Restrict addressing for DI because of our SUBREG hackery. */
4213 && !(TARGET_E500_DOUBLE
4214 && (mode == DFmode || mode == DDmode || mode == DImode))
4216 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
4218 if (legitimate_small_data_p (mode, x))
4220 if (legitimate_constant_pool_address_p (x))
4222 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4224 && GET_CODE (x) == PLUS
4225 && GET_CODE (XEXP (x, 0)) == REG
4226 && (XEXP (x, 0) == virtual_stack_vars_rtx
4227 || XEXP (x, 0) == arg_pointer_rtx)
4228 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4230 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
4235 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4237 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
4238 && (TARGET_POWERPC64 || mode != DImode)
4239 && legitimate_indexed_address_p (x, reg_ok_strict))
4241 if (GET_CODE (x) == PRE_MODIFY
4245 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4247 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
4248 && (TARGET_POWERPC64 || mode != DImode)
4249 && !ALTIVEC_VECTOR_MODE (mode)
4250 && !SPE_VECTOR_MODE (mode)
4251 /* Restrict addressing for DI because of our SUBREG hackery. */
4252 && !(TARGET_E500_DOUBLE
4253 && (mode == DFmode || mode == DDmode || mode == DImode))
4255 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
4256 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
4257 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
4258 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4260 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
4265 /* Go to LABEL if ADDR (a legitimate address expression)
4266 has an effect that depends on the machine mode it is used for.
4268 On the RS/6000 this is true of all integral offsets (since AltiVec
4269 modes don't allow them) or is a pre-increment or decrement.
4271 ??? Except that due to conceptual problems in offsettable_address_p
4272 we can't really report the problems of integral offsets. So leave
4273 this assuming that the adjustable offset must be valid for the
4274 sub-words of a TFmode operand, which is what we had before. */
4277 rs6000_mode_dependent_address (rtx addr)
4279 switch (GET_CODE (addr))
4282 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4284 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4285 return val + 12 + 0x8000 >= 0x10000;
4295 return TARGET_UPDATE;
4304 /* More elaborate version of recog's offsettable_memref_p predicate
4305 that works around the ??? note of rs6000_mode_dependent_address.
4306 In particular it accepts
4308 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4310 in 32-bit mode, that the recog predicate rejects. */
4313 rs6000_offsettable_memref_p (rtx op)
4318 /* First mimic offsettable_memref_p. */
4319 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4322 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4323 the latter predicate knows nothing about the mode of the memory
4324 reference and, therefore, assumes that it is the largest supported
4325 mode (TFmode). As a consequence, legitimate offsettable memory
4326 references are rejected. rs6000_legitimate_offset_address_p contains
4327 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4328 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4331 /* Return number of consecutive hard regs needed starting at reg REGNO
4332 to hold something of mode MODE.
4333 This is ordinarily the length in words of a value of mode MODE
4334 but can be less for certain modes in special long registers.
4336 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4337 scalar instructions. The upper 32 bits are only available to the
4340 POWER and PowerPC GPRs hold 32 bits worth;
4341 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4344 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4346 if (FP_REGNO_P (regno))
4347 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4349 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4350 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4352 if (ALTIVEC_REGNO_P (regno))
4354 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4356 /* The value returned for SCmode in the E500 double case is 2 for
4357 ABI compatibility; storing an SCmode value in a single register
4358 would require function_arg and rs6000_spe_function_arg to handle
4359 SCmode so as to pass the value correctly in a pair of
4361 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
4362 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4364 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4367 /* Change register usage conditional on target flags. */
4369 rs6000_conditional_register_usage (void)
4373 /* Set MQ register fixed (already call_used) if not POWER
4374 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4379 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4381 fixed_regs[13] = call_used_regs[13]
4382 = call_really_used_regs[13] = 1;
4384 /* Conditionally disable FPRs. */
4385 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4386 for (i = 32; i < 64; i++)
4387 fixed_regs[i] = call_used_regs[i]
4388 = call_really_used_regs[i] = 1;
4390 /* The TOC register is not killed across calls in a way that is
4391 visible to the compiler. */
4392 if (DEFAULT_ABI == ABI_AIX)
4393 call_really_used_regs[2] = 0;
4395 if (DEFAULT_ABI == ABI_V4
4396 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4398 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4400 if (DEFAULT_ABI == ABI_V4
4401 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4403 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4404 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4405 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4407 if (DEFAULT_ABI == ABI_DARWIN
4408 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4409 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4410 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4411 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4413 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4414 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4415 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4419 global_regs[SPEFSCR_REGNO] = 1;
4420 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4421 registers in prologues and epilogues. We no longer use r14
4422 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4423 pool for link-compatibility with older versions of GCC. Once
4424 "old" code has died out, we can return r14 to the allocation
4427 = call_used_regs[14]
4428 = call_really_used_regs[14] = 1;
4431 if (!TARGET_ALTIVEC)
4433 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4434 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4435 call_really_used_regs[VRSAVE_REGNO] = 1;
4439 global_regs[VSCR_REGNO] = 1;
4441 if (TARGET_ALTIVEC_ABI)
4443 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4444 call_used_regs[i] = call_really_used_regs[i] = 1;
4446 /* AIX reserves VR20:31 in non-extended ABI mode. */
4448 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
4449 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4453 /* Try to output insns to set TARGET equal to the constant C if it can
4454 be done in less than N insns. Do all computations in MODE.
4455 Returns the place where the output has been placed if it can be
4456 done and the insns have been emitted. If it would take more than N
4457 insns, zero is returned and no insns and emitted. */
4460 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4461 rtx source, int n ATTRIBUTE_UNUSED)
4463 rtx result, insn, set;
4464 HOST_WIDE_INT c0, c1;
4471 dest = gen_reg_rtx (mode);
4472 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4476 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4478 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4479 GEN_INT (INTVAL (source)
4480 & (~ (HOST_WIDE_INT) 0xffff))));
4481 emit_insn (gen_rtx_SET (VOIDmode, dest,
4482 gen_rtx_IOR (SImode, copy_rtx (result),
4483 GEN_INT (INTVAL (source) & 0xffff))));
4488 switch (GET_CODE (source))
4491 c0 = INTVAL (source);
4496 #if HOST_BITS_PER_WIDE_INT >= 64
4497 c0 = CONST_DOUBLE_LOW (source);
4500 c0 = CONST_DOUBLE_LOW (source);
4501 c1 = CONST_DOUBLE_HIGH (source);
4509 result = rs6000_emit_set_long_const (dest, c0, c1);
4516 insn = get_last_insn ();
4517 set = single_set (insn);
4518 if (! CONSTANT_P (SET_SRC (set)))
4519 set_unique_reg_note (insn, REG_EQUAL, source);
4524 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4525 fall back to a straight forward decomposition. We do this to avoid
4526 exponential run times encountered when looking for longer sequences
4527 with rs6000_emit_set_const. */
4529 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4531 if (!TARGET_POWERPC64)
4533 rtx operand1, operand2;
4535 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4537 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4539 emit_move_insn (operand1, GEN_INT (c1));
4540 emit_move_insn (operand2, GEN_INT (c2));
4544 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4547 ud2 = (c1 & 0xffff0000) >> 16;
4548 #if HOST_BITS_PER_WIDE_INT >= 64
4552 ud4 = (c2 & 0xffff0000) >> 16;
4554 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4555 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4558 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4560 emit_move_insn (dest, GEN_INT (ud1));
4563 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4564 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4567 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4570 emit_move_insn (dest, GEN_INT (ud2 << 16));
4572 emit_move_insn (copy_rtx (dest),
4573 gen_rtx_IOR (DImode, copy_rtx (dest),
4576 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4577 || (ud4 == 0 && ! (ud3 & 0x8000)))
4580 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4583 emit_move_insn (dest, GEN_INT (ud3 << 16));
4586 emit_move_insn (copy_rtx (dest),
4587 gen_rtx_IOR (DImode, copy_rtx (dest),
4589 emit_move_insn (copy_rtx (dest),
4590 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4593 emit_move_insn (copy_rtx (dest),
4594 gen_rtx_IOR (DImode, copy_rtx (dest),
4600 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4603 emit_move_insn (dest, GEN_INT (ud4 << 16));
4606 emit_move_insn (copy_rtx (dest),
4607 gen_rtx_IOR (DImode, copy_rtx (dest),
4610 emit_move_insn (copy_rtx (dest),
4611 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4614 emit_move_insn (copy_rtx (dest),
4615 gen_rtx_IOR (DImode, copy_rtx (dest),
4616 GEN_INT (ud2 << 16)));
4618 emit_move_insn (copy_rtx (dest),
4619 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4625 /* Helper for the following. Get rid of [r+r] memory refs
4626 in cases where it won't work (TImode, TFmode, TDmode). */
4629 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4631 if (GET_CODE (operands[0]) == MEM
4632 && GET_CODE (XEXP (operands[0], 0)) != REG
4633 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4634 && ! reload_in_progress)
4636 = replace_equiv_address (operands[0],
4637 copy_addr_to_reg (XEXP (operands[0], 0)));
4639 if (GET_CODE (operands[1]) == MEM
4640 && GET_CODE (XEXP (operands[1], 0)) != REG
4641 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4642 && ! reload_in_progress)
4644 = replace_equiv_address (operands[1],
4645 copy_addr_to_reg (XEXP (operands[1], 0)));
4648 /* Emit a move from SOURCE to DEST in mode MODE. */
4650 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4654 operands[1] = source;
4656 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4657 if (GET_CODE (operands[1]) == CONST_DOUBLE
4658 && ! FLOAT_MODE_P (mode)
4659 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4661 /* FIXME. This should never happen. */
4662 /* Since it seems that it does, do the safe thing and convert
4664 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4666 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4667 || FLOAT_MODE_P (mode)
4668 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4669 || CONST_DOUBLE_LOW (operands[1]) < 0)
4670 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4671 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4673 /* Check if GCC is setting up a block move that will end up using FP
4674 registers as temporaries. We must make sure this is acceptable. */
4675 if (GET_CODE (operands[0]) == MEM
4676 && GET_CODE (operands[1]) == MEM
4678 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4679 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4680 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4681 ? 32 : MEM_ALIGN (operands[0])))
4682 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4684 : MEM_ALIGN (operands[1]))))
4685 && ! MEM_VOLATILE_P (operands [0])
4686 && ! MEM_VOLATILE_P (operands [1]))
4688 emit_move_insn (adjust_address (operands[0], SImode, 0),
4689 adjust_address (operands[1], SImode, 0));
4690 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4691 adjust_address (copy_rtx (operands[1]), SImode, 4));
4695 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4696 && !gpc_reg_operand (operands[1], mode))
4697 operands[1] = force_reg (mode, operands[1]);
4699 if (mode == SFmode && ! TARGET_POWERPC
4700 && TARGET_HARD_FLOAT && TARGET_FPRS
4701 && GET_CODE (operands[0]) == MEM)
4705 if (reload_in_progress || reload_completed)
4706 regnum = true_regnum (operands[1]);
4707 else if (GET_CODE (operands[1]) == REG)
4708 regnum = REGNO (operands[1]);
4712 /* If operands[1] is a register, on POWER it may have
4713 double-precision data in it, so truncate it to single
4715 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4718 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4719 : gen_reg_rtx (mode));
4720 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4721 operands[1] = newreg;
4725 /* Recognize the case where operand[1] is a reference to thread-local
4726 data and load its address to a register. */
4727 if (rs6000_tls_referenced_p (operands[1]))
4729 enum tls_model model;
4730 rtx tmp = operands[1];
4733 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4735 addend = XEXP (XEXP (tmp, 0), 1);
4736 tmp = XEXP (XEXP (tmp, 0), 0);
4739 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4740 model = SYMBOL_REF_TLS_MODEL (tmp);
4741 gcc_assert (model != 0);
4743 tmp = rs6000_legitimize_tls_address (tmp, model);
4746 tmp = gen_rtx_PLUS (mode, tmp, addend);
4747 tmp = force_operand (tmp, operands[0]);
4752 /* Handle the case where reload calls us with an invalid address. */
4753 if (reload_in_progress && mode == Pmode
4754 && (! general_operand (operands[1], mode)
4755 || ! nonimmediate_operand (operands[0], mode)))
4758 /* 128-bit constant floating-point values on Darwin should really be
4759 loaded as two parts. */
4760 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4761 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4763 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4764 know how to get a DFmode SUBREG of a TFmode. */
4765 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4766 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4767 simplify_gen_subreg (imode, operands[1], mode, 0),
4769 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4770 GET_MODE_SIZE (imode)),
4771 simplify_gen_subreg (imode, operands[1], mode,
4772 GET_MODE_SIZE (imode)),
4777 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
4778 cfun->machine->sdmode_stack_slot =
4779 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
4781 if (reload_in_progress
4783 && MEM_P (operands[0])
4784 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
4785 && REG_P (operands[1]))
4787 if (FP_REGNO_P (REGNO (operands[1])))
4789 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
4790 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4791 emit_insn (gen_movsd_store (mem, operands[1]));
4793 else if (INT_REGNO_P (REGNO (operands[1])))
4795 rtx mem = adjust_address_nv (operands[0], mode, 4);
4796 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4797 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
4803 if (reload_in_progress
4805 && REG_P (operands[0])
4806 && MEM_P (operands[1])
4807 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
4809 if (FP_REGNO_P (REGNO (operands[0])))
4811 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
4812 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4813 emit_insn (gen_movsd_load (operands[0], mem));
4815 else if (INT_REGNO_P (REGNO (operands[0])))
4817 rtx mem = adjust_address_nv (operands[1], mode, 4);
4818 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4819 emit_insn (gen_movsd_hardfloat (operands[0], mem));
4826 /* FIXME: In the long term, this switch statement should go away
4827 and be replaced by a sequence of tests based on things like
4833 if (CONSTANT_P (operands[1])
4834 && GET_CODE (operands[1]) != CONST_INT)
4835 operands[1] = force_const_mem (mode, operands[1]);
4840 rs6000_eliminate_indexed_memrefs (operands);
4847 if (CONSTANT_P (operands[1])
4848 && ! easy_fp_constant (operands[1], mode))
4849 operands[1] = force_const_mem (mode, operands[1]);
4860 if (CONSTANT_P (operands[1])
4861 && !easy_vector_constant (operands[1], mode))
4862 operands[1] = force_const_mem (mode, operands[1]);
4867 /* Use default pattern for address of ELF small data */
4870 && DEFAULT_ABI == ABI_V4
4871 && (GET_CODE (operands[1]) == SYMBOL_REF
4872 || GET_CODE (operands[1]) == CONST)
4873 && small_data_operand (operands[1], mode))
4875 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4879 if (DEFAULT_ABI == ABI_V4
4880 && mode == Pmode && mode == SImode
4881 && flag_pic == 1 && got_operand (operands[1], mode))
4883 emit_insn (gen_movsi_got (operands[0], operands[1]));
4887 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4891 && CONSTANT_P (operands[1])
4892 && GET_CODE (operands[1]) != HIGH
4893 && GET_CODE (operands[1]) != CONST_INT)
4895 rtx target = (!can_create_pseudo_p ()
4897 : gen_reg_rtx (mode));
4899 /* If this is a function address on -mcall-aixdesc,
4900 convert it to the address of the descriptor. */
4901 if (DEFAULT_ABI == ABI_AIX
4902 && GET_CODE (operands[1]) == SYMBOL_REF
4903 && XSTR (operands[1], 0)[0] == '.')
4905 const char *name = XSTR (operands[1], 0);
4907 while (*name == '.')
4909 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4910 CONSTANT_POOL_ADDRESS_P (new_ref)
4911 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4912 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4913 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4914 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4915 operands[1] = new_ref;
4918 if (DEFAULT_ABI == ABI_DARWIN)
4921 if (MACHO_DYNAMIC_NO_PIC_P)
4923 /* Take care of any required data indirection. */
4924 operands[1] = rs6000_machopic_legitimize_pic_address (
4925 operands[1], mode, operands[0]);
4926 if (operands[0] != operands[1])
4927 emit_insn (gen_rtx_SET (VOIDmode,
4928 operands[0], operands[1]));
4932 emit_insn (gen_macho_high (target, operands[1]));
4933 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4937 emit_insn (gen_elf_high (target, operands[1]));
4938 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4942 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4943 and we have put it in the TOC, we just need to make a TOC-relative
4946 && GET_CODE (operands[1]) == SYMBOL_REF
4947 && constant_pool_expr_p (operands[1])
4948 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4949 get_pool_mode (operands[1])))
4951 operands[1] = create_TOC_reference (operands[1]);
4953 else if (mode == Pmode
4954 && CONSTANT_P (operands[1])
4955 && ((GET_CODE (operands[1]) != CONST_INT
4956 && ! easy_fp_constant (operands[1], mode))
4957 || (GET_CODE (operands[1]) == CONST_INT
4958 && num_insns_constant (operands[1], mode) > 2)
4959 || (GET_CODE (operands[0]) == REG
4960 && FP_REGNO_P (REGNO (operands[0]))))
4961 && GET_CODE (operands[1]) != HIGH
4962 && ! legitimate_constant_pool_address_p (operands[1])
4963 && ! toc_relative_expr_p (operands[1]))
4965 /* Emit a USE operation so that the constant isn't deleted if
4966 expensive optimizations are turned on because nobody
4967 references it. This should only be done for operands that
4968 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4969 This should not be done for operands that contain LABEL_REFs.
4970 For now, we just handle the obvious case. */
4971 if (GET_CODE (operands[1]) != LABEL_REF)
4972 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4975 /* Darwin uses a special PIC legitimizer. */
4976 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4979 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4981 if (operands[0] != operands[1])
4982 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4987 /* If we are to limit the number of things we put in the TOC and
4988 this is a symbol plus a constant we can add in one insn,
4989 just put the symbol in the TOC and add the constant. Don't do
4990 this if reload is in progress. */
4991 if (GET_CODE (operands[1]) == CONST
4992 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4993 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4994 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4995 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4996 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4997 && ! side_effects_p (operands[0]))
5000 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
5001 rtx other = XEXP (XEXP (operands[1], 0), 1);
5003 sym = force_reg (mode, sym);
5005 emit_insn (gen_addsi3 (operands[0], sym, other));
5007 emit_insn (gen_adddi3 (operands[0], sym, other));
5011 operands[1] = force_const_mem (mode, operands[1]);
5014 && constant_pool_expr_p (XEXP (operands[1], 0))
5015 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
5016 get_pool_constant (XEXP (operands[1], 0)),
5017 get_pool_mode (XEXP (operands[1], 0))))
5020 = gen_const_mem (mode,
5021 create_TOC_reference (XEXP (operands[1], 0)));
5022 set_mem_alias_set (operands[1], get_TOC_alias_set ());
5028 rs6000_eliminate_indexed_memrefs (operands);
5032 emit_insn (gen_rtx_PARALLEL (VOIDmode,
5034 gen_rtx_SET (VOIDmode,
5035 operands[0], operands[1]),
5036 gen_rtx_CLOBBER (VOIDmode,
5037 gen_rtx_SCRATCH (SImode)))));
5046 /* Above, we may have called force_const_mem which may have returned
5047 an invalid address. If we can, fix this up; otherwise, reload will
5048 have to deal with it. */
5049 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
5050 operands[1] = validize_mem (operands[1]);
5053 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5056 /* Nonzero if we can use a floating-point register to pass this arg. */
5057 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5058 (SCALAR_FLOAT_MODE_P (MODE) \
5059 && (CUM)->fregno <= FP_ARG_MAX_REG \
5060 && TARGET_HARD_FLOAT && TARGET_FPRS)
5062 /* Nonzero if we can use an AltiVec register to pass this arg. */
5063 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5064 (ALTIVEC_VECTOR_MODE (MODE) \
5065 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5066 && TARGET_ALTIVEC_ABI \
5069 /* Return a nonzero value to say to return the function value in
5070 memory, just as large structures are always returned. TYPE will be
5071 the data type of the value, and FNTYPE will be the type of the
5072 function doing the returning, or @code{NULL} for libcalls.
5074 The AIX ABI for the RS/6000 specifies that all structures are
5075 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5076 specifies that structures <= 8 bytes are returned in r3/r4, but a
5077 draft put them in memory, and GCC used to implement the draft
5078 instead of the final standard. Therefore, aix_struct_return
5079 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5080 compatibility can change DRAFT_V4_STRUCT_RET to override the
5081 default, and -m switches get the final word. See
5082 rs6000_override_options for more details.
5084 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5085 long double support is enabled. These values are returned in memory.
5087 int_size_in_bytes returns -1 for variable size objects, which go in
5088 memory always. The cast to unsigned makes -1 > 8. */
5091 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5093 /* In the darwin64 abi, try to use registers for larger structs
5095 if (rs6000_darwin64_abi
5096 && TREE_CODE (type) == RECORD_TYPE
5097 && int_size_in_bytes (type) > 0)
5099 CUMULATIVE_ARGS valcum;
5103 valcum.fregno = FP_ARG_MIN_REG;
5104 valcum.vregno = ALTIVEC_ARG_MIN_REG;
5105 /* Do a trial code generation as if this were going to be passed
5106 as an argument; if any part goes in memory, we return NULL. */
5107 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
5110 /* Otherwise fall through to more conventional ABI rules. */
5113 if (AGGREGATE_TYPE_P (type)
5114 && (aix_struct_return
5115 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
5118 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5119 modes only exist for GCC vector types if -maltivec. */
5120 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
5121 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5124 /* Return synthetic vectors in memory. */
5125 if (TREE_CODE (type) == VECTOR_TYPE
5126 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5128 static bool warned_for_return_big_vectors = false;
5129 if (!warned_for_return_big_vectors)
5131 warning (0, "GCC vector returned by reference: "
5132 "non-standard ABI extension with no compatibility guarantee");
5133 warned_for_return_big_vectors = true;
5138 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
5144 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5145 for a call to a function whose data type is FNTYPE.
5146 For a library call, FNTYPE is 0.
5148 For incoming args we set the number of arguments in the prototype large
5149 so we never return a PARALLEL. */
5152 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
5153 rtx libname ATTRIBUTE_UNUSED, int incoming,
5154 int libcall, int n_named_args)
5156 static CUMULATIVE_ARGS zero_cumulative;
5158 *cum = zero_cumulative;
5160 cum->fregno = FP_ARG_MIN_REG;
5161 cum->vregno = ALTIVEC_ARG_MIN_REG;
5162 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
5163 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
5164 ? CALL_LIBCALL : CALL_NORMAL);
5165 cum->sysv_gregno = GP_ARG_MIN_REG;
5166 cum->stdarg = fntype
5167 && (TYPE_ARG_TYPES (fntype) != 0
5168 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5169 != void_type_node));
5171 cum->nargs_prototype = 0;
5172 if (incoming || cum->prototype)
5173 cum->nargs_prototype = n_named_args;
5175 /* Check for a longcall attribute. */
5176 if ((!fntype && rs6000_default_long_calls)
5178 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
5179 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
5180 cum->call_cookie |= CALL_LONG;
5182 if (TARGET_DEBUG_ARG)
5184 fprintf (stderr, "\ninit_cumulative_args:");
5187 tree ret_type = TREE_TYPE (fntype);
5188 fprintf (stderr, " ret code = %s,",
5189 tree_code_name[ (int)TREE_CODE (ret_type) ]);
5192 if (cum->call_cookie & CALL_LONG)
5193 fprintf (stderr, " longcall,");
5195 fprintf (stderr, " proto = %d, nargs = %d\n",
5196 cum->prototype, cum->nargs_prototype);
5201 && TARGET_ALTIVEC_ABI
5202 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
5204 error ("cannot return value in vector register because"
5205 " altivec instructions are disabled, use -maltivec"
5210 /* Return true if TYPE must be passed on the stack and not in registers. */
5213 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
5215 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
5216 return must_pass_in_stack_var_size (mode, type);
5218 return must_pass_in_stack_var_size_or_pad (mode, type);
5221 /* If defined, a C expression which determines whether, and in which
5222 direction, to pad out an argument with extra space. The value
5223 should be of type `enum direction': either `upward' to pad above
5224 the argument, `downward' to pad below, or `none' to inhibit
5227 For the AIX ABI structs are always stored left shifted in their
5231 function_arg_padding (enum machine_mode mode, const_tree type)
5233 #ifndef AGGREGATE_PADDING_FIXED
5234 #define AGGREGATE_PADDING_FIXED 0
5236 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5237 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5240 if (!AGGREGATE_PADDING_FIXED)
5242 /* GCC used to pass structures of the same size as integer types as
5243 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5244 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5245 passed padded downward, except that -mstrict-align further
5246 muddied the water in that multi-component structures of 2 and 4
5247 bytes in size were passed padded upward.
5249 The following arranges for best compatibility with previous
5250 versions of gcc, but removes the -mstrict-align dependency. */
5251 if (BYTES_BIG_ENDIAN)
5253 HOST_WIDE_INT size = 0;
5255 if (mode == BLKmode)
5257 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5258 size = int_size_in_bytes (type);
5261 size = GET_MODE_SIZE (mode);
5263 if (size == 1 || size == 2 || size == 4)
5269 if (AGGREGATES_PAD_UPWARD_ALWAYS)
5271 if (type != 0 && AGGREGATE_TYPE_P (type))
5275 /* Fall back to the default. */
5276 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5279 /* If defined, a C expression that gives the alignment boundary, in bits,
5280 of an argument with the specified mode and type. If it is not defined,
5281 PARM_BOUNDARY is used for all arguments.
5283 V.4 wants long longs and doubles to be double word aligned. Just
5284 testing the mode size is a boneheaded way to do this as it means
5285 that other types such as complex int are also double word aligned.
5286 However, we're stuck with this because changing the ABI might break
5287 existing library interfaces.
5289 Doubleword align SPE vectors.
5290 Quadword align Altivec vectors.
5291 Quadword align large synthetic vector types. */
5294 function_arg_boundary (enum machine_mode mode, tree type)
5296 if (DEFAULT_ABI == ABI_V4
5297 && (GET_MODE_SIZE (mode) == 8
5298 || (TARGET_HARD_FLOAT
5300 && (mode == TFmode || mode == TDmode))))
5302 else if (SPE_VECTOR_MODE (mode)
5303 || (type && TREE_CODE (type) == VECTOR_TYPE
5304 && int_size_in_bytes (type) >= 8
5305 && int_size_in_bytes (type) < 16))
5307 else if (ALTIVEC_VECTOR_MODE (mode)
5308 || (type && TREE_CODE (type) == VECTOR_TYPE
5309 && int_size_in_bytes (type) >= 16))
5311 else if (rs6000_darwin64_abi && mode == BLKmode
5312 && type && TYPE_ALIGN (type) > 64)
5315 return PARM_BOUNDARY;
5318 /* For a function parm of MODE and TYPE, return the starting word in
5319 the parameter area. NWORDS of the parameter area are already used. */
5322 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
5325 unsigned int parm_offset;
5327 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5328 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5329 return nwords + (-(parm_offset + nwords) & align);
5332 /* Compute the size (in words) of a function argument. */
5334 static unsigned long
5335 rs6000_arg_size (enum machine_mode mode, tree type)
5339 if (mode != BLKmode)
5340 size = GET_MODE_SIZE (mode);
5342 size = int_size_in_bytes (type);
5345 return (size + 3) >> 2;
5347 return (size + 7) >> 3;
5350 /* Use this to flush pending int fields. */
5353 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5354 HOST_WIDE_INT bitpos)
5356 unsigned int startbit, endbit;
5357 int intregs, intoffset;
5358 enum machine_mode mode;
5360 if (cum->intoffset == -1)
5363 intoffset = cum->intoffset;
5364 cum->intoffset = -1;
5366 if (intoffset % BITS_PER_WORD != 0)
5368 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5370 if (mode == BLKmode)
5372 /* We couldn't find an appropriate mode, which happens,
5373 e.g., in packed structs when there are 3 bytes to load.
5374 Back intoffset back to the beginning of the word in this
5376 intoffset = intoffset & -BITS_PER_WORD;
5380 startbit = intoffset & -BITS_PER_WORD;
5381 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5382 intregs = (endbit - startbit) / BITS_PER_WORD;
5383 cum->words += intregs;
5386 /* The darwin64 ABI calls for us to recurse down through structs,
5387 looking for elements passed in registers. Unfortunately, we have
5388 to track int register count here also because of misalignments
5389 in powerpc alignment mode. */
5392 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5394 HOST_WIDE_INT startbitpos)
5398 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5399 if (TREE_CODE (f) == FIELD_DECL)
5401 HOST_WIDE_INT bitpos = startbitpos;
5402 tree ftype = TREE_TYPE (f);
5403 enum machine_mode mode;
5404 if (ftype == error_mark_node)
5406 mode = TYPE_MODE (ftype);
5408 if (DECL_SIZE (f) != 0
5409 && host_integerp (bit_position (f), 1))
5410 bitpos += int_bit_position (f);
5412 /* ??? FIXME: else assume zero offset. */
5414 if (TREE_CODE (ftype) == RECORD_TYPE)
5415 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5416 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5418 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5419 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5420 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5422 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5424 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5428 else if (cum->intoffset == -1)
5429 cum->intoffset = bitpos;
5433 /* Update the data in CUM to advance over an argument
5434 of mode MODE and data type TYPE.
5435 (TYPE is null for libcalls where that information may not be available.)
5437 Note that for args passed by reference, function_arg will be called
5438 with MODE and TYPE set to that of the pointer to the arg, not the arg
5442 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5443 tree type, int named, int depth)
5447 /* Only tick off an argument if we're not recursing. */
5449 cum->nargs_prototype--;
5451 if (TARGET_ALTIVEC_ABI
5452 && (ALTIVEC_VECTOR_MODE (mode)
5453 || (type && TREE_CODE (type) == VECTOR_TYPE
5454 && int_size_in_bytes (type) == 16)))
5458 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5461 if (!TARGET_ALTIVEC)
5462 error ("cannot pass argument in vector register because"
5463 " altivec instructions are disabled, use -maltivec"
5466 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5467 even if it is going to be passed in a vector register.
5468 Darwin does the same for variable-argument functions. */
5469 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5470 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5480 /* Vector parameters must be 16-byte aligned. This places
5481 them at 2 mod 4 in terms of words in 32-bit mode, since
5482 the parameter save area starts at offset 24 from the
5483 stack. In 64-bit mode, they just have to start on an
5484 even word, since the parameter save area is 16-byte
5485 aligned. Space for GPRs is reserved even if the argument
5486 will be passed in memory. */
5488 align = (2 - cum->words) & 3;
5490 align = cum->words & 1;
5491 cum->words += align + rs6000_arg_size (mode, type);
5493 if (TARGET_DEBUG_ARG)
5495 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5497 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5498 cum->nargs_prototype, cum->prototype,
5499 GET_MODE_NAME (mode));
5503 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5505 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5508 else if (rs6000_darwin64_abi
5510 && TREE_CODE (type) == RECORD_TYPE
5511 && (size = int_size_in_bytes (type)) > 0)
5513 /* Variable sized types have size == -1 and are
5514 treated as if consisting entirely of ints.
5515 Pad to 16 byte boundary if needed. */
5516 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5517 && (cum->words % 2) != 0)
5519 /* For varargs, we can just go up by the size of the struct. */
5521 cum->words += (size + 7) / 8;
5524 /* It is tempting to say int register count just goes up by
5525 sizeof(type)/8, but this is wrong in a case such as
5526 { int; double; int; } [powerpc alignment]. We have to
5527 grovel through the fields for these too. */
5529 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5530 rs6000_darwin64_record_arg_advance_flush (cum,
5531 size * BITS_PER_UNIT);
5534 else if (DEFAULT_ABI == ABI_V4)
5536 if (TARGET_HARD_FLOAT && TARGET_FPRS
5537 && (mode == SFmode || mode == DFmode
5538 || mode == SDmode || mode == DDmode || mode == TDmode
5539 || (mode == TFmode && !TARGET_IEEEQUAD)))
5541 /* _Decimal128 must use an even/odd register pair. This assumes
5542 that the register number is odd when fregno is odd. */
5543 if (mode == TDmode && (cum->fregno % 2) == 1)
5546 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5547 <= FP_ARG_V4_MAX_REG)
5548 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5551 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5552 if (mode == DFmode || mode == TFmode
5553 || mode == DDmode || mode == TDmode)
5554 cum->words += cum->words & 1;
5555 cum->words += rs6000_arg_size (mode, type);
5560 int n_words = rs6000_arg_size (mode, type);
5561 int gregno = cum->sysv_gregno;
5563 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5564 (r7,r8) or (r9,r10). As does any other 2 word item such
5565 as complex int due to a historical mistake. */
5567 gregno += (1 - gregno) & 1;
5569 /* Multi-reg args are not split between registers and stack. */
5570 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5572 /* Long long and SPE vectors are aligned on the stack.
5573 So are other 2 word items such as complex int due to
5574 a historical mistake. */
5576 cum->words += cum->words & 1;
5577 cum->words += n_words;
5580 /* Note: continuing to accumulate gregno past when we've started
5581 spilling to the stack indicates the fact that we've started
5582 spilling to the stack to expand_builtin_saveregs. */
5583 cum->sysv_gregno = gregno + n_words;
5586 if (TARGET_DEBUG_ARG)
5588 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5589 cum->words, cum->fregno);
5590 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5591 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5592 fprintf (stderr, "mode = %4s, named = %d\n",
5593 GET_MODE_NAME (mode), named);
5598 int n_words = rs6000_arg_size (mode, type);
5599 int start_words = cum->words;
5600 int align_words = rs6000_parm_start (mode, type, start_words);
5602 cum->words = align_words + n_words;
5604 if (SCALAR_FLOAT_MODE_P (mode)
5605 && TARGET_HARD_FLOAT && TARGET_FPRS)
5607 /* _Decimal128 must be passed in an even/odd float register pair.
5608 This assumes that the register number is odd when fregno is
5610 if (mode == TDmode && (cum->fregno % 2) == 1)
5612 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5615 if (TARGET_DEBUG_ARG)
5617 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5618 cum->words, cum->fregno);
5619 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5620 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5621 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5622 named, align_words - start_words, depth);
5628 spe_build_register_parallel (enum machine_mode mode, int gregno)
5636 r1 = gen_rtx_REG (DImode, gregno);
5637 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5638 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5643 r1 = gen_rtx_REG (DImode, gregno);
5644 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5645 r3 = gen_rtx_REG (DImode, gregno + 2);
5646 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5647 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5650 r1 = gen_rtx_REG (DImode, gregno);
5651 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5652 r3 = gen_rtx_REG (DImode, gregno + 2);
5653 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5654 r5 = gen_rtx_REG (DImode, gregno + 4);
5655 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5656 r7 = gen_rtx_REG (DImode, gregno + 6);
5657 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5658 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5665 /* Determine where to put a SIMD argument on the SPE. */
5667 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5670 int gregno = cum->sysv_gregno;
5672 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5673 are passed and returned in a pair of GPRs for ABI compatibility. */
5674 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5675 || mode == DDmode || mode == TDmode
5676 || mode == DCmode || mode == TCmode))
5678 int n_words = rs6000_arg_size (mode, type);
5680 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5681 if (mode == DFmode || mode == DDmode)
5682 gregno += (1 - gregno) & 1;
5684 /* Multi-reg args are not split between registers and stack. */
5685 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5688 return spe_build_register_parallel (mode, gregno);
5692 int n_words = rs6000_arg_size (mode, type);
5694 /* SPE vectors are put in odd registers. */
5695 if (n_words == 2 && (gregno & 1) == 0)
5698 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5701 enum machine_mode m = SImode;
5703 r1 = gen_rtx_REG (m, gregno);
5704 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5705 r2 = gen_rtx_REG (m, gregno + 1);
5706 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5707 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5714 if (gregno <= GP_ARG_MAX_REG)
5715 return gen_rtx_REG (mode, gregno);
5721 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5722 structure between cum->intoffset and bitpos to integer registers. */
5725 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5726 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5728 enum machine_mode mode;
5730 unsigned int startbit, endbit;
5731 int this_regno, intregs, intoffset;
5734 if (cum->intoffset == -1)
5737 intoffset = cum->intoffset;
5738 cum->intoffset = -1;
5740 /* If this is the trailing part of a word, try to only load that
5741 much into the register. Otherwise load the whole register. Note
5742 that in the latter case we may pick up unwanted bits. It's not a
5743 problem at the moment but may wish to revisit. */
5745 if (intoffset % BITS_PER_WORD != 0)
5747 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5749 if (mode == BLKmode)
5751 /* We couldn't find an appropriate mode, which happens,
5752 e.g., in packed structs when there are 3 bytes to load.
5753 Back intoffset back to the beginning of the word in this
5755 intoffset = intoffset & -BITS_PER_WORD;
5762 startbit = intoffset & -BITS_PER_WORD;
5763 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5764 intregs = (endbit - startbit) / BITS_PER_WORD;
5765 this_regno = cum->words + intoffset / BITS_PER_WORD;
5767 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5770 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5774 intoffset /= BITS_PER_UNIT;
5777 regno = GP_ARG_MIN_REG + this_regno;
5778 reg = gen_rtx_REG (mode, regno);
5780 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5783 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5787 while (intregs > 0);
5790 /* Recursive workhorse for the following. */
5793 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
5794 HOST_WIDE_INT startbitpos, rtx rvec[],
5799 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5800 if (TREE_CODE (f) == FIELD_DECL)
5802 HOST_WIDE_INT bitpos = startbitpos;
5803 tree ftype = TREE_TYPE (f);
5804 enum machine_mode mode;
5805 if (ftype == error_mark_node)
5807 mode = TYPE_MODE (ftype);
5809 if (DECL_SIZE (f) != 0
5810 && host_integerp (bit_position (f), 1))
5811 bitpos += int_bit_position (f);
5813 /* ??? FIXME: else assume zero offset. */
5815 if (TREE_CODE (ftype) == RECORD_TYPE)
5816 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5817 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5822 case SCmode: mode = SFmode; break;
5823 case DCmode: mode = DFmode; break;
5824 case TCmode: mode = TFmode; break;
5828 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5830 = gen_rtx_EXPR_LIST (VOIDmode,
5831 gen_rtx_REG (mode, cum->fregno++),
5832 GEN_INT (bitpos / BITS_PER_UNIT));
5833 if (mode == TFmode || mode == TDmode)
5836 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5838 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5840 = gen_rtx_EXPR_LIST (VOIDmode,
5841 gen_rtx_REG (mode, cum->vregno++),
5842 GEN_INT (bitpos / BITS_PER_UNIT));
5844 else if (cum->intoffset == -1)
5845 cum->intoffset = bitpos;
5849 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5850 the register(s) to be used for each field and subfield of a struct
5851 being passed by value, along with the offset of where the
5852 register's value may be found in the block. FP fields go in FP
5853 register, vector fields go in vector registers, and everything
5854 else goes in int registers, packed as in memory.
5856 This code is also used for function return values. RETVAL indicates
5857 whether this is the case.
5859 Much of this is taken from the SPARC V9 port, which has a similar
5860 calling convention. */
5863 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
5864 int named, bool retval)
5866 rtx rvec[FIRST_PSEUDO_REGISTER];
5867 int k = 1, kbase = 1;
5868 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5869 /* This is a copy; modifications are not visible to our caller. */
5870 CUMULATIVE_ARGS copy_cum = *orig_cum;
5871 CUMULATIVE_ARGS *cum = ©_cum;
5873 /* Pad to 16 byte boundary if needed. */
5874 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5875 && (cum->words % 2) != 0)
5882 /* Put entries into rvec[] for individual FP and vector fields, and
5883 for the chunks of memory that go in int regs. Note we start at
5884 element 1; 0 is reserved for an indication of using memory, and
5885 may or may not be filled in below. */
5886 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5887 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5889 /* If any part of the struct went on the stack put all of it there.
5890 This hack is because the generic code for
5891 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5892 parts of the struct are not at the beginning. */
5896 return NULL_RTX; /* doesn't go in registers at all */
5898 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5900 if (k > 1 || cum->use_stack)
5901 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5906 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5909 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5913 rtx rvec[GP_ARG_NUM_REG + 1];
5915 if (align_words >= GP_ARG_NUM_REG)
5918 n_units = rs6000_arg_size (mode, type);
5920 /* Optimize the simple case where the arg fits in one gpr, except in
5921 the case of BLKmode due to assign_parms assuming that registers are
5922 BITS_PER_WORD wide. */
5924 || (n_units == 1 && mode != BLKmode))
5925 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5928 if (align_words + n_units > GP_ARG_NUM_REG)
5929 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5930 using a magic NULL_RTX component.
5931 This is not strictly correct. Only some of the arg belongs in
5932 memory, not all of it. However, the normal scheme using
5933 function_arg_partial_nregs can result in unusual subregs, eg.
5934 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5935 store the whole arg to memory is often more efficient than code
5936 to store pieces, and we know that space is available in the right
5937 place for the whole arg. */
5938 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5943 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5944 rtx off = GEN_INT (i++ * 4);
5945 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5947 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5949 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5952 /* Determine where to put an argument to a function.
5953 Value is zero to push the argument on the stack,
5954 or a hard register in which to store the argument.
5956 MODE is the argument's machine mode.
5957 TYPE is the data type of the argument (as a tree).
5958 This is null for libcalls where that information may
5960 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5961 the preceding args and about the function being called. It is
5962 not modified in this routine.
5963 NAMED is nonzero if this argument is a named parameter
5964 (otherwise it is an extra parameter matching an ellipsis).
5966 On RS/6000 the first eight words of non-FP are normally in registers
5967 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5968 Under V.4, the first 8 FP args are in registers.
5970 If this is floating-point and no prototype is specified, we use
5971 both an FP and integer register (or possibly FP reg and stack). Library
5972 functions (when CALL_LIBCALL is set) always have the proper types for args,
5973 so we can pass the FP value just in one register. emit_library_function
5974 doesn't support PARALLEL anyway.
5976 Note that for args passed by reference, function_arg will be called
5977 with MODE and TYPE set to that of the pointer to the arg, not the arg
5981 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5982 tree type, int named)
5984 enum rs6000_abi abi = DEFAULT_ABI;
5986 /* Return a marker to indicate whether CR1 needs to set or clear the
5987 bit that V.4 uses to say fp args were passed in registers.
5988 Assume that we don't need the marker for software floating point,
5989 or compiler generated library calls. */
5990 if (mode == VOIDmode)
5993 && (cum->call_cookie & CALL_LIBCALL) == 0
5995 || (cum->nargs_prototype < 0
5996 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5998 /* For the SPE, we need to crxor CR6 always. */
6000 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
6001 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
6002 return GEN_INT (cum->call_cookie
6003 | ((cum->fregno == FP_ARG_MIN_REG)
6004 ? CALL_V4_SET_FP_ARGS
6005 : CALL_V4_CLEAR_FP_ARGS));
6008 return GEN_INT (cum->call_cookie);
6011 if (rs6000_darwin64_abi && mode == BLKmode
6012 && TREE_CODE (type) == RECORD_TYPE)
6014 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
6015 if (rslt != NULL_RTX)
6017 /* Else fall through to usual handling. */
6020 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
6021 if (TARGET_64BIT && ! cum->prototype)
6023 /* Vector parameters get passed in vector register
6024 and also in GPRs or memory, in absence of prototype. */
6027 align_words = (cum->words + 1) & ~1;
6029 if (align_words >= GP_ARG_NUM_REG)
6035 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6037 return gen_rtx_PARALLEL (mode,
6039 gen_rtx_EXPR_LIST (VOIDmode,
6041 gen_rtx_EXPR_LIST (VOIDmode,
6042 gen_rtx_REG (mode, cum->vregno),
6046 return gen_rtx_REG (mode, cum->vregno);
6047 else if (TARGET_ALTIVEC_ABI
6048 && (ALTIVEC_VECTOR_MODE (mode)
6049 || (type && TREE_CODE (type) == VECTOR_TYPE
6050 && int_size_in_bytes (type) == 16)))
6052 if (named || abi == ABI_V4)
6056 /* Vector parameters to varargs functions under AIX or Darwin
6057 get passed in memory and possibly also in GPRs. */
6058 int align, align_words, n_words;
6059 enum machine_mode part_mode;
6061 /* Vector parameters must be 16-byte aligned. This places them at
6062 2 mod 4 in terms of words in 32-bit mode, since the parameter
6063 save area starts at offset 24 from the stack. In 64-bit mode,
6064 they just have to start on an even word, since the parameter
6065 save area is 16-byte aligned. */
6067 align = (2 - cum->words) & 3;
6069 align = cum->words & 1;
6070 align_words = cum->words + align;
6072 /* Out of registers? Memory, then. */
6073 if (align_words >= GP_ARG_NUM_REG)
6076 if (TARGET_32BIT && TARGET_POWERPC64)
6077 return rs6000_mixed_function_arg (mode, type, align_words);
6079 /* The vector value goes in GPRs. Only the part of the
6080 value in GPRs is reported here. */
6082 n_words = rs6000_arg_size (mode, type);
6083 if (align_words + n_words > GP_ARG_NUM_REG)
6084 /* Fortunately, there are only two possibilities, the value
6085 is either wholly in GPRs or half in GPRs and half not. */
6088 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
6091 else if (TARGET_SPE_ABI && TARGET_SPE
6092 && (SPE_VECTOR_MODE (mode)
6093 || (TARGET_E500_DOUBLE && (mode == DFmode
6098 || mode == TCmode))))
6099 return rs6000_spe_function_arg (cum, mode, type);
6101 else if (abi == ABI_V4)
6103 if (TARGET_HARD_FLOAT && TARGET_FPRS
6104 && (mode == SFmode || mode == DFmode
6105 || (mode == TFmode && !TARGET_IEEEQUAD)
6106 || mode == SDmode || mode == DDmode || mode == TDmode))
6108 /* _Decimal128 must use an even/odd register pair. This assumes
6109 that the register number is odd when fregno is odd. */
6110 if (mode == TDmode && (cum->fregno % 2) == 1)
6113 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
6114 <= FP_ARG_V4_MAX_REG)
6115 return gen_rtx_REG (mode, cum->fregno);
6121 int n_words = rs6000_arg_size (mode, type);
6122 int gregno = cum->sysv_gregno;
6124 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6125 (r7,r8) or (r9,r10). As does any other 2 word item such
6126 as complex int due to a historical mistake. */
6128 gregno += (1 - gregno) & 1;
6130 /* Multi-reg args are not split between registers and stack. */
6131 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
6134 if (TARGET_32BIT && TARGET_POWERPC64)
6135 return rs6000_mixed_function_arg (mode, type,
6136 gregno - GP_ARG_MIN_REG);
6137 return gen_rtx_REG (mode, gregno);
6142 int align_words = rs6000_parm_start (mode, type, cum->words);
6144 /* _Decimal128 must be passed in an even/odd float register pair.
6145 This assumes that the register number is odd when fregno is odd. */
6146 if (mode == TDmode && (cum->fregno % 2) == 1)
6149 if (USE_FP_FOR_ARG_P (cum, mode, type))
6151 rtx rvec[GP_ARG_NUM_REG + 1];
6155 enum machine_mode fmode = mode;
6156 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
6158 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
6160 /* Currently, we only ever need one reg here because complex
6161 doubles are split. */
6162 gcc_assert (cum->fregno == FP_ARG_MAX_REG
6163 && (fmode == TFmode || fmode == TDmode));
6165 /* Long double or _Decimal128 split over regs and memory. */
6166 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
6169 /* Do we also need to pass this arg in the parameter save
6172 && (cum->nargs_prototype <= 0
6173 || (DEFAULT_ABI == ABI_AIX
6175 && align_words >= GP_ARG_NUM_REG)));
6177 if (!needs_psave && mode == fmode)
6178 return gen_rtx_REG (fmode, cum->fregno);
6183 /* Describe the part that goes in gprs or the stack.
6184 This piece must come first, before the fprs. */
6185 if (align_words < GP_ARG_NUM_REG)
6187 unsigned long n_words = rs6000_arg_size (mode, type);
6189 if (align_words + n_words > GP_ARG_NUM_REG
6190 || (TARGET_32BIT && TARGET_POWERPC64))
6192 /* If this is partially on the stack, then we only
6193 include the portion actually in registers here. */
6194 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
6197 if (align_words + n_words > GP_ARG_NUM_REG)
6198 /* Not all of the arg fits in gprs. Say that it
6199 goes in memory too, using a magic NULL_RTX
6200 component. Also see comment in
6201 rs6000_mixed_function_arg for why the normal
6202 function_arg_partial_nregs scheme doesn't work
6204 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
6208 r = gen_rtx_REG (rmode,
6209 GP_ARG_MIN_REG + align_words);
6210 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
6211 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6213 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
6217 /* The whole arg fits in gprs. */
6218 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6219 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6223 /* It's entirely in memory. */
6224 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6227 /* Describe where this piece goes in the fprs. */
6228 r = gen_rtx_REG (fmode, cum->fregno);
6229 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6231 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6233 else if (align_words < GP_ARG_NUM_REG)
6235 if (TARGET_32BIT && TARGET_POWERPC64)
6236 return rs6000_mixed_function_arg (mode, type, align_words);
6238 if (mode == BLKmode)
6241 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6248 /* For an arg passed partly in registers and partly in memory, this is
6249 the number of bytes passed in registers. For args passed entirely in
6250 registers or entirely in memory, zero. When an arg is described by a
6251 PARALLEL, perhaps using more than one register type, this function
6252 returns the number of bytes used by the first element of the PARALLEL. */
6255 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6256 tree type, bool named)
6261 if (DEFAULT_ABI == ABI_V4)
6264 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
6265 && cum->nargs_prototype >= 0)
6268 /* In this complicated case we just disable the partial_nregs code. */
6269 if (rs6000_darwin64_abi && mode == BLKmode
6270 && TREE_CODE (type) == RECORD_TYPE
6271 && int_size_in_bytes (type) > 0)
6274 align_words = rs6000_parm_start (mode, type, cum->words);
6276 if (USE_FP_FOR_ARG_P (cum, mode, type))
6278 /* If we are passing this arg in the fixed parameter save area
6279 (gprs or memory) as well as fprs, then this function should
6280 return the number of partial bytes passed in the parameter
6281 save area rather than partial bytes passed in fprs. */
6283 && (cum->nargs_prototype <= 0
6284 || (DEFAULT_ABI == ABI_AIX
6286 && align_words >= GP_ARG_NUM_REG)))
6288 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
6289 > FP_ARG_MAX_REG + 1)
6290 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
6291 else if (cum->nargs_prototype >= 0)
6295 if (align_words < GP_ARG_NUM_REG
6296 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
6297 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
6299 if (ret != 0 && TARGET_DEBUG_ARG)
6300 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
6305 /* A C expression that indicates when an argument must be passed by
6306 reference. If nonzero for an argument, a copy of that argument is
6307 made in memory and a pointer to the argument is passed instead of
6308 the argument itself. The pointer is passed in whatever way is
6309 appropriate for passing a pointer to that type.
6311 Under V.4, aggregates and long double are passed by reference.
6313 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6314 reference unless the AltiVec vector extension ABI is in force.
6316 As an extension to all ABIs, variable sized types are passed by
6320 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6321 enum machine_mode mode, const_tree type,
6322 bool named ATTRIBUTE_UNUSED)
6324 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
6326 if (TARGET_DEBUG_ARG)
6327 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6334 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6336 if (TARGET_DEBUG_ARG)
6337 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6341 if (int_size_in_bytes (type) < 0)
6343 if (TARGET_DEBUG_ARG)
6344 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6348 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6349 modes only exist for GCC vector types if -maltivec. */
6350 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6352 if (TARGET_DEBUG_ARG)
6353 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6357 /* Pass synthetic vectors in memory. */
6358 if (TREE_CODE (type) == VECTOR_TYPE
6359 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6361 static bool warned_for_pass_big_vectors = false;
6362 if (TARGET_DEBUG_ARG)
6363 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6364 if (!warned_for_pass_big_vectors)
6366 warning (0, "GCC vector passed by reference: "
6367 "non-standard ABI extension with no compatibility guarantee");
6368 warned_for_pass_big_vectors = true;
6377 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6380 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6385 for (i = 0; i < nregs; i++)
6387 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6388 if (reload_completed)
6390 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6393 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6394 i * GET_MODE_SIZE (reg_mode));
6397 tem = replace_equiv_address (tem, XEXP (tem, 0));
6401 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6405 /* Perform any needed actions needed for a function that is receiving a
6406 variable number of arguments.
6410 MODE and TYPE are the mode and type of the current parameter.
6412 PRETEND_SIZE is a variable that should be set to the amount of stack
6413 that must be pushed by the prolog to pretend that our caller pushed
6416 Normally, this macro will push all remaining incoming registers on the
6417 stack and set PRETEND_SIZE to the length of the registers pushed. */
6420 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6421 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6424 CUMULATIVE_ARGS next_cum;
6425 int reg_size = TARGET_32BIT ? 4 : 8;
6426 rtx save_area = NULL_RTX, mem;
6427 int first_reg_offset;
6430 /* Skip the last named argument. */
6432 function_arg_advance (&next_cum, mode, type, 1, 0);
6434 if (DEFAULT_ABI == ABI_V4)
6436 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6440 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6441 HOST_WIDE_INT offset = 0;
6443 /* Try to optimize the size of the varargs save area.
6444 The ABI requires that ap.reg_save_area is doubleword
6445 aligned, but we don't need to allocate space for all
6446 the bytes, only those to which we actually will save
6448 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6449 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6450 if (TARGET_HARD_FLOAT && TARGET_FPRS
6451 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6452 && cfun->va_list_fpr_size)
6455 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6456 * UNITS_PER_FP_WORD;
6457 if (cfun->va_list_fpr_size
6458 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6459 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6461 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6462 * UNITS_PER_FP_WORD;
6466 offset = -((first_reg_offset * reg_size) & ~7);
6467 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6469 gpr_reg_num = cfun->va_list_gpr_size;
6470 if (reg_size == 4 && (first_reg_offset & 1))
6473 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6476 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6478 - (int) (GP_ARG_NUM_REG * reg_size);
6480 if (gpr_size + fpr_size)
6483 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6484 gcc_assert (GET_CODE (reg_save_area) == MEM);
6485 reg_save_area = XEXP (reg_save_area, 0);
6486 if (GET_CODE (reg_save_area) == PLUS)
6488 gcc_assert (XEXP (reg_save_area, 0)
6489 == virtual_stack_vars_rtx);
6490 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6491 offset += INTVAL (XEXP (reg_save_area, 1));
6494 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6497 cfun->machine->varargs_save_offset = offset;
6498 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6503 first_reg_offset = next_cum.words;
6504 save_area = virtual_incoming_args_rtx;
6506 if (targetm.calls.must_pass_in_stack (mode, type))
6507 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6510 set = get_varargs_alias_set ();
6511 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6512 && cfun->va_list_gpr_size)
6514 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6516 if (va_list_gpr_counter_field)
6518 /* V4 va_list_gpr_size counts number of registers needed. */
6519 if (nregs > cfun->va_list_gpr_size)
6520 nregs = cfun->va_list_gpr_size;
6524 /* char * va_list instead counts number of bytes needed. */
6525 if (nregs > cfun->va_list_gpr_size / reg_size)
6526 nregs = cfun->va_list_gpr_size / reg_size;
6529 mem = gen_rtx_MEM (BLKmode,
6530 plus_constant (save_area,
6531 first_reg_offset * reg_size));
6532 MEM_NOTRAP_P (mem) = 1;
6533 set_mem_alias_set (mem, set);
6534 set_mem_align (mem, BITS_PER_WORD);
6536 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6540 /* Save FP registers if needed. */
6541 if (DEFAULT_ABI == ABI_V4
6542 && TARGET_HARD_FLOAT && TARGET_FPRS
6544 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6545 && cfun->va_list_fpr_size)
6547 int fregno = next_cum.fregno, nregs;
6548 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6549 rtx lab = gen_label_rtx ();
6550 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6551 * UNITS_PER_FP_WORD);
6554 (gen_rtx_SET (VOIDmode,
6556 gen_rtx_IF_THEN_ELSE (VOIDmode,
6557 gen_rtx_NE (VOIDmode, cr1,
6559 gen_rtx_LABEL_REF (VOIDmode, lab),
6563 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6564 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6566 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6567 MEM_NOTRAP_P (mem) = 1;
6568 set_mem_alias_set (mem, set);
6569 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6570 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6577 /* Create the va_list data type. */
6580 rs6000_build_builtin_va_list (void)
6582 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6584 /* For AIX, prefer 'char *' because that's what the system
6585 header files like. */
6586 if (DEFAULT_ABI != ABI_V4)
6587 return build_pointer_type (char_type_node);
6589 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6590 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6592 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6593 unsigned_char_type_node);
6594 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6595 unsigned_char_type_node);
6596 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6598 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6599 short_unsigned_type_node);
6600 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6602 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6605 va_list_gpr_counter_field = f_gpr;
6606 va_list_fpr_counter_field = f_fpr;
6608 DECL_FIELD_CONTEXT (f_gpr) = record;
6609 DECL_FIELD_CONTEXT (f_fpr) = record;
6610 DECL_FIELD_CONTEXT (f_res) = record;
6611 DECL_FIELD_CONTEXT (f_ovf) = record;
6612 DECL_FIELD_CONTEXT (f_sav) = record;
6614 TREE_CHAIN (record) = type_decl;
6615 TYPE_NAME (record) = type_decl;
6616 TYPE_FIELDS (record) = f_gpr;
6617 TREE_CHAIN (f_gpr) = f_fpr;
6618 TREE_CHAIN (f_fpr) = f_res;
6619 TREE_CHAIN (f_res) = f_ovf;
6620 TREE_CHAIN (f_ovf) = f_sav;
6622 layout_type (record);
6624 /* The correct type is an array type of one element. */
6625 return build_array_type (record, build_index_type (size_zero_node));
6628 /* Implement va_start. */
6631 rs6000_va_start (tree valist, rtx nextarg)
6633 HOST_WIDE_INT words, n_gpr, n_fpr;
6634 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6635 tree gpr, fpr, ovf, sav, t;
6637 /* Only SVR4 needs something special. */
6638 if (DEFAULT_ABI != ABI_V4)
6640 std_expand_builtin_va_start (valist, nextarg);
6644 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6645 f_fpr = TREE_CHAIN (f_gpr);
6646 f_res = TREE_CHAIN (f_fpr);
6647 f_ovf = TREE_CHAIN (f_res);
6648 f_sav = TREE_CHAIN (f_ovf);
6650 valist = build_va_arg_indirect_ref (valist);
6651 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6652 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6653 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6654 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6656 /* Count number of gp and fp argument registers used. */
6657 words = current_function_args_info.words;
6658 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6660 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6663 if (TARGET_DEBUG_ARG)
6664 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6665 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6666 words, n_gpr, n_fpr);
6668 if (cfun->va_list_gpr_size)
6670 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6671 build_int_cst (NULL_TREE, n_gpr));
6672 TREE_SIDE_EFFECTS (t) = 1;
6673 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6676 if (cfun->va_list_fpr_size)
6678 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6679 build_int_cst (NULL_TREE, n_fpr));
6680 TREE_SIDE_EFFECTS (t) = 1;
6681 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6684 /* Find the overflow area. */
6685 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6687 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6688 size_int (words * UNITS_PER_WORD));
6689 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6690 TREE_SIDE_EFFECTS (t) = 1;
6691 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6693 /* If there were no va_arg invocations, don't set up the register
6695 if (!cfun->va_list_gpr_size
6696 && !cfun->va_list_fpr_size
6697 && n_gpr < GP_ARG_NUM_REG
6698 && n_fpr < FP_ARG_V4_MAX_REG)
6701 /* Find the register save area. */
6702 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6703 if (cfun->machine->varargs_save_offset)
6704 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6705 size_int (cfun->machine->varargs_save_offset));
6706 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6707 TREE_SIDE_EFFECTS (t) = 1;
6708 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6711 /* Implement va_arg. */
6714 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6716 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6717 tree gpr, fpr, ovf, sav, reg, t, u;
6718 int size, rsize, n_reg, sav_ofs, sav_scale;
6719 tree lab_false, lab_over, addr;
6721 tree ptrtype = build_pointer_type (type);
6724 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6726 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6727 return build_va_arg_indirect_ref (t);
6730 if (DEFAULT_ABI != ABI_V4)
6732 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6734 tree elem_type = TREE_TYPE (type);
6735 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6736 int elem_size = GET_MODE_SIZE (elem_mode);
6738 if (elem_size < UNITS_PER_WORD)
6740 tree real_part, imag_part;
6741 tree post = NULL_TREE;
6743 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6745 /* Copy the value into a temporary, lest the formal temporary
6746 be reused out from under us. */
6747 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6748 append_to_statement_list (post, pre_p);
6750 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6753 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6757 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6760 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6761 f_fpr = TREE_CHAIN (f_gpr);
6762 f_res = TREE_CHAIN (f_fpr);
6763 f_ovf = TREE_CHAIN (f_res);
6764 f_sav = TREE_CHAIN (f_ovf);
6766 valist = build_va_arg_indirect_ref (valist);
6767 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6768 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6769 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6770 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6772 size = int_size_in_bytes (type);
6773 rsize = (size + 3) / 4;
6776 if (TARGET_HARD_FLOAT && TARGET_FPRS
6777 && (TYPE_MODE (type) == SFmode
6778 || TYPE_MODE (type) == DFmode
6779 || TYPE_MODE (type) == TFmode
6780 || TYPE_MODE (type) == SDmode
6781 || TYPE_MODE (type) == DDmode
6782 || TYPE_MODE (type) == TDmode))
6784 /* FP args go in FP registers, if present. */
6786 n_reg = (size + 7) / 8;
6789 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
6794 /* Otherwise into GP registers. */
6803 /* Pull the value out of the saved registers.... */
6806 addr = create_tmp_var (ptr_type_node, "addr");
6807 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6809 /* AltiVec vectors never go in registers when -mabi=altivec. */
6810 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6814 lab_false = create_artificial_label ();
6815 lab_over = create_artificial_label ();
6817 /* Long long and SPE vectors are aligned in the registers.
6818 As are any other 2 gpr item such as complex int due to a
6819 historical mistake. */
6821 if (n_reg == 2 && reg == gpr)
6824 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6825 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6826 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6828 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6829 reg number is 0 for f1, so we want to make it odd. */
6830 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6833 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6834 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6837 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6838 t = build2 (GE_EXPR, boolean_type_node, u, t);
6839 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6840 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6841 gimplify_and_add (t, pre_p);
6845 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6847 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
6848 build_int_cst (TREE_TYPE (reg), n_reg));
6849 u = fold_convert (sizetype, u);
6850 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6851 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6853 /* _Decimal32 varargs are located in the second word of the 64-bit
6854 FP register for 32-bit binaries. */
6855 if (!TARGET_POWERPC64 && TYPE_MODE (type) == SDmode)
6856 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6858 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6859 gimplify_and_add (t, pre_p);
6861 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6862 gimplify_and_add (t, pre_p);
6864 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6865 append_to_statement_list (t, pre_p);
6867 if ((n_reg == 2 && !regalign) || n_reg > 2)
6869 /* Ensure that we don't find any more args in regs.
6870 Alignment has taken care of for special cases. */
6871 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6872 gimplify_and_add (t, pre_p);
6876 /* ... otherwise out of the overflow area. */
6878 /* Care for on-stack alignment if needed. */
6882 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6883 t = fold_convert (sizetype, t);
6884 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6886 t = fold_convert (TREE_TYPE (ovf), t);
6888 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6890 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6891 gimplify_and_add (u, pre_p);
6893 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6894 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6895 gimplify_and_add (t, pre_p);
6899 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6900 append_to_statement_list (t, pre_p);
6903 if (STRICT_ALIGNMENT
6904 && (TYPE_ALIGN (type)
6905 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6907 /* The value (of type complex double, for example) may not be
6908 aligned in memory in the saved registers, so copy via a
6909 temporary. (This is the same code as used for SPARC.) */
6910 tree tmp = create_tmp_var (type, "va_arg_tmp");
6911 tree dest_addr = build_fold_addr_expr (tmp);
6913 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6914 3, dest_addr, addr, size_int (rsize * 4));
6916 gimplify_and_add (copy, pre_p);
6920 addr = fold_convert (ptrtype, addr);
6921 return build_va_arg_indirect_ref (addr);
6927 def_builtin (int mask, const char *name, tree type, int code)
6929 if ((mask & target_flags) || TARGET_PAIRED_FLOAT)
6931 if (rs6000_builtin_decls[code])
6934 rs6000_builtin_decls[code] =
6935 add_builtin_function (name, type, code, BUILT_IN_MD,
6940 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6942 static const struct builtin_description bdesc_3arg[] =
6944 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6945 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6946 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6947 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6948 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6949 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6950 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6951 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6952 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6953 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6954 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6955 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6956 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6957 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6958 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6959 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6960 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6961 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6962 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6963 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6964 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6965 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6966 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6968 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6969 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6970 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6971 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6972 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6973 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6974 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6975 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6976 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6977 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6978 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6979 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6980 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6981 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6982 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6984 { 0, CODE_FOR_paired_msub, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB },
6985 { 0, CODE_FOR_paired_madd, "__builtin_paired_madd", PAIRED_BUILTIN_MADD },
6986 { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 },
6987 { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 },
6988 { 0, CODE_FOR_paired_nmsub, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB },
6989 { 0, CODE_FOR_paired_nmadd, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD },
6990 { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 },
6991 { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 },
6992 { 0, CODE_FOR_selv2sf4, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4 },
6995 /* DST operations: void foo (void *, const int, const char). */
6997 static const struct builtin_description bdesc_dst[] =
6999 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
7000 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
7001 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
7002 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
7004 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
7005 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
7006 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
7007 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
7010 /* Simple binary operations: VECc = foo (VECa, VECb). */
7012 static struct builtin_description bdesc_2arg[] =
7014 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
7015 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
7016 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
7017 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
7018 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
7019 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
7020 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
7021 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
7022 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
7023 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
7024 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
7025 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
7026 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
7027 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
7028 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
7029 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
7030 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
7031 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
7032 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
7033 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
7034 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
7035 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
7036 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
7037 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
7038 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
7039 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
7040 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
7041 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
7042 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
7043 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
7044 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
7045 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
7046 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
7047 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
7048 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
7049 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
7050 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
7051 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
7052 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
7053 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
7054 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
7055 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
7056 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
7057 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
7058 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
7059 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
7060 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
7061 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
7062 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
7063 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
7064 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
7065 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
7066 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
7067 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
7068 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
7069 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
7070 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
7071 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
7072 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
7073 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
7074 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
7075 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
7076 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
7077 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
7078 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
7079 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
7080 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
7081 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
7082 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
7083 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
7084 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
7085 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
7086 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
7087 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
7088 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
7089 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
7090 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
7091 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
7092 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
7093 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
7094 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
7095 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
7096 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
7097 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
7098 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
7099 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
7100 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
7101 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
7102 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
7103 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
7104 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
7105 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
7106 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
7107 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
7108 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
7109 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
7110 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
7111 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
7112 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
7113 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
7114 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
7115 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
7116 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
7117 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
7118 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
7119 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
7120 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
7121 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
7122 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
7123 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
7124 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
7126 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
7127 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
7128 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
7129 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
7130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
7131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
7132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
7133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
7134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
7135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
7136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
7137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
7138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
7139 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
7140 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
7141 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
7142 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
7143 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
7144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
7145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
7146 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
7147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
7148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
7149 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
7150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
7151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
7152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
7153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
7154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
7155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
7156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
7157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
7158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
7159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
7160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
7161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
7162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
7163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
7164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
7165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
7166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
7167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
7168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
7169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
7170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
7171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
7172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
7173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
7174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
7175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
7176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
7177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
7178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
7179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
7180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
7181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
7182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
7183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
7184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
7185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
7186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
7187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
7188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
7189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
7190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
7191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
7192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
7193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
7194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
7195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
7196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
7197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
7198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
7199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
7200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
7201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
7202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
7203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
7204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
7205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
7206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
7207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
7208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
7209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
7210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
7211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
7212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
7213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
7214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
7215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
7216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
7217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
7218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
7219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
7220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
7221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
7222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
7223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
7224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
7225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
7226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
7227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
7228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
7229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
7230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
7231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
7232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
7233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
7234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
7235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
7236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
7237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
7238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
7239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
7240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
7241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
7242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
7243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
7244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
7245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
7246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
7247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
7248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
7249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
7250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
7251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
7252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
7254 { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
7255 { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
7256 { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
7257 { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
7258 { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
7259 { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
7260 { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
7261 { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 },
7262 { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 },
7263 { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
7265 /* Place holder, leave as first spe builtin. */
7266 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
7267 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
7268 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
7269 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
7270 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
7271 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
7272 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
7273 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
7274 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
7275 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
7276 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
7277 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
7278 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
7279 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
7280 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
7281 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
7282 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
7283 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
7284 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
7285 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
7286 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
7287 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
7288 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
7289 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
7290 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
7291 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
7292 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
7293 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
7294 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
7295 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
7296 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
7297 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
7298 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
7299 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
7300 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
7301 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
7302 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
7303 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
7304 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
7305 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
7306 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
7307 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
7308 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
7309 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
7310 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
7311 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
7312 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
7313 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
7314 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
7315 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
7316 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
7317 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
7318 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
7319 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
7320 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
7321 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
7322 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
7323 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
7324 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
7325 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
7326 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
7327 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
7328 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
7329 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
7330 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
7331 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
7332 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
7333 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
7334 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
7335 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
7336 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
7337 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
7338 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
7339 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
7340 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
7341 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
7342 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
7343 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
7344 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
7345 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
7346 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
7347 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
7348 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
7349 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
7350 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
7351 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
7352 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
7353 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
7354 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
7355 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
7356 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
7357 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
7358 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7359 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7360 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7361 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7362 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7363 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7364 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7365 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7366 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7367 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7368 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7369 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7370 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7371 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7372 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7373 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7374 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7376 /* SPE binary operations expecting a 5-bit unsigned literal. */
7377 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7379 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7380 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7381 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7382 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7383 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7384 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7385 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7386 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7387 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7388 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7389 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7390 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7391 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7392 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7393 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7394 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7395 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7396 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7397 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7398 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7399 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7400 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7401 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7402 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7403 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7404 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7406 /* Place-holder. Leave as last binary SPE builtin. */
7407 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7410 /* AltiVec predicates. */
7412 struct builtin_description_predicates
7414 const unsigned int mask;
7415 const enum insn_code icode;
7417 const char *const name;
7418 const enum rs6000_builtins code;
7421 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7423 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7424 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7425 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7426 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7427 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7428 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7429 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7430 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7431 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7432 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7433 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7434 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7435 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7437 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7438 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7439 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7442 /* SPE predicates. */
7443 static struct builtin_description bdesc_spe_predicates[] =
7445 /* Place-holder. Leave as first. */
7446 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7447 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7448 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7449 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7450 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7451 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7452 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7453 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7454 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7455 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7456 /* Place-holder. Leave as last. */
7457 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7460 /* SPE evsel predicates. */
7461 static struct builtin_description bdesc_spe_evsel[] =
7463 /* Place-holder. Leave as first. */
7464 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7465 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7466 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7467 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7468 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7469 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7470 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7471 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7472 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7473 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7474 /* Place-holder. Leave as last. */
7475 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7478 /* PAIRED predicates. */
7479 static const struct builtin_description bdesc_paired_preds[] =
7481 /* Place-holder. Leave as first. */
7482 { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 },
7483 /* Place-holder. Leave as last. */
7484 { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 },
7487 /* ABS* operations. */
7489 static const struct builtin_description bdesc_abs[] =
7491 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7492 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7493 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7494 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7495 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7496 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7497 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7500 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7503 static struct builtin_description bdesc_1arg[] =
7505 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7506 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7507 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7508 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7509 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7510 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7511 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7512 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7513 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7514 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7515 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7516 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7517 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7518 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7519 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7520 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7521 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7523 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7524 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7525 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7526 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7527 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7528 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7529 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7530 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7531 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7532 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7533 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7534 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7535 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7536 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7537 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7538 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7539 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7540 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7541 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7543 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7544 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7545 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7546 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7547 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7548 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7549 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7550 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7551 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7552 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7553 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7554 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7555 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7556 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7557 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7558 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7559 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7560 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7561 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7562 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7563 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7564 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7565 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7566 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7567 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7568 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7569 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7570 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7571 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7572 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7574 /* Place-holder. Leave as last unary SPE builtin. */
7575 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
7577 { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
7578 { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
7579 { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
7580 { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
7581 { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
7585 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7588 tree arg0 = CALL_EXPR_ARG (exp, 0);
7589 rtx op0 = expand_normal (arg0);
7590 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7591 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7593 if (icode == CODE_FOR_nothing)
7594 /* Builtin not supported on this processor. */
7597 /* If we got invalid arguments bail out before generating bad rtl. */
7598 if (arg0 == error_mark_node)
7601 if (icode == CODE_FOR_altivec_vspltisb
7602 || icode == CODE_FOR_altivec_vspltish
7603 || icode == CODE_FOR_altivec_vspltisw
7604 || icode == CODE_FOR_spe_evsplatfi
7605 || icode == CODE_FOR_spe_evsplati)
7607 /* Only allow 5-bit *signed* literals. */
7608 if (GET_CODE (op0) != CONST_INT
7609 || INTVAL (op0) > 15
7610 || INTVAL (op0) < -16)
7612 error ("argument 1 must be a 5-bit signed literal");
7618 || GET_MODE (target) != tmode
7619 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7620 target = gen_reg_rtx (tmode);
7622 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7623 op0 = copy_to_mode_reg (mode0, op0);
7625 pat = GEN_FCN (icode) (target, op0);
7634 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7636 rtx pat, scratch1, scratch2;
7637 tree arg0 = CALL_EXPR_ARG (exp, 0);
7638 rtx op0 = expand_normal (arg0);
7639 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7640 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7642 /* If we have invalid arguments, bail out before generating bad rtl. */
7643 if (arg0 == error_mark_node)
7647 || GET_MODE (target) != tmode
7648 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7649 target = gen_reg_rtx (tmode);
7651 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7652 op0 = copy_to_mode_reg (mode0, op0);
7654 scratch1 = gen_reg_rtx (mode0);
7655 scratch2 = gen_reg_rtx (mode0);
7657 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7666 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7669 tree arg0 = CALL_EXPR_ARG (exp, 0);
7670 tree arg1 = CALL_EXPR_ARG (exp, 1);
7671 rtx op0 = expand_normal (arg0);
7672 rtx op1 = expand_normal (arg1);
7673 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7674 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7675 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7677 if (icode == CODE_FOR_nothing)
7678 /* Builtin not supported on this processor. */
7681 /* If we got invalid arguments bail out before generating bad rtl. */
7682 if (arg0 == error_mark_node || arg1 == error_mark_node)
7685 if (icode == CODE_FOR_altivec_vcfux
7686 || icode == CODE_FOR_altivec_vcfsx
7687 || icode == CODE_FOR_altivec_vctsxs
7688 || icode == CODE_FOR_altivec_vctuxs
7689 || icode == CODE_FOR_altivec_vspltb
7690 || icode == CODE_FOR_altivec_vsplth
7691 || icode == CODE_FOR_altivec_vspltw
7692 || icode == CODE_FOR_spe_evaddiw
7693 || icode == CODE_FOR_spe_evldd
7694 || icode == CODE_FOR_spe_evldh
7695 || icode == CODE_FOR_spe_evldw
7696 || icode == CODE_FOR_spe_evlhhesplat
7697 || icode == CODE_FOR_spe_evlhhossplat
7698 || icode == CODE_FOR_spe_evlhhousplat
7699 || icode == CODE_FOR_spe_evlwhe
7700 || icode == CODE_FOR_spe_evlwhos
7701 || icode == CODE_FOR_spe_evlwhou
7702 || icode == CODE_FOR_spe_evlwhsplat
7703 || icode == CODE_FOR_spe_evlwwsplat
7704 || icode == CODE_FOR_spe_evrlwi
7705 || icode == CODE_FOR_spe_evslwi
7706 || icode == CODE_FOR_spe_evsrwis
7707 || icode == CODE_FOR_spe_evsubifw
7708 || icode == CODE_FOR_spe_evsrwiu)
7710 /* Only allow 5-bit unsigned literals. */
7712 if (TREE_CODE (arg1) != INTEGER_CST
7713 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7715 error ("argument 2 must be a 5-bit unsigned literal");
7721 || GET_MODE (target) != tmode
7722 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7723 target = gen_reg_rtx (tmode);
7725 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7726 op0 = copy_to_mode_reg (mode0, op0);
7727 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7728 op1 = copy_to_mode_reg (mode1, op1);
7730 pat = GEN_FCN (icode) (target, op0, op1);
7739 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7740 tree exp, rtx target)
7743 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7744 tree arg0 = CALL_EXPR_ARG (exp, 1);
7745 tree arg1 = CALL_EXPR_ARG (exp, 2);
7746 rtx op0 = expand_normal (arg0);
7747 rtx op1 = expand_normal (arg1);
7748 enum machine_mode tmode = SImode;
7749 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7750 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7753 if (TREE_CODE (cr6_form) != INTEGER_CST)
7755 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7759 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7761 gcc_assert (mode0 == mode1);
7763 /* If we have invalid arguments, bail out before generating bad rtl. */
7764 if (arg0 == error_mark_node || arg1 == error_mark_node)
7768 || GET_MODE (target) != tmode
7769 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7770 target = gen_reg_rtx (tmode);
7772 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7773 op0 = copy_to_mode_reg (mode0, op0);
7774 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7775 op1 = copy_to_mode_reg (mode1, op1);
7777 scratch = gen_reg_rtx (mode0);
7779 pat = GEN_FCN (icode) (scratch, op0, op1,
7780 gen_rtx_SYMBOL_REF (Pmode, opcode));
7785 /* The vec_any* and vec_all* predicates use the same opcodes for two
7786 different operations, but the bits in CR6 will be different
7787 depending on what information we want. So we have to play tricks
7788 with CR6 to get the right bits out.
7790 If you think this is disgusting, look at the specs for the
7791 AltiVec predicates. */
7793 switch (cr6_form_int)
7796 emit_insn (gen_cr6_test_for_zero (target));
7799 emit_insn (gen_cr6_test_for_zero_reverse (target));
7802 emit_insn (gen_cr6_test_for_lt (target));
7805 emit_insn (gen_cr6_test_for_lt_reverse (target));
7808 error ("argument 1 of __builtin_altivec_predicate is out of range");
7816 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7819 tree arg0 = CALL_EXPR_ARG (exp, 0);
7820 tree arg1 = CALL_EXPR_ARG (exp, 1);
7821 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7822 enum machine_mode mode0 = Pmode;
7823 enum machine_mode mode1 = Pmode;
7824 rtx op0 = expand_normal (arg0);
7825 rtx op1 = expand_normal (arg1);
7827 if (icode == CODE_FOR_nothing)
7828 /* Builtin not supported on this processor. */
7831 /* If we got invalid arguments bail out before generating bad rtl. */
7832 if (arg0 == error_mark_node || arg1 == error_mark_node)
7836 || GET_MODE (target) != tmode
7837 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7838 target = gen_reg_rtx (tmode);
7840 op1 = copy_to_mode_reg (mode1, op1);
7842 if (op0 == const0_rtx)
7844 addr = gen_rtx_MEM (tmode, op1);
7848 op0 = copy_to_mode_reg (mode0, op0);
7849 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7852 pat = GEN_FCN (icode) (target, addr);
7862 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7865 tree arg0 = CALL_EXPR_ARG (exp, 0);
7866 tree arg1 = CALL_EXPR_ARG (exp, 1);
7867 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7868 enum machine_mode mode0 = Pmode;
7869 enum machine_mode mode1 = Pmode;
7870 rtx op0 = expand_normal (arg0);
7871 rtx op1 = expand_normal (arg1);
7873 if (icode == CODE_FOR_nothing)
7874 /* Builtin not supported on this processor. */
7877 /* If we got invalid arguments bail out before generating bad rtl. */
7878 if (arg0 == error_mark_node || arg1 == error_mark_node)
7882 || GET_MODE (target) != tmode
7883 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7884 target = gen_reg_rtx (tmode);
7886 op1 = copy_to_mode_reg (mode1, op1);
7888 if (op0 == const0_rtx)
7890 addr = gen_rtx_MEM (tmode, op1);
7894 op0 = copy_to_mode_reg (mode0, op0);
7895 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7898 pat = GEN_FCN (icode) (target, addr);
7908 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7910 tree arg0 = CALL_EXPR_ARG (exp, 0);
7911 tree arg1 = CALL_EXPR_ARG (exp, 1);
7912 tree arg2 = CALL_EXPR_ARG (exp, 2);
7913 rtx op0 = expand_normal (arg0);
7914 rtx op1 = expand_normal (arg1);
7915 rtx op2 = expand_normal (arg2);
7917 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7918 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7919 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7921 /* Invalid arguments. Bail before doing anything stoopid! */
7922 if (arg0 == error_mark_node
7923 || arg1 == error_mark_node
7924 || arg2 == error_mark_node)
7927 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7928 op0 = copy_to_mode_reg (mode2, op0);
7929 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7930 op1 = copy_to_mode_reg (mode0, op1);
7931 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7932 op2 = copy_to_mode_reg (mode1, op2);
7934 pat = GEN_FCN (icode) (op1, op2, op0);
7941 paired_expand_stv_builtin (enum insn_code icode, tree exp)
7943 tree arg0 = CALL_EXPR_ARG (exp, 0);
7944 tree arg1 = CALL_EXPR_ARG (exp, 1);
7945 tree arg2 = CALL_EXPR_ARG (exp, 2);
7946 rtx op0 = expand_normal (arg0);
7947 rtx op1 = expand_normal (arg1);
7948 rtx op2 = expand_normal (arg2);
7950 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7951 enum machine_mode mode1 = Pmode;
7952 enum machine_mode mode2 = Pmode;
7954 /* Invalid arguments. Bail before doing anything stoopid! */
7955 if (arg0 == error_mark_node
7956 || arg1 == error_mark_node
7957 || arg2 == error_mark_node)
7960 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7961 op0 = copy_to_mode_reg (tmode, op0);
7963 op2 = copy_to_mode_reg (mode2, op2);
7965 if (op1 == const0_rtx)
7967 addr = gen_rtx_MEM (tmode, op2);
7971 op1 = copy_to_mode_reg (mode1, op1);
7972 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7975 pat = GEN_FCN (icode) (addr, op0);
7982 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7984 tree arg0 = CALL_EXPR_ARG (exp, 0);
7985 tree arg1 = CALL_EXPR_ARG (exp, 1);
7986 tree arg2 = CALL_EXPR_ARG (exp, 2);
7987 rtx op0 = expand_normal (arg0);
7988 rtx op1 = expand_normal (arg1);
7989 rtx op2 = expand_normal (arg2);
7991 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7992 enum machine_mode mode1 = Pmode;
7993 enum machine_mode mode2 = Pmode;
7995 /* Invalid arguments. Bail before doing anything stoopid! */
7996 if (arg0 == error_mark_node
7997 || arg1 == error_mark_node
7998 || arg2 == error_mark_node)
8001 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
8002 op0 = copy_to_mode_reg (tmode, op0);
8004 op2 = copy_to_mode_reg (mode2, op2);
8006 if (op1 == const0_rtx)
8008 addr = gen_rtx_MEM (tmode, op2);
8012 op1 = copy_to_mode_reg (mode1, op1);
8013 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
8016 pat = GEN_FCN (icode) (addr, op0);
8023 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
8026 tree arg0 = CALL_EXPR_ARG (exp, 0);
8027 tree arg1 = CALL_EXPR_ARG (exp, 1);
8028 tree arg2 = CALL_EXPR_ARG (exp, 2);
8029 rtx op0 = expand_normal (arg0);
8030 rtx op1 = expand_normal (arg1);
8031 rtx op2 = expand_normal (arg2);
8032 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8033 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8034 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8035 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
8037 if (icode == CODE_FOR_nothing)
8038 /* Builtin not supported on this processor. */
8041 /* If we got invalid arguments bail out before generating bad rtl. */
8042 if (arg0 == error_mark_node
8043 || arg1 == error_mark_node
8044 || arg2 == error_mark_node)
8047 if (icode == CODE_FOR_altivec_vsldoi_v4sf
8048 || icode == CODE_FOR_altivec_vsldoi_v4si
8049 || icode == CODE_FOR_altivec_vsldoi_v8hi
8050 || icode == CODE_FOR_altivec_vsldoi_v16qi)
8052 /* Only allow 4-bit unsigned literals. */
8054 if (TREE_CODE (arg2) != INTEGER_CST
8055 || TREE_INT_CST_LOW (arg2) & ~0xf)
8057 error ("argument 3 must be a 4-bit unsigned literal");
8063 || GET_MODE (target) != tmode
8064 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8065 target = gen_reg_rtx (tmode);
8067 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8068 op0 = copy_to_mode_reg (mode0, op0);
8069 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8070 op1 = copy_to_mode_reg (mode1, op1);
8071 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
8072 op2 = copy_to_mode_reg (mode2, op2);
8074 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
8075 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
8077 pat = GEN_FCN (icode) (target, op0, op1, op2);
8085 /* Expand the lvx builtins. */
8087 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
8089 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8090 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8092 enum machine_mode tmode, mode0;
8094 enum insn_code icode;
8098 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
8099 icode = CODE_FOR_altivec_lvx_v16qi;
8101 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
8102 icode = CODE_FOR_altivec_lvx_v8hi;
8104 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
8105 icode = CODE_FOR_altivec_lvx_v4si;
8107 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
8108 icode = CODE_FOR_altivec_lvx_v4sf;
8117 arg0 = CALL_EXPR_ARG (exp, 0);
8118 op0 = expand_normal (arg0);
8119 tmode = insn_data[icode].operand[0].mode;
8120 mode0 = insn_data[icode].operand[1].mode;
8123 || GET_MODE (target) != tmode
8124 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8125 target = gen_reg_rtx (tmode);
8127 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8128 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8130 pat = GEN_FCN (icode) (target, op0);
8137 /* Expand the stvx builtins. */
8139 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8142 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8143 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8145 enum machine_mode mode0, mode1;
8147 enum insn_code icode;
8151 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
8152 icode = CODE_FOR_altivec_stvx_v16qi;
8154 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
8155 icode = CODE_FOR_altivec_stvx_v8hi;
8157 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
8158 icode = CODE_FOR_altivec_stvx_v4si;
8160 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
8161 icode = CODE_FOR_altivec_stvx_v4sf;
8168 arg0 = CALL_EXPR_ARG (exp, 0);
8169 arg1 = CALL_EXPR_ARG (exp, 1);
8170 op0 = expand_normal (arg0);
8171 op1 = expand_normal (arg1);
8172 mode0 = insn_data[icode].operand[0].mode;
8173 mode1 = insn_data[icode].operand[1].mode;
8175 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8176 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8177 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8178 op1 = copy_to_mode_reg (mode1, op1);
8180 pat = GEN_FCN (icode) (op0, op1);
8188 /* Expand the dst builtins. */
8190 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8193 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8194 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8195 tree arg0, arg1, arg2;
8196 enum machine_mode mode0, mode1, mode2;
8197 rtx pat, op0, op1, op2;
8198 const struct builtin_description *d;
8203 /* Handle DST variants. */
8205 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8206 if (d->code == fcode)
8208 arg0 = CALL_EXPR_ARG (exp, 0);
8209 arg1 = CALL_EXPR_ARG (exp, 1);
8210 arg2 = CALL_EXPR_ARG (exp, 2);
8211 op0 = expand_normal (arg0);
8212 op1 = expand_normal (arg1);
8213 op2 = expand_normal (arg2);
8214 mode0 = insn_data[d->icode].operand[0].mode;
8215 mode1 = insn_data[d->icode].operand[1].mode;
8216 mode2 = insn_data[d->icode].operand[2].mode;
8218 /* Invalid arguments, bail out before generating bad rtl. */
8219 if (arg0 == error_mark_node
8220 || arg1 == error_mark_node
8221 || arg2 == error_mark_node)
8226 if (TREE_CODE (arg2) != INTEGER_CST
8227 || TREE_INT_CST_LOW (arg2) & ~0x3)
8229 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
8233 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
8234 op0 = copy_to_mode_reg (Pmode, op0);
8235 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
8236 op1 = copy_to_mode_reg (mode1, op1);
8238 pat = GEN_FCN (d->icode) (op0, op1, op2);
8248 /* Expand vec_init builtin. */
8250 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
8252 enum machine_mode tmode = TYPE_MODE (type);
8253 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
8254 int i, n_elt = GET_MODE_NUNITS (tmode);
8255 rtvec v = rtvec_alloc (n_elt);
8257 gcc_assert (VECTOR_MODE_P (tmode));
8258 gcc_assert (n_elt == call_expr_nargs (exp));
8260 for (i = 0; i < n_elt; ++i)
8262 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
8263 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
8266 if (!target || !register_operand (target, tmode))
8267 target = gen_reg_rtx (tmode);
8269 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
8273 /* Return the integer constant in ARG. Constrain it to be in the range
8274 of the subparts of VEC_TYPE; issue an error if not. */
8277 get_element_number (tree vec_type, tree arg)
8279 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
8281 if (!host_integerp (arg, 1)
8282 || (elt = tree_low_cst (arg, 1), elt > max))
8284 error ("selector must be an integer constant in the range 0..%wi", max);
8291 /* Expand vec_set builtin. */
8293 altivec_expand_vec_set_builtin (tree exp)
8295 enum machine_mode tmode, mode1;
8296 tree arg0, arg1, arg2;
8300 arg0 = CALL_EXPR_ARG (exp, 0);
8301 arg1 = CALL_EXPR_ARG (exp, 1);
8302 arg2 = CALL_EXPR_ARG (exp, 2);
8304 tmode = TYPE_MODE (TREE_TYPE (arg0));
8305 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8306 gcc_assert (VECTOR_MODE_P (tmode));
8308 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
8309 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
8310 elt = get_element_number (TREE_TYPE (arg0), arg2);
8312 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
8313 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
8315 op0 = force_reg (tmode, op0);
8316 op1 = force_reg (mode1, op1);
8318 rs6000_expand_vector_set (op0, op1, elt);
8323 /* Expand vec_ext builtin. */
8325 altivec_expand_vec_ext_builtin (tree exp, rtx target)
8327 enum machine_mode tmode, mode0;
8332 arg0 = CALL_EXPR_ARG (exp, 0);
8333 arg1 = CALL_EXPR_ARG (exp, 1);
8335 op0 = expand_normal (arg0);
8336 elt = get_element_number (TREE_TYPE (arg0), arg1);
8338 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8339 mode0 = TYPE_MODE (TREE_TYPE (arg0));
8340 gcc_assert (VECTOR_MODE_P (mode0));
8342 op0 = force_reg (mode0, op0);
8344 if (optimize || !target || !register_operand (target, tmode))
8345 target = gen_reg_rtx (tmode);
8347 rs6000_expand_vector_extract (target, op0, elt);
8352 /* Expand the builtin in EXP and store the result in TARGET. Store
8353 true in *EXPANDEDP if we found a builtin to expand. */
8355 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
8357 const struct builtin_description *d;
8358 const struct builtin_description_predicates *dp;
8360 enum insn_code icode;
8361 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8364 enum machine_mode tmode, mode0;
8365 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8367 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8368 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
8371 error ("unresolved overload for Altivec builtin %qF", fndecl);
8375 target = altivec_expand_ld_builtin (exp, target, expandedp);
8379 target = altivec_expand_st_builtin (exp, target, expandedp);
8383 target = altivec_expand_dst_builtin (exp, target, expandedp);
8391 case ALTIVEC_BUILTIN_STVX:
8392 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
8393 case ALTIVEC_BUILTIN_STVEBX:
8394 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
8395 case ALTIVEC_BUILTIN_STVEHX:
8396 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
8397 case ALTIVEC_BUILTIN_STVEWX:
8398 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
8399 case ALTIVEC_BUILTIN_STVXL:
8400 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
8402 case ALTIVEC_BUILTIN_MFVSCR:
8403 icode = CODE_FOR_altivec_mfvscr;
8404 tmode = insn_data[icode].operand[0].mode;
8407 || GET_MODE (target) != tmode
8408 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8409 target = gen_reg_rtx (tmode);
8411 pat = GEN_FCN (icode) (target);
8417 case ALTIVEC_BUILTIN_MTVSCR:
8418 icode = CODE_FOR_altivec_mtvscr;
8419 arg0 = CALL_EXPR_ARG (exp, 0);
8420 op0 = expand_normal (arg0);
8421 mode0 = insn_data[icode].operand[0].mode;
8423 /* If we got invalid arguments bail out before generating bad rtl. */
8424 if (arg0 == error_mark_node)
8427 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8428 op0 = copy_to_mode_reg (mode0, op0);
8430 pat = GEN_FCN (icode) (op0);
8435 case ALTIVEC_BUILTIN_DSSALL:
8436 emit_insn (gen_altivec_dssall ());
8439 case ALTIVEC_BUILTIN_DSS:
8440 icode = CODE_FOR_altivec_dss;
8441 arg0 = CALL_EXPR_ARG (exp, 0);
8443 op0 = expand_normal (arg0);
8444 mode0 = insn_data[icode].operand[0].mode;
8446 /* If we got invalid arguments bail out before generating bad rtl. */
8447 if (arg0 == error_mark_node)
8450 if (TREE_CODE (arg0) != INTEGER_CST
8451 || TREE_INT_CST_LOW (arg0) & ~0x3)
8453 error ("argument to dss must be a 2-bit unsigned literal");
8457 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8458 op0 = copy_to_mode_reg (mode0, op0);
8460 emit_insn (gen_altivec_dss (op0));
8463 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8464 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8465 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8466 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8467 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8469 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8470 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8471 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8472 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8473 return altivec_expand_vec_set_builtin (exp);
8475 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8476 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8477 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8478 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8479 return altivec_expand_vec_ext_builtin (exp, target);
8486 /* Expand abs* operations. */
8488 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8489 if (d->code == fcode)
8490 return altivec_expand_abs_builtin (d->icode, exp, target);
8492 /* Expand the AltiVec predicates. */
8493 dp = bdesc_altivec_preds;
8494 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8495 if (dp->code == fcode)
8496 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8499 /* LV* are funky. We initialized them differently. */
8502 case ALTIVEC_BUILTIN_LVSL:
8503 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8505 case ALTIVEC_BUILTIN_LVSR:
8506 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8508 case ALTIVEC_BUILTIN_LVEBX:
8509 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8511 case ALTIVEC_BUILTIN_LVEHX:
8512 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8514 case ALTIVEC_BUILTIN_LVEWX:
8515 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8517 case ALTIVEC_BUILTIN_LVXL:
8518 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8520 case ALTIVEC_BUILTIN_LVX:
8521 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8532 /* Expand the builtin in EXP and store the result in TARGET. Store
8533 true in *EXPANDEDP if we found a builtin to expand. */
8535 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
8537 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8538 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8539 const struct builtin_description *d;
8546 case PAIRED_BUILTIN_STX:
8547 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
8548 case PAIRED_BUILTIN_LX:
8549 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
8555 /* Expand the paired predicates. */
8556 d = bdesc_paired_preds;
8557 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
8558 if (d->code == fcode)
8559 return paired_expand_predicate_builtin (d->icode, exp, target);
8565 /* Binops that need to be initialized manually, but can be expanded
8566 automagically by rs6000_expand_binop_builtin. */
8567 static struct builtin_description bdesc_2arg_spe[] =
8569 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8570 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8571 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8572 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8573 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8574 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8575 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8576 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8577 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8578 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8579 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8580 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8581 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8582 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8583 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8584 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8585 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8586 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8587 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8588 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8589 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8590 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8593 /* Expand the builtin in EXP and store the result in TARGET. Store
8594 true in *EXPANDEDP if we found a builtin to expand.
8596 This expands the SPE builtins that are not simple unary and binary
8599 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8601 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8603 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8604 enum insn_code icode;
8605 enum machine_mode tmode, mode0;
8607 struct builtin_description *d;
8612 /* Syntax check for a 5-bit unsigned immediate. */
8615 case SPE_BUILTIN_EVSTDD:
8616 case SPE_BUILTIN_EVSTDH:
8617 case SPE_BUILTIN_EVSTDW:
8618 case SPE_BUILTIN_EVSTWHE:
8619 case SPE_BUILTIN_EVSTWHO:
8620 case SPE_BUILTIN_EVSTWWE:
8621 case SPE_BUILTIN_EVSTWWO:
8622 arg1 = CALL_EXPR_ARG (exp, 2);
8623 if (TREE_CODE (arg1) != INTEGER_CST
8624 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8626 error ("argument 2 must be a 5-bit unsigned literal");
8634 /* The evsplat*i instructions are not quite generic. */
8637 case SPE_BUILTIN_EVSPLATFI:
8638 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8640 case SPE_BUILTIN_EVSPLATI:
8641 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8647 d = (struct builtin_description *) bdesc_2arg_spe;
8648 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8649 if (d->code == fcode)
8650 return rs6000_expand_binop_builtin (d->icode, exp, target);
8652 d = (struct builtin_description *) bdesc_spe_predicates;
8653 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8654 if (d->code == fcode)
8655 return spe_expand_predicate_builtin (d->icode, exp, target);
8657 d = (struct builtin_description *) bdesc_spe_evsel;
8658 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8659 if (d->code == fcode)
8660 return spe_expand_evsel_builtin (d->icode, exp, target);
8664 case SPE_BUILTIN_EVSTDDX:
8665 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8666 case SPE_BUILTIN_EVSTDHX:
8667 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8668 case SPE_BUILTIN_EVSTDWX:
8669 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8670 case SPE_BUILTIN_EVSTWHEX:
8671 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8672 case SPE_BUILTIN_EVSTWHOX:
8673 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8674 case SPE_BUILTIN_EVSTWWEX:
8675 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8676 case SPE_BUILTIN_EVSTWWOX:
8677 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8678 case SPE_BUILTIN_EVSTDD:
8679 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8680 case SPE_BUILTIN_EVSTDH:
8681 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8682 case SPE_BUILTIN_EVSTDW:
8683 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8684 case SPE_BUILTIN_EVSTWHE:
8685 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8686 case SPE_BUILTIN_EVSTWHO:
8687 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8688 case SPE_BUILTIN_EVSTWWE:
8689 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8690 case SPE_BUILTIN_EVSTWWO:
8691 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8692 case SPE_BUILTIN_MFSPEFSCR:
8693 icode = CODE_FOR_spe_mfspefscr;
8694 tmode = insn_data[icode].operand[0].mode;
8697 || GET_MODE (target) != tmode
8698 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8699 target = gen_reg_rtx (tmode);
8701 pat = GEN_FCN (icode) (target);
8706 case SPE_BUILTIN_MTSPEFSCR:
8707 icode = CODE_FOR_spe_mtspefscr;
8708 arg0 = CALL_EXPR_ARG (exp, 0);
8709 op0 = expand_normal (arg0);
8710 mode0 = insn_data[icode].operand[0].mode;
8712 if (arg0 == error_mark_node)
8715 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8716 op0 = copy_to_mode_reg (mode0, op0);
8718 pat = GEN_FCN (icode) (op0);
8731 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8733 rtx pat, scratch, tmp;
8734 tree form = CALL_EXPR_ARG (exp, 0);
8735 tree arg0 = CALL_EXPR_ARG (exp, 1);
8736 tree arg1 = CALL_EXPR_ARG (exp, 2);
8737 rtx op0 = expand_normal (arg0);
8738 rtx op1 = expand_normal (arg1);
8739 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8740 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8744 if (TREE_CODE (form) != INTEGER_CST)
8746 error ("argument 1 of __builtin_paired_predicate must be a constant");
8750 form_int = TREE_INT_CST_LOW (form);
8752 gcc_assert (mode0 == mode1);
8754 if (arg0 == error_mark_node || arg1 == error_mark_node)
8758 || GET_MODE (target) != SImode
8759 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
8760 target = gen_reg_rtx (SImode);
8761 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
8762 op0 = copy_to_mode_reg (mode0, op0);
8763 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
8764 op1 = copy_to_mode_reg (mode1, op1);
8766 scratch = gen_reg_rtx (CCFPmode);
8768 pat = GEN_FCN (icode) (scratch, op0, op1);
8790 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8793 error ("argument 1 of __builtin_paired_predicate is out of range");
8797 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8798 emit_move_insn (target, tmp);
8803 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8805 rtx pat, scratch, tmp;
8806 tree form = CALL_EXPR_ARG (exp, 0);
8807 tree arg0 = CALL_EXPR_ARG (exp, 1);
8808 tree arg1 = CALL_EXPR_ARG (exp, 2);
8809 rtx op0 = expand_normal (arg0);
8810 rtx op1 = expand_normal (arg1);
8811 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8812 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8816 if (TREE_CODE (form) != INTEGER_CST)
8818 error ("argument 1 of __builtin_spe_predicate must be a constant");
8822 form_int = TREE_INT_CST_LOW (form);
8824 gcc_assert (mode0 == mode1);
8826 if (arg0 == error_mark_node || arg1 == error_mark_node)
8830 || GET_MODE (target) != SImode
8831 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8832 target = gen_reg_rtx (SImode);
8834 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8835 op0 = copy_to_mode_reg (mode0, op0);
8836 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8837 op1 = copy_to_mode_reg (mode1, op1);
8839 scratch = gen_reg_rtx (CCmode);
8841 pat = GEN_FCN (icode) (scratch, op0, op1);
8846 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8847 _lower_. We use one compare, but look in different bits of the
8848 CR for each variant.
8850 There are 2 elements in each SPE simd type (upper/lower). The CR
8851 bits are set as follows:
8853 BIT0 | BIT 1 | BIT 2 | BIT 3
8854 U | L | (U | L) | (U & L)
8856 So, for an "all" relationship, BIT 3 would be set.
8857 For an "any" relationship, BIT 2 would be set. Etc.
8859 Following traditional nomenclature, these bits map to:
8861 BIT0 | BIT 1 | BIT 2 | BIT 3
8864 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8869 /* All variant. OV bit. */
8871 /* We need to get to the OV bit, which is the ORDERED bit. We
8872 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8873 that's ugly and will make validate_condition_mode die.
8874 So let's just use another pattern. */
8875 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8877 /* Any variant. EQ bit. */
8881 /* Upper variant. LT bit. */
8885 /* Lower variant. GT bit. */
8890 error ("argument 1 of __builtin_spe_predicate is out of range");
8894 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8895 emit_move_insn (target, tmp);
8900 /* The evsel builtins look like this:
8902 e = __builtin_spe_evsel_OP (a, b, c, d);
8906 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8907 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8911 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8914 tree arg0 = CALL_EXPR_ARG (exp, 0);
8915 tree arg1 = CALL_EXPR_ARG (exp, 1);
8916 tree arg2 = CALL_EXPR_ARG (exp, 2);
8917 tree arg3 = CALL_EXPR_ARG (exp, 3);
8918 rtx op0 = expand_normal (arg0);
8919 rtx op1 = expand_normal (arg1);
8920 rtx op2 = expand_normal (arg2);
8921 rtx op3 = expand_normal (arg3);
8922 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8923 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8925 gcc_assert (mode0 == mode1);
8927 if (arg0 == error_mark_node || arg1 == error_mark_node
8928 || arg2 == error_mark_node || arg3 == error_mark_node)
8932 || GET_MODE (target) != mode0
8933 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8934 target = gen_reg_rtx (mode0);
8936 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8937 op0 = copy_to_mode_reg (mode0, op0);
8938 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8939 op1 = copy_to_mode_reg (mode0, op1);
8940 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8941 op2 = copy_to_mode_reg (mode0, op2);
8942 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8943 op3 = copy_to_mode_reg (mode0, op3);
8945 /* Generate the compare. */
8946 scratch = gen_reg_rtx (CCmode);
8947 pat = GEN_FCN (icode) (scratch, op0, op1);
8952 if (mode0 == V2SImode)
8953 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8955 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8960 /* Expand an expression EXP that calls a built-in function,
8961 with result going to TARGET if that's convenient
8962 (and in mode MODE if that's convenient).
8963 SUBTARGET may be used as the target for computing one of EXP's operands.
8964 IGNORE is nonzero if the value is to be ignored. */
8967 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8968 enum machine_mode mode ATTRIBUTE_UNUSED,
8969 int ignore ATTRIBUTE_UNUSED)
8971 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8972 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8973 const struct builtin_description *d;
8978 if (fcode == RS6000_BUILTIN_RECIP)
8979 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
8981 if (fcode == RS6000_BUILTIN_RECIPF)
8982 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
8984 if (fcode == RS6000_BUILTIN_RSQRTF)
8985 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
8987 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8988 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8990 int icode = (int) CODE_FOR_altivec_lvsr;
8991 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8992 enum machine_mode mode = insn_data[icode].operand[1].mode;
8996 gcc_assert (TARGET_ALTIVEC);
8998 arg = CALL_EXPR_ARG (exp, 0);
8999 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
9000 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
9001 addr = memory_address (mode, op);
9002 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
9006 /* For the load case need to negate the address. */
9007 op = gen_reg_rtx (GET_MODE (addr));
9008 emit_insn (gen_rtx_SET (VOIDmode, op,
9009 gen_rtx_NEG (GET_MODE (addr), addr)));
9011 op = gen_rtx_MEM (mode, op);
9014 || GET_MODE (target) != tmode
9015 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9016 target = gen_reg_rtx (tmode);
9018 /*pat = gen_altivec_lvsr (target, op);*/
9019 pat = GEN_FCN (icode) (target, op);
9027 /* FIXME: There's got to be a nicer way to handle this case than
9028 constructing a new CALL_EXPR. */
9029 if (fcode == ALTIVEC_BUILTIN_VCFUX
9030 || fcode == ALTIVEC_BUILTIN_VCFSX)
9032 if (call_expr_nargs (exp) == 1)
9033 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
9034 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
9039 ret = altivec_expand_builtin (exp, target, &success);
9046 ret = spe_expand_builtin (exp, target, &success);
9051 if (TARGET_PAIRED_FLOAT)
9053 ret = paired_expand_builtin (exp, target, &success);
9059 gcc_assert (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT);
9061 /* Handle simple unary operations. */
9062 d = (struct builtin_description *) bdesc_1arg;
9063 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9064 if (d->code == fcode)
9065 return rs6000_expand_unop_builtin (d->icode, exp, target);
9067 /* Handle simple binary operations. */
9068 d = (struct builtin_description *) bdesc_2arg;
9069 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9070 if (d->code == fcode)
9071 return rs6000_expand_binop_builtin (d->icode, exp, target);
9073 /* Handle simple ternary operations. */
9075 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9076 if (d->code == fcode)
9077 return rs6000_expand_ternop_builtin (d->icode, exp, target);
9083 build_opaque_vector_type (tree node, int nunits)
9085 node = copy_node (node);
9086 TYPE_MAIN_VARIANT (node) = node;
9087 return build_vector_type (node, nunits);
9091 rs6000_init_builtins (void)
9093 V2SI_type_node = build_vector_type (intSI_type_node, 2);
9094 V2SF_type_node = build_vector_type (float_type_node, 2);
9095 V4HI_type_node = build_vector_type (intHI_type_node, 4);
9096 V4SI_type_node = build_vector_type (intSI_type_node, 4);
9097 V4SF_type_node = build_vector_type (float_type_node, 4);
9098 V8HI_type_node = build_vector_type (intHI_type_node, 8);
9099 V16QI_type_node = build_vector_type (intQI_type_node, 16);
9101 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
9102 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
9103 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
9105 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
9106 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
9107 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
9108 opaque_V4SI_type_node = copy_node (V4SI_type_node);
9110 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9111 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9112 'vector unsigned short'. */
9114 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
9115 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9116 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
9117 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9119 long_integer_type_internal_node = long_integer_type_node;
9120 long_unsigned_type_internal_node = long_unsigned_type_node;
9121 intQI_type_internal_node = intQI_type_node;
9122 uintQI_type_internal_node = unsigned_intQI_type_node;
9123 intHI_type_internal_node = intHI_type_node;
9124 uintHI_type_internal_node = unsigned_intHI_type_node;
9125 intSI_type_internal_node = intSI_type_node;
9126 uintSI_type_internal_node = unsigned_intSI_type_node;
9127 float_type_internal_node = float_type_node;
9128 void_type_internal_node = void_type_node;
9130 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9131 get_identifier ("__bool char"),
9132 bool_char_type_node));
9133 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9134 get_identifier ("__bool short"),
9135 bool_short_type_node));
9136 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9137 get_identifier ("__bool int"),
9138 bool_int_type_node));
9139 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9140 get_identifier ("__pixel"),
9143 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
9144 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
9145 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
9146 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
9148 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9149 get_identifier ("__vector unsigned char"),
9150 unsigned_V16QI_type_node));
9151 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9152 get_identifier ("__vector signed char"),
9154 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9155 get_identifier ("__vector __bool char"),
9156 bool_V16QI_type_node));
9158 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9159 get_identifier ("__vector unsigned short"),
9160 unsigned_V8HI_type_node));
9161 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9162 get_identifier ("__vector signed short"),
9164 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9165 get_identifier ("__vector __bool short"),
9166 bool_V8HI_type_node));
9168 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9169 get_identifier ("__vector unsigned int"),
9170 unsigned_V4SI_type_node));
9171 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9172 get_identifier ("__vector signed int"),
9174 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9175 get_identifier ("__vector __bool int"),
9176 bool_V4SI_type_node));
9178 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9179 get_identifier ("__vector float"),
9181 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9182 get_identifier ("__vector __pixel"),
9183 pixel_V8HI_type_node));
9185 if (TARGET_PAIRED_FLOAT)
9186 paired_init_builtins ();
9188 spe_init_builtins ();
9190 altivec_init_builtins ();
9191 if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT)
9192 rs6000_common_init_builtins ();
9193 if (TARGET_PPC_GFXOPT)
9195 tree ftype = build_function_type_list (float_type_node,
9199 def_builtin (MASK_PPC_GFXOPT, "__builtin_recipdivf", ftype,
9200 RS6000_BUILTIN_RECIPF);
9202 ftype = build_function_type_list (float_type_node,
9205 def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrtf", ftype,
9206 RS6000_BUILTIN_RSQRTF);
9210 tree ftype = build_function_type_list (double_type_node,
9214 def_builtin (MASK_POPCNTB, "__builtin_recipdiv", ftype,
9215 RS6000_BUILTIN_RECIP);
9220 /* AIX libm provides clog as __clog. */
9221 if (built_in_decls [BUILT_IN_CLOG])
9222 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
9225 #ifdef SUBTARGET_INIT_BUILTINS
9226 SUBTARGET_INIT_BUILTINS;
9230 /* Search through a set of builtins and enable the mask bits.
9231 DESC is an array of builtins.
9232 SIZE is the total number of builtins.
9233 START is the builtin enum at which to start.
9234 END is the builtin enum at which to end. */
9236 enable_mask_for_builtins (struct builtin_description *desc, int size,
9237 enum rs6000_builtins start,
9238 enum rs6000_builtins end)
9242 for (i = 0; i < size; ++i)
9243 if (desc[i].code == start)
9249 for (; i < size; ++i)
9251 /* Flip all the bits on. */
9252 desc[i].mask = target_flags;
9253 if (desc[i].code == end)
9259 spe_init_builtins (void)
9261 tree endlink = void_list_node;
9262 tree puint_type_node = build_pointer_type (unsigned_type_node);
9263 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
9264 struct builtin_description *d;
9267 tree v2si_ftype_4_v2si
9268 = build_function_type
9269 (opaque_V2SI_type_node,
9270 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9271 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9272 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9273 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9276 tree v2sf_ftype_4_v2sf
9277 = build_function_type
9278 (opaque_V2SF_type_node,
9279 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9280 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9281 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9282 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9285 tree int_ftype_int_v2si_v2si
9286 = build_function_type
9288 tree_cons (NULL_TREE, integer_type_node,
9289 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9290 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9293 tree int_ftype_int_v2sf_v2sf
9294 = build_function_type
9296 tree_cons (NULL_TREE, integer_type_node,
9297 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9298 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9301 tree void_ftype_v2si_puint_int
9302 = build_function_type (void_type_node,
9303 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9304 tree_cons (NULL_TREE, puint_type_node,
9305 tree_cons (NULL_TREE,
9309 tree void_ftype_v2si_puint_char
9310 = build_function_type (void_type_node,
9311 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9312 tree_cons (NULL_TREE, puint_type_node,
9313 tree_cons (NULL_TREE,
9317 tree void_ftype_v2si_pv2si_int
9318 = build_function_type (void_type_node,
9319 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9320 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9321 tree_cons (NULL_TREE,
9325 tree void_ftype_v2si_pv2si_char
9326 = build_function_type (void_type_node,
9327 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9328 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9329 tree_cons (NULL_TREE,
9334 = build_function_type (void_type_node,
9335 tree_cons (NULL_TREE, integer_type_node, endlink));
9338 = build_function_type (integer_type_node, endlink);
9340 tree v2si_ftype_pv2si_int
9341 = build_function_type (opaque_V2SI_type_node,
9342 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9343 tree_cons (NULL_TREE, integer_type_node,
9346 tree v2si_ftype_puint_int
9347 = build_function_type (opaque_V2SI_type_node,
9348 tree_cons (NULL_TREE, puint_type_node,
9349 tree_cons (NULL_TREE, integer_type_node,
9352 tree v2si_ftype_pushort_int
9353 = build_function_type (opaque_V2SI_type_node,
9354 tree_cons (NULL_TREE, pushort_type_node,
9355 tree_cons (NULL_TREE, integer_type_node,
9358 tree v2si_ftype_signed_char
9359 = build_function_type (opaque_V2SI_type_node,
9360 tree_cons (NULL_TREE, signed_char_type_node,
9363 /* The initialization of the simple binary and unary builtins is
9364 done in rs6000_common_init_builtins, but we have to enable the
9365 mask bits here manually because we have run out of `target_flags'
9366 bits. We really need to redesign this mask business. */
9368 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
9369 ARRAY_SIZE (bdesc_2arg),
9372 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
9373 ARRAY_SIZE (bdesc_1arg),
9375 SPE_BUILTIN_EVSUBFUSIAAW);
9376 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
9377 ARRAY_SIZE (bdesc_spe_predicates),
9378 SPE_BUILTIN_EVCMPEQ,
9379 SPE_BUILTIN_EVFSTSTLT);
9380 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
9381 ARRAY_SIZE (bdesc_spe_evsel),
9382 SPE_BUILTIN_EVSEL_CMPGTS,
9383 SPE_BUILTIN_EVSEL_FSTSTEQ);
9385 (*lang_hooks.decls.pushdecl)
9386 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
9387 opaque_V2SI_type_node));
9389 /* Initialize irregular SPE builtins. */
9391 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
9392 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
9393 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
9394 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
9395 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
9396 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
9397 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
9398 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
9399 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
9400 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
9401 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
9402 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
9403 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
9404 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
9405 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
9406 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
9407 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
9408 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
9411 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
9412 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
9413 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
9414 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
9415 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
9416 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
9417 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
9418 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
9419 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
9420 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
9421 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
9422 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
9423 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
9424 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
9425 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
9426 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
9427 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
9428 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
9429 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
9430 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
9431 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
9432 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
9435 d = (struct builtin_description *) bdesc_spe_predicates;
9436 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
9440 switch (insn_data[d->icode].operand[1].mode)
9443 type = int_ftype_int_v2si_v2si;
9446 type = int_ftype_int_v2sf_v2sf;
9452 def_builtin (d->mask, d->name, type, d->code);
9455 /* Evsel predicates. */
9456 d = (struct builtin_description *) bdesc_spe_evsel;
9457 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
9461 switch (insn_data[d->icode].operand[1].mode)
9464 type = v2si_ftype_4_v2si;
9467 type = v2sf_ftype_4_v2sf;
9473 def_builtin (d->mask, d->name, type, d->code);
9478 paired_init_builtins (void)
9480 const struct builtin_description *d;
9482 tree endlink = void_list_node;
9484 tree int_ftype_int_v2sf_v2sf
9485 = build_function_type
9487 tree_cons (NULL_TREE, integer_type_node,
9488 tree_cons (NULL_TREE, V2SF_type_node,
9489 tree_cons (NULL_TREE, V2SF_type_node,
9491 tree pcfloat_type_node =
9492 build_pointer_type (build_qualified_type
9493 (float_type_node, TYPE_QUAL_CONST));
9495 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
9496 long_integer_type_node,
9499 tree void_ftype_v2sf_long_pcfloat =
9500 build_function_type_list (void_type_node,
9502 long_integer_type_node,
9507 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat,
9511 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
9512 PAIRED_BUILTIN_STX);
9515 d = bdesc_paired_preds;
9516 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
9520 switch (insn_data[d->icode].operand[1].mode)
9523 type = int_ftype_int_v2sf_v2sf;
9529 def_builtin (d->mask, d->name, type, d->code);
9534 altivec_init_builtins (void)
9536 const struct builtin_description *d;
9537 const struct builtin_description_predicates *dp;
9541 tree pfloat_type_node = build_pointer_type (float_type_node);
9542 tree pint_type_node = build_pointer_type (integer_type_node);
9543 tree pshort_type_node = build_pointer_type (short_integer_type_node);
9544 tree pchar_type_node = build_pointer_type (char_type_node);
9546 tree pvoid_type_node = build_pointer_type (void_type_node);
9548 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
9549 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
9550 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
9551 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
9553 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
9555 tree int_ftype_opaque
9556 = build_function_type_list (integer_type_node,
9557 opaque_V4SI_type_node, NULL_TREE);
9559 tree opaque_ftype_opaque_int
9560 = build_function_type_list (opaque_V4SI_type_node,
9561 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
9562 tree opaque_ftype_opaque_opaque_int
9563 = build_function_type_list (opaque_V4SI_type_node,
9564 opaque_V4SI_type_node, opaque_V4SI_type_node,
9565 integer_type_node, NULL_TREE);
9566 tree int_ftype_int_opaque_opaque
9567 = build_function_type_list (integer_type_node,
9568 integer_type_node, opaque_V4SI_type_node,
9569 opaque_V4SI_type_node, NULL_TREE);
9570 tree int_ftype_int_v4si_v4si
9571 = build_function_type_list (integer_type_node,
9572 integer_type_node, V4SI_type_node,
9573 V4SI_type_node, NULL_TREE);
9574 tree v4sf_ftype_pcfloat
9575 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
9576 tree void_ftype_pfloat_v4sf
9577 = build_function_type_list (void_type_node,
9578 pfloat_type_node, V4SF_type_node, NULL_TREE);
9579 tree v4si_ftype_pcint
9580 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
9581 tree void_ftype_pint_v4si
9582 = build_function_type_list (void_type_node,
9583 pint_type_node, V4SI_type_node, NULL_TREE);
9584 tree v8hi_ftype_pcshort
9585 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
9586 tree void_ftype_pshort_v8hi
9587 = build_function_type_list (void_type_node,
9588 pshort_type_node, V8HI_type_node, NULL_TREE);
9589 tree v16qi_ftype_pcchar
9590 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
9591 tree void_ftype_pchar_v16qi
9592 = build_function_type_list (void_type_node,
9593 pchar_type_node, V16QI_type_node, NULL_TREE);
9594 tree void_ftype_v4si
9595 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
9596 tree v8hi_ftype_void
9597 = build_function_type (V8HI_type_node, void_list_node);
9598 tree void_ftype_void
9599 = build_function_type (void_type_node, void_list_node);
9601 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
9603 tree opaque_ftype_long_pcvoid
9604 = build_function_type_list (opaque_V4SI_type_node,
9605 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9606 tree v16qi_ftype_long_pcvoid
9607 = build_function_type_list (V16QI_type_node,
9608 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9609 tree v8hi_ftype_long_pcvoid
9610 = build_function_type_list (V8HI_type_node,
9611 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9612 tree v4si_ftype_long_pcvoid
9613 = build_function_type_list (V4SI_type_node,
9614 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9616 tree void_ftype_opaque_long_pvoid
9617 = build_function_type_list (void_type_node,
9618 opaque_V4SI_type_node, long_integer_type_node,
9619 pvoid_type_node, NULL_TREE);
9620 tree void_ftype_v4si_long_pvoid
9621 = build_function_type_list (void_type_node,
9622 V4SI_type_node, long_integer_type_node,
9623 pvoid_type_node, NULL_TREE);
9624 tree void_ftype_v16qi_long_pvoid
9625 = build_function_type_list (void_type_node,
9626 V16QI_type_node, long_integer_type_node,
9627 pvoid_type_node, NULL_TREE);
9628 tree void_ftype_v8hi_long_pvoid
9629 = build_function_type_list (void_type_node,
9630 V8HI_type_node, long_integer_type_node,
9631 pvoid_type_node, NULL_TREE);
9632 tree int_ftype_int_v8hi_v8hi
9633 = build_function_type_list (integer_type_node,
9634 integer_type_node, V8HI_type_node,
9635 V8HI_type_node, NULL_TREE);
9636 tree int_ftype_int_v16qi_v16qi
9637 = build_function_type_list (integer_type_node,
9638 integer_type_node, V16QI_type_node,
9639 V16QI_type_node, NULL_TREE);
9640 tree int_ftype_int_v4sf_v4sf
9641 = build_function_type_list (integer_type_node,
9642 integer_type_node, V4SF_type_node,
9643 V4SF_type_node, NULL_TREE);
9644 tree v4si_ftype_v4si
9645 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
9646 tree v8hi_ftype_v8hi
9647 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
9648 tree v16qi_ftype_v16qi
9649 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
9650 tree v4sf_ftype_v4sf
9651 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9652 tree void_ftype_pcvoid_int_int
9653 = build_function_type_list (void_type_node,
9654 pcvoid_type_node, integer_type_node,
9655 integer_type_node, NULL_TREE);
9657 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
9658 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
9659 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
9660 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
9661 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
9662 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
9663 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
9664 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
9665 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
9666 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
9667 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
9668 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
9669 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
9670 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
9671 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9672 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9673 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9674 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9675 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9676 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9677 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9678 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9679 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9680 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9681 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9682 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9683 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9684 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9685 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9686 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9687 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9688 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9689 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9690 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9691 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9692 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9693 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9694 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9695 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9696 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9697 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9698 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9699 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9700 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9701 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9702 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9704 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9706 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9707 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9708 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9709 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9710 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9711 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9712 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9713 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9714 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9715 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9717 /* Add the DST variants. */
9719 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9720 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9722 /* Initialize the predicates. */
9723 dp = bdesc_altivec_preds;
9724 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9726 enum machine_mode mode1;
9728 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9729 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9734 mode1 = insn_data[dp->icode].operand[1].mode;
9739 type = int_ftype_int_opaque_opaque;
9742 type = int_ftype_int_v4si_v4si;
9745 type = int_ftype_int_v8hi_v8hi;
9748 type = int_ftype_int_v16qi_v16qi;
9751 type = int_ftype_int_v4sf_v4sf;
9757 def_builtin (dp->mask, dp->name, type, dp->code);
9760 /* Initialize the abs* operators. */
9762 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9764 enum machine_mode mode0;
9767 mode0 = insn_data[d->icode].operand[0].mode;
9772 type = v4si_ftype_v4si;
9775 type = v8hi_ftype_v8hi;
9778 type = v16qi_ftype_v16qi;
9781 type = v4sf_ftype_v4sf;
9787 def_builtin (d->mask, d->name, type, d->code);
9794 /* Initialize target builtin that implements
9795 targetm.vectorize.builtin_mask_for_load. */
9797 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9798 v16qi_ftype_long_pcvoid,
9799 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9800 BUILT_IN_MD, NULL, NULL_TREE);
9801 TREE_READONLY (decl) = 1;
9802 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9803 altivec_builtin_mask_for_load = decl;
9806 /* Access to the vec_init patterns. */
9807 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9808 integer_type_node, integer_type_node,
9809 integer_type_node, NULL_TREE);
9810 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9811 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9813 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9814 short_integer_type_node,
9815 short_integer_type_node,
9816 short_integer_type_node,
9817 short_integer_type_node,
9818 short_integer_type_node,
9819 short_integer_type_node,
9820 short_integer_type_node, NULL_TREE);
9821 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9822 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9824 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9825 char_type_node, char_type_node,
9826 char_type_node, char_type_node,
9827 char_type_node, char_type_node,
9828 char_type_node, char_type_node,
9829 char_type_node, char_type_node,
9830 char_type_node, char_type_node,
9831 char_type_node, char_type_node,
9832 char_type_node, NULL_TREE);
9833 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9834 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9836 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9837 float_type_node, float_type_node,
9838 float_type_node, NULL_TREE);
9839 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9840 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9842 /* Access to the vec_set patterns. */
9843 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9845 integer_type_node, NULL_TREE);
9846 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9847 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9849 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9851 integer_type_node, NULL_TREE);
9852 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9853 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9855 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9857 integer_type_node, NULL_TREE);
9858 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9859 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9861 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9863 integer_type_node, NULL_TREE);
9864 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9865 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9867 /* Access to the vec_extract patterns. */
9868 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9869 integer_type_node, NULL_TREE);
9870 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9871 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9873 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9874 integer_type_node, NULL_TREE);
9875 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9876 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9878 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9879 integer_type_node, NULL_TREE);
9880 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9881 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9883 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9884 integer_type_node, NULL_TREE);
9885 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9886 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9890 rs6000_common_init_builtins (void)
9892 const struct builtin_description *d;
9895 tree v2sf_ftype_v2sf_v2sf_v2sf
9896 = build_function_type_list (V2SF_type_node,
9897 V2SF_type_node, V2SF_type_node,
9898 V2SF_type_node, NULL_TREE);
9900 tree v4sf_ftype_v4sf_v4sf_v16qi
9901 = build_function_type_list (V4SF_type_node,
9902 V4SF_type_node, V4SF_type_node,
9903 V16QI_type_node, NULL_TREE);
9904 tree v4si_ftype_v4si_v4si_v16qi
9905 = build_function_type_list (V4SI_type_node,
9906 V4SI_type_node, V4SI_type_node,
9907 V16QI_type_node, NULL_TREE);
9908 tree v8hi_ftype_v8hi_v8hi_v16qi
9909 = build_function_type_list (V8HI_type_node,
9910 V8HI_type_node, V8HI_type_node,
9911 V16QI_type_node, NULL_TREE);
9912 tree v16qi_ftype_v16qi_v16qi_v16qi
9913 = build_function_type_list (V16QI_type_node,
9914 V16QI_type_node, V16QI_type_node,
9915 V16QI_type_node, NULL_TREE);
9917 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9919 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9920 tree v16qi_ftype_int
9921 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9922 tree v8hi_ftype_v16qi
9923 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9924 tree v4sf_ftype_v4sf
9925 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9927 tree v2si_ftype_v2si_v2si
9928 = build_function_type_list (opaque_V2SI_type_node,
9929 opaque_V2SI_type_node,
9930 opaque_V2SI_type_node, NULL_TREE);
9932 tree v2sf_ftype_v2sf_v2sf_spe
9933 = build_function_type_list (opaque_V2SF_type_node,
9934 opaque_V2SF_type_node,
9935 opaque_V2SF_type_node, NULL_TREE);
9937 tree v2sf_ftype_v2sf_v2sf
9938 = build_function_type_list (V2SF_type_node,
9940 V2SF_type_node, NULL_TREE);
9943 tree v2si_ftype_int_int
9944 = build_function_type_list (opaque_V2SI_type_node,
9945 integer_type_node, integer_type_node,
9948 tree opaque_ftype_opaque
9949 = build_function_type_list (opaque_V4SI_type_node,
9950 opaque_V4SI_type_node, NULL_TREE);
9952 tree v2si_ftype_v2si
9953 = build_function_type_list (opaque_V2SI_type_node,
9954 opaque_V2SI_type_node, NULL_TREE);
9956 tree v2sf_ftype_v2sf_spe
9957 = build_function_type_list (opaque_V2SF_type_node,
9958 opaque_V2SF_type_node, NULL_TREE);
9960 tree v2sf_ftype_v2sf
9961 = build_function_type_list (V2SF_type_node,
9962 V2SF_type_node, NULL_TREE);
9964 tree v2sf_ftype_v2si
9965 = build_function_type_list (opaque_V2SF_type_node,
9966 opaque_V2SI_type_node, NULL_TREE);
9968 tree v2si_ftype_v2sf
9969 = build_function_type_list (opaque_V2SI_type_node,
9970 opaque_V2SF_type_node, NULL_TREE);
9972 tree v2si_ftype_v2si_char
9973 = build_function_type_list (opaque_V2SI_type_node,
9974 opaque_V2SI_type_node,
9975 char_type_node, NULL_TREE);
9977 tree v2si_ftype_int_char
9978 = build_function_type_list (opaque_V2SI_type_node,
9979 integer_type_node, char_type_node, NULL_TREE);
9981 tree v2si_ftype_char
9982 = build_function_type_list (opaque_V2SI_type_node,
9983 char_type_node, NULL_TREE);
9985 tree int_ftype_int_int
9986 = build_function_type_list (integer_type_node,
9987 integer_type_node, integer_type_node,
9990 tree opaque_ftype_opaque_opaque
9991 = build_function_type_list (opaque_V4SI_type_node,
9992 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9993 tree v4si_ftype_v4si_v4si
9994 = build_function_type_list (V4SI_type_node,
9995 V4SI_type_node, V4SI_type_node, NULL_TREE);
9996 tree v4sf_ftype_v4si_int
9997 = build_function_type_list (V4SF_type_node,
9998 V4SI_type_node, integer_type_node, NULL_TREE);
9999 tree v4si_ftype_v4sf_int
10000 = build_function_type_list (V4SI_type_node,
10001 V4SF_type_node, integer_type_node, NULL_TREE);
10002 tree v4si_ftype_v4si_int
10003 = build_function_type_list (V4SI_type_node,
10004 V4SI_type_node, integer_type_node, NULL_TREE);
10005 tree v8hi_ftype_v8hi_int
10006 = build_function_type_list (V8HI_type_node,
10007 V8HI_type_node, integer_type_node, NULL_TREE);
10008 tree v16qi_ftype_v16qi_int
10009 = build_function_type_list (V16QI_type_node,
10010 V16QI_type_node, integer_type_node, NULL_TREE);
10011 tree v16qi_ftype_v16qi_v16qi_int
10012 = build_function_type_list (V16QI_type_node,
10013 V16QI_type_node, V16QI_type_node,
10014 integer_type_node, NULL_TREE);
10015 tree v8hi_ftype_v8hi_v8hi_int
10016 = build_function_type_list (V8HI_type_node,
10017 V8HI_type_node, V8HI_type_node,
10018 integer_type_node, NULL_TREE);
10019 tree v4si_ftype_v4si_v4si_int
10020 = build_function_type_list (V4SI_type_node,
10021 V4SI_type_node, V4SI_type_node,
10022 integer_type_node, NULL_TREE);
10023 tree v4sf_ftype_v4sf_v4sf_int
10024 = build_function_type_list (V4SF_type_node,
10025 V4SF_type_node, V4SF_type_node,
10026 integer_type_node, NULL_TREE);
10027 tree v4sf_ftype_v4sf_v4sf
10028 = build_function_type_list (V4SF_type_node,
10029 V4SF_type_node, V4SF_type_node, NULL_TREE);
10030 tree opaque_ftype_opaque_opaque_opaque
10031 = build_function_type_list (opaque_V4SI_type_node,
10032 opaque_V4SI_type_node, opaque_V4SI_type_node,
10033 opaque_V4SI_type_node, NULL_TREE);
10034 tree v4sf_ftype_v4sf_v4sf_v4si
10035 = build_function_type_list (V4SF_type_node,
10036 V4SF_type_node, V4SF_type_node,
10037 V4SI_type_node, NULL_TREE);
10038 tree v4sf_ftype_v4sf_v4sf_v4sf
10039 = build_function_type_list (V4SF_type_node,
10040 V4SF_type_node, V4SF_type_node,
10041 V4SF_type_node, NULL_TREE);
10042 tree v4si_ftype_v4si_v4si_v4si
10043 = build_function_type_list (V4SI_type_node,
10044 V4SI_type_node, V4SI_type_node,
10045 V4SI_type_node, NULL_TREE);
10046 tree v8hi_ftype_v8hi_v8hi
10047 = build_function_type_list (V8HI_type_node,
10048 V8HI_type_node, V8HI_type_node, NULL_TREE);
10049 tree v8hi_ftype_v8hi_v8hi_v8hi
10050 = build_function_type_list (V8HI_type_node,
10051 V8HI_type_node, V8HI_type_node,
10052 V8HI_type_node, NULL_TREE);
10053 tree v4si_ftype_v8hi_v8hi_v4si
10054 = build_function_type_list (V4SI_type_node,
10055 V8HI_type_node, V8HI_type_node,
10056 V4SI_type_node, NULL_TREE);
10057 tree v4si_ftype_v16qi_v16qi_v4si
10058 = build_function_type_list (V4SI_type_node,
10059 V16QI_type_node, V16QI_type_node,
10060 V4SI_type_node, NULL_TREE);
10061 tree v16qi_ftype_v16qi_v16qi
10062 = build_function_type_list (V16QI_type_node,
10063 V16QI_type_node, V16QI_type_node, NULL_TREE);
10064 tree v4si_ftype_v4sf_v4sf
10065 = build_function_type_list (V4SI_type_node,
10066 V4SF_type_node, V4SF_type_node, NULL_TREE);
10067 tree v8hi_ftype_v16qi_v16qi
10068 = build_function_type_list (V8HI_type_node,
10069 V16QI_type_node, V16QI_type_node, NULL_TREE);
10070 tree v4si_ftype_v8hi_v8hi
10071 = build_function_type_list (V4SI_type_node,
10072 V8HI_type_node, V8HI_type_node, NULL_TREE);
10073 tree v8hi_ftype_v4si_v4si
10074 = build_function_type_list (V8HI_type_node,
10075 V4SI_type_node, V4SI_type_node, NULL_TREE);
10076 tree v16qi_ftype_v8hi_v8hi
10077 = build_function_type_list (V16QI_type_node,
10078 V8HI_type_node, V8HI_type_node, NULL_TREE);
10079 tree v4si_ftype_v16qi_v4si
10080 = build_function_type_list (V4SI_type_node,
10081 V16QI_type_node, V4SI_type_node, NULL_TREE);
10082 tree v4si_ftype_v16qi_v16qi
10083 = build_function_type_list (V4SI_type_node,
10084 V16QI_type_node, V16QI_type_node, NULL_TREE);
10085 tree v4si_ftype_v8hi_v4si
10086 = build_function_type_list (V4SI_type_node,
10087 V8HI_type_node, V4SI_type_node, NULL_TREE);
10088 tree v4si_ftype_v8hi
10089 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
10090 tree int_ftype_v4si_v4si
10091 = build_function_type_list (integer_type_node,
10092 V4SI_type_node, V4SI_type_node, NULL_TREE);
10093 tree int_ftype_v4sf_v4sf
10094 = build_function_type_list (integer_type_node,
10095 V4SF_type_node, V4SF_type_node, NULL_TREE);
10096 tree int_ftype_v16qi_v16qi
10097 = build_function_type_list (integer_type_node,
10098 V16QI_type_node, V16QI_type_node, NULL_TREE);
10099 tree int_ftype_v8hi_v8hi
10100 = build_function_type_list (integer_type_node,
10101 V8HI_type_node, V8HI_type_node, NULL_TREE);
10103 /* Add the simple ternary operators. */
10105 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
10107 enum machine_mode mode0, mode1, mode2, mode3;
10109 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10110 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10121 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10124 mode0 = insn_data[d->icode].operand[0].mode;
10125 mode1 = insn_data[d->icode].operand[1].mode;
10126 mode2 = insn_data[d->icode].operand[2].mode;
10127 mode3 = insn_data[d->icode].operand[3].mode;
10130 /* When all four are of the same mode. */
10131 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
10136 type = opaque_ftype_opaque_opaque_opaque;
10139 type = v4si_ftype_v4si_v4si_v4si;
10142 type = v4sf_ftype_v4sf_v4sf_v4sf;
10145 type = v8hi_ftype_v8hi_v8hi_v8hi;
10148 type = v16qi_ftype_v16qi_v16qi_v16qi;
10151 type = v2sf_ftype_v2sf_v2sf_v2sf;
10154 gcc_unreachable ();
10157 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
10162 type = v4si_ftype_v4si_v4si_v16qi;
10165 type = v4sf_ftype_v4sf_v4sf_v16qi;
10168 type = v8hi_ftype_v8hi_v8hi_v16qi;
10171 type = v16qi_ftype_v16qi_v16qi_v16qi;
10174 gcc_unreachable ();
10177 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
10178 && mode3 == V4SImode)
10179 type = v4si_ftype_v16qi_v16qi_v4si;
10180 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
10181 && mode3 == V4SImode)
10182 type = v4si_ftype_v8hi_v8hi_v4si;
10183 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
10184 && mode3 == V4SImode)
10185 type = v4sf_ftype_v4sf_v4sf_v4si;
10187 /* vchar, vchar, vchar, 4-bit literal. */
10188 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
10189 && mode3 == QImode)
10190 type = v16qi_ftype_v16qi_v16qi_int;
10192 /* vshort, vshort, vshort, 4-bit literal. */
10193 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
10194 && mode3 == QImode)
10195 type = v8hi_ftype_v8hi_v8hi_int;
10197 /* vint, vint, vint, 4-bit literal. */
10198 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
10199 && mode3 == QImode)
10200 type = v4si_ftype_v4si_v4si_int;
10202 /* vfloat, vfloat, vfloat, 4-bit literal. */
10203 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
10204 && mode3 == QImode)
10205 type = v4sf_ftype_v4sf_v4sf_int;
10208 gcc_unreachable ();
10210 def_builtin (d->mask, d->name, type, d->code);
10213 /* Add the simple binary operators. */
10214 d = (struct builtin_description *) bdesc_2arg;
10215 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10217 enum machine_mode mode0, mode1, mode2;
10219 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10220 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10230 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10233 mode0 = insn_data[d->icode].operand[0].mode;
10234 mode1 = insn_data[d->icode].operand[1].mode;
10235 mode2 = insn_data[d->icode].operand[2].mode;
10238 /* When all three operands are of the same mode. */
10239 if (mode0 == mode1 && mode1 == mode2)
10244 type = opaque_ftype_opaque_opaque;
10247 type = v4sf_ftype_v4sf_v4sf;
10250 type = v4si_ftype_v4si_v4si;
10253 type = v16qi_ftype_v16qi_v16qi;
10256 type = v8hi_ftype_v8hi_v8hi;
10259 type = v2si_ftype_v2si_v2si;
10262 if (TARGET_PAIRED_FLOAT)
10263 type = v2sf_ftype_v2sf_v2sf;
10265 type = v2sf_ftype_v2sf_v2sf_spe;
10268 type = int_ftype_int_int;
10271 gcc_unreachable ();
10275 /* A few other combos we really don't want to do manually. */
10277 /* vint, vfloat, vfloat. */
10278 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
10279 type = v4si_ftype_v4sf_v4sf;
10281 /* vshort, vchar, vchar. */
10282 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
10283 type = v8hi_ftype_v16qi_v16qi;
10285 /* vint, vshort, vshort. */
10286 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
10287 type = v4si_ftype_v8hi_v8hi;
10289 /* vshort, vint, vint. */
10290 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
10291 type = v8hi_ftype_v4si_v4si;
10293 /* vchar, vshort, vshort. */
10294 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
10295 type = v16qi_ftype_v8hi_v8hi;
10297 /* vint, vchar, vint. */
10298 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
10299 type = v4si_ftype_v16qi_v4si;
10301 /* vint, vchar, vchar. */
10302 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
10303 type = v4si_ftype_v16qi_v16qi;
10305 /* vint, vshort, vint. */
10306 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
10307 type = v4si_ftype_v8hi_v4si;
10309 /* vint, vint, 5-bit literal. */
10310 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
10311 type = v4si_ftype_v4si_int;
10313 /* vshort, vshort, 5-bit literal. */
10314 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
10315 type = v8hi_ftype_v8hi_int;
10317 /* vchar, vchar, 5-bit literal. */
10318 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
10319 type = v16qi_ftype_v16qi_int;
10321 /* vfloat, vint, 5-bit literal. */
10322 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
10323 type = v4sf_ftype_v4si_int;
10325 /* vint, vfloat, 5-bit literal. */
10326 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
10327 type = v4si_ftype_v4sf_int;
10329 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
10330 type = v2si_ftype_int_int;
10332 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
10333 type = v2si_ftype_v2si_char;
10335 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
10336 type = v2si_ftype_int_char;
10341 gcc_assert (mode0 == SImode);
10345 type = int_ftype_v4si_v4si;
10348 type = int_ftype_v4sf_v4sf;
10351 type = int_ftype_v16qi_v16qi;
10354 type = int_ftype_v8hi_v8hi;
10357 gcc_unreachable ();
10361 def_builtin (d->mask, d->name, type, d->code);
10364 /* Add the simple unary operators. */
10365 d = (struct builtin_description *) bdesc_1arg;
10366 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10368 enum machine_mode mode0, mode1;
10370 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10371 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10380 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10383 mode0 = insn_data[d->icode].operand[0].mode;
10384 mode1 = insn_data[d->icode].operand[1].mode;
10387 if (mode0 == V4SImode && mode1 == QImode)
10388 type = v4si_ftype_int;
10389 else if (mode0 == V8HImode && mode1 == QImode)
10390 type = v8hi_ftype_int;
10391 else if (mode0 == V16QImode && mode1 == QImode)
10392 type = v16qi_ftype_int;
10393 else if (mode0 == VOIDmode && mode1 == VOIDmode)
10394 type = opaque_ftype_opaque;
10395 else if (mode0 == V4SFmode && mode1 == V4SFmode)
10396 type = v4sf_ftype_v4sf;
10397 else if (mode0 == V8HImode && mode1 == V16QImode)
10398 type = v8hi_ftype_v16qi;
10399 else if (mode0 == V4SImode && mode1 == V8HImode)
10400 type = v4si_ftype_v8hi;
10401 else if (mode0 == V2SImode && mode1 == V2SImode)
10402 type = v2si_ftype_v2si;
10403 else if (mode0 == V2SFmode && mode1 == V2SFmode)
10405 if (TARGET_PAIRED_FLOAT)
10406 type = v2sf_ftype_v2sf;
10408 type = v2sf_ftype_v2sf_spe;
10410 else if (mode0 == V2SFmode && mode1 == V2SImode)
10411 type = v2sf_ftype_v2si;
10412 else if (mode0 == V2SImode && mode1 == V2SFmode)
10413 type = v2si_ftype_v2sf;
10414 else if (mode0 == V2SImode && mode1 == QImode)
10415 type = v2si_ftype_char;
10417 gcc_unreachable ();
10419 def_builtin (d->mask, d->name, type, d->code);
10424 rs6000_init_libfuncs (void)
10426 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
10427 && !TARGET_POWER2 && !TARGET_POWERPC)
10429 /* AIX library routines for float->int conversion. */
10430 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
10431 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
10432 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
10433 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
10436 if (!TARGET_IEEEQUAD)
10437 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10438 if (!TARGET_XL_COMPAT)
10440 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
10441 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
10442 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
10443 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
10445 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
10447 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
10448 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
10449 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
10450 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
10451 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
10452 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
10453 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
10455 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
10456 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
10457 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
10458 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
10459 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
10460 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
10461 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
10462 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
10465 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
10466 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
10470 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
10471 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
10472 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
10473 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
10477 /* 32-bit SVR4 quad floating point routines. */
10479 set_optab_libfunc (add_optab, TFmode, "_q_add");
10480 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
10481 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
10482 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
10483 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
10484 if (TARGET_PPC_GPOPT || TARGET_POWER2)
10485 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
10487 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
10488 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
10489 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
10490 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
10491 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
10492 set_optab_libfunc (le_optab, TFmode, "_q_fle");
10494 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
10495 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
10496 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
10497 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
10498 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
10499 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
10500 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
10501 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
10506 /* Expand a block clear operation, and return 1 if successful. Return 0
10507 if we should let the compiler generate normal code.
10509 operands[0] is the destination
10510 operands[1] is the length
10511 operands[3] is the alignment */
10514 expand_block_clear (rtx operands[])
10516 rtx orig_dest = operands[0];
10517 rtx bytes_rtx = operands[1];
10518 rtx align_rtx = operands[3];
10519 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
10520 HOST_WIDE_INT align;
10521 HOST_WIDE_INT bytes;
10526 /* If this is not a fixed size move, just call memcpy */
10530 /* This must be a fixed size alignment */
10531 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10532 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10534 /* Anything to clear? */
10535 bytes = INTVAL (bytes_rtx);
10539 /* Use the builtin memset after a point, to avoid huge code bloat.
10540 When optimize_size, avoid any significant code bloat; calling
10541 memset is about 4 instructions, so allow for one instruction to
10542 load zero and three to do clearing. */
10543 if (TARGET_ALTIVEC && align >= 128)
10545 else if (TARGET_POWERPC64 && align >= 32)
10547 else if (TARGET_SPE && align >= 64)
10552 if (optimize_size && bytes > 3 * clear_step)
10554 if (! optimize_size && bytes > 8 * clear_step)
10557 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
10559 enum machine_mode mode = BLKmode;
10562 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
10567 else if (bytes >= 8 && TARGET_SPE && align >= 64)
10572 else if (bytes >= 8 && TARGET_POWERPC64
10573 /* 64-bit loads and stores require word-aligned
10575 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10580 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10581 { /* move 4 bytes */
10585 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10586 { /* move 2 bytes */
10590 else /* move 1 byte at a time */
10596 dest = adjust_address (orig_dest, mode, offset);
10598 emit_move_insn (dest, CONST0_RTX (mode));
10605 /* Expand a block move operation, and return 1 if successful. Return 0
10606 if we should let the compiler generate normal code.
10608 operands[0] is the destination
10609 operands[1] is the source
10610 operands[2] is the length
10611 operands[3] is the alignment */
10613 #define MAX_MOVE_REG 4
10616 expand_block_move (rtx operands[])
10618 rtx orig_dest = operands[0];
10619 rtx orig_src = operands[1];
10620 rtx bytes_rtx = operands[2];
10621 rtx align_rtx = operands[3];
10622 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
10627 rtx stores[MAX_MOVE_REG];
10630 /* If this is not a fixed size move, just call memcpy */
10634 /* This must be a fixed size alignment */
10635 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10636 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10638 /* Anything to move? */
10639 bytes = INTVAL (bytes_rtx);
10643 /* store_one_arg depends on expand_block_move to handle at least the size of
10644 reg_parm_stack_space. */
10645 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
10648 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
10651 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
10652 rtx (*mov) (rtx, rtx);
10654 enum machine_mode mode = BLKmode;
10657 /* Altivec first, since it will be faster than a string move
10658 when it applies, and usually not significantly larger. */
10659 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
10663 gen_func.mov = gen_movv4si;
10665 else if (TARGET_SPE && bytes >= 8 && align >= 64)
10669 gen_func.mov = gen_movv2si;
10671 else if (TARGET_STRING
10672 && bytes > 24 /* move up to 32 bytes at a time */
10678 && ! fixed_regs[10]
10679 && ! fixed_regs[11]
10680 && ! fixed_regs[12])
10682 move_bytes = (bytes > 32) ? 32 : bytes;
10683 gen_func.movmemsi = gen_movmemsi_8reg;
10685 else if (TARGET_STRING
10686 && bytes > 16 /* move up to 24 bytes at a time */
10692 && ! fixed_regs[10])
10694 move_bytes = (bytes > 24) ? 24 : bytes;
10695 gen_func.movmemsi = gen_movmemsi_6reg;
10697 else if (TARGET_STRING
10698 && bytes > 8 /* move up to 16 bytes at a time */
10702 && ! fixed_regs[8])
10704 move_bytes = (bytes > 16) ? 16 : bytes;
10705 gen_func.movmemsi = gen_movmemsi_4reg;
10707 else if (bytes >= 8 && TARGET_POWERPC64
10708 /* 64-bit loads and stores require word-aligned
10710 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10714 gen_func.mov = gen_movdi;
10716 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10717 { /* move up to 8 bytes at a time */
10718 move_bytes = (bytes > 8) ? 8 : bytes;
10719 gen_func.movmemsi = gen_movmemsi_2reg;
10721 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10722 { /* move 4 bytes */
10725 gen_func.mov = gen_movsi;
10727 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10728 { /* move 2 bytes */
10731 gen_func.mov = gen_movhi;
10733 else if (TARGET_STRING && bytes > 1)
10734 { /* move up to 4 bytes at a time */
10735 move_bytes = (bytes > 4) ? 4 : bytes;
10736 gen_func.movmemsi = gen_movmemsi_1reg;
10738 else /* move 1 byte at a time */
10742 gen_func.mov = gen_movqi;
10745 src = adjust_address (orig_src, mode, offset);
10746 dest = adjust_address (orig_dest, mode, offset);
10748 if (mode != BLKmode)
10750 rtx tmp_reg = gen_reg_rtx (mode);
10752 emit_insn ((*gen_func.mov) (tmp_reg, src));
10753 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10756 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10759 for (i = 0; i < num_reg; i++)
10760 emit_insn (stores[i]);
10764 if (mode == BLKmode)
10766 /* Move the address into scratch registers. The movmemsi
10767 patterns require zero offset. */
10768 if (!REG_P (XEXP (src, 0)))
10770 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10771 src = replace_equiv_address (src, src_reg);
10773 set_mem_size (src, GEN_INT (move_bytes));
10775 if (!REG_P (XEXP (dest, 0)))
10777 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10778 dest = replace_equiv_address (dest, dest_reg);
10780 set_mem_size (dest, GEN_INT (move_bytes));
10782 emit_insn ((*gen_func.movmemsi) (dest, src,
10783 GEN_INT (move_bytes & 31),
10792 /* Return a string to perform a load_multiple operation.
10793 operands[0] is the vector.
10794 operands[1] is the source address.
10795 operands[2] is the first destination register. */
10798 rs6000_output_load_multiple (rtx operands[3])
10800 /* We have to handle the case where the pseudo used to contain the address
10801 is assigned to one of the output registers. */
10803 int words = XVECLEN (operands[0], 0);
10806 if (XVECLEN (operands[0], 0) == 1)
10807 return "{l|lwz} %2,0(%1)";
10809 for (i = 0; i < words; i++)
10810 if (refers_to_regno_p (REGNO (operands[2]) + i,
10811 REGNO (operands[2]) + i + 1, operands[1], 0))
10815 xop[0] = GEN_INT (4 * (words-1));
10816 xop[1] = operands[1];
10817 xop[2] = operands[2];
10818 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10823 xop[0] = GEN_INT (4 * (words-1));
10824 xop[1] = operands[1];
10825 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10826 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10831 for (j = 0; j < words; j++)
10834 xop[0] = GEN_INT (j * 4);
10835 xop[1] = operands[1];
10836 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10837 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10839 xop[0] = GEN_INT (i * 4);
10840 xop[1] = operands[1];
10841 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10846 return "{lsi|lswi} %2,%1,%N0";
10850 /* A validation routine: say whether CODE, a condition code, and MODE
10851 match. The other alternatives either don't make sense or should
10852 never be generated. */
10855 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10857 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10858 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10859 && GET_MODE_CLASS (mode) == MODE_CC);
10861 /* These don't make sense. */
10862 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10863 || mode != CCUNSmode);
10865 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10866 || mode == CCUNSmode);
10868 gcc_assert (mode == CCFPmode
10869 || (code != ORDERED && code != UNORDERED
10870 && code != UNEQ && code != LTGT
10871 && code != UNGT && code != UNLT
10872 && code != UNGE && code != UNLE));
10874 /* These should never be generated except for
10875 flag_finite_math_only. */
10876 gcc_assert (mode != CCFPmode
10877 || flag_finite_math_only
10878 || (code != LE && code != GE
10879 && code != UNEQ && code != LTGT
10880 && code != UNGT && code != UNLT));
10882 /* These are invalid; the information is not there. */
10883 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10887 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10888 mask required to convert the result of a rotate insn into a shift
10889 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10892 includes_lshift_p (rtx shiftop, rtx andop)
10894 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10896 shift_mask <<= INTVAL (shiftop);
10898 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10901 /* Similar, but for right shift. */
10904 includes_rshift_p (rtx shiftop, rtx andop)
10906 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10908 shift_mask >>= INTVAL (shiftop);
10910 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10913 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10914 to perform a left shift. It must have exactly SHIFTOP least
10915 significant 0's, then one or more 1's, then zero or more 0's. */
10918 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10920 if (GET_CODE (andop) == CONST_INT)
10922 HOST_WIDE_INT c, lsb, shift_mask;
10924 c = INTVAL (andop);
10925 if (c == 0 || c == ~0)
10929 shift_mask <<= INTVAL (shiftop);
10931 /* Find the least significant one bit. */
10934 /* It must coincide with the LSB of the shift mask. */
10935 if (-lsb != shift_mask)
10938 /* Invert to look for the next transition (if any). */
10941 /* Remove the low group of ones (originally low group of zeros). */
10944 /* Again find the lsb, and check we have all 1's above. */
10948 else if (GET_CODE (andop) == CONST_DOUBLE
10949 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10951 HOST_WIDE_INT low, high, lsb;
10952 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10954 low = CONST_DOUBLE_LOW (andop);
10955 if (HOST_BITS_PER_WIDE_INT < 64)
10956 high = CONST_DOUBLE_HIGH (andop);
10958 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10959 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10962 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10964 shift_mask_high = ~0;
10965 if (INTVAL (shiftop) > 32)
10966 shift_mask_high <<= INTVAL (shiftop) - 32;
10968 lsb = high & -high;
10970 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10976 lsb = high & -high;
10977 return high == -lsb;
10980 shift_mask_low = ~0;
10981 shift_mask_low <<= INTVAL (shiftop);
10985 if (-lsb != shift_mask_low)
10988 if (HOST_BITS_PER_WIDE_INT < 64)
10993 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10995 lsb = high & -high;
10996 return high == -lsb;
11000 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
11006 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
11007 to perform a left shift. It must have SHIFTOP or more least
11008 significant 0's, with the remainder of the word 1's. */
11011 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
11013 if (GET_CODE (andop) == CONST_INT)
11015 HOST_WIDE_INT c, lsb, shift_mask;
11018 shift_mask <<= INTVAL (shiftop);
11019 c = INTVAL (andop);
11021 /* Find the least significant one bit. */
11024 /* It must be covered by the shift mask.
11025 This test also rejects c == 0. */
11026 if ((lsb & shift_mask) == 0)
11029 /* Check we have all 1's above the transition, and reject all 1's. */
11030 return c == -lsb && lsb != 1;
11032 else if (GET_CODE (andop) == CONST_DOUBLE
11033 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
11035 HOST_WIDE_INT low, lsb, shift_mask_low;
11037 low = CONST_DOUBLE_LOW (andop);
11039 if (HOST_BITS_PER_WIDE_INT < 64)
11041 HOST_WIDE_INT high, shift_mask_high;
11043 high = CONST_DOUBLE_HIGH (andop);
11047 shift_mask_high = ~0;
11048 if (INTVAL (shiftop) > 32)
11049 shift_mask_high <<= INTVAL (shiftop) - 32;
11051 lsb = high & -high;
11053 if ((lsb & shift_mask_high) == 0)
11056 return high == -lsb;
11062 shift_mask_low = ~0;
11063 shift_mask_low <<= INTVAL (shiftop);
11067 if ((lsb & shift_mask_low) == 0)
11070 return low == -lsb && lsb != 1;
11076 /* Return 1 if operands will generate a valid arguments to rlwimi
11077 instruction for insert with right shift in 64-bit mode. The mask may
11078 not start on the first bit or stop on the last bit because wrap-around
11079 effects of instruction do not correspond to semantics of RTL insn. */
11082 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
11084 if (INTVAL (startop) > 32
11085 && INTVAL (startop) < 64
11086 && INTVAL (sizeop) > 1
11087 && INTVAL (sizeop) + INTVAL (startop) < 64
11088 && INTVAL (shiftop) > 0
11089 && INTVAL (sizeop) + INTVAL (shiftop) < 32
11090 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
11096 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11097 for lfq and stfq insns iff the registers are hard registers. */
11100 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
11102 /* We might have been passed a SUBREG. */
11103 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
11106 /* We might have been passed non floating point registers. */
11107 if (!FP_REGNO_P (REGNO (reg1))
11108 || !FP_REGNO_P (REGNO (reg2)))
11111 return (REGNO (reg1) == REGNO (reg2) - 1);
11114 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11115 addr1 and addr2 must be in consecutive memory locations
11116 (addr2 == addr1 + 8). */
11119 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
11122 unsigned int reg1, reg2;
11123 int offset1, offset2;
11125 /* The mems cannot be volatile. */
11126 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
11129 addr1 = XEXP (mem1, 0);
11130 addr2 = XEXP (mem2, 0);
11132 /* Extract an offset (if used) from the first addr. */
11133 if (GET_CODE (addr1) == PLUS)
11135 /* If not a REG, return zero. */
11136 if (GET_CODE (XEXP (addr1, 0)) != REG)
11140 reg1 = REGNO (XEXP (addr1, 0));
11141 /* The offset must be constant! */
11142 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
11144 offset1 = INTVAL (XEXP (addr1, 1));
11147 else if (GET_CODE (addr1) != REG)
11151 reg1 = REGNO (addr1);
11152 /* This was a simple (mem (reg)) expression. Offset is 0. */
11156 /* And now for the second addr. */
11157 if (GET_CODE (addr2) == PLUS)
11159 /* If not a REG, return zero. */
11160 if (GET_CODE (XEXP (addr2, 0)) != REG)
11164 reg2 = REGNO (XEXP (addr2, 0));
11165 /* The offset must be constant. */
11166 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
11168 offset2 = INTVAL (XEXP (addr2, 1));
11171 else if (GET_CODE (addr2) != REG)
11175 reg2 = REGNO (addr2);
11176 /* This was a simple (mem (reg)) expression. Offset is 0. */
11180 /* Both of these must have the same base register. */
11184 /* The offset for the second addr must be 8 more than the first addr. */
11185 if (offset2 != offset1 + 8)
11188 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11195 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
11197 static bool eliminated = false;
11198 if (mode != SDmode)
11199 return assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
11202 rtx mem = cfun->machine->sdmode_stack_slot;
11203 gcc_assert (mem != NULL_RTX);
11207 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
11208 cfun->machine->sdmode_stack_slot = mem;
11216 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
11218 /* Don't walk into types. */
11219 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
11221 *walk_subtrees = 0;
11225 switch (TREE_CODE (*tp))
11232 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
11243 /* Allocate a 64-bit stack slot to be used for copying SDmode
11244 values through if this function has any SDmode references. */
11247 rs6000_alloc_sdmode_stack_slot (void)
11251 block_stmt_iterator bsi;
11253 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
11256 for (bsi = bsi_start (bb); !bsi_end_p (bsi); bsi_next (&bsi))
11258 tree ret = walk_tree_without_duplicates (bsi_stmt_ptr (bsi),
11259 rs6000_check_sdmode, NULL);
11262 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11263 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11269 /* Check for any SDmode parameters of the function. */
11270 for (t = DECL_ARGUMENTS (cfun->decl); t; t = TREE_CHAIN (t))
11272 if (TREE_TYPE (t) == error_mark_node)
11275 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
11276 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
11278 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11279 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11287 rs6000_instantiate_decls (void)
11289 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
11290 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
11293 /* Return the register class of a scratch register needed to copy IN into
11294 or out of a register in CLASS in MODE. If it can be done directly,
11295 NO_REGS is returned. */
11298 rs6000_secondary_reload_class (enum reg_class class,
11299 enum machine_mode mode ATTRIBUTE_UNUSED,
11304 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
11306 && MACHOPIC_INDIRECT
11310 /* We cannot copy a symbolic operand directly into anything
11311 other than BASE_REGS for TARGET_ELF. So indicate that a
11312 register from BASE_REGS is needed as an intermediate
11315 On Darwin, pic addresses require a load from memory, which
11316 needs a base register. */
11317 if (class != BASE_REGS
11318 && (GET_CODE (in) == SYMBOL_REF
11319 || GET_CODE (in) == HIGH
11320 || GET_CODE (in) == LABEL_REF
11321 || GET_CODE (in) == CONST))
11325 if (GET_CODE (in) == REG)
11327 regno = REGNO (in);
11328 if (regno >= FIRST_PSEUDO_REGISTER)
11330 regno = true_regnum (in);
11331 if (regno >= FIRST_PSEUDO_REGISTER)
11335 else if (GET_CODE (in) == SUBREG)
11337 regno = true_regnum (in);
11338 if (regno >= FIRST_PSEUDO_REGISTER)
11344 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11346 if (class == GENERAL_REGS || class == BASE_REGS
11347 || (regno >= 0 && INT_REGNO_P (regno)))
11350 /* Constants, memory, and FP registers can go into FP registers. */
11351 if ((regno == -1 || FP_REGNO_P (regno))
11352 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
11353 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
11355 /* Memory, and AltiVec registers can go into AltiVec registers. */
11356 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
11357 && class == ALTIVEC_REGS)
11360 /* We can copy among the CR registers. */
11361 if ((class == CR_REGS || class == CR0_REGS)
11362 && regno >= 0 && CR_REGNO_P (regno))
11365 /* Otherwise, we need GENERAL_REGS. */
11366 return GENERAL_REGS;
11369 /* Given a comparison operation, return the bit number in CCR to test. We
11370 know this is a valid comparison.
11372 SCC_P is 1 if this is for an scc. That means that %D will have been
11373 used instead of %C, so the bits will be in different places.
11375 Return -1 if OP isn't a valid comparison for some reason. */
11378 ccr_bit (rtx op, int scc_p)
11380 enum rtx_code code = GET_CODE (op);
11381 enum machine_mode cc_mode;
11386 if (!COMPARISON_P (op))
11389 reg = XEXP (op, 0);
11391 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
11393 cc_mode = GET_MODE (reg);
11394 cc_regnum = REGNO (reg);
11395 base_bit = 4 * (cc_regnum - CR0_REGNO);
11397 validate_condition_mode (code, cc_mode);
11399 /* When generating a sCOND operation, only positive conditions are
11402 || code == EQ || code == GT || code == LT || code == UNORDERED
11403 || code == GTU || code == LTU);
11408 return scc_p ? base_bit + 3 : base_bit + 2;
11410 return base_bit + 2;
11411 case GT: case GTU: case UNLE:
11412 return base_bit + 1;
11413 case LT: case LTU: case UNGE:
11415 case ORDERED: case UNORDERED:
11416 return base_bit + 3;
11419 /* If scc, we will have done a cror to put the bit in the
11420 unordered position. So test that bit. For integer, this is ! LT
11421 unless this is an scc insn. */
11422 return scc_p ? base_bit + 3 : base_bit;
11425 return scc_p ? base_bit + 3 : base_bit + 1;
11428 gcc_unreachable ();
11432 /* Return the GOT register. */
11435 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
11437 /* The second flow pass currently (June 1999) can't update
11438 regs_ever_live without disturbing other parts of the compiler, so
11439 update it here to make the prolog/epilogue code happy. */
11440 if (!can_create_pseudo_p ()
11441 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
11442 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
11444 current_function_uses_pic_offset_table = 1;
11446 return pic_offset_table_rtx;
11449 /* Function to init struct machine_function.
11450 This will be called, via a pointer variable,
11451 from push_function_context. */
11453 static struct machine_function *
11454 rs6000_init_machine_status (void)
11456 return ggc_alloc_cleared (sizeof (machine_function));
11459 /* These macros test for integers and extract the low-order bits. */
11461 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11462 && GET_MODE (X) == VOIDmode)
11464 #define INT_LOWPART(X) \
11465 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11468 extract_MB (rtx op)
11471 unsigned long val = INT_LOWPART (op);
11473 /* If the high bit is zero, the value is the first 1 bit we find
11475 if ((val & 0x80000000) == 0)
11477 gcc_assert (val & 0xffffffff);
11480 while (((val <<= 1) & 0x80000000) == 0)
11485 /* If the high bit is set and the low bit is not, or the mask is all
11486 1's, the value is zero. */
11487 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
11490 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11493 while (((val >>= 1) & 1) != 0)
11500 extract_ME (rtx op)
11503 unsigned long val = INT_LOWPART (op);
11505 /* If the low bit is zero, the value is the first 1 bit we find from
11507 if ((val & 1) == 0)
11509 gcc_assert (val & 0xffffffff);
11512 while (((val >>= 1) & 1) == 0)
11518 /* If the low bit is set and the high bit is not, or the mask is all
11519 1's, the value is 31. */
11520 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
11523 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11526 while (((val <<= 1) & 0x80000000) != 0)
11532 /* Locate some local-dynamic symbol still in use by this function
11533 so that we can print its name in some tls_ld pattern. */
11535 static const char *
11536 rs6000_get_some_local_dynamic_name (void)
11540 if (cfun->machine->some_ld_name)
11541 return cfun->machine->some_ld_name;
11543 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11545 && for_each_rtx (&PATTERN (insn),
11546 rs6000_get_some_local_dynamic_name_1, 0))
11547 return cfun->machine->some_ld_name;
11549 gcc_unreachable ();
11552 /* Helper function for rs6000_get_some_local_dynamic_name. */
11555 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11559 if (GET_CODE (x) == SYMBOL_REF)
11561 const char *str = XSTR (x, 0);
11562 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11564 cfun->machine->some_ld_name = str;
11572 /* Write out a function code label. */
11575 rs6000_output_function_entry (FILE *file, const char *fname)
11577 if (fname[0] != '.')
11579 switch (DEFAULT_ABI)
11582 gcc_unreachable ();
11588 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
11597 RS6000_OUTPUT_BASENAME (file, fname);
11599 assemble_name (file, fname);
11602 /* Print an operand. Recognize special options, documented below. */
11605 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11606 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11608 #define SMALL_DATA_RELOC "sda21"
11609 #define SMALL_DATA_REG 0
11613 print_operand (FILE *file, rtx x, int code)
11617 unsigned HOST_WIDE_INT uval;
11622 /* Write out an instruction after the call which may be replaced
11623 with glue code by the loader. This depends on the AIX version. */
11624 asm_fprintf (file, RS6000_CALL_GLUE);
11627 /* %a is output_address. */
11630 /* If X is a constant integer whose low-order 5 bits are zero,
11631 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11632 in the AIX assembler where "sri" with a zero shift count
11633 writes a trash instruction. */
11634 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
11641 /* If constant, low-order 16 bits of constant, unsigned.
11642 Otherwise, write normally. */
11644 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
11646 print_operand (file, x, 0);
11650 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11651 for 64-bit mask direction. */
11652 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
11655 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11659 /* X is a CR register. Print the number of the GT bit of the CR. */
11660 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11661 output_operand_lossage ("invalid %%E value");
11663 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
11667 /* Like 'J' but get to the GT bit only. */
11668 gcc_assert (GET_CODE (x) == REG);
11670 /* Bit 1 is GT bit. */
11671 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
11673 /* Add one for shift count in rlinm for scc. */
11674 fprintf (file, "%d", i + 1);
11678 /* X is a CR register. Print the number of the EQ bit of the CR */
11679 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11680 output_operand_lossage ("invalid %%E value");
11682 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
11686 /* X is a CR register. Print the shift count needed to move it
11687 to the high-order four bits. */
11688 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11689 output_operand_lossage ("invalid %%f value");
11691 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
11695 /* Similar, but print the count for the rotate in the opposite
11697 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11698 output_operand_lossage ("invalid %%F value");
11700 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
11704 /* X is a constant integer. If it is negative, print "m",
11705 otherwise print "z". This is to make an aze or ame insn. */
11706 if (GET_CODE (x) != CONST_INT)
11707 output_operand_lossage ("invalid %%G value");
11708 else if (INTVAL (x) >= 0)
11715 /* If constant, output low-order five bits. Otherwise, write
11718 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
11720 print_operand (file, x, 0);
11724 /* If constant, output low-order six bits. Otherwise, write
11727 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
11729 print_operand (file, x, 0);
11733 /* Print `i' if this is a constant, else nothing. */
11739 /* Write the bit number in CCR for jump. */
11740 i = ccr_bit (x, 0);
11742 output_operand_lossage ("invalid %%j code");
11744 fprintf (file, "%d", i);
11748 /* Similar, but add one for shift count in rlinm for scc and pass
11749 scc flag to `ccr_bit'. */
11750 i = ccr_bit (x, 1);
11752 output_operand_lossage ("invalid %%J code");
11754 /* If we want bit 31, write a shift count of zero, not 32. */
11755 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11759 /* X must be a constant. Write the 1's complement of the
11762 output_operand_lossage ("invalid %%k value");
11764 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
11768 /* X must be a symbolic constant on ELF. Write an
11769 expression suitable for an 'addi' that adds in the low 16
11770 bits of the MEM. */
11771 if (GET_CODE (x) != CONST)
11773 print_operand_address (file, x);
11774 fputs ("@l", file);
11778 if (GET_CODE (XEXP (x, 0)) != PLUS
11779 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
11780 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
11781 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
11782 output_operand_lossage ("invalid %%K value");
11783 print_operand_address (file, XEXP (XEXP (x, 0), 0));
11784 fputs ("@l", file);
11785 /* For GNU as, there must be a non-alphanumeric character
11786 between 'l' and the number. The '-' is added by
11787 print_operand() already. */
11788 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
11790 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
11794 /* %l is output_asm_label. */
11797 /* Write second word of DImode or DFmode reference. Works on register
11798 or non-indexed memory only. */
11799 if (GET_CODE (x) == REG)
11800 fputs (reg_names[REGNO (x) + 1], file);
11801 else if (GET_CODE (x) == MEM)
11803 /* Handle possible auto-increment. Since it is pre-increment and
11804 we have already done it, we can just use an offset of word. */
11805 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11806 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11807 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11809 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11810 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11813 output_address (XEXP (adjust_address_nv (x, SImode,
11817 if (small_data_operand (x, GET_MODE (x)))
11818 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11819 reg_names[SMALL_DATA_REG]);
11824 /* MB value for a mask operand. */
11825 if (! mask_operand (x, SImode))
11826 output_operand_lossage ("invalid %%m value");
11828 fprintf (file, "%d", extract_MB (x));
11832 /* ME value for a mask operand. */
11833 if (! mask_operand (x, SImode))
11834 output_operand_lossage ("invalid %%M value");
11836 fprintf (file, "%d", extract_ME (x));
11839 /* %n outputs the negative of its operand. */
11842 /* Write the number of elements in the vector times 4. */
11843 if (GET_CODE (x) != PARALLEL)
11844 output_operand_lossage ("invalid %%N value");
11846 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11850 /* Similar, but subtract 1 first. */
11851 if (GET_CODE (x) != PARALLEL)
11852 output_operand_lossage ("invalid %%O value");
11854 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11858 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11860 || INT_LOWPART (x) < 0
11861 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11862 output_operand_lossage ("invalid %%p value");
11864 fprintf (file, "%d", i);
11868 /* The operand must be an indirect memory reference. The result
11869 is the register name. */
11870 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11871 || REGNO (XEXP (x, 0)) >= 32)
11872 output_operand_lossage ("invalid %%P value");
11874 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11878 /* This outputs the logical code corresponding to a boolean
11879 expression. The expression may have one or both operands
11880 negated (if one, only the first one). For condition register
11881 logical operations, it will also treat the negated
11882 CR codes as NOTs, but not handle NOTs of them. */
11884 const char *const *t = 0;
11886 enum rtx_code code = GET_CODE (x);
11887 static const char * const tbl[3][3] = {
11888 { "and", "andc", "nor" },
11889 { "or", "orc", "nand" },
11890 { "xor", "eqv", "xor" } };
11894 else if (code == IOR)
11896 else if (code == XOR)
11899 output_operand_lossage ("invalid %%q value");
11901 if (GET_CODE (XEXP (x, 0)) != NOT)
11905 if (GET_CODE (XEXP (x, 1)) == NOT)
11923 /* X is a CR register. Print the mask for `mtcrf'. */
11924 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11925 output_operand_lossage ("invalid %%R value");
11927 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11931 /* Low 5 bits of 32 - value */
11933 output_operand_lossage ("invalid %%s value");
11935 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11939 /* PowerPC64 mask position. All 0's is excluded.
11940 CONST_INT 32-bit mask is considered sign-extended so any
11941 transition must occur within the CONST_INT, not on the boundary. */
11942 if (! mask64_operand (x, DImode))
11943 output_operand_lossage ("invalid %%S value");
11945 uval = INT_LOWPART (x);
11947 if (uval & 1) /* Clear Left */
11949 #if HOST_BITS_PER_WIDE_INT > 64
11950 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11954 else /* Clear Right */
11957 #if HOST_BITS_PER_WIDE_INT > 64
11958 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11964 gcc_assert (i >= 0);
11965 fprintf (file, "%d", i);
11969 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11970 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11972 /* Bit 3 is OV bit. */
11973 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11975 /* If we want bit 31, write a shift count of zero, not 32. */
11976 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11980 /* Print the symbolic name of a branch target register. */
11981 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11982 && REGNO (x) != CTR_REGNO))
11983 output_operand_lossage ("invalid %%T value");
11984 else if (REGNO (x) == LR_REGNO)
11985 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11987 fputs ("ctr", file);
11991 /* High-order 16 bits of constant for use in unsigned operand. */
11993 output_operand_lossage ("invalid %%u value");
11995 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11996 (INT_LOWPART (x) >> 16) & 0xffff);
12000 /* High-order 16 bits of constant for use in signed operand. */
12002 output_operand_lossage ("invalid %%v value");
12004 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
12005 (INT_LOWPART (x) >> 16) & 0xffff);
12009 /* Print `u' if this has an auto-increment or auto-decrement. */
12010 if (GET_CODE (x) == MEM
12011 && (GET_CODE (XEXP (x, 0)) == PRE_INC
12012 || GET_CODE (XEXP (x, 0)) == PRE_DEC
12013 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
12018 /* Print the trap code for this operand. */
12019 switch (GET_CODE (x))
12022 fputs ("eq", file); /* 4 */
12025 fputs ("ne", file); /* 24 */
12028 fputs ("lt", file); /* 16 */
12031 fputs ("le", file); /* 20 */
12034 fputs ("gt", file); /* 8 */
12037 fputs ("ge", file); /* 12 */
12040 fputs ("llt", file); /* 2 */
12043 fputs ("lle", file); /* 6 */
12046 fputs ("lgt", file); /* 1 */
12049 fputs ("lge", file); /* 5 */
12052 gcc_unreachable ();
12057 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12060 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
12061 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
12063 print_operand (file, x, 0);
12067 /* MB value for a PowerPC64 rldic operand. */
12068 val = (GET_CODE (x) == CONST_INT
12069 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
12074 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
12075 if ((val <<= 1) < 0)
12078 #if HOST_BITS_PER_WIDE_INT == 32
12079 if (GET_CODE (x) == CONST_INT && i >= 0)
12080 i += 32; /* zero-extend high-part was all 0's */
12081 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
12083 val = CONST_DOUBLE_LOW (x);
12089 for ( ; i < 64; i++)
12090 if ((val <<= 1) < 0)
12095 fprintf (file, "%d", i + 1);
12099 if (GET_CODE (x) == MEM
12100 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
12101 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
12102 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
12107 /* Like 'L', for third word of TImode */
12108 if (GET_CODE (x) == REG)
12109 fputs (reg_names[REGNO (x) + 2], file);
12110 else if (GET_CODE (x) == MEM)
12112 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12113 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12114 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12115 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12116 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12118 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
12119 if (small_data_operand (x, GET_MODE (x)))
12120 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12121 reg_names[SMALL_DATA_REG]);
12126 /* X is a SYMBOL_REF. Write out the name preceded by a
12127 period and without any trailing data in brackets. Used for function
12128 names. If we are configured for System V (or the embedded ABI) on
12129 the PowerPC, do not emit the period, since those systems do not use
12130 TOCs and the like. */
12131 gcc_assert (GET_CODE (x) == SYMBOL_REF);
12133 /* Mark the decl as referenced so that cgraph will output the
12135 if (SYMBOL_REF_DECL (x))
12136 mark_decl_referenced (SYMBOL_REF_DECL (x));
12138 /* For macho, check to see if we need a stub. */
12141 const char *name = XSTR (x, 0);
12143 if (MACHOPIC_INDIRECT
12144 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
12145 name = machopic_indirection_name (x, /*stub_p=*/true);
12147 assemble_name (file, name);
12149 else if (!DOT_SYMBOLS)
12150 assemble_name (file, XSTR (x, 0));
12152 rs6000_output_function_entry (file, XSTR (x, 0));
12156 /* Like 'L', for last word of TImode. */
12157 if (GET_CODE (x) == REG)
12158 fputs (reg_names[REGNO (x) + 3], file);
12159 else if (GET_CODE (x) == MEM)
12161 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12162 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12163 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12164 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12165 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12167 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
12168 if (small_data_operand (x, GET_MODE (x)))
12169 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12170 reg_names[SMALL_DATA_REG]);
12174 /* Print AltiVec or SPE memory operand. */
12179 gcc_assert (GET_CODE (x) == MEM);
12183 /* Ugly hack because %y is overloaded. */
12184 if ((TARGET_SPE || TARGET_E500_DOUBLE)
12185 && (GET_MODE_SIZE (GET_MODE (x)) == 8
12186 || GET_MODE (x) == TFmode
12187 || GET_MODE (x) == TImode))
12189 /* Handle [reg]. */
12190 if (GET_CODE (tmp) == REG)
12192 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
12195 /* Handle [reg+UIMM]. */
12196 else if (GET_CODE (tmp) == PLUS &&
12197 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
12201 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
12203 x = INTVAL (XEXP (tmp, 1));
12204 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
12208 /* Fall through. Must be [reg+reg]. */
12211 && GET_CODE (tmp) == AND
12212 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
12213 && INTVAL (XEXP (tmp, 1)) == -16)
12214 tmp = XEXP (tmp, 0);
12215 if (GET_CODE (tmp) == REG)
12216 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
12219 gcc_assert (GET_CODE (tmp) == PLUS
12220 && REG_P (XEXP (tmp, 0))
12221 && REG_P (XEXP (tmp, 1)));
12223 if (REGNO (XEXP (tmp, 0)) == 0)
12224 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
12225 reg_names[ REGNO (XEXP (tmp, 0)) ]);
12227 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
12228 reg_names[ REGNO (XEXP (tmp, 1)) ]);
12234 if (GET_CODE (x) == REG)
12235 fprintf (file, "%s", reg_names[REGNO (x)]);
12236 else if (GET_CODE (x) == MEM)
12238 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12239 know the width from the mode. */
12240 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
12241 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
12242 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12243 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
12244 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
12245 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12246 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12247 output_address (XEXP (XEXP (x, 0), 1));
12249 output_address (XEXP (x, 0));
12252 output_addr_const (file, x);
12256 assemble_name (file, rs6000_get_some_local_dynamic_name ());
12260 output_operand_lossage ("invalid %%xn code");
12264 /* Print the address of an operand. */
12267 print_operand_address (FILE *file, rtx x)
12269 if (GET_CODE (x) == REG)
12270 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
12271 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
12272 || GET_CODE (x) == LABEL_REF)
12274 output_addr_const (file, x);
12275 if (small_data_operand (x, GET_MODE (x)))
12276 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12277 reg_names[SMALL_DATA_REG]);
12279 gcc_assert (!TARGET_TOC);
12281 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
12283 gcc_assert (REG_P (XEXP (x, 0)));
12284 if (REGNO (XEXP (x, 0)) == 0)
12285 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
12286 reg_names[ REGNO (XEXP (x, 0)) ]);
12288 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
12289 reg_names[ REGNO (XEXP (x, 1)) ]);
12291 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
12292 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
12293 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
12295 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12296 && CONSTANT_P (XEXP (x, 1)))
12298 output_addr_const (file, XEXP (x, 1));
12299 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12303 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12304 && CONSTANT_P (XEXP (x, 1)))
12306 fprintf (file, "lo16(");
12307 output_addr_const (file, XEXP (x, 1));
12308 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12311 else if (legitimate_constant_pool_address_p (x))
12313 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
12315 rtx contains_minus = XEXP (x, 1);
12319 /* Find the (minus (sym) (toc)) buried in X, and temporarily
12320 turn it into (sym) for output_addr_const. */
12321 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
12322 contains_minus = XEXP (contains_minus, 0);
12324 minus = XEXP (contains_minus, 0);
12325 symref = XEXP (minus, 0);
12326 XEXP (contains_minus, 0) = symref;
12331 name = XSTR (symref, 0);
12332 newname = alloca (strlen (name) + sizeof ("@toc"));
12333 strcpy (newname, name);
12334 strcat (newname, "@toc");
12335 XSTR (symref, 0) = newname;
12337 output_addr_const (file, XEXP (x, 1));
12339 XSTR (symref, 0) = name;
12340 XEXP (contains_minus, 0) = minus;
12343 output_addr_const (file, XEXP (x, 1));
12345 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
12348 gcc_unreachable ();
12351 /* Target hook for assembling integer objects. The PowerPC version has
12352 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12353 is defined. It also needs to handle DI-mode objects on 64-bit
12357 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
12359 #ifdef RELOCATABLE_NEEDS_FIXUP
12360 /* Special handling for SI values. */
12361 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
12363 static int recurse = 0;
12365 /* For -mrelocatable, we mark all addresses that need to be fixed up
12366 in the .fixup section. */
12367 if (TARGET_RELOCATABLE
12368 && in_section != toc_section
12369 && in_section != text_section
12370 && !unlikely_text_section_p (in_section)
12372 && GET_CODE (x) != CONST_INT
12373 && GET_CODE (x) != CONST_DOUBLE
12379 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
12381 ASM_OUTPUT_LABEL (asm_out_file, buf);
12382 fprintf (asm_out_file, "\t.long\t(");
12383 output_addr_const (asm_out_file, x);
12384 fprintf (asm_out_file, ")@fixup\n");
12385 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
12386 ASM_OUTPUT_ALIGN (asm_out_file, 2);
12387 fprintf (asm_out_file, "\t.long\t");
12388 assemble_name (asm_out_file, buf);
12389 fprintf (asm_out_file, "\n\t.previous\n");
12393 /* Remove initial .'s to turn a -mcall-aixdesc function
12394 address into the address of the descriptor, not the function
12396 else if (GET_CODE (x) == SYMBOL_REF
12397 && XSTR (x, 0)[0] == '.'
12398 && DEFAULT_ABI == ABI_AIX)
12400 const char *name = XSTR (x, 0);
12401 while (*name == '.')
12404 fprintf (asm_out_file, "\t.long\t%s\n", name);
12408 #endif /* RELOCATABLE_NEEDS_FIXUP */
12409 return default_assemble_integer (x, size, aligned_p);
12412 #ifdef HAVE_GAS_HIDDEN
12413 /* Emit an assembler directive to set symbol visibility for DECL to
12414 VISIBILITY_TYPE. */
12417 rs6000_assemble_visibility (tree decl, int vis)
12419 /* Functions need to have their entry point symbol visibility set as
12420 well as their descriptor symbol visibility. */
12421 if (DEFAULT_ABI == ABI_AIX
12423 && TREE_CODE (decl) == FUNCTION_DECL)
12425 static const char * const visibility_types[] = {
12426 NULL, "internal", "hidden", "protected"
12429 const char *name, *type;
12431 name = ((* targetm.strip_name_encoding)
12432 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
12433 type = visibility_types[vis];
12435 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
12436 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
12439 default_assemble_visibility (decl, vis);
12444 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
12446 /* Reversal of FP compares takes care -- an ordered compare
12447 becomes an unordered compare and vice versa. */
12448 if (mode == CCFPmode
12449 && (!flag_finite_math_only
12450 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
12451 || code == UNEQ || code == LTGT))
12452 return reverse_condition_maybe_unordered (code);
12454 return reverse_condition (code);
12457 /* Generate a compare for CODE. Return a brand-new rtx that
12458 represents the result of the compare. */
12461 rs6000_generate_compare (enum rtx_code code)
12463 enum machine_mode comp_mode;
12464 rtx compare_result;
12466 if (rs6000_compare_fp_p)
12467 comp_mode = CCFPmode;
12468 else if (code == GTU || code == LTU
12469 || code == GEU || code == LEU)
12470 comp_mode = CCUNSmode;
12471 else if ((code == EQ || code == NE)
12472 && GET_CODE (rs6000_compare_op0) == SUBREG
12473 && GET_CODE (rs6000_compare_op1) == SUBREG
12474 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
12475 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
12476 /* These are unsigned values, perhaps there will be a later
12477 ordering compare that can be shared with this one.
12478 Unfortunately we cannot detect the signedness of the operands
12479 for non-subregs. */
12480 comp_mode = CCUNSmode;
12482 comp_mode = CCmode;
12484 /* First, the compare. */
12485 compare_result = gen_reg_rtx (comp_mode);
12487 /* E500 FP compare instructions on the GPRs. Yuck! */
12488 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
12489 && rs6000_compare_fp_p)
12491 rtx cmp, or_result, compare_result2;
12492 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
12494 if (op_mode == VOIDmode)
12495 op_mode = GET_MODE (rs6000_compare_op1);
12497 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12498 This explains the following mess. */
12502 case EQ: case UNEQ: case NE: case LTGT:
12506 cmp = flag_unsafe_math_optimizations
12507 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
12508 rs6000_compare_op1)
12509 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
12510 rs6000_compare_op1);
12514 cmp = flag_unsafe_math_optimizations
12515 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
12516 rs6000_compare_op1)
12517 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
12518 rs6000_compare_op1);
12522 cmp = flag_unsafe_math_optimizations
12523 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
12524 rs6000_compare_op1)
12525 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
12526 rs6000_compare_op1);
12530 gcc_unreachable ();
12534 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
12538 cmp = flag_unsafe_math_optimizations
12539 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
12540 rs6000_compare_op1)
12541 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
12542 rs6000_compare_op1);
12546 cmp = flag_unsafe_math_optimizations
12547 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
12548 rs6000_compare_op1)
12549 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
12550 rs6000_compare_op1);
12554 cmp = flag_unsafe_math_optimizations
12555 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
12556 rs6000_compare_op1)
12557 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
12558 rs6000_compare_op1);
12562 gcc_unreachable ();
12566 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
12570 cmp = flag_unsafe_math_optimizations
12571 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
12572 rs6000_compare_op1)
12573 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
12574 rs6000_compare_op1);
12578 cmp = flag_unsafe_math_optimizations
12579 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
12580 rs6000_compare_op1)
12581 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
12582 rs6000_compare_op1);
12586 cmp = flag_unsafe_math_optimizations
12587 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
12588 rs6000_compare_op1)
12589 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
12590 rs6000_compare_op1);
12594 gcc_unreachable ();
12598 gcc_unreachable ();
12601 /* Synthesize LE and GE from LT/GT || EQ. */
12602 if (code == LE || code == GE || code == LEU || code == GEU)
12608 case LE: code = LT; break;
12609 case GE: code = GT; break;
12610 case LEU: code = LT; break;
12611 case GEU: code = GT; break;
12612 default: gcc_unreachable ();
12615 compare_result2 = gen_reg_rtx (CCFPmode);
12621 cmp = flag_unsafe_math_optimizations
12622 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
12623 rs6000_compare_op1)
12624 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
12625 rs6000_compare_op1);
12629 cmp = flag_unsafe_math_optimizations
12630 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
12631 rs6000_compare_op1)
12632 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
12633 rs6000_compare_op1);
12637 cmp = flag_unsafe_math_optimizations
12638 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
12639 rs6000_compare_op1)
12640 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
12641 rs6000_compare_op1);
12645 gcc_unreachable ();
12649 /* OR them together. */
12650 or_result = gen_reg_rtx (CCFPmode);
12651 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
12653 compare_result = or_result;
12658 if (code == NE || code == LTGT)
12668 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12669 CLOBBERs to match cmptf_internal2 pattern. */
12670 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
12671 && GET_MODE (rs6000_compare_op0) == TFmode
12672 && !TARGET_IEEEQUAD
12673 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
12674 emit_insn (gen_rtx_PARALLEL (VOIDmode,
12676 gen_rtx_SET (VOIDmode,
12678 gen_rtx_COMPARE (comp_mode,
12679 rs6000_compare_op0,
12680 rs6000_compare_op1)),
12681 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12682 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12683 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12684 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12685 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12686 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12687 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12688 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
12689 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
12690 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
12692 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
12693 comp_mode = CCEQmode;
12694 compare_result = gen_reg_rtx (CCEQmode);
12696 emit_insn (gen_stack_protect_testdi (compare_result,
12697 rs6000_compare_op0, op1));
12699 emit_insn (gen_stack_protect_testsi (compare_result,
12700 rs6000_compare_op0, op1));
12703 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
12704 gen_rtx_COMPARE (comp_mode,
12705 rs6000_compare_op0,
12706 rs6000_compare_op1)));
12709 /* Some kinds of FP comparisons need an OR operation;
12710 under flag_finite_math_only we don't bother. */
12711 if (rs6000_compare_fp_p
12712 && !flag_finite_math_only
12713 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
12714 && (code == LE || code == GE
12715 || code == UNEQ || code == LTGT
12716 || code == UNGT || code == UNLT))
12718 enum rtx_code or1, or2;
12719 rtx or1_rtx, or2_rtx, compare2_rtx;
12720 rtx or_result = gen_reg_rtx (CCEQmode);
12724 case LE: or1 = LT; or2 = EQ; break;
12725 case GE: or1 = GT; or2 = EQ; break;
12726 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
12727 case LTGT: or1 = LT; or2 = GT; break;
12728 case UNGT: or1 = UNORDERED; or2 = GT; break;
12729 case UNLT: or1 = UNORDERED; or2 = LT; break;
12730 default: gcc_unreachable ();
12732 validate_condition_mode (or1, comp_mode);
12733 validate_condition_mode (or2, comp_mode);
12734 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
12735 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
12736 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
12737 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
12739 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
12741 compare_result = or_result;
12745 validate_condition_mode (code, GET_MODE (compare_result));
12747 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
12751 /* Emit the RTL for an sCOND pattern. */
12754 rs6000_emit_sCOND (enum rtx_code code, rtx result)
12757 enum machine_mode op_mode;
12758 enum rtx_code cond_code;
12760 condition_rtx = rs6000_generate_compare (code);
12761 cond_code = GET_CODE (condition_rtx);
12763 if (rs6000_compare_fp_p
12764 && !TARGET_FPRS && TARGET_HARD_FLOAT)
12768 PUT_MODE (condition_rtx, SImode);
12769 t = XEXP (condition_rtx, 0);
12771 gcc_assert (cond_code == NE || cond_code == EQ);
12773 if (cond_code == NE)
12774 emit_insn (gen_e500_flip_gt_bit (t, t));
12776 emit_insn (gen_move_from_CR_gt_bit (result, t));
12780 if (cond_code == NE
12781 || cond_code == GE || cond_code == LE
12782 || cond_code == GEU || cond_code == LEU
12783 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
12785 rtx not_result = gen_reg_rtx (CCEQmode);
12786 rtx not_op, rev_cond_rtx;
12787 enum machine_mode cc_mode;
12789 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
12791 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
12792 SImode, XEXP (condition_rtx, 0), const0_rtx);
12793 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
12794 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
12795 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
12798 op_mode = GET_MODE (rs6000_compare_op0);
12799 if (op_mode == VOIDmode)
12800 op_mode = GET_MODE (rs6000_compare_op1);
12802 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
12804 PUT_MODE (condition_rtx, DImode);
12805 convert_move (result, condition_rtx, 0);
12809 PUT_MODE (condition_rtx, SImode);
12810 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12814 /* Emit a branch of kind CODE to location LOC. */
12817 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12819 rtx condition_rtx, loc_ref;
12821 condition_rtx = rs6000_generate_compare (code);
12822 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12823 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12824 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12825 loc_ref, pc_rtx)));
12828 /* Return the string to output a conditional branch to LABEL, which is
12829 the operand number of the label, or -1 if the branch is really a
12830 conditional return.
12832 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12833 condition code register and its mode specifies what kind of
12834 comparison we made.
12836 REVERSED is nonzero if we should reverse the sense of the comparison.
12838 INSN is the insn. */
12841 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12843 static char string[64];
12844 enum rtx_code code = GET_CODE (op);
12845 rtx cc_reg = XEXP (op, 0);
12846 enum machine_mode mode = GET_MODE (cc_reg);
12847 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12848 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12849 int really_reversed = reversed ^ need_longbranch;
12855 validate_condition_mode (code, mode);
12857 /* Work out which way this really branches. We could use
12858 reverse_condition_maybe_unordered here always but this
12859 makes the resulting assembler clearer. */
12860 if (really_reversed)
12862 /* Reversal of FP compares takes care -- an ordered compare
12863 becomes an unordered compare and vice versa. */
12864 if (mode == CCFPmode)
12865 code = reverse_condition_maybe_unordered (code);
12867 code = reverse_condition (code);
12870 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12872 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12877 /* Opposite of GT. */
12886 gcc_unreachable ();
12892 /* Not all of these are actually distinct opcodes, but
12893 we distinguish them for clarity of the resulting assembler. */
12894 case NE: case LTGT:
12895 ccode = "ne"; break;
12896 case EQ: case UNEQ:
12897 ccode = "eq"; break;
12899 ccode = "ge"; break;
12900 case GT: case GTU: case UNGT:
12901 ccode = "gt"; break;
12903 ccode = "le"; break;
12904 case LT: case LTU: case UNLT:
12905 ccode = "lt"; break;
12906 case UNORDERED: ccode = "un"; break;
12907 case ORDERED: ccode = "nu"; break;
12908 case UNGE: ccode = "nl"; break;
12909 case UNLE: ccode = "ng"; break;
12911 gcc_unreachable ();
12914 /* Maybe we have a guess as to how likely the branch is.
12915 The old mnemonics don't have a way to specify this information. */
12917 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12918 if (note != NULL_RTX)
12920 /* PROB is the difference from 50%. */
12921 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12923 /* Only hint for highly probable/improbable branches on newer
12924 cpus as static prediction overrides processor dynamic
12925 prediction. For older cpus we may as well always hint, but
12926 assume not taken for branches that are very close to 50% as a
12927 mispredicted taken branch is more expensive than a
12928 mispredicted not-taken branch. */
12929 if (rs6000_always_hint
12930 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12931 && br_prob_note_reliable_p (note)))
12933 if (abs (prob) > REG_BR_PROB_BASE / 20
12934 && ((prob > 0) ^ need_longbranch))
12942 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12944 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12946 /* We need to escape any '%' characters in the reg_names string.
12947 Assume they'd only be the first character.... */
12948 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12950 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12954 /* If the branch distance was too far, we may have to use an
12955 unconditional branch to go the distance. */
12956 if (need_longbranch)
12957 s += sprintf (s, ",$+8\n\tb %s", label);
12959 s += sprintf (s, ",%s", label);
12965 /* Return the string to flip the GT bit on a CR. */
12967 output_e500_flip_gt_bit (rtx dst, rtx src)
12969 static char string[64];
12972 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12973 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12976 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12977 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12979 sprintf (string, "crnot %d,%d", a, b);
12983 /* Return insn index for the vector compare instruction for given CODE,
12984 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12988 get_vec_cmp_insn (enum rtx_code code,
12989 enum machine_mode dest_mode,
12990 enum machine_mode op_mode)
12992 if (!TARGET_ALTIVEC)
12993 return INSN_NOT_AVAILABLE;
12998 if (dest_mode == V16QImode && op_mode == V16QImode)
12999 return UNSPEC_VCMPEQUB;
13000 if (dest_mode == V8HImode && op_mode == V8HImode)
13001 return UNSPEC_VCMPEQUH;
13002 if (dest_mode == V4SImode && op_mode == V4SImode)
13003 return UNSPEC_VCMPEQUW;
13004 if (dest_mode == V4SImode && op_mode == V4SFmode)
13005 return UNSPEC_VCMPEQFP;
13008 if (dest_mode == V4SImode && op_mode == V4SFmode)
13009 return UNSPEC_VCMPGEFP;
13011 if (dest_mode == V16QImode && op_mode == V16QImode)
13012 return UNSPEC_VCMPGTSB;
13013 if (dest_mode == V8HImode && op_mode == V8HImode)
13014 return UNSPEC_VCMPGTSH;
13015 if (dest_mode == V4SImode && op_mode == V4SImode)
13016 return UNSPEC_VCMPGTSW;
13017 if (dest_mode == V4SImode && op_mode == V4SFmode)
13018 return UNSPEC_VCMPGTFP;
13021 if (dest_mode == V16QImode && op_mode == V16QImode)
13022 return UNSPEC_VCMPGTUB;
13023 if (dest_mode == V8HImode && op_mode == V8HImode)
13024 return UNSPEC_VCMPGTUH;
13025 if (dest_mode == V4SImode && op_mode == V4SImode)
13026 return UNSPEC_VCMPGTUW;
13031 return INSN_NOT_AVAILABLE;
13034 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
13035 DMODE is expected destination mode. This is a recursive function. */
13038 rs6000_emit_vector_compare (enum rtx_code rcode,
13040 enum machine_mode dmode)
13044 enum machine_mode dest_mode;
13045 enum machine_mode op_mode = GET_MODE (op1);
13047 gcc_assert (TARGET_ALTIVEC);
13048 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
13050 /* Floating point vector compare instructions uses destination V4SImode.
13051 Move destination to appropriate mode later. */
13052 if (dmode == V4SFmode)
13053 dest_mode = V4SImode;
13057 mask = gen_reg_rtx (dest_mode);
13058 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13060 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
13062 bool swap_operands = false;
13063 bool try_again = false;
13068 swap_operands = true;
13073 swap_operands = true;
13081 /* Invert condition and try again.
13082 e.g., A != B becomes ~(A==B). */
13084 enum rtx_code rev_code;
13085 enum insn_code nor_code;
13088 rev_code = reverse_condition_maybe_unordered (rcode);
13089 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
13092 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
13093 gcc_assert (nor_code != CODE_FOR_nothing);
13094 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
13096 if (dmode != dest_mode)
13098 rtx temp = gen_reg_rtx (dest_mode);
13099 convert_move (temp, mask, 0);
13109 /* Try GT/GTU/LT/LTU OR EQ */
13112 enum insn_code ior_code;
13113 enum rtx_code new_code;
13134 gcc_unreachable ();
13137 c_rtx = rs6000_emit_vector_compare (new_code,
13138 op0, op1, dest_mode);
13139 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
13142 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
13143 gcc_assert (ior_code != CODE_FOR_nothing);
13144 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
13145 if (dmode != dest_mode)
13147 rtx temp = gen_reg_rtx (dest_mode);
13148 convert_move (temp, mask, 0);
13155 gcc_unreachable ();
13160 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13161 /* You only get two chances. */
13162 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
13174 emit_insn (gen_rtx_SET (VOIDmode, mask,
13175 gen_rtx_UNSPEC (dest_mode,
13176 gen_rtvec (2, op0, op1),
13178 if (dmode != dest_mode)
13180 rtx temp = gen_reg_rtx (dest_mode);
13181 convert_move (temp, mask, 0);
13187 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13188 valid insn doesn exist for given mode. */
13191 get_vsel_insn (enum machine_mode mode)
13196 return UNSPEC_VSEL4SI;
13199 return UNSPEC_VSEL4SF;
13202 return UNSPEC_VSEL8HI;
13205 return UNSPEC_VSEL16QI;
13208 return INSN_NOT_AVAILABLE;
13211 return INSN_NOT_AVAILABLE;
13214 /* Emit vector select insn where DEST is destination using
13215 operands OP1, OP2 and MASK. */
13218 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
13221 enum machine_mode dest_mode = GET_MODE (dest);
13222 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
13224 temp = gen_reg_rtx (dest_mode);
13226 /* For each vector element, select op1 when mask is 1 otherwise
13228 t = gen_rtx_SET (VOIDmode, temp,
13229 gen_rtx_UNSPEC (dest_mode,
13230 gen_rtvec (3, op2, op1, mask),
13233 emit_move_insn (dest, temp);
13237 /* Emit vector conditional expression.
13238 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13239 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13242 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
13243 rtx cond, rtx cc_op0, rtx cc_op1)
13245 enum machine_mode dest_mode = GET_MODE (dest);
13246 enum rtx_code rcode = GET_CODE (cond);
13249 if (!TARGET_ALTIVEC)
13252 /* Get the vector mask for the given relational operations. */
13253 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
13255 rs6000_emit_vector_select (dest, op1, op2, mask);
13260 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13261 operands of the last comparison is nonzero/true, FALSE_COND if it
13262 is zero/false. Return 0 if the hardware has no such operation. */
13265 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13267 enum rtx_code code = GET_CODE (op);
13268 rtx op0 = rs6000_compare_op0;
13269 rtx op1 = rs6000_compare_op1;
13270 REAL_VALUE_TYPE c1;
13271 enum machine_mode compare_mode = GET_MODE (op0);
13272 enum machine_mode result_mode = GET_MODE (dest);
13274 bool is_against_zero;
13276 /* These modes should always match. */
13277 if (GET_MODE (op1) != compare_mode
13278 /* In the isel case however, we can use a compare immediate, so
13279 op1 may be a small constant. */
13280 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
13282 if (GET_MODE (true_cond) != result_mode)
13284 if (GET_MODE (false_cond) != result_mode)
13287 /* First, work out if the hardware can do this at all, or
13288 if it's too slow.... */
13289 if (! rs6000_compare_fp_p)
13292 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
13295 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
13296 && SCALAR_FLOAT_MODE_P (compare_mode))
13299 is_against_zero = op1 == CONST0_RTX (compare_mode);
13301 /* A floating-point subtract might overflow, underflow, or produce
13302 an inexact result, thus changing the floating-point flags, so it
13303 can't be generated if we care about that. It's safe if one side
13304 of the construct is zero, since then no subtract will be
13306 if (SCALAR_FLOAT_MODE_P (compare_mode)
13307 && flag_trapping_math && ! is_against_zero)
13310 /* Eliminate half of the comparisons by switching operands, this
13311 makes the remaining code simpler. */
13312 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
13313 || code == LTGT || code == LT || code == UNLE)
13315 code = reverse_condition_maybe_unordered (code);
13317 true_cond = false_cond;
13321 /* UNEQ and LTGT take four instructions for a comparison with zero,
13322 it'll probably be faster to use a branch here too. */
13323 if (code == UNEQ && HONOR_NANS (compare_mode))
13326 if (GET_CODE (op1) == CONST_DOUBLE)
13327 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
13329 /* We're going to try to implement comparisons by performing
13330 a subtract, then comparing against zero. Unfortunately,
13331 Inf - Inf is NaN which is not zero, and so if we don't
13332 know that the operand is finite and the comparison
13333 would treat EQ different to UNORDERED, we can't do it. */
13334 if (HONOR_INFINITIES (compare_mode)
13335 && code != GT && code != UNGE
13336 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
13337 /* Constructs of the form (a OP b ? a : b) are safe. */
13338 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
13339 || (! rtx_equal_p (op0, true_cond)
13340 && ! rtx_equal_p (op1, true_cond))))
13343 /* At this point we know we can use fsel. */
13345 /* Reduce the comparison to a comparison against zero. */
13346 if (! is_against_zero)
13348 temp = gen_reg_rtx (compare_mode);
13349 emit_insn (gen_rtx_SET (VOIDmode, temp,
13350 gen_rtx_MINUS (compare_mode, op0, op1)));
13352 op1 = CONST0_RTX (compare_mode);
13355 /* If we don't care about NaNs we can reduce some of the comparisons
13356 down to faster ones. */
13357 if (! HONOR_NANS (compare_mode))
13363 true_cond = false_cond;
13376 /* Now, reduce everything down to a GE. */
13383 temp = gen_reg_rtx (compare_mode);
13384 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13389 temp = gen_reg_rtx (compare_mode);
13390 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
13395 temp = gen_reg_rtx (compare_mode);
13396 emit_insn (gen_rtx_SET (VOIDmode, temp,
13397 gen_rtx_NEG (compare_mode,
13398 gen_rtx_ABS (compare_mode, op0))));
13403 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13404 temp = gen_reg_rtx (result_mode);
13405 emit_insn (gen_rtx_SET (VOIDmode, temp,
13406 gen_rtx_IF_THEN_ELSE (result_mode,
13407 gen_rtx_GE (VOIDmode,
13409 true_cond, false_cond)));
13410 false_cond = true_cond;
13413 temp = gen_reg_rtx (compare_mode);
13414 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13419 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13420 temp = gen_reg_rtx (result_mode);
13421 emit_insn (gen_rtx_SET (VOIDmode, temp,
13422 gen_rtx_IF_THEN_ELSE (result_mode,
13423 gen_rtx_GE (VOIDmode,
13425 true_cond, false_cond)));
13426 true_cond = false_cond;
13429 temp = gen_reg_rtx (compare_mode);
13430 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13435 gcc_unreachable ();
13438 emit_insn (gen_rtx_SET (VOIDmode, dest,
13439 gen_rtx_IF_THEN_ELSE (result_mode,
13440 gen_rtx_GE (VOIDmode,
13442 true_cond, false_cond)));
13446 /* Same as above, but for ints (isel). */
13449 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13451 rtx condition_rtx, cr;
13453 /* All isel implementations thus far are 32-bits. */
13454 if (GET_MODE (rs6000_compare_op0) != SImode)
13457 /* We still have to do the compare, because isel doesn't do a
13458 compare, it just looks at the CRx bits set by a previous compare
13460 condition_rtx = rs6000_generate_compare (GET_CODE (op));
13461 cr = XEXP (condition_rtx, 0);
13463 if (GET_MODE (cr) == CCmode)
13464 emit_insn (gen_isel_signed (dest, condition_rtx,
13465 true_cond, false_cond, cr));
13467 emit_insn (gen_isel_unsigned (dest, condition_rtx,
13468 true_cond, false_cond, cr));
13474 output_isel (rtx *operands)
13476 enum rtx_code code;
13478 code = GET_CODE (operands[1]);
13479 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
13481 PUT_CODE (operands[1], reverse_condition (code));
13482 return "isel %0,%3,%2,%j1";
13485 return "isel %0,%2,%3,%j1";
13489 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
13491 enum machine_mode mode = GET_MODE (op0);
13495 if (code == SMAX || code == SMIN)
13500 if (code == SMAX || code == UMAX)
13501 target = emit_conditional_move (dest, c, op0, op1, mode,
13502 op0, op1, mode, 0);
13504 target = emit_conditional_move (dest, c, op0, op1, mode,
13505 op1, op0, mode, 0);
13506 gcc_assert (target);
13507 if (target != dest)
13508 emit_move_insn (dest, target);
13511 /* Emit instructions to perform a load-reserved/store-conditional operation.
13512 The operation performed is an atomic
13513 (set M (CODE:MODE M OP))
13514 If not NULL, BEFORE is atomically set to M before the operation, and
13515 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13516 If SYNC_P then a memory barrier is emitted before the operation.
13517 Either OP or M may be wrapped in a NOT operation. */
13520 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
13521 rtx m, rtx op, rtx before_param, rtx after_param,
13524 enum machine_mode used_mode;
13525 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
13528 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13529 rtx shift = NULL_RTX;
13532 emit_insn (gen_memory_barrier ());
13534 if (GET_CODE (m) == NOT)
13535 used_m = XEXP (m, 0);
13539 /* If this is smaller than SImode, we'll have to use SImode with
13541 if (mode == QImode || mode == HImode)
13545 if (MEM_ALIGN (used_m) >= 32)
13548 if (BYTES_BIG_ENDIAN)
13549 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
13551 shift = GEN_INT (ishift);
13552 used_m = change_address (used_m, SImode, 0);
13556 rtx addrSI, aligned_addr;
13557 int shift_mask = mode == QImode ? 0x18 : 0x10;
13559 addrSI = gen_lowpart_common (SImode,
13560 force_reg (Pmode, XEXP (used_m, 0)));
13561 addrSI = force_reg (SImode, addrSI);
13562 shift = gen_reg_rtx (SImode);
13564 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13565 GEN_INT (shift_mask)));
13566 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13568 aligned_addr = expand_binop (Pmode, and_optab,
13570 GEN_INT (-4), NULL_RTX,
13571 1, OPTAB_LIB_WIDEN);
13572 used_m = change_address (used_m, SImode, aligned_addr);
13573 set_mem_align (used_m, 32);
13575 /* It's safe to keep the old alias set of USED_M, because
13576 the operation is atomic and only affects the original
13578 if (GET_CODE (m) == NOT)
13579 m = gen_rtx_NOT (SImode, used_m);
13583 if (GET_CODE (op) == NOT)
13585 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
13586 oldop = gen_rtx_NOT (SImode, oldop);
13589 oldop = lowpart_subreg (SImode, op, mode);
13595 newop = expand_binop (SImode, and_optab,
13596 oldop, GEN_INT (imask), NULL_RTX,
13597 1, OPTAB_LIB_WIDEN);
13598 emit_insn (gen_ashlsi3 (newop, newop, shift));
13602 newop = expand_binop (SImode, ior_optab,
13603 oldop, GEN_INT (~imask), NULL_RTX,
13604 1, OPTAB_LIB_WIDEN);
13605 emit_insn (gen_rotlsi3 (newop, newop, shift));
13613 newop = expand_binop (SImode, and_optab,
13614 oldop, GEN_INT (imask), NULL_RTX,
13615 1, OPTAB_LIB_WIDEN);
13616 emit_insn (gen_ashlsi3 (newop, newop, shift));
13618 mask = gen_reg_rtx (SImode);
13619 emit_move_insn (mask, GEN_INT (imask));
13620 emit_insn (gen_ashlsi3 (mask, mask, shift));
13623 newop = gen_rtx_PLUS (SImode, m, newop);
13625 newop = gen_rtx_MINUS (SImode, m, newop);
13626 newop = gen_rtx_AND (SImode, newop, mask);
13627 newop = gen_rtx_IOR (SImode, newop,
13628 gen_rtx_AND (SImode,
13629 gen_rtx_NOT (SImode, mask),
13635 gcc_unreachable ();
13638 if (GET_CODE (m) == NOT)
13642 mask = gen_reg_rtx (SImode);
13643 emit_move_insn (mask, GEN_INT (imask));
13644 emit_insn (gen_ashlsi3 (mask, mask, shift));
13646 xorm = gen_rtx_XOR (SImode, used_m, mask);
13647 /* Depending on the value of 'op', the XOR or the operation might
13648 be able to be simplified away. */
13649 newop = simplify_gen_binary (code, SImode, xorm, newop);
13652 used_mode = SImode;
13653 before = gen_reg_rtx (used_mode);
13654 after = gen_reg_rtx (used_mode);
13659 before = before_param;
13660 after = after_param;
13662 if (before == NULL_RTX)
13663 before = gen_reg_rtx (used_mode);
13664 if (after == NULL_RTX)
13665 after = gen_reg_rtx (used_mode);
13668 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
13669 && used_mode != mode)
13670 the_op = op; /* Computed above. */
13671 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
13672 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
13674 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
13676 set_after = gen_rtx_SET (VOIDmode, after, the_op);
13677 set_before = gen_rtx_SET (VOIDmode, before, used_m);
13678 set_atomic = gen_rtx_SET (VOIDmode, used_m,
13679 gen_rtx_UNSPEC (used_mode,
13680 gen_rtvec (1, the_op),
13682 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
13684 if ((code == PLUS || code == MINUS) && used_mode != mode)
13685 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
13686 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
13688 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
13689 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
13691 /* Shift and mask the return values properly. */
13692 if (used_mode != mode && before_param)
13694 emit_insn (gen_lshrsi3 (before, before, shift));
13695 convert_move (before_param, before, 1);
13698 if (used_mode != mode && after_param)
13700 emit_insn (gen_lshrsi3 (after, after, shift));
13701 convert_move (after_param, after, 1);
13704 /* The previous sequence will end with a branch that's dependent on
13705 the conditional store, so placing an isync will ensure that no
13706 other instructions (especially, no load or store instructions)
13707 can start before the atomic operation completes. */
13709 emit_insn (gen_isync ());
13712 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13713 COND is true. Mark the jump as unlikely to be taken. */
13716 emit_unlikely_jump (rtx cond, rtx label)
13718 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
13721 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
13722 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
13723 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
13726 /* A subroutine of the atomic operation splitters. Emit a load-locked
13727 instruction in MODE. */
13730 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
13732 rtx (*fn) (rtx, rtx) = NULL;
13733 if (mode == SImode)
13734 fn = gen_load_locked_si;
13735 else if (mode == DImode)
13736 fn = gen_load_locked_di;
13737 emit_insn (fn (reg, mem));
13740 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13741 instruction in MODE. */
13744 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
13746 rtx (*fn) (rtx, rtx, rtx) = NULL;
13747 if (mode == SImode)
13748 fn = gen_store_conditional_si;
13749 else if (mode == DImode)
13750 fn = gen_store_conditional_di;
13752 /* Emit sync before stwcx. to address PPC405 Erratum. */
13753 if (PPC405_ERRATUM77)
13754 emit_insn (gen_memory_barrier ());
13756 emit_insn (fn (res, mem, val));
13759 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13760 to perform. MEM is the memory on which to operate. VAL is the second
13761 operand of the binary operator. BEFORE and AFTER are optional locations to
13762 return the value of MEM either before of after the operation. SCRATCH is
13763 a scratch register. */
13766 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
13767 rtx before, rtx after, rtx scratch)
13769 enum machine_mode mode = GET_MODE (mem);
13770 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13772 emit_insn (gen_memory_barrier ());
13774 label = gen_label_rtx ();
13775 emit_label (label);
13776 label = gen_rtx_LABEL_REF (VOIDmode, label);
13778 if (before == NULL_RTX)
13780 emit_load_locked (mode, before, mem);
13783 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
13784 else if (code == AND)
13785 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
13787 x = gen_rtx_fmt_ee (code, mode, before, val);
13789 if (after != NULL_RTX)
13790 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
13791 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13793 emit_store_conditional (mode, cond, mem, scratch);
13795 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13796 emit_unlikely_jump (x, label);
13798 emit_insn (gen_isync ());
13801 /* Expand an atomic compare and swap operation. MEM is the memory on which
13802 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13803 value to be stored. SCRATCH is a scratch GPR. */
13806 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
13809 enum machine_mode mode = GET_MODE (mem);
13810 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13812 emit_insn (gen_memory_barrier ());
13814 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13815 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13816 emit_label (XEXP (label1, 0));
13818 emit_load_locked (mode, retval, mem);
13820 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13821 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13823 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13824 emit_unlikely_jump (x, label2);
13826 emit_move_insn (scratch, newval);
13827 emit_store_conditional (mode, cond, mem, scratch);
13829 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13830 emit_unlikely_jump (x, label1);
13832 emit_insn (gen_isync ());
13833 emit_label (XEXP (label2, 0));
13836 /* Expand an atomic test and set operation. MEM is the memory on which
13837 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13840 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13842 enum machine_mode mode = GET_MODE (mem);
13843 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13845 emit_insn (gen_memory_barrier ());
13847 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13848 emit_label (XEXP (label, 0));
13850 emit_load_locked (mode, retval, mem);
13851 emit_move_insn (scratch, val);
13852 emit_store_conditional (mode, cond, mem, scratch);
13854 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13855 emit_unlikely_jump (x, label);
13857 emit_insn (gen_isync ());
13861 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13863 enum machine_mode mode = GET_MODE (mem);
13864 rtx addrSI, align, wdst, shift, mask;
13865 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13866 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13868 /* Shift amount for subword relative to aligned word. */
13869 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13870 shift = gen_reg_rtx (SImode);
13871 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13872 GEN_INT (shift_mask)));
13873 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13875 /* Shift and mask old value into position within word. */
13876 oldval = convert_modes (SImode, mode, oldval, 1);
13877 oldval = expand_binop (SImode, and_optab,
13878 oldval, GEN_INT (imask), NULL_RTX,
13879 1, OPTAB_LIB_WIDEN);
13880 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13882 /* Shift and mask new value into position within word. */
13883 newval = convert_modes (SImode, mode, newval, 1);
13884 newval = expand_binop (SImode, and_optab,
13885 newval, GEN_INT (imask), NULL_RTX,
13886 1, OPTAB_LIB_WIDEN);
13887 emit_insn (gen_ashlsi3 (newval, newval, shift));
13889 /* Mask for insertion. */
13890 mask = gen_reg_rtx (SImode);
13891 emit_move_insn (mask, GEN_INT (imask));
13892 emit_insn (gen_ashlsi3 (mask, mask, shift));
13894 /* Address of aligned word containing subword. */
13895 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13896 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13897 mem = change_address (mem, SImode, align);
13898 set_mem_align (mem, 32);
13899 MEM_VOLATILE_P (mem) = 1;
13901 wdst = gen_reg_rtx (SImode);
13902 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13903 oldval, newval, mem));
13905 emit_move_insn (dst, gen_lowpart (mode, wdst));
13909 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13910 rtx oldval, rtx newval, rtx mem,
13913 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13915 emit_insn (gen_memory_barrier ());
13916 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13917 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13918 emit_label (XEXP (label1, 0));
13920 emit_load_locked (SImode, scratch, mem);
13922 /* Mask subword within loaded value for comparison with oldval.
13923 Use UNSPEC_AND to avoid clobber.*/
13924 emit_insn (gen_rtx_SET (SImode, dest,
13925 gen_rtx_UNSPEC (SImode,
13926 gen_rtvec (2, scratch, mask),
13929 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13930 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13932 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13933 emit_unlikely_jump (x, label2);
13935 /* Clear subword within loaded value for insertion of new value. */
13936 emit_insn (gen_rtx_SET (SImode, scratch,
13937 gen_rtx_AND (SImode,
13938 gen_rtx_NOT (SImode, mask), scratch)));
13939 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13940 emit_store_conditional (SImode, cond, mem, scratch);
13942 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13943 emit_unlikely_jump (x, label1);
13945 emit_insn (gen_isync ());
13946 emit_label (XEXP (label2, 0));
13950 /* Emit instructions to move SRC to DST. Called by splitters for
13951 multi-register moves. It will emit at most one instruction for
13952 each register that is accessed; that is, it won't emit li/lis pairs
13953 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13957 rs6000_split_multireg_move (rtx dst, rtx src)
13959 /* The register number of the first register being moved. */
13961 /* The mode that is to be moved. */
13962 enum machine_mode mode;
13963 /* The mode that the move is being done in, and its size. */
13964 enum machine_mode reg_mode;
13966 /* The number of registers that will be moved. */
13969 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13970 mode = GET_MODE (dst);
13971 nregs = hard_regno_nregs[reg][mode];
13972 if (FP_REGNO_P (reg))
13973 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13974 else if (ALTIVEC_REGNO_P (reg))
13975 reg_mode = V16QImode;
13976 else if (TARGET_E500_DOUBLE && (mode == TFmode || mode == TDmode))
13977 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13979 reg_mode = word_mode;
13980 reg_mode_size = GET_MODE_SIZE (reg_mode);
13982 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13984 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13986 /* Move register range backwards, if we might have destructive
13989 for (i = nregs - 1; i >= 0; i--)
13990 emit_insn (gen_rtx_SET (VOIDmode,
13991 simplify_gen_subreg (reg_mode, dst, mode,
13992 i * reg_mode_size),
13993 simplify_gen_subreg (reg_mode, src, mode,
13994 i * reg_mode_size)));
14000 bool used_update = false;
14002 if (MEM_P (src) && INT_REGNO_P (reg))
14006 if (GET_CODE (XEXP (src, 0)) == PRE_INC
14007 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
14010 breg = XEXP (XEXP (src, 0), 0);
14011 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
14012 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
14013 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
14014 emit_insn (TARGET_32BIT
14015 ? gen_addsi3 (breg, breg, delta_rtx)
14016 : gen_adddi3 (breg, breg, delta_rtx));
14017 src = replace_equiv_address (src, breg);
14019 else if (! rs6000_offsettable_memref_p (src))
14022 basereg = gen_rtx_REG (Pmode, reg);
14023 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
14024 src = replace_equiv_address (src, basereg);
14027 breg = XEXP (src, 0);
14028 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
14029 breg = XEXP (breg, 0);
14031 /* If the base register we are using to address memory is
14032 also a destination reg, then change that register last. */
14034 && REGNO (breg) >= REGNO (dst)
14035 && REGNO (breg) < REGNO (dst) + nregs)
14036 j = REGNO (breg) - REGNO (dst);
14039 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
14043 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
14044 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
14047 breg = XEXP (XEXP (dst, 0), 0);
14048 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
14049 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
14050 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
14052 /* We have to update the breg before doing the store.
14053 Use store with update, if available. */
14057 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
14058 emit_insn (TARGET_32BIT
14059 ? (TARGET_POWERPC64
14060 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
14061 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
14062 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
14063 used_update = true;
14066 emit_insn (TARGET_32BIT
14067 ? gen_addsi3 (breg, breg, delta_rtx)
14068 : gen_adddi3 (breg, breg, delta_rtx));
14069 dst = replace_equiv_address (dst, breg);
14072 gcc_assert (rs6000_offsettable_memref_p (dst));
14075 for (i = 0; i < nregs; i++)
14077 /* Calculate index to next subword. */
14082 /* If compiler already emitted move of first word by
14083 store with update, no need to do anything. */
14084 if (j == 0 && used_update)
14087 emit_insn (gen_rtx_SET (VOIDmode,
14088 simplify_gen_subreg (reg_mode, dst, mode,
14089 j * reg_mode_size),
14090 simplify_gen_subreg (reg_mode, src, mode,
14091 j * reg_mode_size)));
14097 /* This page contains routines that are used to determine what the
14098 function prologue and epilogue code will do and write them out. */
14100 /* Return the first fixed-point register that is required to be
14101 saved. 32 if none. */
14104 first_reg_to_save (void)
14108 /* Find lowest numbered live register. */
14109 for (first_reg = 13; first_reg <= 31; first_reg++)
14110 if (df_regs_ever_live_p (first_reg)
14111 && (! call_used_regs[first_reg]
14112 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14113 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14114 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
14115 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
14120 && current_function_uses_pic_offset_table
14121 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
14122 return RS6000_PIC_OFFSET_TABLE_REGNUM;
14128 /* Similar, for FP regs. */
14131 first_fp_reg_to_save (void)
14135 /* Find lowest numbered live register. */
14136 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
14137 if (df_regs_ever_live_p (first_reg))
14143 /* Similar, for AltiVec regs. */
14146 first_altivec_reg_to_save (void)
14150 /* Stack frame remains as is unless we are in AltiVec ABI. */
14151 if (! TARGET_ALTIVEC_ABI)
14152 return LAST_ALTIVEC_REGNO + 1;
14154 /* On Darwin, the unwind routines are compiled without
14155 TARGET_ALTIVEC, and use save_world to save/restore the
14156 altivec registers when necessary. */
14157 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
14158 && ! TARGET_ALTIVEC)
14159 return FIRST_ALTIVEC_REGNO + 20;
14161 /* Find lowest numbered live register. */
14162 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
14163 if (df_regs_ever_live_p (i))
14169 /* Return a 32-bit mask of the AltiVec registers we need to set in
14170 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14171 the 32-bit word is 0. */
14173 static unsigned int
14174 compute_vrsave_mask (void)
14176 unsigned int i, mask = 0;
14178 /* On Darwin, the unwind routines are compiled without
14179 TARGET_ALTIVEC, and use save_world to save/restore the
14180 call-saved altivec registers when necessary. */
14181 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
14182 && ! TARGET_ALTIVEC)
14185 /* First, find out if we use _any_ altivec registers. */
14186 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14187 if (df_regs_ever_live_p (i))
14188 mask |= ALTIVEC_REG_BIT (i);
14193 /* Next, remove the argument registers from the set. These must
14194 be in the VRSAVE mask set by the caller, so we don't need to add
14195 them in again. More importantly, the mask we compute here is
14196 used to generate CLOBBERs in the set_vrsave insn, and we do not
14197 wish the argument registers to die. */
14198 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
14199 mask &= ~ALTIVEC_REG_BIT (i);
14201 /* Similarly, remove the return value from the set. */
14204 diddle_return_value (is_altivec_return_reg, &yes);
14206 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
14212 /* For a very restricted set of circumstances, we can cut down the
14213 size of prologues/epilogues by calling our own save/restore-the-world
14217 compute_save_world_info (rs6000_stack_t *info_ptr)
14219 info_ptr->world_save_p = 1;
14220 info_ptr->world_save_p
14221 = (WORLD_SAVE_P (info_ptr)
14222 && DEFAULT_ABI == ABI_DARWIN
14223 && ! (current_function_calls_setjmp && flag_exceptions)
14224 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
14225 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
14226 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
14227 && info_ptr->cr_save_p);
14229 /* This will not work in conjunction with sibcalls. Make sure there
14230 are none. (This check is expensive, but seldom executed.) */
14231 if (WORLD_SAVE_P (info_ptr))
14234 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
14235 if ( GET_CODE (insn) == CALL_INSN
14236 && SIBLING_CALL_P (insn))
14238 info_ptr->world_save_p = 0;
14243 if (WORLD_SAVE_P (info_ptr))
14245 /* Even if we're not touching VRsave, make sure there's room on the
14246 stack for it, if it looks like we're calling SAVE_WORLD, which
14247 will attempt to save it. */
14248 info_ptr->vrsave_size = 4;
14250 /* "Save" the VRsave register too if we're saving the world. */
14251 if (info_ptr->vrsave_mask == 0)
14252 info_ptr->vrsave_mask = compute_vrsave_mask ();
14254 /* Because the Darwin register save/restore routines only handle
14255 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14257 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
14258 && (info_ptr->first_altivec_reg_save
14259 >= FIRST_SAVED_ALTIVEC_REGNO));
14266 is_altivec_return_reg (rtx reg, void *xyes)
14268 bool *yes = (bool *) xyes;
14269 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
14274 /* Calculate the stack information for the current function. This is
14275 complicated by having two separate calling sequences, the AIX calling
14276 sequence and the V.4 calling sequence.
14278 AIX (and Darwin/Mac OS X) stack frames look like:
14280 SP----> +---------------------------------------+
14281 | back chain to caller | 0 0
14282 +---------------------------------------+
14283 | saved CR | 4 8 (8-11)
14284 +---------------------------------------+
14286 +---------------------------------------+
14287 | reserved for compilers | 12 24
14288 +---------------------------------------+
14289 | reserved for binders | 16 32
14290 +---------------------------------------+
14291 | saved TOC pointer | 20 40
14292 +---------------------------------------+
14293 | Parameter save area (P) | 24 48
14294 +---------------------------------------+
14295 | Alloca space (A) | 24+P etc.
14296 +---------------------------------------+
14297 | Local variable space (L) | 24+P+A
14298 +---------------------------------------+
14299 | Float/int conversion temporary (X) | 24+P+A+L
14300 +---------------------------------------+
14301 | Save area for AltiVec registers (W) | 24+P+A+L+X
14302 +---------------------------------------+
14303 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14304 +---------------------------------------+
14305 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14306 +---------------------------------------+
14307 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14308 +---------------------------------------+
14309 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14310 +---------------------------------------+
14311 old SP->| back chain to caller's caller |
14312 +---------------------------------------+
14314 The required alignment for AIX configurations is two words (i.e., 8
14318 V.4 stack frames look like:
14320 SP----> +---------------------------------------+
14321 | back chain to caller | 0
14322 +---------------------------------------+
14323 | caller's saved LR | 4
14324 +---------------------------------------+
14325 | Parameter save area (P) | 8
14326 +---------------------------------------+
14327 | Alloca space (A) | 8+P
14328 +---------------------------------------+
14329 | Varargs save area (V) | 8+P+A
14330 +---------------------------------------+
14331 | Local variable space (L) | 8+P+A+V
14332 +---------------------------------------+
14333 | Float/int conversion temporary (X) | 8+P+A+V+L
14334 +---------------------------------------+
14335 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14336 +---------------------------------------+
14337 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14338 +---------------------------------------+
14339 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14340 +---------------------------------------+
14341 | SPE: area for 64-bit GP registers |
14342 +---------------------------------------+
14343 | SPE alignment padding |
14344 +---------------------------------------+
14345 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14346 +---------------------------------------+
14347 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14348 +---------------------------------------+
14349 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14350 +---------------------------------------+
14351 old SP->| back chain to caller's caller |
14352 +---------------------------------------+
14354 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14355 given. (But note below and in sysv4.h that we require only 8 and
14356 may round up the size of our stack frame anyways. The historical
14357 reason is early versions of powerpc-linux which didn't properly
14358 align the stack at program startup. A happy side-effect is that
14359 -mno-eabi libraries can be used with -meabi programs.)
14361 The EABI configuration defaults to the V.4 layout. However,
14362 the stack alignment requirements may differ. If -mno-eabi is not
14363 given, the required stack alignment is 8 bytes; if -mno-eabi is
14364 given, the required alignment is 16 bytes. (But see V.4 comment
14367 #ifndef ABI_STACK_BOUNDARY
14368 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14371 static rs6000_stack_t *
14372 rs6000_stack_info (void)
14374 static rs6000_stack_t info;
14375 rs6000_stack_t *info_ptr = &info;
14376 int reg_size = TARGET_32BIT ? 4 : 8;
14380 HOST_WIDE_INT non_fixed_size;
14382 memset (&info, 0, sizeof (info));
14386 /* Cache value so we don't rescan instruction chain over and over. */
14387 if (cfun->machine->insn_chain_scanned_p == 0)
14388 cfun->machine->insn_chain_scanned_p
14389 = spe_func_has_64bit_regs_p () + 1;
14390 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
14393 /* Select which calling sequence. */
14394 info_ptr->abi = DEFAULT_ABI;
14396 /* Calculate which registers need to be saved & save area size. */
14397 info_ptr->first_gp_reg_save = first_reg_to_save ();
14398 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14399 even if it currently looks like we won't. Reload may need it to
14400 get at a constant; if so, it will have already created a constant
14401 pool entry for it. */
14402 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
14403 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
14404 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
14405 && current_function_uses_const_pool
14406 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
14407 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
14409 first_gp = info_ptr->first_gp_reg_save;
14411 info_ptr->gp_size = reg_size * (32 - first_gp);
14413 /* For the SPE, we have an additional upper 32-bits on each GPR.
14414 Ideally we should save the entire 64-bits only when the upper
14415 half is used in SIMD instructions. Since we only record
14416 registers live (not the size they are used in), this proves
14417 difficult because we'd have to traverse the instruction chain at
14418 the right time, taking reload into account. This is a real pain,
14419 so we opt to save the GPRs in 64-bits always if but one register
14420 gets used in 64-bits. Otherwise, all the registers in the frame
14421 get saved in 32-bits.
14423 So... since when we save all GPRs (except the SP) in 64-bits, the
14424 traditional GP save area will be empty. */
14425 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14426 info_ptr->gp_size = 0;
14428 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
14429 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
14431 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
14432 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
14433 - info_ptr->first_altivec_reg_save);
14435 /* Does this function call anything? */
14436 info_ptr->calls_p = (! current_function_is_leaf
14437 || cfun->machine->ra_needs_full_frame);
14439 /* Determine if we need to save the link register. */
14440 if ((DEFAULT_ABI == ABI_AIX
14441 && current_function_profile
14442 && !TARGET_PROFILE_KERNEL)
14443 #ifdef TARGET_RELOCATABLE
14444 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
14446 || (info_ptr->first_fp_reg_save != 64
14447 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
14448 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
14449 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
14450 || info_ptr->calls_p
14451 || rs6000_ra_ever_killed ())
14453 info_ptr->lr_save_p = 1;
14454 df_set_regs_ever_live (LR_REGNO, true);
14457 /* Determine if we need to save the condition code registers. */
14458 if (df_regs_ever_live_p (CR2_REGNO)
14459 || df_regs_ever_live_p (CR3_REGNO)
14460 || df_regs_ever_live_p (CR4_REGNO))
14462 info_ptr->cr_save_p = 1;
14463 if (DEFAULT_ABI == ABI_V4)
14464 info_ptr->cr_size = reg_size;
14467 /* If the current function calls __builtin_eh_return, then we need
14468 to allocate stack space for registers that will hold data for
14469 the exception handler. */
14470 if (current_function_calls_eh_return)
14473 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
14476 /* SPE saves EH registers in 64-bits. */
14477 ehrd_size = i * (TARGET_SPE_ABI
14478 && info_ptr->spe_64bit_regs_used != 0
14479 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
14484 /* Determine various sizes. */
14485 info_ptr->reg_size = reg_size;
14486 info_ptr->fixed_size = RS6000_SAVE_AREA;
14487 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
14488 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
14489 TARGET_ALTIVEC ? 16 : 8);
14490 if (FRAME_GROWS_DOWNWARD)
14491 info_ptr->vars_size
14492 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
14493 + info_ptr->parm_size,
14494 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
14495 - (info_ptr->fixed_size + info_ptr->vars_size
14496 + info_ptr->parm_size);
14498 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14499 info_ptr->spe_gp_size = 8 * (32 - first_gp);
14501 info_ptr->spe_gp_size = 0;
14503 if (TARGET_ALTIVEC_ABI)
14504 info_ptr->vrsave_mask = compute_vrsave_mask ();
14506 info_ptr->vrsave_mask = 0;
14508 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
14509 info_ptr->vrsave_size = 4;
14511 info_ptr->vrsave_size = 0;
14513 compute_save_world_info (info_ptr);
14515 /* Calculate the offsets. */
14516 switch (DEFAULT_ABI)
14520 gcc_unreachable ();
14524 info_ptr->fp_save_offset = - info_ptr->fp_size;
14525 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14527 if (TARGET_ALTIVEC_ABI)
14529 info_ptr->vrsave_save_offset
14530 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
14532 /* Align stack so vector save area is on a quadword boundary.
14533 The padding goes above the vectors. */
14534 if (info_ptr->altivec_size != 0)
14535 info_ptr->altivec_padding_size
14536 = info_ptr->vrsave_save_offset & 0xF;
14538 info_ptr->altivec_padding_size = 0;
14540 info_ptr->altivec_save_offset
14541 = info_ptr->vrsave_save_offset
14542 - info_ptr->altivec_padding_size
14543 - info_ptr->altivec_size;
14544 gcc_assert (info_ptr->altivec_size == 0
14545 || info_ptr->altivec_save_offset % 16 == 0);
14547 /* Adjust for AltiVec case. */
14548 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
14551 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
14552 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
14553 info_ptr->lr_save_offset = 2*reg_size;
14557 info_ptr->fp_save_offset = - info_ptr->fp_size;
14558 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14559 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
14561 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14563 /* Align stack so SPE GPR save area is aligned on a
14564 double-word boundary. */
14565 if (info_ptr->spe_gp_size != 0)
14566 info_ptr->spe_padding_size
14567 = 8 - (-info_ptr->cr_save_offset % 8);
14569 info_ptr->spe_padding_size = 0;
14571 info_ptr->spe_gp_save_offset
14572 = info_ptr->cr_save_offset
14573 - info_ptr->spe_padding_size
14574 - info_ptr->spe_gp_size;
14576 /* Adjust for SPE case. */
14577 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
14579 else if (TARGET_ALTIVEC_ABI)
14581 info_ptr->vrsave_save_offset
14582 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
14584 /* Align stack so vector save area is on a quadword boundary. */
14585 if (info_ptr->altivec_size != 0)
14586 info_ptr->altivec_padding_size
14587 = 16 - (-info_ptr->vrsave_save_offset % 16);
14589 info_ptr->altivec_padding_size = 0;
14591 info_ptr->altivec_save_offset
14592 = info_ptr->vrsave_save_offset
14593 - info_ptr->altivec_padding_size
14594 - info_ptr->altivec_size;
14596 /* Adjust for AltiVec case. */
14597 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
14600 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
14601 info_ptr->ehrd_offset -= ehrd_size;
14602 info_ptr->lr_save_offset = reg_size;
14606 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
14607 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
14608 + info_ptr->gp_size
14609 + info_ptr->altivec_size
14610 + info_ptr->altivec_padding_size
14611 + info_ptr->spe_gp_size
14612 + info_ptr->spe_padding_size
14614 + info_ptr->cr_size
14615 + info_ptr->vrsave_size,
14618 non_fixed_size = (info_ptr->vars_size
14619 + info_ptr->parm_size
14620 + info_ptr->save_size);
14622 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
14623 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
14625 /* Determine if we need to allocate any stack frame:
14627 For AIX we need to push the stack if a frame pointer is needed
14628 (because the stack might be dynamically adjusted), if we are
14629 debugging, if we make calls, or if the sum of fp_save, gp_save,
14630 and local variables are more than the space needed to save all
14631 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14632 + 18*8 = 288 (GPR13 reserved).
14634 For V.4 we don't have the stack cushion that AIX uses, but assume
14635 that the debugger can handle stackless frames. */
14637 if (info_ptr->calls_p)
14638 info_ptr->push_p = 1;
14640 else if (DEFAULT_ABI == ABI_V4)
14641 info_ptr->push_p = non_fixed_size != 0;
14643 else if (frame_pointer_needed)
14644 info_ptr->push_p = 1;
14646 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
14647 info_ptr->push_p = 1;
14650 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
14652 /* Zero offsets if we're not saving those registers. */
14653 if (info_ptr->fp_size == 0)
14654 info_ptr->fp_save_offset = 0;
14656 if (info_ptr->gp_size == 0)
14657 info_ptr->gp_save_offset = 0;
14659 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
14660 info_ptr->altivec_save_offset = 0;
14662 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
14663 info_ptr->vrsave_save_offset = 0;
14665 if (! TARGET_SPE_ABI
14666 || info_ptr->spe_64bit_regs_used == 0
14667 || info_ptr->spe_gp_size == 0)
14668 info_ptr->spe_gp_save_offset = 0;
14670 if (! info_ptr->lr_save_p)
14671 info_ptr->lr_save_offset = 0;
14673 if (! info_ptr->cr_save_p)
14674 info_ptr->cr_save_offset = 0;
14679 /* Return true if the current function uses any GPRs in 64-bit SIMD
14683 spe_func_has_64bit_regs_p (void)
14687 /* Functions that save and restore all the call-saved registers will
14688 need to save/restore the registers in 64-bits. */
14689 if (current_function_calls_eh_return
14690 || current_function_calls_setjmp
14691 || current_function_has_nonlocal_goto)
14694 insns = get_insns ();
14696 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
14702 /* FIXME: This should be implemented with attributes...
14704 (set_attr "spe64" "true")....then,
14705 if (get_spe64(insn)) return true;
14707 It's the only reliable way to do the stuff below. */
14709 i = PATTERN (insn);
14710 if (GET_CODE (i) == SET)
14712 enum machine_mode mode = GET_MODE (SET_SRC (i));
14714 if (SPE_VECTOR_MODE (mode))
14716 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
14717 || mode == DDmode || mode == TDmode))
14727 debug_stack_info (rs6000_stack_t *info)
14729 const char *abi_string;
14732 info = rs6000_stack_info ();
14734 fprintf (stderr, "\nStack information for function %s:\n",
14735 ((current_function_decl && DECL_NAME (current_function_decl))
14736 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
14741 default: abi_string = "Unknown"; break;
14742 case ABI_NONE: abi_string = "NONE"; break;
14743 case ABI_AIX: abi_string = "AIX"; break;
14744 case ABI_DARWIN: abi_string = "Darwin"; break;
14745 case ABI_V4: abi_string = "V.4"; break;
14748 fprintf (stderr, "\tABI = %5s\n", abi_string);
14750 if (TARGET_ALTIVEC_ABI)
14751 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
14753 if (TARGET_SPE_ABI)
14754 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
14756 if (info->first_gp_reg_save != 32)
14757 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
14759 if (info->first_fp_reg_save != 64)
14760 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
14762 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
14763 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
14764 info->first_altivec_reg_save);
14766 if (info->lr_save_p)
14767 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
14769 if (info->cr_save_p)
14770 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
14772 if (info->vrsave_mask)
14773 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
14776 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
14779 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
14781 if (info->gp_save_offset)
14782 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
14784 if (info->fp_save_offset)
14785 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
14787 if (info->altivec_save_offset)
14788 fprintf (stderr, "\taltivec_save_offset = %5d\n",
14789 info->altivec_save_offset);
14791 if (info->spe_gp_save_offset)
14792 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
14793 info->spe_gp_save_offset);
14795 if (info->vrsave_save_offset)
14796 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
14797 info->vrsave_save_offset);
14799 if (info->lr_save_offset)
14800 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
14802 if (info->cr_save_offset)
14803 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
14805 if (info->varargs_save_offset)
14806 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
14808 if (info->total_size)
14809 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14812 if (info->vars_size)
14813 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14816 if (info->parm_size)
14817 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
14819 if (info->fixed_size)
14820 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14823 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14825 if (info->spe_gp_size)
14826 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14829 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14831 if (info->altivec_size)
14832 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14834 if (info->vrsave_size)
14835 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14837 if (info->altivec_padding_size)
14838 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14839 info->altivec_padding_size);
14841 if (info->spe_padding_size)
14842 fprintf (stderr, "\tspe_padding_size = %5d\n",
14843 info->spe_padding_size);
14846 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14848 if (info->save_size)
14849 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14851 if (info->reg_size != 4)
14852 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14854 fprintf (stderr, "\n");
14858 rs6000_return_addr (int count, rtx frame)
14860 /* Currently we don't optimize very well between prolog and body
14861 code and for PIC code the code can be actually quite bad, so
14862 don't try to be too clever here. */
14863 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14865 cfun->machine->ra_needs_full_frame = 1;
14872 plus_constant (copy_to_reg
14873 (gen_rtx_MEM (Pmode,
14874 memory_address (Pmode, frame))),
14875 RETURN_ADDRESS_OFFSET)));
14878 cfun->machine->ra_need_lr = 1;
14879 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14882 /* Say whether a function is a candidate for sibcall handling or not.
14883 We do not allow indirect calls to be optimized into sibling calls.
14884 Also, we can't do it if there are any vector parameters; there's
14885 nowhere to put the VRsave code so it works; note that functions with
14886 vector parameters are required to have a prototype, so the argument
14887 type info must be available here. (The tail recursion case can work
14888 with vector parameters, but there's no way to distinguish here.) */
14890 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14895 if (TARGET_ALTIVEC_VRSAVE)
14897 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14898 type; type = TREE_CHAIN (type))
14900 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14904 if (DEFAULT_ABI == ABI_DARWIN
14905 || ((*targetm.binds_local_p) (decl)
14906 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14908 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14910 if (!lookup_attribute ("longcall", attr_list)
14911 || lookup_attribute ("shortcall", attr_list))
14918 /* NULL if INSN insn is valid within a low-overhead loop.
14919 Otherwise return why doloop cannot be applied.
14920 PowerPC uses the COUNT register for branch on table instructions. */
14922 static const char *
14923 rs6000_invalid_within_doloop (const_rtx insn)
14926 return "Function call in the loop.";
14929 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14930 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14931 return "Computed branch in the loop.";
14937 rs6000_ra_ever_killed (void)
14943 if (current_function_is_thunk)
14946 /* regs_ever_live has LR marked as used if any sibcalls are present,
14947 but this should not force saving and restoring in the
14948 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14949 clobbers LR, so that is inappropriate. */
14951 /* Also, the prologue can generate a store into LR that
14952 doesn't really count, like this:
14955 bcl to set PIC register
14959 When we're called from the epilogue, we need to avoid counting
14960 this as a store. */
14962 push_topmost_sequence ();
14963 top = get_insns ();
14964 pop_topmost_sequence ();
14965 reg = gen_rtx_REG (Pmode, LR_REGNO);
14967 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14973 if (!SIBLING_CALL_P (insn))
14976 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14978 else if (set_of (reg, insn) != NULL_RTX
14979 && !prologue_epilogue_contains (insn))
14986 /* Emit instructions needed to load the TOC register.
14987 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14988 a constant pool; or for SVR4 -fpic. */
14991 rs6000_emit_load_toc_table (int fromprolog)
14994 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14996 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14999 rtx lab, tmp1, tmp2, got;
15001 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15002 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15004 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15006 got = rs6000_got_sym ();
15007 tmp1 = tmp2 = dest;
15010 tmp1 = gen_reg_rtx (Pmode);
15011 tmp2 = gen_reg_rtx (Pmode);
15013 emit_insn (gen_load_toc_v4_PIC_1 (lab));
15014 emit_move_insn (tmp1,
15015 gen_rtx_REG (Pmode, LR_REGNO));
15016 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
15017 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
15019 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
15021 emit_insn (gen_load_toc_v4_pic_si ());
15022 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
15024 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
15027 rtx temp0 = (fromprolog
15028 ? gen_rtx_REG (Pmode, 0)
15029 : gen_reg_rtx (Pmode));
15035 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15036 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15038 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
15039 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15041 emit_insn (gen_load_toc_v4_PIC_1 (symF));
15042 emit_move_insn (dest,
15043 gen_rtx_REG (Pmode, LR_REGNO));
15044 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
15050 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15051 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
15052 emit_move_insn (dest,
15053 gen_rtx_REG (Pmode, LR_REGNO));
15054 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
15056 emit_insn (gen_addsi3 (dest, temp0, dest));
15058 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
15060 /* This is for AIX code running in non-PIC ELF32. */
15063 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15064 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15066 emit_insn (gen_elf_high (dest, realsym));
15067 emit_insn (gen_elf_low (dest, dest, realsym));
15071 gcc_assert (DEFAULT_ABI == ABI_AIX);
15074 emit_insn (gen_load_toc_aix_si (dest));
15076 emit_insn (gen_load_toc_aix_di (dest));
15080 /* Emit instructions to restore the link register after determining where
15081 its value has been stored. */
15084 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
15086 rs6000_stack_t *info = rs6000_stack_info ();
15089 operands[0] = source;
15090 operands[1] = scratch;
15092 if (info->lr_save_p)
15094 rtx frame_rtx = stack_pointer_rtx;
15095 HOST_WIDE_INT sp_offset = 0;
15098 if (frame_pointer_needed
15099 || current_function_calls_alloca
15100 || info->total_size > 32767)
15102 tmp = gen_frame_mem (Pmode, frame_rtx);
15103 emit_move_insn (operands[1], tmp);
15104 frame_rtx = operands[1];
15106 else if (info->push_p)
15107 sp_offset = info->total_size;
15109 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
15110 tmp = gen_frame_mem (Pmode, tmp);
15111 emit_move_insn (tmp, operands[0]);
15114 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
15117 static GTY(()) alias_set_type set = -1;
15120 get_TOC_alias_set (void)
15123 set = new_alias_set ();
15127 /* This returns nonzero if the current function uses the TOC. This is
15128 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15129 is generated by the ABI_V4 load_toc_* patterns. */
15136 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15139 rtx pat = PATTERN (insn);
15142 if (GET_CODE (pat) == PARALLEL)
15143 for (i = 0; i < XVECLEN (pat, 0); i++)
15145 rtx sub = XVECEXP (pat, 0, i);
15146 if (GET_CODE (sub) == USE)
15148 sub = XEXP (sub, 0);
15149 if (GET_CODE (sub) == UNSPEC
15150 && XINT (sub, 1) == UNSPEC_TOC)
15160 create_TOC_reference (rtx symbol)
15162 if (!can_create_pseudo_p ())
15163 df_set_regs_ever_live (TOC_REGISTER, true);
15164 return gen_rtx_PLUS (Pmode,
15165 gen_rtx_REG (Pmode, TOC_REGISTER),
15166 gen_rtx_CONST (Pmode,
15167 gen_rtx_MINUS (Pmode, symbol,
15168 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
15171 /* If _Unwind_* has been called from within the same module,
15172 toc register is not guaranteed to be saved to 40(1) on function
15173 entry. Save it there in that case. */
15176 rs6000_aix_emit_builtin_unwind_init (void)
15179 rtx stack_top = gen_reg_rtx (Pmode);
15180 rtx opcode_addr = gen_reg_rtx (Pmode);
15181 rtx opcode = gen_reg_rtx (SImode);
15182 rtx tocompare = gen_reg_rtx (SImode);
15183 rtx no_toc_save_needed = gen_label_rtx ();
15185 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
15186 emit_move_insn (stack_top, mem);
15188 mem = gen_frame_mem (Pmode,
15189 gen_rtx_PLUS (Pmode, stack_top,
15190 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
15191 emit_move_insn (opcode_addr, mem);
15192 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
15193 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
15194 : 0xE8410028, SImode));
15196 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
15197 SImode, NULL_RTX, NULL_RTX,
15198 no_toc_save_needed);
15200 mem = gen_frame_mem (Pmode,
15201 gen_rtx_PLUS (Pmode, stack_top,
15202 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
15203 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
15204 emit_label (no_toc_save_needed);
15207 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15208 and the change to the stack pointer. */
15211 rs6000_emit_stack_tie (void)
15213 rtx mem = gen_frame_mem (BLKmode,
15214 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
15216 emit_insn (gen_stack_tie (mem));
15219 /* Emit the correct code for allocating stack space, as insns.
15220 If COPY_R12, make sure a copy of the old frame is left in r12.
15221 The generated code may use hard register 0 as a temporary. */
15224 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
15227 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15228 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
15229 rtx todec = gen_int_mode (-size, Pmode);
15231 if (INTVAL (todec) != -size)
15233 warning (0, "stack frame too large");
15234 emit_insn (gen_trap ());
15238 if (current_function_limit_stack)
15240 if (REG_P (stack_limit_rtx)
15241 && REGNO (stack_limit_rtx) > 1
15242 && REGNO (stack_limit_rtx) <= 31)
15244 emit_insn (TARGET_32BIT
15245 ? gen_addsi3 (tmp_reg,
15248 : gen_adddi3 (tmp_reg,
15252 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15255 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
15257 && DEFAULT_ABI == ABI_V4)
15259 rtx toload = gen_rtx_CONST (VOIDmode,
15260 gen_rtx_PLUS (Pmode,
15264 emit_insn (gen_elf_high (tmp_reg, toload));
15265 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
15266 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15270 warning (0, "stack limit expression is not supported");
15273 if (copy_r12 || ! TARGET_UPDATE)
15274 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
15280 /* Need a note here so that try_split doesn't get confused. */
15281 if (get_last_insn () == NULL_RTX)
15282 emit_note (NOTE_INSN_DELETED);
15283 insn = emit_move_insn (tmp_reg, todec);
15284 try_split (PATTERN (insn), insn, 0);
15288 insn = emit_insn (TARGET_32BIT
15289 ? gen_movsi_update (stack_reg, stack_reg,
15291 : gen_movdi_di_update (stack_reg, stack_reg,
15292 todec, stack_reg));
15296 insn = emit_insn (TARGET_32BIT
15297 ? gen_addsi3 (stack_reg, stack_reg, todec)
15298 : gen_adddi3 (stack_reg, stack_reg, todec));
15299 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
15300 gen_rtx_REG (Pmode, 12));
15303 RTX_FRAME_RELATED_P (insn) = 1;
15305 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15306 gen_rtx_SET (VOIDmode, stack_reg,
15307 gen_rtx_PLUS (Pmode, stack_reg,
15312 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15313 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15314 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15315 deduce these equivalences by itself so it wasn't necessary to hold
15316 its hand so much. */
15319 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
15320 rtx reg2, rtx rreg)
15324 /* copy_rtx will not make unique copies of registers, so we need to
15325 ensure we don't have unwanted sharing here. */
15327 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15330 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15332 real = copy_rtx (PATTERN (insn));
15334 if (reg2 != NULL_RTX)
15335 real = replace_rtx (real, reg2, rreg);
15337 real = replace_rtx (real, reg,
15338 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
15339 STACK_POINTER_REGNUM),
15342 /* We expect that 'real' is either a SET or a PARALLEL containing
15343 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15344 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15346 if (GET_CODE (real) == SET)
15350 temp = simplify_rtx (SET_SRC (set));
15352 SET_SRC (set) = temp;
15353 temp = simplify_rtx (SET_DEST (set));
15355 SET_DEST (set) = temp;
15356 if (GET_CODE (SET_DEST (set)) == MEM)
15358 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15360 XEXP (SET_DEST (set), 0) = temp;
15367 gcc_assert (GET_CODE (real) == PARALLEL);
15368 for (i = 0; i < XVECLEN (real, 0); i++)
15369 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
15371 rtx set = XVECEXP (real, 0, i);
15373 temp = simplify_rtx (SET_SRC (set));
15375 SET_SRC (set) = temp;
15376 temp = simplify_rtx (SET_DEST (set));
15378 SET_DEST (set) = temp;
15379 if (GET_CODE (SET_DEST (set)) == MEM)
15381 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15383 XEXP (SET_DEST (set), 0) = temp;
15385 RTX_FRAME_RELATED_P (set) = 1;
15390 real = spe_synthesize_frame_save (real);
15392 RTX_FRAME_RELATED_P (insn) = 1;
15393 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15398 /* Given an SPE frame note, return a PARALLEL of SETs with the
15399 original note, plus a synthetic register save. */
15402 spe_synthesize_frame_save (rtx real)
15404 rtx synth, offset, reg, real2;
15406 if (GET_CODE (real) != SET
15407 || GET_MODE (SET_SRC (real)) != V2SImode)
15410 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
15411 frame related note. The parallel contains a set of the register
15412 being saved, and another set to a synthetic register (n+1200).
15413 This is so we can differentiate between 64-bit and 32-bit saves.
15414 Words cannot describe this nastiness. */
15416 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
15417 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
15418 && GET_CODE (SET_SRC (real)) == REG);
15421 (set (mem (plus (reg x) (const y)))
15424 (set (mem (plus (reg x) (const y+4)))
15428 real2 = copy_rtx (real);
15429 PUT_MODE (SET_DEST (real2), SImode);
15430 reg = SET_SRC (real2);
15431 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
15432 synth = copy_rtx (real2);
15434 if (BYTES_BIG_ENDIAN)
15436 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
15437 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
15440 reg = SET_SRC (synth);
15442 synth = replace_rtx (synth, reg,
15443 gen_rtx_REG (SImode, REGNO (reg) + 1200));
15445 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
15446 synth = replace_rtx (synth, offset,
15447 GEN_INT (INTVAL (offset)
15448 + (BYTES_BIG_ENDIAN ? 0 : 4)));
15450 RTX_FRAME_RELATED_P (synth) = 1;
15451 RTX_FRAME_RELATED_P (real2) = 1;
15452 if (BYTES_BIG_ENDIAN)
15453 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
15455 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
15460 /* Returns an insn that has a vrsave set operation with the
15461 appropriate CLOBBERs. */
15464 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
15467 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
15468 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15471 = gen_rtx_SET (VOIDmode,
15473 gen_rtx_UNSPEC_VOLATILE (SImode,
15474 gen_rtvec (2, reg, vrsave),
15475 UNSPECV_SET_VRSAVE));
15479 /* We need to clobber the registers in the mask so the scheduler
15480 does not move sets to VRSAVE before sets of AltiVec registers.
15482 However, if the function receives nonlocal gotos, reload will set
15483 all call saved registers live. We will end up with:
15485 (set (reg 999) (mem))
15486 (parallel [ (set (reg vrsave) (unspec blah))
15487 (clobber (reg 999))])
15489 The clobber will cause the store into reg 999 to be dead, and
15490 flow will attempt to delete an epilogue insn. In this case, we
15491 need an unspec use/set of the register. */
15493 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
15494 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15496 if (!epiloguep || call_used_regs [i])
15497 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
15498 gen_rtx_REG (V4SImode, i));
15501 rtx reg = gen_rtx_REG (V4SImode, i);
15504 = gen_rtx_SET (VOIDmode,
15506 gen_rtx_UNSPEC (V4SImode,
15507 gen_rtvec (1, reg), 27));
15511 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
15513 for (i = 0; i < nclobs; ++i)
15514 XVECEXP (insn, 0, i) = clobs[i];
15519 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15520 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15523 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
15524 unsigned int regno, int offset, HOST_WIDE_INT total_size)
15526 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
15527 rtx replacea, replaceb;
15529 int_rtx = GEN_INT (offset);
15531 /* Some cases that need register indexed addressing. */
15532 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
15533 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == DDmode))
15535 && SPE_VECTOR_MODE (mode)
15536 && !SPE_CONST_OFFSET_OK (offset)))
15538 /* Whomever calls us must make sure r11 is available in the
15539 flow path of instructions in the prologue. */
15540 offset_rtx = gen_rtx_REG (Pmode, 11);
15541 emit_move_insn (offset_rtx, int_rtx);
15543 replacea = offset_rtx;
15544 replaceb = int_rtx;
15548 offset_rtx = int_rtx;
15549 replacea = NULL_RTX;
15550 replaceb = NULL_RTX;
15553 reg = gen_rtx_REG (mode, regno);
15554 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
15555 mem = gen_frame_mem (mode, addr);
15557 insn = emit_move_insn (mem, reg);
15559 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
15562 /* Emit an offset memory reference suitable for a frame store, while
15563 converting to a valid addressing mode. */
15566 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
15568 rtx int_rtx, offset_rtx;
15570 int_rtx = GEN_INT (offset);
15572 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
15573 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == DDmode)))
15575 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15576 emit_move_insn (offset_rtx, int_rtx);
15579 offset_rtx = int_rtx;
15581 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
15584 /* Look for user-defined global regs. We should not save and restore these,
15585 and cannot use stmw/lmw if there are any in its range. */
15588 no_global_regs_above (int first_greg)
15591 for (i = 0; i < 32 - first_greg; i++)
15592 if (global_regs[first_greg + i])
15597 #ifndef TARGET_FIX_AND_CONTINUE
15598 #define TARGET_FIX_AND_CONTINUE 0
15601 /* Determine whether the gp REG is really used. */
15604 rs6000_reg_live_or_pic_offset_p (int reg)
15606 return ((df_regs_ever_live_p (reg)
15607 && (!call_used_regs[reg]
15608 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15609 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15610 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15611 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15612 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
15615 /* Emit function prologue as insns. */
15618 rs6000_emit_prologue (void)
15620 rs6000_stack_t *info = rs6000_stack_info ();
15621 enum machine_mode reg_mode = Pmode;
15622 int reg_size = TARGET_32BIT ? 4 : 8;
15623 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15624 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
15625 rtx frame_reg_rtx = sp_reg_rtx;
15626 rtx cr_save_rtx = NULL_RTX;
15628 int saving_FPRs_inline;
15629 int using_store_multiple;
15630 HOST_WIDE_INT sp_offset = 0;
15632 if (TARGET_FIX_AND_CONTINUE)
15634 /* gdb on darwin arranges to forward a function from the old
15635 address by modifying the first 5 instructions of the function
15636 to branch to the overriding function. This is necessary to
15637 permit function pointers that point to the old function to
15638 actually forward to the new function. */
15639 emit_insn (gen_nop ());
15640 emit_insn (gen_nop ());
15641 emit_insn (gen_nop ());
15642 emit_insn (gen_nop ());
15643 emit_insn (gen_nop ());
15646 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15648 reg_mode = V2SImode;
15652 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15653 && (!TARGET_SPE_ABI
15654 || info->spe_64bit_regs_used == 0)
15655 && info->first_gp_reg_save < 31
15656 && no_global_regs_above (info->first_gp_reg_save));
15657 saving_FPRs_inline = (info->first_fp_reg_save == 64
15658 || FP_SAVE_INLINE (info->first_fp_reg_save)
15659 || current_function_calls_eh_return
15660 || cfun->machine->ra_need_lr);
15662 /* For V.4, update stack before we do any saving and set back pointer. */
15663 if (! WORLD_SAVE_P (info)
15665 && (DEFAULT_ABI == ABI_V4
15666 || current_function_calls_eh_return))
15668 if (info->total_size < 32767)
15669 sp_offset = info->total_size;
15671 frame_reg_rtx = frame_ptr_rtx;
15672 rs6000_emit_allocate_stack (info->total_size,
15673 (frame_reg_rtx != sp_reg_rtx
15674 && (info->cr_save_p
15676 || info->first_fp_reg_save < 64
15677 || info->first_gp_reg_save < 32
15679 if (frame_reg_rtx != sp_reg_rtx)
15680 rs6000_emit_stack_tie ();
15683 /* Handle world saves specially here. */
15684 if (WORLD_SAVE_P (info))
15691 /* save_world expects lr in r0. */
15692 reg0 = gen_rtx_REG (Pmode, 0);
15693 if (info->lr_save_p)
15695 insn = emit_move_insn (reg0,
15696 gen_rtx_REG (Pmode, LR_REGNO));
15697 RTX_FRAME_RELATED_P (insn) = 1;
15700 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15701 assumptions about the offsets of various bits of the stack
15703 gcc_assert (info->gp_save_offset == -220
15704 && info->fp_save_offset == -144
15705 && info->lr_save_offset == 8
15706 && info->cr_save_offset == 4
15709 && (!current_function_calls_eh_return
15710 || info->ehrd_offset == -432)
15711 && info->vrsave_save_offset == -224
15712 && info->altivec_save_offset == -416);
15714 treg = gen_rtx_REG (SImode, 11);
15715 emit_move_insn (treg, GEN_INT (-info->total_size));
15717 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15718 in R11. It also clobbers R12, so beware! */
15720 /* Preserve CR2 for save_world prologues */
15722 sz += 32 - info->first_gp_reg_save;
15723 sz += 64 - info->first_fp_reg_save;
15724 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
15725 p = rtvec_alloc (sz);
15727 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
15728 gen_rtx_REG (SImode,
15730 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15731 gen_rtx_SYMBOL_REF (Pmode,
15733 /* We do floats first so that the instruction pattern matches
15735 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15737 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15738 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15739 GEN_INT (info->fp_save_offset
15740 + sp_offset + 8 * i));
15741 rtx mem = gen_frame_mem (DFmode, addr);
15743 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15745 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15747 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15748 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15749 GEN_INT (info->altivec_save_offset
15750 + sp_offset + 16 * i));
15751 rtx mem = gen_frame_mem (V4SImode, addr);
15753 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15755 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15757 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15758 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15759 GEN_INT (info->gp_save_offset
15760 + sp_offset + reg_size * i));
15761 rtx mem = gen_frame_mem (reg_mode, addr);
15763 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15767 /* CR register traditionally saved as CR2. */
15768 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15769 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15770 GEN_INT (info->cr_save_offset
15772 rtx mem = gen_frame_mem (reg_mode, addr);
15774 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15776 /* Explain about use of R0. */
15777 if (info->lr_save_p)
15779 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15780 GEN_INT (info->lr_save_offset
15782 rtx mem = gen_frame_mem (reg_mode, addr);
15784 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
15786 /* Explain what happens to the stack pointer. */
15788 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
15789 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
15792 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15793 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15794 treg, GEN_INT (-info->total_size));
15795 sp_offset = info->total_size;
15798 /* If we use the link register, get it into r0. */
15799 if (!WORLD_SAVE_P (info) && info->lr_save_p)
15801 rtx addr, reg, mem;
15803 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
15804 gen_rtx_REG (Pmode, LR_REGNO));
15805 RTX_FRAME_RELATED_P (insn) = 1;
15807 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15808 GEN_INT (info->lr_save_offset + sp_offset));
15809 reg = gen_rtx_REG (Pmode, 0);
15810 mem = gen_rtx_MEM (Pmode, addr);
15811 /* This should not be of rs6000_sr_alias_set, because of
15812 __builtin_return_address. */
15814 insn = emit_move_insn (mem, reg);
15815 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15816 NULL_RTX, NULL_RTX);
15819 /* If we need to save CR, put it into r12. */
15820 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
15824 cr_save_rtx = gen_rtx_REG (SImode, 12);
15825 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15826 RTX_FRAME_RELATED_P (insn) = 1;
15827 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15828 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15829 But that's OK. All we have to do is specify that _one_ condition
15830 code register is saved in this stack slot. The thrower's epilogue
15831 will then restore all the call-saved registers.
15832 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15833 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
15834 gen_rtx_REG (SImode, CR2_REGNO));
15835 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15840 /* Do any required saving of fpr's. If only one or two to save, do
15841 it ourselves. Otherwise, call function. */
15842 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
15845 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15846 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15847 && ! call_used_regs[info->first_fp_reg_save+i]))
15848 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
15849 info->first_fp_reg_save + i,
15850 info->fp_save_offset + sp_offset + 8 * i,
15853 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
15857 const char *alloc_rname;
15859 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
15861 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
15862 gen_rtx_REG (Pmode,
15864 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
15865 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
15866 alloc_rname = ggc_strdup (rname);
15867 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15868 gen_rtx_SYMBOL_REF (Pmode,
15870 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15872 rtx addr, reg, mem;
15873 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15874 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15875 GEN_INT (info->fp_save_offset
15876 + sp_offset + 8*i));
15877 mem = gen_frame_mem (DFmode, addr);
15879 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
15881 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15882 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15883 NULL_RTX, NULL_RTX);
15886 /* Save GPRs. This is done as a PARALLEL if we are using
15887 the store-multiple instructions. */
15888 if (!WORLD_SAVE_P (info) && using_store_multiple)
15892 p = rtvec_alloc (32 - info->first_gp_reg_save);
15893 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15895 rtx addr, reg, mem;
15896 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15897 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15898 GEN_INT (info->gp_save_offset
15901 mem = gen_frame_mem (reg_mode, addr);
15903 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
15905 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15906 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15907 NULL_RTX, NULL_RTX);
15909 else if (!WORLD_SAVE_P (info)
15911 && info->spe_64bit_regs_used != 0
15912 && info->first_gp_reg_save != 32)
15915 rtx spe_save_area_ptr;
15916 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15917 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15918 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15920 /* Determine whether we can address all of the registers that need
15921 to be saved with an offset from the stack pointer that fits in
15922 the small const field for SPE memory instructions. */
15923 int spe_regs_addressable_via_sp
15924 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15925 + (32 - info->first_gp_reg_save - 1) * reg_size);
15928 if (spe_regs_addressable_via_sp)
15930 spe_save_area_ptr = frame_reg_rtx;
15931 spe_offset = info->spe_gp_save_offset + sp_offset;
15935 /* Make r11 point to the start of the SPE save area. We need
15936 to be careful here if r11 is holding the static chain. If
15937 it is, then temporarily save it in r0. We would use r0 as
15938 our base register here, but using r0 as a base register in
15939 loads and stores means something different from what we
15941 if (using_static_chain_p)
15943 rtx r0 = gen_rtx_REG (Pmode, 0);
15945 gcc_assert (info->first_gp_reg_save > 11);
15947 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15950 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15951 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15952 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15957 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15958 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15960 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15961 rtx offset, addr, mem;
15963 /* We're doing all this to ensure that the offset fits into
15964 the immediate offset of 'evstdd'. */
15965 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15967 offset = GEN_INT (reg_size * i + spe_offset);
15968 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15969 mem = gen_rtx_MEM (V2SImode, addr);
15971 insn = emit_move_insn (mem, reg);
15973 rs6000_frame_related (insn, spe_save_area_ptr,
15974 info->spe_gp_save_offset
15975 + sp_offset + reg_size * i,
15976 offset, const0_rtx);
15979 /* Move the static chain pointer back. */
15980 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15981 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15983 else if (!WORLD_SAVE_P (info))
15986 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15987 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15989 rtx addr, reg, mem;
15990 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15992 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15993 GEN_INT (info->gp_save_offset
15996 mem = gen_frame_mem (reg_mode, addr);
15998 insn = emit_move_insn (mem, reg);
15999 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16000 NULL_RTX, NULL_RTX);
16004 /* ??? There's no need to emit actual instructions here, but it's the
16005 easiest way to get the frame unwind information emitted. */
16006 if (current_function_calls_eh_return)
16008 unsigned int i, regno;
16010 /* In AIX ABI we need to pretend we save r2 here. */
16013 rtx addr, reg, mem;
16015 reg = gen_rtx_REG (reg_mode, 2);
16016 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16017 GEN_INT (sp_offset + 5 * reg_size));
16018 mem = gen_frame_mem (reg_mode, addr);
16020 insn = emit_move_insn (mem, reg);
16021 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16022 NULL_RTX, NULL_RTX);
16023 PATTERN (insn) = gen_blockage ();
16028 regno = EH_RETURN_DATA_REGNO (i);
16029 if (regno == INVALID_REGNUM)
16032 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
16033 info->ehrd_offset + sp_offset
16034 + reg_size * (int) i,
16039 /* Save CR if we use any that must be preserved. */
16040 if (!WORLD_SAVE_P (info) && info->cr_save_p)
16042 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16043 GEN_INT (info->cr_save_offset + sp_offset));
16044 rtx mem = gen_frame_mem (SImode, addr);
16045 /* See the large comment above about why CR2_REGNO is used. */
16046 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
16048 /* If r12 was used to hold the original sp, copy cr into r0 now
16050 if (REGNO (frame_reg_rtx) == 12)
16054 cr_save_rtx = gen_rtx_REG (SImode, 0);
16055 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
16056 RTX_FRAME_RELATED_P (insn) = 1;
16057 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
16058 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
16063 insn = emit_move_insn (mem, cr_save_rtx);
16065 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16066 NULL_RTX, NULL_RTX);
16069 /* Update stack and set back pointer unless this is V.4,
16070 for which it was done previously. */
16071 if (!WORLD_SAVE_P (info) && info->push_p
16072 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
16074 if (info->total_size < 32767)
16075 sp_offset = info->total_size;
16077 frame_reg_rtx = frame_ptr_rtx;
16078 rs6000_emit_allocate_stack (info->total_size,
16079 (frame_reg_rtx != sp_reg_rtx
16080 && ((info->altivec_size != 0)
16081 || (info->vrsave_mask != 0)
16083 if (frame_reg_rtx != sp_reg_rtx)
16084 rs6000_emit_stack_tie ();
16087 /* Set frame pointer, if needed. */
16088 if (frame_pointer_needed)
16090 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
16092 RTX_FRAME_RELATED_P (insn) = 1;
16095 /* Save AltiVec registers if needed. Save here because the red zone does
16096 not include AltiVec registers. */
16097 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
16101 /* There should be a non inline version of this, for when we
16102 are saving lots of vector registers. */
16103 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16104 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16106 rtx areg, savereg, mem;
16109 offset = info->altivec_save_offset + sp_offset
16110 + 16 * (i - info->first_altivec_reg_save);
16112 savereg = gen_rtx_REG (V4SImode, i);
16114 areg = gen_rtx_REG (Pmode, 0);
16115 emit_move_insn (areg, GEN_INT (offset));
16117 /* AltiVec addressing mode is [reg+reg]. */
16118 mem = gen_frame_mem (V4SImode,
16119 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
16121 insn = emit_move_insn (mem, savereg);
16123 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16124 areg, GEN_INT (offset));
16128 /* VRSAVE is a bit vector representing which AltiVec registers
16129 are used. The OS uses this to determine which vector
16130 registers to save on a context switch. We need to save
16131 VRSAVE on the stack frame, add whatever AltiVec registers we
16132 used in this function, and do the corresponding magic in the
16135 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
16136 && info->vrsave_mask != 0)
16138 rtx reg, mem, vrsave;
16141 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16142 as frame_reg_rtx and r11 as the static chain pointer for
16143 nested functions. */
16144 reg = gen_rtx_REG (SImode, 0);
16145 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
16147 emit_insn (gen_get_vrsave_internal (reg));
16149 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
16151 if (!WORLD_SAVE_P (info))
16154 offset = info->vrsave_save_offset + sp_offset;
16155 mem = gen_frame_mem (SImode,
16156 gen_rtx_PLUS (Pmode, frame_reg_rtx,
16157 GEN_INT (offset)));
16158 insn = emit_move_insn (mem, reg);
16161 /* Include the registers in the mask. */
16162 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
16164 insn = emit_insn (generate_set_vrsave (reg, info, 0));
16167 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16168 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
16169 || (DEFAULT_ABI == ABI_V4
16170 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
16171 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
16173 /* If emit_load_toc_table will use the link register, we need to save
16174 it. We use R12 for this purpose because emit_load_toc_table
16175 can use register 0. This allows us to use a plain 'blr' to return
16176 from the procedure more often. */
16177 int save_LR_around_toc_setup = (TARGET_ELF
16178 && DEFAULT_ABI != ABI_AIX
16180 && ! info->lr_save_p
16181 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
16182 if (save_LR_around_toc_setup)
16184 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16186 insn = emit_move_insn (frame_ptr_rtx, lr);
16187 RTX_FRAME_RELATED_P (insn) = 1;
16189 rs6000_emit_load_toc_table (TRUE);
16191 insn = emit_move_insn (lr, frame_ptr_rtx);
16192 RTX_FRAME_RELATED_P (insn) = 1;
16195 rs6000_emit_load_toc_table (TRUE);
16199 if (DEFAULT_ABI == ABI_DARWIN
16200 && flag_pic && current_function_uses_pic_offset_table)
16202 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16203 rtx src = machopic_function_base_sym ();
16205 /* Save and restore LR locally around this call (in R0). */
16206 if (!info->lr_save_p)
16207 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
16209 emit_insn (gen_load_macho_picbase (src));
16211 emit_move_insn (gen_rtx_REG (Pmode,
16212 RS6000_PIC_OFFSET_TABLE_REGNUM),
16215 if (!info->lr_save_p)
16216 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
16221 /* Write function prologue. */
16224 rs6000_output_function_prologue (FILE *file,
16225 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
16227 rs6000_stack_t *info = rs6000_stack_info ();
16229 if (TARGET_DEBUG_STACK)
16230 debug_stack_info (info);
16232 /* Write .extern for any function we will call to save and restore
16234 if (info->first_fp_reg_save < 64
16235 && !FP_SAVE_INLINE (info->first_fp_reg_save))
16236 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16237 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
16238 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
16239 RESTORE_FP_SUFFIX);
16241 /* Write .extern for AIX common mode routines, if needed. */
16242 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
16244 fputs ("\t.extern __mulh\n", file);
16245 fputs ("\t.extern __mull\n", file);
16246 fputs ("\t.extern __divss\n", file);
16247 fputs ("\t.extern __divus\n", file);
16248 fputs ("\t.extern __quoss\n", file);
16249 fputs ("\t.extern __quous\n", file);
16250 common_mode_defined = 1;
16253 if (! HAVE_prologue)
16257 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16258 the "toplevel" insn chain. */
16259 emit_note (NOTE_INSN_DELETED);
16260 rs6000_emit_prologue ();
16261 emit_note (NOTE_INSN_DELETED);
16263 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16267 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16269 INSN_ADDRESSES_NEW (insn, addr);
16274 if (TARGET_DEBUG_STACK)
16275 debug_rtx_list (get_insns (), 100);
16276 final (get_insns (), file, FALSE);
16280 rs6000_pic_labelno++;
16283 /* Emit function epilogue as insns.
16285 At present, dwarf2out_frame_debug_expr doesn't understand
16286 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16287 anywhere in the epilogue. Most of the insns below would in any case
16288 need special notes to explain where r11 is in relation to the stack. */
16291 rs6000_emit_epilogue (int sibcall)
16293 rs6000_stack_t *info;
16294 int restoring_FPRs_inline;
16295 int using_load_multiple;
16296 int using_mtcr_multiple;
16297 int use_backchain_to_restore_sp;
16299 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
16300 rtx frame_reg_rtx = sp_reg_rtx;
16301 enum machine_mode reg_mode = Pmode;
16302 int reg_size = TARGET_32BIT ? 4 : 8;
16305 info = rs6000_stack_info ();
16307 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
16309 reg_mode = V2SImode;
16313 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
16314 && (!TARGET_SPE_ABI
16315 || info->spe_64bit_regs_used == 0)
16316 && info->first_gp_reg_save < 31
16317 && no_global_regs_above (info->first_gp_reg_save));
16318 restoring_FPRs_inline = (sibcall
16319 || current_function_calls_eh_return
16320 || info->first_fp_reg_save == 64
16321 || FP_SAVE_INLINE (info->first_fp_reg_save));
16322 use_backchain_to_restore_sp = (frame_pointer_needed
16323 || current_function_calls_alloca
16324 || info->total_size > 32767);
16325 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
16326 || rs6000_cpu == PROCESSOR_PPC603
16327 || rs6000_cpu == PROCESSOR_PPC750
16330 if (WORLD_SAVE_P (info))
16334 const char *alloc_rname;
16337 /* eh_rest_world_r10 will return to the location saved in the LR
16338 stack slot (which is not likely to be our caller.)
16339 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16340 rest_world is similar, except any R10 parameter is ignored.
16341 The exception-handling stuff that was here in 2.95 is no
16342 longer necessary. */
16346 + 32 - info->first_gp_reg_save
16347 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
16348 + 63 + 1 - info->first_fp_reg_save);
16350 strcpy (rname, ((current_function_calls_eh_return) ?
16351 "*eh_rest_world_r10" : "*rest_world"));
16352 alloc_rname = ggc_strdup (rname);
16355 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
16356 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
16357 gen_rtx_REG (Pmode,
16360 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
16361 /* The instruction pattern requires a clobber here;
16362 it is shared with the restVEC helper. */
16364 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
16367 /* CR register traditionally saved as CR2. */
16368 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16369 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16370 GEN_INT (info->cr_save_offset));
16371 rtx mem = gen_frame_mem (reg_mode, addr);
16373 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16376 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16378 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16379 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16380 GEN_INT (info->gp_save_offset
16382 rtx mem = gen_frame_mem (reg_mode, addr);
16384 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16386 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16388 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16389 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16390 GEN_INT (info->altivec_save_offset
16392 rtx mem = gen_frame_mem (V4SImode, addr);
16394 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16396 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
16398 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
16399 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16400 GEN_INT (info->fp_save_offset
16402 rtx mem = gen_frame_mem (DFmode, addr);
16404 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16407 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
16409 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
16411 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
16413 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
16415 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
16416 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
16421 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
16423 sp_offset = info->total_size;
16425 /* Restore AltiVec registers if needed. */
16426 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
16430 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16431 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16433 rtx addr, areg, mem;
16435 areg = gen_rtx_REG (Pmode, 0);
16437 (areg, GEN_INT (info->altivec_save_offset
16439 + 16 * (i - info->first_altivec_reg_save)));
16441 /* AltiVec addressing mode is [reg+reg]. */
16442 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
16443 mem = gen_frame_mem (V4SImode, addr);
16445 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
16449 /* If we have a frame pointer, a call to alloca, or a large stack
16450 frame, restore the old stack pointer using the backchain. Otherwise,
16451 we know what size to update it with. */
16452 if (use_backchain_to_restore_sp)
16454 /* Under V.4, don't reset the stack pointer until after we're done
16455 loading the saved registers. */
16456 if (DEFAULT_ABI == ABI_V4)
16457 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16459 emit_move_insn (frame_reg_rtx,
16460 gen_rtx_MEM (Pmode, sp_reg_rtx));
16463 else if (info->push_p
16464 && DEFAULT_ABI != ABI_V4
16465 && !current_function_calls_eh_return)
16467 emit_insn (TARGET_32BIT
16468 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16469 GEN_INT (info->total_size))
16470 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16471 GEN_INT (info->total_size)));
16475 /* Restore VRSAVE if needed. */
16476 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
16477 && info->vrsave_mask != 0)
16479 rtx addr, mem, reg;
16481 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16482 GEN_INT (info->vrsave_save_offset + sp_offset));
16483 mem = gen_frame_mem (SImode, addr);
16484 reg = gen_rtx_REG (SImode, 12);
16485 emit_move_insn (reg, mem);
16487 emit_insn (generate_set_vrsave (reg, info, 1));
16490 /* Get the old lr if we saved it. */
16491 if (info->lr_save_p)
16493 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
16494 info->lr_save_offset + sp_offset);
16496 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
16499 /* Get the old cr if we saved it. */
16500 if (info->cr_save_p)
16502 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16503 GEN_INT (info->cr_save_offset + sp_offset));
16504 rtx mem = gen_frame_mem (SImode, addr);
16506 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
16509 /* Set LR here to try to overlap restores below. */
16510 if (info->lr_save_p)
16511 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
16512 gen_rtx_REG (Pmode, 0));
16514 /* Load exception handler data registers, if needed. */
16515 if (current_function_calls_eh_return)
16517 unsigned int i, regno;
16521 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16522 GEN_INT (sp_offset + 5 * reg_size));
16523 rtx mem = gen_frame_mem (reg_mode, addr);
16525 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
16532 regno = EH_RETURN_DATA_REGNO (i);
16533 if (regno == INVALID_REGNUM)
16536 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
16537 info->ehrd_offset + sp_offset
16538 + reg_size * (int) i);
16540 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
16544 /* Restore GPRs. This is done as a PARALLEL if we are using
16545 the load-multiple instructions. */
16546 if (using_load_multiple)
16549 p = rtvec_alloc (32 - info->first_gp_reg_save);
16550 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16552 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16553 GEN_INT (info->gp_save_offset
16556 rtx mem = gen_frame_mem (reg_mode, addr);
16559 gen_rtx_SET (VOIDmode,
16560 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
16563 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16565 else if (TARGET_SPE_ABI
16566 && info->spe_64bit_regs_used != 0
16567 && info->first_gp_reg_save != 32)
16569 /* Determine whether we can address all of the registers that need
16570 to be saved with an offset from the stack pointer that fits in
16571 the small const field for SPE memory instructions. */
16572 int spe_regs_addressable_via_sp
16573 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
16574 + (32 - info->first_gp_reg_save - 1) * reg_size);
16577 if (spe_regs_addressable_via_sp)
16578 spe_offset = info->spe_gp_save_offset + sp_offset;
16581 rtx old_frame_reg_rtx = frame_reg_rtx;
16582 /* Make r11 point to the start of the SPE save area. We worried about
16583 not clobbering it when we were saving registers in the prologue.
16584 There's no need to worry here because the static chain is passed
16585 anew to every function. */
16586 if (frame_reg_rtx == sp_reg_rtx)
16587 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16588 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
16589 GEN_INT (info->spe_gp_save_offset + sp_offset)));
16590 /* Keep the invariant that frame_reg_rtx + sp_offset points
16591 at the top of the stack frame. */
16592 sp_offset = -info->spe_gp_save_offset;
16597 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16598 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16600 rtx offset, addr, mem;
16602 /* We're doing all this to ensure that the immediate offset
16603 fits into the immediate field of 'evldd'. */
16604 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
16606 offset = GEN_INT (spe_offset + reg_size * i);
16607 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
16608 mem = gen_rtx_MEM (V2SImode, addr);
16610 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
16615 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16616 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16618 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16619 GEN_INT (info->gp_save_offset
16622 rtx mem = gen_frame_mem (reg_mode, addr);
16624 emit_move_insn (gen_rtx_REG (reg_mode,
16625 info->first_gp_reg_save + i), mem);
16628 /* Restore fpr's if we need to do it without calling a function. */
16629 if (restoring_FPRs_inline)
16630 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16631 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
16632 && ! call_used_regs[info->first_fp_reg_save+i]))
16635 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16636 GEN_INT (info->fp_save_offset
16639 mem = gen_frame_mem (DFmode, addr);
16641 emit_move_insn (gen_rtx_REG (DFmode,
16642 info->first_fp_reg_save + i),
16646 /* If we saved cr, restore it here. Just those that were used. */
16647 if (info->cr_save_p)
16649 rtx r12_rtx = gen_rtx_REG (SImode, 12);
16652 if (using_mtcr_multiple)
16654 for (i = 0; i < 8; i++)
16655 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16657 gcc_assert (count);
16660 if (using_mtcr_multiple && count > 1)
16665 p = rtvec_alloc (count);
16668 for (i = 0; i < 8; i++)
16669 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16671 rtvec r = rtvec_alloc (2);
16672 RTVEC_ELT (r, 0) = r12_rtx;
16673 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
16674 RTVEC_ELT (p, ndx) =
16675 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
16676 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
16679 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16680 gcc_assert (ndx == count);
16683 for (i = 0; i < 8; i++)
16684 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16686 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
16692 /* If this is V.4, unwind the stack pointer after all of the loads
16694 if (frame_reg_rtx != sp_reg_rtx)
16696 /* This blockage is needed so that sched doesn't decide to move
16697 the sp change before the register restores. */
16698 rs6000_emit_stack_tie ();
16699 if (sp_offset != 0)
16700 emit_insn (gen_addsi3 (sp_reg_rtx, frame_reg_rtx,
16701 GEN_INT (sp_offset)));
16703 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
16705 else if (sp_offset != 0)
16706 emit_insn (TARGET_32BIT
16707 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16708 GEN_INT (sp_offset))
16709 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16710 GEN_INT (sp_offset)));
16712 if (current_function_calls_eh_return)
16714 rtx sa = EH_RETURN_STACKADJ_RTX;
16715 emit_insn (TARGET_32BIT
16716 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
16717 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
16723 if (! restoring_FPRs_inline)
16724 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
16726 p = rtvec_alloc (2);
16728 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
16729 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
16730 gen_rtx_REG (Pmode,
16733 /* If we have to restore more than two FP registers, branch to the
16734 restore function. It will return to our caller. */
16735 if (! restoring_FPRs_inline)
16739 const char *alloc_rname;
16741 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
16742 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
16743 alloc_rname = ggc_strdup (rname);
16744 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
16745 gen_rtx_SYMBOL_REF (Pmode,
16748 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16751 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
16752 GEN_INT (info->fp_save_offset + 8*i));
16753 mem = gen_frame_mem (DFmode, addr);
16755 RTVEC_ELT (p, i+3) =
16756 gen_rtx_SET (VOIDmode,
16757 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
16762 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
16766 /* Write function epilogue. */
16769 rs6000_output_function_epilogue (FILE *file,
16770 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
16772 if (! HAVE_epilogue)
16774 rtx insn = get_last_insn ();
16775 /* If the last insn was a BARRIER, we don't have to write anything except
16776 the trace table. */
16777 if (GET_CODE (insn) == NOTE)
16778 insn = prev_nonnote_insn (insn);
16779 if (insn == 0 || GET_CODE (insn) != BARRIER)
16781 /* This is slightly ugly, but at least we don't have two
16782 copies of the epilogue-emitting code. */
16785 /* A NOTE_INSN_DELETED is supposed to be at the start
16786 and end of the "toplevel" insn chain. */
16787 emit_note (NOTE_INSN_DELETED);
16788 rs6000_emit_epilogue (FALSE);
16789 emit_note (NOTE_INSN_DELETED);
16791 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16795 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16797 INSN_ADDRESSES_NEW (insn, addr);
16802 if (TARGET_DEBUG_STACK)
16803 debug_rtx_list (get_insns (), 100);
16804 final (get_insns (), file, FALSE);
16810 macho_branch_islands ();
16811 /* Mach-O doesn't support labels at the end of objects, so if
16812 it looks like we might want one, insert a NOP. */
16814 rtx insn = get_last_insn ();
16817 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
16818 insn = PREV_INSN (insn);
16822 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
16823 fputs ("\tnop\n", file);
16827 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16830 We don't output a traceback table if -finhibit-size-directive was
16831 used. The documentation for -finhibit-size-directive reads
16832 ``don't output a @code{.size} assembler directive, or anything
16833 else that would cause trouble if the function is split in the
16834 middle, and the two halves are placed at locations far apart in
16835 memory.'' The traceback table has this property, since it
16836 includes the offset from the start of the function to the
16837 traceback table itself.
16839 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16840 different traceback table. */
16841 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
16842 && rs6000_traceback != traceback_none && !current_function_is_thunk)
16844 const char *fname = NULL;
16845 const char *language_string = lang_hooks.name;
16846 int fixed_parms = 0, float_parms = 0, parm_info = 0;
16848 int optional_tbtab;
16849 rs6000_stack_t *info = rs6000_stack_info ();
16851 if (rs6000_traceback == traceback_full)
16852 optional_tbtab = 1;
16853 else if (rs6000_traceback == traceback_part)
16854 optional_tbtab = 0;
16856 optional_tbtab = !optimize_size && !TARGET_ELF;
16858 if (optional_tbtab)
16860 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
16861 while (*fname == '.') /* V.4 encodes . in the name */
16864 /* Need label immediately before tbtab, so we can compute
16865 its offset from the function start. */
16866 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16867 ASM_OUTPUT_LABEL (file, fname);
16870 /* The .tbtab pseudo-op can only be used for the first eight
16871 expressions, since it can't handle the possibly variable
16872 length fields that follow. However, if you omit the optional
16873 fields, the assembler outputs zeros for all optional fields
16874 anyways, giving each variable length field is minimum length
16875 (as defined in sys/debug.h). Thus we can not use the .tbtab
16876 pseudo-op at all. */
16878 /* An all-zero word flags the start of the tbtab, for debuggers
16879 that have to find it by searching forward from the entry
16880 point or from the current pc. */
16881 fputs ("\t.long 0\n", file);
16883 /* Tbtab format type. Use format type 0. */
16884 fputs ("\t.byte 0,", file);
16886 /* Language type. Unfortunately, there does not seem to be any
16887 official way to discover the language being compiled, so we
16888 use language_string.
16889 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16890 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16891 a number, so for now use 9. */
16892 if (! strcmp (language_string, "GNU C"))
16894 else if (! strcmp (language_string, "GNU F77")
16895 || ! strcmp (language_string, "GNU F95"))
16897 else if (! strcmp (language_string, "GNU Pascal"))
16899 else if (! strcmp (language_string, "GNU Ada"))
16901 else if (! strcmp (language_string, "GNU C++")
16902 || ! strcmp (language_string, "GNU Objective-C++"))
16904 else if (! strcmp (language_string, "GNU Java"))
16906 else if (! strcmp (language_string, "GNU Objective-C"))
16909 gcc_unreachable ();
16910 fprintf (file, "%d,", i);
16912 /* 8 single bit fields: global linkage (not set for C extern linkage,
16913 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16914 from start of procedure stored in tbtab, internal function, function
16915 has controlled storage, function has no toc, function uses fp,
16916 function logs/aborts fp operations. */
16917 /* Assume that fp operations are used if any fp reg must be saved. */
16918 fprintf (file, "%d,",
16919 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16921 /* 6 bitfields: function is interrupt handler, name present in
16922 proc table, function calls alloca, on condition directives
16923 (controls stack walks, 3 bits), saves condition reg, saves
16925 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16926 set up as a frame pointer, even when there is no alloca call. */
16927 fprintf (file, "%d,",
16928 ((optional_tbtab << 6)
16929 | ((optional_tbtab & frame_pointer_needed) << 5)
16930 | (info->cr_save_p << 1)
16931 | (info->lr_save_p)));
16933 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16935 fprintf (file, "%d,",
16936 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16938 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16939 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16941 if (optional_tbtab)
16943 /* Compute the parameter info from the function decl argument
16946 int next_parm_info_bit = 31;
16948 for (decl = DECL_ARGUMENTS (current_function_decl);
16949 decl; decl = TREE_CHAIN (decl))
16951 rtx parameter = DECL_INCOMING_RTL (decl);
16952 enum machine_mode mode = GET_MODE (parameter);
16954 if (GET_CODE (parameter) == REG)
16956 if (SCALAR_FLOAT_MODE_P (mode))
16977 gcc_unreachable ();
16980 /* If only one bit will fit, don't or in this entry. */
16981 if (next_parm_info_bit > 0)
16982 parm_info |= (bits << (next_parm_info_bit - 1));
16983 next_parm_info_bit -= 2;
16987 fixed_parms += ((GET_MODE_SIZE (mode)
16988 + (UNITS_PER_WORD - 1))
16990 next_parm_info_bit -= 1;
16996 /* Number of fixed point parameters. */
16997 /* This is actually the number of words of fixed point parameters; thus
16998 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16999 fprintf (file, "%d,", fixed_parms);
17001 /* 2 bitfields: number of floating point parameters (7 bits), parameters
17003 /* This is actually the number of fp registers that hold parameters;
17004 and thus the maximum value is 13. */
17005 /* Set parameters on stack bit if parameters are not in their original
17006 registers, regardless of whether they are on the stack? Xlc
17007 seems to set the bit when not optimizing. */
17008 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
17010 if (! optional_tbtab)
17013 /* Optional fields follow. Some are variable length. */
17015 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
17016 11 double float. */
17017 /* There is an entry for each parameter in a register, in the order that
17018 they occur in the parameter list. Any intervening arguments on the
17019 stack are ignored. If the list overflows a long (max possible length
17020 34 bits) then completely leave off all elements that don't fit. */
17021 /* Only emit this long if there was at least one parameter. */
17022 if (fixed_parms || float_parms)
17023 fprintf (file, "\t.long %d\n", parm_info);
17025 /* Offset from start of code to tb table. */
17026 fputs ("\t.long ", file);
17027 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
17029 RS6000_OUTPUT_BASENAME (file, fname);
17031 assemble_name (file, fname);
17033 rs6000_output_function_entry (file, fname);
17036 /* Interrupt handler mask. */
17037 /* Omit this long, since we never set the interrupt handler bit
17040 /* Number of CTL (controlled storage) anchors. */
17041 /* Omit this long, since the has_ctl bit is never set above. */
17043 /* Displacement into stack of each CTL anchor. */
17044 /* Omit this list of longs, because there are no CTL anchors. */
17046 /* Length of function name. */
17049 fprintf (file, "\t.short %d\n", (int) strlen (fname));
17051 /* Function name. */
17052 assemble_string (fname, strlen (fname));
17054 /* Register for alloca automatic storage; this is always reg 31.
17055 Only emit this if the alloca bit was set above. */
17056 if (frame_pointer_needed)
17057 fputs ("\t.byte 31\n", file);
17059 fputs ("\t.align 2\n", file);
17063 /* A C compound statement that outputs the assembler code for a thunk
17064 function, used to implement C++ virtual function calls with
17065 multiple inheritance. The thunk acts as a wrapper around a virtual
17066 function, adjusting the implicit object parameter before handing
17067 control off to the real function.
17069 First, emit code to add the integer DELTA to the location that
17070 contains the incoming first argument. Assume that this argument
17071 contains a pointer, and is the one used to pass the `this' pointer
17072 in C++. This is the incoming argument *before* the function
17073 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17074 values of all other incoming arguments.
17076 After the addition, emit code to jump to FUNCTION, which is a
17077 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17078 not touch the return address. Hence returning from FUNCTION will
17079 return to whoever called the current `thunk'.
17081 The effect must be as if FUNCTION had been called directly with the
17082 adjusted first argument. This macro is responsible for emitting
17083 all of the code for a thunk function; output_function_prologue()
17084 and output_function_epilogue() are not invoked.
17086 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17087 been extracted from it.) It might possibly be useful on some
17088 targets, but probably not.
17090 If you do not define this macro, the target-independent code in the
17091 C++ frontend will generate a less efficient heavyweight thunk that
17092 calls FUNCTION instead of jumping to it. The generic approach does
17093 not support varargs. */
17096 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
17097 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
17100 rtx this, insn, funexp;
17102 reload_completed = 1;
17103 epilogue_completed = 1;
17105 /* Mark the end of the (empty) prologue. */
17106 emit_note (NOTE_INSN_PROLOGUE_END);
17108 /* Find the "this" pointer. If the function returns a structure,
17109 the structure return pointer is in r3. */
17110 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
17111 this = gen_rtx_REG (Pmode, 4);
17113 this = gen_rtx_REG (Pmode, 3);
17115 /* Apply the constant offset, if required. */
17118 rtx delta_rtx = GEN_INT (delta);
17119 emit_insn (TARGET_32BIT
17120 ? gen_addsi3 (this, this, delta_rtx)
17121 : gen_adddi3 (this, this, delta_rtx));
17124 /* Apply the offset from the vtable, if required. */
17127 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
17128 rtx tmp = gen_rtx_REG (Pmode, 12);
17130 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
17131 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
17133 emit_insn (TARGET_32BIT
17134 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
17135 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
17136 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
17140 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
17142 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
17144 emit_insn (TARGET_32BIT
17145 ? gen_addsi3 (this, this, tmp)
17146 : gen_adddi3 (this, this, tmp));
17149 /* Generate a tail call to the target function. */
17150 if (!TREE_USED (function))
17152 assemble_external (function);
17153 TREE_USED (function) = 1;
17155 funexp = XEXP (DECL_RTL (function), 0);
17156 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
17159 if (MACHOPIC_INDIRECT)
17160 funexp = machopic_indirect_call_target (funexp);
17163 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17164 generate sibcall RTL explicitly. */
17165 insn = emit_call_insn (
17166 gen_rtx_PARALLEL (VOIDmode,
17168 gen_rtx_CALL (VOIDmode,
17169 funexp, const0_rtx),
17170 gen_rtx_USE (VOIDmode, const0_rtx),
17171 gen_rtx_USE (VOIDmode,
17172 gen_rtx_REG (SImode,
17174 gen_rtx_RETURN (VOIDmode))));
17175 SIBLING_CALL_P (insn) = 1;
17178 /* Run just enough of rest_of_compilation to get the insns emitted.
17179 There's not really enough bulk here to make other passes such as
17180 instruction scheduling worth while. Note that use_thunk calls
17181 assemble_start_function and assemble_end_function. */
17182 insn = get_insns ();
17183 insn_locators_alloc ();
17184 shorten_branches (insn);
17185 final_start_function (insn, file, 1);
17186 final (insn, file, 1);
17187 final_end_function ();
17189 reload_completed = 0;
17190 epilogue_completed = 0;
17193 /* A quick summary of the various types of 'constant-pool tables'
17196 Target Flags Name One table per
17197 AIX (none) AIX TOC object file
17198 AIX -mfull-toc AIX TOC object file
17199 AIX -mminimal-toc AIX minimal TOC translation unit
17200 SVR4/EABI (none) SVR4 SDATA object file
17201 SVR4/EABI -fpic SVR4 pic object file
17202 SVR4/EABI -fPIC SVR4 PIC translation unit
17203 SVR4/EABI -mrelocatable EABI TOC function
17204 SVR4/EABI -maix AIX TOC object file
17205 SVR4/EABI -maix -mminimal-toc
17206 AIX minimal TOC translation unit
17208 Name Reg. Set by entries contains:
17209 made by addrs? fp? sum?
17211 AIX TOC 2 crt0 as Y option option
17212 AIX minimal TOC 30 prolog gcc Y Y option
17213 SVR4 SDATA 13 crt0 gcc N Y N
17214 SVR4 pic 30 prolog ld Y not yet N
17215 SVR4 PIC 30 prolog gcc Y option option
17216 EABI TOC 30 prolog gcc Y option option
17220 /* Hash functions for the hash table. */
17223 rs6000_hash_constant (rtx k)
17225 enum rtx_code code = GET_CODE (k);
17226 enum machine_mode mode = GET_MODE (k);
17227 unsigned result = (code << 3) ^ mode;
17228 const char *format;
17231 format = GET_RTX_FORMAT (code);
17232 flen = strlen (format);
17238 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
17241 if (mode != VOIDmode)
17242 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
17254 for (; fidx < flen; fidx++)
17255 switch (format[fidx])
17260 const char *str = XSTR (k, fidx);
17261 len = strlen (str);
17262 result = result * 613 + len;
17263 for (i = 0; i < len; i++)
17264 result = result * 613 + (unsigned) str[i];
17269 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
17273 result = result * 613 + (unsigned) XINT (k, fidx);
17276 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
17277 result = result * 613 + (unsigned) XWINT (k, fidx);
17281 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
17282 result = result * 613 + (unsigned) (XWINT (k, fidx)
17289 gcc_unreachable ();
17296 toc_hash_function (const void *hash_entry)
17298 const struct toc_hash_struct *thc =
17299 (const struct toc_hash_struct *) hash_entry;
17300 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
17303 /* Compare H1 and H2 for equivalence. */
17306 toc_hash_eq (const void *h1, const void *h2)
17308 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
17309 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
17311 if (((const struct toc_hash_struct *) h1)->key_mode
17312 != ((const struct toc_hash_struct *) h2)->key_mode)
17315 return rtx_equal_p (r1, r2);
17318 /* These are the names given by the C++ front-end to vtables, and
17319 vtable-like objects. Ideally, this logic should not be here;
17320 instead, there should be some programmatic way of inquiring as
17321 to whether or not an object is a vtable. */
17323 #define VTABLE_NAME_P(NAME) \
17324 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
17325 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
17326 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
17327 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
17328 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
17331 rs6000_output_symbol_ref (FILE *file, rtx x)
17333 /* Currently C++ toc references to vtables can be emitted before it
17334 is decided whether the vtable is public or private. If this is
17335 the case, then the linker will eventually complain that there is
17336 a reference to an unknown section. Thus, for vtables only,
17337 we emit the TOC reference to reference the symbol and not the
17339 const char *name = XSTR (x, 0);
17341 if (VTABLE_NAME_P (name))
17343 RS6000_OUTPUT_BASENAME (file, name);
17346 assemble_name (file, name);
17349 /* Output a TOC entry. We derive the entry name from what is being
17353 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
17356 const char *name = buf;
17357 const char *real_name;
17359 HOST_WIDE_INT offset = 0;
17361 gcc_assert (!TARGET_NO_TOC);
17363 /* When the linker won't eliminate them, don't output duplicate
17364 TOC entries (this happens on AIX if there is any kind of TOC,
17365 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
17367 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
17369 struct toc_hash_struct *h;
17372 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
17373 time because GGC is not initialized at that point. */
17374 if (toc_hash_table == NULL)
17375 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17376 toc_hash_eq, NULL);
17378 h = ggc_alloc (sizeof (*h));
17380 h->key_mode = mode;
17381 h->labelno = labelno;
17383 found = htab_find_slot (toc_hash_table, h, 1);
17384 if (*found == NULL)
17386 else /* This is indeed a duplicate.
17387 Set this label equal to that label. */
17389 fputs ("\t.set ", file);
17390 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17391 fprintf (file, "%d,", labelno);
17392 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17393 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
17399 /* If we're going to put a double constant in the TOC, make sure it's
17400 aligned properly when strict alignment is on. */
17401 if (GET_CODE (x) == CONST_DOUBLE
17402 && STRICT_ALIGNMENT
17403 && GET_MODE_BITSIZE (mode) >= 64
17404 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
17405 ASM_OUTPUT_ALIGN (file, 3);
17408 (*targetm.asm_out.internal_label) (file, "LC", labelno);
17410 /* Handle FP constants specially. Note that if we have a minimal
17411 TOC, things we put here aren't actually in the TOC, so we can allow
17413 if (GET_CODE (x) == CONST_DOUBLE &&
17414 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
17416 REAL_VALUE_TYPE rv;
17419 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17420 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17421 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
17423 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
17427 if (TARGET_MINIMAL_TOC)
17428 fputs (DOUBLE_INT_ASM_OP, file);
17430 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17431 k[0] & 0xffffffff, k[1] & 0xffffffff,
17432 k[2] & 0xffffffff, k[3] & 0xffffffff);
17433 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
17434 k[0] & 0xffffffff, k[1] & 0xffffffff,
17435 k[2] & 0xffffffff, k[3] & 0xffffffff);
17440 if (TARGET_MINIMAL_TOC)
17441 fputs ("\t.long ", file);
17443 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17444 k[0] & 0xffffffff, k[1] & 0xffffffff,
17445 k[2] & 0xffffffff, k[3] & 0xffffffff);
17446 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17447 k[0] & 0xffffffff, k[1] & 0xffffffff,
17448 k[2] & 0xffffffff, k[3] & 0xffffffff);
17452 else if (GET_CODE (x) == CONST_DOUBLE &&
17453 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
17455 REAL_VALUE_TYPE rv;
17458 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17460 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17461 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
17463 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
17467 if (TARGET_MINIMAL_TOC)
17468 fputs (DOUBLE_INT_ASM_OP, file);
17470 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17471 k[0] & 0xffffffff, k[1] & 0xffffffff);
17472 fprintf (file, "0x%lx%08lx\n",
17473 k[0] & 0xffffffff, k[1] & 0xffffffff);
17478 if (TARGET_MINIMAL_TOC)
17479 fputs ("\t.long ", file);
17481 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17482 k[0] & 0xffffffff, k[1] & 0xffffffff);
17483 fprintf (file, "0x%lx,0x%lx\n",
17484 k[0] & 0xffffffff, k[1] & 0xffffffff);
17488 else if (GET_CODE (x) == CONST_DOUBLE &&
17489 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
17491 REAL_VALUE_TYPE rv;
17494 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17495 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17496 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
17498 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
17502 if (TARGET_MINIMAL_TOC)
17503 fputs (DOUBLE_INT_ASM_OP, file);
17505 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17506 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
17511 if (TARGET_MINIMAL_TOC)
17512 fputs ("\t.long ", file);
17514 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17515 fprintf (file, "0x%lx\n", l & 0xffffffff);
17519 else if (GET_MODE (x) == VOIDmode
17520 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
17522 unsigned HOST_WIDE_INT low;
17523 HOST_WIDE_INT high;
17525 if (GET_CODE (x) == CONST_DOUBLE)
17527 low = CONST_DOUBLE_LOW (x);
17528 high = CONST_DOUBLE_HIGH (x);
17531 #if HOST_BITS_PER_WIDE_INT == 32
17534 high = (low & 0x80000000) ? ~0 : 0;
17538 low = INTVAL (x) & 0xffffffff;
17539 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
17543 /* TOC entries are always Pmode-sized, but since this
17544 is a bigendian machine then if we're putting smaller
17545 integer constants in the TOC we have to pad them.
17546 (This is still a win over putting the constants in
17547 a separate constant pool, because then we'd have
17548 to have both a TOC entry _and_ the actual constant.)
17550 For a 32-bit target, CONST_INT values are loaded and shifted
17551 entirely within `low' and can be stored in one TOC entry. */
17553 /* It would be easy to make this work, but it doesn't now. */
17554 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
17556 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
17558 #if HOST_BITS_PER_WIDE_INT == 32
17559 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
17560 POINTER_SIZE, &low, &high, 0);
17563 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
17564 high = (HOST_WIDE_INT) low >> 32;
17571 if (TARGET_MINIMAL_TOC)
17572 fputs (DOUBLE_INT_ASM_OP, file);
17574 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
17575 (long) high & 0xffffffff, (long) low & 0xffffffff);
17576 fprintf (file, "0x%lx%08lx\n",
17577 (long) high & 0xffffffff, (long) low & 0xffffffff);
17582 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
17584 if (TARGET_MINIMAL_TOC)
17585 fputs ("\t.long ", file);
17587 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
17588 (long) high & 0xffffffff, (long) low & 0xffffffff);
17589 fprintf (file, "0x%lx,0x%lx\n",
17590 (long) high & 0xffffffff, (long) low & 0xffffffff);
17594 if (TARGET_MINIMAL_TOC)
17595 fputs ("\t.long ", file);
17597 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
17598 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
17604 if (GET_CODE (x) == CONST)
17606 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
17608 base = XEXP (XEXP (x, 0), 0);
17609 offset = INTVAL (XEXP (XEXP (x, 0), 1));
17612 switch (GET_CODE (base))
17615 name = XSTR (base, 0);
17619 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
17620 CODE_LABEL_NUMBER (XEXP (base, 0)));
17624 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
17628 gcc_unreachable ();
17631 real_name = (*targetm.strip_name_encoding) (name);
17632 if (TARGET_MINIMAL_TOC)
17633 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
17636 fprintf (file, "\t.tc %s", real_name);
17639 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
17641 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
17643 fputs ("[TC],", file);
17646 /* Currently C++ toc references to vtables can be emitted before it
17647 is decided whether the vtable is public or private. If this is
17648 the case, then the linker will eventually complain that there is
17649 a TOC reference to an unknown section. Thus, for vtables only,
17650 we emit the TOC reference to reference the symbol and not the
17652 if (VTABLE_NAME_P (name))
17654 RS6000_OUTPUT_BASENAME (file, name);
17656 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
17657 else if (offset > 0)
17658 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
17661 output_addr_const (file, x);
17665 /* Output an assembler pseudo-op to write an ASCII string of N characters
17666 starting at P to FILE.
17668 On the RS/6000, we have to do this using the .byte operation and
17669 write out special characters outside the quoted string.
17670 Also, the assembler is broken; very long strings are truncated,
17671 so we must artificially break them up early. */
17674 output_ascii (FILE *file, const char *p, int n)
17677 int i, count_string;
17678 const char *for_string = "\t.byte \"";
17679 const char *for_decimal = "\t.byte ";
17680 const char *to_close = NULL;
17683 for (i = 0; i < n; i++)
17686 if (c >= ' ' && c < 0177)
17689 fputs (for_string, file);
17692 /* Write two quotes to get one. */
17700 for_decimal = "\"\n\t.byte ";
17704 if (count_string >= 512)
17706 fputs (to_close, file);
17708 for_string = "\t.byte \"";
17709 for_decimal = "\t.byte ";
17717 fputs (for_decimal, file);
17718 fprintf (file, "%d", c);
17720 for_string = "\n\t.byte \"";
17721 for_decimal = ", ";
17727 /* Now close the string if we have written one. Then end the line. */
17729 fputs (to_close, file);
17732 /* Generate a unique section name for FILENAME for a section type
17733 represented by SECTION_DESC. Output goes into BUF.
17735 SECTION_DESC can be any string, as long as it is different for each
17736 possible section type.
17738 We name the section in the same manner as xlc. The name begins with an
17739 underscore followed by the filename (after stripping any leading directory
17740 names) with the last period replaced by the string SECTION_DESC. If
17741 FILENAME does not contain a period, SECTION_DESC is appended to the end of
17745 rs6000_gen_section_name (char **buf, const char *filename,
17746 const char *section_desc)
17748 const char *q, *after_last_slash, *last_period = 0;
17752 after_last_slash = filename;
17753 for (q = filename; *q; q++)
17756 after_last_slash = q + 1;
17757 else if (*q == '.')
17761 len = strlen (after_last_slash) + strlen (section_desc) + 2;
17762 *buf = (char *) xmalloc (len);
17767 for (q = after_last_slash; *q; q++)
17769 if (q == last_period)
17771 strcpy (p, section_desc);
17772 p += strlen (section_desc);
17776 else if (ISALNUM (*q))
17780 if (last_period == 0)
17781 strcpy (p, section_desc);
17786 /* Emit profile function. */
17789 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
17791 /* Non-standard profiling for kernels, which just saves LR then calls
17792 _mcount without worrying about arg saves. The idea is to change
17793 the function prologue as little as possible as it isn't easy to
17794 account for arg save/restore code added just for _mcount. */
17795 if (TARGET_PROFILE_KERNEL)
17798 if (DEFAULT_ABI == ABI_AIX)
17800 #ifndef NO_PROFILE_COUNTERS
17801 # define NO_PROFILE_COUNTERS 0
17803 if (NO_PROFILE_COUNTERS)
17804 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
17808 const char *label_name;
17811 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17812 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
17813 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
17815 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
17819 else if (DEFAULT_ABI == ABI_DARWIN)
17821 const char *mcount_name = RS6000_MCOUNT;
17822 int caller_addr_regno = LR_REGNO;
17824 /* Be conservative and always set this, at least for now. */
17825 current_function_uses_pic_offset_table = 1;
17828 /* For PIC code, set up a stub and collect the caller's address
17829 from r0, which is where the prologue puts it. */
17830 if (MACHOPIC_INDIRECT
17831 && current_function_uses_pic_offset_table)
17832 caller_addr_regno = 0;
17834 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
17836 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
17840 /* Write function profiler code. */
17843 output_function_profiler (FILE *file, int labelno)
17847 switch (DEFAULT_ABI)
17850 gcc_unreachable ();
17855 warning (0, "no profiling of 64-bit code for this ABI");
17858 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17859 fprintf (file, "\tmflr %s\n", reg_names[0]);
17860 if (NO_PROFILE_COUNTERS)
17862 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17863 reg_names[0], reg_names[1]);
17865 else if (TARGET_SECURE_PLT && flag_pic)
17867 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17868 reg_names[0], reg_names[1]);
17869 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17870 asm_fprintf (file, "\t{cau|addis} %s,%s,",
17871 reg_names[12], reg_names[12]);
17872 assemble_name (file, buf);
17873 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
17874 assemble_name (file, buf);
17875 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
17877 else if (flag_pic == 1)
17879 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
17880 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17881 reg_names[0], reg_names[1]);
17882 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17883 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
17884 assemble_name (file, buf);
17885 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
17887 else if (flag_pic > 1)
17889 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17890 reg_names[0], reg_names[1]);
17891 /* Now, we need to get the address of the label. */
17892 fputs ("\tbcl 20,31,1f\n\t.long ", file);
17893 assemble_name (file, buf);
17894 fputs ("-.\n1:", file);
17895 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
17896 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
17897 reg_names[0], reg_names[11]);
17898 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
17899 reg_names[0], reg_names[0], reg_names[11]);
17903 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
17904 assemble_name (file, buf);
17905 fputs ("@ha\n", file);
17906 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17907 reg_names[0], reg_names[1]);
17908 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
17909 assemble_name (file, buf);
17910 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
17913 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17914 fprintf (file, "\tbl %s%s\n",
17915 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17920 if (!TARGET_PROFILE_KERNEL)
17922 /* Don't do anything, done in output_profile_hook (). */
17926 gcc_assert (!TARGET_32BIT);
17928 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17929 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17931 if (cfun->static_chain_decl != NULL)
17933 asm_fprintf (file, "\tstd %s,24(%s)\n",
17934 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17935 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17936 asm_fprintf (file, "\tld %s,24(%s)\n",
17937 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17940 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17948 /* The following variable value is the last issued insn. */
17950 static rtx last_scheduled_insn;
17952 /* The following variable helps to balance issuing of load and
17953 store instructions */
17955 static int load_store_pendulum;
17957 /* Power4 load update and store update instructions are cracked into a
17958 load or store and an integer insn which are executed in the same cycle.
17959 Branches have their own dispatch slot which does not count against the
17960 GCC issue rate, but it changes the program flow so there are no other
17961 instructions to issue in this cycle. */
17964 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17965 int verbose ATTRIBUTE_UNUSED,
17966 rtx insn, int more)
17968 last_scheduled_insn = insn;
17969 if (GET_CODE (PATTERN (insn)) == USE
17970 || GET_CODE (PATTERN (insn)) == CLOBBER)
17972 cached_can_issue_more = more;
17973 return cached_can_issue_more;
17976 if (insn_terminates_group_p (insn, current_group))
17978 cached_can_issue_more = 0;
17979 return cached_can_issue_more;
17982 /* If no reservation, but reach here */
17983 if (recog_memoized (insn) < 0)
17986 if (rs6000_sched_groups)
17988 if (is_microcoded_insn (insn))
17989 cached_can_issue_more = 0;
17990 else if (is_cracked_insn (insn))
17991 cached_can_issue_more = more > 2 ? more - 2 : 0;
17993 cached_can_issue_more = more - 1;
17995 return cached_can_issue_more;
17998 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
18001 cached_can_issue_more = more - 1;
18002 return cached_can_issue_more;
18005 /* Adjust the cost of a scheduling dependency. Return the new cost of
18006 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
18009 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
18011 enum attr_type attr_type;
18013 if (! recog_memoized (insn))
18016 switch (REG_NOTE_KIND (link))
18020 /* Data dependency; DEP_INSN writes a register that INSN reads
18021 some cycles later. */
18023 /* Separate a load from a narrower, dependent store. */
18024 if (rs6000_sched_groups
18025 && GET_CODE (PATTERN (insn)) == SET
18026 && GET_CODE (PATTERN (dep_insn)) == SET
18027 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
18028 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
18029 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
18030 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
18033 attr_type = get_attr_type (insn);
18038 /* Tell the first scheduling pass about the latency between
18039 a mtctr and bctr (and mtlr and br/blr). The first
18040 scheduling pass will not know about this latency since
18041 the mtctr instruction, which has the latency associated
18042 to it, will be generated by reload. */
18043 return TARGET_POWER ? 5 : 4;
18045 /* Leave some extra cycles between a compare and its
18046 dependent branch, to inhibit expensive mispredicts. */
18047 if ((rs6000_cpu_attr == CPU_PPC603
18048 || rs6000_cpu_attr == CPU_PPC604
18049 || rs6000_cpu_attr == CPU_PPC604E
18050 || rs6000_cpu_attr == CPU_PPC620
18051 || rs6000_cpu_attr == CPU_PPC630
18052 || rs6000_cpu_attr == CPU_PPC750
18053 || rs6000_cpu_attr == CPU_PPC7400
18054 || rs6000_cpu_attr == CPU_PPC7450
18055 || rs6000_cpu_attr == CPU_POWER4
18056 || rs6000_cpu_attr == CPU_POWER5
18057 || rs6000_cpu_attr == CPU_CELL)
18058 && recog_memoized (dep_insn)
18059 && (INSN_CODE (dep_insn) >= 0))
18061 switch (get_attr_type (dep_insn))
18065 case TYPE_DELAYED_COMPARE:
18066 case TYPE_IMUL_COMPARE:
18067 case TYPE_LMUL_COMPARE:
18068 case TYPE_FPCOMPARE:
18069 case TYPE_CR_LOGICAL:
18070 case TYPE_DELAYED_CR:
18079 case TYPE_STORE_UX:
18081 case TYPE_FPSTORE_U:
18082 case TYPE_FPSTORE_UX:
18083 if ((rs6000_cpu == PROCESSOR_POWER6)
18084 && recog_memoized (dep_insn)
18085 && (INSN_CODE (dep_insn) >= 0))
18088 if (GET_CODE (PATTERN (insn)) != SET)
18089 /* If this happens, we have to extend this to schedule
18090 optimally. Return default for now. */
18093 /* Adjust the cost for the case where the value written
18094 by a fixed point operation is used as the address
18095 gen value on a store. */
18096 switch (get_attr_type (dep_insn))
18103 if (! store_data_bypass_p (dep_insn, insn))
18107 case TYPE_LOAD_EXT:
18108 case TYPE_LOAD_EXT_U:
18109 case TYPE_LOAD_EXT_UX:
18110 case TYPE_VAR_SHIFT_ROTATE:
18111 case TYPE_VAR_DELAYED_COMPARE:
18113 if (! store_data_bypass_p (dep_insn, insn))
18119 case TYPE_FAST_COMPARE:
18122 case TYPE_INSERT_WORD:
18123 case TYPE_INSERT_DWORD:
18124 case TYPE_FPLOAD_U:
18125 case TYPE_FPLOAD_UX:
18127 case TYPE_STORE_UX:
18128 case TYPE_FPSTORE_U:
18129 case TYPE_FPSTORE_UX:
18131 if (! store_data_bypass_p (dep_insn, insn))
18139 case TYPE_IMUL_COMPARE:
18140 case TYPE_LMUL_COMPARE:
18142 if (! store_data_bypass_p (dep_insn, insn))
18148 if (! store_data_bypass_p (dep_insn, insn))
18154 if (! store_data_bypass_p (dep_insn, insn))
18167 case TYPE_LOAD_EXT:
18168 case TYPE_LOAD_EXT_U:
18169 case TYPE_LOAD_EXT_UX:
18170 if ((rs6000_cpu == PROCESSOR_POWER6)
18171 && recog_memoized (dep_insn)
18172 && (INSN_CODE (dep_insn) >= 0))
18175 /* Adjust the cost for the case where the value written
18176 by a fixed point instruction is used within the address
18177 gen portion of a subsequent load(u)(x) */
18178 switch (get_attr_type (dep_insn))
18185 if (set_to_load_agen (dep_insn, insn))
18189 case TYPE_LOAD_EXT:
18190 case TYPE_LOAD_EXT_U:
18191 case TYPE_LOAD_EXT_UX:
18192 case TYPE_VAR_SHIFT_ROTATE:
18193 case TYPE_VAR_DELAYED_COMPARE:
18195 if (set_to_load_agen (dep_insn, insn))
18201 case TYPE_FAST_COMPARE:
18204 case TYPE_INSERT_WORD:
18205 case TYPE_INSERT_DWORD:
18206 case TYPE_FPLOAD_U:
18207 case TYPE_FPLOAD_UX:
18209 case TYPE_STORE_UX:
18210 case TYPE_FPSTORE_U:
18211 case TYPE_FPSTORE_UX:
18213 if (set_to_load_agen (dep_insn, insn))
18221 case TYPE_IMUL_COMPARE:
18222 case TYPE_LMUL_COMPARE:
18224 if (set_to_load_agen (dep_insn, insn))
18230 if (set_to_load_agen (dep_insn, insn))
18236 if (set_to_load_agen (dep_insn, insn))
18247 if ((rs6000_cpu == PROCESSOR_POWER6)
18248 && recog_memoized (dep_insn)
18249 && (INSN_CODE (dep_insn) >= 0)
18250 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
18257 /* Fall out to return default cost. */
18261 case REG_DEP_OUTPUT:
18262 /* Output dependency; DEP_INSN writes a register that INSN writes some
18264 if ((rs6000_cpu == PROCESSOR_POWER6)
18265 && recog_memoized (dep_insn)
18266 && (INSN_CODE (dep_insn) >= 0))
18268 attr_type = get_attr_type (insn);
18273 if (get_attr_type (dep_insn) == TYPE_FP)
18277 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
18285 /* Anti dependency; DEP_INSN reads a register that INSN writes some
18290 gcc_unreachable ();
18296 /* The function returns a true if INSN is microcoded.
18297 Return false otherwise. */
18300 is_microcoded_insn (rtx insn)
18302 if (!insn || !INSN_P (insn)
18303 || GET_CODE (PATTERN (insn)) == USE
18304 || GET_CODE (PATTERN (insn)) == CLOBBER)
18307 if (rs6000_cpu_attr == CPU_CELL)
18308 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
18310 if (rs6000_sched_groups)
18312 enum attr_type type = get_attr_type (insn);
18313 if (type == TYPE_LOAD_EXT_U
18314 || type == TYPE_LOAD_EXT_UX
18315 || type == TYPE_LOAD_UX
18316 || type == TYPE_STORE_UX
18317 || type == TYPE_MFCR)
18324 /* The function returns true if INSN is cracked into 2 instructions
18325 by the processor (and therefore occupies 2 issue slots). */
18328 is_cracked_insn (rtx insn)
18330 if (!insn || !INSN_P (insn)
18331 || GET_CODE (PATTERN (insn)) == USE
18332 || GET_CODE (PATTERN (insn)) == CLOBBER)
18335 if (rs6000_sched_groups)
18337 enum attr_type type = get_attr_type (insn);
18338 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
18339 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
18340 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
18341 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
18342 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
18343 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
18344 || type == TYPE_IDIV || type == TYPE_LDIV
18345 || type == TYPE_INSERT_WORD)
18352 /* The function returns true if INSN can be issued only from
18353 the branch slot. */
18356 is_branch_slot_insn (rtx insn)
18358 if (!insn || !INSN_P (insn)
18359 || GET_CODE (PATTERN (insn)) == USE
18360 || GET_CODE (PATTERN (insn)) == CLOBBER)
18363 if (rs6000_sched_groups)
18365 enum attr_type type = get_attr_type (insn);
18366 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
18374 /* The function returns true if out_inst sets a value that is
18375 used in the address generation computation of in_insn */
18377 set_to_load_agen (rtx out_insn, rtx in_insn)
18379 rtx out_set, in_set;
18381 /* For performance reasons, only handle the simple case where
18382 both loads are a single_set. */
18383 out_set = single_set (out_insn);
18386 in_set = single_set (in_insn);
18388 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
18394 /* The function returns true if the target storage location of
18395 out_insn is adjacent to the target storage location of in_insn */
18396 /* Return 1 if memory locations are adjacent. */
18399 adjacent_mem_locations (rtx insn1, rtx insn2)
18402 rtx a = get_store_dest (PATTERN (insn1));
18403 rtx b = get_store_dest (PATTERN (insn2));
18405 if ((GET_CODE (XEXP (a, 0)) == REG
18406 || (GET_CODE (XEXP (a, 0)) == PLUS
18407 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
18408 && (GET_CODE (XEXP (b, 0)) == REG
18409 || (GET_CODE (XEXP (b, 0)) == PLUS
18410 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
18412 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
18415 if (GET_CODE (XEXP (a, 0)) == PLUS)
18417 reg0 = XEXP (XEXP (a, 0), 0);
18418 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
18421 reg0 = XEXP (a, 0);
18423 if (GET_CODE (XEXP (b, 0)) == PLUS)
18425 reg1 = XEXP (XEXP (b, 0), 0);
18426 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
18429 reg1 = XEXP (b, 0);
18431 val_diff = val1 - val0;
18433 return ((REGNO (reg0) == REGNO (reg1))
18434 && ((MEM_SIZE (a) && val_diff == INTVAL (MEM_SIZE (a)))
18435 || (MEM_SIZE (b) && val_diff == -INTVAL (MEM_SIZE (b)))));
18441 /* A C statement (sans semicolon) to update the integer scheduling
18442 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18443 INSN earlier, reduce the priority to execute INSN later. Do not
18444 define this macro if you do not need to adjust the scheduling
18445 priorities of insns. */
18448 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
18450 /* On machines (like the 750) which have asymmetric integer units,
18451 where one integer unit can do multiply and divides and the other
18452 can't, reduce the priority of multiply/divide so it is scheduled
18453 before other integer operations. */
18456 if (! INSN_P (insn))
18459 if (GET_CODE (PATTERN (insn)) == USE)
18462 switch (rs6000_cpu_attr) {
18464 switch (get_attr_type (insn))
18471 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
18472 priority, priority);
18473 if (priority >= 0 && priority < 0x01000000)
18480 if (insn_must_be_first_in_group (insn)
18481 && reload_completed
18482 && current_sched_info->sched_max_insns_priority
18483 && rs6000_sched_restricted_insns_priority)
18486 /* Prioritize insns that can be dispatched only in the first
18488 if (rs6000_sched_restricted_insns_priority == 1)
18489 /* Attach highest priority to insn. This means that in
18490 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18491 precede 'priority' (critical path) considerations. */
18492 return current_sched_info->sched_max_insns_priority;
18493 else if (rs6000_sched_restricted_insns_priority == 2)
18494 /* Increase priority of insn by a minimal amount. This means that in
18495 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18496 considerations precede dispatch-slot restriction considerations. */
18497 return (priority + 1);
18500 if (rs6000_cpu == PROCESSOR_POWER6
18501 && ((load_store_pendulum == -2 && is_load_insn (insn))
18502 || (load_store_pendulum == 2 && is_store_insn (insn))))
18503 /* Attach highest priority to insn if the scheduler has just issued two
18504 stores and this instruction is a load, or two loads and this instruction
18505 is a store. Power6 wants loads and stores scheduled alternately
18507 return current_sched_info->sched_max_insns_priority;
18512 /* Return true if the instruction is nonpipelined on the Cell. */
18514 is_nonpipeline_insn (rtx insn)
18516 enum attr_type type;
18517 if (!insn || !INSN_P (insn)
18518 || GET_CODE (PATTERN (insn)) == USE
18519 || GET_CODE (PATTERN (insn)) == CLOBBER)
18522 type = get_attr_type (insn);
18523 if (type == TYPE_IMUL
18524 || type == TYPE_IMUL2
18525 || type == TYPE_IMUL3
18526 || type == TYPE_LMUL
18527 || type == TYPE_IDIV
18528 || type == TYPE_LDIV
18529 || type == TYPE_SDIV
18530 || type == TYPE_DDIV
18531 || type == TYPE_SSQRT
18532 || type == TYPE_DSQRT
18533 || type == TYPE_MFCR
18534 || type == TYPE_MFCRF
18535 || type == TYPE_MFJMPR)
18543 /* Return how many instructions the machine can issue per cycle. */
18546 rs6000_issue_rate (void)
18548 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
18549 if (!reload_completed)
18552 switch (rs6000_cpu_attr) {
18553 case CPU_RIOS1: /* ? */
18555 case CPU_PPC601: /* ? */
18564 case CPU_PPCE300C2:
18565 case CPU_PPCE300C3:
18582 /* Return how many instructions to look ahead for better insn
18586 rs6000_use_sched_lookahead (void)
18588 if (rs6000_cpu_attr == CPU_PPC8540)
18590 if (rs6000_cpu_attr == CPU_CELL)
18591 return (reload_completed ? 8 : 0);
18595 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
18597 rs6000_use_sched_lookahead_guard (rtx insn)
18599 if (rs6000_cpu_attr != CPU_CELL)
18602 if (insn == NULL_RTX || !INSN_P (insn))
18605 if (!reload_completed
18606 || is_nonpipeline_insn (insn)
18607 || is_microcoded_insn (insn))
18613 /* Determine is PAT refers to memory. */
18616 is_mem_ref (rtx pat)
18622 /* stack_tie does not produce any real memory traffic. */
18623 if (GET_CODE (pat) == UNSPEC
18624 && XINT (pat, 1) == UNSPEC_TIE)
18627 if (GET_CODE (pat) == MEM)
18630 /* Recursively process the pattern. */
18631 fmt = GET_RTX_FORMAT (GET_CODE (pat));
18633 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
18636 ret |= is_mem_ref (XEXP (pat, i));
18637 else if (fmt[i] == 'E')
18638 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
18639 ret |= is_mem_ref (XVECEXP (pat, i, j));
18645 /* Determine if PAT is a PATTERN of a load insn. */
18648 is_load_insn1 (rtx pat)
18650 if (!pat || pat == NULL_RTX)
18653 if (GET_CODE (pat) == SET)
18654 return is_mem_ref (SET_SRC (pat));
18656 if (GET_CODE (pat) == PARALLEL)
18660 for (i = 0; i < XVECLEN (pat, 0); i++)
18661 if (is_load_insn1 (XVECEXP (pat, 0, i)))
18668 /* Determine if INSN loads from memory. */
18671 is_load_insn (rtx insn)
18673 if (!insn || !INSN_P (insn))
18676 if (GET_CODE (insn) == CALL_INSN)
18679 return is_load_insn1 (PATTERN (insn));
18682 /* Determine if PAT is a PATTERN of a store insn. */
18685 is_store_insn1 (rtx pat)
18687 if (!pat || pat == NULL_RTX)
18690 if (GET_CODE (pat) == SET)
18691 return is_mem_ref (SET_DEST (pat));
18693 if (GET_CODE (pat) == PARALLEL)
18697 for (i = 0; i < XVECLEN (pat, 0); i++)
18698 if (is_store_insn1 (XVECEXP (pat, 0, i)))
18705 /* Determine if INSN stores to memory. */
18708 is_store_insn (rtx insn)
18710 if (!insn || !INSN_P (insn))
18713 return is_store_insn1 (PATTERN (insn));
18716 /* Return the dest of a store insn. */
18719 get_store_dest (rtx pat)
18721 gcc_assert (is_store_insn1 (pat));
18723 if (GET_CODE (pat) == SET)
18724 return SET_DEST (pat);
18725 else if (GET_CODE (pat) == PARALLEL)
18729 for (i = 0; i < XVECLEN (pat, 0); i++)
18731 rtx inner_pat = XVECEXP (pat, 0, i);
18732 if (GET_CODE (inner_pat) == SET
18733 && is_mem_ref (SET_DEST (inner_pat)))
18737 /* We shouldn't get here, because we should have either a simple
18738 store insn or a store with update which are covered above. */
18742 /* Returns whether the dependence between INSN and NEXT is considered
18743 costly by the given target. */
18746 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
18751 /* If the flag is not enabled - no dependence is considered costly;
18752 allow all dependent insns in the same group.
18753 This is the most aggressive option. */
18754 if (rs6000_sched_costly_dep == no_dep_costly)
18757 /* If the flag is set to 1 - a dependence is always considered costly;
18758 do not allow dependent instructions in the same group.
18759 This is the most conservative option. */
18760 if (rs6000_sched_costly_dep == all_deps_costly)
18763 insn = DEP_PRO (dep);
18764 next = DEP_CON (dep);
18766 if (rs6000_sched_costly_dep == store_to_load_dep_costly
18767 && is_load_insn (next)
18768 && is_store_insn (insn))
18769 /* Prevent load after store in the same group. */
18772 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
18773 && is_load_insn (next)
18774 && is_store_insn (insn)
18775 && DEP_TYPE (dep) == REG_DEP_TRUE)
18776 /* Prevent load after store in the same group if it is a true
18780 /* The flag is set to X; dependences with latency >= X are considered costly,
18781 and will not be scheduled in the same group. */
18782 if (rs6000_sched_costly_dep <= max_dep_latency
18783 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
18789 /* Return the next insn after INSN that is found before TAIL is reached,
18790 skipping any "non-active" insns - insns that will not actually occupy
18791 an issue slot. Return NULL_RTX if such an insn is not found. */
18794 get_next_active_insn (rtx insn, rtx tail)
18796 if (insn == NULL_RTX || insn == tail)
18801 insn = NEXT_INSN (insn);
18802 if (insn == NULL_RTX || insn == tail)
18807 || (NONJUMP_INSN_P (insn)
18808 && GET_CODE (PATTERN (insn)) != USE
18809 && GET_CODE (PATTERN (insn)) != CLOBBER
18810 && INSN_CODE (insn) != CODE_FOR_stack_tie))
18816 /* We are about to begin issuing insns for this clock cycle. */
18819 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
18820 rtx *ready ATTRIBUTE_UNUSED,
18821 int *pn_ready ATTRIBUTE_UNUSED,
18822 int clock_var ATTRIBUTE_UNUSED)
18824 int n_ready = *pn_ready;
18827 fprintf (dump, "// rs6000_sched_reorder :\n");
18829 /* Reorder the ready list, if the second to last ready insn
18830 is a nonepipeline insn. */
18831 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
18833 if (is_nonpipeline_insn (ready[n_ready - 1])
18834 && (recog_memoized (ready[n_ready - 2]) > 0))
18835 /* Simply swap first two insns. */
18837 rtx tmp = ready[n_ready - 1];
18838 ready[n_ready - 1] = ready[n_ready - 2];
18839 ready[n_ready - 2] = tmp;
18843 if (rs6000_cpu == PROCESSOR_POWER6)
18844 load_store_pendulum = 0;
18846 return rs6000_issue_rate ();
18849 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18852 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
18853 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
18856 fprintf (dump, "// rs6000_sched_reorder2 :\n");
18858 /* For Power6, we need to handle some special cases to try and keep the
18859 store queue from overflowing and triggering expensive flushes.
18861 This code monitors how load and store instructions are being issued
18862 and skews the ready list one way or the other to increase the likelihood
18863 that a desired instruction is issued at the proper time.
18865 A couple of things are done. First, we maintain a "load_store_pendulum"
18866 to track the current state of load/store issue.
18868 - If the pendulum is at zero, then no loads or stores have been
18869 issued in the current cycle so we do nothing.
18871 - If the pendulum is 1, then a single load has been issued in this
18872 cycle and we attempt to locate another load in the ready list to
18875 - If the pendulum is -2, then two stores have already been
18876 issued in this cycle, so we increase the priority of the first load
18877 in the ready list to increase it's likelihood of being chosen first
18880 - If the pendulum is -1, then a single store has been issued in this
18881 cycle and we attempt to locate another store in the ready list to
18882 issue with it, preferring a store to an adjacent memory location to
18883 facilitate store pairing in the store queue.
18885 - If the pendulum is 2, then two loads have already been
18886 issued in this cycle, so we increase the priority of the first store
18887 in the ready list to increase it's likelihood of being chosen first
18890 - If the pendulum < -2 or > 2, then do nothing.
18892 Note: This code covers the most common scenarios. There exist non
18893 load/store instructions which make use of the LSU and which
18894 would need to be accounted for to strictly model the behavior
18895 of the machine. Those instructions are currently unaccounted
18896 for to help minimize compile time overhead of this code.
18898 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
18904 if (is_store_insn (last_scheduled_insn))
18905 /* Issuing a store, swing the load_store_pendulum to the left */
18906 load_store_pendulum--;
18907 else if (is_load_insn (last_scheduled_insn))
18908 /* Issuing a load, swing the load_store_pendulum to the right */
18909 load_store_pendulum++;
18911 return cached_can_issue_more;
18913 /* If the pendulum is balanced, or there is only one instruction on
18914 the ready list, then all is well, so return. */
18915 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
18916 return cached_can_issue_more;
18918 if (load_store_pendulum == 1)
18920 /* A load has been issued in this cycle. Scan the ready list
18921 for another load to issue with it */
18926 if (is_load_insn (ready[pos]))
18928 /* Found a load. Move it to the head of the ready list,
18929 and adjust it's priority so that it is more likely to
18932 for (i=pos; i<*pn_ready-1; i++)
18933 ready[i] = ready[i + 1];
18934 ready[*pn_ready-1] = tmp;
18935 if INSN_PRIORITY_KNOWN (tmp)
18936 INSN_PRIORITY (tmp)++;
18942 else if (load_store_pendulum == -2)
18944 /* Two stores have been issued in this cycle. Increase the
18945 priority of the first load in the ready list to favor it for
18946 issuing in the next cycle. */
18951 if (is_load_insn (ready[pos])
18952 && INSN_PRIORITY_KNOWN (ready[pos]))
18954 INSN_PRIORITY (ready[pos])++;
18956 /* Adjust the pendulum to account for the fact that a load
18957 was found and increased in priority. This is to prevent
18958 increasing the priority of multiple loads */
18959 load_store_pendulum--;
18966 else if (load_store_pendulum == -1)
18968 /* A store has been issued in this cycle. Scan the ready list for
18969 another store to issue with it, preferring a store to an adjacent
18971 int first_store_pos = -1;
18977 if (is_store_insn (ready[pos]))
18979 /* Maintain the index of the first store found on the
18981 if (first_store_pos == -1)
18982 first_store_pos = pos;
18984 if (is_store_insn (last_scheduled_insn)
18985 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18987 /* Found an adjacent store. Move it to the head of the
18988 ready list, and adjust it's priority so that it is
18989 more likely to stay there */
18991 for (i=pos; i<*pn_ready-1; i++)
18992 ready[i] = ready[i + 1];
18993 ready[*pn_ready-1] = tmp;
18994 if INSN_PRIORITY_KNOWN (tmp)
18995 INSN_PRIORITY (tmp)++;
18996 first_store_pos = -1;
19004 if (first_store_pos >= 0)
19006 /* An adjacent store wasn't found, but a non-adjacent store was,
19007 so move the non-adjacent store to the front of the ready
19008 list, and adjust its priority so that it is more likely to
19010 tmp = ready[first_store_pos];
19011 for (i=first_store_pos; i<*pn_ready-1; i++)
19012 ready[i] = ready[i + 1];
19013 ready[*pn_ready-1] = tmp;
19014 if INSN_PRIORITY_KNOWN (tmp)
19015 INSN_PRIORITY (tmp)++;
19018 else if (load_store_pendulum == 2)
19020 /* Two loads have been issued in this cycle. Increase the priority
19021 of the first store in the ready list to favor it for issuing in
19027 if (is_store_insn (ready[pos])
19028 && INSN_PRIORITY_KNOWN (ready[pos]))
19030 INSN_PRIORITY (ready[pos])++;
19032 /* Adjust the pendulum to account for the fact that a store
19033 was found and increased in priority. This is to prevent
19034 increasing the priority of multiple stores */
19035 load_store_pendulum++;
19044 return cached_can_issue_more;
19047 /* Return whether the presence of INSN causes a dispatch group termination
19048 of group WHICH_GROUP.
19050 If WHICH_GROUP == current_group, this function will return true if INSN
19051 causes the termination of the current group (i.e, the dispatch group to
19052 which INSN belongs). This means that INSN will be the last insn in the
19053 group it belongs to.
19055 If WHICH_GROUP == previous_group, this function will return true if INSN
19056 causes the termination of the previous group (i.e, the dispatch group that
19057 precedes the group to which INSN belongs). This means that INSN will be
19058 the first insn in the group it belongs to). */
19061 insn_terminates_group_p (rtx insn, enum group_termination which_group)
19068 first = insn_must_be_first_in_group (insn);
19069 last = insn_must_be_last_in_group (insn);
19074 if (which_group == current_group)
19076 else if (which_group == previous_group)
19084 insn_must_be_first_in_group (rtx insn)
19086 enum attr_type type;
19089 || insn == NULL_RTX
19090 || GET_CODE (insn) == NOTE
19091 || GET_CODE (PATTERN (insn)) == USE
19092 || GET_CODE (PATTERN (insn)) == CLOBBER)
19095 switch (rs6000_cpu)
19097 case PROCESSOR_POWER5:
19098 if (is_cracked_insn (insn))
19100 case PROCESSOR_POWER4:
19101 if (is_microcoded_insn (insn))
19104 if (!rs6000_sched_groups)
19107 type = get_attr_type (insn);
19114 case TYPE_DELAYED_CR:
19115 case TYPE_CR_LOGICAL:
19129 case PROCESSOR_POWER6:
19130 type = get_attr_type (insn);
19134 case TYPE_INSERT_DWORD:
19138 case TYPE_VAR_SHIFT_ROTATE:
19145 case TYPE_INSERT_WORD:
19146 case TYPE_DELAYED_COMPARE:
19147 case TYPE_IMUL_COMPARE:
19148 case TYPE_LMUL_COMPARE:
19149 case TYPE_FPCOMPARE:
19160 case TYPE_LOAD_EXT_UX:
19162 case TYPE_STORE_UX:
19163 case TYPE_FPLOAD_U:
19164 case TYPE_FPLOAD_UX:
19165 case TYPE_FPSTORE_U:
19166 case TYPE_FPSTORE_UX:
19180 insn_must_be_last_in_group (rtx insn)
19182 enum attr_type type;
19185 || insn == NULL_RTX
19186 || GET_CODE (insn) == NOTE
19187 || GET_CODE (PATTERN (insn)) == USE
19188 || GET_CODE (PATTERN (insn)) == CLOBBER)
19191 switch (rs6000_cpu) {
19192 case PROCESSOR_POWER4:
19193 case PROCESSOR_POWER5:
19194 if (is_microcoded_insn (insn))
19197 if (is_branch_slot_insn (insn))
19201 case PROCESSOR_POWER6:
19202 type = get_attr_type (insn);
19209 case TYPE_VAR_SHIFT_ROTATE:
19216 case TYPE_DELAYED_COMPARE:
19217 case TYPE_IMUL_COMPARE:
19218 case TYPE_LMUL_COMPARE:
19219 case TYPE_FPCOMPARE:
19240 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19241 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
19244 is_costly_group (rtx *group_insns, rtx next_insn)
19247 int issue_rate = rs6000_issue_rate ();
19249 for (i = 0; i < issue_rate; i++)
19251 sd_iterator_def sd_it;
19253 rtx insn = group_insns[i];
19258 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
19260 rtx next = DEP_CON (dep);
19262 if (next == next_insn
19263 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
19271 /* Utility of the function redefine_groups.
19272 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
19273 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
19274 to keep it "far" (in a separate group) from GROUP_INSNS, following
19275 one of the following schemes, depending on the value of the flag
19276 -minsert_sched_nops = X:
19277 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
19278 in order to force NEXT_INSN into a separate group.
19279 (2) X < sched_finish_regroup_exact: insert exactly X nops.
19280 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
19281 insertion (has a group just ended, how many vacant issue slots remain in the
19282 last group, and how many dispatch groups were encountered so far). */
19285 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
19286 rtx next_insn, bool *group_end, int can_issue_more,
19291 int issue_rate = rs6000_issue_rate ();
19292 bool end = *group_end;
19295 if (next_insn == NULL_RTX)
19296 return can_issue_more;
19298 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
19299 return can_issue_more;
19301 force = is_costly_group (group_insns, next_insn);
19303 return can_issue_more;
19305 if (sched_verbose > 6)
19306 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
19307 *group_count ,can_issue_more);
19309 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
19312 can_issue_more = 0;
19314 /* Since only a branch can be issued in the last issue_slot, it is
19315 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
19316 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
19317 in this case the last nop will start a new group and the branch
19318 will be forced to the new group. */
19319 if (can_issue_more && !is_branch_slot_insn (next_insn))
19322 while (can_issue_more > 0)
19325 emit_insn_before (nop, next_insn);
19333 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
19335 int n_nops = rs6000_sched_insert_nops;
19337 /* Nops can't be issued from the branch slot, so the effective
19338 issue_rate for nops is 'issue_rate - 1'. */
19339 if (can_issue_more == 0)
19340 can_issue_more = issue_rate;
19342 if (can_issue_more == 0)
19344 can_issue_more = issue_rate - 1;
19347 for (i = 0; i < issue_rate; i++)
19349 group_insns[i] = 0;
19356 emit_insn_before (nop, next_insn);
19357 if (can_issue_more == issue_rate - 1) /* new group begins */
19360 if (can_issue_more == 0)
19362 can_issue_more = issue_rate - 1;
19365 for (i = 0; i < issue_rate; i++)
19367 group_insns[i] = 0;
19373 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
19376 /* Is next_insn going to start a new group? */
19379 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19380 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19381 || (can_issue_more < issue_rate &&
19382 insn_terminates_group_p (next_insn, previous_group)));
19383 if (*group_end && end)
19386 if (sched_verbose > 6)
19387 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
19388 *group_count, can_issue_more);
19389 return can_issue_more;
19392 return can_issue_more;
19395 /* This function tries to synch the dispatch groups that the compiler "sees"
19396 with the dispatch groups that the processor dispatcher is expected to
19397 form in practice. It tries to achieve this synchronization by forcing the
19398 estimated processor grouping on the compiler (as opposed to the function
19399 'pad_goups' which tries to force the scheduler's grouping on the processor).
19401 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
19402 examines the (estimated) dispatch groups that will be formed by the processor
19403 dispatcher. It marks these group boundaries to reflect the estimated
19404 processor grouping, overriding the grouping that the scheduler had marked.
19405 Depending on the value of the flag '-minsert-sched-nops' this function can
19406 force certain insns into separate groups or force a certain distance between
19407 them by inserting nops, for example, if there exists a "costly dependence"
19410 The function estimates the group boundaries that the processor will form as
19411 follows: It keeps track of how many vacant issue slots are available after
19412 each insn. A subsequent insn will start a new group if one of the following
19414 - no more vacant issue slots remain in the current dispatch group.
19415 - only the last issue slot, which is the branch slot, is vacant, but the next
19416 insn is not a branch.
19417 - only the last 2 or less issue slots, including the branch slot, are vacant,
19418 which means that a cracked insn (which occupies two issue slots) can't be
19419 issued in this group.
19420 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19421 start a new group. */
19424 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19426 rtx insn, next_insn;
19428 int can_issue_more;
19431 int group_count = 0;
19435 issue_rate = rs6000_issue_rate ();
19436 group_insns = alloca (issue_rate * sizeof (rtx));
19437 for (i = 0; i < issue_rate; i++)
19439 group_insns[i] = 0;
19441 can_issue_more = issue_rate;
19443 insn = get_next_active_insn (prev_head_insn, tail);
19446 while (insn != NULL_RTX)
19448 slot = (issue_rate - can_issue_more);
19449 group_insns[slot] = insn;
19451 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19452 if (insn_terminates_group_p (insn, current_group))
19453 can_issue_more = 0;
19455 next_insn = get_next_active_insn (insn, tail);
19456 if (next_insn == NULL_RTX)
19457 return group_count + 1;
19459 /* Is next_insn going to start a new group? */
19461 = (can_issue_more == 0
19462 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19463 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19464 || (can_issue_more < issue_rate &&
19465 insn_terminates_group_p (next_insn, previous_group)));
19467 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
19468 next_insn, &group_end, can_issue_more,
19474 can_issue_more = 0;
19475 for (i = 0; i < issue_rate; i++)
19477 group_insns[i] = 0;
19481 if (GET_MODE (next_insn) == TImode && can_issue_more)
19482 PUT_MODE (next_insn, VOIDmode);
19483 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
19484 PUT_MODE (next_insn, TImode);
19487 if (can_issue_more == 0)
19488 can_issue_more = issue_rate;
19491 return group_count;
19494 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19495 dispatch group boundaries that the scheduler had marked. Pad with nops
19496 any dispatch groups which have vacant issue slots, in order to force the
19497 scheduler's grouping on the processor dispatcher. The function
19498 returns the number of dispatch groups found. */
19501 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19503 rtx insn, next_insn;
19506 int can_issue_more;
19508 int group_count = 0;
19510 /* Initialize issue_rate. */
19511 issue_rate = rs6000_issue_rate ();
19512 can_issue_more = issue_rate;
19514 insn = get_next_active_insn (prev_head_insn, tail);
19515 next_insn = get_next_active_insn (insn, tail);
19517 while (insn != NULL_RTX)
19520 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19522 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
19524 if (next_insn == NULL_RTX)
19529 /* If the scheduler had marked group termination at this location
19530 (between insn and next_indn), and neither insn nor next_insn will
19531 force group termination, pad the group with nops to force group
19534 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
19535 && !insn_terminates_group_p (insn, current_group)
19536 && !insn_terminates_group_p (next_insn, previous_group))
19538 if (!is_branch_slot_insn (next_insn))
19541 while (can_issue_more)
19544 emit_insn_before (nop, next_insn);
19549 can_issue_more = issue_rate;
19554 next_insn = get_next_active_insn (insn, tail);
19557 return group_count;
19560 /* We're beginning a new block. Initialize data structures as necessary. */
19563 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
19564 int sched_verbose ATTRIBUTE_UNUSED,
19565 int max_ready ATTRIBUTE_UNUSED)
19567 last_scheduled_insn = NULL_RTX;
19568 load_store_pendulum = 0;
19571 /* The following function is called at the end of scheduling BB.
19572 After reload, it inserts nops at insn group bundling. */
19575 rs6000_sched_finish (FILE *dump, int sched_verbose)
19580 fprintf (dump, "=== Finishing schedule.\n");
19582 if (reload_completed && rs6000_sched_groups)
19584 if (rs6000_sched_insert_nops == sched_finish_none)
19587 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
19588 n_groups = pad_groups (dump, sched_verbose,
19589 current_sched_info->prev_head,
19590 current_sched_info->next_tail);
19592 n_groups = redefine_groups (dump, sched_verbose,
19593 current_sched_info->prev_head,
19594 current_sched_info->next_tail);
19596 if (sched_verbose >= 6)
19598 fprintf (dump, "ngroups = %d\n", n_groups);
19599 print_rtl (dump, current_sched_info->prev_head);
19600 fprintf (dump, "Done finish_sched\n");
19605 /* Length in units of the trampoline for entering a nested function. */
19608 rs6000_trampoline_size (void)
19612 switch (DEFAULT_ABI)
19615 gcc_unreachable ();
19618 ret = (TARGET_32BIT) ? 12 : 24;
19623 ret = (TARGET_32BIT) ? 40 : 48;
19630 /* Emit RTL insns to initialize the variable parts of a trampoline.
19631 FNADDR is an RTX for the address of the function's pure code.
19632 CXT is an RTX for the static chain value for the function. */
19635 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
19637 int regsize = (TARGET_32BIT) ? 4 : 8;
19638 rtx ctx_reg = force_reg (Pmode, cxt);
19640 switch (DEFAULT_ABI)
19643 gcc_unreachable ();
19645 /* Macros to shorten the code expansions below. */
19646 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
19647 #define MEM_PLUS(addr,offset) \
19648 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
19650 /* Under AIX, just build the 3 word function descriptor */
19653 rtx fn_reg = gen_reg_rtx (Pmode);
19654 rtx toc_reg = gen_reg_rtx (Pmode);
19655 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
19656 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
19657 emit_move_insn (MEM_DEREF (addr), fn_reg);
19658 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
19659 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
19663 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
19666 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
19667 FALSE, VOIDmode, 4,
19669 GEN_INT (rs6000_trampoline_size ()), SImode,
19679 /* Table of valid machine attributes. */
19681 const struct attribute_spec rs6000_attribute_table[] =
19683 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
19684 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
19685 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
19686 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
19687 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
19688 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
19689 #ifdef SUBTARGET_ATTRIBUTE_TABLE
19690 SUBTARGET_ATTRIBUTE_TABLE,
19692 { NULL, 0, 0, false, false, false, NULL }
19695 /* Handle the "altivec" attribute. The attribute may have
19696 arguments as follows:
19698 __attribute__((altivec(vector__)))
19699 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
19700 __attribute__((altivec(bool__))) (always followed by 'unsigned')
19702 and may appear more than once (e.g., 'vector bool char') in a
19703 given declaration. */
19706 rs6000_handle_altivec_attribute (tree *node,
19707 tree name ATTRIBUTE_UNUSED,
19709 int flags ATTRIBUTE_UNUSED,
19710 bool *no_add_attrs)
19712 tree type = *node, result = NULL_TREE;
19713 enum machine_mode mode;
19716 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
19717 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
19718 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
19721 while (POINTER_TYPE_P (type)
19722 || TREE_CODE (type) == FUNCTION_TYPE
19723 || TREE_CODE (type) == METHOD_TYPE
19724 || TREE_CODE (type) == ARRAY_TYPE)
19725 type = TREE_TYPE (type);
19727 mode = TYPE_MODE (type);
19729 /* Check for invalid AltiVec type qualifiers. */
19730 if (type == long_unsigned_type_node || type == long_integer_type_node)
19733 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
19734 else if (rs6000_warn_altivec_long)
19735 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
19737 else if (type == long_long_unsigned_type_node
19738 || type == long_long_integer_type_node)
19739 error ("use of %<long long%> in AltiVec types is invalid");
19740 else if (type == double_type_node)
19741 error ("use of %<double%> in AltiVec types is invalid");
19742 else if (type == long_double_type_node)
19743 error ("use of %<long double%> in AltiVec types is invalid");
19744 else if (type == boolean_type_node)
19745 error ("use of boolean types in AltiVec types is invalid");
19746 else if (TREE_CODE (type) == COMPLEX_TYPE)
19747 error ("use of %<complex%> in AltiVec types is invalid");
19748 else if (DECIMAL_FLOAT_MODE_P (mode))
19749 error ("use of decimal floating point types in AltiVec types is invalid");
19751 switch (altivec_type)
19754 unsigned_p = TYPE_UNSIGNED (type);
19758 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
19761 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
19764 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
19766 case SFmode: result = V4SF_type_node; break;
19767 /* If the user says 'vector int bool', we may be handed the 'bool'
19768 attribute _before_ the 'vector' attribute, and so select the
19769 proper type in the 'b' case below. */
19770 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
19778 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
19779 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
19780 case QImode: case V16QImode: result = bool_V16QI_type_node;
19787 case V8HImode: result = pixel_V8HI_type_node;
19793 if (result && result != type && TYPE_READONLY (type))
19794 result = build_qualified_type (result, TYPE_QUAL_CONST);
19796 *no_add_attrs = true; /* No need to hang on to the attribute. */
19799 *node = reconstruct_complex_type (*node, result);
19804 /* AltiVec defines four built-in scalar types that serve as vector
19805 elements; we must teach the compiler how to mangle them. */
19807 static const char *
19808 rs6000_mangle_type (const_tree type)
19810 type = TYPE_MAIN_VARIANT (type);
19812 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
19813 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
19816 if (type == bool_char_type_node) return "U6__boolc";
19817 if (type == bool_short_type_node) return "U6__bools";
19818 if (type == pixel_type_node) return "u7__pixel";
19819 if (type == bool_int_type_node) return "U6__booli";
19821 /* Mangle IBM extended float long double as `g' (__float128) on
19822 powerpc*-linux where long-double-64 previously was the default. */
19823 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
19825 && TARGET_LONG_DOUBLE_128
19826 && !TARGET_IEEEQUAD)
19829 /* For all other types, use normal C++ mangling. */
19833 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19834 struct attribute_spec.handler. */
19837 rs6000_handle_longcall_attribute (tree *node, tree name,
19838 tree args ATTRIBUTE_UNUSED,
19839 int flags ATTRIBUTE_UNUSED,
19840 bool *no_add_attrs)
19842 if (TREE_CODE (*node) != FUNCTION_TYPE
19843 && TREE_CODE (*node) != FIELD_DECL
19844 && TREE_CODE (*node) != TYPE_DECL)
19846 warning (OPT_Wattributes, "%qs attribute only applies to functions",
19847 IDENTIFIER_POINTER (name));
19848 *no_add_attrs = true;
19854 /* Set longcall attributes on all functions declared when
19855 rs6000_default_long_calls is true. */
19857 rs6000_set_default_type_attributes (tree type)
19859 if (rs6000_default_long_calls
19860 && (TREE_CODE (type) == FUNCTION_TYPE
19861 || TREE_CODE (type) == METHOD_TYPE))
19862 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
19864 TYPE_ATTRIBUTES (type));
19867 darwin_set_default_type_attributes (type);
19871 /* Return a reference suitable for calling a function with the
19872 longcall attribute. */
19875 rs6000_longcall_ref (rtx call_ref)
19877 const char *call_name;
19880 if (GET_CODE (call_ref) != SYMBOL_REF)
19883 /* System V adds '.' to the internal name, so skip them. */
19884 call_name = XSTR (call_ref, 0);
19885 if (*call_name == '.')
19887 while (*call_name == '.')
19890 node = get_identifier (call_name);
19891 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
19894 return force_reg (Pmode, call_ref);
19897 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19898 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19901 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19902 struct attribute_spec.handler. */
19904 rs6000_handle_struct_attribute (tree *node, tree name,
19905 tree args ATTRIBUTE_UNUSED,
19906 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
19909 if (DECL_P (*node))
19911 if (TREE_CODE (*node) == TYPE_DECL)
19912 type = &TREE_TYPE (*node);
19917 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
19918 || TREE_CODE (*type) == UNION_TYPE)))
19920 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
19921 *no_add_attrs = true;
19924 else if ((is_attribute_p ("ms_struct", name)
19925 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
19926 || ((is_attribute_p ("gcc_struct", name)
19927 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19929 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19930 IDENTIFIER_POINTER (name));
19931 *no_add_attrs = true;
19938 rs6000_ms_bitfield_layout_p (const_tree record_type)
19940 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19941 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19942 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19945 #ifdef USING_ELFOS_H
19947 /* A get_unnamed_section callback, used for switching to toc_section. */
19950 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19952 if (DEFAULT_ABI == ABI_AIX
19953 && TARGET_MINIMAL_TOC
19954 && !TARGET_RELOCATABLE)
19956 if (!toc_initialized)
19958 toc_initialized = 1;
19959 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19960 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19961 fprintf (asm_out_file, "\t.tc ");
19962 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19963 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19964 fprintf (asm_out_file, "\n");
19966 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19967 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19968 fprintf (asm_out_file, " = .+32768\n");
19971 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19973 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19974 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19977 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19978 if (!toc_initialized)
19980 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19981 fprintf (asm_out_file, " = .+32768\n");
19982 toc_initialized = 1;
19987 /* Implement TARGET_ASM_INIT_SECTIONS. */
19990 rs6000_elf_asm_init_sections (void)
19993 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19996 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19997 SDATA2_SECTION_ASM_OP);
20000 /* Implement TARGET_SELECT_RTX_SECTION. */
20003 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
20004 unsigned HOST_WIDE_INT align)
20006 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20007 return toc_section;
20009 return default_elf_select_rtx_section (mode, x, align);
20012 /* For a SYMBOL_REF, set generic flags and then perform some
20013 target-specific processing.
20015 When the AIX ABI is requested on a non-AIX system, replace the
20016 function name with the real name (with a leading .) rather than the
20017 function descriptor name. This saves a lot of overriding code to
20018 read the prefixes. */
20021 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
20023 default_encode_section_info (decl, rtl, first);
20026 && TREE_CODE (decl) == FUNCTION_DECL
20028 && DEFAULT_ABI == ABI_AIX)
20030 rtx sym_ref = XEXP (rtl, 0);
20031 size_t len = strlen (XSTR (sym_ref, 0));
20032 char *str = alloca (len + 2);
20034 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
20035 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
20040 compare_section_name (const char *section, const char *template)
20044 len = strlen (template);
20045 return (strncmp (section, template, len) == 0
20046 && (section[len] == 0 || section[len] == '.'));
20050 rs6000_elf_in_small_data_p (const_tree decl)
20052 if (rs6000_sdata == SDATA_NONE)
20055 /* We want to merge strings, so we never consider them small data. */
20056 if (TREE_CODE (decl) == STRING_CST)
20059 /* Functions are never in the small data area. */
20060 if (TREE_CODE (decl) == FUNCTION_DECL)
20063 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
20065 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
20066 if (compare_section_name (section, ".sdata")
20067 || compare_section_name (section, ".sdata2")
20068 || compare_section_name (section, ".gnu.linkonce.s")
20069 || compare_section_name (section, ".sbss")
20070 || compare_section_name (section, ".sbss2")
20071 || compare_section_name (section, ".gnu.linkonce.sb")
20072 || strcmp (section, ".PPC.EMB.sdata0") == 0
20073 || strcmp (section, ".PPC.EMB.sbss0") == 0)
20078 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
20081 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20082 /* If it's not public, and we're not going to reference it there,
20083 there's no need to put it in the small data section. */
20084 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
20091 #endif /* USING_ELFOS_H */
20093 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20096 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
20098 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
20101 /* Return a REG that occurs in ADDR with coefficient 1.
20102 ADDR can be effectively incremented by incrementing REG.
20104 r0 is special and we must not select it as an address
20105 register by this routine since our caller will try to
20106 increment the returned register via an "la" instruction. */
20109 find_addr_reg (rtx addr)
20111 while (GET_CODE (addr) == PLUS)
20113 if (GET_CODE (XEXP (addr, 0)) == REG
20114 && REGNO (XEXP (addr, 0)) != 0)
20115 addr = XEXP (addr, 0);
20116 else if (GET_CODE (XEXP (addr, 1)) == REG
20117 && REGNO (XEXP (addr, 1)) != 0)
20118 addr = XEXP (addr, 1);
20119 else if (CONSTANT_P (XEXP (addr, 0)))
20120 addr = XEXP (addr, 1);
20121 else if (CONSTANT_P (XEXP (addr, 1)))
20122 addr = XEXP (addr, 0);
20124 gcc_unreachable ();
20126 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
20131 rs6000_fatal_bad_address (rtx op)
20133 fatal_insn ("bad address", op);
20138 static tree branch_island_list = 0;
20140 /* Remember to generate a branch island for far calls to the given
20144 add_compiler_branch_island (tree label_name, tree function_name,
20147 tree branch_island = build_tree_list (function_name, label_name);
20148 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
20149 TREE_CHAIN (branch_island) = branch_island_list;
20150 branch_island_list = branch_island;
20153 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20154 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20155 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20156 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20158 /* Generate far-jump branch islands for everything on the
20159 branch_island_list. Invoked immediately after the last instruction
20160 of the epilogue has been emitted; the branch-islands must be
20161 appended to, and contiguous with, the function body. Mach-O stubs
20162 are generated in machopic_output_stub(). */
20165 macho_branch_islands (void)
20168 tree branch_island;
20170 for (branch_island = branch_island_list;
20172 branch_island = TREE_CHAIN (branch_island))
20174 const char *label =
20175 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
20177 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
20178 char name_buf[512];
20179 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
20180 if (name[0] == '*' || name[0] == '&')
20181 strcpy (name_buf, name+1);
20185 strcpy (name_buf+1, name);
20187 strcpy (tmp_buf, "\n");
20188 strcat (tmp_buf, label);
20189 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20190 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
20191 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
20192 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20195 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
20196 strcat (tmp_buf, label);
20197 strcat (tmp_buf, "_pic\n");
20198 strcat (tmp_buf, label);
20199 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
20201 strcat (tmp_buf, "\taddis r11,r11,ha16(");
20202 strcat (tmp_buf, name_buf);
20203 strcat (tmp_buf, " - ");
20204 strcat (tmp_buf, label);
20205 strcat (tmp_buf, "_pic)\n");
20207 strcat (tmp_buf, "\tmtlr r0\n");
20209 strcat (tmp_buf, "\taddi r12,r11,lo16(");
20210 strcat (tmp_buf, name_buf);
20211 strcat (tmp_buf, " - ");
20212 strcat (tmp_buf, label);
20213 strcat (tmp_buf, "_pic)\n");
20215 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
20219 strcat (tmp_buf, ":\nlis r12,hi16(");
20220 strcat (tmp_buf, name_buf);
20221 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
20222 strcat (tmp_buf, name_buf);
20223 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
20225 output_asm_insn (tmp_buf, 0);
20226 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20227 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
20228 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
20229 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20232 branch_island_list = 0;
20235 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
20236 already there or not. */
20239 no_previous_def (tree function_name)
20241 tree branch_island;
20242 for (branch_island = branch_island_list;
20244 branch_island = TREE_CHAIN (branch_island))
20245 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
20250 /* GET_PREV_LABEL gets the label name from the previous definition of
20254 get_prev_label (tree function_name)
20256 tree branch_island;
20257 for (branch_island = branch_island_list;
20259 branch_island = TREE_CHAIN (branch_island))
20260 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
20261 return BRANCH_ISLAND_LABEL_NAME (branch_island);
20265 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
20266 #define DARWIN_LINKER_GENERATES_ISLANDS 0
20269 /* KEXTs still need branch islands. */
20270 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
20271 || flag_mkernel || flag_apple_kext)
20273 /* INSN is either a function call or a millicode call. It may have an
20274 unconditional jump in its delay slot.
20276 CALL_DEST is the routine we are calling. */
20279 output_call (rtx insn, rtx *operands, int dest_operand_number,
20280 int cookie_operand_number)
20282 static char buf[256];
20283 if (DARWIN_GENERATE_ISLANDS
20284 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
20285 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
20288 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
20290 if (no_previous_def (funname))
20292 rtx label_rtx = gen_label_rtx ();
20293 char *label_buf, temp_buf[256];
20294 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
20295 CODE_LABEL_NUMBER (label_rtx));
20296 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
20297 labelname = get_identifier (label_buf);
20298 add_compiler_branch_island (labelname, funname, insn_line (insn));
20301 labelname = get_prev_label (funname);
20303 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
20304 instruction will reach 'foo', otherwise link as 'bl L42'".
20305 "L42" should be a 'branch island', that will do a far jump to
20306 'foo'. Branch islands are generated in
20307 macho_branch_islands(). */
20308 sprintf (buf, "jbsr %%z%d,%.246s",
20309 dest_operand_number, IDENTIFIER_POINTER (labelname));
20312 sprintf (buf, "bl %%z%d", dest_operand_number);
20316 /* Generate PIC and indirect symbol stubs. */
20319 machopic_output_stub (FILE *file, const char *symb, const char *stub)
20321 unsigned int length;
20322 char *symbol_name, *lazy_ptr_name;
20323 char *local_label_0;
20324 static int label = 0;
20326 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20327 symb = (*targetm.strip_name_encoding) (symb);
20330 length = strlen (symb);
20331 symbol_name = alloca (length + 32);
20332 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
20334 lazy_ptr_name = alloca (length + 32);
20335 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
20338 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
20340 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
20344 fprintf (file, "\t.align 5\n");
20346 fprintf (file, "%s:\n", stub);
20347 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20350 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
20351 sprintf (local_label_0, "\"L%011d$spb\"", label);
20353 fprintf (file, "\tmflr r0\n");
20354 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
20355 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
20356 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
20357 lazy_ptr_name, local_label_0);
20358 fprintf (file, "\tmtlr r0\n");
20359 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
20360 (TARGET_64BIT ? "ldu" : "lwzu"),
20361 lazy_ptr_name, local_label_0);
20362 fprintf (file, "\tmtctr r12\n");
20363 fprintf (file, "\tbctr\n");
20367 fprintf (file, "\t.align 4\n");
20369 fprintf (file, "%s:\n", stub);
20370 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20372 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
20373 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
20374 (TARGET_64BIT ? "ldu" : "lwzu"),
20376 fprintf (file, "\tmtctr r12\n");
20377 fprintf (file, "\tbctr\n");
20380 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
20381 fprintf (file, "%s:\n", lazy_ptr_name);
20382 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20383 fprintf (file, "%sdyld_stub_binding_helper\n",
20384 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
20387 /* Legitimize PIC addresses. If the address is already
20388 position-independent, we return ORIG. Newly generated
20389 position-independent addresses go into a reg. This is REG if non
20390 zero, otherwise we allocate register(s) as necessary. */
20392 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
20395 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
20400 if (reg == NULL && ! reload_in_progress && ! reload_completed)
20401 reg = gen_reg_rtx (Pmode);
20403 if (GET_CODE (orig) == CONST)
20407 if (GET_CODE (XEXP (orig, 0)) == PLUS
20408 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
20411 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
20413 /* Use a different reg for the intermediate value, as
20414 it will be marked UNCHANGING. */
20415 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
20416 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
20419 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
20422 if (GET_CODE (offset) == CONST_INT)
20424 if (SMALL_INT (offset))
20425 return plus_constant (base, INTVAL (offset));
20426 else if (! reload_in_progress && ! reload_completed)
20427 offset = force_reg (Pmode, offset);
20430 rtx mem = force_const_mem (Pmode, orig);
20431 return machopic_legitimize_pic_address (mem, Pmode, reg);
20434 return gen_rtx_PLUS (Pmode, base, offset);
20437 /* Fall back on generic machopic code. */
20438 return machopic_legitimize_pic_address (orig, mode, reg);
20441 /* Output a .machine directive for the Darwin assembler, and call
20442 the generic start_file routine. */
20445 rs6000_darwin_file_start (void)
20447 static const struct
20453 { "ppc64", "ppc64", MASK_64BIT },
20454 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
20455 { "power4", "ppc970", 0 },
20456 { "G5", "ppc970", 0 },
20457 { "7450", "ppc7450", 0 },
20458 { "7400", "ppc7400", MASK_ALTIVEC },
20459 { "G4", "ppc7400", 0 },
20460 { "750", "ppc750", 0 },
20461 { "740", "ppc750", 0 },
20462 { "G3", "ppc750", 0 },
20463 { "604e", "ppc604e", 0 },
20464 { "604", "ppc604", 0 },
20465 { "603e", "ppc603", 0 },
20466 { "603", "ppc603", 0 },
20467 { "601", "ppc601", 0 },
20468 { NULL, "ppc", 0 } };
20469 const char *cpu_id = "";
20472 rs6000_file_start ();
20473 darwin_file_start ();
20475 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20476 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
20477 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
20478 && rs6000_select[i].string[0] != '\0')
20479 cpu_id = rs6000_select[i].string;
20481 /* Look through the mapping array. Pick the first name that either
20482 matches the argument, has a bit set in IF_SET that is also set
20483 in the target flags, or has a NULL name. */
20486 while (mapping[i].arg != NULL
20487 && strcmp (mapping[i].arg, cpu_id) != 0
20488 && (mapping[i].if_set & target_flags) == 0)
20491 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
20494 #endif /* TARGET_MACHO */
20498 rs6000_elf_reloc_rw_mask (void)
20502 else if (DEFAULT_ABI == ABI_AIX)
20508 /* Record an element in the table of global constructors. SYMBOL is
20509 a SYMBOL_REF of the function to be called; PRIORITY is a number
20510 between 0 and MAX_INIT_PRIORITY.
20512 This differs from default_named_section_asm_out_constructor in
20513 that we have special handling for -mrelocatable. */
20516 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
20518 const char *section = ".ctors";
20521 if (priority != DEFAULT_INIT_PRIORITY)
20523 sprintf (buf, ".ctors.%.5u",
20524 /* Invert the numbering so the linker puts us in the proper
20525 order; constructors are run from right to left, and the
20526 linker sorts in increasing order. */
20527 MAX_INIT_PRIORITY - priority);
20531 switch_to_section (get_section (section, SECTION_WRITE, NULL));
20532 assemble_align (POINTER_SIZE);
20534 if (TARGET_RELOCATABLE)
20536 fputs ("\t.long (", asm_out_file);
20537 output_addr_const (asm_out_file, symbol);
20538 fputs (")@fixup\n", asm_out_file);
20541 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
20545 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
20547 const char *section = ".dtors";
20550 if (priority != DEFAULT_INIT_PRIORITY)
20552 sprintf (buf, ".dtors.%.5u",
20553 /* Invert the numbering so the linker puts us in the proper
20554 order; constructors are run from right to left, and the
20555 linker sorts in increasing order. */
20556 MAX_INIT_PRIORITY - priority);
20560 switch_to_section (get_section (section, SECTION_WRITE, NULL));
20561 assemble_align (POINTER_SIZE);
20563 if (TARGET_RELOCATABLE)
20565 fputs ("\t.long (", asm_out_file);
20566 output_addr_const (asm_out_file, symbol);
20567 fputs (")@fixup\n", asm_out_file);
20570 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
20574 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
20578 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
20579 ASM_OUTPUT_LABEL (file, name);
20580 fputs (DOUBLE_INT_ASM_OP, file);
20581 rs6000_output_function_entry (file, name);
20582 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
20585 fputs ("\t.size\t", file);
20586 assemble_name (file, name);
20587 fputs (",24\n\t.type\t.", file);
20588 assemble_name (file, name);
20589 fputs (",@function\n", file);
20590 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
20592 fputs ("\t.globl\t.", file);
20593 assemble_name (file, name);
20598 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
20599 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
20600 rs6000_output_function_entry (file, name);
20601 fputs (":\n", file);
20605 if (TARGET_RELOCATABLE
20606 && !TARGET_SECURE_PLT
20607 && (get_pool_size () != 0 || current_function_profile)
20612 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
20614 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
20615 fprintf (file, "\t.long ");
20616 assemble_name (file, buf);
20618 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
20619 assemble_name (file, buf);
20623 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
20624 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
20626 if (DEFAULT_ABI == ABI_AIX)
20628 const char *desc_name, *orig_name;
20630 orig_name = (*targetm.strip_name_encoding) (name);
20631 desc_name = orig_name;
20632 while (*desc_name == '.')
20635 if (TREE_PUBLIC (decl))
20636 fprintf (file, "\t.globl %s\n", desc_name);
20638 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20639 fprintf (file, "%s:\n", desc_name);
20640 fprintf (file, "\t.long %s\n", orig_name);
20641 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
20642 if (DEFAULT_ABI == ABI_AIX)
20643 fputs ("\t.long 0\n", file);
20644 fprintf (file, "\t.previous\n");
20646 ASM_OUTPUT_LABEL (file, name);
20650 rs6000_elf_end_indicate_exec_stack (void)
20653 file_end_indicate_exec_stack ();
20659 rs6000_xcoff_asm_output_anchor (rtx symbol)
20663 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
20664 SYMBOL_REF_BLOCK_OFFSET (symbol));
20665 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
20669 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
20671 fputs (GLOBAL_ASM_OP, stream);
20672 RS6000_OUTPUT_BASENAME (stream, name);
20673 putc ('\n', stream);
20676 /* A get_unnamed_decl callback, used for read-only sections. PTR
20677 points to the section string variable. */
20680 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
20682 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
20683 *(const char *const *) directive,
20684 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
20687 /* Likewise for read-write sections. */
20690 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
20692 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
20693 *(const char *const *) directive,
20694 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
20697 /* A get_unnamed_section callback, used for switching to toc_section. */
20700 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
20702 if (TARGET_MINIMAL_TOC)
20704 /* toc_section is always selected at least once from
20705 rs6000_xcoff_file_start, so this is guaranteed to
20706 always be defined once and only once in each file. */
20707 if (!toc_initialized)
20709 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
20710 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
20711 toc_initialized = 1;
20713 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
20714 (TARGET_32BIT ? "" : ",3"));
20717 fputs ("\t.toc\n", asm_out_file);
20720 /* Implement TARGET_ASM_INIT_SECTIONS. */
20723 rs6000_xcoff_asm_init_sections (void)
20725 read_only_data_section
20726 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
20727 &xcoff_read_only_section_name);
20729 private_data_section
20730 = get_unnamed_section (SECTION_WRITE,
20731 rs6000_xcoff_output_readwrite_section_asm_op,
20732 &xcoff_private_data_section_name);
20734 read_only_private_data_section
20735 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
20736 &xcoff_private_data_section_name);
20739 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
20741 readonly_data_section = read_only_data_section;
20742 exception_section = data_section;
20746 rs6000_xcoff_reloc_rw_mask (void)
20752 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
20753 tree decl ATTRIBUTE_UNUSED)
20756 static const char * const suffix[3] = { "PR", "RO", "RW" };
20758 if (flags & SECTION_CODE)
20760 else if (flags & SECTION_WRITE)
20765 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
20766 (flags & SECTION_CODE) ? "." : "",
20767 name, suffix[smclass], flags & SECTION_ENTSIZE);
20771 rs6000_xcoff_select_section (tree decl, int reloc,
20772 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
20774 if (decl_readonly_section (decl, reloc))
20776 if (TREE_PUBLIC (decl))
20777 return read_only_data_section;
20779 return read_only_private_data_section;
20783 if (TREE_PUBLIC (decl))
20784 return data_section;
20786 return private_data_section;
20791 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
20795 /* Use select_section for private and uninitialized data. */
20796 if (!TREE_PUBLIC (decl)
20797 || DECL_COMMON (decl)
20798 || DECL_INITIAL (decl) == NULL_TREE
20799 || DECL_INITIAL (decl) == error_mark_node
20800 || (flag_zero_initialized_in_bss
20801 && initializer_zerop (DECL_INITIAL (decl))))
20804 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
20805 name = (*targetm.strip_name_encoding) (name);
20806 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
20809 /* Select section for constant in constant pool.
20811 On RS/6000, all constants are in the private read-only data area.
20812 However, if this is being placed in the TOC it must be output as a
20816 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
20817 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
20819 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20820 return toc_section;
20822 return read_only_private_data_section;
20825 /* Remove any trailing [DS] or the like from the symbol name. */
20827 static const char *
20828 rs6000_xcoff_strip_name_encoding (const char *name)
20833 len = strlen (name);
20834 if (name[len - 1] == ']')
20835 return ggc_alloc_string (name, len - 4);
20840 /* Section attributes. AIX is always PIC. */
20842 static unsigned int
20843 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
20845 unsigned int align;
20846 unsigned int flags = default_section_type_flags (decl, name, reloc);
20848 /* Align to at least UNIT size. */
20849 if (flags & SECTION_CODE)
20850 align = MIN_UNITS_PER_WORD;
20852 /* Increase alignment of large objects if not already stricter. */
20853 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
20854 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
20855 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
20857 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
20860 /* Output at beginning of assembler file.
20862 Initialize the section names for the RS/6000 at this point.
20864 Specify filename, including full path, to assembler.
20866 We want to go into the TOC section so at least one .toc will be emitted.
20867 Also, in order to output proper .bs/.es pairs, we need at least one static
20868 [RW] section emitted.
20870 Finally, declare mcount when profiling to make the assembler happy. */
20873 rs6000_xcoff_file_start (void)
20875 rs6000_gen_section_name (&xcoff_bss_section_name,
20876 main_input_filename, ".bss_");
20877 rs6000_gen_section_name (&xcoff_private_data_section_name,
20878 main_input_filename, ".rw_");
20879 rs6000_gen_section_name (&xcoff_read_only_section_name,
20880 main_input_filename, ".ro_");
20882 fputs ("\t.file\t", asm_out_file);
20883 output_quoted_string (asm_out_file, main_input_filename);
20884 fputc ('\n', asm_out_file);
20885 if (write_symbols != NO_DEBUG)
20886 switch_to_section (private_data_section);
20887 switch_to_section (text_section);
20889 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
20890 rs6000_file_start ();
20893 /* Output at end of assembler file.
20894 On the RS/6000, referencing data should automatically pull in text. */
20897 rs6000_xcoff_file_end (void)
20899 switch_to_section (text_section);
20900 fputs ("_section_.text:\n", asm_out_file);
20901 switch_to_section (data_section);
20902 fputs (TARGET_32BIT
20903 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20906 #endif /* TARGET_XCOFF */
20908 /* Compute a (partial) cost for rtx X. Return true if the complete
20909 cost has been computed, and false if subexpressions should be
20910 scanned. In either case, *TOTAL contains the cost result. */
20913 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
20915 enum machine_mode mode = GET_MODE (x);
20919 /* On the RS/6000, if it is valid in the insn, it is free. */
20921 if (((outer_code == SET
20922 || outer_code == PLUS
20923 || outer_code == MINUS)
20924 && (satisfies_constraint_I (x)
20925 || satisfies_constraint_L (x)))
20926 || (outer_code == AND
20927 && (satisfies_constraint_K (x)
20929 ? satisfies_constraint_L (x)
20930 : satisfies_constraint_J (x))
20931 || mask_operand (x, mode)
20933 && mask64_operand (x, DImode))))
20934 || ((outer_code == IOR || outer_code == XOR)
20935 && (satisfies_constraint_K (x)
20937 ? satisfies_constraint_L (x)
20938 : satisfies_constraint_J (x))))
20939 || outer_code == ASHIFT
20940 || outer_code == ASHIFTRT
20941 || outer_code == LSHIFTRT
20942 || outer_code == ROTATE
20943 || outer_code == ROTATERT
20944 || outer_code == ZERO_EXTRACT
20945 || (outer_code == MULT
20946 && satisfies_constraint_I (x))
20947 || ((outer_code == DIV || outer_code == UDIV
20948 || outer_code == MOD || outer_code == UMOD)
20949 && exact_log2 (INTVAL (x)) >= 0)
20950 || (outer_code == COMPARE
20951 && (satisfies_constraint_I (x)
20952 || satisfies_constraint_K (x)))
20953 || (outer_code == EQ
20954 && (satisfies_constraint_I (x)
20955 || satisfies_constraint_K (x)
20957 ? satisfies_constraint_L (x)
20958 : satisfies_constraint_J (x))))
20959 || (outer_code == GTU
20960 && satisfies_constraint_I (x))
20961 || (outer_code == LTU
20962 && satisfies_constraint_P (x)))
20967 else if ((outer_code == PLUS
20968 && reg_or_add_cint_operand (x, VOIDmode))
20969 || (outer_code == MINUS
20970 && reg_or_sub_cint_operand (x, VOIDmode))
20971 || ((outer_code == SET
20972 || outer_code == IOR
20973 || outer_code == XOR)
20975 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20977 *total = COSTS_N_INSNS (1);
20983 if (mode == DImode && code == CONST_DOUBLE)
20985 if ((outer_code == IOR || outer_code == XOR)
20986 && CONST_DOUBLE_HIGH (x) == 0
20987 && (CONST_DOUBLE_LOW (x)
20988 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20993 else if ((outer_code == AND && and64_2_operand (x, DImode))
20994 || ((outer_code == SET
20995 || outer_code == IOR
20996 || outer_code == XOR)
20997 && CONST_DOUBLE_HIGH (x) == 0))
20999 *total = COSTS_N_INSNS (1);
21009 /* When optimizing for size, MEM should be slightly more expensive
21010 than generating address, e.g., (plus (reg) (const)).
21011 L1 cache latency is about two instructions. */
21012 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
21020 if (mode == DFmode)
21022 if (GET_CODE (XEXP (x, 0)) == MULT)
21024 /* FNMA accounted in outer NEG. */
21025 if (outer_code == NEG)
21026 *total = rs6000_cost->dmul - rs6000_cost->fp;
21028 *total = rs6000_cost->dmul;
21031 *total = rs6000_cost->fp;
21033 else if (mode == SFmode)
21035 /* FNMA accounted in outer NEG. */
21036 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21039 *total = rs6000_cost->fp;
21042 *total = COSTS_N_INSNS (1);
21046 if (mode == DFmode)
21048 if (GET_CODE (XEXP (x, 0)) == MULT
21049 || GET_CODE (XEXP (x, 1)) == MULT)
21051 /* FNMA accounted in outer NEG. */
21052 if (outer_code == NEG)
21053 *total = rs6000_cost->dmul - rs6000_cost->fp;
21055 *total = rs6000_cost->dmul;
21058 *total = rs6000_cost->fp;
21060 else if (mode == SFmode)
21062 /* FNMA accounted in outer NEG. */
21063 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21066 *total = rs6000_cost->fp;
21069 *total = COSTS_N_INSNS (1);
21073 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21074 && satisfies_constraint_I (XEXP (x, 1)))
21076 if (INTVAL (XEXP (x, 1)) >= -256
21077 && INTVAL (XEXP (x, 1)) <= 255)
21078 *total = rs6000_cost->mulsi_const9;
21080 *total = rs6000_cost->mulsi_const;
21082 /* FMA accounted in outer PLUS/MINUS. */
21083 else if ((mode == DFmode || mode == SFmode)
21084 && (outer_code == PLUS || outer_code == MINUS))
21086 else if (mode == DFmode)
21087 *total = rs6000_cost->dmul;
21088 else if (mode == SFmode)
21089 *total = rs6000_cost->fp;
21090 else if (mode == DImode)
21091 *total = rs6000_cost->muldi;
21093 *total = rs6000_cost->mulsi;
21098 if (FLOAT_MODE_P (mode))
21100 *total = mode == DFmode ? rs6000_cost->ddiv
21101 : rs6000_cost->sdiv;
21108 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21109 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
21111 if (code == DIV || code == MOD)
21113 *total = COSTS_N_INSNS (2);
21116 *total = COSTS_N_INSNS (1);
21120 if (GET_MODE (XEXP (x, 1)) == DImode)
21121 *total = rs6000_cost->divdi;
21123 *total = rs6000_cost->divsi;
21125 /* Add in shift and subtract for MOD. */
21126 if (code == MOD || code == UMOD)
21127 *total += COSTS_N_INSNS (2);
21132 *total = COSTS_N_INSNS (4);
21136 *total = COSTS_N_INSNS (6);
21140 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
21152 *total = COSTS_N_INSNS (1);
21160 /* Handle mul_highpart. */
21161 if (outer_code == TRUNCATE
21162 && GET_CODE (XEXP (x, 0)) == MULT)
21164 if (mode == DImode)
21165 *total = rs6000_cost->muldi;
21167 *total = rs6000_cost->mulsi;
21170 else if (outer_code == AND)
21173 *total = COSTS_N_INSNS (1);
21178 if (GET_CODE (XEXP (x, 0)) == MEM)
21181 *total = COSTS_N_INSNS (1);
21187 if (!FLOAT_MODE_P (mode))
21189 *total = COSTS_N_INSNS (1);
21195 case UNSIGNED_FLOAT:
21198 case FLOAT_TRUNCATE:
21199 *total = rs6000_cost->fp;
21203 if (mode == DFmode)
21206 *total = rs6000_cost->fp;
21210 switch (XINT (x, 1))
21213 *total = rs6000_cost->fp;
21225 *total = COSTS_N_INSNS (1);
21228 else if (FLOAT_MODE_P (mode)
21229 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
21231 *total = rs6000_cost->fp;
21239 /* Carry bit requires mode == Pmode.
21240 NEG or PLUS already counted so only add one. */
21242 && (outer_code == NEG || outer_code == PLUS))
21244 *total = COSTS_N_INSNS (1);
21247 if (outer_code == SET)
21249 if (XEXP (x, 1) == const0_rtx)
21251 *total = COSTS_N_INSNS (2);
21254 else if (mode == Pmode)
21256 *total = COSTS_N_INSNS (3);
21265 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
21267 *total = COSTS_N_INSNS (2);
21271 if (outer_code == COMPARE)
21285 /* A C expression returning the cost of moving data from a register of class
21286 CLASS1 to one of CLASS2. */
21289 rs6000_register_move_cost (enum machine_mode mode,
21290 enum reg_class from, enum reg_class to)
21292 /* Moves from/to GENERAL_REGS. */
21293 if (reg_classes_intersect_p (to, GENERAL_REGS)
21294 || reg_classes_intersect_p (from, GENERAL_REGS))
21296 if (! reg_classes_intersect_p (to, GENERAL_REGS))
21299 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
21300 return (rs6000_memory_move_cost (mode, from, 0)
21301 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
21303 /* It's more expensive to move CR_REGS than CR0_REGS because of the
21305 else if (from == CR_REGS)
21309 /* A move will cost one instruction per GPR moved. */
21310 return 2 * hard_regno_nregs[0][mode];
21313 /* Moving between two similar registers is just one instruction. */
21314 else if (reg_classes_intersect_p (to, from))
21315 return (mode == TFmode || mode == TDmode) ? 4 : 2;
21317 /* Everything else has to go through GENERAL_REGS. */
21319 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
21320 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
21323 /* A C expressions returning the cost of moving data of MODE from a register to
21327 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
21328 int in ATTRIBUTE_UNUSED)
21330 if (reg_classes_intersect_p (class, GENERAL_REGS))
21331 return 4 * hard_regno_nregs[0][mode];
21332 else if (reg_classes_intersect_p (class, FLOAT_REGS))
21333 return 4 * hard_regno_nregs[32][mode];
21334 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
21335 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
21337 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
21340 /* Returns a code for a target-specific builtin that implements
21341 reciprocal of the function, or NULL_TREE if not available. */
21344 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
21345 bool sqrt ATTRIBUTE_UNUSED)
21347 if (! (TARGET_RECIP && TARGET_PPC_GFXOPT && !optimize_size
21348 && flag_finite_math_only && !flag_trapping_math
21349 && flag_unsafe_math_optimizations))
21357 case BUILT_IN_SQRTF:
21358 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
21365 /* Newton-Raphson approximation of single-precision floating point divide n/d.
21366 Assumes no trapping math and finite arguments. */
21369 rs6000_emit_swdivsf (rtx dst, rtx n, rtx d)
21371 rtx x0, e0, e1, y1, u0, v0, one;
21373 x0 = gen_reg_rtx (SFmode);
21374 e0 = gen_reg_rtx (SFmode);
21375 e1 = gen_reg_rtx (SFmode);
21376 y1 = gen_reg_rtx (SFmode);
21377 u0 = gen_reg_rtx (SFmode);
21378 v0 = gen_reg_rtx (SFmode);
21379 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21381 /* x0 = 1./d estimate */
21382 emit_insn (gen_rtx_SET (VOIDmode, x0,
21383 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
21385 /* e0 = 1. - d * x0 */
21386 emit_insn (gen_rtx_SET (VOIDmode, e0,
21387 gen_rtx_MINUS (SFmode, one,
21388 gen_rtx_MULT (SFmode, d, x0))));
21389 /* e1 = e0 + e0 * e0 */
21390 emit_insn (gen_rtx_SET (VOIDmode, e1,
21391 gen_rtx_PLUS (SFmode,
21392 gen_rtx_MULT (SFmode, e0, e0), e0)));
21393 /* y1 = x0 + e1 * x0 */
21394 emit_insn (gen_rtx_SET (VOIDmode, y1,
21395 gen_rtx_PLUS (SFmode,
21396 gen_rtx_MULT (SFmode, e1, x0), x0)));
21398 emit_insn (gen_rtx_SET (VOIDmode, u0,
21399 gen_rtx_MULT (SFmode, n, y1)));
21400 /* v0 = n - d * u0 */
21401 emit_insn (gen_rtx_SET (VOIDmode, v0,
21402 gen_rtx_MINUS (SFmode, n,
21403 gen_rtx_MULT (SFmode, d, u0))));
21404 /* dst = u0 + v0 * y1 */
21405 emit_insn (gen_rtx_SET (VOIDmode, dst,
21406 gen_rtx_PLUS (SFmode,
21407 gen_rtx_MULT (SFmode, v0, y1), u0)));
21410 /* Newton-Raphson approximation of double-precision floating point divide n/d.
21411 Assumes no trapping math and finite arguments. */
21414 rs6000_emit_swdivdf (rtx dst, rtx n, rtx d)
21416 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
21418 x0 = gen_reg_rtx (DFmode);
21419 e0 = gen_reg_rtx (DFmode);
21420 e1 = gen_reg_rtx (DFmode);
21421 e2 = gen_reg_rtx (DFmode);
21422 y1 = gen_reg_rtx (DFmode);
21423 y2 = gen_reg_rtx (DFmode);
21424 y3 = gen_reg_rtx (DFmode);
21425 u0 = gen_reg_rtx (DFmode);
21426 v0 = gen_reg_rtx (DFmode);
21427 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
21429 /* x0 = 1./d estimate */
21430 emit_insn (gen_rtx_SET (VOIDmode, x0,
21431 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
21433 /* e0 = 1. - d * x0 */
21434 emit_insn (gen_rtx_SET (VOIDmode, e0,
21435 gen_rtx_MINUS (DFmode, one,
21436 gen_rtx_MULT (SFmode, d, x0))));
21437 /* y1 = x0 + e0 * x0 */
21438 emit_insn (gen_rtx_SET (VOIDmode, y1,
21439 gen_rtx_PLUS (DFmode,
21440 gen_rtx_MULT (DFmode, e0, x0), x0)));
21442 emit_insn (gen_rtx_SET (VOIDmode, e1,
21443 gen_rtx_MULT (DFmode, e0, e0)));
21444 /* y2 = y1 + e1 * y1 */
21445 emit_insn (gen_rtx_SET (VOIDmode, y2,
21446 gen_rtx_PLUS (DFmode,
21447 gen_rtx_MULT (DFmode, e1, y1), y1)));
21449 emit_insn (gen_rtx_SET (VOIDmode, e2,
21450 gen_rtx_MULT (DFmode, e1, e1)));
21451 /* y3 = y2 + e2 * y2 */
21452 emit_insn (gen_rtx_SET (VOIDmode, y3,
21453 gen_rtx_PLUS (DFmode,
21454 gen_rtx_MULT (DFmode, e2, y2), y2)));
21456 emit_insn (gen_rtx_SET (VOIDmode, u0,
21457 gen_rtx_MULT (DFmode, n, y3)));
21458 /* v0 = n - d * u0 */
21459 emit_insn (gen_rtx_SET (VOIDmode, v0,
21460 gen_rtx_MINUS (DFmode, n,
21461 gen_rtx_MULT (DFmode, d, u0))));
21462 /* dst = u0 + v0 * y3 */
21463 emit_insn (gen_rtx_SET (VOIDmode, dst,
21464 gen_rtx_PLUS (DFmode,
21465 gen_rtx_MULT (DFmode, v0, y3), u0)));
21469 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21470 Assumes no trapping math and finite arguments. */
21473 rs6000_emit_swrsqrtsf (rtx dst, rtx src)
21475 rtx x0, x1, x2, y1, u0, u1, u2, v0, v1, v2, t0,
21476 half, one, halfthree, c1, cond, label;
21478 x0 = gen_reg_rtx (SFmode);
21479 x1 = gen_reg_rtx (SFmode);
21480 x2 = gen_reg_rtx (SFmode);
21481 y1 = gen_reg_rtx (SFmode);
21482 u0 = gen_reg_rtx (SFmode);
21483 u1 = gen_reg_rtx (SFmode);
21484 u2 = gen_reg_rtx (SFmode);
21485 v0 = gen_reg_rtx (SFmode);
21486 v1 = gen_reg_rtx (SFmode);
21487 v2 = gen_reg_rtx (SFmode);
21488 t0 = gen_reg_rtx (SFmode);
21489 halfthree = gen_reg_rtx (SFmode);
21490 cond = gen_rtx_REG (CCFPmode, CR1_REGNO);
21491 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
21493 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
21494 emit_insn (gen_rtx_SET (VOIDmode, t0,
21495 gen_rtx_MULT (SFmode, src, src)));
21497 emit_insn (gen_rtx_SET (VOIDmode, cond,
21498 gen_rtx_COMPARE (CCFPmode, t0, src)));
21499 c1 = gen_rtx_EQ (VOIDmode, cond, const0_rtx);
21500 emit_unlikely_jump (c1, label);
21502 half = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode));
21503 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21505 /* halfthree = 1.5 = 1.0 + 0.5 */
21506 emit_insn (gen_rtx_SET (VOIDmode, halfthree,
21507 gen_rtx_PLUS (SFmode, one, half)));
21509 /* x0 = rsqrt estimate */
21510 emit_insn (gen_rtx_SET (VOIDmode, x0,
21511 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, src),
21514 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
21515 emit_insn (gen_rtx_SET (VOIDmode, y1,
21516 gen_rtx_MINUS (SFmode,
21517 gen_rtx_MULT (SFmode, src, halfthree),
21520 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
21521 emit_insn (gen_rtx_SET (VOIDmode, u0,
21522 gen_rtx_MULT (SFmode, x0, x0)));
21523 emit_insn (gen_rtx_SET (VOIDmode, v0,
21524 gen_rtx_MINUS (SFmode,
21526 gen_rtx_MULT (SFmode, y1, u0))));
21527 emit_insn (gen_rtx_SET (VOIDmode, x1,
21528 gen_rtx_MULT (SFmode, x0, v0)));
21530 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
21531 emit_insn (gen_rtx_SET (VOIDmode, u1,
21532 gen_rtx_MULT (SFmode, x1, x1)));
21533 emit_insn (gen_rtx_SET (VOIDmode, v1,
21534 gen_rtx_MINUS (SFmode,
21536 gen_rtx_MULT (SFmode, y1, u1))));
21537 emit_insn (gen_rtx_SET (VOIDmode, x2,
21538 gen_rtx_MULT (SFmode, x1, v1)));
21540 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
21541 emit_insn (gen_rtx_SET (VOIDmode, u2,
21542 gen_rtx_MULT (SFmode, x2, x2)));
21543 emit_insn (gen_rtx_SET (VOIDmode, v2,
21544 gen_rtx_MINUS (SFmode,
21546 gen_rtx_MULT (SFmode, y1, u2))));
21547 emit_insn (gen_rtx_SET (VOIDmode, dst,
21548 gen_rtx_MULT (SFmode, x2, v2)));
21550 emit_label (XEXP (label, 0));
21553 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
21554 target, and SRC is the argument operand. */
21557 rs6000_emit_popcount (rtx dst, rtx src)
21559 enum machine_mode mode = GET_MODE (dst);
21562 tmp1 = gen_reg_rtx (mode);
21564 if (mode == SImode)
21566 emit_insn (gen_popcntbsi2 (tmp1, src));
21567 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
21569 tmp2 = force_reg (SImode, tmp2);
21570 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
21574 emit_insn (gen_popcntbdi2 (tmp1, src));
21575 tmp2 = expand_mult (DImode, tmp1,
21576 GEN_INT ((HOST_WIDE_INT)
21577 0x01010101 << 32 | 0x01010101),
21579 tmp2 = force_reg (DImode, tmp2);
21580 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
21585 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
21586 target, and SRC is the argument operand. */
21589 rs6000_emit_parity (rtx dst, rtx src)
21591 enum machine_mode mode = GET_MODE (dst);
21594 tmp = gen_reg_rtx (mode);
21595 if (mode == SImode)
21597 /* Is mult+shift >= shift+xor+shift+xor? */
21598 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
21600 rtx tmp1, tmp2, tmp3, tmp4;
21602 tmp1 = gen_reg_rtx (SImode);
21603 emit_insn (gen_popcntbsi2 (tmp1, src));
21605 tmp2 = gen_reg_rtx (SImode);
21606 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
21607 tmp3 = gen_reg_rtx (SImode);
21608 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
21610 tmp4 = gen_reg_rtx (SImode);
21611 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
21612 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
21615 rs6000_emit_popcount (tmp, src);
21616 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
21620 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
21621 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
21623 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
21625 tmp1 = gen_reg_rtx (DImode);
21626 emit_insn (gen_popcntbdi2 (tmp1, src));
21628 tmp2 = gen_reg_rtx (DImode);
21629 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
21630 tmp3 = gen_reg_rtx (DImode);
21631 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
21633 tmp4 = gen_reg_rtx (DImode);
21634 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
21635 tmp5 = gen_reg_rtx (DImode);
21636 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
21638 tmp6 = gen_reg_rtx (DImode);
21639 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
21640 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
21643 rs6000_emit_popcount (tmp, src);
21644 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
21648 /* Return an RTX representing where to find the function value of a
21649 function returning MODE. */
21651 rs6000_complex_function_value (enum machine_mode mode)
21653 unsigned int regno;
21655 enum machine_mode inner = GET_MODE_INNER (mode);
21656 unsigned int inner_bytes = GET_MODE_SIZE (inner);
21658 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
21659 regno = FP_ARG_RETURN;
21662 regno = GP_ARG_RETURN;
21664 /* 32-bit is OK since it'll go in r3/r4. */
21665 if (TARGET_32BIT && inner_bytes >= 4)
21666 return gen_rtx_REG (mode, regno);
21669 if (inner_bytes >= 8)
21670 return gen_rtx_REG (mode, regno);
21672 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
21674 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
21675 GEN_INT (inner_bytes));
21676 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
21679 /* Define how to find the value returned by a function.
21680 VALTYPE is the data type of the value (as a tree).
21681 If the precise function being called is known, FUNC is its FUNCTION_DECL;
21682 otherwise, FUNC is 0.
21684 On the SPE, both FPs and vectors are returned in r3.
21686 On RS/6000 an integer value is in r3 and a floating-point value is in
21687 fp1, unless -msoft-float. */
21690 rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
21692 enum machine_mode mode;
21693 unsigned int regno;
21695 /* Special handling for structs in darwin64. */
21696 if (rs6000_darwin64_abi
21697 && TYPE_MODE (valtype) == BLKmode
21698 && TREE_CODE (valtype) == RECORD_TYPE
21699 && int_size_in_bytes (valtype) > 0)
21701 CUMULATIVE_ARGS valcum;
21705 valcum.fregno = FP_ARG_MIN_REG;
21706 valcum.vregno = ALTIVEC_ARG_MIN_REG;
21707 /* Do a trial code generation as if this were going to be passed as
21708 an argument; if any part goes in memory, we return NULL. */
21709 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
21712 /* Otherwise fall through to standard ABI rules. */
21715 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
21717 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21718 return gen_rtx_PARALLEL (DImode,
21720 gen_rtx_EXPR_LIST (VOIDmode,
21721 gen_rtx_REG (SImode, GP_ARG_RETURN),
21723 gen_rtx_EXPR_LIST (VOIDmode,
21724 gen_rtx_REG (SImode,
21725 GP_ARG_RETURN + 1),
21728 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
21730 return gen_rtx_PARALLEL (DCmode,
21732 gen_rtx_EXPR_LIST (VOIDmode,
21733 gen_rtx_REG (SImode, GP_ARG_RETURN),
21735 gen_rtx_EXPR_LIST (VOIDmode,
21736 gen_rtx_REG (SImode,
21737 GP_ARG_RETURN + 1),
21739 gen_rtx_EXPR_LIST (VOIDmode,
21740 gen_rtx_REG (SImode,
21741 GP_ARG_RETURN + 2),
21743 gen_rtx_EXPR_LIST (VOIDmode,
21744 gen_rtx_REG (SImode,
21745 GP_ARG_RETURN + 3),
21749 mode = TYPE_MODE (valtype);
21750 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
21751 || POINTER_TYPE_P (valtype))
21752 mode = TARGET_32BIT ? SImode : DImode;
21754 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
21755 /* _Decimal128 must use an even/odd register pair. */
21756 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
21757 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
21758 regno = FP_ARG_RETURN;
21759 else if (TREE_CODE (valtype) == COMPLEX_TYPE
21760 && targetm.calls.split_complex_arg)
21761 return rs6000_complex_function_value (mode);
21762 else if (TREE_CODE (valtype) == VECTOR_TYPE
21763 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
21764 && ALTIVEC_VECTOR_MODE (mode))
21765 regno = ALTIVEC_ARG_RETURN;
21766 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
21767 && (mode == DFmode || mode == DDmode || mode == DCmode
21768 || mode == TFmode || mode == TDmode || mode == TCmode))
21769 return spe_build_register_parallel (mode, GP_ARG_RETURN);
21771 regno = GP_ARG_RETURN;
21773 return gen_rtx_REG (mode, regno);
21776 /* Define how to find the value returned by a library function
21777 assuming the value has mode MODE. */
21779 rs6000_libcall_value (enum machine_mode mode)
21781 unsigned int regno;
21783 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
21785 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21786 return gen_rtx_PARALLEL (DImode,
21788 gen_rtx_EXPR_LIST (VOIDmode,
21789 gen_rtx_REG (SImode, GP_ARG_RETURN),
21791 gen_rtx_EXPR_LIST (VOIDmode,
21792 gen_rtx_REG (SImode,
21793 GP_ARG_RETURN + 1),
21797 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
21798 /* _Decimal128 must use an even/odd register pair. */
21799 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
21800 else if (SCALAR_FLOAT_MODE_P (mode)
21801 && TARGET_HARD_FLOAT && TARGET_FPRS)
21802 regno = FP_ARG_RETURN;
21803 else if (ALTIVEC_VECTOR_MODE (mode)
21804 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
21805 regno = ALTIVEC_ARG_RETURN;
21806 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
21807 return rs6000_complex_function_value (mode);
21808 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
21809 && (mode == DFmode || mode == DDmode || mode == DCmode
21810 || mode == TFmode || mode == TDmode || mode == TCmode))
21811 return spe_build_register_parallel (mode, GP_ARG_RETURN);
21813 regno = GP_ARG_RETURN;
21815 return gen_rtx_REG (mode, regno);
21818 /* Define the offset between two registers, FROM to be eliminated and its
21819 replacement TO, at the start of a routine. */
21821 rs6000_initial_elimination_offset (int from, int to)
21823 rs6000_stack_t *info = rs6000_stack_info ();
21824 HOST_WIDE_INT offset;
21826 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21827 offset = info->push_p ? 0 : -info->total_size;
21828 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21830 offset = info->push_p ? 0 : -info->total_size;
21831 if (FRAME_GROWS_DOWNWARD)
21832 offset += info->fixed_size + info->vars_size + info->parm_size;
21834 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
21835 offset = FRAME_GROWS_DOWNWARD
21836 ? info->fixed_size + info->vars_size + info->parm_size
21838 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
21839 offset = info->total_size;
21840 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21841 offset = info->push_p ? info->total_size : 0;
21842 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
21845 gcc_unreachable ();
21850 /* Return true if TYPE is a SPE or AltiVec opaque type. */
21853 rs6000_is_opaque_type (const_tree type)
21855 return (type == opaque_V2SI_type_node
21856 || type == opaque_V2SF_type_node
21857 || type == opaque_p_V2SI_type_node
21858 || type == opaque_V4SI_type_node);
21862 rs6000_dwarf_register_span (rtx reg)
21867 && (SPE_VECTOR_MODE (GET_MODE (reg))
21868 || (TARGET_E500_DOUBLE
21869 && (GET_MODE (reg) == DFmode || GET_MODE (reg) == DDmode))))
21874 regno = REGNO (reg);
21876 /* The duality of the SPE register size wreaks all kinds of havoc.
21877 This is a way of distinguishing r0 in 32-bits from r0 in
21880 gen_rtx_PARALLEL (VOIDmode,
21883 gen_rtx_REG (SImode, regno + 1200),
21884 gen_rtx_REG (SImode, regno))
21886 gen_rtx_REG (SImode, regno),
21887 gen_rtx_REG (SImode, regno + 1200)));
21890 /* Fill in sizes for SPE register high parts in table used by unwinder. */
21893 rs6000_init_dwarf_reg_sizes_extra (tree address)
21898 enum machine_mode mode = TYPE_MODE (char_type_node);
21899 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
21900 rtx mem = gen_rtx_MEM (BLKmode, addr);
21901 rtx value = gen_int_mode (4, mode);
21903 for (i = 1201; i < 1232; i++)
21905 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
21906 HOST_WIDE_INT offset
21907 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
21909 emit_move_insn (adjust_address (mem, mode, offset), value);
21914 /* Map internal gcc register numbers to DWARF2 register numbers. */
21917 rs6000_dbx_register_number (unsigned int regno)
21919 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
21921 if (regno == MQ_REGNO)
21923 if (regno == LR_REGNO)
21925 if (regno == CTR_REGNO)
21927 if (CR_REGNO_P (regno))
21928 return regno - CR0_REGNO + 86;
21929 if (regno == XER_REGNO)
21931 if (ALTIVEC_REGNO_P (regno))
21932 return regno - FIRST_ALTIVEC_REGNO + 1124;
21933 if (regno == VRSAVE_REGNO)
21935 if (regno == VSCR_REGNO)
21937 if (regno == SPE_ACC_REGNO)
21939 if (regno == SPEFSCR_REGNO)
21941 /* SPE high reg number. We get these values of regno from
21942 rs6000_dwarf_register_span. */
21943 gcc_assert (regno >= 1200 && regno < 1232);
21947 /* target hook eh_return_filter_mode */
21948 static enum machine_mode
21949 rs6000_eh_return_filter_mode (void)
21951 return TARGET_32BIT ? SImode : word_mode;
21954 /* Target hook for scalar_mode_supported_p. */
21956 rs6000_scalar_mode_supported_p (enum machine_mode mode)
21958 if (DECIMAL_FLOAT_MODE_P (mode))
21961 return default_scalar_mode_supported_p (mode);
21964 /* Target hook for vector_mode_supported_p. */
21966 rs6000_vector_mode_supported_p (enum machine_mode mode)
21969 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
21972 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
21975 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
21982 /* Target hook for invalid_arg_for_unprototyped_fn. */
21983 static const char *
21984 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
21986 return (!rs6000_darwin64_abi
21988 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
21989 && (funcdecl == NULL_TREE
21990 || (TREE_CODE (funcdecl) == FUNCTION_DECL
21991 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
21992 ? N_("AltiVec argument passed to unprototyped function")
21996 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21997 setup by using __stack_chk_fail_local hidden function instead of
21998 calling __stack_chk_fail directly. Otherwise it is better to call
21999 __stack_chk_fail directly. */
22002 rs6000_stack_protect_fail (void)
22004 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
22005 ? default_hidden_stack_protect_fail ()
22006 : default_external_stack_protect_fail ();
22009 #include "gt-rs6000.h"