1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 static GTY(()) bool rs6000_cell_dont_microcode;
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups;
150 /* Align branch targets. */
151 static GTY(()) bool rs6000_align_branch_targets;
153 /* Support for -msched-costly-dep option. */
154 const char *rs6000_sched_costly_dep_str;
155 enum rs6000_dependence_cost rs6000_sched_costly_dep;
157 /* Support for -minsert-sched-nops option. */
158 const char *rs6000_sched_insert_nops_str;
159 enum rs6000_nop_insertion rs6000_sched_insert_nops;
161 /* Support targetm.vectorize.builtin_mask_for_load. */
162 static GTY(()) tree altivec_builtin_mask_for_load;
164 /* Size of long double. */
165 int rs6000_long_double_type_size;
167 /* IEEE quad extended precision long double. */
170 /* Whether -mabi=altivec has appeared. */
171 int rs6000_altivec_abi;
173 /* Nonzero if we want SPE ABI extensions. */
176 /* Nonzero if floating point operations are done in the GPRs. */
177 int rs6000_float_gprs = 0;
179 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
180 int rs6000_darwin64_abi;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Save information from a "cmpxx" operation until the branch or scc is
187 rtx rs6000_compare_op0, rs6000_compare_op1;
188 int rs6000_compare_fp_p;
190 /* Label number of label created for -mrelocatable, to call to so we can
191 get the address of the GOT section */
192 int rs6000_pic_labelno;
195 /* Which abi to adhere to */
196 const char *rs6000_abi_name;
198 /* Semantics of the small data area */
199 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
201 /* Which small data model to use */
202 const char *rs6000_sdata_name = (char *)0;
204 /* Counter for labels which are to be placed in .fixup. */
205 int fixuplabelno = 0;
208 /* Bit size of immediate TLS offsets and string from which it is decoded. */
209 int rs6000_tls_size = 32;
210 const char *rs6000_tls_size_string;
212 /* ABI enumeration available for subtarget to use. */
213 enum rs6000_abi rs6000_current_abi;
215 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
219 const char *rs6000_debug_name;
220 int rs6000_debug_stack; /* debug stack applications */
221 int rs6000_debug_arg; /* debug argument handling */
223 /* Value is TRUE if register/mode pair is acceptable. */
224 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Built in types. */
228 tree rs6000_builtin_types[RS6000_BTI_MAX];
229 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
231 const char *rs6000_traceback_name;
233 traceback_default = 0,
239 /* Flag to say the TOC is initialized */
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *read_only_private_data_section;
250 static GTY(()) section *sdata2_section;
251 static GTY(()) section *toc_section;
253 /* Control alignment for fields within structures. */
254 /* String from -malign-XXXXX. */
255 int rs6000_alignment_flags;
257 /* True for any options that were explicitly set. */
259 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
260 bool alignment; /* True if -malign- was used. */
261 bool abi; /* True if -mabi=spe/nospe was used. */
262 bool spe; /* True if -mspe= was used. */
263 bool float_gprs; /* True if -mfloat-gprs= was used. */
264 bool isel; /* True if -misel was used. */
265 bool long_double; /* True if -mlong-double- was used. */
266 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
267 } rs6000_explicit_options;
269 struct builtin_description
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
280 /* Target cpu costs. */
282 struct processor_costs {
283 const int mulsi; /* cost of SImode multiplication. */
284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
293 const int cache_line_size; /* cache block in bytes. */
294 const int l1_cache_lines; /* number of lines in L1 cache. */
295 const int simultaneous_prefetches; /* number of parallel prefetch
299 const struct processor_costs *rs6000_cost;
301 /* Processor costs (relative to an add) */
303 /* Instruction size costs on 32bit processors. */
305 struct processor_costs size32_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
321 /* Instruction size costs on 64bit processors. */
323 struct processor_costs size64_cost = {
324 COSTS_N_INSNS (1), /* mulsi */
325 COSTS_N_INSNS (1), /* mulsi_const */
326 COSTS_N_INSNS (1), /* mulsi_const9 */
327 COSTS_N_INSNS (1), /* muldi */
328 COSTS_N_INSNS (1), /* divsi */
329 COSTS_N_INSNS (1), /* divdi */
330 COSTS_N_INSNS (1), /* fp */
331 COSTS_N_INSNS (1), /* dmul */
332 COSTS_N_INSNS (1), /* sdiv */
333 COSTS_N_INSNS (1), /* ddiv */
339 /* Instruction costs on RIOS1 processors. */
341 struct processor_costs rios1_cost = {
342 COSTS_N_INSNS (5), /* mulsi */
343 COSTS_N_INSNS (4), /* mulsi_const */
344 COSTS_N_INSNS (3), /* mulsi_const9 */
345 COSTS_N_INSNS (5), /* muldi */
346 COSTS_N_INSNS (19), /* divsi */
347 COSTS_N_INSNS (19), /* divdi */
348 COSTS_N_INSNS (2), /* fp */
349 COSTS_N_INSNS (2), /* dmul */
350 COSTS_N_INSNS (19), /* sdiv */
351 COSTS_N_INSNS (19), /* ddiv */
353 1024, /* cache lines */
357 /* Instruction costs on RIOS2 processors. */
359 struct processor_costs rios2_cost = {
360 COSTS_N_INSNS (2), /* mulsi */
361 COSTS_N_INSNS (2), /* mulsi_const */
362 COSTS_N_INSNS (2), /* mulsi_const9 */
363 COSTS_N_INSNS (2), /* muldi */
364 COSTS_N_INSNS (13), /* divsi */
365 COSTS_N_INSNS (13), /* divdi */
366 COSTS_N_INSNS (2), /* fp */
367 COSTS_N_INSNS (2), /* dmul */
368 COSTS_N_INSNS (17), /* sdiv */
369 COSTS_N_INSNS (17), /* ddiv */
371 1024, /* cache lines */
375 /* Instruction costs on RS64A processors. */
377 struct processor_costs rs64a_cost = {
378 COSTS_N_INSNS (20), /* mulsi */
379 COSTS_N_INSNS (12), /* mulsi_const */
380 COSTS_N_INSNS (8), /* mulsi_const9 */
381 COSTS_N_INSNS (34), /* muldi */
382 COSTS_N_INSNS (65), /* divsi */
383 COSTS_N_INSNS (67), /* divdi */
384 COSTS_N_INSNS (4), /* fp */
385 COSTS_N_INSNS (4), /* dmul */
386 COSTS_N_INSNS (31), /* sdiv */
387 COSTS_N_INSNS (31), /* ddiv */
389 1024, /* cache lines */
393 /* Instruction costs on MPCCORE processors. */
395 struct processor_costs mpccore_cost = {
396 COSTS_N_INSNS (2), /* mulsi */
397 COSTS_N_INSNS (2), /* mulsi_const */
398 COSTS_N_INSNS (2), /* mulsi_const9 */
399 COSTS_N_INSNS (2), /* muldi */
400 COSTS_N_INSNS (6), /* divsi */
401 COSTS_N_INSNS (6), /* divdi */
402 COSTS_N_INSNS (4), /* fp */
403 COSTS_N_INSNS (5), /* dmul */
404 COSTS_N_INSNS (10), /* sdiv */
405 COSTS_N_INSNS (17), /* ddiv */
407 512, /* cache lines */
411 /* Instruction costs on PPC403 processors. */
413 struct processor_costs ppc403_cost = {
414 COSTS_N_INSNS (4), /* mulsi */
415 COSTS_N_INSNS (4), /* mulsi_const */
416 COSTS_N_INSNS (4), /* mulsi_const9 */
417 COSTS_N_INSNS (4), /* muldi */
418 COSTS_N_INSNS (33), /* divsi */
419 COSTS_N_INSNS (33), /* divdi */
420 COSTS_N_INSNS (11), /* fp */
421 COSTS_N_INSNS (11), /* dmul */
422 COSTS_N_INSNS (11), /* sdiv */
423 COSTS_N_INSNS (11), /* ddiv */
425 128, /* cache lines */
429 /* Instruction costs on PPC405 processors. */
431 struct processor_costs ppc405_cost = {
432 COSTS_N_INSNS (5), /* mulsi */
433 COSTS_N_INSNS (4), /* mulsi_const */
434 COSTS_N_INSNS (3), /* mulsi_const9 */
435 COSTS_N_INSNS (5), /* muldi */
436 COSTS_N_INSNS (35), /* divsi */
437 COSTS_N_INSNS (35), /* divdi */
438 COSTS_N_INSNS (11), /* fp */
439 COSTS_N_INSNS (11), /* dmul */
440 COSTS_N_INSNS (11), /* sdiv */
441 COSTS_N_INSNS (11), /* ddiv */
443 512, /* cache lines */
447 /* Instruction costs on PPC440 processors. */
449 struct processor_costs ppc440_cost = {
450 COSTS_N_INSNS (3), /* mulsi */
451 COSTS_N_INSNS (2), /* mulsi_const */
452 COSTS_N_INSNS (2), /* mulsi_const9 */
453 COSTS_N_INSNS (3), /* muldi */
454 COSTS_N_INSNS (34), /* divsi */
455 COSTS_N_INSNS (34), /* divdi */
456 COSTS_N_INSNS (5), /* fp */
457 COSTS_N_INSNS (5), /* dmul */
458 COSTS_N_INSNS (19), /* sdiv */
459 COSTS_N_INSNS (33), /* ddiv */
461 1024, /* cache lines */
465 /* Instruction costs on PPC601 processors. */
467 struct processor_costs ppc601_cost = {
468 COSTS_N_INSNS (5), /* mulsi */
469 COSTS_N_INSNS (5), /* mulsi_const */
470 COSTS_N_INSNS (5), /* mulsi_const9 */
471 COSTS_N_INSNS (5), /* muldi */
472 COSTS_N_INSNS (36), /* divsi */
473 COSTS_N_INSNS (36), /* divdi */
474 COSTS_N_INSNS (4), /* fp */
475 COSTS_N_INSNS (5), /* dmul */
476 COSTS_N_INSNS (17), /* sdiv */
477 COSTS_N_INSNS (31), /* ddiv */
479 1024, /* cache lines */
483 /* Instruction costs on PPC603 processors. */
485 struct processor_costs ppc603_cost = {
486 COSTS_N_INSNS (5), /* mulsi */
487 COSTS_N_INSNS (3), /* mulsi_const */
488 COSTS_N_INSNS (2), /* mulsi_const9 */
489 COSTS_N_INSNS (5), /* muldi */
490 COSTS_N_INSNS (37), /* divsi */
491 COSTS_N_INSNS (37), /* divdi */
492 COSTS_N_INSNS (3), /* fp */
493 COSTS_N_INSNS (4), /* dmul */
494 COSTS_N_INSNS (18), /* sdiv */
495 COSTS_N_INSNS (33), /* ddiv */
497 256, /* cache lines */
501 /* Instruction costs on PPC604 processors. */
503 struct processor_costs ppc604_cost = {
504 COSTS_N_INSNS (4), /* mulsi */
505 COSTS_N_INSNS (4), /* mulsi_const */
506 COSTS_N_INSNS (4), /* mulsi_const9 */
507 COSTS_N_INSNS (4), /* muldi */
508 COSTS_N_INSNS (20), /* divsi */
509 COSTS_N_INSNS (20), /* divdi */
510 COSTS_N_INSNS (3), /* fp */
511 COSTS_N_INSNS (3), /* dmul */
512 COSTS_N_INSNS (18), /* sdiv */
513 COSTS_N_INSNS (32), /* ddiv */
515 512, /* cache lines */
519 /* Instruction costs on PPC604e processors. */
521 struct processor_costs ppc604e_cost = {
522 COSTS_N_INSNS (2), /* mulsi */
523 COSTS_N_INSNS (2), /* mulsi_const */
524 COSTS_N_INSNS (2), /* mulsi_const9 */
525 COSTS_N_INSNS (2), /* muldi */
526 COSTS_N_INSNS (20), /* divsi */
527 COSTS_N_INSNS (20), /* divdi */
528 COSTS_N_INSNS (3), /* fp */
529 COSTS_N_INSNS (3), /* dmul */
530 COSTS_N_INSNS (18), /* sdiv */
531 COSTS_N_INSNS (32), /* ddiv */
533 1024, /* cache lines */
537 /* Instruction costs on PPC620 processors. */
539 struct processor_costs ppc620_cost = {
540 COSTS_N_INSNS (5), /* mulsi */
541 COSTS_N_INSNS (4), /* mulsi_const */
542 COSTS_N_INSNS (3), /* mulsi_const9 */
543 COSTS_N_INSNS (7), /* muldi */
544 COSTS_N_INSNS (21), /* divsi */
545 COSTS_N_INSNS (37), /* divdi */
546 COSTS_N_INSNS (3), /* fp */
547 COSTS_N_INSNS (3), /* dmul */
548 COSTS_N_INSNS (18), /* sdiv */
549 COSTS_N_INSNS (32), /* ddiv */
551 512, /* cache lines */
555 /* Instruction costs on PPC630 processors. */
557 struct processor_costs ppc630_cost = {
558 COSTS_N_INSNS (5), /* mulsi */
559 COSTS_N_INSNS (4), /* mulsi_const */
560 COSTS_N_INSNS (3), /* mulsi_const9 */
561 COSTS_N_INSNS (7), /* muldi */
562 COSTS_N_INSNS (21), /* divsi */
563 COSTS_N_INSNS (37), /* divdi */
564 COSTS_N_INSNS (3), /* fp */
565 COSTS_N_INSNS (3), /* dmul */
566 COSTS_N_INSNS (17), /* sdiv */
567 COSTS_N_INSNS (21), /* ddiv */
569 512, /* cache lines */
573 /* Instruction costs on Cell processor. */
574 /* COSTS_N_INSNS (1) ~ one add. */
576 struct processor_costs ppccell_cost = {
577 COSTS_N_INSNS (9/2)+2, /* mulsi */
578 COSTS_N_INSNS (6/2), /* mulsi_const */
579 COSTS_N_INSNS (6/2), /* mulsi_const9 */
580 COSTS_N_INSNS (15/2)+2, /* muldi */
581 COSTS_N_INSNS (38/2), /* divsi */
582 COSTS_N_INSNS (70/2), /* divdi */
583 COSTS_N_INSNS (10/2), /* fp */
584 COSTS_N_INSNS (10/2), /* dmul */
585 COSTS_N_INSNS (74/2), /* sdiv */
586 COSTS_N_INSNS (74/2), /* ddiv */
588 256, /* cache lines */
592 /* Instruction costs on PPC750 and PPC7400 processors. */
594 struct processor_costs ppc750_cost = {
595 COSTS_N_INSNS (5), /* mulsi */
596 COSTS_N_INSNS (3), /* mulsi_const */
597 COSTS_N_INSNS (2), /* mulsi_const9 */
598 COSTS_N_INSNS (5), /* muldi */
599 COSTS_N_INSNS (17), /* divsi */
600 COSTS_N_INSNS (17), /* divdi */
601 COSTS_N_INSNS (3), /* fp */
602 COSTS_N_INSNS (3), /* dmul */
603 COSTS_N_INSNS (17), /* sdiv */
604 COSTS_N_INSNS (31), /* ddiv */
606 1024, /* cache lines */
610 /* Instruction costs on PPC7450 processors. */
612 struct processor_costs ppc7450_cost = {
613 COSTS_N_INSNS (4), /* mulsi */
614 COSTS_N_INSNS (3), /* mulsi_const */
615 COSTS_N_INSNS (3), /* mulsi_const9 */
616 COSTS_N_INSNS (4), /* muldi */
617 COSTS_N_INSNS (23), /* divsi */
618 COSTS_N_INSNS (23), /* divdi */
619 COSTS_N_INSNS (5), /* fp */
620 COSTS_N_INSNS (5), /* dmul */
621 COSTS_N_INSNS (21), /* sdiv */
622 COSTS_N_INSNS (35), /* ddiv */
624 1024, /* cache lines */
628 /* Instruction costs on PPC8540 processors. */
630 struct processor_costs ppc8540_cost = {
631 COSTS_N_INSNS (4), /* mulsi */
632 COSTS_N_INSNS (4), /* mulsi_const */
633 COSTS_N_INSNS (4), /* mulsi_const9 */
634 COSTS_N_INSNS (4), /* muldi */
635 COSTS_N_INSNS (19), /* divsi */
636 COSTS_N_INSNS (19), /* divdi */
637 COSTS_N_INSNS (4), /* fp */
638 COSTS_N_INSNS (4), /* dmul */
639 COSTS_N_INSNS (29), /* sdiv */
640 COSTS_N_INSNS (29), /* ddiv */
642 1024, /* cache lines */
643 1, /* prefetch streams /*/
646 /* Instruction costs on POWER4 and POWER5 processors. */
648 struct processor_costs power4_cost = {
649 COSTS_N_INSNS (3), /* mulsi */
650 COSTS_N_INSNS (2), /* mulsi_const */
651 COSTS_N_INSNS (2), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (18), /* divsi */
654 COSTS_N_INSNS (34), /* divdi */
655 COSTS_N_INSNS (3), /* fp */
656 COSTS_N_INSNS (3), /* dmul */
657 COSTS_N_INSNS (17), /* sdiv */
658 COSTS_N_INSNS (17), /* ddiv */
660 256, /* cache lines */
661 8, /* prefetch streams /*/
664 /* Instruction costs on POWER6 processors. */
666 struct processor_costs power6_cost = {
667 COSTS_N_INSNS (8), /* mulsi */
668 COSTS_N_INSNS (8), /* mulsi_const */
669 COSTS_N_INSNS (8), /* mulsi_const9 */
670 COSTS_N_INSNS (8), /* muldi */
671 COSTS_N_INSNS (22), /* divsi */
672 COSTS_N_INSNS (28), /* divdi */
673 COSTS_N_INSNS (3), /* fp */
674 COSTS_N_INSNS (3), /* dmul */
675 COSTS_N_INSNS (13), /* sdiv */
676 COSTS_N_INSNS (16), /* ddiv */
678 512, /* cache lines */
679 16, /* prefetch streams */
683 static bool rs6000_function_ok_for_sibcall (tree, tree);
684 static const char *rs6000_invalid_within_doloop (rtx);
685 static rtx rs6000_generate_compare (enum rtx_code);
686 static void rs6000_emit_stack_tie (void);
687 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
688 static rtx spe_synthesize_frame_save (rtx);
689 static bool spe_func_has_64bit_regs_p (void);
690 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
692 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
693 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
694 static unsigned rs6000_hash_constant (rtx);
695 static unsigned toc_hash_function (const void *);
696 static int toc_hash_eq (const void *, const void *);
697 static int constant_pool_expr_1 (rtx, int *, int *);
698 static bool constant_pool_expr_p (rtx);
699 static bool legitimate_small_data_p (enum machine_mode, rtx);
700 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
701 static struct machine_function * rs6000_init_machine_status (void);
702 static bool rs6000_assemble_integer (rtx, unsigned int, int);
703 static bool no_global_regs_above (int);
704 #ifdef HAVE_GAS_HIDDEN
705 static void rs6000_assemble_visibility (tree, int);
707 static int rs6000_ra_ever_killed (void);
708 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
709 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
710 static bool rs6000_ms_bitfield_layout_p (tree);
711 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
712 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
713 static const char *rs6000_mangle_type (tree);
714 extern const struct attribute_spec rs6000_attribute_table[];
715 static void rs6000_set_default_type_attributes (tree);
716 static bool rs6000_reg_live_or_pic_offset_p (int);
717 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
718 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
719 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
721 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
722 static bool rs6000_return_in_memory (tree, tree);
723 static void rs6000_file_start (void);
725 static int rs6000_elf_reloc_rw_mask (void);
726 static void rs6000_elf_asm_out_constructor (rtx, int);
727 static void rs6000_elf_asm_out_destructor (rtx, int);
728 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
729 static void rs6000_elf_asm_init_sections (void);
730 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
731 unsigned HOST_WIDE_INT);
732 static void rs6000_elf_encode_section_info (tree, rtx, int)
735 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
737 static void rs6000_xcoff_asm_output_anchor (rtx);
738 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
739 static void rs6000_xcoff_asm_init_sections (void);
740 static int rs6000_xcoff_reloc_rw_mask (void);
741 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
742 static section *rs6000_xcoff_select_section (tree, int,
743 unsigned HOST_WIDE_INT);
744 static void rs6000_xcoff_unique_section (tree, int);
745 static section *rs6000_xcoff_select_rtx_section
746 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
747 static const char * rs6000_xcoff_strip_name_encoding (const char *);
748 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
749 static void rs6000_xcoff_file_start (void);
750 static void rs6000_xcoff_file_end (void);
752 static int rs6000_variable_issue (FILE *, int, rtx, int);
753 static bool rs6000_rtx_costs (rtx, int, int, int *);
754 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
755 static void rs6000_sched_init (FILE *, int, int);
756 static bool is_microcoded_insn (rtx);
757 static bool is_nonpipeline_insn (rtx);
758 static bool is_cracked_insn (rtx);
759 static bool is_branch_slot_insn (rtx);
760 static bool is_load_insn (rtx);
761 static rtx get_store_dest (rtx pat);
762 static bool is_store_insn (rtx);
763 static bool set_to_load_agen (rtx,rtx);
764 static bool adjacent_mem_locations (rtx,rtx);
765 static int rs6000_adjust_priority (rtx, int);
766 static int rs6000_issue_rate (void);
767 static bool rs6000_is_costly_dependence (dep_t, int, int);
768 static rtx get_next_active_insn (rtx, rtx);
769 static bool insn_terminates_group_p (rtx , enum group_termination);
770 static bool insn_must_be_first_in_group (rtx);
771 static bool insn_must_be_last_in_group (rtx);
772 static bool is_costly_group (rtx *, rtx);
773 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
774 static int redefine_groups (FILE *, int, rtx, rtx);
775 static int pad_groups (FILE *, int, rtx, rtx);
776 static void rs6000_sched_finish (FILE *, int);
777 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
778 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
779 static int rs6000_use_sched_lookahead (void);
780 static int rs6000_use_sched_lookahead_guard (rtx);
781 static tree rs6000_builtin_mask_for_load (void);
782 static tree rs6000_builtin_mul_widen_even (tree);
783 static tree rs6000_builtin_mul_widen_odd (tree);
784 static tree rs6000_builtin_conversion (enum tree_code, tree);
786 static void def_builtin (int, const char *, tree, int);
787 static bool rs6000_vector_alignment_reachable (tree, bool);
788 static void rs6000_init_builtins (void);
789 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
790 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
791 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
792 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
793 static void altivec_init_builtins (void);
794 static void rs6000_common_init_builtins (void);
795 static void rs6000_init_libfuncs (void);
797 static void enable_mask_for_builtins (struct builtin_description *, int,
798 enum rs6000_builtins,
799 enum rs6000_builtins);
800 static tree build_opaque_vector_type (tree, int);
801 static void spe_init_builtins (void);
802 static rtx spe_expand_builtin (tree, rtx, bool *);
803 static rtx spe_expand_stv_builtin (enum insn_code, tree);
804 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
805 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
806 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
807 static rs6000_stack_t *rs6000_stack_info (void);
808 static void debug_stack_info (rs6000_stack_t *);
810 static rtx altivec_expand_builtin (tree, rtx, bool *);
811 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
812 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
813 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
814 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
815 static rtx altivec_expand_predicate_builtin (enum insn_code,
816 const char *, tree, rtx);
817 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
818 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
819 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
820 static rtx altivec_expand_vec_set_builtin (tree);
821 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
822 static int get_element_number (tree, tree);
823 static bool rs6000_handle_option (size_t, const char *, int);
824 static void rs6000_parse_tls_size_option (void);
825 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
826 static int first_altivec_reg_to_save (void);
827 static unsigned int compute_vrsave_mask (void);
828 static void compute_save_world_info (rs6000_stack_t *info_ptr);
829 static void is_altivec_return_reg (rtx, void *);
830 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
831 int easy_vector_constant (rtx, enum machine_mode);
832 static bool rs6000_is_opaque_type (tree);
833 static rtx rs6000_dwarf_register_span (rtx);
834 static void rs6000_init_dwarf_reg_sizes_extra (tree);
835 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
836 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
837 static rtx rs6000_tls_get_addr (void);
838 static rtx rs6000_got_sym (void);
839 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
840 static const char *rs6000_get_some_local_dynamic_name (void);
841 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
842 static rtx rs6000_complex_function_value (enum machine_mode);
843 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
844 enum machine_mode, tree);
845 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
847 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
848 tree, HOST_WIDE_INT);
849 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
852 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
855 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
856 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
857 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
858 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
859 enum machine_mode, tree,
861 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
863 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
865 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
867 static void macho_branch_islands (void);
868 static int no_previous_def (tree function_name);
869 static tree get_prev_label (tree function_name);
870 static void rs6000_darwin_file_start (void);
873 static tree rs6000_build_builtin_va_list (void);
874 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
875 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
876 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
877 static bool rs6000_vector_mode_supported_p (enum machine_mode);
878 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
880 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
882 static int get_vsel_insn (enum machine_mode);
883 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
884 static tree rs6000_stack_protect_fail (void);
886 const int INSN_NOT_AVAILABLE = -1;
887 static enum machine_mode rs6000_eh_return_filter_mode (void);
889 /* Hash table stuff for keeping track of TOC entries. */
891 struct toc_hash_struct GTY(())
893 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
894 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
896 enum machine_mode key_mode;
900 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
902 /* Default register names. */
903 char rs6000_reg_names[][8] =
905 "0", "1", "2", "3", "4", "5", "6", "7",
906 "8", "9", "10", "11", "12", "13", "14", "15",
907 "16", "17", "18", "19", "20", "21", "22", "23",
908 "24", "25", "26", "27", "28", "29", "30", "31",
909 "0", "1", "2", "3", "4", "5", "6", "7",
910 "8", "9", "10", "11", "12", "13", "14", "15",
911 "16", "17", "18", "19", "20", "21", "22", "23",
912 "24", "25", "26", "27", "28", "29", "30", "31",
913 "mq", "lr", "ctr","ap",
914 "0", "1", "2", "3", "4", "5", "6", "7",
916 /* AltiVec registers. */
917 "0", "1", "2", "3", "4", "5", "6", "7",
918 "8", "9", "10", "11", "12", "13", "14", "15",
919 "16", "17", "18", "19", "20", "21", "22", "23",
920 "24", "25", "26", "27", "28", "29", "30", "31",
923 "spe_acc", "spefscr",
924 /* Soft frame pointer. */
928 #ifdef TARGET_REGNAMES
929 static const char alt_reg_names[][8] =
931 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
932 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
933 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
934 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
935 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
936 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
937 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
938 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
939 "mq", "lr", "ctr", "ap",
940 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
942 /* AltiVec registers. */
943 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
944 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
945 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
946 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
949 "spe_acc", "spefscr",
950 /* Soft frame pointer. */
955 #ifndef MASK_STRICT_ALIGN
956 #define MASK_STRICT_ALIGN 0
958 #ifndef TARGET_PROFILE_KERNEL
959 #define TARGET_PROFILE_KERNEL 0
962 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
963 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
965 /* Initialize the GCC target structure. */
966 #undef TARGET_ATTRIBUTE_TABLE
967 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
968 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
969 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
971 #undef TARGET_ASM_ALIGNED_DI_OP
972 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
974 /* Default unaligned ops are only provided for ELF. Find the ops needed
975 for non-ELF systems. */
976 #ifndef OBJECT_FORMAT_ELF
978 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
980 #undef TARGET_ASM_UNALIGNED_HI_OP
981 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
982 #undef TARGET_ASM_UNALIGNED_SI_OP
983 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
984 #undef TARGET_ASM_UNALIGNED_DI_OP
985 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
988 #undef TARGET_ASM_UNALIGNED_HI_OP
989 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
990 #undef TARGET_ASM_UNALIGNED_SI_OP
991 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
992 #undef TARGET_ASM_UNALIGNED_DI_OP
993 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
994 #undef TARGET_ASM_ALIGNED_DI_OP
995 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
999 /* This hook deals with fixups for relocatable code and DI-mode objects
1001 #undef TARGET_ASM_INTEGER
1002 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1004 #ifdef HAVE_GAS_HIDDEN
1005 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1006 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1009 #undef TARGET_HAVE_TLS
1010 #define TARGET_HAVE_TLS HAVE_AS_TLS
1012 #undef TARGET_CANNOT_FORCE_CONST_MEM
1013 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1015 #undef TARGET_ASM_FUNCTION_PROLOGUE
1016 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1017 #undef TARGET_ASM_FUNCTION_EPILOGUE
1018 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1020 #undef TARGET_SCHED_VARIABLE_ISSUE
1021 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1023 #undef TARGET_SCHED_ISSUE_RATE
1024 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1025 #undef TARGET_SCHED_ADJUST_COST
1026 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1027 #undef TARGET_SCHED_ADJUST_PRIORITY
1028 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1029 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1030 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1031 #undef TARGET_SCHED_INIT
1032 #define TARGET_SCHED_INIT rs6000_sched_init
1033 #undef TARGET_SCHED_FINISH
1034 #define TARGET_SCHED_FINISH rs6000_sched_finish
1035 #undef TARGET_SCHED_REORDER
1036 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1037 #undef TARGET_SCHED_REORDER2
1038 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1040 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1041 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1043 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1044 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1046 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1047 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1048 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1049 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1050 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1051 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1052 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1053 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1055 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1056 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1058 #undef TARGET_INIT_BUILTINS
1059 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1061 #undef TARGET_EXPAND_BUILTIN
1062 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1064 #undef TARGET_MANGLE_TYPE
1065 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1067 #undef TARGET_INIT_LIBFUNCS
1068 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1071 #undef TARGET_BINDS_LOCAL_P
1072 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1075 #undef TARGET_MS_BITFIELD_LAYOUT_P
1076 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1078 #undef TARGET_ASM_OUTPUT_MI_THUNK
1079 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1081 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1082 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1084 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1085 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1087 #undef TARGET_INVALID_WITHIN_DOLOOP
1088 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1090 #undef TARGET_RTX_COSTS
1091 #define TARGET_RTX_COSTS rs6000_rtx_costs
1092 #undef TARGET_ADDRESS_COST
1093 #define TARGET_ADDRESS_COST hook_int_rtx_0
1095 #undef TARGET_VECTOR_OPAQUE_P
1096 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1098 #undef TARGET_DWARF_REGISTER_SPAN
1099 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1101 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1102 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1104 /* On rs6000, function arguments are promoted, as are function return
1106 #undef TARGET_PROMOTE_FUNCTION_ARGS
1107 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1108 #undef TARGET_PROMOTE_FUNCTION_RETURN
1109 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1111 #undef TARGET_RETURN_IN_MEMORY
1112 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1114 #undef TARGET_SETUP_INCOMING_VARARGS
1115 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1117 /* Always strict argument naming on rs6000. */
1118 #undef TARGET_STRICT_ARGUMENT_NAMING
1119 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1120 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1121 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1122 #undef TARGET_SPLIT_COMPLEX_ARG
1123 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1124 #undef TARGET_MUST_PASS_IN_STACK
1125 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1126 #undef TARGET_PASS_BY_REFERENCE
1127 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1128 #undef TARGET_ARG_PARTIAL_BYTES
1129 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1131 #undef TARGET_BUILD_BUILTIN_VA_LIST
1132 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1134 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1135 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1137 #undef TARGET_EH_RETURN_FILTER_MODE
1138 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1140 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1141 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1143 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1144 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1146 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1147 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1149 #undef TARGET_HANDLE_OPTION
1150 #define TARGET_HANDLE_OPTION rs6000_handle_option
1152 #undef TARGET_DEFAULT_TARGET_FLAGS
1153 #define TARGET_DEFAULT_TARGET_FLAGS \
1156 #undef TARGET_STACK_PROTECT_FAIL
1157 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1159 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1160 The PowerPC architecture requires only weak consistency among
1161 processors--that is, memory accesses between processors need not be
1162 sequentially consistent and memory accesses among processors can occur
1163 in any order. The ability to order memory accesses weakly provides
1164 opportunities for more efficient use of the system bus. Unless a
1165 dependency exists, the 604e allows read operations to precede store
1167 #undef TARGET_RELAXED_ORDERING
1168 #define TARGET_RELAXED_ORDERING true
1171 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1172 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1175 /* Use a 32-bit anchor range. This leads to sequences like:
1177 addis tmp,anchor,high
1180 where tmp itself acts as an anchor, and can be shared between
1181 accesses to the same 64k page. */
1182 #undef TARGET_MIN_ANCHOR_OFFSET
1183 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1184 #undef TARGET_MAX_ANCHOR_OFFSET
1185 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1186 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1187 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1189 struct gcc_target targetm = TARGET_INITIALIZER;
1192 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1195 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1197 /* The GPRs can hold any mode, but values bigger than one register
1198 cannot go past R31. */
1199 if (INT_REGNO_P (regno))
1200 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1202 /* The float registers can only hold floating modes and DImode.
1203 This excludes the 32-bit decimal float mode for now. */
1204 if (FP_REGNO_P (regno))
1206 (SCALAR_FLOAT_MODE_P (mode)
1207 && (mode != TDmode || (regno % 2) == 0)
1209 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1210 || (GET_MODE_CLASS (mode) == MODE_INT
1211 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1213 /* The CR register can only hold CC modes. */
1214 if (CR_REGNO_P (regno))
1215 return GET_MODE_CLASS (mode) == MODE_CC;
1217 if (XER_REGNO_P (regno))
1218 return mode == PSImode;
1220 /* AltiVec only in AldyVec registers. */
1221 if (ALTIVEC_REGNO_P (regno))
1222 return ALTIVEC_VECTOR_MODE (mode);
1224 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1225 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1228 /* We cannot put TImode anywhere except general register and it must be
1229 able to fit within the register set. */
1231 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1234 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1236 rs6000_init_hard_regno_mode_ok (void)
1240 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1241 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1242 if (rs6000_hard_regno_mode_ok (r, m))
1243 rs6000_hard_regno_mode_ok_p[m][r] = true;
1247 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1250 darwin_rs6000_override_options (void)
1252 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1254 rs6000_altivec_abi = 1;
1255 TARGET_ALTIVEC_VRSAVE = 1;
1256 if (DEFAULT_ABI == ABI_DARWIN)
1258 if (MACHO_DYNAMIC_NO_PIC_P)
1261 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1264 else if (flag_pic == 1)
1269 if (TARGET_64BIT && ! TARGET_POWERPC64)
1271 target_flags |= MASK_POWERPC64;
1272 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1276 rs6000_default_long_calls = 1;
1277 target_flags |= MASK_SOFT_FLOAT;
1280 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1282 if (!flag_mkernel && !flag_apple_kext
1284 && ! (target_flags_explicit & MASK_ALTIVEC))
1285 target_flags |= MASK_ALTIVEC;
1287 /* Unless the user (not the configurer) has explicitly overridden
1288 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1289 G4 unless targetting the kernel. */
1292 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1293 && ! (target_flags_explicit & MASK_ALTIVEC)
1294 && ! rs6000_select[1].string)
1296 target_flags |= MASK_ALTIVEC;
1301 /* If not otherwise specified by a target, make 'long double' equivalent to
1304 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1305 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1308 /* Override command line options. Mostly we process the processor
1309 type and sometimes adjust other TARGET_ options. */
1312 rs6000_override_options (const char *default_cpu)
1315 struct rs6000_cpu_select *ptr;
1318 /* Simplifications for entries below. */
1321 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1322 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1325 /* This table occasionally claims that a processor does not support
1326 a particular feature even though it does, but the feature is slower
1327 than the alternative. Thus, it shouldn't be relied on as a
1328 complete description of the processor's support.
1330 Please keep this list in order, and don't forget to update the
1331 documentation in invoke.texi when adding a new processor or
1335 const char *const name; /* Canonical processor name. */
1336 const enum processor_type processor; /* Processor type enum value. */
1337 const int target_enable; /* Target flags to enable. */
1338 } const processor_target_table[]
1339 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1340 {"403", PROCESSOR_PPC403,
1341 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1342 {"405", PROCESSOR_PPC405,
1343 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1344 {"405fp", PROCESSOR_PPC405,
1345 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1346 {"440", PROCESSOR_PPC440,
1347 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1348 {"440fp", PROCESSOR_PPC440,
1349 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1350 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1351 {"601", PROCESSOR_PPC601,
1352 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1353 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1354 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1355 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1356 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1357 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1358 {"620", PROCESSOR_PPC620,
1359 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1360 {"630", PROCESSOR_PPC630,
1361 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1362 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1363 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1364 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1365 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1366 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1367 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1368 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1369 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1370 /* 8548 has a dummy entry for now. */
1371 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1372 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1373 {"970", PROCESSOR_POWER4,
1374 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1375 {"cell", PROCESSOR_CELL,
1376 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1377 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1378 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1379 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1380 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1381 {"G5", PROCESSOR_POWER4,
1382 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1383 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1384 {"power2", PROCESSOR_POWER,
1385 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1386 {"power3", PROCESSOR_PPC630,
1387 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1388 {"power4", PROCESSOR_POWER4,
1389 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1390 {"power5", PROCESSOR_POWER5,
1391 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1392 | MASK_MFCRF | MASK_POPCNTB},
1393 {"power5+", PROCESSOR_POWER5,
1394 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1395 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1396 {"power6", PROCESSOR_POWER6,
1397 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1398 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1399 {"power6x", PROCESSOR_POWER6,
1400 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1401 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1402 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1403 {"powerpc64", PROCESSOR_POWERPC64,
1404 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1405 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1406 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1407 {"rios2", PROCESSOR_RIOS2,
1408 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1409 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1410 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1411 {"rs64", PROCESSOR_RS64A,
1412 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1415 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1417 /* Some OSs don't support saving the high part of 64-bit registers on
1418 context switch. Other OSs don't support saving Altivec registers.
1419 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1420 settings; if the user wants either, the user must explicitly specify
1421 them and we won't interfere with the user's specification. */
1424 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1425 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1426 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1427 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1428 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1431 rs6000_init_hard_regno_mode_ok ();
1433 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1434 #ifdef OS_MISSING_POWERPC64
1435 if (OS_MISSING_POWERPC64)
1436 set_masks &= ~MASK_POWERPC64;
1438 #ifdef OS_MISSING_ALTIVEC
1439 if (OS_MISSING_ALTIVEC)
1440 set_masks &= ~MASK_ALTIVEC;
1443 /* Don't override by the processor default if given explicitly. */
1444 set_masks &= ~target_flags_explicit;
1446 /* Identify the processor type. */
1447 rs6000_select[0].string = default_cpu;
1448 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1450 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1452 ptr = &rs6000_select[i];
1453 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1455 for (j = 0; j < ptt_size; j++)
1456 if (! strcmp (ptr->string, processor_target_table[j].name))
1458 if (ptr->set_tune_p)
1459 rs6000_cpu = processor_target_table[j].processor;
1461 if (ptr->set_arch_p)
1463 target_flags &= ~set_masks;
1464 target_flags |= (processor_target_table[j].target_enable
1471 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1478 /* If we are optimizing big endian systems for space, use the load/store
1479 multiple and string instructions. */
1480 if (BYTES_BIG_ENDIAN && optimize_size)
1481 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1483 /* Don't allow -mmultiple or -mstring on little endian systems
1484 unless the cpu is a 750, because the hardware doesn't support the
1485 instructions used in little endian mode, and causes an alignment
1486 trap. The 750 does not cause an alignment trap (except when the
1487 target is unaligned). */
1489 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1491 if (TARGET_MULTIPLE)
1493 target_flags &= ~MASK_MULTIPLE;
1494 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1495 warning (0, "-mmultiple is not supported on little endian systems");
1500 target_flags &= ~MASK_STRING;
1501 if ((target_flags_explicit & MASK_STRING) != 0)
1502 warning (0, "-mstring is not supported on little endian systems");
1506 /* Set debug flags */
1507 if (rs6000_debug_name)
1509 if (! strcmp (rs6000_debug_name, "all"))
1510 rs6000_debug_stack = rs6000_debug_arg = 1;
1511 else if (! strcmp (rs6000_debug_name, "stack"))
1512 rs6000_debug_stack = 1;
1513 else if (! strcmp (rs6000_debug_name, "arg"))
1514 rs6000_debug_arg = 1;
1516 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1519 if (rs6000_traceback_name)
1521 if (! strncmp (rs6000_traceback_name, "full", 4))
1522 rs6000_traceback = traceback_full;
1523 else if (! strncmp (rs6000_traceback_name, "part", 4))
1524 rs6000_traceback = traceback_part;
1525 else if (! strncmp (rs6000_traceback_name, "no", 2))
1526 rs6000_traceback = traceback_none;
1528 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1529 rs6000_traceback_name);
1532 if (!rs6000_explicit_options.long_double)
1533 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1535 #ifndef POWERPC_LINUX
1536 if (!rs6000_explicit_options.ieee)
1537 rs6000_ieeequad = 1;
1540 /* Set Altivec ABI as default for powerpc64 linux. */
1541 if (TARGET_ELF && TARGET_64BIT)
1543 rs6000_altivec_abi = 1;
1544 TARGET_ALTIVEC_VRSAVE = 1;
1547 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1548 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1550 rs6000_darwin64_abi = 1;
1552 darwin_one_byte_bool = 1;
1554 /* Default to natural alignment, for better performance. */
1555 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1558 /* Place FP constants in the constant pool instead of TOC
1559 if section anchors enabled. */
1560 if (flag_section_anchors)
1561 TARGET_NO_FP_IN_TOC = 1;
1563 /* Handle -mtls-size option. */
1564 rs6000_parse_tls_size_option ();
1566 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1567 SUBTARGET_OVERRIDE_OPTIONS;
1569 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1570 SUBSUBTARGET_OVERRIDE_OPTIONS;
1572 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1573 SUB3TARGET_OVERRIDE_OPTIONS;
1578 /* The e500 does not have string instructions, and we set
1579 MASK_STRING above when optimizing for size. */
1580 if ((target_flags & MASK_STRING) != 0)
1581 target_flags = target_flags & ~MASK_STRING;
1583 else if (rs6000_select[1].string != NULL)
1585 /* For the powerpc-eabispe configuration, we set all these by
1586 default, so let's unset them if we manually set another
1587 CPU that is not the E500. */
1588 if (!rs6000_explicit_options.abi)
1590 if (!rs6000_explicit_options.spe)
1592 if (!rs6000_explicit_options.float_gprs)
1593 rs6000_float_gprs = 0;
1594 if (!rs6000_explicit_options.isel)
1598 /* Detect invalid option combinations with E500. */
1601 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1602 && rs6000_cpu != PROCESSOR_POWER5
1603 && rs6000_cpu != PROCESSOR_POWER6
1604 && rs6000_cpu != PROCESSOR_CELL);
1605 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1606 || rs6000_cpu == PROCESSOR_POWER5);
1607 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1608 || rs6000_cpu == PROCESSOR_POWER5
1609 || rs6000_cpu == PROCESSOR_POWER6);
1611 rs6000_sched_restricted_insns_priority
1612 = (rs6000_sched_groups ? 1 : 0);
1614 /* Handle -msched-costly-dep option. */
1615 rs6000_sched_costly_dep
1616 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1618 if (rs6000_sched_costly_dep_str)
1620 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1621 rs6000_sched_costly_dep = no_dep_costly;
1622 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1623 rs6000_sched_costly_dep = all_deps_costly;
1624 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1625 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1626 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1627 rs6000_sched_costly_dep = store_to_load_dep_costly;
1629 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1632 /* Handle -minsert-sched-nops option. */
1633 rs6000_sched_insert_nops
1634 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1636 if (rs6000_sched_insert_nops_str)
1638 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1639 rs6000_sched_insert_nops = sched_finish_none;
1640 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1641 rs6000_sched_insert_nops = sched_finish_pad_groups;
1642 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1643 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1645 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1648 #ifdef TARGET_REGNAMES
1649 /* If the user desires alternate register names, copy in the
1650 alternate names now. */
1651 if (TARGET_REGNAMES)
1652 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1655 /* Set aix_struct_return last, after the ABI is determined.
1656 If -maix-struct-return or -msvr4-struct-return was explicitly
1657 used, don't override with the ABI default. */
1658 if (!rs6000_explicit_options.aix_struct_ret)
1659 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1661 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1662 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1665 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1667 /* We can only guarantee the availability of DI pseudo-ops when
1668 assembling for 64-bit targets. */
1671 targetm.asm_out.aligned_op.di = NULL;
1672 targetm.asm_out.unaligned_op.di = NULL;
1675 /* Set branch target alignment, if not optimizing for size. */
1678 /* Cell wants to be aligned 8byte for dual issue. */
1679 if (rs6000_cpu == PROCESSOR_CELL)
1681 if (align_functions <= 0)
1682 align_functions = 8;
1683 if (align_jumps <= 0)
1685 if (align_loops <= 0)
1688 if (rs6000_align_branch_targets)
1690 if (align_functions <= 0)
1691 align_functions = 16;
1692 if (align_jumps <= 0)
1694 if (align_loops <= 0)
1697 if (align_jumps_max_skip <= 0)
1698 align_jumps_max_skip = 15;
1699 if (align_loops_max_skip <= 0)
1700 align_loops_max_skip = 15;
1703 /* Arrange to save and restore machine status around nested functions. */
1704 init_machine_status = rs6000_init_machine_status;
1706 /* We should always be splitting complex arguments, but we can't break
1707 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1708 if (DEFAULT_ABI != ABI_AIX)
1709 targetm.calls.split_complex_arg = NULL;
1711 /* Initialize rs6000_cost with the appropriate target costs. */
1713 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1717 case PROCESSOR_RIOS1:
1718 rs6000_cost = &rios1_cost;
1721 case PROCESSOR_RIOS2:
1722 rs6000_cost = &rios2_cost;
1725 case PROCESSOR_RS64A:
1726 rs6000_cost = &rs64a_cost;
1729 case PROCESSOR_MPCCORE:
1730 rs6000_cost = &mpccore_cost;
1733 case PROCESSOR_PPC403:
1734 rs6000_cost = &ppc403_cost;
1737 case PROCESSOR_PPC405:
1738 rs6000_cost = &ppc405_cost;
1741 case PROCESSOR_PPC440:
1742 rs6000_cost = &ppc440_cost;
1745 case PROCESSOR_PPC601:
1746 rs6000_cost = &ppc601_cost;
1749 case PROCESSOR_PPC603:
1750 rs6000_cost = &ppc603_cost;
1753 case PROCESSOR_PPC604:
1754 rs6000_cost = &ppc604_cost;
1757 case PROCESSOR_PPC604e:
1758 rs6000_cost = &ppc604e_cost;
1761 case PROCESSOR_PPC620:
1762 rs6000_cost = &ppc620_cost;
1765 case PROCESSOR_PPC630:
1766 rs6000_cost = &ppc630_cost;
1769 case PROCESSOR_CELL:
1770 rs6000_cost = &ppccell_cost;
1773 case PROCESSOR_PPC750:
1774 case PROCESSOR_PPC7400:
1775 rs6000_cost = &ppc750_cost;
1778 case PROCESSOR_PPC7450:
1779 rs6000_cost = &ppc7450_cost;
1782 case PROCESSOR_PPC8540:
1783 rs6000_cost = &ppc8540_cost;
1786 case PROCESSOR_POWER4:
1787 case PROCESSOR_POWER5:
1788 rs6000_cost = &power4_cost;
1791 case PROCESSOR_POWER6:
1792 rs6000_cost = &power6_cost;
1799 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1800 set_param_value ("simultaneous-prefetches",
1801 rs6000_cost->simultaneous_prefetches);
1802 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1803 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_lines);
1804 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1805 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1808 /* Implement targetm.vectorize.builtin_mask_for_load. */
1810 rs6000_builtin_mask_for_load (void)
1813 return altivec_builtin_mask_for_load;
1818 /* Implement targetm.vectorize.builtin_conversion. */
1820 rs6000_builtin_conversion (enum tree_code code, tree type)
1822 if (!TARGET_ALTIVEC)
1828 switch (TYPE_MODE (type))
1831 return TYPE_UNSIGNED (type) ?
1832 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1833 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1842 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1844 rs6000_builtin_mul_widen_even (tree type)
1846 if (!TARGET_ALTIVEC)
1849 switch (TYPE_MODE (type))
1852 return TYPE_UNSIGNED (type) ?
1853 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1854 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1857 return TYPE_UNSIGNED (type) ?
1858 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1859 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1865 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1867 rs6000_builtin_mul_widen_odd (tree type)
1869 if (!TARGET_ALTIVEC)
1872 switch (TYPE_MODE (type))
1875 return TYPE_UNSIGNED (type) ?
1876 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1877 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1880 return TYPE_UNSIGNED (type) ?
1881 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1882 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1889 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1890 after applying N number of iterations. This routine does not determine
1891 how may iterations are required to reach desired alignment. */
1894 rs6000_vector_alignment_reachable (tree type ATTRIBUTE_UNUSED, bool is_packed)
1901 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
1904 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
1914 /* Assuming that all other types are naturally aligned. CHECKME! */
1919 /* Handle generic options of the form -mfoo=yes/no.
1920 NAME is the option name.
1921 VALUE is the option value.
1922 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1923 whether the option value is 'yes' or 'no' respectively. */
1925 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1929 else if (!strcmp (value, "yes"))
1931 else if (!strcmp (value, "no"))
1934 error ("unknown -m%s= option specified: '%s'", name, value);
1937 /* Validate and record the size specified with the -mtls-size option. */
1940 rs6000_parse_tls_size_option (void)
1942 if (rs6000_tls_size_string == 0)
1944 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1945 rs6000_tls_size = 16;
1946 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1947 rs6000_tls_size = 32;
1948 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1949 rs6000_tls_size = 64;
1951 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1955 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1957 if (DEFAULT_ABI == ABI_DARWIN)
1958 /* The Darwin libraries never set errno, so we might as well
1959 avoid calling them when that's the only reason we would. */
1960 flag_errno_math = 0;
1962 /* Double growth factor to counter reduced min jump length. */
1963 set_param_value ("max-grow-copy-bb-insns", 16);
1965 /* Enable section anchors by default.
1966 Skip section anchors for Objective C and Objective C++
1967 until front-ends fixed. */
1968 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1969 flag_section_anchors = 1;
1972 /* Implement TARGET_HANDLE_OPTION. */
1975 rs6000_handle_option (size_t code, const char *arg, int value)
1980 target_flags &= ~(MASK_POWER | MASK_POWER2
1981 | MASK_MULTIPLE | MASK_STRING);
1982 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1983 | MASK_MULTIPLE | MASK_STRING);
1985 case OPT_mno_powerpc:
1986 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1987 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1988 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1989 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1992 target_flags &= ~MASK_MINIMAL_TOC;
1993 TARGET_NO_FP_IN_TOC = 0;
1994 TARGET_NO_SUM_IN_TOC = 0;
1995 target_flags_explicit |= MASK_MINIMAL_TOC;
1996 #ifdef TARGET_USES_SYSV4_OPT
1997 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1998 just the same as -mminimal-toc. */
1999 target_flags |= MASK_MINIMAL_TOC;
2000 target_flags_explicit |= MASK_MINIMAL_TOC;
2004 #ifdef TARGET_USES_SYSV4_OPT
2006 /* Make -mtoc behave like -mminimal-toc. */
2007 target_flags |= MASK_MINIMAL_TOC;
2008 target_flags_explicit |= MASK_MINIMAL_TOC;
2012 #ifdef TARGET_USES_AIX64_OPT
2017 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2018 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2019 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2022 #ifdef TARGET_USES_AIX64_OPT
2027 target_flags &= ~MASK_POWERPC64;
2028 target_flags_explicit |= MASK_POWERPC64;
2031 case OPT_minsert_sched_nops_:
2032 rs6000_sched_insert_nops_str = arg;
2035 case OPT_mminimal_toc:
2038 TARGET_NO_FP_IN_TOC = 0;
2039 TARGET_NO_SUM_IN_TOC = 0;
2046 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2047 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2054 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2055 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2059 case OPT_mpowerpc_gpopt:
2060 case OPT_mpowerpc_gfxopt:
2063 target_flags |= MASK_POWERPC;
2064 target_flags_explicit |= MASK_POWERPC;
2068 case OPT_maix_struct_return:
2069 case OPT_msvr4_struct_return:
2070 rs6000_explicit_options.aix_struct_ret = true;
2074 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2078 rs6000_explicit_options.isel = true;
2079 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2083 rs6000_explicit_options.spe = true;
2084 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2088 rs6000_debug_name = arg;
2091 #ifdef TARGET_USES_SYSV4_OPT
2093 rs6000_abi_name = arg;
2097 rs6000_sdata_name = arg;
2100 case OPT_mtls_size_:
2101 rs6000_tls_size_string = arg;
2104 case OPT_mrelocatable:
2107 target_flags |= MASK_MINIMAL_TOC;
2108 target_flags_explicit |= MASK_MINIMAL_TOC;
2109 TARGET_NO_FP_IN_TOC = 1;
2113 case OPT_mrelocatable_lib:
2116 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2117 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2118 TARGET_NO_FP_IN_TOC = 1;
2122 target_flags &= ~MASK_RELOCATABLE;
2123 target_flags_explicit |= MASK_RELOCATABLE;
2129 if (!strcmp (arg, "altivec"))
2131 rs6000_explicit_options.abi = true;
2132 rs6000_altivec_abi = 1;
2135 else if (! strcmp (arg, "no-altivec"))
2137 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2138 the default for rs6000_spe_abi to be chosen later. */
2139 rs6000_altivec_abi = 0;
2141 else if (! strcmp (arg, "spe"))
2143 rs6000_explicit_options.abi = true;
2145 rs6000_altivec_abi = 0;
2146 if (!TARGET_SPE_ABI)
2147 error ("not configured for ABI: '%s'", arg);
2149 else if (! strcmp (arg, "no-spe"))
2151 rs6000_explicit_options.abi = true;
2155 /* These are here for testing during development only, do not
2156 document in the manual please. */
2157 else if (! strcmp (arg, "d64"))
2159 rs6000_darwin64_abi = 1;
2160 warning (0, "Using darwin64 ABI");
2162 else if (! strcmp (arg, "d32"))
2164 rs6000_darwin64_abi = 0;
2165 warning (0, "Using old darwin ABI");
2168 else if (! strcmp (arg, "ibmlongdouble"))
2170 rs6000_explicit_options.ieee = true;
2171 rs6000_ieeequad = 0;
2172 warning (0, "Using IBM extended precision long double");
2174 else if (! strcmp (arg, "ieeelongdouble"))
2176 rs6000_explicit_options.ieee = true;
2177 rs6000_ieeequad = 1;
2178 warning (0, "Using IEEE extended precision long double");
2183 error ("unknown ABI specified: '%s'", arg);
2189 rs6000_select[1].string = arg;
2193 rs6000_select[2].string = arg;
2196 case OPT_mtraceback_:
2197 rs6000_traceback_name = arg;
2200 case OPT_mfloat_gprs_:
2201 rs6000_explicit_options.float_gprs = true;
2202 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2203 rs6000_float_gprs = 1;
2204 else if (! strcmp (arg, "double"))
2205 rs6000_float_gprs = 2;
2206 else if (! strcmp (arg, "no"))
2207 rs6000_float_gprs = 0;
2210 error ("invalid option for -mfloat-gprs: '%s'", arg);
2215 case OPT_mlong_double_:
2216 rs6000_explicit_options.long_double = true;
2217 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2218 if (value != 64 && value != 128)
2220 error ("Unknown switch -mlong-double-%s", arg);
2221 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2225 rs6000_long_double_type_size = value;
2228 case OPT_msched_costly_dep_:
2229 rs6000_sched_costly_dep_str = arg;
2233 rs6000_explicit_options.alignment = true;
2234 if (! strcmp (arg, "power"))
2236 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2237 some C library functions, so warn about it. The flag may be
2238 useful for performance studies from time to time though, so
2239 don't disable it entirely. */
2240 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2241 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2242 " it is incompatible with the installed C and C++ libraries");
2243 rs6000_alignment_flags = MASK_ALIGN_POWER;
2245 else if (! strcmp (arg, "natural"))
2246 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2249 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2257 /* Do anything needed at the start of the asm file. */
2260 rs6000_file_start (void)
2264 const char *start = buffer;
2265 struct rs6000_cpu_select *ptr;
2266 const char *default_cpu = TARGET_CPU_DEFAULT;
2267 FILE *file = asm_out_file;
2269 default_file_start ();
2271 #ifdef TARGET_BI_ARCH
2272 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2276 if (flag_verbose_asm)
2278 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2279 rs6000_select[0].string = default_cpu;
2281 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2283 ptr = &rs6000_select[i];
2284 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2286 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2291 if (PPC405_ERRATUM77)
2293 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2297 #ifdef USING_ELFOS_H
2298 switch (rs6000_sdata)
2300 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2301 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2302 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2303 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2306 if (rs6000_sdata && g_switch_value)
2308 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2318 #ifdef HAVE_AS_GNU_ATTRIBUTE
2319 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2320 fprintf (file, "\t.gnu_attribute 4, %d\n",
2321 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2324 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2326 switch_to_section (toc_section);
2327 switch_to_section (text_section);
2332 /* Return nonzero if this function is known to have a null epilogue. */
2335 direct_return (void)
2337 if (reload_completed)
2339 rs6000_stack_t *info = rs6000_stack_info ();
2341 if (info->first_gp_reg_save == 32
2342 && info->first_fp_reg_save == 64
2343 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2344 && ! info->lr_save_p
2345 && ! info->cr_save_p
2346 && info->vrsave_mask == 0
2354 /* Return the number of instructions it takes to form a constant in an
2355 integer register. */
2358 num_insns_constant_wide (HOST_WIDE_INT value)
2360 /* signed constant loadable with {cal|addi} */
2361 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2364 /* constant loadable with {cau|addis} */
2365 else if ((value & 0xffff) == 0
2366 && (value >> 31 == -1 || value >> 31 == 0))
2369 #if HOST_BITS_PER_WIDE_INT == 64
2370 else if (TARGET_POWERPC64)
2372 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2373 HOST_WIDE_INT high = value >> 31;
2375 if (high == 0 || high == -1)
2381 return num_insns_constant_wide (high) + 1;
2383 return (num_insns_constant_wide (high)
2384 + num_insns_constant_wide (low) + 1);
2393 num_insns_constant (rtx op, enum machine_mode mode)
2395 HOST_WIDE_INT low, high;
2397 switch (GET_CODE (op))
2400 #if HOST_BITS_PER_WIDE_INT == 64
2401 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2402 && mask64_operand (op, mode))
2406 return num_insns_constant_wide (INTVAL (op));
2414 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2415 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2416 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2419 if (mode == VOIDmode || mode == DImode)
2421 high = CONST_DOUBLE_HIGH (op);
2422 low = CONST_DOUBLE_LOW (op);
2429 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2430 if (DECIMAL_FLOAT_MODE_P (mode))
2431 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2433 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2434 high = l[WORDS_BIG_ENDIAN == 0];
2435 low = l[WORDS_BIG_ENDIAN != 0];
2439 return (num_insns_constant_wide (low)
2440 + num_insns_constant_wide (high));
2443 if ((high == 0 && low >= 0)
2444 || (high == -1 && low < 0))
2445 return num_insns_constant_wide (low);
2447 else if (mask64_operand (op, mode))
2451 return num_insns_constant_wide (high) + 1;
2454 return (num_insns_constant_wide (high)
2455 + num_insns_constant_wide (low) + 1);
2463 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2464 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2465 corresponding element of the vector, but for V4SFmode and V2SFmode,
2466 the corresponding "float" is interpreted as an SImode integer. */
2468 static HOST_WIDE_INT
2469 const_vector_elt_as_int (rtx op, unsigned int elt)
2471 rtx tmp = CONST_VECTOR_ELT (op, elt);
2472 if (GET_MODE (op) == V4SFmode
2473 || GET_MODE (op) == V2SFmode)
2474 tmp = gen_lowpart (SImode, tmp);
2475 return INTVAL (tmp);
2478 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2479 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2480 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2481 all items are set to the same value and contain COPIES replicas of the
2482 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2483 operand and the others are set to the value of the operand's msb. */
2486 vspltis_constant (rtx op, unsigned step, unsigned copies)
2488 enum machine_mode mode = GET_MODE (op);
2489 enum machine_mode inner = GET_MODE_INNER (mode);
2492 unsigned nunits = GET_MODE_NUNITS (mode);
2493 unsigned bitsize = GET_MODE_BITSIZE (inner);
2494 unsigned mask = GET_MODE_MASK (inner);
2496 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2497 HOST_WIDE_INT splat_val = val;
2498 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2500 /* Construct the value to be splatted, if possible. If not, return 0. */
2501 for (i = 2; i <= copies; i *= 2)
2503 HOST_WIDE_INT small_val;
2505 small_val = splat_val >> bitsize;
2507 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2509 splat_val = small_val;
2512 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2513 if (EASY_VECTOR_15 (splat_val))
2516 /* Also check if we can splat, and then add the result to itself. Do so if
2517 the value is positive, of if the splat instruction is using OP's mode;
2518 for splat_val < 0, the splat and the add should use the same mode. */
2519 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2520 && (splat_val >= 0 || (step == 1 && copies == 1)))
2526 /* Check if VAL is present in every STEP-th element, and the
2527 other elements are filled with its most significant bit. */
2528 for (i = 0; i < nunits - 1; ++i)
2530 HOST_WIDE_INT desired_val;
2531 if (((i + 1) & (step - 1)) == 0)
2534 desired_val = msb_val;
2536 if (desired_val != const_vector_elt_as_int (op, i))
2544 /* Return true if OP is of the given MODE and can be synthesized
2545 with a vspltisb, vspltish or vspltisw. */
2548 easy_altivec_constant (rtx op, enum machine_mode mode)
2550 unsigned step, copies;
2552 if (mode == VOIDmode)
2553 mode = GET_MODE (op);
2554 else if (mode != GET_MODE (op))
2557 /* Start with a vspltisw. */
2558 step = GET_MODE_NUNITS (mode) / 4;
2561 if (vspltis_constant (op, step, copies))
2564 /* Then try with a vspltish. */
2570 if (vspltis_constant (op, step, copies))
2573 /* And finally a vspltisb. */
2579 if (vspltis_constant (op, step, copies))
2585 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2586 result is OP. Abort if it is not possible. */
2589 gen_easy_altivec_constant (rtx op)
2591 enum machine_mode mode = GET_MODE (op);
2592 int nunits = GET_MODE_NUNITS (mode);
2593 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2594 unsigned step = nunits / 4;
2595 unsigned copies = 1;
2597 /* Start with a vspltisw. */
2598 if (vspltis_constant (op, step, copies))
2599 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2601 /* Then try with a vspltish. */
2607 if (vspltis_constant (op, step, copies))
2608 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2610 /* And finally a vspltisb. */
2616 if (vspltis_constant (op, step, copies))
2617 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2623 output_vec_const_move (rtx *operands)
2626 enum machine_mode mode;
2631 mode = GET_MODE (dest);
2636 if (zero_constant (vec, mode))
2637 return "vxor %0,%0,%0";
2639 splat_vec = gen_easy_altivec_constant (vec);
2640 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2641 operands[1] = XEXP (splat_vec, 0);
2642 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2645 switch (GET_MODE (splat_vec))
2648 return "vspltisw %0,%1";
2651 return "vspltish %0,%1";
2654 return "vspltisb %0,%1";
2661 gcc_assert (TARGET_SPE);
2663 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2664 pattern of V1DI, V4HI, and V2SF.
2666 FIXME: We should probably return # and add post reload
2667 splitters for these, but this way is so easy ;-). */
2668 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2669 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2670 operands[1] = CONST_VECTOR_ELT (vec, 0);
2671 operands[2] = CONST_VECTOR_ELT (vec, 1);
2673 return "li %0,%1\n\tevmergelo %0,%0,%0";
2675 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2678 /* Initialize vector TARGET to VALS. */
2681 rs6000_expand_vector_init (rtx target, rtx vals)
2683 enum machine_mode mode = GET_MODE (target);
2684 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2685 int n_elts = GET_MODE_NUNITS (mode);
2686 int n_var = 0, one_var = -1;
2687 bool all_same = true, all_const_zero = true;
2691 for (i = 0; i < n_elts; ++i)
2693 x = XVECEXP (vals, 0, i);
2694 if (!CONSTANT_P (x))
2695 ++n_var, one_var = i;
2696 else if (x != CONST0_RTX (inner_mode))
2697 all_const_zero = false;
2699 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2705 if (mode != V4SFmode && all_const_zero)
2707 /* Zero register. */
2708 emit_insn (gen_rtx_SET (VOIDmode, target,
2709 gen_rtx_XOR (mode, target, target)));
2712 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2714 /* Splat immediate. */
2715 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2719 ; /* Splat vector element. */
2722 /* Load from constant pool. */
2723 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2728 /* Store value to stack temp. Load vector element. Splat. */
2731 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2732 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2733 XVECEXP (vals, 0, 0));
2734 x = gen_rtx_UNSPEC (VOIDmode,
2735 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2736 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2738 gen_rtx_SET (VOIDmode,
2741 x = gen_rtx_VEC_SELECT (inner_mode, target,
2742 gen_rtx_PARALLEL (VOIDmode,
2743 gen_rtvec (1, const0_rtx)));
2744 emit_insn (gen_rtx_SET (VOIDmode, target,
2745 gen_rtx_VEC_DUPLICATE (mode, x)));
2749 /* One field is non-constant. Load constant then overwrite
2753 rtx copy = copy_rtx (vals);
2755 /* Load constant part of vector, substitute neighboring value for
2757 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2758 rs6000_expand_vector_init (target, copy);
2760 /* Insert variable. */
2761 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2765 /* Construct the vector in memory one field at a time
2766 and load the whole vector. */
2767 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2768 for (i = 0; i < n_elts; i++)
2769 emit_move_insn (adjust_address_nv (mem, inner_mode,
2770 i * GET_MODE_SIZE (inner_mode)),
2771 XVECEXP (vals, 0, i));
2772 emit_move_insn (target, mem);
2775 /* Set field ELT of TARGET to VAL. */
2778 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2780 enum machine_mode mode = GET_MODE (target);
2781 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2782 rtx reg = gen_reg_rtx (mode);
2784 int width = GET_MODE_SIZE (inner_mode);
2787 /* Load single variable value. */
2788 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2789 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2790 x = gen_rtx_UNSPEC (VOIDmode,
2791 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2792 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2794 gen_rtx_SET (VOIDmode,
2798 /* Linear sequence. */
2799 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2800 for (i = 0; i < 16; ++i)
2801 XVECEXP (mask, 0, i) = GEN_INT (i);
2803 /* Set permute mask to insert element into target. */
2804 for (i = 0; i < width; ++i)
2805 XVECEXP (mask, 0, elt*width + i)
2806 = GEN_INT (i + 0x10);
2807 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2808 x = gen_rtx_UNSPEC (mode,
2809 gen_rtvec (3, target, reg,
2810 force_reg (V16QImode, x)),
2812 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2815 /* Extract field ELT from VEC into TARGET. */
2818 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2820 enum machine_mode mode = GET_MODE (vec);
2821 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2824 /* Allocate mode-sized buffer. */
2825 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2827 /* Add offset to field within buffer matching vector element. */
2828 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2830 /* Store single field into mode-sized buffer. */
2831 x = gen_rtx_UNSPEC (VOIDmode,
2832 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2833 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2835 gen_rtx_SET (VOIDmode,
2838 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2841 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2842 implement ANDing by the mask IN. */
2844 build_mask64_2_operands (rtx in, rtx *out)
2846 #if HOST_BITS_PER_WIDE_INT >= 64
2847 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2850 gcc_assert (GET_CODE (in) == CONST_INT);
2855 /* Assume c initially something like 0x00fff000000fffff. The idea
2856 is to rotate the word so that the middle ^^^^^^ group of zeros
2857 is at the MS end and can be cleared with an rldicl mask. We then
2858 rotate back and clear off the MS ^^ group of zeros with a
2860 c = ~c; /* c == 0xff000ffffff00000 */
2861 lsb = c & -c; /* lsb == 0x0000000000100000 */
2862 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2863 c = ~c; /* c == 0x00fff000000fffff */
2864 c &= -lsb; /* c == 0x00fff00000000000 */
2865 lsb = c & -c; /* lsb == 0x0000100000000000 */
2866 c = ~c; /* c == 0xff000fffffffffff */
2867 c &= -lsb; /* c == 0xff00000000000000 */
2869 while ((lsb >>= 1) != 0)
2870 shift++; /* shift == 44 on exit from loop */
2871 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2872 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2873 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2877 /* Assume c initially something like 0xff000f0000000000. The idea
2878 is to rotate the word so that the ^^^ middle group of zeros
2879 is at the LS end and can be cleared with an rldicr mask. We then
2880 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2882 lsb = c & -c; /* lsb == 0x0000010000000000 */
2883 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2884 c = ~c; /* c == 0x00fff0ffffffffff */
2885 c &= -lsb; /* c == 0x00fff00000000000 */
2886 lsb = c & -c; /* lsb == 0x0000100000000000 */
2887 c = ~c; /* c == 0xff000fffffffffff */
2888 c &= -lsb; /* c == 0xff00000000000000 */
2890 while ((lsb >>= 1) != 0)
2891 shift++; /* shift == 44 on exit from loop */
2892 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2893 m1 >>= shift; /* m1 == 0x0000000000000fff */
2894 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2897 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2898 masks will be all 1's. We are guaranteed more than one transition. */
2899 out[0] = GEN_INT (64 - shift);
2900 out[1] = GEN_INT (m1);
2901 out[2] = GEN_INT (shift);
2902 out[3] = GEN_INT (m2);
2910 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2913 invalid_e500_subreg (rtx op, enum machine_mode mode)
2915 if (TARGET_E500_DOUBLE)
2917 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2918 subreg:TI and reg:TF. */
2919 if (GET_CODE (op) == SUBREG
2920 && (mode == SImode || mode == DImode || mode == TImode)
2921 && REG_P (SUBREG_REG (op))
2922 && (GET_MODE (SUBREG_REG (op)) == DFmode
2923 || GET_MODE (SUBREG_REG (op)) == TFmode))
2926 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2928 if (GET_CODE (op) == SUBREG
2929 && (mode == DFmode || mode == TFmode)
2930 && REG_P (SUBREG_REG (op))
2931 && (GET_MODE (SUBREG_REG (op)) == DImode
2932 || GET_MODE (SUBREG_REG (op)) == TImode))
2937 && GET_CODE (op) == SUBREG
2939 && REG_P (SUBREG_REG (op))
2940 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2946 /* AIX increases natural record alignment to doubleword if the first
2947 field is an FP double while the FP fields remain word aligned. */
2950 rs6000_special_round_type_align (tree type, unsigned int computed,
2951 unsigned int specified)
2953 unsigned int align = MAX (computed, specified);
2954 tree field = TYPE_FIELDS (type);
2956 /* Skip all non field decls */
2957 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2958 field = TREE_CHAIN (field);
2960 if (field != NULL && field != type)
2962 type = TREE_TYPE (field);
2963 while (TREE_CODE (type) == ARRAY_TYPE)
2964 type = TREE_TYPE (type);
2966 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2967 align = MAX (align, 64);
2973 /* Darwin increases record alignment to the natural alignment of
2977 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
2978 unsigned int specified)
2980 unsigned int align = MAX (computed, specified);
2982 if (TYPE_PACKED (type))
2985 /* Find the first field, looking down into aggregates. */
2987 tree field = TYPE_FIELDS (type);
2988 /* Skip all non field decls */
2989 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2990 field = TREE_CHAIN (field);
2993 type = TREE_TYPE (field);
2994 while (TREE_CODE (type) == ARRAY_TYPE)
2995 type = TREE_TYPE (type);
2996 } while (AGGREGATE_TYPE_P (type));
2998 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
2999 align = MAX (align, TYPE_ALIGN (type));
3004 /* Return 1 for an operand in small memory on V.4/eabi. */
3007 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3008 enum machine_mode mode ATTRIBUTE_UNUSED)
3013 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3016 if (DEFAULT_ABI != ABI_V4)
3019 if (GET_CODE (op) == SYMBOL_REF)
3022 else if (GET_CODE (op) != CONST
3023 || GET_CODE (XEXP (op, 0)) != PLUS
3024 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3025 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3030 rtx sum = XEXP (op, 0);
3031 HOST_WIDE_INT summand;
3033 /* We have to be careful here, because it is the referenced address
3034 that must be 32k from _SDA_BASE_, not just the symbol. */
3035 summand = INTVAL (XEXP (sum, 1));
3036 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3039 sym_ref = XEXP (sum, 0);
3042 return SYMBOL_REF_SMALL_P (sym_ref);
3048 /* Return true if either operand is a general purpose register. */
3051 gpr_or_gpr_p (rtx op0, rtx op1)
3053 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3054 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3058 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3061 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3063 switch (GET_CODE (op))
3066 if (RS6000_SYMBOL_REF_TLS_P (op))
3068 else if (CONSTANT_POOL_ADDRESS_P (op))
3070 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3078 else if (! strcmp (XSTR (op, 0), toc_label_name))
3087 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3088 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3090 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3099 constant_pool_expr_p (rtx op)
3103 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3107 toc_relative_expr_p (rtx op)
3111 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3115 legitimate_constant_pool_address_p (rtx x)
3118 && GET_CODE (x) == PLUS
3119 && GET_CODE (XEXP (x, 0)) == REG
3120 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3121 && constant_pool_expr_p (XEXP (x, 1)));
3125 legitimate_small_data_p (enum machine_mode mode, rtx x)
3127 return (DEFAULT_ABI == ABI_V4
3128 && !flag_pic && !TARGET_TOC
3129 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3130 && small_data_operand (x, mode));
3133 /* SPE offset addressing is limited to 5-bits worth of double words. */
3134 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3137 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3139 unsigned HOST_WIDE_INT offset, extra;
3141 if (GET_CODE (x) != PLUS)
3143 if (GET_CODE (XEXP (x, 0)) != REG)
3145 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3147 if (legitimate_constant_pool_address_p (x))
3149 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3152 offset = INTVAL (XEXP (x, 1));
3160 /* AltiVec vector modes. Only reg+reg addressing is valid and
3161 constant offset zero should not occur due to canonicalization.
3162 Allow any offset when not strict before reload. */
3169 /* SPE vector modes. */
3170 return SPE_CONST_OFFSET_OK (offset);
3174 if (TARGET_E500_DOUBLE)
3175 return SPE_CONST_OFFSET_OK (offset);
3178 /* On e500v2, we may have:
3180 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3182 Which gets addressed with evldd instructions. */
3183 if (TARGET_E500_DOUBLE)
3184 return SPE_CONST_OFFSET_OK (offset);
3186 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3188 else if (offset & 3)
3193 if (TARGET_E500_DOUBLE)
3194 return (SPE_CONST_OFFSET_OK (offset)
3195 && SPE_CONST_OFFSET_OK (offset + 8));
3199 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3201 else if (offset & 3)
3212 return (offset < 0x10000) && (offset + extra < 0x10000);
3216 legitimate_indexed_address_p (rtx x, int strict)
3220 if (GET_CODE (x) != PLUS)
3226 /* Recognize the rtl generated by reload which we know will later be
3227 replaced with proper base and index regs. */
3229 && reload_in_progress
3230 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3234 return (REG_P (op0) && REG_P (op1)
3235 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3236 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3237 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3238 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3242 legitimate_indirect_address_p (rtx x, int strict)
3244 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3248 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3250 if (!TARGET_MACHO || !flag_pic
3251 || mode != SImode || GET_CODE (x) != MEM)
3255 if (GET_CODE (x) != LO_SUM)
3257 if (GET_CODE (XEXP (x, 0)) != REG)
3259 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3263 return CONSTANT_P (x);
3267 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3269 if (GET_CODE (x) != LO_SUM)
3271 if (GET_CODE (XEXP (x, 0)) != REG)
3273 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3275 /* Restrict addressing for DI because of our SUBREG hackery. */
3276 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3281 if (TARGET_ELF || TARGET_MACHO)
3283 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3287 if (GET_MODE_NUNITS (mode) != 1)
3289 if (GET_MODE_BITSIZE (mode) > 64
3290 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3291 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3294 return CONSTANT_P (x);
3301 /* Try machine-dependent ways of modifying an illegitimate address
3302 to be legitimate. If we find one, return the new, valid address.
3303 This is used from only one place: `memory_address' in explow.c.
3305 OLDX is the address as it was before break_out_memory_refs was
3306 called. In some cases it is useful to look at this to decide what
3309 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3311 It is always safe for this function to do nothing. It exists to
3312 recognize opportunities to optimize the output.
3314 On RS/6000, first check for the sum of a register with a constant
3315 integer that is out of range. If so, generate code to add the
3316 constant with the low-order 16 bits masked to the register and force
3317 this result into another register (this can be done with `cau').
3318 Then generate an address of REG+(CONST&0xffff), allowing for the
3319 possibility of bit 16 being a one.
3321 Then check for the sum of a register and something not constant, try to
3322 load the other things into a register and return the sum. */
3325 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3326 enum machine_mode mode)
3328 if (GET_CODE (x) == SYMBOL_REF)
3330 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3332 return rs6000_legitimize_tls_address (x, model);
3335 if (GET_CODE (x) == PLUS
3336 && GET_CODE (XEXP (x, 0)) == REG
3337 && GET_CODE (XEXP (x, 1)) == CONST_INT
3338 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3340 HOST_WIDE_INT high_int, low_int;
3342 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3343 high_int = INTVAL (XEXP (x, 1)) - low_int;
3344 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3345 GEN_INT (high_int)), 0);
3346 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3348 else if (GET_CODE (x) == PLUS
3349 && GET_CODE (XEXP (x, 0)) == REG
3350 && GET_CODE (XEXP (x, 1)) != CONST_INT
3351 && GET_MODE_NUNITS (mode) == 1
3352 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3354 || (((mode != DImode && mode != DFmode && mode != DDmode)
3355 || TARGET_E500_DOUBLE)
3356 && mode != TFmode && mode != TDmode))
3357 && (TARGET_POWERPC64 || mode != DImode)
3360 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3361 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3363 else if (ALTIVEC_VECTOR_MODE (mode))
3367 /* Make sure both operands are registers. */
3368 if (GET_CODE (x) == PLUS)
3369 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3370 force_reg (Pmode, XEXP (x, 1)));
3372 reg = force_reg (Pmode, x);
3375 else if (SPE_VECTOR_MODE (mode)
3376 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3377 || mode == DDmode || mode == TDmode
3378 || mode == DImode)))
3382 /* We accept [reg + reg] and [reg + OFFSET]. */
3384 if (GET_CODE (x) == PLUS)
3386 rtx op1 = XEXP (x, 0);
3387 rtx op2 = XEXP (x, 1);
3389 op1 = force_reg (Pmode, op1);
3391 if (GET_CODE (op2) != REG
3392 && (GET_CODE (op2) != CONST_INT
3393 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3394 op2 = force_reg (Pmode, op2);
3396 return gen_rtx_PLUS (Pmode, op1, op2);
3399 return force_reg (Pmode, x);
3405 && GET_CODE (x) != CONST_INT
3406 && GET_CODE (x) != CONST_DOUBLE
3408 && GET_MODE_NUNITS (mode) == 1
3409 && (GET_MODE_BITSIZE (mode) <= 32
3410 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3412 rtx reg = gen_reg_rtx (Pmode);
3413 emit_insn (gen_elf_high (reg, x));
3414 return gen_rtx_LO_SUM (Pmode, reg, x);
3416 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3419 && ! MACHO_DYNAMIC_NO_PIC_P
3421 && GET_CODE (x) != CONST_INT
3422 && GET_CODE (x) != CONST_DOUBLE
3424 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3428 rtx reg = gen_reg_rtx (Pmode);
3429 emit_insn (gen_macho_high (reg, x));
3430 return gen_rtx_LO_SUM (Pmode, reg, x);
3433 && constant_pool_expr_p (x)
3434 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3436 return create_TOC_reference (x);
3442 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3443 We need to emit DTP-relative relocations. */
3446 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3451 fputs ("\t.long\t", file);
3454 fputs (DOUBLE_INT_ASM_OP, file);
3459 output_addr_const (file, x);
3460 fputs ("@dtprel+0x8000", file);
3463 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3465 static GTY(()) rtx rs6000_tls_symbol;
3467 rs6000_tls_get_addr (void)
3469 if (!rs6000_tls_symbol)
3470 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3472 return rs6000_tls_symbol;
3475 /* Construct the SYMBOL_REF for TLS GOT references. */
3477 static GTY(()) rtx rs6000_got_symbol;
3479 rs6000_got_sym (void)
3481 if (!rs6000_got_symbol)
3483 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3484 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3485 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3488 return rs6000_got_symbol;
3491 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3492 this (thread-local) address. */
3495 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3499 dest = gen_reg_rtx (Pmode);
3500 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3506 tlsreg = gen_rtx_REG (Pmode, 13);
3507 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3511 tlsreg = gen_rtx_REG (Pmode, 2);
3512 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3516 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3520 tmp = gen_reg_rtx (Pmode);
3523 tlsreg = gen_rtx_REG (Pmode, 13);
3524 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3528 tlsreg = gen_rtx_REG (Pmode, 2);
3529 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3533 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3535 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3540 rtx r3, got, tga, tmp1, tmp2, eqv;
3542 /* We currently use relocations like @got@tlsgd for tls, which
3543 means the linker will handle allocation of tls entries, placing
3544 them in the .got section. So use a pointer to the .got section,
3545 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3546 or to secondary GOT sections used by 32-bit -fPIC. */
3548 got = gen_rtx_REG (Pmode, 2);
3552 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3555 rtx gsym = rs6000_got_sym ();
3556 got = gen_reg_rtx (Pmode);
3558 rs6000_emit_move (got, gsym, Pmode);
3564 tmp1 = gen_reg_rtx (Pmode);
3565 tmp2 = gen_reg_rtx (Pmode);
3566 tmp3 = gen_reg_rtx (Pmode);
3567 mem = gen_const_mem (Pmode, tmp1);
3569 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3570 emit_move_insn (tmp1,
3571 gen_rtx_REG (Pmode, LR_REGNO));
3572 emit_move_insn (tmp2, mem);
3573 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3574 last = emit_move_insn (got, tmp3);
3575 set_unique_reg_note (last, REG_EQUAL, gsym);
3576 maybe_encapsulate_block (first, last, gsym);
3581 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3583 r3 = gen_rtx_REG (Pmode, 3);
3585 insn = gen_tls_gd_64 (r3, got, addr);
3587 insn = gen_tls_gd_32 (r3, got, addr);
3590 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3591 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3592 insn = emit_call_insn (insn);
3593 CONST_OR_PURE_CALL_P (insn) = 1;
3594 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3595 insn = get_insns ();
3597 emit_libcall_block (insn, dest, r3, addr);
3599 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3601 r3 = gen_rtx_REG (Pmode, 3);
3603 insn = gen_tls_ld_64 (r3, got);
3605 insn = gen_tls_ld_32 (r3, got);
3608 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3609 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3610 insn = emit_call_insn (insn);
3611 CONST_OR_PURE_CALL_P (insn) = 1;
3612 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3613 insn = get_insns ();
3615 tmp1 = gen_reg_rtx (Pmode);
3616 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3618 emit_libcall_block (insn, tmp1, r3, eqv);
3619 if (rs6000_tls_size == 16)
3622 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3624 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3626 else if (rs6000_tls_size == 32)
3628 tmp2 = gen_reg_rtx (Pmode);
3630 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3632 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3635 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3637 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3641 tmp2 = gen_reg_rtx (Pmode);
3643 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3645 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3647 insn = gen_rtx_SET (Pmode, dest,
3648 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3654 /* IE, or 64-bit offset LE. */
3655 tmp2 = gen_reg_rtx (Pmode);
3657 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3659 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3662 insn = gen_tls_tls_64 (dest, tmp2, addr);
3664 insn = gen_tls_tls_32 (dest, tmp2, addr);
3672 /* Return 1 if X contains a thread-local symbol. */
3675 rs6000_tls_referenced_p (rtx x)
3677 if (! TARGET_HAVE_TLS)
3680 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3683 /* Return 1 if *X is a thread-local symbol. This is the same as
3684 rs6000_tls_symbol_ref except for the type of the unused argument. */
3687 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3689 return RS6000_SYMBOL_REF_TLS_P (*x);
3692 /* The convention appears to be to define this wherever it is used.
3693 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3694 is now used here. */
3695 #ifndef REG_MODE_OK_FOR_BASE_P
3696 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3699 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3700 replace the input X, or the original X if no replacement is called for.
3701 The output parameter *WIN is 1 if the calling macro should goto WIN,
3704 For RS/6000, we wish to handle large displacements off a base
3705 register by splitting the addend across an addiu/addis and the mem insn.
3706 This cuts number of extra insns needed from 3 to 1.
3708 On Darwin, we use this to generate code for floating point constants.
3709 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3710 The Darwin code is inside #if TARGET_MACHO because only then is
3711 machopic_function_base_name() defined. */
3713 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3714 int opnum, int type,
3715 int ind_levels ATTRIBUTE_UNUSED, int *win)
3717 /* We must recognize output that we have already generated ourselves. */
3718 if (GET_CODE (x) == PLUS
3719 && GET_CODE (XEXP (x, 0)) == PLUS
3720 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3721 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3722 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3724 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3725 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3726 opnum, (enum reload_type)type);
3732 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3733 && GET_CODE (x) == LO_SUM
3734 && GET_CODE (XEXP (x, 0)) == PLUS
3735 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3736 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3737 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3738 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3739 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3740 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3741 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3743 /* Result of previous invocation of this function on Darwin
3744 floating point constant. */
3745 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3746 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3747 opnum, (enum reload_type)type);
3753 /* Force ld/std non-word aligned offset into base register by wrapping
3755 if (GET_CODE (x) == PLUS
3756 && GET_CODE (XEXP (x, 0)) == REG
3757 && REGNO (XEXP (x, 0)) < 32
3758 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3759 && GET_CODE (XEXP (x, 1)) == CONST_INT
3760 && (INTVAL (XEXP (x, 1)) & 3) != 0
3761 && !ALTIVEC_VECTOR_MODE (mode)
3762 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3763 && TARGET_POWERPC64)
3765 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3766 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3767 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3768 opnum, (enum reload_type) type);
3773 if (GET_CODE (x) == PLUS
3774 && GET_CODE (XEXP (x, 0)) == REG
3775 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3776 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3777 && GET_CODE (XEXP (x, 1)) == CONST_INT
3778 && !SPE_VECTOR_MODE (mode)
3779 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3781 && !ALTIVEC_VECTOR_MODE (mode))
3783 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3784 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3786 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3788 /* Check for 32-bit overflow. */
3789 if (high + low != val)
3795 /* Reload the high part into a base reg; leave the low part
3796 in the mem directly. */
3798 x = gen_rtx_PLUS (GET_MODE (x),
3799 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3803 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3804 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3805 opnum, (enum reload_type)type);
3810 if (GET_CODE (x) == SYMBOL_REF
3811 && !ALTIVEC_VECTOR_MODE (mode)
3812 && !SPE_VECTOR_MODE (mode)
3814 && DEFAULT_ABI == ABI_DARWIN
3815 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3817 && DEFAULT_ABI == ABI_V4
3820 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3821 The same goes for DImode without 64-bit gprs and DFmode
3825 && (mode != DImode || TARGET_POWERPC64)
3826 && (mode != DFmode || TARGET_POWERPC64
3827 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3832 rtx offset = gen_rtx_CONST (Pmode,
3833 gen_rtx_MINUS (Pmode, x,
3834 machopic_function_base_sym ()));
3835 x = gen_rtx_LO_SUM (GET_MODE (x),
3836 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3837 gen_rtx_HIGH (Pmode, offset)), offset);
3841 x = gen_rtx_LO_SUM (GET_MODE (x),
3842 gen_rtx_HIGH (Pmode, x), x);
3844 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3845 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3846 opnum, (enum reload_type)type);
3851 /* Reload an offset address wrapped by an AND that represents the
3852 masking of the lower bits. Strip the outer AND and let reload
3853 convert the offset address into an indirect address. */
3855 && ALTIVEC_VECTOR_MODE (mode)
3856 && GET_CODE (x) == AND
3857 && GET_CODE (XEXP (x, 0)) == PLUS
3858 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3859 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3860 && GET_CODE (XEXP (x, 1)) == CONST_INT
3861 && INTVAL (XEXP (x, 1)) == -16)
3869 && constant_pool_expr_p (x)
3870 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3872 x = create_TOC_reference (x);
3880 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3881 that is a valid memory address for an instruction.
3882 The MODE argument is the machine mode for the MEM expression
3883 that wants to use this address.
3885 On the RS/6000, there are four valid address: a SYMBOL_REF that
3886 refers to a constant pool entry of an address (or the sum of it
3887 plus a constant), a short (16-bit signed) constant plus a register,
3888 the sum of two registers, or a register indirect, possibly with an
3889 auto-increment. For DFmode and DImode with a constant plus register,
3890 we must ensure that both words are addressable or PowerPC64 with offset
3893 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3894 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3895 because adjacent memory cells are accessed by adding word-sized offsets
3896 during assembly output. */
3898 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3900 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3902 && ALTIVEC_VECTOR_MODE (mode)
3903 && GET_CODE (x) == AND
3904 && GET_CODE (XEXP (x, 1)) == CONST_INT
3905 && INTVAL (XEXP (x, 1)) == -16)
3908 if (RS6000_SYMBOL_REF_TLS_P (x))
3910 if (legitimate_indirect_address_p (x, reg_ok_strict))
3912 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3913 && !ALTIVEC_VECTOR_MODE (mode)
3914 && !SPE_VECTOR_MODE (mode)
3917 /* Restrict addressing for DI because of our SUBREG hackery. */
3918 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3921 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3923 if (legitimate_small_data_p (mode, x))
3925 if (legitimate_constant_pool_address_p (x))
3927 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3929 && GET_CODE (x) == PLUS
3930 && GET_CODE (XEXP (x, 0)) == REG
3931 && (XEXP (x, 0) == virtual_stack_vars_rtx
3932 || XEXP (x, 0) == arg_pointer_rtx)
3933 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3935 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3940 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3942 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3943 && (TARGET_POWERPC64 || mode != DImode)
3944 && legitimate_indexed_address_p (x, reg_ok_strict))
3946 if (GET_CODE (x) == PRE_MODIFY
3950 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3952 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3953 && (TARGET_POWERPC64 || mode != DImode)
3954 && !ALTIVEC_VECTOR_MODE (mode)
3955 && !SPE_VECTOR_MODE (mode)
3956 /* Restrict addressing for DI because of our SUBREG hackery. */
3957 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3959 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
3960 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
3961 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
3962 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3964 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3969 /* Go to LABEL if ADDR (a legitimate address expression)
3970 has an effect that depends on the machine mode it is used for.
3972 On the RS/6000 this is true of all integral offsets (since AltiVec
3973 modes don't allow them) or is a pre-increment or decrement.
3975 ??? Except that due to conceptual problems in offsettable_address_p
3976 we can't really report the problems of integral offsets. So leave
3977 this assuming that the adjustable offset must be valid for the
3978 sub-words of a TFmode operand, which is what we had before. */
3981 rs6000_mode_dependent_address (rtx addr)
3983 switch (GET_CODE (addr))
3986 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3988 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3989 return val + 12 + 0x8000 >= 0x10000;
3999 return TARGET_UPDATE;
4008 /* More elaborate version of recog's offsettable_memref_p predicate
4009 that works around the ??? note of rs6000_mode_dependent_address.
4010 In particular it accepts
4012 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4014 in 32-bit mode, that the recog predicate rejects. */
4017 rs6000_offsettable_memref_p (rtx op)
4022 /* First mimic offsettable_memref_p. */
4023 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4026 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4027 the latter predicate knows nothing about the mode of the memory
4028 reference and, therefore, assumes that it is the largest supported
4029 mode (TFmode). As a consequence, legitimate offsettable memory
4030 references are rejected. rs6000_legitimate_offset_address_p contains
4031 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4032 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4035 /* Return number of consecutive hard regs needed starting at reg REGNO
4036 to hold something of mode MODE.
4037 This is ordinarily the length in words of a value of mode MODE
4038 but can be less for certain modes in special long registers.
4040 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4041 scalar instructions. The upper 32 bits are only available to the
4044 POWER and PowerPC GPRs hold 32 bits worth;
4045 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4048 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4050 if (FP_REGNO_P (regno))
4051 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4053 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4054 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4056 if (ALTIVEC_REGNO_P (regno))
4058 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4060 /* The value returned for SCmode in the E500 double case is 2 for
4061 ABI compatibility; storing an SCmode value in a single register
4062 would require function_arg and rs6000_spe_function_arg to handle
4063 SCmode so as to pass the value correctly in a pair of
4065 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
4066 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4068 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4071 /* Change register usage conditional on target flags. */
4073 rs6000_conditional_register_usage (void)
4077 /* Set MQ register fixed (already call_used) if not POWER
4078 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4083 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4085 fixed_regs[13] = call_used_regs[13]
4086 = call_really_used_regs[13] = 1;
4088 /* Conditionally disable FPRs. */
4089 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4090 for (i = 32; i < 64; i++)
4091 fixed_regs[i] = call_used_regs[i]
4092 = call_really_used_regs[i] = 1;
4094 /* The TOC register is not killed across calls in a way that is
4095 visible to the compiler. */
4096 if (DEFAULT_ABI == ABI_AIX)
4097 call_really_used_regs[2] = 0;
4099 if (DEFAULT_ABI == ABI_V4
4100 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4102 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4104 if (DEFAULT_ABI == ABI_V4
4105 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4107 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4108 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4109 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4111 if (DEFAULT_ABI == ABI_DARWIN
4112 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4113 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4114 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4115 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4117 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4118 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4119 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4122 global_regs[VSCR_REGNO] = 1;
4126 global_regs[SPEFSCR_REGNO] = 1;
4127 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4128 registers in prologues and epilogues. We no longer use r14
4129 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4130 pool for link-compatibility with older versions of GCC. Once
4131 "old" code has died out, we can return r14 to the allocation
4134 = call_used_regs[14]
4135 = call_really_used_regs[14] = 1;
4138 if (! TARGET_ALTIVEC)
4140 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4141 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4142 call_really_used_regs[VRSAVE_REGNO] = 1;
4145 if (TARGET_ALTIVEC_ABI)
4146 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4147 call_used_regs[i] = call_really_used_regs[i] = 1;
4150 /* Try to output insns to set TARGET equal to the constant C if it can
4151 be done in less than N insns. Do all computations in MODE.
4152 Returns the place where the output has been placed if it can be
4153 done and the insns have been emitted. If it would take more than N
4154 insns, zero is returned and no insns and emitted. */
4157 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4158 rtx source, int n ATTRIBUTE_UNUSED)
4160 rtx result, insn, set;
4161 HOST_WIDE_INT c0, c1;
4168 dest = gen_reg_rtx (mode);
4169 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4173 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4175 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4176 GEN_INT (INTVAL (source)
4177 & (~ (HOST_WIDE_INT) 0xffff))));
4178 emit_insn (gen_rtx_SET (VOIDmode, dest,
4179 gen_rtx_IOR (SImode, copy_rtx (result),
4180 GEN_INT (INTVAL (source) & 0xffff))));
4185 switch (GET_CODE (source))
4188 c0 = INTVAL (source);
4193 #if HOST_BITS_PER_WIDE_INT >= 64
4194 c0 = CONST_DOUBLE_LOW (source);
4197 c0 = CONST_DOUBLE_LOW (source);
4198 c1 = CONST_DOUBLE_HIGH (source);
4206 result = rs6000_emit_set_long_const (dest, c0, c1);
4213 insn = get_last_insn ();
4214 set = single_set (insn);
4215 if (! CONSTANT_P (SET_SRC (set)))
4216 set_unique_reg_note (insn, REG_EQUAL, source);
4221 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4222 fall back to a straight forward decomposition. We do this to avoid
4223 exponential run times encountered when looking for longer sequences
4224 with rs6000_emit_set_const. */
4226 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4228 if (!TARGET_POWERPC64)
4230 rtx operand1, operand2;
4232 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4234 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4236 emit_move_insn (operand1, GEN_INT (c1));
4237 emit_move_insn (operand2, GEN_INT (c2));
4241 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4244 ud2 = (c1 & 0xffff0000) >> 16;
4245 #if HOST_BITS_PER_WIDE_INT >= 64
4249 ud4 = (c2 & 0xffff0000) >> 16;
4251 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4252 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4255 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4257 emit_move_insn (dest, GEN_INT (ud1));
4260 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4261 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4264 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4267 emit_move_insn (dest, GEN_INT (ud2 << 16));
4269 emit_move_insn (copy_rtx (dest),
4270 gen_rtx_IOR (DImode, copy_rtx (dest),
4273 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4274 || (ud4 == 0 && ! (ud3 & 0x8000)))
4277 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4280 emit_move_insn (dest, GEN_INT (ud3 << 16));
4283 emit_move_insn (copy_rtx (dest),
4284 gen_rtx_IOR (DImode, copy_rtx (dest),
4286 emit_move_insn (copy_rtx (dest),
4287 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4290 emit_move_insn (copy_rtx (dest),
4291 gen_rtx_IOR (DImode, copy_rtx (dest),
4297 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4300 emit_move_insn (dest, GEN_INT (ud4 << 16));
4303 emit_move_insn (copy_rtx (dest),
4304 gen_rtx_IOR (DImode, copy_rtx (dest),
4307 emit_move_insn (copy_rtx (dest),
4308 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4311 emit_move_insn (copy_rtx (dest),
4312 gen_rtx_IOR (DImode, copy_rtx (dest),
4313 GEN_INT (ud2 << 16)));
4315 emit_move_insn (copy_rtx (dest),
4316 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4322 /* Helper for the following. Get rid of [r+r] memory refs
4323 in cases where it won't work (TImode, TFmode, TDmode). */
4326 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4328 if (GET_CODE (operands[0]) == MEM
4329 && GET_CODE (XEXP (operands[0], 0)) != REG
4330 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4331 && ! reload_in_progress)
4333 = replace_equiv_address (operands[0],
4334 copy_addr_to_reg (XEXP (operands[0], 0)));
4336 if (GET_CODE (operands[1]) == MEM
4337 && GET_CODE (XEXP (operands[1], 0)) != REG
4338 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4339 && ! reload_in_progress)
4341 = replace_equiv_address (operands[1],
4342 copy_addr_to_reg (XEXP (operands[1], 0)));
4345 /* Emit a move from SOURCE to DEST in mode MODE. */
4347 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4351 operands[1] = source;
4353 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4354 if (GET_CODE (operands[1]) == CONST_DOUBLE
4355 && ! FLOAT_MODE_P (mode)
4356 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4358 /* FIXME. This should never happen. */
4359 /* Since it seems that it does, do the safe thing and convert
4361 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4363 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4364 || FLOAT_MODE_P (mode)
4365 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4366 || CONST_DOUBLE_LOW (operands[1]) < 0)
4367 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4368 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4370 /* Check if GCC is setting up a block move that will end up using FP
4371 registers as temporaries. We must make sure this is acceptable. */
4372 if (GET_CODE (operands[0]) == MEM
4373 && GET_CODE (operands[1]) == MEM
4375 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4376 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4377 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4378 ? 32 : MEM_ALIGN (operands[0])))
4379 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4381 : MEM_ALIGN (operands[1]))))
4382 && ! MEM_VOLATILE_P (operands [0])
4383 && ! MEM_VOLATILE_P (operands [1]))
4385 emit_move_insn (adjust_address (operands[0], SImode, 0),
4386 adjust_address (operands[1], SImode, 0));
4387 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4388 adjust_address (copy_rtx (operands[1]), SImode, 4));
4392 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4393 && !gpc_reg_operand (operands[1], mode))
4394 operands[1] = force_reg (mode, operands[1]);
4396 if (mode == SFmode && ! TARGET_POWERPC
4397 && TARGET_HARD_FLOAT && TARGET_FPRS
4398 && GET_CODE (operands[0]) == MEM)
4402 if (reload_in_progress || reload_completed)
4403 regnum = true_regnum (operands[1]);
4404 else if (GET_CODE (operands[1]) == REG)
4405 regnum = REGNO (operands[1]);
4409 /* If operands[1] is a register, on POWER it may have
4410 double-precision data in it, so truncate it to single
4412 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4415 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4416 : gen_reg_rtx (mode));
4417 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4418 operands[1] = newreg;
4422 /* Recognize the case where operand[1] is a reference to thread-local
4423 data and load its address to a register. */
4424 if (rs6000_tls_referenced_p (operands[1]))
4426 enum tls_model model;
4427 rtx tmp = operands[1];
4430 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4432 addend = XEXP (XEXP (tmp, 0), 1);
4433 tmp = XEXP (XEXP (tmp, 0), 0);
4436 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4437 model = SYMBOL_REF_TLS_MODEL (tmp);
4438 gcc_assert (model != 0);
4440 tmp = rs6000_legitimize_tls_address (tmp, model);
4443 tmp = gen_rtx_PLUS (mode, tmp, addend);
4444 tmp = force_operand (tmp, operands[0]);
4449 /* Handle the case where reload calls us with an invalid address. */
4450 if (reload_in_progress && mode == Pmode
4451 && (! general_operand (operands[1], mode)
4452 || ! nonimmediate_operand (operands[0], mode)))
4455 /* 128-bit constant floating-point values on Darwin should really be
4456 loaded as two parts. */
4457 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4458 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4460 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4461 know how to get a DFmode SUBREG of a TFmode. */
4462 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4463 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4464 simplify_gen_subreg (imode, operands[1], mode, 0),
4466 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4467 GET_MODE_SIZE (imode)),
4468 simplify_gen_subreg (imode, operands[1], mode,
4469 GET_MODE_SIZE (imode)),
4474 /* FIXME: In the long term, this switch statement should go away
4475 and be replaced by a sequence of tests based on things like
4481 if (CONSTANT_P (operands[1])
4482 && GET_CODE (operands[1]) != CONST_INT)
4483 operands[1] = force_const_mem (mode, operands[1]);
4488 rs6000_eliminate_indexed_memrefs (operands);
4494 if (CONSTANT_P (operands[1])
4495 && ! easy_fp_constant (operands[1], mode))
4496 operands[1] = force_const_mem (mode, operands[1]);
4507 if (CONSTANT_P (operands[1])
4508 && !easy_vector_constant (operands[1], mode))
4509 operands[1] = force_const_mem (mode, operands[1]);
4514 /* Use default pattern for address of ELF small data */
4517 && DEFAULT_ABI == ABI_V4
4518 && (GET_CODE (operands[1]) == SYMBOL_REF
4519 || GET_CODE (operands[1]) == CONST)
4520 && small_data_operand (operands[1], mode))
4522 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4526 if (DEFAULT_ABI == ABI_V4
4527 && mode == Pmode && mode == SImode
4528 && flag_pic == 1 && got_operand (operands[1], mode))
4530 emit_insn (gen_movsi_got (operands[0], operands[1]));
4534 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4538 && CONSTANT_P (operands[1])
4539 && GET_CODE (operands[1]) != HIGH
4540 && GET_CODE (operands[1]) != CONST_INT)
4542 rtx target = (!can_create_pseudo_p ()
4544 : gen_reg_rtx (mode));
4546 /* If this is a function address on -mcall-aixdesc,
4547 convert it to the address of the descriptor. */
4548 if (DEFAULT_ABI == ABI_AIX
4549 && GET_CODE (operands[1]) == SYMBOL_REF
4550 && XSTR (operands[1], 0)[0] == '.')
4552 const char *name = XSTR (operands[1], 0);
4554 while (*name == '.')
4556 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4557 CONSTANT_POOL_ADDRESS_P (new_ref)
4558 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4559 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4560 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4561 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4562 operands[1] = new_ref;
4565 if (DEFAULT_ABI == ABI_DARWIN)
4568 if (MACHO_DYNAMIC_NO_PIC_P)
4570 /* Take care of any required data indirection. */
4571 operands[1] = rs6000_machopic_legitimize_pic_address (
4572 operands[1], mode, operands[0]);
4573 if (operands[0] != operands[1])
4574 emit_insn (gen_rtx_SET (VOIDmode,
4575 operands[0], operands[1]));
4579 emit_insn (gen_macho_high (target, operands[1]));
4580 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4584 emit_insn (gen_elf_high (target, operands[1]));
4585 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4589 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4590 and we have put it in the TOC, we just need to make a TOC-relative
4593 && GET_CODE (operands[1]) == SYMBOL_REF
4594 && constant_pool_expr_p (operands[1])
4595 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4596 get_pool_mode (operands[1])))
4598 operands[1] = create_TOC_reference (operands[1]);
4600 else if (mode == Pmode
4601 && CONSTANT_P (operands[1])
4602 && ((GET_CODE (operands[1]) != CONST_INT
4603 && ! easy_fp_constant (operands[1], mode))
4604 || (GET_CODE (operands[1]) == CONST_INT
4605 && num_insns_constant (operands[1], mode) > 2)
4606 || (GET_CODE (operands[0]) == REG
4607 && FP_REGNO_P (REGNO (operands[0]))))
4608 && GET_CODE (operands[1]) != HIGH
4609 && ! legitimate_constant_pool_address_p (operands[1])
4610 && ! toc_relative_expr_p (operands[1]))
4612 /* Emit a USE operation so that the constant isn't deleted if
4613 expensive optimizations are turned on because nobody
4614 references it. This should only be done for operands that
4615 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4616 This should not be done for operands that contain LABEL_REFs.
4617 For now, we just handle the obvious case. */
4618 if (GET_CODE (operands[1]) != LABEL_REF)
4619 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4622 /* Darwin uses a special PIC legitimizer. */
4623 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4626 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4628 if (operands[0] != operands[1])
4629 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4634 /* If we are to limit the number of things we put in the TOC and
4635 this is a symbol plus a constant we can add in one insn,
4636 just put the symbol in the TOC and add the constant. Don't do
4637 this if reload is in progress. */
4638 if (GET_CODE (operands[1]) == CONST
4639 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4640 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4641 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4642 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4643 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4644 && ! side_effects_p (operands[0]))
4647 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4648 rtx other = XEXP (XEXP (operands[1], 0), 1);
4650 sym = force_reg (mode, sym);
4652 emit_insn (gen_addsi3 (operands[0], sym, other));
4654 emit_insn (gen_adddi3 (operands[0], sym, other));
4658 operands[1] = force_const_mem (mode, operands[1]);
4661 && constant_pool_expr_p (XEXP (operands[1], 0))
4662 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4663 get_pool_constant (XEXP (operands[1], 0)),
4664 get_pool_mode (XEXP (operands[1], 0))))
4667 = gen_const_mem (mode,
4668 create_TOC_reference (XEXP (operands[1], 0)));
4669 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4675 rs6000_eliminate_indexed_memrefs (operands);
4679 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4681 gen_rtx_SET (VOIDmode,
4682 operands[0], operands[1]),
4683 gen_rtx_CLOBBER (VOIDmode,
4684 gen_rtx_SCRATCH (SImode)))));
4693 /* Above, we may have called force_const_mem which may have returned
4694 an invalid address. If we can, fix this up; otherwise, reload will
4695 have to deal with it. */
4696 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4697 operands[1] = validize_mem (operands[1]);
4700 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4703 /* Nonzero if we can use a floating-point register to pass this arg. */
4704 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4705 (SCALAR_FLOAT_MODE_P (MODE) \
4706 && (MODE) != SDmode \
4707 && (CUM)->fregno <= FP_ARG_MAX_REG \
4708 && TARGET_HARD_FLOAT && TARGET_FPRS)
4710 /* Nonzero if we can use an AltiVec register to pass this arg. */
4711 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4712 (ALTIVEC_VECTOR_MODE (MODE) \
4713 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4714 && TARGET_ALTIVEC_ABI \
4717 /* Return a nonzero value to say to return the function value in
4718 memory, just as large structures are always returned. TYPE will be
4719 the data type of the value, and FNTYPE will be the type of the
4720 function doing the returning, or @code{NULL} for libcalls.
4722 The AIX ABI for the RS/6000 specifies that all structures are
4723 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4724 specifies that structures <= 8 bytes are returned in r3/r4, but a
4725 draft put them in memory, and GCC used to implement the draft
4726 instead of the final standard. Therefore, aix_struct_return
4727 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4728 compatibility can change DRAFT_V4_STRUCT_RET to override the
4729 default, and -m switches get the final word. See
4730 rs6000_override_options for more details.
4732 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4733 long double support is enabled. These values are returned in memory.
4735 int_size_in_bytes returns -1 for variable size objects, which go in
4736 memory always. The cast to unsigned makes -1 > 8. */
4739 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4741 /* In the darwin64 abi, try to use registers for larger structs
4743 if (rs6000_darwin64_abi
4744 && TREE_CODE (type) == RECORD_TYPE
4745 && int_size_in_bytes (type) > 0)
4747 CUMULATIVE_ARGS valcum;
4751 valcum.fregno = FP_ARG_MIN_REG;
4752 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4753 /* Do a trial code generation as if this were going to be passed
4754 as an argument; if any part goes in memory, we return NULL. */
4755 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4758 /* Otherwise fall through to more conventional ABI rules. */
4761 if (AGGREGATE_TYPE_P (type)
4762 && (aix_struct_return
4763 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4766 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4767 modes only exist for GCC vector types if -maltivec. */
4768 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4769 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4772 /* Return synthetic vectors in memory. */
4773 if (TREE_CODE (type) == VECTOR_TYPE
4774 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4776 static bool warned_for_return_big_vectors = false;
4777 if (!warned_for_return_big_vectors)
4779 warning (0, "GCC vector returned by reference: "
4780 "non-standard ABI extension with no compatibility guarantee");
4781 warned_for_return_big_vectors = true;
4786 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4792 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4793 for a call to a function whose data type is FNTYPE.
4794 For a library call, FNTYPE is 0.
4796 For incoming args we set the number of arguments in the prototype large
4797 so we never return a PARALLEL. */
4800 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4801 rtx libname ATTRIBUTE_UNUSED, int incoming,
4802 int libcall, int n_named_args)
4804 static CUMULATIVE_ARGS zero_cumulative;
4806 *cum = zero_cumulative;
4808 cum->fregno = FP_ARG_MIN_REG;
4809 cum->vregno = ALTIVEC_ARG_MIN_REG;
4810 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4811 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4812 ? CALL_LIBCALL : CALL_NORMAL);
4813 cum->sysv_gregno = GP_ARG_MIN_REG;
4814 cum->stdarg = fntype
4815 && (TYPE_ARG_TYPES (fntype) != 0
4816 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4817 != void_type_node));
4819 cum->nargs_prototype = 0;
4820 if (incoming || cum->prototype)
4821 cum->nargs_prototype = n_named_args;
4823 /* Check for a longcall attribute. */
4824 if ((!fntype && rs6000_default_long_calls)
4826 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4827 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4828 cum->call_cookie |= CALL_LONG;
4830 if (TARGET_DEBUG_ARG)
4832 fprintf (stderr, "\ninit_cumulative_args:");
4835 tree ret_type = TREE_TYPE (fntype);
4836 fprintf (stderr, " ret code = %s,",
4837 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4840 if (cum->call_cookie & CALL_LONG)
4841 fprintf (stderr, " longcall,");
4843 fprintf (stderr, " proto = %d, nargs = %d\n",
4844 cum->prototype, cum->nargs_prototype);
4849 && TARGET_ALTIVEC_ABI
4850 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4852 error ("cannot return value in vector register because"
4853 " altivec instructions are disabled, use -maltivec"
4858 /* Return true if TYPE must be passed on the stack and not in registers. */
4861 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4863 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4864 return must_pass_in_stack_var_size (mode, type);
4866 return must_pass_in_stack_var_size_or_pad (mode, type);
4869 /* If defined, a C expression which determines whether, and in which
4870 direction, to pad out an argument with extra space. The value
4871 should be of type `enum direction': either `upward' to pad above
4872 the argument, `downward' to pad below, or `none' to inhibit
4875 For the AIX ABI structs are always stored left shifted in their
4879 function_arg_padding (enum machine_mode mode, tree type)
4881 #ifndef AGGREGATE_PADDING_FIXED
4882 #define AGGREGATE_PADDING_FIXED 0
4884 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4885 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4888 if (!AGGREGATE_PADDING_FIXED)
4890 /* GCC used to pass structures of the same size as integer types as
4891 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4892 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4893 passed padded downward, except that -mstrict-align further
4894 muddied the water in that multi-component structures of 2 and 4
4895 bytes in size were passed padded upward.
4897 The following arranges for best compatibility with previous
4898 versions of gcc, but removes the -mstrict-align dependency. */
4899 if (BYTES_BIG_ENDIAN)
4901 HOST_WIDE_INT size = 0;
4903 if (mode == BLKmode)
4905 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4906 size = int_size_in_bytes (type);
4909 size = GET_MODE_SIZE (mode);
4911 if (size == 1 || size == 2 || size == 4)
4917 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4919 if (type != 0 && AGGREGATE_TYPE_P (type))
4923 /* Fall back to the default. */
4924 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4927 /* If defined, a C expression that gives the alignment boundary, in bits,
4928 of an argument with the specified mode and type. If it is not defined,
4929 PARM_BOUNDARY is used for all arguments.
4931 V.4 wants long longs and doubles to be double word aligned. Just
4932 testing the mode size is a boneheaded way to do this as it means
4933 that other types such as complex int are also double word aligned.
4934 However, we're stuck with this because changing the ABI might break
4935 existing library interfaces.
4937 Doubleword align SPE vectors.
4938 Quadword align Altivec vectors.
4939 Quadword align large synthetic vector types. */
4942 function_arg_boundary (enum machine_mode mode, tree type)
4944 if (DEFAULT_ABI == ABI_V4
4945 && (GET_MODE_SIZE (mode) == 8
4946 || (TARGET_HARD_FLOAT
4948 && (mode == TFmode || mode == TDmode))))
4950 else if (SPE_VECTOR_MODE (mode)
4951 || (type && TREE_CODE (type) == VECTOR_TYPE
4952 && int_size_in_bytes (type) >= 8
4953 && int_size_in_bytes (type) < 16))
4955 else if (ALTIVEC_VECTOR_MODE (mode)
4956 || (type && TREE_CODE (type) == VECTOR_TYPE
4957 && int_size_in_bytes (type) >= 16))
4959 else if (rs6000_darwin64_abi && mode == BLKmode
4960 && type && TYPE_ALIGN (type) > 64)
4963 return PARM_BOUNDARY;
4966 /* For a function parm of MODE and TYPE, return the starting word in
4967 the parameter area. NWORDS of the parameter area are already used. */
4970 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4973 unsigned int parm_offset;
4975 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4976 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4977 return nwords + (-(parm_offset + nwords) & align);
4980 /* Compute the size (in words) of a function argument. */
4982 static unsigned long
4983 rs6000_arg_size (enum machine_mode mode, tree type)
4987 if (mode != BLKmode)
4988 size = GET_MODE_SIZE (mode);
4990 size = int_size_in_bytes (type);
4993 return (size + 3) >> 2;
4995 return (size + 7) >> 3;
4998 /* Use this to flush pending int fields. */
5001 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5002 HOST_WIDE_INT bitpos)
5004 unsigned int startbit, endbit;
5005 int intregs, intoffset;
5006 enum machine_mode mode;
5008 if (cum->intoffset == -1)
5011 intoffset = cum->intoffset;
5012 cum->intoffset = -1;
5014 if (intoffset % BITS_PER_WORD != 0)
5016 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5018 if (mode == BLKmode)
5020 /* We couldn't find an appropriate mode, which happens,
5021 e.g., in packed structs when there are 3 bytes to load.
5022 Back intoffset back to the beginning of the word in this
5024 intoffset = intoffset & -BITS_PER_WORD;
5028 startbit = intoffset & -BITS_PER_WORD;
5029 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5030 intregs = (endbit - startbit) / BITS_PER_WORD;
5031 cum->words += intregs;
5034 /* The darwin64 ABI calls for us to recurse down through structs,
5035 looking for elements passed in registers. Unfortunately, we have
5036 to track int register count here also because of misalignments
5037 in powerpc alignment mode. */
5040 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5042 HOST_WIDE_INT startbitpos)
5046 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5047 if (TREE_CODE (f) == FIELD_DECL)
5049 HOST_WIDE_INT bitpos = startbitpos;
5050 tree ftype = TREE_TYPE (f);
5051 enum machine_mode mode;
5052 if (ftype == error_mark_node)
5054 mode = TYPE_MODE (ftype);
5056 if (DECL_SIZE (f) != 0
5057 && host_integerp (bit_position (f), 1))
5058 bitpos += int_bit_position (f);
5060 /* ??? FIXME: else assume zero offset. */
5062 if (TREE_CODE (ftype) == RECORD_TYPE)
5063 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5064 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5066 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5067 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5068 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5070 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5072 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5076 else if (cum->intoffset == -1)
5077 cum->intoffset = bitpos;
5081 /* Update the data in CUM to advance over an argument
5082 of mode MODE and data type TYPE.
5083 (TYPE is null for libcalls where that information may not be available.)
5085 Note that for args passed by reference, function_arg will be called
5086 with MODE and TYPE set to that of the pointer to the arg, not the arg
5090 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5091 tree type, int named, int depth)
5095 /* Only tick off an argument if we're not recursing. */
5097 cum->nargs_prototype--;
5099 if (TARGET_ALTIVEC_ABI
5100 && (ALTIVEC_VECTOR_MODE (mode)
5101 || (type && TREE_CODE (type) == VECTOR_TYPE
5102 && int_size_in_bytes (type) == 16)))
5106 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5109 if (!TARGET_ALTIVEC)
5110 error ("cannot pass argument in vector register because"
5111 " altivec instructions are disabled, use -maltivec"
5114 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5115 even if it is going to be passed in a vector register.
5116 Darwin does the same for variable-argument functions. */
5117 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5118 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5128 /* Vector parameters must be 16-byte aligned. This places
5129 them at 2 mod 4 in terms of words in 32-bit mode, since
5130 the parameter save area starts at offset 24 from the
5131 stack. In 64-bit mode, they just have to start on an
5132 even word, since the parameter save area is 16-byte
5133 aligned. Space for GPRs is reserved even if the argument
5134 will be passed in memory. */
5136 align = (2 - cum->words) & 3;
5138 align = cum->words & 1;
5139 cum->words += align + rs6000_arg_size (mode, type);
5141 if (TARGET_DEBUG_ARG)
5143 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5145 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5146 cum->nargs_prototype, cum->prototype,
5147 GET_MODE_NAME (mode));
5151 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5153 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5156 else if (rs6000_darwin64_abi
5158 && TREE_CODE (type) == RECORD_TYPE
5159 && (size = int_size_in_bytes (type)) > 0)
5161 /* Variable sized types have size == -1 and are
5162 treated as if consisting entirely of ints.
5163 Pad to 16 byte boundary if needed. */
5164 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5165 && (cum->words % 2) != 0)
5167 /* For varargs, we can just go up by the size of the struct. */
5169 cum->words += (size + 7) / 8;
5172 /* It is tempting to say int register count just goes up by
5173 sizeof(type)/8, but this is wrong in a case such as
5174 { int; double; int; } [powerpc alignment]. We have to
5175 grovel through the fields for these too. */
5177 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5178 rs6000_darwin64_record_arg_advance_flush (cum,
5179 size * BITS_PER_UNIT);
5182 else if (DEFAULT_ABI == ABI_V4)
5184 if (TARGET_HARD_FLOAT && TARGET_FPRS
5185 && (mode == SFmode || mode == DFmode
5186 || mode == DDmode || mode == TDmode
5187 || (mode == TFmode && !TARGET_IEEEQUAD)))
5189 /* _Decimal128 must use an even/odd register pair. This assumes
5190 that the register number is odd when fregno is odd. */
5191 if (mode == TDmode && (cum->fregno % 2) == 1)
5194 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5195 <= FP_ARG_V4_MAX_REG)
5196 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5199 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5200 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5201 cum->words += cum->words & 1;
5202 cum->words += rs6000_arg_size (mode, type);
5207 int n_words = rs6000_arg_size (mode, type);
5208 int gregno = cum->sysv_gregno;
5210 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5211 (r7,r8) or (r9,r10). As does any other 2 word item such
5212 as complex int due to a historical mistake. */
5214 gregno += (1 - gregno) & 1;
5216 /* Multi-reg args are not split between registers and stack. */
5217 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5219 /* Long long and SPE vectors are aligned on the stack.
5220 So are other 2 word items such as complex int due to
5221 a historical mistake. */
5223 cum->words += cum->words & 1;
5224 cum->words += n_words;
5227 /* Note: continuing to accumulate gregno past when we've started
5228 spilling to the stack indicates the fact that we've started
5229 spilling to the stack to expand_builtin_saveregs. */
5230 cum->sysv_gregno = gregno + n_words;
5233 if (TARGET_DEBUG_ARG)
5235 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5236 cum->words, cum->fregno);
5237 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5238 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5239 fprintf (stderr, "mode = %4s, named = %d\n",
5240 GET_MODE_NAME (mode), named);
5245 int n_words = rs6000_arg_size (mode, type);
5246 int start_words = cum->words;
5247 int align_words = rs6000_parm_start (mode, type, start_words);
5249 cum->words = align_words + n_words;
5251 if (SCALAR_FLOAT_MODE_P (mode)
5253 && TARGET_HARD_FLOAT && TARGET_FPRS)
5255 /* _Decimal128 must be passed in an even/odd float register pair.
5256 This assumes that the register number is odd when fregno is
5258 if (mode == TDmode && (cum->fregno % 2) == 1)
5260 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5263 if (TARGET_DEBUG_ARG)
5265 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5266 cum->words, cum->fregno);
5267 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5268 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5269 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5270 named, align_words - start_words, depth);
5276 spe_build_register_parallel (enum machine_mode mode, int gregno)
5283 r1 = gen_rtx_REG (DImode, gregno);
5284 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5285 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5289 r1 = gen_rtx_REG (DImode, gregno);
5290 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5291 r3 = gen_rtx_REG (DImode, gregno + 2);
5292 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5293 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5296 r1 = gen_rtx_REG (DImode, gregno);
5297 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5298 r3 = gen_rtx_REG (DImode, gregno + 2);
5299 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5300 r5 = gen_rtx_REG (DImode, gregno + 4);
5301 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5302 r7 = gen_rtx_REG (DImode, gregno + 6);
5303 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5304 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5311 /* Determine where to put a SIMD argument on the SPE. */
5313 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5316 int gregno = cum->sysv_gregno;
5318 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5319 are passed and returned in a pair of GPRs for ABI compatibility. */
5320 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5321 || mode == TFmode || mode == TCmode))
5323 int n_words = rs6000_arg_size (mode, type);
5325 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5327 gregno += (1 - gregno) & 1;
5329 /* Multi-reg args are not split between registers and stack. */
5330 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5333 return spe_build_register_parallel (mode, gregno);
5337 int n_words = rs6000_arg_size (mode, type);
5339 /* SPE vectors are put in odd registers. */
5340 if (n_words == 2 && (gregno & 1) == 0)
5343 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5346 enum machine_mode m = SImode;
5348 r1 = gen_rtx_REG (m, gregno);
5349 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5350 r2 = gen_rtx_REG (m, gregno + 1);
5351 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5352 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5359 if (gregno <= GP_ARG_MAX_REG)
5360 return gen_rtx_REG (mode, gregno);
5366 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5367 structure between cum->intoffset and bitpos to integer registers. */
5370 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5371 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5373 enum machine_mode mode;
5375 unsigned int startbit, endbit;
5376 int this_regno, intregs, intoffset;
5379 if (cum->intoffset == -1)
5382 intoffset = cum->intoffset;
5383 cum->intoffset = -1;
5385 /* If this is the trailing part of a word, try to only load that
5386 much into the register. Otherwise load the whole register. Note
5387 that in the latter case we may pick up unwanted bits. It's not a
5388 problem at the moment but may wish to revisit. */
5390 if (intoffset % BITS_PER_WORD != 0)
5392 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5394 if (mode == BLKmode)
5396 /* We couldn't find an appropriate mode, which happens,
5397 e.g., in packed structs when there are 3 bytes to load.
5398 Back intoffset back to the beginning of the word in this
5400 intoffset = intoffset & -BITS_PER_WORD;
5407 startbit = intoffset & -BITS_PER_WORD;
5408 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5409 intregs = (endbit - startbit) / BITS_PER_WORD;
5410 this_regno = cum->words + intoffset / BITS_PER_WORD;
5412 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5415 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5419 intoffset /= BITS_PER_UNIT;
5422 regno = GP_ARG_MIN_REG + this_regno;
5423 reg = gen_rtx_REG (mode, regno);
5425 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5428 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5432 while (intregs > 0);
5435 /* Recursive workhorse for the following. */
5438 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5439 HOST_WIDE_INT startbitpos, rtx rvec[],
5444 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5445 if (TREE_CODE (f) == FIELD_DECL)
5447 HOST_WIDE_INT bitpos = startbitpos;
5448 tree ftype = TREE_TYPE (f);
5449 enum machine_mode mode;
5450 if (ftype == error_mark_node)
5452 mode = TYPE_MODE (ftype);
5454 if (DECL_SIZE (f) != 0
5455 && host_integerp (bit_position (f), 1))
5456 bitpos += int_bit_position (f);
5458 /* ??? FIXME: else assume zero offset. */
5460 if (TREE_CODE (ftype) == RECORD_TYPE)
5461 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5462 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5467 case SCmode: mode = SFmode; break;
5468 case DCmode: mode = DFmode; break;
5469 case TCmode: mode = TFmode; break;
5473 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5475 = gen_rtx_EXPR_LIST (VOIDmode,
5476 gen_rtx_REG (mode, cum->fregno++),
5477 GEN_INT (bitpos / BITS_PER_UNIT));
5478 if (mode == TFmode || mode == TDmode)
5481 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5483 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5485 = gen_rtx_EXPR_LIST (VOIDmode,
5486 gen_rtx_REG (mode, cum->vregno++),
5487 GEN_INT (bitpos / BITS_PER_UNIT));
5489 else if (cum->intoffset == -1)
5490 cum->intoffset = bitpos;
5494 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5495 the register(s) to be used for each field and subfield of a struct
5496 being passed by value, along with the offset of where the
5497 register's value may be found in the block. FP fields go in FP
5498 register, vector fields go in vector registers, and everything
5499 else goes in int registers, packed as in memory.
5501 This code is also used for function return values. RETVAL indicates
5502 whether this is the case.
5504 Much of this is taken from the SPARC V9 port, which has a similar
5505 calling convention. */
5508 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5509 int named, bool retval)
5511 rtx rvec[FIRST_PSEUDO_REGISTER];
5512 int k = 1, kbase = 1;
5513 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5514 /* This is a copy; modifications are not visible to our caller. */
5515 CUMULATIVE_ARGS copy_cum = *orig_cum;
5516 CUMULATIVE_ARGS *cum = ©_cum;
5518 /* Pad to 16 byte boundary if needed. */
5519 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5520 && (cum->words % 2) != 0)
5527 /* Put entries into rvec[] for individual FP and vector fields, and
5528 for the chunks of memory that go in int regs. Note we start at
5529 element 1; 0 is reserved for an indication of using memory, and
5530 may or may not be filled in below. */
5531 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5532 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5534 /* If any part of the struct went on the stack put all of it there.
5535 This hack is because the generic code for
5536 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5537 parts of the struct are not at the beginning. */
5541 return NULL_RTX; /* doesn't go in registers at all */
5543 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5545 if (k > 1 || cum->use_stack)
5546 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5551 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5554 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5558 rtx rvec[GP_ARG_NUM_REG + 1];
5560 if (align_words >= GP_ARG_NUM_REG)
5563 n_units = rs6000_arg_size (mode, type);
5565 /* Optimize the simple case where the arg fits in one gpr, except in
5566 the case of BLKmode due to assign_parms assuming that registers are
5567 BITS_PER_WORD wide. */
5569 || (n_units == 1 && mode != BLKmode))
5570 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5573 if (align_words + n_units > GP_ARG_NUM_REG)
5574 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5575 using a magic NULL_RTX component.
5576 This is not strictly correct. Only some of the arg belongs in
5577 memory, not all of it. However, the normal scheme using
5578 function_arg_partial_nregs can result in unusual subregs, eg.
5579 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5580 store the whole arg to memory is often more efficient than code
5581 to store pieces, and we know that space is available in the right
5582 place for the whole arg. */
5583 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5588 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5589 rtx off = GEN_INT (i++ * 4);
5590 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5592 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5594 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5597 /* Determine where to put an argument to a function.
5598 Value is zero to push the argument on the stack,
5599 or a hard register in which to store the argument.
5601 MODE is the argument's machine mode.
5602 TYPE is the data type of the argument (as a tree).
5603 This is null for libcalls where that information may
5605 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5606 the preceding args and about the function being called. It is
5607 not modified in this routine.
5608 NAMED is nonzero if this argument is a named parameter
5609 (otherwise it is an extra parameter matching an ellipsis).
5611 On RS/6000 the first eight words of non-FP are normally in registers
5612 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5613 Under V.4, the first 8 FP args are in registers.
5615 If this is floating-point and no prototype is specified, we use
5616 both an FP and integer register (or possibly FP reg and stack). Library
5617 functions (when CALL_LIBCALL is set) always have the proper types for args,
5618 so we can pass the FP value just in one register. emit_library_function
5619 doesn't support PARALLEL anyway.
5621 Note that for args passed by reference, function_arg will be called
5622 with MODE and TYPE set to that of the pointer to the arg, not the arg
5626 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5627 tree type, int named)
5629 enum rs6000_abi abi = DEFAULT_ABI;
5631 /* Return a marker to indicate whether CR1 needs to set or clear the
5632 bit that V.4 uses to say fp args were passed in registers.
5633 Assume that we don't need the marker for software floating point,
5634 or compiler generated library calls. */
5635 if (mode == VOIDmode)
5638 && (cum->call_cookie & CALL_LIBCALL) == 0
5640 || (cum->nargs_prototype < 0
5641 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5643 /* For the SPE, we need to crxor CR6 always. */
5645 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5646 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5647 return GEN_INT (cum->call_cookie
5648 | ((cum->fregno == FP_ARG_MIN_REG)
5649 ? CALL_V4_SET_FP_ARGS
5650 : CALL_V4_CLEAR_FP_ARGS));
5653 return GEN_INT (cum->call_cookie);
5656 if (rs6000_darwin64_abi && mode == BLKmode
5657 && TREE_CODE (type) == RECORD_TYPE)
5659 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5660 if (rslt != NULL_RTX)
5662 /* Else fall through to usual handling. */
5665 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5666 if (TARGET_64BIT && ! cum->prototype)
5668 /* Vector parameters get passed in vector register
5669 and also in GPRs or memory, in absence of prototype. */
5672 align_words = (cum->words + 1) & ~1;
5674 if (align_words >= GP_ARG_NUM_REG)
5680 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5682 return gen_rtx_PARALLEL (mode,
5684 gen_rtx_EXPR_LIST (VOIDmode,
5686 gen_rtx_EXPR_LIST (VOIDmode,
5687 gen_rtx_REG (mode, cum->vregno),
5691 return gen_rtx_REG (mode, cum->vregno);
5692 else if (TARGET_ALTIVEC_ABI
5693 && (ALTIVEC_VECTOR_MODE (mode)
5694 || (type && TREE_CODE (type) == VECTOR_TYPE
5695 && int_size_in_bytes (type) == 16)))
5697 if (named || abi == ABI_V4)
5701 /* Vector parameters to varargs functions under AIX or Darwin
5702 get passed in memory and possibly also in GPRs. */
5703 int align, align_words, n_words;
5704 enum machine_mode part_mode;
5706 /* Vector parameters must be 16-byte aligned. This places them at
5707 2 mod 4 in terms of words in 32-bit mode, since the parameter
5708 save area starts at offset 24 from the stack. In 64-bit mode,
5709 they just have to start on an even word, since the parameter
5710 save area is 16-byte aligned. */
5712 align = (2 - cum->words) & 3;
5714 align = cum->words & 1;
5715 align_words = cum->words + align;
5717 /* Out of registers? Memory, then. */
5718 if (align_words >= GP_ARG_NUM_REG)
5721 if (TARGET_32BIT && TARGET_POWERPC64)
5722 return rs6000_mixed_function_arg (mode, type, align_words);
5724 /* The vector value goes in GPRs. Only the part of the
5725 value in GPRs is reported here. */
5727 n_words = rs6000_arg_size (mode, type);
5728 if (align_words + n_words > GP_ARG_NUM_REG)
5729 /* Fortunately, there are only two possibilities, the value
5730 is either wholly in GPRs or half in GPRs and half not. */
5733 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5736 else if (TARGET_SPE_ABI && TARGET_SPE
5737 && (SPE_VECTOR_MODE (mode)
5738 || (TARGET_E500_DOUBLE && (mode == DFmode
5743 || mode == TCmode))))
5744 return rs6000_spe_function_arg (cum, mode, type);
5746 else if (abi == ABI_V4)
5748 if (TARGET_HARD_FLOAT && TARGET_FPRS
5749 && (mode == SFmode || mode == DFmode
5750 || (mode == TFmode && !TARGET_IEEEQUAD)
5751 || mode == DDmode || mode == TDmode))
5753 /* _Decimal128 must use an even/odd register pair. This assumes
5754 that the register number is odd when fregno is odd. */
5755 if (mode == TDmode && (cum->fregno % 2) == 1)
5758 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5759 <= FP_ARG_V4_MAX_REG)
5760 return gen_rtx_REG (mode, cum->fregno);
5766 int n_words = rs6000_arg_size (mode, type);
5767 int gregno = cum->sysv_gregno;
5769 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5770 (r7,r8) or (r9,r10). As does any other 2 word item such
5771 as complex int due to a historical mistake. */
5773 gregno += (1 - gregno) & 1;
5775 /* Multi-reg args are not split between registers and stack. */
5776 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5779 if (TARGET_32BIT && TARGET_POWERPC64)
5780 return rs6000_mixed_function_arg (mode, type,
5781 gregno - GP_ARG_MIN_REG);
5782 return gen_rtx_REG (mode, gregno);
5787 int align_words = rs6000_parm_start (mode, type, cum->words);
5789 /* _Decimal128 must be passed in an even/odd float register pair.
5790 This assumes that the register number is odd when fregno is odd. */
5791 if (mode == TDmode && (cum->fregno % 2) == 1)
5794 if (USE_FP_FOR_ARG_P (cum, mode, type))
5796 rtx rvec[GP_ARG_NUM_REG + 1];
5800 enum machine_mode fmode = mode;
5801 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5803 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5805 /* Currently, we only ever need one reg here because complex
5806 doubles are split. */
5807 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5808 && (fmode == TFmode || fmode == TDmode));
5810 /* Long double or _Decimal128 split over regs and memory. */
5811 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5814 /* Do we also need to pass this arg in the parameter save
5817 && (cum->nargs_prototype <= 0
5818 || (DEFAULT_ABI == ABI_AIX
5820 && align_words >= GP_ARG_NUM_REG)));
5822 if (!needs_psave && mode == fmode)
5823 return gen_rtx_REG (fmode, cum->fregno);
5828 /* Describe the part that goes in gprs or the stack.
5829 This piece must come first, before the fprs. */
5830 if (align_words < GP_ARG_NUM_REG)
5832 unsigned long n_words = rs6000_arg_size (mode, type);
5834 if (align_words + n_words > GP_ARG_NUM_REG
5835 || (TARGET_32BIT && TARGET_POWERPC64))
5837 /* If this is partially on the stack, then we only
5838 include the portion actually in registers here. */
5839 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5842 if (align_words + n_words > GP_ARG_NUM_REG)
5843 /* Not all of the arg fits in gprs. Say that it
5844 goes in memory too, using a magic NULL_RTX
5845 component. Also see comment in
5846 rs6000_mixed_function_arg for why the normal
5847 function_arg_partial_nregs scheme doesn't work
5849 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5853 r = gen_rtx_REG (rmode,
5854 GP_ARG_MIN_REG + align_words);
5855 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5856 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5858 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5862 /* The whole arg fits in gprs. */
5863 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5864 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5868 /* It's entirely in memory. */
5869 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5872 /* Describe where this piece goes in the fprs. */
5873 r = gen_rtx_REG (fmode, cum->fregno);
5874 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5876 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5878 else if (align_words < GP_ARG_NUM_REG)
5880 if (TARGET_32BIT && TARGET_POWERPC64)
5881 return rs6000_mixed_function_arg (mode, type, align_words);
5883 if (mode == BLKmode)
5886 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5893 /* For an arg passed partly in registers and partly in memory, this is
5894 the number of bytes passed in registers. For args passed entirely in
5895 registers or entirely in memory, zero. When an arg is described by a
5896 PARALLEL, perhaps using more than one register type, this function
5897 returns the number of bytes used by the first element of the PARALLEL. */
5900 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5901 tree type, bool named)
5906 if (DEFAULT_ABI == ABI_V4)
5909 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5910 && cum->nargs_prototype >= 0)
5913 /* In this complicated case we just disable the partial_nregs code. */
5914 if (rs6000_darwin64_abi && mode == BLKmode
5915 && TREE_CODE (type) == RECORD_TYPE
5916 && int_size_in_bytes (type) > 0)
5919 align_words = rs6000_parm_start (mode, type, cum->words);
5921 if (USE_FP_FOR_ARG_P (cum, mode, type))
5923 /* If we are passing this arg in the fixed parameter save area
5924 (gprs or memory) as well as fprs, then this function should
5925 return the number of partial bytes passed in the parameter
5926 save area rather than partial bytes passed in fprs. */
5928 && (cum->nargs_prototype <= 0
5929 || (DEFAULT_ABI == ABI_AIX
5931 && align_words >= GP_ARG_NUM_REG)))
5933 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5934 > FP_ARG_MAX_REG + 1)
5935 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5936 else if (cum->nargs_prototype >= 0)
5940 if (align_words < GP_ARG_NUM_REG
5941 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5942 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5944 if (ret != 0 && TARGET_DEBUG_ARG)
5945 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5950 /* A C expression that indicates when an argument must be passed by
5951 reference. If nonzero for an argument, a copy of that argument is
5952 made in memory and a pointer to the argument is passed instead of
5953 the argument itself. The pointer is passed in whatever way is
5954 appropriate for passing a pointer to that type.
5956 Under V.4, aggregates and long double are passed by reference.
5958 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5959 reference unless the AltiVec vector extension ABI is in force.
5961 As an extension to all ABIs, variable sized types are passed by
5965 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5966 enum machine_mode mode, tree type,
5967 bool named ATTRIBUTE_UNUSED)
5969 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5971 if (TARGET_DEBUG_ARG)
5972 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5979 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5981 if (TARGET_DEBUG_ARG)
5982 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5986 if (int_size_in_bytes (type) < 0)
5988 if (TARGET_DEBUG_ARG)
5989 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5993 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5994 modes only exist for GCC vector types if -maltivec. */
5995 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5997 if (TARGET_DEBUG_ARG)
5998 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6002 /* Pass synthetic vectors in memory. */
6003 if (TREE_CODE (type) == VECTOR_TYPE
6004 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6006 static bool warned_for_pass_big_vectors = false;
6007 if (TARGET_DEBUG_ARG)
6008 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6009 if (!warned_for_pass_big_vectors)
6011 warning (0, "GCC vector passed by reference: "
6012 "non-standard ABI extension with no compatibility guarantee");
6013 warned_for_pass_big_vectors = true;
6022 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6025 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6030 for (i = 0; i < nregs; i++)
6032 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6033 if (reload_completed)
6035 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6038 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6039 i * GET_MODE_SIZE (reg_mode));
6042 tem = replace_equiv_address (tem, XEXP (tem, 0));
6046 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6050 /* Perform any needed actions needed for a function that is receiving a
6051 variable number of arguments.
6055 MODE and TYPE are the mode and type of the current parameter.
6057 PRETEND_SIZE is a variable that should be set to the amount of stack
6058 that must be pushed by the prolog to pretend that our caller pushed
6061 Normally, this macro will push all remaining incoming registers on the
6062 stack and set PRETEND_SIZE to the length of the registers pushed. */
6065 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6066 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6069 CUMULATIVE_ARGS next_cum;
6070 int reg_size = TARGET_32BIT ? 4 : 8;
6071 rtx save_area = NULL_RTX, mem;
6072 int first_reg_offset, set;
6074 /* Skip the last named argument. */
6076 function_arg_advance (&next_cum, mode, type, 1, 0);
6078 if (DEFAULT_ABI == ABI_V4)
6080 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6084 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6085 HOST_WIDE_INT offset = 0;
6087 /* Try to optimize the size of the varargs save area.
6088 The ABI requires that ap.reg_save_area is doubleword
6089 aligned, but we don't need to allocate space for all
6090 the bytes, only those to which we actually will save
6092 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6093 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6094 if (TARGET_HARD_FLOAT && TARGET_FPRS
6095 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6096 && cfun->va_list_fpr_size)
6099 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6100 * UNITS_PER_FP_WORD;
6101 if (cfun->va_list_fpr_size
6102 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6103 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6105 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6106 * UNITS_PER_FP_WORD;
6110 offset = -((first_reg_offset * reg_size) & ~7);
6111 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6113 gpr_reg_num = cfun->va_list_gpr_size;
6114 if (reg_size == 4 && (first_reg_offset & 1))
6117 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6120 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6122 - (int) (GP_ARG_NUM_REG * reg_size);
6124 if (gpr_size + fpr_size)
6127 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6128 gcc_assert (GET_CODE (reg_save_area) == MEM);
6129 reg_save_area = XEXP (reg_save_area, 0);
6130 if (GET_CODE (reg_save_area) == PLUS)
6132 gcc_assert (XEXP (reg_save_area, 0)
6133 == virtual_stack_vars_rtx);
6134 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6135 offset += INTVAL (XEXP (reg_save_area, 1));
6138 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6141 cfun->machine->varargs_save_offset = offset;
6142 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6147 first_reg_offset = next_cum.words;
6148 save_area = virtual_incoming_args_rtx;
6150 if (targetm.calls.must_pass_in_stack (mode, type))
6151 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6154 set = get_varargs_alias_set ();
6155 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6156 && cfun->va_list_gpr_size)
6158 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6160 if (va_list_gpr_counter_field)
6162 /* V4 va_list_gpr_size counts number of registers needed. */
6163 if (nregs > cfun->va_list_gpr_size)
6164 nregs = cfun->va_list_gpr_size;
6168 /* char * va_list instead counts number of bytes needed. */
6169 if (nregs > cfun->va_list_gpr_size / reg_size)
6170 nregs = cfun->va_list_gpr_size / reg_size;
6173 mem = gen_rtx_MEM (BLKmode,
6174 plus_constant (save_area,
6175 first_reg_offset * reg_size));
6176 MEM_NOTRAP_P (mem) = 1;
6177 set_mem_alias_set (mem, set);
6178 set_mem_align (mem, BITS_PER_WORD);
6180 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6184 /* Save FP registers if needed. */
6185 if (DEFAULT_ABI == ABI_V4
6186 && TARGET_HARD_FLOAT && TARGET_FPRS
6188 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6189 && cfun->va_list_fpr_size)
6191 int fregno = next_cum.fregno, nregs;
6192 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6193 rtx lab = gen_label_rtx ();
6194 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6195 * UNITS_PER_FP_WORD);
6198 (gen_rtx_SET (VOIDmode,
6200 gen_rtx_IF_THEN_ELSE (VOIDmode,
6201 gen_rtx_NE (VOIDmode, cr1,
6203 gen_rtx_LABEL_REF (VOIDmode, lab),
6207 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6208 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6210 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6211 MEM_NOTRAP_P (mem) = 1;
6212 set_mem_alias_set (mem, set);
6213 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6214 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6221 /* Create the va_list data type. */
6224 rs6000_build_builtin_va_list (void)
6226 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6228 /* For AIX, prefer 'char *' because that's what the system
6229 header files like. */
6230 if (DEFAULT_ABI != ABI_V4)
6231 return build_pointer_type (char_type_node);
6233 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6234 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6236 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6237 unsigned_char_type_node);
6238 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6239 unsigned_char_type_node);
6240 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6242 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6243 short_unsigned_type_node);
6244 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6246 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6249 va_list_gpr_counter_field = f_gpr;
6250 va_list_fpr_counter_field = f_fpr;
6252 DECL_FIELD_CONTEXT (f_gpr) = record;
6253 DECL_FIELD_CONTEXT (f_fpr) = record;
6254 DECL_FIELD_CONTEXT (f_res) = record;
6255 DECL_FIELD_CONTEXT (f_ovf) = record;
6256 DECL_FIELD_CONTEXT (f_sav) = record;
6258 TREE_CHAIN (record) = type_decl;
6259 TYPE_NAME (record) = type_decl;
6260 TYPE_FIELDS (record) = f_gpr;
6261 TREE_CHAIN (f_gpr) = f_fpr;
6262 TREE_CHAIN (f_fpr) = f_res;
6263 TREE_CHAIN (f_res) = f_ovf;
6264 TREE_CHAIN (f_ovf) = f_sav;
6266 layout_type (record);
6268 /* The correct type is an array type of one element. */
6269 return build_array_type (record, build_index_type (size_zero_node));
6272 /* Implement va_start. */
6275 rs6000_va_start (tree valist, rtx nextarg)
6277 HOST_WIDE_INT words, n_gpr, n_fpr;
6278 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6279 tree gpr, fpr, ovf, sav, t;
6281 /* Only SVR4 needs something special. */
6282 if (DEFAULT_ABI != ABI_V4)
6284 std_expand_builtin_va_start (valist, nextarg);
6288 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6289 f_fpr = TREE_CHAIN (f_gpr);
6290 f_res = TREE_CHAIN (f_fpr);
6291 f_ovf = TREE_CHAIN (f_res);
6292 f_sav = TREE_CHAIN (f_ovf);
6294 valist = build_va_arg_indirect_ref (valist);
6295 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6296 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6297 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6298 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6300 /* Count number of gp and fp argument registers used. */
6301 words = current_function_args_info.words;
6302 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6304 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6307 if (TARGET_DEBUG_ARG)
6308 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6309 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6310 words, n_gpr, n_fpr);
6312 if (cfun->va_list_gpr_size)
6314 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6315 build_int_cst (NULL_TREE, n_gpr));
6316 TREE_SIDE_EFFECTS (t) = 1;
6317 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6320 if (cfun->va_list_fpr_size)
6322 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6323 build_int_cst (NULL_TREE, n_fpr));
6324 TREE_SIDE_EFFECTS (t) = 1;
6325 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6328 /* Find the overflow area. */
6329 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6331 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6332 size_int (words * UNITS_PER_WORD));
6333 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6334 TREE_SIDE_EFFECTS (t) = 1;
6335 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6337 /* If there were no va_arg invocations, don't set up the register
6339 if (!cfun->va_list_gpr_size
6340 && !cfun->va_list_fpr_size
6341 && n_gpr < GP_ARG_NUM_REG
6342 && n_fpr < FP_ARG_V4_MAX_REG)
6345 /* Find the register save area. */
6346 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6347 if (cfun->machine->varargs_save_offset)
6348 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6349 size_int (cfun->machine->varargs_save_offset));
6350 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6351 TREE_SIDE_EFFECTS (t) = 1;
6352 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6355 /* Implement va_arg. */
6358 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6360 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6361 tree gpr, fpr, ovf, sav, reg, t, u;
6362 int size, rsize, n_reg, sav_ofs, sav_scale;
6363 tree lab_false, lab_over, addr;
6365 tree ptrtype = build_pointer_type (type);
6368 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6370 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6371 return build_va_arg_indirect_ref (t);
6374 if (DEFAULT_ABI != ABI_V4)
6376 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6378 tree elem_type = TREE_TYPE (type);
6379 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6380 int elem_size = GET_MODE_SIZE (elem_mode);
6382 if (elem_size < UNITS_PER_WORD)
6384 tree real_part, imag_part;
6385 tree post = NULL_TREE;
6387 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6389 /* Copy the value into a temporary, lest the formal temporary
6390 be reused out from under us. */
6391 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6392 append_to_statement_list (post, pre_p);
6394 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6397 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6401 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6404 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6405 f_fpr = TREE_CHAIN (f_gpr);
6406 f_res = TREE_CHAIN (f_fpr);
6407 f_ovf = TREE_CHAIN (f_res);
6408 f_sav = TREE_CHAIN (f_ovf);
6410 valist = build_va_arg_indirect_ref (valist);
6411 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6412 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6413 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6414 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6416 size = int_size_in_bytes (type);
6417 rsize = (size + 3) / 4;
6420 if (TARGET_HARD_FLOAT && TARGET_FPRS
6421 && (TYPE_MODE (type) == SFmode
6422 || TYPE_MODE (type) == DFmode
6423 || TYPE_MODE (type) == TFmode
6424 || TYPE_MODE (type) == DDmode
6425 || TYPE_MODE (type) == TDmode))
6427 /* FP args go in FP registers, if present. */
6429 n_reg = (size + 7) / 8;
6432 if (TYPE_MODE (type) != SFmode)
6437 /* Otherwise into GP registers. */
6446 /* Pull the value out of the saved registers.... */
6449 addr = create_tmp_var (ptr_type_node, "addr");
6450 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6452 /* AltiVec vectors never go in registers when -mabi=altivec. */
6453 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6457 lab_false = create_artificial_label ();
6458 lab_over = create_artificial_label ();
6460 /* Long long and SPE vectors are aligned in the registers.
6461 As are any other 2 gpr item such as complex int due to a
6462 historical mistake. */
6464 if (n_reg == 2 && reg == gpr)
6467 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6468 size_int (n_reg - 1));
6469 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6471 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6472 reg number is 0 for f1, so we want to make it odd. */
6473 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6476 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6477 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6480 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6481 t = build2 (GE_EXPR, boolean_type_node, u, t);
6482 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6483 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6484 gimplify_and_add (t, pre_p);
6488 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6490 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6491 u = fold_convert (sizetype, u);
6492 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6493 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6495 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6496 gimplify_and_add (t, pre_p);
6498 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6499 gimplify_and_add (t, pre_p);
6501 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6502 append_to_statement_list (t, pre_p);
6504 if ((n_reg == 2 && !regalign) || n_reg > 2)
6506 /* Ensure that we don't find any more args in regs.
6507 Alignment has taken care of for special cases. */
6508 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6509 gimplify_and_add (t, pre_p);
6513 /* ... otherwise out of the overflow area. */
6515 /* Care for on-stack alignment if needed. */
6519 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6520 t = fold_convert (sizetype, t);
6521 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6523 t = fold_convert (TREE_TYPE (ovf), t);
6525 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6527 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6528 gimplify_and_add (u, pre_p);
6530 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6531 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6532 gimplify_and_add (t, pre_p);
6536 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6537 append_to_statement_list (t, pre_p);
6540 if (STRICT_ALIGNMENT
6541 && (TYPE_ALIGN (type)
6542 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6544 /* The value (of type complex double, for example) may not be
6545 aligned in memory in the saved registers, so copy via a
6546 temporary. (This is the same code as used for SPARC.) */
6547 tree tmp = create_tmp_var (type, "va_arg_tmp");
6548 tree dest_addr = build_fold_addr_expr (tmp);
6550 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6551 3, dest_addr, addr, size_int (rsize * 4));
6553 gimplify_and_add (copy, pre_p);
6557 addr = fold_convert (ptrtype, addr);
6558 return build_va_arg_indirect_ref (addr);
6564 def_builtin (int mask, const char *name, tree type, int code)
6566 if (mask & target_flags)
6568 if (rs6000_builtin_decls[code])
6571 rs6000_builtin_decls[code] =
6572 add_builtin_function (name, type, code, BUILT_IN_MD,
6577 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6579 static const struct builtin_description bdesc_3arg[] =
6581 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6582 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6583 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6584 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6585 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6586 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6587 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6588 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6589 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6590 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6591 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6592 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6593 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6594 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6595 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6596 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6597 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6598 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6599 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6600 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6601 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6602 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6603 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6605 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6606 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6607 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6608 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6609 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6610 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6611 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6612 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6613 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6614 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6615 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6616 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6617 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6618 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6619 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6622 /* DST operations: void foo (void *, const int, const char). */
6624 static const struct builtin_description bdesc_dst[] =
6626 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6627 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6628 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6629 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6631 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6632 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6633 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6634 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6637 /* Simple binary operations: VECc = foo (VECa, VECb). */
6639 static struct builtin_description bdesc_2arg[] =
6641 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6642 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6643 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6644 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6645 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6646 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6647 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6648 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6649 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6650 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6651 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6652 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6653 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6654 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6655 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6656 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6657 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6658 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6659 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6660 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6661 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6662 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6663 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6664 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6665 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6666 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6667 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6668 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6669 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6670 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6671 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6672 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6673 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6674 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6675 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6676 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6677 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6678 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6679 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6680 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6681 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6682 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6683 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6684 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6685 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6686 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6687 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6688 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6689 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6690 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6691 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6692 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6693 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6694 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6695 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6696 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6697 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6698 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6699 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6700 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6701 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6702 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6703 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6704 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6705 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6706 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6707 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6708 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6709 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6710 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6711 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6712 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6713 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6714 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6715 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6716 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6717 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6718 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6719 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6720 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6721 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6722 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6723 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6724 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6725 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6726 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6727 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6728 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6729 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6730 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6731 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6732 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6733 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6734 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6735 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6736 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6737 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6738 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6739 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6740 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6741 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6742 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6743 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6744 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6745 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6746 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6747 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6748 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6749 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6750 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6751 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6753 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6754 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6755 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6756 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6757 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6758 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6759 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6760 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6761 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6762 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6763 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6764 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6765 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6766 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6767 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6768 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6769 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6770 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6771 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6772 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6773 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6774 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6775 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6776 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6777 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6778 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6779 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6780 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6781 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6782 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6783 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6784 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6785 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6786 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6787 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6788 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6789 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6790 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6791 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6792 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6793 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6794 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6856 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6857 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6858 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6859 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6860 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6861 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6862 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6863 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6864 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6865 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6866 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6881 /* Place holder, leave as first spe builtin. */
6882 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6883 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6884 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6885 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6886 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6887 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6888 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6889 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6890 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6891 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6892 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6893 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6894 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6895 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6896 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6897 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6898 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6899 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6900 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6901 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6902 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6903 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6904 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6905 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6906 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6907 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6908 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6909 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6910 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6911 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6912 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6913 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6914 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6915 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6916 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6917 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6918 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6919 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6920 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6921 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6922 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6923 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6924 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6925 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6926 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6927 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6928 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6929 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6930 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6931 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6932 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6933 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6934 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6935 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6936 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6937 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6938 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6939 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6940 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6941 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6942 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6943 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6944 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6945 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6946 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6947 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6948 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6949 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6950 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6951 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6952 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6953 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6954 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6955 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6956 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6957 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6958 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6959 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6960 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6961 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6962 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6963 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6964 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6965 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6966 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6967 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6968 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6969 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6970 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6971 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6972 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6973 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6974 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6975 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6976 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6977 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6978 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6979 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6980 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6981 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6982 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6983 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6984 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6985 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6986 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6987 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6988 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6989 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6990 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6992 /* SPE binary operations expecting a 5-bit unsigned literal. */
6993 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6995 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6996 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6997 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6998 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6999 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7000 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7001 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7002 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7003 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7004 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7005 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7006 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7007 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7008 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7009 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7010 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7011 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7012 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7013 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7014 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7015 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7016 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7017 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7018 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7019 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7020 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7022 /* Place-holder. Leave as last binary SPE builtin. */
7023 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7026 /* AltiVec predicates. */
7028 struct builtin_description_predicates
7030 const unsigned int mask;
7031 const enum insn_code icode;
7033 const char *const name;
7034 const enum rs6000_builtins code;
7037 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7039 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7040 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7041 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7042 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7043 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7044 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7045 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7046 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7047 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7048 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7049 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7050 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7051 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7053 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7054 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7055 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7058 /* SPE predicates. */
7059 static struct builtin_description bdesc_spe_predicates[] =
7061 /* Place-holder. Leave as first. */
7062 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7063 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7064 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7065 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7066 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7067 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7068 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7069 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7070 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7071 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7072 /* Place-holder. Leave as last. */
7073 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7076 /* SPE evsel predicates. */
7077 static struct builtin_description bdesc_spe_evsel[] =
7079 /* Place-holder. Leave as first. */
7080 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7081 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7082 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7083 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7084 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7085 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7086 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7087 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7088 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7089 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7090 /* Place-holder. Leave as last. */
7091 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7094 /* ABS* operations. */
7096 static const struct builtin_description bdesc_abs[] =
7098 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7099 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7100 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7101 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7102 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7103 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7104 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7107 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7110 static struct builtin_description bdesc_1arg[] =
7112 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7113 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7114 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7115 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7116 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7117 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7118 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7119 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7120 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7121 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7122 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7123 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7124 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7125 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7126 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7127 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7128 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7139 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7140 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7141 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7142 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7143 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7146 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7150 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7151 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7152 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7153 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7154 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7155 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7156 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7157 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7158 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7159 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7160 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7161 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7162 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7163 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7164 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7165 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7166 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7167 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7168 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7169 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7170 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7171 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7172 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7173 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7174 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7175 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7176 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7177 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7178 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7179 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7181 /* Place-holder. Leave as last unary SPE builtin. */
7182 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7186 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7189 tree arg0 = CALL_EXPR_ARG (exp, 0);
7190 rtx op0 = expand_normal (arg0);
7191 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7192 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7194 if (icode == CODE_FOR_nothing)
7195 /* Builtin not supported on this processor. */
7198 /* If we got invalid arguments bail out before generating bad rtl. */
7199 if (arg0 == error_mark_node)
7202 if (icode == CODE_FOR_altivec_vspltisb
7203 || icode == CODE_FOR_altivec_vspltish
7204 || icode == CODE_FOR_altivec_vspltisw
7205 || icode == CODE_FOR_spe_evsplatfi
7206 || icode == CODE_FOR_spe_evsplati)
7208 /* Only allow 5-bit *signed* literals. */
7209 if (GET_CODE (op0) != CONST_INT
7210 || INTVAL (op0) > 15
7211 || INTVAL (op0) < -16)
7213 error ("argument 1 must be a 5-bit signed literal");
7219 || GET_MODE (target) != tmode
7220 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7221 target = gen_reg_rtx (tmode);
7223 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7224 op0 = copy_to_mode_reg (mode0, op0);
7226 pat = GEN_FCN (icode) (target, op0);
7235 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7237 rtx pat, scratch1, scratch2;
7238 tree arg0 = CALL_EXPR_ARG (exp, 0);
7239 rtx op0 = expand_normal (arg0);
7240 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7241 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7243 /* If we have invalid arguments, bail out before generating bad rtl. */
7244 if (arg0 == error_mark_node)
7248 || GET_MODE (target) != tmode
7249 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7250 target = gen_reg_rtx (tmode);
7252 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7253 op0 = copy_to_mode_reg (mode0, op0);
7255 scratch1 = gen_reg_rtx (mode0);
7256 scratch2 = gen_reg_rtx (mode0);
7258 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7267 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7270 tree arg0 = CALL_EXPR_ARG (exp, 0);
7271 tree arg1 = CALL_EXPR_ARG (exp, 1);
7272 rtx op0 = expand_normal (arg0);
7273 rtx op1 = expand_normal (arg1);
7274 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7275 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7276 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7278 if (icode == CODE_FOR_nothing)
7279 /* Builtin not supported on this processor. */
7282 /* If we got invalid arguments bail out before generating bad rtl. */
7283 if (arg0 == error_mark_node || arg1 == error_mark_node)
7286 if (icode == CODE_FOR_altivec_vcfux
7287 || icode == CODE_FOR_altivec_vcfsx
7288 || icode == CODE_FOR_altivec_vctsxs
7289 || icode == CODE_FOR_altivec_vctuxs
7290 || icode == CODE_FOR_altivec_vspltb
7291 || icode == CODE_FOR_altivec_vsplth
7292 || icode == CODE_FOR_altivec_vspltw
7293 || icode == CODE_FOR_spe_evaddiw
7294 || icode == CODE_FOR_spe_evldd
7295 || icode == CODE_FOR_spe_evldh
7296 || icode == CODE_FOR_spe_evldw
7297 || icode == CODE_FOR_spe_evlhhesplat
7298 || icode == CODE_FOR_spe_evlhhossplat
7299 || icode == CODE_FOR_spe_evlhhousplat
7300 || icode == CODE_FOR_spe_evlwhe
7301 || icode == CODE_FOR_spe_evlwhos
7302 || icode == CODE_FOR_spe_evlwhou
7303 || icode == CODE_FOR_spe_evlwhsplat
7304 || icode == CODE_FOR_spe_evlwwsplat
7305 || icode == CODE_FOR_spe_evrlwi
7306 || icode == CODE_FOR_spe_evslwi
7307 || icode == CODE_FOR_spe_evsrwis
7308 || icode == CODE_FOR_spe_evsubifw
7309 || icode == CODE_FOR_spe_evsrwiu)
7311 /* Only allow 5-bit unsigned literals. */
7313 if (TREE_CODE (arg1) != INTEGER_CST
7314 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7316 error ("argument 2 must be a 5-bit unsigned literal");
7322 || GET_MODE (target) != tmode
7323 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7324 target = gen_reg_rtx (tmode);
7326 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7327 op0 = copy_to_mode_reg (mode0, op0);
7328 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7329 op1 = copy_to_mode_reg (mode1, op1);
7331 pat = GEN_FCN (icode) (target, op0, op1);
7340 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7341 tree exp, rtx target)
7344 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7345 tree arg0 = CALL_EXPR_ARG (exp, 1);
7346 tree arg1 = CALL_EXPR_ARG (exp, 2);
7347 rtx op0 = expand_normal (arg0);
7348 rtx op1 = expand_normal (arg1);
7349 enum machine_mode tmode = SImode;
7350 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7351 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7354 if (TREE_CODE (cr6_form) != INTEGER_CST)
7356 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7360 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7362 gcc_assert (mode0 == mode1);
7364 /* If we have invalid arguments, bail out before generating bad rtl. */
7365 if (arg0 == error_mark_node || arg1 == error_mark_node)
7369 || GET_MODE (target) != tmode
7370 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7371 target = gen_reg_rtx (tmode);
7373 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7374 op0 = copy_to_mode_reg (mode0, op0);
7375 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7376 op1 = copy_to_mode_reg (mode1, op1);
7378 scratch = gen_reg_rtx (mode0);
7380 pat = GEN_FCN (icode) (scratch, op0, op1,
7381 gen_rtx_SYMBOL_REF (Pmode, opcode));
7386 /* The vec_any* and vec_all* predicates use the same opcodes for two
7387 different operations, but the bits in CR6 will be different
7388 depending on what information we want. So we have to play tricks
7389 with CR6 to get the right bits out.
7391 If you think this is disgusting, look at the specs for the
7392 AltiVec predicates. */
7394 switch (cr6_form_int)
7397 emit_insn (gen_cr6_test_for_zero (target));
7400 emit_insn (gen_cr6_test_for_zero_reverse (target));
7403 emit_insn (gen_cr6_test_for_lt (target));
7406 emit_insn (gen_cr6_test_for_lt_reverse (target));
7409 error ("argument 1 of __builtin_altivec_predicate is out of range");
7417 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7420 tree arg0 = CALL_EXPR_ARG (exp, 0);
7421 tree arg1 = CALL_EXPR_ARG (exp, 1);
7422 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7423 enum machine_mode mode0 = Pmode;
7424 enum machine_mode mode1 = Pmode;
7425 rtx op0 = expand_normal (arg0);
7426 rtx op1 = expand_normal (arg1);
7428 if (icode == CODE_FOR_nothing)
7429 /* Builtin not supported on this processor. */
7432 /* If we got invalid arguments bail out before generating bad rtl. */
7433 if (arg0 == error_mark_node || arg1 == error_mark_node)
7437 || GET_MODE (target) != tmode
7438 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7439 target = gen_reg_rtx (tmode);
7441 op1 = copy_to_mode_reg (mode1, op1);
7443 if (op0 == const0_rtx)
7445 addr = gen_rtx_MEM (tmode, op1);
7449 op0 = copy_to_mode_reg (mode0, op0);
7450 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7453 pat = GEN_FCN (icode) (target, addr);
7463 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7465 tree arg0 = CALL_EXPR_ARG (exp, 0);
7466 tree arg1 = CALL_EXPR_ARG (exp, 1);
7467 tree arg2 = CALL_EXPR_ARG (exp, 2);
7468 rtx op0 = expand_normal (arg0);
7469 rtx op1 = expand_normal (arg1);
7470 rtx op2 = expand_normal (arg2);
7472 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7473 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7474 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7476 /* Invalid arguments. Bail before doing anything stoopid! */
7477 if (arg0 == error_mark_node
7478 || arg1 == error_mark_node
7479 || arg2 == error_mark_node)
7482 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7483 op0 = copy_to_mode_reg (mode2, op0);
7484 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7485 op1 = copy_to_mode_reg (mode0, op1);
7486 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7487 op2 = copy_to_mode_reg (mode1, op2);
7489 pat = GEN_FCN (icode) (op1, op2, op0);
7496 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7498 tree arg0 = CALL_EXPR_ARG (exp, 0);
7499 tree arg1 = CALL_EXPR_ARG (exp, 1);
7500 tree arg2 = CALL_EXPR_ARG (exp, 2);
7501 rtx op0 = expand_normal (arg0);
7502 rtx op1 = expand_normal (arg1);
7503 rtx op2 = expand_normal (arg2);
7505 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7506 enum machine_mode mode1 = Pmode;
7507 enum machine_mode mode2 = Pmode;
7509 /* Invalid arguments. Bail before doing anything stoopid! */
7510 if (arg0 == error_mark_node
7511 || arg1 == error_mark_node
7512 || arg2 == error_mark_node)
7515 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7516 op0 = copy_to_mode_reg (tmode, op0);
7518 op2 = copy_to_mode_reg (mode2, op2);
7520 if (op1 == const0_rtx)
7522 addr = gen_rtx_MEM (tmode, op2);
7526 op1 = copy_to_mode_reg (mode1, op1);
7527 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7530 pat = GEN_FCN (icode) (addr, op0);
7537 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7540 tree arg0 = CALL_EXPR_ARG (exp, 0);
7541 tree arg1 = CALL_EXPR_ARG (exp, 1);
7542 tree arg2 = CALL_EXPR_ARG (exp, 2);
7543 rtx op0 = expand_normal (arg0);
7544 rtx op1 = expand_normal (arg1);
7545 rtx op2 = expand_normal (arg2);
7546 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7547 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7548 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7549 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7551 if (icode == CODE_FOR_nothing)
7552 /* Builtin not supported on this processor. */
7555 /* If we got invalid arguments bail out before generating bad rtl. */
7556 if (arg0 == error_mark_node
7557 || arg1 == error_mark_node
7558 || arg2 == error_mark_node)
7561 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7562 || icode == CODE_FOR_altivec_vsldoi_v4si
7563 || icode == CODE_FOR_altivec_vsldoi_v8hi
7564 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7566 /* Only allow 4-bit unsigned literals. */
7568 if (TREE_CODE (arg2) != INTEGER_CST
7569 || TREE_INT_CST_LOW (arg2) & ~0xf)
7571 error ("argument 3 must be a 4-bit unsigned literal");
7577 || GET_MODE (target) != tmode
7578 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7579 target = gen_reg_rtx (tmode);
7581 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7582 op0 = copy_to_mode_reg (mode0, op0);
7583 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7584 op1 = copy_to_mode_reg (mode1, op1);
7585 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7586 op2 = copy_to_mode_reg (mode2, op2);
7588 pat = GEN_FCN (icode) (target, op0, op1, op2);
7596 /* Expand the lvx builtins. */
7598 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7600 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7601 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7603 enum machine_mode tmode, mode0;
7605 enum insn_code icode;
7609 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7610 icode = CODE_FOR_altivec_lvx_v16qi;
7612 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7613 icode = CODE_FOR_altivec_lvx_v8hi;
7615 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7616 icode = CODE_FOR_altivec_lvx_v4si;
7618 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7619 icode = CODE_FOR_altivec_lvx_v4sf;
7628 arg0 = CALL_EXPR_ARG (exp, 0);
7629 op0 = expand_normal (arg0);
7630 tmode = insn_data[icode].operand[0].mode;
7631 mode0 = insn_data[icode].operand[1].mode;
7634 || GET_MODE (target) != tmode
7635 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7636 target = gen_reg_rtx (tmode);
7638 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7639 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7641 pat = GEN_FCN (icode) (target, op0);
7648 /* Expand the stvx builtins. */
7650 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7653 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7654 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7656 enum machine_mode mode0, mode1;
7658 enum insn_code icode;
7662 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7663 icode = CODE_FOR_altivec_stvx_v16qi;
7665 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7666 icode = CODE_FOR_altivec_stvx_v8hi;
7668 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7669 icode = CODE_FOR_altivec_stvx_v4si;
7671 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7672 icode = CODE_FOR_altivec_stvx_v4sf;
7679 arg0 = CALL_EXPR_ARG (exp, 0);
7680 arg1 = CALL_EXPR_ARG (exp, 1);
7681 op0 = expand_normal (arg0);
7682 op1 = expand_normal (arg1);
7683 mode0 = insn_data[icode].operand[0].mode;
7684 mode1 = insn_data[icode].operand[1].mode;
7686 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7687 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7688 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7689 op1 = copy_to_mode_reg (mode1, op1);
7691 pat = GEN_FCN (icode) (op0, op1);
7699 /* Expand the dst builtins. */
7701 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7704 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7705 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7706 tree arg0, arg1, arg2;
7707 enum machine_mode mode0, mode1, mode2;
7708 rtx pat, op0, op1, op2;
7709 struct builtin_description *d;
7714 /* Handle DST variants. */
7715 d = (struct builtin_description *) bdesc_dst;
7716 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7717 if (d->code == fcode)
7719 arg0 = CALL_EXPR_ARG (exp, 0);
7720 arg1 = CALL_EXPR_ARG (exp, 1);
7721 arg2 = CALL_EXPR_ARG (exp, 2);
7722 op0 = expand_normal (arg0);
7723 op1 = expand_normal (arg1);
7724 op2 = expand_normal (arg2);
7725 mode0 = insn_data[d->icode].operand[0].mode;
7726 mode1 = insn_data[d->icode].operand[1].mode;
7727 mode2 = insn_data[d->icode].operand[2].mode;
7729 /* Invalid arguments, bail out before generating bad rtl. */
7730 if (arg0 == error_mark_node
7731 || arg1 == error_mark_node
7732 || arg2 == error_mark_node)
7737 if (TREE_CODE (arg2) != INTEGER_CST
7738 || TREE_INT_CST_LOW (arg2) & ~0x3)
7740 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7744 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7745 op0 = copy_to_mode_reg (Pmode, op0);
7746 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7747 op1 = copy_to_mode_reg (mode1, op1);
7749 pat = GEN_FCN (d->icode) (op0, op1, op2);
7759 /* Expand vec_init builtin. */
7761 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7763 enum machine_mode tmode = TYPE_MODE (type);
7764 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7765 int i, n_elt = GET_MODE_NUNITS (tmode);
7766 rtvec v = rtvec_alloc (n_elt);
7768 gcc_assert (VECTOR_MODE_P (tmode));
7769 gcc_assert (n_elt == call_expr_nargs (exp));
7771 for (i = 0; i < n_elt; ++i)
7773 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7774 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7777 if (!target || !register_operand (target, tmode))
7778 target = gen_reg_rtx (tmode);
7780 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7784 /* Return the integer constant in ARG. Constrain it to be in the range
7785 of the subparts of VEC_TYPE; issue an error if not. */
7788 get_element_number (tree vec_type, tree arg)
7790 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7792 if (!host_integerp (arg, 1)
7793 || (elt = tree_low_cst (arg, 1), elt > max))
7795 error ("selector must be an integer constant in the range 0..%wi", max);
7802 /* Expand vec_set builtin. */
7804 altivec_expand_vec_set_builtin (tree exp)
7806 enum machine_mode tmode, mode1;
7807 tree arg0, arg1, arg2;
7811 arg0 = CALL_EXPR_ARG (exp, 0);
7812 arg1 = CALL_EXPR_ARG (exp, 1);
7813 arg2 = CALL_EXPR_ARG (exp, 2);
7815 tmode = TYPE_MODE (TREE_TYPE (arg0));
7816 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7817 gcc_assert (VECTOR_MODE_P (tmode));
7819 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7820 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7821 elt = get_element_number (TREE_TYPE (arg0), arg2);
7823 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7824 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7826 op0 = force_reg (tmode, op0);
7827 op1 = force_reg (mode1, op1);
7829 rs6000_expand_vector_set (op0, op1, elt);
7834 /* Expand vec_ext builtin. */
7836 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7838 enum machine_mode tmode, mode0;
7843 arg0 = CALL_EXPR_ARG (exp, 0);
7844 arg1 = CALL_EXPR_ARG (exp, 1);
7846 op0 = expand_normal (arg0);
7847 elt = get_element_number (TREE_TYPE (arg0), arg1);
7849 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7850 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7851 gcc_assert (VECTOR_MODE_P (mode0));
7853 op0 = force_reg (mode0, op0);
7855 if (optimize || !target || !register_operand (target, tmode))
7856 target = gen_reg_rtx (tmode);
7858 rs6000_expand_vector_extract (target, op0, elt);
7863 /* Expand the builtin in EXP and store the result in TARGET. Store
7864 true in *EXPANDEDP if we found a builtin to expand. */
7866 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7868 struct builtin_description *d;
7869 struct builtin_description_predicates *dp;
7871 enum insn_code icode;
7872 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7875 enum machine_mode tmode, mode0;
7876 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7878 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7879 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7882 error ("unresolved overload for Altivec builtin %qF", fndecl);
7886 target = altivec_expand_ld_builtin (exp, target, expandedp);
7890 target = altivec_expand_st_builtin (exp, target, expandedp);
7894 target = altivec_expand_dst_builtin (exp, target, expandedp);
7902 case ALTIVEC_BUILTIN_STVX:
7903 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7904 case ALTIVEC_BUILTIN_STVEBX:
7905 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7906 case ALTIVEC_BUILTIN_STVEHX:
7907 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7908 case ALTIVEC_BUILTIN_STVEWX:
7909 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7910 case ALTIVEC_BUILTIN_STVXL:
7911 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7913 case ALTIVEC_BUILTIN_MFVSCR:
7914 icode = CODE_FOR_altivec_mfvscr;
7915 tmode = insn_data[icode].operand[0].mode;
7918 || GET_MODE (target) != tmode
7919 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7920 target = gen_reg_rtx (tmode);
7922 pat = GEN_FCN (icode) (target);
7928 case ALTIVEC_BUILTIN_MTVSCR:
7929 icode = CODE_FOR_altivec_mtvscr;
7930 arg0 = CALL_EXPR_ARG (exp, 0);
7931 op0 = expand_normal (arg0);
7932 mode0 = insn_data[icode].operand[0].mode;
7934 /* If we got invalid arguments bail out before generating bad rtl. */
7935 if (arg0 == error_mark_node)
7938 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7939 op0 = copy_to_mode_reg (mode0, op0);
7941 pat = GEN_FCN (icode) (op0);
7946 case ALTIVEC_BUILTIN_DSSALL:
7947 emit_insn (gen_altivec_dssall ());
7950 case ALTIVEC_BUILTIN_DSS:
7951 icode = CODE_FOR_altivec_dss;
7952 arg0 = CALL_EXPR_ARG (exp, 0);
7954 op0 = expand_normal (arg0);
7955 mode0 = insn_data[icode].operand[0].mode;
7957 /* If we got invalid arguments bail out before generating bad rtl. */
7958 if (arg0 == error_mark_node)
7961 if (TREE_CODE (arg0) != INTEGER_CST
7962 || TREE_INT_CST_LOW (arg0) & ~0x3)
7964 error ("argument to dss must be a 2-bit unsigned literal");
7968 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7969 op0 = copy_to_mode_reg (mode0, op0);
7971 emit_insn (gen_altivec_dss (op0));
7974 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7975 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7976 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7977 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7978 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
7980 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7981 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7982 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7983 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7984 return altivec_expand_vec_set_builtin (exp);
7986 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7987 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7988 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7989 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7990 return altivec_expand_vec_ext_builtin (exp, target);
7997 /* Expand abs* operations. */
7998 d = (struct builtin_description *) bdesc_abs;
7999 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8000 if (d->code == fcode)
8001 return altivec_expand_abs_builtin (d->icode, exp, target);
8003 /* Expand the AltiVec predicates. */
8004 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8005 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8006 if (dp->code == fcode)
8007 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8010 /* LV* are funky. We initialized them differently. */
8013 case ALTIVEC_BUILTIN_LVSL:
8014 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8016 case ALTIVEC_BUILTIN_LVSR:
8017 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8019 case ALTIVEC_BUILTIN_LVEBX:
8020 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8022 case ALTIVEC_BUILTIN_LVEHX:
8023 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8025 case ALTIVEC_BUILTIN_LVEWX:
8026 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8028 case ALTIVEC_BUILTIN_LVXL:
8029 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8031 case ALTIVEC_BUILTIN_LVX:
8032 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8043 /* Binops that need to be initialized manually, but can be expanded
8044 automagically by rs6000_expand_binop_builtin. */
8045 static struct builtin_description bdesc_2arg_spe[] =
8047 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8048 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8049 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8050 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8051 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8052 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8053 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8054 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8055 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8056 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8057 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8058 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8059 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8060 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8061 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8062 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8063 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8064 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8065 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8066 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8067 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8068 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8071 /* Expand the builtin in EXP and store the result in TARGET. Store
8072 true in *EXPANDEDP if we found a builtin to expand.
8074 This expands the SPE builtins that are not simple unary and binary
8077 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8079 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8081 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8082 enum insn_code icode;
8083 enum machine_mode tmode, mode0;
8085 struct builtin_description *d;
8090 /* Syntax check for a 5-bit unsigned immediate. */
8093 case SPE_BUILTIN_EVSTDD:
8094 case SPE_BUILTIN_EVSTDH:
8095 case SPE_BUILTIN_EVSTDW:
8096 case SPE_BUILTIN_EVSTWHE:
8097 case SPE_BUILTIN_EVSTWHO:
8098 case SPE_BUILTIN_EVSTWWE:
8099 case SPE_BUILTIN_EVSTWWO:
8100 arg1 = CALL_EXPR_ARG (exp, 2);
8101 if (TREE_CODE (arg1) != INTEGER_CST
8102 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8104 error ("argument 2 must be a 5-bit unsigned literal");
8112 /* The evsplat*i instructions are not quite generic. */
8115 case SPE_BUILTIN_EVSPLATFI:
8116 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8118 case SPE_BUILTIN_EVSPLATI:
8119 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8125 d = (struct builtin_description *) bdesc_2arg_spe;
8126 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8127 if (d->code == fcode)
8128 return rs6000_expand_binop_builtin (d->icode, exp, target);
8130 d = (struct builtin_description *) bdesc_spe_predicates;
8131 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8132 if (d->code == fcode)
8133 return spe_expand_predicate_builtin (d->icode, exp, target);
8135 d = (struct builtin_description *) bdesc_spe_evsel;
8136 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8137 if (d->code == fcode)
8138 return spe_expand_evsel_builtin (d->icode, exp, target);
8142 case SPE_BUILTIN_EVSTDDX:
8143 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8144 case SPE_BUILTIN_EVSTDHX:
8145 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8146 case SPE_BUILTIN_EVSTDWX:
8147 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8148 case SPE_BUILTIN_EVSTWHEX:
8149 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8150 case SPE_BUILTIN_EVSTWHOX:
8151 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8152 case SPE_BUILTIN_EVSTWWEX:
8153 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8154 case SPE_BUILTIN_EVSTWWOX:
8155 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8156 case SPE_BUILTIN_EVSTDD:
8157 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8158 case SPE_BUILTIN_EVSTDH:
8159 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8160 case SPE_BUILTIN_EVSTDW:
8161 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8162 case SPE_BUILTIN_EVSTWHE:
8163 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8164 case SPE_BUILTIN_EVSTWHO:
8165 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8166 case SPE_BUILTIN_EVSTWWE:
8167 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8168 case SPE_BUILTIN_EVSTWWO:
8169 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8170 case SPE_BUILTIN_MFSPEFSCR:
8171 icode = CODE_FOR_spe_mfspefscr;
8172 tmode = insn_data[icode].operand[0].mode;
8175 || GET_MODE (target) != tmode
8176 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8177 target = gen_reg_rtx (tmode);
8179 pat = GEN_FCN (icode) (target);
8184 case SPE_BUILTIN_MTSPEFSCR:
8185 icode = CODE_FOR_spe_mtspefscr;
8186 arg0 = CALL_EXPR_ARG (exp, 0);
8187 op0 = expand_normal (arg0);
8188 mode0 = insn_data[icode].operand[0].mode;
8190 if (arg0 == error_mark_node)
8193 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8194 op0 = copy_to_mode_reg (mode0, op0);
8196 pat = GEN_FCN (icode) (op0);
8209 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8211 rtx pat, scratch, tmp;
8212 tree form = CALL_EXPR_ARG (exp, 0);
8213 tree arg0 = CALL_EXPR_ARG (exp, 1);
8214 tree arg1 = CALL_EXPR_ARG (exp, 2);
8215 rtx op0 = expand_normal (arg0);
8216 rtx op1 = expand_normal (arg1);
8217 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8218 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8222 if (TREE_CODE (form) != INTEGER_CST)
8224 error ("argument 1 of __builtin_spe_predicate must be a constant");
8228 form_int = TREE_INT_CST_LOW (form);
8230 gcc_assert (mode0 == mode1);
8232 if (arg0 == error_mark_node || arg1 == error_mark_node)
8236 || GET_MODE (target) != SImode
8237 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8238 target = gen_reg_rtx (SImode);
8240 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8241 op0 = copy_to_mode_reg (mode0, op0);
8242 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8243 op1 = copy_to_mode_reg (mode1, op1);
8245 scratch = gen_reg_rtx (CCmode);
8247 pat = GEN_FCN (icode) (scratch, op0, op1);
8252 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8253 _lower_. We use one compare, but look in different bits of the
8254 CR for each variant.
8256 There are 2 elements in each SPE simd type (upper/lower). The CR
8257 bits are set as follows:
8259 BIT0 | BIT 1 | BIT 2 | BIT 3
8260 U | L | (U | L) | (U & L)
8262 So, for an "all" relationship, BIT 3 would be set.
8263 For an "any" relationship, BIT 2 would be set. Etc.
8265 Following traditional nomenclature, these bits map to:
8267 BIT0 | BIT 1 | BIT 2 | BIT 3
8270 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8275 /* All variant. OV bit. */
8277 /* We need to get to the OV bit, which is the ORDERED bit. We
8278 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8279 that's ugly and will make validate_condition_mode die.
8280 So let's just use another pattern. */
8281 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8283 /* Any variant. EQ bit. */
8287 /* Upper variant. LT bit. */
8291 /* Lower variant. GT bit. */
8296 error ("argument 1 of __builtin_spe_predicate is out of range");
8300 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8301 emit_move_insn (target, tmp);
8306 /* The evsel builtins look like this:
8308 e = __builtin_spe_evsel_OP (a, b, c, d);
8312 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8313 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8317 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8320 tree arg0 = CALL_EXPR_ARG (exp, 0);
8321 tree arg1 = CALL_EXPR_ARG (exp, 1);
8322 tree arg2 = CALL_EXPR_ARG (exp, 2);
8323 tree arg3 = CALL_EXPR_ARG (exp, 3);
8324 rtx op0 = expand_normal (arg0);
8325 rtx op1 = expand_normal (arg1);
8326 rtx op2 = expand_normal (arg2);
8327 rtx op3 = expand_normal (arg3);
8328 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8329 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8331 gcc_assert (mode0 == mode1);
8333 if (arg0 == error_mark_node || arg1 == error_mark_node
8334 || arg2 == error_mark_node || arg3 == error_mark_node)
8338 || GET_MODE (target) != mode0
8339 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8340 target = gen_reg_rtx (mode0);
8342 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8343 op0 = copy_to_mode_reg (mode0, op0);
8344 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8345 op1 = copy_to_mode_reg (mode0, op1);
8346 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8347 op2 = copy_to_mode_reg (mode0, op2);
8348 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8349 op3 = copy_to_mode_reg (mode0, op3);
8351 /* Generate the compare. */
8352 scratch = gen_reg_rtx (CCmode);
8353 pat = GEN_FCN (icode) (scratch, op0, op1);
8358 if (mode0 == V2SImode)
8359 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8361 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8366 /* Expand an expression EXP that calls a built-in function,
8367 with result going to TARGET if that's convenient
8368 (and in mode MODE if that's convenient).
8369 SUBTARGET may be used as the target for computing one of EXP's operands.
8370 IGNORE is nonzero if the value is to be ignored. */
8373 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8374 enum machine_mode mode ATTRIBUTE_UNUSED,
8375 int ignore ATTRIBUTE_UNUSED)
8377 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8378 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8379 struct builtin_description *d;
8384 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8385 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8387 int icode = (int) CODE_FOR_altivec_lvsr;
8388 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8389 enum machine_mode mode = insn_data[icode].operand[1].mode;
8393 gcc_assert (TARGET_ALTIVEC);
8395 arg = CALL_EXPR_ARG (exp, 0);
8396 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8397 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8398 addr = memory_address (mode, op);
8399 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8403 /* For the load case need to negate the address. */
8404 op = gen_reg_rtx (GET_MODE (addr));
8405 emit_insn (gen_rtx_SET (VOIDmode, op,
8406 gen_rtx_NEG (GET_MODE (addr), addr)));
8408 op = gen_rtx_MEM (mode, op);
8411 || GET_MODE (target) != tmode
8412 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8413 target = gen_reg_rtx (tmode);
8415 /*pat = gen_altivec_lvsr (target, op);*/
8416 pat = GEN_FCN (icode) (target, op);
8424 /* FIXME: There's got to be a nicer way to handle this case than
8425 constructing a new CALL_EXPR. */
8426 if (fcode == ALTIVEC_BUILTIN_VCFUX
8427 || fcode == ALTIVEC_BUILTIN_VCFSX)
8429 if (call_expr_nargs (exp) == 1)
8430 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8431 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8436 ret = altivec_expand_builtin (exp, target, &success);
8443 ret = spe_expand_builtin (exp, target, &success);
8449 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8451 /* Handle simple unary operations. */
8452 d = (struct builtin_description *) bdesc_1arg;
8453 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8454 if (d->code == fcode)
8455 return rs6000_expand_unop_builtin (d->icode, exp, target);
8457 /* Handle simple binary operations. */
8458 d = (struct builtin_description *) bdesc_2arg;
8459 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8460 if (d->code == fcode)
8461 return rs6000_expand_binop_builtin (d->icode, exp, target);
8463 /* Handle simple ternary operations. */
8464 d = (struct builtin_description *) bdesc_3arg;
8465 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8466 if (d->code == fcode)
8467 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8473 build_opaque_vector_type (tree node, int nunits)
8475 node = copy_node (node);
8476 TYPE_MAIN_VARIANT (node) = node;
8477 return build_vector_type (node, nunits);
8481 rs6000_init_builtins (void)
8483 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8484 V2SF_type_node = build_vector_type (float_type_node, 2);
8485 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8486 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8487 V4SF_type_node = build_vector_type (float_type_node, 4);
8488 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8489 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8491 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8492 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8493 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8495 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8496 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8497 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8498 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8500 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8501 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8502 'vector unsigned short'. */
8504 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8505 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8506 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8507 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8509 long_integer_type_internal_node = long_integer_type_node;
8510 long_unsigned_type_internal_node = long_unsigned_type_node;
8511 intQI_type_internal_node = intQI_type_node;
8512 uintQI_type_internal_node = unsigned_intQI_type_node;
8513 intHI_type_internal_node = intHI_type_node;
8514 uintHI_type_internal_node = unsigned_intHI_type_node;
8515 intSI_type_internal_node = intSI_type_node;
8516 uintSI_type_internal_node = unsigned_intSI_type_node;
8517 float_type_internal_node = float_type_node;
8518 void_type_internal_node = void_type_node;
8520 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8521 get_identifier ("__bool char"),
8522 bool_char_type_node));
8523 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8524 get_identifier ("__bool short"),
8525 bool_short_type_node));
8526 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8527 get_identifier ("__bool int"),
8528 bool_int_type_node));
8529 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8530 get_identifier ("__pixel"),
8533 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8534 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8535 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8536 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8538 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8539 get_identifier ("__vector unsigned char"),
8540 unsigned_V16QI_type_node));
8541 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8542 get_identifier ("__vector signed char"),
8544 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8545 get_identifier ("__vector __bool char"),
8546 bool_V16QI_type_node));
8548 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8549 get_identifier ("__vector unsigned short"),
8550 unsigned_V8HI_type_node));
8551 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8552 get_identifier ("__vector signed short"),
8554 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8555 get_identifier ("__vector __bool short"),
8556 bool_V8HI_type_node));
8558 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8559 get_identifier ("__vector unsigned int"),
8560 unsigned_V4SI_type_node));
8561 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8562 get_identifier ("__vector signed int"),
8564 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8565 get_identifier ("__vector __bool int"),
8566 bool_V4SI_type_node));
8568 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8569 get_identifier ("__vector float"),
8571 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8572 get_identifier ("__vector __pixel"),
8573 pixel_V8HI_type_node));
8576 spe_init_builtins ();
8578 altivec_init_builtins ();
8579 if (TARGET_ALTIVEC || TARGET_SPE)
8580 rs6000_common_init_builtins ();
8583 /* AIX libm provides clog as __clog. */
8584 if (built_in_decls [BUILT_IN_CLOG])
8585 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8589 /* Search through a set of builtins and enable the mask bits.
8590 DESC is an array of builtins.
8591 SIZE is the total number of builtins.
8592 START is the builtin enum at which to start.
8593 END is the builtin enum at which to end. */
8595 enable_mask_for_builtins (struct builtin_description *desc, int size,
8596 enum rs6000_builtins start,
8597 enum rs6000_builtins end)
8601 for (i = 0; i < size; ++i)
8602 if (desc[i].code == start)
8608 for (; i < size; ++i)
8610 /* Flip all the bits on. */
8611 desc[i].mask = target_flags;
8612 if (desc[i].code == end)
8618 spe_init_builtins (void)
8620 tree endlink = void_list_node;
8621 tree puint_type_node = build_pointer_type (unsigned_type_node);
8622 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8623 struct builtin_description *d;
8626 tree v2si_ftype_4_v2si
8627 = build_function_type
8628 (opaque_V2SI_type_node,
8629 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8630 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8631 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8632 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8635 tree v2sf_ftype_4_v2sf
8636 = build_function_type
8637 (opaque_V2SF_type_node,
8638 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8639 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8640 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8641 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8644 tree int_ftype_int_v2si_v2si
8645 = build_function_type
8647 tree_cons (NULL_TREE, integer_type_node,
8648 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8649 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8652 tree int_ftype_int_v2sf_v2sf
8653 = build_function_type
8655 tree_cons (NULL_TREE, integer_type_node,
8656 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8657 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8660 tree void_ftype_v2si_puint_int
8661 = build_function_type (void_type_node,
8662 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8663 tree_cons (NULL_TREE, puint_type_node,
8664 tree_cons (NULL_TREE,
8668 tree void_ftype_v2si_puint_char
8669 = build_function_type (void_type_node,
8670 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8671 tree_cons (NULL_TREE, puint_type_node,
8672 tree_cons (NULL_TREE,
8676 tree void_ftype_v2si_pv2si_int
8677 = build_function_type (void_type_node,
8678 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8679 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8680 tree_cons (NULL_TREE,
8684 tree void_ftype_v2si_pv2si_char
8685 = build_function_type (void_type_node,
8686 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8687 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8688 tree_cons (NULL_TREE,
8693 = build_function_type (void_type_node,
8694 tree_cons (NULL_TREE, integer_type_node, endlink));
8697 = build_function_type (integer_type_node, endlink);
8699 tree v2si_ftype_pv2si_int
8700 = build_function_type (opaque_V2SI_type_node,
8701 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8702 tree_cons (NULL_TREE, integer_type_node,
8705 tree v2si_ftype_puint_int
8706 = build_function_type (opaque_V2SI_type_node,
8707 tree_cons (NULL_TREE, puint_type_node,
8708 tree_cons (NULL_TREE, integer_type_node,
8711 tree v2si_ftype_pushort_int
8712 = build_function_type (opaque_V2SI_type_node,
8713 tree_cons (NULL_TREE, pushort_type_node,
8714 tree_cons (NULL_TREE, integer_type_node,
8717 tree v2si_ftype_signed_char
8718 = build_function_type (opaque_V2SI_type_node,
8719 tree_cons (NULL_TREE, signed_char_type_node,
8722 /* The initialization of the simple binary and unary builtins is
8723 done in rs6000_common_init_builtins, but we have to enable the
8724 mask bits here manually because we have run out of `target_flags'
8725 bits. We really need to redesign this mask business. */
8727 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8728 ARRAY_SIZE (bdesc_2arg),
8731 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8732 ARRAY_SIZE (bdesc_1arg),
8734 SPE_BUILTIN_EVSUBFUSIAAW);
8735 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8736 ARRAY_SIZE (bdesc_spe_predicates),
8737 SPE_BUILTIN_EVCMPEQ,
8738 SPE_BUILTIN_EVFSTSTLT);
8739 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8740 ARRAY_SIZE (bdesc_spe_evsel),
8741 SPE_BUILTIN_EVSEL_CMPGTS,
8742 SPE_BUILTIN_EVSEL_FSTSTEQ);
8744 (*lang_hooks.decls.pushdecl)
8745 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8746 opaque_V2SI_type_node));
8748 /* Initialize irregular SPE builtins. */
8750 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8751 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8752 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8753 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8754 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8755 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8756 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8757 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8758 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8759 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8760 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8761 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8762 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8763 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8764 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8765 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8766 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8767 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8770 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8771 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8772 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8773 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8774 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8775 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8776 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8777 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8778 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8779 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8780 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8781 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8782 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8783 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8784 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8785 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8786 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8787 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8788 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8789 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8790 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8791 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8794 d = (struct builtin_description *) bdesc_spe_predicates;
8795 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8799 switch (insn_data[d->icode].operand[1].mode)
8802 type = int_ftype_int_v2si_v2si;
8805 type = int_ftype_int_v2sf_v2sf;
8811 def_builtin (d->mask, d->name, type, d->code);
8814 /* Evsel predicates. */
8815 d = (struct builtin_description *) bdesc_spe_evsel;
8816 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8820 switch (insn_data[d->icode].operand[1].mode)
8823 type = v2si_ftype_4_v2si;
8826 type = v2sf_ftype_4_v2sf;
8832 def_builtin (d->mask, d->name, type, d->code);
8837 altivec_init_builtins (void)
8839 struct builtin_description *d;
8840 struct builtin_description_predicates *dp;
8844 tree pfloat_type_node = build_pointer_type (float_type_node);
8845 tree pint_type_node = build_pointer_type (integer_type_node);
8846 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8847 tree pchar_type_node = build_pointer_type (char_type_node);
8849 tree pvoid_type_node = build_pointer_type (void_type_node);
8851 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8852 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8853 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8854 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8856 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8858 tree int_ftype_opaque
8859 = build_function_type_list (integer_type_node,
8860 opaque_V4SI_type_node, NULL_TREE);
8862 tree opaque_ftype_opaque_int
8863 = build_function_type_list (opaque_V4SI_type_node,
8864 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8865 tree opaque_ftype_opaque_opaque_int
8866 = build_function_type_list (opaque_V4SI_type_node,
8867 opaque_V4SI_type_node, opaque_V4SI_type_node,
8868 integer_type_node, NULL_TREE);
8869 tree int_ftype_int_opaque_opaque
8870 = build_function_type_list (integer_type_node,
8871 integer_type_node, opaque_V4SI_type_node,
8872 opaque_V4SI_type_node, NULL_TREE);
8873 tree int_ftype_int_v4si_v4si
8874 = build_function_type_list (integer_type_node,
8875 integer_type_node, V4SI_type_node,
8876 V4SI_type_node, NULL_TREE);
8877 tree v4sf_ftype_pcfloat
8878 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8879 tree void_ftype_pfloat_v4sf
8880 = build_function_type_list (void_type_node,
8881 pfloat_type_node, V4SF_type_node, NULL_TREE);
8882 tree v4si_ftype_pcint
8883 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8884 tree void_ftype_pint_v4si
8885 = build_function_type_list (void_type_node,
8886 pint_type_node, V4SI_type_node, NULL_TREE);
8887 tree v8hi_ftype_pcshort
8888 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8889 tree void_ftype_pshort_v8hi
8890 = build_function_type_list (void_type_node,
8891 pshort_type_node, V8HI_type_node, NULL_TREE);
8892 tree v16qi_ftype_pcchar
8893 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8894 tree void_ftype_pchar_v16qi
8895 = build_function_type_list (void_type_node,
8896 pchar_type_node, V16QI_type_node, NULL_TREE);
8897 tree void_ftype_v4si
8898 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8899 tree v8hi_ftype_void
8900 = build_function_type (V8HI_type_node, void_list_node);
8901 tree void_ftype_void
8902 = build_function_type (void_type_node, void_list_node);
8904 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8906 tree opaque_ftype_long_pcvoid
8907 = build_function_type_list (opaque_V4SI_type_node,
8908 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8909 tree v16qi_ftype_long_pcvoid
8910 = build_function_type_list (V16QI_type_node,
8911 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8912 tree v8hi_ftype_long_pcvoid
8913 = build_function_type_list (V8HI_type_node,
8914 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8915 tree v4si_ftype_long_pcvoid
8916 = build_function_type_list (V4SI_type_node,
8917 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8919 tree void_ftype_opaque_long_pvoid
8920 = build_function_type_list (void_type_node,
8921 opaque_V4SI_type_node, long_integer_type_node,
8922 pvoid_type_node, NULL_TREE);
8923 tree void_ftype_v4si_long_pvoid
8924 = build_function_type_list (void_type_node,
8925 V4SI_type_node, long_integer_type_node,
8926 pvoid_type_node, NULL_TREE);
8927 tree void_ftype_v16qi_long_pvoid
8928 = build_function_type_list (void_type_node,
8929 V16QI_type_node, long_integer_type_node,
8930 pvoid_type_node, NULL_TREE);
8931 tree void_ftype_v8hi_long_pvoid
8932 = build_function_type_list (void_type_node,
8933 V8HI_type_node, long_integer_type_node,
8934 pvoid_type_node, NULL_TREE);
8935 tree int_ftype_int_v8hi_v8hi
8936 = build_function_type_list (integer_type_node,
8937 integer_type_node, V8HI_type_node,
8938 V8HI_type_node, NULL_TREE);
8939 tree int_ftype_int_v16qi_v16qi
8940 = build_function_type_list (integer_type_node,
8941 integer_type_node, V16QI_type_node,
8942 V16QI_type_node, NULL_TREE);
8943 tree int_ftype_int_v4sf_v4sf
8944 = build_function_type_list (integer_type_node,
8945 integer_type_node, V4SF_type_node,
8946 V4SF_type_node, NULL_TREE);
8947 tree v4si_ftype_v4si
8948 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8949 tree v8hi_ftype_v8hi
8950 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8951 tree v16qi_ftype_v16qi
8952 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8953 tree v4sf_ftype_v4sf
8954 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8955 tree void_ftype_pcvoid_int_int
8956 = build_function_type_list (void_type_node,
8957 pcvoid_type_node, integer_type_node,
8958 integer_type_node, NULL_TREE);
8960 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8961 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8962 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8963 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8964 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8965 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8966 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8967 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8968 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8969 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8970 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8971 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8972 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8973 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8974 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8975 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8976 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8977 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8978 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8979 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8980 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8981 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8982 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8983 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8984 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8985 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8986 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8987 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8988 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8989 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8990 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8991 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8992 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8993 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8994 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8995 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8996 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8997 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8998 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8999 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9000 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9001 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9002 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9003 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9004 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9005 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9007 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9009 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9010 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9011 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9012 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9013 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9014 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9015 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9016 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9017 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9018 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9020 /* Add the DST variants. */
9021 d = (struct builtin_description *) bdesc_dst;
9022 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9023 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9025 /* Initialize the predicates. */
9026 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
9027 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9029 enum machine_mode mode1;
9031 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9032 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9037 mode1 = insn_data[dp->icode].operand[1].mode;
9042 type = int_ftype_int_opaque_opaque;
9045 type = int_ftype_int_v4si_v4si;
9048 type = int_ftype_int_v8hi_v8hi;
9051 type = int_ftype_int_v16qi_v16qi;
9054 type = int_ftype_int_v4sf_v4sf;
9060 def_builtin (dp->mask, dp->name, type, dp->code);
9063 /* Initialize the abs* operators. */
9064 d = (struct builtin_description *) bdesc_abs;
9065 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9067 enum machine_mode mode0;
9070 mode0 = insn_data[d->icode].operand[0].mode;
9075 type = v4si_ftype_v4si;
9078 type = v8hi_ftype_v8hi;
9081 type = v16qi_ftype_v16qi;
9084 type = v4sf_ftype_v4sf;
9090 def_builtin (d->mask, d->name, type, d->code);
9097 /* Initialize target builtin that implements
9098 targetm.vectorize.builtin_mask_for_load. */
9100 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9101 v16qi_ftype_long_pcvoid,
9102 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9103 BUILT_IN_MD, NULL, NULL_TREE);
9104 TREE_READONLY (decl) = 1;
9105 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9106 altivec_builtin_mask_for_load = decl;
9109 /* Access to the vec_init patterns. */
9110 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9111 integer_type_node, integer_type_node,
9112 integer_type_node, NULL_TREE);
9113 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9114 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9116 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9117 short_integer_type_node,
9118 short_integer_type_node,
9119 short_integer_type_node,
9120 short_integer_type_node,
9121 short_integer_type_node,
9122 short_integer_type_node,
9123 short_integer_type_node, NULL_TREE);
9124 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9125 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9127 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9128 char_type_node, char_type_node,
9129 char_type_node, char_type_node,
9130 char_type_node, char_type_node,
9131 char_type_node, char_type_node,
9132 char_type_node, char_type_node,
9133 char_type_node, char_type_node,
9134 char_type_node, char_type_node,
9135 char_type_node, NULL_TREE);
9136 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9137 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9139 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9140 float_type_node, float_type_node,
9141 float_type_node, NULL_TREE);
9142 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9143 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9145 /* Access to the vec_set patterns. */
9146 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9148 integer_type_node, NULL_TREE);
9149 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9150 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9152 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9154 integer_type_node, NULL_TREE);
9155 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9156 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9158 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9160 integer_type_node, NULL_TREE);
9161 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9162 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9164 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9166 integer_type_node, NULL_TREE);
9167 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9168 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9170 /* Access to the vec_extract patterns. */
9171 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9172 integer_type_node, NULL_TREE);
9173 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9174 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9176 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9177 integer_type_node, NULL_TREE);
9178 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9179 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9181 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9182 integer_type_node, NULL_TREE);
9183 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9184 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9186 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9187 integer_type_node, NULL_TREE);
9188 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9189 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9193 rs6000_common_init_builtins (void)
9195 struct builtin_description *d;
9198 tree v4sf_ftype_v4sf_v4sf_v16qi
9199 = build_function_type_list (V4SF_type_node,
9200 V4SF_type_node, V4SF_type_node,
9201 V16QI_type_node, NULL_TREE);
9202 tree v4si_ftype_v4si_v4si_v16qi
9203 = build_function_type_list (V4SI_type_node,
9204 V4SI_type_node, V4SI_type_node,
9205 V16QI_type_node, NULL_TREE);
9206 tree v8hi_ftype_v8hi_v8hi_v16qi
9207 = build_function_type_list (V8HI_type_node,
9208 V8HI_type_node, V8HI_type_node,
9209 V16QI_type_node, NULL_TREE);
9210 tree v16qi_ftype_v16qi_v16qi_v16qi
9211 = build_function_type_list (V16QI_type_node,
9212 V16QI_type_node, V16QI_type_node,
9213 V16QI_type_node, NULL_TREE);
9215 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9217 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9218 tree v16qi_ftype_int
9219 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9220 tree v8hi_ftype_v16qi
9221 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9222 tree v4sf_ftype_v4sf
9223 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9225 tree v2si_ftype_v2si_v2si
9226 = build_function_type_list (opaque_V2SI_type_node,
9227 opaque_V2SI_type_node,
9228 opaque_V2SI_type_node, NULL_TREE);
9230 tree v2sf_ftype_v2sf_v2sf
9231 = build_function_type_list (opaque_V2SF_type_node,
9232 opaque_V2SF_type_node,
9233 opaque_V2SF_type_node, NULL_TREE);
9235 tree v2si_ftype_int_int
9236 = build_function_type_list (opaque_V2SI_type_node,
9237 integer_type_node, integer_type_node,
9240 tree opaque_ftype_opaque
9241 = build_function_type_list (opaque_V4SI_type_node,
9242 opaque_V4SI_type_node, NULL_TREE);
9244 tree v2si_ftype_v2si
9245 = build_function_type_list (opaque_V2SI_type_node,
9246 opaque_V2SI_type_node, NULL_TREE);
9248 tree v2sf_ftype_v2sf
9249 = build_function_type_list (opaque_V2SF_type_node,
9250 opaque_V2SF_type_node, NULL_TREE);
9252 tree v2sf_ftype_v2si
9253 = build_function_type_list (opaque_V2SF_type_node,
9254 opaque_V2SI_type_node, NULL_TREE);
9256 tree v2si_ftype_v2sf
9257 = build_function_type_list (opaque_V2SI_type_node,
9258 opaque_V2SF_type_node, NULL_TREE);
9260 tree v2si_ftype_v2si_char
9261 = build_function_type_list (opaque_V2SI_type_node,
9262 opaque_V2SI_type_node,
9263 char_type_node, NULL_TREE);
9265 tree v2si_ftype_int_char
9266 = build_function_type_list (opaque_V2SI_type_node,
9267 integer_type_node, char_type_node, NULL_TREE);
9269 tree v2si_ftype_char
9270 = build_function_type_list (opaque_V2SI_type_node,
9271 char_type_node, NULL_TREE);
9273 tree int_ftype_int_int
9274 = build_function_type_list (integer_type_node,
9275 integer_type_node, integer_type_node,
9278 tree opaque_ftype_opaque_opaque
9279 = build_function_type_list (opaque_V4SI_type_node,
9280 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9281 tree v4si_ftype_v4si_v4si
9282 = build_function_type_list (V4SI_type_node,
9283 V4SI_type_node, V4SI_type_node, NULL_TREE);
9284 tree v4sf_ftype_v4si_int
9285 = build_function_type_list (V4SF_type_node,
9286 V4SI_type_node, integer_type_node, NULL_TREE);
9287 tree v4si_ftype_v4sf_int
9288 = build_function_type_list (V4SI_type_node,
9289 V4SF_type_node, integer_type_node, NULL_TREE);
9290 tree v4si_ftype_v4si_int
9291 = build_function_type_list (V4SI_type_node,
9292 V4SI_type_node, integer_type_node, NULL_TREE);
9293 tree v8hi_ftype_v8hi_int
9294 = build_function_type_list (V8HI_type_node,
9295 V8HI_type_node, integer_type_node, NULL_TREE);
9296 tree v16qi_ftype_v16qi_int
9297 = build_function_type_list (V16QI_type_node,
9298 V16QI_type_node, integer_type_node, NULL_TREE);
9299 tree v16qi_ftype_v16qi_v16qi_int
9300 = build_function_type_list (V16QI_type_node,
9301 V16QI_type_node, V16QI_type_node,
9302 integer_type_node, NULL_TREE);
9303 tree v8hi_ftype_v8hi_v8hi_int
9304 = build_function_type_list (V8HI_type_node,
9305 V8HI_type_node, V8HI_type_node,
9306 integer_type_node, NULL_TREE);
9307 tree v4si_ftype_v4si_v4si_int
9308 = build_function_type_list (V4SI_type_node,
9309 V4SI_type_node, V4SI_type_node,
9310 integer_type_node, NULL_TREE);
9311 tree v4sf_ftype_v4sf_v4sf_int
9312 = build_function_type_list (V4SF_type_node,
9313 V4SF_type_node, V4SF_type_node,
9314 integer_type_node, NULL_TREE);
9315 tree v4sf_ftype_v4sf_v4sf
9316 = build_function_type_list (V4SF_type_node,
9317 V4SF_type_node, V4SF_type_node, NULL_TREE);
9318 tree opaque_ftype_opaque_opaque_opaque
9319 = build_function_type_list (opaque_V4SI_type_node,
9320 opaque_V4SI_type_node, opaque_V4SI_type_node,
9321 opaque_V4SI_type_node, NULL_TREE);
9322 tree v4sf_ftype_v4sf_v4sf_v4si
9323 = build_function_type_list (V4SF_type_node,
9324 V4SF_type_node, V4SF_type_node,
9325 V4SI_type_node, NULL_TREE);
9326 tree v4sf_ftype_v4sf_v4sf_v4sf
9327 = build_function_type_list (V4SF_type_node,
9328 V4SF_type_node, V4SF_type_node,
9329 V4SF_type_node, NULL_TREE);
9330 tree v4si_ftype_v4si_v4si_v4si
9331 = build_function_type_list (V4SI_type_node,
9332 V4SI_type_node, V4SI_type_node,
9333 V4SI_type_node, NULL_TREE);
9334 tree v8hi_ftype_v8hi_v8hi
9335 = build_function_type_list (V8HI_type_node,
9336 V8HI_type_node, V8HI_type_node, NULL_TREE);
9337 tree v8hi_ftype_v8hi_v8hi_v8hi
9338 = build_function_type_list (V8HI_type_node,
9339 V8HI_type_node, V8HI_type_node,
9340 V8HI_type_node, NULL_TREE);
9341 tree v4si_ftype_v8hi_v8hi_v4si
9342 = build_function_type_list (V4SI_type_node,
9343 V8HI_type_node, V8HI_type_node,
9344 V4SI_type_node, NULL_TREE);
9345 tree v4si_ftype_v16qi_v16qi_v4si
9346 = build_function_type_list (V4SI_type_node,
9347 V16QI_type_node, V16QI_type_node,
9348 V4SI_type_node, NULL_TREE);
9349 tree v16qi_ftype_v16qi_v16qi
9350 = build_function_type_list (V16QI_type_node,
9351 V16QI_type_node, V16QI_type_node, NULL_TREE);
9352 tree v4si_ftype_v4sf_v4sf
9353 = build_function_type_list (V4SI_type_node,
9354 V4SF_type_node, V4SF_type_node, NULL_TREE);
9355 tree v8hi_ftype_v16qi_v16qi
9356 = build_function_type_list (V8HI_type_node,
9357 V16QI_type_node, V16QI_type_node, NULL_TREE);
9358 tree v4si_ftype_v8hi_v8hi
9359 = build_function_type_list (V4SI_type_node,
9360 V8HI_type_node, V8HI_type_node, NULL_TREE);
9361 tree v8hi_ftype_v4si_v4si
9362 = build_function_type_list (V8HI_type_node,
9363 V4SI_type_node, V4SI_type_node, NULL_TREE);
9364 tree v16qi_ftype_v8hi_v8hi
9365 = build_function_type_list (V16QI_type_node,
9366 V8HI_type_node, V8HI_type_node, NULL_TREE);
9367 tree v4si_ftype_v16qi_v4si
9368 = build_function_type_list (V4SI_type_node,
9369 V16QI_type_node, V4SI_type_node, NULL_TREE);
9370 tree v4si_ftype_v16qi_v16qi
9371 = build_function_type_list (V4SI_type_node,
9372 V16QI_type_node, V16QI_type_node, NULL_TREE);
9373 tree v4si_ftype_v8hi_v4si
9374 = build_function_type_list (V4SI_type_node,
9375 V8HI_type_node, V4SI_type_node, NULL_TREE);
9376 tree v4si_ftype_v8hi
9377 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9378 tree int_ftype_v4si_v4si
9379 = build_function_type_list (integer_type_node,
9380 V4SI_type_node, V4SI_type_node, NULL_TREE);
9381 tree int_ftype_v4sf_v4sf
9382 = build_function_type_list (integer_type_node,
9383 V4SF_type_node, V4SF_type_node, NULL_TREE);
9384 tree int_ftype_v16qi_v16qi
9385 = build_function_type_list (integer_type_node,
9386 V16QI_type_node, V16QI_type_node, NULL_TREE);
9387 tree int_ftype_v8hi_v8hi
9388 = build_function_type_list (integer_type_node,
9389 V8HI_type_node, V8HI_type_node, NULL_TREE);
9391 /* Add the simple ternary operators. */
9392 d = (struct builtin_description *) bdesc_3arg;
9393 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9395 enum machine_mode mode0, mode1, mode2, mode3;
9397 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9398 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9409 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9412 mode0 = insn_data[d->icode].operand[0].mode;
9413 mode1 = insn_data[d->icode].operand[1].mode;
9414 mode2 = insn_data[d->icode].operand[2].mode;
9415 mode3 = insn_data[d->icode].operand[3].mode;
9418 /* When all four are of the same mode. */
9419 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9424 type = opaque_ftype_opaque_opaque_opaque;
9427 type = v4si_ftype_v4si_v4si_v4si;
9430 type = v4sf_ftype_v4sf_v4sf_v4sf;
9433 type = v8hi_ftype_v8hi_v8hi_v8hi;
9436 type = v16qi_ftype_v16qi_v16qi_v16qi;
9442 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9447 type = v4si_ftype_v4si_v4si_v16qi;
9450 type = v4sf_ftype_v4sf_v4sf_v16qi;
9453 type = v8hi_ftype_v8hi_v8hi_v16qi;
9456 type = v16qi_ftype_v16qi_v16qi_v16qi;
9462 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9463 && mode3 == V4SImode)
9464 type = v4si_ftype_v16qi_v16qi_v4si;
9465 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9466 && mode3 == V4SImode)
9467 type = v4si_ftype_v8hi_v8hi_v4si;
9468 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9469 && mode3 == V4SImode)
9470 type = v4sf_ftype_v4sf_v4sf_v4si;
9472 /* vchar, vchar, vchar, 4-bit literal. */
9473 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9475 type = v16qi_ftype_v16qi_v16qi_int;
9477 /* vshort, vshort, vshort, 4-bit literal. */
9478 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9480 type = v8hi_ftype_v8hi_v8hi_int;
9482 /* vint, vint, vint, 4-bit literal. */
9483 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9485 type = v4si_ftype_v4si_v4si_int;
9487 /* vfloat, vfloat, vfloat, 4-bit literal. */
9488 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9490 type = v4sf_ftype_v4sf_v4sf_int;
9495 def_builtin (d->mask, d->name, type, d->code);
9498 /* Add the simple binary operators. */
9499 d = (struct builtin_description *) bdesc_2arg;
9500 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9502 enum machine_mode mode0, mode1, mode2;
9504 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9505 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9515 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9518 mode0 = insn_data[d->icode].operand[0].mode;
9519 mode1 = insn_data[d->icode].operand[1].mode;
9520 mode2 = insn_data[d->icode].operand[2].mode;
9523 /* When all three operands are of the same mode. */
9524 if (mode0 == mode1 && mode1 == mode2)
9529 type = opaque_ftype_opaque_opaque;
9532 type = v4sf_ftype_v4sf_v4sf;
9535 type = v4si_ftype_v4si_v4si;
9538 type = v16qi_ftype_v16qi_v16qi;
9541 type = v8hi_ftype_v8hi_v8hi;
9544 type = v2si_ftype_v2si_v2si;
9547 type = v2sf_ftype_v2sf_v2sf;
9550 type = int_ftype_int_int;
9557 /* A few other combos we really don't want to do manually. */
9559 /* vint, vfloat, vfloat. */
9560 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9561 type = v4si_ftype_v4sf_v4sf;
9563 /* vshort, vchar, vchar. */
9564 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9565 type = v8hi_ftype_v16qi_v16qi;
9567 /* vint, vshort, vshort. */
9568 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9569 type = v4si_ftype_v8hi_v8hi;
9571 /* vshort, vint, vint. */
9572 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9573 type = v8hi_ftype_v4si_v4si;
9575 /* vchar, vshort, vshort. */
9576 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9577 type = v16qi_ftype_v8hi_v8hi;
9579 /* vint, vchar, vint. */
9580 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9581 type = v4si_ftype_v16qi_v4si;
9583 /* vint, vchar, vchar. */
9584 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9585 type = v4si_ftype_v16qi_v16qi;
9587 /* vint, vshort, vint. */
9588 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9589 type = v4si_ftype_v8hi_v4si;
9591 /* vint, vint, 5-bit literal. */
9592 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9593 type = v4si_ftype_v4si_int;
9595 /* vshort, vshort, 5-bit literal. */
9596 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9597 type = v8hi_ftype_v8hi_int;
9599 /* vchar, vchar, 5-bit literal. */
9600 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9601 type = v16qi_ftype_v16qi_int;
9603 /* vfloat, vint, 5-bit literal. */
9604 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9605 type = v4sf_ftype_v4si_int;
9607 /* vint, vfloat, 5-bit literal. */
9608 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9609 type = v4si_ftype_v4sf_int;
9611 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9612 type = v2si_ftype_int_int;
9614 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9615 type = v2si_ftype_v2si_char;
9617 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9618 type = v2si_ftype_int_char;
9623 gcc_assert (mode0 == SImode);
9627 type = int_ftype_v4si_v4si;
9630 type = int_ftype_v4sf_v4sf;
9633 type = int_ftype_v16qi_v16qi;
9636 type = int_ftype_v8hi_v8hi;
9643 def_builtin (d->mask, d->name, type, d->code);
9646 /* Add the simple unary operators. */
9647 d = (struct builtin_description *) bdesc_1arg;
9648 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9650 enum machine_mode mode0, mode1;
9652 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9653 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9662 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9665 mode0 = insn_data[d->icode].operand[0].mode;
9666 mode1 = insn_data[d->icode].operand[1].mode;
9669 if (mode0 == V4SImode && mode1 == QImode)
9670 type = v4si_ftype_int;
9671 else if (mode0 == V8HImode && mode1 == QImode)
9672 type = v8hi_ftype_int;
9673 else if (mode0 == V16QImode && mode1 == QImode)
9674 type = v16qi_ftype_int;
9675 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9676 type = opaque_ftype_opaque;
9677 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9678 type = v4sf_ftype_v4sf;
9679 else if (mode0 == V8HImode && mode1 == V16QImode)
9680 type = v8hi_ftype_v16qi;
9681 else if (mode0 == V4SImode && mode1 == V8HImode)
9682 type = v4si_ftype_v8hi;
9683 else if (mode0 == V2SImode && mode1 == V2SImode)
9684 type = v2si_ftype_v2si;
9685 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9686 type = v2sf_ftype_v2sf;
9687 else if (mode0 == V2SFmode && mode1 == V2SImode)
9688 type = v2sf_ftype_v2si;
9689 else if (mode0 == V2SImode && mode1 == V2SFmode)
9690 type = v2si_ftype_v2sf;
9691 else if (mode0 == V2SImode && mode1 == QImode)
9692 type = v2si_ftype_char;
9696 def_builtin (d->mask, d->name, type, d->code);
9701 rs6000_init_libfuncs (void)
9703 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9704 && !TARGET_POWER2 && !TARGET_POWERPC)
9706 /* AIX library routines for float->int conversion. */
9707 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9708 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9709 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9710 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9713 if (!TARGET_IEEEQUAD)
9714 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9715 if (!TARGET_XL_COMPAT)
9717 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9718 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9719 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9720 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9722 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9724 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9725 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9726 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9727 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9728 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9729 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9730 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9732 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9733 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9734 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9735 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9736 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9737 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9738 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9739 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9742 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
9743 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9747 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9748 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9749 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9750 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9754 /* 32-bit SVR4 quad floating point routines. */
9756 set_optab_libfunc (add_optab, TFmode, "_q_add");
9757 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9758 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9759 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9760 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9761 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9762 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9764 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9765 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9766 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9767 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9768 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9769 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9771 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9772 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9773 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9774 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9775 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9776 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9777 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9778 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9783 /* Expand a block clear operation, and return 1 if successful. Return 0
9784 if we should let the compiler generate normal code.
9786 operands[0] is the destination
9787 operands[1] is the length
9788 operands[3] is the alignment */
9791 expand_block_clear (rtx operands[])
9793 rtx orig_dest = operands[0];
9794 rtx bytes_rtx = operands[1];
9795 rtx align_rtx = operands[3];
9796 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9797 HOST_WIDE_INT align;
9798 HOST_WIDE_INT bytes;
9803 /* If this is not a fixed size move, just call memcpy */
9807 /* This must be a fixed size alignment */
9808 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9809 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9811 /* Anything to clear? */
9812 bytes = INTVAL (bytes_rtx);
9816 /* Use the builtin memset after a point, to avoid huge code bloat.
9817 When optimize_size, avoid any significant code bloat; calling
9818 memset is about 4 instructions, so allow for one instruction to
9819 load zero and three to do clearing. */
9820 if (TARGET_ALTIVEC && align >= 128)
9822 else if (TARGET_POWERPC64 && align >= 32)
9827 if (optimize_size && bytes > 3 * clear_step)
9829 if (! optimize_size && bytes > 8 * clear_step)
9832 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9834 enum machine_mode mode = BLKmode;
9837 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9842 else if (bytes >= 8 && TARGET_POWERPC64
9843 /* 64-bit loads and stores require word-aligned
9845 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9850 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9851 { /* move 4 bytes */
9855 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9856 { /* move 2 bytes */
9860 else /* move 1 byte at a time */
9866 dest = adjust_address (orig_dest, mode, offset);
9868 emit_move_insn (dest, CONST0_RTX (mode));
9875 /* Expand a block move operation, and return 1 if successful. Return 0
9876 if we should let the compiler generate normal code.
9878 operands[0] is the destination
9879 operands[1] is the source
9880 operands[2] is the length
9881 operands[3] is the alignment */
9883 #define MAX_MOVE_REG 4
9886 expand_block_move (rtx operands[])
9888 rtx orig_dest = operands[0];
9889 rtx orig_src = operands[1];
9890 rtx bytes_rtx = operands[2];
9891 rtx align_rtx = operands[3];
9892 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9897 rtx stores[MAX_MOVE_REG];
9900 /* If this is not a fixed size move, just call memcpy */
9904 /* This must be a fixed size alignment */
9905 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9906 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9908 /* Anything to move? */
9909 bytes = INTVAL (bytes_rtx);
9913 /* store_one_arg depends on expand_block_move to handle at least the size of
9914 reg_parm_stack_space. */
9915 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9918 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9921 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9922 rtx (*mov) (rtx, rtx);
9924 enum machine_mode mode = BLKmode;
9927 /* Altivec first, since it will be faster than a string move
9928 when it applies, and usually not significantly larger. */
9929 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9933 gen_func.mov = gen_movv4si;
9935 else if (TARGET_STRING
9936 && bytes > 24 /* move up to 32 bytes at a time */
9944 && ! fixed_regs[12])
9946 move_bytes = (bytes > 32) ? 32 : bytes;
9947 gen_func.movmemsi = gen_movmemsi_8reg;
9949 else if (TARGET_STRING
9950 && bytes > 16 /* move up to 24 bytes at a time */
9956 && ! fixed_regs[10])
9958 move_bytes = (bytes > 24) ? 24 : bytes;
9959 gen_func.movmemsi = gen_movmemsi_6reg;
9961 else if (TARGET_STRING
9962 && bytes > 8 /* move up to 16 bytes at a time */
9968 move_bytes = (bytes > 16) ? 16 : bytes;
9969 gen_func.movmemsi = gen_movmemsi_4reg;
9971 else if (bytes >= 8 && TARGET_POWERPC64
9972 /* 64-bit loads and stores require word-aligned
9974 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9978 gen_func.mov = gen_movdi;
9980 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9981 { /* move up to 8 bytes at a time */
9982 move_bytes = (bytes > 8) ? 8 : bytes;
9983 gen_func.movmemsi = gen_movmemsi_2reg;
9985 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9986 { /* move 4 bytes */
9989 gen_func.mov = gen_movsi;
9991 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9992 { /* move 2 bytes */
9995 gen_func.mov = gen_movhi;
9997 else if (TARGET_STRING && bytes > 1)
9998 { /* move up to 4 bytes at a time */
9999 move_bytes = (bytes > 4) ? 4 : bytes;
10000 gen_func.movmemsi = gen_movmemsi_1reg;
10002 else /* move 1 byte at a time */
10006 gen_func.mov = gen_movqi;
10009 src = adjust_address (orig_src, mode, offset);
10010 dest = adjust_address (orig_dest, mode, offset);
10012 if (mode != BLKmode)
10014 rtx tmp_reg = gen_reg_rtx (mode);
10016 emit_insn ((*gen_func.mov) (tmp_reg, src));
10017 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10020 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10023 for (i = 0; i < num_reg; i++)
10024 emit_insn (stores[i]);
10028 if (mode == BLKmode)
10030 /* Move the address into scratch registers. The movmemsi
10031 patterns require zero offset. */
10032 if (!REG_P (XEXP (src, 0)))
10034 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10035 src = replace_equiv_address (src, src_reg);
10037 set_mem_size (src, GEN_INT (move_bytes));
10039 if (!REG_P (XEXP (dest, 0)))
10041 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10042 dest = replace_equiv_address (dest, dest_reg);
10044 set_mem_size (dest, GEN_INT (move_bytes));
10046 emit_insn ((*gen_func.movmemsi) (dest, src,
10047 GEN_INT (move_bytes & 31),
10056 /* Return a string to perform a load_multiple operation.
10057 operands[0] is the vector.
10058 operands[1] is the source address.
10059 operands[2] is the first destination register. */
10062 rs6000_output_load_multiple (rtx operands[3])
10064 /* We have to handle the case where the pseudo used to contain the address
10065 is assigned to one of the output registers. */
10067 int words = XVECLEN (operands[0], 0);
10070 if (XVECLEN (operands[0], 0) == 1)
10071 return "{l|lwz} %2,0(%1)";
10073 for (i = 0; i < words; i++)
10074 if (refers_to_regno_p (REGNO (operands[2]) + i,
10075 REGNO (operands[2]) + i + 1, operands[1], 0))
10079 xop[0] = GEN_INT (4 * (words-1));
10080 xop[1] = operands[1];
10081 xop[2] = operands[2];
10082 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10087 xop[0] = GEN_INT (4 * (words-1));
10088 xop[1] = operands[1];
10089 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10090 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10095 for (j = 0; j < words; j++)
10098 xop[0] = GEN_INT (j * 4);
10099 xop[1] = operands[1];
10100 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10101 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10103 xop[0] = GEN_INT (i * 4);
10104 xop[1] = operands[1];
10105 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10110 return "{lsi|lswi} %2,%1,%N0";
10114 /* A validation routine: say whether CODE, a condition code, and MODE
10115 match. The other alternatives either don't make sense or should
10116 never be generated. */
10119 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10121 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10122 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10123 && GET_MODE_CLASS (mode) == MODE_CC);
10125 /* These don't make sense. */
10126 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10127 || mode != CCUNSmode);
10129 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10130 || mode == CCUNSmode);
10132 gcc_assert (mode == CCFPmode
10133 || (code != ORDERED && code != UNORDERED
10134 && code != UNEQ && code != LTGT
10135 && code != UNGT && code != UNLT
10136 && code != UNGE && code != UNLE));
10138 /* These should never be generated except for
10139 flag_finite_math_only. */
10140 gcc_assert (mode != CCFPmode
10141 || flag_finite_math_only
10142 || (code != LE && code != GE
10143 && code != UNEQ && code != LTGT
10144 && code != UNGT && code != UNLT));
10146 /* These are invalid; the information is not there. */
10147 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10151 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10152 mask required to convert the result of a rotate insn into a shift
10153 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10156 includes_lshift_p (rtx shiftop, rtx andop)
10158 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10160 shift_mask <<= INTVAL (shiftop);
10162 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10165 /* Similar, but for right shift. */
10168 includes_rshift_p (rtx shiftop, rtx andop)
10170 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10172 shift_mask >>= INTVAL (shiftop);
10174 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10177 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10178 to perform a left shift. It must have exactly SHIFTOP least
10179 significant 0's, then one or more 1's, then zero or more 0's. */
10182 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10184 if (GET_CODE (andop) == CONST_INT)
10186 HOST_WIDE_INT c, lsb, shift_mask;
10188 c = INTVAL (andop);
10189 if (c == 0 || c == ~0)
10193 shift_mask <<= INTVAL (shiftop);
10195 /* Find the least significant one bit. */
10198 /* It must coincide with the LSB of the shift mask. */
10199 if (-lsb != shift_mask)
10202 /* Invert to look for the next transition (if any). */
10205 /* Remove the low group of ones (originally low group of zeros). */
10208 /* Again find the lsb, and check we have all 1's above. */
10212 else if (GET_CODE (andop) == CONST_DOUBLE
10213 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10215 HOST_WIDE_INT low, high, lsb;
10216 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10218 low = CONST_DOUBLE_LOW (andop);
10219 if (HOST_BITS_PER_WIDE_INT < 64)
10220 high = CONST_DOUBLE_HIGH (andop);
10222 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10223 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10226 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10228 shift_mask_high = ~0;
10229 if (INTVAL (shiftop) > 32)
10230 shift_mask_high <<= INTVAL (shiftop) - 32;
10232 lsb = high & -high;
10234 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10240 lsb = high & -high;
10241 return high == -lsb;
10244 shift_mask_low = ~0;
10245 shift_mask_low <<= INTVAL (shiftop);
10249 if (-lsb != shift_mask_low)
10252 if (HOST_BITS_PER_WIDE_INT < 64)
10257 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10259 lsb = high & -high;
10260 return high == -lsb;
10264 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10270 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10271 to perform a left shift. It must have SHIFTOP or more least
10272 significant 0's, with the remainder of the word 1's. */
10275 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10277 if (GET_CODE (andop) == CONST_INT)
10279 HOST_WIDE_INT c, lsb, shift_mask;
10282 shift_mask <<= INTVAL (shiftop);
10283 c = INTVAL (andop);
10285 /* Find the least significant one bit. */
10288 /* It must be covered by the shift mask.
10289 This test also rejects c == 0. */
10290 if ((lsb & shift_mask) == 0)
10293 /* Check we have all 1's above the transition, and reject all 1's. */
10294 return c == -lsb && lsb != 1;
10296 else if (GET_CODE (andop) == CONST_DOUBLE
10297 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10299 HOST_WIDE_INT low, lsb, shift_mask_low;
10301 low = CONST_DOUBLE_LOW (andop);
10303 if (HOST_BITS_PER_WIDE_INT < 64)
10305 HOST_WIDE_INT high, shift_mask_high;
10307 high = CONST_DOUBLE_HIGH (andop);
10311 shift_mask_high = ~0;
10312 if (INTVAL (shiftop) > 32)
10313 shift_mask_high <<= INTVAL (shiftop) - 32;
10315 lsb = high & -high;
10317 if ((lsb & shift_mask_high) == 0)
10320 return high == -lsb;
10326 shift_mask_low = ~0;
10327 shift_mask_low <<= INTVAL (shiftop);
10331 if ((lsb & shift_mask_low) == 0)
10334 return low == -lsb && lsb != 1;
10340 /* Return 1 if operands will generate a valid arguments to rlwimi
10341 instruction for insert with right shift in 64-bit mode. The mask may
10342 not start on the first bit or stop on the last bit because wrap-around
10343 effects of instruction do not correspond to semantics of RTL insn. */
10346 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10348 if (INTVAL (startop) > 32
10349 && INTVAL (startop) < 64
10350 && INTVAL (sizeop) > 1
10351 && INTVAL (sizeop) + INTVAL (startop) < 64
10352 && INTVAL (shiftop) > 0
10353 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10354 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10360 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10361 for lfq and stfq insns iff the registers are hard registers. */
10364 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10366 /* We might have been passed a SUBREG. */
10367 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10370 /* We might have been passed non floating point registers. */
10371 if (!FP_REGNO_P (REGNO (reg1))
10372 || !FP_REGNO_P (REGNO (reg2)))
10375 return (REGNO (reg1) == REGNO (reg2) - 1);
10378 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10379 addr1 and addr2 must be in consecutive memory locations
10380 (addr2 == addr1 + 8). */
10383 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10386 unsigned int reg1, reg2;
10387 int offset1, offset2;
10389 /* The mems cannot be volatile. */
10390 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10393 addr1 = XEXP (mem1, 0);
10394 addr2 = XEXP (mem2, 0);
10396 /* Extract an offset (if used) from the first addr. */
10397 if (GET_CODE (addr1) == PLUS)
10399 /* If not a REG, return zero. */
10400 if (GET_CODE (XEXP (addr1, 0)) != REG)
10404 reg1 = REGNO (XEXP (addr1, 0));
10405 /* The offset must be constant! */
10406 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10408 offset1 = INTVAL (XEXP (addr1, 1));
10411 else if (GET_CODE (addr1) != REG)
10415 reg1 = REGNO (addr1);
10416 /* This was a simple (mem (reg)) expression. Offset is 0. */
10420 /* And now for the second addr. */
10421 if (GET_CODE (addr2) == PLUS)
10423 /* If not a REG, return zero. */
10424 if (GET_CODE (XEXP (addr2, 0)) != REG)
10428 reg2 = REGNO (XEXP (addr2, 0));
10429 /* The offset must be constant. */
10430 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10432 offset2 = INTVAL (XEXP (addr2, 1));
10435 else if (GET_CODE (addr2) != REG)
10439 reg2 = REGNO (addr2);
10440 /* This was a simple (mem (reg)) expression. Offset is 0. */
10444 /* Both of these must have the same base register. */
10448 /* The offset for the second addr must be 8 more than the first addr. */
10449 if (offset2 != offset1 + 8)
10452 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10457 /* Return the register class of a scratch register needed to copy IN into
10458 or out of a register in CLASS in MODE. If it can be done directly,
10459 NO_REGS is returned. */
10462 rs6000_secondary_reload_class (enum reg_class class,
10463 enum machine_mode mode ATTRIBUTE_UNUSED,
10468 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10470 && MACHOPIC_INDIRECT
10474 /* We cannot copy a symbolic operand directly into anything
10475 other than BASE_REGS for TARGET_ELF. So indicate that a
10476 register from BASE_REGS is needed as an intermediate
10479 On Darwin, pic addresses require a load from memory, which
10480 needs a base register. */
10481 if (class != BASE_REGS
10482 && (GET_CODE (in) == SYMBOL_REF
10483 || GET_CODE (in) == HIGH
10484 || GET_CODE (in) == LABEL_REF
10485 || GET_CODE (in) == CONST))
10489 if (GET_CODE (in) == REG)
10491 regno = REGNO (in);
10492 if (regno >= FIRST_PSEUDO_REGISTER)
10494 regno = true_regnum (in);
10495 if (regno >= FIRST_PSEUDO_REGISTER)
10499 else if (GET_CODE (in) == SUBREG)
10501 regno = true_regnum (in);
10502 if (regno >= FIRST_PSEUDO_REGISTER)
10508 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10510 if (class == GENERAL_REGS || class == BASE_REGS
10511 || (regno >= 0 && INT_REGNO_P (regno)))
10514 /* Constants, memory, and FP registers can go into FP registers. */
10515 if ((regno == -1 || FP_REGNO_P (regno))
10516 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10519 /* Memory, and AltiVec registers can go into AltiVec registers. */
10520 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10521 && class == ALTIVEC_REGS)
10524 /* We can copy among the CR registers. */
10525 if ((class == CR_REGS || class == CR0_REGS)
10526 && regno >= 0 && CR_REGNO_P (regno))
10529 /* Otherwise, we need GENERAL_REGS. */
10530 return GENERAL_REGS;
10533 /* Given a comparison operation, return the bit number in CCR to test. We
10534 know this is a valid comparison.
10536 SCC_P is 1 if this is for an scc. That means that %D will have been
10537 used instead of %C, so the bits will be in different places.
10539 Return -1 if OP isn't a valid comparison for some reason. */
10542 ccr_bit (rtx op, int scc_p)
10544 enum rtx_code code = GET_CODE (op);
10545 enum machine_mode cc_mode;
10550 if (!COMPARISON_P (op))
10553 reg = XEXP (op, 0);
10555 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10557 cc_mode = GET_MODE (reg);
10558 cc_regnum = REGNO (reg);
10559 base_bit = 4 * (cc_regnum - CR0_REGNO);
10561 validate_condition_mode (code, cc_mode);
10563 /* When generating a sCOND operation, only positive conditions are
10566 || code == EQ || code == GT || code == LT || code == UNORDERED
10567 || code == GTU || code == LTU);
10572 return scc_p ? base_bit + 3 : base_bit + 2;
10574 return base_bit + 2;
10575 case GT: case GTU: case UNLE:
10576 return base_bit + 1;
10577 case LT: case LTU: case UNGE:
10579 case ORDERED: case UNORDERED:
10580 return base_bit + 3;
10583 /* If scc, we will have done a cror to put the bit in the
10584 unordered position. So test that bit. For integer, this is ! LT
10585 unless this is an scc insn. */
10586 return scc_p ? base_bit + 3 : base_bit;
10589 return scc_p ? base_bit + 3 : base_bit + 1;
10592 gcc_unreachable ();
10596 /* Return the GOT register. */
10599 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10601 /* The second flow pass currently (June 1999) can't update
10602 regs_ever_live without disturbing other parts of the compiler, so
10603 update it here to make the prolog/epilogue code happy. */
10604 if (!can_create_pseudo_p ()
10605 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
10606 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
10608 current_function_uses_pic_offset_table = 1;
10610 return pic_offset_table_rtx;
10613 /* Function to init struct machine_function.
10614 This will be called, via a pointer variable,
10615 from push_function_context. */
10617 static struct machine_function *
10618 rs6000_init_machine_status (void)
10620 return ggc_alloc_cleared (sizeof (machine_function));
10623 /* These macros test for integers and extract the low-order bits. */
10625 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10626 && GET_MODE (X) == VOIDmode)
10628 #define INT_LOWPART(X) \
10629 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10632 extract_MB (rtx op)
10635 unsigned long val = INT_LOWPART (op);
10637 /* If the high bit is zero, the value is the first 1 bit we find
10639 if ((val & 0x80000000) == 0)
10641 gcc_assert (val & 0xffffffff);
10644 while (((val <<= 1) & 0x80000000) == 0)
10649 /* If the high bit is set and the low bit is not, or the mask is all
10650 1's, the value is zero. */
10651 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10654 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10657 while (((val >>= 1) & 1) != 0)
10664 extract_ME (rtx op)
10667 unsigned long val = INT_LOWPART (op);
10669 /* If the low bit is zero, the value is the first 1 bit we find from
10671 if ((val & 1) == 0)
10673 gcc_assert (val & 0xffffffff);
10676 while (((val >>= 1) & 1) == 0)
10682 /* If the low bit is set and the high bit is not, or the mask is all
10683 1's, the value is 31. */
10684 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10687 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10690 while (((val <<= 1) & 0x80000000) != 0)
10696 /* Locate some local-dynamic symbol still in use by this function
10697 so that we can print its name in some tls_ld pattern. */
10699 static const char *
10700 rs6000_get_some_local_dynamic_name (void)
10704 if (cfun->machine->some_ld_name)
10705 return cfun->machine->some_ld_name;
10707 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10709 && for_each_rtx (&PATTERN (insn),
10710 rs6000_get_some_local_dynamic_name_1, 0))
10711 return cfun->machine->some_ld_name;
10713 gcc_unreachable ();
10716 /* Helper function for rs6000_get_some_local_dynamic_name. */
10719 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10723 if (GET_CODE (x) == SYMBOL_REF)
10725 const char *str = XSTR (x, 0);
10726 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10728 cfun->machine->some_ld_name = str;
10736 /* Write out a function code label. */
10739 rs6000_output_function_entry (FILE *file, const char *fname)
10741 if (fname[0] != '.')
10743 switch (DEFAULT_ABI)
10746 gcc_unreachable ();
10752 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10761 RS6000_OUTPUT_BASENAME (file, fname);
10763 assemble_name (file, fname);
10766 /* Print an operand. Recognize special options, documented below. */
10769 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10770 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10772 #define SMALL_DATA_RELOC "sda21"
10773 #define SMALL_DATA_REG 0
10777 print_operand (FILE *file, rtx x, int code)
10781 unsigned HOST_WIDE_INT uval;
10786 /* Write out an instruction after the call which may be replaced
10787 with glue code by the loader. This depends on the AIX version. */
10788 asm_fprintf (file, RS6000_CALL_GLUE);
10791 /* %a is output_address. */
10794 /* If X is a constant integer whose low-order 5 bits are zero,
10795 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10796 in the AIX assembler where "sri" with a zero shift count
10797 writes a trash instruction. */
10798 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10805 /* If constant, low-order 16 bits of constant, unsigned.
10806 Otherwise, write normally. */
10808 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10810 print_operand (file, x, 0);
10814 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10815 for 64-bit mask direction. */
10816 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10819 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10823 /* X is a CR register. Print the number of the GT bit of the CR. */
10824 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10825 output_operand_lossage ("invalid %%E value");
10827 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10831 /* Like 'J' but get to the GT bit only. */
10832 gcc_assert (GET_CODE (x) == REG);
10834 /* Bit 1 is GT bit. */
10835 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10837 /* Add one for shift count in rlinm for scc. */
10838 fprintf (file, "%d", i + 1);
10842 /* X is a CR register. Print the number of the EQ bit of the CR */
10843 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10844 output_operand_lossage ("invalid %%E value");
10846 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10850 /* X is a CR register. Print the shift count needed to move it
10851 to the high-order four bits. */
10852 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10853 output_operand_lossage ("invalid %%f value");
10855 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10859 /* Similar, but print the count for the rotate in the opposite
10861 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10862 output_operand_lossage ("invalid %%F value");
10864 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10868 /* X is a constant integer. If it is negative, print "m",
10869 otherwise print "z". This is to make an aze or ame insn. */
10870 if (GET_CODE (x) != CONST_INT)
10871 output_operand_lossage ("invalid %%G value");
10872 else if (INTVAL (x) >= 0)
10879 /* If constant, output low-order five bits. Otherwise, write
10882 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10884 print_operand (file, x, 0);
10888 /* If constant, output low-order six bits. Otherwise, write
10891 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10893 print_operand (file, x, 0);
10897 /* Print `i' if this is a constant, else nothing. */
10903 /* Write the bit number in CCR for jump. */
10904 i = ccr_bit (x, 0);
10906 output_operand_lossage ("invalid %%j code");
10908 fprintf (file, "%d", i);
10912 /* Similar, but add one for shift count in rlinm for scc and pass
10913 scc flag to `ccr_bit'. */
10914 i = ccr_bit (x, 1);
10916 output_operand_lossage ("invalid %%J code");
10918 /* If we want bit 31, write a shift count of zero, not 32. */
10919 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10923 /* X must be a constant. Write the 1's complement of the
10926 output_operand_lossage ("invalid %%k value");
10928 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10932 /* X must be a symbolic constant on ELF. Write an
10933 expression suitable for an 'addi' that adds in the low 16
10934 bits of the MEM. */
10935 if (GET_CODE (x) != CONST)
10937 print_operand_address (file, x);
10938 fputs ("@l", file);
10942 if (GET_CODE (XEXP (x, 0)) != PLUS
10943 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10944 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10945 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10946 output_operand_lossage ("invalid %%K value");
10947 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10948 fputs ("@l", file);
10949 /* For GNU as, there must be a non-alphanumeric character
10950 between 'l' and the number. The '-' is added by
10951 print_operand() already. */
10952 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10954 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10958 /* %l is output_asm_label. */
10961 /* Write second word of DImode or DFmode reference. Works on register
10962 or non-indexed memory only. */
10963 if (GET_CODE (x) == REG)
10964 fputs (reg_names[REGNO (x) + 1], file);
10965 else if (GET_CODE (x) == MEM)
10967 /* Handle possible auto-increment. Since it is pre-increment and
10968 we have already done it, we can just use an offset of word. */
10969 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10970 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10971 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10973 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
10974 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10977 output_address (XEXP (adjust_address_nv (x, SImode,
10981 if (small_data_operand (x, GET_MODE (x)))
10982 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10983 reg_names[SMALL_DATA_REG]);
10988 /* MB value for a mask operand. */
10989 if (! mask_operand (x, SImode))
10990 output_operand_lossage ("invalid %%m value");
10992 fprintf (file, "%d", extract_MB (x));
10996 /* ME value for a mask operand. */
10997 if (! mask_operand (x, SImode))
10998 output_operand_lossage ("invalid %%M value");
11000 fprintf (file, "%d", extract_ME (x));
11003 /* %n outputs the negative of its operand. */
11006 /* Write the number of elements in the vector times 4. */
11007 if (GET_CODE (x) != PARALLEL)
11008 output_operand_lossage ("invalid %%N value");
11010 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11014 /* Similar, but subtract 1 first. */
11015 if (GET_CODE (x) != PARALLEL)
11016 output_operand_lossage ("invalid %%O value");
11018 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11022 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11024 || INT_LOWPART (x) < 0
11025 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11026 output_operand_lossage ("invalid %%p value");
11028 fprintf (file, "%d", i);
11032 /* The operand must be an indirect memory reference. The result
11033 is the register name. */
11034 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11035 || REGNO (XEXP (x, 0)) >= 32)
11036 output_operand_lossage ("invalid %%P value");
11038 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11042 /* This outputs the logical code corresponding to a boolean
11043 expression. The expression may have one or both operands
11044 negated (if one, only the first one). For condition register
11045 logical operations, it will also treat the negated
11046 CR codes as NOTs, but not handle NOTs of them. */
11048 const char *const *t = 0;
11050 enum rtx_code code = GET_CODE (x);
11051 static const char * const tbl[3][3] = {
11052 { "and", "andc", "nor" },
11053 { "or", "orc", "nand" },
11054 { "xor", "eqv", "xor" } };
11058 else if (code == IOR)
11060 else if (code == XOR)
11063 output_operand_lossage ("invalid %%q value");
11065 if (GET_CODE (XEXP (x, 0)) != NOT)
11069 if (GET_CODE (XEXP (x, 1)) == NOT)
11087 /* X is a CR register. Print the mask for `mtcrf'. */
11088 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11089 output_operand_lossage ("invalid %%R value");
11091 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11095 /* Low 5 bits of 32 - value */
11097 output_operand_lossage ("invalid %%s value");
11099 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11103 /* PowerPC64 mask position. All 0's is excluded.
11104 CONST_INT 32-bit mask is considered sign-extended so any
11105 transition must occur within the CONST_INT, not on the boundary. */
11106 if (! mask64_operand (x, DImode))
11107 output_operand_lossage ("invalid %%S value");
11109 uval = INT_LOWPART (x);
11111 if (uval & 1) /* Clear Left */
11113 #if HOST_BITS_PER_WIDE_INT > 64
11114 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11118 else /* Clear Right */
11121 #if HOST_BITS_PER_WIDE_INT > 64
11122 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11128 gcc_assert (i >= 0);
11129 fprintf (file, "%d", i);
11133 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11134 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11136 /* Bit 3 is OV bit. */
11137 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11139 /* If we want bit 31, write a shift count of zero, not 32. */
11140 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11144 /* Print the symbolic name of a branch target register. */
11145 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11146 && REGNO (x) != CTR_REGNO))
11147 output_operand_lossage ("invalid %%T value");
11148 else if (REGNO (x) == LR_REGNO)
11149 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11151 fputs ("ctr", file);
11155 /* High-order 16 bits of constant for use in unsigned operand. */
11157 output_operand_lossage ("invalid %%u value");
11159 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11160 (INT_LOWPART (x) >> 16) & 0xffff);
11164 /* High-order 16 bits of constant for use in signed operand. */
11166 output_operand_lossage ("invalid %%v value");
11168 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11169 (INT_LOWPART (x) >> 16) & 0xffff);
11173 /* Print `u' if this has an auto-increment or auto-decrement. */
11174 if (GET_CODE (x) == MEM
11175 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11176 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11177 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11182 /* Print the trap code for this operand. */
11183 switch (GET_CODE (x))
11186 fputs ("eq", file); /* 4 */
11189 fputs ("ne", file); /* 24 */
11192 fputs ("lt", file); /* 16 */
11195 fputs ("le", file); /* 20 */
11198 fputs ("gt", file); /* 8 */
11201 fputs ("ge", file); /* 12 */
11204 fputs ("llt", file); /* 2 */
11207 fputs ("lle", file); /* 6 */
11210 fputs ("lgt", file); /* 1 */
11213 fputs ("lge", file); /* 5 */
11216 gcc_unreachable ();
11221 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11224 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11225 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11227 print_operand (file, x, 0);
11231 /* MB value for a PowerPC64 rldic operand. */
11232 val = (GET_CODE (x) == CONST_INT
11233 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11238 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11239 if ((val <<= 1) < 0)
11242 #if HOST_BITS_PER_WIDE_INT == 32
11243 if (GET_CODE (x) == CONST_INT && i >= 0)
11244 i += 32; /* zero-extend high-part was all 0's */
11245 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11247 val = CONST_DOUBLE_LOW (x);
11253 for ( ; i < 64; i++)
11254 if ((val <<= 1) < 0)
11259 fprintf (file, "%d", i + 1);
11263 if (GET_CODE (x) == MEM
11264 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11265 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11266 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11271 /* Like 'L', for third word of TImode */
11272 if (GET_CODE (x) == REG)
11273 fputs (reg_names[REGNO (x) + 2], file);
11274 else if (GET_CODE (x) == MEM)
11276 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11277 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11278 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11279 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11280 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11282 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11283 if (small_data_operand (x, GET_MODE (x)))
11284 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11285 reg_names[SMALL_DATA_REG]);
11290 /* X is a SYMBOL_REF. Write out the name preceded by a
11291 period and without any trailing data in brackets. Used for function
11292 names. If we are configured for System V (or the embedded ABI) on
11293 the PowerPC, do not emit the period, since those systems do not use
11294 TOCs and the like. */
11295 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11297 /* Mark the decl as referenced so that cgraph will output the
11299 if (SYMBOL_REF_DECL (x))
11300 mark_decl_referenced (SYMBOL_REF_DECL (x));
11302 /* For macho, check to see if we need a stub. */
11305 const char *name = XSTR (x, 0);
11307 if (MACHOPIC_INDIRECT
11308 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11309 name = machopic_indirection_name (x, /*stub_p=*/true);
11311 assemble_name (file, name);
11313 else if (!DOT_SYMBOLS)
11314 assemble_name (file, XSTR (x, 0));
11316 rs6000_output_function_entry (file, XSTR (x, 0));
11320 /* Like 'L', for last word of TImode. */
11321 if (GET_CODE (x) == REG)
11322 fputs (reg_names[REGNO (x) + 3], file);
11323 else if (GET_CODE (x) == MEM)
11325 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11326 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11327 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11328 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11329 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11331 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11332 if (small_data_operand (x, GET_MODE (x)))
11333 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11334 reg_names[SMALL_DATA_REG]);
11338 /* Print AltiVec or SPE memory operand. */
11343 gcc_assert (GET_CODE (x) == MEM);
11347 /* Ugly hack because %y is overloaded. */
11348 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11349 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11350 || GET_MODE (x) == TFmode
11351 || GET_MODE (x) == TImode))
11353 /* Handle [reg]. */
11354 if (GET_CODE (tmp) == REG)
11356 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11359 /* Handle [reg+UIMM]. */
11360 else if (GET_CODE (tmp) == PLUS &&
11361 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11365 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11367 x = INTVAL (XEXP (tmp, 1));
11368 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11372 /* Fall through. Must be [reg+reg]. */
11375 && GET_CODE (tmp) == AND
11376 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11377 && INTVAL (XEXP (tmp, 1)) == -16)
11378 tmp = XEXP (tmp, 0);
11379 if (GET_CODE (tmp) == REG)
11380 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11383 gcc_assert (GET_CODE (tmp) == PLUS
11384 && REG_P (XEXP (tmp, 0))
11385 && REG_P (XEXP (tmp, 1)));
11387 if (REGNO (XEXP (tmp, 0)) == 0)
11388 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11389 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11391 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11392 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11398 if (GET_CODE (x) == REG)
11399 fprintf (file, "%s", reg_names[REGNO (x)]);
11400 else if (GET_CODE (x) == MEM)
11402 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11403 know the width from the mode. */
11404 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11405 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11406 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11407 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11408 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11409 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11410 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11411 output_address (XEXP (XEXP (x, 0), 1));
11413 output_address (XEXP (x, 0));
11416 output_addr_const (file, x);
11420 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11424 output_operand_lossage ("invalid %%xn code");
11428 /* Print the address of an operand. */
11431 print_operand_address (FILE *file, rtx x)
11433 if (GET_CODE (x) == REG)
11434 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11435 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11436 || GET_CODE (x) == LABEL_REF)
11438 output_addr_const (file, x);
11439 if (small_data_operand (x, GET_MODE (x)))
11440 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11441 reg_names[SMALL_DATA_REG]);
11443 gcc_assert (!TARGET_TOC);
11445 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11447 gcc_assert (REG_P (XEXP (x, 0)));
11448 if (REGNO (XEXP (x, 0)) == 0)
11449 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11450 reg_names[ REGNO (XEXP (x, 0)) ]);
11452 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11453 reg_names[ REGNO (XEXP (x, 1)) ]);
11455 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11456 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11457 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11459 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11460 && CONSTANT_P (XEXP (x, 1)))
11462 output_addr_const (file, XEXP (x, 1));
11463 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11467 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11468 && CONSTANT_P (XEXP (x, 1)))
11470 fprintf (file, "lo16(");
11471 output_addr_const (file, XEXP (x, 1));
11472 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11475 else if (legitimate_constant_pool_address_p (x))
11477 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11479 rtx contains_minus = XEXP (x, 1);
11483 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11484 turn it into (sym) for output_addr_const. */
11485 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11486 contains_minus = XEXP (contains_minus, 0);
11488 minus = XEXP (contains_minus, 0);
11489 symref = XEXP (minus, 0);
11490 XEXP (contains_minus, 0) = symref;
11495 name = XSTR (symref, 0);
11496 newname = alloca (strlen (name) + sizeof ("@toc"));
11497 strcpy (newname, name);
11498 strcat (newname, "@toc");
11499 XSTR (symref, 0) = newname;
11501 output_addr_const (file, XEXP (x, 1));
11503 XSTR (symref, 0) = name;
11504 XEXP (contains_minus, 0) = minus;
11507 output_addr_const (file, XEXP (x, 1));
11509 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11512 gcc_unreachable ();
11515 /* Target hook for assembling integer objects. The PowerPC version has
11516 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11517 is defined. It also needs to handle DI-mode objects on 64-bit
11521 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11523 #ifdef RELOCATABLE_NEEDS_FIXUP
11524 /* Special handling for SI values. */
11525 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11527 static int recurse = 0;
11529 /* For -mrelocatable, we mark all addresses that need to be fixed up
11530 in the .fixup section. */
11531 if (TARGET_RELOCATABLE
11532 && in_section != toc_section
11533 && in_section != text_section
11534 && !unlikely_text_section_p (in_section)
11536 && GET_CODE (x) != CONST_INT
11537 && GET_CODE (x) != CONST_DOUBLE
11543 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11545 ASM_OUTPUT_LABEL (asm_out_file, buf);
11546 fprintf (asm_out_file, "\t.long\t(");
11547 output_addr_const (asm_out_file, x);
11548 fprintf (asm_out_file, ")@fixup\n");
11549 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11550 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11551 fprintf (asm_out_file, "\t.long\t");
11552 assemble_name (asm_out_file, buf);
11553 fprintf (asm_out_file, "\n\t.previous\n");
11557 /* Remove initial .'s to turn a -mcall-aixdesc function
11558 address into the address of the descriptor, not the function
11560 else if (GET_CODE (x) == SYMBOL_REF
11561 && XSTR (x, 0)[0] == '.'
11562 && DEFAULT_ABI == ABI_AIX)
11564 const char *name = XSTR (x, 0);
11565 while (*name == '.')
11568 fprintf (asm_out_file, "\t.long\t%s\n", name);
11572 #endif /* RELOCATABLE_NEEDS_FIXUP */
11573 return default_assemble_integer (x, size, aligned_p);
11576 #ifdef HAVE_GAS_HIDDEN
11577 /* Emit an assembler directive to set symbol visibility for DECL to
11578 VISIBILITY_TYPE. */
11581 rs6000_assemble_visibility (tree decl, int vis)
11583 /* Functions need to have their entry point symbol visibility set as
11584 well as their descriptor symbol visibility. */
11585 if (DEFAULT_ABI == ABI_AIX
11587 && TREE_CODE (decl) == FUNCTION_DECL)
11589 static const char * const visibility_types[] = {
11590 NULL, "internal", "hidden", "protected"
11593 const char *name, *type;
11595 name = ((* targetm.strip_name_encoding)
11596 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11597 type = visibility_types[vis];
11599 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11600 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11603 default_assemble_visibility (decl, vis);
11608 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11610 /* Reversal of FP compares takes care -- an ordered compare
11611 becomes an unordered compare and vice versa. */
11612 if (mode == CCFPmode
11613 && (!flag_finite_math_only
11614 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11615 || code == UNEQ || code == LTGT))
11616 return reverse_condition_maybe_unordered (code);
11618 return reverse_condition (code);
11621 /* Generate a compare for CODE. Return a brand-new rtx that
11622 represents the result of the compare. */
11625 rs6000_generate_compare (enum rtx_code code)
11627 enum machine_mode comp_mode;
11628 rtx compare_result;
11630 if (rs6000_compare_fp_p)
11631 comp_mode = CCFPmode;
11632 else if (code == GTU || code == LTU
11633 || code == GEU || code == LEU)
11634 comp_mode = CCUNSmode;
11635 else if ((code == EQ || code == NE)
11636 && GET_CODE (rs6000_compare_op0) == SUBREG
11637 && GET_CODE (rs6000_compare_op1) == SUBREG
11638 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11639 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11640 /* These are unsigned values, perhaps there will be a later
11641 ordering compare that can be shared with this one.
11642 Unfortunately we cannot detect the signedness of the operands
11643 for non-subregs. */
11644 comp_mode = CCUNSmode;
11646 comp_mode = CCmode;
11648 /* First, the compare. */
11649 compare_result = gen_reg_rtx (comp_mode);
11651 /* E500 FP compare instructions on the GPRs. Yuck! */
11652 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11653 && rs6000_compare_fp_p)
11655 rtx cmp, or_result, compare_result2;
11656 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11658 if (op_mode == VOIDmode)
11659 op_mode = GET_MODE (rs6000_compare_op1);
11661 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11662 This explains the following mess. */
11666 case EQ: case UNEQ: case NE: case LTGT:
11670 cmp = flag_unsafe_math_optimizations
11671 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11672 rs6000_compare_op1)
11673 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11674 rs6000_compare_op1);
11678 cmp = flag_unsafe_math_optimizations
11679 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11680 rs6000_compare_op1)
11681 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11682 rs6000_compare_op1);
11686 cmp = flag_unsafe_math_optimizations
11687 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11688 rs6000_compare_op1)
11689 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11690 rs6000_compare_op1);
11694 gcc_unreachable ();
11698 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11702 cmp = flag_unsafe_math_optimizations
11703 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11704 rs6000_compare_op1)
11705 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11706 rs6000_compare_op1);
11710 cmp = flag_unsafe_math_optimizations
11711 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11712 rs6000_compare_op1)
11713 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11714 rs6000_compare_op1);
11718 cmp = flag_unsafe_math_optimizations
11719 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11720 rs6000_compare_op1)
11721 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11722 rs6000_compare_op1);
11726 gcc_unreachable ();
11730 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11734 cmp = flag_unsafe_math_optimizations
11735 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11736 rs6000_compare_op1)
11737 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11738 rs6000_compare_op1);
11742 cmp = flag_unsafe_math_optimizations
11743 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11744 rs6000_compare_op1)
11745 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11746 rs6000_compare_op1);
11750 cmp = flag_unsafe_math_optimizations
11751 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11752 rs6000_compare_op1)
11753 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11754 rs6000_compare_op1);
11758 gcc_unreachable ();
11762 gcc_unreachable ();
11765 /* Synthesize LE and GE from LT/GT || EQ. */
11766 if (code == LE || code == GE || code == LEU || code == GEU)
11772 case LE: code = LT; break;
11773 case GE: code = GT; break;
11774 case LEU: code = LT; break;
11775 case GEU: code = GT; break;
11776 default: gcc_unreachable ();
11779 compare_result2 = gen_reg_rtx (CCFPmode);
11785 cmp = flag_unsafe_math_optimizations
11786 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11787 rs6000_compare_op1)
11788 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11789 rs6000_compare_op1);
11793 cmp = flag_unsafe_math_optimizations
11794 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11795 rs6000_compare_op1)
11796 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11797 rs6000_compare_op1);
11801 cmp = flag_unsafe_math_optimizations
11802 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11803 rs6000_compare_op1)
11804 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11805 rs6000_compare_op1);
11809 gcc_unreachable ();
11813 /* OR them together. */
11814 or_result = gen_reg_rtx (CCFPmode);
11815 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11817 compare_result = or_result;
11822 if (code == NE || code == LTGT)
11832 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11833 CLOBBERs to match cmptf_internal2 pattern. */
11834 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11835 && GET_MODE (rs6000_compare_op0) == TFmode
11836 && !TARGET_IEEEQUAD
11837 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11838 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11840 gen_rtx_SET (VOIDmode,
11842 gen_rtx_COMPARE (comp_mode,
11843 rs6000_compare_op0,
11844 rs6000_compare_op1)),
11845 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11846 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11847 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11848 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11849 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11850 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11851 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11852 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11853 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11854 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11856 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11857 comp_mode = CCEQmode;
11858 compare_result = gen_reg_rtx (CCEQmode);
11860 emit_insn (gen_stack_protect_testdi (compare_result,
11861 rs6000_compare_op0, op1));
11863 emit_insn (gen_stack_protect_testsi (compare_result,
11864 rs6000_compare_op0, op1));
11867 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11868 gen_rtx_COMPARE (comp_mode,
11869 rs6000_compare_op0,
11870 rs6000_compare_op1)));
11873 /* Some kinds of FP comparisons need an OR operation;
11874 under flag_finite_math_only we don't bother. */
11875 if (rs6000_compare_fp_p
11876 && !flag_finite_math_only
11877 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11878 && (code == LE || code == GE
11879 || code == UNEQ || code == LTGT
11880 || code == UNGT || code == UNLT))
11882 enum rtx_code or1, or2;
11883 rtx or1_rtx, or2_rtx, compare2_rtx;
11884 rtx or_result = gen_reg_rtx (CCEQmode);
11888 case LE: or1 = LT; or2 = EQ; break;
11889 case GE: or1 = GT; or2 = EQ; break;
11890 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11891 case LTGT: or1 = LT; or2 = GT; break;
11892 case UNGT: or1 = UNORDERED; or2 = GT; break;
11893 case UNLT: or1 = UNORDERED; or2 = LT; break;
11894 default: gcc_unreachable ();
11896 validate_condition_mode (or1, comp_mode);
11897 validate_condition_mode (or2, comp_mode);
11898 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11899 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11900 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11901 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11903 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11905 compare_result = or_result;
11909 validate_condition_mode (code, GET_MODE (compare_result));
11911 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11915 /* Emit the RTL for an sCOND pattern. */
11918 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11921 enum machine_mode op_mode;
11922 enum rtx_code cond_code;
11924 condition_rtx = rs6000_generate_compare (code);
11925 cond_code = GET_CODE (condition_rtx);
11927 if (rs6000_compare_fp_p
11928 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11932 PUT_MODE (condition_rtx, SImode);
11933 t = XEXP (condition_rtx, 0);
11935 gcc_assert (cond_code == NE || cond_code == EQ);
11937 if (cond_code == NE)
11938 emit_insn (gen_e500_flip_gt_bit (t, t));
11940 emit_insn (gen_move_from_CR_gt_bit (result, t));
11944 if (cond_code == NE
11945 || cond_code == GE || cond_code == LE
11946 || cond_code == GEU || cond_code == LEU
11947 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11949 rtx not_result = gen_reg_rtx (CCEQmode);
11950 rtx not_op, rev_cond_rtx;
11951 enum machine_mode cc_mode;
11953 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11955 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11956 SImode, XEXP (condition_rtx, 0), const0_rtx);
11957 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11958 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11959 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11962 op_mode = GET_MODE (rs6000_compare_op0);
11963 if (op_mode == VOIDmode)
11964 op_mode = GET_MODE (rs6000_compare_op1);
11966 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11968 PUT_MODE (condition_rtx, DImode);
11969 convert_move (result, condition_rtx, 0);
11973 PUT_MODE (condition_rtx, SImode);
11974 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11978 /* Emit a branch of kind CODE to location LOC. */
11981 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11983 rtx condition_rtx, loc_ref;
11985 condition_rtx = rs6000_generate_compare (code);
11986 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11987 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11988 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11989 loc_ref, pc_rtx)));
11992 /* Return the string to output a conditional branch to LABEL, which is
11993 the operand number of the label, or -1 if the branch is really a
11994 conditional return.
11996 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11997 condition code register and its mode specifies what kind of
11998 comparison we made.
12000 REVERSED is nonzero if we should reverse the sense of the comparison.
12002 INSN is the insn. */
12005 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12007 static char string[64];
12008 enum rtx_code code = GET_CODE (op);
12009 rtx cc_reg = XEXP (op, 0);
12010 enum machine_mode mode = GET_MODE (cc_reg);
12011 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12012 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12013 int really_reversed = reversed ^ need_longbranch;
12019 validate_condition_mode (code, mode);
12021 /* Work out which way this really branches. We could use
12022 reverse_condition_maybe_unordered here always but this
12023 makes the resulting assembler clearer. */
12024 if (really_reversed)
12026 /* Reversal of FP compares takes care -- an ordered compare
12027 becomes an unordered compare and vice versa. */
12028 if (mode == CCFPmode)
12029 code = reverse_condition_maybe_unordered (code);
12031 code = reverse_condition (code);
12034 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12036 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12041 /* Opposite of GT. */
12050 gcc_unreachable ();
12056 /* Not all of these are actually distinct opcodes, but
12057 we distinguish them for clarity of the resulting assembler. */
12058 case NE: case LTGT:
12059 ccode = "ne"; break;
12060 case EQ: case UNEQ:
12061 ccode = "eq"; break;
12063 ccode = "ge"; break;
12064 case GT: case GTU: case UNGT:
12065 ccode = "gt"; break;
12067 ccode = "le"; break;
12068 case LT: case LTU: case UNLT:
12069 ccode = "lt"; break;
12070 case UNORDERED: ccode = "un"; break;
12071 case ORDERED: ccode = "nu"; break;
12072 case UNGE: ccode = "nl"; break;
12073 case UNLE: ccode = "ng"; break;
12075 gcc_unreachable ();
12078 /* Maybe we have a guess as to how likely the branch is.
12079 The old mnemonics don't have a way to specify this information. */
12081 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12082 if (note != NULL_RTX)
12084 /* PROB is the difference from 50%. */
12085 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12087 /* Only hint for highly probable/improbable branches on newer
12088 cpus as static prediction overrides processor dynamic
12089 prediction. For older cpus we may as well always hint, but
12090 assume not taken for branches that are very close to 50% as a
12091 mispredicted taken branch is more expensive than a
12092 mispredicted not-taken branch. */
12093 if (rs6000_always_hint
12094 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12095 && br_prob_note_reliable_p (note)))
12097 if (abs (prob) > REG_BR_PROB_BASE / 20
12098 && ((prob > 0) ^ need_longbranch))
12106 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12108 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12110 /* We need to escape any '%' characters in the reg_names string.
12111 Assume they'd only be the first character.... */
12112 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12114 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12118 /* If the branch distance was too far, we may have to use an
12119 unconditional branch to go the distance. */
12120 if (need_longbranch)
12121 s += sprintf (s, ",$+8\n\tb %s", label);
12123 s += sprintf (s, ",%s", label);
12129 /* Return the string to flip the GT bit on a CR. */
12131 output_e500_flip_gt_bit (rtx dst, rtx src)
12133 static char string[64];
12136 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12137 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12140 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12141 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12143 sprintf (string, "crnot %d,%d", a, b);
12147 /* Return insn index for the vector compare instruction for given CODE,
12148 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12152 get_vec_cmp_insn (enum rtx_code code,
12153 enum machine_mode dest_mode,
12154 enum machine_mode op_mode)
12156 if (!TARGET_ALTIVEC)
12157 return INSN_NOT_AVAILABLE;
12162 if (dest_mode == V16QImode && op_mode == V16QImode)
12163 return UNSPEC_VCMPEQUB;
12164 if (dest_mode == V8HImode && op_mode == V8HImode)
12165 return UNSPEC_VCMPEQUH;
12166 if (dest_mode == V4SImode && op_mode == V4SImode)
12167 return UNSPEC_VCMPEQUW;
12168 if (dest_mode == V4SImode && op_mode == V4SFmode)
12169 return UNSPEC_VCMPEQFP;
12172 if (dest_mode == V4SImode && op_mode == V4SFmode)
12173 return UNSPEC_VCMPGEFP;
12175 if (dest_mode == V16QImode && op_mode == V16QImode)
12176 return UNSPEC_VCMPGTSB;
12177 if (dest_mode == V8HImode && op_mode == V8HImode)
12178 return UNSPEC_VCMPGTSH;
12179 if (dest_mode == V4SImode && op_mode == V4SImode)
12180 return UNSPEC_VCMPGTSW;
12181 if (dest_mode == V4SImode && op_mode == V4SFmode)
12182 return UNSPEC_VCMPGTFP;
12185 if (dest_mode == V16QImode && op_mode == V16QImode)
12186 return UNSPEC_VCMPGTUB;
12187 if (dest_mode == V8HImode && op_mode == V8HImode)
12188 return UNSPEC_VCMPGTUH;
12189 if (dest_mode == V4SImode && op_mode == V4SImode)
12190 return UNSPEC_VCMPGTUW;
12195 return INSN_NOT_AVAILABLE;
12198 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12199 DMODE is expected destination mode. This is a recursive function. */
12202 rs6000_emit_vector_compare (enum rtx_code rcode,
12204 enum machine_mode dmode)
12208 enum machine_mode dest_mode;
12209 enum machine_mode op_mode = GET_MODE (op1);
12211 gcc_assert (TARGET_ALTIVEC);
12212 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12214 /* Floating point vector compare instructions uses destination V4SImode.
12215 Move destination to appropriate mode later. */
12216 if (dmode == V4SFmode)
12217 dest_mode = V4SImode;
12221 mask = gen_reg_rtx (dest_mode);
12222 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12224 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12226 bool swap_operands = false;
12227 bool try_again = false;
12232 swap_operands = true;
12237 swap_operands = true;
12245 /* Invert condition and try again.
12246 e.g., A != B becomes ~(A==B). */
12248 enum rtx_code rev_code;
12249 enum insn_code nor_code;
12252 rev_code = reverse_condition_maybe_unordered (rcode);
12253 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12256 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
12257 gcc_assert (nor_code != CODE_FOR_nothing);
12258 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12260 if (dmode != dest_mode)
12262 rtx temp = gen_reg_rtx (dest_mode);
12263 convert_move (temp, mask, 0);
12273 /* Try GT/GTU/LT/LTU OR EQ */
12276 enum insn_code ior_code;
12277 enum rtx_code new_code;
12298 gcc_unreachable ();
12301 c_rtx = rs6000_emit_vector_compare (new_code,
12302 op0, op1, dest_mode);
12303 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12306 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
12307 gcc_assert (ior_code != CODE_FOR_nothing);
12308 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12309 if (dmode != dest_mode)
12311 rtx temp = gen_reg_rtx (dest_mode);
12312 convert_move (temp, mask, 0);
12319 gcc_unreachable ();
12324 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12325 /* You only get two chances. */
12326 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12338 emit_insn (gen_rtx_SET (VOIDmode, mask,
12339 gen_rtx_UNSPEC (dest_mode,
12340 gen_rtvec (2, op0, op1),
12342 if (dmode != dest_mode)
12344 rtx temp = gen_reg_rtx (dest_mode);
12345 convert_move (temp, mask, 0);
12351 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12352 valid insn doesn exist for given mode. */
12355 get_vsel_insn (enum machine_mode mode)
12360 return UNSPEC_VSEL4SI;
12363 return UNSPEC_VSEL4SF;
12366 return UNSPEC_VSEL8HI;
12369 return UNSPEC_VSEL16QI;
12372 return INSN_NOT_AVAILABLE;
12375 return INSN_NOT_AVAILABLE;
12378 /* Emit vector select insn where DEST is destination using
12379 operands OP1, OP2 and MASK. */
12382 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12385 enum machine_mode dest_mode = GET_MODE (dest);
12386 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12388 temp = gen_reg_rtx (dest_mode);
12390 /* For each vector element, select op1 when mask is 1 otherwise
12392 t = gen_rtx_SET (VOIDmode, temp,
12393 gen_rtx_UNSPEC (dest_mode,
12394 gen_rtvec (3, op2, op1, mask),
12397 emit_move_insn (dest, temp);
12401 /* Emit vector conditional expression.
12402 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12403 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12406 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12407 rtx cond, rtx cc_op0, rtx cc_op1)
12409 enum machine_mode dest_mode = GET_MODE (dest);
12410 enum rtx_code rcode = GET_CODE (cond);
12413 if (!TARGET_ALTIVEC)
12416 /* Get the vector mask for the given relational operations. */
12417 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12419 rs6000_emit_vector_select (dest, op1, op2, mask);
12424 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12425 operands of the last comparison is nonzero/true, FALSE_COND if it
12426 is zero/false. Return 0 if the hardware has no such operation. */
12429 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12431 enum rtx_code code = GET_CODE (op);
12432 rtx op0 = rs6000_compare_op0;
12433 rtx op1 = rs6000_compare_op1;
12434 REAL_VALUE_TYPE c1;
12435 enum machine_mode compare_mode = GET_MODE (op0);
12436 enum machine_mode result_mode = GET_MODE (dest);
12438 bool is_against_zero;
12440 /* These modes should always match. */
12441 if (GET_MODE (op1) != compare_mode
12442 /* In the isel case however, we can use a compare immediate, so
12443 op1 may be a small constant. */
12444 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12446 if (GET_MODE (true_cond) != result_mode)
12448 if (GET_MODE (false_cond) != result_mode)
12451 /* First, work out if the hardware can do this at all, or
12452 if it's too slow.... */
12453 if (! rs6000_compare_fp_p)
12456 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12459 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12460 && SCALAR_FLOAT_MODE_P (compare_mode))
12463 is_against_zero = op1 == CONST0_RTX (compare_mode);
12465 /* A floating-point subtract might overflow, underflow, or produce
12466 an inexact result, thus changing the floating-point flags, so it
12467 can't be generated if we care about that. It's safe if one side
12468 of the construct is zero, since then no subtract will be
12470 if (SCALAR_FLOAT_MODE_P (compare_mode)
12471 && flag_trapping_math && ! is_against_zero)
12474 /* Eliminate half of the comparisons by switching operands, this
12475 makes the remaining code simpler. */
12476 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12477 || code == LTGT || code == LT || code == UNLE)
12479 code = reverse_condition_maybe_unordered (code);
12481 true_cond = false_cond;
12485 /* UNEQ and LTGT take four instructions for a comparison with zero,
12486 it'll probably be faster to use a branch here too. */
12487 if (code == UNEQ && HONOR_NANS (compare_mode))
12490 if (GET_CODE (op1) == CONST_DOUBLE)
12491 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12493 /* We're going to try to implement comparisons by performing
12494 a subtract, then comparing against zero. Unfortunately,
12495 Inf - Inf is NaN which is not zero, and so if we don't
12496 know that the operand is finite and the comparison
12497 would treat EQ different to UNORDERED, we can't do it. */
12498 if (HONOR_INFINITIES (compare_mode)
12499 && code != GT && code != UNGE
12500 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12501 /* Constructs of the form (a OP b ? a : b) are safe. */
12502 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12503 || (! rtx_equal_p (op0, true_cond)
12504 && ! rtx_equal_p (op1, true_cond))))
12507 /* At this point we know we can use fsel. */
12509 /* Reduce the comparison to a comparison against zero. */
12510 if (! is_against_zero)
12512 temp = gen_reg_rtx (compare_mode);
12513 emit_insn (gen_rtx_SET (VOIDmode, temp,
12514 gen_rtx_MINUS (compare_mode, op0, op1)));
12516 op1 = CONST0_RTX (compare_mode);
12519 /* If we don't care about NaNs we can reduce some of the comparisons
12520 down to faster ones. */
12521 if (! HONOR_NANS (compare_mode))
12527 true_cond = false_cond;
12540 /* Now, reduce everything down to a GE. */
12547 temp = gen_reg_rtx (compare_mode);
12548 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12553 temp = gen_reg_rtx (compare_mode);
12554 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12559 temp = gen_reg_rtx (compare_mode);
12560 emit_insn (gen_rtx_SET (VOIDmode, temp,
12561 gen_rtx_NEG (compare_mode,
12562 gen_rtx_ABS (compare_mode, op0))));
12567 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12568 temp = gen_reg_rtx (result_mode);
12569 emit_insn (gen_rtx_SET (VOIDmode, temp,
12570 gen_rtx_IF_THEN_ELSE (result_mode,
12571 gen_rtx_GE (VOIDmode,
12573 true_cond, false_cond)));
12574 false_cond = true_cond;
12577 temp = gen_reg_rtx (compare_mode);
12578 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12583 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12584 temp = gen_reg_rtx (result_mode);
12585 emit_insn (gen_rtx_SET (VOIDmode, temp,
12586 gen_rtx_IF_THEN_ELSE (result_mode,
12587 gen_rtx_GE (VOIDmode,
12589 true_cond, false_cond)));
12590 true_cond = false_cond;
12593 temp = gen_reg_rtx (compare_mode);
12594 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12599 gcc_unreachable ();
12602 emit_insn (gen_rtx_SET (VOIDmode, dest,
12603 gen_rtx_IF_THEN_ELSE (result_mode,
12604 gen_rtx_GE (VOIDmode,
12606 true_cond, false_cond)));
12610 /* Same as above, but for ints (isel). */
12613 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12615 rtx condition_rtx, cr;
12617 /* All isel implementations thus far are 32-bits. */
12618 if (GET_MODE (rs6000_compare_op0) != SImode)
12621 /* We still have to do the compare, because isel doesn't do a
12622 compare, it just looks at the CRx bits set by a previous compare
12624 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12625 cr = XEXP (condition_rtx, 0);
12627 if (GET_MODE (cr) == CCmode)
12628 emit_insn (gen_isel_signed (dest, condition_rtx,
12629 true_cond, false_cond, cr));
12631 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12632 true_cond, false_cond, cr));
12638 output_isel (rtx *operands)
12640 enum rtx_code code;
12642 code = GET_CODE (operands[1]);
12643 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12645 PUT_CODE (operands[1], reverse_condition (code));
12646 return "isel %0,%3,%2,%j1";
12649 return "isel %0,%2,%3,%j1";
12653 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12655 enum machine_mode mode = GET_MODE (op0);
12659 if (code == SMAX || code == SMIN)
12664 if (code == SMAX || code == UMAX)
12665 target = emit_conditional_move (dest, c, op0, op1, mode,
12666 op0, op1, mode, 0);
12668 target = emit_conditional_move (dest, c, op0, op1, mode,
12669 op1, op0, mode, 0);
12670 gcc_assert (target);
12671 if (target != dest)
12672 emit_move_insn (dest, target);
12675 /* Emit instructions to perform a load-reserved/store-conditional operation.
12676 The operation performed is an atomic
12677 (set M (CODE:MODE M OP))
12678 If not NULL, BEFORE is atomically set to M before the operation, and
12679 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12680 If SYNC_P then a memory barrier is emitted before the operation.
12681 Either OP or M may be wrapped in a NOT operation. */
12684 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12685 rtx m, rtx op, rtx before_param, rtx after_param,
12688 enum machine_mode used_mode;
12689 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12692 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12693 rtx shift = NULL_RTX;
12696 emit_insn (gen_memory_barrier ());
12698 if (GET_CODE (m) == NOT)
12699 used_m = XEXP (m, 0);
12703 /* If this is smaller than SImode, we'll have to use SImode with
12705 if (mode == QImode || mode == HImode)
12709 if (MEM_ALIGN (used_m) >= 32)
12712 if (BYTES_BIG_ENDIAN)
12713 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12715 shift = GEN_INT (ishift);
12719 rtx addrSI, aligned_addr;
12720 int shift_mask = mode == QImode ? 0x18 : 0x10;
12722 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12723 XEXP (used_m, 0)));
12724 shift = gen_reg_rtx (SImode);
12726 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12727 GEN_INT (shift_mask)));
12728 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12730 aligned_addr = expand_binop (Pmode, and_optab,
12732 GEN_INT (-4), NULL_RTX,
12733 1, OPTAB_LIB_WIDEN);
12734 used_m = change_address (used_m, SImode, aligned_addr);
12735 set_mem_align (used_m, 32);
12736 /* It's safe to keep the old alias set of USED_M, because
12737 the operation is atomic and only affects the original
12739 if (GET_CODE (m) == NOT)
12740 m = gen_rtx_NOT (SImode, used_m);
12745 if (GET_CODE (op) == NOT)
12747 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12748 oldop = gen_rtx_NOT (SImode, oldop);
12751 oldop = lowpart_subreg (SImode, op, mode);
12757 newop = expand_binop (SImode, and_optab,
12758 oldop, GEN_INT (imask), NULL_RTX,
12759 1, OPTAB_LIB_WIDEN);
12760 emit_insn (gen_ashlsi3 (newop, newop, shift));
12764 newop = expand_binop (SImode, ior_optab,
12765 oldop, GEN_INT (~imask), NULL_RTX,
12766 1, OPTAB_LIB_WIDEN);
12767 emit_insn (gen_rotlsi3 (newop, newop, shift));
12775 newop = expand_binop (SImode, and_optab,
12776 oldop, GEN_INT (imask), NULL_RTX,
12777 1, OPTAB_LIB_WIDEN);
12778 emit_insn (gen_ashlsi3 (newop, newop, shift));
12780 mask = gen_reg_rtx (SImode);
12781 emit_move_insn (mask, GEN_INT (imask));
12782 emit_insn (gen_ashlsi3 (mask, mask, shift));
12785 newop = gen_rtx_PLUS (SImode, m, newop);
12787 newop = gen_rtx_MINUS (SImode, m, newop);
12788 newop = gen_rtx_AND (SImode, newop, mask);
12789 newop = gen_rtx_IOR (SImode, newop,
12790 gen_rtx_AND (SImode,
12791 gen_rtx_NOT (SImode, mask),
12797 gcc_unreachable ();
12800 if (GET_CODE (m) == NOT)
12804 mask = gen_reg_rtx (SImode);
12805 emit_move_insn (mask, GEN_INT (imask));
12806 emit_insn (gen_ashlsi3 (mask, mask, shift));
12808 xorm = gen_rtx_XOR (SImode, used_m, mask);
12809 /* Depending on the value of 'op', the XOR or the operation might
12810 be able to be simplified away. */
12811 newop = simplify_gen_binary (code, SImode, xorm, newop);
12814 used_mode = SImode;
12815 before = gen_reg_rtx (used_mode);
12816 after = gen_reg_rtx (used_mode);
12821 before = before_param;
12822 after = after_param;
12824 if (before == NULL_RTX)
12825 before = gen_reg_rtx (used_mode);
12826 if (after == NULL_RTX)
12827 after = gen_reg_rtx (used_mode);
12830 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12831 && used_mode != mode)
12832 the_op = op; /* Computed above. */
12833 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12834 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12836 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12838 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12839 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12840 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12841 gen_rtx_UNSPEC (used_mode,
12842 gen_rtvec (1, the_op),
12844 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12846 if ((code == PLUS || code == MINUS) && used_mode != mode)
12847 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12848 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12850 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12851 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12853 /* Shift and mask the return values properly. */
12854 if (used_mode != mode && before_param)
12856 emit_insn (gen_lshrsi3 (before, before, shift));
12857 convert_move (before_param, before, 1);
12860 if (used_mode != mode && after_param)
12862 emit_insn (gen_lshrsi3 (after, after, shift));
12863 convert_move (after_param, after, 1);
12866 /* The previous sequence will end with a branch that's dependent on
12867 the conditional store, so placing an isync will ensure that no
12868 other instructions (especially, no load or store instructions)
12869 can start before the atomic operation completes. */
12871 emit_insn (gen_isync ());
12874 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12875 COND is true. Mark the jump as unlikely to be taken. */
12878 emit_unlikely_jump (rtx cond, rtx label)
12880 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12883 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12884 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12885 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12888 /* A subroutine of the atomic operation splitters. Emit a load-locked
12889 instruction in MODE. */
12892 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12894 rtx (*fn) (rtx, rtx) = NULL;
12895 if (mode == SImode)
12896 fn = gen_load_locked_si;
12897 else if (mode == DImode)
12898 fn = gen_load_locked_di;
12899 emit_insn (fn (reg, mem));
12902 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12903 instruction in MODE. */
12906 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12908 rtx (*fn) (rtx, rtx, rtx) = NULL;
12909 if (mode == SImode)
12910 fn = gen_store_conditional_si;
12911 else if (mode == DImode)
12912 fn = gen_store_conditional_di;
12914 /* Emit sync before stwcx. to address PPC405 Erratum. */
12915 if (PPC405_ERRATUM77)
12916 emit_insn (gen_memory_barrier ());
12918 emit_insn (fn (res, mem, val));
12921 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12922 to perform. MEM is the memory on which to operate. VAL is the second
12923 operand of the binary operator. BEFORE and AFTER are optional locations to
12924 return the value of MEM either before of after the operation. SCRATCH is
12925 a scratch register. */
12928 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12929 rtx before, rtx after, rtx scratch)
12931 enum machine_mode mode = GET_MODE (mem);
12932 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12934 emit_insn (gen_memory_barrier ());
12936 label = gen_label_rtx ();
12937 emit_label (label);
12938 label = gen_rtx_LABEL_REF (VOIDmode, label);
12940 if (before == NULL_RTX)
12942 emit_load_locked (mode, before, mem);
12945 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12946 else if (code == AND)
12947 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12949 x = gen_rtx_fmt_ee (code, mode, before, val);
12951 if (after != NULL_RTX)
12952 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12953 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12955 emit_store_conditional (mode, cond, mem, scratch);
12957 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12958 emit_unlikely_jump (x, label);
12960 emit_insn (gen_isync ());
12963 /* Expand an atomic compare and swap operation. MEM is the memory on which
12964 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12965 value to be stored. SCRATCH is a scratch GPR. */
12968 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12971 enum machine_mode mode = GET_MODE (mem);
12972 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12974 emit_insn (gen_memory_barrier ());
12976 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12977 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12978 emit_label (XEXP (label1, 0));
12980 emit_load_locked (mode, retval, mem);
12982 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12983 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12985 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12986 emit_unlikely_jump (x, label2);
12988 emit_move_insn (scratch, newval);
12989 emit_store_conditional (mode, cond, mem, scratch);
12991 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12992 emit_unlikely_jump (x, label1);
12994 emit_insn (gen_isync ());
12995 emit_label (XEXP (label2, 0));
12998 /* Expand an atomic test and set operation. MEM is the memory on which
12999 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13002 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13004 enum machine_mode mode = GET_MODE (mem);
13005 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13007 emit_insn (gen_memory_barrier ());
13009 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13010 emit_label (XEXP (label, 0));
13012 emit_load_locked (mode, retval, mem);
13013 emit_move_insn (scratch, val);
13014 emit_store_conditional (mode, cond, mem, scratch);
13016 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13017 emit_unlikely_jump (x, label);
13019 emit_insn (gen_isync ());
13023 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13025 enum machine_mode mode = GET_MODE (mem);
13026 rtx addrSI, align, wdst, shift, mask;
13027 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13028 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13030 /* Shift amount for subword relative to aligned word. */
13031 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13032 shift = gen_reg_rtx (SImode);
13033 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13034 GEN_INT (shift_mask)));
13035 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13037 /* Shift and mask old value into position within word. */
13038 oldval = convert_modes (SImode, mode, oldval, 1);
13039 oldval = expand_binop (SImode, and_optab,
13040 oldval, GEN_INT (imask), NULL_RTX,
13041 1, OPTAB_LIB_WIDEN);
13042 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13044 /* Shift and mask new value into position within word. */
13045 newval = convert_modes (SImode, mode, newval, 1);
13046 newval = expand_binop (SImode, and_optab,
13047 newval, GEN_INT (imask), NULL_RTX,
13048 1, OPTAB_LIB_WIDEN);
13049 emit_insn (gen_ashlsi3 (newval, newval, shift));
13051 /* Mask for insertion. */
13052 mask = gen_reg_rtx (SImode);
13053 emit_move_insn (mask, GEN_INT (imask));
13054 emit_insn (gen_ashlsi3 (mask, mask, shift));
13056 /* Address of aligned word containing subword. */
13057 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13058 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13059 mem = change_address (mem, SImode, align);
13060 set_mem_align (mem, 32);
13061 MEM_VOLATILE_P (mem) = 1;
13063 wdst = gen_reg_rtx (SImode);
13064 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13065 oldval, newval, mem));
13067 emit_move_insn (dst, gen_lowpart (mode, wdst));
13071 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13072 rtx oldval, rtx newval, rtx mem,
13075 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13077 emit_insn (gen_memory_barrier ());
13078 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13079 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13080 emit_label (XEXP (label1, 0));
13082 emit_load_locked (SImode, scratch, mem);
13084 /* Mask subword within loaded value for comparison with oldval.
13085 Use UNSPEC_AND to avoid clobber.*/
13086 emit_insn (gen_rtx_SET (SImode, dest,
13087 gen_rtx_UNSPEC (SImode,
13088 gen_rtvec (2, scratch, mask),
13091 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13092 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13094 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13095 emit_unlikely_jump (x, label2);
13097 /* Clear subword within loaded value for insertion of new value. */
13098 emit_insn (gen_rtx_SET (SImode, scratch,
13099 gen_rtx_AND (SImode,
13100 gen_rtx_NOT (SImode, mask), scratch)));
13101 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13102 emit_store_conditional (SImode, cond, mem, scratch);
13104 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13105 emit_unlikely_jump (x, label1);
13107 emit_insn (gen_isync ());
13108 emit_label (XEXP (label2, 0));
13112 /* Emit instructions to move SRC to DST. Called by splitters for
13113 multi-register moves. It will emit at most one instruction for
13114 each register that is accessed; that is, it won't emit li/lis pairs
13115 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13119 rs6000_split_multireg_move (rtx dst, rtx src)
13121 /* The register number of the first register being moved. */
13123 /* The mode that is to be moved. */
13124 enum machine_mode mode;
13125 /* The mode that the move is being done in, and its size. */
13126 enum machine_mode reg_mode;
13128 /* The number of registers that will be moved. */
13131 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13132 mode = GET_MODE (dst);
13133 nregs = hard_regno_nregs[reg][mode];
13134 if (FP_REGNO_P (reg))
13135 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13136 else if (ALTIVEC_REGNO_P (reg))
13137 reg_mode = V16QImode;
13138 else if (TARGET_E500_DOUBLE && mode == TFmode)
13141 reg_mode = word_mode;
13142 reg_mode_size = GET_MODE_SIZE (reg_mode);
13144 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13146 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13148 /* Move register range backwards, if we might have destructive
13151 for (i = nregs - 1; i >= 0; i--)
13152 emit_insn (gen_rtx_SET (VOIDmode,
13153 simplify_gen_subreg (reg_mode, dst, mode,
13154 i * reg_mode_size),
13155 simplify_gen_subreg (reg_mode, src, mode,
13156 i * reg_mode_size)));
13162 bool used_update = false;
13164 if (MEM_P (src) && INT_REGNO_P (reg))
13168 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13169 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13172 breg = XEXP (XEXP (src, 0), 0);
13173 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13174 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13175 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13176 emit_insn (TARGET_32BIT
13177 ? gen_addsi3 (breg, breg, delta_rtx)
13178 : gen_adddi3 (breg, breg, delta_rtx));
13179 src = replace_equiv_address (src, breg);
13181 else if (! rs6000_offsettable_memref_p (src))
13184 basereg = gen_rtx_REG (Pmode, reg);
13185 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13186 src = replace_equiv_address (src, basereg);
13189 breg = XEXP (src, 0);
13190 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13191 breg = XEXP (breg, 0);
13193 /* If the base register we are using to address memory is
13194 also a destination reg, then change that register last. */
13196 && REGNO (breg) >= REGNO (dst)
13197 && REGNO (breg) < REGNO (dst) + nregs)
13198 j = REGNO (breg) - REGNO (dst);
13201 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13205 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13206 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13209 breg = XEXP (XEXP (dst, 0), 0);
13210 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13211 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13212 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13214 /* We have to update the breg before doing the store.
13215 Use store with update, if available. */
13219 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13220 emit_insn (TARGET_32BIT
13221 ? (TARGET_POWERPC64
13222 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13223 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13224 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13225 used_update = true;
13228 emit_insn (TARGET_32BIT
13229 ? gen_addsi3 (breg, breg, delta_rtx)
13230 : gen_adddi3 (breg, breg, delta_rtx));
13231 dst = replace_equiv_address (dst, breg);
13234 gcc_assert (rs6000_offsettable_memref_p (dst));
13237 for (i = 0; i < nregs; i++)
13239 /* Calculate index to next subword. */
13244 /* If compiler already emitted move of first word by
13245 store with update, no need to do anything. */
13246 if (j == 0 && used_update)
13249 emit_insn (gen_rtx_SET (VOIDmode,
13250 simplify_gen_subreg (reg_mode, dst, mode,
13251 j * reg_mode_size),
13252 simplify_gen_subreg (reg_mode, src, mode,
13253 j * reg_mode_size)));
13259 /* This page contains routines that are used to determine what the
13260 function prologue and epilogue code will do and write them out. */
13262 /* Return the first fixed-point register that is required to be
13263 saved. 32 if none. */
13266 first_reg_to_save (void)
13270 /* Find lowest numbered live register. */
13271 for (first_reg = 13; first_reg <= 31; first_reg++)
13272 if (df_regs_ever_live_p (first_reg)
13273 && (! call_used_regs[first_reg]
13274 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13275 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13276 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13277 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13282 && current_function_uses_pic_offset_table
13283 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13284 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13290 /* Similar, for FP regs. */
13293 first_fp_reg_to_save (void)
13297 /* Find lowest numbered live register. */
13298 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13299 if (df_regs_ever_live_p (first_reg))
13305 /* Similar, for AltiVec regs. */
13308 first_altivec_reg_to_save (void)
13312 /* Stack frame remains as is unless we are in AltiVec ABI. */
13313 if (! TARGET_ALTIVEC_ABI)
13314 return LAST_ALTIVEC_REGNO + 1;
13316 /* On Darwin, the unwind routines are compiled without
13317 TARGET_ALTIVEC, and use save_world to save/restore the
13318 altivec registers when necessary. */
13319 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13320 && ! TARGET_ALTIVEC)
13321 return FIRST_ALTIVEC_REGNO + 20;
13323 /* Find lowest numbered live register. */
13324 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13325 if (df_regs_ever_live_p (i))
13331 /* Return a 32-bit mask of the AltiVec registers we need to set in
13332 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13333 the 32-bit word is 0. */
13335 static unsigned int
13336 compute_vrsave_mask (void)
13338 unsigned int i, mask = 0;
13340 /* On Darwin, the unwind routines are compiled without
13341 TARGET_ALTIVEC, and use save_world to save/restore the
13342 call-saved altivec registers when necessary. */
13343 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13344 && ! TARGET_ALTIVEC)
13347 /* First, find out if we use _any_ altivec registers. */
13348 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13349 if (df_regs_ever_live_p (i))
13350 mask |= ALTIVEC_REG_BIT (i);
13355 /* Next, remove the argument registers from the set. These must
13356 be in the VRSAVE mask set by the caller, so we don't need to add
13357 them in again. More importantly, the mask we compute here is
13358 used to generate CLOBBERs in the set_vrsave insn, and we do not
13359 wish the argument registers to die. */
13360 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13361 mask &= ~ALTIVEC_REG_BIT (i);
13363 /* Similarly, remove the return value from the set. */
13366 diddle_return_value (is_altivec_return_reg, &yes);
13368 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13374 /* For a very restricted set of circumstances, we can cut down the
13375 size of prologues/epilogues by calling our own save/restore-the-world
13379 compute_save_world_info (rs6000_stack_t *info_ptr)
13381 info_ptr->world_save_p = 1;
13382 info_ptr->world_save_p
13383 = (WORLD_SAVE_P (info_ptr)
13384 && DEFAULT_ABI == ABI_DARWIN
13385 && ! (current_function_calls_setjmp && flag_exceptions)
13386 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13387 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13388 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13389 && info_ptr->cr_save_p);
13391 /* This will not work in conjunction with sibcalls. Make sure there
13392 are none. (This check is expensive, but seldom executed.) */
13393 if (WORLD_SAVE_P (info_ptr))
13396 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13397 if ( GET_CODE (insn) == CALL_INSN
13398 && SIBLING_CALL_P (insn))
13400 info_ptr->world_save_p = 0;
13405 if (WORLD_SAVE_P (info_ptr))
13407 /* Even if we're not touching VRsave, make sure there's room on the
13408 stack for it, if it looks like we're calling SAVE_WORLD, which
13409 will attempt to save it. */
13410 info_ptr->vrsave_size = 4;
13412 /* "Save" the VRsave register too if we're saving the world. */
13413 if (info_ptr->vrsave_mask == 0)
13414 info_ptr->vrsave_mask = compute_vrsave_mask ();
13416 /* Because the Darwin register save/restore routines only handle
13417 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13419 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13420 && (info_ptr->first_altivec_reg_save
13421 >= FIRST_SAVED_ALTIVEC_REGNO));
13428 is_altivec_return_reg (rtx reg, void *xyes)
13430 bool *yes = (bool *) xyes;
13431 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13436 /* Calculate the stack information for the current function. This is
13437 complicated by having two separate calling sequences, the AIX calling
13438 sequence and the V.4 calling sequence.
13440 AIX (and Darwin/Mac OS X) stack frames look like:
13442 SP----> +---------------------------------------+
13443 | back chain to caller | 0 0
13444 +---------------------------------------+
13445 | saved CR | 4 8 (8-11)
13446 +---------------------------------------+
13448 +---------------------------------------+
13449 | reserved for compilers | 12 24
13450 +---------------------------------------+
13451 | reserved for binders | 16 32
13452 +---------------------------------------+
13453 | saved TOC pointer | 20 40
13454 +---------------------------------------+
13455 | Parameter save area (P) | 24 48
13456 +---------------------------------------+
13457 | Alloca space (A) | 24+P etc.
13458 +---------------------------------------+
13459 | Local variable space (L) | 24+P+A
13460 +---------------------------------------+
13461 | Float/int conversion temporary (X) | 24+P+A+L
13462 +---------------------------------------+
13463 | Save area for AltiVec registers (W) | 24+P+A+L+X
13464 +---------------------------------------+
13465 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13466 +---------------------------------------+
13467 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13468 +---------------------------------------+
13469 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13470 +---------------------------------------+
13471 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13472 +---------------------------------------+
13473 old SP->| back chain to caller's caller |
13474 +---------------------------------------+
13476 The required alignment for AIX configurations is two words (i.e., 8
13480 V.4 stack frames look like:
13482 SP----> +---------------------------------------+
13483 | back chain to caller | 0
13484 +---------------------------------------+
13485 | caller's saved LR | 4
13486 +---------------------------------------+
13487 | Parameter save area (P) | 8
13488 +---------------------------------------+
13489 | Alloca space (A) | 8+P
13490 +---------------------------------------+
13491 | Varargs save area (V) | 8+P+A
13492 +---------------------------------------+
13493 | Local variable space (L) | 8+P+A+V
13494 +---------------------------------------+
13495 | Float/int conversion temporary (X) | 8+P+A+V+L
13496 +---------------------------------------+
13497 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13498 +---------------------------------------+
13499 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13500 +---------------------------------------+
13501 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13502 +---------------------------------------+
13503 | SPE: area for 64-bit GP registers |
13504 +---------------------------------------+
13505 | SPE alignment padding |
13506 +---------------------------------------+
13507 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13508 +---------------------------------------+
13509 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13510 +---------------------------------------+
13511 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13512 +---------------------------------------+
13513 old SP->| back chain to caller's caller |
13514 +---------------------------------------+
13516 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13517 given. (But note below and in sysv4.h that we require only 8 and
13518 may round up the size of our stack frame anyways. The historical
13519 reason is early versions of powerpc-linux which didn't properly
13520 align the stack at program startup. A happy side-effect is that
13521 -mno-eabi libraries can be used with -meabi programs.)
13523 The EABI configuration defaults to the V.4 layout. However,
13524 the stack alignment requirements may differ. If -mno-eabi is not
13525 given, the required stack alignment is 8 bytes; if -mno-eabi is
13526 given, the required alignment is 16 bytes. (But see V.4 comment
13529 #ifndef ABI_STACK_BOUNDARY
13530 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13533 static rs6000_stack_t *
13534 rs6000_stack_info (void)
13536 static rs6000_stack_t info;
13537 rs6000_stack_t *info_ptr = &info;
13538 int reg_size = TARGET_32BIT ? 4 : 8;
13541 HOST_WIDE_INT non_fixed_size;
13543 memset (&info, 0, sizeof (info));
13547 /* Cache value so we don't rescan instruction chain over and over. */
13548 if (cfun->machine->insn_chain_scanned_p == 0)
13549 cfun->machine->insn_chain_scanned_p
13550 = spe_func_has_64bit_regs_p () + 1;
13551 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13554 /* Select which calling sequence. */
13555 info_ptr->abi = DEFAULT_ABI;
13557 /* Calculate which registers need to be saved & save area size. */
13558 info_ptr->first_gp_reg_save = first_reg_to_save ();
13559 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13560 even if it currently looks like we won't. */
13561 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13562 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13563 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13564 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13565 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13567 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13569 /* For the SPE, we have an additional upper 32-bits on each GPR.
13570 Ideally we should save the entire 64-bits only when the upper
13571 half is used in SIMD instructions. Since we only record
13572 registers live (not the size they are used in), this proves
13573 difficult because we'd have to traverse the instruction chain at
13574 the right time, taking reload into account. This is a real pain,
13575 so we opt to save the GPRs in 64-bits always if but one register
13576 gets used in 64-bits. Otherwise, all the registers in the frame
13577 get saved in 32-bits.
13579 So... since when we save all GPRs (except the SP) in 64-bits, the
13580 traditional GP save area will be empty. */
13581 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13582 info_ptr->gp_size = 0;
13584 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13585 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13587 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13588 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13589 - info_ptr->first_altivec_reg_save);
13591 /* Does this function call anything? */
13592 info_ptr->calls_p = (! current_function_is_leaf
13593 || cfun->machine->ra_needs_full_frame);
13595 /* Determine if we need to save the link register. */
13596 if ((DEFAULT_ABI == ABI_AIX
13597 && current_function_profile
13598 && !TARGET_PROFILE_KERNEL)
13599 #ifdef TARGET_RELOCATABLE
13600 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13602 || (info_ptr->first_fp_reg_save != 64
13603 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13604 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13605 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13606 || info_ptr->calls_p
13607 || rs6000_ra_ever_killed ())
13609 info_ptr->lr_save_p = 1;
13610 df_set_regs_ever_live (LR_REGNO, true);
13613 /* Determine if we need to save the condition code registers. */
13614 if (df_regs_ever_live_p (CR2_REGNO)
13615 || df_regs_ever_live_p (CR3_REGNO)
13616 || df_regs_ever_live_p (CR4_REGNO))
13618 info_ptr->cr_save_p = 1;
13619 if (DEFAULT_ABI == ABI_V4)
13620 info_ptr->cr_size = reg_size;
13623 /* If the current function calls __builtin_eh_return, then we need
13624 to allocate stack space for registers that will hold data for
13625 the exception handler. */
13626 if (current_function_calls_eh_return)
13629 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13632 /* SPE saves EH registers in 64-bits. */
13633 ehrd_size = i * (TARGET_SPE_ABI
13634 && info_ptr->spe_64bit_regs_used != 0
13635 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13640 /* Determine various sizes. */
13641 info_ptr->reg_size = reg_size;
13642 info_ptr->fixed_size = RS6000_SAVE_AREA;
13643 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13644 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13645 TARGET_ALTIVEC ? 16 : 8);
13646 if (FRAME_GROWS_DOWNWARD)
13647 info_ptr->vars_size
13648 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13649 + info_ptr->parm_size,
13650 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13651 - (info_ptr->fixed_size + info_ptr->vars_size
13652 + info_ptr->parm_size);
13654 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13655 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13657 info_ptr->spe_gp_size = 0;
13659 if (TARGET_ALTIVEC_ABI)
13660 info_ptr->vrsave_mask = compute_vrsave_mask ();
13662 info_ptr->vrsave_mask = 0;
13664 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13665 info_ptr->vrsave_size = 4;
13667 info_ptr->vrsave_size = 0;
13669 compute_save_world_info (info_ptr);
13671 /* Calculate the offsets. */
13672 switch (DEFAULT_ABI)
13676 gcc_unreachable ();
13680 info_ptr->fp_save_offset = - info_ptr->fp_size;
13681 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13683 if (TARGET_ALTIVEC_ABI)
13685 info_ptr->vrsave_save_offset
13686 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13688 /* Align stack so vector save area is on a quadword boundary.
13689 The padding goes above the vectors. */
13690 if (info_ptr->altivec_size != 0)
13691 info_ptr->altivec_padding_size
13692 = info_ptr->vrsave_save_offset & 0xF;
13694 info_ptr->altivec_padding_size = 0;
13696 info_ptr->altivec_save_offset
13697 = info_ptr->vrsave_save_offset
13698 - info_ptr->altivec_padding_size
13699 - info_ptr->altivec_size;
13700 gcc_assert (info_ptr->altivec_size == 0
13701 || info_ptr->altivec_save_offset % 16 == 0);
13703 /* Adjust for AltiVec case. */
13704 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13707 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13708 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13709 info_ptr->lr_save_offset = 2*reg_size;
13713 info_ptr->fp_save_offset = - info_ptr->fp_size;
13714 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13715 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13717 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13719 /* Align stack so SPE GPR save area is aligned on a
13720 double-word boundary. */
13721 if (info_ptr->spe_gp_size != 0)
13722 info_ptr->spe_padding_size
13723 = 8 - (-info_ptr->cr_save_offset % 8);
13725 info_ptr->spe_padding_size = 0;
13727 info_ptr->spe_gp_save_offset
13728 = info_ptr->cr_save_offset
13729 - info_ptr->spe_padding_size
13730 - info_ptr->spe_gp_size;
13732 /* Adjust for SPE case. */
13733 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13735 else if (TARGET_ALTIVEC_ABI)
13737 info_ptr->vrsave_save_offset
13738 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13740 /* Align stack so vector save area is on a quadword boundary. */
13741 if (info_ptr->altivec_size != 0)
13742 info_ptr->altivec_padding_size
13743 = 16 - (-info_ptr->vrsave_save_offset % 16);
13745 info_ptr->altivec_padding_size = 0;
13747 info_ptr->altivec_save_offset
13748 = info_ptr->vrsave_save_offset
13749 - info_ptr->altivec_padding_size
13750 - info_ptr->altivec_size;
13752 /* Adjust for AltiVec case. */
13753 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13756 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13757 info_ptr->ehrd_offset -= ehrd_size;
13758 info_ptr->lr_save_offset = reg_size;
13762 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13763 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13764 + info_ptr->gp_size
13765 + info_ptr->altivec_size
13766 + info_ptr->altivec_padding_size
13767 + info_ptr->spe_gp_size
13768 + info_ptr->spe_padding_size
13770 + info_ptr->cr_size
13771 + info_ptr->vrsave_size,
13774 non_fixed_size = (info_ptr->vars_size
13775 + info_ptr->parm_size
13776 + info_ptr->save_size);
13778 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13779 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13781 /* Determine if we need to allocate any stack frame:
13783 For AIX we need to push the stack if a frame pointer is needed
13784 (because the stack might be dynamically adjusted), if we are
13785 debugging, if we make calls, or if the sum of fp_save, gp_save,
13786 and local variables are more than the space needed to save all
13787 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13788 + 18*8 = 288 (GPR13 reserved).
13790 For V.4 we don't have the stack cushion that AIX uses, but assume
13791 that the debugger can handle stackless frames. */
13793 if (info_ptr->calls_p)
13794 info_ptr->push_p = 1;
13796 else if (DEFAULT_ABI == ABI_V4)
13797 info_ptr->push_p = non_fixed_size != 0;
13799 else if (frame_pointer_needed)
13800 info_ptr->push_p = 1;
13802 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13803 info_ptr->push_p = 1;
13806 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13808 /* Zero offsets if we're not saving those registers. */
13809 if (info_ptr->fp_size == 0)
13810 info_ptr->fp_save_offset = 0;
13812 if (info_ptr->gp_size == 0)
13813 info_ptr->gp_save_offset = 0;
13815 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13816 info_ptr->altivec_save_offset = 0;
13818 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13819 info_ptr->vrsave_save_offset = 0;
13821 if (! TARGET_SPE_ABI
13822 || info_ptr->spe_64bit_regs_used == 0
13823 || info_ptr->spe_gp_size == 0)
13824 info_ptr->spe_gp_save_offset = 0;
13826 if (! info_ptr->lr_save_p)
13827 info_ptr->lr_save_offset = 0;
13829 if (! info_ptr->cr_save_p)
13830 info_ptr->cr_save_offset = 0;
13835 /* Return true if the current function uses any GPRs in 64-bit SIMD
13839 spe_func_has_64bit_regs_p (void)
13843 /* Functions that save and restore all the call-saved registers will
13844 need to save/restore the registers in 64-bits. */
13845 if (current_function_calls_eh_return
13846 || current_function_calls_setjmp
13847 || current_function_has_nonlocal_goto)
13850 insns = get_insns ();
13852 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13858 /* FIXME: This should be implemented with attributes...
13860 (set_attr "spe64" "true")....then,
13861 if (get_spe64(insn)) return true;
13863 It's the only reliable way to do the stuff below. */
13865 i = PATTERN (insn);
13866 if (GET_CODE (i) == SET)
13868 enum machine_mode mode = GET_MODE (SET_SRC (i));
13870 if (SPE_VECTOR_MODE (mode))
13872 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13882 debug_stack_info (rs6000_stack_t *info)
13884 const char *abi_string;
13887 info = rs6000_stack_info ();
13889 fprintf (stderr, "\nStack information for function %s:\n",
13890 ((current_function_decl && DECL_NAME (current_function_decl))
13891 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13896 default: abi_string = "Unknown"; break;
13897 case ABI_NONE: abi_string = "NONE"; break;
13898 case ABI_AIX: abi_string = "AIX"; break;
13899 case ABI_DARWIN: abi_string = "Darwin"; break;
13900 case ABI_V4: abi_string = "V.4"; break;
13903 fprintf (stderr, "\tABI = %5s\n", abi_string);
13905 if (TARGET_ALTIVEC_ABI)
13906 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13908 if (TARGET_SPE_ABI)
13909 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13911 if (info->first_gp_reg_save != 32)
13912 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13914 if (info->first_fp_reg_save != 64)
13915 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13917 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13918 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13919 info->first_altivec_reg_save);
13921 if (info->lr_save_p)
13922 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13924 if (info->cr_save_p)
13925 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13927 if (info->vrsave_mask)
13928 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13931 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13934 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13936 if (info->gp_save_offset)
13937 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13939 if (info->fp_save_offset)
13940 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13942 if (info->altivec_save_offset)
13943 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13944 info->altivec_save_offset);
13946 if (info->spe_gp_save_offset)
13947 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13948 info->spe_gp_save_offset);
13950 if (info->vrsave_save_offset)
13951 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13952 info->vrsave_save_offset);
13954 if (info->lr_save_offset)
13955 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13957 if (info->cr_save_offset)
13958 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13960 if (info->varargs_save_offset)
13961 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13963 if (info->total_size)
13964 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13967 if (info->vars_size)
13968 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13971 if (info->parm_size)
13972 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13974 if (info->fixed_size)
13975 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13978 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13980 if (info->spe_gp_size)
13981 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13984 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13986 if (info->altivec_size)
13987 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13989 if (info->vrsave_size)
13990 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13992 if (info->altivec_padding_size)
13993 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13994 info->altivec_padding_size);
13996 if (info->spe_padding_size)
13997 fprintf (stderr, "\tspe_padding_size = %5d\n",
13998 info->spe_padding_size);
14001 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14003 if (info->save_size)
14004 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14006 if (info->reg_size != 4)
14007 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14009 fprintf (stderr, "\n");
14013 rs6000_return_addr (int count, rtx frame)
14015 /* Currently we don't optimize very well between prolog and body
14016 code and for PIC code the code can be actually quite bad, so
14017 don't try to be too clever here. */
14018 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14020 cfun->machine->ra_needs_full_frame = 1;
14027 plus_constant (copy_to_reg
14028 (gen_rtx_MEM (Pmode,
14029 memory_address (Pmode, frame))),
14030 RETURN_ADDRESS_OFFSET)));
14033 cfun->machine->ra_need_lr = 1;
14034 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14037 /* Say whether a function is a candidate for sibcall handling or not.
14038 We do not allow indirect calls to be optimized into sibling calls.
14039 Also, we can't do it if there are any vector parameters; there's
14040 nowhere to put the VRsave code so it works; note that functions with
14041 vector parameters are required to have a prototype, so the argument
14042 type info must be available here. (The tail recursion case can work
14043 with vector parameters, but there's no way to distinguish here.) */
14045 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14050 if (TARGET_ALTIVEC_VRSAVE)
14052 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14053 type; type = TREE_CHAIN (type))
14055 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14059 if (DEFAULT_ABI == ABI_DARWIN
14060 || ((*targetm.binds_local_p) (decl)
14061 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14063 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14065 if (!lookup_attribute ("longcall", attr_list)
14066 || lookup_attribute ("shortcall", attr_list))
14073 /* NULL if INSN insn is valid within a low-overhead loop.
14074 Otherwise return why doloop cannot be applied.
14075 PowerPC uses the COUNT register for branch on table instructions. */
14077 static const char *
14078 rs6000_invalid_within_doloop (rtx insn)
14081 return "Function call in the loop.";
14084 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14085 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14086 return "Computed branch in the loop.";
14092 rs6000_ra_ever_killed (void)
14098 if (current_function_is_thunk)
14101 /* regs_ever_live has LR marked as used if any sibcalls are present,
14102 but this should not force saving and restoring in the
14103 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14104 clobbers LR, so that is inappropriate. */
14106 /* Also, the prologue can generate a store into LR that
14107 doesn't really count, like this:
14110 bcl to set PIC register
14114 When we're called from the epilogue, we need to avoid counting
14115 this as a store. */
14117 push_topmost_sequence ();
14118 top = get_insns ();
14119 pop_topmost_sequence ();
14120 reg = gen_rtx_REG (Pmode, LR_REGNO);
14122 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14128 if (!SIBLING_CALL_P (insn))
14131 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14133 else if (set_of (reg, insn) != NULL_RTX
14134 && !prologue_epilogue_contains (insn))
14141 /* Emit instructions needed to load the TOC register.
14142 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14143 a constant pool; or for SVR4 -fpic. */
14146 rs6000_emit_load_toc_table (int fromprolog)
14149 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14151 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14154 rtx lab, tmp1, tmp2, got;
14156 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14157 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14159 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14161 got = rs6000_got_sym ();
14162 tmp1 = tmp2 = dest;
14165 tmp1 = gen_reg_rtx (Pmode);
14166 tmp2 = gen_reg_rtx (Pmode);
14168 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14169 emit_move_insn (tmp1,
14170 gen_rtx_REG (Pmode, LR_REGNO));
14171 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14172 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14174 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14176 emit_insn (gen_load_toc_v4_pic_si ());
14177 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
14179 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14182 rtx temp0 = (fromprolog
14183 ? gen_rtx_REG (Pmode, 0)
14184 : gen_reg_rtx (Pmode));
14190 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14191 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14193 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14194 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14196 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14197 emit_move_insn (dest,
14198 gen_rtx_REG (Pmode, LR_REGNO));
14199 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14205 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14206 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14207 emit_move_insn (dest,
14208 gen_rtx_REG (Pmode, LR_REGNO));
14209 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14211 emit_insn (gen_addsi3 (dest, temp0, dest));
14213 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14215 /* This is for AIX code running in non-PIC ELF32. */
14218 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14219 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14221 emit_insn (gen_elf_high (dest, realsym));
14222 emit_insn (gen_elf_low (dest, dest, realsym));
14226 gcc_assert (DEFAULT_ABI == ABI_AIX);
14229 emit_insn (gen_load_toc_aix_si (dest));
14231 emit_insn (gen_load_toc_aix_di (dest));
14235 /* Emit instructions to restore the link register after determining where
14236 its value has been stored. */
14239 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14241 rs6000_stack_t *info = rs6000_stack_info ();
14244 operands[0] = source;
14245 operands[1] = scratch;
14247 if (info->lr_save_p)
14249 rtx frame_rtx = stack_pointer_rtx;
14250 HOST_WIDE_INT sp_offset = 0;
14253 if (frame_pointer_needed
14254 || current_function_calls_alloca
14255 || info->total_size > 32767)
14257 tmp = gen_frame_mem (Pmode, frame_rtx);
14258 emit_move_insn (operands[1], tmp);
14259 frame_rtx = operands[1];
14261 else if (info->push_p)
14262 sp_offset = info->total_size;
14264 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14265 tmp = gen_frame_mem (Pmode, tmp);
14266 emit_move_insn (tmp, operands[0]);
14269 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
14272 static GTY(()) int set = -1;
14275 get_TOC_alias_set (void)
14278 set = new_alias_set ();
14282 /* This returns nonzero if the current function uses the TOC. This is
14283 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14284 is generated by the ABI_V4 load_toc_* patterns. */
14291 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14294 rtx pat = PATTERN (insn);
14297 if (GET_CODE (pat) == PARALLEL)
14298 for (i = 0; i < XVECLEN (pat, 0); i++)
14300 rtx sub = XVECEXP (pat, 0, i);
14301 if (GET_CODE (sub) == USE)
14303 sub = XEXP (sub, 0);
14304 if (GET_CODE (sub) == UNSPEC
14305 && XINT (sub, 1) == UNSPEC_TOC)
14315 create_TOC_reference (rtx symbol)
14317 if (!can_create_pseudo_p ())
14318 df_set_regs_ever_live (TOC_REGISTER, true);
14319 return gen_rtx_PLUS (Pmode,
14320 gen_rtx_REG (Pmode, TOC_REGISTER),
14321 gen_rtx_CONST (Pmode,
14322 gen_rtx_MINUS (Pmode, symbol,
14323 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14326 /* If _Unwind_* has been called from within the same module,
14327 toc register is not guaranteed to be saved to 40(1) on function
14328 entry. Save it there in that case. */
14331 rs6000_aix_emit_builtin_unwind_init (void)
14334 rtx stack_top = gen_reg_rtx (Pmode);
14335 rtx opcode_addr = gen_reg_rtx (Pmode);
14336 rtx opcode = gen_reg_rtx (SImode);
14337 rtx tocompare = gen_reg_rtx (SImode);
14338 rtx no_toc_save_needed = gen_label_rtx ();
14340 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14341 emit_move_insn (stack_top, mem);
14343 mem = gen_frame_mem (Pmode,
14344 gen_rtx_PLUS (Pmode, stack_top,
14345 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14346 emit_move_insn (opcode_addr, mem);
14347 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14348 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14349 : 0xE8410028, SImode));
14351 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14352 SImode, NULL_RTX, NULL_RTX,
14353 no_toc_save_needed);
14355 mem = gen_frame_mem (Pmode,
14356 gen_rtx_PLUS (Pmode, stack_top,
14357 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14358 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14359 emit_label (no_toc_save_needed);
14362 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14363 and the change to the stack pointer. */
14366 rs6000_emit_stack_tie (void)
14368 rtx mem = gen_frame_mem (BLKmode,
14369 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14371 emit_insn (gen_stack_tie (mem));
14374 /* Emit the correct code for allocating stack space, as insns.
14375 If COPY_R12, make sure a copy of the old frame is left in r12.
14376 The generated code may use hard register 0 as a temporary. */
14379 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14382 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14383 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14384 rtx todec = gen_int_mode (-size, Pmode);
14386 if (INTVAL (todec) != -size)
14388 warning (0, "stack frame too large");
14389 emit_insn (gen_trap ());
14393 if (current_function_limit_stack)
14395 if (REG_P (stack_limit_rtx)
14396 && REGNO (stack_limit_rtx) > 1
14397 && REGNO (stack_limit_rtx) <= 31)
14399 emit_insn (TARGET_32BIT
14400 ? gen_addsi3 (tmp_reg,
14403 : gen_adddi3 (tmp_reg,
14407 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14410 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14412 && DEFAULT_ABI == ABI_V4)
14414 rtx toload = gen_rtx_CONST (VOIDmode,
14415 gen_rtx_PLUS (Pmode,
14419 emit_insn (gen_elf_high (tmp_reg, toload));
14420 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14421 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14425 warning (0, "stack limit expression is not supported");
14428 if (copy_r12 || ! TARGET_UPDATE)
14429 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14435 /* Need a note here so that try_split doesn't get confused. */
14436 if (get_last_insn () == NULL_RTX)
14437 emit_note (NOTE_INSN_DELETED);
14438 insn = emit_move_insn (tmp_reg, todec);
14439 try_split (PATTERN (insn), insn, 0);
14443 insn = emit_insn (TARGET_32BIT
14444 ? gen_movsi_update (stack_reg, stack_reg,
14446 : gen_movdi_di_update (stack_reg, stack_reg,
14447 todec, stack_reg));
14451 insn = emit_insn (TARGET_32BIT
14452 ? gen_addsi3 (stack_reg, stack_reg, todec)
14453 : gen_adddi3 (stack_reg, stack_reg, todec));
14454 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14455 gen_rtx_REG (Pmode, 12));
14458 RTX_FRAME_RELATED_P (insn) = 1;
14460 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14461 gen_rtx_SET (VOIDmode, stack_reg,
14462 gen_rtx_PLUS (Pmode, stack_reg,
14467 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14468 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14469 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14470 deduce these equivalences by itself so it wasn't necessary to hold
14471 its hand so much. */
14474 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14475 rtx reg2, rtx rreg)
14479 /* copy_rtx will not make unique copies of registers, so we need to
14480 ensure we don't have unwanted sharing here. */
14482 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14485 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14487 real = copy_rtx (PATTERN (insn));
14489 if (reg2 != NULL_RTX)
14490 real = replace_rtx (real, reg2, rreg);
14492 real = replace_rtx (real, reg,
14493 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14494 STACK_POINTER_REGNUM),
14497 /* We expect that 'real' is either a SET or a PARALLEL containing
14498 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14499 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14501 if (GET_CODE (real) == SET)
14505 temp = simplify_rtx (SET_SRC (set));
14507 SET_SRC (set) = temp;
14508 temp = simplify_rtx (SET_DEST (set));
14510 SET_DEST (set) = temp;
14511 if (GET_CODE (SET_DEST (set)) == MEM)
14513 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14515 XEXP (SET_DEST (set), 0) = temp;
14522 gcc_assert (GET_CODE (real) == PARALLEL);
14523 for (i = 0; i < XVECLEN (real, 0); i++)
14524 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14526 rtx set = XVECEXP (real, 0, i);
14528 temp = simplify_rtx (SET_SRC (set));
14530 SET_SRC (set) = temp;
14531 temp = simplify_rtx (SET_DEST (set));
14533 SET_DEST (set) = temp;
14534 if (GET_CODE (SET_DEST (set)) == MEM)
14536 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14538 XEXP (SET_DEST (set), 0) = temp;
14540 RTX_FRAME_RELATED_P (set) = 1;
14545 real = spe_synthesize_frame_save (real);
14547 RTX_FRAME_RELATED_P (insn) = 1;
14548 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14553 /* Given an SPE frame note, return a PARALLEL of SETs with the
14554 original note, plus a synthetic register save. */
14557 spe_synthesize_frame_save (rtx real)
14559 rtx synth, offset, reg, real2;
14561 if (GET_CODE (real) != SET
14562 || GET_MODE (SET_SRC (real)) != V2SImode)
14565 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14566 frame related note. The parallel contains a set of the register
14567 being saved, and another set to a synthetic register (n+1200).
14568 This is so we can differentiate between 64-bit and 32-bit saves.
14569 Words cannot describe this nastiness. */
14571 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14572 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14573 && GET_CODE (SET_SRC (real)) == REG);
14576 (set (mem (plus (reg x) (const y)))
14579 (set (mem (plus (reg x) (const y+4)))
14583 real2 = copy_rtx (real);
14584 PUT_MODE (SET_DEST (real2), SImode);
14585 reg = SET_SRC (real2);
14586 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14587 synth = copy_rtx (real2);
14589 if (BYTES_BIG_ENDIAN)
14591 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14592 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14595 reg = SET_SRC (synth);
14597 synth = replace_rtx (synth, reg,
14598 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14600 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14601 synth = replace_rtx (synth, offset,
14602 GEN_INT (INTVAL (offset)
14603 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14605 RTX_FRAME_RELATED_P (synth) = 1;
14606 RTX_FRAME_RELATED_P (real2) = 1;
14607 if (BYTES_BIG_ENDIAN)
14608 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14610 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14615 /* Returns an insn that has a vrsave set operation with the
14616 appropriate CLOBBERs. */
14619 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14622 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14623 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14626 = gen_rtx_SET (VOIDmode,
14628 gen_rtx_UNSPEC_VOLATILE (SImode,
14629 gen_rtvec (2, reg, vrsave),
14630 UNSPECV_SET_VRSAVE));
14634 /* We need to clobber the registers in the mask so the scheduler
14635 does not move sets to VRSAVE before sets of AltiVec registers.
14637 However, if the function receives nonlocal gotos, reload will set
14638 all call saved registers live. We will end up with:
14640 (set (reg 999) (mem))
14641 (parallel [ (set (reg vrsave) (unspec blah))
14642 (clobber (reg 999))])
14644 The clobber will cause the store into reg 999 to be dead, and
14645 flow will attempt to delete an epilogue insn. In this case, we
14646 need an unspec use/set of the register. */
14648 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14649 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14651 if (!epiloguep || call_used_regs [i])
14652 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14653 gen_rtx_REG (V4SImode, i));
14656 rtx reg = gen_rtx_REG (V4SImode, i);
14659 = gen_rtx_SET (VOIDmode,
14661 gen_rtx_UNSPEC (V4SImode,
14662 gen_rtvec (1, reg), 27));
14666 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14668 for (i = 0; i < nclobs; ++i)
14669 XVECEXP (insn, 0, i) = clobs[i];
14674 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14675 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14678 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14679 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14681 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14682 rtx replacea, replaceb;
14684 int_rtx = GEN_INT (offset);
14686 /* Some cases that need register indexed addressing. */
14687 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14688 || (TARGET_E500_DOUBLE && mode == DFmode)
14690 && SPE_VECTOR_MODE (mode)
14691 && !SPE_CONST_OFFSET_OK (offset)))
14693 /* Whomever calls us must make sure r11 is available in the
14694 flow path of instructions in the prologue. */
14695 offset_rtx = gen_rtx_REG (Pmode, 11);
14696 emit_move_insn (offset_rtx, int_rtx);
14698 replacea = offset_rtx;
14699 replaceb = int_rtx;
14703 offset_rtx = int_rtx;
14704 replacea = NULL_RTX;
14705 replaceb = NULL_RTX;
14708 reg = gen_rtx_REG (mode, regno);
14709 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14710 mem = gen_frame_mem (mode, addr);
14712 insn = emit_move_insn (mem, reg);
14714 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14717 /* Emit an offset memory reference suitable for a frame store, while
14718 converting to a valid addressing mode. */
14721 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14723 rtx int_rtx, offset_rtx;
14725 int_rtx = GEN_INT (offset);
14727 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14728 || (TARGET_E500_DOUBLE && mode == DFmode))
14730 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14731 emit_move_insn (offset_rtx, int_rtx);
14734 offset_rtx = int_rtx;
14736 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14739 /* Look for user-defined global regs. We should not save and restore these,
14740 and cannot use stmw/lmw if there are any in its range. */
14743 no_global_regs_above (int first_greg)
14746 for (i = 0; i < 32 - first_greg; i++)
14747 if (global_regs[first_greg + i])
14752 #ifndef TARGET_FIX_AND_CONTINUE
14753 #define TARGET_FIX_AND_CONTINUE 0
14756 /* Determine whether the gp REG is really used. */
14759 rs6000_reg_live_or_pic_offset_p (int reg)
14761 return ((df_regs_ever_live_p (reg)
14762 && (!call_used_regs[reg]
14763 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14764 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14765 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14766 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14767 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
14770 /* Emit function prologue as insns. */
14773 rs6000_emit_prologue (void)
14775 rs6000_stack_t *info = rs6000_stack_info ();
14776 enum machine_mode reg_mode = Pmode;
14777 int reg_size = TARGET_32BIT ? 4 : 8;
14778 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14779 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14780 rtx frame_reg_rtx = sp_reg_rtx;
14781 rtx cr_save_rtx = NULL_RTX;
14783 int saving_FPRs_inline;
14784 int using_store_multiple;
14785 HOST_WIDE_INT sp_offset = 0;
14787 if (TARGET_FIX_AND_CONTINUE)
14789 /* gdb on darwin arranges to forward a function from the old
14790 address by modifying the first 5 instructions of the function
14791 to branch to the overriding function. This is necessary to
14792 permit function pointers that point to the old function to
14793 actually forward to the new function. */
14794 emit_insn (gen_nop ());
14795 emit_insn (gen_nop ());
14796 emit_insn (gen_nop ());
14797 emit_insn (gen_nop ());
14798 emit_insn (gen_nop ());
14801 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14803 reg_mode = V2SImode;
14807 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14808 && (!TARGET_SPE_ABI
14809 || info->spe_64bit_regs_used == 0)
14810 && info->first_gp_reg_save < 31
14811 && no_global_regs_above (info->first_gp_reg_save));
14812 saving_FPRs_inline = (info->first_fp_reg_save == 64
14813 || FP_SAVE_INLINE (info->first_fp_reg_save)
14814 || current_function_calls_eh_return
14815 || cfun->machine->ra_need_lr);
14817 /* For V.4, update stack before we do any saving and set back pointer. */
14818 if (! WORLD_SAVE_P (info)
14820 && (DEFAULT_ABI == ABI_V4
14821 || current_function_calls_eh_return))
14823 if (info->total_size < 32767)
14824 sp_offset = info->total_size;
14826 frame_reg_rtx = frame_ptr_rtx;
14827 rs6000_emit_allocate_stack (info->total_size,
14828 (frame_reg_rtx != sp_reg_rtx
14829 && (info->cr_save_p
14831 || info->first_fp_reg_save < 64
14832 || info->first_gp_reg_save < 32
14834 if (frame_reg_rtx != sp_reg_rtx)
14835 rs6000_emit_stack_tie ();
14838 /* Handle world saves specially here. */
14839 if (WORLD_SAVE_P (info))
14846 /* save_world expects lr in r0. */
14847 reg0 = gen_rtx_REG (Pmode, 0);
14848 if (info->lr_save_p)
14850 insn = emit_move_insn (reg0,
14851 gen_rtx_REG (Pmode, LR_REGNO));
14852 RTX_FRAME_RELATED_P (insn) = 1;
14855 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14856 assumptions about the offsets of various bits of the stack
14858 gcc_assert (info->gp_save_offset == -220
14859 && info->fp_save_offset == -144
14860 && info->lr_save_offset == 8
14861 && info->cr_save_offset == 4
14864 && (!current_function_calls_eh_return
14865 || info->ehrd_offset == -432)
14866 && info->vrsave_save_offset == -224
14867 && info->altivec_save_offset == -416);
14869 treg = gen_rtx_REG (SImode, 11);
14870 emit_move_insn (treg, GEN_INT (-info->total_size));
14872 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14873 in R11. It also clobbers R12, so beware! */
14875 /* Preserve CR2 for save_world prologues */
14877 sz += 32 - info->first_gp_reg_save;
14878 sz += 64 - info->first_fp_reg_save;
14879 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14880 p = rtvec_alloc (sz);
14882 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14883 gen_rtx_REG (SImode,
14885 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14886 gen_rtx_SYMBOL_REF (Pmode,
14888 /* We do floats first so that the instruction pattern matches
14890 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14892 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14893 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14894 GEN_INT (info->fp_save_offset
14895 + sp_offset + 8 * i));
14896 rtx mem = gen_frame_mem (DFmode, addr);
14898 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14900 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14902 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14903 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14904 GEN_INT (info->altivec_save_offset
14905 + sp_offset + 16 * i));
14906 rtx mem = gen_frame_mem (V4SImode, addr);
14908 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14910 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14912 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14913 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14914 GEN_INT (info->gp_save_offset
14915 + sp_offset + reg_size * i));
14916 rtx mem = gen_frame_mem (reg_mode, addr);
14918 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14922 /* CR register traditionally saved as CR2. */
14923 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14924 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14925 GEN_INT (info->cr_save_offset
14927 rtx mem = gen_frame_mem (reg_mode, addr);
14929 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14931 /* Explain about use of R0. */
14932 if (info->lr_save_p)
14934 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14935 GEN_INT (info->lr_save_offset
14937 rtx mem = gen_frame_mem (reg_mode, addr);
14939 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14941 /* Explain what happens to the stack pointer. */
14943 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14944 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14947 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14948 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14949 treg, GEN_INT (-info->total_size));
14950 sp_offset = info->total_size;
14953 /* If we use the link register, get it into r0. */
14954 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14956 rtx addr, reg, mem;
14958 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14959 gen_rtx_REG (Pmode, LR_REGNO));
14960 RTX_FRAME_RELATED_P (insn) = 1;
14962 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14963 GEN_INT (info->lr_save_offset + sp_offset));
14964 reg = gen_rtx_REG (Pmode, 0);
14965 mem = gen_rtx_MEM (Pmode, addr);
14966 /* This should not be of rs6000_sr_alias_set, because of
14967 __builtin_return_address. */
14969 insn = emit_move_insn (mem, reg);
14970 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14971 NULL_RTX, NULL_RTX);
14974 /* If we need to save CR, put it into r12. */
14975 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14979 cr_save_rtx = gen_rtx_REG (SImode, 12);
14980 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14981 RTX_FRAME_RELATED_P (insn) = 1;
14982 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14983 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14984 But that's OK. All we have to do is specify that _one_ condition
14985 code register is saved in this stack slot. The thrower's epilogue
14986 will then restore all the call-saved registers.
14987 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14988 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14989 gen_rtx_REG (SImode, CR2_REGNO));
14990 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14995 /* Do any required saving of fpr's. If only one or two to save, do
14996 it ourselves. Otherwise, call function. */
14997 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
15000 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15001 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15002 && ! call_used_regs[info->first_fp_reg_save+i]))
15003 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
15004 info->first_fp_reg_save + i,
15005 info->fp_save_offset + sp_offset + 8 * i,
15008 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
15012 const char *alloc_rname;
15014 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
15016 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
15017 gen_rtx_REG (Pmode,
15019 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
15020 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
15021 alloc_rname = ggc_strdup (rname);
15022 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15023 gen_rtx_SYMBOL_REF (Pmode,
15025 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15027 rtx addr, reg, mem;
15028 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15029 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15030 GEN_INT (info->fp_save_offset
15031 + sp_offset + 8*i));
15032 mem = gen_frame_mem (DFmode, addr);
15034 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
15036 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15037 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15038 NULL_RTX, NULL_RTX);
15041 /* Save GPRs. This is done as a PARALLEL if we are using
15042 the store-multiple instructions. */
15043 if (!WORLD_SAVE_P (info) && using_store_multiple)
15047 p = rtvec_alloc (32 - info->first_gp_reg_save);
15048 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15050 rtx addr, reg, mem;
15051 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15052 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15053 GEN_INT (info->gp_save_offset
15056 mem = gen_frame_mem (reg_mode, addr);
15058 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
15060 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15061 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15062 NULL_RTX, NULL_RTX);
15064 else if (!WORLD_SAVE_P (info)
15066 && info->spe_64bit_regs_used != 0
15067 && info->first_gp_reg_save != 32)
15070 rtx spe_save_area_ptr;
15071 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15072 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15073 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15075 /* Determine whether we can address all of the registers that need
15076 to be saved with an offset from the stack pointer that fits in
15077 the small const field for SPE memory instructions. */
15078 int spe_regs_addressable_via_sp
15079 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15080 + (32 - info->first_gp_reg_save - 1) * reg_size);
15083 if (spe_regs_addressable_via_sp)
15085 spe_save_area_ptr = sp_reg_rtx;
15086 spe_offset = info->spe_gp_save_offset + sp_offset;
15090 /* Make r11 point to the start of the SPE save area. We need
15091 to be careful here if r11 is holding the static chain. If
15092 it is, then temporarily save it in r0. We would use r0 as
15093 our base register here, but using r0 as a base register in
15094 loads and stores means something different from what we
15096 if (using_static_chain_p)
15098 rtx r0 = gen_rtx_REG (Pmode, 0);
15100 gcc_assert (info->first_gp_reg_save > 11);
15102 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15105 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15106 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
15107 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15112 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15113 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15115 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15116 rtx offset, addr, mem;
15118 /* We're doing all this to ensure that the offset fits into
15119 the immediate offset of 'evstdd'. */
15120 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15122 offset = GEN_INT (reg_size * i + spe_offset);
15123 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15124 mem = gen_rtx_MEM (V2SImode, addr);
15126 insn = emit_move_insn (mem, reg);
15128 rs6000_frame_related (insn, spe_save_area_ptr,
15129 info->spe_gp_save_offset
15130 + sp_offset + reg_size * i,
15131 offset, const0_rtx);
15134 /* Move the static chain pointer back. */
15135 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15136 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15138 else if (!WORLD_SAVE_P (info))
15141 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15142 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15144 rtx addr, reg, mem;
15145 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15147 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15148 GEN_INT (info->gp_save_offset
15151 mem = gen_frame_mem (reg_mode, addr);
15153 insn = emit_move_insn (mem, reg);
15154 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15155 NULL_RTX, NULL_RTX);
15159 /* ??? There's no need to emit actual instructions here, but it's the
15160 easiest way to get the frame unwind information emitted. */
15161 if (current_function_calls_eh_return)
15163 unsigned int i, regno;
15165 /* In AIX ABI we need to pretend we save r2 here. */
15168 rtx addr, reg, mem;
15170 reg = gen_rtx_REG (reg_mode, 2);
15171 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15172 GEN_INT (sp_offset + 5 * reg_size));
15173 mem = gen_frame_mem (reg_mode, addr);
15175 insn = emit_move_insn (mem, reg);
15176 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15177 NULL_RTX, NULL_RTX);
15178 PATTERN (insn) = gen_blockage ();
15183 regno = EH_RETURN_DATA_REGNO (i);
15184 if (regno == INVALID_REGNUM)
15187 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15188 info->ehrd_offset + sp_offset
15189 + reg_size * (int) i,
15194 /* Save CR if we use any that must be preserved. */
15195 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15197 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15198 GEN_INT (info->cr_save_offset + sp_offset));
15199 rtx mem = gen_frame_mem (SImode, addr);
15200 /* See the large comment above about why CR2_REGNO is used. */
15201 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15203 /* If r12 was used to hold the original sp, copy cr into r0 now
15205 if (REGNO (frame_reg_rtx) == 12)
15209 cr_save_rtx = gen_rtx_REG (SImode, 0);
15210 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15211 RTX_FRAME_RELATED_P (insn) = 1;
15212 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15213 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15218 insn = emit_move_insn (mem, cr_save_rtx);
15220 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15221 NULL_RTX, NULL_RTX);
15224 /* Update stack and set back pointer unless this is V.4,
15225 for which it was done previously. */
15226 if (!WORLD_SAVE_P (info) && info->push_p
15227 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15229 if (info->total_size < 32767)
15230 sp_offset = info->total_size;
15232 frame_reg_rtx = frame_ptr_rtx;
15233 rs6000_emit_allocate_stack (info->total_size,
15234 (frame_reg_rtx != sp_reg_rtx
15235 && ((info->altivec_size != 0)
15236 || (info->vrsave_mask != 0)
15238 if (frame_reg_rtx != sp_reg_rtx)
15239 rs6000_emit_stack_tie ();
15242 /* Set frame pointer, if needed. */
15243 if (frame_pointer_needed)
15245 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15247 RTX_FRAME_RELATED_P (insn) = 1;
15250 /* Save AltiVec registers if needed. Save here because the red zone does
15251 not include AltiVec registers. */
15252 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15256 /* There should be a non inline version of this, for when we
15257 are saving lots of vector registers. */
15258 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15259 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15261 rtx areg, savereg, mem;
15264 offset = info->altivec_save_offset + sp_offset
15265 + 16 * (i - info->first_altivec_reg_save);
15267 savereg = gen_rtx_REG (V4SImode, i);
15269 areg = gen_rtx_REG (Pmode, 0);
15270 emit_move_insn (areg, GEN_INT (offset));
15272 /* AltiVec addressing mode is [reg+reg]. */
15273 mem = gen_frame_mem (V4SImode,
15274 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15276 insn = emit_move_insn (mem, savereg);
15278 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15279 areg, GEN_INT (offset));
15283 /* VRSAVE is a bit vector representing which AltiVec registers
15284 are used. The OS uses this to determine which vector
15285 registers to save on a context switch. We need to save
15286 VRSAVE on the stack frame, add whatever AltiVec registers we
15287 used in this function, and do the corresponding magic in the
15290 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15291 && info->vrsave_mask != 0)
15293 rtx reg, mem, vrsave;
15296 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15297 as frame_reg_rtx and r11 as the static chain pointer for
15298 nested functions. */
15299 reg = gen_rtx_REG (SImode, 0);
15300 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15302 emit_insn (gen_get_vrsave_internal (reg));
15304 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15306 if (!WORLD_SAVE_P (info))
15309 offset = info->vrsave_save_offset + sp_offset;
15310 mem = gen_frame_mem (SImode,
15311 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15312 GEN_INT (offset)));
15313 insn = emit_move_insn (mem, reg);
15316 /* Include the registers in the mask. */
15317 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15319 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15322 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15323 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15324 || (DEFAULT_ABI == ABI_V4
15325 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15326 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15328 /* If emit_load_toc_table will use the link register, we need to save
15329 it. We use R12 for this purpose because emit_load_toc_table
15330 can use register 0. This allows us to use a plain 'blr' to return
15331 from the procedure more often. */
15332 int save_LR_around_toc_setup = (TARGET_ELF
15333 && DEFAULT_ABI != ABI_AIX
15335 && ! info->lr_save_p
15336 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15337 if (save_LR_around_toc_setup)
15339 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15341 insn = emit_move_insn (frame_ptr_rtx, lr);
15342 RTX_FRAME_RELATED_P (insn) = 1;
15344 rs6000_emit_load_toc_table (TRUE);
15346 insn = emit_move_insn (lr, frame_ptr_rtx);
15347 RTX_FRAME_RELATED_P (insn) = 1;
15350 rs6000_emit_load_toc_table (TRUE);
15354 if (DEFAULT_ABI == ABI_DARWIN
15355 && flag_pic && current_function_uses_pic_offset_table)
15357 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15358 rtx src = machopic_function_base_sym ();
15360 /* Save and restore LR locally around this call (in R0). */
15361 if (!info->lr_save_p)
15362 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15364 emit_insn (gen_load_macho_picbase (src));
15366 emit_move_insn (gen_rtx_REG (Pmode,
15367 RS6000_PIC_OFFSET_TABLE_REGNUM),
15370 if (!info->lr_save_p)
15371 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15376 /* Write function prologue. */
15379 rs6000_output_function_prologue (FILE *file,
15380 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15382 rs6000_stack_t *info = rs6000_stack_info ();
15384 if (TARGET_DEBUG_STACK)
15385 debug_stack_info (info);
15387 /* Write .extern for any function we will call to save and restore
15389 if (info->first_fp_reg_save < 64
15390 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15391 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15392 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15393 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15394 RESTORE_FP_SUFFIX);
15396 /* Write .extern for AIX common mode routines, if needed. */
15397 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15399 fputs ("\t.extern __mulh\n", file);
15400 fputs ("\t.extern __mull\n", file);
15401 fputs ("\t.extern __divss\n", file);
15402 fputs ("\t.extern __divus\n", file);
15403 fputs ("\t.extern __quoss\n", file);
15404 fputs ("\t.extern __quous\n", file);
15405 common_mode_defined = 1;
15408 if (! HAVE_prologue)
15412 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15413 the "toplevel" insn chain. */
15414 emit_note (NOTE_INSN_DELETED);
15415 rs6000_emit_prologue ();
15416 emit_note (NOTE_INSN_DELETED);
15418 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15422 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15424 INSN_ADDRESSES_NEW (insn, addr);
15429 if (TARGET_DEBUG_STACK)
15430 debug_rtx_list (get_insns (), 100);
15431 final (get_insns (), file, FALSE);
15435 rs6000_pic_labelno++;
15438 /* Emit function epilogue as insns.
15440 At present, dwarf2out_frame_debug_expr doesn't understand
15441 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15442 anywhere in the epilogue. Most of the insns below would in any case
15443 need special notes to explain where r11 is in relation to the stack. */
15446 rs6000_emit_epilogue (int sibcall)
15448 rs6000_stack_t *info;
15449 int restoring_FPRs_inline;
15450 int using_load_multiple;
15451 int using_mtcr_multiple;
15452 int use_backchain_to_restore_sp;
15454 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15455 rtx frame_reg_rtx = sp_reg_rtx;
15456 enum machine_mode reg_mode = Pmode;
15457 int reg_size = TARGET_32BIT ? 4 : 8;
15460 info = rs6000_stack_info ();
15462 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15464 reg_mode = V2SImode;
15468 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15469 && (!TARGET_SPE_ABI
15470 || info->spe_64bit_regs_used == 0)
15471 && info->first_gp_reg_save < 31
15472 && no_global_regs_above (info->first_gp_reg_save));
15473 restoring_FPRs_inline = (sibcall
15474 || current_function_calls_eh_return
15475 || info->first_fp_reg_save == 64
15476 || FP_SAVE_INLINE (info->first_fp_reg_save));
15477 use_backchain_to_restore_sp = (frame_pointer_needed
15478 || current_function_calls_alloca
15479 || info->total_size > 32767);
15480 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15481 || rs6000_cpu == PROCESSOR_PPC603
15482 || rs6000_cpu == PROCESSOR_PPC750
15485 if (WORLD_SAVE_P (info))
15489 const char *alloc_rname;
15492 /* eh_rest_world_r10 will return to the location saved in the LR
15493 stack slot (which is not likely to be our caller.)
15494 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15495 rest_world is similar, except any R10 parameter is ignored.
15496 The exception-handling stuff that was here in 2.95 is no
15497 longer necessary. */
15501 + 32 - info->first_gp_reg_save
15502 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15503 + 63 + 1 - info->first_fp_reg_save);
15505 strcpy (rname, ((current_function_calls_eh_return) ?
15506 "*eh_rest_world_r10" : "*rest_world"));
15507 alloc_rname = ggc_strdup (rname);
15510 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15511 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15512 gen_rtx_REG (Pmode,
15515 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15516 /* The instruction pattern requires a clobber here;
15517 it is shared with the restVEC helper. */
15519 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15522 /* CR register traditionally saved as CR2. */
15523 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15524 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15525 GEN_INT (info->cr_save_offset));
15526 rtx mem = gen_frame_mem (reg_mode, addr);
15528 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15531 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15533 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15534 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15535 GEN_INT (info->gp_save_offset
15537 rtx mem = gen_frame_mem (reg_mode, addr);
15539 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15541 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15543 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15544 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15545 GEN_INT (info->altivec_save_offset
15547 rtx mem = gen_frame_mem (V4SImode, addr);
15549 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15551 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15553 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15554 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15555 GEN_INT (info->fp_save_offset
15557 rtx mem = gen_frame_mem (DFmode, addr);
15559 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15562 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15564 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15566 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15568 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15570 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15571 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15576 /* Set sp_offset based on the stack push from the prologue. */
15577 if (info->total_size < 32767)
15578 sp_offset = info->total_size;
15580 /* Restore AltiVec registers if needed. */
15581 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15585 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15586 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15588 rtx addr, areg, mem;
15590 areg = gen_rtx_REG (Pmode, 0);
15592 (areg, GEN_INT (info->altivec_save_offset
15594 + 16 * (i - info->first_altivec_reg_save)));
15596 /* AltiVec addressing mode is [reg+reg]. */
15597 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15598 mem = gen_frame_mem (V4SImode, addr);
15600 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15604 /* Restore VRSAVE if needed. */
15605 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15606 && info->vrsave_mask != 0)
15608 rtx addr, mem, reg;
15610 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15611 GEN_INT (info->vrsave_save_offset + sp_offset));
15612 mem = gen_frame_mem (SImode, addr);
15613 reg = gen_rtx_REG (SImode, 12);
15614 emit_move_insn (reg, mem);
15616 emit_insn (generate_set_vrsave (reg, info, 1));
15621 /* If we have a frame pointer, a call to alloca, or a large stack
15622 frame, restore the old stack pointer using the backchain. Otherwise,
15623 we know what size to update it with. */
15624 if (use_backchain_to_restore_sp)
15626 /* Under V.4, don't reset the stack pointer until after we're done
15627 loading the saved registers. */
15628 if (DEFAULT_ABI == ABI_V4)
15629 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15631 emit_move_insn (frame_reg_rtx,
15632 gen_rtx_MEM (Pmode, sp_reg_rtx));
15634 else if (info->push_p)
15636 if (DEFAULT_ABI == ABI_V4
15637 || current_function_calls_eh_return)
15638 sp_offset = info->total_size;
15641 emit_insn (TARGET_32BIT
15642 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15643 GEN_INT (info->total_size))
15644 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15645 GEN_INT (info->total_size)));
15649 /* Get the old lr if we saved it. */
15650 if (info->lr_save_p)
15652 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15653 info->lr_save_offset + sp_offset);
15655 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15658 /* Get the old cr if we saved it. */
15659 if (info->cr_save_p)
15661 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15662 GEN_INT (info->cr_save_offset + sp_offset));
15663 rtx mem = gen_frame_mem (SImode, addr);
15665 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15668 /* Set LR here to try to overlap restores below. */
15669 if (info->lr_save_p)
15670 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
15671 gen_rtx_REG (Pmode, 0));
15673 /* Load exception handler data registers, if needed. */
15674 if (current_function_calls_eh_return)
15676 unsigned int i, regno;
15680 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15681 GEN_INT (sp_offset + 5 * reg_size));
15682 rtx mem = gen_frame_mem (reg_mode, addr);
15684 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15691 regno = EH_RETURN_DATA_REGNO (i);
15692 if (regno == INVALID_REGNUM)
15695 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15696 info->ehrd_offset + sp_offset
15697 + reg_size * (int) i);
15699 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15703 /* Restore GPRs. This is done as a PARALLEL if we are using
15704 the load-multiple instructions. */
15705 if (using_load_multiple)
15708 p = rtvec_alloc (32 - info->first_gp_reg_save);
15709 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15711 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15712 GEN_INT (info->gp_save_offset
15715 rtx mem = gen_frame_mem (reg_mode, addr);
15718 gen_rtx_SET (VOIDmode,
15719 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15722 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15724 else if (TARGET_SPE_ABI
15725 && info->spe_64bit_regs_used != 0
15726 && info->first_gp_reg_save != 32)
15728 rtx spe_save_area_ptr;
15729 /* Determine whether we can address all of the registers that need
15730 to be saved with an offset from the stack pointer that fits in
15731 the small const field for SPE memory instructions. */
15732 int spe_regs_addressable_via_sp
15733 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15734 + (32 - info->first_gp_reg_save - 1) * reg_size);
15737 if (spe_regs_addressable_via_sp)
15739 spe_save_area_ptr = frame_reg_rtx;
15740 spe_offset = info->spe_gp_save_offset + sp_offset;
15744 /* Make r11 point to the start of the SPE save area. We worried about
15745 not clobbering it when we were saving registers in the prologue.
15746 There's no need to worry here because the static chain is passed
15747 anew to every function. */
15748 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15750 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15751 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15756 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15757 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15759 rtx offset, addr, mem;
15761 /* We're doing all this to ensure that the immediate offset
15762 fits into the immediate field of 'evldd'. */
15763 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
15765 offset = GEN_INT (spe_offset + reg_size * i);
15766 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15767 mem = gen_rtx_MEM (V2SImode, addr);
15769 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15774 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15775 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15777 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15778 GEN_INT (info->gp_save_offset
15781 rtx mem = gen_frame_mem (reg_mode, addr);
15783 emit_move_insn (gen_rtx_REG (reg_mode,
15784 info->first_gp_reg_save + i), mem);
15787 /* Restore fpr's if we need to do it without calling a function. */
15788 if (restoring_FPRs_inline)
15789 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15790 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15791 && ! call_used_regs[info->first_fp_reg_save+i]))
15794 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15795 GEN_INT (info->fp_save_offset
15798 mem = gen_frame_mem (DFmode, addr);
15800 emit_move_insn (gen_rtx_REG (DFmode,
15801 info->first_fp_reg_save + i),
15805 /* If we saved cr, restore it here. Just those that were used. */
15806 if (info->cr_save_p)
15808 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15811 if (using_mtcr_multiple)
15813 for (i = 0; i < 8; i++)
15814 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15816 gcc_assert (count);
15819 if (using_mtcr_multiple && count > 1)
15824 p = rtvec_alloc (count);
15827 for (i = 0; i < 8; i++)
15828 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15830 rtvec r = rtvec_alloc (2);
15831 RTVEC_ELT (r, 0) = r12_rtx;
15832 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15833 RTVEC_ELT (p, ndx) =
15834 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15835 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15838 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15839 gcc_assert (ndx == count);
15842 for (i = 0; i < 8; i++)
15843 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15845 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15851 /* If this is V.4, unwind the stack pointer after all of the loads
15853 if (frame_reg_rtx != sp_reg_rtx)
15855 /* This blockage is needed so that sched doesn't decide to move
15856 the sp change before the register restores. */
15857 rs6000_emit_stack_tie ();
15859 && info->spe_64bit_regs_used != 0
15860 && info->first_gp_reg_save != 32)
15861 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
15862 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
15864 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15866 else if (sp_offset != 0)
15867 emit_insn (TARGET_32BIT
15868 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15869 GEN_INT (sp_offset))
15870 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15871 GEN_INT (sp_offset)));
15873 if (current_function_calls_eh_return)
15875 rtx sa = EH_RETURN_STACKADJ_RTX;
15876 emit_insn (TARGET_32BIT
15877 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15878 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15884 if (! restoring_FPRs_inline)
15885 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15887 p = rtvec_alloc (2);
15889 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15890 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15891 gen_rtx_REG (Pmode,
15894 /* If we have to restore more than two FP registers, branch to the
15895 restore function. It will return to our caller. */
15896 if (! restoring_FPRs_inline)
15900 const char *alloc_rname;
15902 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15903 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15904 alloc_rname = ggc_strdup (rname);
15905 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15906 gen_rtx_SYMBOL_REF (Pmode,
15909 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15912 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15913 GEN_INT (info->fp_save_offset + 8*i));
15914 mem = gen_frame_mem (DFmode, addr);
15916 RTVEC_ELT (p, i+3) =
15917 gen_rtx_SET (VOIDmode,
15918 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15923 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15927 /* Write function epilogue. */
15930 rs6000_output_function_epilogue (FILE *file,
15931 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15933 if (! HAVE_epilogue)
15935 rtx insn = get_last_insn ();
15936 /* If the last insn was a BARRIER, we don't have to write anything except
15937 the trace table. */
15938 if (GET_CODE (insn) == NOTE)
15939 insn = prev_nonnote_insn (insn);
15940 if (insn == 0 || GET_CODE (insn) != BARRIER)
15942 /* This is slightly ugly, but at least we don't have two
15943 copies of the epilogue-emitting code. */
15946 /* A NOTE_INSN_DELETED is supposed to be at the start
15947 and end of the "toplevel" insn chain. */
15948 emit_note (NOTE_INSN_DELETED);
15949 rs6000_emit_epilogue (FALSE);
15950 emit_note (NOTE_INSN_DELETED);
15952 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15956 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15958 INSN_ADDRESSES_NEW (insn, addr);
15963 if (TARGET_DEBUG_STACK)
15964 debug_rtx_list (get_insns (), 100);
15965 final (get_insns (), file, FALSE);
15971 macho_branch_islands ();
15972 /* Mach-O doesn't support labels at the end of objects, so if
15973 it looks like we might want one, insert a NOP. */
15975 rtx insn = get_last_insn ();
15978 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
15979 insn = PREV_INSN (insn);
15983 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
15984 fputs ("\tnop\n", file);
15988 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15991 We don't output a traceback table if -finhibit-size-directive was
15992 used. The documentation for -finhibit-size-directive reads
15993 ``don't output a @code{.size} assembler directive, or anything
15994 else that would cause trouble if the function is split in the
15995 middle, and the two halves are placed at locations far apart in
15996 memory.'' The traceback table has this property, since it
15997 includes the offset from the start of the function to the
15998 traceback table itself.
16000 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16001 different traceback table. */
16002 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
16003 && rs6000_traceback != traceback_none && !current_function_is_thunk)
16005 const char *fname = NULL;
16006 const char *language_string = lang_hooks.name;
16007 int fixed_parms = 0, float_parms = 0, parm_info = 0;
16009 int optional_tbtab;
16010 rs6000_stack_t *info = rs6000_stack_info ();
16012 if (rs6000_traceback == traceback_full)
16013 optional_tbtab = 1;
16014 else if (rs6000_traceback == traceback_part)
16015 optional_tbtab = 0;
16017 optional_tbtab = !optimize_size && !TARGET_ELF;
16019 if (optional_tbtab)
16021 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
16022 while (*fname == '.') /* V.4 encodes . in the name */
16025 /* Need label immediately before tbtab, so we can compute
16026 its offset from the function start. */
16027 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16028 ASM_OUTPUT_LABEL (file, fname);
16031 /* The .tbtab pseudo-op can only be used for the first eight
16032 expressions, since it can't handle the possibly variable
16033 length fields that follow. However, if you omit the optional
16034 fields, the assembler outputs zeros for all optional fields
16035 anyways, giving each variable length field is minimum length
16036 (as defined in sys/debug.h). Thus we can not use the .tbtab
16037 pseudo-op at all. */
16039 /* An all-zero word flags the start of the tbtab, for debuggers
16040 that have to find it by searching forward from the entry
16041 point or from the current pc. */
16042 fputs ("\t.long 0\n", file);
16044 /* Tbtab format type. Use format type 0. */
16045 fputs ("\t.byte 0,", file);
16047 /* Language type. Unfortunately, there does not seem to be any
16048 official way to discover the language being compiled, so we
16049 use language_string.
16050 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16051 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16052 a number, so for now use 9. */
16053 if (! strcmp (language_string, "GNU C"))
16055 else if (! strcmp (language_string, "GNU F77")
16056 || ! strcmp (language_string, "GNU F95"))
16058 else if (! strcmp (language_string, "GNU Pascal"))
16060 else if (! strcmp (language_string, "GNU Ada"))
16062 else if (! strcmp (language_string, "GNU C++")
16063 || ! strcmp (language_string, "GNU Objective-C++"))
16065 else if (! strcmp (language_string, "GNU Java"))
16067 else if (! strcmp (language_string, "GNU Objective-C"))
16070 gcc_unreachable ();
16071 fprintf (file, "%d,", i);
16073 /* 8 single bit fields: global linkage (not set for C extern linkage,
16074 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16075 from start of procedure stored in tbtab, internal function, function
16076 has controlled storage, function has no toc, function uses fp,
16077 function logs/aborts fp operations. */
16078 /* Assume that fp operations are used if any fp reg must be saved. */
16079 fprintf (file, "%d,",
16080 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16082 /* 6 bitfields: function is interrupt handler, name present in
16083 proc table, function calls alloca, on condition directives
16084 (controls stack walks, 3 bits), saves condition reg, saves
16086 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16087 set up as a frame pointer, even when there is no alloca call. */
16088 fprintf (file, "%d,",
16089 ((optional_tbtab << 6)
16090 | ((optional_tbtab & frame_pointer_needed) << 5)
16091 | (info->cr_save_p << 1)
16092 | (info->lr_save_p)));
16094 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16096 fprintf (file, "%d,",
16097 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16099 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16100 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16102 if (optional_tbtab)
16104 /* Compute the parameter info from the function decl argument
16107 int next_parm_info_bit = 31;
16109 for (decl = DECL_ARGUMENTS (current_function_decl);
16110 decl; decl = TREE_CHAIN (decl))
16112 rtx parameter = DECL_INCOMING_RTL (decl);
16113 enum machine_mode mode = GET_MODE (parameter);
16115 if (GET_CODE (parameter) == REG)
16117 if (SCALAR_FLOAT_MODE_P (mode))
16137 gcc_unreachable ();
16140 /* If only one bit will fit, don't or in this entry. */
16141 if (next_parm_info_bit > 0)
16142 parm_info |= (bits << (next_parm_info_bit - 1));
16143 next_parm_info_bit -= 2;
16147 fixed_parms += ((GET_MODE_SIZE (mode)
16148 + (UNITS_PER_WORD - 1))
16150 next_parm_info_bit -= 1;
16156 /* Number of fixed point parameters. */
16157 /* This is actually the number of words of fixed point parameters; thus
16158 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16159 fprintf (file, "%d,", fixed_parms);
16161 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16163 /* This is actually the number of fp registers that hold parameters;
16164 and thus the maximum value is 13. */
16165 /* Set parameters on stack bit if parameters are not in their original
16166 registers, regardless of whether they are on the stack? Xlc
16167 seems to set the bit when not optimizing. */
16168 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16170 if (! optional_tbtab)
16173 /* Optional fields follow. Some are variable length. */
16175 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16176 11 double float. */
16177 /* There is an entry for each parameter in a register, in the order that
16178 they occur in the parameter list. Any intervening arguments on the
16179 stack are ignored. If the list overflows a long (max possible length
16180 34 bits) then completely leave off all elements that don't fit. */
16181 /* Only emit this long if there was at least one parameter. */
16182 if (fixed_parms || float_parms)
16183 fprintf (file, "\t.long %d\n", parm_info);
16185 /* Offset from start of code to tb table. */
16186 fputs ("\t.long ", file);
16187 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16189 RS6000_OUTPUT_BASENAME (file, fname);
16191 assemble_name (file, fname);
16193 rs6000_output_function_entry (file, fname);
16196 /* Interrupt handler mask. */
16197 /* Omit this long, since we never set the interrupt handler bit
16200 /* Number of CTL (controlled storage) anchors. */
16201 /* Omit this long, since the has_ctl bit is never set above. */
16203 /* Displacement into stack of each CTL anchor. */
16204 /* Omit this list of longs, because there are no CTL anchors. */
16206 /* Length of function name. */
16209 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16211 /* Function name. */
16212 assemble_string (fname, strlen (fname));
16214 /* Register for alloca automatic storage; this is always reg 31.
16215 Only emit this if the alloca bit was set above. */
16216 if (frame_pointer_needed)
16217 fputs ("\t.byte 31\n", file);
16219 fputs ("\t.align 2\n", file);
16223 /* A C compound statement that outputs the assembler code for a thunk
16224 function, used to implement C++ virtual function calls with
16225 multiple inheritance. The thunk acts as a wrapper around a virtual
16226 function, adjusting the implicit object parameter before handing
16227 control off to the real function.
16229 First, emit code to add the integer DELTA to the location that
16230 contains the incoming first argument. Assume that this argument
16231 contains a pointer, and is the one used to pass the `this' pointer
16232 in C++. This is the incoming argument *before* the function
16233 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16234 values of all other incoming arguments.
16236 After the addition, emit code to jump to FUNCTION, which is a
16237 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16238 not touch the return address. Hence returning from FUNCTION will
16239 return to whoever called the current `thunk'.
16241 The effect must be as if FUNCTION had been called directly with the
16242 adjusted first argument. This macro is responsible for emitting
16243 all of the code for a thunk function; output_function_prologue()
16244 and output_function_epilogue() are not invoked.
16246 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16247 been extracted from it.) It might possibly be useful on some
16248 targets, but probably not.
16250 If you do not define this macro, the target-independent code in the
16251 C++ frontend will generate a less efficient heavyweight thunk that
16252 calls FUNCTION instead of jumping to it. The generic approach does
16253 not support varargs. */
16256 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16257 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16260 rtx this, insn, funexp;
16262 reload_completed = 1;
16263 epilogue_completed = 1;
16265 /* Mark the end of the (empty) prologue. */
16266 emit_note (NOTE_INSN_PROLOGUE_END);
16268 /* Find the "this" pointer. If the function returns a structure,
16269 the structure return pointer is in r3. */
16270 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16271 this = gen_rtx_REG (Pmode, 4);
16273 this = gen_rtx_REG (Pmode, 3);
16275 /* Apply the constant offset, if required. */
16278 rtx delta_rtx = GEN_INT (delta);
16279 emit_insn (TARGET_32BIT
16280 ? gen_addsi3 (this, this, delta_rtx)
16281 : gen_adddi3 (this, this, delta_rtx));
16284 /* Apply the offset from the vtable, if required. */
16287 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16288 rtx tmp = gen_rtx_REG (Pmode, 12);
16290 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16291 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16293 emit_insn (TARGET_32BIT
16294 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16295 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16296 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16300 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16302 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16304 emit_insn (TARGET_32BIT
16305 ? gen_addsi3 (this, this, tmp)
16306 : gen_adddi3 (this, this, tmp));
16309 /* Generate a tail call to the target function. */
16310 if (!TREE_USED (function))
16312 assemble_external (function);
16313 TREE_USED (function) = 1;
16315 funexp = XEXP (DECL_RTL (function), 0);
16316 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16319 if (MACHOPIC_INDIRECT)
16320 funexp = machopic_indirect_call_target (funexp);
16323 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16324 generate sibcall RTL explicitly. */
16325 insn = emit_call_insn (
16326 gen_rtx_PARALLEL (VOIDmode,
16328 gen_rtx_CALL (VOIDmode,
16329 funexp, const0_rtx),
16330 gen_rtx_USE (VOIDmode, const0_rtx),
16331 gen_rtx_USE (VOIDmode,
16332 gen_rtx_REG (SImode,
16334 gen_rtx_RETURN (VOIDmode))));
16335 SIBLING_CALL_P (insn) = 1;
16338 /* Run just enough of rest_of_compilation to get the insns emitted.
16339 There's not really enough bulk here to make other passes such as
16340 instruction scheduling worth while. Note that use_thunk calls
16341 assemble_start_function and assemble_end_function. */
16342 insn = get_insns ();
16343 insn_locators_alloc ();
16344 shorten_branches (insn);
16345 final_start_function (insn, file, 1);
16346 final (insn, file, 1);
16347 final_end_function ();
16349 reload_completed = 0;
16350 epilogue_completed = 0;
16353 /* A quick summary of the various types of 'constant-pool tables'
16356 Target Flags Name One table per
16357 AIX (none) AIX TOC object file
16358 AIX -mfull-toc AIX TOC object file
16359 AIX -mminimal-toc AIX minimal TOC translation unit
16360 SVR4/EABI (none) SVR4 SDATA object file
16361 SVR4/EABI -fpic SVR4 pic object file
16362 SVR4/EABI -fPIC SVR4 PIC translation unit
16363 SVR4/EABI -mrelocatable EABI TOC function
16364 SVR4/EABI -maix AIX TOC object file
16365 SVR4/EABI -maix -mminimal-toc
16366 AIX minimal TOC translation unit
16368 Name Reg. Set by entries contains:
16369 made by addrs? fp? sum?
16371 AIX TOC 2 crt0 as Y option option
16372 AIX minimal TOC 30 prolog gcc Y Y option
16373 SVR4 SDATA 13 crt0 gcc N Y N
16374 SVR4 pic 30 prolog ld Y not yet N
16375 SVR4 PIC 30 prolog gcc Y option option
16376 EABI TOC 30 prolog gcc Y option option
16380 /* Hash functions for the hash table. */
16383 rs6000_hash_constant (rtx k)
16385 enum rtx_code code = GET_CODE (k);
16386 enum machine_mode mode = GET_MODE (k);
16387 unsigned result = (code << 3) ^ mode;
16388 const char *format;
16391 format = GET_RTX_FORMAT (code);
16392 flen = strlen (format);
16398 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16401 if (mode != VOIDmode)
16402 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16414 for (; fidx < flen; fidx++)
16415 switch (format[fidx])
16420 const char *str = XSTR (k, fidx);
16421 len = strlen (str);
16422 result = result * 613 + len;
16423 for (i = 0; i < len; i++)
16424 result = result * 613 + (unsigned) str[i];
16429 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16433 result = result * 613 + (unsigned) XINT (k, fidx);
16436 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16437 result = result * 613 + (unsigned) XWINT (k, fidx);
16441 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16442 result = result * 613 + (unsigned) (XWINT (k, fidx)
16449 gcc_unreachable ();
16456 toc_hash_function (const void *hash_entry)
16458 const struct toc_hash_struct *thc =
16459 (const struct toc_hash_struct *) hash_entry;
16460 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16463 /* Compare H1 and H2 for equivalence. */
16466 toc_hash_eq (const void *h1, const void *h2)
16468 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16469 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16471 if (((const struct toc_hash_struct *) h1)->key_mode
16472 != ((const struct toc_hash_struct *) h2)->key_mode)
16475 return rtx_equal_p (r1, r2);
16478 /* These are the names given by the C++ front-end to vtables, and
16479 vtable-like objects. Ideally, this logic should not be here;
16480 instead, there should be some programmatic way of inquiring as
16481 to whether or not an object is a vtable. */
16483 #define VTABLE_NAME_P(NAME) \
16484 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16485 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16486 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16487 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16488 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16491 rs6000_output_symbol_ref (FILE *file, rtx x)
16493 /* Currently C++ toc references to vtables can be emitted before it
16494 is decided whether the vtable is public or private. If this is
16495 the case, then the linker will eventually complain that there is
16496 a reference to an unknown section. Thus, for vtables only,
16497 we emit the TOC reference to reference the symbol and not the
16499 const char *name = XSTR (x, 0);
16501 if (VTABLE_NAME_P (name))
16503 RS6000_OUTPUT_BASENAME (file, name);
16506 assemble_name (file, name);
16509 /* Output a TOC entry. We derive the entry name from what is being
16513 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16516 const char *name = buf;
16517 const char *real_name;
16519 HOST_WIDE_INT offset = 0;
16521 gcc_assert (!TARGET_NO_TOC);
16523 /* When the linker won't eliminate them, don't output duplicate
16524 TOC entries (this happens on AIX if there is any kind of TOC,
16525 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16527 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16529 struct toc_hash_struct *h;
16532 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16533 time because GGC is not initialized at that point. */
16534 if (toc_hash_table == NULL)
16535 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16536 toc_hash_eq, NULL);
16538 h = ggc_alloc (sizeof (*h));
16540 h->key_mode = mode;
16541 h->labelno = labelno;
16543 found = htab_find_slot (toc_hash_table, h, 1);
16544 if (*found == NULL)
16546 else /* This is indeed a duplicate.
16547 Set this label equal to that label. */
16549 fputs ("\t.set ", file);
16550 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16551 fprintf (file, "%d,", labelno);
16552 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16553 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16559 /* If we're going to put a double constant in the TOC, make sure it's
16560 aligned properly when strict alignment is on. */
16561 if (GET_CODE (x) == CONST_DOUBLE
16562 && STRICT_ALIGNMENT
16563 && GET_MODE_BITSIZE (mode) >= 64
16564 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16565 ASM_OUTPUT_ALIGN (file, 3);
16568 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16570 /* Handle FP constants specially. Note that if we have a minimal
16571 TOC, things we put here aren't actually in the TOC, so we can allow
16573 if (GET_CODE (x) == CONST_DOUBLE &&
16574 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16576 REAL_VALUE_TYPE rv;
16579 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16580 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16581 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16583 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16587 if (TARGET_MINIMAL_TOC)
16588 fputs (DOUBLE_INT_ASM_OP, file);
16590 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16591 k[0] & 0xffffffff, k[1] & 0xffffffff,
16592 k[2] & 0xffffffff, k[3] & 0xffffffff);
16593 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16594 k[0] & 0xffffffff, k[1] & 0xffffffff,
16595 k[2] & 0xffffffff, k[3] & 0xffffffff);
16600 if (TARGET_MINIMAL_TOC)
16601 fputs ("\t.long ", file);
16603 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16604 k[0] & 0xffffffff, k[1] & 0xffffffff,
16605 k[2] & 0xffffffff, k[3] & 0xffffffff);
16606 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16607 k[0] & 0xffffffff, k[1] & 0xffffffff,
16608 k[2] & 0xffffffff, k[3] & 0xffffffff);
16612 else if (GET_CODE (x) == CONST_DOUBLE &&
16613 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16615 REAL_VALUE_TYPE rv;
16618 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16620 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16621 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16623 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16627 if (TARGET_MINIMAL_TOC)
16628 fputs (DOUBLE_INT_ASM_OP, file);
16630 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16631 k[0] & 0xffffffff, k[1] & 0xffffffff);
16632 fprintf (file, "0x%lx%08lx\n",
16633 k[0] & 0xffffffff, k[1] & 0xffffffff);
16638 if (TARGET_MINIMAL_TOC)
16639 fputs ("\t.long ", file);
16641 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16642 k[0] & 0xffffffff, k[1] & 0xffffffff);
16643 fprintf (file, "0x%lx,0x%lx\n",
16644 k[0] & 0xffffffff, k[1] & 0xffffffff);
16648 else if (GET_CODE (x) == CONST_DOUBLE &&
16649 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16651 REAL_VALUE_TYPE rv;
16654 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16655 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16656 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16658 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16662 if (TARGET_MINIMAL_TOC)
16663 fputs (DOUBLE_INT_ASM_OP, file);
16665 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16666 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16671 if (TARGET_MINIMAL_TOC)
16672 fputs ("\t.long ", file);
16674 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16675 fprintf (file, "0x%lx\n", l & 0xffffffff);
16679 else if (GET_MODE (x) == VOIDmode
16680 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16682 unsigned HOST_WIDE_INT low;
16683 HOST_WIDE_INT high;
16685 if (GET_CODE (x) == CONST_DOUBLE)
16687 low = CONST_DOUBLE_LOW (x);
16688 high = CONST_DOUBLE_HIGH (x);
16691 #if HOST_BITS_PER_WIDE_INT == 32
16694 high = (low & 0x80000000) ? ~0 : 0;
16698 low = INTVAL (x) & 0xffffffff;
16699 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16703 /* TOC entries are always Pmode-sized, but since this
16704 is a bigendian machine then if we're putting smaller
16705 integer constants in the TOC we have to pad them.
16706 (This is still a win over putting the constants in
16707 a separate constant pool, because then we'd have
16708 to have both a TOC entry _and_ the actual constant.)
16710 For a 32-bit target, CONST_INT values are loaded and shifted
16711 entirely within `low' and can be stored in one TOC entry. */
16713 /* It would be easy to make this work, but it doesn't now. */
16714 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16716 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16718 #if HOST_BITS_PER_WIDE_INT == 32
16719 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16720 POINTER_SIZE, &low, &high, 0);
16723 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16724 high = (HOST_WIDE_INT) low >> 32;
16731 if (TARGET_MINIMAL_TOC)
16732 fputs (DOUBLE_INT_ASM_OP, file);
16734 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16735 (long) high & 0xffffffff, (long) low & 0xffffffff);
16736 fprintf (file, "0x%lx%08lx\n",
16737 (long) high & 0xffffffff, (long) low & 0xffffffff);
16742 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16744 if (TARGET_MINIMAL_TOC)
16745 fputs ("\t.long ", file);
16747 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16748 (long) high & 0xffffffff, (long) low & 0xffffffff);
16749 fprintf (file, "0x%lx,0x%lx\n",
16750 (long) high & 0xffffffff, (long) low & 0xffffffff);
16754 if (TARGET_MINIMAL_TOC)
16755 fputs ("\t.long ", file);
16757 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16758 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16764 if (GET_CODE (x) == CONST)
16766 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16768 base = XEXP (XEXP (x, 0), 0);
16769 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16772 switch (GET_CODE (base))
16775 name = XSTR (base, 0);
16779 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16780 CODE_LABEL_NUMBER (XEXP (base, 0)));
16784 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16788 gcc_unreachable ();
16791 real_name = (*targetm.strip_name_encoding) (name);
16792 if (TARGET_MINIMAL_TOC)
16793 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16796 fprintf (file, "\t.tc %s", real_name);
16799 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16801 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16803 fputs ("[TC],", file);
16806 /* Currently C++ toc references to vtables can be emitted before it
16807 is decided whether the vtable is public or private. If this is
16808 the case, then the linker will eventually complain that there is
16809 a TOC reference to an unknown section. Thus, for vtables only,
16810 we emit the TOC reference to reference the symbol and not the
16812 if (VTABLE_NAME_P (name))
16814 RS6000_OUTPUT_BASENAME (file, name);
16816 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16817 else if (offset > 0)
16818 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16821 output_addr_const (file, x);
16825 /* Output an assembler pseudo-op to write an ASCII string of N characters
16826 starting at P to FILE.
16828 On the RS/6000, we have to do this using the .byte operation and
16829 write out special characters outside the quoted string.
16830 Also, the assembler is broken; very long strings are truncated,
16831 so we must artificially break them up early. */
16834 output_ascii (FILE *file, const char *p, int n)
16837 int i, count_string;
16838 const char *for_string = "\t.byte \"";
16839 const char *for_decimal = "\t.byte ";
16840 const char *to_close = NULL;
16843 for (i = 0; i < n; i++)
16846 if (c >= ' ' && c < 0177)
16849 fputs (for_string, file);
16852 /* Write two quotes to get one. */
16860 for_decimal = "\"\n\t.byte ";
16864 if (count_string >= 512)
16866 fputs (to_close, file);
16868 for_string = "\t.byte \"";
16869 for_decimal = "\t.byte ";
16877 fputs (for_decimal, file);
16878 fprintf (file, "%d", c);
16880 for_string = "\n\t.byte \"";
16881 for_decimal = ", ";
16887 /* Now close the string if we have written one. Then end the line. */
16889 fputs (to_close, file);
16892 /* Generate a unique section name for FILENAME for a section type
16893 represented by SECTION_DESC. Output goes into BUF.
16895 SECTION_DESC can be any string, as long as it is different for each
16896 possible section type.
16898 We name the section in the same manner as xlc. The name begins with an
16899 underscore followed by the filename (after stripping any leading directory
16900 names) with the last period replaced by the string SECTION_DESC. If
16901 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16905 rs6000_gen_section_name (char **buf, const char *filename,
16906 const char *section_desc)
16908 const char *q, *after_last_slash, *last_period = 0;
16912 after_last_slash = filename;
16913 for (q = filename; *q; q++)
16916 after_last_slash = q + 1;
16917 else if (*q == '.')
16921 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16922 *buf = (char *) xmalloc (len);
16927 for (q = after_last_slash; *q; q++)
16929 if (q == last_period)
16931 strcpy (p, section_desc);
16932 p += strlen (section_desc);
16936 else if (ISALNUM (*q))
16940 if (last_period == 0)
16941 strcpy (p, section_desc);
16946 /* Emit profile function. */
16949 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16951 /* Non-standard profiling for kernels, which just saves LR then calls
16952 _mcount without worrying about arg saves. The idea is to change
16953 the function prologue as little as possible as it isn't easy to
16954 account for arg save/restore code added just for _mcount. */
16955 if (TARGET_PROFILE_KERNEL)
16958 if (DEFAULT_ABI == ABI_AIX)
16960 #ifndef NO_PROFILE_COUNTERS
16961 # define NO_PROFILE_COUNTERS 0
16963 if (NO_PROFILE_COUNTERS)
16964 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16968 const char *label_name;
16971 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16972 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16973 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16975 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16979 else if (DEFAULT_ABI == ABI_DARWIN)
16981 const char *mcount_name = RS6000_MCOUNT;
16982 int caller_addr_regno = LR_REGNO;
16984 /* Be conservative and always set this, at least for now. */
16985 current_function_uses_pic_offset_table = 1;
16988 /* For PIC code, set up a stub and collect the caller's address
16989 from r0, which is where the prologue puts it. */
16990 if (MACHOPIC_INDIRECT
16991 && current_function_uses_pic_offset_table)
16992 caller_addr_regno = 0;
16994 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16996 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
17000 /* Write function profiler code. */
17003 output_function_profiler (FILE *file, int labelno)
17007 switch (DEFAULT_ABI)
17010 gcc_unreachable ();
17015 warning (0, "no profiling of 64-bit code for this ABI");
17018 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17019 fprintf (file, "\tmflr %s\n", reg_names[0]);
17020 if (NO_PROFILE_COUNTERS)
17022 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17023 reg_names[0], reg_names[1]);
17025 else if (TARGET_SECURE_PLT && flag_pic)
17027 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17028 reg_names[0], reg_names[1]);
17029 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17030 asm_fprintf (file, "\t{cau|addis} %s,%s,",
17031 reg_names[12], reg_names[12]);
17032 assemble_name (file, buf);
17033 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
17034 assemble_name (file, buf);
17035 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
17037 else if (flag_pic == 1)
17039 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
17040 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17041 reg_names[0], reg_names[1]);
17042 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17043 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
17044 assemble_name (file, buf);
17045 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
17047 else if (flag_pic > 1)
17049 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17050 reg_names[0], reg_names[1]);
17051 /* Now, we need to get the address of the label. */
17052 fputs ("\tbcl 20,31,1f\n\t.long ", file);
17053 assemble_name (file, buf);
17054 fputs ("-.\n1:", file);
17055 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
17056 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
17057 reg_names[0], reg_names[11]);
17058 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
17059 reg_names[0], reg_names[0], reg_names[11]);
17063 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
17064 assemble_name (file, buf);
17065 fputs ("@ha\n", file);
17066 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17067 reg_names[0], reg_names[1]);
17068 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
17069 assemble_name (file, buf);
17070 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
17073 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17074 fprintf (file, "\tbl %s%s\n",
17075 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17080 if (!TARGET_PROFILE_KERNEL)
17082 /* Don't do anything, done in output_profile_hook (). */
17086 gcc_assert (!TARGET_32BIT);
17088 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17089 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17091 if (cfun->static_chain_decl != NULL)
17093 asm_fprintf (file, "\tstd %s,24(%s)\n",
17094 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17095 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17096 asm_fprintf (file, "\tld %s,24(%s)\n",
17097 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17100 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17108 /* The following variable value is the last issued insn. */
17110 static rtx last_scheduled_insn;
17112 /* The following variable helps to balance issuing of load and
17113 store instructions */
17115 static int load_store_pendulum;
17117 /* Power4 load update and store update instructions are cracked into a
17118 load or store and an integer insn which are executed in the same cycle.
17119 Branches have their own dispatch slot which does not count against the
17120 GCC issue rate, but it changes the program flow so there are no other
17121 instructions to issue in this cycle. */
17124 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17125 int verbose ATTRIBUTE_UNUSED,
17126 rtx insn, int more)
17128 last_scheduled_insn = insn;
17129 if (GET_CODE (PATTERN (insn)) == USE
17130 || GET_CODE (PATTERN (insn)) == CLOBBER)
17132 cached_can_issue_more = more;
17133 return cached_can_issue_more;
17136 if (insn_terminates_group_p (insn, current_group))
17138 cached_can_issue_more = 0;
17139 return cached_can_issue_more;
17142 /* If no reservation, but reach here */
17143 if (recog_memoized (insn) < 0)
17146 if (rs6000_sched_groups)
17148 if (is_microcoded_insn (insn))
17149 cached_can_issue_more = 0;
17150 else if (is_cracked_insn (insn))
17151 cached_can_issue_more = more > 2 ? more - 2 : 0;
17153 cached_can_issue_more = more - 1;
17155 return cached_can_issue_more;
17158 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17161 cached_can_issue_more = more - 1;
17162 return cached_can_issue_more;
17165 /* Adjust the cost of a scheduling dependency. Return the new cost of
17166 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17169 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17171 enum attr_type attr_type;
17173 if (! recog_memoized (insn))
17176 switch (REG_NOTE_KIND (link))
17180 /* Data dependency; DEP_INSN writes a register that INSN reads
17181 some cycles later. */
17183 /* Separate a load from a narrower, dependent store. */
17184 if (rs6000_sched_groups
17185 && GET_CODE (PATTERN (insn)) == SET
17186 && GET_CODE (PATTERN (dep_insn)) == SET
17187 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17188 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17189 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17190 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17193 attr_type = get_attr_type (insn);
17198 /* Tell the first scheduling pass about the latency between
17199 a mtctr and bctr (and mtlr and br/blr). The first
17200 scheduling pass will not know about this latency since
17201 the mtctr instruction, which has the latency associated
17202 to it, will be generated by reload. */
17203 return TARGET_POWER ? 5 : 4;
17205 /* Leave some extra cycles between a compare and its
17206 dependent branch, to inhibit expensive mispredicts. */
17207 if ((rs6000_cpu_attr == CPU_PPC603
17208 || rs6000_cpu_attr == CPU_PPC604
17209 || rs6000_cpu_attr == CPU_PPC604E
17210 || rs6000_cpu_attr == CPU_PPC620
17211 || rs6000_cpu_attr == CPU_PPC630
17212 || rs6000_cpu_attr == CPU_PPC750
17213 || rs6000_cpu_attr == CPU_PPC7400
17214 || rs6000_cpu_attr == CPU_PPC7450
17215 || rs6000_cpu_attr == CPU_POWER4
17216 || rs6000_cpu_attr == CPU_POWER5
17217 || rs6000_cpu_attr == CPU_CELL)
17218 && recog_memoized (dep_insn)
17219 && (INSN_CODE (dep_insn) >= 0))
17221 switch (get_attr_type (dep_insn))
17225 case TYPE_DELAYED_COMPARE:
17226 case TYPE_IMUL_COMPARE:
17227 case TYPE_LMUL_COMPARE:
17228 case TYPE_FPCOMPARE:
17229 case TYPE_CR_LOGICAL:
17230 case TYPE_DELAYED_CR:
17239 case TYPE_STORE_UX:
17241 case TYPE_FPSTORE_U:
17242 case TYPE_FPSTORE_UX:
17243 if ((rs6000_cpu == PROCESSOR_POWER6)
17244 && recog_memoized (dep_insn)
17245 && (INSN_CODE (dep_insn) >= 0))
17248 if (GET_CODE (PATTERN (insn)) != SET)
17249 /* If this happens, we have to extend this to schedule
17250 optimally. Return default for now. */
17253 /* Adjust the cost for the case where the value written
17254 by a fixed point operation is used as the address
17255 gen value on a store. */
17256 switch (get_attr_type (dep_insn))
17263 if (! store_data_bypass_p (dep_insn, insn))
17267 case TYPE_LOAD_EXT:
17268 case TYPE_LOAD_EXT_U:
17269 case TYPE_LOAD_EXT_UX:
17270 case TYPE_VAR_SHIFT_ROTATE:
17271 case TYPE_VAR_DELAYED_COMPARE:
17273 if (! store_data_bypass_p (dep_insn, insn))
17279 case TYPE_FAST_COMPARE:
17282 case TYPE_INSERT_WORD:
17283 case TYPE_INSERT_DWORD:
17284 case TYPE_FPLOAD_U:
17285 case TYPE_FPLOAD_UX:
17287 case TYPE_STORE_UX:
17288 case TYPE_FPSTORE_U:
17289 case TYPE_FPSTORE_UX:
17291 if (! store_data_bypass_p (dep_insn, insn))
17299 case TYPE_IMUL_COMPARE:
17300 case TYPE_LMUL_COMPARE:
17302 if (! store_data_bypass_p (dep_insn, insn))
17308 if (! store_data_bypass_p (dep_insn, insn))
17314 if (! store_data_bypass_p (dep_insn, insn))
17327 case TYPE_LOAD_EXT:
17328 case TYPE_LOAD_EXT_U:
17329 case TYPE_LOAD_EXT_UX:
17330 if ((rs6000_cpu == PROCESSOR_POWER6)
17331 && recog_memoized (dep_insn)
17332 && (INSN_CODE (dep_insn) >= 0))
17335 /* Adjust the cost for the case where the value written
17336 by a fixed point instruction is used within the address
17337 gen portion of a subsequent load(u)(x) */
17338 switch (get_attr_type (dep_insn))
17345 if (set_to_load_agen (dep_insn, insn))
17349 case TYPE_LOAD_EXT:
17350 case TYPE_LOAD_EXT_U:
17351 case TYPE_LOAD_EXT_UX:
17352 case TYPE_VAR_SHIFT_ROTATE:
17353 case TYPE_VAR_DELAYED_COMPARE:
17355 if (set_to_load_agen (dep_insn, insn))
17361 case TYPE_FAST_COMPARE:
17364 case TYPE_INSERT_WORD:
17365 case TYPE_INSERT_DWORD:
17366 case TYPE_FPLOAD_U:
17367 case TYPE_FPLOAD_UX:
17369 case TYPE_STORE_UX:
17370 case TYPE_FPSTORE_U:
17371 case TYPE_FPSTORE_UX:
17373 if (set_to_load_agen (dep_insn, insn))
17381 case TYPE_IMUL_COMPARE:
17382 case TYPE_LMUL_COMPARE:
17384 if (set_to_load_agen (dep_insn, insn))
17390 if (set_to_load_agen (dep_insn, insn))
17396 if (set_to_load_agen (dep_insn, insn))
17407 if ((rs6000_cpu == PROCESSOR_POWER6)
17408 && recog_memoized (dep_insn)
17409 && (INSN_CODE (dep_insn) >= 0)
17410 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17417 /* Fall out to return default cost. */
17421 case REG_DEP_OUTPUT:
17422 /* Output dependency; DEP_INSN writes a register that INSN writes some
17424 if ((rs6000_cpu == PROCESSOR_POWER6)
17425 && recog_memoized (dep_insn)
17426 && (INSN_CODE (dep_insn) >= 0))
17428 attr_type = get_attr_type (insn);
17433 if (get_attr_type (dep_insn) == TYPE_FP)
17437 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17445 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17450 gcc_unreachable ();
17456 /* The function returns a true if INSN is microcoded.
17457 Return false otherwise. */
17460 is_microcoded_insn (rtx insn)
17462 if (!insn || !INSN_P (insn)
17463 || GET_CODE (PATTERN (insn)) == USE
17464 || GET_CODE (PATTERN (insn)) == CLOBBER)
17467 if (rs6000_cpu_attr == CPU_CELL)
17468 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17470 if (rs6000_sched_groups)
17472 enum attr_type type = get_attr_type (insn);
17473 if (type == TYPE_LOAD_EXT_U
17474 || type == TYPE_LOAD_EXT_UX
17475 || type == TYPE_LOAD_UX
17476 || type == TYPE_STORE_UX
17477 || type == TYPE_MFCR)
17484 /* The function returns true if INSN is cracked into 2 instructions
17485 by the processor (and therefore occupies 2 issue slots). */
17488 is_cracked_insn (rtx insn)
17490 if (!insn || !INSN_P (insn)
17491 || GET_CODE (PATTERN (insn)) == USE
17492 || GET_CODE (PATTERN (insn)) == CLOBBER)
17495 if (rs6000_sched_groups)
17497 enum attr_type type = get_attr_type (insn);
17498 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17499 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17500 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17501 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17502 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17503 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17504 || type == TYPE_IDIV || type == TYPE_LDIV
17505 || type == TYPE_INSERT_WORD)
17512 /* The function returns true if INSN can be issued only from
17513 the branch slot. */
17516 is_branch_slot_insn (rtx insn)
17518 if (!insn || !INSN_P (insn)
17519 || GET_CODE (PATTERN (insn)) == USE
17520 || GET_CODE (PATTERN (insn)) == CLOBBER)
17523 if (rs6000_sched_groups)
17525 enum attr_type type = get_attr_type (insn);
17526 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17534 /* The function returns true if out_inst sets a value that is
17535 used in the address generation computation of in_insn */
17537 set_to_load_agen (rtx out_insn, rtx in_insn)
17539 rtx out_set, in_set;
17541 /* For performance reasons, only handle the simple case where
17542 both loads are a single_set. */
17543 out_set = single_set (out_insn);
17546 in_set = single_set (in_insn);
17548 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17554 /* The function returns true if the target storage location of
17555 out_insn is adjacent to the target storage location of in_insn */
17556 /* Return 1 if memory locations are adjacent. */
17559 adjacent_mem_locations (rtx insn1, rtx insn2)
17562 rtx a = get_store_dest (PATTERN (insn1));
17563 rtx b = get_store_dest (PATTERN (insn2));
17565 if ((GET_CODE (XEXP (a, 0)) == REG
17566 || (GET_CODE (XEXP (a, 0)) == PLUS
17567 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17568 && (GET_CODE (XEXP (b, 0)) == REG
17569 || (GET_CODE (XEXP (b, 0)) == PLUS
17570 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17572 HOST_WIDE_INT val0 = 0, val1 = 0;
17576 if (GET_CODE (XEXP (a, 0)) == PLUS)
17578 reg0 = XEXP (XEXP (a, 0), 0);
17579 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17582 reg0 = XEXP (a, 0);
17584 if (GET_CODE (XEXP (b, 0)) == PLUS)
17586 reg1 = XEXP (XEXP (b, 0), 0);
17587 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17590 reg1 = XEXP (b, 0);
17592 val_diff = val1 - val0;
17594 return ((REGNO (reg0) == REGNO (reg1))
17595 && (val_diff == INTVAL (MEM_SIZE (a))
17596 || val_diff == -INTVAL (MEM_SIZE (b))));
17602 /* A C statement (sans semicolon) to update the integer scheduling
17603 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17604 INSN earlier, reduce the priority to execute INSN later. Do not
17605 define this macro if you do not need to adjust the scheduling
17606 priorities of insns. */
17609 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17611 /* On machines (like the 750) which have asymmetric integer units,
17612 where one integer unit can do multiply and divides and the other
17613 can't, reduce the priority of multiply/divide so it is scheduled
17614 before other integer operations. */
17617 if (! INSN_P (insn))
17620 if (GET_CODE (PATTERN (insn)) == USE)
17623 switch (rs6000_cpu_attr) {
17625 switch (get_attr_type (insn))
17632 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17633 priority, priority);
17634 if (priority >= 0 && priority < 0x01000000)
17641 if (insn_must_be_first_in_group (insn)
17642 && reload_completed
17643 && current_sched_info->sched_max_insns_priority
17644 && rs6000_sched_restricted_insns_priority)
17647 /* Prioritize insns that can be dispatched only in the first
17649 if (rs6000_sched_restricted_insns_priority == 1)
17650 /* Attach highest priority to insn. This means that in
17651 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17652 precede 'priority' (critical path) considerations. */
17653 return current_sched_info->sched_max_insns_priority;
17654 else if (rs6000_sched_restricted_insns_priority == 2)
17655 /* Increase priority of insn by a minimal amount. This means that in
17656 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17657 considerations precede dispatch-slot restriction considerations. */
17658 return (priority + 1);
17661 if (rs6000_cpu == PROCESSOR_POWER6
17662 && ((load_store_pendulum == -2 && is_load_insn (insn))
17663 || (load_store_pendulum == 2 && is_store_insn (insn))))
17664 /* Attach highest priority to insn if the scheduler has just issued two
17665 stores and this instruction is a load, or two loads and this instruction
17666 is a store. Power6 wants loads and stores scheduled alternately
17668 return current_sched_info->sched_max_insns_priority;
17673 /* Return true if the instruction is nonpipelined on the Cell. */
17675 is_nonpipeline_insn (rtx insn)
17677 enum attr_type type;
17678 if (!insn || !INSN_P (insn)
17679 || GET_CODE (PATTERN (insn)) == USE
17680 || GET_CODE (PATTERN (insn)) == CLOBBER)
17683 type = get_attr_type (insn);
17684 if (type == TYPE_IMUL
17685 || type == TYPE_IMUL2
17686 || type == TYPE_IMUL3
17687 || type == TYPE_LMUL
17688 || type == TYPE_IDIV
17689 || type == TYPE_LDIV
17690 || type == TYPE_SDIV
17691 || type == TYPE_DDIV
17692 || type == TYPE_SSQRT
17693 || type == TYPE_DSQRT
17694 || type == TYPE_MFCR
17695 || type == TYPE_MFCRF
17696 || type == TYPE_MFJMPR)
17704 /* Return how many instructions the machine can issue per cycle. */
17707 rs6000_issue_rate (void)
17709 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17710 if (!reload_completed)
17713 switch (rs6000_cpu_attr) {
17714 case CPU_RIOS1: /* ? */
17716 case CPU_PPC601: /* ? */
17741 /* Return how many instructions to look ahead for better insn
17745 rs6000_use_sched_lookahead (void)
17747 if (rs6000_cpu_attr == CPU_PPC8540)
17749 if (rs6000_cpu_attr == CPU_CELL)
17750 return (reload_completed ? 8 : 0);
17754 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17756 rs6000_use_sched_lookahead_guard (rtx insn)
17758 if (rs6000_cpu_attr != CPU_CELL)
17761 if (insn == NULL_RTX || !INSN_P (insn))
17764 if (!reload_completed
17765 || is_nonpipeline_insn (insn)
17766 || is_microcoded_insn (insn))
17772 /* Determine is PAT refers to memory. */
17775 is_mem_ref (rtx pat)
17781 if (GET_CODE (pat) == MEM)
17784 /* Recursively process the pattern. */
17785 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17787 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17790 ret |= is_mem_ref (XEXP (pat, i));
17791 else if (fmt[i] == 'E')
17792 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17793 ret |= is_mem_ref (XVECEXP (pat, i, j));
17799 /* Determine if PAT is a PATTERN of a load insn. */
17802 is_load_insn1 (rtx pat)
17804 if (!pat || pat == NULL_RTX)
17807 if (GET_CODE (pat) == SET)
17808 return is_mem_ref (SET_SRC (pat));
17810 if (GET_CODE (pat) == PARALLEL)
17814 for (i = 0; i < XVECLEN (pat, 0); i++)
17815 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17822 /* Determine if INSN loads from memory. */
17825 is_load_insn (rtx insn)
17827 if (!insn || !INSN_P (insn))
17830 if (GET_CODE (insn) == CALL_INSN)
17833 return is_load_insn1 (PATTERN (insn));
17836 /* Determine if PAT is a PATTERN of a store insn. */
17839 is_store_insn1 (rtx pat)
17841 if (!pat || pat == NULL_RTX)
17844 if (GET_CODE (pat) == SET)
17845 return is_mem_ref (SET_DEST (pat));
17847 if (GET_CODE (pat) == PARALLEL)
17851 for (i = 0; i < XVECLEN (pat, 0); i++)
17852 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17859 /* Determine if INSN stores to memory. */
17862 is_store_insn (rtx insn)
17864 if (!insn || !INSN_P (insn))
17867 return is_store_insn1 (PATTERN (insn));
17870 /* Return the dest of a store insn. */
17873 get_store_dest (rtx pat)
17875 gcc_assert (is_store_insn1 (pat));
17877 if (GET_CODE (pat) == SET)
17878 return SET_DEST (pat);
17879 else if (GET_CODE (pat) == PARALLEL)
17883 for (i = 0; i < XVECLEN (pat, 0); i++)
17885 rtx inner_pat = XVECEXP (pat, 0, i);
17886 if (GET_CODE (inner_pat) == SET
17887 && is_mem_ref (SET_DEST (inner_pat)))
17891 /* We shouldn't get here, because we should have either a simple
17892 store insn or a store with update which are covered above. */
17896 /* Returns whether the dependence between INSN and NEXT is considered
17897 costly by the given target. */
17900 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17905 /* If the flag is not enabled - no dependence is considered costly;
17906 allow all dependent insns in the same group.
17907 This is the most aggressive option. */
17908 if (rs6000_sched_costly_dep == no_dep_costly)
17911 /* If the flag is set to 1 - a dependence is always considered costly;
17912 do not allow dependent instructions in the same group.
17913 This is the most conservative option. */
17914 if (rs6000_sched_costly_dep == all_deps_costly)
17917 insn = DEP_PRO (dep);
17918 next = DEP_CON (dep);
17920 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17921 && is_load_insn (next)
17922 && is_store_insn (insn))
17923 /* Prevent load after store in the same group. */
17926 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17927 && is_load_insn (next)
17928 && is_store_insn (insn)
17929 && DEP_KIND (dep) == REG_DEP_TRUE)
17930 /* Prevent load after store in the same group if it is a true
17934 /* The flag is set to X; dependences with latency >= X are considered costly,
17935 and will not be scheduled in the same group. */
17936 if (rs6000_sched_costly_dep <= max_dep_latency
17937 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17943 /* Return the next insn after INSN that is found before TAIL is reached,
17944 skipping any "non-active" insns - insns that will not actually occupy
17945 an issue slot. Return NULL_RTX if such an insn is not found. */
17948 get_next_active_insn (rtx insn, rtx tail)
17950 if (insn == NULL_RTX || insn == tail)
17955 insn = NEXT_INSN (insn);
17956 if (insn == NULL_RTX || insn == tail)
17961 || (NONJUMP_INSN_P (insn)
17962 && GET_CODE (PATTERN (insn)) != USE
17963 && GET_CODE (PATTERN (insn)) != CLOBBER
17964 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17970 /* We are about to begin issuing insns for this clock cycle. */
17973 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17974 rtx *ready ATTRIBUTE_UNUSED,
17975 int *pn_ready ATTRIBUTE_UNUSED,
17976 int clock_var ATTRIBUTE_UNUSED)
17978 int n_ready = *pn_ready;
17981 fprintf (dump, "// rs6000_sched_reorder :\n");
17983 /* Reorder the ready list, if the second to last ready insn
17984 is a nonepipeline insn. */
17985 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
17987 if (is_nonpipeline_insn (ready[n_ready - 1])
17988 && (recog_memoized (ready[n_ready - 2]) > 0))
17989 /* Simply swap first two insns. */
17991 rtx tmp = ready[n_ready - 1];
17992 ready[n_ready - 1] = ready[n_ready - 2];
17993 ready[n_ready - 2] = tmp;
17997 if (rs6000_cpu == PROCESSOR_POWER6)
17998 load_store_pendulum = 0;
18000 return rs6000_issue_rate ();
18003 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18006 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
18007 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
18010 fprintf (dump, "// rs6000_sched_reorder2 :\n");
18012 /* For Power6, we need to handle some special cases to try and keep the
18013 store queue from overflowing and triggering expensive flushes.
18015 This code monitors how load and store instructions are being issued
18016 and skews the ready list one way or the other to increase the likelihood
18017 that a desired instruction is issued at the proper time.
18019 A couple of things are done. First, we maintain a "load_store_pendulum"
18020 to track the current state of load/store issue.
18022 - If the pendulum is at zero, then no loads or stores have been
18023 issued in the current cycle so we do nothing.
18025 - If the pendulum is 1, then a single load has been issued in this
18026 cycle and we attempt to locate another load in the ready list to
18029 - If the pendulum is -2, then two stores have already been
18030 issued in this cycle, so we increase the priority of the first load
18031 in the ready list to increase it's likelihood of being chosen first
18034 - If the pendulum is -1, then a single store has been issued in this
18035 cycle and we attempt to locate another store in the ready list to
18036 issue with it, preferring a store to an adjacent memory location to
18037 facilitate store pairing in the store queue.
18039 - If the pendulum is 2, then two loads have already been
18040 issued in this cycle, so we increase the priority of the first store
18041 in the ready list to increase it's likelihood of being chosen first
18044 - If the pendulum < -2 or > 2, then do nothing.
18046 Note: This code covers the most common scenarios. There exist non
18047 load/store instructions which make use of the LSU and which
18048 would need to be accounted for to strictly model the behavior
18049 of the machine. Those instructions are currently unaccounted
18050 for to help minimize compile time overhead of this code.
18052 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
18058 if (is_store_insn (last_scheduled_insn))
18059 /* Issuing a store, swing the load_store_pendulum to the left */
18060 load_store_pendulum--;
18061 else if (is_load_insn (last_scheduled_insn))
18062 /* Issuing a load, swing the load_store_pendulum to the right */
18063 load_store_pendulum++;
18065 return cached_can_issue_more;
18067 /* If the pendulum is balanced, or there is only one instruction on
18068 the ready list, then all is well, so return. */
18069 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
18070 return cached_can_issue_more;
18072 if (load_store_pendulum == 1)
18074 /* A load has been issued in this cycle. Scan the ready list
18075 for another load to issue with it */
18080 if (is_load_insn (ready[pos]))
18082 /* Found a load. Move it to the head of the ready list,
18083 and adjust it's priority so that it is more likely to
18086 for (i=pos; i<*pn_ready-1; i++)
18087 ready[i] = ready[i + 1];
18088 ready[*pn_ready-1] = tmp;
18089 if INSN_PRIORITY_KNOWN (tmp)
18090 INSN_PRIORITY (tmp)++;
18096 else if (load_store_pendulum == -2)
18098 /* Two stores have been issued in this cycle. Increase the
18099 priority of the first load in the ready list to favor it for
18100 issuing in the next cycle. */
18105 if (is_load_insn (ready[pos])
18106 && INSN_PRIORITY_KNOWN (ready[pos]))
18108 INSN_PRIORITY (ready[pos])++;
18110 /* Adjust the pendulum to account for the fact that a load
18111 was found and increased in priority. This is to prevent
18112 increasing the priority of multiple loads */
18113 load_store_pendulum--;
18120 else if (load_store_pendulum == -1)
18122 /* A store has been issued in this cycle. Scan the ready list for
18123 another store to issue with it, preferring a store to an adjacent
18125 int first_store_pos = -1;
18131 if (is_store_insn (ready[pos]))
18133 /* Maintain the index of the first store found on the
18135 if (first_store_pos == -1)
18136 first_store_pos = pos;
18138 if (is_store_insn (last_scheduled_insn)
18139 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18141 /* Found an adjacent store. Move it to the head of the
18142 ready list, and adjust it's priority so that it is
18143 more likely to stay there */
18145 for (i=pos; i<*pn_ready-1; i++)
18146 ready[i] = ready[i + 1];
18147 ready[*pn_ready-1] = tmp;
18148 if INSN_PRIORITY_KNOWN (tmp)
18149 INSN_PRIORITY (tmp)++;
18150 first_store_pos = -1;
18158 if (first_store_pos >= 0)
18160 /* An adjacent store wasn't found, but a non-adjacent store was,
18161 so move the non-adjacent store to the front of the ready
18162 list, and adjust its priority so that it is more likely to
18164 tmp = ready[first_store_pos];
18165 for (i=first_store_pos; i<*pn_ready-1; i++)
18166 ready[i] = ready[i + 1];
18167 ready[*pn_ready-1] = tmp;
18168 if INSN_PRIORITY_KNOWN (tmp)
18169 INSN_PRIORITY (tmp)++;
18172 else if (load_store_pendulum == 2)
18174 /* Two loads have been issued in this cycle. Increase the priority
18175 of the first store in the ready list to favor it for issuing in
18181 if (is_store_insn (ready[pos])
18182 && INSN_PRIORITY_KNOWN (ready[pos]))
18184 INSN_PRIORITY (ready[pos])++;
18186 /* Adjust the pendulum to account for the fact that a store
18187 was found and increased in priority. This is to prevent
18188 increasing the priority of multiple stores */
18189 load_store_pendulum++;
18198 return cached_can_issue_more;
18201 /* Return whether the presence of INSN causes a dispatch group termination
18202 of group WHICH_GROUP.
18204 If WHICH_GROUP == current_group, this function will return true if INSN
18205 causes the termination of the current group (i.e, the dispatch group to
18206 which INSN belongs). This means that INSN will be the last insn in the
18207 group it belongs to.
18209 If WHICH_GROUP == previous_group, this function will return true if INSN
18210 causes the termination of the previous group (i.e, the dispatch group that
18211 precedes the group to which INSN belongs). This means that INSN will be
18212 the first insn in the group it belongs to). */
18215 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18222 first = insn_must_be_first_in_group (insn);
18223 last = insn_must_be_last_in_group (insn);
18228 if (which_group == current_group)
18230 else if (which_group == previous_group)
18238 insn_must_be_first_in_group (rtx insn)
18240 enum attr_type type;
18243 || insn == NULL_RTX
18244 || GET_CODE (insn) == NOTE
18245 || GET_CODE (PATTERN (insn)) == USE
18246 || GET_CODE (PATTERN (insn)) == CLOBBER)
18249 switch (rs6000_cpu)
18251 case PROCESSOR_POWER5:
18252 if (is_cracked_insn (insn))
18254 case PROCESSOR_POWER4:
18255 if (is_microcoded_insn (insn))
18258 if (!rs6000_sched_groups)
18261 type = get_attr_type (insn);
18268 case TYPE_DELAYED_CR:
18269 case TYPE_CR_LOGICAL:
18283 case PROCESSOR_POWER6:
18284 type = get_attr_type (insn);
18288 case TYPE_INSERT_DWORD:
18292 case TYPE_VAR_SHIFT_ROTATE:
18299 case TYPE_INSERT_WORD:
18300 case TYPE_DELAYED_COMPARE:
18301 case TYPE_IMUL_COMPARE:
18302 case TYPE_LMUL_COMPARE:
18303 case TYPE_FPCOMPARE:
18314 case TYPE_LOAD_EXT_UX:
18316 case TYPE_STORE_UX:
18317 case TYPE_FPLOAD_U:
18318 case TYPE_FPLOAD_UX:
18319 case TYPE_FPSTORE_U:
18320 case TYPE_FPSTORE_UX:
18334 insn_must_be_last_in_group (rtx insn)
18336 enum attr_type type;
18339 || insn == NULL_RTX
18340 || GET_CODE (insn) == NOTE
18341 || GET_CODE (PATTERN (insn)) == USE
18342 || GET_CODE (PATTERN (insn)) == CLOBBER)
18345 switch (rs6000_cpu) {
18346 case PROCESSOR_POWER4:
18347 case PROCESSOR_POWER5:
18348 if (is_microcoded_insn (insn))
18351 if (is_branch_slot_insn (insn))
18355 case PROCESSOR_POWER6:
18356 type = get_attr_type (insn);
18363 case TYPE_VAR_SHIFT_ROTATE:
18370 case TYPE_DELAYED_COMPARE:
18371 case TYPE_IMUL_COMPARE:
18372 case TYPE_LMUL_COMPARE:
18373 case TYPE_FPCOMPARE:
18394 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18395 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18398 is_costly_group (rtx *group_insns, rtx next_insn)
18401 int issue_rate = rs6000_issue_rate ();
18403 for (i = 0; i < issue_rate; i++)
18406 rtx insn = group_insns[i];
18411 FOR_EACH_DEP_LINK (link, INSN_FORW_DEPS (insn))
18413 dep_t dep = DEP_LINK_DEP (link);
18414 rtx next = DEP_CON (dep);
18416 if (next == next_insn
18417 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18425 /* Utility of the function redefine_groups.
18426 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18427 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18428 to keep it "far" (in a separate group) from GROUP_INSNS, following
18429 one of the following schemes, depending on the value of the flag
18430 -minsert_sched_nops = X:
18431 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18432 in order to force NEXT_INSN into a separate group.
18433 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18434 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18435 insertion (has a group just ended, how many vacant issue slots remain in the
18436 last group, and how many dispatch groups were encountered so far). */
18439 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18440 rtx next_insn, bool *group_end, int can_issue_more,
18445 int issue_rate = rs6000_issue_rate ();
18446 bool end = *group_end;
18449 if (next_insn == NULL_RTX)
18450 return can_issue_more;
18452 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18453 return can_issue_more;
18455 force = is_costly_group (group_insns, next_insn);
18457 return can_issue_more;
18459 if (sched_verbose > 6)
18460 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18461 *group_count ,can_issue_more);
18463 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18466 can_issue_more = 0;
18468 /* Since only a branch can be issued in the last issue_slot, it is
18469 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18470 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18471 in this case the last nop will start a new group and the branch
18472 will be forced to the new group. */
18473 if (can_issue_more && !is_branch_slot_insn (next_insn))
18476 while (can_issue_more > 0)
18479 emit_insn_before (nop, next_insn);
18487 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18489 int n_nops = rs6000_sched_insert_nops;
18491 /* Nops can't be issued from the branch slot, so the effective
18492 issue_rate for nops is 'issue_rate - 1'. */
18493 if (can_issue_more == 0)
18494 can_issue_more = issue_rate;
18496 if (can_issue_more == 0)
18498 can_issue_more = issue_rate - 1;
18501 for (i = 0; i < issue_rate; i++)
18503 group_insns[i] = 0;
18510 emit_insn_before (nop, next_insn);
18511 if (can_issue_more == issue_rate - 1) /* new group begins */
18514 if (can_issue_more == 0)
18516 can_issue_more = issue_rate - 1;
18519 for (i = 0; i < issue_rate; i++)
18521 group_insns[i] = 0;
18527 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18530 /* Is next_insn going to start a new group? */
18533 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18534 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18535 || (can_issue_more < issue_rate &&
18536 insn_terminates_group_p (next_insn, previous_group)));
18537 if (*group_end && end)
18540 if (sched_verbose > 6)
18541 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18542 *group_count, can_issue_more);
18543 return can_issue_more;
18546 return can_issue_more;
18549 /* This function tries to synch the dispatch groups that the compiler "sees"
18550 with the dispatch groups that the processor dispatcher is expected to
18551 form in practice. It tries to achieve this synchronization by forcing the
18552 estimated processor grouping on the compiler (as opposed to the function
18553 'pad_goups' which tries to force the scheduler's grouping on the processor).
18555 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18556 examines the (estimated) dispatch groups that will be formed by the processor
18557 dispatcher. It marks these group boundaries to reflect the estimated
18558 processor grouping, overriding the grouping that the scheduler had marked.
18559 Depending on the value of the flag '-minsert-sched-nops' this function can
18560 force certain insns into separate groups or force a certain distance between
18561 them by inserting nops, for example, if there exists a "costly dependence"
18564 The function estimates the group boundaries that the processor will form as
18565 follows: It keeps track of how many vacant issue slots are available after
18566 each insn. A subsequent insn will start a new group if one of the following
18568 - no more vacant issue slots remain in the current dispatch group.
18569 - only the last issue slot, which is the branch slot, is vacant, but the next
18570 insn is not a branch.
18571 - only the last 2 or less issue slots, including the branch slot, are vacant,
18572 which means that a cracked insn (which occupies two issue slots) can't be
18573 issued in this group.
18574 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18575 start a new group. */
18578 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18580 rtx insn, next_insn;
18582 int can_issue_more;
18585 int group_count = 0;
18589 issue_rate = rs6000_issue_rate ();
18590 group_insns = alloca (issue_rate * sizeof (rtx));
18591 for (i = 0; i < issue_rate; i++)
18593 group_insns[i] = 0;
18595 can_issue_more = issue_rate;
18597 insn = get_next_active_insn (prev_head_insn, tail);
18600 while (insn != NULL_RTX)
18602 slot = (issue_rate - can_issue_more);
18603 group_insns[slot] = insn;
18605 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18606 if (insn_terminates_group_p (insn, current_group))
18607 can_issue_more = 0;
18609 next_insn = get_next_active_insn (insn, tail);
18610 if (next_insn == NULL_RTX)
18611 return group_count + 1;
18613 /* Is next_insn going to start a new group? */
18615 = (can_issue_more == 0
18616 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18617 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18618 || (can_issue_more < issue_rate &&
18619 insn_terminates_group_p (next_insn, previous_group)));
18621 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18622 next_insn, &group_end, can_issue_more,
18628 can_issue_more = 0;
18629 for (i = 0; i < issue_rate; i++)
18631 group_insns[i] = 0;
18635 if (GET_MODE (next_insn) == TImode && can_issue_more)
18636 PUT_MODE (next_insn, VOIDmode);
18637 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18638 PUT_MODE (next_insn, TImode);
18641 if (can_issue_more == 0)
18642 can_issue_more = issue_rate;
18645 return group_count;
18648 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18649 dispatch group boundaries that the scheduler had marked. Pad with nops
18650 any dispatch groups which have vacant issue slots, in order to force the
18651 scheduler's grouping on the processor dispatcher. The function
18652 returns the number of dispatch groups found. */
18655 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18657 rtx insn, next_insn;
18660 int can_issue_more;
18662 int group_count = 0;
18664 /* Initialize issue_rate. */
18665 issue_rate = rs6000_issue_rate ();
18666 can_issue_more = issue_rate;
18668 insn = get_next_active_insn (prev_head_insn, tail);
18669 next_insn = get_next_active_insn (insn, tail);
18671 while (insn != NULL_RTX)
18674 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18676 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18678 if (next_insn == NULL_RTX)
18683 /* If the scheduler had marked group termination at this location
18684 (between insn and next_indn), and neither insn nor next_insn will
18685 force group termination, pad the group with nops to force group
18688 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18689 && !insn_terminates_group_p (insn, current_group)
18690 && !insn_terminates_group_p (next_insn, previous_group))
18692 if (!is_branch_slot_insn (next_insn))
18695 while (can_issue_more)
18698 emit_insn_before (nop, next_insn);
18703 can_issue_more = issue_rate;
18708 next_insn = get_next_active_insn (insn, tail);
18711 return group_count;
18714 /* We're beginning a new block. Initialize data structures as necessary. */
18717 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18718 int sched_verbose ATTRIBUTE_UNUSED,
18719 int max_ready ATTRIBUTE_UNUSED)
18721 last_scheduled_insn = NULL_RTX;
18722 load_store_pendulum = 0;
18725 /* The following function is called at the end of scheduling BB.
18726 After reload, it inserts nops at insn group bundling. */
18729 rs6000_sched_finish (FILE *dump, int sched_verbose)
18734 fprintf (dump, "=== Finishing schedule.\n");
18736 if (reload_completed && rs6000_sched_groups)
18738 if (rs6000_sched_insert_nops == sched_finish_none)
18741 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18742 n_groups = pad_groups (dump, sched_verbose,
18743 current_sched_info->prev_head,
18744 current_sched_info->next_tail);
18746 n_groups = redefine_groups (dump, sched_verbose,
18747 current_sched_info->prev_head,
18748 current_sched_info->next_tail);
18750 if (sched_verbose >= 6)
18752 fprintf (dump, "ngroups = %d\n", n_groups);
18753 print_rtl (dump, current_sched_info->prev_head);
18754 fprintf (dump, "Done finish_sched\n");
18759 /* Length in units of the trampoline for entering a nested function. */
18762 rs6000_trampoline_size (void)
18766 switch (DEFAULT_ABI)
18769 gcc_unreachable ();
18772 ret = (TARGET_32BIT) ? 12 : 24;
18777 ret = (TARGET_32BIT) ? 40 : 48;
18784 /* Emit RTL insns to initialize the variable parts of a trampoline.
18785 FNADDR is an RTX for the address of the function's pure code.
18786 CXT is an RTX for the static chain value for the function. */
18789 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18791 int regsize = (TARGET_32BIT) ? 4 : 8;
18792 rtx ctx_reg = force_reg (Pmode, cxt);
18794 switch (DEFAULT_ABI)
18797 gcc_unreachable ();
18799 /* Macros to shorten the code expansions below. */
18800 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18801 #define MEM_PLUS(addr,offset) \
18802 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18804 /* Under AIX, just build the 3 word function descriptor */
18807 rtx fn_reg = gen_reg_rtx (Pmode);
18808 rtx toc_reg = gen_reg_rtx (Pmode);
18809 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18810 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18811 emit_move_insn (MEM_DEREF (addr), fn_reg);
18812 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18813 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18817 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18820 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18821 FALSE, VOIDmode, 4,
18823 GEN_INT (rs6000_trampoline_size ()), SImode,
18833 /* Table of valid machine attributes. */
18835 const struct attribute_spec rs6000_attribute_table[] =
18837 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18838 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18839 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18840 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18841 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18842 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18843 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18844 SUBTARGET_ATTRIBUTE_TABLE,
18846 { NULL, 0, 0, false, false, false, NULL }
18849 /* Handle the "altivec" attribute. The attribute may have
18850 arguments as follows:
18852 __attribute__((altivec(vector__)))
18853 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18854 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18856 and may appear more than once (e.g., 'vector bool char') in a
18857 given declaration. */
18860 rs6000_handle_altivec_attribute (tree *node,
18861 tree name ATTRIBUTE_UNUSED,
18863 int flags ATTRIBUTE_UNUSED,
18864 bool *no_add_attrs)
18866 tree type = *node, result = NULL_TREE;
18867 enum machine_mode mode;
18870 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18871 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18872 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18875 while (POINTER_TYPE_P (type)
18876 || TREE_CODE (type) == FUNCTION_TYPE
18877 || TREE_CODE (type) == METHOD_TYPE
18878 || TREE_CODE (type) == ARRAY_TYPE)
18879 type = TREE_TYPE (type);
18881 mode = TYPE_MODE (type);
18883 /* Check for invalid AltiVec type qualifiers. */
18884 if (type == long_unsigned_type_node || type == long_integer_type_node)
18887 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18888 else if (rs6000_warn_altivec_long)
18889 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18891 else if (type == long_long_unsigned_type_node
18892 || type == long_long_integer_type_node)
18893 error ("use of %<long long%> in AltiVec types is invalid");
18894 else if (type == double_type_node)
18895 error ("use of %<double%> in AltiVec types is invalid");
18896 else if (type == long_double_type_node)
18897 error ("use of %<long double%> in AltiVec types is invalid");
18898 else if (type == boolean_type_node)
18899 error ("use of boolean types in AltiVec types is invalid");
18900 else if (TREE_CODE (type) == COMPLEX_TYPE)
18901 error ("use of %<complex%> in AltiVec types is invalid");
18902 else if (DECIMAL_FLOAT_MODE_P (mode))
18903 error ("use of decimal floating point types in AltiVec types is invalid");
18905 switch (altivec_type)
18908 unsigned_p = TYPE_UNSIGNED (type);
18912 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18915 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18918 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18920 case SFmode: result = V4SF_type_node; break;
18921 /* If the user says 'vector int bool', we may be handed the 'bool'
18922 attribute _before_ the 'vector' attribute, and so select the
18923 proper type in the 'b' case below. */
18924 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18932 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18933 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18934 case QImode: case V16QImode: result = bool_V16QI_type_node;
18941 case V8HImode: result = pixel_V8HI_type_node;
18947 if (result && result != type && TYPE_READONLY (type))
18948 result = build_qualified_type (result, TYPE_QUAL_CONST);
18950 *no_add_attrs = true; /* No need to hang on to the attribute. */
18953 *node = reconstruct_complex_type (*node, result);
18958 /* AltiVec defines four built-in scalar types that serve as vector
18959 elements; we must teach the compiler how to mangle them. */
18961 static const char *
18962 rs6000_mangle_type (tree type)
18964 type = TYPE_MAIN_VARIANT (type);
18966 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
18967 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
18970 if (type == bool_char_type_node) return "U6__boolc";
18971 if (type == bool_short_type_node) return "U6__bools";
18972 if (type == pixel_type_node) return "u7__pixel";
18973 if (type == bool_int_type_node) return "U6__booli";
18975 /* Mangle IBM extended float long double as `g' (__float128) on
18976 powerpc*-linux where long-double-64 previously was the default. */
18977 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
18979 && TARGET_LONG_DOUBLE_128
18980 && !TARGET_IEEEQUAD)
18983 /* For all other types, use normal C++ mangling. */
18987 /* Handle a "longcall" or "shortcall" attribute; arguments as in
18988 struct attribute_spec.handler. */
18991 rs6000_handle_longcall_attribute (tree *node, tree name,
18992 tree args ATTRIBUTE_UNUSED,
18993 int flags ATTRIBUTE_UNUSED,
18994 bool *no_add_attrs)
18996 if (TREE_CODE (*node) != FUNCTION_TYPE
18997 && TREE_CODE (*node) != FIELD_DECL
18998 && TREE_CODE (*node) != TYPE_DECL)
19000 warning (OPT_Wattributes, "%qs attribute only applies to functions",
19001 IDENTIFIER_POINTER (name));
19002 *no_add_attrs = true;
19008 /* Set longcall attributes on all functions declared when
19009 rs6000_default_long_calls is true. */
19011 rs6000_set_default_type_attributes (tree type)
19013 if (rs6000_default_long_calls
19014 && (TREE_CODE (type) == FUNCTION_TYPE
19015 || TREE_CODE (type) == METHOD_TYPE))
19016 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
19018 TYPE_ATTRIBUTES (type));
19021 darwin_set_default_type_attributes (type);
19025 /* Return a reference suitable for calling a function with the
19026 longcall attribute. */
19029 rs6000_longcall_ref (rtx call_ref)
19031 const char *call_name;
19034 if (GET_CODE (call_ref) != SYMBOL_REF)
19037 /* System V adds '.' to the internal name, so skip them. */
19038 call_name = XSTR (call_ref, 0);
19039 if (*call_name == '.')
19041 while (*call_name == '.')
19044 node = get_identifier (call_name);
19045 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
19048 return force_reg (Pmode, call_ref);
19051 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19052 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19055 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19056 struct attribute_spec.handler. */
19058 rs6000_handle_struct_attribute (tree *node, tree name,
19059 tree args ATTRIBUTE_UNUSED,
19060 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
19063 if (DECL_P (*node))
19065 if (TREE_CODE (*node) == TYPE_DECL)
19066 type = &TREE_TYPE (*node);
19071 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
19072 || TREE_CODE (*type) == UNION_TYPE)))
19074 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
19075 *no_add_attrs = true;
19078 else if ((is_attribute_p ("ms_struct", name)
19079 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
19080 || ((is_attribute_p ("gcc_struct", name)
19081 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19083 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19084 IDENTIFIER_POINTER (name));
19085 *no_add_attrs = true;
19092 rs6000_ms_bitfield_layout_p (tree record_type)
19094 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19095 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19096 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19099 #ifdef USING_ELFOS_H
19101 /* A get_unnamed_section callback, used for switching to toc_section. */
19104 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19106 if (DEFAULT_ABI == ABI_AIX
19107 && TARGET_MINIMAL_TOC
19108 && !TARGET_RELOCATABLE)
19110 if (!toc_initialized)
19112 toc_initialized = 1;
19113 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19114 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19115 fprintf (asm_out_file, "\t.tc ");
19116 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19117 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19118 fprintf (asm_out_file, "\n");
19120 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19121 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19122 fprintf (asm_out_file, " = .+32768\n");
19125 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19127 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19128 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19131 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19132 if (!toc_initialized)
19134 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19135 fprintf (asm_out_file, " = .+32768\n");
19136 toc_initialized = 1;
19141 /* Implement TARGET_ASM_INIT_SECTIONS. */
19144 rs6000_elf_asm_init_sections (void)
19147 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19150 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19151 SDATA2_SECTION_ASM_OP);
19154 /* Implement TARGET_SELECT_RTX_SECTION. */
19157 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19158 unsigned HOST_WIDE_INT align)
19160 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19161 return toc_section;
19163 return default_elf_select_rtx_section (mode, x, align);
19166 /* For a SYMBOL_REF, set generic flags and then perform some
19167 target-specific processing.
19169 When the AIX ABI is requested on a non-AIX system, replace the
19170 function name with the real name (with a leading .) rather than the
19171 function descriptor name. This saves a lot of overriding code to
19172 read the prefixes. */
19175 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19177 default_encode_section_info (decl, rtl, first);
19180 && TREE_CODE (decl) == FUNCTION_DECL
19182 && DEFAULT_ABI == ABI_AIX)
19184 rtx sym_ref = XEXP (rtl, 0);
19185 size_t len = strlen (XSTR (sym_ref, 0));
19186 char *str = alloca (len + 2);
19188 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19189 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19194 rs6000_elf_in_small_data_p (tree decl)
19196 if (rs6000_sdata == SDATA_NONE)
19199 /* We want to merge strings, so we never consider them small data. */
19200 if (TREE_CODE (decl) == STRING_CST)
19203 /* Functions are never in the small data area. */
19204 if (TREE_CODE (decl) == FUNCTION_DECL)
19207 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19209 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19210 if (strcmp (section, ".sdata") == 0
19211 || strcmp (section, ".sdata2") == 0
19212 || strcmp (section, ".sbss") == 0
19213 || strcmp (section, ".sbss2") == 0
19214 || strcmp (section, ".PPC.EMB.sdata0") == 0
19215 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19220 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19223 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19224 /* If it's not public, and we're not going to reference it there,
19225 there's no need to put it in the small data section. */
19226 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19233 #endif /* USING_ELFOS_H */
19235 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19238 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
19240 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19243 /* Return a REG that occurs in ADDR with coefficient 1.
19244 ADDR can be effectively incremented by incrementing REG.
19246 r0 is special and we must not select it as an address
19247 register by this routine since our caller will try to
19248 increment the returned register via an "la" instruction. */
19251 find_addr_reg (rtx addr)
19253 while (GET_CODE (addr) == PLUS)
19255 if (GET_CODE (XEXP (addr, 0)) == REG
19256 && REGNO (XEXP (addr, 0)) != 0)
19257 addr = XEXP (addr, 0);
19258 else if (GET_CODE (XEXP (addr, 1)) == REG
19259 && REGNO (XEXP (addr, 1)) != 0)
19260 addr = XEXP (addr, 1);
19261 else if (CONSTANT_P (XEXP (addr, 0)))
19262 addr = XEXP (addr, 1);
19263 else if (CONSTANT_P (XEXP (addr, 1)))
19264 addr = XEXP (addr, 0);
19266 gcc_unreachable ();
19268 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19273 rs6000_fatal_bad_address (rtx op)
19275 fatal_insn ("bad address", op);
19280 static tree branch_island_list = 0;
19282 /* Remember to generate a branch island for far calls to the given
19286 add_compiler_branch_island (tree label_name, tree function_name,
19289 tree branch_island = build_tree_list (function_name, label_name);
19290 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19291 TREE_CHAIN (branch_island) = branch_island_list;
19292 branch_island_list = branch_island;
19295 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19296 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19297 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19298 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19300 /* Generate far-jump branch islands for everything on the
19301 branch_island_list. Invoked immediately after the last instruction
19302 of the epilogue has been emitted; the branch-islands must be
19303 appended to, and contiguous with, the function body. Mach-O stubs
19304 are generated in machopic_output_stub(). */
19307 macho_branch_islands (void)
19310 tree branch_island;
19312 for (branch_island = branch_island_list;
19314 branch_island = TREE_CHAIN (branch_island))
19316 const char *label =
19317 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19319 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19320 char name_buf[512];
19321 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19322 if (name[0] == '*' || name[0] == '&')
19323 strcpy (name_buf, name+1);
19327 strcpy (name_buf+1, name);
19329 strcpy (tmp_buf, "\n");
19330 strcat (tmp_buf, label);
19331 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19332 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19333 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19334 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19337 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19338 strcat (tmp_buf, label);
19339 strcat (tmp_buf, "_pic\n");
19340 strcat (tmp_buf, label);
19341 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19343 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19344 strcat (tmp_buf, name_buf);
19345 strcat (tmp_buf, " - ");
19346 strcat (tmp_buf, label);
19347 strcat (tmp_buf, "_pic)\n");
19349 strcat (tmp_buf, "\tmtlr r0\n");
19351 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19352 strcat (tmp_buf, name_buf);
19353 strcat (tmp_buf, " - ");
19354 strcat (tmp_buf, label);
19355 strcat (tmp_buf, "_pic)\n");
19357 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19361 strcat (tmp_buf, ":\nlis r12,hi16(");
19362 strcat (tmp_buf, name_buf);
19363 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19364 strcat (tmp_buf, name_buf);
19365 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19367 output_asm_insn (tmp_buf, 0);
19368 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19369 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19370 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19371 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19374 branch_island_list = 0;
19377 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19378 already there or not. */
19381 no_previous_def (tree function_name)
19383 tree branch_island;
19384 for (branch_island = branch_island_list;
19386 branch_island = TREE_CHAIN (branch_island))
19387 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19392 /* GET_PREV_LABEL gets the label name from the previous definition of
19396 get_prev_label (tree function_name)
19398 tree branch_island;
19399 for (branch_island = branch_island_list;
19401 branch_island = TREE_CHAIN (branch_island))
19402 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19403 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19407 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19408 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19411 /* KEXTs still need branch islands. */
19412 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19413 || flag_mkernel || flag_apple_kext)
19415 /* INSN is either a function call or a millicode call. It may have an
19416 unconditional jump in its delay slot.
19418 CALL_DEST is the routine we are calling. */
19421 output_call (rtx insn, rtx *operands, int dest_operand_number,
19422 int cookie_operand_number)
19424 static char buf[256];
19425 if (DARWIN_GENERATE_ISLANDS
19426 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19427 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19430 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19432 if (no_previous_def (funname))
19434 rtx label_rtx = gen_label_rtx ();
19435 char *label_buf, temp_buf[256];
19436 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19437 CODE_LABEL_NUMBER (label_rtx));
19438 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19439 labelname = get_identifier (label_buf);
19440 add_compiler_branch_island (labelname, funname, insn_line (insn));
19443 labelname = get_prev_label (funname);
19445 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19446 instruction will reach 'foo', otherwise link as 'bl L42'".
19447 "L42" should be a 'branch island', that will do a far jump to
19448 'foo'. Branch islands are generated in
19449 macho_branch_islands(). */
19450 sprintf (buf, "jbsr %%z%d,%.246s",
19451 dest_operand_number, IDENTIFIER_POINTER (labelname));
19454 sprintf (buf, "bl %%z%d", dest_operand_number);
19458 /* Generate PIC and indirect symbol stubs. */
19461 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19463 unsigned int length;
19464 char *symbol_name, *lazy_ptr_name;
19465 char *local_label_0;
19466 static int label = 0;
19468 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19469 symb = (*targetm.strip_name_encoding) (symb);
19472 length = strlen (symb);
19473 symbol_name = alloca (length + 32);
19474 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19476 lazy_ptr_name = alloca (length + 32);
19477 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19480 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19482 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19486 fprintf (file, "\t.align 5\n");
19488 fprintf (file, "%s:\n", stub);
19489 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19492 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19493 sprintf (local_label_0, "\"L%011d$spb\"", label);
19495 fprintf (file, "\tmflr r0\n");
19496 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19497 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19498 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19499 lazy_ptr_name, local_label_0);
19500 fprintf (file, "\tmtlr r0\n");
19501 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19502 (TARGET_64BIT ? "ldu" : "lwzu"),
19503 lazy_ptr_name, local_label_0);
19504 fprintf (file, "\tmtctr r12\n");
19505 fprintf (file, "\tbctr\n");
19509 fprintf (file, "\t.align 4\n");
19511 fprintf (file, "%s:\n", stub);
19512 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19514 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19515 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19516 (TARGET_64BIT ? "ldu" : "lwzu"),
19518 fprintf (file, "\tmtctr r12\n");
19519 fprintf (file, "\tbctr\n");
19522 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19523 fprintf (file, "%s:\n", lazy_ptr_name);
19524 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19525 fprintf (file, "%sdyld_stub_binding_helper\n",
19526 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19529 /* Legitimize PIC addresses. If the address is already
19530 position-independent, we return ORIG. Newly generated
19531 position-independent addresses go into a reg. This is REG if non
19532 zero, otherwise we allocate register(s) as necessary. */
19534 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19537 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19542 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19543 reg = gen_reg_rtx (Pmode);
19545 if (GET_CODE (orig) == CONST)
19549 if (GET_CODE (XEXP (orig, 0)) == PLUS
19550 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19553 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19555 /* Use a different reg for the intermediate value, as
19556 it will be marked UNCHANGING. */
19557 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
19558 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19561 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19564 if (GET_CODE (offset) == CONST_INT)
19566 if (SMALL_INT (offset))
19567 return plus_constant (base, INTVAL (offset));
19568 else if (! reload_in_progress && ! reload_completed)
19569 offset = force_reg (Pmode, offset);
19572 rtx mem = force_const_mem (Pmode, orig);
19573 return machopic_legitimize_pic_address (mem, Pmode, reg);
19576 return gen_rtx_PLUS (Pmode, base, offset);
19579 /* Fall back on generic machopic code. */
19580 return machopic_legitimize_pic_address (orig, mode, reg);
19583 /* Output a .machine directive for the Darwin assembler, and call
19584 the generic start_file routine. */
19587 rs6000_darwin_file_start (void)
19589 static const struct
19595 { "ppc64", "ppc64", MASK_64BIT },
19596 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19597 { "power4", "ppc970", 0 },
19598 { "G5", "ppc970", 0 },
19599 { "7450", "ppc7450", 0 },
19600 { "7400", "ppc7400", MASK_ALTIVEC },
19601 { "G4", "ppc7400", 0 },
19602 { "750", "ppc750", 0 },
19603 { "740", "ppc750", 0 },
19604 { "G3", "ppc750", 0 },
19605 { "604e", "ppc604e", 0 },
19606 { "604", "ppc604", 0 },
19607 { "603e", "ppc603", 0 },
19608 { "603", "ppc603", 0 },
19609 { "601", "ppc601", 0 },
19610 { NULL, "ppc", 0 } };
19611 const char *cpu_id = "";
19614 rs6000_file_start ();
19615 darwin_file_start ();
19617 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19618 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19619 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19620 && rs6000_select[i].string[0] != '\0')
19621 cpu_id = rs6000_select[i].string;
19623 /* Look through the mapping array. Pick the first name that either
19624 matches the argument, has a bit set in IF_SET that is also set
19625 in the target flags, or has a NULL name. */
19628 while (mapping[i].arg != NULL
19629 && strcmp (mapping[i].arg, cpu_id) != 0
19630 && (mapping[i].if_set & target_flags) == 0)
19633 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19636 #endif /* TARGET_MACHO */
19640 rs6000_elf_reloc_rw_mask (void)
19644 else if (DEFAULT_ABI == ABI_AIX)
19650 /* Record an element in the table of global constructors. SYMBOL is
19651 a SYMBOL_REF of the function to be called; PRIORITY is a number
19652 between 0 and MAX_INIT_PRIORITY.
19654 This differs from default_named_section_asm_out_constructor in
19655 that we have special handling for -mrelocatable. */
19658 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19660 const char *section = ".ctors";
19663 if (priority != DEFAULT_INIT_PRIORITY)
19665 sprintf (buf, ".ctors.%.5u",
19666 /* Invert the numbering so the linker puts us in the proper
19667 order; constructors are run from right to left, and the
19668 linker sorts in increasing order. */
19669 MAX_INIT_PRIORITY - priority);
19673 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19674 assemble_align (POINTER_SIZE);
19676 if (TARGET_RELOCATABLE)
19678 fputs ("\t.long (", asm_out_file);
19679 output_addr_const (asm_out_file, symbol);
19680 fputs (")@fixup\n", asm_out_file);
19683 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19687 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19689 const char *section = ".dtors";
19692 if (priority != DEFAULT_INIT_PRIORITY)
19694 sprintf (buf, ".dtors.%.5u",
19695 /* Invert the numbering so the linker puts us in the proper
19696 order; constructors are run from right to left, and the
19697 linker sorts in increasing order. */
19698 MAX_INIT_PRIORITY - priority);
19702 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19703 assemble_align (POINTER_SIZE);
19705 if (TARGET_RELOCATABLE)
19707 fputs ("\t.long (", asm_out_file);
19708 output_addr_const (asm_out_file, symbol);
19709 fputs (")@fixup\n", asm_out_file);
19712 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19716 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19720 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19721 ASM_OUTPUT_LABEL (file, name);
19722 fputs (DOUBLE_INT_ASM_OP, file);
19723 rs6000_output_function_entry (file, name);
19724 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19727 fputs ("\t.size\t", file);
19728 assemble_name (file, name);
19729 fputs (",24\n\t.type\t.", file);
19730 assemble_name (file, name);
19731 fputs (",@function\n", file);
19732 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19734 fputs ("\t.globl\t.", file);
19735 assemble_name (file, name);
19740 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19741 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19742 rs6000_output_function_entry (file, name);
19743 fputs (":\n", file);
19747 if (TARGET_RELOCATABLE
19748 && !TARGET_SECURE_PLT
19749 && (get_pool_size () != 0 || current_function_profile)
19754 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19756 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19757 fprintf (file, "\t.long ");
19758 assemble_name (file, buf);
19760 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19761 assemble_name (file, buf);
19765 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19766 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19768 if (DEFAULT_ABI == ABI_AIX)
19770 const char *desc_name, *orig_name;
19772 orig_name = (*targetm.strip_name_encoding) (name);
19773 desc_name = orig_name;
19774 while (*desc_name == '.')
19777 if (TREE_PUBLIC (decl))
19778 fprintf (file, "\t.globl %s\n", desc_name);
19780 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19781 fprintf (file, "%s:\n", desc_name);
19782 fprintf (file, "\t.long %s\n", orig_name);
19783 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19784 if (DEFAULT_ABI == ABI_AIX)
19785 fputs ("\t.long 0\n", file);
19786 fprintf (file, "\t.previous\n");
19788 ASM_OUTPUT_LABEL (file, name);
19792 rs6000_elf_end_indicate_exec_stack (void)
19795 file_end_indicate_exec_stack ();
19801 rs6000_xcoff_asm_output_anchor (rtx symbol)
19805 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19806 SYMBOL_REF_BLOCK_OFFSET (symbol));
19807 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19811 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19813 fputs (GLOBAL_ASM_OP, stream);
19814 RS6000_OUTPUT_BASENAME (stream, name);
19815 putc ('\n', stream);
19818 /* A get_unnamed_decl callback, used for read-only sections. PTR
19819 points to the section string variable. */
19822 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19824 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19825 *(const char *const *) directive);
19828 /* Likewise for read-write sections. */
19831 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19833 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19834 *(const char *const *) directive);
19837 /* A get_unnamed_section callback, used for switching to toc_section. */
19840 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19842 if (TARGET_MINIMAL_TOC)
19844 /* toc_section is always selected at least once from
19845 rs6000_xcoff_file_start, so this is guaranteed to
19846 always be defined once and only once in each file. */
19847 if (!toc_initialized)
19849 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19850 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19851 toc_initialized = 1;
19853 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19854 (TARGET_32BIT ? "" : ",3"));
19857 fputs ("\t.toc\n", asm_out_file);
19860 /* Implement TARGET_ASM_INIT_SECTIONS. */
19863 rs6000_xcoff_asm_init_sections (void)
19865 read_only_data_section
19866 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19867 &xcoff_read_only_section_name);
19869 private_data_section
19870 = get_unnamed_section (SECTION_WRITE,
19871 rs6000_xcoff_output_readwrite_section_asm_op,
19872 &xcoff_private_data_section_name);
19874 read_only_private_data_section
19875 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19876 &xcoff_private_data_section_name);
19879 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19881 readonly_data_section = read_only_data_section;
19882 exception_section = data_section;
19886 rs6000_xcoff_reloc_rw_mask (void)
19892 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19893 tree decl ATTRIBUTE_UNUSED)
19896 static const char * const suffix[3] = { "PR", "RO", "RW" };
19898 if (flags & SECTION_CODE)
19900 else if (flags & SECTION_WRITE)
19905 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19906 (flags & SECTION_CODE) ? "." : "",
19907 name, suffix[smclass], flags & SECTION_ENTSIZE);
19911 rs6000_xcoff_select_section (tree decl, int reloc,
19912 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19914 if (decl_readonly_section (decl, reloc))
19916 if (TREE_PUBLIC (decl))
19917 return read_only_data_section;
19919 return read_only_private_data_section;
19923 if (TREE_PUBLIC (decl))
19924 return data_section;
19926 return private_data_section;
19931 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19935 /* Use select_section for private and uninitialized data. */
19936 if (!TREE_PUBLIC (decl)
19937 || DECL_COMMON (decl)
19938 || DECL_INITIAL (decl) == NULL_TREE
19939 || DECL_INITIAL (decl) == error_mark_node
19940 || (flag_zero_initialized_in_bss
19941 && initializer_zerop (DECL_INITIAL (decl))))
19944 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19945 name = (*targetm.strip_name_encoding) (name);
19946 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19949 /* Select section for constant in constant pool.
19951 On RS/6000, all constants are in the private read-only data area.
19952 However, if this is being placed in the TOC it must be output as a
19956 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19957 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19959 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19960 return toc_section;
19962 return read_only_private_data_section;
19965 /* Remove any trailing [DS] or the like from the symbol name. */
19967 static const char *
19968 rs6000_xcoff_strip_name_encoding (const char *name)
19973 len = strlen (name);
19974 if (name[len - 1] == ']')
19975 return ggc_alloc_string (name, len - 4);
19980 /* Section attributes. AIX is always PIC. */
19982 static unsigned int
19983 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
19985 unsigned int align;
19986 unsigned int flags = default_section_type_flags (decl, name, reloc);
19988 /* Align to at least UNIT size. */
19989 if (flags & SECTION_CODE)
19990 align = MIN_UNITS_PER_WORD;
19992 /* Increase alignment of large objects if not already stricter. */
19993 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
19994 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
19995 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
19997 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
20000 /* Output at beginning of assembler file.
20002 Initialize the section names for the RS/6000 at this point.
20004 Specify filename, including full path, to assembler.
20006 We want to go into the TOC section so at least one .toc will be emitted.
20007 Also, in order to output proper .bs/.es pairs, we need at least one static
20008 [RW] section emitted.
20010 Finally, declare mcount when profiling to make the assembler happy. */
20013 rs6000_xcoff_file_start (void)
20015 rs6000_gen_section_name (&xcoff_bss_section_name,
20016 main_input_filename, ".bss_");
20017 rs6000_gen_section_name (&xcoff_private_data_section_name,
20018 main_input_filename, ".rw_");
20019 rs6000_gen_section_name (&xcoff_read_only_section_name,
20020 main_input_filename, ".ro_");
20022 fputs ("\t.file\t", asm_out_file);
20023 output_quoted_string (asm_out_file, main_input_filename);
20024 fputc ('\n', asm_out_file);
20025 if (write_symbols != NO_DEBUG)
20026 switch_to_section (private_data_section);
20027 switch_to_section (text_section);
20029 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
20030 rs6000_file_start ();
20033 /* Output at end of assembler file.
20034 On the RS/6000, referencing data should automatically pull in text. */
20037 rs6000_xcoff_file_end (void)
20039 switch_to_section (text_section);
20040 fputs ("_section_.text:\n", asm_out_file);
20041 switch_to_section (data_section);
20042 fputs (TARGET_32BIT
20043 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20046 #endif /* TARGET_XCOFF */
20048 /* Compute a (partial) cost for rtx X. Return true if the complete
20049 cost has been computed, and false if subexpressions should be
20050 scanned. In either case, *TOTAL contains the cost result. */
20053 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
20055 enum machine_mode mode = GET_MODE (x);
20059 /* On the RS/6000, if it is valid in the insn, it is free. */
20061 if (((outer_code == SET
20062 || outer_code == PLUS
20063 || outer_code == MINUS)
20064 && (satisfies_constraint_I (x)
20065 || satisfies_constraint_L (x)))
20066 || (outer_code == AND
20067 && (satisfies_constraint_K (x)
20069 ? satisfies_constraint_L (x)
20070 : satisfies_constraint_J (x))
20071 || mask_operand (x, mode)
20073 && mask64_operand (x, DImode))))
20074 || ((outer_code == IOR || outer_code == XOR)
20075 && (satisfies_constraint_K (x)
20077 ? satisfies_constraint_L (x)
20078 : satisfies_constraint_J (x))))
20079 || outer_code == ASHIFT
20080 || outer_code == ASHIFTRT
20081 || outer_code == LSHIFTRT
20082 || outer_code == ROTATE
20083 || outer_code == ROTATERT
20084 || outer_code == ZERO_EXTRACT
20085 || (outer_code == MULT
20086 && satisfies_constraint_I (x))
20087 || ((outer_code == DIV || outer_code == UDIV
20088 || outer_code == MOD || outer_code == UMOD)
20089 && exact_log2 (INTVAL (x)) >= 0)
20090 || (outer_code == COMPARE
20091 && (satisfies_constraint_I (x)
20092 || satisfies_constraint_K (x)))
20093 || (outer_code == EQ
20094 && (satisfies_constraint_I (x)
20095 || satisfies_constraint_K (x)
20097 ? satisfies_constraint_L (x)
20098 : satisfies_constraint_J (x))))
20099 || (outer_code == GTU
20100 && satisfies_constraint_I (x))
20101 || (outer_code == LTU
20102 && satisfies_constraint_P (x)))
20107 else if ((outer_code == PLUS
20108 && reg_or_add_cint_operand (x, VOIDmode))
20109 || (outer_code == MINUS
20110 && reg_or_sub_cint_operand (x, VOIDmode))
20111 || ((outer_code == SET
20112 || outer_code == IOR
20113 || outer_code == XOR)
20115 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20117 *total = COSTS_N_INSNS (1);
20123 if (mode == DImode && code == CONST_DOUBLE)
20125 if ((outer_code == IOR || outer_code == XOR)
20126 && CONST_DOUBLE_HIGH (x) == 0
20127 && (CONST_DOUBLE_LOW (x)
20128 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20133 else if ((outer_code == AND && and64_2_operand (x, DImode))
20134 || ((outer_code == SET
20135 || outer_code == IOR
20136 || outer_code == XOR)
20137 && CONST_DOUBLE_HIGH (x) == 0))
20139 *total = COSTS_N_INSNS (1);
20149 /* When optimizing for size, MEM should be slightly more expensive
20150 than generating address, e.g., (plus (reg) (const)).
20151 L1 cache latency is about two instructions. */
20152 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20160 if (mode == DFmode)
20162 if (GET_CODE (XEXP (x, 0)) == MULT)
20164 /* FNMA accounted in outer NEG. */
20165 if (outer_code == NEG)
20166 *total = rs6000_cost->dmul - rs6000_cost->fp;
20168 *total = rs6000_cost->dmul;
20171 *total = rs6000_cost->fp;
20173 else if (mode == SFmode)
20175 /* FNMA accounted in outer NEG. */
20176 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20179 *total = rs6000_cost->fp;
20182 *total = COSTS_N_INSNS (1);
20186 if (mode == DFmode)
20188 if (GET_CODE (XEXP (x, 0)) == MULT
20189 || GET_CODE (XEXP (x, 1)) == MULT)
20191 /* FNMA accounted in outer NEG. */
20192 if (outer_code == NEG)
20193 *total = rs6000_cost->dmul - rs6000_cost->fp;
20195 *total = rs6000_cost->dmul;
20198 *total = rs6000_cost->fp;
20200 else if (mode == SFmode)
20202 /* FNMA accounted in outer NEG. */
20203 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20206 *total = rs6000_cost->fp;
20209 *total = COSTS_N_INSNS (1);
20213 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20214 && satisfies_constraint_I (XEXP (x, 1)))
20216 if (INTVAL (XEXP (x, 1)) >= -256
20217 && INTVAL (XEXP (x, 1)) <= 255)
20218 *total = rs6000_cost->mulsi_const9;
20220 *total = rs6000_cost->mulsi_const;
20222 /* FMA accounted in outer PLUS/MINUS. */
20223 else if ((mode == DFmode || mode == SFmode)
20224 && (outer_code == PLUS || outer_code == MINUS))
20226 else if (mode == DFmode)
20227 *total = rs6000_cost->dmul;
20228 else if (mode == SFmode)
20229 *total = rs6000_cost->fp;
20230 else if (mode == DImode)
20231 *total = rs6000_cost->muldi;
20233 *total = rs6000_cost->mulsi;
20238 if (FLOAT_MODE_P (mode))
20240 *total = mode == DFmode ? rs6000_cost->ddiv
20241 : rs6000_cost->sdiv;
20248 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20249 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20251 if (code == DIV || code == MOD)
20253 *total = COSTS_N_INSNS (2);
20256 *total = COSTS_N_INSNS (1);
20260 if (GET_MODE (XEXP (x, 1)) == DImode)
20261 *total = rs6000_cost->divdi;
20263 *total = rs6000_cost->divsi;
20265 /* Add in shift and subtract for MOD. */
20266 if (code == MOD || code == UMOD)
20267 *total += COSTS_N_INSNS (2);
20271 *total = COSTS_N_INSNS (4);
20275 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20286 *total = COSTS_N_INSNS (1);
20294 /* Handle mul_highpart. */
20295 if (outer_code == TRUNCATE
20296 && GET_CODE (XEXP (x, 0)) == MULT)
20298 if (mode == DImode)
20299 *total = rs6000_cost->muldi;
20301 *total = rs6000_cost->mulsi;
20304 else if (outer_code == AND)
20307 *total = COSTS_N_INSNS (1);
20312 if (GET_CODE (XEXP (x, 0)) == MEM)
20315 *total = COSTS_N_INSNS (1);
20321 if (!FLOAT_MODE_P (mode))
20323 *total = COSTS_N_INSNS (1);
20329 case UNSIGNED_FLOAT:
20332 case FLOAT_TRUNCATE:
20333 *total = rs6000_cost->fp;
20337 if (mode == DFmode)
20340 *total = rs6000_cost->fp;
20344 switch (XINT (x, 1))
20347 *total = rs6000_cost->fp;
20359 *total = COSTS_N_INSNS (1);
20362 else if (FLOAT_MODE_P (mode)
20363 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20365 *total = rs6000_cost->fp;
20373 /* Carry bit requires mode == Pmode.
20374 NEG or PLUS already counted so only add one. */
20376 && (outer_code == NEG || outer_code == PLUS))
20378 *total = COSTS_N_INSNS (1);
20381 if (outer_code == SET)
20383 if (XEXP (x, 1) == const0_rtx)
20385 *total = COSTS_N_INSNS (2);
20388 else if (mode == Pmode)
20390 *total = COSTS_N_INSNS (3);
20399 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20401 *total = COSTS_N_INSNS (2);
20405 if (outer_code == COMPARE)
20419 /* A C expression returning the cost of moving data from a register of class
20420 CLASS1 to one of CLASS2. */
20423 rs6000_register_move_cost (enum machine_mode mode,
20424 enum reg_class from, enum reg_class to)
20426 /* Moves from/to GENERAL_REGS. */
20427 if (reg_classes_intersect_p (to, GENERAL_REGS)
20428 || reg_classes_intersect_p (from, GENERAL_REGS))
20430 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20433 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20434 return (rs6000_memory_move_cost (mode, from, 0)
20435 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20437 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20439 else if (from == CR_REGS)
20443 /* A move will cost one instruction per GPR moved. */
20444 return 2 * hard_regno_nregs[0][mode];
20447 /* Moving between two similar registers is just one instruction. */
20448 else if (reg_classes_intersect_p (to, from))
20449 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20451 /* Everything else has to go through GENERAL_REGS. */
20453 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20454 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20457 /* A C expressions returning the cost of moving data of MODE from a register to
20461 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20462 int in ATTRIBUTE_UNUSED)
20464 if (reg_classes_intersect_p (class, GENERAL_REGS))
20465 return 4 * hard_regno_nregs[0][mode];
20466 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20467 return 4 * hard_regno_nregs[32][mode];
20468 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20469 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20471 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20474 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20475 Assumes no trapping math and finite arguments. */
20478 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20480 rtx x0, e0, e1, y1, u0, v0, one;
20482 x0 = gen_reg_rtx (SFmode);
20483 e0 = gen_reg_rtx (SFmode);
20484 e1 = gen_reg_rtx (SFmode);
20485 y1 = gen_reg_rtx (SFmode);
20486 u0 = gen_reg_rtx (SFmode);
20487 v0 = gen_reg_rtx (SFmode);
20488 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20490 /* x0 = 1./d estimate */
20491 emit_insn (gen_rtx_SET (VOIDmode, x0,
20492 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20494 /* e0 = 1. - d * x0 */
20495 emit_insn (gen_rtx_SET (VOIDmode, e0,
20496 gen_rtx_MINUS (SFmode, one,
20497 gen_rtx_MULT (SFmode, d, x0))));
20498 /* e1 = e0 + e0 * e0 */
20499 emit_insn (gen_rtx_SET (VOIDmode, e1,
20500 gen_rtx_PLUS (SFmode,
20501 gen_rtx_MULT (SFmode, e0, e0), e0)));
20502 /* y1 = x0 + e1 * x0 */
20503 emit_insn (gen_rtx_SET (VOIDmode, y1,
20504 gen_rtx_PLUS (SFmode,
20505 gen_rtx_MULT (SFmode, e1, x0), x0)));
20507 emit_insn (gen_rtx_SET (VOIDmode, u0,
20508 gen_rtx_MULT (SFmode, n, y1)));
20509 /* v0 = n - d * u0 */
20510 emit_insn (gen_rtx_SET (VOIDmode, v0,
20511 gen_rtx_MINUS (SFmode, n,
20512 gen_rtx_MULT (SFmode, d, u0))));
20513 /* res = u0 + v0 * y1 */
20514 emit_insn (gen_rtx_SET (VOIDmode, res,
20515 gen_rtx_PLUS (SFmode,
20516 gen_rtx_MULT (SFmode, v0, y1), u0)));
20519 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20520 Assumes no trapping math and finite arguments. */
20523 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20525 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20527 x0 = gen_reg_rtx (DFmode);
20528 e0 = gen_reg_rtx (DFmode);
20529 e1 = gen_reg_rtx (DFmode);
20530 e2 = gen_reg_rtx (DFmode);
20531 y1 = gen_reg_rtx (DFmode);
20532 y2 = gen_reg_rtx (DFmode);
20533 y3 = gen_reg_rtx (DFmode);
20534 u0 = gen_reg_rtx (DFmode);
20535 v0 = gen_reg_rtx (DFmode);
20536 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20538 /* x0 = 1./d estimate */
20539 emit_insn (gen_rtx_SET (VOIDmode, x0,
20540 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20542 /* e0 = 1. - d * x0 */
20543 emit_insn (gen_rtx_SET (VOIDmode, e0,
20544 gen_rtx_MINUS (DFmode, one,
20545 gen_rtx_MULT (SFmode, d, x0))));
20546 /* y1 = x0 + e0 * x0 */
20547 emit_insn (gen_rtx_SET (VOIDmode, y1,
20548 gen_rtx_PLUS (DFmode,
20549 gen_rtx_MULT (DFmode, e0, x0), x0)));
20551 emit_insn (gen_rtx_SET (VOIDmode, e1,
20552 gen_rtx_MULT (DFmode, e0, e0)));
20553 /* y2 = y1 + e1 * y1 */
20554 emit_insn (gen_rtx_SET (VOIDmode, y2,
20555 gen_rtx_PLUS (DFmode,
20556 gen_rtx_MULT (DFmode, e1, y1), y1)));
20558 emit_insn (gen_rtx_SET (VOIDmode, e2,
20559 gen_rtx_MULT (DFmode, e1, e1)));
20560 /* y3 = y2 + e2 * y2 */
20561 emit_insn (gen_rtx_SET (VOIDmode, y3,
20562 gen_rtx_PLUS (DFmode,
20563 gen_rtx_MULT (DFmode, e2, y2), y2)));
20565 emit_insn (gen_rtx_SET (VOIDmode, u0,
20566 gen_rtx_MULT (DFmode, n, y3)));
20567 /* v0 = n - d * u0 */
20568 emit_insn (gen_rtx_SET (VOIDmode, v0,
20569 gen_rtx_MINUS (DFmode, n,
20570 gen_rtx_MULT (DFmode, d, u0))));
20571 /* res = u0 + v0 * y3 */
20572 emit_insn (gen_rtx_SET (VOIDmode, res,
20573 gen_rtx_PLUS (DFmode,
20574 gen_rtx_MULT (DFmode, v0, y3), u0)));
20578 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20579 target, and SRC is the argument operand. */
20582 rs6000_emit_popcount (rtx dst, rtx src)
20584 enum machine_mode mode = GET_MODE (dst);
20587 tmp1 = gen_reg_rtx (mode);
20589 if (mode == SImode)
20591 emit_insn (gen_popcntbsi2 (tmp1, src));
20592 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20594 tmp2 = force_reg (SImode, tmp2);
20595 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20599 emit_insn (gen_popcntbdi2 (tmp1, src));
20600 tmp2 = expand_mult (DImode, tmp1,
20601 GEN_INT ((HOST_WIDE_INT)
20602 0x01010101 << 32 | 0x01010101),
20604 tmp2 = force_reg (DImode, tmp2);
20605 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20610 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20611 target, and SRC is the argument operand. */
20614 rs6000_emit_parity (rtx dst, rtx src)
20616 enum machine_mode mode = GET_MODE (dst);
20619 tmp = gen_reg_rtx (mode);
20620 if (mode == SImode)
20622 /* Is mult+shift >= shift+xor+shift+xor? */
20623 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20625 rtx tmp1, tmp2, tmp3, tmp4;
20627 tmp1 = gen_reg_rtx (SImode);
20628 emit_insn (gen_popcntbsi2 (tmp1, src));
20630 tmp2 = gen_reg_rtx (SImode);
20631 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20632 tmp3 = gen_reg_rtx (SImode);
20633 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20635 tmp4 = gen_reg_rtx (SImode);
20636 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20637 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20640 rs6000_emit_popcount (tmp, src);
20641 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20645 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20646 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20648 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20650 tmp1 = gen_reg_rtx (DImode);
20651 emit_insn (gen_popcntbdi2 (tmp1, src));
20653 tmp2 = gen_reg_rtx (DImode);
20654 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20655 tmp3 = gen_reg_rtx (DImode);
20656 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20658 tmp4 = gen_reg_rtx (DImode);
20659 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20660 tmp5 = gen_reg_rtx (DImode);
20661 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20663 tmp6 = gen_reg_rtx (DImode);
20664 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20665 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20668 rs6000_emit_popcount (tmp, src);
20669 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20673 /* Return an RTX representing where to find the function value of a
20674 function returning MODE. */
20676 rs6000_complex_function_value (enum machine_mode mode)
20678 unsigned int regno;
20680 enum machine_mode inner = GET_MODE_INNER (mode);
20681 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20683 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20684 regno = FP_ARG_RETURN;
20687 regno = GP_ARG_RETURN;
20689 /* 32-bit is OK since it'll go in r3/r4. */
20690 if (TARGET_32BIT && inner_bytes >= 4)
20691 return gen_rtx_REG (mode, regno);
20694 if (inner_bytes >= 8)
20695 return gen_rtx_REG (mode, regno);
20697 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20699 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20700 GEN_INT (inner_bytes));
20701 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20704 /* Define how to find the value returned by a function.
20705 VALTYPE is the data type of the value (as a tree).
20706 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20707 otherwise, FUNC is 0.
20709 On the SPE, both FPs and vectors are returned in r3.
20711 On RS/6000 an integer value is in r3 and a floating-point value is in
20712 fp1, unless -msoft-float. */
20715 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20717 enum machine_mode mode;
20718 unsigned int regno;
20720 /* Special handling for structs in darwin64. */
20721 if (rs6000_darwin64_abi
20722 && TYPE_MODE (valtype) == BLKmode
20723 && TREE_CODE (valtype) == RECORD_TYPE
20724 && int_size_in_bytes (valtype) > 0)
20726 CUMULATIVE_ARGS valcum;
20730 valcum.fregno = FP_ARG_MIN_REG;
20731 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20732 /* Do a trial code generation as if this were going to be passed as
20733 an argument; if any part goes in memory, we return NULL. */
20734 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20737 /* Otherwise fall through to standard ABI rules. */
20740 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20742 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20743 return gen_rtx_PARALLEL (DImode,
20745 gen_rtx_EXPR_LIST (VOIDmode,
20746 gen_rtx_REG (SImode, GP_ARG_RETURN),
20748 gen_rtx_EXPR_LIST (VOIDmode,
20749 gen_rtx_REG (SImode,
20750 GP_ARG_RETURN + 1),
20753 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20755 return gen_rtx_PARALLEL (DCmode,
20757 gen_rtx_EXPR_LIST (VOIDmode,
20758 gen_rtx_REG (SImode, GP_ARG_RETURN),
20760 gen_rtx_EXPR_LIST (VOIDmode,
20761 gen_rtx_REG (SImode,
20762 GP_ARG_RETURN + 1),
20764 gen_rtx_EXPR_LIST (VOIDmode,
20765 gen_rtx_REG (SImode,
20766 GP_ARG_RETURN + 2),
20768 gen_rtx_EXPR_LIST (VOIDmode,
20769 gen_rtx_REG (SImode,
20770 GP_ARG_RETURN + 3),
20774 mode = TYPE_MODE (valtype);
20775 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20776 || POINTER_TYPE_P (valtype))
20777 mode = TARGET_32BIT ? SImode : DImode;
20779 if (DECIMAL_FLOAT_MODE_P (mode))
20781 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20786 gcc_unreachable ();
20788 regno = GP_ARG_RETURN;
20791 regno = FP_ARG_RETURN;
20794 /* Use f2:f3 specified by the ABI. */
20795 regno = FP_ARG_RETURN + 1;
20800 regno = GP_ARG_RETURN;
20802 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20803 regno = FP_ARG_RETURN;
20804 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20805 && targetm.calls.split_complex_arg)
20806 return rs6000_complex_function_value (mode);
20807 else if (TREE_CODE (valtype) == VECTOR_TYPE
20808 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20809 && ALTIVEC_VECTOR_MODE (mode))
20810 regno = ALTIVEC_ARG_RETURN;
20811 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20812 && (mode == DFmode || mode == DCmode
20813 || mode == TFmode || mode == TCmode))
20814 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20816 regno = GP_ARG_RETURN;
20818 return gen_rtx_REG (mode, regno);
20821 /* Define how to find the value returned by a library function
20822 assuming the value has mode MODE. */
20824 rs6000_libcall_value (enum machine_mode mode)
20826 unsigned int regno;
20828 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20830 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20831 return gen_rtx_PARALLEL (DImode,
20833 gen_rtx_EXPR_LIST (VOIDmode,
20834 gen_rtx_REG (SImode, GP_ARG_RETURN),
20836 gen_rtx_EXPR_LIST (VOIDmode,
20837 gen_rtx_REG (SImode,
20838 GP_ARG_RETURN + 1),
20842 if (DECIMAL_FLOAT_MODE_P (mode))
20844 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20849 gcc_unreachable ();
20851 regno = GP_ARG_RETURN;
20854 regno = FP_ARG_RETURN;
20857 /* Use f2:f3 specified by the ABI. */
20858 regno = FP_ARG_RETURN + 1;
20863 regno = GP_ARG_RETURN;
20865 else if (SCALAR_FLOAT_MODE_P (mode)
20866 && TARGET_HARD_FLOAT && TARGET_FPRS)
20867 regno = FP_ARG_RETURN;
20868 else if (ALTIVEC_VECTOR_MODE (mode)
20869 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20870 regno = ALTIVEC_ARG_RETURN;
20871 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20872 return rs6000_complex_function_value (mode);
20873 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20874 && (mode == DFmode || mode == DCmode
20875 || mode == TFmode || mode == TCmode))
20876 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20878 regno = GP_ARG_RETURN;
20880 return gen_rtx_REG (mode, regno);
20883 /* Define the offset between two registers, FROM to be eliminated and its
20884 replacement TO, at the start of a routine. */
20886 rs6000_initial_elimination_offset (int from, int to)
20888 rs6000_stack_t *info = rs6000_stack_info ();
20889 HOST_WIDE_INT offset;
20891 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20892 offset = info->push_p ? 0 : -info->total_size;
20893 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20895 offset = info->push_p ? 0 : -info->total_size;
20896 if (FRAME_GROWS_DOWNWARD)
20897 offset += info->fixed_size + info->vars_size + info->parm_size;
20899 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20900 offset = FRAME_GROWS_DOWNWARD
20901 ? info->fixed_size + info->vars_size + info->parm_size
20903 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20904 offset = info->total_size;
20905 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20906 offset = info->push_p ? info->total_size : 0;
20907 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20910 gcc_unreachable ();
20915 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20918 rs6000_is_opaque_type (tree type)
20920 return (type == opaque_V2SI_type_node
20921 || type == opaque_V2SF_type_node
20922 || type == opaque_p_V2SI_type_node
20923 || type == opaque_V4SI_type_node);
20927 rs6000_dwarf_register_span (rtx reg)
20932 && (SPE_VECTOR_MODE (GET_MODE (reg))
20933 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20938 regno = REGNO (reg);
20940 /* The duality of the SPE register size wreaks all kinds of havoc.
20941 This is a way of distinguishing r0 in 32-bits from r0 in
20944 gen_rtx_PARALLEL (VOIDmode,
20947 gen_rtx_REG (SImode, regno + 1200),
20948 gen_rtx_REG (SImode, regno))
20950 gen_rtx_REG (SImode, regno),
20951 gen_rtx_REG (SImode, regno + 1200)));
20954 /* Fill in sizes for SPE register high parts in table used by unwinder. */
20957 rs6000_init_dwarf_reg_sizes_extra (tree address)
20962 enum machine_mode mode = TYPE_MODE (char_type_node);
20963 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
20964 rtx mem = gen_rtx_MEM (BLKmode, addr);
20965 rtx value = gen_int_mode (4, mode);
20967 for (i = 1201; i < 1232; i++)
20969 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
20970 HOST_WIDE_INT offset
20971 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
20973 emit_move_insn (adjust_address (mem, mode, offset), value);
20978 /* Map internal gcc register numbers to DWARF2 register numbers. */
20981 rs6000_dbx_register_number (unsigned int regno)
20983 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
20985 if (regno == MQ_REGNO)
20987 if (regno == LR_REGNO)
20989 if (regno == CTR_REGNO)
20991 if (CR_REGNO_P (regno))
20992 return regno - CR0_REGNO + 86;
20993 if (regno == XER_REGNO)
20995 if (ALTIVEC_REGNO_P (regno))
20996 return regno - FIRST_ALTIVEC_REGNO + 1124;
20997 if (regno == VRSAVE_REGNO)
20999 if (regno == VSCR_REGNO)
21001 if (regno == SPE_ACC_REGNO)
21003 if (regno == SPEFSCR_REGNO)
21005 /* SPE high reg number. We get these values of regno from
21006 rs6000_dwarf_register_span. */
21007 gcc_assert (regno >= 1200 && regno < 1232);
21011 /* target hook eh_return_filter_mode */
21012 static enum machine_mode
21013 rs6000_eh_return_filter_mode (void)
21015 return TARGET_32BIT ? SImode : word_mode;
21018 /* Target hook for scalar_mode_supported_p. */
21020 rs6000_scalar_mode_supported_p (enum machine_mode mode)
21022 if (DECIMAL_FLOAT_MODE_P (mode))
21025 return default_scalar_mode_supported_p (mode);
21028 /* Target hook for vector_mode_supported_p. */
21030 rs6000_vector_mode_supported_p (enum machine_mode mode)
21033 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
21036 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
21043 /* Target hook for invalid_arg_for_unprototyped_fn. */
21044 static const char *
21045 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
21047 return (!rs6000_darwin64_abi
21049 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
21050 && (funcdecl == NULL_TREE
21051 || (TREE_CODE (funcdecl) == FUNCTION_DECL
21052 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
21053 ? N_("AltiVec argument passed to unprototyped function")
21057 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21058 setup by using __stack_chk_fail_local hidden function instead of
21059 calling __stack_chk_fail directly. Otherwise it is better to call
21060 __stack_chk_fail directly. */
21063 rs6000_stack_protect_fail (void)
21065 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
21066 ? default_hidden_stack_protect_fail ()
21067 : default_external_stack_protect_fail ();
21070 #include "gt-rs6000.h"