1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu;
138 struct rs6000_cpu_select rs6000_select[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 static GTY(()) bool rs6000_cell_dont_microcode;
148 /* Always emit branch hint bits. */
149 static GTY(()) bool rs6000_always_hint;
151 /* Schedule instructions for group formation. */
152 static GTY(()) bool rs6000_sched_groups;
154 /* Align branch targets. */
155 static GTY(()) bool rs6000_align_branch_targets;
157 /* Support for -msched-costly-dep option. */
158 const char *rs6000_sched_costly_dep_str;
159 enum rs6000_dependence_cost rs6000_sched_costly_dep;
161 /* Support for -minsert-sched-nops option. */
162 const char *rs6000_sched_insert_nops_str;
163 enum rs6000_nop_insertion rs6000_sched_insert_nops;
165 /* Support targetm.vectorize.builtin_mask_for_load. */
166 static GTY(()) tree altivec_builtin_mask_for_load;
168 /* Size of long double. */
169 int rs6000_long_double_type_size;
171 /* IEEE quad extended precision long double. */
174 /* Nonzero to use AltiVec ABI. */
175 int rs6000_altivec_abi;
177 /* Nonzero if we want SPE SIMD instructions. */
180 /* Nonzero if we want SPE ABI extensions. */
183 /* Nonzero to use isel instructions. */
186 /* Nonzero if floating point operations are done in the GPRs. */
187 int rs6000_float_gprs = 0;
189 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
190 int rs6000_darwin64_abi;
192 /* Set to nonzero once AIX common-mode calls have been defined. */
193 static GTY(()) int common_mode_defined;
195 /* Save information from a "cmpxx" operation until the branch or scc is
197 rtx rs6000_compare_op0, rs6000_compare_op1;
198 int rs6000_compare_fp_p;
200 /* Label number of label created for -mrelocatable, to call to so we can
201 get the address of the GOT section */
202 int rs6000_pic_labelno;
205 /* Which abi to adhere to */
206 const char *rs6000_abi_name;
208 /* Semantics of the small data area */
209 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
211 /* Which small data model to use */
212 const char *rs6000_sdata_name = (char *)0;
214 /* Counter for labels which are to be placed in .fixup. */
215 int fixuplabelno = 0;
218 /* Bit size of immediate TLS offsets and string from which it is decoded. */
219 int rs6000_tls_size = 32;
220 const char *rs6000_tls_size_string;
222 /* ABI enumeration available for subtarget to use. */
223 enum rs6000_abi rs6000_current_abi;
225 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
229 const char *rs6000_debug_name;
230 int rs6000_debug_stack; /* debug stack applications */
231 int rs6000_debug_arg; /* debug argument handling */
233 /* Value is TRUE if register/mode pair is acceptable. */
234 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
236 /* Built in types. */
238 tree rs6000_builtin_types[RS6000_BTI_MAX];
239 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
241 const char *rs6000_traceback_name;
243 traceback_default = 0,
249 /* Flag to say the TOC is initialized */
251 char toc_label_name[10];
253 /* Cached value of rs6000_variable_issue. This is cached in
254 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
255 static short cached_can_issue_more;
257 static GTY(()) section *read_only_data_section;
258 static GTY(()) section *private_data_section;
259 static GTY(()) section *read_only_private_data_section;
260 static GTY(()) section *sdata2_section;
261 static GTY(()) section *toc_section;
263 /* Control alignment for fields within structures. */
264 /* String from -malign-XXXXX. */
265 int rs6000_alignment_flags;
267 /* True for any options that were explicitly set. */
269 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
270 bool alignment; /* True if -malign- was used. */
271 bool spe_abi; /* True if -mabi=spe/no-spe was used. */
272 bool altivec_abi; /* True if -mabi=altivec/no-altivec used. */
273 bool spe; /* True if -mspe= was used. */
274 bool float_gprs; /* True if -mfloat-gprs= was used. */
275 bool isel; /* True if -misel was used. */
276 bool long_double; /* True if -mlong-double- was used. */
277 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
278 bool vrsave; /* True if -mvrsave was used. */
279 } rs6000_explicit_options;
281 struct builtin_description
283 /* mask is not const because we're going to alter it below. This
284 nonsense will go away when we rewrite the -march infrastructure
285 to give us more target flag bits. */
287 const enum insn_code icode;
288 const char *const name;
289 const enum rs6000_builtins code;
292 /* Target cpu costs. */
294 struct processor_costs {
295 const int mulsi; /* cost of SImode multiplication. */
296 const int mulsi_const; /* cost of SImode multiplication by constant. */
297 const int mulsi_const9; /* cost of SImode mult by short constant. */
298 const int muldi; /* cost of DImode multiplication. */
299 const int divsi; /* cost of SImode division. */
300 const int divdi; /* cost of DImode division. */
301 const int fp; /* cost of simple SFmode and DFmode insns. */
302 const int dmul; /* cost of DFmode multiplication (and fmadd). */
303 const int sdiv; /* cost of SFmode division (fdivs). */
304 const int ddiv; /* cost of DFmode division (fdiv). */
305 const int cache_line_size; /* cache line size in bytes. */
306 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
307 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
308 const int simultaneous_prefetches; /* number of parallel prefetch
312 const struct processor_costs *rs6000_cost;
314 /* Processor costs (relative to an add) */
316 /* Instruction size costs on 32bit processors. */
318 struct processor_costs size32_cost = {
319 COSTS_N_INSNS (1), /* mulsi */
320 COSTS_N_INSNS (1), /* mulsi_const */
321 COSTS_N_INSNS (1), /* mulsi_const9 */
322 COSTS_N_INSNS (1), /* muldi */
323 COSTS_N_INSNS (1), /* divsi */
324 COSTS_N_INSNS (1), /* divdi */
325 COSTS_N_INSNS (1), /* fp */
326 COSTS_N_INSNS (1), /* dmul */
327 COSTS_N_INSNS (1), /* sdiv */
328 COSTS_N_INSNS (1), /* ddiv */
335 /* Instruction size costs on 64bit processors. */
337 struct processor_costs size64_cost = {
338 COSTS_N_INSNS (1), /* mulsi */
339 COSTS_N_INSNS (1), /* mulsi_const */
340 COSTS_N_INSNS (1), /* mulsi_const9 */
341 COSTS_N_INSNS (1), /* muldi */
342 COSTS_N_INSNS (1), /* divsi */
343 COSTS_N_INSNS (1), /* divdi */
344 COSTS_N_INSNS (1), /* fp */
345 COSTS_N_INSNS (1), /* dmul */
346 COSTS_N_INSNS (1), /* sdiv */
347 COSTS_N_INSNS (1), /* ddiv */
354 /* Instruction costs on RIOS1 processors. */
356 struct processor_costs rios1_cost = {
357 COSTS_N_INSNS (5), /* mulsi */
358 COSTS_N_INSNS (4), /* mulsi_const */
359 COSTS_N_INSNS (3), /* mulsi_const9 */
360 COSTS_N_INSNS (5), /* muldi */
361 COSTS_N_INSNS (19), /* divsi */
362 COSTS_N_INSNS (19), /* divdi */
363 COSTS_N_INSNS (2), /* fp */
364 COSTS_N_INSNS (2), /* dmul */
365 COSTS_N_INSNS (19), /* sdiv */
366 COSTS_N_INSNS (19), /* ddiv */
367 128, /* cache line size */
373 /* Instruction costs on RIOS2 processors. */
375 struct processor_costs rios2_cost = {
376 COSTS_N_INSNS (2), /* mulsi */
377 COSTS_N_INSNS (2), /* mulsi_const */
378 COSTS_N_INSNS (2), /* mulsi_const9 */
379 COSTS_N_INSNS (2), /* muldi */
380 COSTS_N_INSNS (13), /* divsi */
381 COSTS_N_INSNS (13), /* divdi */
382 COSTS_N_INSNS (2), /* fp */
383 COSTS_N_INSNS (2), /* dmul */
384 COSTS_N_INSNS (17), /* sdiv */
385 COSTS_N_INSNS (17), /* ddiv */
386 256, /* cache line size */
392 /* Instruction costs on RS64A processors. */
394 struct processor_costs rs64a_cost = {
395 COSTS_N_INSNS (20), /* mulsi */
396 COSTS_N_INSNS (12), /* mulsi_const */
397 COSTS_N_INSNS (8), /* mulsi_const9 */
398 COSTS_N_INSNS (34), /* muldi */
399 COSTS_N_INSNS (65), /* divsi */
400 COSTS_N_INSNS (67), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (4), /* dmul */
403 COSTS_N_INSNS (31), /* sdiv */
404 COSTS_N_INSNS (31), /* ddiv */
405 128, /* cache line size */
411 /* Instruction costs on MPCCORE processors. */
413 struct processor_costs mpccore_cost = {
414 COSTS_N_INSNS (2), /* mulsi */
415 COSTS_N_INSNS (2), /* mulsi_const */
416 COSTS_N_INSNS (2), /* mulsi_const9 */
417 COSTS_N_INSNS (2), /* muldi */
418 COSTS_N_INSNS (6), /* divsi */
419 COSTS_N_INSNS (6), /* divdi */
420 COSTS_N_INSNS (4), /* fp */
421 COSTS_N_INSNS (5), /* dmul */
422 COSTS_N_INSNS (10), /* sdiv */
423 COSTS_N_INSNS (17), /* ddiv */
424 32, /* cache line size */
430 /* Instruction costs on PPC403 processors. */
432 struct processor_costs ppc403_cost = {
433 COSTS_N_INSNS (4), /* mulsi */
434 COSTS_N_INSNS (4), /* mulsi_const */
435 COSTS_N_INSNS (4), /* mulsi_const9 */
436 COSTS_N_INSNS (4), /* muldi */
437 COSTS_N_INSNS (33), /* divsi */
438 COSTS_N_INSNS (33), /* divdi */
439 COSTS_N_INSNS (11), /* fp */
440 COSTS_N_INSNS (11), /* dmul */
441 COSTS_N_INSNS (11), /* sdiv */
442 COSTS_N_INSNS (11), /* ddiv */
443 32, /* cache line size */
449 /* Instruction costs on PPC405 processors. */
451 struct processor_costs ppc405_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (3), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (35), /* divsi */
457 COSTS_N_INSNS (35), /* divdi */
458 COSTS_N_INSNS (11), /* fp */
459 COSTS_N_INSNS (11), /* dmul */
460 COSTS_N_INSNS (11), /* sdiv */
461 COSTS_N_INSNS (11), /* ddiv */
462 32, /* cache line size */
468 /* Instruction costs on PPC440 processors. */
470 struct processor_costs ppc440_cost = {
471 COSTS_N_INSNS (3), /* mulsi */
472 COSTS_N_INSNS (2), /* mulsi_const */
473 COSTS_N_INSNS (2), /* mulsi_const9 */
474 COSTS_N_INSNS (3), /* muldi */
475 COSTS_N_INSNS (34), /* divsi */
476 COSTS_N_INSNS (34), /* divdi */
477 COSTS_N_INSNS (5), /* fp */
478 COSTS_N_INSNS (5), /* dmul */
479 COSTS_N_INSNS (19), /* sdiv */
480 COSTS_N_INSNS (33), /* ddiv */
481 32, /* cache line size */
487 /* Instruction costs on PPC601 processors. */
489 struct processor_costs ppc601_cost = {
490 COSTS_N_INSNS (5), /* mulsi */
491 COSTS_N_INSNS (5), /* mulsi_const */
492 COSTS_N_INSNS (5), /* mulsi_const9 */
493 COSTS_N_INSNS (5), /* muldi */
494 COSTS_N_INSNS (36), /* divsi */
495 COSTS_N_INSNS (36), /* divdi */
496 COSTS_N_INSNS (4), /* fp */
497 COSTS_N_INSNS (5), /* dmul */
498 COSTS_N_INSNS (17), /* sdiv */
499 COSTS_N_INSNS (31), /* ddiv */
500 32, /* cache line size */
506 /* Instruction costs on PPC603 processors. */
508 struct processor_costs ppc603_cost = {
509 COSTS_N_INSNS (5), /* mulsi */
510 COSTS_N_INSNS (3), /* mulsi_const */
511 COSTS_N_INSNS (2), /* mulsi_const9 */
512 COSTS_N_INSNS (5), /* muldi */
513 COSTS_N_INSNS (37), /* divsi */
514 COSTS_N_INSNS (37), /* divdi */
515 COSTS_N_INSNS (3), /* fp */
516 COSTS_N_INSNS (4), /* dmul */
517 COSTS_N_INSNS (18), /* sdiv */
518 COSTS_N_INSNS (33), /* ddiv */
519 32, /* cache line size */
525 /* Instruction costs on PPC604 processors. */
527 struct processor_costs ppc604_cost = {
528 COSTS_N_INSNS (4), /* mulsi */
529 COSTS_N_INSNS (4), /* mulsi_const */
530 COSTS_N_INSNS (4), /* mulsi_const9 */
531 COSTS_N_INSNS (4), /* muldi */
532 COSTS_N_INSNS (20), /* divsi */
533 COSTS_N_INSNS (20), /* divdi */
534 COSTS_N_INSNS (3), /* fp */
535 COSTS_N_INSNS (3), /* dmul */
536 COSTS_N_INSNS (18), /* sdiv */
537 COSTS_N_INSNS (32), /* ddiv */
538 32, /* cache line size */
544 /* Instruction costs on PPC604e processors. */
546 struct processor_costs ppc604e_cost = {
547 COSTS_N_INSNS (2), /* mulsi */
548 COSTS_N_INSNS (2), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (2), /* muldi */
551 COSTS_N_INSNS (20), /* divsi */
552 COSTS_N_INSNS (20), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (18), /* sdiv */
556 COSTS_N_INSNS (32), /* ddiv */
557 32, /* cache line size */
563 /* Instruction costs on PPC620 processors. */
565 struct processor_costs ppc620_cost = {
566 COSTS_N_INSNS (5), /* mulsi */
567 COSTS_N_INSNS (4), /* mulsi_const */
568 COSTS_N_INSNS (3), /* mulsi_const9 */
569 COSTS_N_INSNS (7), /* muldi */
570 COSTS_N_INSNS (21), /* divsi */
571 COSTS_N_INSNS (37), /* divdi */
572 COSTS_N_INSNS (3), /* fp */
573 COSTS_N_INSNS (3), /* dmul */
574 COSTS_N_INSNS (18), /* sdiv */
575 COSTS_N_INSNS (32), /* ddiv */
576 128, /* cache line size */
582 /* Instruction costs on PPC630 processors. */
584 struct processor_costs ppc630_cost = {
585 COSTS_N_INSNS (5), /* mulsi */
586 COSTS_N_INSNS (4), /* mulsi_const */
587 COSTS_N_INSNS (3), /* mulsi_const9 */
588 COSTS_N_INSNS (7), /* muldi */
589 COSTS_N_INSNS (21), /* divsi */
590 COSTS_N_INSNS (37), /* divdi */
591 COSTS_N_INSNS (3), /* fp */
592 COSTS_N_INSNS (3), /* dmul */
593 COSTS_N_INSNS (17), /* sdiv */
594 COSTS_N_INSNS (21), /* ddiv */
595 128, /* cache line size */
601 /* Instruction costs on Cell processor. */
602 /* COSTS_N_INSNS (1) ~ one add. */
604 struct processor_costs ppccell_cost = {
605 COSTS_N_INSNS (9/2)+2, /* mulsi */
606 COSTS_N_INSNS (6/2), /* mulsi_const */
607 COSTS_N_INSNS (6/2), /* mulsi_const9 */
608 COSTS_N_INSNS (15/2)+2, /* muldi */
609 COSTS_N_INSNS (38/2), /* divsi */
610 COSTS_N_INSNS (70/2), /* divdi */
611 COSTS_N_INSNS (10/2), /* fp */
612 COSTS_N_INSNS (10/2), /* dmul */
613 COSTS_N_INSNS (74/2), /* sdiv */
614 COSTS_N_INSNS (74/2), /* ddiv */
615 128, /* cache line size */
621 /* Instruction costs on PPC750 and PPC7400 processors. */
623 struct processor_costs ppc750_cost = {
624 COSTS_N_INSNS (5), /* mulsi */
625 COSTS_N_INSNS (3), /* mulsi_const */
626 COSTS_N_INSNS (2), /* mulsi_const9 */
627 COSTS_N_INSNS (5), /* muldi */
628 COSTS_N_INSNS (17), /* divsi */
629 COSTS_N_INSNS (17), /* divdi */
630 COSTS_N_INSNS (3), /* fp */
631 COSTS_N_INSNS (3), /* dmul */
632 COSTS_N_INSNS (17), /* sdiv */
633 COSTS_N_INSNS (31), /* ddiv */
634 32, /* cache line size */
640 /* Instruction costs on PPC7450 processors. */
642 struct processor_costs ppc7450_cost = {
643 COSTS_N_INSNS (4), /* mulsi */
644 COSTS_N_INSNS (3), /* mulsi_const */
645 COSTS_N_INSNS (3), /* mulsi_const9 */
646 COSTS_N_INSNS (4), /* muldi */
647 COSTS_N_INSNS (23), /* divsi */
648 COSTS_N_INSNS (23), /* divdi */
649 COSTS_N_INSNS (5), /* fp */
650 COSTS_N_INSNS (5), /* dmul */
651 COSTS_N_INSNS (21), /* sdiv */
652 COSTS_N_INSNS (35), /* ddiv */
653 32, /* cache line size */
659 /* Instruction costs on PPC8540 processors. */
661 struct processor_costs ppc8540_cost = {
662 COSTS_N_INSNS (4), /* mulsi */
663 COSTS_N_INSNS (4), /* mulsi_const */
664 COSTS_N_INSNS (4), /* mulsi_const9 */
665 COSTS_N_INSNS (4), /* muldi */
666 COSTS_N_INSNS (19), /* divsi */
667 COSTS_N_INSNS (19), /* divdi */
668 COSTS_N_INSNS (4), /* fp */
669 COSTS_N_INSNS (4), /* dmul */
670 COSTS_N_INSNS (29), /* sdiv */
671 COSTS_N_INSNS (29), /* ddiv */
672 32, /* cache line size */
675 1, /* prefetch streams /*/
678 /* Instruction costs on E300C2 and E300C3 cores. */
680 struct processor_costs ppce300c2c3_cost = {
681 COSTS_N_INSNS (4), /* mulsi */
682 COSTS_N_INSNS (4), /* mulsi_const */
683 COSTS_N_INSNS (4), /* mulsi_const9 */
684 COSTS_N_INSNS (4), /* muldi */
685 COSTS_N_INSNS (19), /* divsi */
686 COSTS_N_INSNS (19), /* divdi */
687 COSTS_N_INSNS (3), /* fp */
688 COSTS_N_INSNS (4), /* dmul */
689 COSTS_N_INSNS (18), /* sdiv */
690 COSTS_N_INSNS (33), /* ddiv */
694 1, /* prefetch streams /*/
697 /* Instruction costs on PPCE500MC processors. */
699 struct processor_costs ppce500mc_cost = {
700 COSTS_N_INSNS (4), /* mulsi */
701 COSTS_N_INSNS (4), /* mulsi_const */
702 COSTS_N_INSNS (4), /* mulsi_const9 */
703 COSTS_N_INSNS (4), /* muldi */
704 COSTS_N_INSNS (14), /* divsi */
705 COSTS_N_INSNS (14), /* divdi */
706 COSTS_N_INSNS (8), /* fp */
707 COSTS_N_INSNS (10), /* dmul */
708 COSTS_N_INSNS (36), /* sdiv */
709 COSTS_N_INSNS (66), /* ddiv */
710 64, /* cache line size */
713 1, /* prefetch streams /*/
716 /* Instruction costs on POWER4 and POWER5 processors. */
718 struct processor_costs power4_cost = {
719 COSTS_N_INSNS (3), /* mulsi */
720 COSTS_N_INSNS (2), /* mulsi_const */
721 COSTS_N_INSNS (2), /* mulsi_const9 */
722 COSTS_N_INSNS (4), /* muldi */
723 COSTS_N_INSNS (18), /* divsi */
724 COSTS_N_INSNS (34), /* divdi */
725 COSTS_N_INSNS (3), /* fp */
726 COSTS_N_INSNS (3), /* dmul */
727 COSTS_N_INSNS (17), /* sdiv */
728 COSTS_N_INSNS (17), /* ddiv */
729 128, /* cache line size */
732 8, /* prefetch streams /*/
735 /* Instruction costs on POWER6 processors. */
737 struct processor_costs power6_cost = {
738 COSTS_N_INSNS (8), /* mulsi */
739 COSTS_N_INSNS (8), /* mulsi_const */
740 COSTS_N_INSNS (8), /* mulsi_const9 */
741 COSTS_N_INSNS (8), /* muldi */
742 COSTS_N_INSNS (22), /* divsi */
743 COSTS_N_INSNS (28), /* divdi */
744 COSTS_N_INSNS (3), /* fp */
745 COSTS_N_INSNS (3), /* dmul */
746 COSTS_N_INSNS (13), /* sdiv */
747 COSTS_N_INSNS (16), /* ddiv */
748 128, /* cache line size */
751 16, /* prefetch streams */
755 static bool rs6000_function_ok_for_sibcall (tree, tree);
756 static const char *rs6000_invalid_within_doloop (const_rtx);
757 static rtx rs6000_generate_compare (enum rtx_code);
758 static void rs6000_emit_stack_tie (void);
759 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
760 static bool spe_func_has_64bit_regs_p (void);
761 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
763 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
764 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int, int);
765 static unsigned rs6000_hash_constant (rtx);
766 static unsigned toc_hash_function (const void *);
767 static int toc_hash_eq (const void *, const void *);
768 static int constant_pool_expr_1 (rtx, int *, int *);
769 static bool constant_pool_expr_p (rtx);
770 static bool legitimate_small_data_p (enum machine_mode, rtx);
771 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
772 static struct machine_function * rs6000_init_machine_status (void);
773 static bool rs6000_assemble_integer (rtx, unsigned int, int);
774 static bool no_global_regs_above (int, bool);
775 #ifdef HAVE_GAS_HIDDEN
776 static void rs6000_assemble_visibility (tree, int);
778 static int rs6000_ra_ever_killed (void);
779 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
780 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
781 static bool rs6000_ms_bitfield_layout_p (const_tree);
782 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
783 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
784 static const char *rs6000_mangle_type (const_tree);
785 extern const struct attribute_spec rs6000_attribute_table[];
786 static void rs6000_set_default_type_attributes (tree);
787 static rtx rs6000_savres_routine_sym (rs6000_stack_t *, bool, bool, bool);
788 static void rs6000_emit_stack_reset (rs6000_stack_t *, rtx, rtx, int, bool);
789 static rtx rs6000_make_savres_rtx (rs6000_stack_t *, rtx, int,
790 enum machine_mode, bool, bool, bool);
791 static bool rs6000_reg_live_or_pic_offset_p (int);
792 static int rs6000_savres_strategy (rs6000_stack_t *, bool, int, int);
793 static void rs6000_restore_saved_cr (rtx, int);
794 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
795 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
796 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
798 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
799 static bool rs6000_return_in_memory (const_tree, const_tree);
800 static void rs6000_file_start (void);
802 static int rs6000_elf_reloc_rw_mask (void);
803 static void rs6000_elf_asm_out_constructor (rtx, int);
804 static void rs6000_elf_asm_out_destructor (rtx, int);
805 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
806 static void rs6000_elf_asm_init_sections (void);
807 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
808 unsigned HOST_WIDE_INT);
809 static void rs6000_elf_encode_section_info (tree, rtx, int)
812 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
813 static void rs6000_alloc_sdmode_stack_slot (void);
814 static void rs6000_instantiate_decls (void);
816 static void rs6000_xcoff_asm_output_anchor (rtx);
817 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
818 static void rs6000_xcoff_asm_init_sections (void);
819 static int rs6000_xcoff_reloc_rw_mask (void);
820 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
821 static section *rs6000_xcoff_select_section (tree, int,
822 unsigned HOST_WIDE_INT);
823 static void rs6000_xcoff_unique_section (tree, int);
824 static section *rs6000_xcoff_select_rtx_section
825 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
826 static const char * rs6000_xcoff_strip_name_encoding (const char *);
827 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
828 static void rs6000_xcoff_file_start (void);
829 static void rs6000_xcoff_file_end (void);
831 static int rs6000_variable_issue (FILE *, int, rtx, int);
832 static bool rs6000_rtx_costs (rtx, int, int, int *);
833 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
834 static void rs6000_sched_init (FILE *, int, int);
835 static bool is_microcoded_insn (rtx);
836 static bool is_nonpipeline_insn (rtx);
837 static bool is_cracked_insn (rtx);
838 static bool is_branch_slot_insn (rtx);
839 static bool is_load_insn (rtx);
840 static rtx get_store_dest (rtx pat);
841 static bool is_store_insn (rtx);
842 static bool set_to_load_agen (rtx,rtx);
843 static bool adjacent_mem_locations (rtx,rtx);
844 static int rs6000_adjust_priority (rtx, int);
845 static int rs6000_issue_rate (void);
846 static bool rs6000_is_costly_dependence (dep_t, int, int);
847 static rtx get_next_active_insn (rtx, rtx);
848 static bool insn_terminates_group_p (rtx , enum group_termination);
849 static bool insn_must_be_first_in_group (rtx);
850 static bool insn_must_be_last_in_group (rtx);
851 static bool is_costly_group (rtx *, rtx);
852 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
853 static int redefine_groups (FILE *, int, rtx, rtx);
854 static int pad_groups (FILE *, int, rtx, rtx);
855 static void rs6000_sched_finish (FILE *, int);
856 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
857 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
858 static int rs6000_use_sched_lookahead (void);
859 static int rs6000_use_sched_lookahead_guard (rtx);
860 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
861 static tree rs6000_builtin_mask_for_load (void);
862 static tree rs6000_builtin_mul_widen_even (tree);
863 static tree rs6000_builtin_mul_widen_odd (tree);
864 static tree rs6000_builtin_conversion (enum tree_code, tree);
866 static void def_builtin (int, const char *, tree, int);
867 static bool rs6000_vector_alignment_reachable (const_tree, bool);
868 static void rs6000_init_builtins (void);
869 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
870 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
871 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
872 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
873 static void altivec_init_builtins (void);
874 static void rs6000_common_init_builtins (void);
875 static void rs6000_init_libfuncs (void);
877 static void paired_init_builtins (void);
878 static rtx paired_expand_builtin (tree, rtx, bool *);
879 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
880 static rtx paired_expand_stv_builtin (enum insn_code, tree);
881 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
883 static void enable_mask_for_builtins (struct builtin_description *, int,
884 enum rs6000_builtins,
885 enum rs6000_builtins);
886 static tree build_opaque_vector_type (tree, int);
887 static void spe_init_builtins (void);
888 static rtx spe_expand_builtin (tree, rtx, bool *);
889 static rtx spe_expand_stv_builtin (enum insn_code, tree);
890 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
891 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
892 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
893 static rs6000_stack_t *rs6000_stack_info (void);
894 static void debug_stack_info (rs6000_stack_t *);
896 static rtx altivec_expand_builtin (tree, rtx, bool *);
897 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
898 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
899 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
900 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
901 static rtx altivec_expand_predicate_builtin (enum insn_code,
902 const char *, tree, rtx);
903 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
904 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
905 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
906 static rtx altivec_expand_vec_set_builtin (tree);
907 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
908 static int get_element_number (tree, tree);
909 static bool rs6000_handle_option (size_t, const char *, int);
910 static void rs6000_parse_tls_size_option (void);
911 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
912 static int first_altivec_reg_to_save (void);
913 static unsigned int compute_vrsave_mask (void);
914 static void compute_save_world_info (rs6000_stack_t *info_ptr);
915 static void is_altivec_return_reg (rtx, void *);
916 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
917 int easy_vector_constant (rtx, enum machine_mode);
918 static bool rs6000_is_opaque_type (const_tree);
919 static rtx rs6000_dwarf_register_span (rtx);
920 static void rs6000_init_dwarf_reg_sizes_extra (tree);
921 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
922 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
923 static rtx rs6000_tls_get_addr (void);
924 static rtx rs6000_got_sym (void);
925 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
926 static const char *rs6000_get_some_local_dynamic_name (void);
927 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
928 static rtx rs6000_complex_function_value (enum machine_mode);
929 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
930 enum machine_mode, tree);
931 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
933 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
934 tree, HOST_WIDE_INT);
935 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
938 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
939 const_tree, HOST_WIDE_INT,
941 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool);
942 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
943 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
944 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
945 enum machine_mode, tree,
947 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
949 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
951 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
953 static void macho_branch_islands (void);
954 static int no_previous_def (tree function_name);
955 static tree get_prev_label (tree function_name);
956 static void rs6000_darwin_file_start (void);
959 static tree rs6000_build_builtin_va_list (void);
960 static void rs6000_va_start (tree, rtx);
961 static tree rs6000_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
962 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
963 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
964 static bool rs6000_vector_mode_supported_p (enum machine_mode);
965 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
967 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
969 static int get_vsel_insn (enum machine_mode);
970 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
971 static tree rs6000_stack_protect_fail (void);
973 const int INSN_NOT_AVAILABLE = -1;
974 static enum machine_mode rs6000_eh_return_filter_mode (void);
976 /* Hash table stuff for keeping track of TOC entries. */
978 struct toc_hash_struct GTY(())
980 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
981 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
983 enum machine_mode key_mode;
987 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
989 /* Default register names. */
990 char rs6000_reg_names[][8] =
992 "0", "1", "2", "3", "4", "5", "6", "7",
993 "8", "9", "10", "11", "12", "13", "14", "15",
994 "16", "17", "18", "19", "20", "21", "22", "23",
995 "24", "25", "26", "27", "28", "29", "30", "31",
996 "0", "1", "2", "3", "4", "5", "6", "7",
997 "8", "9", "10", "11", "12", "13", "14", "15",
998 "16", "17", "18", "19", "20", "21", "22", "23",
999 "24", "25", "26", "27", "28", "29", "30", "31",
1000 "mq", "lr", "ctr","ap",
1001 "0", "1", "2", "3", "4", "5", "6", "7",
1003 /* AltiVec registers. */
1004 "0", "1", "2", "3", "4", "5", "6", "7",
1005 "8", "9", "10", "11", "12", "13", "14", "15",
1006 "16", "17", "18", "19", "20", "21", "22", "23",
1007 "24", "25", "26", "27", "28", "29", "30", "31",
1009 /* SPE registers. */
1010 "spe_acc", "spefscr",
1011 /* Soft frame pointer. */
1015 #ifdef TARGET_REGNAMES
1016 static const char alt_reg_names[][8] =
1018 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1019 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1020 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1021 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1022 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1023 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1024 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1025 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1026 "mq", "lr", "ctr", "ap",
1027 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1029 /* AltiVec registers. */
1030 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1031 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1032 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1033 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1035 /* SPE registers. */
1036 "spe_acc", "spefscr",
1037 /* Soft frame pointer. */
1042 #ifndef MASK_STRICT_ALIGN
1043 #define MASK_STRICT_ALIGN 0
1045 #ifndef TARGET_PROFILE_KERNEL
1046 #define TARGET_PROFILE_KERNEL 0
1049 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1050 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1052 /* Initialize the GCC target structure. */
1053 #undef TARGET_ATTRIBUTE_TABLE
1054 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1055 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1056 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1058 #undef TARGET_ASM_ALIGNED_DI_OP
1059 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1061 /* Default unaligned ops are only provided for ELF. Find the ops needed
1062 for non-ELF systems. */
1063 #ifndef OBJECT_FORMAT_ELF
1065 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1067 #undef TARGET_ASM_UNALIGNED_HI_OP
1068 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1069 #undef TARGET_ASM_UNALIGNED_SI_OP
1070 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1071 #undef TARGET_ASM_UNALIGNED_DI_OP
1072 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1075 #undef TARGET_ASM_UNALIGNED_HI_OP
1076 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1077 #undef TARGET_ASM_UNALIGNED_SI_OP
1078 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1079 #undef TARGET_ASM_UNALIGNED_DI_OP
1080 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1081 #undef TARGET_ASM_ALIGNED_DI_OP
1082 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1086 /* This hook deals with fixups for relocatable code and DI-mode objects
1088 #undef TARGET_ASM_INTEGER
1089 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1091 #ifdef HAVE_GAS_HIDDEN
1092 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1093 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1096 #undef TARGET_HAVE_TLS
1097 #define TARGET_HAVE_TLS HAVE_AS_TLS
1099 #undef TARGET_CANNOT_FORCE_CONST_MEM
1100 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1102 #undef TARGET_ASM_FUNCTION_PROLOGUE
1103 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1104 #undef TARGET_ASM_FUNCTION_EPILOGUE
1105 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1107 #undef TARGET_SCHED_VARIABLE_ISSUE
1108 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1110 #undef TARGET_SCHED_ISSUE_RATE
1111 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1112 #undef TARGET_SCHED_ADJUST_COST
1113 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1114 #undef TARGET_SCHED_ADJUST_PRIORITY
1115 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1116 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1117 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1118 #undef TARGET_SCHED_INIT
1119 #define TARGET_SCHED_INIT rs6000_sched_init
1120 #undef TARGET_SCHED_FINISH
1121 #define TARGET_SCHED_FINISH rs6000_sched_finish
1122 #undef TARGET_SCHED_REORDER
1123 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1124 #undef TARGET_SCHED_REORDER2
1125 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1127 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1128 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1130 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1131 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1133 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1134 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1135 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1136 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1137 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1138 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1139 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1140 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1142 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1143 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1145 #undef TARGET_INIT_BUILTINS
1146 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1148 #undef TARGET_EXPAND_BUILTIN
1149 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1151 #undef TARGET_MANGLE_TYPE
1152 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1154 #undef TARGET_INIT_LIBFUNCS
1155 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1158 #undef TARGET_BINDS_LOCAL_P
1159 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1162 #undef TARGET_MS_BITFIELD_LAYOUT_P
1163 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1165 #undef TARGET_ASM_OUTPUT_MI_THUNK
1166 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1168 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1169 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1171 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1172 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1174 #undef TARGET_INVALID_WITHIN_DOLOOP
1175 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1177 #undef TARGET_RTX_COSTS
1178 #define TARGET_RTX_COSTS rs6000_rtx_costs
1179 #undef TARGET_ADDRESS_COST
1180 #define TARGET_ADDRESS_COST hook_int_rtx_0
1182 #undef TARGET_VECTOR_OPAQUE_P
1183 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1185 #undef TARGET_DWARF_REGISTER_SPAN
1186 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1188 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1189 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1191 /* On rs6000, function arguments are promoted, as are function return
1193 #undef TARGET_PROMOTE_FUNCTION_ARGS
1194 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1195 #undef TARGET_PROMOTE_FUNCTION_RETURN
1196 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1198 #undef TARGET_RETURN_IN_MEMORY
1199 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1201 #undef TARGET_SETUP_INCOMING_VARARGS
1202 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1204 /* Always strict argument naming on rs6000. */
1205 #undef TARGET_STRICT_ARGUMENT_NAMING
1206 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1207 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1208 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1209 #undef TARGET_SPLIT_COMPLEX_ARG
1210 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1211 #undef TARGET_MUST_PASS_IN_STACK
1212 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1213 #undef TARGET_PASS_BY_REFERENCE
1214 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1215 #undef TARGET_ARG_PARTIAL_BYTES
1216 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1218 #undef TARGET_BUILD_BUILTIN_VA_LIST
1219 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1221 #undef TARGET_EXPAND_BUILTIN_VA_START
1222 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1224 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1225 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1227 #undef TARGET_EH_RETURN_FILTER_MODE
1228 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1230 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1231 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1233 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1234 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1236 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1237 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1239 #undef TARGET_HANDLE_OPTION
1240 #define TARGET_HANDLE_OPTION rs6000_handle_option
1242 #undef TARGET_DEFAULT_TARGET_FLAGS
1243 #define TARGET_DEFAULT_TARGET_FLAGS \
1246 #undef TARGET_STACK_PROTECT_FAIL
1247 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1249 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1250 The PowerPC architecture requires only weak consistency among
1251 processors--that is, memory accesses between processors need not be
1252 sequentially consistent and memory accesses among processors can occur
1253 in any order. The ability to order memory accesses weakly provides
1254 opportunities for more efficient use of the system bus. Unless a
1255 dependency exists, the 604e allows read operations to precede store
1257 #undef TARGET_RELAXED_ORDERING
1258 #define TARGET_RELAXED_ORDERING true
1261 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1262 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1265 /* Use a 32-bit anchor range. This leads to sequences like:
1267 addis tmp,anchor,high
1270 where tmp itself acts as an anchor, and can be shared between
1271 accesses to the same 64k page. */
1272 #undef TARGET_MIN_ANCHOR_OFFSET
1273 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1274 #undef TARGET_MAX_ANCHOR_OFFSET
1275 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1276 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1277 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1279 #undef TARGET_BUILTIN_RECIPROCAL
1280 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1282 #undef TARGET_EXPAND_TO_RTL_HOOK
1283 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1285 #undef TARGET_INSTANTIATE_DECLS
1286 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1288 struct gcc_target targetm = TARGET_INITIALIZER;
1291 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1294 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1296 /* The GPRs can hold any mode, but values bigger than one register
1297 cannot go past R31. */
1298 if (INT_REGNO_P (regno))
1299 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1301 /* The float registers can only hold floating modes and DImode.
1302 This excludes the 32-bit decimal float mode for now. */
1303 if (FP_REGNO_P (regno))
1305 ((SCALAR_FLOAT_MODE_P (mode)
1306 && (mode != TDmode || (regno % 2) == 0)
1307 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1308 || (GET_MODE_CLASS (mode) == MODE_INT
1309 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1310 || (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1311 && PAIRED_VECTOR_MODE (mode)));
1313 /* The CR register can only hold CC modes. */
1314 if (CR_REGNO_P (regno))
1315 return GET_MODE_CLASS (mode) == MODE_CC;
1317 if (XER_REGNO_P (regno))
1318 return mode == PSImode;
1320 /* AltiVec only in AldyVec registers. */
1321 if (ALTIVEC_REGNO_P (regno))
1322 return ALTIVEC_VECTOR_MODE (mode);
1324 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1325 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1328 /* We cannot put TImode anywhere except general register and it must be
1329 able to fit within the register set. */
1331 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1334 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1336 rs6000_init_hard_regno_mode_ok (void)
1340 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1341 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1342 if (rs6000_hard_regno_mode_ok (r, m))
1343 rs6000_hard_regno_mode_ok_p[m][r] = true;
1347 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1350 darwin_rs6000_override_options (void)
1352 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1354 rs6000_altivec_abi = 1;
1355 TARGET_ALTIVEC_VRSAVE = 1;
1356 if (DEFAULT_ABI == ABI_DARWIN)
1358 if (MACHO_DYNAMIC_NO_PIC_P)
1361 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1364 else if (flag_pic == 1)
1369 if (TARGET_64BIT && ! TARGET_POWERPC64)
1371 target_flags |= MASK_POWERPC64;
1372 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1376 rs6000_default_long_calls = 1;
1377 target_flags |= MASK_SOFT_FLOAT;
1380 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1382 if (!flag_mkernel && !flag_apple_kext
1384 && ! (target_flags_explicit & MASK_ALTIVEC))
1385 target_flags |= MASK_ALTIVEC;
1387 /* Unless the user (not the configurer) has explicitly overridden
1388 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1389 G4 unless targetting the kernel. */
1392 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1393 && ! (target_flags_explicit & MASK_ALTIVEC)
1394 && ! rs6000_select[1].string)
1396 target_flags |= MASK_ALTIVEC;
1401 /* If not otherwise specified by a target, make 'long double' equivalent to
1404 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1405 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1408 /* Override command line options. Mostly we process the processor
1409 type and sometimes adjust other TARGET_ options. */
1412 rs6000_override_options (const char *default_cpu)
1415 struct rs6000_cpu_select *ptr;
1418 /* Simplifications for entries below. */
1421 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1422 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1425 /* This table occasionally claims that a processor does not support
1426 a particular feature even though it does, but the feature is slower
1427 than the alternative. Thus, it shouldn't be relied on as a
1428 complete description of the processor's support.
1430 Please keep this list in order, and don't forget to update the
1431 documentation in invoke.texi when adding a new processor or
1435 const char *const name; /* Canonical processor name. */
1436 const enum processor_type processor; /* Processor type enum value. */
1437 const int target_enable; /* Target flags to enable. */
1438 } const processor_target_table[]
1439 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1440 {"403", PROCESSOR_PPC403,
1441 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1442 {"405", PROCESSOR_PPC405,
1443 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1444 {"405fp", PROCESSOR_PPC405,
1445 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1446 {"440", PROCESSOR_PPC440,
1447 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1448 {"440fp", PROCESSOR_PPC440,
1449 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1450 {"464", PROCESSOR_PPC440,
1451 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1452 {"464fp", PROCESSOR_PPC440,
1453 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1454 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1455 {"601", PROCESSOR_PPC601,
1456 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1457 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1458 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1459 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1460 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1461 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1462 {"620", PROCESSOR_PPC620,
1463 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1464 {"630", PROCESSOR_PPC630,
1465 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1466 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1467 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1468 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1469 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1470 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1471 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1472 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1473 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1474 /* 8548 has a dummy entry for now. */
1475 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1476 {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1477 {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
1478 {"e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1479 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1480 {"970", PROCESSOR_POWER4,
1481 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1482 {"cell", PROCESSOR_CELL,
1483 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1484 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1485 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1486 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1487 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1488 {"G5", PROCESSOR_POWER4,
1489 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1490 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1491 {"power2", PROCESSOR_POWER,
1492 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1493 {"power3", PROCESSOR_PPC630,
1494 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1495 {"power4", PROCESSOR_POWER4,
1496 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1498 {"power5", PROCESSOR_POWER5,
1499 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1500 | MASK_MFCRF | MASK_POPCNTB},
1501 {"power5+", PROCESSOR_POWER5,
1502 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1503 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1504 {"power6", PROCESSOR_POWER6,
1505 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
1506 | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP},
1507 {"power6x", PROCESSOR_POWER6,
1508 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
1509 | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_MFPGPR},
1510 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1511 {"powerpc64", PROCESSOR_POWERPC64,
1512 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1513 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1514 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1515 {"rios2", PROCESSOR_RIOS2,
1516 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1517 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1518 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1519 {"rs64", PROCESSOR_RS64A,
1520 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1523 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1525 /* Some OSs don't support saving the high part of 64-bit registers on
1526 context switch. Other OSs don't support saving Altivec registers.
1527 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1528 settings; if the user wants either, the user must explicitly specify
1529 them and we won't interfere with the user's specification. */
1532 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1533 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1534 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1535 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1536 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1539 rs6000_init_hard_regno_mode_ok ();
1541 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1542 #ifdef OS_MISSING_POWERPC64
1543 if (OS_MISSING_POWERPC64)
1544 set_masks &= ~MASK_POWERPC64;
1546 #ifdef OS_MISSING_ALTIVEC
1547 if (OS_MISSING_ALTIVEC)
1548 set_masks &= ~MASK_ALTIVEC;
1551 /* Don't override by the processor default if given explicitly. */
1552 set_masks &= ~target_flags_explicit;
1554 /* Identify the processor type. */
1555 rs6000_select[0].string = default_cpu;
1556 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1558 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1560 ptr = &rs6000_select[i];
1561 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1563 for (j = 0; j < ptt_size; j++)
1564 if (! strcmp (ptr->string, processor_target_table[j].name))
1566 if (ptr->set_tune_p)
1567 rs6000_cpu = processor_target_table[j].processor;
1569 if (ptr->set_arch_p)
1571 target_flags &= ~set_masks;
1572 target_flags |= (processor_target_table[j].target_enable
1579 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1583 if ((TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
1584 && !rs6000_explicit_options.isel)
1587 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
1588 || rs6000_cpu == PROCESSOR_PPCE500MC)
1591 error ("AltiVec not supported in this target");
1593 error ("Spe not supported in this target");
1596 /* If we are optimizing big endian systems for space, use the load/store
1597 multiple and string instructions. */
1598 if (BYTES_BIG_ENDIAN && optimize_size)
1599 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1601 /* Don't allow -mmultiple or -mstring on little endian systems
1602 unless the cpu is a 750, because the hardware doesn't support the
1603 instructions used in little endian mode, and causes an alignment
1604 trap. The 750 does not cause an alignment trap (except when the
1605 target is unaligned). */
1607 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1609 if (TARGET_MULTIPLE)
1611 target_flags &= ~MASK_MULTIPLE;
1612 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1613 warning (0, "-mmultiple is not supported on little endian systems");
1618 target_flags &= ~MASK_STRING;
1619 if ((target_flags_explicit & MASK_STRING) != 0)
1620 warning (0, "-mstring is not supported on little endian systems");
1624 /* Set debug flags */
1625 if (rs6000_debug_name)
1627 if (! strcmp (rs6000_debug_name, "all"))
1628 rs6000_debug_stack = rs6000_debug_arg = 1;
1629 else if (! strcmp (rs6000_debug_name, "stack"))
1630 rs6000_debug_stack = 1;
1631 else if (! strcmp (rs6000_debug_name, "arg"))
1632 rs6000_debug_arg = 1;
1634 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1637 if (rs6000_traceback_name)
1639 if (! strncmp (rs6000_traceback_name, "full", 4))
1640 rs6000_traceback = traceback_full;
1641 else if (! strncmp (rs6000_traceback_name, "part", 4))
1642 rs6000_traceback = traceback_part;
1643 else if (! strncmp (rs6000_traceback_name, "no", 2))
1644 rs6000_traceback = traceback_none;
1646 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1647 rs6000_traceback_name);
1650 if (!rs6000_explicit_options.long_double)
1651 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1653 #ifndef POWERPC_LINUX
1654 if (!rs6000_explicit_options.ieee)
1655 rs6000_ieeequad = 1;
1658 /* Enable Altivec ABI for AIX -maltivec. */
1659 if (TARGET_XCOFF && TARGET_ALTIVEC)
1660 rs6000_altivec_abi = 1;
1662 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1663 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1664 be explicitly overridden in either case. */
1667 if (!rs6000_explicit_options.altivec_abi
1668 && (TARGET_64BIT || TARGET_ALTIVEC))
1669 rs6000_altivec_abi = 1;
1671 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1672 if (!rs6000_explicit_options.vrsave)
1673 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
1676 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1677 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1679 rs6000_darwin64_abi = 1;
1681 darwin_one_byte_bool = 1;
1683 /* Default to natural alignment, for better performance. */
1684 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1687 /* Place FP constants in the constant pool instead of TOC
1688 if section anchors enabled. */
1689 if (flag_section_anchors)
1690 TARGET_NO_FP_IN_TOC = 1;
1692 /* Handle -mtls-size option. */
1693 rs6000_parse_tls_size_option ();
1695 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1696 SUBTARGET_OVERRIDE_OPTIONS;
1698 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1699 SUBSUBTARGET_OVERRIDE_OPTIONS;
1701 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1702 SUB3TARGET_OVERRIDE_OPTIONS;
1705 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
1707 /* The e500 and e500mc do not have string instructions, and we set
1708 MASK_STRING above when optimizing for size. */
1709 if ((target_flags & MASK_STRING) != 0)
1710 target_flags = target_flags & ~MASK_STRING;
1712 else if (rs6000_select[1].string != NULL)
1714 /* For the powerpc-eabispe configuration, we set all these by
1715 default, so let's unset them if we manually set another
1716 CPU that is not the E500. */
1717 if (!rs6000_explicit_options.spe_abi)
1719 if (!rs6000_explicit_options.spe)
1721 if (!rs6000_explicit_options.float_gprs)
1722 rs6000_float_gprs = 0;
1723 if (!rs6000_explicit_options.isel)
1727 /* Detect invalid option combinations with E500. */
1730 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1731 && rs6000_cpu != PROCESSOR_POWER5
1732 && rs6000_cpu != PROCESSOR_POWER6
1733 && rs6000_cpu != PROCESSOR_CELL);
1734 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1735 || rs6000_cpu == PROCESSOR_POWER5);
1736 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1737 || rs6000_cpu == PROCESSOR_POWER5
1738 || rs6000_cpu == PROCESSOR_POWER6);
1740 rs6000_sched_restricted_insns_priority
1741 = (rs6000_sched_groups ? 1 : 0);
1743 /* Handle -msched-costly-dep option. */
1744 rs6000_sched_costly_dep
1745 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1747 if (rs6000_sched_costly_dep_str)
1749 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1750 rs6000_sched_costly_dep = no_dep_costly;
1751 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1752 rs6000_sched_costly_dep = all_deps_costly;
1753 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1754 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1755 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1756 rs6000_sched_costly_dep = store_to_load_dep_costly;
1758 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1761 /* Handle -minsert-sched-nops option. */
1762 rs6000_sched_insert_nops
1763 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1765 if (rs6000_sched_insert_nops_str)
1767 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1768 rs6000_sched_insert_nops = sched_finish_none;
1769 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1770 rs6000_sched_insert_nops = sched_finish_pad_groups;
1771 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1772 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1774 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1777 #ifdef TARGET_REGNAMES
1778 /* If the user desires alternate register names, copy in the
1779 alternate names now. */
1780 if (TARGET_REGNAMES)
1781 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1784 /* Set aix_struct_return last, after the ABI is determined.
1785 If -maix-struct-return or -msvr4-struct-return was explicitly
1786 used, don't override with the ABI default. */
1787 if (!rs6000_explicit_options.aix_struct_ret)
1788 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1790 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1791 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1794 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1796 /* We can only guarantee the availability of DI pseudo-ops when
1797 assembling for 64-bit targets. */
1800 targetm.asm_out.aligned_op.di = NULL;
1801 targetm.asm_out.unaligned_op.di = NULL;
1804 /* Set branch target alignment, if not optimizing for size. */
1807 /* Cell wants to be aligned 8byte for dual issue. */
1808 if (rs6000_cpu == PROCESSOR_CELL)
1810 if (align_functions <= 0)
1811 align_functions = 8;
1812 if (align_jumps <= 0)
1814 if (align_loops <= 0)
1817 if (rs6000_align_branch_targets)
1819 if (align_functions <= 0)
1820 align_functions = 16;
1821 if (align_jumps <= 0)
1823 if (align_loops <= 0)
1826 if (align_jumps_max_skip <= 0)
1827 align_jumps_max_skip = 15;
1828 if (align_loops_max_skip <= 0)
1829 align_loops_max_skip = 15;
1832 /* Arrange to save and restore machine status around nested functions. */
1833 init_machine_status = rs6000_init_machine_status;
1835 /* We should always be splitting complex arguments, but we can't break
1836 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1837 if (DEFAULT_ABI != ABI_AIX)
1838 targetm.calls.split_complex_arg = NULL;
1840 /* Initialize rs6000_cost with the appropriate target costs. */
1842 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1846 case PROCESSOR_RIOS1:
1847 rs6000_cost = &rios1_cost;
1850 case PROCESSOR_RIOS2:
1851 rs6000_cost = &rios2_cost;
1854 case PROCESSOR_RS64A:
1855 rs6000_cost = &rs64a_cost;
1858 case PROCESSOR_MPCCORE:
1859 rs6000_cost = &mpccore_cost;
1862 case PROCESSOR_PPC403:
1863 rs6000_cost = &ppc403_cost;
1866 case PROCESSOR_PPC405:
1867 rs6000_cost = &ppc405_cost;
1870 case PROCESSOR_PPC440:
1871 rs6000_cost = &ppc440_cost;
1874 case PROCESSOR_PPC601:
1875 rs6000_cost = &ppc601_cost;
1878 case PROCESSOR_PPC603:
1879 rs6000_cost = &ppc603_cost;
1882 case PROCESSOR_PPC604:
1883 rs6000_cost = &ppc604_cost;
1886 case PROCESSOR_PPC604e:
1887 rs6000_cost = &ppc604e_cost;
1890 case PROCESSOR_PPC620:
1891 rs6000_cost = &ppc620_cost;
1894 case PROCESSOR_PPC630:
1895 rs6000_cost = &ppc630_cost;
1898 case PROCESSOR_CELL:
1899 rs6000_cost = &ppccell_cost;
1902 case PROCESSOR_PPC750:
1903 case PROCESSOR_PPC7400:
1904 rs6000_cost = &ppc750_cost;
1907 case PROCESSOR_PPC7450:
1908 rs6000_cost = &ppc7450_cost;
1911 case PROCESSOR_PPC8540:
1912 rs6000_cost = &ppc8540_cost;
1915 case PROCESSOR_PPCE300C2:
1916 case PROCESSOR_PPCE300C3:
1917 rs6000_cost = &ppce300c2c3_cost;
1920 case PROCESSOR_PPCE500MC:
1921 rs6000_cost = &ppce500mc_cost;
1924 case PROCESSOR_POWER4:
1925 case PROCESSOR_POWER5:
1926 rs6000_cost = &power4_cost;
1929 case PROCESSOR_POWER6:
1930 rs6000_cost = &power6_cost;
1937 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1938 set_param_value ("simultaneous-prefetches",
1939 rs6000_cost->simultaneous_prefetches);
1940 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1941 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1942 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1943 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1944 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1945 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1947 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1948 can be optimized to ap = __builtin_next_arg (0). */
1949 if (DEFAULT_ABI != ABI_V4)
1950 targetm.expand_builtin_va_start = NULL;
1953 /* Implement targetm.vectorize.builtin_mask_for_load. */
1955 rs6000_builtin_mask_for_load (void)
1958 return altivec_builtin_mask_for_load;
1963 /* Implement targetm.vectorize.builtin_conversion. */
1965 rs6000_builtin_conversion (enum tree_code code, tree type)
1967 if (!TARGET_ALTIVEC)
1973 switch (TYPE_MODE (type))
1976 return TYPE_UNSIGNED (type) ?
1977 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1978 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1987 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1989 rs6000_builtin_mul_widen_even (tree type)
1991 if (!TARGET_ALTIVEC)
1994 switch (TYPE_MODE (type))
1997 return TYPE_UNSIGNED (type) ?
1998 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1999 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
2002 return TYPE_UNSIGNED (type) ?
2003 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
2004 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
2010 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
2012 rs6000_builtin_mul_widen_odd (tree type)
2014 if (!TARGET_ALTIVEC)
2017 switch (TYPE_MODE (type))
2020 return TYPE_UNSIGNED (type) ?
2021 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
2022 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
2025 return TYPE_UNSIGNED (type) ?
2026 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
2027 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
2034 /* Return true iff, data reference of TYPE can reach vector alignment (16)
2035 after applying N number of iterations. This routine does not determine
2036 how may iterations are required to reach desired alignment. */
2039 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
2046 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
2049 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
2059 /* Assuming that all other types are naturally aligned. CHECKME! */
2064 /* Handle generic options of the form -mfoo=yes/no.
2065 NAME is the option name.
2066 VALUE is the option value.
2067 FLAG is the pointer to the flag where to store a 1 or 0, depending on
2068 whether the option value is 'yes' or 'no' respectively. */
2070 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
2074 else if (!strcmp (value, "yes"))
2076 else if (!strcmp (value, "no"))
2079 error ("unknown -m%s= option specified: '%s'", name, value);
2082 /* Validate and record the size specified with the -mtls-size option. */
2085 rs6000_parse_tls_size_option (void)
2087 if (rs6000_tls_size_string == 0)
2089 else if (strcmp (rs6000_tls_size_string, "16") == 0)
2090 rs6000_tls_size = 16;
2091 else if (strcmp (rs6000_tls_size_string, "32") == 0)
2092 rs6000_tls_size = 32;
2093 else if (strcmp (rs6000_tls_size_string, "64") == 0)
2094 rs6000_tls_size = 64;
2096 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
2100 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
2102 if (DEFAULT_ABI == ABI_DARWIN)
2103 /* The Darwin libraries never set errno, so we might as well
2104 avoid calling them when that's the only reason we would. */
2105 flag_errno_math = 0;
2107 /* Double growth factor to counter reduced min jump length. */
2108 set_param_value ("max-grow-copy-bb-insns", 16);
2110 /* Enable section anchors by default.
2111 Skip section anchors for Objective C and Objective C++
2112 until front-ends fixed. */
2113 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
2114 flag_section_anchors = 2;
2117 /* Implement TARGET_HANDLE_OPTION. */
2120 rs6000_handle_option (size_t code, const char *arg, int value)
2125 target_flags &= ~(MASK_POWER | MASK_POWER2
2126 | MASK_MULTIPLE | MASK_STRING);
2127 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2128 | MASK_MULTIPLE | MASK_STRING);
2130 case OPT_mno_powerpc:
2131 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2132 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2133 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2134 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2137 target_flags &= ~MASK_MINIMAL_TOC;
2138 TARGET_NO_FP_IN_TOC = 0;
2139 TARGET_NO_SUM_IN_TOC = 0;
2140 target_flags_explicit |= MASK_MINIMAL_TOC;
2141 #ifdef TARGET_USES_SYSV4_OPT
2142 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2143 just the same as -mminimal-toc. */
2144 target_flags |= MASK_MINIMAL_TOC;
2145 target_flags_explicit |= MASK_MINIMAL_TOC;
2149 #ifdef TARGET_USES_SYSV4_OPT
2151 /* Make -mtoc behave like -mminimal-toc. */
2152 target_flags |= MASK_MINIMAL_TOC;
2153 target_flags_explicit |= MASK_MINIMAL_TOC;
2157 #ifdef TARGET_USES_AIX64_OPT
2162 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2163 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2164 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2167 #ifdef TARGET_USES_AIX64_OPT
2172 target_flags &= ~MASK_POWERPC64;
2173 target_flags_explicit |= MASK_POWERPC64;
2176 case OPT_minsert_sched_nops_:
2177 rs6000_sched_insert_nops_str = arg;
2180 case OPT_mminimal_toc:
2183 TARGET_NO_FP_IN_TOC = 0;
2184 TARGET_NO_SUM_IN_TOC = 0;
2191 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2192 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2199 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2200 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2204 case OPT_mpowerpc_gpopt:
2205 case OPT_mpowerpc_gfxopt:
2208 target_flags |= MASK_POWERPC;
2209 target_flags_explicit |= MASK_POWERPC;
2213 case OPT_maix_struct_return:
2214 case OPT_msvr4_struct_return:
2215 rs6000_explicit_options.aix_struct_ret = true;
2219 rs6000_explicit_options.vrsave = true;
2220 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2224 rs6000_explicit_options.isel = true;
2225 rs6000_isel = value;
2229 rs6000_explicit_options.isel = true;
2230 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2234 rs6000_explicit_options.spe = true;
2239 rs6000_explicit_options.spe = true;
2240 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2244 rs6000_debug_name = arg;
2247 #ifdef TARGET_USES_SYSV4_OPT
2249 rs6000_abi_name = arg;
2253 rs6000_sdata_name = arg;
2256 case OPT_mtls_size_:
2257 rs6000_tls_size_string = arg;
2260 case OPT_mrelocatable:
2263 target_flags |= MASK_MINIMAL_TOC;
2264 target_flags_explicit |= MASK_MINIMAL_TOC;
2265 TARGET_NO_FP_IN_TOC = 1;
2269 case OPT_mrelocatable_lib:
2272 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2273 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2274 TARGET_NO_FP_IN_TOC = 1;
2278 target_flags &= ~MASK_RELOCATABLE;
2279 target_flags_explicit |= MASK_RELOCATABLE;
2285 if (!strcmp (arg, "altivec"))
2287 rs6000_explicit_options.altivec_abi = true;
2288 rs6000_altivec_abi = 1;
2290 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2293 else if (! strcmp (arg, "no-altivec"))
2295 rs6000_explicit_options.altivec_abi = true;
2296 rs6000_altivec_abi = 0;
2298 else if (! strcmp (arg, "spe"))
2300 rs6000_explicit_options.spe_abi = true;
2302 rs6000_altivec_abi = 0;
2303 if (!TARGET_SPE_ABI)
2304 error ("not configured for ABI: '%s'", arg);
2306 else if (! strcmp (arg, "no-spe"))
2308 rs6000_explicit_options.spe_abi = true;
2312 /* These are here for testing during development only, do not
2313 document in the manual please. */
2314 else if (! strcmp (arg, "d64"))
2316 rs6000_darwin64_abi = 1;
2317 warning (0, "Using darwin64 ABI");
2319 else if (! strcmp (arg, "d32"))
2321 rs6000_darwin64_abi = 0;
2322 warning (0, "Using old darwin ABI");
2325 else if (! strcmp (arg, "ibmlongdouble"))
2327 rs6000_explicit_options.ieee = true;
2328 rs6000_ieeequad = 0;
2329 warning (0, "Using IBM extended precision long double");
2331 else if (! strcmp (arg, "ieeelongdouble"))
2333 rs6000_explicit_options.ieee = true;
2334 rs6000_ieeequad = 1;
2335 warning (0, "Using IEEE extended precision long double");
2340 error ("unknown ABI specified: '%s'", arg);
2346 rs6000_select[1].string = arg;
2350 rs6000_select[2].string = arg;
2353 case OPT_mtraceback_:
2354 rs6000_traceback_name = arg;
2357 case OPT_mfloat_gprs_:
2358 rs6000_explicit_options.float_gprs = true;
2359 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2360 rs6000_float_gprs = 1;
2361 else if (! strcmp (arg, "double"))
2362 rs6000_float_gprs = 2;
2363 else if (! strcmp (arg, "no"))
2364 rs6000_float_gprs = 0;
2367 error ("invalid option for -mfloat-gprs: '%s'", arg);
2372 case OPT_mlong_double_:
2373 rs6000_explicit_options.long_double = true;
2374 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2375 if (value != 64 && value != 128)
2377 error ("Unknown switch -mlong-double-%s", arg);
2378 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2382 rs6000_long_double_type_size = value;
2385 case OPT_msched_costly_dep_:
2386 rs6000_sched_costly_dep_str = arg;
2390 rs6000_explicit_options.alignment = true;
2391 if (! strcmp (arg, "power"))
2393 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2394 some C library functions, so warn about it. The flag may be
2395 useful for performance studies from time to time though, so
2396 don't disable it entirely. */
2397 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2398 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2399 " it is incompatible with the installed C and C++ libraries");
2400 rs6000_alignment_flags = MASK_ALIGN_POWER;
2402 else if (! strcmp (arg, "natural"))
2403 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2406 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2414 /* Do anything needed at the start of the asm file. */
2417 rs6000_file_start (void)
2421 const char *start = buffer;
2422 struct rs6000_cpu_select *ptr;
2423 const char *default_cpu = TARGET_CPU_DEFAULT;
2424 FILE *file = asm_out_file;
2426 default_file_start ();
2428 #ifdef TARGET_BI_ARCH
2429 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2433 if (flag_verbose_asm)
2435 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2436 rs6000_select[0].string = default_cpu;
2438 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2440 ptr = &rs6000_select[i];
2441 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2443 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2448 if (PPC405_ERRATUM77)
2450 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2454 #ifdef USING_ELFOS_H
2455 switch (rs6000_sdata)
2457 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2458 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2459 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2460 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2463 if (rs6000_sdata && g_switch_value)
2465 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2475 #ifdef HAVE_AS_GNU_ATTRIBUTE
2476 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2478 fprintf (file, "\t.gnu_attribute 4, %d\n",
2479 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2480 fprintf (file, "\t.gnu_attribute 8, %d\n",
2481 (TARGET_ALTIVEC_ABI ? 2
2482 : TARGET_SPE_ABI ? 3
2487 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2489 switch_to_section (toc_section);
2490 switch_to_section (text_section);
2495 /* Return nonzero if this function is known to have a null epilogue. */
2498 direct_return (void)
2500 if (reload_completed)
2502 rs6000_stack_t *info = rs6000_stack_info ();
2504 if (info->first_gp_reg_save == 32
2505 && info->first_fp_reg_save == 64
2506 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2507 && ! info->lr_save_p
2508 && ! info->cr_save_p
2509 && info->vrsave_mask == 0
2517 /* Return the number of instructions it takes to form a constant in an
2518 integer register. */
2521 num_insns_constant_wide (HOST_WIDE_INT value)
2523 /* signed constant loadable with {cal|addi} */
2524 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2527 /* constant loadable with {cau|addis} */
2528 else if ((value & 0xffff) == 0
2529 && (value >> 31 == -1 || value >> 31 == 0))
2532 #if HOST_BITS_PER_WIDE_INT == 64
2533 else if (TARGET_POWERPC64)
2535 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2536 HOST_WIDE_INT high = value >> 31;
2538 if (high == 0 || high == -1)
2544 return num_insns_constant_wide (high) + 1;
2546 return (num_insns_constant_wide (high)
2547 + num_insns_constant_wide (low) + 1);
2556 num_insns_constant (rtx op, enum machine_mode mode)
2558 HOST_WIDE_INT low, high;
2560 switch (GET_CODE (op))
2563 #if HOST_BITS_PER_WIDE_INT == 64
2564 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2565 && mask64_operand (op, mode))
2569 return num_insns_constant_wide (INTVAL (op));
2572 if (mode == SFmode || mode == SDmode)
2577 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2578 if (DECIMAL_FLOAT_MODE_P (mode))
2579 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
2581 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2582 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2585 if (mode == VOIDmode || mode == DImode)
2587 high = CONST_DOUBLE_HIGH (op);
2588 low = CONST_DOUBLE_LOW (op);
2595 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2596 if (DECIMAL_FLOAT_MODE_P (mode))
2597 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2599 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2600 high = l[WORDS_BIG_ENDIAN == 0];
2601 low = l[WORDS_BIG_ENDIAN != 0];
2605 return (num_insns_constant_wide (low)
2606 + num_insns_constant_wide (high));
2609 if ((high == 0 && low >= 0)
2610 || (high == -1 && low < 0))
2611 return num_insns_constant_wide (low);
2613 else if (mask64_operand (op, mode))
2617 return num_insns_constant_wide (high) + 1;
2620 return (num_insns_constant_wide (high)
2621 + num_insns_constant_wide (low) + 1);
2629 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2630 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2631 corresponding element of the vector, but for V4SFmode and V2SFmode,
2632 the corresponding "float" is interpreted as an SImode integer. */
2634 static HOST_WIDE_INT
2635 const_vector_elt_as_int (rtx op, unsigned int elt)
2637 rtx tmp = CONST_VECTOR_ELT (op, elt);
2638 if (GET_MODE (op) == V4SFmode
2639 || GET_MODE (op) == V2SFmode)
2640 tmp = gen_lowpart (SImode, tmp);
2641 return INTVAL (tmp);
2644 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2645 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2646 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2647 all items are set to the same value and contain COPIES replicas of the
2648 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2649 operand and the others are set to the value of the operand's msb. */
2652 vspltis_constant (rtx op, unsigned step, unsigned copies)
2654 enum machine_mode mode = GET_MODE (op);
2655 enum machine_mode inner = GET_MODE_INNER (mode);
2658 unsigned nunits = GET_MODE_NUNITS (mode);
2659 unsigned bitsize = GET_MODE_BITSIZE (inner);
2660 unsigned mask = GET_MODE_MASK (inner);
2662 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2663 HOST_WIDE_INT splat_val = val;
2664 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2666 /* Construct the value to be splatted, if possible. If not, return 0. */
2667 for (i = 2; i <= copies; i *= 2)
2669 HOST_WIDE_INT small_val;
2671 small_val = splat_val >> bitsize;
2673 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2675 splat_val = small_val;
2678 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2679 if (EASY_VECTOR_15 (splat_val))
2682 /* Also check if we can splat, and then add the result to itself. Do so if
2683 the value is positive, of if the splat instruction is using OP's mode;
2684 for splat_val < 0, the splat and the add should use the same mode. */
2685 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2686 && (splat_val >= 0 || (step == 1 && copies == 1)))
2692 /* Check if VAL is present in every STEP-th element, and the
2693 other elements are filled with its most significant bit. */
2694 for (i = 0; i < nunits - 1; ++i)
2696 HOST_WIDE_INT desired_val;
2697 if (((i + 1) & (step - 1)) == 0)
2700 desired_val = msb_val;
2702 if (desired_val != const_vector_elt_as_int (op, i))
2710 /* Return true if OP is of the given MODE and can be synthesized
2711 with a vspltisb, vspltish or vspltisw. */
2714 easy_altivec_constant (rtx op, enum machine_mode mode)
2716 unsigned step, copies;
2718 if (mode == VOIDmode)
2719 mode = GET_MODE (op);
2720 else if (mode != GET_MODE (op))
2723 /* Start with a vspltisw. */
2724 step = GET_MODE_NUNITS (mode) / 4;
2727 if (vspltis_constant (op, step, copies))
2730 /* Then try with a vspltish. */
2736 if (vspltis_constant (op, step, copies))
2739 /* And finally a vspltisb. */
2745 if (vspltis_constant (op, step, copies))
2751 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2752 result is OP. Abort if it is not possible. */
2755 gen_easy_altivec_constant (rtx op)
2757 enum machine_mode mode = GET_MODE (op);
2758 int nunits = GET_MODE_NUNITS (mode);
2759 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2760 unsigned step = nunits / 4;
2761 unsigned copies = 1;
2763 /* Start with a vspltisw. */
2764 if (vspltis_constant (op, step, copies))
2765 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2767 /* Then try with a vspltish. */
2773 if (vspltis_constant (op, step, copies))
2774 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2776 /* And finally a vspltisb. */
2782 if (vspltis_constant (op, step, copies))
2783 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2789 output_vec_const_move (rtx *operands)
2792 enum machine_mode mode;
2797 mode = GET_MODE (dest);
2802 if (zero_constant (vec, mode))
2803 return "vxor %0,%0,%0";
2805 splat_vec = gen_easy_altivec_constant (vec);
2806 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2807 operands[1] = XEXP (splat_vec, 0);
2808 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2811 switch (GET_MODE (splat_vec))
2814 return "vspltisw %0,%1";
2817 return "vspltish %0,%1";
2820 return "vspltisb %0,%1";
2827 gcc_assert (TARGET_SPE);
2829 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2830 pattern of V1DI, V4HI, and V2SF.
2832 FIXME: We should probably return # and add post reload
2833 splitters for these, but this way is so easy ;-). */
2834 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2835 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2836 operands[1] = CONST_VECTOR_ELT (vec, 0);
2837 operands[2] = CONST_VECTOR_ELT (vec, 1);
2839 return "li %0,%1\n\tevmergelo %0,%0,%0";
2841 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2844 /* Initialize TARGET of vector PAIRED to VALS. */
2847 paired_expand_vector_init (rtx target, rtx vals)
2849 enum machine_mode mode = GET_MODE (target);
2850 int n_elts = GET_MODE_NUNITS (mode);
2852 rtx x, new, tmp, constant_op, op1, op2;
2855 for (i = 0; i < n_elts; ++i)
2857 x = XVECEXP (vals, 0, i);
2858 if (!CONSTANT_P (x))
2863 /* Load from constant pool. */
2864 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2870 /* The vector is initialized only with non-constants. */
2871 new = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
2872 XVECEXP (vals, 0, 1));
2874 emit_move_insn (target, new);
2878 /* One field is non-constant and the other one is a constant. Load the
2879 constant from the constant pool and use ps_merge instruction to
2880 construct the whole vector. */
2881 op1 = XVECEXP (vals, 0, 0);
2882 op2 = XVECEXP (vals, 0, 1);
2884 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
2886 tmp = gen_reg_rtx (GET_MODE (constant_op));
2887 emit_move_insn (tmp, constant_op);
2889 if (CONSTANT_P (op1))
2890 new = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
2892 new = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
2894 emit_move_insn (target, new);
2898 paired_expand_vector_move (rtx operands[])
2900 rtx op0 = operands[0], op1 = operands[1];
2902 emit_move_insn (op0, op1);
2905 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
2906 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
2907 operands for the relation operation COND. This is a recursive
2911 paired_emit_vector_compare (enum rtx_code rcode,
2912 rtx dest, rtx op0, rtx op1,
2913 rtx cc_op0, rtx cc_op1)
2915 rtx tmp = gen_reg_rtx (V2SFmode);
2916 rtx tmp1, max, min, equal_zero;
2918 gcc_assert (TARGET_PAIRED_FLOAT);
2919 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
2925 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
2929 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
2930 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
2934 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
2937 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
2940 tmp1 = gen_reg_rtx (V2SFmode);
2941 max = gen_reg_rtx (V2SFmode);
2942 min = gen_reg_rtx (V2SFmode);
2943 equal_zero = gen_reg_rtx (V2SFmode);
2945 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
2946 emit_insn (gen_selv2sf4
2947 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
2948 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
2949 emit_insn (gen_selv2sf4
2950 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
2951 emit_insn (gen_subv2sf3 (tmp1, min, max));
2952 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
2955 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
2958 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
2961 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
2964 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
2967 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
2976 /* Emit vector conditional expression.
2977 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
2978 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
2981 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
2982 rtx cond, rtx cc_op0, rtx cc_op1)
2984 enum rtx_code rcode = GET_CODE (cond);
2986 if (!TARGET_PAIRED_FLOAT)
2989 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
2994 /* Initialize vector TARGET to VALS. */
2997 rs6000_expand_vector_init (rtx target, rtx vals)
2999 enum machine_mode mode = GET_MODE (target);
3000 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3001 int n_elts = GET_MODE_NUNITS (mode);
3002 int n_var = 0, one_var = -1;
3003 bool all_same = true, all_const_zero = true;
3007 for (i = 0; i < n_elts; ++i)
3009 x = XVECEXP (vals, 0, i);
3010 if (!CONSTANT_P (x))
3011 ++n_var, one_var = i;
3012 else if (x != CONST0_RTX (inner_mode))
3013 all_const_zero = false;
3015 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
3021 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
3022 if (mode != V4SFmode && all_const_zero)
3024 /* Zero register. */
3025 emit_insn (gen_rtx_SET (VOIDmode, target,
3026 gen_rtx_XOR (mode, target, target)));
3029 else if (mode != V4SFmode && easy_vector_constant (const_vec, mode))
3031 /* Splat immediate. */
3032 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
3036 ; /* Splat vector element. */
3039 /* Load from constant pool. */
3040 emit_move_insn (target, const_vec);
3045 /* Store value to stack temp. Load vector element. Splat. */
3048 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
3049 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
3050 XVECEXP (vals, 0, 0));
3051 x = gen_rtx_UNSPEC (VOIDmode,
3052 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3053 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3055 gen_rtx_SET (VOIDmode,
3058 x = gen_rtx_VEC_SELECT (inner_mode, target,
3059 gen_rtx_PARALLEL (VOIDmode,
3060 gen_rtvec (1, const0_rtx)));
3061 emit_insn (gen_rtx_SET (VOIDmode, target,
3062 gen_rtx_VEC_DUPLICATE (mode, x)));
3066 /* One field is non-constant. Load constant then overwrite
3070 rtx copy = copy_rtx (vals);
3072 /* Load constant part of vector, substitute neighboring value for
3074 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
3075 rs6000_expand_vector_init (target, copy);
3077 /* Insert variable. */
3078 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
3082 /* Construct the vector in memory one field at a time
3083 and load the whole vector. */
3084 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3085 for (i = 0; i < n_elts; i++)
3086 emit_move_insn (adjust_address_nv (mem, inner_mode,
3087 i * GET_MODE_SIZE (inner_mode)),
3088 XVECEXP (vals, 0, i));
3089 emit_move_insn (target, mem);
3092 /* Set field ELT of TARGET to VAL. */
3095 rs6000_expand_vector_set (rtx target, rtx val, int elt)
3097 enum machine_mode mode = GET_MODE (target);
3098 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3099 rtx reg = gen_reg_rtx (mode);
3101 int width = GET_MODE_SIZE (inner_mode);
3104 /* Load single variable value. */
3105 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
3106 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
3107 x = gen_rtx_UNSPEC (VOIDmode,
3108 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3109 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3111 gen_rtx_SET (VOIDmode,
3115 /* Linear sequence. */
3116 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
3117 for (i = 0; i < 16; ++i)
3118 XVECEXP (mask, 0, i) = GEN_INT (i);
3120 /* Set permute mask to insert element into target. */
3121 for (i = 0; i < width; ++i)
3122 XVECEXP (mask, 0, elt*width + i)
3123 = GEN_INT (i + 0x10);
3124 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
3125 x = gen_rtx_UNSPEC (mode,
3126 gen_rtvec (3, target, reg,
3127 force_reg (V16QImode, x)),
3129 emit_insn (gen_rtx_SET (VOIDmode, target, x));
3132 /* Extract field ELT from VEC into TARGET. */
3135 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
3137 enum machine_mode mode = GET_MODE (vec);
3138 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3141 /* Allocate mode-sized buffer. */
3142 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3144 /* Add offset to field within buffer matching vector element. */
3145 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
3147 /* Store single field into mode-sized buffer. */
3148 x = gen_rtx_UNSPEC (VOIDmode,
3149 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
3150 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3152 gen_rtx_SET (VOIDmode,
3155 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
3158 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3159 implement ANDing by the mask IN. */
3161 build_mask64_2_operands (rtx in, rtx *out)
3163 #if HOST_BITS_PER_WIDE_INT >= 64
3164 unsigned HOST_WIDE_INT c, lsb, m1, m2;
3167 gcc_assert (GET_CODE (in) == CONST_INT);
3172 /* Assume c initially something like 0x00fff000000fffff. The idea
3173 is to rotate the word so that the middle ^^^^^^ group of zeros
3174 is at the MS end and can be cleared with an rldicl mask. We then
3175 rotate back and clear off the MS ^^ group of zeros with a
3177 c = ~c; /* c == 0xff000ffffff00000 */
3178 lsb = c & -c; /* lsb == 0x0000000000100000 */
3179 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
3180 c = ~c; /* c == 0x00fff000000fffff */
3181 c &= -lsb; /* c == 0x00fff00000000000 */
3182 lsb = c & -c; /* lsb == 0x0000100000000000 */
3183 c = ~c; /* c == 0xff000fffffffffff */
3184 c &= -lsb; /* c == 0xff00000000000000 */
3186 while ((lsb >>= 1) != 0)
3187 shift++; /* shift == 44 on exit from loop */
3188 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
3189 m1 = ~m1; /* m1 == 0x000000ffffffffff */
3190 m2 = ~c; /* m2 == 0x00ffffffffffffff */
3194 /* Assume c initially something like 0xff000f0000000000. The idea
3195 is to rotate the word so that the ^^^ middle group of zeros
3196 is at the LS end and can be cleared with an rldicr mask. We then
3197 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3199 lsb = c & -c; /* lsb == 0x0000010000000000 */
3200 m2 = -lsb; /* m2 == 0xffffff0000000000 */
3201 c = ~c; /* c == 0x00fff0ffffffffff */
3202 c &= -lsb; /* c == 0x00fff00000000000 */
3203 lsb = c & -c; /* lsb == 0x0000100000000000 */
3204 c = ~c; /* c == 0xff000fffffffffff */
3205 c &= -lsb; /* c == 0xff00000000000000 */
3207 while ((lsb >>= 1) != 0)
3208 shift++; /* shift == 44 on exit from loop */
3209 m1 = ~c; /* m1 == 0x00ffffffffffffff */
3210 m1 >>= shift; /* m1 == 0x0000000000000fff */
3211 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
3214 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3215 masks will be all 1's. We are guaranteed more than one transition. */
3216 out[0] = GEN_INT (64 - shift);
3217 out[1] = GEN_INT (m1);
3218 out[2] = GEN_INT (shift);
3219 out[3] = GEN_INT (m2);
3227 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3230 invalid_e500_subreg (rtx op, enum machine_mode mode)
3232 if (TARGET_E500_DOUBLE)
3234 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3235 subreg:TI and reg:TF. Decimal float modes are like integer
3236 modes (only low part of each register used) for this
3238 if (GET_CODE (op) == SUBREG
3239 && (mode == SImode || mode == DImode || mode == TImode
3240 || mode == DDmode || mode == TDmode)
3241 && REG_P (SUBREG_REG (op))
3242 && (GET_MODE (SUBREG_REG (op)) == DFmode
3243 || GET_MODE (SUBREG_REG (op)) == TFmode))
3246 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3248 if (GET_CODE (op) == SUBREG
3249 && (mode == DFmode || mode == TFmode)
3250 && REG_P (SUBREG_REG (op))
3251 && (GET_MODE (SUBREG_REG (op)) == DImode
3252 || GET_MODE (SUBREG_REG (op)) == TImode
3253 || GET_MODE (SUBREG_REG (op)) == DDmode
3254 || GET_MODE (SUBREG_REG (op)) == TDmode))
3259 && GET_CODE (op) == SUBREG
3261 && REG_P (SUBREG_REG (op))
3262 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
3268 /* AIX increases natural record alignment to doubleword if the first
3269 field is an FP double while the FP fields remain word aligned. */
3272 rs6000_special_round_type_align (tree type, unsigned int computed,
3273 unsigned int specified)
3275 unsigned int align = MAX (computed, specified);
3276 tree field = TYPE_FIELDS (type);
3278 /* Skip all non field decls */
3279 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3280 field = TREE_CHAIN (field);
3282 if (field != NULL && field != type)
3284 type = TREE_TYPE (field);
3285 while (TREE_CODE (type) == ARRAY_TYPE)
3286 type = TREE_TYPE (type);
3288 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
3289 align = MAX (align, 64);
3295 /* Darwin increases record alignment to the natural alignment of
3299 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3300 unsigned int specified)
3302 unsigned int align = MAX (computed, specified);
3304 if (TYPE_PACKED (type))
3307 /* Find the first field, looking down into aggregates. */
3309 tree field = TYPE_FIELDS (type);
3310 /* Skip all non field decls */
3311 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3312 field = TREE_CHAIN (field);
3315 type = TREE_TYPE (field);
3316 while (TREE_CODE (type) == ARRAY_TYPE)
3317 type = TREE_TYPE (type);
3318 } while (AGGREGATE_TYPE_P (type));
3320 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3321 align = MAX (align, TYPE_ALIGN (type));
3326 /* Return 1 for an operand in small memory on V.4/eabi. */
3329 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3330 enum machine_mode mode ATTRIBUTE_UNUSED)
3335 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3338 if (DEFAULT_ABI != ABI_V4)
3341 /* Vector and float memory instructions have a limited offset on the
3342 SPE, so using a vector or float variable directly as an operand is
3345 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
3348 if (GET_CODE (op) == SYMBOL_REF)
3351 else if (GET_CODE (op) != CONST
3352 || GET_CODE (XEXP (op, 0)) != PLUS
3353 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3354 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3359 rtx sum = XEXP (op, 0);
3360 HOST_WIDE_INT summand;
3362 /* We have to be careful here, because it is the referenced address
3363 that must be 32k from _SDA_BASE_, not just the symbol. */
3364 summand = INTVAL (XEXP (sum, 1));
3365 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3368 sym_ref = XEXP (sum, 0);
3371 return SYMBOL_REF_SMALL_P (sym_ref);
3377 /* Return true if either operand is a general purpose register. */
3380 gpr_or_gpr_p (rtx op0, rtx op1)
3382 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3383 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3387 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3390 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3392 switch (GET_CODE (op))
3395 if (RS6000_SYMBOL_REF_TLS_P (op))
3397 else if (CONSTANT_POOL_ADDRESS_P (op))
3399 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3407 else if (! strcmp (XSTR (op, 0), toc_label_name))
3416 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3417 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3419 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3428 constant_pool_expr_p (rtx op)
3432 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3436 toc_relative_expr_p (rtx op)
3440 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3444 legitimate_constant_pool_address_p (rtx x)
3447 && GET_CODE (x) == PLUS
3448 && GET_CODE (XEXP (x, 0)) == REG
3449 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3450 && constant_pool_expr_p (XEXP (x, 1)));
3454 legitimate_small_data_p (enum machine_mode mode, rtx x)
3456 return (DEFAULT_ABI == ABI_V4
3457 && !flag_pic && !TARGET_TOC
3458 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3459 && small_data_operand (x, mode));
3462 /* SPE offset addressing is limited to 5-bits worth of double words. */
3463 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3466 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3468 unsigned HOST_WIDE_INT offset, extra;
3470 if (GET_CODE (x) != PLUS)
3472 if (GET_CODE (XEXP (x, 0)) != REG)
3474 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3476 if (legitimate_constant_pool_address_p (x))
3478 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3481 offset = INTVAL (XEXP (x, 1));
3489 /* AltiVec vector modes. Only reg+reg addressing is valid and
3490 constant offset zero should not occur due to canonicalization. */
3497 /* Paired vector modes. Only reg+reg addressing is valid and
3498 constant offset zero should not occur due to canonicalization. */
3499 if (TARGET_PAIRED_FLOAT)
3501 /* SPE vector modes. */
3502 return SPE_CONST_OFFSET_OK (offset);
3505 if (TARGET_E500_DOUBLE)
3506 return SPE_CONST_OFFSET_OK (offset);
3510 /* On e500v2, we may have:
3512 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3514 Which gets addressed with evldd instructions. */
3515 if (TARGET_E500_DOUBLE)
3516 return SPE_CONST_OFFSET_OK (offset);
3518 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3520 else if (offset & 3)
3525 if (TARGET_E500_DOUBLE)
3526 return (SPE_CONST_OFFSET_OK (offset)
3527 && SPE_CONST_OFFSET_OK (offset + 8));
3531 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3533 else if (offset & 3)
3544 return (offset < 0x10000) && (offset + extra < 0x10000);
3548 legitimate_indexed_address_p (rtx x, int strict)
3552 if (GET_CODE (x) != PLUS)
3558 /* Recognize the rtl generated by reload which we know will later be
3559 replaced with proper base and index regs. */
3561 && reload_in_progress
3562 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3566 return (REG_P (op0) && REG_P (op1)
3567 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3568 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3569 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3570 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3574 legitimate_indirect_address_p (rtx x, int strict)
3576 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3580 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3582 if (!TARGET_MACHO || !flag_pic
3583 || mode != SImode || GET_CODE (x) != MEM)
3587 if (GET_CODE (x) != LO_SUM)
3589 if (GET_CODE (XEXP (x, 0)) != REG)
3591 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3595 return CONSTANT_P (x);
3599 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3601 if (GET_CODE (x) != LO_SUM)
3603 if (GET_CODE (XEXP (x, 0)) != REG)
3605 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3607 /* Restrict addressing for DI because of our SUBREG hackery. */
3608 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3609 || mode == DDmode || mode == TDmode
3614 if (TARGET_ELF || TARGET_MACHO)
3616 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3620 if (GET_MODE_NUNITS (mode) != 1)
3622 if (GET_MODE_BITSIZE (mode) > 64
3623 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3624 && !(TARGET_HARD_FLOAT && TARGET_FPRS
3625 && (mode == DFmode || mode == DDmode))))
3628 return CONSTANT_P (x);
3635 /* Try machine-dependent ways of modifying an illegitimate address
3636 to be legitimate. If we find one, return the new, valid address.
3637 This is used from only one place: `memory_address' in explow.c.
3639 OLDX is the address as it was before break_out_memory_refs was
3640 called. In some cases it is useful to look at this to decide what
3643 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3645 It is always safe for this function to do nothing. It exists to
3646 recognize opportunities to optimize the output.
3648 On RS/6000, first check for the sum of a register with a constant
3649 integer that is out of range. If so, generate code to add the
3650 constant with the low-order 16 bits masked to the register and force
3651 this result into another register (this can be done with `cau').
3652 Then generate an address of REG+(CONST&0xffff), allowing for the
3653 possibility of bit 16 being a one.
3655 Then check for the sum of a register and something not constant, try to
3656 load the other things into a register and return the sum. */
3659 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3660 enum machine_mode mode)
3662 if (GET_CODE (x) == SYMBOL_REF)
3664 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3666 return rs6000_legitimize_tls_address (x, model);
3669 if (GET_CODE (x) == PLUS
3670 && GET_CODE (XEXP (x, 0)) == REG
3671 && GET_CODE (XEXP (x, 1)) == CONST_INT
3672 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
3673 && !(SPE_VECTOR_MODE (mode)
3674 || ALTIVEC_VECTOR_MODE (mode)
3675 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3676 || mode == DImode || mode == DDmode
3677 || mode == TDmode))))
3679 HOST_WIDE_INT high_int, low_int;
3681 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3682 high_int = INTVAL (XEXP (x, 1)) - low_int;
3683 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3684 GEN_INT (high_int)), 0);
3685 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3687 else if (GET_CODE (x) == PLUS
3688 && GET_CODE (XEXP (x, 0)) == REG
3689 && GET_CODE (XEXP (x, 1)) != CONST_INT
3690 && GET_MODE_NUNITS (mode) == 1
3691 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3693 || ((mode != DImode && mode != DFmode && mode != DDmode)
3694 || (TARGET_E500_DOUBLE && mode != DDmode)))
3695 && (TARGET_POWERPC64 || mode != DImode)
3700 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3701 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3703 else if (ALTIVEC_VECTOR_MODE (mode))
3707 /* Make sure both operands are registers. */
3708 if (GET_CODE (x) == PLUS)
3709 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3710 force_reg (Pmode, XEXP (x, 1)));
3712 reg = force_reg (Pmode, x);
3715 else if (SPE_VECTOR_MODE (mode)
3716 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3717 || mode == DDmode || mode == TDmode
3718 || mode == DImode)))
3722 /* We accept [reg + reg] and [reg + OFFSET]. */
3724 if (GET_CODE (x) == PLUS)
3726 rtx op1 = XEXP (x, 0);
3727 rtx op2 = XEXP (x, 1);
3730 op1 = force_reg (Pmode, op1);
3732 if (GET_CODE (op2) != REG
3733 && (GET_CODE (op2) != CONST_INT
3734 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
3735 || (GET_MODE_SIZE (mode) > 8
3736 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
3737 op2 = force_reg (Pmode, op2);
3739 /* We can't always do [reg + reg] for these, because [reg +
3740 reg + offset] is not a legitimate addressing mode. */
3741 y = gen_rtx_PLUS (Pmode, op1, op2);
3743 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
3744 return force_reg (Pmode, y);
3749 return force_reg (Pmode, x);
3755 && GET_CODE (x) != CONST_INT
3756 && GET_CODE (x) != CONST_DOUBLE
3758 && GET_MODE_NUNITS (mode) == 1
3759 && (GET_MODE_BITSIZE (mode) <= 32
3760 || ((TARGET_HARD_FLOAT && TARGET_FPRS)
3761 && (mode == DFmode || mode == DDmode))))
3763 rtx reg = gen_reg_rtx (Pmode);
3764 emit_insn (gen_elf_high (reg, x));
3765 return gen_rtx_LO_SUM (Pmode, reg, x);
3767 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3770 && ! MACHO_DYNAMIC_NO_PIC_P
3772 && GET_CODE (x) != CONST_INT
3773 && GET_CODE (x) != CONST_DOUBLE
3775 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3776 || (mode != DFmode && mode != DDmode))
3780 rtx reg = gen_reg_rtx (Pmode);
3781 emit_insn (gen_macho_high (reg, x));
3782 return gen_rtx_LO_SUM (Pmode, reg, x);
3785 && GET_CODE (x) == SYMBOL_REF
3786 && constant_pool_expr_p (x)
3787 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3789 return create_TOC_reference (x);
3795 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3796 We need to emit DTP-relative relocations. */
3799 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3804 fputs ("\t.long\t", file);
3807 fputs (DOUBLE_INT_ASM_OP, file);
3812 output_addr_const (file, x);
3813 fputs ("@dtprel+0x8000", file);
3816 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3818 static GTY(()) rtx rs6000_tls_symbol;
3820 rs6000_tls_get_addr (void)
3822 if (!rs6000_tls_symbol)
3823 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3825 return rs6000_tls_symbol;
3828 /* Construct the SYMBOL_REF for TLS GOT references. */
3830 static GTY(()) rtx rs6000_got_symbol;
3832 rs6000_got_sym (void)
3834 if (!rs6000_got_symbol)
3836 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3837 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3838 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3841 return rs6000_got_symbol;
3844 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3845 this (thread-local) address. */
3848 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3852 dest = gen_reg_rtx (Pmode);
3853 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3859 tlsreg = gen_rtx_REG (Pmode, 13);
3860 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3864 tlsreg = gen_rtx_REG (Pmode, 2);
3865 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3869 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3873 tmp = gen_reg_rtx (Pmode);
3876 tlsreg = gen_rtx_REG (Pmode, 13);
3877 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3881 tlsreg = gen_rtx_REG (Pmode, 2);
3882 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3886 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3888 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3893 rtx r3, got, tga, tmp1, tmp2, eqv;
3895 /* We currently use relocations like @got@tlsgd for tls, which
3896 means the linker will handle allocation of tls entries, placing
3897 them in the .got section. So use a pointer to the .got section,
3898 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3899 or to secondary GOT sections used by 32-bit -fPIC. */
3901 got = gen_rtx_REG (Pmode, 2);
3905 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3908 rtx gsym = rs6000_got_sym ();
3909 got = gen_reg_rtx (Pmode);
3911 rs6000_emit_move (got, gsym, Pmode);
3917 tmp1 = gen_reg_rtx (Pmode);
3918 tmp2 = gen_reg_rtx (Pmode);
3919 tmp3 = gen_reg_rtx (Pmode);
3920 mem = gen_const_mem (Pmode, tmp1);
3922 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3923 emit_move_insn (tmp1,
3924 gen_rtx_REG (Pmode, LR_REGNO));
3925 emit_move_insn (tmp2, mem);
3926 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3927 last = emit_move_insn (got, tmp3);
3928 set_unique_reg_note (last, REG_EQUAL, gsym);
3933 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3935 r3 = gen_rtx_REG (Pmode, 3);
3936 tga = rs6000_tls_get_addr ();
3938 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
3939 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
3940 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
3941 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
3942 else if (DEFAULT_ABI == ABI_V4)
3943 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
3948 insn = emit_call_insn (insn);
3949 RTL_CONST_CALL_P (insn) = 1;
3950 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3951 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
3952 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3953 insn = get_insns ();
3955 emit_libcall_block (insn, dest, r3, addr);
3957 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3959 r3 = gen_rtx_REG (Pmode, 3);
3960 tga = rs6000_tls_get_addr ();
3962 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
3963 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
3964 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
3965 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
3966 else if (DEFAULT_ABI == ABI_V4)
3967 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
3972 insn = emit_call_insn (insn);
3973 RTL_CONST_CALL_P (insn) = 1;
3974 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3975 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
3976 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3977 insn = get_insns ();
3979 tmp1 = gen_reg_rtx (Pmode);
3980 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3982 emit_libcall_block (insn, tmp1, r3, eqv);
3983 if (rs6000_tls_size == 16)
3986 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3988 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3990 else if (rs6000_tls_size == 32)
3992 tmp2 = gen_reg_rtx (Pmode);
3994 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3996 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3999 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
4001 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
4005 tmp2 = gen_reg_rtx (Pmode);
4007 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
4009 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
4011 insn = gen_rtx_SET (Pmode, dest,
4012 gen_rtx_PLUS (Pmode, tmp2, tmp1));
4018 /* IE, or 64-bit offset LE. */
4019 tmp2 = gen_reg_rtx (Pmode);
4021 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
4023 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
4026 insn = gen_tls_tls_64 (dest, tmp2, addr);
4028 insn = gen_tls_tls_32 (dest, tmp2, addr);
4036 /* Return 1 if X contains a thread-local symbol. */
4039 rs6000_tls_referenced_p (rtx x)
4041 if (! TARGET_HAVE_TLS)
4044 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
4047 /* Return 1 if *X is a thread-local symbol. This is the same as
4048 rs6000_tls_symbol_ref except for the type of the unused argument. */
4051 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4053 return RS6000_SYMBOL_REF_TLS_P (*x);
4056 /* The convention appears to be to define this wherever it is used.
4057 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
4058 is now used here. */
4059 #ifndef REG_MODE_OK_FOR_BASE_P
4060 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
4063 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4064 replace the input X, or the original X if no replacement is called for.
4065 The output parameter *WIN is 1 if the calling macro should goto WIN,
4068 For RS/6000, we wish to handle large displacements off a base
4069 register by splitting the addend across an addiu/addis and the mem insn.
4070 This cuts number of extra insns needed from 3 to 1.
4072 On Darwin, we use this to generate code for floating point constants.
4073 A movsf_low is generated so we wind up with 2 instructions rather than 3.
4074 The Darwin code is inside #if TARGET_MACHO because only then is
4075 machopic_function_base_name() defined. */
4077 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
4078 int opnum, int type,
4079 int ind_levels ATTRIBUTE_UNUSED, int *win)
4081 /* We must recognize output that we have already generated ourselves. */
4082 if (GET_CODE (x) == PLUS
4083 && GET_CODE (XEXP (x, 0)) == PLUS
4084 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4085 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4086 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4088 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4089 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4090 opnum, (enum reload_type)type);
4096 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
4097 && GET_CODE (x) == LO_SUM
4098 && GET_CODE (XEXP (x, 0)) == PLUS
4099 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
4100 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
4101 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
4102 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
4103 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
4104 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
4105 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
4107 /* Result of previous invocation of this function on Darwin
4108 floating point constant. */
4109 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4110 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4111 opnum, (enum reload_type)type);
4117 /* Force ld/std non-word aligned offset into base register by wrapping
4119 if (GET_CODE (x) == PLUS
4120 && GET_CODE (XEXP (x, 0)) == REG
4121 && REGNO (XEXP (x, 0)) < 32
4122 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4123 && GET_CODE (XEXP (x, 1)) == CONST_INT
4124 && (INTVAL (XEXP (x, 1)) & 3) != 0
4125 && !ALTIVEC_VECTOR_MODE (mode)
4126 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
4127 && TARGET_POWERPC64)
4129 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
4130 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4131 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4132 opnum, (enum reload_type) type);
4137 if (GET_CODE (x) == PLUS
4138 && GET_CODE (XEXP (x, 0)) == REG
4139 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
4140 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4141 && GET_CODE (XEXP (x, 1)) == CONST_INT
4142 && !SPE_VECTOR_MODE (mode)
4143 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
4144 || mode == DDmode || mode == TDmode
4146 && !ALTIVEC_VECTOR_MODE (mode))
4148 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
4149 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
4151 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4153 /* Check for 32-bit overflow. */
4154 if (high + low != val)
4160 /* Reload the high part into a base reg; leave the low part
4161 in the mem directly. */
4163 x = gen_rtx_PLUS (GET_MODE (x),
4164 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
4168 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4169 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4170 opnum, (enum reload_type)type);
4175 if (GET_CODE (x) == SYMBOL_REF
4176 && !ALTIVEC_VECTOR_MODE (mode)
4177 && !SPE_VECTOR_MODE (mode)
4179 && DEFAULT_ABI == ABI_DARWIN
4180 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
4182 && DEFAULT_ABI == ABI_V4
4185 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4186 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4190 && (mode != DImode || TARGET_POWERPC64)
4191 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
4192 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
4197 rtx offset = gen_rtx_CONST (Pmode,
4198 gen_rtx_MINUS (Pmode, x,
4199 machopic_function_base_sym ()));
4200 x = gen_rtx_LO_SUM (GET_MODE (x),
4201 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
4202 gen_rtx_HIGH (Pmode, offset)), offset);
4206 x = gen_rtx_LO_SUM (GET_MODE (x),
4207 gen_rtx_HIGH (Pmode, x), x);
4209 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4210 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4211 opnum, (enum reload_type)type);
4216 /* Reload an offset address wrapped by an AND that represents the
4217 masking of the lower bits. Strip the outer AND and let reload
4218 convert the offset address into an indirect address. */
4220 && ALTIVEC_VECTOR_MODE (mode)
4221 && GET_CODE (x) == AND
4222 && GET_CODE (XEXP (x, 0)) == PLUS
4223 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4224 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4225 && GET_CODE (XEXP (x, 1)) == CONST_INT
4226 && INTVAL (XEXP (x, 1)) == -16)
4234 && GET_CODE (x) == SYMBOL_REF
4235 && constant_pool_expr_p (x)
4236 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
4238 x = create_TOC_reference (x);
4246 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4247 that is a valid memory address for an instruction.
4248 The MODE argument is the machine mode for the MEM expression
4249 that wants to use this address.
4251 On the RS/6000, there are four valid address: a SYMBOL_REF that
4252 refers to a constant pool entry of an address (or the sum of it
4253 plus a constant), a short (16-bit signed) constant plus a register,
4254 the sum of two registers, or a register indirect, possibly with an
4255 auto-increment. For DFmode, DDmode and DImode with a constant plus
4256 register, we must ensure that both words are addressable or PowerPC64
4257 with offset word aligned.
4259 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4260 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4261 because adjacent memory cells are accessed by adding word-sized offsets
4262 during assembly output. */
4264 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
4266 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4268 && ALTIVEC_VECTOR_MODE (mode)
4269 && GET_CODE (x) == AND
4270 && GET_CODE (XEXP (x, 1)) == CONST_INT
4271 && INTVAL (XEXP (x, 1)) == -16)
4274 if (RS6000_SYMBOL_REF_TLS_P (x))
4276 if (legitimate_indirect_address_p (x, reg_ok_strict))
4278 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
4279 && !ALTIVEC_VECTOR_MODE (mode)
4280 && !SPE_VECTOR_MODE (mode)
4283 /* Restrict addressing for DI because of our SUBREG hackery. */
4284 && !(TARGET_E500_DOUBLE
4285 && (mode == DFmode || mode == DDmode || mode == DImode))
4287 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
4289 if (legitimate_small_data_p (mode, x))
4291 if (legitimate_constant_pool_address_p (x))
4293 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4295 && GET_CODE (x) == PLUS
4296 && GET_CODE (XEXP (x, 0)) == REG
4297 && (XEXP (x, 0) == virtual_stack_vars_rtx
4298 || XEXP (x, 0) == arg_pointer_rtx)
4299 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4301 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
4306 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4308 || (mode != DFmode && mode != DDmode)
4309 || (TARGET_E500_DOUBLE && mode != DDmode))
4310 && (TARGET_POWERPC64 || mode != DImode)
4311 && legitimate_indexed_address_p (x, reg_ok_strict))
4313 if (GET_CODE (x) == PRE_MODIFY
4317 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4319 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
4320 && (TARGET_POWERPC64 || mode != DImode)
4321 && !ALTIVEC_VECTOR_MODE (mode)
4322 && !SPE_VECTOR_MODE (mode)
4323 /* Restrict addressing for DI because of our SUBREG hackery. */
4324 && !(TARGET_E500_DOUBLE
4325 && (mode == DFmode || mode == DDmode || mode == DImode))
4327 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
4328 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
4329 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
4330 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4332 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
4337 /* Go to LABEL if ADDR (a legitimate address expression)
4338 has an effect that depends on the machine mode it is used for.
4340 On the RS/6000 this is true of all integral offsets (since AltiVec
4341 modes don't allow them) or is a pre-increment or decrement.
4343 ??? Except that due to conceptual problems in offsettable_address_p
4344 we can't really report the problems of integral offsets. So leave
4345 this assuming that the adjustable offset must be valid for the
4346 sub-words of a TFmode operand, which is what we had before. */
4349 rs6000_mode_dependent_address (rtx addr)
4351 switch (GET_CODE (addr))
4354 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4356 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4357 return val + 12 + 0x8000 >= 0x10000;
4364 /* Auto-increment cases are now treated generically in recog.c. */
4366 return TARGET_UPDATE;
4375 /* More elaborate version of recog's offsettable_memref_p predicate
4376 that works around the ??? note of rs6000_mode_dependent_address.
4377 In particular it accepts
4379 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4381 in 32-bit mode, that the recog predicate rejects. */
4384 rs6000_offsettable_memref_p (rtx op)
4389 /* First mimic offsettable_memref_p. */
4390 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4393 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4394 the latter predicate knows nothing about the mode of the memory
4395 reference and, therefore, assumes that it is the largest supported
4396 mode (TFmode). As a consequence, legitimate offsettable memory
4397 references are rejected. rs6000_legitimate_offset_address_p contains
4398 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4399 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4402 /* Return number of consecutive hard regs needed starting at reg REGNO
4403 to hold something of mode MODE.
4404 This is ordinarily the length in words of a value of mode MODE
4405 but can be less for certain modes in special long registers.
4407 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4408 scalar instructions. The upper 32 bits are only available to the
4411 POWER and PowerPC GPRs hold 32 bits worth;
4412 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4415 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4417 if (FP_REGNO_P (regno))
4418 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4420 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4421 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4423 if (ALTIVEC_REGNO_P (regno))
4425 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4427 /* The value returned for SCmode in the E500 double case is 2 for
4428 ABI compatibility; storing an SCmode value in a single register
4429 would require function_arg and rs6000_spe_function_arg to handle
4430 SCmode so as to pass the value correctly in a pair of
4432 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
4433 && !DECIMAL_FLOAT_MODE_P (mode))
4434 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4436 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4439 /* Change register usage conditional on target flags. */
4441 rs6000_conditional_register_usage (void)
4445 /* Set MQ register fixed (already call_used) if not POWER
4446 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4451 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4453 fixed_regs[13] = call_used_regs[13]
4454 = call_really_used_regs[13] = 1;
4456 /* Conditionally disable FPRs. */
4457 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4458 for (i = 32; i < 64; i++)
4459 fixed_regs[i] = call_used_regs[i]
4460 = call_really_used_regs[i] = 1;
4462 /* The TOC register is not killed across calls in a way that is
4463 visible to the compiler. */
4464 if (DEFAULT_ABI == ABI_AIX)
4465 call_really_used_regs[2] = 0;
4467 if (DEFAULT_ABI == ABI_V4
4468 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4470 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4472 if (DEFAULT_ABI == ABI_V4
4473 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4475 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4476 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4477 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4479 if (DEFAULT_ABI == ABI_DARWIN
4480 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4481 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4482 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4483 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4485 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4486 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4487 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4491 global_regs[SPEFSCR_REGNO] = 1;
4492 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4493 registers in prologues and epilogues. We no longer use r14
4494 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4495 pool for link-compatibility with older versions of GCC. Once
4496 "old" code has died out, we can return r14 to the allocation
4499 = call_used_regs[14]
4500 = call_really_used_regs[14] = 1;
4503 if (!TARGET_ALTIVEC)
4505 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4506 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4507 call_really_used_regs[VRSAVE_REGNO] = 1;
4511 global_regs[VSCR_REGNO] = 1;
4513 if (TARGET_ALTIVEC_ABI)
4515 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4516 call_used_regs[i] = call_really_used_regs[i] = 1;
4518 /* AIX reserves VR20:31 in non-extended ABI mode. */
4520 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
4521 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4525 /* Try to output insns to set TARGET equal to the constant C if it can
4526 be done in less than N insns. Do all computations in MODE.
4527 Returns the place where the output has been placed if it can be
4528 done and the insns have been emitted. If it would take more than N
4529 insns, zero is returned and no insns and emitted. */
4532 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4533 rtx source, int n ATTRIBUTE_UNUSED)
4535 rtx result, insn, set;
4536 HOST_WIDE_INT c0, c1;
4543 dest = gen_reg_rtx (mode);
4544 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4548 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4550 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4551 GEN_INT (INTVAL (source)
4552 & (~ (HOST_WIDE_INT) 0xffff))));
4553 emit_insn (gen_rtx_SET (VOIDmode, dest,
4554 gen_rtx_IOR (SImode, copy_rtx (result),
4555 GEN_INT (INTVAL (source) & 0xffff))));
4560 switch (GET_CODE (source))
4563 c0 = INTVAL (source);
4568 #if HOST_BITS_PER_WIDE_INT >= 64
4569 c0 = CONST_DOUBLE_LOW (source);
4572 c0 = CONST_DOUBLE_LOW (source);
4573 c1 = CONST_DOUBLE_HIGH (source);
4581 result = rs6000_emit_set_long_const (dest, c0, c1);
4588 insn = get_last_insn ();
4589 set = single_set (insn);
4590 if (! CONSTANT_P (SET_SRC (set)))
4591 set_unique_reg_note (insn, REG_EQUAL, source);
4596 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4597 fall back to a straight forward decomposition. We do this to avoid
4598 exponential run times encountered when looking for longer sequences
4599 with rs6000_emit_set_const. */
4601 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4603 if (!TARGET_POWERPC64)
4605 rtx operand1, operand2;
4607 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4609 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4611 emit_move_insn (operand1, GEN_INT (c1));
4612 emit_move_insn (operand2, GEN_INT (c2));
4616 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4619 ud2 = (c1 & 0xffff0000) >> 16;
4620 #if HOST_BITS_PER_WIDE_INT >= 64
4624 ud4 = (c2 & 0xffff0000) >> 16;
4626 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4627 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4630 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4632 emit_move_insn (dest, GEN_INT (ud1));
4635 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4636 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4639 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4642 emit_move_insn (dest, GEN_INT (ud2 << 16));
4644 emit_move_insn (copy_rtx (dest),
4645 gen_rtx_IOR (DImode, copy_rtx (dest),
4648 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4649 || (ud4 == 0 && ! (ud3 & 0x8000)))
4652 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4655 emit_move_insn (dest, GEN_INT (ud3 << 16));
4658 emit_move_insn (copy_rtx (dest),
4659 gen_rtx_IOR (DImode, copy_rtx (dest),
4661 emit_move_insn (copy_rtx (dest),
4662 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4665 emit_move_insn (copy_rtx (dest),
4666 gen_rtx_IOR (DImode, copy_rtx (dest),
4672 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4675 emit_move_insn (dest, GEN_INT (ud4 << 16));
4678 emit_move_insn (copy_rtx (dest),
4679 gen_rtx_IOR (DImode, copy_rtx (dest),
4682 emit_move_insn (copy_rtx (dest),
4683 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4686 emit_move_insn (copy_rtx (dest),
4687 gen_rtx_IOR (DImode, copy_rtx (dest),
4688 GEN_INT (ud2 << 16)));
4690 emit_move_insn (copy_rtx (dest),
4691 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4697 /* Helper for the following. Get rid of [r+r] memory refs
4698 in cases where it won't work (TImode, TFmode, TDmode). */
4701 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4703 if (GET_CODE (operands[0]) == MEM
4704 && GET_CODE (XEXP (operands[0], 0)) != REG
4705 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4706 && ! reload_in_progress)
4708 = replace_equiv_address (operands[0],
4709 copy_addr_to_reg (XEXP (operands[0], 0)));
4711 if (GET_CODE (operands[1]) == MEM
4712 && GET_CODE (XEXP (operands[1], 0)) != REG
4713 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4714 && ! reload_in_progress)
4716 = replace_equiv_address (operands[1],
4717 copy_addr_to_reg (XEXP (operands[1], 0)));
4720 /* Emit a move from SOURCE to DEST in mode MODE. */
4722 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4726 operands[1] = source;
4728 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4729 if (GET_CODE (operands[1]) == CONST_DOUBLE
4730 && ! FLOAT_MODE_P (mode)
4731 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4733 /* FIXME. This should never happen. */
4734 /* Since it seems that it does, do the safe thing and convert
4736 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4738 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4739 || FLOAT_MODE_P (mode)
4740 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4741 || CONST_DOUBLE_LOW (operands[1]) < 0)
4742 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4743 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4745 /* Check if GCC is setting up a block move that will end up using FP
4746 registers as temporaries. We must make sure this is acceptable. */
4747 if (GET_CODE (operands[0]) == MEM
4748 && GET_CODE (operands[1]) == MEM
4750 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4751 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4752 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4753 ? 32 : MEM_ALIGN (operands[0])))
4754 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4756 : MEM_ALIGN (operands[1]))))
4757 && ! MEM_VOLATILE_P (operands [0])
4758 && ! MEM_VOLATILE_P (operands [1]))
4760 emit_move_insn (adjust_address (operands[0], SImode, 0),
4761 adjust_address (operands[1], SImode, 0));
4762 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4763 adjust_address (copy_rtx (operands[1]), SImode, 4));
4767 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4768 && !gpc_reg_operand (operands[1], mode))
4769 operands[1] = force_reg (mode, operands[1]);
4771 if (mode == SFmode && ! TARGET_POWERPC
4772 && TARGET_HARD_FLOAT && TARGET_FPRS
4773 && GET_CODE (operands[0]) == MEM)
4777 if (reload_in_progress || reload_completed)
4778 regnum = true_regnum (operands[1]);
4779 else if (GET_CODE (operands[1]) == REG)
4780 regnum = REGNO (operands[1]);
4784 /* If operands[1] is a register, on POWER it may have
4785 double-precision data in it, so truncate it to single
4787 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4790 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4791 : gen_reg_rtx (mode));
4792 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4793 operands[1] = newreg;
4797 /* Recognize the case where operand[1] is a reference to thread-local
4798 data and load its address to a register. */
4799 if (rs6000_tls_referenced_p (operands[1]))
4801 enum tls_model model;
4802 rtx tmp = operands[1];
4805 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4807 addend = XEXP (XEXP (tmp, 0), 1);
4808 tmp = XEXP (XEXP (tmp, 0), 0);
4811 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4812 model = SYMBOL_REF_TLS_MODEL (tmp);
4813 gcc_assert (model != 0);
4815 tmp = rs6000_legitimize_tls_address (tmp, model);
4818 tmp = gen_rtx_PLUS (mode, tmp, addend);
4819 tmp = force_operand (tmp, operands[0]);
4824 /* Handle the case where reload calls us with an invalid address. */
4825 if (reload_in_progress && mode == Pmode
4826 && (! general_operand (operands[1], mode)
4827 || ! nonimmediate_operand (operands[0], mode)))
4830 /* 128-bit constant floating-point values on Darwin should really be
4831 loaded as two parts. */
4832 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4833 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4835 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4836 know how to get a DFmode SUBREG of a TFmode. */
4837 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4838 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4839 simplify_gen_subreg (imode, operands[1], mode, 0),
4841 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4842 GET_MODE_SIZE (imode)),
4843 simplify_gen_subreg (imode, operands[1], mode,
4844 GET_MODE_SIZE (imode)),
4849 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
4850 cfun->machine->sdmode_stack_slot =
4851 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
4853 if (reload_in_progress
4855 && MEM_P (operands[0])
4856 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
4857 && REG_P (operands[1]))
4859 if (FP_REGNO_P (REGNO (operands[1])))
4861 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
4862 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4863 emit_insn (gen_movsd_store (mem, operands[1]));
4865 else if (INT_REGNO_P (REGNO (operands[1])))
4867 rtx mem = adjust_address_nv (operands[0], mode, 4);
4868 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4869 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
4875 if (reload_in_progress
4877 && REG_P (operands[0])
4878 && MEM_P (operands[1])
4879 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
4881 if (FP_REGNO_P (REGNO (operands[0])))
4883 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
4884 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4885 emit_insn (gen_movsd_load (operands[0], mem));
4887 else if (INT_REGNO_P (REGNO (operands[0])))
4889 rtx mem = adjust_address_nv (operands[1], mode, 4);
4890 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
4891 emit_insn (gen_movsd_hardfloat (operands[0], mem));
4898 /* FIXME: In the long term, this switch statement should go away
4899 and be replaced by a sequence of tests based on things like
4905 if (CONSTANT_P (operands[1])
4906 && GET_CODE (operands[1]) != CONST_INT)
4907 operands[1] = force_const_mem (mode, operands[1]);
4912 rs6000_eliminate_indexed_memrefs (operands);
4919 if (CONSTANT_P (operands[1])
4920 && ! easy_fp_constant (operands[1], mode))
4921 operands[1] = force_const_mem (mode, operands[1]);
4932 if (CONSTANT_P (operands[1])
4933 && !easy_vector_constant (operands[1], mode))
4934 operands[1] = force_const_mem (mode, operands[1]);
4939 /* Use default pattern for address of ELF small data */
4942 && DEFAULT_ABI == ABI_V4
4943 && (GET_CODE (operands[1]) == SYMBOL_REF
4944 || GET_CODE (operands[1]) == CONST)
4945 && small_data_operand (operands[1], mode))
4947 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4951 if (DEFAULT_ABI == ABI_V4
4952 && mode == Pmode && mode == SImode
4953 && flag_pic == 1 && got_operand (operands[1], mode))
4955 emit_insn (gen_movsi_got (operands[0], operands[1]));
4959 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4963 && CONSTANT_P (operands[1])
4964 && GET_CODE (operands[1]) != HIGH
4965 && GET_CODE (operands[1]) != CONST_INT)
4967 rtx target = (!can_create_pseudo_p ()
4969 : gen_reg_rtx (mode));
4971 /* If this is a function address on -mcall-aixdesc,
4972 convert it to the address of the descriptor. */
4973 if (DEFAULT_ABI == ABI_AIX
4974 && GET_CODE (operands[1]) == SYMBOL_REF
4975 && XSTR (operands[1], 0)[0] == '.')
4977 const char *name = XSTR (operands[1], 0);
4979 while (*name == '.')
4981 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4982 CONSTANT_POOL_ADDRESS_P (new_ref)
4983 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4984 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4985 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4986 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4987 operands[1] = new_ref;
4990 if (DEFAULT_ABI == ABI_DARWIN)
4993 if (MACHO_DYNAMIC_NO_PIC_P)
4995 /* Take care of any required data indirection. */
4996 operands[1] = rs6000_machopic_legitimize_pic_address (
4997 operands[1], mode, operands[0]);
4998 if (operands[0] != operands[1])
4999 emit_insn (gen_rtx_SET (VOIDmode,
5000 operands[0], operands[1]));
5004 emit_insn (gen_macho_high (target, operands[1]));
5005 emit_insn (gen_macho_low (operands[0], target, operands[1]));
5009 emit_insn (gen_elf_high (target, operands[1]));
5010 emit_insn (gen_elf_low (operands[0], target, operands[1]));
5014 /* If this is a SYMBOL_REF that refers to a constant pool entry,
5015 and we have put it in the TOC, we just need to make a TOC-relative
5018 && GET_CODE (operands[1]) == SYMBOL_REF
5019 && constant_pool_expr_p (operands[1])
5020 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
5021 get_pool_mode (operands[1])))
5023 operands[1] = create_TOC_reference (operands[1]);
5025 else if (mode == Pmode
5026 && CONSTANT_P (operands[1])
5027 && ((GET_CODE (operands[1]) != CONST_INT
5028 && ! easy_fp_constant (operands[1], mode))
5029 || (GET_CODE (operands[1]) == CONST_INT
5030 && num_insns_constant (operands[1], mode) > 2)
5031 || (GET_CODE (operands[0]) == REG
5032 && FP_REGNO_P (REGNO (operands[0]))))
5033 && GET_CODE (operands[1]) != HIGH
5034 && ! legitimate_constant_pool_address_p (operands[1])
5035 && ! toc_relative_expr_p (operands[1]))
5037 /* Emit a USE operation so that the constant isn't deleted if
5038 expensive optimizations are turned on because nobody
5039 references it. This should only be done for operands that
5040 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5041 This should not be done for operands that contain LABEL_REFs.
5042 For now, we just handle the obvious case. */
5043 if (GET_CODE (operands[1]) != LABEL_REF)
5044 emit_use (operands[1]);
5047 /* Darwin uses a special PIC legitimizer. */
5048 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
5051 rs6000_machopic_legitimize_pic_address (operands[1], mode,
5053 if (operands[0] != operands[1])
5054 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5059 /* If we are to limit the number of things we put in the TOC and
5060 this is a symbol plus a constant we can add in one insn,
5061 just put the symbol in the TOC and add the constant. Don't do
5062 this if reload is in progress. */
5063 if (GET_CODE (operands[1]) == CONST
5064 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5065 && GET_CODE (XEXP (operands[1], 0)) == PLUS
5066 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
5067 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
5068 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
5069 && ! side_effects_p (operands[0]))
5072 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
5073 rtx other = XEXP (XEXP (operands[1], 0), 1);
5075 sym = force_reg (mode, sym);
5077 emit_insn (gen_addsi3 (operands[0], sym, other));
5079 emit_insn (gen_adddi3 (operands[0], sym, other));
5083 operands[1] = force_const_mem (mode, operands[1]);
5086 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
5087 && constant_pool_expr_p (XEXP (operands[1], 0))
5088 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
5089 get_pool_constant (XEXP (operands[1], 0)),
5090 get_pool_mode (XEXP (operands[1], 0))))
5093 = gen_const_mem (mode,
5094 create_TOC_reference (XEXP (operands[1], 0)));
5095 set_mem_alias_set (operands[1], get_TOC_alias_set ());
5101 rs6000_eliminate_indexed_memrefs (operands);
5105 emit_insn (gen_rtx_PARALLEL (VOIDmode,
5107 gen_rtx_SET (VOIDmode,
5108 operands[0], operands[1]),
5109 gen_rtx_CLOBBER (VOIDmode,
5110 gen_rtx_SCRATCH (SImode)))));
5119 /* Above, we may have called force_const_mem which may have returned
5120 an invalid address. If we can, fix this up; otherwise, reload will
5121 have to deal with it. */
5122 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
5123 operands[1] = validize_mem (operands[1]);
5126 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5129 /* Nonzero if we can use a floating-point register to pass this arg. */
5130 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5131 (SCALAR_FLOAT_MODE_P (MODE) \
5132 && (CUM)->fregno <= FP_ARG_MAX_REG \
5133 && TARGET_HARD_FLOAT && TARGET_FPRS)
5135 /* Nonzero if we can use an AltiVec register to pass this arg. */
5136 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5137 (ALTIVEC_VECTOR_MODE (MODE) \
5138 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5139 && TARGET_ALTIVEC_ABI \
5142 /* Return a nonzero value to say to return the function value in
5143 memory, just as large structures are always returned. TYPE will be
5144 the data type of the value, and FNTYPE will be the type of the
5145 function doing the returning, or @code{NULL} for libcalls.
5147 The AIX ABI for the RS/6000 specifies that all structures are
5148 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5149 specifies that structures <= 8 bytes are returned in r3/r4, but a
5150 draft put them in memory, and GCC used to implement the draft
5151 instead of the final standard. Therefore, aix_struct_return
5152 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5153 compatibility can change DRAFT_V4_STRUCT_RET to override the
5154 default, and -m switches get the final word. See
5155 rs6000_override_options for more details.
5157 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5158 long double support is enabled. These values are returned in memory.
5160 int_size_in_bytes returns -1 for variable size objects, which go in
5161 memory always. The cast to unsigned makes -1 > 8. */
5164 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5166 /* In the darwin64 abi, try to use registers for larger structs
5168 if (rs6000_darwin64_abi
5169 && TREE_CODE (type) == RECORD_TYPE
5170 && int_size_in_bytes (type) > 0)
5172 CUMULATIVE_ARGS valcum;
5176 valcum.fregno = FP_ARG_MIN_REG;
5177 valcum.vregno = ALTIVEC_ARG_MIN_REG;
5178 /* Do a trial code generation as if this were going to be passed
5179 as an argument; if any part goes in memory, we return NULL. */
5180 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
5183 /* Otherwise fall through to more conventional ABI rules. */
5186 if (AGGREGATE_TYPE_P (type)
5187 && (aix_struct_return
5188 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
5191 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5192 modes only exist for GCC vector types if -maltivec. */
5193 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
5194 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5197 /* Return synthetic vectors in memory. */
5198 if (TREE_CODE (type) == VECTOR_TYPE
5199 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5201 static bool warned_for_return_big_vectors = false;
5202 if (!warned_for_return_big_vectors)
5204 warning (0, "GCC vector returned by reference: "
5205 "non-standard ABI extension with no compatibility guarantee");
5206 warned_for_return_big_vectors = true;
5211 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
5217 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5218 for a call to a function whose data type is FNTYPE.
5219 For a library call, FNTYPE is 0.
5221 For incoming args we set the number of arguments in the prototype large
5222 so we never return a PARALLEL. */
5225 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
5226 rtx libname ATTRIBUTE_UNUSED, int incoming,
5227 int libcall, int n_named_args)
5229 static CUMULATIVE_ARGS zero_cumulative;
5231 *cum = zero_cumulative;
5233 cum->fregno = FP_ARG_MIN_REG;
5234 cum->vregno = ALTIVEC_ARG_MIN_REG;
5235 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
5236 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
5237 ? CALL_LIBCALL : CALL_NORMAL);
5238 cum->sysv_gregno = GP_ARG_MIN_REG;
5239 cum->stdarg = fntype
5240 && (TYPE_ARG_TYPES (fntype) != 0
5241 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5242 != void_type_node));
5244 cum->nargs_prototype = 0;
5245 if (incoming || cum->prototype)
5246 cum->nargs_prototype = n_named_args;
5248 /* Check for a longcall attribute. */
5249 if ((!fntype && rs6000_default_long_calls)
5251 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
5252 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
5253 cum->call_cookie |= CALL_LONG;
5255 if (TARGET_DEBUG_ARG)
5257 fprintf (stderr, "\ninit_cumulative_args:");
5260 tree ret_type = TREE_TYPE (fntype);
5261 fprintf (stderr, " ret code = %s,",
5262 tree_code_name[ (int)TREE_CODE (ret_type) ]);
5265 if (cum->call_cookie & CALL_LONG)
5266 fprintf (stderr, " longcall,");
5268 fprintf (stderr, " proto = %d, nargs = %d\n",
5269 cum->prototype, cum->nargs_prototype);
5274 && TARGET_ALTIVEC_ABI
5275 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
5277 error ("cannot return value in vector register because"
5278 " altivec instructions are disabled, use -maltivec"
5283 /* Return true if TYPE must be passed on the stack and not in registers. */
5286 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
5288 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
5289 return must_pass_in_stack_var_size (mode, type);
5291 return must_pass_in_stack_var_size_or_pad (mode, type);
5294 /* If defined, a C expression which determines whether, and in which
5295 direction, to pad out an argument with extra space. The value
5296 should be of type `enum direction': either `upward' to pad above
5297 the argument, `downward' to pad below, or `none' to inhibit
5300 For the AIX ABI structs are always stored left shifted in their
5304 function_arg_padding (enum machine_mode mode, const_tree type)
5306 #ifndef AGGREGATE_PADDING_FIXED
5307 #define AGGREGATE_PADDING_FIXED 0
5309 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5310 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5313 if (!AGGREGATE_PADDING_FIXED)
5315 /* GCC used to pass structures of the same size as integer types as
5316 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5317 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5318 passed padded downward, except that -mstrict-align further
5319 muddied the water in that multi-component structures of 2 and 4
5320 bytes in size were passed padded upward.
5322 The following arranges for best compatibility with previous
5323 versions of gcc, but removes the -mstrict-align dependency. */
5324 if (BYTES_BIG_ENDIAN)
5326 HOST_WIDE_INT size = 0;
5328 if (mode == BLKmode)
5330 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5331 size = int_size_in_bytes (type);
5334 size = GET_MODE_SIZE (mode);
5336 if (size == 1 || size == 2 || size == 4)
5342 if (AGGREGATES_PAD_UPWARD_ALWAYS)
5344 if (type != 0 && AGGREGATE_TYPE_P (type))
5348 /* Fall back to the default. */
5349 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5352 /* If defined, a C expression that gives the alignment boundary, in bits,
5353 of an argument with the specified mode and type. If it is not defined,
5354 PARM_BOUNDARY is used for all arguments.
5356 V.4 wants long longs and doubles to be double word aligned. Just
5357 testing the mode size is a boneheaded way to do this as it means
5358 that other types such as complex int are also double word aligned.
5359 However, we're stuck with this because changing the ABI might break
5360 existing library interfaces.
5362 Doubleword align SPE vectors.
5363 Quadword align Altivec vectors.
5364 Quadword align large synthetic vector types. */
5367 function_arg_boundary (enum machine_mode mode, tree type)
5369 if (DEFAULT_ABI == ABI_V4
5370 && (GET_MODE_SIZE (mode) == 8
5371 || (TARGET_HARD_FLOAT
5373 && (mode == TFmode || mode == TDmode))))
5375 else if (SPE_VECTOR_MODE (mode)
5376 || (type && TREE_CODE (type) == VECTOR_TYPE
5377 && int_size_in_bytes (type) >= 8
5378 && int_size_in_bytes (type) < 16))
5380 else if (ALTIVEC_VECTOR_MODE (mode)
5381 || (type && TREE_CODE (type) == VECTOR_TYPE
5382 && int_size_in_bytes (type) >= 16))
5384 else if (rs6000_darwin64_abi && mode == BLKmode
5385 && type && TYPE_ALIGN (type) > 64)
5388 return PARM_BOUNDARY;
5391 /* For a function parm of MODE and TYPE, return the starting word in
5392 the parameter area. NWORDS of the parameter area are already used. */
5395 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
5398 unsigned int parm_offset;
5400 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5401 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5402 return nwords + (-(parm_offset + nwords) & align);
5405 /* Compute the size (in words) of a function argument. */
5407 static unsigned long
5408 rs6000_arg_size (enum machine_mode mode, tree type)
5412 if (mode != BLKmode)
5413 size = GET_MODE_SIZE (mode);
5415 size = int_size_in_bytes (type);
5418 return (size + 3) >> 2;
5420 return (size + 7) >> 3;
5423 /* Use this to flush pending int fields. */
5426 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5427 HOST_WIDE_INT bitpos)
5429 unsigned int startbit, endbit;
5430 int intregs, intoffset;
5431 enum machine_mode mode;
5433 if (cum->intoffset == -1)
5436 intoffset = cum->intoffset;
5437 cum->intoffset = -1;
5439 if (intoffset % BITS_PER_WORD != 0)
5441 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5443 if (mode == BLKmode)
5445 /* We couldn't find an appropriate mode, which happens,
5446 e.g., in packed structs when there are 3 bytes to load.
5447 Back intoffset back to the beginning of the word in this
5449 intoffset = intoffset & -BITS_PER_WORD;
5453 startbit = intoffset & -BITS_PER_WORD;
5454 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5455 intregs = (endbit - startbit) / BITS_PER_WORD;
5456 cum->words += intregs;
5459 /* The darwin64 ABI calls for us to recurse down through structs,
5460 looking for elements passed in registers. Unfortunately, we have
5461 to track int register count here also because of misalignments
5462 in powerpc alignment mode. */
5465 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5467 HOST_WIDE_INT startbitpos)
5471 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5472 if (TREE_CODE (f) == FIELD_DECL)
5474 HOST_WIDE_INT bitpos = startbitpos;
5475 tree ftype = TREE_TYPE (f);
5476 enum machine_mode mode;
5477 if (ftype == error_mark_node)
5479 mode = TYPE_MODE (ftype);
5481 if (DECL_SIZE (f) != 0
5482 && host_integerp (bit_position (f), 1))
5483 bitpos += int_bit_position (f);
5485 /* ??? FIXME: else assume zero offset. */
5487 if (TREE_CODE (ftype) == RECORD_TYPE)
5488 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5489 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5491 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5492 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5493 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5495 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5497 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5501 else if (cum->intoffset == -1)
5502 cum->intoffset = bitpos;
5506 /* Update the data in CUM to advance over an argument
5507 of mode MODE and data type TYPE.
5508 (TYPE is null for libcalls where that information may not be available.)
5510 Note that for args passed by reference, function_arg will be called
5511 with MODE and TYPE set to that of the pointer to the arg, not the arg
5515 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5516 tree type, int named, int depth)
5520 /* Only tick off an argument if we're not recursing. */
5522 cum->nargs_prototype--;
5524 if (TARGET_ALTIVEC_ABI
5525 && (ALTIVEC_VECTOR_MODE (mode)
5526 || (type && TREE_CODE (type) == VECTOR_TYPE
5527 && int_size_in_bytes (type) == 16)))
5531 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5534 if (!TARGET_ALTIVEC)
5535 error ("cannot pass argument in vector register because"
5536 " altivec instructions are disabled, use -maltivec"
5539 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5540 even if it is going to be passed in a vector register.
5541 Darwin does the same for variable-argument functions. */
5542 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5543 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5553 /* Vector parameters must be 16-byte aligned. This places
5554 them at 2 mod 4 in terms of words in 32-bit mode, since
5555 the parameter save area starts at offset 24 from the
5556 stack. In 64-bit mode, they just have to start on an
5557 even word, since the parameter save area is 16-byte
5558 aligned. Space for GPRs is reserved even if the argument
5559 will be passed in memory. */
5561 align = (2 - cum->words) & 3;
5563 align = cum->words & 1;
5564 cum->words += align + rs6000_arg_size (mode, type);
5566 if (TARGET_DEBUG_ARG)
5568 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5570 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5571 cum->nargs_prototype, cum->prototype,
5572 GET_MODE_NAME (mode));
5576 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5578 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5581 else if (rs6000_darwin64_abi
5583 && TREE_CODE (type) == RECORD_TYPE
5584 && (size = int_size_in_bytes (type)) > 0)
5586 /* Variable sized types have size == -1 and are
5587 treated as if consisting entirely of ints.
5588 Pad to 16 byte boundary if needed. */
5589 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5590 && (cum->words % 2) != 0)
5592 /* For varargs, we can just go up by the size of the struct. */
5594 cum->words += (size + 7) / 8;
5597 /* It is tempting to say int register count just goes up by
5598 sizeof(type)/8, but this is wrong in a case such as
5599 { int; double; int; } [powerpc alignment]. We have to
5600 grovel through the fields for these too. */
5602 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5603 rs6000_darwin64_record_arg_advance_flush (cum,
5604 size * BITS_PER_UNIT);
5607 else if (DEFAULT_ABI == ABI_V4)
5609 if (TARGET_HARD_FLOAT && TARGET_FPRS
5610 && (mode == SFmode || mode == DFmode
5611 || mode == SDmode || mode == DDmode || mode == TDmode
5612 || (mode == TFmode && !TARGET_IEEEQUAD)))
5614 /* _Decimal128 must use an even/odd register pair. This assumes
5615 that the register number is odd when fregno is odd. */
5616 if (mode == TDmode && (cum->fregno % 2) == 1)
5619 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5620 <= FP_ARG_V4_MAX_REG)
5621 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5624 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5625 if (mode == DFmode || mode == TFmode
5626 || mode == DDmode || mode == TDmode)
5627 cum->words += cum->words & 1;
5628 cum->words += rs6000_arg_size (mode, type);
5633 int n_words = rs6000_arg_size (mode, type);
5634 int gregno = cum->sysv_gregno;
5636 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5637 (r7,r8) or (r9,r10). As does any other 2 word item such
5638 as complex int due to a historical mistake. */
5640 gregno += (1 - gregno) & 1;
5642 /* Multi-reg args are not split between registers and stack. */
5643 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5645 /* Long long and SPE vectors are aligned on the stack.
5646 So are other 2 word items such as complex int due to
5647 a historical mistake. */
5649 cum->words += cum->words & 1;
5650 cum->words += n_words;
5653 /* Note: continuing to accumulate gregno past when we've started
5654 spilling to the stack indicates the fact that we've started
5655 spilling to the stack to expand_builtin_saveregs. */
5656 cum->sysv_gregno = gregno + n_words;
5659 if (TARGET_DEBUG_ARG)
5661 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5662 cum->words, cum->fregno);
5663 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5664 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5665 fprintf (stderr, "mode = %4s, named = %d\n",
5666 GET_MODE_NAME (mode), named);
5671 int n_words = rs6000_arg_size (mode, type);
5672 int start_words = cum->words;
5673 int align_words = rs6000_parm_start (mode, type, start_words);
5675 cum->words = align_words + n_words;
5677 if (SCALAR_FLOAT_MODE_P (mode)
5678 && TARGET_HARD_FLOAT && TARGET_FPRS)
5680 /* _Decimal128 must be passed in an even/odd float register pair.
5681 This assumes that the register number is odd when fregno is
5683 if (mode == TDmode && (cum->fregno % 2) == 1)
5685 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5688 if (TARGET_DEBUG_ARG)
5690 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5691 cum->words, cum->fregno);
5692 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5693 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5694 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5695 named, align_words - start_words, depth);
5701 spe_build_register_parallel (enum machine_mode mode, int gregno)
5708 r1 = gen_rtx_REG (DImode, gregno);
5709 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5710 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5714 r1 = gen_rtx_REG (DImode, gregno);
5715 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5716 r3 = gen_rtx_REG (DImode, gregno + 2);
5717 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5718 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5721 r1 = gen_rtx_REG (DImode, gregno);
5722 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5723 r3 = gen_rtx_REG (DImode, gregno + 2);
5724 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5725 r5 = gen_rtx_REG (DImode, gregno + 4);
5726 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5727 r7 = gen_rtx_REG (DImode, gregno + 6);
5728 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5729 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5736 /* Determine where to put a SIMD argument on the SPE. */
5738 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5741 int gregno = cum->sysv_gregno;
5743 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5744 are passed and returned in a pair of GPRs for ABI compatibility. */
5745 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5746 || mode == DCmode || mode == TCmode))
5748 int n_words = rs6000_arg_size (mode, type);
5750 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5752 gregno += (1 - gregno) & 1;
5754 /* Multi-reg args are not split between registers and stack. */
5755 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5758 return spe_build_register_parallel (mode, gregno);
5762 int n_words = rs6000_arg_size (mode, type);
5764 /* SPE vectors are put in odd registers. */
5765 if (n_words == 2 && (gregno & 1) == 0)
5768 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5771 enum machine_mode m = SImode;
5773 r1 = gen_rtx_REG (m, gregno);
5774 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5775 r2 = gen_rtx_REG (m, gregno + 1);
5776 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5777 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5784 if (gregno <= GP_ARG_MAX_REG)
5785 return gen_rtx_REG (mode, gregno);
5791 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5792 structure between cum->intoffset and bitpos to integer registers. */
5795 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5796 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5798 enum machine_mode mode;
5800 unsigned int startbit, endbit;
5801 int this_regno, intregs, intoffset;
5804 if (cum->intoffset == -1)
5807 intoffset = cum->intoffset;
5808 cum->intoffset = -1;
5810 /* If this is the trailing part of a word, try to only load that
5811 much into the register. Otherwise load the whole register. Note
5812 that in the latter case we may pick up unwanted bits. It's not a
5813 problem at the moment but may wish to revisit. */
5815 if (intoffset % BITS_PER_WORD != 0)
5817 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5819 if (mode == BLKmode)
5821 /* We couldn't find an appropriate mode, which happens,
5822 e.g., in packed structs when there are 3 bytes to load.
5823 Back intoffset back to the beginning of the word in this
5825 intoffset = intoffset & -BITS_PER_WORD;
5832 startbit = intoffset & -BITS_PER_WORD;
5833 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5834 intregs = (endbit - startbit) / BITS_PER_WORD;
5835 this_regno = cum->words + intoffset / BITS_PER_WORD;
5837 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5840 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5844 intoffset /= BITS_PER_UNIT;
5847 regno = GP_ARG_MIN_REG + this_regno;
5848 reg = gen_rtx_REG (mode, regno);
5850 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5853 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5857 while (intregs > 0);
5860 /* Recursive workhorse for the following. */
5863 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
5864 HOST_WIDE_INT startbitpos, rtx rvec[],
5869 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5870 if (TREE_CODE (f) == FIELD_DECL)
5872 HOST_WIDE_INT bitpos = startbitpos;
5873 tree ftype = TREE_TYPE (f);
5874 enum machine_mode mode;
5875 if (ftype == error_mark_node)
5877 mode = TYPE_MODE (ftype);
5879 if (DECL_SIZE (f) != 0
5880 && host_integerp (bit_position (f), 1))
5881 bitpos += int_bit_position (f);
5883 /* ??? FIXME: else assume zero offset. */
5885 if (TREE_CODE (ftype) == RECORD_TYPE)
5886 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5887 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5892 case SCmode: mode = SFmode; break;
5893 case DCmode: mode = DFmode; break;
5894 case TCmode: mode = TFmode; break;
5898 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5900 = gen_rtx_EXPR_LIST (VOIDmode,
5901 gen_rtx_REG (mode, cum->fregno++),
5902 GEN_INT (bitpos / BITS_PER_UNIT));
5903 if (mode == TFmode || mode == TDmode)
5906 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5908 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5910 = gen_rtx_EXPR_LIST (VOIDmode,
5911 gen_rtx_REG (mode, cum->vregno++),
5912 GEN_INT (bitpos / BITS_PER_UNIT));
5914 else if (cum->intoffset == -1)
5915 cum->intoffset = bitpos;
5919 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5920 the register(s) to be used for each field and subfield of a struct
5921 being passed by value, along with the offset of where the
5922 register's value may be found in the block. FP fields go in FP
5923 register, vector fields go in vector registers, and everything
5924 else goes in int registers, packed as in memory.
5926 This code is also used for function return values. RETVAL indicates
5927 whether this is the case.
5929 Much of this is taken from the SPARC V9 port, which has a similar
5930 calling convention. */
5933 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
5934 int named, bool retval)
5936 rtx rvec[FIRST_PSEUDO_REGISTER];
5937 int k = 1, kbase = 1;
5938 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5939 /* This is a copy; modifications are not visible to our caller. */
5940 CUMULATIVE_ARGS copy_cum = *orig_cum;
5941 CUMULATIVE_ARGS *cum = ©_cum;
5943 /* Pad to 16 byte boundary if needed. */
5944 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5945 && (cum->words % 2) != 0)
5952 /* Put entries into rvec[] for individual FP and vector fields, and
5953 for the chunks of memory that go in int regs. Note we start at
5954 element 1; 0 is reserved for an indication of using memory, and
5955 may or may not be filled in below. */
5956 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5957 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5959 /* If any part of the struct went on the stack put all of it there.
5960 This hack is because the generic code for
5961 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5962 parts of the struct are not at the beginning. */
5966 return NULL_RTX; /* doesn't go in registers at all */
5968 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5970 if (k > 1 || cum->use_stack)
5971 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5976 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5979 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5983 rtx rvec[GP_ARG_NUM_REG + 1];
5985 if (align_words >= GP_ARG_NUM_REG)
5988 n_units = rs6000_arg_size (mode, type);
5990 /* Optimize the simple case where the arg fits in one gpr, except in
5991 the case of BLKmode due to assign_parms assuming that registers are
5992 BITS_PER_WORD wide. */
5994 || (n_units == 1 && mode != BLKmode))
5995 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5998 if (align_words + n_units > GP_ARG_NUM_REG)
5999 /* Not all of the arg fits in gprs. Say that it goes in memory too,
6000 using a magic NULL_RTX component.
6001 This is not strictly correct. Only some of the arg belongs in
6002 memory, not all of it. However, the normal scheme using
6003 function_arg_partial_nregs can result in unusual subregs, eg.
6004 (subreg:SI (reg:DF) 4), which are not handled well. The code to
6005 store the whole arg to memory is often more efficient than code
6006 to store pieces, and we know that space is available in the right
6007 place for the whole arg. */
6008 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6013 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
6014 rtx off = GEN_INT (i++ * 4);
6015 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6017 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
6019 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6022 /* Determine where to put an argument to a function.
6023 Value is zero to push the argument on the stack,
6024 or a hard register in which to store the argument.
6026 MODE is the argument's machine mode.
6027 TYPE is the data type of the argument (as a tree).
6028 This is null for libcalls where that information may
6030 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6031 the preceding args and about the function being called. It is
6032 not modified in this routine.
6033 NAMED is nonzero if this argument is a named parameter
6034 (otherwise it is an extra parameter matching an ellipsis).
6036 On RS/6000 the first eight words of non-FP are normally in registers
6037 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
6038 Under V.4, the first 8 FP args are in registers.
6040 If this is floating-point and no prototype is specified, we use
6041 both an FP and integer register (or possibly FP reg and stack). Library
6042 functions (when CALL_LIBCALL is set) always have the proper types for args,
6043 so we can pass the FP value just in one register. emit_library_function
6044 doesn't support PARALLEL anyway.
6046 Note that for args passed by reference, function_arg will be called
6047 with MODE and TYPE set to that of the pointer to the arg, not the arg
6051 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6052 tree type, int named)
6054 enum rs6000_abi abi = DEFAULT_ABI;
6056 /* Return a marker to indicate whether CR1 needs to set or clear the
6057 bit that V.4 uses to say fp args were passed in registers.
6058 Assume that we don't need the marker for software floating point,
6059 or compiler generated library calls. */
6060 if (mode == VOIDmode)
6063 && (cum->call_cookie & CALL_LIBCALL) == 0
6065 || (cum->nargs_prototype < 0
6066 && (cum->prototype || TARGET_NO_PROTOTYPE))))
6068 /* For the SPE, we need to crxor CR6 always. */
6070 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
6071 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
6072 return GEN_INT (cum->call_cookie
6073 | ((cum->fregno == FP_ARG_MIN_REG)
6074 ? CALL_V4_SET_FP_ARGS
6075 : CALL_V4_CLEAR_FP_ARGS));
6078 return GEN_INT (cum->call_cookie);
6081 if (rs6000_darwin64_abi && mode == BLKmode
6082 && TREE_CODE (type) == RECORD_TYPE)
6084 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
6085 if (rslt != NULL_RTX)
6087 /* Else fall through to usual handling. */
6090 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
6091 if (TARGET_64BIT && ! cum->prototype)
6093 /* Vector parameters get passed in vector register
6094 and also in GPRs or memory, in absence of prototype. */
6097 align_words = (cum->words + 1) & ~1;
6099 if (align_words >= GP_ARG_NUM_REG)
6105 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6107 return gen_rtx_PARALLEL (mode,
6109 gen_rtx_EXPR_LIST (VOIDmode,
6111 gen_rtx_EXPR_LIST (VOIDmode,
6112 gen_rtx_REG (mode, cum->vregno),
6116 return gen_rtx_REG (mode, cum->vregno);
6117 else if (TARGET_ALTIVEC_ABI
6118 && (ALTIVEC_VECTOR_MODE (mode)
6119 || (type && TREE_CODE (type) == VECTOR_TYPE
6120 && int_size_in_bytes (type) == 16)))
6122 if (named || abi == ABI_V4)
6126 /* Vector parameters to varargs functions under AIX or Darwin
6127 get passed in memory and possibly also in GPRs. */
6128 int align, align_words, n_words;
6129 enum machine_mode part_mode;
6131 /* Vector parameters must be 16-byte aligned. This places them at
6132 2 mod 4 in terms of words in 32-bit mode, since the parameter
6133 save area starts at offset 24 from the stack. In 64-bit mode,
6134 they just have to start on an even word, since the parameter
6135 save area is 16-byte aligned. */
6137 align = (2 - cum->words) & 3;
6139 align = cum->words & 1;
6140 align_words = cum->words + align;
6142 /* Out of registers? Memory, then. */
6143 if (align_words >= GP_ARG_NUM_REG)
6146 if (TARGET_32BIT && TARGET_POWERPC64)
6147 return rs6000_mixed_function_arg (mode, type, align_words);
6149 /* The vector value goes in GPRs. Only the part of the
6150 value in GPRs is reported here. */
6152 n_words = rs6000_arg_size (mode, type);
6153 if (align_words + n_words > GP_ARG_NUM_REG)
6154 /* Fortunately, there are only two possibilities, the value
6155 is either wholly in GPRs or half in GPRs and half not. */
6158 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
6161 else if (TARGET_SPE_ABI && TARGET_SPE
6162 && (SPE_VECTOR_MODE (mode)
6163 || (TARGET_E500_DOUBLE && (mode == DFmode
6166 || mode == TCmode))))
6167 return rs6000_spe_function_arg (cum, mode, type);
6169 else if (abi == ABI_V4)
6171 if (TARGET_HARD_FLOAT && TARGET_FPRS
6172 && (mode == SFmode || mode == DFmode
6173 || (mode == TFmode && !TARGET_IEEEQUAD)
6174 || mode == SDmode || mode == DDmode || mode == TDmode))
6176 /* _Decimal128 must use an even/odd register pair. This assumes
6177 that the register number is odd when fregno is odd. */
6178 if (mode == TDmode && (cum->fregno % 2) == 1)
6181 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
6182 <= FP_ARG_V4_MAX_REG)
6183 return gen_rtx_REG (mode, cum->fregno);
6189 int n_words = rs6000_arg_size (mode, type);
6190 int gregno = cum->sysv_gregno;
6192 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6193 (r7,r8) or (r9,r10). As does any other 2 word item such
6194 as complex int due to a historical mistake. */
6196 gregno += (1 - gregno) & 1;
6198 /* Multi-reg args are not split between registers and stack. */
6199 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
6202 if (TARGET_32BIT && TARGET_POWERPC64)
6203 return rs6000_mixed_function_arg (mode, type,
6204 gregno - GP_ARG_MIN_REG);
6205 return gen_rtx_REG (mode, gregno);
6210 int align_words = rs6000_parm_start (mode, type, cum->words);
6212 /* _Decimal128 must be passed in an even/odd float register pair.
6213 This assumes that the register number is odd when fregno is odd. */
6214 if (mode == TDmode && (cum->fregno % 2) == 1)
6217 if (USE_FP_FOR_ARG_P (cum, mode, type))
6219 rtx rvec[GP_ARG_NUM_REG + 1];
6223 enum machine_mode fmode = mode;
6224 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
6226 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
6228 /* Currently, we only ever need one reg here because complex
6229 doubles are split. */
6230 gcc_assert (cum->fregno == FP_ARG_MAX_REG
6231 && (fmode == TFmode || fmode == TDmode));
6233 /* Long double or _Decimal128 split over regs and memory. */
6234 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
6237 /* Do we also need to pass this arg in the parameter save
6240 && (cum->nargs_prototype <= 0
6241 || (DEFAULT_ABI == ABI_AIX
6243 && align_words >= GP_ARG_NUM_REG)));
6245 if (!needs_psave && mode == fmode)
6246 return gen_rtx_REG (fmode, cum->fregno);
6251 /* Describe the part that goes in gprs or the stack.
6252 This piece must come first, before the fprs. */
6253 if (align_words < GP_ARG_NUM_REG)
6255 unsigned long n_words = rs6000_arg_size (mode, type);
6257 if (align_words + n_words > GP_ARG_NUM_REG
6258 || (TARGET_32BIT && TARGET_POWERPC64))
6260 /* If this is partially on the stack, then we only
6261 include the portion actually in registers here. */
6262 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
6265 if (align_words + n_words > GP_ARG_NUM_REG)
6266 /* Not all of the arg fits in gprs. Say that it
6267 goes in memory too, using a magic NULL_RTX
6268 component. Also see comment in
6269 rs6000_mixed_function_arg for why the normal
6270 function_arg_partial_nregs scheme doesn't work
6272 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
6276 r = gen_rtx_REG (rmode,
6277 GP_ARG_MIN_REG + align_words);
6278 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
6279 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6281 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
6285 /* The whole arg fits in gprs. */
6286 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6287 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6291 /* It's entirely in memory. */
6292 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6295 /* Describe where this piece goes in the fprs. */
6296 r = gen_rtx_REG (fmode, cum->fregno);
6297 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6299 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6301 else if (align_words < GP_ARG_NUM_REG)
6303 if (TARGET_32BIT && TARGET_POWERPC64)
6304 return rs6000_mixed_function_arg (mode, type, align_words);
6306 if (mode == BLKmode)
6309 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6316 /* For an arg passed partly in registers and partly in memory, this is
6317 the number of bytes passed in registers. For args passed entirely in
6318 registers or entirely in memory, zero. When an arg is described by a
6319 PARALLEL, perhaps using more than one register type, this function
6320 returns the number of bytes used by the first element of the PARALLEL. */
6323 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6324 tree type, bool named)
6329 if (DEFAULT_ABI == ABI_V4)
6332 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
6333 && cum->nargs_prototype >= 0)
6336 /* In this complicated case we just disable the partial_nregs code. */
6337 if (rs6000_darwin64_abi && mode == BLKmode
6338 && TREE_CODE (type) == RECORD_TYPE
6339 && int_size_in_bytes (type) > 0)
6342 align_words = rs6000_parm_start (mode, type, cum->words);
6344 if (USE_FP_FOR_ARG_P (cum, mode, type))
6346 /* If we are passing this arg in the fixed parameter save area
6347 (gprs or memory) as well as fprs, then this function should
6348 return the number of partial bytes passed in the parameter
6349 save area rather than partial bytes passed in fprs. */
6351 && (cum->nargs_prototype <= 0
6352 || (DEFAULT_ABI == ABI_AIX
6354 && align_words >= GP_ARG_NUM_REG)))
6356 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
6357 > FP_ARG_MAX_REG + 1)
6358 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
6359 else if (cum->nargs_prototype >= 0)
6363 if (align_words < GP_ARG_NUM_REG
6364 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
6365 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
6367 if (ret != 0 && TARGET_DEBUG_ARG)
6368 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
6373 /* A C expression that indicates when an argument must be passed by
6374 reference. If nonzero for an argument, a copy of that argument is
6375 made in memory and a pointer to the argument is passed instead of
6376 the argument itself. The pointer is passed in whatever way is
6377 appropriate for passing a pointer to that type.
6379 Under V.4, aggregates and long double are passed by reference.
6381 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6382 reference unless the AltiVec vector extension ABI is in force.
6384 As an extension to all ABIs, variable sized types are passed by
6388 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6389 enum machine_mode mode, const_tree type,
6390 bool named ATTRIBUTE_UNUSED)
6392 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
6394 if (TARGET_DEBUG_ARG)
6395 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6402 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6404 if (TARGET_DEBUG_ARG)
6405 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6409 if (int_size_in_bytes (type) < 0)
6411 if (TARGET_DEBUG_ARG)
6412 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6416 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6417 modes only exist for GCC vector types if -maltivec. */
6418 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6420 if (TARGET_DEBUG_ARG)
6421 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6425 /* Pass synthetic vectors in memory. */
6426 if (TREE_CODE (type) == VECTOR_TYPE
6427 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6429 static bool warned_for_pass_big_vectors = false;
6430 if (TARGET_DEBUG_ARG)
6431 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6432 if (!warned_for_pass_big_vectors)
6434 warning (0, "GCC vector passed by reference: "
6435 "non-standard ABI extension with no compatibility guarantee");
6436 warned_for_pass_big_vectors = true;
6445 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6448 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6453 for (i = 0; i < nregs; i++)
6455 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6456 if (reload_completed)
6458 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6461 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6462 i * GET_MODE_SIZE (reg_mode));
6465 tem = replace_equiv_address (tem, XEXP (tem, 0));
6469 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6473 /* Perform any needed actions needed for a function that is receiving a
6474 variable number of arguments.
6478 MODE and TYPE are the mode and type of the current parameter.
6480 PRETEND_SIZE is a variable that should be set to the amount of stack
6481 that must be pushed by the prolog to pretend that our caller pushed
6484 Normally, this macro will push all remaining incoming registers on the
6485 stack and set PRETEND_SIZE to the length of the registers pushed. */
6488 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6489 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6492 CUMULATIVE_ARGS next_cum;
6493 int reg_size = TARGET_32BIT ? 4 : 8;
6494 rtx save_area = NULL_RTX, mem;
6495 int first_reg_offset;
6498 /* Skip the last named argument. */
6500 function_arg_advance (&next_cum, mode, type, 1, 0);
6502 if (DEFAULT_ABI == ABI_V4)
6504 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6508 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6509 HOST_WIDE_INT offset = 0;
6511 /* Try to optimize the size of the varargs save area.
6512 The ABI requires that ap.reg_save_area is doubleword
6513 aligned, but we don't need to allocate space for all
6514 the bytes, only those to which we actually will save
6516 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6517 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6518 if (TARGET_HARD_FLOAT && TARGET_FPRS
6519 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6520 && cfun->va_list_fpr_size)
6523 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6524 * UNITS_PER_FP_WORD;
6525 if (cfun->va_list_fpr_size
6526 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6527 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6529 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6530 * UNITS_PER_FP_WORD;
6534 offset = -((first_reg_offset * reg_size) & ~7);
6535 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6537 gpr_reg_num = cfun->va_list_gpr_size;
6538 if (reg_size == 4 && (first_reg_offset & 1))
6541 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6544 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6546 - (int) (GP_ARG_NUM_REG * reg_size);
6548 if (gpr_size + fpr_size)
6551 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6552 gcc_assert (GET_CODE (reg_save_area) == MEM);
6553 reg_save_area = XEXP (reg_save_area, 0);
6554 if (GET_CODE (reg_save_area) == PLUS)
6556 gcc_assert (XEXP (reg_save_area, 0)
6557 == virtual_stack_vars_rtx);
6558 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6559 offset += INTVAL (XEXP (reg_save_area, 1));
6562 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6565 cfun->machine->varargs_save_offset = offset;
6566 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6571 first_reg_offset = next_cum.words;
6572 save_area = virtual_incoming_args_rtx;
6574 if (targetm.calls.must_pass_in_stack (mode, type))
6575 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6578 set = get_varargs_alias_set ();
6579 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6580 && cfun->va_list_gpr_size)
6582 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6584 if (va_list_gpr_counter_field)
6586 /* V4 va_list_gpr_size counts number of registers needed. */
6587 if (nregs > cfun->va_list_gpr_size)
6588 nregs = cfun->va_list_gpr_size;
6592 /* char * va_list instead counts number of bytes needed. */
6593 if (nregs > cfun->va_list_gpr_size / reg_size)
6594 nregs = cfun->va_list_gpr_size / reg_size;
6597 mem = gen_rtx_MEM (BLKmode,
6598 plus_constant (save_area,
6599 first_reg_offset * reg_size));
6600 MEM_NOTRAP_P (mem) = 1;
6601 set_mem_alias_set (mem, set);
6602 set_mem_align (mem, BITS_PER_WORD);
6604 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6608 /* Save FP registers if needed. */
6609 if (DEFAULT_ABI == ABI_V4
6610 && TARGET_HARD_FLOAT && TARGET_FPRS
6612 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6613 && cfun->va_list_fpr_size)
6615 int fregno = next_cum.fregno, nregs;
6616 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6617 rtx lab = gen_label_rtx ();
6618 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6619 * UNITS_PER_FP_WORD);
6622 (gen_rtx_SET (VOIDmode,
6624 gen_rtx_IF_THEN_ELSE (VOIDmode,
6625 gen_rtx_NE (VOIDmode, cr1,
6627 gen_rtx_LABEL_REF (VOIDmode, lab),
6631 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6632 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6634 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6635 MEM_NOTRAP_P (mem) = 1;
6636 set_mem_alias_set (mem, set);
6637 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6638 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6645 /* Create the va_list data type. */
6648 rs6000_build_builtin_va_list (void)
6650 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6652 /* For AIX, prefer 'char *' because that's what the system
6653 header files like. */
6654 if (DEFAULT_ABI != ABI_V4)
6655 return build_pointer_type (char_type_node);
6657 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6658 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6660 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6661 unsigned_char_type_node);
6662 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6663 unsigned_char_type_node);
6664 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6666 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6667 short_unsigned_type_node);
6668 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6670 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6673 va_list_gpr_counter_field = f_gpr;
6674 va_list_fpr_counter_field = f_fpr;
6676 DECL_FIELD_CONTEXT (f_gpr) = record;
6677 DECL_FIELD_CONTEXT (f_fpr) = record;
6678 DECL_FIELD_CONTEXT (f_res) = record;
6679 DECL_FIELD_CONTEXT (f_ovf) = record;
6680 DECL_FIELD_CONTEXT (f_sav) = record;
6682 TREE_CHAIN (record) = type_decl;
6683 TYPE_NAME (record) = type_decl;
6684 TYPE_FIELDS (record) = f_gpr;
6685 TREE_CHAIN (f_gpr) = f_fpr;
6686 TREE_CHAIN (f_fpr) = f_res;
6687 TREE_CHAIN (f_res) = f_ovf;
6688 TREE_CHAIN (f_ovf) = f_sav;
6690 layout_type (record);
6692 /* The correct type is an array type of one element. */
6693 return build_array_type (record, build_index_type (size_zero_node));
6696 /* Implement va_start. */
6699 rs6000_va_start (tree valist, rtx nextarg)
6701 HOST_WIDE_INT words, n_gpr, n_fpr;
6702 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6703 tree gpr, fpr, ovf, sav, t;
6705 /* Only SVR4 needs something special. */
6706 if (DEFAULT_ABI != ABI_V4)
6708 std_expand_builtin_va_start (valist, nextarg);
6712 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6713 f_fpr = TREE_CHAIN (f_gpr);
6714 f_res = TREE_CHAIN (f_fpr);
6715 f_ovf = TREE_CHAIN (f_res);
6716 f_sav = TREE_CHAIN (f_ovf);
6718 valist = build_va_arg_indirect_ref (valist);
6719 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6720 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
6722 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
6724 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
6727 /* Count number of gp and fp argument registers used. */
6728 words = crtl->args.info.words;
6729 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
6731 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
6734 if (TARGET_DEBUG_ARG)
6735 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6736 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6737 words, n_gpr, n_fpr);
6739 if (cfun->va_list_gpr_size)
6741 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
6742 build_int_cst (NULL_TREE, n_gpr));
6743 TREE_SIDE_EFFECTS (t) = 1;
6744 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6747 if (cfun->va_list_fpr_size)
6749 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
6750 build_int_cst (NULL_TREE, n_fpr));
6751 TREE_SIDE_EFFECTS (t) = 1;
6752 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6755 /* Find the overflow area. */
6756 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6758 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6759 size_int (words * UNITS_PER_WORD));
6760 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6761 TREE_SIDE_EFFECTS (t) = 1;
6762 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6764 /* If there were no va_arg invocations, don't set up the register
6766 if (!cfun->va_list_gpr_size
6767 && !cfun->va_list_fpr_size
6768 && n_gpr < GP_ARG_NUM_REG
6769 && n_fpr < FP_ARG_V4_MAX_REG)
6772 /* Find the register save area. */
6773 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6774 if (cfun->machine->varargs_save_offset)
6775 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6776 size_int (cfun->machine->varargs_save_offset));
6777 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
6778 TREE_SIDE_EFFECTS (t) = 1;
6779 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6782 /* Implement va_arg. */
6785 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6788 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6789 tree gpr, fpr, ovf, sav, reg, t, u;
6790 int size, rsize, n_reg, sav_ofs, sav_scale;
6791 tree lab_false, lab_over, addr;
6793 tree ptrtype = build_pointer_type (type);
6797 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6799 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6800 return build_va_arg_indirect_ref (t);
6803 if (DEFAULT_ABI != ABI_V4)
6805 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6807 tree elem_type = TREE_TYPE (type);
6808 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6809 int elem_size = GET_MODE_SIZE (elem_mode);
6811 if (elem_size < UNITS_PER_WORD)
6813 tree real_part, imag_part;
6814 gimple_seq post = NULL;
6816 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6818 /* Copy the value into a temporary, lest the formal temporary
6819 be reused out from under us. */
6820 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6821 gimple_seq_add_seq (pre_p, post);
6823 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6826 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6830 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6833 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6834 f_fpr = TREE_CHAIN (f_gpr);
6835 f_res = TREE_CHAIN (f_fpr);
6836 f_ovf = TREE_CHAIN (f_res);
6837 f_sav = TREE_CHAIN (f_ovf);
6839 valist = build_va_arg_indirect_ref (valist);
6840 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6841 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
6843 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
6845 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
6848 size = int_size_in_bytes (type);
6849 rsize = (size + 3) / 4;
6852 if (TARGET_HARD_FLOAT && TARGET_FPRS
6853 && (TYPE_MODE (type) == SFmode
6854 || TYPE_MODE (type) == DFmode
6855 || TYPE_MODE (type) == TFmode
6856 || TYPE_MODE (type) == SDmode
6857 || TYPE_MODE (type) == DDmode
6858 || TYPE_MODE (type) == TDmode))
6860 /* FP args go in FP registers, if present. */
6862 n_reg = (size + 7) / 8;
6865 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
6870 /* Otherwise into GP registers. */
6879 /* Pull the value out of the saved registers.... */
6882 addr = create_tmp_var (ptr_type_node, "addr");
6883 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6885 /* AltiVec vectors never go in registers when -mabi=altivec. */
6886 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6890 lab_false = create_artificial_label ();
6891 lab_over = create_artificial_label ();
6893 /* Long long and SPE vectors are aligned in the registers.
6894 As are any other 2 gpr item such as complex int due to a
6895 historical mistake. */
6897 if (n_reg == 2 && reg == gpr)
6900 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
6901 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6902 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
6903 unshare_expr (reg), u);
6905 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6906 reg number is 0 for f1, so we want to make it odd. */
6907 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6910 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
6911 build_int_cst (TREE_TYPE (reg), 1));
6912 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
6915 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6916 t = build2 (GE_EXPR, boolean_type_node, u, t);
6917 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6918 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6919 gimplify_and_add (t, pre_p);
6923 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6925 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
6926 build_int_cst (TREE_TYPE (reg), n_reg));
6927 u = fold_convert (sizetype, u);
6928 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6929 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6931 /* _Decimal32 varargs are located in the second word of the 64-bit
6932 FP register for 32-bit binaries. */
6933 if (!TARGET_POWERPC64
6934 && TARGET_HARD_FLOAT && TARGET_FPRS
6935 && TYPE_MODE (type) == SDmode)
6936 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6938 gimplify_assign (addr, t, pre_p);
6940 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6942 stmt = gimple_build_label (lab_false);
6943 gimple_seq_add_stmt (pre_p, stmt);
6945 if ((n_reg == 2 && !regalign) || n_reg > 2)
6947 /* Ensure that we don't find any more args in regs.
6948 Alignment has taken care of for special cases. */
6949 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
6953 /* ... otherwise out of the overflow area. */
6955 /* Care for on-stack alignment if needed. */
6959 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6960 t = fold_convert (sizetype, t);
6961 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6963 t = fold_convert (TREE_TYPE (ovf), t);
6965 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6967 gimplify_assign (unshare_expr (addr), t, pre_p);
6969 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6970 gimplify_assign (unshare_expr (ovf), t, pre_p);
6974 stmt = gimple_build_label (lab_over);
6975 gimple_seq_add_stmt (pre_p, stmt);
6978 if (STRICT_ALIGNMENT
6979 && (TYPE_ALIGN (type)
6980 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6982 /* The value (of type complex double, for example) may not be
6983 aligned in memory in the saved registers, so copy via a
6984 temporary. (This is the same code as used for SPARC.) */
6985 tree tmp = create_tmp_var (type, "va_arg_tmp");
6986 tree dest_addr = build_fold_addr_expr (tmp);
6988 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6989 3, dest_addr, addr, size_int (rsize * 4));
6991 gimplify_and_add (copy, pre_p);
6995 addr = fold_convert (ptrtype, addr);
6996 return build_va_arg_indirect_ref (addr);
7002 def_builtin (int mask, const char *name, tree type, int code)
7004 if ((mask & target_flags) || TARGET_PAIRED_FLOAT)
7006 if (rs6000_builtin_decls[code])
7009 rs6000_builtin_decls[code] =
7010 add_builtin_function (name, type, code, BUILT_IN_MD,
7015 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
7017 static const struct builtin_description bdesc_3arg[] =
7019 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
7020 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
7021 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
7022 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
7023 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
7024 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
7025 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
7026 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
7027 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
7028 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
7029 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
7030 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
7031 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
7032 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
7033 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
7034 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
7035 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
7036 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
7037 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
7038 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
7039 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
7040 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
7041 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
7043 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
7044 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
7045 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
7046 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
7047 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
7048 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
7049 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
7050 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
7051 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
7052 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
7053 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
7054 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
7055 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
7056 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
7057 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
7059 { 0, CODE_FOR_paired_msub, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB },
7060 { 0, CODE_FOR_paired_madd, "__builtin_paired_madd", PAIRED_BUILTIN_MADD },
7061 { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 },
7062 { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 },
7063 { 0, CODE_FOR_paired_nmsub, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB },
7064 { 0, CODE_FOR_paired_nmadd, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD },
7065 { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 },
7066 { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 },
7067 { 0, CODE_FOR_selv2sf4, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4 },
7070 /* DST operations: void foo (void *, const int, const char). */
7072 static const struct builtin_description bdesc_dst[] =
7074 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
7075 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
7076 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
7077 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
7079 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
7080 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
7081 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
7082 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
7085 /* Simple binary operations: VECc = foo (VECa, VECb). */
7087 static struct builtin_description bdesc_2arg[] =
7089 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
7090 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
7091 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
7092 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
7093 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
7094 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
7095 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
7096 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
7097 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
7098 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
7099 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
7100 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
7101 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
7102 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
7103 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
7104 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
7105 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
7106 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
7107 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
7108 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
7109 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
7110 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
7111 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
7112 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
7113 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
7114 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
7115 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
7116 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
7117 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
7118 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
7119 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
7120 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
7121 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
7122 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
7123 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
7124 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
7125 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
7126 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
7127 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
7128 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
7129 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
7130 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
7131 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
7132 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
7133 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
7134 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
7135 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
7136 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
7137 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
7138 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
7139 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
7140 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
7141 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
7142 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
7143 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
7144 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
7145 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
7146 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
7147 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
7148 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
7149 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
7150 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
7151 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
7152 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
7153 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
7154 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
7155 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
7156 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
7157 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
7158 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
7159 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
7160 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
7161 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
7162 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
7163 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
7164 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
7165 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
7166 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
7167 { MASK_ALTIVEC, CODE_FOR_vashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
7168 { MASK_ALTIVEC, CODE_FOR_vashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
7169 { MASK_ALTIVEC, CODE_FOR_vashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
7170 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
7171 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
7172 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
7173 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
7174 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
7175 { MASK_ALTIVEC, CODE_FOR_vlshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
7176 { MASK_ALTIVEC, CODE_FOR_vlshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
7177 { MASK_ALTIVEC, CODE_FOR_vlshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
7178 { MASK_ALTIVEC, CODE_FOR_vashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
7179 { MASK_ALTIVEC, CODE_FOR_vashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
7180 { MASK_ALTIVEC, CODE_FOR_vashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
7181 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
7182 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
7183 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
7184 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
7185 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
7186 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
7187 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
7188 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
7189 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
7190 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
7191 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
7192 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
7193 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
7194 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
7195 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
7196 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
7197 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
7198 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
7199 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
7201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
7202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
7203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
7204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
7205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
7206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
7207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
7208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
7209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
7210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
7211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
7212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
7213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
7214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
7215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
7216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
7217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
7218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
7219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
7220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
7221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
7222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
7223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
7224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
7225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
7226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
7227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
7228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
7229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
7230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
7231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
7232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
7233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
7234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
7235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
7236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
7237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
7238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
7239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
7240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
7241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
7242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
7243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
7244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
7245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
7246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
7247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
7248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
7249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
7250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
7251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
7252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
7253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
7254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
7255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
7256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
7257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
7258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
7259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
7260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
7261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
7262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
7263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
7264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
7265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
7266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
7267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
7268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
7269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
7270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
7271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
7272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
7273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
7274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
7275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
7276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
7277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
7278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
7279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
7280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
7281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
7282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
7283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
7284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
7285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
7286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
7287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
7288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
7289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
7290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
7291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
7292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
7293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
7294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
7295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
7296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
7297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
7298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
7299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
7300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
7301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
7302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
7303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
7304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
7305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
7306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
7307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
7308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
7309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
7310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
7311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
7312 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
7313 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
7314 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
7315 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
7316 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
7317 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
7318 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
7319 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
7320 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
7321 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
7322 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
7323 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
7324 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
7325 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
7326 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
7327 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
7329 { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
7330 { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
7331 { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
7332 { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
7333 { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
7334 { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
7335 { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
7336 { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 },
7337 { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 },
7338 { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
7340 /* Place holder, leave as first spe builtin. */
7341 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
7342 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
7343 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
7344 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
7345 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
7346 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
7347 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
7348 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
7349 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
7350 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
7351 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
7352 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
7353 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
7354 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
7355 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
7356 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
7357 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
7358 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
7359 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
7360 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
7361 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
7362 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
7363 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
7364 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
7365 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
7366 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
7367 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
7368 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
7369 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
7370 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
7371 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
7372 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
7373 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
7374 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
7375 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
7376 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
7377 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
7378 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
7379 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
7380 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
7381 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
7382 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
7383 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
7384 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
7385 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
7386 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
7387 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
7388 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
7389 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
7390 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
7391 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
7392 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
7393 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
7394 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
7395 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
7396 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
7397 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
7398 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
7399 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
7400 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
7401 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
7402 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
7403 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
7404 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
7405 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
7406 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
7407 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
7408 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
7409 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
7410 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
7411 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
7412 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
7413 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
7414 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
7415 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
7416 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
7417 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
7418 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
7419 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
7420 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
7421 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
7422 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
7423 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
7424 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
7425 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
7426 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
7427 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
7428 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
7429 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
7430 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
7431 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
7432 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
7433 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7434 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7435 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7436 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7437 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7438 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7439 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7440 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7441 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7442 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7443 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7444 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7445 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7446 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7447 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7448 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7449 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7451 /* SPE binary operations expecting a 5-bit unsigned literal. */
7452 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7454 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7455 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7456 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7457 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7458 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7459 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7460 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7461 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7462 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7463 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7464 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7465 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7466 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7467 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7468 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7469 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7470 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7471 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7472 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7473 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7474 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7475 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7476 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7477 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7478 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7479 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7481 /* Place-holder. Leave as last binary SPE builtin. */
7482 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7485 /* AltiVec predicates. */
7487 struct builtin_description_predicates
7489 const unsigned int mask;
7490 const enum insn_code icode;
7492 const char *const name;
7493 const enum rs6000_builtins code;
7496 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7498 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7499 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7500 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7501 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7502 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7503 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7504 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7505 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7506 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7507 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7508 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7509 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7510 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7512 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7513 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7514 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7517 /* SPE predicates. */
7518 static struct builtin_description bdesc_spe_predicates[] =
7520 /* Place-holder. Leave as first. */
7521 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7522 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7523 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7524 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7525 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7526 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7527 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7528 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7529 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7530 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7531 /* Place-holder. Leave as last. */
7532 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7535 /* SPE evsel predicates. */
7536 static struct builtin_description bdesc_spe_evsel[] =
7538 /* Place-holder. Leave as first. */
7539 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7540 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7541 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7542 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7543 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7544 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7545 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7546 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7547 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7548 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7549 /* Place-holder. Leave as last. */
7550 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7553 /* PAIRED predicates. */
7554 static const struct builtin_description bdesc_paired_preds[] =
7556 /* Place-holder. Leave as first. */
7557 { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 },
7558 /* Place-holder. Leave as last. */
7559 { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 },
7562 /* ABS* operations. */
7564 static const struct builtin_description bdesc_abs[] =
7566 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7567 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7568 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7569 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7570 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7571 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7572 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7575 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7578 static struct builtin_description bdesc_1arg[] =
7580 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7581 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7582 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7583 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7584 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7585 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7586 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7587 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7588 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7589 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7590 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7591 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7592 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7593 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7594 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7595 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7596 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7598 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7599 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7600 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7601 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7602 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7603 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7604 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7605 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7606 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7607 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7608 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7609 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7610 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7611 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7612 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7613 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7614 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7615 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7616 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7618 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7619 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7620 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7621 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7622 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7623 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7624 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7625 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7626 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7627 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7628 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7629 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7630 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7631 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7632 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7633 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7634 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7635 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7636 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7637 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7638 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7639 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7640 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7641 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7642 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7643 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7644 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7645 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7646 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7647 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7649 /* Place-holder. Leave as last unary SPE builtin. */
7650 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
7652 { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
7653 { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
7654 { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
7655 { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
7656 { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
7660 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7663 tree arg0 = CALL_EXPR_ARG (exp, 0);
7664 rtx op0 = expand_normal (arg0);
7665 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7666 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7668 if (icode == CODE_FOR_nothing)
7669 /* Builtin not supported on this processor. */
7672 /* If we got invalid arguments bail out before generating bad rtl. */
7673 if (arg0 == error_mark_node)
7676 if (icode == CODE_FOR_altivec_vspltisb
7677 || icode == CODE_FOR_altivec_vspltish
7678 || icode == CODE_FOR_altivec_vspltisw
7679 || icode == CODE_FOR_spe_evsplatfi
7680 || icode == CODE_FOR_spe_evsplati)
7682 /* Only allow 5-bit *signed* literals. */
7683 if (GET_CODE (op0) != CONST_INT
7684 || INTVAL (op0) > 15
7685 || INTVAL (op0) < -16)
7687 error ("argument 1 must be a 5-bit signed literal");
7693 || GET_MODE (target) != tmode
7694 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7695 target = gen_reg_rtx (tmode);
7697 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7698 op0 = copy_to_mode_reg (mode0, op0);
7700 pat = GEN_FCN (icode) (target, op0);
7709 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7711 rtx pat, scratch1, scratch2;
7712 tree arg0 = CALL_EXPR_ARG (exp, 0);
7713 rtx op0 = expand_normal (arg0);
7714 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7715 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7717 /* If we have invalid arguments, bail out before generating bad rtl. */
7718 if (arg0 == error_mark_node)
7722 || GET_MODE (target) != tmode
7723 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7724 target = gen_reg_rtx (tmode);
7726 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7727 op0 = copy_to_mode_reg (mode0, op0);
7729 scratch1 = gen_reg_rtx (mode0);
7730 scratch2 = gen_reg_rtx (mode0);
7732 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7741 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7744 tree arg0 = CALL_EXPR_ARG (exp, 0);
7745 tree arg1 = CALL_EXPR_ARG (exp, 1);
7746 rtx op0 = expand_normal (arg0);
7747 rtx op1 = expand_normal (arg1);
7748 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7749 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7750 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7752 if (icode == CODE_FOR_nothing)
7753 /* Builtin not supported on this processor. */
7756 /* If we got invalid arguments bail out before generating bad rtl. */
7757 if (arg0 == error_mark_node || arg1 == error_mark_node)
7760 if (icode == CODE_FOR_altivec_vcfux
7761 || icode == CODE_FOR_altivec_vcfsx
7762 || icode == CODE_FOR_altivec_vctsxs
7763 || icode == CODE_FOR_altivec_vctuxs
7764 || icode == CODE_FOR_altivec_vspltb
7765 || icode == CODE_FOR_altivec_vsplth
7766 || icode == CODE_FOR_altivec_vspltw
7767 || icode == CODE_FOR_spe_evaddiw
7768 || icode == CODE_FOR_spe_evldd
7769 || icode == CODE_FOR_spe_evldh
7770 || icode == CODE_FOR_spe_evldw
7771 || icode == CODE_FOR_spe_evlhhesplat
7772 || icode == CODE_FOR_spe_evlhhossplat
7773 || icode == CODE_FOR_spe_evlhhousplat
7774 || icode == CODE_FOR_spe_evlwhe
7775 || icode == CODE_FOR_spe_evlwhos
7776 || icode == CODE_FOR_spe_evlwhou
7777 || icode == CODE_FOR_spe_evlwhsplat
7778 || icode == CODE_FOR_spe_evlwwsplat
7779 || icode == CODE_FOR_spe_evrlwi
7780 || icode == CODE_FOR_spe_evslwi
7781 || icode == CODE_FOR_spe_evsrwis
7782 || icode == CODE_FOR_spe_evsubifw
7783 || icode == CODE_FOR_spe_evsrwiu)
7785 /* Only allow 5-bit unsigned literals. */
7787 if (TREE_CODE (arg1) != INTEGER_CST
7788 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7790 error ("argument 2 must be a 5-bit unsigned literal");
7796 || GET_MODE (target) != tmode
7797 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7798 target = gen_reg_rtx (tmode);
7800 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7801 op0 = copy_to_mode_reg (mode0, op0);
7802 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7803 op1 = copy_to_mode_reg (mode1, op1);
7805 pat = GEN_FCN (icode) (target, op0, op1);
7814 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7815 tree exp, rtx target)
7818 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7819 tree arg0 = CALL_EXPR_ARG (exp, 1);
7820 tree arg1 = CALL_EXPR_ARG (exp, 2);
7821 rtx op0 = expand_normal (arg0);
7822 rtx op1 = expand_normal (arg1);
7823 enum machine_mode tmode = SImode;
7824 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7825 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7828 if (TREE_CODE (cr6_form) != INTEGER_CST)
7830 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7834 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7836 gcc_assert (mode0 == mode1);
7838 /* If we have invalid arguments, bail out before generating bad rtl. */
7839 if (arg0 == error_mark_node || arg1 == error_mark_node)
7843 || GET_MODE (target) != tmode
7844 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7845 target = gen_reg_rtx (tmode);
7847 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7848 op0 = copy_to_mode_reg (mode0, op0);
7849 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7850 op1 = copy_to_mode_reg (mode1, op1);
7852 scratch = gen_reg_rtx (mode0);
7854 pat = GEN_FCN (icode) (scratch, op0, op1,
7855 gen_rtx_SYMBOL_REF (Pmode, opcode));
7860 /* The vec_any* and vec_all* predicates use the same opcodes for two
7861 different operations, but the bits in CR6 will be different
7862 depending on what information we want. So we have to play tricks
7863 with CR6 to get the right bits out.
7865 If you think this is disgusting, look at the specs for the
7866 AltiVec predicates. */
7868 switch (cr6_form_int)
7871 emit_insn (gen_cr6_test_for_zero (target));
7874 emit_insn (gen_cr6_test_for_zero_reverse (target));
7877 emit_insn (gen_cr6_test_for_lt (target));
7880 emit_insn (gen_cr6_test_for_lt_reverse (target));
7883 error ("argument 1 of __builtin_altivec_predicate is out of range");
7891 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7894 tree arg0 = CALL_EXPR_ARG (exp, 0);
7895 tree arg1 = CALL_EXPR_ARG (exp, 1);
7896 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7897 enum machine_mode mode0 = Pmode;
7898 enum machine_mode mode1 = Pmode;
7899 rtx op0 = expand_normal (arg0);
7900 rtx op1 = expand_normal (arg1);
7902 if (icode == CODE_FOR_nothing)
7903 /* Builtin not supported on this processor. */
7906 /* If we got invalid arguments bail out before generating bad rtl. */
7907 if (arg0 == error_mark_node || arg1 == error_mark_node)
7911 || GET_MODE (target) != tmode
7912 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7913 target = gen_reg_rtx (tmode);
7915 op1 = copy_to_mode_reg (mode1, op1);
7917 if (op0 == const0_rtx)
7919 addr = gen_rtx_MEM (tmode, op1);
7923 op0 = copy_to_mode_reg (mode0, op0);
7924 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7927 pat = GEN_FCN (icode) (target, addr);
7937 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7940 tree arg0 = CALL_EXPR_ARG (exp, 0);
7941 tree arg1 = CALL_EXPR_ARG (exp, 1);
7942 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7943 enum machine_mode mode0 = Pmode;
7944 enum machine_mode mode1 = Pmode;
7945 rtx op0 = expand_normal (arg0);
7946 rtx op1 = expand_normal (arg1);
7948 if (icode == CODE_FOR_nothing)
7949 /* Builtin not supported on this processor. */
7952 /* If we got invalid arguments bail out before generating bad rtl. */
7953 if (arg0 == error_mark_node || arg1 == error_mark_node)
7957 || GET_MODE (target) != tmode
7958 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7959 target = gen_reg_rtx (tmode);
7961 op1 = copy_to_mode_reg (mode1, op1);
7963 if (op0 == const0_rtx)
7965 addr = gen_rtx_MEM (tmode, op1);
7969 op0 = copy_to_mode_reg (mode0, op0);
7970 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7973 pat = GEN_FCN (icode) (target, addr);
7983 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7985 tree arg0 = CALL_EXPR_ARG (exp, 0);
7986 tree arg1 = CALL_EXPR_ARG (exp, 1);
7987 tree arg2 = CALL_EXPR_ARG (exp, 2);
7988 rtx op0 = expand_normal (arg0);
7989 rtx op1 = expand_normal (arg1);
7990 rtx op2 = expand_normal (arg2);
7992 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7993 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7994 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7996 /* Invalid arguments. Bail before doing anything stoopid! */
7997 if (arg0 == error_mark_node
7998 || arg1 == error_mark_node
7999 || arg2 == error_mark_node)
8002 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
8003 op0 = copy_to_mode_reg (mode2, op0);
8004 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
8005 op1 = copy_to_mode_reg (mode0, op1);
8006 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8007 op2 = copy_to_mode_reg (mode1, op2);
8009 pat = GEN_FCN (icode) (op1, op2, op0);
8016 paired_expand_stv_builtin (enum insn_code icode, tree exp)
8018 tree arg0 = CALL_EXPR_ARG (exp, 0);
8019 tree arg1 = CALL_EXPR_ARG (exp, 1);
8020 tree arg2 = CALL_EXPR_ARG (exp, 2);
8021 rtx op0 = expand_normal (arg0);
8022 rtx op1 = expand_normal (arg1);
8023 rtx op2 = expand_normal (arg2);
8025 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8026 enum machine_mode mode1 = Pmode;
8027 enum machine_mode mode2 = Pmode;
8029 /* Invalid arguments. Bail before doing anything stoopid! */
8030 if (arg0 == error_mark_node
8031 || arg1 == error_mark_node
8032 || arg2 == error_mark_node)
8035 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
8036 op0 = copy_to_mode_reg (tmode, op0);
8038 op2 = copy_to_mode_reg (mode2, op2);
8040 if (op1 == const0_rtx)
8042 addr = gen_rtx_MEM (tmode, op2);
8046 op1 = copy_to_mode_reg (mode1, op1);
8047 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
8050 pat = GEN_FCN (icode) (addr, op0);
8057 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
8059 tree arg0 = CALL_EXPR_ARG (exp, 0);
8060 tree arg1 = CALL_EXPR_ARG (exp, 1);
8061 tree arg2 = CALL_EXPR_ARG (exp, 2);
8062 rtx op0 = expand_normal (arg0);
8063 rtx op1 = expand_normal (arg1);
8064 rtx op2 = expand_normal (arg2);
8066 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8067 enum machine_mode mode1 = Pmode;
8068 enum machine_mode mode2 = Pmode;
8070 /* Invalid arguments. Bail before doing anything stoopid! */
8071 if (arg0 == error_mark_node
8072 || arg1 == error_mark_node
8073 || arg2 == error_mark_node)
8076 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
8077 op0 = copy_to_mode_reg (tmode, op0);
8079 op2 = copy_to_mode_reg (mode2, op2);
8081 if (op1 == const0_rtx)
8083 addr = gen_rtx_MEM (tmode, op2);
8087 op1 = copy_to_mode_reg (mode1, op1);
8088 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
8091 pat = GEN_FCN (icode) (addr, op0);
8098 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
8101 tree arg0 = CALL_EXPR_ARG (exp, 0);
8102 tree arg1 = CALL_EXPR_ARG (exp, 1);
8103 tree arg2 = CALL_EXPR_ARG (exp, 2);
8104 rtx op0 = expand_normal (arg0);
8105 rtx op1 = expand_normal (arg1);
8106 rtx op2 = expand_normal (arg2);
8107 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8108 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8109 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8110 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
8112 if (icode == CODE_FOR_nothing)
8113 /* Builtin not supported on this processor. */
8116 /* If we got invalid arguments bail out before generating bad rtl. */
8117 if (arg0 == error_mark_node
8118 || arg1 == error_mark_node
8119 || arg2 == error_mark_node)
8122 if (icode == CODE_FOR_altivec_vsldoi_v4sf
8123 || icode == CODE_FOR_altivec_vsldoi_v4si
8124 || icode == CODE_FOR_altivec_vsldoi_v8hi
8125 || icode == CODE_FOR_altivec_vsldoi_v16qi)
8127 /* Only allow 4-bit unsigned literals. */
8129 if (TREE_CODE (arg2) != INTEGER_CST
8130 || TREE_INT_CST_LOW (arg2) & ~0xf)
8132 error ("argument 3 must be a 4-bit unsigned literal");
8138 || GET_MODE (target) != tmode
8139 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8140 target = gen_reg_rtx (tmode);
8142 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8143 op0 = copy_to_mode_reg (mode0, op0);
8144 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8145 op1 = copy_to_mode_reg (mode1, op1);
8146 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
8147 op2 = copy_to_mode_reg (mode2, op2);
8149 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
8150 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
8152 pat = GEN_FCN (icode) (target, op0, op1, op2);
8160 /* Expand the lvx builtins. */
8162 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
8164 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8165 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8167 enum machine_mode tmode, mode0;
8169 enum insn_code icode;
8173 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
8174 icode = CODE_FOR_altivec_lvx_v16qi;
8176 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
8177 icode = CODE_FOR_altivec_lvx_v8hi;
8179 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
8180 icode = CODE_FOR_altivec_lvx_v4si;
8182 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
8183 icode = CODE_FOR_altivec_lvx_v4sf;
8192 arg0 = CALL_EXPR_ARG (exp, 0);
8193 op0 = expand_normal (arg0);
8194 tmode = insn_data[icode].operand[0].mode;
8195 mode0 = insn_data[icode].operand[1].mode;
8198 || GET_MODE (target) != tmode
8199 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8200 target = gen_reg_rtx (tmode);
8202 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8203 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8205 pat = GEN_FCN (icode) (target, op0);
8212 /* Expand the stvx builtins. */
8214 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8217 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8218 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8220 enum machine_mode mode0, mode1;
8222 enum insn_code icode;
8226 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
8227 icode = CODE_FOR_altivec_stvx_v16qi;
8229 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
8230 icode = CODE_FOR_altivec_stvx_v8hi;
8232 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
8233 icode = CODE_FOR_altivec_stvx_v4si;
8235 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
8236 icode = CODE_FOR_altivec_stvx_v4sf;
8243 arg0 = CALL_EXPR_ARG (exp, 0);
8244 arg1 = CALL_EXPR_ARG (exp, 1);
8245 op0 = expand_normal (arg0);
8246 op1 = expand_normal (arg1);
8247 mode0 = insn_data[icode].operand[0].mode;
8248 mode1 = insn_data[icode].operand[1].mode;
8250 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8251 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8252 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8253 op1 = copy_to_mode_reg (mode1, op1);
8255 pat = GEN_FCN (icode) (op0, op1);
8263 /* Expand the dst builtins. */
8265 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8268 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8269 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8270 tree arg0, arg1, arg2;
8271 enum machine_mode mode0, mode1, mode2;
8272 rtx pat, op0, op1, op2;
8273 const struct builtin_description *d;
8278 /* Handle DST variants. */
8280 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8281 if (d->code == fcode)
8283 arg0 = CALL_EXPR_ARG (exp, 0);
8284 arg1 = CALL_EXPR_ARG (exp, 1);
8285 arg2 = CALL_EXPR_ARG (exp, 2);
8286 op0 = expand_normal (arg0);
8287 op1 = expand_normal (arg1);
8288 op2 = expand_normal (arg2);
8289 mode0 = insn_data[d->icode].operand[0].mode;
8290 mode1 = insn_data[d->icode].operand[1].mode;
8291 mode2 = insn_data[d->icode].operand[2].mode;
8293 /* Invalid arguments, bail out before generating bad rtl. */
8294 if (arg0 == error_mark_node
8295 || arg1 == error_mark_node
8296 || arg2 == error_mark_node)
8301 if (TREE_CODE (arg2) != INTEGER_CST
8302 || TREE_INT_CST_LOW (arg2) & ~0x3)
8304 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
8308 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
8309 op0 = copy_to_mode_reg (Pmode, op0);
8310 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
8311 op1 = copy_to_mode_reg (mode1, op1);
8313 pat = GEN_FCN (d->icode) (op0, op1, op2);
8323 /* Expand vec_init builtin. */
8325 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
8327 enum machine_mode tmode = TYPE_MODE (type);
8328 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
8329 int i, n_elt = GET_MODE_NUNITS (tmode);
8330 rtvec v = rtvec_alloc (n_elt);
8332 gcc_assert (VECTOR_MODE_P (tmode));
8333 gcc_assert (n_elt == call_expr_nargs (exp));
8335 for (i = 0; i < n_elt; ++i)
8337 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
8338 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
8341 if (!target || !register_operand (target, tmode))
8342 target = gen_reg_rtx (tmode);
8344 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
8348 /* Return the integer constant in ARG. Constrain it to be in the range
8349 of the subparts of VEC_TYPE; issue an error if not. */
8352 get_element_number (tree vec_type, tree arg)
8354 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
8356 if (!host_integerp (arg, 1)
8357 || (elt = tree_low_cst (arg, 1), elt > max))
8359 error ("selector must be an integer constant in the range 0..%wi", max);
8366 /* Expand vec_set builtin. */
8368 altivec_expand_vec_set_builtin (tree exp)
8370 enum machine_mode tmode, mode1;
8371 tree arg0, arg1, arg2;
8375 arg0 = CALL_EXPR_ARG (exp, 0);
8376 arg1 = CALL_EXPR_ARG (exp, 1);
8377 arg2 = CALL_EXPR_ARG (exp, 2);
8379 tmode = TYPE_MODE (TREE_TYPE (arg0));
8380 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8381 gcc_assert (VECTOR_MODE_P (tmode));
8383 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
8384 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
8385 elt = get_element_number (TREE_TYPE (arg0), arg2);
8387 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
8388 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
8390 op0 = force_reg (tmode, op0);
8391 op1 = force_reg (mode1, op1);
8393 rs6000_expand_vector_set (op0, op1, elt);
8398 /* Expand vec_ext builtin. */
8400 altivec_expand_vec_ext_builtin (tree exp, rtx target)
8402 enum machine_mode tmode, mode0;
8407 arg0 = CALL_EXPR_ARG (exp, 0);
8408 arg1 = CALL_EXPR_ARG (exp, 1);
8410 op0 = expand_normal (arg0);
8411 elt = get_element_number (TREE_TYPE (arg0), arg1);
8413 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8414 mode0 = TYPE_MODE (TREE_TYPE (arg0));
8415 gcc_assert (VECTOR_MODE_P (mode0));
8417 op0 = force_reg (mode0, op0);
8419 if (optimize || !target || !register_operand (target, tmode))
8420 target = gen_reg_rtx (tmode);
8422 rs6000_expand_vector_extract (target, op0, elt);
8427 /* Expand the builtin in EXP and store the result in TARGET. Store
8428 true in *EXPANDEDP if we found a builtin to expand. */
8430 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
8432 const struct builtin_description *d;
8433 const struct builtin_description_predicates *dp;
8435 enum insn_code icode;
8436 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8439 enum machine_mode tmode, mode0;
8440 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8442 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8443 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
8446 error ("unresolved overload for Altivec builtin %qF", fndecl);
8450 target = altivec_expand_ld_builtin (exp, target, expandedp);
8454 target = altivec_expand_st_builtin (exp, target, expandedp);
8458 target = altivec_expand_dst_builtin (exp, target, expandedp);
8466 case ALTIVEC_BUILTIN_STVX:
8467 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
8468 case ALTIVEC_BUILTIN_STVEBX:
8469 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
8470 case ALTIVEC_BUILTIN_STVEHX:
8471 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
8472 case ALTIVEC_BUILTIN_STVEWX:
8473 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
8474 case ALTIVEC_BUILTIN_STVXL:
8475 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
8477 case ALTIVEC_BUILTIN_MFVSCR:
8478 icode = CODE_FOR_altivec_mfvscr;
8479 tmode = insn_data[icode].operand[0].mode;
8482 || GET_MODE (target) != tmode
8483 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8484 target = gen_reg_rtx (tmode);
8486 pat = GEN_FCN (icode) (target);
8492 case ALTIVEC_BUILTIN_MTVSCR:
8493 icode = CODE_FOR_altivec_mtvscr;
8494 arg0 = CALL_EXPR_ARG (exp, 0);
8495 op0 = expand_normal (arg0);
8496 mode0 = insn_data[icode].operand[0].mode;
8498 /* If we got invalid arguments bail out before generating bad rtl. */
8499 if (arg0 == error_mark_node)
8502 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8503 op0 = copy_to_mode_reg (mode0, op0);
8505 pat = GEN_FCN (icode) (op0);
8510 case ALTIVEC_BUILTIN_DSSALL:
8511 emit_insn (gen_altivec_dssall ());
8514 case ALTIVEC_BUILTIN_DSS:
8515 icode = CODE_FOR_altivec_dss;
8516 arg0 = CALL_EXPR_ARG (exp, 0);
8518 op0 = expand_normal (arg0);
8519 mode0 = insn_data[icode].operand[0].mode;
8521 /* If we got invalid arguments bail out before generating bad rtl. */
8522 if (arg0 == error_mark_node)
8525 if (TREE_CODE (arg0) != INTEGER_CST
8526 || TREE_INT_CST_LOW (arg0) & ~0x3)
8528 error ("argument to dss must be a 2-bit unsigned literal");
8532 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8533 op0 = copy_to_mode_reg (mode0, op0);
8535 emit_insn (gen_altivec_dss (op0));
8538 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8539 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8540 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8541 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8542 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8544 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8545 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8546 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8547 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8548 return altivec_expand_vec_set_builtin (exp);
8550 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8551 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8552 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8553 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8554 return altivec_expand_vec_ext_builtin (exp, target);
8561 /* Expand abs* operations. */
8563 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8564 if (d->code == fcode)
8565 return altivec_expand_abs_builtin (d->icode, exp, target);
8567 /* Expand the AltiVec predicates. */
8568 dp = bdesc_altivec_preds;
8569 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8570 if (dp->code == fcode)
8571 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8574 /* LV* are funky. We initialized them differently. */
8577 case ALTIVEC_BUILTIN_LVSL:
8578 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8580 case ALTIVEC_BUILTIN_LVSR:
8581 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8583 case ALTIVEC_BUILTIN_LVEBX:
8584 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8586 case ALTIVEC_BUILTIN_LVEHX:
8587 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8589 case ALTIVEC_BUILTIN_LVEWX:
8590 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8592 case ALTIVEC_BUILTIN_LVXL:
8593 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8595 case ALTIVEC_BUILTIN_LVX:
8596 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8607 /* Expand the builtin in EXP and store the result in TARGET. Store
8608 true in *EXPANDEDP if we found a builtin to expand. */
8610 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
8612 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8613 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8614 const struct builtin_description *d;
8621 case PAIRED_BUILTIN_STX:
8622 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
8623 case PAIRED_BUILTIN_LX:
8624 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
8630 /* Expand the paired predicates. */
8631 d = bdesc_paired_preds;
8632 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
8633 if (d->code == fcode)
8634 return paired_expand_predicate_builtin (d->icode, exp, target);
8640 /* Binops that need to be initialized manually, but can be expanded
8641 automagically by rs6000_expand_binop_builtin. */
8642 static struct builtin_description bdesc_2arg_spe[] =
8644 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8645 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8646 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8647 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8648 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8649 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8650 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8651 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8652 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8653 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8654 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8655 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8656 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8657 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8658 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8659 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8660 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8661 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8662 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8663 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8664 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8665 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8668 /* Expand the builtin in EXP and store the result in TARGET. Store
8669 true in *EXPANDEDP if we found a builtin to expand.
8671 This expands the SPE builtins that are not simple unary and binary
8674 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8676 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8678 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8679 enum insn_code icode;
8680 enum machine_mode tmode, mode0;
8682 struct builtin_description *d;
8687 /* Syntax check for a 5-bit unsigned immediate. */
8690 case SPE_BUILTIN_EVSTDD:
8691 case SPE_BUILTIN_EVSTDH:
8692 case SPE_BUILTIN_EVSTDW:
8693 case SPE_BUILTIN_EVSTWHE:
8694 case SPE_BUILTIN_EVSTWHO:
8695 case SPE_BUILTIN_EVSTWWE:
8696 case SPE_BUILTIN_EVSTWWO:
8697 arg1 = CALL_EXPR_ARG (exp, 2);
8698 if (TREE_CODE (arg1) != INTEGER_CST
8699 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8701 error ("argument 2 must be a 5-bit unsigned literal");
8709 /* The evsplat*i instructions are not quite generic. */
8712 case SPE_BUILTIN_EVSPLATFI:
8713 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8715 case SPE_BUILTIN_EVSPLATI:
8716 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8722 d = (struct builtin_description *) bdesc_2arg_spe;
8723 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8724 if (d->code == fcode)
8725 return rs6000_expand_binop_builtin (d->icode, exp, target);
8727 d = (struct builtin_description *) bdesc_spe_predicates;
8728 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8729 if (d->code == fcode)
8730 return spe_expand_predicate_builtin (d->icode, exp, target);
8732 d = (struct builtin_description *) bdesc_spe_evsel;
8733 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8734 if (d->code == fcode)
8735 return spe_expand_evsel_builtin (d->icode, exp, target);
8739 case SPE_BUILTIN_EVSTDDX:
8740 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8741 case SPE_BUILTIN_EVSTDHX:
8742 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8743 case SPE_BUILTIN_EVSTDWX:
8744 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8745 case SPE_BUILTIN_EVSTWHEX:
8746 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8747 case SPE_BUILTIN_EVSTWHOX:
8748 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8749 case SPE_BUILTIN_EVSTWWEX:
8750 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8751 case SPE_BUILTIN_EVSTWWOX:
8752 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8753 case SPE_BUILTIN_EVSTDD:
8754 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8755 case SPE_BUILTIN_EVSTDH:
8756 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8757 case SPE_BUILTIN_EVSTDW:
8758 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8759 case SPE_BUILTIN_EVSTWHE:
8760 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8761 case SPE_BUILTIN_EVSTWHO:
8762 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8763 case SPE_BUILTIN_EVSTWWE:
8764 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8765 case SPE_BUILTIN_EVSTWWO:
8766 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8767 case SPE_BUILTIN_MFSPEFSCR:
8768 icode = CODE_FOR_spe_mfspefscr;
8769 tmode = insn_data[icode].operand[0].mode;
8772 || GET_MODE (target) != tmode
8773 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8774 target = gen_reg_rtx (tmode);
8776 pat = GEN_FCN (icode) (target);
8781 case SPE_BUILTIN_MTSPEFSCR:
8782 icode = CODE_FOR_spe_mtspefscr;
8783 arg0 = CALL_EXPR_ARG (exp, 0);
8784 op0 = expand_normal (arg0);
8785 mode0 = insn_data[icode].operand[0].mode;
8787 if (arg0 == error_mark_node)
8790 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8791 op0 = copy_to_mode_reg (mode0, op0);
8793 pat = GEN_FCN (icode) (op0);
8806 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8808 rtx pat, scratch, tmp;
8809 tree form = CALL_EXPR_ARG (exp, 0);
8810 tree arg0 = CALL_EXPR_ARG (exp, 1);
8811 tree arg1 = CALL_EXPR_ARG (exp, 2);
8812 rtx op0 = expand_normal (arg0);
8813 rtx op1 = expand_normal (arg1);
8814 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8815 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8819 if (TREE_CODE (form) != INTEGER_CST)
8821 error ("argument 1 of __builtin_paired_predicate must be a constant");
8825 form_int = TREE_INT_CST_LOW (form);
8827 gcc_assert (mode0 == mode1);
8829 if (arg0 == error_mark_node || arg1 == error_mark_node)
8833 || GET_MODE (target) != SImode
8834 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
8835 target = gen_reg_rtx (SImode);
8836 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
8837 op0 = copy_to_mode_reg (mode0, op0);
8838 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
8839 op1 = copy_to_mode_reg (mode1, op1);
8841 scratch = gen_reg_rtx (CCFPmode);
8843 pat = GEN_FCN (icode) (scratch, op0, op1);
8865 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8868 error ("argument 1 of __builtin_paired_predicate is out of range");
8872 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8873 emit_move_insn (target, tmp);
8878 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8880 rtx pat, scratch, tmp;
8881 tree form = CALL_EXPR_ARG (exp, 0);
8882 tree arg0 = CALL_EXPR_ARG (exp, 1);
8883 tree arg1 = CALL_EXPR_ARG (exp, 2);
8884 rtx op0 = expand_normal (arg0);
8885 rtx op1 = expand_normal (arg1);
8886 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8887 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8891 if (TREE_CODE (form) != INTEGER_CST)
8893 error ("argument 1 of __builtin_spe_predicate must be a constant");
8897 form_int = TREE_INT_CST_LOW (form);
8899 gcc_assert (mode0 == mode1);
8901 if (arg0 == error_mark_node || arg1 == error_mark_node)
8905 || GET_MODE (target) != SImode
8906 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8907 target = gen_reg_rtx (SImode);
8909 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8910 op0 = copy_to_mode_reg (mode0, op0);
8911 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8912 op1 = copy_to_mode_reg (mode1, op1);
8914 scratch = gen_reg_rtx (CCmode);
8916 pat = GEN_FCN (icode) (scratch, op0, op1);
8921 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8922 _lower_. We use one compare, but look in different bits of the
8923 CR for each variant.
8925 There are 2 elements in each SPE simd type (upper/lower). The CR
8926 bits are set as follows:
8928 BIT0 | BIT 1 | BIT 2 | BIT 3
8929 U | L | (U | L) | (U & L)
8931 So, for an "all" relationship, BIT 3 would be set.
8932 For an "any" relationship, BIT 2 would be set. Etc.
8934 Following traditional nomenclature, these bits map to:
8936 BIT0 | BIT 1 | BIT 2 | BIT 3
8939 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8944 /* All variant. OV bit. */
8946 /* We need to get to the OV bit, which is the ORDERED bit. We
8947 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8948 that's ugly and will make validate_condition_mode die.
8949 So let's just use another pattern. */
8950 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8952 /* Any variant. EQ bit. */
8956 /* Upper variant. LT bit. */
8960 /* Lower variant. GT bit. */
8965 error ("argument 1 of __builtin_spe_predicate is out of range");
8969 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8970 emit_move_insn (target, tmp);
8975 /* The evsel builtins look like this:
8977 e = __builtin_spe_evsel_OP (a, b, c, d);
8981 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8982 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8986 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8989 tree arg0 = CALL_EXPR_ARG (exp, 0);
8990 tree arg1 = CALL_EXPR_ARG (exp, 1);
8991 tree arg2 = CALL_EXPR_ARG (exp, 2);
8992 tree arg3 = CALL_EXPR_ARG (exp, 3);
8993 rtx op0 = expand_normal (arg0);
8994 rtx op1 = expand_normal (arg1);
8995 rtx op2 = expand_normal (arg2);
8996 rtx op3 = expand_normal (arg3);
8997 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8998 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9000 gcc_assert (mode0 == mode1);
9002 if (arg0 == error_mark_node || arg1 == error_mark_node
9003 || arg2 == error_mark_node || arg3 == error_mark_node)
9007 || GET_MODE (target) != mode0
9008 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
9009 target = gen_reg_rtx (mode0);
9011 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9012 op0 = copy_to_mode_reg (mode0, op0);
9013 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
9014 op1 = copy_to_mode_reg (mode0, op1);
9015 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
9016 op2 = copy_to_mode_reg (mode0, op2);
9017 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
9018 op3 = copy_to_mode_reg (mode0, op3);
9020 /* Generate the compare. */
9021 scratch = gen_reg_rtx (CCmode);
9022 pat = GEN_FCN (icode) (scratch, op0, op1);
9027 if (mode0 == V2SImode)
9028 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
9030 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
9035 /* Expand an expression EXP that calls a built-in function,
9036 with result going to TARGET if that's convenient
9037 (and in mode MODE if that's convenient).
9038 SUBTARGET may be used as the target for computing one of EXP's operands.
9039 IGNORE is nonzero if the value is to be ignored. */
9042 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9043 enum machine_mode mode ATTRIBUTE_UNUSED,
9044 int ignore ATTRIBUTE_UNUSED)
9046 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9047 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9048 const struct builtin_description *d;
9053 if (fcode == RS6000_BUILTIN_RECIP)
9054 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
9056 if (fcode == RS6000_BUILTIN_RECIPF)
9057 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
9059 if (fcode == RS6000_BUILTIN_RSQRTF)
9060 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
9062 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
9063 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
9065 int icode = (int) CODE_FOR_altivec_lvsr;
9066 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9067 enum machine_mode mode = insn_data[icode].operand[1].mode;
9071 gcc_assert (TARGET_ALTIVEC);
9073 arg = CALL_EXPR_ARG (exp, 0);
9074 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
9075 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
9076 addr = memory_address (mode, op);
9077 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
9081 /* For the load case need to negate the address. */
9082 op = gen_reg_rtx (GET_MODE (addr));
9083 emit_insn (gen_rtx_SET (VOIDmode, op,
9084 gen_rtx_NEG (GET_MODE (addr), addr)));
9086 op = gen_rtx_MEM (mode, op);
9089 || GET_MODE (target) != tmode
9090 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9091 target = gen_reg_rtx (tmode);
9093 /*pat = gen_altivec_lvsr (target, op);*/
9094 pat = GEN_FCN (icode) (target, op);
9102 /* FIXME: There's got to be a nicer way to handle this case than
9103 constructing a new CALL_EXPR. */
9104 if (fcode == ALTIVEC_BUILTIN_VCFUX
9105 || fcode == ALTIVEC_BUILTIN_VCFSX)
9107 if (call_expr_nargs (exp) == 1)
9108 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
9109 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
9114 ret = altivec_expand_builtin (exp, target, &success);
9121 ret = spe_expand_builtin (exp, target, &success);
9126 if (TARGET_PAIRED_FLOAT)
9128 ret = paired_expand_builtin (exp, target, &success);
9134 gcc_assert (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT);
9136 /* Handle simple unary operations. */
9137 d = (struct builtin_description *) bdesc_1arg;
9138 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9139 if (d->code == fcode)
9140 return rs6000_expand_unop_builtin (d->icode, exp, target);
9142 /* Handle simple binary operations. */
9143 d = (struct builtin_description *) bdesc_2arg;
9144 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9145 if (d->code == fcode)
9146 return rs6000_expand_binop_builtin (d->icode, exp, target);
9148 /* Handle simple ternary operations. */
9150 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9151 if (d->code == fcode)
9152 return rs6000_expand_ternop_builtin (d->icode, exp, target);
9158 build_opaque_vector_type (tree node, int nunits)
9160 node = copy_node (node);
9161 TYPE_MAIN_VARIANT (node) = node;
9162 TYPE_CANONICAL (node) = node;
9163 return build_vector_type (node, nunits);
9167 rs6000_init_builtins (void)
9169 V2SI_type_node = build_vector_type (intSI_type_node, 2);
9170 V2SF_type_node = build_vector_type (float_type_node, 2);
9171 V4HI_type_node = build_vector_type (intHI_type_node, 4);
9172 V4SI_type_node = build_vector_type (intSI_type_node, 4);
9173 V4SF_type_node = build_vector_type (float_type_node, 4);
9174 V8HI_type_node = build_vector_type (intHI_type_node, 8);
9175 V16QI_type_node = build_vector_type (intQI_type_node, 16);
9177 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
9178 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
9179 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
9181 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
9182 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
9183 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
9184 opaque_V4SI_type_node = copy_node (V4SI_type_node);
9186 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9187 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9188 'vector unsigned short'. */
9190 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
9191 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9192 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
9193 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9195 long_integer_type_internal_node = long_integer_type_node;
9196 long_unsigned_type_internal_node = long_unsigned_type_node;
9197 intQI_type_internal_node = intQI_type_node;
9198 uintQI_type_internal_node = unsigned_intQI_type_node;
9199 intHI_type_internal_node = intHI_type_node;
9200 uintHI_type_internal_node = unsigned_intHI_type_node;
9201 intSI_type_internal_node = intSI_type_node;
9202 uintSI_type_internal_node = unsigned_intSI_type_node;
9203 float_type_internal_node = float_type_node;
9204 void_type_internal_node = void_type_node;
9206 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9207 get_identifier ("__bool char"),
9208 bool_char_type_node));
9209 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9210 get_identifier ("__bool short"),
9211 bool_short_type_node));
9212 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9213 get_identifier ("__bool int"),
9214 bool_int_type_node));
9215 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9216 get_identifier ("__pixel"),
9219 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
9220 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
9221 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
9222 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
9224 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9225 get_identifier ("__vector unsigned char"),
9226 unsigned_V16QI_type_node));
9227 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9228 get_identifier ("__vector signed char"),
9230 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9231 get_identifier ("__vector __bool char"),
9232 bool_V16QI_type_node));
9234 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9235 get_identifier ("__vector unsigned short"),
9236 unsigned_V8HI_type_node));
9237 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9238 get_identifier ("__vector signed short"),
9240 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9241 get_identifier ("__vector __bool short"),
9242 bool_V8HI_type_node));
9244 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9245 get_identifier ("__vector unsigned int"),
9246 unsigned_V4SI_type_node));
9247 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9248 get_identifier ("__vector signed int"),
9250 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9251 get_identifier ("__vector __bool int"),
9252 bool_V4SI_type_node));
9254 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9255 get_identifier ("__vector float"),
9257 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
9258 get_identifier ("__vector __pixel"),
9259 pixel_V8HI_type_node));
9261 if (TARGET_PAIRED_FLOAT)
9262 paired_init_builtins ();
9264 spe_init_builtins ();
9266 altivec_init_builtins ();
9267 if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT)
9268 rs6000_common_init_builtins ();
9269 if (TARGET_PPC_GFXOPT)
9271 tree ftype = build_function_type_list (float_type_node,
9275 def_builtin (MASK_PPC_GFXOPT, "__builtin_recipdivf", ftype,
9276 RS6000_BUILTIN_RECIPF);
9278 ftype = build_function_type_list (float_type_node,
9281 def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrtf", ftype,
9282 RS6000_BUILTIN_RSQRTF);
9286 tree ftype = build_function_type_list (double_type_node,
9290 def_builtin (MASK_POPCNTB, "__builtin_recipdiv", ftype,
9291 RS6000_BUILTIN_RECIP);
9296 /* AIX libm provides clog as __clog. */
9297 if (built_in_decls [BUILT_IN_CLOG])
9298 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
9301 #ifdef SUBTARGET_INIT_BUILTINS
9302 SUBTARGET_INIT_BUILTINS;
9306 /* Search through a set of builtins and enable the mask bits.
9307 DESC is an array of builtins.
9308 SIZE is the total number of builtins.
9309 START is the builtin enum at which to start.
9310 END is the builtin enum at which to end. */
9312 enable_mask_for_builtins (struct builtin_description *desc, int size,
9313 enum rs6000_builtins start,
9314 enum rs6000_builtins end)
9318 for (i = 0; i < size; ++i)
9319 if (desc[i].code == start)
9325 for (; i < size; ++i)
9327 /* Flip all the bits on. */
9328 desc[i].mask = target_flags;
9329 if (desc[i].code == end)
9335 spe_init_builtins (void)
9337 tree endlink = void_list_node;
9338 tree puint_type_node = build_pointer_type (unsigned_type_node);
9339 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
9340 struct builtin_description *d;
9343 tree v2si_ftype_4_v2si
9344 = build_function_type
9345 (opaque_V2SI_type_node,
9346 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9347 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9348 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9349 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9352 tree v2sf_ftype_4_v2sf
9353 = build_function_type
9354 (opaque_V2SF_type_node,
9355 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9356 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9357 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9358 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9361 tree int_ftype_int_v2si_v2si
9362 = build_function_type
9364 tree_cons (NULL_TREE, integer_type_node,
9365 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9366 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9369 tree int_ftype_int_v2sf_v2sf
9370 = build_function_type
9372 tree_cons (NULL_TREE, integer_type_node,
9373 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9374 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9377 tree void_ftype_v2si_puint_int
9378 = build_function_type (void_type_node,
9379 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9380 tree_cons (NULL_TREE, puint_type_node,
9381 tree_cons (NULL_TREE,
9385 tree void_ftype_v2si_puint_char
9386 = build_function_type (void_type_node,
9387 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9388 tree_cons (NULL_TREE, puint_type_node,
9389 tree_cons (NULL_TREE,
9393 tree void_ftype_v2si_pv2si_int
9394 = build_function_type (void_type_node,
9395 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9396 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9397 tree_cons (NULL_TREE,
9401 tree void_ftype_v2si_pv2si_char
9402 = build_function_type (void_type_node,
9403 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9404 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9405 tree_cons (NULL_TREE,
9410 = build_function_type (void_type_node,
9411 tree_cons (NULL_TREE, integer_type_node, endlink));
9414 = build_function_type (integer_type_node, endlink);
9416 tree v2si_ftype_pv2si_int
9417 = build_function_type (opaque_V2SI_type_node,
9418 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9419 tree_cons (NULL_TREE, integer_type_node,
9422 tree v2si_ftype_puint_int
9423 = build_function_type (opaque_V2SI_type_node,
9424 tree_cons (NULL_TREE, puint_type_node,
9425 tree_cons (NULL_TREE, integer_type_node,
9428 tree v2si_ftype_pushort_int
9429 = build_function_type (opaque_V2SI_type_node,
9430 tree_cons (NULL_TREE, pushort_type_node,
9431 tree_cons (NULL_TREE, integer_type_node,
9434 tree v2si_ftype_signed_char
9435 = build_function_type (opaque_V2SI_type_node,
9436 tree_cons (NULL_TREE, signed_char_type_node,
9439 /* The initialization of the simple binary and unary builtins is
9440 done in rs6000_common_init_builtins, but we have to enable the
9441 mask bits here manually because we have run out of `target_flags'
9442 bits. We really need to redesign this mask business. */
9444 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
9445 ARRAY_SIZE (bdesc_2arg),
9448 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
9449 ARRAY_SIZE (bdesc_1arg),
9451 SPE_BUILTIN_EVSUBFUSIAAW);
9452 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
9453 ARRAY_SIZE (bdesc_spe_predicates),
9454 SPE_BUILTIN_EVCMPEQ,
9455 SPE_BUILTIN_EVFSTSTLT);
9456 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
9457 ARRAY_SIZE (bdesc_spe_evsel),
9458 SPE_BUILTIN_EVSEL_CMPGTS,
9459 SPE_BUILTIN_EVSEL_FSTSTEQ);
9461 (*lang_hooks.decls.pushdecl)
9462 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
9463 opaque_V2SI_type_node));
9465 /* Initialize irregular SPE builtins. */
9467 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
9468 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
9469 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
9470 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
9471 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
9472 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
9473 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
9474 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
9475 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
9476 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
9477 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
9478 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
9479 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
9480 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
9481 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
9482 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
9483 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
9484 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
9487 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
9488 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
9489 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
9490 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
9491 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
9492 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
9493 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
9494 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
9495 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
9496 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
9497 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
9498 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
9499 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
9500 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
9501 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
9502 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
9503 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
9504 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
9505 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
9506 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
9507 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
9508 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
9511 d = (struct builtin_description *) bdesc_spe_predicates;
9512 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
9516 switch (insn_data[d->icode].operand[1].mode)
9519 type = int_ftype_int_v2si_v2si;
9522 type = int_ftype_int_v2sf_v2sf;
9528 def_builtin (d->mask, d->name, type, d->code);
9531 /* Evsel predicates. */
9532 d = (struct builtin_description *) bdesc_spe_evsel;
9533 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
9537 switch (insn_data[d->icode].operand[1].mode)
9540 type = v2si_ftype_4_v2si;
9543 type = v2sf_ftype_4_v2sf;
9549 def_builtin (d->mask, d->name, type, d->code);
9554 paired_init_builtins (void)
9556 const struct builtin_description *d;
9558 tree endlink = void_list_node;
9560 tree int_ftype_int_v2sf_v2sf
9561 = build_function_type
9563 tree_cons (NULL_TREE, integer_type_node,
9564 tree_cons (NULL_TREE, V2SF_type_node,
9565 tree_cons (NULL_TREE, V2SF_type_node,
9567 tree pcfloat_type_node =
9568 build_pointer_type (build_qualified_type
9569 (float_type_node, TYPE_QUAL_CONST));
9571 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
9572 long_integer_type_node,
9575 tree void_ftype_v2sf_long_pcfloat =
9576 build_function_type_list (void_type_node,
9578 long_integer_type_node,
9583 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat,
9587 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
9588 PAIRED_BUILTIN_STX);
9591 d = bdesc_paired_preds;
9592 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
9596 switch (insn_data[d->icode].operand[1].mode)
9599 type = int_ftype_int_v2sf_v2sf;
9605 def_builtin (d->mask, d->name, type, d->code);
9610 altivec_init_builtins (void)
9612 const struct builtin_description *d;
9613 const struct builtin_description_predicates *dp;
9617 tree pfloat_type_node = build_pointer_type (float_type_node);
9618 tree pint_type_node = build_pointer_type (integer_type_node);
9619 tree pshort_type_node = build_pointer_type (short_integer_type_node);
9620 tree pchar_type_node = build_pointer_type (char_type_node);
9622 tree pvoid_type_node = build_pointer_type (void_type_node);
9624 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
9625 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
9626 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
9627 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
9629 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
9631 tree int_ftype_opaque
9632 = build_function_type_list (integer_type_node,
9633 opaque_V4SI_type_node, NULL_TREE);
9635 tree opaque_ftype_opaque_int
9636 = build_function_type_list (opaque_V4SI_type_node,
9637 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
9638 tree opaque_ftype_opaque_opaque_int
9639 = build_function_type_list (opaque_V4SI_type_node,
9640 opaque_V4SI_type_node, opaque_V4SI_type_node,
9641 integer_type_node, NULL_TREE);
9642 tree int_ftype_int_opaque_opaque
9643 = build_function_type_list (integer_type_node,
9644 integer_type_node, opaque_V4SI_type_node,
9645 opaque_V4SI_type_node, NULL_TREE);
9646 tree int_ftype_int_v4si_v4si
9647 = build_function_type_list (integer_type_node,
9648 integer_type_node, V4SI_type_node,
9649 V4SI_type_node, NULL_TREE);
9650 tree v4sf_ftype_pcfloat
9651 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
9652 tree void_ftype_pfloat_v4sf
9653 = build_function_type_list (void_type_node,
9654 pfloat_type_node, V4SF_type_node, NULL_TREE);
9655 tree v4si_ftype_pcint
9656 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
9657 tree void_ftype_pint_v4si
9658 = build_function_type_list (void_type_node,
9659 pint_type_node, V4SI_type_node, NULL_TREE);
9660 tree v8hi_ftype_pcshort
9661 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
9662 tree void_ftype_pshort_v8hi
9663 = build_function_type_list (void_type_node,
9664 pshort_type_node, V8HI_type_node, NULL_TREE);
9665 tree v16qi_ftype_pcchar
9666 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
9667 tree void_ftype_pchar_v16qi
9668 = build_function_type_list (void_type_node,
9669 pchar_type_node, V16QI_type_node, NULL_TREE);
9670 tree void_ftype_v4si
9671 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
9672 tree v8hi_ftype_void
9673 = build_function_type (V8HI_type_node, void_list_node);
9674 tree void_ftype_void
9675 = build_function_type (void_type_node, void_list_node);
9677 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
9679 tree opaque_ftype_long_pcvoid
9680 = build_function_type_list (opaque_V4SI_type_node,
9681 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9682 tree v16qi_ftype_long_pcvoid
9683 = build_function_type_list (V16QI_type_node,
9684 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9685 tree v8hi_ftype_long_pcvoid
9686 = build_function_type_list (V8HI_type_node,
9687 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9688 tree v4si_ftype_long_pcvoid
9689 = build_function_type_list (V4SI_type_node,
9690 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9692 tree void_ftype_opaque_long_pvoid
9693 = build_function_type_list (void_type_node,
9694 opaque_V4SI_type_node, long_integer_type_node,
9695 pvoid_type_node, NULL_TREE);
9696 tree void_ftype_v4si_long_pvoid
9697 = build_function_type_list (void_type_node,
9698 V4SI_type_node, long_integer_type_node,
9699 pvoid_type_node, NULL_TREE);
9700 tree void_ftype_v16qi_long_pvoid
9701 = build_function_type_list (void_type_node,
9702 V16QI_type_node, long_integer_type_node,
9703 pvoid_type_node, NULL_TREE);
9704 tree void_ftype_v8hi_long_pvoid
9705 = build_function_type_list (void_type_node,
9706 V8HI_type_node, long_integer_type_node,
9707 pvoid_type_node, NULL_TREE);
9708 tree int_ftype_int_v8hi_v8hi
9709 = build_function_type_list (integer_type_node,
9710 integer_type_node, V8HI_type_node,
9711 V8HI_type_node, NULL_TREE);
9712 tree int_ftype_int_v16qi_v16qi
9713 = build_function_type_list (integer_type_node,
9714 integer_type_node, V16QI_type_node,
9715 V16QI_type_node, NULL_TREE);
9716 tree int_ftype_int_v4sf_v4sf
9717 = build_function_type_list (integer_type_node,
9718 integer_type_node, V4SF_type_node,
9719 V4SF_type_node, NULL_TREE);
9720 tree v4si_ftype_v4si
9721 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
9722 tree v8hi_ftype_v8hi
9723 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
9724 tree v16qi_ftype_v16qi
9725 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
9726 tree v4sf_ftype_v4sf
9727 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9728 tree void_ftype_pcvoid_int_int
9729 = build_function_type_list (void_type_node,
9730 pcvoid_type_node, integer_type_node,
9731 integer_type_node, NULL_TREE);
9733 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
9734 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
9735 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
9736 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
9737 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
9738 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
9739 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
9740 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
9741 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
9742 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
9743 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
9744 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
9745 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
9746 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
9747 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9748 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9749 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9750 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9751 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9752 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9753 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9754 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9755 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9756 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9757 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9758 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9759 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9760 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9761 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9762 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9763 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9764 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9765 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9766 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9767 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9768 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9769 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9770 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9771 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9772 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9773 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9774 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9775 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9776 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9777 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9778 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9780 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9782 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9783 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9784 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9785 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9786 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9787 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9788 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9789 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9790 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9791 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9793 /* Add the DST variants. */
9795 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9796 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9798 /* Initialize the predicates. */
9799 dp = bdesc_altivec_preds;
9800 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9802 enum machine_mode mode1;
9804 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9805 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9810 mode1 = insn_data[dp->icode].operand[1].mode;
9815 type = int_ftype_int_opaque_opaque;
9818 type = int_ftype_int_v4si_v4si;
9821 type = int_ftype_int_v8hi_v8hi;
9824 type = int_ftype_int_v16qi_v16qi;
9827 type = int_ftype_int_v4sf_v4sf;
9833 def_builtin (dp->mask, dp->name, type, dp->code);
9836 /* Initialize the abs* operators. */
9838 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9840 enum machine_mode mode0;
9843 mode0 = insn_data[d->icode].operand[0].mode;
9848 type = v4si_ftype_v4si;
9851 type = v8hi_ftype_v8hi;
9854 type = v16qi_ftype_v16qi;
9857 type = v4sf_ftype_v4sf;
9863 def_builtin (d->mask, d->name, type, d->code);
9870 /* Initialize target builtin that implements
9871 targetm.vectorize.builtin_mask_for_load. */
9873 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9874 v16qi_ftype_long_pcvoid,
9875 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9876 BUILT_IN_MD, NULL, NULL_TREE);
9877 TREE_READONLY (decl) = 1;
9878 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9879 altivec_builtin_mask_for_load = decl;
9882 /* Access to the vec_init patterns. */
9883 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9884 integer_type_node, integer_type_node,
9885 integer_type_node, NULL_TREE);
9886 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9887 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9889 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9890 short_integer_type_node,
9891 short_integer_type_node,
9892 short_integer_type_node,
9893 short_integer_type_node,
9894 short_integer_type_node,
9895 short_integer_type_node,
9896 short_integer_type_node, NULL_TREE);
9897 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9898 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9900 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9901 char_type_node, char_type_node,
9902 char_type_node, char_type_node,
9903 char_type_node, char_type_node,
9904 char_type_node, char_type_node,
9905 char_type_node, char_type_node,
9906 char_type_node, char_type_node,
9907 char_type_node, char_type_node,
9908 char_type_node, NULL_TREE);
9909 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9910 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9912 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9913 float_type_node, float_type_node,
9914 float_type_node, NULL_TREE);
9915 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9916 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9918 /* Access to the vec_set patterns. */
9919 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9921 integer_type_node, NULL_TREE);
9922 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9923 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9925 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9927 integer_type_node, NULL_TREE);
9928 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9929 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9931 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9933 integer_type_node, NULL_TREE);
9934 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9935 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9937 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9939 integer_type_node, NULL_TREE);
9940 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9941 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9943 /* Access to the vec_extract patterns. */
9944 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9945 integer_type_node, NULL_TREE);
9946 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9947 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9949 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9950 integer_type_node, NULL_TREE);
9951 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9952 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9954 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9955 integer_type_node, NULL_TREE);
9956 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9957 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9959 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9960 integer_type_node, NULL_TREE);
9961 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9962 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9966 rs6000_common_init_builtins (void)
9968 const struct builtin_description *d;
9971 tree v2sf_ftype_v2sf_v2sf_v2sf
9972 = build_function_type_list (V2SF_type_node,
9973 V2SF_type_node, V2SF_type_node,
9974 V2SF_type_node, NULL_TREE);
9976 tree v4sf_ftype_v4sf_v4sf_v16qi
9977 = build_function_type_list (V4SF_type_node,
9978 V4SF_type_node, V4SF_type_node,
9979 V16QI_type_node, NULL_TREE);
9980 tree v4si_ftype_v4si_v4si_v16qi
9981 = build_function_type_list (V4SI_type_node,
9982 V4SI_type_node, V4SI_type_node,
9983 V16QI_type_node, NULL_TREE);
9984 tree v8hi_ftype_v8hi_v8hi_v16qi
9985 = build_function_type_list (V8HI_type_node,
9986 V8HI_type_node, V8HI_type_node,
9987 V16QI_type_node, NULL_TREE);
9988 tree v16qi_ftype_v16qi_v16qi_v16qi
9989 = build_function_type_list (V16QI_type_node,
9990 V16QI_type_node, V16QI_type_node,
9991 V16QI_type_node, NULL_TREE);
9993 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9995 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9996 tree v16qi_ftype_int
9997 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9998 tree v8hi_ftype_v16qi
9999 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
10000 tree v4sf_ftype_v4sf
10001 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
10003 tree v2si_ftype_v2si_v2si
10004 = build_function_type_list (opaque_V2SI_type_node,
10005 opaque_V2SI_type_node,
10006 opaque_V2SI_type_node, NULL_TREE);
10008 tree v2sf_ftype_v2sf_v2sf_spe
10009 = build_function_type_list (opaque_V2SF_type_node,
10010 opaque_V2SF_type_node,
10011 opaque_V2SF_type_node, NULL_TREE);
10013 tree v2sf_ftype_v2sf_v2sf
10014 = build_function_type_list (V2SF_type_node,
10016 V2SF_type_node, NULL_TREE);
10019 tree v2si_ftype_int_int
10020 = build_function_type_list (opaque_V2SI_type_node,
10021 integer_type_node, integer_type_node,
10024 tree opaque_ftype_opaque
10025 = build_function_type_list (opaque_V4SI_type_node,
10026 opaque_V4SI_type_node, NULL_TREE);
10028 tree v2si_ftype_v2si
10029 = build_function_type_list (opaque_V2SI_type_node,
10030 opaque_V2SI_type_node, NULL_TREE);
10032 tree v2sf_ftype_v2sf_spe
10033 = build_function_type_list (opaque_V2SF_type_node,
10034 opaque_V2SF_type_node, NULL_TREE);
10036 tree v2sf_ftype_v2sf
10037 = build_function_type_list (V2SF_type_node,
10038 V2SF_type_node, NULL_TREE);
10040 tree v2sf_ftype_v2si
10041 = build_function_type_list (opaque_V2SF_type_node,
10042 opaque_V2SI_type_node, NULL_TREE);
10044 tree v2si_ftype_v2sf
10045 = build_function_type_list (opaque_V2SI_type_node,
10046 opaque_V2SF_type_node, NULL_TREE);
10048 tree v2si_ftype_v2si_char
10049 = build_function_type_list (opaque_V2SI_type_node,
10050 opaque_V2SI_type_node,
10051 char_type_node, NULL_TREE);
10053 tree v2si_ftype_int_char
10054 = build_function_type_list (opaque_V2SI_type_node,
10055 integer_type_node, char_type_node, NULL_TREE);
10057 tree v2si_ftype_char
10058 = build_function_type_list (opaque_V2SI_type_node,
10059 char_type_node, NULL_TREE);
10061 tree int_ftype_int_int
10062 = build_function_type_list (integer_type_node,
10063 integer_type_node, integer_type_node,
10066 tree opaque_ftype_opaque_opaque
10067 = build_function_type_list (opaque_V4SI_type_node,
10068 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
10069 tree v4si_ftype_v4si_v4si
10070 = build_function_type_list (V4SI_type_node,
10071 V4SI_type_node, V4SI_type_node, NULL_TREE);
10072 tree v4sf_ftype_v4si_int
10073 = build_function_type_list (V4SF_type_node,
10074 V4SI_type_node, integer_type_node, NULL_TREE);
10075 tree v4si_ftype_v4sf_int
10076 = build_function_type_list (V4SI_type_node,
10077 V4SF_type_node, integer_type_node, NULL_TREE);
10078 tree v4si_ftype_v4si_int
10079 = build_function_type_list (V4SI_type_node,
10080 V4SI_type_node, integer_type_node, NULL_TREE);
10081 tree v8hi_ftype_v8hi_int
10082 = build_function_type_list (V8HI_type_node,
10083 V8HI_type_node, integer_type_node, NULL_TREE);
10084 tree v16qi_ftype_v16qi_int
10085 = build_function_type_list (V16QI_type_node,
10086 V16QI_type_node, integer_type_node, NULL_TREE);
10087 tree v16qi_ftype_v16qi_v16qi_int
10088 = build_function_type_list (V16QI_type_node,
10089 V16QI_type_node, V16QI_type_node,
10090 integer_type_node, NULL_TREE);
10091 tree v8hi_ftype_v8hi_v8hi_int
10092 = build_function_type_list (V8HI_type_node,
10093 V8HI_type_node, V8HI_type_node,
10094 integer_type_node, NULL_TREE);
10095 tree v4si_ftype_v4si_v4si_int
10096 = build_function_type_list (V4SI_type_node,
10097 V4SI_type_node, V4SI_type_node,
10098 integer_type_node, NULL_TREE);
10099 tree v4sf_ftype_v4sf_v4sf_int
10100 = build_function_type_list (V4SF_type_node,
10101 V4SF_type_node, V4SF_type_node,
10102 integer_type_node, NULL_TREE);
10103 tree v4sf_ftype_v4sf_v4sf
10104 = build_function_type_list (V4SF_type_node,
10105 V4SF_type_node, V4SF_type_node, NULL_TREE);
10106 tree opaque_ftype_opaque_opaque_opaque
10107 = build_function_type_list (opaque_V4SI_type_node,
10108 opaque_V4SI_type_node, opaque_V4SI_type_node,
10109 opaque_V4SI_type_node, NULL_TREE);
10110 tree v4sf_ftype_v4sf_v4sf_v4si
10111 = build_function_type_list (V4SF_type_node,
10112 V4SF_type_node, V4SF_type_node,
10113 V4SI_type_node, NULL_TREE);
10114 tree v4sf_ftype_v4sf_v4sf_v4sf
10115 = build_function_type_list (V4SF_type_node,
10116 V4SF_type_node, V4SF_type_node,
10117 V4SF_type_node, NULL_TREE);
10118 tree v4si_ftype_v4si_v4si_v4si
10119 = build_function_type_list (V4SI_type_node,
10120 V4SI_type_node, V4SI_type_node,
10121 V4SI_type_node, NULL_TREE);
10122 tree v8hi_ftype_v8hi_v8hi
10123 = build_function_type_list (V8HI_type_node,
10124 V8HI_type_node, V8HI_type_node, NULL_TREE);
10125 tree v8hi_ftype_v8hi_v8hi_v8hi
10126 = build_function_type_list (V8HI_type_node,
10127 V8HI_type_node, V8HI_type_node,
10128 V8HI_type_node, NULL_TREE);
10129 tree v4si_ftype_v8hi_v8hi_v4si
10130 = build_function_type_list (V4SI_type_node,
10131 V8HI_type_node, V8HI_type_node,
10132 V4SI_type_node, NULL_TREE);
10133 tree v4si_ftype_v16qi_v16qi_v4si
10134 = build_function_type_list (V4SI_type_node,
10135 V16QI_type_node, V16QI_type_node,
10136 V4SI_type_node, NULL_TREE);
10137 tree v16qi_ftype_v16qi_v16qi
10138 = build_function_type_list (V16QI_type_node,
10139 V16QI_type_node, V16QI_type_node, NULL_TREE);
10140 tree v4si_ftype_v4sf_v4sf
10141 = build_function_type_list (V4SI_type_node,
10142 V4SF_type_node, V4SF_type_node, NULL_TREE);
10143 tree v8hi_ftype_v16qi_v16qi
10144 = build_function_type_list (V8HI_type_node,
10145 V16QI_type_node, V16QI_type_node, NULL_TREE);
10146 tree v4si_ftype_v8hi_v8hi
10147 = build_function_type_list (V4SI_type_node,
10148 V8HI_type_node, V8HI_type_node, NULL_TREE);
10149 tree v8hi_ftype_v4si_v4si
10150 = build_function_type_list (V8HI_type_node,
10151 V4SI_type_node, V4SI_type_node, NULL_TREE);
10152 tree v16qi_ftype_v8hi_v8hi
10153 = build_function_type_list (V16QI_type_node,
10154 V8HI_type_node, V8HI_type_node, NULL_TREE);
10155 tree v4si_ftype_v16qi_v4si
10156 = build_function_type_list (V4SI_type_node,
10157 V16QI_type_node, V4SI_type_node, NULL_TREE);
10158 tree v4si_ftype_v16qi_v16qi
10159 = build_function_type_list (V4SI_type_node,
10160 V16QI_type_node, V16QI_type_node, NULL_TREE);
10161 tree v4si_ftype_v8hi_v4si
10162 = build_function_type_list (V4SI_type_node,
10163 V8HI_type_node, V4SI_type_node, NULL_TREE);
10164 tree v4si_ftype_v8hi
10165 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
10166 tree int_ftype_v4si_v4si
10167 = build_function_type_list (integer_type_node,
10168 V4SI_type_node, V4SI_type_node, NULL_TREE);
10169 tree int_ftype_v4sf_v4sf
10170 = build_function_type_list (integer_type_node,
10171 V4SF_type_node, V4SF_type_node, NULL_TREE);
10172 tree int_ftype_v16qi_v16qi
10173 = build_function_type_list (integer_type_node,
10174 V16QI_type_node, V16QI_type_node, NULL_TREE);
10175 tree int_ftype_v8hi_v8hi
10176 = build_function_type_list (integer_type_node,
10177 V8HI_type_node, V8HI_type_node, NULL_TREE);
10179 /* Add the simple ternary operators. */
10181 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
10183 enum machine_mode mode0, mode1, mode2, mode3;
10185 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10186 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10197 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10200 mode0 = insn_data[d->icode].operand[0].mode;
10201 mode1 = insn_data[d->icode].operand[1].mode;
10202 mode2 = insn_data[d->icode].operand[2].mode;
10203 mode3 = insn_data[d->icode].operand[3].mode;
10206 /* When all four are of the same mode. */
10207 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
10212 type = opaque_ftype_opaque_opaque_opaque;
10215 type = v4si_ftype_v4si_v4si_v4si;
10218 type = v4sf_ftype_v4sf_v4sf_v4sf;
10221 type = v8hi_ftype_v8hi_v8hi_v8hi;
10224 type = v16qi_ftype_v16qi_v16qi_v16qi;
10227 type = v2sf_ftype_v2sf_v2sf_v2sf;
10230 gcc_unreachable ();
10233 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
10238 type = v4si_ftype_v4si_v4si_v16qi;
10241 type = v4sf_ftype_v4sf_v4sf_v16qi;
10244 type = v8hi_ftype_v8hi_v8hi_v16qi;
10247 type = v16qi_ftype_v16qi_v16qi_v16qi;
10250 gcc_unreachable ();
10253 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
10254 && mode3 == V4SImode)
10255 type = v4si_ftype_v16qi_v16qi_v4si;
10256 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
10257 && mode3 == V4SImode)
10258 type = v4si_ftype_v8hi_v8hi_v4si;
10259 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
10260 && mode3 == V4SImode)
10261 type = v4sf_ftype_v4sf_v4sf_v4si;
10263 /* vchar, vchar, vchar, 4-bit literal. */
10264 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
10265 && mode3 == QImode)
10266 type = v16qi_ftype_v16qi_v16qi_int;
10268 /* vshort, vshort, vshort, 4-bit literal. */
10269 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
10270 && mode3 == QImode)
10271 type = v8hi_ftype_v8hi_v8hi_int;
10273 /* vint, vint, vint, 4-bit literal. */
10274 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
10275 && mode3 == QImode)
10276 type = v4si_ftype_v4si_v4si_int;
10278 /* vfloat, vfloat, vfloat, 4-bit literal. */
10279 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
10280 && mode3 == QImode)
10281 type = v4sf_ftype_v4sf_v4sf_int;
10284 gcc_unreachable ();
10286 def_builtin (d->mask, d->name, type, d->code);
10289 /* Add the simple binary operators. */
10290 d = (struct builtin_description *) bdesc_2arg;
10291 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10293 enum machine_mode mode0, mode1, mode2;
10295 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10296 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10306 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10309 mode0 = insn_data[d->icode].operand[0].mode;
10310 mode1 = insn_data[d->icode].operand[1].mode;
10311 mode2 = insn_data[d->icode].operand[2].mode;
10314 /* When all three operands are of the same mode. */
10315 if (mode0 == mode1 && mode1 == mode2)
10320 type = opaque_ftype_opaque_opaque;
10323 type = v4sf_ftype_v4sf_v4sf;
10326 type = v4si_ftype_v4si_v4si;
10329 type = v16qi_ftype_v16qi_v16qi;
10332 type = v8hi_ftype_v8hi_v8hi;
10335 type = v2si_ftype_v2si_v2si;
10338 if (TARGET_PAIRED_FLOAT)
10339 type = v2sf_ftype_v2sf_v2sf;
10341 type = v2sf_ftype_v2sf_v2sf_spe;
10344 type = int_ftype_int_int;
10347 gcc_unreachable ();
10351 /* A few other combos we really don't want to do manually. */
10353 /* vint, vfloat, vfloat. */
10354 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
10355 type = v4si_ftype_v4sf_v4sf;
10357 /* vshort, vchar, vchar. */
10358 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
10359 type = v8hi_ftype_v16qi_v16qi;
10361 /* vint, vshort, vshort. */
10362 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
10363 type = v4si_ftype_v8hi_v8hi;
10365 /* vshort, vint, vint. */
10366 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
10367 type = v8hi_ftype_v4si_v4si;
10369 /* vchar, vshort, vshort. */
10370 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
10371 type = v16qi_ftype_v8hi_v8hi;
10373 /* vint, vchar, vint. */
10374 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
10375 type = v4si_ftype_v16qi_v4si;
10377 /* vint, vchar, vchar. */
10378 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
10379 type = v4si_ftype_v16qi_v16qi;
10381 /* vint, vshort, vint. */
10382 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
10383 type = v4si_ftype_v8hi_v4si;
10385 /* vint, vint, 5-bit literal. */
10386 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
10387 type = v4si_ftype_v4si_int;
10389 /* vshort, vshort, 5-bit literal. */
10390 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
10391 type = v8hi_ftype_v8hi_int;
10393 /* vchar, vchar, 5-bit literal. */
10394 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
10395 type = v16qi_ftype_v16qi_int;
10397 /* vfloat, vint, 5-bit literal. */
10398 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
10399 type = v4sf_ftype_v4si_int;
10401 /* vint, vfloat, 5-bit literal. */
10402 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
10403 type = v4si_ftype_v4sf_int;
10405 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
10406 type = v2si_ftype_int_int;
10408 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
10409 type = v2si_ftype_v2si_char;
10411 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
10412 type = v2si_ftype_int_char;
10417 gcc_assert (mode0 == SImode);
10421 type = int_ftype_v4si_v4si;
10424 type = int_ftype_v4sf_v4sf;
10427 type = int_ftype_v16qi_v16qi;
10430 type = int_ftype_v8hi_v8hi;
10433 gcc_unreachable ();
10437 def_builtin (d->mask, d->name, type, d->code);
10440 /* Add the simple unary operators. */
10441 d = (struct builtin_description *) bdesc_1arg;
10442 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10444 enum machine_mode mode0, mode1;
10446 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10447 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10456 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10459 mode0 = insn_data[d->icode].operand[0].mode;
10460 mode1 = insn_data[d->icode].operand[1].mode;
10463 if (mode0 == V4SImode && mode1 == QImode)
10464 type = v4si_ftype_int;
10465 else if (mode0 == V8HImode && mode1 == QImode)
10466 type = v8hi_ftype_int;
10467 else if (mode0 == V16QImode && mode1 == QImode)
10468 type = v16qi_ftype_int;
10469 else if (mode0 == VOIDmode && mode1 == VOIDmode)
10470 type = opaque_ftype_opaque;
10471 else if (mode0 == V4SFmode && mode1 == V4SFmode)
10472 type = v4sf_ftype_v4sf;
10473 else if (mode0 == V8HImode && mode1 == V16QImode)
10474 type = v8hi_ftype_v16qi;
10475 else if (mode0 == V4SImode && mode1 == V8HImode)
10476 type = v4si_ftype_v8hi;
10477 else if (mode0 == V2SImode && mode1 == V2SImode)
10478 type = v2si_ftype_v2si;
10479 else if (mode0 == V2SFmode && mode1 == V2SFmode)
10481 if (TARGET_PAIRED_FLOAT)
10482 type = v2sf_ftype_v2sf;
10484 type = v2sf_ftype_v2sf_spe;
10486 else if (mode0 == V2SFmode && mode1 == V2SImode)
10487 type = v2sf_ftype_v2si;
10488 else if (mode0 == V2SImode && mode1 == V2SFmode)
10489 type = v2si_ftype_v2sf;
10490 else if (mode0 == V2SImode && mode1 == QImode)
10491 type = v2si_ftype_char;
10493 gcc_unreachable ();
10495 def_builtin (d->mask, d->name, type, d->code);
10500 rs6000_init_libfuncs (void)
10502 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
10503 && !TARGET_POWER2 && !TARGET_POWERPC)
10505 /* AIX library routines for float->int conversion. */
10506 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
10507 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
10508 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
10509 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
10512 if (!TARGET_IEEEQUAD)
10513 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10514 if (!TARGET_XL_COMPAT)
10516 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
10517 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
10518 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
10519 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
10521 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
10523 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
10524 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
10525 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
10526 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
10527 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
10528 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
10529 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
10531 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
10532 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
10533 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
10534 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
10535 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
10536 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
10537 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
10538 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
10541 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
10542 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
10546 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
10547 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
10548 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
10549 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
10553 /* 32-bit SVR4 quad floating point routines. */
10555 set_optab_libfunc (add_optab, TFmode, "_q_add");
10556 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
10557 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
10558 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
10559 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
10560 if (TARGET_PPC_GPOPT || TARGET_POWER2)
10561 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
10563 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
10564 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
10565 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
10566 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
10567 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
10568 set_optab_libfunc (le_optab, TFmode, "_q_fle");
10570 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
10571 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
10572 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
10573 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
10574 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
10575 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
10576 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
10577 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
10582 /* Expand a block clear operation, and return 1 if successful. Return 0
10583 if we should let the compiler generate normal code.
10585 operands[0] is the destination
10586 operands[1] is the length
10587 operands[3] is the alignment */
10590 expand_block_clear (rtx operands[])
10592 rtx orig_dest = operands[0];
10593 rtx bytes_rtx = operands[1];
10594 rtx align_rtx = operands[3];
10595 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
10596 HOST_WIDE_INT align;
10597 HOST_WIDE_INT bytes;
10602 /* If this is not a fixed size move, just call memcpy */
10606 /* This must be a fixed size alignment */
10607 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10608 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10610 /* Anything to clear? */
10611 bytes = INTVAL (bytes_rtx);
10615 /* Use the builtin memset after a point, to avoid huge code bloat.
10616 When optimize_size, avoid any significant code bloat; calling
10617 memset is about 4 instructions, so allow for one instruction to
10618 load zero and three to do clearing. */
10619 if (TARGET_ALTIVEC && align >= 128)
10621 else if (TARGET_POWERPC64 && align >= 32)
10623 else if (TARGET_SPE && align >= 64)
10628 if (optimize_size && bytes > 3 * clear_step)
10630 if (! optimize_size && bytes > 8 * clear_step)
10633 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
10635 enum machine_mode mode = BLKmode;
10638 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
10643 else if (bytes >= 8 && TARGET_SPE && align >= 64)
10648 else if (bytes >= 8 && TARGET_POWERPC64
10649 /* 64-bit loads and stores require word-aligned
10651 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10656 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10657 { /* move 4 bytes */
10661 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10662 { /* move 2 bytes */
10666 else /* move 1 byte at a time */
10672 dest = adjust_address (orig_dest, mode, offset);
10674 emit_move_insn (dest, CONST0_RTX (mode));
10681 /* Expand a block move operation, and return 1 if successful. Return 0
10682 if we should let the compiler generate normal code.
10684 operands[0] is the destination
10685 operands[1] is the source
10686 operands[2] is the length
10687 operands[3] is the alignment */
10689 #define MAX_MOVE_REG 4
10692 expand_block_move (rtx operands[])
10694 rtx orig_dest = operands[0];
10695 rtx orig_src = operands[1];
10696 rtx bytes_rtx = operands[2];
10697 rtx align_rtx = operands[3];
10698 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
10703 rtx stores[MAX_MOVE_REG];
10706 /* If this is not a fixed size move, just call memcpy */
10710 /* This must be a fixed size alignment */
10711 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10712 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10714 /* Anything to move? */
10715 bytes = INTVAL (bytes_rtx);
10719 /* store_one_arg depends on expand_block_move to handle at least the size of
10720 reg_parm_stack_space. */
10721 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
10724 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
10727 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
10728 rtx (*mov) (rtx, rtx);
10730 enum machine_mode mode = BLKmode;
10733 /* Altivec first, since it will be faster than a string move
10734 when it applies, and usually not significantly larger. */
10735 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
10739 gen_func.mov = gen_movv4si;
10741 else if (TARGET_SPE && bytes >= 8 && align >= 64)
10745 gen_func.mov = gen_movv2si;
10747 else if (TARGET_STRING
10748 && bytes > 24 /* move up to 32 bytes at a time */
10754 && ! fixed_regs[10]
10755 && ! fixed_regs[11]
10756 && ! fixed_regs[12])
10758 move_bytes = (bytes > 32) ? 32 : bytes;
10759 gen_func.movmemsi = gen_movmemsi_8reg;
10761 else if (TARGET_STRING
10762 && bytes > 16 /* move up to 24 bytes at a time */
10768 && ! fixed_regs[10])
10770 move_bytes = (bytes > 24) ? 24 : bytes;
10771 gen_func.movmemsi = gen_movmemsi_6reg;
10773 else if (TARGET_STRING
10774 && bytes > 8 /* move up to 16 bytes at a time */
10778 && ! fixed_regs[8])
10780 move_bytes = (bytes > 16) ? 16 : bytes;
10781 gen_func.movmemsi = gen_movmemsi_4reg;
10783 else if (bytes >= 8 && TARGET_POWERPC64
10784 /* 64-bit loads and stores require word-aligned
10786 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10790 gen_func.mov = gen_movdi;
10792 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10793 { /* move up to 8 bytes at a time */
10794 move_bytes = (bytes > 8) ? 8 : bytes;
10795 gen_func.movmemsi = gen_movmemsi_2reg;
10797 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10798 { /* move 4 bytes */
10801 gen_func.mov = gen_movsi;
10803 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10804 { /* move 2 bytes */
10807 gen_func.mov = gen_movhi;
10809 else if (TARGET_STRING && bytes > 1)
10810 { /* move up to 4 bytes at a time */
10811 move_bytes = (bytes > 4) ? 4 : bytes;
10812 gen_func.movmemsi = gen_movmemsi_1reg;
10814 else /* move 1 byte at a time */
10818 gen_func.mov = gen_movqi;
10821 src = adjust_address (orig_src, mode, offset);
10822 dest = adjust_address (orig_dest, mode, offset);
10824 if (mode != BLKmode)
10826 rtx tmp_reg = gen_reg_rtx (mode);
10828 emit_insn ((*gen_func.mov) (tmp_reg, src));
10829 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10832 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10835 for (i = 0; i < num_reg; i++)
10836 emit_insn (stores[i]);
10840 if (mode == BLKmode)
10842 /* Move the address into scratch registers. The movmemsi
10843 patterns require zero offset. */
10844 if (!REG_P (XEXP (src, 0)))
10846 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10847 src = replace_equiv_address (src, src_reg);
10849 set_mem_size (src, GEN_INT (move_bytes));
10851 if (!REG_P (XEXP (dest, 0)))
10853 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10854 dest = replace_equiv_address (dest, dest_reg);
10856 set_mem_size (dest, GEN_INT (move_bytes));
10858 emit_insn ((*gen_func.movmemsi) (dest, src,
10859 GEN_INT (move_bytes & 31),
10868 /* Return a string to perform a load_multiple operation.
10869 operands[0] is the vector.
10870 operands[1] is the source address.
10871 operands[2] is the first destination register. */
10874 rs6000_output_load_multiple (rtx operands[3])
10876 /* We have to handle the case where the pseudo used to contain the address
10877 is assigned to one of the output registers. */
10879 int words = XVECLEN (operands[0], 0);
10882 if (XVECLEN (operands[0], 0) == 1)
10883 return "{l|lwz} %2,0(%1)";
10885 for (i = 0; i < words; i++)
10886 if (refers_to_regno_p (REGNO (operands[2]) + i,
10887 REGNO (operands[2]) + i + 1, operands[1], 0))
10891 xop[0] = GEN_INT (4 * (words-1));
10892 xop[1] = operands[1];
10893 xop[2] = operands[2];
10894 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10899 xop[0] = GEN_INT (4 * (words-1));
10900 xop[1] = operands[1];
10901 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10902 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10907 for (j = 0; j < words; j++)
10910 xop[0] = GEN_INT (j * 4);
10911 xop[1] = operands[1];
10912 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10913 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10915 xop[0] = GEN_INT (i * 4);
10916 xop[1] = operands[1];
10917 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10922 return "{lsi|lswi} %2,%1,%N0";
10926 /* A validation routine: say whether CODE, a condition code, and MODE
10927 match. The other alternatives either don't make sense or should
10928 never be generated. */
10931 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10933 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10934 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10935 && GET_MODE_CLASS (mode) == MODE_CC);
10937 /* These don't make sense. */
10938 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10939 || mode != CCUNSmode);
10941 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10942 || mode == CCUNSmode);
10944 gcc_assert (mode == CCFPmode
10945 || (code != ORDERED && code != UNORDERED
10946 && code != UNEQ && code != LTGT
10947 && code != UNGT && code != UNLT
10948 && code != UNGE && code != UNLE));
10950 /* These should never be generated except for
10951 flag_finite_math_only. */
10952 gcc_assert (mode != CCFPmode
10953 || flag_finite_math_only
10954 || (code != LE && code != GE
10955 && code != UNEQ && code != LTGT
10956 && code != UNGT && code != UNLT));
10958 /* These are invalid; the information is not there. */
10959 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10963 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10964 mask required to convert the result of a rotate insn into a shift
10965 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10968 includes_lshift_p (rtx shiftop, rtx andop)
10970 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10972 shift_mask <<= INTVAL (shiftop);
10974 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10977 /* Similar, but for right shift. */
10980 includes_rshift_p (rtx shiftop, rtx andop)
10982 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10984 shift_mask >>= INTVAL (shiftop);
10986 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10989 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10990 to perform a left shift. It must have exactly SHIFTOP least
10991 significant 0's, then one or more 1's, then zero or more 0's. */
10994 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10996 if (GET_CODE (andop) == CONST_INT)
10998 HOST_WIDE_INT c, lsb, shift_mask;
11000 c = INTVAL (andop);
11001 if (c == 0 || c == ~0)
11005 shift_mask <<= INTVAL (shiftop);
11007 /* Find the least significant one bit. */
11010 /* It must coincide with the LSB of the shift mask. */
11011 if (-lsb != shift_mask)
11014 /* Invert to look for the next transition (if any). */
11017 /* Remove the low group of ones (originally low group of zeros). */
11020 /* Again find the lsb, and check we have all 1's above. */
11024 else if (GET_CODE (andop) == CONST_DOUBLE
11025 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
11027 HOST_WIDE_INT low, high, lsb;
11028 HOST_WIDE_INT shift_mask_low, shift_mask_high;
11030 low = CONST_DOUBLE_LOW (andop);
11031 if (HOST_BITS_PER_WIDE_INT < 64)
11032 high = CONST_DOUBLE_HIGH (andop);
11034 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
11035 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
11038 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
11040 shift_mask_high = ~0;
11041 if (INTVAL (shiftop) > 32)
11042 shift_mask_high <<= INTVAL (shiftop) - 32;
11044 lsb = high & -high;
11046 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
11052 lsb = high & -high;
11053 return high == -lsb;
11056 shift_mask_low = ~0;
11057 shift_mask_low <<= INTVAL (shiftop);
11061 if (-lsb != shift_mask_low)
11064 if (HOST_BITS_PER_WIDE_INT < 64)
11069 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
11071 lsb = high & -high;
11072 return high == -lsb;
11076 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
11082 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
11083 to perform a left shift. It must have SHIFTOP or more least
11084 significant 0's, with the remainder of the word 1's. */
11087 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
11089 if (GET_CODE (andop) == CONST_INT)
11091 HOST_WIDE_INT c, lsb, shift_mask;
11094 shift_mask <<= INTVAL (shiftop);
11095 c = INTVAL (andop);
11097 /* Find the least significant one bit. */
11100 /* It must be covered by the shift mask.
11101 This test also rejects c == 0. */
11102 if ((lsb & shift_mask) == 0)
11105 /* Check we have all 1's above the transition, and reject all 1's. */
11106 return c == -lsb && lsb != 1;
11108 else if (GET_CODE (andop) == CONST_DOUBLE
11109 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
11111 HOST_WIDE_INT low, lsb, shift_mask_low;
11113 low = CONST_DOUBLE_LOW (andop);
11115 if (HOST_BITS_PER_WIDE_INT < 64)
11117 HOST_WIDE_INT high, shift_mask_high;
11119 high = CONST_DOUBLE_HIGH (andop);
11123 shift_mask_high = ~0;
11124 if (INTVAL (shiftop) > 32)
11125 shift_mask_high <<= INTVAL (shiftop) - 32;
11127 lsb = high & -high;
11129 if ((lsb & shift_mask_high) == 0)
11132 return high == -lsb;
11138 shift_mask_low = ~0;
11139 shift_mask_low <<= INTVAL (shiftop);
11143 if ((lsb & shift_mask_low) == 0)
11146 return low == -lsb && lsb != 1;
11152 /* Return 1 if operands will generate a valid arguments to rlwimi
11153 instruction for insert with right shift in 64-bit mode. The mask may
11154 not start on the first bit or stop on the last bit because wrap-around
11155 effects of instruction do not correspond to semantics of RTL insn. */
11158 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
11160 if (INTVAL (startop) > 32
11161 && INTVAL (startop) < 64
11162 && INTVAL (sizeop) > 1
11163 && INTVAL (sizeop) + INTVAL (startop) < 64
11164 && INTVAL (shiftop) > 0
11165 && INTVAL (sizeop) + INTVAL (shiftop) < 32
11166 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
11172 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11173 for lfq and stfq insns iff the registers are hard registers. */
11176 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
11178 /* We might have been passed a SUBREG. */
11179 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
11182 /* We might have been passed non floating point registers. */
11183 if (!FP_REGNO_P (REGNO (reg1))
11184 || !FP_REGNO_P (REGNO (reg2)))
11187 return (REGNO (reg1) == REGNO (reg2) - 1);
11190 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11191 addr1 and addr2 must be in consecutive memory locations
11192 (addr2 == addr1 + 8). */
11195 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
11198 unsigned int reg1, reg2;
11199 int offset1, offset2;
11201 /* The mems cannot be volatile. */
11202 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
11205 addr1 = XEXP (mem1, 0);
11206 addr2 = XEXP (mem2, 0);
11208 /* Extract an offset (if used) from the first addr. */
11209 if (GET_CODE (addr1) == PLUS)
11211 /* If not a REG, return zero. */
11212 if (GET_CODE (XEXP (addr1, 0)) != REG)
11216 reg1 = REGNO (XEXP (addr1, 0));
11217 /* The offset must be constant! */
11218 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
11220 offset1 = INTVAL (XEXP (addr1, 1));
11223 else if (GET_CODE (addr1) != REG)
11227 reg1 = REGNO (addr1);
11228 /* This was a simple (mem (reg)) expression. Offset is 0. */
11232 /* And now for the second addr. */
11233 if (GET_CODE (addr2) == PLUS)
11235 /* If not a REG, return zero. */
11236 if (GET_CODE (XEXP (addr2, 0)) != REG)
11240 reg2 = REGNO (XEXP (addr2, 0));
11241 /* The offset must be constant. */
11242 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
11244 offset2 = INTVAL (XEXP (addr2, 1));
11247 else if (GET_CODE (addr2) != REG)
11251 reg2 = REGNO (addr2);
11252 /* This was a simple (mem (reg)) expression. Offset is 0. */
11256 /* Both of these must have the same base register. */
11260 /* The offset for the second addr must be 8 more than the first addr. */
11261 if (offset2 != offset1 + 8)
11264 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11271 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
11273 static bool eliminated = false;
11274 if (mode != SDmode)
11275 return assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
11278 rtx mem = cfun->machine->sdmode_stack_slot;
11279 gcc_assert (mem != NULL_RTX);
11283 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
11284 cfun->machine->sdmode_stack_slot = mem;
11292 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
11294 /* Don't walk into types. */
11295 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
11297 *walk_subtrees = 0;
11301 switch (TREE_CODE (*tp))
11309 case ALIGN_INDIRECT_REF:
11310 case MISALIGNED_INDIRECT_REF:
11311 case VIEW_CONVERT_EXPR:
11312 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
11323 /* Allocate a 64-bit stack slot to be used for copying SDmode
11324 values through if this function has any SDmode references. */
11327 rs6000_alloc_sdmode_stack_slot (void)
11331 gimple_stmt_iterator gsi;
11333 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
11336 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
11338 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
11341 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11342 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11348 /* Check for any SDmode parameters of the function. */
11349 for (t = DECL_ARGUMENTS (cfun->decl); t; t = TREE_CHAIN (t))
11351 if (TREE_TYPE (t) == error_mark_node)
11354 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
11355 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
11357 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11358 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11366 rs6000_instantiate_decls (void)
11368 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
11369 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
11372 /* Return the register class of a scratch register needed to copy IN into
11373 or out of a register in CLASS in MODE. If it can be done directly,
11374 NO_REGS is returned. */
11377 rs6000_secondary_reload_class (enum reg_class class,
11378 enum machine_mode mode ATTRIBUTE_UNUSED,
11383 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
11385 && MACHOPIC_INDIRECT
11389 /* We cannot copy a symbolic operand directly into anything
11390 other than BASE_REGS for TARGET_ELF. So indicate that a
11391 register from BASE_REGS is needed as an intermediate
11394 On Darwin, pic addresses require a load from memory, which
11395 needs a base register. */
11396 if (class != BASE_REGS
11397 && (GET_CODE (in) == SYMBOL_REF
11398 || GET_CODE (in) == HIGH
11399 || GET_CODE (in) == LABEL_REF
11400 || GET_CODE (in) == CONST))
11404 if (GET_CODE (in) == REG)
11406 regno = REGNO (in);
11407 if (regno >= FIRST_PSEUDO_REGISTER)
11409 regno = true_regnum (in);
11410 if (regno >= FIRST_PSEUDO_REGISTER)
11414 else if (GET_CODE (in) == SUBREG)
11416 regno = true_regnum (in);
11417 if (regno >= FIRST_PSEUDO_REGISTER)
11423 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11425 if (class == GENERAL_REGS || class == BASE_REGS
11426 || (regno >= 0 && INT_REGNO_P (regno)))
11429 /* Constants, memory, and FP registers can go into FP registers. */
11430 if ((regno == -1 || FP_REGNO_P (regno))
11431 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
11432 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
11434 /* Memory, and AltiVec registers can go into AltiVec registers. */
11435 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
11436 && class == ALTIVEC_REGS)
11439 /* We can copy among the CR registers. */
11440 if ((class == CR_REGS || class == CR0_REGS)
11441 && regno >= 0 && CR_REGNO_P (regno))
11444 /* Otherwise, we need GENERAL_REGS. */
11445 return GENERAL_REGS;
11448 /* Given a comparison operation, return the bit number in CCR to test. We
11449 know this is a valid comparison.
11451 SCC_P is 1 if this is for an scc. That means that %D will have been
11452 used instead of %C, so the bits will be in different places.
11454 Return -1 if OP isn't a valid comparison for some reason. */
11457 ccr_bit (rtx op, int scc_p)
11459 enum rtx_code code = GET_CODE (op);
11460 enum machine_mode cc_mode;
11465 if (!COMPARISON_P (op))
11468 reg = XEXP (op, 0);
11470 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
11472 cc_mode = GET_MODE (reg);
11473 cc_regnum = REGNO (reg);
11474 base_bit = 4 * (cc_regnum - CR0_REGNO);
11476 validate_condition_mode (code, cc_mode);
11478 /* When generating a sCOND operation, only positive conditions are
11481 || code == EQ || code == GT || code == LT || code == UNORDERED
11482 || code == GTU || code == LTU);
11487 return scc_p ? base_bit + 3 : base_bit + 2;
11489 return base_bit + 2;
11490 case GT: case GTU: case UNLE:
11491 return base_bit + 1;
11492 case LT: case LTU: case UNGE:
11494 case ORDERED: case UNORDERED:
11495 return base_bit + 3;
11498 /* If scc, we will have done a cror to put the bit in the
11499 unordered position. So test that bit. For integer, this is ! LT
11500 unless this is an scc insn. */
11501 return scc_p ? base_bit + 3 : base_bit;
11504 return scc_p ? base_bit + 3 : base_bit + 1;
11507 gcc_unreachable ();
11511 /* Return the GOT register. */
11514 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
11516 /* The second flow pass currently (June 1999) can't update
11517 regs_ever_live without disturbing other parts of the compiler, so
11518 update it here to make the prolog/epilogue code happy. */
11519 if (!can_create_pseudo_p ()
11520 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
11521 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
11523 crtl->uses_pic_offset_table = 1;
11525 return pic_offset_table_rtx;
11528 /* Function to init struct machine_function.
11529 This will be called, via a pointer variable,
11530 from push_function_context. */
11532 static struct machine_function *
11533 rs6000_init_machine_status (void)
11535 return GGC_CNEW (machine_function);
11538 /* These macros test for integers and extract the low-order bits. */
11540 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11541 && GET_MODE (X) == VOIDmode)
11543 #define INT_LOWPART(X) \
11544 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11547 extract_MB (rtx op)
11550 unsigned long val = INT_LOWPART (op);
11552 /* If the high bit is zero, the value is the first 1 bit we find
11554 if ((val & 0x80000000) == 0)
11556 gcc_assert (val & 0xffffffff);
11559 while (((val <<= 1) & 0x80000000) == 0)
11564 /* If the high bit is set and the low bit is not, or the mask is all
11565 1's, the value is zero. */
11566 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
11569 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11572 while (((val >>= 1) & 1) != 0)
11579 extract_ME (rtx op)
11582 unsigned long val = INT_LOWPART (op);
11584 /* If the low bit is zero, the value is the first 1 bit we find from
11586 if ((val & 1) == 0)
11588 gcc_assert (val & 0xffffffff);
11591 while (((val >>= 1) & 1) == 0)
11597 /* If the low bit is set and the high bit is not, or the mask is all
11598 1's, the value is 31. */
11599 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
11602 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11605 while (((val <<= 1) & 0x80000000) != 0)
11611 /* Locate some local-dynamic symbol still in use by this function
11612 so that we can print its name in some tls_ld pattern. */
11614 static const char *
11615 rs6000_get_some_local_dynamic_name (void)
11619 if (cfun->machine->some_ld_name)
11620 return cfun->machine->some_ld_name;
11622 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11624 && for_each_rtx (&PATTERN (insn),
11625 rs6000_get_some_local_dynamic_name_1, 0))
11626 return cfun->machine->some_ld_name;
11628 gcc_unreachable ();
11631 /* Helper function for rs6000_get_some_local_dynamic_name. */
11634 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11638 if (GET_CODE (x) == SYMBOL_REF)
11640 const char *str = XSTR (x, 0);
11641 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11643 cfun->machine->some_ld_name = str;
11651 /* Write out a function code label. */
11654 rs6000_output_function_entry (FILE *file, const char *fname)
11656 if (fname[0] != '.')
11658 switch (DEFAULT_ABI)
11661 gcc_unreachable ();
11667 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
11676 RS6000_OUTPUT_BASENAME (file, fname);
11678 assemble_name (file, fname);
11681 /* Print an operand. Recognize special options, documented below. */
11684 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11685 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11687 #define SMALL_DATA_RELOC "sda21"
11688 #define SMALL_DATA_REG 0
11692 print_operand (FILE *file, rtx x, int code)
11696 unsigned HOST_WIDE_INT uval;
11701 /* Write out an instruction after the call which may be replaced
11702 with glue code by the loader. This depends on the AIX version. */
11703 asm_fprintf (file, RS6000_CALL_GLUE);
11706 /* %a is output_address. */
11709 /* If X is a constant integer whose low-order 5 bits are zero,
11710 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11711 in the AIX assembler where "sri" with a zero shift count
11712 writes a trash instruction. */
11713 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
11720 /* If constant, low-order 16 bits of constant, unsigned.
11721 Otherwise, write normally. */
11723 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
11725 print_operand (file, x, 0);
11729 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11730 for 64-bit mask direction. */
11731 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
11734 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11738 /* X is a CR register. Print the number of the GT bit of the CR. */
11739 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11740 output_operand_lossage ("invalid %%E value");
11742 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
11746 /* Like 'J' but get to the GT bit only. */
11747 gcc_assert (GET_CODE (x) == REG);
11749 /* Bit 1 is GT bit. */
11750 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
11752 /* Add one for shift count in rlinm for scc. */
11753 fprintf (file, "%d", i + 1);
11757 /* X is a CR register. Print the number of the EQ bit of the CR */
11758 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11759 output_operand_lossage ("invalid %%E value");
11761 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
11765 /* X is a CR register. Print the shift count needed to move it
11766 to the high-order four bits. */
11767 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11768 output_operand_lossage ("invalid %%f value");
11770 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
11774 /* Similar, but print the count for the rotate in the opposite
11776 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11777 output_operand_lossage ("invalid %%F value");
11779 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
11783 /* X is a constant integer. If it is negative, print "m",
11784 otherwise print "z". This is to make an aze or ame insn. */
11785 if (GET_CODE (x) != CONST_INT)
11786 output_operand_lossage ("invalid %%G value");
11787 else if (INTVAL (x) >= 0)
11794 /* If constant, output low-order five bits. Otherwise, write
11797 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
11799 print_operand (file, x, 0);
11803 /* If constant, output low-order six bits. Otherwise, write
11806 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
11808 print_operand (file, x, 0);
11812 /* Print `i' if this is a constant, else nothing. */
11818 /* Write the bit number in CCR for jump. */
11819 i = ccr_bit (x, 0);
11821 output_operand_lossage ("invalid %%j code");
11823 fprintf (file, "%d", i);
11827 /* Similar, but add one for shift count in rlinm for scc and pass
11828 scc flag to `ccr_bit'. */
11829 i = ccr_bit (x, 1);
11831 output_operand_lossage ("invalid %%J code");
11833 /* If we want bit 31, write a shift count of zero, not 32. */
11834 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11838 /* X must be a constant. Write the 1's complement of the
11841 output_operand_lossage ("invalid %%k value");
11843 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
11847 /* X must be a symbolic constant on ELF. Write an
11848 expression suitable for an 'addi' that adds in the low 16
11849 bits of the MEM. */
11850 if (GET_CODE (x) != CONST)
11852 print_operand_address (file, x);
11853 fputs ("@l", file);
11857 if (GET_CODE (XEXP (x, 0)) != PLUS
11858 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
11859 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
11860 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
11861 output_operand_lossage ("invalid %%K value");
11862 print_operand_address (file, XEXP (XEXP (x, 0), 0));
11863 fputs ("@l", file);
11864 /* For GNU as, there must be a non-alphanumeric character
11865 between 'l' and the number. The '-' is added by
11866 print_operand() already. */
11867 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
11869 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
11873 /* %l is output_asm_label. */
11876 /* Write second word of DImode or DFmode reference. Works on register
11877 or non-indexed memory only. */
11878 if (GET_CODE (x) == REG)
11879 fputs (reg_names[REGNO (x) + 1], file);
11880 else if (GET_CODE (x) == MEM)
11882 /* Handle possible auto-increment. Since it is pre-increment and
11883 we have already done it, we can just use an offset of word. */
11884 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11885 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11886 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11888 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11889 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11892 output_address (XEXP (adjust_address_nv (x, SImode,
11896 if (small_data_operand (x, GET_MODE (x)))
11897 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11898 reg_names[SMALL_DATA_REG]);
11903 /* MB value for a mask operand. */
11904 if (! mask_operand (x, SImode))
11905 output_operand_lossage ("invalid %%m value");
11907 fprintf (file, "%d", extract_MB (x));
11911 /* ME value for a mask operand. */
11912 if (! mask_operand (x, SImode))
11913 output_operand_lossage ("invalid %%M value");
11915 fprintf (file, "%d", extract_ME (x));
11918 /* %n outputs the negative of its operand. */
11921 /* Write the number of elements in the vector times 4. */
11922 if (GET_CODE (x) != PARALLEL)
11923 output_operand_lossage ("invalid %%N value");
11925 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11929 /* Similar, but subtract 1 first. */
11930 if (GET_CODE (x) != PARALLEL)
11931 output_operand_lossage ("invalid %%O value");
11933 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11937 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11939 || INT_LOWPART (x) < 0
11940 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11941 output_operand_lossage ("invalid %%p value");
11943 fprintf (file, "%d", i);
11947 /* The operand must be an indirect memory reference. The result
11948 is the register name. */
11949 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11950 || REGNO (XEXP (x, 0)) >= 32)
11951 output_operand_lossage ("invalid %%P value");
11953 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11957 /* This outputs the logical code corresponding to a boolean
11958 expression. The expression may have one or both operands
11959 negated (if one, only the first one). For condition register
11960 logical operations, it will also treat the negated
11961 CR codes as NOTs, but not handle NOTs of them. */
11963 const char *const *t = 0;
11965 enum rtx_code code = GET_CODE (x);
11966 static const char * const tbl[3][3] = {
11967 { "and", "andc", "nor" },
11968 { "or", "orc", "nand" },
11969 { "xor", "eqv", "xor" } };
11973 else if (code == IOR)
11975 else if (code == XOR)
11978 output_operand_lossage ("invalid %%q value");
11980 if (GET_CODE (XEXP (x, 0)) != NOT)
11984 if (GET_CODE (XEXP (x, 1)) == NOT)
12002 /* X is a CR register. Print the mask for `mtcrf'. */
12003 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
12004 output_operand_lossage ("invalid %%R value");
12006 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
12010 /* Low 5 bits of 32 - value */
12012 output_operand_lossage ("invalid %%s value");
12014 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
12018 /* PowerPC64 mask position. All 0's is excluded.
12019 CONST_INT 32-bit mask is considered sign-extended so any
12020 transition must occur within the CONST_INT, not on the boundary. */
12021 if (! mask64_operand (x, DImode))
12022 output_operand_lossage ("invalid %%S value");
12024 uval = INT_LOWPART (x);
12026 if (uval & 1) /* Clear Left */
12028 #if HOST_BITS_PER_WIDE_INT > 64
12029 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
12033 else /* Clear Right */
12036 #if HOST_BITS_PER_WIDE_INT > 64
12037 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
12043 gcc_assert (i >= 0);
12044 fprintf (file, "%d", i);
12048 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
12049 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
12051 /* Bit 3 is OV bit. */
12052 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
12054 /* If we want bit 31, write a shift count of zero, not 32. */
12055 fprintf (file, "%d", i == 31 ? 0 : i + 1);
12059 /* Print the symbolic name of a branch target register. */
12060 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
12061 && REGNO (x) != CTR_REGNO))
12062 output_operand_lossage ("invalid %%T value");
12063 else if (REGNO (x) == LR_REGNO)
12064 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
12066 fputs ("ctr", file);
12070 /* High-order 16 bits of constant for use in unsigned operand. */
12072 output_operand_lossage ("invalid %%u value");
12074 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
12075 (INT_LOWPART (x) >> 16) & 0xffff);
12079 /* High-order 16 bits of constant for use in signed operand. */
12081 output_operand_lossage ("invalid %%v value");
12083 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
12084 (INT_LOWPART (x) >> 16) & 0xffff);
12088 /* Print `u' if this has an auto-increment or auto-decrement. */
12089 if (GET_CODE (x) == MEM
12090 && (GET_CODE (XEXP (x, 0)) == PRE_INC
12091 || GET_CODE (XEXP (x, 0)) == PRE_DEC
12092 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
12097 /* Print the trap code for this operand. */
12098 switch (GET_CODE (x))
12101 fputs ("eq", file); /* 4 */
12104 fputs ("ne", file); /* 24 */
12107 fputs ("lt", file); /* 16 */
12110 fputs ("le", file); /* 20 */
12113 fputs ("gt", file); /* 8 */
12116 fputs ("ge", file); /* 12 */
12119 fputs ("llt", file); /* 2 */
12122 fputs ("lle", file); /* 6 */
12125 fputs ("lgt", file); /* 1 */
12128 fputs ("lge", file); /* 5 */
12131 gcc_unreachable ();
12136 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12139 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
12140 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
12142 print_operand (file, x, 0);
12146 /* MB value for a PowerPC64 rldic operand. */
12147 val = (GET_CODE (x) == CONST_INT
12148 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
12153 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
12154 if ((val <<= 1) < 0)
12157 #if HOST_BITS_PER_WIDE_INT == 32
12158 if (GET_CODE (x) == CONST_INT && i >= 0)
12159 i += 32; /* zero-extend high-part was all 0's */
12160 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
12162 val = CONST_DOUBLE_LOW (x);
12168 for ( ; i < 64; i++)
12169 if ((val <<= 1) < 0)
12174 fprintf (file, "%d", i + 1);
12178 if (GET_CODE (x) == MEM
12179 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
12180 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
12181 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
12186 /* Like 'L', for third word of TImode */
12187 if (GET_CODE (x) == REG)
12188 fputs (reg_names[REGNO (x) + 2], file);
12189 else if (GET_CODE (x) == MEM)
12191 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12192 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12193 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12194 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12195 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12197 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
12198 if (small_data_operand (x, GET_MODE (x)))
12199 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12200 reg_names[SMALL_DATA_REG]);
12205 /* X is a SYMBOL_REF. Write out the name preceded by a
12206 period and without any trailing data in brackets. Used for function
12207 names. If we are configured for System V (or the embedded ABI) on
12208 the PowerPC, do not emit the period, since those systems do not use
12209 TOCs and the like. */
12210 gcc_assert (GET_CODE (x) == SYMBOL_REF);
12212 /* Mark the decl as referenced so that cgraph will output the
12214 if (SYMBOL_REF_DECL (x))
12215 mark_decl_referenced (SYMBOL_REF_DECL (x));
12217 /* For macho, check to see if we need a stub. */
12220 const char *name = XSTR (x, 0);
12222 if (MACHOPIC_INDIRECT
12223 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
12224 name = machopic_indirection_name (x, /*stub_p=*/true);
12226 assemble_name (file, name);
12228 else if (!DOT_SYMBOLS)
12229 assemble_name (file, XSTR (x, 0));
12231 rs6000_output_function_entry (file, XSTR (x, 0));
12235 /* Like 'L', for last word of TImode. */
12236 if (GET_CODE (x) == REG)
12237 fputs (reg_names[REGNO (x) + 3], file);
12238 else if (GET_CODE (x) == MEM)
12240 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12241 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12242 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12243 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12244 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12246 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
12247 if (small_data_operand (x, GET_MODE (x)))
12248 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12249 reg_names[SMALL_DATA_REG]);
12253 /* Print AltiVec or SPE memory operand. */
12258 gcc_assert (GET_CODE (x) == MEM);
12262 /* Ugly hack because %y is overloaded. */
12263 if ((TARGET_SPE || TARGET_E500_DOUBLE)
12264 && (GET_MODE_SIZE (GET_MODE (x)) == 8
12265 || GET_MODE (x) == TFmode
12266 || GET_MODE (x) == TImode))
12268 /* Handle [reg]. */
12269 if (GET_CODE (tmp) == REG)
12271 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
12274 /* Handle [reg+UIMM]. */
12275 else if (GET_CODE (tmp) == PLUS &&
12276 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
12280 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
12282 x = INTVAL (XEXP (tmp, 1));
12283 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
12287 /* Fall through. Must be [reg+reg]. */
12290 && GET_CODE (tmp) == AND
12291 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
12292 && INTVAL (XEXP (tmp, 1)) == -16)
12293 tmp = XEXP (tmp, 0);
12294 if (GET_CODE (tmp) == REG)
12295 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
12298 if (!GET_CODE (tmp) == PLUS
12299 || !REG_P (XEXP (tmp, 0))
12300 || !REG_P (XEXP (tmp, 1)))
12302 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
12306 if (REGNO (XEXP (tmp, 0)) == 0)
12307 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
12308 reg_names[ REGNO (XEXP (tmp, 0)) ]);
12310 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
12311 reg_names[ REGNO (XEXP (tmp, 1)) ]);
12317 if (GET_CODE (x) == REG)
12318 fprintf (file, "%s", reg_names[REGNO (x)]);
12319 else if (GET_CODE (x) == MEM)
12321 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12322 know the width from the mode. */
12323 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
12324 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
12325 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12326 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
12327 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
12328 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12329 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12330 output_address (XEXP (XEXP (x, 0), 1));
12332 output_address (XEXP (x, 0));
12335 output_addr_const (file, x);
12339 assemble_name (file, rs6000_get_some_local_dynamic_name ());
12343 output_operand_lossage ("invalid %%xn code");
12347 /* Print the address of an operand. */
12350 print_operand_address (FILE *file, rtx x)
12352 if (GET_CODE (x) == REG)
12353 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
12354 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
12355 || GET_CODE (x) == LABEL_REF)
12357 output_addr_const (file, x);
12358 if (small_data_operand (x, GET_MODE (x)))
12359 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12360 reg_names[SMALL_DATA_REG]);
12362 gcc_assert (!TARGET_TOC);
12364 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
12366 gcc_assert (REG_P (XEXP (x, 0)));
12367 if (REGNO (XEXP (x, 0)) == 0)
12368 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
12369 reg_names[ REGNO (XEXP (x, 0)) ]);
12371 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
12372 reg_names[ REGNO (XEXP (x, 1)) ]);
12374 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
12375 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
12376 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
12378 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12379 && CONSTANT_P (XEXP (x, 1)))
12381 output_addr_const (file, XEXP (x, 1));
12382 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12386 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12387 && CONSTANT_P (XEXP (x, 1)))
12389 fprintf (file, "lo16(");
12390 output_addr_const (file, XEXP (x, 1));
12391 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12394 else if (legitimate_constant_pool_address_p (x))
12396 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
12398 rtx contains_minus = XEXP (x, 1);
12402 /* Find the (minus (sym) (toc)) buried in X, and temporarily
12403 turn it into (sym) for output_addr_const. */
12404 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
12405 contains_minus = XEXP (contains_minus, 0);
12407 minus = XEXP (contains_minus, 0);
12408 symref = XEXP (minus, 0);
12409 gcc_assert (GET_CODE (XEXP (minus, 1)) == SYMBOL_REF);
12410 XEXP (contains_minus, 0) = symref;
12415 name = XSTR (symref, 0);
12416 newname = XALLOCAVEC (char, strlen (name) + sizeof ("@toc"));
12417 strcpy (newname, name);
12418 strcat (newname, "@toc");
12419 XSTR (symref, 0) = newname;
12421 output_addr_const (file, XEXP (x, 1));
12423 XSTR (symref, 0) = name;
12424 XEXP (contains_minus, 0) = minus;
12427 output_addr_const (file, XEXP (x, 1));
12429 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
12432 gcc_unreachable ();
12435 /* Target hook for assembling integer objects. The PowerPC version has
12436 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12437 is defined. It also needs to handle DI-mode objects on 64-bit
12441 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
12443 #ifdef RELOCATABLE_NEEDS_FIXUP
12444 /* Special handling for SI values. */
12445 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
12447 static int recurse = 0;
12449 /* For -mrelocatable, we mark all addresses that need to be fixed up
12450 in the .fixup section. */
12451 if (TARGET_RELOCATABLE
12452 && in_section != toc_section
12453 && in_section != text_section
12454 && !unlikely_text_section_p (in_section)
12456 && GET_CODE (x) != CONST_INT
12457 && GET_CODE (x) != CONST_DOUBLE
12463 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
12465 ASM_OUTPUT_LABEL (asm_out_file, buf);
12466 fprintf (asm_out_file, "\t.long\t(");
12467 output_addr_const (asm_out_file, x);
12468 fprintf (asm_out_file, ")@fixup\n");
12469 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
12470 ASM_OUTPUT_ALIGN (asm_out_file, 2);
12471 fprintf (asm_out_file, "\t.long\t");
12472 assemble_name (asm_out_file, buf);
12473 fprintf (asm_out_file, "\n\t.previous\n");
12477 /* Remove initial .'s to turn a -mcall-aixdesc function
12478 address into the address of the descriptor, not the function
12480 else if (GET_CODE (x) == SYMBOL_REF
12481 && XSTR (x, 0)[0] == '.'
12482 && DEFAULT_ABI == ABI_AIX)
12484 const char *name = XSTR (x, 0);
12485 while (*name == '.')
12488 fprintf (asm_out_file, "\t.long\t%s\n", name);
12492 #endif /* RELOCATABLE_NEEDS_FIXUP */
12493 return default_assemble_integer (x, size, aligned_p);
12496 #ifdef HAVE_GAS_HIDDEN
12497 /* Emit an assembler directive to set symbol visibility for DECL to
12498 VISIBILITY_TYPE. */
12501 rs6000_assemble_visibility (tree decl, int vis)
12503 /* Functions need to have their entry point symbol visibility set as
12504 well as their descriptor symbol visibility. */
12505 if (DEFAULT_ABI == ABI_AIX
12507 && TREE_CODE (decl) == FUNCTION_DECL)
12509 static const char * const visibility_types[] = {
12510 NULL, "internal", "hidden", "protected"
12513 const char *name, *type;
12515 name = ((* targetm.strip_name_encoding)
12516 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
12517 type = visibility_types[vis];
12519 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
12520 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
12523 default_assemble_visibility (decl, vis);
12528 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
12530 /* Reversal of FP compares takes care -- an ordered compare
12531 becomes an unordered compare and vice versa. */
12532 if (mode == CCFPmode
12533 && (!flag_finite_math_only
12534 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
12535 || code == UNEQ || code == LTGT))
12536 return reverse_condition_maybe_unordered (code);
12538 return reverse_condition (code);
12541 /* Generate a compare for CODE. Return a brand-new rtx that
12542 represents the result of the compare. */
12545 rs6000_generate_compare (enum rtx_code code)
12547 enum machine_mode comp_mode;
12548 rtx compare_result;
12550 if (rs6000_compare_fp_p)
12551 comp_mode = CCFPmode;
12552 else if (code == GTU || code == LTU
12553 || code == GEU || code == LEU)
12554 comp_mode = CCUNSmode;
12555 else if ((code == EQ || code == NE)
12556 && GET_CODE (rs6000_compare_op0) == SUBREG
12557 && GET_CODE (rs6000_compare_op1) == SUBREG
12558 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
12559 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
12560 /* These are unsigned values, perhaps there will be a later
12561 ordering compare that can be shared with this one.
12562 Unfortunately we cannot detect the signedness of the operands
12563 for non-subregs. */
12564 comp_mode = CCUNSmode;
12566 comp_mode = CCmode;
12568 /* First, the compare. */
12569 compare_result = gen_reg_rtx (comp_mode);
12571 /* E500 FP compare instructions on the GPRs. Yuck! */
12572 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
12573 && rs6000_compare_fp_p)
12575 rtx cmp, or_result, compare_result2;
12576 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
12578 if (op_mode == VOIDmode)
12579 op_mode = GET_MODE (rs6000_compare_op1);
12581 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12582 This explains the following mess. */
12586 case EQ: case UNEQ: case NE: case LTGT:
12590 cmp = flag_unsafe_math_optimizations
12591 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
12592 rs6000_compare_op1)
12593 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
12594 rs6000_compare_op1);
12598 cmp = flag_unsafe_math_optimizations
12599 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
12600 rs6000_compare_op1)
12601 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
12602 rs6000_compare_op1);
12606 cmp = flag_unsafe_math_optimizations
12607 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
12608 rs6000_compare_op1)
12609 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
12610 rs6000_compare_op1);
12614 gcc_unreachable ();
12618 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
12622 cmp = flag_unsafe_math_optimizations
12623 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
12624 rs6000_compare_op1)
12625 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
12626 rs6000_compare_op1);
12630 cmp = flag_unsafe_math_optimizations
12631 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
12632 rs6000_compare_op1)
12633 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
12634 rs6000_compare_op1);
12638 cmp = flag_unsafe_math_optimizations
12639 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
12640 rs6000_compare_op1)
12641 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
12642 rs6000_compare_op1);
12646 gcc_unreachable ();
12650 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
12654 cmp = flag_unsafe_math_optimizations
12655 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
12656 rs6000_compare_op1)
12657 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
12658 rs6000_compare_op1);
12662 cmp = flag_unsafe_math_optimizations
12663 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
12664 rs6000_compare_op1)
12665 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
12666 rs6000_compare_op1);
12670 cmp = flag_unsafe_math_optimizations
12671 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
12672 rs6000_compare_op1)
12673 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
12674 rs6000_compare_op1);
12678 gcc_unreachable ();
12682 gcc_unreachable ();
12685 /* Synthesize LE and GE from LT/GT || EQ. */
12686 if (code == LE || code == GE || code == LEU || code == GEU)
12692 case LE: code = LT; break;
12693 case GE: code = GT; break;
12694 case LEU: code = LT; break;
12695 case GEU: code = GT; break;
12696 default: gcc_unreachable ();
12699 compare_result2 = gen_reg_rtx (CCFPmode);
12705 cmp = flag_unsafe_math_optimizations
12706 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
12707 rs6000_compare_op1)
12708 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
12709 rs6000_compare_op1);
12713 cmp = flag_unsafe_math_optimizations
12714 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
12715 rs6000_compare_op1)
12716 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
12717 rs6000_compare_op1);
12721 cmp = flag_unsafe_math_optimizations
12722 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
12723 rs6000_compare_op1)
12724 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
12725 rs6000_compare_op1);
12729 gcc_unreachable ();
12733 /* OR them together. */
12734 or_result = gen_reg_rtx (CCFPmode);
12735 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
12737 compare_result = or_result;
12742 if (code == NE || code == LTGT)
12752 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12753 CLOBBERs to match cmptf_internal2 pattern. */
12754 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
12755 && GET_MODE (rs6000_compare_op0) == TFmode
12756 && !TARGET_IEEEQUAD
12757 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
12758 emit_insn (gen_rtx_PARALLEL (VOIDmode,
12760 gen_rtx_SET (VOIDmode,
12762 gen_rtx_COMPARE (comp_mode,
12763 rs6000_compare_op0,
12764 rs6000_compare_op1)),
12765 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12766 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12767 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12768 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12769 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12770 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12771 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12772 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
12773 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
12774 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
12776 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
12777 comp_mode = CCEQmode;
12778 compare_result = gen_reg_rtx (CCEQmode);
12780 emit_insn (gen_stack_protect_testdi (compare_result,
12781 rs6000_compare_op0, op1));
12783 emit_insn (gen_stack_protect_testsi (compare_result,
12784 rs6000_compare_op0, op1));
12787 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
12788 gen_rtx_COMPARE (comp_mode,
12789 rs6000_compare_op0,
12790 rs6000_compare_op1)));
12793 /* Some kinds of FP comparisons need an OR operation;
12794 under flag_finite_math_only we don't bother. */
12795 if (rs6000_compare_fp_p
12796 && !flag_finite_math_only
12797 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
12798 && (code == LE || code == GE
12799 || code == UNEQ || code == LTGT
12800 || code == UNGT || code == UNLT))
12802 enum rtx_code or1, or2;
12803 rtx or1_rtx, or2_rtx, compare2_rtx;
12804 rtx or_result = gen_reg_rtx (CCEQmode);
12808 case LE: or1 = LT; or2 = EQ; break;
12809 case GE: or1 = GT; or2 = EQ; break;
12810 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
12811 case LTGT: or1 = LT; or2 = GT; break;
12812 case UNGT: or1 = UNORDERED; or2 = GT; break;
12813 case UNLT: or1 = UNORDERED; or2 = LT; break;
12814 default: gcc_unreachable ();
12816 validate_condition_mode (or1, comp_mode);
12817 validate_condition_mode (or2, comp_mode);
12818 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
12819 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
12820 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
12821 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
12823 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
12825 compare_result = or_result;
12829 validate_condition_mode (code, GET_MODE (compare_result));
12831 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
12835 /* Emit the RTL for an sCOND pattern. */
12838 rs6000_emit_sCOND (enum rtx_code code, rtx result)
12841 enum machine_mode op_mode;
12842 enum rtx_code cond_code;
12844 condition_rtx = rs6000_generate_compare (code);
12845 cond_code = GET_CODE (condition_rtx);
12847 if (rs6000_compare_fp_p
12848 && !TARGET_FPRS && TARGET_HARD_FLOAT)
12852 PUT_MODE (condition_rtx, SImode);
12853 t = XEXP (condition_rtx, 0);
12855 gcc_assert (cond_code == NE || cond_code == EQ);
12857 if (cond_code == NE)
12858 emit_insn (gen_e500_flip_gt_bit (t, t));
12860 emit_insn (gen_move_from_CR_gt_bit (result, t));
12864 if (cond_code == NE
12865 || cond_code == GE || cond_code == LE
12866 || cond_code == GEU || cond_code == LEU
12867 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
12869 rtx not_result = gen_reg_rtx (CCEQmode);
12870 rtx not_op, rev_cond_rtx;
12871 enum machine_mode cc_mode;
12873 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
12875 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
12876 SImode, XEXP (condition_rtx, 0), const0_rtx);
12877 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
12878 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
12879 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
12882 op_mode = GET_MODE (rs6000_compare_op0);
12883 if (op_mode == VOIDmode)
12884 op_mode = GET_MODE (rs6000_compare_op1);
12886 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
12888 PUT_MODE (condition_rtx, DImode);
12889 convert_move (result, condition_rtx, 0);
12893 PUT_MODE (condition_rtx, SImode);
12894 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12898 /* Emit a branch of kind CODE to location LOC. */
12901 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12903 rtx condition_rtx, loc_ref;
12905 condition_rtx = rs6000_generate_compare (code);
12906 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12907 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12908 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12909 loc_ref, pc_rtx)));
12912 /* Return the string to output a conditional branch to LABEL, which is
12913 the operand number of the label, or -1 if the branch is really a
12914 conditional return.
12916 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12917 condition code register and its mode specifies what kind of
12918 comparison we made.
12920 REVERSED is nonzero if we should reverse the sense of the comparison.
12922 INSN is the insn. */
12925 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12927 static char string[64];
12928 enum rtx_code code = GET_CODE (op);
12929 rtx cc_reg = XEXP (op, 0);
12930 enum machine_mode mode = GET_MODE (cc_reg);
12931 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12932 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12933 int really_reversed = reversed ^ need_longbranch;
12939 validate_condition_mode (code, mode);
12941 /* Work out which way this really branches. We could use
12942 reverse_condition_maybe_unordered here always but this
12943 makes the resulting assembler clearer. */
12944 if (really_reversed)
12946 /* Reversal of FP compares takes care -- an ordered compare
12947 becomes an unordered compare and vice versa. */
12948 if (mode == CCFPmode)
12949 code = reverse_condition_maybe_unordered (code);
12951 code = reverse_condition (code);
12954 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12956 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12961 /* Opposite of GT. */
12970 gcc_unreachable ();
12976 /* Not all of these are actually distinct opcodes, but
12977 we distinguish them for clarity of the resulting assembler. */
12978 case NE: case LTGT:
12979 ccode = "ne"; break;
12980 case EQ: case UNEQ:
12981 ccode = "eq"; break;
12983 ccode = "ge"; break;
12984 case GT: case GTU: case UNGT:
12985 ccode = "gt"; break;
12987 ccode = "le"; break;
12988 case LT: case LTU: case UNLT:
12989 ccode = "lt"; break;
12990 case UNORDERED: ccode = "un"; break;
12991 case ORDERED: ccode = "nu"; break;
12992 case UNGE: ccode = "nl"; break;
12993 case UNLE: ccode = "ng"; break;
12995 gcc_unreachable ();
12998 /* Maybe we have a guess as to how likely the branch is.
12999 The old mnemonics don't have a way to specify this information. */
13001 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
13002 if (note != NULL_RTX)
13004 /* PROB is the difference from 50%. */
13005 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
13007 /* Only hint for highly probable/improbable branches on newer
13008 cpus as static prediction overrides processor dynamic
13009 prediction. For older cpus we may as well always hint, but
13010 assume not taken for branches that are very close to 50% as a
13011 mispredicted taken branch is more expensive than a
13012 mispredicted not-taken branch. */
13013 if (rs6000_always_hint
13014 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
13015 && br_prob_note_reliable_p (note)))
13017 if (abs (prob) > REG_BR_PROB_BASE / 20
13018 && ((prob > 0) ^ need_longbranch))
13026 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
13028 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
13030 /* We need to escape any '%' characters in the reg_names string.
13031 Assume they'd only be the first character.... */
13032 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
13034 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
13038 /* If the branch distance was too far, we may have to use an
13039 unconditional branch to go the distance. */
13040 if (need_longbranch)
13041 s += sprintf (s, ",$+8\n\tb %s", label);
13043 s += sprintf (s, ",%s", label);
13049 /* Return the string to flip the GT bit on a CR. */
13051 output_e500_flip_gt_bit (rtx dst, rtx src)
13053 static char string[64];
13056 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
13057 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
13060 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
13061 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
13063 sprintf (string, "crnot %d,%d", a, b);
13067 /* Return insn index for the vector compare instruction for given CODE,
13068 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
13072 get_vec_cmp_insn (enum rtx_code code,
13073 enum machine_mode dest_mode,
13074 enum machine_mode op_mode)
13076 if (!TARGET_ALTIVEC)
13077 return INSN_NOT_AVAILABLE;
13082 if (dest_mode == V16QImode && op_mode == V16QImode)
13083 return UNSPEC_VCMPEQUB;
13084 if (dest_mode == V8HImode && op_mode == V8HImode)
13085 return UNSPEC_VCMPEQUH;
13086 if (dest_mode == V4SImode && op_mode == V4SImode)
13087 return UNSPEC_VCMPEQUW;
13088 if (dest_mode == V4SImode && op_mode == V4SFmode)
13089 return UNSPEC_VCMPEQFP;
13092 if (dest_mode == V4SImode && op_mode == V4SFmode)
13093 return UNSPEC_VCMPGEFP;
13095 if (dest_mode == V16QImode && op_mode == V16QImode)
13096 return UNSPEC_VCMPGTSB;
13097 if (dest_mode == V8HImode && op_mode == V8HImode)
13098 return UNSPEC_VCMPGTSH;
13099 if (dest_mode == V4SImode && op_mode == V4SImode)
13100 return UNSPEC_VCMPGTSW;
13101 if (dest_mode == V4SImode && op_mode == V4SFmode)
13102 return UNSPEC_VCMPGTFP;
13105 if (dest_mode == V16QImode && op_mode == V16QImode)
13106 return UNSPEC_VCMPGTUB;
13107 if (dest_mode == V8HImode && op_mode == V8HImode)
13108 return UNSPEC_VCMPGTUH;
13109 if (dest_mode == V4SImode && op_mode == V4SImode)
13110 return UNSPEC_VCMPGTUW;
13115 return INSN_NOT_AVAILABLE;
13118 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
13119 DMODE is expected destination mode. This is a recursive function. */
13122 rs6000_emit_vector_compare (enum rtx_code rcode,
13124 enum machine_mode dmode)
13128 enum machine_mode dest_mode;
13129 enum machine_mode op_mode = GET_MODE (op1);
13131 gcc_assert (TARGET_ALTIVEC);
13132 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
13134 /* Floating point vector compare instructions uses destination V4SImode.
13135 Move destination to appropriate mode later. */
13136 if (dmode == V4SFmode)
13137 dest_mode = V4SImode;
13141 mask = gen_reg_rtx (dest_mode);
13142 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13144 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
13146 bool swap_operands = false;
13147 bool try_again = false;
13152 swap_operands = true;
13157 swap_operands = true;
13165 /* Invert condition and try again.
13166 e.g., A != B becomes ~(A==B). */
13168 enum rtx_code rev_code;
13169 enum insn_code nor_code;
13172 rev_code = reverse_condition_maybe_unordered (rcode);
13173 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
13176 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
13177 gcc_assert (nor_code != CODE_FOR_nothing);
13178 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
13180 if (dmode != dest_mode)
13182 rtx temp = gen_reg_rtx (dest_mode);
13183 convert_move (temp, mask, 0);
13193 /* Try GT/GTU/LT/LTU OR EQ */
13196 enum insn_code ior_code;
13197 enum rtx_code new_code;
13218 gcc_unreachable ();
13221 c_rtx = rs6000_emit_vector_compare (new_code,
13222 op0, op1, dest_mode);
13223 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
13226 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
13227 gcc_assert (ior_code != CODE_FOR_nothing);
13228 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
13229 if (dmode != dest_mode)
13231 rtx temp = gen_reg_rtx (dest_mode);
13232 convert_move (temp, mask, 0);
13239 gcc_unreachable ();
13244 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13245 /* You only get two chances. */
13246 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
13258 emit_insn (gen_rtx_SET (VOIDmode, mask,
13259 gen_rtx_UNSPEC (dest_mode,
13260 gen_rtvec (2, op0, op1),
13262 if (dmode != dest_mode)
13264 rtx temp = gen_reg_rtx (dest_mode);
13265 convert_move (temp, mask, 0);
13271 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13272 valid insn doesn exist for given mode. */
13275 get_vsel_insn (enum machine_mode mode)
13280 return UNSPEC_VSEL4SI;
13283 return UNSPEC_VSEL4SF;
13286 return UNSPEC_VSEL8HI;
13289 return UNSPEC_VSEL16QI;
13292 return INSN_NOT_AVAILABLE;
13295 return INSN_NOT_AVAILABLE;
13298 /* Emit vector select insn where DEST is destination using
13299 operands OP1, OP2 and MASK. */
13302 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
13305 enum machine_mode dest_mode = GET_MODE (dest);
13306 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
13308 temp = gen_reg_rtx (dest_mode);
13310 /* For each vector element, select op1 when mask is 1 otherwise
13312 t = gen_rtx_SET (VOIDmode, temp,
13313 gen_rtx_UNSPEC (dest_mode,
13314 gen_rtvec (3, op2, op1, mask),
13317 emit_move_insn (dest, temp);
13321 /* Emit vector conditional expression.
13322 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13323 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13326 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
13327 rtx cond, rtx cc_op0, rtx cc_op1)
13329 enum machine_mode dest_mode = GET_MODE (dest);
13330 enum rtx_code rcode = GET_CODE (cond);
13333 if (!TARGET_ALTIVEC)
13336 /* Get the vector mask for the given relational operations. */
13337 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
13339 rs6000_emit_vector_select (dest, op1, op2, mask);
13344 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13345 operands of the last comparison is nonzero/true, FALSE_COND if it
13346 is zero/false. Return 0 if the hardware has no such operation. */
13349 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13351 enum rtx_code code = GET_CODE (op);
13352 rtx op0 = rs6000_compare_op0;
13353 rtx op1 = rs6000_compare_op1;
13354 REAL_VALUE_TYPE c1;
13355 enum machine_mode compare_mode = GET_MODE (op0);
13356 enum machine_mode result_mode = GET_MODE (dest);
13358 bool is_against_zero;
13360 /* These modes should always match. */
13361 if (GET_MODE (op1) != compare_mode
13362 /* In the isel case however, we can use a compare immediate, so
13363 op1 may be a small constant. */
13364 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
13366 if (GET_MODE (true_cond) != result_mode)
13368 if (GET_MODE (false_cond) != result_mode)
13371 /* First, work out if the hardware can do this at all, or
13372 if it's too slow.... */
13373 if (! rs6000_compare_fp_p)
13376 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
13379 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
13380 && SCALAR_FLOAT_MODE_P (compare_mode))
13383 is_against_zero = op1 == CONST0_RTX (compare_mode);
13385 /* A floating-point subtract might overflow, underflow, or produce
13386 an inexact result, thus changing the floating-point flags, so it
13387 can't be generated if we care about that. It's safe if one side
13388 of the construct is zero, since then no subtract will be
13390 if (SCALAR_FLOAT_MODE_P (compare_mode)
13391 && flag_trapping_math && ! is_against_zero)
13394 /* Eliminate half of the comparisons by switching operands, this
13395 makes the remaining code simpler. */
13396 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
13397 || code == LTGT || code == LT || code == UNLE)
13399 code = reverse_condition_maybe_unordered (code);
13401 true_cond = false_cond;
13405 /* UNEQ and LTGT take four instructions for a comparison with zero,
13406 it'll probably be faster to use a branch here too. */
13407 if (code == UNEQ && HONOR_NANS (compare_mode))
13410 if (GET_CODE (op1) == CONST_DOUBLE)
13411 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
13413 /* We're going to try to implement comparisons by performing
13414 a subtract, then comparing against zero. Unfortunately,
13415 Inf - Inf is NaN which is not zero, and so if we don't
13416 know that the operand is finite and the comparison
13417 would treat EQ different to UNORDERED, we can't do it. */
13418 if (HONOR_INFINITIES (compare_mode)
13419 && code != GT && code != UNGE
13420 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
13421 /* Constructs of the form (a OP b ? a : b) are safe. */
13422 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
13423 || (! rtx_equal_p (op0, true_cond)
13424 && ! rtx_equal_p (op1, true_cond))))
13427 /* At this point we know we can use fsel. */
13429 /* Reduce the comparison to a comparison against zero. */
13430 if (! is_against_zero)
13432 temp = gen_reg_rtx (compare_mode);
13433 emit_insn (gen_rtx_SET (VOIDmode, temp,
13434 gen_rtx_MINUS (compare_mode, op0, op1)));
13436 op1 = CONST0_RTX (compare_mode);
13439 /* If we don't care about NaNs we can reduce some of the comparisons
13440 down to faster ones. */
13441 if (! HONOR_NANS (compare_mode))
13447 true_cond = false_cond;
13460 /* Now, reduce everything down to a GE. */
13467 temp = gen_reg_rtx (compare_mode);
13468 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13473 temp = gen_reg_rtx (compare_mode);
13474 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
13479 temp = gen_reg_rtx (compare_mode);
13480 emit_insn (gen_rtx_SET (VOIDmode, temp,
13481 gen_rtx_NEG (compare_mode,
13482 gen_rtx_ABS (compare_mode, op0))));
13487 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13488 temp = gen_reg_rtx (result_mode);
13489 emit_insn (gen_rtx_SET (VOIDmode, temp,
13490 gen_rtx_IF_THEN_ELSE (result_mode,
13491 gen_rtx_GE (VOIDmode,
13493 true_cond, false_cond)));
13494 false_cond = true_cond;
13497 temp = gen_reg_rtx (compare_mode);
13498 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13503 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13504 temp = gen_reg_rtx (result_mode);
13505 emit_insn (gen_rtx_SET (VOIDmode, temp,
13506 gen_rtx_IF_THEN_ELSE (result_mode,
13507 gen_rtx_GE (VOIDmode,
13509 true_cond, false_cond)));
13510 true_cond = false_cond;
13513 temp = gen_reg_rtx (compare_mode);
13514 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13519 gcc_unreachable ();
13522 emit_insn (gen_rtx_SET (VOIDmode, dest,
13523 gen_rtx_IF_THEN_ELSE (result_mode,
13524 gen_rtx_GE (VOIDmode,
13526 true_cond, false_cond)));
13530 /* Same as above, but for ints (isel). */
13533 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13535 rtx condition_rtx, cr;
13537 /* All isel implementations thus far are 32-bits. */
13538 if (GET_MODE (rs6000_compare_op0) != SImode)
13541 /* We still have to do the compare, because isel doesn't do a
13542 compare, it just looks at the CRx bits set by a previous compare
13544 condition_rtx = rs6000_generate_compare (GET_CODE (op));
13545 cr = XEXP (condition_rtx, 0);
13547 if (GET_MODE (cr) == CCmode)
13548 emit_insn (gen_isel_signed (dest, condition_rtx,
13549 true_cond, false_cond, cr));
13551 emit_insn (gen_isel_unsigned (dest, condition_rtx,
13552 true_cond, false_cond, cr));
13558 output_isel (rtx *operands)
13560 enum rtx_code code;
13562 code = GET_CODE (operands[1]);
13563 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
13565 PUT_CODE (operands[1], reverse_condition (code));
13566 return "isel %0,%3,%2,%j1";
13569 return "isel %0,%2,%3,%j1";
13573 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
13575 enum machine_mode mode = GET_MODE (op0);
13579 if (code == SMAX || code == SMIN)
13584 if (code == SMAX || code == UMAX)
13585 target = emit_conditional_move (dest, c, op0, op1, mode,
13586 op0, op1, mode, 0);
13588 target = emit_conditional_move (dest, c, op0, op1, mode,
13589 op1, op0, mode, 0);
13590 gcc_assert (target);
13591 if (target != dest)
13592 emit_move_insn (dest, target);
13595 /* Emit instructions to perform a load-reserved/store-conditional operation.
13596 The operation performed is an atomic
13597 (set M (CODE:MODE M OP))
13598 If not NULL, BEFORE is atomically set to M before the operation, and
13599 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13600 If SYNC_P then a memory barrier is emitted before the operation.
13601 Either OP or M may be wrapped in a NOT operation. */
13604 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
13605 rtx m, rtx op, rtx before_param, rtx after_param,
13608 enum machine_mode used_mode;
13609 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
13612 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13613 rtx shift = NULL_RTX;
13616 emit_insn (gen_memory_barrier ());
13618 if (GET_CODE (m) == NOT)
13619 used_m = XEXP (m, 0);
13623 /* If this is smaller than SImode, we'll have to use SImode with
13625 if (mode == QImode || mode == HImode)
13629 if (MEM_ALIGN (used_m) >= 32)
13632 if (BYTES_BIG_ENDIAN)
13633 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
13635 shift = GEN_INT (ishift);
13636 used_m = change_address (used_m, SImode, 0);
13640 rtx addrSI, aligned_addr;
13641 int shift_mask = mode == QImode ? 0x18 : 0x10;
13643 addrSI = gen_lowpart_common (SImode,
13644 force_reg (Pmode, XEXP (used_m, 0)));
13645 addrSI = force_reg (SImode, addrSI);
13646 shift = gen_reg_rtx (SImode);
13648 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13649 GEN_INT (shift_mask)));
13650 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13652 aligned_addr = expand_binop (Pmode, and_optab,
13654 GEN_INT (-4), NULL_RTX,
13655 1, OPTAB_LIB_WIDEN);
13656 used_m = change_address (used_m, SImode, aligned_addr);
13657 set_mem_align (used_m, 32);
13659 /* It's safe to keep the old alias set of USED_M, because
13660 the operation is atomic and only affects the original
13662 if (GET_CODE (m) == NOT)
13663 m = gen_rtx_NOT (SImode, used_m);
13667 if (GET_CODE (op) == NOT)
13669 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
13670 oldop = gen_rtx_NOT (SImode, oldop);
13673 oldop = lowpart_subreg (SImode, op, mode);
13679 newop = expand_binop (SImode, and_optab,
13680 oldop, GEN_INT (imask), NULL_RTX,
13681 1, OPTAB_LIB_WIDEN);
13682 emit_insn (gen_ashlsi3 (newop, newop, shift));
13686 newop = expand_binop (SImode, ior_optab,
13687 oldop, GEN_INT (~imask), NULL_RTX,
13688 1, OPTAB_LIB_WIDEN);
13689 emit_insn (gen_rotlsi3 (newop, newop, shift));
13697 newop = expand_binop (SImode, and_optab,
13698 oldop, GEN_INT (imask), NULL_RTX,
13699 1, OPTAB_LIB_WIDEN);
13700 emit_insn (gen_ashlsi3 (newop, newop, shift));
13702 mask = gen_reg_rtx (SImode);
13703 emit_move_insn (mask, GEN_INT (imask));
13704 emit_insn (gen_ashlsi3 (mask, mask, shift));
13707 newop = gen_rtx_PLUS (SImode, m, newop);
13709 newop = gen_rtx_MINUS (SImode, m, newop);
13710 newop = gen_rtx_AND (SImode, newop, mask);
13711 newop = gen_rtx_IOR (SImode, newop,
13712 gen_rtx_AND (SImode,
13713 gen_rtx_NOT (SImode, mask),
13719 gcc_unreachable ();
13722 if (GET_CODE (m) == NOT)
13726 mask = gen_reg_rtx (SImode);
13727 emit_move_insn (mask, GEN_INT (imask));
13728 emit_insn (gen_ashlsi3 (mask, mask, shift));
13730 xorm = gen_rtx_XOR (SImode, used_m, mask);
13731 /* Depending on the value of 'op', the XOR or the operation might
13732 be able to be simplified away. */
13733 newop = simplify_gen_binary (code, SImode, xorm, newop);
13736 used_mode = SImode;
13737 before = gen_reg_rtx (used_mode);
13738 after = gen_reg_rtx (used_mode);
13743 before = before_param;
13744 after = after_param;
13746 if (before == NULL_RTX)
13747 before = gen_reg_rtx (used_mode);
13748 if (after == NULL_RTX)
13749 after = gen_reg_rtx (used_mode);
13752 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
13753 && used_mode != mode)
13754 the_op = op; /* Computed above. */
13755 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
13756 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
13758 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
13760 set_after = gen_rtx_SET (VOIDmode, after, the_op);
13761 set_before = gen_rtx_SET (VOIDmode, before, used_m);
13762 set_atomic = gen_rtx_SET (VOIDmode, used_m,
13763 gen_rtx_UNSPEC (used_mode,
13764 gen_rtvec (1, the_op),
13766 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
13768 if ((code == PLUS || code == MINUS) && used_mode != mode)
13769 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
13770 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
13772 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
13773 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
13775 /* Shift and mask the return values properly. */
13776 if (used_mode != mode && before_param)
13778 emit_insn (gen_lshrsi3 (before, before, shift));
13779 convert_move (before_param, before, 1);
13782 if (used_mode != mode && after_param)
13784 emit_insn (gen_lshrsi3 (after, after, shift));
13785 convert_move (after_param, after, 1);
13788 /* The previous sequence will end with a branch that's dependent on
13789 the conditional store, so placing an isync will ensure that no
13790 other instructions (especially, no load or store instructions)
13791 can start before the atomic operation completes. */
13793 emit_insn (gen_isync ());
13796 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13797 COND is true. Mark the jump as unlikely to be taken. */
13800 emit_unlikely_jump (rtx cond, rtx label)
13802 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
13805 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
13806 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
13807 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
13810 /* A subroutine of the atomic operation splitters. Emit a load-locked
13811 instruction in MODE. */
13814 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
13816 rtx (*fn) (rtx, rtx) = NULL;
13817 if (mode == SImode)
13818 fn = gen_load_locked_si;
13819 else if (mode == DImode)
13820 fn = gen_load_locked_di;
13821 emit_insn (fn (reg, mem));
13824 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13825 instruction in MODE. */
13828 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
13830 rtx (*fn) (rtx, rtx, rtx) = NULL;
13831 if (mode == SImode)
13832 fn = gen_store_conditional_si;
13833 else if (mode == DImode)
13834 fn = gen_store_conditional_di;
13836 /* Emit sync before stwcx. to address PPC405 Erratum. */
13837 if (PPC405_ERRATUM77)
13838 emit_insn (gen_memory_barrier ());
13840 emit_insn (fn (res, mem, val));
13843 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13844 to perform. MEM is the memory on which to operate. VAL is the second
13845 operand of the binary operator. BEFORE and AFTER are optional locations to
13846 return the value of MEM either before of after the operation. SCRATCH is
13847 a scratch register. */
13850 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
13851 rtx before, rtx after, rtx scratch)
13853 enum machine_mode mode = GET_MODE (mem);
13854 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13856 emit_insn (gen_memory_barrier ());
13858 label = gen_label_rtx ();
13859 emit_label (label);
13860 label = gen_rtx_LABEL_REF (VOIDmode, label);
13862 if (before == NULL_RTX)
13864 emit_load_locked (mode, before, mem);
13867 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
13868 else if (code == AND)
13869 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
13871 x = gen_rtx_fmt_ee (code, mode, before, val);
13873 if (after != NULL_RTX)
13874 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
13875 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13877 emit_store_conditional (mode, cond, mem, scratch);
13879 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13880 emit_unlikely_jump (x, label);
13882 emit_insn (gen_isync ());
13885 /* Expand an atomic compare and swap operation. MEM is the memory on which
13886 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13887 value to be stored. SCRATCH is a scratch GPR. */
13890 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
13893 enum machine_mode mode = GET_MODE (mem);
13894 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13896 emit_insn (gen_memory_barrier ());
13898 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13899 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13900 emit_label (XEXP (label1, 0));
13902 emit_load_locked (mode, retval, mem);
13904 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13905 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13907 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13908 emit_unlikely_jump (x, label2);
13910 emit_move_insn (scratch, newval);
13911 emit_store_conditional (mode, cond, mem, scratch);
13913 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13914 emit_unlikely_jump (x, label1);
13916 emit_insn (gen_isync ());
13917 emit_label (XEXP (label2, 0));
13920 /* Expand an atomic test and set operation. MEM is the memory on which
13921 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13924 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13926 enum machine_mode mode = GET_MODE (mem);
13927 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13929 emit_insn (gen_memory_barrier ());
13931 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13932 emit_label (XEXP (label, 0));
13934 emit_load_locked (mode, retval, mem);
13935 emit_move_insn (scratch, val);
13936 emit_store_conditional (mode, cond, mem, scratch);
13938 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13939 emit_unlikely_jump (x, label);
13941 emit_insn (gen_isync ());
13945 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13947 enum machine_mode mode = GET_MODE (mem);
13948 rtx addrSI, align, wdst, shift, mask;
13949 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13950 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13952 /* Shift amount for subword relative to aligned word. */
13953 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13954 shift = gen_reg_rtx (SImode);
13955 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13956 GEN_INT (shift_mask)));
13957 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13959 /* Shift and mask old value into position within word. */
13960 oldval = convert_modes (SImode, mode, oldval, 1);
13961 oldval = expand_binop (SImode, and_optab,
13962 oldval, GEN_INT (imask), NULL_RTX,
13963 1, OPTAB_LIB_WIDEN);
13964 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13966 /* Shift and mask new value into position within word. */
13967 newval = convert_modes (SImode, mode, newval, 1);
13968 newval = expand_binop (SImode, and_optab,
13969 newval, GEN_INT (imask), NULL_RTX,
13970 1, OPTAB_LIB_WIDEN);
13971 emit_insn (gen_ashlsi3 (newval, newval, shift));
13973 /* Mask for insertion. */
13974 mask = gen_reg_rtx (SImode);
13975 emit_move_insn (mask, GEN_INT (imask));
13976 emit_insn (gen_ashlsi3 (mask, mask, shift));
13978 /* Address of aligned word containing subword. */
13979 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13980 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13981 mem = change_address (mem, SImode, align);
13982 set_mem_align (mem, 32);
13983 MEM_VOLATILE_P (mem) = 1;
13985 wdst = gen_reg_rtx (SImode);
13986 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13987 oldval, newval, mem));
13989 /* Shift the result back. */
13990 emit_insn (gen_lshrsi3 (wdst, wdst, shift));
13992 emit_move_insn (dst, gen_lowpart (mode, wdst));
13996 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13997 rtx oldval, rtx newval, rtx mem,
14000 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
14002 emit_insn (gen_memory_barrier ());
14003 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
14004 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
14005 emit_label (XEXP (label1, 0));
14007 emit_load_locked (SImode, scratch, mem);
14009 /* Mask subword within loaded value for comparison with oldval.
14010 Use UNSPEC_AND to avoid clobber.*/
14011 emit_insn (gen_rtx_SET (SImode, dest,
14012 gen_rtx_UNSPEC (SImode,
14013 gen_rtvec (2, scratch, mask),
14016 x = gen_rtx_COMPARE (CCmode, dest, oldval);
14017 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
14019 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14020 emit_unlikely_jump (x, label2);
14022 /* Clear subword within loaded value for insertion of new value. */
14023 emit_insn (gen_rtx_SET (SImode, scratch,
14024 gen_rtx_AND (SImode,
14025 gen_rtx_NOT (SImode, mask), scratch)));
14026 emit_insn (gen_iorsi3 (scratch, scratch, newval));
14027 emit_store_conditional (SImode, cond, mem, scratch);
14029 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14030 emit_unlikely_jump (x, label1);
14032 emit_insn (gen_isync ());
14033 emit_label (XEXP (label2, 0));
14037 /* Emit instructions to move SRC to DST. Called by splitters for
14038 multi-register moves. It will emit at most one instruction for
14039 each register that is accessed; that is, it won't emit li/lis pairs
14040 (or equivalent for 64-bit code). One of SRC or DST must be a hard
14044 rs6000_split_multireg_move (rtx dst, rtx src)
14046 /* The register number of the first register being moved. */
14048 /* The mode that is to be moved. */
14049 enum machine_mode mode;
14050 /* The mode that the move is being done in, and its size. */
14051 enum machine_mode reg_mode;
14053 /* The number of registers that will be moved. */
14056 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
14057 mode = GET_MODE (dst);
14058 nregs = hard_regno_nregs[reg][mode];
14059 if (FP_REGNO_P (reg))
14060 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
14061 else if (ALTIVEC_REGNO_P (reg))
14062 reg_mode = V16QImode;
14063 else if (TARGET_E500_DOUBLE && mode == TFmode)
14066 reg_mode = word_mode;
14067 reg_mode_size = GET_MODE_SIZE (reg_mode);
14069 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
14071 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
14073 /* Move register range backwards, if we might have destructive
14076 for (i = nregs - 1; i >= 0; i--)
14077 emit_insn (gen_rtx_SET (VOIDmode,
14078 simplify_gen_subreg (reg_mode, dst, mode,
14079 i * reg_mode_size),
14080 simplify_gen_subreg (reg_mode, src, mode,
14081 i * reg_mode_size)));
14087 bool used_update = false;
14089 if (MEM_P (src) && INT_REGNO_P (reg))
14093 if (GET_CODE (XEXP (src, 0)) == PRE_INC
14094 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
14097 breg = XEXP (XEXP (src, 0), 0);
14098 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
14099 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
14100 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
14101 emit_insn (TARGET_32BIT
14102 ? gen_addsi3 (breg, breg, delta_rtx)
14103 : gen_adddi3 (breg, breg, delta_rtx));
14104 src = replace_equiv_address (src, breg);
14106 else if (! rs6000_offsettable_memref_p (src))
14109 basereg = gen_rtx_REG (Pmode, reg);
14110 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
14111 src = replace_equiv_address (src, basereg);
14114 breg = XEXP (src, 0);
14115 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
14116 breg = XEXP (breg, 0);
14118 /* If the base register we are using to address memory is
14119 also a destination reg, then change that register last. */
14121 && REGNO (breg) >= REGNO (dst)
14122 && REGNO (breg) < REGNO (dst) + nregs)
14123 j = REGNO (breg) - REGNO (dst);
14126 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
14130 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
14131 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
14134 breg = XEXP (XEXP (dst, 0), 0);
14135 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
14136 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
14137 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
14139 /* We have to update the breg before doing the store.
14140 Use store with update, if available. */
14144 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
14145 emit_insn (TARGET_32BIT
14146 ? (TARGET_POWERPC64
14147 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
14148 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
14149 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
14150 used_update = true;
14153 emit_insn (TARGET_32BIT
14154 ? gen_addsi3 (breg, breg, delta_rtx)
14155 : gen_adddi3 (breg, breg, delta_rtx));
14156 dst = replace_equiv_address (dst, breg);
14159 gcc_assert (rs6000_offsettable_memref_p (dst));
14162 for (i = 0; i < nregs; i++)
14164 /* Calculate index to next subword. */
14169 /* If compiler already emitted move of first word by
14170 store with update, no need to do anything. */
14171 if (j == 0 && used_update)
14174 emit_insn (gen_rtx_SET (VOIDmode,
14175 simplify_gen_subreg (reg_mode, dst, mode,
14176 j * reg_mode_size),
14177 simplify_gen_subreg (reg_mode, src, mode,
14178 j * reg_mode_size)));
14184 /* This page contains routines that are used to determine what the
14185 function prologue and epilogue code will do and write them out. */
14187 /* Return the first fixed-point register that is required to be
14188 saved. 32 if none. */
14191 first_reg_to_save (void)
14195 /* Find lowest numbered live register. */
14196 for (first_reg = 13; first_reg <= 31; first_reg++)
14197 if (df_regs_ever_live_p (first_reg)
14198 && (! call_used_regs[first_reg]
14199 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14200 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14201 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
14202 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
14207 && crtl->uses_pic_offset_table
14208 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
14209 return RS6000_PIC_OFFSET_TABLE_REGNUM;
14215 /* Similar, for FP regs. */
14218 first_fp_reg_to_save (void)
14222 /* Find lowest numbered live register. */
14223 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
14224 if (df_regs_ever_live_p (first_reg))
14230 /* Similar, for AltiVec regs. */
14233 first_altivec_reg_to_save (void)
14237 /* Stack frame remains as is unless we are in AltiVec ABI. */
14238 if (! TARGET_ALTIVEC_ABI)
14239 return LAST_ALTIVEC_REGNO + 1;
14241 /* On Darwin, the unwind routines are compiled without
14242 TARGET_ALTIVEC, and use save_world to save/restore the
14243 altivec registers when necessary. */
14244 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
14245 && ! TARGET_ALTIVEC)
14246 return FIRST_ALTIVEC_REGNO + 20;
14248 /* Find lowest numbered live register. */
14249 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
14250 if (df_regs_ever_live_p (i))
14256 /* Return a 32-bit mask of the AltiVec registers we need to set in
14257 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14258 the 32-bit word is 0. */
14260 static unsigned int
14261 compute_vrsave_mask (void)
14263 unsigned int i, mask = 0;
14265 /* On Darwin, the unwind routines are compiled without
14266 TARGET_ALTIVEC, and use save_world to save/restore the
14267 call-saved altivec registers when necessary. */
14268 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
14269 && ! TARGET_ALTIVEC)
14272 /* First, find out if we use _any_ altivec registers. */
14273 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14274 if (df_regs_ever_live_p (i))
14275 mask |= ALTIVEC_REG_BIT (i);
14280 /* Next, remove the argument registers from the set. These must
14281 be in the VRSAVE mask set by the caller, so we don't need to add
14282 them in again. More importantly, the mask we compute here is
14283 used to generate CLOBBERs in the set_vrsave insn, and we do not
14284 wish the argument registers to die. */
14285 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
14286 mask &= ~ALTIVEC_REG_BIT (i);
14288 /* Similarly, remove the return value from the set. */
14291 diddle_return_value (is_altivec_return_reg, &yes);
14293 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
14299 /* For a very restricted set of circumstances, we can cut down the
14300 size of prologues/epilogues by calling our own save/restore-the-world
14304 compute_save_world_info (rs6000_stack_t *info_ptr)
14306 info_ptr->world_save_p = 1;
14307 info_ptr->world_save_p
14308 = (WORLD_SAVE_P (info_ptr)
14309 && DEFAULT_ABI == ABI_DARWIN
14310 && ! (cfun->calls_setjmp && flag_exceptions)
14311 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
14312 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
14313 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
14314 && info_ptr->cr_save_p);
14316 /* This will not work in conjunction with sibcalls. Make sure there
14317 are none. (This check is expensive, but seldom executed.) */
14318 if (WORLD_SAVE_P (info_ptr))
14321 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
14322 if ( GET_CODE (insn) == CALL_INSN
14323 && SIBLING_CALL_P (insn))
14325 info_ptr->world_save_p = 0;
14330 if (WORLD_SAVE_P (info_ptr))
14332 /* Even if we're not touching VRsave, make sure there's room on the
14333 stack for it, if it looks like we're calling SAVE_WORLD, which
14334 will attempt to save it. */
14335 info_ptr->vrsave_size = 4;
14337 /* If we are going to save the world, we need to save the link register too. */
14338 info_ptr->lr_save_p = 1;
14340 /* "Save" the VRsave register too if we're saving the world. */
14341 if (info_ptr->vrsave_mask == 0)
14342 info_ptr->vrsave_mask = compute_vrsave_mask ();
14344 /* Because the Darwin register save/restore routines only handle
14345 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14347 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
14348 && (info_ptr->first_altivec_reg_save
14349 >= FIRST_SAVED_ALTIVEC_REGNO));
14356 is_altivec_return_reg (rtx reg, void *xyes)
14358 bool *yes = (bool *) xyes;
14359 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
14364 /* Calculate the stack information for the current function. This is
14365 complicated by having two separate calling sequences, the AIX calling
14366 sequence and the V.4 calling sequence.
14368 AIX (and Darwin/Mac OS X) stack frames look like:
14370 SP----> +---------------------------------------+
14371 | back chain to caller | 0 0
14372 +---------------------------------------+
14373 | saved CR | 4 8 (8-11)
14374 +---------------------------------------+
14376 +---------------------------------------+
14377 | reserved for compilers | 12 24
14378 +---------------------------------------+
14379 | reserved for binders | 16 32
14380 +---------------------------------------+
14381 | saved TOC pointer | 20 40
14382 +---------------------------------------+
14383 | Parameter save area (P) | 24 48
14384 +---------------------------------------+
14385 | Alloca space (A) | 24+P etc.
14386 +---------------------------------------+
14387 | Local variable space (L) | 24+P+A
14388 +---------------------------------------+
14389 | Float/int conversion temporary (X) | 24+P+A+L
14390 +---------------------------------------+
14391 | Save area for AltiVec registers (W) | 24+P+A+L+X
14392 +---------------------------------------+
14393 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14394 +---------------------------------------+
14395 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14396 +---------------------------------------+
14397 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14398 +---------------------------------------+
14399 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14400 +---------------------------------------+
14401 old SP->| back chain to caller's caller |
14402 +---------------------------------------+
14404 The required alignment for AIX configurations is two words (i.e., 8
14408 V.4 stack frames look like:
14410 SP----> +---------------------------------------+
14411 | back chain to caller | 0
14412 +---------------------------------------+
14413 | caller's saved LR | 4
14414 +---------------------------------------+
14415 | Parameter save area (P) | 8
14416 +---------------------------------------+
14417 | Alloca space (A) | 8+P
14418 +---------------------------------------+
14419 | Varargs save area (V) | 8+P+A
14420 +---------------------------------------+
14421 | Local variable space (L) | 8+P+A+V
14422 +---------------------------------------+
14423 | Float/int conversion temporary (X) | 8+P+A+V+L
14424 +---------------------------------------+
14425 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14426 +---------------------------------------+
14427 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14428 +---------------------------------------+
14429 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14430 +---------------------------------------+
14431 | SPE: area for 64-bit GP registers |
14432 +---------------------------------------+
14433 | SPE alignment padding |
14434 +---------------------------------------+
14435 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14436 +---------------------------------------+
14437 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14438 +---------------------------------------+
14439 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14440 +---------------------------------------+
14441 old SP->| back chain to caller's caller |
14442 +---------------------------------------+
14444 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14445 given. (But note below and in sysv4.h that we require only 8 and
14446 may round up the size of our stack frame anyways. The historical
14447 reason is early versions of powerpc-linux which didn't properly
14448 align the stack at program startup. A happy side-effect is that
14449 -mno-eabi libraries can be used with -meabi programs.)
14451 The EABI configuration defaults to the V.4 layout. However,
14452 the stack alignment requirements may differ. If -mno-eabi is not
14453 given, the required stack alignment is 8 bytes; if -mno-eabi is
14454 given, the required alignment is 16 bytes. (But see V.4 comment
14457 #ifndef ABI_STACK_BOUNDARY
14458 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14461 static rs6000_stack_t *
14462 rs6000_stack_info (void)
14464 static rs6000_stack_t info;
14465 rs6000_stack_t *info_ptr = &info;
14466 int reg_size = TARGET_32BIT ? 4 : 8;
14470 HOST_WIDE_INT non_fixed_size;
14472 memset (&info, 0, sizeof (info));
14476 /* Cache value so we don't rescan instruction chain over and over. */
14477 if (cfun->machine->insn_chain_scanned_p == 0)
14478 cfun->machine->insn_chain_scanned_p
14479 = spe_func_has_64bit_regs_p () + 1;
14480 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
14483 /* Select which calling sequence. */
14484 info_ptr->abi = DEFAULT_ABI;
14486 /* Calculate which registers need to be saved & save area size. */
14487 info_ptr->first_gp_reg_save = first_reg_to_save ();
14488 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14489 even if it currently looks like we won't. Reload may need it to
14490 get at a constant; if so, it will have already created a constant
14491 pool entry for it. */
14492 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
14493 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
14494 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
14495 && crtl->uses_const_pool
14496 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
14497 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
14499 first_gp = info_ptr->first_gp_reg_save;
14501 info_ptr->gp_size = reg_size * (32 - first_gp);
14503 /* For the SPE, we have an additional upper 32-bits on each GPR.
14504 Ideally we should save the entire 64-bits only when the upper
14505 half is used in SIMD instructions. Since we only record
14506 registers live (not the size they are used in), this proves
14507 difficult because we'd have to traverse the instruction chain at
14508 the right time, taking reload into account. This is a real pain,
14509 so we opt to save the GPRs in 64-bits always if but one register
14510 gets used in 64-bits. Otherwise, all the registers in the frame
14511 get saved in 32-bits.
14513 So... since when we save all GPRs (except the SP) in 64-bits, the
14514 traditional GP save area will be empty. */
14515 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14516 info_ptr->gp_size = 0;
14518 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
14519 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
14521 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
14522 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
14523 - info_ptr->first_altivec_reg_save);
14525 /* Does this function call anything? */
14526 info_ptr->calls_p = (! current_function_is_leaf
14527 || cfun->machine->ra_needs_full_frame);
14529 /* Determine if we need to save the link register. */
14530 if ((DEFAULT_ABI == ABI_AIX
14532 && !TARGET_PROFILE_KERNEL)
14533 #ifdef TARGET_RELOCATABLE
14534 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
14536 || (info_ptr->first_fp_reg_save != 64
14537 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
14538 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
14539 || info_ptr->calls_p
14540 || rs6000_ra_ever_killed ())
14542 info_ptr->lr_save_p = 1;
14543 df_set_regs_ever_live (LR_REGNO, true);
14546 /* Determine if we need to save the condition code registers. */
14547 if (df_regs_ever_live_p (CR2_REGNO)
14548 || df_regs_ever_live_p (CR3_REGNO)
14549 || df_regs_ever_live_p (CR4_REGNO))
14551 info_ptr->cr_save_p = 1;
14552 if (DEFAULT_ABI == ABI_V4)
14553 info_ptr->cr_size = reg_size;
14556 /* If the current function calls __builtin_eh_return, then we need
14557 to allocate stack space for registers that will hold data for
14558 the exception handler. */
14559 if (crtl->calls_eh_return)
14562 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
14565 /* SPE saves EH registers in 64-bits. */
14566 ehrd_size = i * (TARGET_SPE_ABI
14567 && info_ptr->spe_64bit_regs_used != 0
14568 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
14573 /* Determine various sizes. */
14574 info_ptr->reg_size = reg_size;
14575 info_ptr->fixed_size = RS6000_SAVE_AREA;
14576 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
14577 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
14578 TARGET_ALTIVEC ? 16 : 8);
14579 if (FRAME_GROWS_DOWNWARD)
14580 info_ptr->vars_size
14581 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
14582 + info_ptr->parm_size,
14583 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
14584 - (info_ptr->fixed_size + info_ptr->vars_size
14585 + info_ptr->parm_size);
14587 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14588 info_ptr->spe_gp_size = 8 * (32 - first_gp);
14590 info_ptr->spe_gp_size = 0;
14592 if (TARGET_ALTIVEC_ABI)
14593 info_ptr->vrsave_mask = compute_vrsave_mask ();
14595 info_ptr->vrsave_mask = 0;
14597 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
14598 info_ptr->vrsave_size = 4;
14600 info_ptr->vrsave_size = 0;
14602 compute_save_world_info (info_ptr);
14604 /* Calculate the offsets. */
14605 switch (DEFAULT_ABI)
14609 gcc_unreachable ();
14613 info_ptr->fp_save_offset = - info_ptr->fp_size;
14614 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14616 if (TARGET_ALTIVEC_ABI)
14618 info_ptr->vrsave_save_offset
14619 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
14621 /* Align stack so vector save area is on a quadword boundary.
14622 The padding goes above the vectors. */
14623 if (info_ptr->altivec_size != 0)
14624 info_ptr->altivec_padding_size
14625 = info_ptr->vrsave_save_offset & 0xF;
14627 info_ptr->altivec_padding_size = 0;
14629 info_ptr->altivec_save_offset
14630 = info_ptr->vrsave_save_offset
14631 - info_ptr->altivec_padding_size
14632 - info_ptr->altivec_size;
14633 gcc_assert (info_ptr->altivec_size == 0
14634 || info_ptr->altivec_save_offset % 16 == 0);
14636 /* Adjust for AltiVec case. */
14637 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
14640 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
14641 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
14642 info_ptr->lr_save_offset = 2*reg_size;
14646 info_ptr->fp_save_offset = - info_ptr->fp_size;
14647 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14648 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
14650 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14652 /* Align stack so SPE GPR save area is aligned on a
14653 double-word boundary. */
14654 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
14655 info_ptr->spe_padding_size
14656 = 8 - (-info_ptr->cr_save_offset % 8);
14658 info_ptr->spe_padding_size = 0;
14660 info_ptr->spe_gp_save_offset
14661 = info_ptr->cr_save_offset
14662 - info_ptr->spe_padding_size
14663 - info_ptr->spe_gp_size;
14665 /* Adjust for SPE case. */
14666 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
14668 else if (TARGET_ALTIVEC_ABI)
14670 info_ptr->vrsave_save_offset
14671 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
14673 /* Align stack so vector save area is on a quadword boundary. */
14674 if (info_ptr->altivec_size != 0)
14675 info_ptr->altivec_padding_size
14676 = 16 - (-info_ptr->vrsave_save_offset % 16);
14678 info_ptr->altivec_padding_size = 0;
14680 info_ptr->altivec_save_offset
14681 = info_ptr->vrsave_save_offset
14682 - info_ptr->altivec_padding_size
14683 - info_ptr->altivec_size;
14685 /* Adjust for AltiVec case. */
14686 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
14689 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
14690 info_ptr->ehrd_offset -= ehrd_size;
14691 info_ptr->lr_save_offset = reg_size;
14695 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
14696 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
14697 + info_ptr->gp_size
14698 + info_ptr->altivec_size
14699 + info_ptr->altivec_padding_size
14700 + info_ptr->spe_gp_size
14701 + info_ptr->spe_padding_size
14703 + info_ptr->cr_size
14704 + info_ptr->vrsave_size,
14707 non_fixed_size = (info_ptr->vars_size
14708 + info_ptr->parm_size
14709 + info_ptr->save_size);
14711 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
14712 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
14714 /* Determine if we need to allocate any stack frame:
14716 For AIX we need to push the stack if a frame pointer is needed
14717 (because the stack might be dynamically adjusted), if we are
14718 debugging, if we make calls, or if the sum of fp_save, gp_save,
14719 and local variables are more than the space needed to save all
14720 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14721 + 18*8 = 288 (GPR13 reserved).
14723 For V.4 we don't have the stack cushion that AIX uses, but assume
14724 that the debugger can handle stackless frames. */
14726 if (info_ptr->calls_p)
14727 info_ptr->push_p = 1;
14729 else if (DEFAULT_ABI == ABI_V4)
14730 info_ptr->push_p = non_fixed_size != 0;
14732 else if (frame_pointer_needed)
14733 info_ptr->push_p = 1;
14735 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
14736 info_ptr->push_p = 1;
14739 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
14741 /* Zero offsets if we're not saving those registers. */
14742 if (info_ptr->fp_size == 0)
14743 info_ptr->fp_save_offset = 0;
14745 if (info_ptr->gp_size == 0)
14746 info_ptr->gp_save_offset = 0;
14748 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
14749 info_ptr->altivec_save_offset = 0;
14751 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
14752 info_ptr->vrsave_save_offset = 0;
14754 if (! TARGET_SPE_ABI
14755 || info_ptr->spe_64bit_regs_used == 0
14756 || info_ptr->spe_gp_size == 0)
14757 info_ptr->spe_gp_save_offset = 0;
14759 if (! info_ptr->lr_save_p)
14760 info_ptr->lr_save_offset = 0;
14762 if (! info_ptr->cr_save_p)
14763 info_ptr->cr_save_offset = 0;
14768 /* Return true if the current function uses any GPRs in 64-bit SIMD
14772 spe_func_has_64bit_regs_p (void)
14776 /* Functions that save and restore all the call-saved registers will
14777 need to save/restore the registers in 64-bits. */
14778 if (crtl->calls_eh_return
14779 || cfun->calls_setjmp
14780 || crtl->has_nonlocal_goto)
14783 insns = get_insns ();
14785 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
14791 /* FIXME: This should be implemented with attributes...
14793 (set_attr "spe64" "true")....then,
14794 if (get_spe64(insn)) return true;
14796 It's the only reliable way to do the stuff below. */
14798 i = PATTERN (insn);
14799 if (GET_CODE (i) == SET)
14801 enum machine_mode mode = GET_MODE (SET_SRC (i));
14803 if (SPE_VECTOR_MODE (mode))
14805 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
14815 debug_stack_info (rs6000_stack_t *info)
14817 const char *abi_string;
14820 info = rs6000_stack_info ();
14822 fprintf (stderr, "\nStack information for function %s:\n",
14823 ((current_function_decl && DECL_NAME (current_function_decl))
14824 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
14829 default: abi_string = "Unknown"; break;
14830 case ABI_NONE: abi_string = "NONE"; break;
14831 case ABI_AIX: abi_string = "AIX"; break;
14832 case ABI_DARWIN: abi_string = "Darwin"; break;
14833 case ABI_V4: abi_string = "V.4"; break;
14836 fprintf (stderr, "\tABI = %5s\n", abi_string);
14838 if (TARGET_ALTIVEC_ABI)
14839 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
14841 if (TARGET_SPE_ABI)
14842 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
14844 if (info->first_gp_reg_save != 32)
14845 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
14847 if (info->first_fp_reg_save != 64)
14848 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
14850 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
14851 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
14852 info->first_altivec_reg_save);
14854 if (info->lr_save_p)
14855 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
14857 if (info->cr_save_p)
14858 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
14860 if (info->vrsave_mask)
14861 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
14864 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
14867 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
14869 if (info->gp_save_offset)
14870 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
14872 if (info->fp_save_offset)
14873 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
14875 if (info->altivec_save_offset)
14876 fprintf (stderr, "\taltivec_save_offset = %5d\n",
14877 info->altivec_save_offset);
14879 if (info->spe_gp_save_offset)
14880 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
14881 info->spe_gp_save_offset);
14883 if (info->vrsave_save_offset)
14884 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
14885 info->vrsave_save_offset);
14887 if (info->lr_save_offset)
14888 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
14890 if (info->cr_save_offset)
14891 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
14893 if (info->varargs_save_offset)
14894 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
14896 if (info->total_size)
14897 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14900 if (info->vars_size)
14901 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14904 if (info->parm_size)
14905 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
14907 if (info->fixed_size)
14908 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14911 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14913 if (info->spe_gp_size)
14914 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14917 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14919 if (info->altivec_size)
14920 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14922 if (info->vrsave_size)
14923 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14925 if (info->altivec_padding_size)
14926 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14927 info->altivec_padding_size);
14929 if (info->spe_padding_size)
14930 fprintf (stderr, "\tspe_padding_size = %5d\n",
14931 info->spe_padding_size);
14934 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14936 if (info->save_size)
14937 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14939 if (info->reg_size != 4)
14940 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14942 fprintf (stderr, "\n");
14946 rs6000_return_addr (int count, rtx frame)
14948 /* Currently we don't optimize very well between prolog and body
14949 code and for PIC code the code can be actually quite bad, so
14950 don't try to be too clever here. */
14951 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14953 cfun->machine->ra_needs_full_frame = 1;
14960 plus_constant (copy_to_reg
14961 (gen_rtx_MEM (Pmode,
14962 memory_address (Pmode, frame))),
14963 RETURN_ADDRESS_OFFSET)));
14966 cfun->machine->ra_need_lr = 1;
14967 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14970 /* Say whether a function is a candidate for sibcall handling or not.
14971 We do not allow indirect calls to be optimized into sibling calls.
14972 Also, we can't do it if there are any vector parameters; there's
14973 nowhere to put the VRsave code so it works; note that functions with
14974 vector parameters are required to have a prototype, so the argument
14975 type info must be available here. (The tail recursion case can work
14976 with vector parameters, but there's no way to distinguish here.) */
14978 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14983 if (TARGET_ALTIVEC_VRSAVE)
14985 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14986 type; type = TREE_CHAIN (type))
14988 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14992 if (DEFAULT_ABI == ABI_DARWIN
14993 || ((*targetm.binds_local_p) (decl)
14994 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14996 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14998 if (!lookup_attribute ("longcall", attr_list)
14999 || lookup_attribute ("shortcall", attr_list))
15006 /* NULL if INSN insn is valid within a low-overhead loop.
15007 Otherwise return why doloop cannot be applied.
15008 PowerPC uses the COUNT register for branch on table instructions. */
15010 static const char *
15011 rs6000_invalid_within_doloop (const_rtx insn)
15014 return "Function call in the loop.";
15017 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
15018 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
15019 return "Computed branch in the loop.";
15025 rs6000_ra_ever_killed (void)
15031 if (crtl->is_thunk)
15034 /* regs_ever_live has LR marked as used if any sibcalls are present,
15035 but this should not force saving and restoring in the
15036 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
15037 clobbers LR, so that is inappropriate. */
15039 /* Also, the prologue can generate a store into LR that
15040 doesn't really count, like this:
15043 bcl to set PIC register
15047 When we're called from the epilogue, we need to avoid counting
15048 this as a store. */
15050 push_topmost_sequence ();
15051 top = get_insns ();
15052 pop_topmost_sequence ();
15053 reg = gen_rtx_REG (Pmode, LR_REGNO);
15055 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
15061 if (!SIBLING_CALL_P (insn))
15064 else if (find_regno_note (insn, REG_INC, LR_REGNO))
15066 else if (set_of (reg, insn) != NULL_RTX
15067 && !prologue_epilogue_contains (insn))
15074 /* Emit instructions needed to load the TOC register.
15075 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
15076 a constant pool; or for SVR4 -fpic. */
15079 rs6000_emit_load_toc_table (int fromprolog)
15082 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
15084 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
15087 rtx lab, tmp1, tmp2, got;
15089 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15090 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15092 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15094 got = rs6000_got_sym ();
15095 tmp1 = tmp2 = dest;
15098 tmp1 = gen_reg_rtx (Pmode);
15099 tmp2 = gen_reg_rtx (Pmode);
15101 emit_insn (gen_load_toc_v4_PIC_1 (lab));
15102 emit_move_insn (tmp1,
15103 gen_rtx_REG (Pmode, LR_REGNO));
15104 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
15105 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
15107 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
15109 emit_insn (gen_load_toc_v4_pic_si ());
15110 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
15112 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
15115 rtx temp0 = (fromprolog
15116 ? gen_rtx_REG (Pmode, 0)
15117 : gen_reg_rtx (Pmode));
15123 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15124 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15126 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
15127 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15129 emit_insn (gen_load_toc_v4_PIC_1 (symF));
15130 emit_move_insn (dest,
15131 gen_rtx_REG (Pmode, LR_REGNO));
15132 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
15138 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15139 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
15140 emit_move_insn (dest,
15141 gen_rtx_REG (Pmode, LR_REGNO));
15142 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
15144 emit_insn (gen_addsi3 (dest, temp0, dest));
15146 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
15148 /* This is for AIX code running in non-PIC ELF32. */
15151 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15152 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15154 emit_insn (gen_elf_high (dest, realsym));
15155 emit_insn (gen_elf_low (dest, dest, realsym));
15159 gcc_assert (DEFAULT_ABI == ABI_AIX);
15162 emit_insn (gen_load_toc_aix_si (dest));
15164 emit_insn (gen_load_toc_aix_di (dest));
15168 /* Emit instructions to restore the link register after determining where
15169 its value has been stored. */
15172 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
15174 rs6000_stack_t *info = rs6000_stack_info ();
15177 operands[0] = source;
15178 operands[1] = scratch;
15180 if (info->lr_save_p)
15182 rtx frame_rtx = stack_pointer_rtx;
15183 HOST_WIDE_INT sp_offset = 0;
15186 if (frame_pointer_needed
15187 || cfun->calls_alloca
15188 || info->total_size > 32767)
15190 tmp = gen_frame_mem (Pmode, frame_rtx);
15191 emit_move_insn (operands[1], tmp);
15192 frame_rtx = operands[1];
15194 else if (info->push_p)
15195 sp_offset = info->total_size;
15197 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
15198 tmp = gen_frame_mem (Pmode, tmp);
15199 emit_move_insn (tmp, operands[0]);
15202 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
15205 static GTY(()) alias_set_type set = -1;
15208 get_TOC_alias_set (void)
15211 set = new_alias_set ();
15215 /* This returns nonzero if the current function uses the TOC. This is
15216 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15217 is generated by the ABI_V4 load_toc_* patterns. */
15224 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15227 rtx pat = PATTERN (insn);
15230 if (GET_CODE (pat) == PARALLEL)
15231 for (i = 0; i < XVECLEN (pat, 0); i++)
15233 rtx sub = XVECEXP (pat, 0, i);
15234 if (GET_CODE (sub) == USE)
15236 sub = XEXP (sub, 0);
15237 if (GET_CODE (sub) == UNSPEC
15238 && XINT (sub, 1) == UNSPEC_TOC)
15248 create_TOC_reference (rtx symbol)
15250 if (!can_create_pseudo_p ())
15251 df_set_regs_ever_live (TOC_REGISTER, true);
15252 return gen_rtx_PLUS (Pmode,
15253 gen_rtx_REG (Pmode, TOC_REGISTER),
15254 gen_rtx_CONST (Pmode,
15255 gen_rtx_MINUS (Pmode, symbol,
15256 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
15259 /* If _Unwind_* has been called from within the same module,
15260 toc register is not guaranteed to be saved to 40(1) on function
15261 entry. Save it there in that case. */
15264 rs6000_aix_emit_builtin_unwind_init (void)
15267 rtx stack_top = gen_reg_rtx (Pmode);
15268 rtx opcode_addr = gen_reg_rtx (Pmode);
15269 rtx opcode = gen_reg_rtx (SImode);
15270 rtx tocompare = gen_reg_rtx (SImode);
15271 rtx no_toc_save_needed = gen_label_rtx ();
15273 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
15274 emit_move_insn (stack_top, mem);
15276 mem = gen_frame_mem (Pmode,
15277 gen_rtx_PLUS (Pmode, stack_top,
15278 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
15279 emit_move_insn (opcode_addr, mem);
15280 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
15281 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
15282 : 0xE8410028, SImode));
15284 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
15285 SImode, NULL_RTX, NULL_RTX,
15286 no_toc_save_needed);
15288 mem = gen_frame_mem (Pmode,
15289 gen_rtx_PLUS (Pmode, stack_top,
15290 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
15291 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
15292 emit_label (no_toc_save_needed);
15295 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15296 and the change to the stack pointer. */
15299 rs6000_emit_stack_tie (void)
15301 rtx mem = gen_frame_mem (BLKmode,
15302 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
15304 emit_insn (gen_stack_tie (mem));
15307 /* Emit the correct code for allocating stack space, as insns.
15308 If COPY_R12, make sure a copy of the old frame is left in r12.
15309 If COPY_R11, make sure a copy of the old frame is left in r11,
15310 in preference to r12 if COPY_R12.
15311 The generated code may use hard register 0 as a temporary. */
15314 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12, int copy_r11)
15317 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15318 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
15319 rtx todec = gen_int_mode (-size, Pmode);
15321 if (INTVAL (todec) != -size)
15323 warning (0, "stack frame too large");
15324 emit_insn (gen_trap ());
15328 if (crtl->limit_stack)
15330 if (REG_P (stack_limit_rtx)
15331 && REGNO (stack_limit_rtx) > 1
15332 && REGNO (stack_limit_rtx) <= 31)
15334 emit_insn (TARGET_32BIT
15335 ? gen_addsi3 (tmp_reg,
15338 : gen_adddi3 (tmp_reg,
15342 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15345 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
15347 && DEFAULT_ABI == ABI_V4)
15349 rtx toload = gen_rtx_CONST (VOIDmode,
15350 gen_rtx_PLUS (Pmode,
15354 emit_insn (gen_elf_high (tmp_reg, toload));
15355 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
15356 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15360 warning (0, "stack limit expression is not supported");
15363 if (copy_r12 || copy_r11 || ! TARGET_UPDATE)
15364 emit_move_insn (copy_r11
15365 ? gen_rtx_REG (Pmode, 11)
15366 : gen_rtx_REG (Pmode, 12),
15373 /* Need a note here so that try_split doesn't get confused. */
15374 if (get_last_insn () == NULL_RTX)
15375 emit_note (NOTE_INSN_DELETED);
15376 insn = emit_move_insn (tmp_reg, todec);
15377 try_split (PATTERN (insn), insn, 0);
15381 insn = emit_insn (TARGET_32BIT
15382 ? gen_movsi_update (stack_reg, stack_reg,
15384 : gen_movdi_di_update (stack_reg, stack_reg,
15385 todec, stack_reg));
15389 insn = emit_insn (TARGET_32BIT
15390 ? gen_addsi3 (stack_reg, stack_reg, todec)
15391 : gen_adddi3 (stack_reg, stack_reg, todec));
15392 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
15394 ? gen_rtx_REG (Pmode, 11)
15395 : gen_rtx_REG (Pmode, 12));
15398 RTX_FRAME_RELATED_P (insn) = 1;
15400 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15401 gen_rtx_SET (VOIDmode, stack_reg,
15402 gen_rtx_PLUS (Pmode, stack_reg,
15407 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15408 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15409 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15410 deduce these equivalences by itself so it wasn't necessary to hold
15411 its hand so much. */
15414 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
15415 rtx reg2, rtx rreg)
15419 /* copy_rtx will not make unique copies of registers, so we need to
15420 ensure we don't have unwanted sharing here. */
15422 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15425 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15427 real = copy_rtx (PATTERN (insn));
15429 if (reg2 != NULL_RTX)
15430 real = replace_rtx (real, reg2, rreg);
15432 real = replace_rtx (real, reg,
15433 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
15434 STACK_POINTER_REGNUM),
15437 /* We expect that 'real' is either a SET or a PARALLEL containing
15438 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15439 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15441 if (GET_CODE (real) == SET)
15445 temp = simplify_rtx (SET_SRC (set));
15447 SET_SRC (set) = temp;
15448 temp = simplify_rtx (SET_DEST (set));
15450 SET_DEST (set) = temp;
15451 if (GET_CODE (SET_DEST (set)) == MEM)
15453 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15455 XEXP (SET_DEST (set), 0) = temp;
15462 gcc_assert (GET_CODE (real) == PARALLEL);
15463 for (i = 0; i < XVECLEN (real, 0); i++)
15464 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
15466 rtx set = XVECEXP (real, 0, i);
15468 temp = simplify_rtx (SET_SRC (set));
15470 SET_SRC (set) = temp;
15471 temp = simplify_rtx (SET_DEST (set));
15473 SET_DEST (set) = temp;
15474 if (GET_CODE (SET_DEST (set)) == MEM)
15476 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15478 XEXP (SET_DEST (set), 0) = temp;
15480 RTX_FRAME_RELATED_P (set) = 1;
15484 RTX_FRAME_RELATED_P (insn) = 1;
15485 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15490 /* Returns an insn that has a vrsave set operation with the
15491 appropriate CLOBBERs. */
15494 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
15497 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
15498 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15501 = gen_rtx_SET (VOIDmode,
15503 gen_rtx_UNSPEC_VOLATILE (SImode,
15504 gen_rtvec (2, reg, vrsave),
15505 UNSPECV_SET_VRSAVE));
15509 /* We need to clobber the registers in the mask so the scheduler
15510 does not move sets to VRSAVE before sets of AltiVec registers.
15512 However, if the function receives nonlocal gotos, reload will set
15513 all call saved registers live. We will end up with:
15515 (set (reg 999) (mem))
15516 (parallel [ (set (reg vrsave) (unspec blah))
15517 (clobber (reg 999))])
15519 The clobber will cause the store into reg 999 to be dead, and
15520 flow will attempt to delete an epilogue insn. In this case, we
15521 need an unspec use/set of the register. */
15523 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
15524 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15526 if (!epiloguep || call_used_regs [i])
15527 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
15528 gen_rtx_REG (V4SImode, i));
15531 rtx reg = gen_rtx_REG (V4SImode, i);
15534 = gen_rtx_SET (VOIDmode,
15536 gen_rtx_UNSPEC (V4SImode,
15537 gen_rtvec (1, reg), 27));
15541 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
15543 for (i = 0; i < nclobs; ++i)
15544 XVECEXP (insn, 0, i) = clobs[i];
15549 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15550 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15553 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
15554 unsigned int regno, int offset, HOST_WIDE_INT total_size)
15556 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
15557 rtx replacea, replaceb;
15559 int_rtx = GEN_INT (offset);
15561 /* Some cases that need register indexed addressing. */
15562 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
15563 || (TARGET_E500_DOUBLE && mode == DFmode)
15565 && SPE_VECTOR_MODE (mode)
15566 && !SPE_CONST_OFFSET_OK (offset)))
15568 /* Whomever calls us must make sure r11 is available in the
15569 flow path of instructions in the prologue. */
15570 offset_rtx = gen_rtx_REG (Pmode, 11);
15571 emit_move_insn (offset_rtx, int_rtx);
15573 replacea = offset_rtx;
15574 replaceb = int_rtx;
15578 offset_rtx = int_rtx;
15579 replacea = NULL_RTX;
15580 replaceb = NULL_RTX;
15583 reg = gen_rtx_REG (mode, regno);
15584 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
15585 mem = gen_frame_mem (mode, addr);
15587 insn = emit_move_insn (mem, reg);
15589 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
15592 /* Emit an offset memory reference suitable for a frame store, while
15593 converting to a valid addressing mode. */
15596 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
15598 rtx int_rtx, offset_rtx;
15600 int_rtx = GEN_INT (offset);
15602 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
15603 || (TARGET_E500_DOUBLE && mode == DFmode))
15605 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15606 emit_move_insn (offset_rtx, int_rtx);
15609 offset_rtx = int_rtx;
15611 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
15614 /* Look for user-defined global regs. We should not save and restore these,
15615 and cannot use stmw/lmw if there are any in its range. */
15618 no_global_regs_above (int first, bool gpr)
15621 for (i = first; i < gpr ? 32 : 64 ; i++)
15622 if (global_regs[i])
15627 #ifndef TARGET_FIX_AND_CONTINUE
15628 #define TARGET_FIX_AND_CONTINUE 0
15631 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
15632 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
15633 #define LAST_SAVRES_REGISTER 31
15634 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
15636 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8];
15638 /* Return the symbol for an out-of-line register save/restore routine.
15639 We are saving/restoring GPRs if GPR is true. */
15642 rs6000_savres_routine_sym (rs6000_stack_t *info, bool savep, bool gpr, bool exitp)
15644 int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32);
15646 int select = ((savep ? 1 : 0) << 2
15648 /* On the SPE, we never have any FPRs, but we do have
15649 32/64-bit versions of the routines. */
15650 ? (TARGET_SPE_ABI && info->spe_64bit_regs_used ? 1 : 0)
15654 /* Don't generate bogus routine names. */
15655 gcc_assert (FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER);
15657 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
15662 const char *action;
15663 const char *regkind;
15664 const char *exit_suffix;
15666 action = savep ? "save" : "rest";
15668 /* SPE has slightly different names for its routines depending on
15669 whether we are saving 32-bit or 64-bit registers. */
15670 if (TARGET_SPE_ABI)
15672 /* No floating point saves on the SPE. */
15675 regkind = info->spe_64bit_regs_used ? "64gpr" : "32gpr";
15678 regkind = gpr ? "gpr" : "fpr";
15680 exit_suffix = exitp ? "_x" : "";
15682 sprintf (name, "_%s%s_%d%s", action, regkind, regno, exit_suffix);
15684 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
15685 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
15691 /* Emit a sequence of insns, including a stack tie if needed, for
15692 resetting the stack pointer. If SAVRES is true, then don't reset the
15693 stack pointer, but move the base of the frame into r11 for use by
15694 out-of-line register restore routines. */
15697 rs6000_emit_stack_reset (rs6000_stack_t *info,
15698 rtx sp_reg_rtx, rtx frame_reg_rtx,
15699 int sp_offset, bool savres)
15701 /* This blockage is needed so that sched doesn't decide to move
15702 the sp change before the register restores. */
15703 if (frame_reg_rtx != sp_reg_rtx
15705 && info->spe_64bit_regs_used != 0
15706 && info->first_gp_reg_save != 32))
15707 rs6000_emit_stack_tie ();
15709 if (frame_reg_rtx != sp_reg_rtx)
15711 rs6000_emit_stack_tie ();
15712 if (sp_offset != 0)
15713 emit_insn (gen_addsi3 (sp_reg_rtx, frame_reg_rtx,
15714 GEN_INT (sp_offset)));
15716 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15718 else if (sp_offset != 0)
15720 /* If we are restoring registers out-of-line, we will be using the
15721 "exit" variants of the restore routines, which will reset the
15722 stack for us. But we do need to point r11 into the right place
15723 for those routines. */
15724 rtx dest_reg = (savres
15725 ? gen_rtx_REG (Pmode, 11)
15728 emit_insn (TARGET_32BIT
15729 ? gen_addsi3 (dest_reg, sp_reg_rtx,
15730 GEN_INT (sp_offset))
15731 : gen_adddi3 (dest_reg, sp_reg_rtx,
15732 GEN_INT (sp_offset)));
15736 /* Construct a parallel rtx describing the effect of a call to an
15737 out-of-line register save/restore routine. */
15740 rs6000_make_savres_rtx (rs6000_stack_t *info,
15741 rtx frame_reg_rtx, int save_area_offset,
15742 enum machine_mode reg_mode,
15743 bool savep, bool gpr, bool exitp)
15746 int offset, start_reg, end_reg, n_regs;
15747 int reg_size = GET_MODE_SIZE (reg_mode);
15753 ? info->first_gp_reg_save
15754 : info->first_fp_reg_save);
15755 end_reg = gpr ? 32 : 64;
15756 n_regs = end_reg - start_reg;
15757 p = rtvec_alloc ((exitp ? 4 : 3) + n_regs);
15759 /* If we're saving registers, then we should never say we're exiting. */
15760 gcc_assert ((savep && !exitp) || !savep);
15763 RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode);
15765 RTVEC_ELT (p, offset++)
15766 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65));
15768 sym = rs6000_savres_routine_sym (info, savep, gpr, exitp);
15769 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
15770 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 11));
15772 for (i = 0; i < end_reg - start_reg; i++)
15774 rtx addr, reg, mem;
15775 reg = gen_rtx_REG (reg_mode, start_reg + i);
15776 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15777 GEN_INT (save_area_offset + reg_size*i));
15778 mem = gen_frame_mem (reg_mode, addr);
15780 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode,
15782 savep ? reg : mem);
15785 return gen_rtx_PARALLEL (VOIDmode, p);
15788 /* Determine whether the gp REG is really used. */
15791 rs6000_reg_live_or_pic_offset_p (int reg)
15793 return ((df_regs_ever_live_p (reg)
15794 && (!call_used_regs[reg]
15795 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15796 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15797 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15798 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15799 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
15803 SAVRES_MULTIPLE = 0x1,
15804 SAVRES_INLINE_FPRS = 0x2,
15805 SAVRES_INLINE_GPRS = 0x4
15808 /* Determine the strategy for savings/restoring registers. */
15811 rs6000_savres_strategy (rs6000_stack_t *info, bool savep,
15812 int using_static_chain_p, int sibcall)
15814 bool using_multiple_p;
15816 bool savres_fprs_inline;
15817 bool savres_gprs_inline;
15818 bool noclobber_global_gprs
15819 = no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true);
15821 using_multiple_p = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15822 && (!TARGET_SPE_ABI
15823 || info->spe_64bit_regs_used == 0)
15824 && info->first_gp_reg_save < 31
15825 && noclobber_global_gprs);
15826 /* Don't bother to try to save things out-of-line if r11 is occupied
15827 by the static chain. It would require too much fiddling and the
15828 static chain is rarely used anyway. */
15829 common = (using_static_chain_p
15831 || crtl->calls_eh_return
15832 || !info->lr_save_p
15833 || cfun->machine->ra_need_lr
15834 || info->total_size > 32767);
15835 savres_fprs_inline = (common
15836 || info->first_fp_reg_save == 64
15837 || !no_global_regs_above (info->first_fp_reg_save,
15839 || FP_SAVE_INLINE (info->first_fp_reg_save));
15840 savres_gprs_inline = (common
15841 /* Saving CR interferes with the exit routines
15842 used on the SPE, so just punt here. */
15845 && info->spe_64bit_regs_used != 0
15846 && info->cr_save_p != 0)
15847 || info->first_gp_reg_save == 32
15848 || !noclobber_global_gprs
15849 || GP_SAVE_INLINE (info->first_gp_reg_save));
15852 /* If we are going to use store multiple, then don't even bother
15853 with the out-of-line routines, since the store-multiple instruction
15854 will always be smaller. */
15855 savres_gprs_inline = savres_gprs_inline || using_multiple_p;
15858 /* The situation is more complicated with load multiple. We'd
15859 prefer to use the out-of-line routines for restores, since the
15860 "exit" out-of-line routines can handle the restore of LR and
15861 the frame teardown. But we can only use the out-of-line
15862 routines if we know that we've used store multiple or
15863 out-of-line routines in the prologue, i.e. if we've saved all
15864 the registers from first_gp_reg_save. Otherwise, we risk
15865 loading garbage from the stack. Furthermore, we can only use
15866 the "exit" out-of-line gpr restore if we haven't saved any
15868 bool saved_all = !savres_gprs_inline || using_multiple_p;
15870 if (saved_all && info->first_fp_reg_save != 64)
15871 /* We can't use the exit routine; use load multiple if it's
15873 savres_gprs_inline = savres_gprs_inline || using_multiple_p;
15876 return (using_multiple_p
15877 | (savres_fprs_inline << 1)
15878 | (savres_gprs_inline << 2));
15881 /* Emit function prologue as insns. */
15884 rs6000_emit_prologue (void)
15886 rs6000_stack_t *info = rs6000_stack_info ();
15887 enum machine_mode reg_mode = Pmode;
15888 int reg_size = TARGET_32BIT ? 4 : 8;
15889 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15890 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
15891 rtx frame_reg_rtx = sp_reg_rtx;
15892 rtx cr_save_rtx = NULL_RTX;
15895 int saving_FPRs_inline;
15896 int saving_GPRs_inline;
15897 int using_store_multiple;
15898 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15899 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15900 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15901 HOST_WIDE_INT sp_offset = 0;
15903 if (TARGET_FIX_AND_CONTINUE)
15905 /* gdb on darwin arranges to forward a function from the old
15906 address by modifying the first 5 instructions of the function
15907 to branch to the overriding function. This is necessary to
15908 permit function pointers that point to the old function to
15909 actually forward to the new function. */
15910 emit_insn (gen_nop ());
15911 emit_insn (gen_nop ());
15912 emit_insn (gen_nop ());
15913 emit_insn (gen_nop ());
15914 emit_insn (gen_nop ());
15917 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15919 reg_mode = V2SImode;
15923 strategy = rs6000_savres_strategy (info, /*savep=*/true,
15924 /*static_chain_p=*/using_static_chain_p,
15926 using_store_multiple = strategy & SAVRES_MULTIPLE;
15927 saving_FPRs_inline = strategy & SAVRES_INLINE_FPRS;
15928 saving_GPRs_inline = strategy & SAVRES_INLINE_GPRS;
15930 /* For V.4, update stack before we do any saving and set back pointer. */
15931 if (! WORLD_SAVE_P (info)
15933 && (DEFAULT_ABI == ABI_V4
15934 || crtl->calls_eh_return))
15936 bool need_r11 = (TARGET_SPE
15937 ? (!saving_GPRs_inline
15938 && info->spe_64bit_regs_used == 0)
15939 : (!saving_FPRs_inline || !saving_GPRs_inline));
15940 if (info->total_size < 32767)
15941 sp_offset = info->total_size;
15943 frame_reg_rtx = (need_r11
15944 ? gen_rtx_REG (Pmode, 11)
15946 rs6000_emit_allocate_stack (info->total_size,
15947 (frame_reg_rtx != sp_reg_rtx
15948 && (info->cr_save_p
15950 || info->first_fp_reg_save < 64
15951 || info->first_gp_reg_save < 32
15954 if (frame_reg_rtx != sp_reg_rtx)
15955 rs6000_emit_stack_tie ();
15958 /* Handle world saves specially here. */
15959 if (WORLD_SAVE_P (info))
15966 /* save_world expects lr in r0. */
15967 reg0 = gen_rtx_REG (Pmode, 0);
15968 if (info->lr_save_p)
15970 insn = emit_move_insn (reg0,
15971 gen_rtx_REG (Pmode, LR_REGNO));
15972 RTX_FRAME_RELATED_P (insn) = 1;
15975 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15976 assumptions about the offsets of various bits of the stack
15978 gcc_assert (info->gp_save_offset == -220
15979 && info->fp_save_offset == -144
15980 && info->lr_save_offset == 8
15981 && info->cr_save_offset == 4
15984 && (!crtl->calls_eh_return
15985 || info->ehrd_offset == -432)
15986 && info->vrsave_save_offset == -224
15987 && info->altivec_save_offset == -416);
15989 treg = gen_rtx_REG (SImode, 11);
15990 emit_move_insn (treg, GEN_INT (-info->total_size));
15992 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15993 in R11. It also clobbers R12, so beware! */
15995 /* Preserve CR2 for save_world prologues */
15997 sz += 32 - info->first_gp_reg_save;
15998 sz += 64 - info->first_fp_reg_save;
15999 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
16000 p = rtvec_alloc (sz);
16002 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
16003 gen_rtx_REG (SImode,
16005 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
16006 gen_rtx_SYMBOL_REF (Pmode,
16008 /* We do floats first so that the instruction pattern matches
16010 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16012 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
16013 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16014 GEN_INT (info->fp_save_offset
16015 + sp_offset + 8 * i));
16016 rtx mem = gen_frame_mem (DFmode, addr);
16018 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16020 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16022 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16023 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16024 GEN_INT (info->altivec_save_offset
16025 + sp_offset + 16 * i));
16026 rtx mem = gen_frame_mem (V4SImode, addr);
16028 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16030 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16032 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16033 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16034 GEN_INT (info->gp_save_offset
16035 + sp_offset + reg_size * i));
16036 rtx mem = gen_frame_mem (reg_mode, addr);
16038 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16042 /* CR register traditionally saved as CR2. */
16043 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16044 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16045 GEN_INT (info->cr_save_offset
16047 rtx mem = gen_frame_mem (reg_mode, addr);
16049 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16051 /* Explain about use of R0. */
16052 if (info->lr_save_p)
16054 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16055 GEN_INT (info->lr_save_offset
16057 rtx mem = gen_frame_mem (reg_mode, addr);
16059 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
16061 /* Explain what happens to the stack pointer. */
16063 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
16064 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
16067 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16068 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16069 treg, GEN_INT (-info->total_size));
16070 sp_offset = info->total_size;
16073 /* If we use the link register, get it into r0. */
16074 if (!WORLD_SAVE_P (info) && info->lr_save_p)
16076 rtx addr, reg, mem;
16078 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
16079 gen_rtx_REG (Pmode, LR_REGNO));
16080 RTX_FRAME_RELATED_P (insn) = 1;
16082 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16083 GEN_INT (info->lr_save_offset + sp_offset));
16084 reg = gen_rtx_REG (Pmode, 0);
16085 mem = gen_rtx_MEM (Pmode, addr);
16086 /* This should not be of rs6000_sr_alias_set, because of
16087 __builtin_return_address. */
16089 insn = emit_move_insn (mem, reg);
16090 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16091 NULL_RTX, NULL_RTX);
16094 /* If we need to save CR, put it into r12. */
16095 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
16099 cr_save_rtx = gen_rtx_REG (SImode, 12);
16100 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
16101 RTX_FRAME_RELATED_P (insn) = 1;
16102 /* Now, there's no way that dwarf2out_frame_debug_expr is going
16103 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
16104 But that's OK. All we have to do is specify that _one_ condition
16105 code register is saved in this stack slot. The thrower's epilogue
16106 will then restore all the call-saved registers.
16107 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
16108 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
16109 gen_rtx_REG (SImode, CR2_REGNO));
16110 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
16115 /* Do any required saving of fpr's. If only one or two to save, do
16116 it ourselves. Otherwise, call function. */
16117 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
16120 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16121 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
16122 && ! call_used_regs[info->first_fp_reg_save+i]))
16123 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
16124 info->first_fp_reg_save + i,
16125 info->fp_save_offset + sp_offset + 8 * i,
16128 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
16132 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
16133 info->fp_save_offset + sp_offset,
16135 /*savep=*/true, /*gpr=*/false,
16137 insn = emit_insn (par);
16138 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16139 NULL_RTX, NULL_RTX);
16142 /* Save GPRs. This is done as a PARALLEL if we are using
16143 the store-multiple instructions. */
16144 if (!WORLD_SAVE_P (info)
16146 && info->spe_64bit_regs_used != 0
16147 && info->first_gp_reg_save != 32)
16150 rtx spe_save_area_ptr;
16152 /* Determine whether we can address all of the registers that need
16153 to be saved with an offset from the stack pointer that fits in
16154 the small const field for SPE memory instructions. */
16155 int spe_regs_addressable_via_sp
16156 = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
16157 + (32 - info->first_gp_reg_save - 1) * reg_size)
16158 && saving_GPRs_inline);
16161 if (spe_regs_addressable_via_sp)
16163 spe_save_area_ptr = frame_reg_rtx;
16164 spe_offset = info->spe_gp_save_offset + sp_offset;
16168 /* Make r11 point to the start of the SPE save area. We need
16169 to be careful here if r11 is holding the static chain. If
16170 it is, then temporarily save it in r0. We would use r0 as
16171 our base register here, but using r0 as a base register in
16172 loads and stores means something different from what we
16174 int ool_adjust = (saving_GPRs_inline
16176 : (info->first_gp_reg_save
16177 - (FIRST_SAVRES_REGISTER+1))*8);
16178 HOST_WIDE_INT offset = (info->spe_gp_save_offset
16179 + sp_offset - ool_adjust);
16181 if (using_static_chain_p)
16183 rtx r0 = gen_rtx_REG (Pmode, 0);
16184 gcc_assert (info->first_gp_reg_save > 11);
16186 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
16189 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
16190 insn = emit_insn (gen_addsi3 (spe_save_area_ptr,
16192 GEN_INT (offset)));
16193 /* We need to make sure the move to r11 gets noted for
16194 properly outputting unwind information. */
16195 if (!saving_GPRs_inline)
16196 rs6000_frame_related (insn, frame_reg_rtx, offset,
16197 NULL_RTX, NULL_RTX);
16201 if (saving_GPRs_inline)
16203 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16204 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16206 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16207 rtx offset, addr, mem;
16209 /* We're doing all this to ensure that the offset fits into
16210 the immediate offset of 'evstdd'. */
16211 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
16213 offset = GEN_INT (reg_size * i + spe_offset);
16214 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
16215 mem = gen_rtx_MEM (V2SImode, addr);
16217 insn = emit_move_insn (mem, reg);
16219 rs6000_frame_related (insn, spe_save_area_ptr,
16220 info->spe_gp_save_offset
16221 + sp_offset + reg_size * i,
16222 offset, const0_rtx);
16229 par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
16231 /*savep=*/true, /*gpr=*/true,
16233 insn = emit_insn (par);
16234 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16235 NULL_RTX, NULL_RTX);
16239 /* Move the static chain pointer back. */
16240 if (using_static_chain_p && !spe_regs_addressable_via_sp)
16241 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
16243 else if (!WORLD_SAVE_P (info) && !saving_GPRs_inline)
16247 /* Need to adjust r11 if we saved any FPRs. */
16248 if (info->first_fp_reg_save != 64)
16250 rtx r11 = gen_rtx_REG (reg_mode, 11);
16251 rtx offset = GEN_INT (info->total_size
16252 + (-8 * (64-info->first_fp_reg_save)));
16253 rtx ptr_reg = (sp_reg_rtx == frame_reg_rtx
16254 ? sp_reg_rtx : r11);
16256 emit_insn (TARGET_32BIT
16257 ? gen_addsi3 (r11, ptr_reg, offset)
16258 : gen_adddi3 (r11, ptr_reg, offset));
16261 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
16262 info->gp_save_offset + sp_offset,
16264 /*savep=*/true, /*gpr=*/true,
16266 insn = emit_insn (par);
16267 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16268 NULL_RTX, NULL_RTX);
16270 else if (!WORLD_SAVE_P (info) && using_store_multiple)
16274 p = rtvec_alloc (32 - info->first_gp_reg_save);
16275 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16277 rtx addr, reg, mem;
16278 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16279 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16280 GEN_INT (info->gp_save_offset
16283 mem = gen_frame_mem (reg_mode, addr);
16285 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
16287 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16288 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16289 NULL_RTX, NULL_RTX);
16291 else if (!WORLD_SAVE_P (info))
16294 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16295 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16297 rtx addr, reg, mem;
16298 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16300 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16301 GEN_INT (info->gp_save_offset
16304 mem = gen_frame_mem (reg_mode, addr);
16306 insn = emit_move_insn (mem, reg);
16307 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16308 NULL_RTX, NULL_RTX);
16312 /* ??? There's no need to emit actual instructions here, but it's the
16313 easiest way to get the frame unwind information emitted. */
16314 if (crtl->calls_eh_return)
16316 unsigned int i, regno;
16318 /* In AIX ABI we need to pretend we save r2 here. */
16321 rtx addr, reg, mem;
16323 reg = gen_rtx_REG (reg_mode, 2);
16324 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16325 GEN_INT (sp_offset + 5 * reg_size));
16326 mem = gen_frame_mem (reg_mode, addr);
16328 insn = emit_move_insn (mem, reg);
16329 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16330 NULL_RTX, NULL_RTX);
16331 PATTERN (insn) = gen_blockage ();
16336 regno = EH_RETURN_DATA_REGNO (i);
16337 if (regno == INVALID_REGNUM)
16340 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
16341 info->ehrd_offset + sp_offset
16342 + reg_size * (int) i,
16347 /* Save CR if we use any that must be preserved. */
16348 if (!WORLD_SAVE_P (info) && info->cr_save_p)
16350 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16351 GEN_INT (info->cr_save_offset + sp_offset));
16352 rtx mem = gen_frame_mem (SImode, addr);
16353 /* See the large comment above about why CR2_REGNO is used. */
16354 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
16356 /* If r12 was used to hold the original sp, copy cr into r0 now
16358 if (REGNO (frame_reg_rtx) == 12)
16362 cr_save_rtx = gen_rtx_REG (SImode, 0);
16363 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
16364 RTX_FRAME_RELATED_P (insn) = 1;
16365 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
16366 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
16371 insn = emit_move_insn (mem, cr_save_rtx);
16373 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16374 NULL_RTX, NULL_RTX);
16377 /* Update stack and set back pointer unless this is V.4,
16378 for which it was done previously. */
16379 if (!WORLD_SAVE_P (info) && info->push_p
16380 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
16382 if (info->total_size < 32767)
16383 sp_offset = info->total_size;
16385 frame_reg_rtx = frame_ptr_rtx;
16386 rs6000_emit_allocate_stack (info->total_size,
16387 (frame_reg_rtx != sp_reg_rtx
16388 && ((info->altivec_size != 0)
16389 || (info->vrsave_mask != 0)
16392 if (frame_reg_rtx != sp_reg_rtx)
16393 rs6000_emit_stack_tie ();
16396 /* Set frame pointer, if needed. */
16397 if (frame_pointer_needed)
16399 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
16401 RTX_FRAME_RELATED_P (insn) = 1;
16404 /* Save AltiVec registers if needed. Save here because the red zone does
16405 not include AltiVec registers. */
16406 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
16410 /* There should be a non inline version of this, for when we
16411 are saving lots of vector registers. */
16412 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16413 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16415 rtx areg, savereg, mem;
16418 offset = info->altivec_save_offset + sp_offset
16419 + 16 * (i - info->first_altivec_reg_save);
16421 savereg = gen_rtx_REG (V4SImode, i);
16423 areg = gen_rtx_REG (Pmode, 0);
16424 emit_move_insn (areg, GEN_INT (offset));
16426 /* AltiVec addressing mode is [reg+reg]. */
16427 mem = gen_frame_mem (V4SImode,
16428 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
16430 insn = emit_move_insn (mem, savereg);
16432 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16433 areg, GEN_INT (offset));
16437 /* VRSAVE is a bit vector representing which AltiVec registers
16438 are used. The OS uses this to determine which vector
16439 registers to save on a context switch. We need to save
16440 VRSAVE on the stack frame, add whatever AltiVec registers we
16441 used in this function, and do the corresponding magic in the
16444 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
16445 && info->vrsave_mask != 0)
16447 rtx reg, mem, vrsave;
16450 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16451 as frame_reg_rtx and r11 as the static chain pointer for
16452 nested functions. */
16453 reg = gen_rtx_REG (SImode, 0);
16454 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
16456 emit_insn (gen_get_vrsave_internal (reg));
16458 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
16460 if (!WORLD_SAVE_P (info))
16463 offset = info->vrsave_save_offset + sp_offset;
16464 mem = gen_frame_mem (SImode,
16465 gen_rtx_PLUS (Pmode, frame_reg_rtx,
16466 GEN_INT (offset)));
16467 insn = emit_move_insn (mem, reg);
16470 /* Include the registers in the mask. */
16471 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
16473 insn = emit_insn (generate_set_vrsave (reg, info, 0));
16476 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16477 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
16478 || (DEFAULT_ABI == ABI_V4
16479 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
16480 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
16482 /* If emit_load_toc_table will use the link register, we need to save
16483 it. We use R12 for this purpose because emit_load_toc_table
16484 can use register 0. This allows us to use a plain 'blr' to return
16485 from the procedure more often. */
16486 int save_LR_around_toc_setup = (TARGET_ELF
16487 && DEFAULT_ABI != ABI_AIX
16489 && ! info->lr_save_p
16490 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
16491 if (save_LR_around_toc_setup)
16493 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16495 insn = emit_move_insn (frame_ptr_rtx, lr);
16496 RTX_FRAME_RELATED_P (insn) = 1;
16498 rs6000_emit_load_toc_table (TRUE);
16500 insn = emit_move_insn (lr, frame_ptr_rtx);
16501 RTX_FRAME_RELATED_P (insn) = 1;
16504 rs6000_emit_load_toc_table (TRUE);
16508 if (DEFAULT_ABI == ABI_DARWIN
16509 && flag_pic && crtl->uses_pic_offset_table)
16511 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16512 rtx src = machopic_function_base_sym ();
16514 /* Save and restore LR locally around this call (in R0). */
16515 if (!info->lr_save_p)
16516 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
16518 emit_insn (gen_load_macho_picbase (src));
16520 emit_move_insn (gen_rtx_REG (Pmode,
16521 RS6000_PIC_OFFSET_TABLE_REGNUM),
16524 if (!info->lr_save_p)
16525 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
16530 /* Write function prologue. */
16533 rs6000_output_function_prologue (FILE *file,
16534 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
16536 rs6000_stack_t *info = rs6000_stack_info ();
16538 if (TARGET_DEBUG_STACK)
16539 debug_stack_info (info);
16541 /* Write .extern for any function we will call to save and restore
16543 if (info->first_fp_reg_save < 64
16544 && !FP_SAVE_INLINE (info->first_fp_reg_save))
16545 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16546 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
16547 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
16549 /* Write .extern for AIX common mode routines, if needed. */
16550 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
16552 fputs ("\t.extern __mulh\n", file);
16553 fputs ("\t.extern __mull\n", file);
16554 fputs ("\t.extern __divss\n", file);
16555 fputs ("\t.extern __divus\n", file);
16556 fputs ("\t.extern __quoss\n", file);
16557 fputs ("\t.extern __quous\n", file);
16558 common_mode_defined = 1;
16561 if (! HAVE_prologue)
16565 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16566 the "toplevel" insn chain. */
16567 emit_note (NOTE_INSN_DELETED);
16568 rs6000_emit_prologue ();
16569 emit_note (NOTE_INSN_DELETED);
16571 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16575 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16577 INSN_ADDRESSES_NEW (insn, addr);
16582 if (TARGET_DEBUG_STACK)
16583 debug_rtx_list (get_insns (), 100);
16584 final (get_insns (), file, FALSE);
16588 rs6000_pic_labelno++;
16591 /* Non-zero if vmx regs are restored before the frame pop, zero if
16592 we restore after the pop when possible. */
16593 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
16595 /* Reload CR from REG. */
16598 rs6000_restore_saved_cr (rtx reg, int using_mfcr_multiple)
16603 if (using_mfcr_multiple)
16605 for (i = 0; i < 8; i++)
16606 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16608 gcc_assert (count);
16611 if (using_mfcr_multiple && count > 1)
16616 p = rtvec_alloc (count);
16619 for (i = 0; i < 8; i++)
16620 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16622 rtvec r = rtvec_alloc (2);
16623 RTVEC_ELT (r, 0) = reg;
16624 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
16625 RTVEC_ELT (p, ndx) =
16626 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
16627 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
16630 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16631 gcc_assert (ndx == count);
16634 for (i = 0; i < 8; i++)
16635 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16637 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
16643 /* Emit function epilogue as insns.
16645 At present, dwarf2out_frame_debug_expr doesn't understand
16646 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16647 anywhere in the epilogue. Most of the insns below would in any case
16648 need special notes to explain where r11 is in relation to the stack. */
16651 rs6000_emit_epilogue (int sibcall)
16653 rs6000_stack_t *info;
16654 int restoring_GPRs_inline;
16655 int restoring_FPRs_inline;
16656 int using_load_multiple;
16657 int using_mtcr_multiple;
16658 int use_backchain_to_restore_sp;
16662 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
16663 rtx frame_reg_rtx = sp_reg_rtx;
16664 enum machine_mode reg_mode = Pmode;
16665 int reg_size = TARGET_32BIT ? 4 : 8;
16668 info = rs6000_stack_info ();
16670 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
16672 reg_mode = V2SImode;
16676 strategy = rs6000_savres_strategy (info, /*savep=*/false,
16677 /*static_chain_p=*/0, sibcall);
16678 using_load_multiple = strategy & SAVRES_MULTIPLE;
16679 restoring_FPRs_inline = strategy & SAVRES_INLINE_FPRS;
16680 restoring_GPRs_inline = strategy & SAVRES_INLINE_GPRS;
16681 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
16682 || rs6000_cpu == PROCESSOR_PPC603
16683 || rs6000_cpu == PROCESSOR_PPC750
16685 /* Restore via the backchain when we have a large frame, since this
16686 is more efficient than an addis, addi pair. The second condition
16687 here will not trigger at the moment; We don't actually need a
16688 frame pointer for alloca, but the generic parts of the compiler
16689 give us one anyway. */
16690 use_backchain_to_restore_sp = (info->total_size > 32767
16691 || info->total_size
16692 + (info->lr_save_p ? info->lr_save_offset : 0)
16694 || (cfun->calls_alloca
16695 && !frame_pointer_needed));
16696 restore_lr = (info->lr_save_p
16697 && restoring_GPRs_inline
16698 && restoring_FPRs_inline);
16700 if (WORLD_SAVE_P (info))
16704 const char *alloc_rname;
16707 /* eh_rest_world_r10 will return to the location saved in the LR
16708 stack slot (which is not likely to be our caller.)
16709 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16710 rest_world is similar, except any R10 parameter is ignored.
16711 The exception-handling stuff that was here in 2.95 is no
16712 longer necessary. */
16716 + 32 - info->first_gp_reg_save
16717 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
16718 + 63 + 1 - info->first_fp_reg_save);
16720 strcpy (rname, ((crtl->calls_eh_return) ?
16721 "*eh_rest_world_r10" : "*rest_world"));
16722 alloc_rname = ggc_strdup (rname);
16725 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
16726 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
16727 gen_rtx_REG (Pmode,
16730 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
16731 /* The instruction pattern requires a clobber here;
16732 it is shared with the restVEC helper. */
16734 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
16737 /* CR register traditionally saved as CR2. */
16738 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16739 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16740 GEN_INT (info->cr_save_offset));
16741 rtx mem = gen_frame_mem (reg_mode, addr);
16743 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16746 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16748 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16749 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16750 GEN_INT (info->gp_save_offset
16752 rtx mem = gen_frame_mem (reg_mode, addr);
16754 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16756 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16758 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16759 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16760 GEN_INT (info->altivec_save_offset
16762 rtx mem = gen_frame_mem (V4SImode, addr);
16764 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16766 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
16768 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
16769 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16770 GEN_INT (info->fp_save_offset
16772 rtx mem = gen_frame_mem (DFmode, addr);
16774 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16777 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
16779 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
16781 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
16783 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
16785 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
16786 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
16791 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
16793 sp_offset = info->total_size;
16795 /* Restore AltiVec registers if we must do so before adjusting the
16797 if (TARGET_ALTIVEC_ABI
16798 && info->altivec_size != 0
16799 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16800 || (DEFAULT_ABI != ABI_V4
16801 && info->altivec_save_offset < (TARGET_32BIT ? -220 : -288))))
16805 if (use_backchain_to_restore_sp)
16807 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16808 emit_move_insn (frame_reg_rtx,
16809 gen_rtx_MEM (Pmode, sp_reg_rtx));
16812 else if (frame_pointer_needed)
16813 frame_reg_rtx = hard_frame_pointer_rtx;
16815 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16816 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16818 rtx addr, areg, mem;
16820 areg = gen_rtx_REG (Pmode, 0);
16822 (areg, GEN_INT (info->altivec_save_offset
16824 + 16 * (i - info->first_altivec_reg_save)));
16826 /* AltiVec addressing mode is [reg+reg]. */
16827 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
16828 mem = gen_frame_mem (V4SImode, addr);
16830 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
16834 /* Restore VRSAVE if we must do so before adjusting the stack. */
16836 && TARGET_ALTIVEC_VRSAVE
16837 && info->vrsave_mask != 0
16838 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16839 || (DEFAULT_ABI != ABI_V4
16840 && info->vrsave_save_offset < (TARGET_32BIT ? -220 : -288))))
16842 rtx addr, mem, reg;
16844 if (frame_reg_rtx == sp_reg_rtx)
16846 if (use_backchain_to_restore_sp)
16848 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16849 emit_move_insn (frame_reg_rtx,
16850 gen_rtx_MEM (Pmode, sp_reg_rtx));
16853 else if (frame_pointer_needed)
16854 frame_reg_rtx = hard_frame_pointer_rtx;
16857 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16858 GEN_INT (info->vrsave_save_offset + sp_offset));
16859 mem = gen_frame_mem (SImode, addr);
16860 reg = gen_rtx_REG (SImode, 12);
16861 emit_move_insn (reg, mem);
16863 emit_insn (generate_set_vrsave (reg, info, 1));
16866 /* If we have a large stack frame, restore the old stack pointer
16867 using the backchain. */
16868 if (use_backchain_to_restore_sp)
16870 if (frame_reg_rtx == sp_reg_rtx)
16872 /* Under V.4, don't reset the stack pointer until after we're done
16873 loading the saved registers. */
16874 if (DEFAULT_ABI == ABI_V4)
16875 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16877 emit_move_insn (frame_reg_rtx,
16878 gen_rtx_MEM (Pmode, sp_reg_rtx));
16881 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16882 && DEFAULT_ABI == ABI_V4)
16883 /* frame_reg_rtx has been set up by the altivec restore. */
16887 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
16888 frame_reg_rtx = sp_reg_rtx;
16891 /* If we have a frame pointer, we can restore the old stack pointer
16893 else if (frame_pointer_needed)
16895 frame_reg_rtx = sp_reg_rtx;
16896 if (DEFAULT_ABI == ABI_V4)
16897 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16899 emit_insn (TARGET_32BIT
16900 ? gen_addsi3 (frame_reg_rtx, hard_frame_pointer_rtx,
16901 GEN_INT (info->total_size))
16902 : gen_adddi3 (frame_reg_rtx, hard_frame_pointer_rtx,
16903 GEN_INT (info->total_size)));
16906 else if (info->push_p
16907 && DEFAULT_ABI != ABI_V4
16908 && !crtl->calls_eh_return)
16910 emit_insn (TARGET_32BIT
16911 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16912 GEN_INT (info->total_size))
16913 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16914 GEN_INT (info->total_size)));
16918 /* Restore AltiVec registers if we have not done so already. */
16919 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16920 && TARGET_ALTIVEC_ABI
16921 && info->altivec_size != 0
16922 && (DEFAULT_ABI == ABI_V4
16923 || info->altivec_save_offset >= (TARGET_32BIT ? -220 : -288)))
16927 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16928 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16930 rtx addr, areg, mem;
16932 areg = gen_rtx_REG (Pmode, 0);
16934 (areg, GEN_INT (info->altivec_save_offset
16936 + 16 * (i - info->first_altivec_reg_save)));
16938 /* AltiVec addressing mode is [reg+reg]. */
16939 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
16940 mem = gen_frame_mem (V4SImode, addr);
16942 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
16946 /* Restore VRSAVE if we have not done so already. */
16947 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16949 && TARGET_ALTIVEC_VRSAVE
16950 && info->vrsave_mask != 0
16951 && (DEFAULT_ABI == ABI_V4
16952 || info->vrsave_save_offset >= (TARGET_32BIT ? -220 : -288)))
16954 rtx addr, mem, reg;
16956 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16957 GEN_INT (info->vrsave_save_offset + sp_offset));
16958 mem = gen_frame_mem (SImode, addr);
16959 reg = gen_rtx_REG (SImode, 12);
16960 emit_move_insn (reg, mem);
16962 emit_insn (generate_set_vrsave (reg, info, 1));
16965 /* Get the old lr if we saved it. If we are restoring registers
16966 out-of-line, then the out-of-line routines can do this for us. */
16969 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
16970 info->lr_save_offset + sp_offset);
16972 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
16975 /* Get the old cr if we saved it. */
16976 if (info->cr_save_p)
16978 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16979 GEN_INT (info->cr_save_offset + sp_offset));
16980 rtx mem = gen_frame_mem (SImode, addr);
16982 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
16985 /* Set LR here to try to overlap restores below. */
16987 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
16988 gen_rtx_REG (Pmode, 0));
16990 /* Load exception handler data registers, if needed. */
16991 if (crtl->calls_eh_return)
16993 unsigned int i, regno;
16997 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16998 GEN_INT (sp_offset + 5 * reg_size));
16999 rtx mem = gen_frame_mem (reg_mode, addr);
17001 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
17008 regno = EH_RETURN_DATA_REGNO (i);
17009 if (regno == INVALID_REGNUM)
17012 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
17013 info->ehrd_offset + sp_offset
17014 + reg_size * (int) i);
17016 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
17020 /* Restore GPRs. This is done as a PARALLEL if we are using
17021 the load-multiple instructions. */
17023 && info->spe_64bit_regs_used != 0
17024 && info->first_gp_reg_save != 32)
17026 /* Determine whether we can address all of the registers that need
17027 to be saved with an offset from the stack pointer that fits in
17028 the small const field for SPE memory instructions. */
17029 int spe_regs_addressable_via_sp
17030 = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
17031 + (32 - info->first_gp_reg_save - 1) * reg_size)
17032 && restoring_GPRs_inline);
17035 if (spe_regs_addressable_via_sp)
17036 spe_offset = info->spe_gp_save_offset + sp_offset;
17039 rtx old_frame_reg_rtx = frame_reg_rtx;
17040 /* Make r11 point to the start of the SPE save area. We worried about
17041 not clobbering it when we were saving registers in the prologue.
17042 There's no need to worry here because the static chain is passed
17043 anew to every function. */
17044 int ool_adjust = (restoring_GPRs_inline
17046 : (info->first_gp_reg_save
17047 - (FIRST_SAVRES_REGISTER+1))*8);
17049 if (frame_reg_rtx == sp_reg_rtx)
17050 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
17051 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
17052 GEN_INT (info->spe_gp_save_offset
17055 /* Keep the invariant that frame_reg_rtx + sp_offset points
17056 at the top of the stack frame. */
17057 sp_offset = -info->spe_gp_save_offset;
17062 if (restoring_GPRs_inline)
17064 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17065 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
17067 rtx offset, addr, mem;
17069 /* We're doing all this to ensure that the immediate offset
17070 fits into the immediate field of 'evldd'. */
17071 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
17073 offset = GEN_INT (spe_offset + reg_size * i);
17074 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
17075 mem = gen_rtx_MEM (V2SImode, addr);
17077 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
17085 par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
17087 /*savep=*/false, /*gpr=*/true,
17089 emit_jump_insn (par);
17091 /* We don't want anybody else emitting things after we jumped
17096 else if (!restoring_GPRs_inline)
17098 /* We are jumping to an out-of-line function. */
17099 bool can_use_exit = info->first_fp_reg_save == 64;
17102 /* Emit stack reset code if we need it. */
17104 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
17105 sp_offset, can_use_exit);
17107 emit_insn (gen_addsi3 (gen_rtx_REG (Pmode, 11),
17109 GEN_INT (sp_offset - info->fp_size)));
17111 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
17112 info->gp_save_offset, reg_mode,
17113 /*savep=*/false, /*gpr=*/true,
17114 /*exitp=*/can_use_exit);
17118 if (info->cr_save_p)
17119 rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12),
17120 using_mtcr_multiple);
17122 emit_jump_insn (par);
17124 /* We don't want anybody else emitting things after we jumped
17131 else if (using_load_multiple)
17134 p = rtvec_alloc (32 - info->first_gp_reg_save);
17135 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17137 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17138 GEN_INT (info->gp_save_offset
17141 rtx mem = gen_frame_mem (reg_mode, addr);
17144 gen_rtx_SET (VOIDmode,
17145 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
17148 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
17152 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17153 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
17155 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17156 GEN_INT (info->gp_save_offset
17159 rtx mem = gen_frame_mem (reg_mode, addr);
17161 emit_move_insn (gen_rtx_REG (reg_mode,
17162 info->first_gp_reg_save + i), mem);
17166 /* Restore fpr's if we need to do it without calling a function. */
17167 if (restoring_FPRs_inline)
17168 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
17169 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
17170 && ! call_used_regs[info->first_fp_reg_save+i]))
17173 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17174 GEN_INT (info->fp_save_offset
17177 mem = gen_frame_mem (DFmode, addr);
17179 emit_move_insn (gen_rtx_REG (DFmode,
17180 info->first_fp_reg_save + i),
17184 /* If we saved cr, restore it here. Just those that were used. */
17185 if (info->cr_save_p)
17186 rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12), using_mtcr_multiple);
17188 /* If this is V.4, unwind the stack pointer after all of the loads
17190 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
17191 sp_offset, !restoring_FPRs_inline);
17193 if (crtl->calls_eh_return)
17195 rtx sa = EH_RETURN_STACKADJ_RTX;
17196 emit_insn (TARGET_32BIT
17197 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
17198 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
17204 if (! restoring_FPRs_inline)
17205 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
17207 p = rtvec_alloc (2);
17209 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
17210 RTVEC_ELT (p, 1) = (restoring_FPRs_inline
17211 ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65))
17212 : gen_rtx_CLOBBER (VOIDmode,
17213 gen_rtx_REG (Pmode, 65)));
17215 /* If we have to restore more than two FP registers, branch to the
17216 restore function. It will return to our caller. */
17217 if (! restoring_FPRs_inline)
17222 sym = rs6000_savres_routine_sym (info,
17226 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
17227 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
17228 gen_rtx_REG (Pmode, 11));
17229 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
17232 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
17233 GEN_INT (info->fp_save_offset + 8*i));
17234 mem = gen_frame_mem (DFmode, addr);
17236 RTVEC_ELT (p, i+4) =
17237 gen_rtx_SET (VOIDmode,
17238 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
17243 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
17247 /* Write function epilogue. */
17250 rs6000_output_function_epilogue (FILE *file,
17251 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
17253 if (! HAVE_epilogue)
17255 rtx insn = get_last_insn ();
17256 /* If the last insn was a BARRIER, we don't have to write anything except
17257 the trace table. */
17258 if (GET_CODE (insn) == NOTE)
17259 insn = prev_nonnote_insn (insn);
17260 if (insn == 0 || GET_CODE (insn) != BARRIER)
17262 /* This is slightly ugly, but at least we don't have two
17263 copies of the epilogue-emitting code. */
17266 /* A NOTE_INSN_DELETED is supposed to be at the start
17267 and end of the "toplevel" insn chain. */
17268 emit_note (NOTE_INSN_DELETED);
17269 rs6000_emit_epilogue (FALSE);
17270 emit_note (NOTE_INSN_DELETED);
17272 /* Expand INSN_ADDRESSES so final() doesn't crash. */
17276 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
17278 INSN_ADDRESSES_NEW (insn, addr);
17283 if (TARGET_DEBUG_STACK)
17284 debug_rtx_list (get_insns (), 100);
17285 final (get_insns (), file, FALSE);
17291 macho_branch_islands ();
17292 /* Mach-O doesn't support labels at the end of objects, so if
17293 it looks like we might want one, insert a NOP. */
17295 rtx insn = get_last_insn ();
17298 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
17299 insn = PREV_INSN (insn);
17303 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
17304 fputs ("\tnop\n", file);
17308 /* Output a traceback table here. See /usr/include/sys/debug.h for info
17311 We don't output a traceback table if -finhibit-size-directive was
17312 used. The documentation for -finhibit-size-directive reads
17313 ``don't output a @code{.size} assembler directive, or anything
17314 else that would cause trouble if the function is split in the
17315 middle, and the two halves are placed at locations far apart in
17316 memory.'' The traceback table has this property, since it
17317 includes the offset from the start of the function to the
17318 traceback table itself.
17320 System V.4 Powerpc's (and the embedded ABI derived from it) use a
17321 different traceback table. */
17322 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
17323 && rs6000_traceback != traceback_none && !crtl->is_thunk)
17325 const char *fname = NULL;
17326 const char *language_string = lang_hooks.name;
17327 int fixed_parms = 0, float_parms = 0, parm_info = 0;
17329 int optional_tbtab;
17330 rs6000_stack_t *info = rs6000_stack_info ();
17332 if (rs6000_traceback == traceback_full)
17333 optional_tbtab = 1;
17334 else if (rs6000_traceback == traceback_part)
17335 optional_tbtab = 0;
17337 optional_tbtab = !optimize_size && !TARGET_ELF;
17339 if (optional_tbtab)
17341 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
17342 while (*fname == '.') /* V.4 encodes . in the name */
17345 /* Need label immediately before tbtab, so we can compute
17346 its offset from the function start. */
17347 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
17348 ASM_OUTPUT_LABEL (file, fname);
17351 /* The .tbtab pseudo-op can only be used for the first eight
17352 expressions, since it can't handle the possibly variable
17353 length fields that follow. However, if you omit the optional
17354 fields, the assembler outputs zeros for all optional fields
17355 anyways, giving each variable length field is minimum length
17356 (as defined in sys/debug.h). Thus we can not use the .tbtab
17357 pseudo-op at all. */
17359 /* An all-zero word flags the start of the tbtab, for debuggers
17360 that have to find it by searching forward from the entry
17361 point or from the current pc. */
17362 fputs ("\t.long 0\n", file);
17364 /* Tbtab format type. Use format type 0. */
17365 fputs ("\t.byte 0,", file);
17367 /* Language type. Unfortunately, there does not seem to be any
17368 official way to discover the language being compiled, so we
17369 use language_string.
17370 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
17371 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
17372 a number, so for now use 9. */
17373 if (! strcmp (language_string, "GNU C"))
17375 else if (! strcmp (language_string, "GNU F77")
17376 || ! strcmp (language_string, "GNU Fortran"))
17378 else if (! strcmp (language_string, "GNU Pascal"))
17380 else if (! strcmp (language_string, "GNU Ada"))
17382 else if (! strcmp (language_string, "GNU C++")
17383 || ! strcmp (language_string, "GNU Objective-C++"))
17385 else if (! strcmp (language_string, "GNU Java"))
17387 else if (! strcmp (language_string, "GNU Objective-C"))
17390 gcc_unreachable ();
17391 fprintf (file, "%d,", i);
17393 /* 8 single bit fields: global linkage (not set for C extern linkage,
17394 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
17395 from start of procedure stored in tbtab, internal function, function
17396 has controlled storage, function has no toc, function uses fp,
17397 function logs/aborts fp operations. */
17398 /* Assume that fp operations are used if any fp reg must be saved. */
17399 fprintf (file, "%d,",
17400 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
17402 /* 6 bitfields: function is interrupt handler, name present in
17403 proc table, function calls alloca, on condition directives
17404 (controls stack walks, 3 bits), saves condition reg, saves
17406 /* The `function calls alloca' bit seems to be set whenever reg 31 is
17407 set up as a frame pointer, even when there is no alloca call. */
17408 fprintf (file, "%d,",
17409 ((optional_tbtab << 6)
17410 | ((optional_tbtab & frame_pointer_needed) << 5)
17411 | (info->cr_save_p << 1)
17412 | (info->lr_save_p)));
17414 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
17416 fprintf (file, "%d,",
17417 (info->push_p << 7) | (64 - info->first_fp_reg_save));
17419 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
17420 fprintf (file, "%d,", (32 - first_reg_to_save ()));
17422 if (optional_tbtab)
17424 /* Compute the parameter info from the function decl argument
17427 int next_parm_info_bit = 31;
17429 for (decl = DECL_ARGUMENTS (current_function_decl);
17430 decl; decl = TREE_CHAIN (decl))
17432 rtx parameter = DECL_INCOMING_RTL (decl);
17433 enum machine_mode mode = GET_MODE (parameter);
17435 if (GET_CODE (parameter) == REG)
17437 if (SCALAR_FLOAT_MODE_P (mode))
17458 gcc_unreachable ();
17461 /* If only one bit will fit, don't or in this entry. */
17462 if (next_parm_info_bit > 0)
17463 parm_info |= (bits << (next_parm_info_bit - 1));
17464 next_parm_info_bit -= 2;
17468 fixed_parms += ((GET_MODE_SIZE (mode)
17469 + (UNITS_PER_WORD - 1))
17471 next_parm_info_bit -= 1;
17477 /* Number of fixed point parameters. */
17478 /* This is actually the number of words of fixed point parameters; thus
17479 an 8 byte struct counts as 2; and thus the maximum value is 8. */
17480 fprintf (file, "%d,", fixed_parms);
17482 /* 2 bitfields: number of floating point parameters (7 bits), parameters
17484 /* This is actually the number of fp registers that hold parameters;
17485 and thus the maximum value is 13. */
17486 /* Set parameters on stack bit if parameters are not in their original
17487 registers, regardless of whether they are on the stack? Xlc
17488 seems to set the bit when not optimizing. */
17489 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
17491 if (! optional_tbtab)
17494 /* Optional fields follow. Some are variable length. */
17496 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
17497 11 double float. */
17498 /* There is an entry for each parameter in a register, in the order that
17499 they occur in the parameter list. Any intervening arguments on the
17500 stack are ignored. If the list overflows a long (max possible length
17501 34 bits) then completely leave off all elements that don't fit. */
17502 /* Only emit this long if there was at least one parameter. */
17503 if (fixed_parms || float_parms)
17504 fprintf (file, "\t.long %d\n", parm_info);
17506 /* Offset from start of code to tb table. */
17507 fputs ("\t.long ", file);
17508 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
17510 RS6000_OUTPUT_BASENAME (file, fname);
17512 assemble_name (file, fname);
17514 rs6000_output_function_entry (file, fname);
17517 /* Interrupt handler mask. */
17518 /* Omit this long, since we never set the interrupt handler bit
17521 /* Number of CTL (controlled storage) anchors. */
17522 /* Omit this long, since the has_ctl bit is never set above. */
17524 /* Displacement into stack of each CTL anchor. */
17525 /* Omit this list of longs, because there are no CTL anchors. */
17527 /* Length of function name. */
17530 fprintf (file, "\t.short %d\n", (int) strlen (fname));
17532 /* Function name. */
17533 assemble_string (fname, strlen (fname));
17535 /* Register for alloca automatic storage; this is always reg 31.
17536 Only emit this if the alloca bit was set above. */
17537 if (frame_pointer_needed)
17538 fputs ("\t.byte 31\n", file);
17540 fputs ("\t.align 2\n", file);
17544 /* A C compound statement that outputs the assembler code for a thunk
17545 function, used to implement C++ virtual function calls with
17546 multiple inheritance. The thunk acts as a wrapper around a virtual
17547 function, adjusting the implicit object parameter before handing
17548 control off to the real function.
17550 First, emit code to add the integer DELTA to the location that
17551 contains the incoming first argument. Assume that this argument
17552 contains a pointer, and is the one used to pass the `this' pointer
17553 in C++. This is the incoming argument *before* the function
17554 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17555 values of all other incoming arguments.
17557 After the addition, emit code to jump to FUNCTION, which is a
17558 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17559 not touch the return address. Hence returning from FUNCTION will
17560 return to whoever called the current `thunk'.
17562 The effect must be as if FUNCTION had been called directly with the
17563 adjusted first argument. This macro is responsible for emitting
17564 all of the code for a thunk function; output_function_prologue()
17565 and output_function_epilogue() are not invoked.
17567 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17568 been extracted from it.) It might possibly be useful on some
17569 targets, but probably not.
17571 If you do not define this macro, the target-independent code in the
17572 C++ frontend will generate a less efficient heavyweight thunk that
17573 calls FUNCTION instead of jumping to it. The generic approach does
17574 not support varargs. */
17577 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
17578 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
17581 rtx this, insn, funexp;
17583 reload_completed = 1;
17584 epilogue_completed = 1;
17586 /* Mark the end of the (empty) prologue. */
17587 emit_note (NOTE_INSN_PROLOGUE_END);
17589 /* Find the "this" pointer. If the function returns a structure,
17590 the structure return pointer is in r3. */
17591 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
17592 this = gen_rtx_REG (Pmode, 4);
17594 this = gen_rtx_REG (Pmode, 3);
17596 /* Apply the constant offset, if required. */
17599 rtx delta_rtx = GEN_INT (delta);
17600 emit_insn (TARGET_32BIT
17601 ? gen_addsi3 (this, this, delta_rtx)
17602 : gen_adddi3 (this, this, delta_rtx));
17605 /* Apply the offset from the vtable, if required. */
17608 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
17609 rtx tmp = gen_rtx_REG (Pmode, 12);
17611 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
17612 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
17614 emit_insn (TARGET_32BIT
17615 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
17616 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
17617 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
17621 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
17623 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
17625 emit_insn (TARGET_32BIT
17626 ? gen_addsi3 (this, this, tmp)
17627 : gen_adddi3 (this, this, tmp));
17630 /* Generate a tail call to the target function. */
17631 if (!TREE_USED (function))
17633 assemble_external (function);
17634 TREE_USED (function) = 1;
17636 funexp = XEXP (DECL_RTL (function), 0);
17637 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
17640 if (MACHOPIC_INDIRECT)
17641 funexp = machopic_indirect_call_target (funexp);
17644 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17645 generate sibcall RTL explicitly. */
17646 insn = emit_call_insn (
17647 gen_rtx_PARALLEL (VOIDmode,
17649 gen_rtx_CALL (VOIDmode,
17650 funexp, const0_rtx),
17651 gen_rtx_USE (VOIDmode, const0_rtx),
17652 gen_rtx_USE (VOIDmode,
17653 gen_rtx_REG (SImode,
17655 gen_rtx_RETURN (VOIDmode))));
17656 SIBLING_CALL_P (insn) = 1;
17659 /* Run just enough of rest_of_compilation to get the insns emitted.
17660 There's not really enough bulk here to make other passes such as
17661 instruction scheduling worth while. Note that use_thunk calls
17662 assemble_start_function and assemble_end_function. */
17663 insn = get_insns ();
17664 insn_locators_alloc ();
17665 shorten_branches (insn);
17666 final_start_function (insn, file, 1);
17667 final (insn, file, 1);
17668 final_end_function ();
17669 free_after_compilation (cfun);
17671 reload_completed = 0;
17672 epilogue_completed = 0;
17675 /* A quick summary of the various types of 'constant-pool tables'
17678 Target Flags Name One table per
17679 AIX (none) AIX TOC object file
17680 AIX -mfull-toc AIX TOC object file
17681 AIX -mminimal-toc AIX minimal TOC translation unit
17682 SVR4/EABI (none) SVR4 SDATA object file
17683 SVR4/EABI -fpic SVR4 pic object file
17684 SVR4/EABI -fPIC SVR4 PIC translation unit
17685 SVR4/EABI -mrelocatable EABI TOC function
17686 SVR4/EABI -maix AIX TOC object file
17687 SVR4/EABI -maix -mminimal-toc
17688 AIX minimal TOC translation unit
17690 Name Reg. Set by entries contains:
17691 made by addrs? fp? sum?
17693 AIX TOC 2 crt0 as Y option option
17694 AIX minimal TOC 30 prolog gcc Y Y option
17695 SVR4 SDATA 13 crt0 gcc N Y N
17696 SVR4 pic 30 prolog ld Y not yet N
17697 SVR4 PIC 30 prolog gcc Y option option
17698 EABI TOC 30 prolog gcc Y option option
17702 /* Hash functions for the hash table. */
17705 rs6000_hash_constant (rtx k)
17707 enum rtx_code code = GET_CODE (k);
17708 enum machine_mode mode = GET_MODE (k);
17709 unsigned result = (code << 3) ^ mode;
17710 const char *format;
17713 format = GET_RTX_FORMAT (code);
17714 flen = strlen (format);
17720 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
17723 if (mode != VOIDmode)
17724 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
17736 for (; fidx < flen; fidx++)
17737 switch (format[fidx])
17742 const char *str = XSTR (k, fidx);
17743 len = strlen (str);
17744 result = result * 613 + len;
17745 for (i = 0; i < len; i++)
17746 result = result * 613 + (unsigned) str[i];
17751 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
17755 result = result * 613 + (unsigned) XINT (k, fidx);
17758 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
17759 result = result * 613 + (unsigned) XWINT (k, fidx);
17763 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
17764 result = result * 613 + (unsigned) (XWINT (k, fidx)
17771 gcc_unreachable ();
17778 toc_hash_function (const void *hash_entry)
17780 const struct toc_hash_struct *thc =
17781 (const struct toc_hash_struct *) hash_entry;
17782 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
17785 /* Compare H1 and H2 for equivalence. */
17788 toc_hash_eq (const void *h1, const void *h2)
17790 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
17791 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
17793 if (((const struct toc_hash_struct *) h1)->key_mode
17794 != ((const struct toc_hash_struct *) h2)->key_mode)
17797 return rtx_equal_p (r1, r2);
17800 /* These are the names given by the C++ front-end to vtables, and
17801 vtable-like objects. Ideally, this logic should not be here;
17802 instead, there should be some programmatic way of inquiring as
17803 to whether or not an object is a vtable. */
17805 #define VTABLE_NAME_P(NAME) \
17806 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
17807 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
17808 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
17809 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
17810 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
17813 rs6000_output_symbol_ref (FILE *file, rtx x)
17815 /* Currently C++ toc references to vtables can be emitted before it
17816 is decided whether the vtable is public or private. If this is
17817 the case, then the linker will eventually complain that there is
17818 a reference to an unknown section. Thus, for vtables only,
17819 we emit the TOC reference to reference the symbol and not the
17821 const char *name = XSTR (x, 0);
17823 if (VTABLE_NAME_P (name))
17825 RS6000_OUTPUT_BASENAME (file, name);
17828 assemble_name (file, name);
17831 /* Output a TOC entry. We derive the entry name from what is being
17835 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
17838 const char *name = buf;
17839 const char *real_name;
17841 HOST_WIDE_INT offset = 0;
17843 gcc_assert (!TARGET_NO_TOC);
17845 /* When the linker won't eliminate them, don't output duplicate
17846 TOC entries (this happens on AIX if there is any kind of TOC,
17847 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
17849 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
17851 struct toc_hash_struct *h;
17854 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
17855 time because GGC is not initialized at that point. */
17856 if (toc_hash_table == NULL)
17857 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17858 toc_hash_eq, NULL);
17860 h = GGC_NEW (struct toc_hash_struct);
17862 h->key_mode = mode;
17863 h->labelno = labelno;
17865 found = htab_find_slot (toc_hash_table, h, 1);
17866 if (*found == NULL)
17868 else /* This is indeed a duplicate.
17869 Set this label equal to that label. */
17871 fputs ("\t.set ", file);
17872 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17873 fprintf (file, "%d,", labelno);
17874 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17875 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
17881 /* If we're going to put a double constant in the TOC, make sure it's
17882 aligned properly when strict alignment is on. */
17883 if (GET_CODE (x) == CONST_DOUBLE
17884 && STRICT_ALIGNMENT
17885 && GET_MODE_BITSIZE (mode) >= 64
17886 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
17887 ASM_OUTPUT_ALIGN (file, 3);
17890 (*targetm.asm_out.internal_label) (file, "LC", labelno);
17892 /* Handle FP constants specially. Note that if we have a minimal
17893 TOC, things we put here aren't actually in the TOC, so we can allow
17895 if (GET_CODE (x) == CONST_DOUBLE &&
17896 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
17898 REAL_VALUE_TYPE rv;
17901 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17902 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17903 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
17905 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
17909 if (TARGET_MINIMAL_TOC)
17910 fputs (DOUBLE_INT_ASM_OP, file);
17912 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17913 k[0] & 0xffffffff, k[1] & 0xffffffff,
17914 k[2] & 0xffffffff, k[3] & 0xffffffff);
17915 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
17916 k[0] & 0xffffffff, k[1] & 0xffffffff,
17917 k[2] & 0xffffffff, k[3] & 0xffffffff);
17922 if (TARGET_MINIMAL_TOC)
17923 fputs ("\t.long ", file);
17925 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17926 k[0] & 0xffffffff, k[1] & 0xffffffff,
17927 k[2] & 0xffffffff, k[3] & 0xffffffff);
17928 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17929 k[0] & 0xffffffff, k[1] & 0xffffffff,
17930 k[2] & 0xffffffff, k[3] & 0xffffffff);
17934 else if (GET_CODE (x) == CONST_DOUBLE &&
17935 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
17937 REAL_VALUE_TYPE rv;
17940 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17942 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17943 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
17945 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
17949 if (TARGET_MINIMAL_TOC)
17950 fputs (DOUBLE_INT_ASM_OP, file);
17952 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17953 k[0] & 0xffffffff, k[1] & 0xffffffff);
17954 fprintf (file, "0x%lx%08lx\n",
17955 k[0] & 0xffffffff, k[1] & 0xffffffff);
17960 if (TARGET_MINIMAL_TOC)
17961 fputs ("\t.long ", file);
17963 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17964 k[0] & 0xffffffff, k[1] & 0xffffffff);
17965 fprintf (file, "0x%lx,0x%lx\n",
17966 k[0] & 0xffffffff, k[1] & 0xffffffff);
17970 else if (GET_CODE (x) == CONST_DOUBLE &&
17971 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
17973 REAL_VALUE_TYPE rv;
17976 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17977 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17978 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
17980 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
17984 if (TARGET_MINIMAL_TOC)
17985 fputs (DOUBLE_INT_ASM_OP, file);
17987 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17988 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
17993 if (TARGET_MINIMAL_TOC)
17994 fputs ("\t.long ", file);
17996 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17997 fprintf (file, "0x%lx\n", l & 0xffffffff);
18001 else if (GET_MODE (x) == VOIDmode
18002 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
18004 unsigned HOST_WIDE_INT low;
18005 HOST_WIDE_INT high;
18007 if (GET_CODE (x) == CONST_DOUBLE)
18009 low = CONST_DOUBLE_LOW (x);
18010 high = CONST_DOUBLE_HIGH (x);
18013 #if HOST_BITS_PER_WIDE_INT == 32
18016 high = (low & 0x80000000) ? ~0 : 0;
18020 low = INTVAL (x) & 0xffffffff;
18021 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
18025 /* TOC entries are always Pmode-sized, but since this
18026 is a bigendian machine then if we're putting smaller
18027 integer constants in the TOC we have to pad them.
18028 (This is still a win over putting the constants in
18029 a separate constant pool, because then we'd have
18030 to have both a TOC entry _and_ the actual constant.)
18032 For a 32-bit target, CONST_INT values are loaded and shifted
18033 entirely within `low' and can be stored in one TOC entry. */
18035 /* It would be easy to make this work, but it doesn't now. */
18036 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
18038 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
18040 #if HOST_BITS_PER_WIDE_INT == 32
18041 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
18042 POINTER_SIZE, &low, &high, 0);
18045 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
18046 high = (HOST_WIDE_INT) low >> 32;
18053 if (TARGET_MINIMAL_TOC)
18054 fputs (DOUBLE_INT_ASM_OP, file);
18056 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
18057 (long) high & 0xffffffff, (long) low & 0xffffffff);
18058 fprintf (file, "0x%lx%08lx\n",
18059 (long) high & 0xffffffff, (long) low & 0xffffffff);
18064 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
18066 if (TARGET_MINIMAL_TOC)
18067 fputs ("\t.long ", file);
18069 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
18070 (long) high & 0xffffffff, (long) low & 0xffffffff);
18071 fprintf (file, "0x%lx,0x%lx\n",
18072 (long) high & 0xffffffff, (long) low & 0xffffffff);
18076 if (TARGET_MINIMAL_TOC)
18077 fputs ("\t.long ", file);
18079 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
18080 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
18086 if (GET_CODE (x) == CONST)
18088 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
18090 base = XEXP (XEXP (x, 0), 0);
18091 offset = INTVAL (XEXP (XEXP (x, 0), 1));
18094 switch (GET_CODE (base))
18097 name = XSTR (base, 0);
18101 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
18102 CODE_LABEL_NUMBER (XEXP (base, 0)));
18106 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
18110 gcc_unreachable ();
18113 real_name = (*targetm.strip_name_encoding) (name);
18114 if (TARGET_MINIMAL_TOC)
18115 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
18118 fprintf (file, "\t.tc %s", real_name);
18121 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
18123 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
18125 fputs ("[TC],", file);
18128 /* Currently C++ toc references to vtables can be emitted before it
18129 is decided whether the vtable is public or private. If this is
18130 the case, then the linker will eventually complain that there is
18131 a TOC reference to an unknown section. Thus, for vtables only,
18132 we emit the TOC reference to reference the symbol and not the
18134 if (VTABLE_NAME_P (name))
18136 RS6000_OUTPUT_BASENAME (file, name);
18138 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
18139 else if (offset > 0)
18140 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
18143 output_addr_const (file, x);
18147 /* Output an assembler pseudo-op to write an ASCII string of N characters
18148 starting at P to FILE.
18150 On the RS/6000, we have to do this using the .byte operation and
18151 write out special characters outside the quoted string.
18152 Also, the assembler is broken; very long strings are truncated,
18153 so we must artificially break them up early. */
18156 output_ascii (FILE *file, const char *p, int n)
18159 int i, count_string;
18160 const char *for_string = "\t.byte \"";
18161 const char *for_decimal = "\t.byte ";
18162 const char *to_close = NULL;
18165 for (i = 0; i < n; i++)
18168 if (c >= ' ' && c < 0177)
18171 fputs (for_string, file);
18174 /* Write two quotes to get one. */
18182 for_decimal = "\"\n\t.byte ";
18186 if (count_string >= 512)
18188 fputs (to_close, file);
18190 for_string = "\t.byte \"";
18191 for_decimal = "\t.byte ";
18199 fputs (for_decimal, file);
18200 fprintf (file, "%d", c);
18202 for_string = "\n\t.byte \"";
18203 for_decimal = ", ";
18209 /* Now close the string if we have written one. Then end the line. */
18211 fputs (to_close, file);
18214 /* Generate a unique section name for FILENAME for a section type
18215 represented by SECTION_DESC. Output goes into BUF.
18217 SECTION_DESC can be any string, as long as it is different for each
18218 possible section type.
18220 We name the section in the same manner as xlc. The name begins with an
18221 underscore followed by the filename (after stripping any leading directory
18222 names) with the last period replaced by the string SECTION_DESC. If
18223 FILENAME does not contain a period, SECTION_DESC is appended to the end of
18227 rs6000_gen_section_name (char **buf, const char *filename,
18228 const char *section_desc)
18230 const char *q, *after_last_slash, *last_period = 0;
18234 after_last_slash = filename;
18235 for (q = filename; *q; q++)
18238 after_last_slash = q + 1;
18239 else if (*q == '.')
18243 len = strlen (after_last_slash) + strlen (section_desc) + 2;
18244 *buf = (char *) xmalloc (len);
18249 for (q = after_last_slash; *q; q++)
18251 if (q == last_period)
18253 strcpy (p, section_desc);
18254 p += strlen (section_desc);
18258 else if (ISALNUM (*q))
18262 if (last_period == 0)
18263 strcpy (p, section_desc);
18268 /* Emit profile function. */
18271 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
18273 /* Non-standard profiling for kernels, which just saves LR then calls
18274 _mcount without worrying about arg saves. The idea is to change
18275 the function prologue as little as possible as it isn't easy to
18276 account for arg save/restore code added just for _mcount. */
18277 if (TARGET_PROFILE_KERNEL)
18280 if (DEFAULT_ABI == ABI_AIX)
18282 #ifndef NO_PROFILE_COUNTERS
18283 # define NO_PROFILE_COUNTERS 0
18285 if (NO_PROFILE_COUNTERS)
18286 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
18290 const char *label_name;
18293 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
18294 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
18295 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
18297 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
18301 else if (DEFAULT_ABI == ABI_DARWIN)
18303 const char *mcount_name = RS6000_MCOUNT;
18304 int caller_addr_regno = LR_REGNO;
18306 /* Be conservative and always set this, at least for now. */
18307 crtl->uses_pic_offset_table = 1;
18310 /* For PIC code, set up a stub and collect the caller's address
18311 from r0, which is where the prologue puts it. */
18312 if (MACHOPIC_INDIRECT
18313 && crtl->uses_pic_offset_table)
18314 caller_addr_regno = 0;
18316 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
18318 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
18322 /* Write function profiler code. */
18325 output_function_profiler (FILE *file, int labelno)
18329 switch (DEFAULT_ABI)
18332 gcc_unreachable ();
18337 warning (0, "no profiling of 64-bit code for this ABI");
18340 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
18341 fprintf (file, "\tmflr %s\n", reg_names[0]);
18342 if (NO_PROFILE_COUNTERS)
18344 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18345 reg_names[0], reg_names[1]);
18347 else if (TARGET_SECURE_PLT && flag_pic)
18349 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
18350 reg_names[0], reg_names[1]);
18351 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
18352 asm_fprintf (file, "\t{cau|addis} %s,%s,",
18353 reg_names[12], reg_names[12]);
18354 assemble_name (file, buf);
18355 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
18356 assemble_name (file, buf);
18357 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
18359 else if (flag_pic == 1)
18361 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
18362 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18363 reg_names[0], reg_names[1]);
18364 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
18365 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
18366 assemble_name (file, buf);
18367 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
18369 else if (flag_pic > 1)
18371 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18372 reg_names[0], reg_names[1]);
18373 /* Now, we need to get the address of the label. */
18374 fputs ("\tbcl 20,31,1f\n\t.long ", file);
18375 assemble_name (file, buf);
18376 fputs ("-.\n1:", file);
18377 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
18378 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
18379 reg_names[0], reg_names[11]);
18380 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
18381 reg_names[0], reg_names[0], reg_names[11]);
18385 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
18386 assemble_name (file, buf);
18387 fputs ("@ha\n", file);
18388 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18389 reg_names[0], reg_names[1]);
18390 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
18391 assemble_name (file, buf);
18392 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
18395 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
18396 fprintf (file, "\tbl %s%s\n",
18397 RS6000_MCOUNT, flag_pic ? "@plt" : "");
18402 if (!TARGET_PROFILE_KERNEL)
18404 /* Don't do anything, done in output_profile_hook (). */
18408 gcc_assert (!TARGET_32BIT);
18410 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
18411 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
18413 if (cfun->static_chain_decl != NULL)
18415 asm_fprintf (file, "\tstd %s,24(%s)\n",
18416 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
18417 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
18418 asm_fprintf (file, "\tld %s,24(%s)\n",
18419 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
18422 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
18430 /* The following variable value is the last issued insn. */
18432 static rtx last_scheduled_insn;
18434 /* The following variable helps to balance issuing of load and
18435 store instructions */
18437 static int load_store_pendulum;
18439 /* Power4 load update and store update instructions are cracked into a
18440 load or store and an integer insn which are executed in the same cycle.
18441 Branches have their own dispatch slot which does not count against the
18442 GCC issue rate, but it changes the program flow so there are no other
18443 instructions to issue in this cycle. */
18446 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
18447 int verbose ATTRIBUTE_UNUSED,
18448 rtx insn, int more)
18450 last_scheduled_insn = insn;
18451 if (GET_CODE (PATTERN (insn)) == USE
18452 || GET_CODE (PATTERN (insn)) == CLOBBER)
18454 cached_can_issue_more = more;
18455 return cached_can_issue_more;
18458 if (insn_terminates_group_p (insn, current_group))
18460 cached_can_issue_more = 0;
18461 return cached_can_issue_more;
18464 /* If no reservation, but reach here */
18465 if (recog_memoized (insn) < 0)
18468 if (rs6000_sched_groups)
18470 if (is_microcoded_insn (insn))
18471 cached_can_issue_more = 0;
18472 else if (is_cracked_insn (insn))
18473 cached_can_issue_more = more > 2 ? more - 2 : 0;
18475 cached_can_issue_more = more - 1;
18477 return cached_can_issue_more;
18480 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
18483 cached_can_issue_more = more - 1;
18484 return cached_can_issue_more;
18487 /* Adjust the cost of a scheduling dependency. Return the new cost of
18488 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
18491 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
18493 enum attr_type attr_type;
18495 if (! recog_memoized (insn))
18498 switch (REG_NOTE_KIND (link))
18502 /* Data dependency; DEP_INSN writes a register that INSN reads
18503 some cycles later. */
18505 /* Separate a load from a narrower, dependent store. */
18506 if (rs6000_sched_groups
18507 && GET_CODE (PATTERN (insn)) == SET
18508 && GET_CODE (PATTERN (dep_insn)) == SET
18509 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
18510 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
18511 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
18512 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
18515 attr_type = get_attr_type (insn);
18520 /* Tell the first scheduling pass about the latency between
18521 a mtctr and bctr (and mtlr and br/blr). The first
18522 scheduling pass will not know about this latency since
18523 the mtctr instruction, which has the latency associated
18524 to it, will be generated by reload. */
18525 return TARGET_POWER ? 5 : 4;
18527 /* Leave some extra cycles between a compare and its
18528 dependent branch, to inhibit expensive mispredicts. */
18529 if ((rs6000_cpu_attr == CPU_PPC603
18530 || rs6000_cpu_attr == CPU_PPC604
18531 || rs6000_cpu_attr == CPU_PPC604E
18532 || rs6000_cpu_attr == CPU_PPC620
18533 || rs6000_cpu_attr == CPU_PPC630
18534 || rs6000_cpu_attr == CPU_PPC750
18535 || rs6000_cpu_attr == CPU_PPC7400
18536 || rs6000_cpu_attr == CPU_PPC7450
18537 || rs6000_cpu_attr == CPU_POWER4
18538 || rs6000_cpu_attr == CPU_POWER5
18539 || rs6000_cpu_attr == CPU_CELL)
18540 && recog_memoized (dep_insn)
18541 && (INSN_CODE (dep_insn) >= 0))
18543 switch (get_attr_type (dep_insn))
18547 case TYPE_DELAYED_COMPARE:
18548 case TYPE_IMUL_COMPARE:
18549 case TYPE_LMUL_COMPARE:
18550 case TYPE_FPCOMPARE:
18551 case TYPE_CR_LOGICAL:
18552 case TYPE_DELAYED_CR:
18561 case TYPE_STORE_UX:
18563 case TYPE_FPSTORE_U:
18564 case TYPE_FPSTORE_UX:
18565 if ((rs6000_cpu == PROCESSOR_POWER6)
18566 && recog_memoized (dep_insn)
18567 && (INSN_CODE (dep_insn) >= 0))
18570 if (GET_CODE (PATTERN (insn)) != SET)
18571 /* If this happens, we have to extend this to schedule
18572 optimally. Return default for now. */
18575 /* Adjust the cost for the case where the value written
18576 by a fixed point operation is used as the address
18577 gen value on a store. */
18578 switch (get_attr_type (dep_insn))
18585 if (! store_data_bypass_p (dep_insn, insn))
18589 case TYPE_LOAD_EXT:
18590 case TYPE_LOAD_EXT_U:
18591 case TYPE_LOAD_EXT_UX:
18592 case TYPE_VAR_SHIFT_ROTATE:
18593 case TYPE_VAR_DELAYED_COMPARE:
18595 if (! store_data_bypass_p (dep_insn, insn))
18601 case TYPE_FAST_COMPARE:
18604 case TYPE_INSERT_WORD:
18605 case TYPE_INSERT_DWORD:
18606 case TYPE_FPLOAD_U:
18607 case TYPE_FPLOAD_UX:
18609 case TYPE_STORE_UX:
18610 case TYPE_FPSTORE_U:
18611 case TYPE_FPSTORE_UX:
18613 if (! store_data_bypass_p (dep_insn, insn))
18621 case TYPE_IMUL_COMPARE:
18622 case TYPE_LMUL_COMPARE:
18624 if (! store_data_bypass_p (dep_insn, insn))
18630 if (! store_data_bypass_p (dep_insn, insn))
18636 if (! store_data_bypass_p (dep_insn, insn))
18649 case TYPE_LOAD_EXT:
18650 case TYPE_LOAD_EXT_U:
18651 case TYPE_LOAD_EXT_UX:
18652 if ((rs6000_cpu == PROCESSOR_POWER6)
18653 && recog_memoized (dep_insn)
18654 && (INSN_CODE (dep_insn) >= 0))
18657 /* Adjust the cost for the case where the value written
18658 by a fixed point instruction is used within the address
18659 gen portion of a subsequent load(u)(x) */
18660 switch (get_attr_type (dep_insn))
18667 if (set_to_load_agen (dep_insn, insn))
18671 case TYPE_LOAD_EXT:
18672 case TYPE_LOAD_EXT_U:
18673 case TYPE_LOAD_EXT_UX:
18674 case TYPE_VAR_SHIFT_ROTATE:
18675 case TYPE_VAR_DELAYED_COMPARE:
18677 if (set_to_load_agen (dep_insn, insn))
18683 case TYPE_FAST_COMPARE:
18686 case TYPE_INSERT_WORD:
18687 case TYPE_INSERT_DWORD:
18688 case TYPE_FPLOAD_U:
18689 case TYPE_FPLOAD_UX:
18691 case TYPE_STORE_UX:
18692 case TYPE_FPSTORE_U:
18693 case TYPE_FPSTORE_UX:
18695 if (set_to_load_agen (dep_insn, insn))
18703 case TYPE_IMUL_COMPARE:
18704 case TYPE_LMUL_COMPARE:
18706 if (set_to_load_agen (dep_insn, insn))
18712 if (set_to_load_agen (dep_insn, insn))
18718 if (set_to_load_agen (dep_insn, insn))
18729 if ((rs6000_cpu == PROCESSOR_POWER6)
18730 && recog_memoized (dep_insn)
18731 && (INSN_CODE (dep_insn) >= 0)
18732 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
18739 /* Fall out to return default cost. */
18743 case REG_DEP_OUTPUT:
18744 /* Output dependency; DEP_INSN writes a register that INSN writes some
18746 if ((rs6000_cpu == PROCESSOR_POWER6)
18747 && recog_memoized (dep_insn)
18748 && (INSN_CODE (dep_insn) >= 0))
18750 attr_type = get_attr_type (insn);
18755 if (get_attr_type (dep_insn) == TYPE_FP)
18759 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
18767 /* Anti dependency; DEP_INSN reads a register that INSN writes some
18772 gcc_unreachable ();
18778 /* The function returns a true if INSN is microcoded.
18779 Return false otherwise. */
18782 is_microcoded_insn (rtx insn)
18784 if (!insn || !INSN_P (insn)
18785 || GET_CODE (PATTERN (insn)) == USE
18786 || GET_CODE (PATTERN (insn)) == CLOBBER)
18789 if (rs6000_cpu_attr == CPU_CELL)
18790 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
18792 if (rs6000_sched_groups)
18794 enum attr_type type = get_attr_type (insn);
18795 if (type == TYPE_LOAD_EXT_U
18796 || type == TYPE_LOAD_EXT_UX
18797 || type == TYPE_LOAD_UX
18798 || type == TYPE_STORE_UX
18799 || type == TYPE_MFCR)
18806 /* The function returns true if INSN is cracked into 2 instructions
18807 by the processor (and therefore occupies 2 issue slots). */
18810 is_cracked_insn (rtx insn)
18812 if (!insn || !INSN_P (insn)
18813 || GET_CODE (PATTERN (insn)) == USE
18814 || GET_CODE (PATTERN (insn)) == CLOBBER)
18817 if (rs6000_sched_groups)
18819 enum attr_type type = get_attr_type (insn);
18820 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
18821 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
18822 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
18823 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
18824 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
18825 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
18826 || type == TYPE_IDIV || type == TYPE_LDIV
18827 || type == TYPE_INSERT_WORD)
18834 /* The function returns true if INSN can be issued only from
18835 the branch slot. */
18838 is_branch_slot_insn (rtx insn)
18840 if (!insn || !INSN_P (insn)
18841 || GET_CODE (PATTERN (insn)) == USE
18842 || GET_CODE (PATTERN (insn)) == CLOBBER)
18845 if (rs6000_sched_groups)
18847 enum attr_type type = get_attr_type (insn);
18848 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
18856 /* The function returns true if out_inst sets a value that is
18857 used in the address generation computation of in_insn */
18859 set_to_load_agen (rtx out_insn, rtx in_insn)
18861 rtx out_set, in_set;
18863 /* For performance reasons, only handle the simple case where
18864 both loads are a single_set. */
18865 out_set = single_set (out_insn);
18868 in_set = single_set (in_insn);
18870 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
18876 /* The function returns true if the target storage location of
18877 out_insn is adjacent to the target storage location of in_insn */
18878 /* Return 1 if memory locations are adjacent. */
18881 adjacent_mem_locations (rtx insn1, rtx insn2)
18884 rtx a = get_store_dest (PATTERN (insn1));
18885 rtx b = get_store_dest (PATTERN (insn2));
18887 if ((GET_CODE (XEXP (a, 0)) == REG
18888 || (GET_CODE (XEXP (a, 0)) == PLUS
18889 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
18890 && (GET_CODE (XEXP (b, 0)) == REG
18891 || (GET_CODE (XEXP (b, 0)) == PLUS
18892 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
18894 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
18897 if (GET_CODE (XEXP (a, 0)) == PLUS)
18899 reg0 = XEXP (XEXP (a, 0), 0);
18900 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
18903 reg0 = XEXP (a, 0);
18905 if (GET_CODE (XEXP (b, 0)) == PLUS)
18907 reg1 = XEXP (XEXP (b, 0), 0);
18908 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
18911 reg1 = XEXP (b, 0);
18913 val_diff = val1 - val0;
18915 return ((REGNO (reg0) == REGNO (reg1))
18916 && ((MEM_SIZE (a) && val_diff == INTVAL (MEM_SIZE (a)))
18917 || (MEM_SIZE (b) && val_diff == -INTVAL (MEM_SIZE (b)))));
18923 /* A C statement (sans semicolon) to update the integer scheduling
18924 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18925 INSN earlier, reduce the priority to execute INSN later. Do not
18926 define this macro if you do not need to adjust the scheduling
18927 priorities of insns. */
18930 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
18932 /* On machines (like the 750) which have asymmetric integer units,
18933 where one integer unit can do multiply and divides and the other
18934 can't, reduce the priority of multiply/divide so it is scheduled
18935 before other integer operations. */
18938 if (! INSN_P (insn))
18941 if (GET_CODE (PATTERN (insn)) == USE)
18944 switch (rs6000_cpu_attr) {
18946 switch (get_attr_type (insn))
18953 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
18954 priority, priority);
18955 if (priority >= 0 && priority < 0x01000000)
18962 if (insn_must_be_first_in_group (insn)
18963 && reload_completed
18964 && current_sched_info->sched_max_insns_priority
18965 && rs6000_sched_restricted_insns_priority)
18968 /* Prioritize insns that can be dispatched only in the first
18970 if (rs6000_sched_restricted_insns_priority == 1)
18971 /* Attach highest priority to insn. This means that in
18972 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18973 precede 'priority' (critical path) considerations. */
18974 return current_sched_info->sched_max_insns_priority;
18975 else if (rs6000_sched_restricted_insns_priority == 2)
18976 /* Increase priority of insn by a minimal amount. This means that in
18977 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18978 considerations precede dispatch-slot restriction considerations. */
18979 return (priority + 1);
18982 if (rs6000_cpu == PROCESSOR_POWER6
18983 && ((load_store_pendulum == -2 && is_load_insn (insn))
18984 || (load_store_pendulum == 2 && is_store_insn (insn))))
18985 /* Attach highest priority to insn if the scheduler has just issued two
18986 stores and this instruction is a load, or two loads and this instruction
18987 is a store. Power6 wants loads and stores scheduled alternately
18989 return current_sched_info->sched_max_insns_priority;
18994 /* Return true if the instruction is nonpipelined on the Cell. */
18996 is_nonpipeline_insn (rtx insn)
18998 enum attr_type type;
18999 if (!insn || !INSN_P (insn)
19000 || GET_CODE (PATTERN (insn)) == USE
19001 || GET_CODE (PATTERN (insn)) == CLOBBER)
19004 type = get_attr_type (insn);
19005 if (type == TYPE_IMUL
19006 || type == TYPE_IMUL2
19007 || type == TYPE_IMUL3
19008 || type == TYPE_LMUL
19009 || type == TYPE_IDIV
19010 || type == TYPE_LDIV
19011 || type == TYPE_SDIV
19012 || type == TYPE_DDIV
19013 || type == TYPE_SSQRT
19014 || type == TYPE_DSQRT
19015 || type == TYPE_MFCR
19016 || type == TYPE_MFCRF
19017 || type == TYPE_MFJMPR)
19025 /* Return how many instructions the machine can issue per cycle. */
19028 rs6000_issue_rate (void)
19030 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
19031 if (!reload_completed)
19034 switch (rs6000_cpu_attr) {
19035 case CPU_RIOS1: /* ? */
19037 case CPU_PPC601: /* ? */
19046 case CPU_PPCE300C2:
19047 case CPU_PPCE300C3:
19048 case CPU_PPCE500MC:
19065 /* Return how many instructions to look ahead for better insn
19069 rs6000_use_sched_lookahead (void)
19071 if (rs6000_cpu_attr == CPU_PPC8540)
19073 if (rs6000_cpu_attr == CPU_CELL)
19074 return (reload_completed ? 8 : 0);
19078 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
19080 rs6000_use_sched_lookahead_guard (rtx insn)
19082 if (rs6000_cpu_attr != CPU_CELL)
19085 if (insn == NULL_RTX || !INSN_P (insn))
19088 if (!reload_completed
19089 || is_nonpipeline_insn (insn)
19090 || is_microcoded_insn (insn))
19096 /* Determine is PAT refers to memory. */
19099 is_mem_ref (rtx pat)
19105 /* stack_tie does not produce any real memory traffic. */
19106 if (GET_CODE (pat) == UNSPEC
19107 && XINT (pat, 1) == UNSPEC_TIE)
19110 if (GET_CODE (pat) == MEM)
19113 /* Recursively process the pattern. */
19114 fmt = GET_RTX_FORMAT (GET_CODE (pat));
19116 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
19119 ret |= is_mem_ref (XEXP (pat, i));
19120 else if (fmt[i] == 'E')
19121 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
19122 ret |= is_mem_ref (XVECEXP (pat, i, j));
19128 /* Determine if PAT is a PATTERN of a load insn. */
19131 is_load_insn1 (rtx pat)
19133 if (!pat || pat == NULL_RTX)
19136 if (GET_CODE (pat) == SET)
19137 return is_mem_ref (SET_SRC (pat));
19139 if (GET_CODE (pat) == PARALLEL)
19143 for (i = 0; i < XVECLEN (pat, 0); i++)
19144 if (is_load_insn1 (XVECEXP (pat, 0, i)))
19151 /* Determine if INSN loads from memory. */
19154 is_load_insn (rtx insn)
19156 if (!insn || !INSN_P (insn))
19159 if (GET_CODE (insn) == CALL_INSN)
19162 return is_load_insn1 (PATTERN (insn));
19165 /* Determine if PAT is a PATTERN of a store insn. */
19168 is_store_insn1 (rtx pat)
19170 if (!pat || pat == NULL_RTX)
19173 if (GET_CODE (pat) == SET)
19174 return is_mem_ref (SET_DEST (pat));
19176 if (GET_CODE (pat) == PARALLEL)
19180 for (i = 0; i < XVECLEN (pat, 0); i++)
19181 if (is_store_insn1 (XVECEXP (pat, 0, i)))
19188 /* Determine if INSN stores to memory. */
19191 is_store_insn (rtx insn)
19193 if (!insn || !INSN_P (insn))
19196 return is_store_insn1 (PATTERN (insn));
19199 /* Return the dest of a store insn. */
19202 get_store_dest (rtx pat)
19204 gcc_assert (is_store_insn1 (pat));
19206 if (GET_CODE (pat) == SET)
19207 return SET_DEST (pat);
19208 else if (GET_CODE (pat) == PARALLEL)
19212 for (i = 0; i < XVECLEN (pat, 0); i++)
19214 rtx inner_pat = XVECEXP (pat, 0, i);
19215 if (GET_CODE (inner_pat) == SET
19216 && is_mem_ref (SET_DEST (inner_pat)))
19220 /* We shouldn't get here, because we should have either a simple
19221 store insn or a store with update which are covered above. */
19225 /* Returns whether the dependence between INSN and NEXT is considered
19226 costly by the given target. */
19229 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
19234 /* If the flag is not enabled - no dependence is considered costly;
19235 allow all dependent insns in the same group.
19236 This is the most aggressive option. */
19237 if (rs6000_sched_costly_dep == no_dep_costly)
19240 /* If the flag is set to 1 - a dependence is always considered costly;
19241 do not allow dependent instructions in the same group.
19242 This is the most conservative option. */
19243 if (rs6000_sched_costly_dep == all_deps_costly)
19246 insn = DEP_PRO (dep);
19247 next = DEP_CON (dep);
19249 if (rs6000_sched_costly_dep == store_to_load_dep_costly
19250 && is_load_insn (next)
19251 && is_store_insn (insn))
19252 /* Prevent load after store in the same group. */
19255 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
19256 && is_load_insn (next)
19257 && is_store_insn (insn)
19258 && DEP_TYPE (dep) == REG_DEP_TRUE)
19259 /* Prevent load after store in the same group if it is a true
19263 /* The flag is set to X; dependences with latency >= X are considered costly,
19264 and will not be scheduled in the same group. */
19265 if (rs6000_sched_costly_dep <= max_dep_latency
19266 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
19272 /* Return the next insn after INSN that is found before TAIL is reached,
19273 skipping any "non-active" insns - insns that will not actually occupy
19274 an issue slot. Return NULL_RTX if such an insn is not found. */
19277 get_next_active_insn (rtx insn, rtx tail)
19279 if (insn == NULL_RTX || insn == tail)
19284 insn = NEXT_INSN (insn);
19285 if (insn == NULL_RTX || insn == tail)
19290 || (NONJUMP_INSN_P (insn)
19291 && GET_CODE (PATTERN (insn)) != USE
19292 && GET_CODE (PATTERN (insn)) != CLOBBER
19293 && INSN_CODE (insn) != CODE_FOR_stack_tie))
19299 /* We are about to begin issuing insns for this clock cycle. */
19302 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
19303 rtx *ready ATTRIBUTE_UNUSED,
19304 int *pn_ready ATTRIBUTE_UNUSED,
19305 int clock_var ATTRIBUTE_UNUSED)
19307 int n_ready = *pn_ready;
19310 fprintf (dump, "// rs6000_sched_reorder :\n");
19312 /* Reorder the ready list, if the second to last ready insn
19313 is a nonepipeline insn. */
19314 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
19316 if (is_nonpipeline_insn (ready[n_ready - 1])
19317 && (recog_memoized (ready[n_ready - 2]) > 0))
19318 /* Simply swap first two insns. */
19320 rtx tmp = ready[n_ready - 1];
19321 ready[n_ready - 1] = ready[n_ready - 2];
19322 ready[n_ready - 2] = tmp;
19326 if (rs6000_cpu == PROCESSOR_POWER6)
19327 load_store_pendulum = 0;
19329 return rs6000_issue_rate ();
19332 /* Like rs6000_sched_reorder, but called after issuing each insn. */
19335 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
19336 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
19339 fprintf (dump, "// rs6000_sched_reorder2 :\n");
19341 /* For Power6, we need to handle some special cases to try and keep the
19342 store queue from overflowing and triggering expensive flushes.
19344 This code monitors how load and store instructions are being issued
19345 and skews the ready list one way or the other to increase the likelihood
19346 that a desired instruction is issued at the proper time.
19348 A couple of things are done. First, we maintain a "load_store_pendulum"
19349 to track the current state of load/store issue.
19351 - If the pendulum is at zero, then no loads or stores have been
19352 issued in the current cycle so we do nothing.
19354 - If the pendulum is 1, then a single load has been issued in this
19355 cycle and we attempt to locate another load in the ready list to
19358 - If the pendulum is -2, then two stores have already been
19359 issued in this cycle, so we increase the priority of the first load
19360 in the ready list to increase it's likelihood of being chosen first
19363 - If the pendulum is -1, then a single store has been issued in this
19364 cycle and we attempt to locate another store in the ready list to
19365 issue with it, preferring a store to an adjacent memory location to
19366 facilitate store pairing in the store queue.
19368 - If the pendulum is 2, then two loads have already been
19369 issued in this cycle, so we increase the priority of the first store
19370 in the ready list to increase it's likelihood of being chosen first
19373 - If the pendulum < -2 or > 2, then do nothing.
19375 Note: This code covers the most common scenarios. There exist non
19376 load/store instructions which make use of the LSU and which
19377 would need to be accounted for to strictly model the behavior
19378 of the machine. Those instructions are currently unaccounted
19379 for to help minimize compile time overhead of this code.
19381 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
19387 if (is_store_insn (last_scheduled_insn))
19388 /* Issuing a store, swing the load_store_pendulum to the left */
19389 load_store_pendulum--;
19390 else if (is_load_insn (last_scheduled_insn))
19391 /* Issuing a load, swing the load_store_pendulum to the right */
19392 load_store_pendulum++;
19394 return cached_can_issue_more;
19396 /* If the pendulum is balanced, or there is only one instruction on
19397 the ready list, then all is well, so return. */
19398 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
19399 return cached_can_issue_more;
19401 if (load_store_pendulum == 1)
19403 /* A load has been issued in this cycle. Scan the ready list
19404 for another load to issue with it */
19409 if (is_load_insn (ready[pos]))
19411 /* Found a load. Move it to the head of the ready list,
19412 and adjust it's priority so that it is more likely to
19415 for (i=pos; i<*pn_ready-1; i++)
19416 ready[i] = ready[i + 1];
19417 ready[*pn_ready-1] = tmp;
19418 if INSN_PRIORITY_KNOWN (tmp)
19419 INSN_PRIORITY (tmp)++;
19425 else if (load_store_pendulum == -2)
19427 /* Two stores have been issued in this cycle. Increase the
19428 priority of the first load in the ready list to favor it for
19429 issuing in the next cycle. */
19434 if (is_load_insn (ready[pos])
19435 && INSN_PRIORITY_KNOWN (ready[pos]))
19437 INSN_PRIORITY (ready[pos])++;
19439 /* Adjust the pendulum to account for the fact that a load
19440 was found and increased in priority. This is to prevent
19441 increasing the priority of multiple loads */
19442 load_store_pendulum--;
19449 else if (load_store_pendulum == -1)
19451 /* A store has been issued in this cycle. Scan the ready list for
19452 another store to issue with it, preferring a store to an adjacent
19454 int first_store_pos = -1;
19460 if (is_store_insn (ready[pos]))
19462 /* Maintain the index of the first store found on the
19464 if (first_store_pos == -1)
19465 first_store_pos = pos;
19467 if (is_store_insn (last_scheduled_insn)
19468 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
19470 /* Found an adjacent store. Move it to the head of the
19471 ready list, and adjust it's priority so that it is
19472 more likely to stay there */
19474 for (i=pos; i<*pn_ready-1; i++)
19475 ready[i] = ready[i + 1];
19476 ready[*pn_ready-1] = tmp;
19477 if INSN_PRIORITY_KNOWN (tmp)
19478 INSN_PRIORITY (tmp)++;
19479 first_store_pos = -1;
19487 if (first_store_pos >= 0)
19489 /* An adjacent store wasn't found, but a non-adjacent store was,
19490 so move the non-adjacent store to the front of the ready
19491 list, and adjust its priority so that it is more likely to
19493 tmp = ready[first_store_pos];
19494 for (i=first_store_pos; i<*pn_ready-1; i++)
19495 ready[i] = ready[i + 1];
19496 ready[*pn_ready-1] = tmp;
19497 if INSN_PRIORITY_KNOWN (tmp)
19498 INSN_PRIORITY (tmp)++;
19501 else if (load_store_pendulum == 2)
19503 /* Two loads have been issued in this cycle. Increase the priority
19504 of the first store in the ready list to favor it for issuing in
19510 if (is_store_insn (ready[pos])
19511 && INSN_PRIORITY_KNOWN (ready[pos]))
19513 INSN_PRIORITY (ready[pos])++;
19515 /* Adjust the pendulum to account for the fact that a store
19516 was found and increased in priority. This is to prevent
19517 increasing the priority of multiple stores */
19518 load_store_pendulum++;
19527 return cached_can_issue_more;
19530 /* Return whether the presence of INSN causes a dispatch group termination
19531 of group WHICH_GROUP.
19533 If WHICH_GROUP == current_group, this function will return true if INSN
19534 causes the termination of the current group (i.e, the dispatch group to
19535 which INSN belongs). This means that INSN will be the last insn in the
19536 group it belongs to.
19538 If WHICH_GROUP == previous_group, this function will return true if INSN
19539 causes the termination of the previous group (i.e, the dispatch group that
19540 precedes the group to which INSN belongs). This means that INSN will be
19541 the first insn in the group it belongs to). */
19544 insn_terminates_group_p (rtx insn, enum group_termination which_group)
19551 first = insn_must_be_first_in_group (insn);
19552 last = insn_must_be_last_in_group (insn);
19557 if (which_group == current_group)
19559 else if (which_group == previous_group)
19567 insn_must_be_first_in_group (rtx insn)
19569 enum attr_type type;
19572 || insn == NULL_RTX
19573 || GET_CODE (insn) == NOTE
19574 || GET_CODE (PATTERN (insn)) == USE
19575 || GET_CODE (PATTERN (insn)) == CLOBBER)
19578 switch (rs6000_cpu)
19580 case PROCESSOR_POWER5:
19581 if (is_cracked_insn (insn))
19583 case PROCESSOR_POWER4:
19584 if (is_microcoded_insn (insn))
19587 if (!rs6000_sched_groups)
19590 type = get_attr_type (insn);
19597 case TYPE_DELAYED_CR:
19598 case TYPE_CR_LOGICAL:
19612 case PROCESSOR_POWER6:
19613 type = get_attr_type (insn);
19617 case TYPE_INSERT_DWORD:
19621 case TYPE_VAR_SHIFT_ROTATE:
19628 case TYPE_INSERT_WORD:
19629 case TYPE_DELAYED_COMPARE:
19630 case TYPE_IMUL_COMPARE:
19631 case TYPE_LMUL_COMPARE:
19632 case TYPE_FPCOMPARE:
19643 case TYPE_LOAD_EXT_UX:
19645 case TYPE_STORE_UX:
19646 case TYPE_FPLOAD_U:
19647 case TYPE_FPLOAD_UX:
19648 case TYPE_FPSTORE_U:
19649 case TYPE_FPSTORE_UX:
19663 insn_must_be_last_in_group (rtx insn)
19665 enum attr_type type;
19668 || insn == NULL_RTX
19669 || GET_CODE (insn) == NOTE
19670 || GET_CODE (PATTERN (insn)) == USE
19671 || GET_CODE (PATTERN (insn)) == CLOBBER)
19674 switch (rs6000_cpu) {
19675 case PROCESSOR_POWER4:
19676 case PROCESSOR_POWER5:
19677 if (is_microcoded_insn (insn))
19680 if (is_branch_slot_insn (insn))
19684 case PROCESSOR_POWER6:
19685 type = get_attr_type (insn);
19692 case TYPE_VAR_SHIFT_ROTATE:
19699 case TYPE_DELAYED_COMPARE:
19700 case TYPE_IMUL_COMPARE:
19701 case TYPE_LMUL_COMPARE:
19702 case TYPE_FPCOMPARE:
19723 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19724 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
19727 is_costly_group (rtx *group_insns, rtx next_insn)
19730 int issue_rate = rs6000_issue_rate ();
19732 for (i = 0; i < issue_rate; i++)
19734 sd_iterator_def sd_it;
19736 rtx insn = group_insns[i];
19741 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
19743 rtx next = DEP_CON (dep);
19745 if (next == next_insn
19746 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
19754 /* Utility of the function redefine_groups.
19755 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
19756 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
19757 to keep it "far" (in a separate group) from GROUP_INSNS, following
19758 one of the following schemes, depending on the value of the flag
19759 -minsert_sched_nops = X:
19760 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
19761 in order to force NEXT_INSN into a separate group.
19762 (2) X < sched_finish_regroup_exact: insert exactly X nops.
19763 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
19764 insertion (has a group just ended, how many vacant issue slots remain in the
19765 last group, and how many dispatch groups were encountered so far). */
19768 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
19769 rtx next_insn, bool *group_end, int can_issue_more,
19774 int issue_rate = rs6000_issue_rate ();
19775 bool end = *group_end;
19778 if (next_insn == NULL_RTX)
19779 return can_issue_more;
19781 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
19782 return can_issue_more;
19784 force = is_costly_group (group_insns, next_insn);
19786 return can_issue_more;
19788 if (sched_verbose > 6)
19789 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
19790 *group_count ,can_issue_more);
19792 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
19795 can_issue_more = 0;
19797 /* Since only a branch can be issued in the last issue_slot, it is
19798 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
19799 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
19800 in this case the last nop will start a new group and the branch
19801 will be forced to the new group. */
19802 if (can_issue_more && !is_branch_slot_insn (next_insn))
19805 while (can_issue_more > 0)
19808 emit_insn_before (nop, next_insn);
19816 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
19818 int n_nops = rs6000_sched_insert_nops;
19820 /* Nops can't be issued from the branch slot, so the effective
19821 issue_rate for nops is 'issue_rate - 1'. */
19822 if (can_issue_more == 0)
19823 can_issue_more = issue_rate;
19825 if (can_issue_more == 0)
19827 can_issue_more = issue_rate - 1;
19830 for (i = 0; i < issue_rate; i++)
19832 group_insns[i] = 0;
19839 emit_insn_before (nop, next_insn);
19840 if (can_issue_more == issue_rate - 1) /* new group begins */
19843 if (can_issue_more == 0)
19845 can_issue_more = issue_rate - 1;
19848 for (i = 0; i < issue_rate; i++)
19850 group_insns[i] = 0;
19856 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
19859 /* Is next_insn going to start a new group? */
19862 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19863 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19864 || (can_issue_more < issue_rate &&
19865 insn_terminates_group_p (next_insn, previous_group)));
19866 if (*group_end && end)
19869 if (sched_verbose > 6)
19870 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
19871 *group_count, can_issue_more);
19872 return can_issue_more;
19875 return can_issue_more;
19878 /* This function tries to synch the dispatch groups that the compiler "sees"
19879 with the dispatch groups that the processor dispatcher is expected to
19880 form in practice. It tries to achieve this synchronization by forcing the
19881 estimated processor grouping on the compiler (as opposed to the function
19882 'pad_goups' which tries to force the scheduler's grouping on the processor).
19884 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
19885 examines the (estimated) dispatch groups that will be formed by the processor
19886 dispatcher. It marks these group boundaries to reflect the estimated
19887 processor grouping, overriding the grouping that the scheduler had marked.
19888 Depending on the value of the flag '-minsert-sched-nops' this function can
19889 force certain insns into separate groups or force a certain distance between
19890 them by inserting nops, for example, if there exists a "costly dependence"
19893 The function estimates the group boundaries that the processor will form as
19894 follows: It keeps track of how many vacant issue slots are available after
19895 each insn. A subsequent insn will start a new group if one of the following
19897 - no more vacant issue slots remain in the current dispatch group.
19898 - only the last issue slot, which is the branch slot, is vacant, but the next
19899 insn is not a branch.
19900 - only the last 2 or less issue slots, including the branch slot, are vacant,
19901 which means that a cracked insn (which occupies two issue slots) can't be
19902 issued in this group.
19903 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19904 start a new group. */
19907 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19909 rtx insn, next_insn;
19911 int can_issue_more;
19914 int group_count = 0;
19918 issue_rate = rs6000_issue_rate ();
19919 group_insns = XALLOCAVEC (rtx, issue_rate);
19920 for (i = 0; i < issue_rate; i++)
19922 group_insns[i] = 0;
19924 can_issue_more = issue_rate;
19926 insn = get_next_active_insn (prev_head_insn, tail);
19929 while (insn != NULL_RTX)
19931 slot = (issue_rate - can_issue_more);
19932 group_insns[slot] = insn;
19934 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19935 if (insn_terminates_group_p (insn, current_group))
19936 can_issue_more = 0;
19938 next_insn = get_next_active_insn (insn, tail);
19939 if (next_insn == NULL_RTX)
19940 return group_count + 1;
19942 /* Is next_insn going to start a new group? */
19944 = (can_issue_more == 0
19945 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19946 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19947 || (can_issue_more < issue_rate &&
19948 insn_terminates_group_p (next_insn, previous_group)));
19950 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
19951 next_insn, &group_end, can_issue_more,
19957 can_issue_more = 0;
19958 for (i = 0; i < issue_rate; i++)
19960 group_insns[i] = 0;
19964 if (GET_MODE (next_insn) == TImode && can_issue_more)
19965 PUT_MODE (next_insn, VOIDmode);
19966 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
19967 PUT_MODE (next_insn, TImode);
19970 if (can_issue_more == 0)
19971 can_issue_more = issue_rate;
19974 return group_count;
19977 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19978 dispatch group boundaries that the scheduler had marked. Pad with nops
19979 any dispatch groups which have vacant issue slots, in order to force the
19980 scheduler's grouping on the processor dispatcher. The function
19981 returns the number of dispatch groups found. */
19984 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19986 rtx insn, next_insn;
19989 int can_issue_more;
19991 int group_count = 0;
19993 /* Initialize issue_rate. */
19994 issue_rate = rs6000_issue_rate ();
19995 can_issue_more = issue_rate;
19997 insn = get_next_active_insn (prev_head_insn, tail);
19998 next_insn = get_next_active_insn (insn, tail);
20000 while (insn != NULL_RTX)
20003 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
20005 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
20007 if (next_insn == NULL_RTX)
20012 /* If the scheduler had marked group termination at this location
20013 (between insn and next_indn), and neither insn nor next_insn will
20014 force group termination, pad the group with nops to force group
20017 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
20018 && !insn_terminates_group_p (insn, current_group)
20019 && !insn_terminates_group_p (next_insn, previous_group))
20021 if (!is_branch_slot_insn (next_insn))
20024 while (can_issue_more)
20027 emit_insn_before (nop, next_insn);
20032 can_issue_more = issue_rate;
20037 next_insn = get_next_active_insn (insn, tail);
20040 return group_count;
20043 /* We're beginning a new block. Initialize data structures as necessary. */
20046 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
20047 int sched_verbose ATTRIBUTE_UNUSED,
20048 int max_ready ATTRIBUTE_UNUSED)
20050 last_scheduled_insn = NULL_RTX;
20051 load_store_pendulum = 0;
20054 /* The following function is called at the end of scheduling BB.
20055 After reload, it inserts nops at insn group bundling. */
20058 rs6000_sched_finish (FILE *dump, int sched_verbose)
20063 fprintf (dump, "=== Finishing schedule.\n");
20065 if (reload_completed && rs6000_sched_groups)
20067 if (rs6000_sched_insert_nops == sched_finish_none)
20070 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
20071 n_groups = pad_groups (dump, sched_verbose,
20072 current_sched_info->prev_head,
20073 current_sched_info->next_tail);
20075 n_groups = redefine_groups (dump, sched_verbose,
20076 current_sched_info->prev_head,
20077 current_sched_info->next_tail);
20079 if (sched_verbose >= 6)
20081 fprintf (dump, "ngroups = %d\n", n_groups);
20082 print_rtl (dump, current_sched_info->prev_head);
20083 fprintf (dump, "Done finish_sched\n");
20088 /* Length in units of the trampoline for entering a nested function. */
20091 rs6000_trampoline_size (void)
20095 switch (DEFAULT_ABI)
20098 gcc_unreachable ();
20101 ret = (TARGET_32BIT) ? 12 : 24;
20106 ret = (TARGET_32BIT) ? 40 : 48;
20113 /* Emit RTL insns to initialize the variable parts of a trampoline.
20114 FNADDR is an RTX for the address of the function's pure code.
20115 CXT is an RTX for the static chain value for the function. */
20118 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
20120 int regsize = (TARGET_32BIT) ? 4 : 8;
20121 rtx ctx_reg = force_reg (Pmode, cxt);
20123 switch (DEFAULT_ABI)
20126 gcc_unreachable ();
20128 /* Macros to shorten the code expansions below. */
20129 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
20130 #define MEM_PLUS(addr,offset) \
20131 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
20133 /* Under AIX, just build the 3 word function descriptor */
20136 rtx fn_reg = gen_reg_rtx (Pmode);
20137 rtx toc_reg = gen_reg_rtx (Pmode);
20138 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
20139 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
20140 emit_move_insn (MEM_DEREF (addr), fn_reg);
20141 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
20142 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
20146 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
20149 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
20150 FALSE, VOIDmode, 4,
20152 GEN_INT (rs6000_trampoline_size ()), SImode,
20162 /* Table of valid machine attributes. */
20164 const struct attribute_spec rs6000_attribute_table[] =
20166 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
20167 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
20168 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
20169 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
20170 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
20171 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
20172 #ifdef SUBTARGET_ATTRIBUTE_TABLE
20173 SUBTARGET_ATTRIBUTE_TABLE,
20175 { NULL, 0, 0, false, false, false, NULL }
20178 /* Handle the "altivec" attribute. The attribute may have
20179 arguments as follows:
20181 __attribute__((altivec(vector__)))
20182 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
20183 __attribute__((altivec(bool__))) (always followed by 'unsigned')
20185 and may appear more than once (e.g., 'vector bool char') in a
20186 given declaration. */
20189 rs6000_handle_altivec_attribute (tree *node,
20190 tree name ATTRIBUTE_UNUSED,
20192 int flags ATTRIBUTE_UNUSED,
20193 bool *no_add_attrs)
20195 tree type = *node, result = NULL_TREE;
20196 enum machine_mode mode;
20199 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
20200 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
20201 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
20204 while (POINTER_TYPE_P (type)
20205 || TREE_CODE (type) == FUNCTION_TYPE
20206 || TREE_CODE (type) == METHOD_TYPE
20207 || TREE_CODE (type) == ARRAY_TYPE)
20208 type = TREE_TYPE (type);
20210 mode = TYPE_MODE (type);
20212 /* Check for invalid AltiVec type qualifiers. */
20213 if (type == long_unsigned_type_node || type == long_integer_type_node)
20216 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
20217 else if (rs6000_warn_altivec_long)
20218 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
20220 else if (type == long_long_unsigned_type_node
20221 || type == long_long_integer_type_node)
20222 error ("use of %<long long%> in AltiVec types is invalid");
20223 else if (type == double_type_node)
20224 error ("use of %<double%> in AltiVec types is invalid");
20225 else if (type == long_double_type_node)
20226 error ("use of %<long double%> in AltiVec types is invalid");
20227 else if (type == boolean_type_node)
20228 error ("use of boolean types in AltiVec types is invalid");
20229 else if (TREE_CODE (type) == COMPLEX_TYPE)
20230 error ("use of %<complex%> in AltiVec types is invalid");
20231 else if (DECIMAL_FLOAT_MODE_P (mode))
20232 error ("use of decimal floating point types in AltiVec types is invalid");
20234 switch (altivec_type)
20237 unsigned_p = TYPE_UNSIGNED (type);
20241 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
20244 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
20247 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
20249 case SFmode: result = V4SF_type_node; break;
20250 /* If the user says 'vector int bool', we may be handed the 'bool'
20251 attribute _before_ the 'vector' attribute, and so select the
20252 proper type in the 'b' case below. */
20253 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
20261 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
20262 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
20263 case QImode: case V16QImode: result = bool_V16QI_type_node;
20270 case V8HImode: result = pixel_V8HI_type_node;
20276 if (result && result != type && TYPE_READONLY (type))
20277 result = build_qualified_type (result, TYPE_QUAL_CONST);
20279 *no_add_attrs = true; /* No need to hang on to the attribute. */
20282 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
20287 /* AltiVec defines four built-in scalar types that serve as vector
20288 elements; we must teach the compiler how to mangle them. */
20290 static const char *
20291 rs6000_mangle_type (const_tree type)
20293 type = TYPE_MAIN_VARIANT (type);
20295 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
20296 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
20299 if (type == bool_char_type_node) return "U6__boolc";
20300 if (type == bool_short_type_node) return "U6__bools";
20301 if (type == pixel_type_node) return "u7__pixel";
20302 if (type == bool_int_type_node) return "U6__booli";
20304 /* Mangle IBM extended float long double as `g' (__float128) on
20305 powerpc*-linux where long-double-64 previously was the default. */
20306 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
20308 && TARGET_LONG_DOUBLE_128
20309 && !TARGET_IEEEQUAD)
20312 /* For all other types, use normal C++ mangling. */
20316 /* Handle a "longcall" or "shortcall" attribute; arguments as in
20317 struct attribute_spec.handler. */
20320 rs6000_handle_longcall_attribute (tree *node, tree name,
20321 tree args ATTRIBUTE_UNUSED,
20322 int flags ATTRIBUTE_UNUSED,
20323 bool *no_add_attrs)
20325 if (TREE_CODE (*node) != FUNCTION_TYPE
20326 && TREE_CODE (*node) != FIELD_DECL
20327 && TREE_CODE (*node) != TYPE_DECL)
20329 warning (OPT_Wattributes, "%qs attribute only applies to functions",
20330 IDENTIFIER_POINTER (name));
20331 *no_add_attrs = true;
20337 /* Set longcall attributes on all functions declared when
20338 rs6000_default_long_calls is true. */
20340 rs6000_set_default_type_attributes (tree type)
20342 if (rs6000_default_long_calls
20343 && (TREE_CODE (type) == FUNCTION_TYPE
20344 || TREE_CODE (type) == METHOD_TYPE))
20345 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
20347 TYPE_ATTRIBUTES (type));
20350 darwin_set_default_type_attributes (type);
20354 /* Return a reference suitable for calling a function with the
20355 longcall attribute. */
20358 rs6000_longcall_ref (rtx call_ref)
20360 const char *call_name;
20363 if (GET_CODE (call_ref) != SYMBOL_REF)
20366 /* System V adds '.' to the internal name, so skip them. */
20367 call_name = XSTR (call_ref, 0);
20368 if (*call_name == '.')
20370 while (*call_name == '.')
20373 node = get_identifier (call_name);
20374 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
20377 return force_reg (Pmode, call_ref);
20380 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
20381 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
20384 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20385 struct attribute_spec.handler. */
20387 rs6000_handle_struct_attribute (tree *node, tree name,
20388 tree args ATTRIBUTE_UNUSED,
20389 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
20392 if (DECL_P (*node))
20394 if (TREE_CODE (*node) == TYPE_DECL)
20395 type = &TREE_TYPE (*node);
20400 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
20401 || TREE_CODE (*type) == UNION_TYPE)))
20403 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
20404 *no_add_attrs = true;
20407 else if ((is_attribute_p ("ms_struct", name)
20408 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
20409 || ((is_attribute_p ("gcc_struct", name)
20410 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
20412 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
20413 IDENTIFIER_POINTER (name));
20414 *no_add_attrs = true;
20421 rs6000_ms_bitfield_layout_p (const_tree record_type)
20423 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
20424 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
20425 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
20428 #ifdef USING_ELFOS_H
20430 /* A get_unnamed_section callback, used for switching to toc_section. */
20433 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
20435 if (DEFAULT_ABI == ABI_AIX
20436 && TARGET_MINIMAL_TOC
20437 && !TARGET_RELOCATABLE)
20439 if (!toc_initialized)
20441 toc_initialized = 1;
20442 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
20443 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
20444 fprintf (asm_out_file, "\t.tc ");
20445 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
20446 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20447 fprintf (asm_out_file, "\n");
20449 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20450 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20451 fprintf (asm_out_file, " = .+32768\n");
20454 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20456 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
20457 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
20460 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20461 if (!toc_initialized)
20463 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20464 fprintf (asm_out_file, " = .+32768\n");
20465 toc_initialized = 1;
20470 /* Implement TARGET_ASM_INIT_SECTIONS. */
20473 rs6000_elf_asm_init_sections (void)
20476 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
20479 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
20480 SDATA2_SECTION_ASM_OP);
20483 /* Implement TARGET_SELECT_RTX_SECTION. */
20486 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
20487 unsigned HOST_WIDE_INT align)
20489 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20490 return toc_section;
20492 return default_elf_select_rtx_section (mode, x, align);
20495 /* For a SYMBOL_REF, set generic flags and then perform some
20496 target-specific processing.
20498 When the AIX ABI is requested on a non-AIX system, replace the
20499 function name with the real name (with a leading .) rather than the
20500 function descriptor name. This saves a lot of overriding code to
20501 read the prefixes. */
20504 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
20506 default_encode_section_info (decl, rtl, first);
20509 && TREE_CODE (decl) == FUNCTION_DECL
20511 && DEFAULT_ABI == ABI_AIX)
20513 rtx sym_ref = XEXP (rtl, 0);
20514 size_t len = strlen (XSTR (sym_ref, 0));
20515 char *str = XALLOCAVEC (char, len + 2);
20517 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
20518 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
20523 compare_section_name (const char *section, const char *template)
20527 len = strlen (template);
20528 return (strncmp (section, template, len) == 0
20529 && (section[len] == 0 || section[len] == '.'));
20533 rs6000_elf_in_small_data_p (const_tree decl)
20535 if (rs6000_sdata == SDATA_NONE)
20538 /* We want to merge strings, so we never consider them small data. */
20539 if (TREE_CODE (decl) == STRING_CST)
20542 /* Functions are never in the small data area. */
20543 if (TREE_CODE (decl) == FUNCTION_DECL)
20546 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
20548 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
20549 if (compare_section_name (section, ".sdata")
20550 || compare_section_name (section, ".sdata2")
20551 || compare_section_name (section, ".gnu.linkonce.s")
20552 || compare_section_name (section, ".sbss")
20553 || compare_section_name (section, ".sbss2")
20554 || compare_section_name (section, ".gnu.linkonce.sb")
20555 || strcmp (section, ".PPC.EMB.sdata0") == 0
20556 || strcmp (section, ".PPC.EMB.sbss0") == 0)
20561 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
20564 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20565 /* If it's not public, and we're not going to reference it there,
20566 there's no need to put it in the small data section. */
20567 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
20574 #endif /* USING_ELFOS_H */
20576 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20579 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
20581 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
20584 /* Return a REG that occurs in ADDR with coefficient 1.
20585 ADDR can be effectively incremented by incrementing REG.
20587 r0 is special and we must not select it as an address
20588 register by this routine since our caller will try to
20589 increment the returned register via an "la" instruction. */
20592 find_addr_reg (rtx addr)
20594 while (GET_CODE (addr) == PLUS)
20596 if (GET_CODE (XEXP (addr, 0)) == REG
20597 && REGNO (XEXP (addr, 0)) != 0)
20598 addr = XEXP (addr, 0);
20599 else if (GET_CODE (XEXP (addr, 1)) == REG
20600 && REGNO (XEXP (addr, 1)) != 0)
20601 addr = XEXP (addr, 1);
20602 else if (CONSTANT_P (XEXP (addr, 0)))
20603 addr = XEXP (addr, 1);
20604 else if (CONSTANT_P (XEXP (addr, 1)))
20605 addr = XEXP (addr, 0);
20607 gcc_unreachable ();
20609 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
20614 rs6000_fatal_bad_address (rtx op)
20616 fatal_insn ("bad address", op);
20621 static tree branch_island_list = 0;
20623 /* Remember to generate a branch island for far calls to the given
20627 add_compiler_branch_island (tree label_name, tree function_name,
20630 tree branch_island = build_tree_list (function_name, label_name);
20631 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
20632 TREE_CHAIN (branch_island) = branch_island_list;
20633 branch_island_list = branch_island;
20636 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20637 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20638 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20639 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20641 /* Generate far-jump branch islands for everything on the
20642 branch_island_list. Invoked immediately after the last instruction
20643 of the epilogue has been emitted; the branch-islands must be
20644 appended to, and contiguous with, the function body. Mach-O stubs
20645 are generated in machopic_output_stub(). */
20648 macho_branch_islands (void)
20651 tree branch_island;
20653 for (branch_island = branch_island_list;
20655 branch_island = TREE_CHAIN (branch_island))
20657 const char *label =
20658 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
20660 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
20661 char name_buf[512];
20662 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
20663 if (name[0] == '*' || name[0] == '&')
20664 strcpy (name_buf, name+1);
20668 strcpy (name_buf+1, name);
20670 strcpy (tmp_buf, "\n");
20671 strcat (tmp_buf, label);
20672 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20673 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
20674 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
20675 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20678 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
20679 strcat (tmp_buf, label);
20680 strcat (tmp_buf, "_pic\n");
20681 strcat (tmp_buf, label);
20682 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
20684 strcat (tmp_buf, "\taddis r11,r11,ha16(");
20685 strcat (tmp_buf, name_buf);
20686 strcat (tmp_buf, " - ");
20687 strcat (tmp_buf, label);
20688 strcat (tmp_buf, "_pic)\n");
20690 strcat (tmp_buf, "\tmtlr r0\n");
20692 strcat (tmp_buf, "\taddi r12,r11,lo16(");
20693 strcat (tmp_buf, name_buf);
20694 strcat (tmp_buf, " - ");
20695 strcat (tmp_buf, label);
20696 strcat (tmp_buf, "_pic)\n");
20698 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
20702 strcat (tmp_buf, ":\nlis r12,hi16(");
20703 strcat (tmp_buf, name_buf);
20704 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
20705 strcat (tmp_buf, name_buf);
20706 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
20708 output_asm_insn (tmp_buf, 0);
20709 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20710 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
20711 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
20712 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20715 branch_island_list = 0;
20718 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
20719 already there or not. */
20722 no_previous_def (tree function_name)
20724 tree branch_island;
20725 for (branch_island = branch_island_list;
20727 branch_island = TREE_CHAIN (branch_island))
20728 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
20733 /* GET_PREV_LABEL gets the label name from the previous definition of
20737 get_prev_label (tree function_name)
20739 tree branch_island;
20740 for (branch_island = branch_island_list;
20742 branch_island = TREE_CHAIN (branch_island))
20743 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
20744 return BRANCH_ISLAND_LABEL_NAME (branch_island);
20748 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
20749 #define DARWIN_LINKER_GENERATES_ISLANDS 0
20752 /* KEXTs still need branch islands. */
20753 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
20754 || flag_mkernel || flag_apple_kext)
20756 /* INSN is either a function call or a millicode call. It may have an
20757 unconditional jump in its delay slot.
20759 CALL_DEST is the routine we are calling. */
20762 output_call (rtx insn, rtx *operands, int dest_operand_number,
20763 int cookie_operand_number)
20765 static char buf[256];
20766 if (DARWIN_GENERATE_ISLANDS
20767 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
20768 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
20771 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
20773 if (no_previous_def (funname))
20775 rtx label_rtx = gen_label_rtx ();
20776 char *label_buf, temp_buf[256];
20777 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
20778 CODE_LABEL_NUMBER (label_rtx));
20779 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
20780 labelname = get_identifier (label_buf);
20781 add_compiler_branch_island (labelname, funname, insn_line (insn));
20784 labelname = get_prev_label (funname);
20786 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
20787 instruction will reach 'foo', otherwise link as 'bl L42'".
20788 "L42" should be a 'branch island', that will do a far jump to
20789 'foo'. Branch islands are generated in
20790 macho_branch_islands(). */
20791 sprintf (buf, "jbsr %%z%d,%.246s",
20792 dest_operand_number, IDENTIFIER_POINTER (labelname));
20795 sprintf (buf, "bl %%z%d", dest_operand_number);
20799 /* Generate PIC and indirect symbol stubs. */
20802 machopic_output_stub (FILE *file, const char *symb, const char *stub)
20804 unsigned int length;
20805 char *symbol_name, *lazy_ptr_name;
20806 char *local_label_0;
20807 static int label = 0;
20809 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20810 symb = (*targetm.strip_name_encoding) (symb);
20813 length = strlen (symb);
20814 symbol_name = XALLOCAVEC (char, length + 32);
20815 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
20817 lazy_ptr_name = XALLOCAVEC (char, length + 32);
20818 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
20821 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
20823 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
20827 fprintf (file, "\t.align 5\n");
20829 fprintf (file, "%s:\n", stub);
20830 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20833 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
20834 sprintf (local_label_0, "\"L%011d$spb\"", label);
20836 fprintf (file, "\tmflr r0\n");
20837 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
20838 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
20839 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
20840 lazy_ptr_name, local_label_0);
20841 fprintf (file, "\tmtlr r0\n");
20842 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
20843 (TARGET_64BIT ? "ldu" : "lwzu"),
20844 lazy_ptr_name, local_label_0);
20845 fprintf (file, "\tmtctr r12\n");
20846 fprintf (file, "\tbctr\n");
20850 fprintf (file, "\t.align 4\n");
20852 fprintf (file, "%s:\n", stub);
20853 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20855 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
20856 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
20857 (TARGET_64BIT ? "ldu" : "lwzu"),
20859 fprintf (file, "\tmtctr r12\n");
20860 fprintf (file, "\tbctr\n");
20863 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
20864 fprintf (file, "%s:\n", lazy_ptr_name);
20865 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20866 fprintf (file, "%sdyld_stub_binding_helper\n",
20867 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
20870 /* Legitimize PIC addresses. If the address is already
20871 position-independent, we return ORIG. Newly generated
20872 position-independent addresses go into a reg. This is REG if non
20873 zero, otherwise we allocate register(s) as necessary. */
20875 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
20878 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
20883 if (reg == NULL && ! reload_in_progress && ! reload_completed)
20884 reg = gen_reg_rtx (Pmode);
20886 if (GET_CODE (orig) == CONST)
20890 if (GET_CODE (XEXP (orig, 0)) == PLUS
20891 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
20894 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
20896 /* Use a different reg for the intermediate value, as
20897 it will be marked UNCHANGING. */
20898 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
20899 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
20902 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
20905 if (GET_CODE (offset) == CONST_INT)
20907 if (SMALL_INT (offset))
20908 return plus_constant (base, INTVAL (offset));
20909 else if (! reload_in_progress && ! reload_completed)
20910 offset = force_reg (Pmode, offset);
20913 rtx mem = force_const_mem (Pmode, orig);
20914 return machopic_legitimize_pic_address (mem, Pmode, reg);
20917 return gen_rtx_PLUS (Pmode, base, offset);
20920 /* Fall back on generic machopic code. */
20921 return machopic_legitimize_pic_address (orig, mode, reg);
20924 /* Output a .machine directive for the Darwin assembler, and call
20925 the generic start_file routine. */
20928 rs6000_darwin_file_start (void)
20930 static const struct
20936 { "ppc64", "ppc64", MASK_64BIT },
20937 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
20938 { "power4", "ppc970", 0 },
20939 { "G5", "ppc970", 0 },
20940 { "7450", "ppc7450", 0 },
20941 { "7400", "ppc7400", MASK_ALTIVEC },
20942 { "G4", "ppc7400", 0 },
20943 { "750", "ppc750", 0 },
20944 { "740", "ppc750", 0 },
20945 { "G3", "ppc750", 0 },
20946 { "604e", "ppc604e", 0 },
20947 { "604", "ppc604", 0 },
20948 { "603e", "ppc603", 0 },
20949 { "603", "ppc603", 0 },
20950 { "601", "ppc601", 0 },
20951 { NULL, "ppc", 0 } };
20952 const char *cpu_id = "";
20955 rs6000_file_start ();
20956 darwin_file_start ();
20958 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20959 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
20960 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
20961 && rs6000_select[i].string[0] != '\0')
20962 cpu_id = rs6000_select[i].string;
20964 /* Look through the mapping array. Pick the first name that either
20965 matches the argument, has a bit set in IF_SET that is also set
20966 in the target flags, or has a NULL name. */
20969 while (mapping[i].arg != NULL
20970 && strcmp (mapping[i].arg, cpu_id) != 0
20971 && (mapping[i].if_set & target_flags) == 0)
20974 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
20977 #endif /* TARGET_MACHO */
20981 rs6000_elf_reloc_rw_mask (void)
20985 else if (DEFAULT_ABI == ABI_AIX)
20991 /* Record an element in the table of global constructors. SYMBOL is
20992 a SYMBOL_REF of the function to be called; PRIORITY is a number
20993 between 0 and MAX_INIT_PRIORITY.
20995 This differs from default_named_section_asm_out_constructor in
20996 that we have special handling for -mrelocatable. */
20999 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
21001 const char *section = ".ctors";
21004 if (priority != DEFAULT_INIT_PRIORITY)
21006 sprintf (buf, ".ctors.%.5u",
21007 /* Invert the numbering so the linker puts us in the proper
21008 order; constructors are run from right to left, and the
21009 linker sorts in increasing order. */
21010 MAX_INIT_PRIORITY - priority);
21014 switch_to_section (get_section (section, SECTION_WRITE, NULL));
21015 assemble_align (POINTER_SIZE);
21017 if (TARGET_RELOCATABLE)
21019 fputs ("\t.long (", asm_out_file);
21020 output_addr_const (asm_out_file, symbol);
21021 fputs (")@fixup\n", asm_out_file);
21024 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
21028 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
21030 const char *section = ".dtors";
21033 if (priority != DEFAULT_INIT_PRIORITY)
21035 sprintf (buf, ".dtors.%.5u",
21036 /* Invert the numbering so the linker puts us in the proper
21037 order; constructors are run from right to left, and the
21038 linker sorts in increasing order. */
21039 MAX_INIT_PRIORITY - priority);
21043 switch_to_section (get_section (section, SECTION_WRITE, NULL));
21044 assemble_align (POINTER_SIZE);
21046 if (TARGET_RELOCATABLE)
21048 fputs ("\t.long (", asm_out_file);
21049 output_addr_const (asm_out_file, symbol);
21050 fputs (")@fixup\n", asm_out_file);
21053 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
21057 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
21061 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
21062 ASM_OUTPUT_LABEL (file, name);
21063 fputs (DOUBLE_INT_ASM_OP, file);
21064 rs6000_output_function_entry (file, name);
21065 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
21068 fputs ("\t.size\t", file);
21069 assemble_name (file, name);
21070 fputs (",24\n\t.type\t.", file);
21071 assemble_name (file, name);
21072 fputs (",@function\n", file);
21073 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
21075 fputs ("\t.globl\t.", file);
21076 assemble_name (file, name);
21081 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
21082 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
21083 rs6000_output_function_entry (file, name);
21084 fputs (":\n", file);
21088 if (TARGET_RELOCATABLE
21089 && !TARGET_SECURE_PLT
21090 && (get_pool_size () != 0 || crtl->profile)
21095 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
21097 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
21098 fprintf (file, "\t.long ");
21099 assemble_name (file, buf);
21101 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
21102 assemble_name (file, buf);
21106 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
21107 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
21109 if (DEFAULT_ABI == ABI_AIX)
21111 const char *desc_name, *orig_name;
21113 orig_name = (*targetm.strip_name_encoding) (name);
21114 desc_name = orig_name;
21115 while (*desc_name == '.')
21118 if (TREE_PUBLIC (decl))
21119 fprintf (file, "\t.globl %s\n", desc_name);
21121 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
21122 fprintf (file, "%s:\n", desc_name);
21123 fprintf (file, "\t.long %s\n", orig_name);
21124 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
21125 if (DEFAULT_ABI == ABI_AIX)
21126 fputs ("\t.long 0\n", file);
21127 fprintf (file, "\t.previous\n");
21129 ASM_OUTPUT_LABEL (file, name);
21133 rs6000_elf_end_indicate_exec_stack (void)
21136 file_end_indicate_exec_stack ();
21142 rs6000_xcoff_asm_output_anchor (rtx symbol)
21146 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
21147 SYMBOL_REF_BLOCK_OFFSET (symbol));
21148 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
21152 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
21154 fputs (GLOBAL_ASM_OP, stream);
21155 RS6000_OUTPUT_BASENAME (stream, name);
21156 putc ('\n', stream);
21159 /* A get_unnamed_decl callback, used for read-only sections. PTR
21160 points to the section string variable. */
21163 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
21165 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
21166 *(const char *const *) directive,
21167 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
21170 /* Likewise for read-write sections. */
21173 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
21175 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
21176 *(const char *const *) directive,
21177 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
21180 /* A get_unnamed_section callback, used for switching to toc_section. */
21183 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
21185 if (TARGET_MINIMAL_TOC)
21187 /* toc_section is always selected at least once from
21188 rs6000_xcoff_file_start, so this is guaranteed to
21189 always be defined once and only once in each file. */
21190 if (!toc_initialized)
21192 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
21193 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
21194 toc_initialized = 1;
21196 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
21197 (TARGET_32BIT ? "" : ",3"));
21200 fputs ("\t.toc\n", asm_out_file);
21203 /* Implement TARGET_ASM_INIT_SECTIONS. */
21206 rs6000_xcoff_asm_init_sections (void)
21208 read_only_data_section
21209 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
21210 &xcoff_read_only_section_name);
21212 private_data_section
21213 = get_unnamed_section (SECTION_WRITE,
21214 rs6000_xcoff_output_readwrite_section_asm_op,
21215 &xcoff_private_data_section_name);
21217 read_only_private_data_section
21218 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
21219 &xcoff_private_data_section_name);
21222 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
21224 readonly_data_section = read_only_data_section;
21225 exception_section = data_section;
21229 rs6000_xcoff_reloc_rw_mask (void)
21235 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
21236 tree decl ATTRIBUTE_UNUSED)
21239 static const char * const suffix[3] = { "PR", "RO", "RW" };
21241 if (flags & SECTION_CODE)
21243 else if (flags & SECTION_WRITE)
21248 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
21249 (flags & SECTION_CODE) ? "." : "",
21250 name, suffix[smclass], flags & SECTION_ENTSIZE);
21254 rs6000_xcoff_select_section (tree decl, int reloc,
21255 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
21257 if (decl_readonly_section (decl, reloc))
21259 if (TREE_PUBLIC (decl))
21260 return read_only_data_section;
21262 return read_only_private_data_section;
21266 if (TREE_PUBLIC (decl))
21267 return data_section;
21269 return private_data_section;
21274 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
21278 /* Use select_section for private and uninitialized data. */
21279 if (!TREE_PUBLIC (decl)
21280 || DECL_COMMON (decl)
21281 || DECL_INITIAL (decl) == NULL_TREE
21282 || DECL_INITIAL (decl) == error_mark_node
21283 || (flag_zero_initialized_in_bss
21284 && initializer_zerop (DECL_INITIAL (decl))))
21287 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
21288 name = (*targetm.strip_name_encoding) (name);
21289 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
21292 /* Select section for constant in constant pool.
21294 On RS/6000, all constants are in the private read-only data area.
21295 However, if this is being placed in the TOC it must be output as a
21299 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
21300 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
21302 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
21303 return toc_section;
21305 return read_only_private_data_section;
21308 /* Remove any trailing [DS] or the like from the symbol name. */
21310 static const char *
21311 rs6000_xcoff_strip_name_encoding (const char *name)
21316 len = strlen (name);
21317 if (name[len - 1] == ']')
21318 return ggc_alloc_string (name, len - 4);
21323 /* Section attributes. AIX is always PIC. */
21325 static unsigned int
21326 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
21328 unsigned int align;
21329 unsigned int flags = default_section_type_flags (decl, name, reloc);
21331 /* Align to at least UNIT size. */
21332 if (flags & SECTION_CODE)
21333 align = MIN_UNITS_PER_WORD;
21335 /* Increase alignment of large objects if not already stricter. */
21336 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
21337 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
21338 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
21340 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
21343 /* Output at beginning of assembler file.
21345 Initialize the section names for the RS/6000 at this point.
21347 Specify filename, including full path, to assembler.
21349 We want to go into the TOC section so at least one .toc will be emitted.
21350 Also, in order to output proper .bs/.es pairs, we need at least one static
21351 [RW] section emitted.
21353 Finally, declare mcount when profiling to make the assembler happy. */
21356 rs6000_xcoff_file_start (void)
21358 rs6000_gen_section_name (&xcoff_bss_section_name,
21359 main_input_filename, ".bss_");
21360 rs6000_gen_section_name (&xcoff_private_data_section_name,
21361 main_input_filename, ".rw_");
21362 rs6000_gen_section_name (&xcoff_read_only_section_name,
21363 main_input_filename, ".ro_");
21365 fputs ("\t.file\t", asm_out_file);
21366 output_quoted_string (asm_out_file, main_input_filename);
21367 fputc ('\n', asm_out_file);
21368 if (write_symbols != NO_DEBUG)
21369 switch_to_section (private_data_section);
21370 switch_to_section (text_section);
21372 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
21373 rs6000_file_start ();
21376 /* Output at end of assembler file.
21377 On the RS/6000, referencing data should automatically pull in text. */
21380 rs6000_xcoff_file_end (void)
21382 switch_to_section (text_section);
21383 fputs ("_section_.text:\n", asm_out_file);
21384 switch_to_section (data_section);
21385 fputs (TARGET_32BIT
21386 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
21389 #endif /* TARGET_XCOFF */
21391 /* Compute a (partial) cost for rtx X. Return true if the complete
21392 cost has been computed, and false if subexpressions should be
21393 scanned. In either case, *TOTAL contains the cost result. */
21396 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
21398 enum machine_mode mode = GET_MODE (x);
21402 /* On the RS/6000, if it is valid in the insn, it is free. */
21404 if (((outer_code == SET
21405 || outer_code == PLUS
21406 || outer_code == MINUS)
21407 && (satisfies_constraint_I (x)
21408 || satisfies_constraint_L (x)))
21409 || (outer_code == AND
21410 && (satisfies_constraint_K (x)
21412 ? satisfies_constraint_L (x)
21413 : satisfies_constraint_J (x))
21414 || mask_operand (x, mode)
21416 && mask64_operand (x, DImode))))
21417 || ((outer_code == IOR || outer_code == XOR)
21418 && (satisfies_constraint_K (x)
21420 ? satisfies_constraint_L (x)
21421 : satisfies_constraint_J (x))))
21422 || outer_code == ASHIFT
21423 || outer_code == ASHIFTRT
21424 || outer_code == LSHIFTRT
21425 || outer_code == ROTATE
21426 || outer_code == ROTATERT
21427 || outer_code == ZERO_EXTRACT
21428 || (outer_code == MULT
21429 && satisfies_constraint_I (x))
21430 || ((outer_code == DIV || outer_code == UDIV
21431 || outer_code == MOD || outer_code == UMOD)
21432 && exact_log2 (INTVAL (x)) >= 0)
21433 || (outer_code == COMPARE
21434 && (satisfies_constraint_I (x)
21435 || satisfies_constraint_K (x)))
21436 || (outer_code == EQ
21437 && (satisfies_constraint_I (x)
21438 || satisfies_constraint_K (x)
21440 ? satisfies_constraint_L (x)
21441 : satisfies_constraint_J (x))))
21442 || (outer_code == GTU
21443 && satisfies_constraint_I (x))
21444 || (outer_code == LTU
21445 && satisfies_constraint_P (x)))
21450 else if ((outer_code == PLUS
21451 && reg_or_add_cint_operand (x, VOIDmode))
21452 || (outer_code == MINUS
21453 && reg_or_sub_cint_operand (x, VOIDmode))
21454 || ((outer_code == SET
21455 || outer_code == IOR
21456 || outer_code == XOR)
21458 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
21460 *total = COSTS_N_INSNS (1);
21466 if (mode == DImode && code == CONST_DOUBLE)
21468 if ((outer_code == IOR || outer_code == XOR)
21469 && CONST_DOUBLE_HIGH (x) == 0
21470 && (CONST_DOUBLE_LOW (x)
21471 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
21476 else if ((outer_code == AND && and64_2_operand (x, DImode))
21477 || ((outer_code == SET
21478 || outer_code == IOR
21479 || outer_code == XOR)
21480 && CONST_DOUBLE_HIGH (x) == 0))
21482 *total = COSTS_N_INSNS (1);
21492 /* When optimizing for size, MEM should be slightly more expensive
21493 than generating address, e.g., (plus (reg) (const)).
21494 L1 cache latency is about two instructions. */
21495 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
21503 if (mode == DFmode)
21505 if (GET_CODE (XEXP (x, 0)) == MULT)
21507 /* FNMA accounted in outer NEG. */
21508 if (outer_code == NEG)
21509 *total = rs6000_cost->dmul - rs6000_cost->fp;
21511 *total = rs6000_cost->dmul;
21514 *total = rs6000_cost->fp;
21516 else if (mode == SFmode)
21518 /* FNMA accounted in outer NEG. */
21519 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21522 *total = rs6000_cost->fp;
21525 *total = COSTS_N_INSNS (1);
21529 if (mode == DFmode)
21531 if (GET_CODE (XEXP (x, 0)) == MULT
21532 || GET_CODE (XEXP (x, 1)) == MULT)
21534 /* FNMA accounted in outer NEG. */
21535 if (outer_code == NEG)
21536 *total = rs6000_cost->dmul - rs6000_cost->fp;
21538 *total = rs6000_cost->dmul;
21541 *total = rs6000_cost->fp;
21543 else if (mode == SFmode)
21545 /* FNMA accounted in outer NEG. */
21546 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21549 *total = rs6000_cost->fp;
21552 *total = COSTS_N_INSNS (1);
21556 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21557 && satisfies_constraint_I (XEXP (x, 1)))
21559 if (INTVAL (XEXP (x, 1)) >= -256
21560 && INTVAL (XEXP (x, 1)) <= 255)
21561 *total = rs6000_cost->mulsi_const9;
21563 *total = rs6000_cost->mulsi_const;
21565 /* FMA accounted in outer PLUS/MINUS. */
21566 else if ((mode == DFmode || mode == SFmode)
21567 && (outer_code == PLUS || outer_code == MINUS))
21569 else if (mode == DFmode)
21570 *total = rs6000_cost->dmul;
21571 else if (mode == SFmode)
21572 *total = rs6000_cost->fp;
21573 else if (mode == DImode)
21574 *total = rs6000_cost->muldi;
21576 *total = rs6000_cost->mulsi;
21581 if (FLOAT_MODE_P (mode))
21583 *total = mode == DFmode ? rs6000_cost->ddiv
21584 : rs6000_cost->sdiv;
21591 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21592 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
21594 if (code == DIV || code == MOD)
21596 *total = COSTS_N_INSNS (2);
21599 *total = COSTS_N_INSNS (1);
21603 if (GET_MODE (XEXP (x, 1)) == DImode)
21604 *total = rs6000_cost->divdi;
21606 *total = rs6000_cost->divsi;
21608 /* Add in shift and subtract for MOD. */
21609 if (code == MOD || code == UMOD)
21610 *total += COSTS_N_INSNS (2);
21615 *total = COSTS_N_INSNS (4);
21619 *total = COSTS_N_INSNS (6);
21623 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
21635 *total = COSTS_N_INSNS (1);
21643 /* Handle mul_highpart. */
21644 if (outer_code == TRUNCATE
21645 && GET_CODE (XEXP (x, 0)) == MULT)
21647 if (mode == DImode)
21648 *total = rs6000_cost->muldi;
21650 *total = rs6000_cost->mulsi;
21653 else if (outer_code == AND)
21656 *total = COSTS_N_INSNS (1);
21661 if (GET_CODE (XEXP (x, 0)) == MEM)
21664 *total = COSTS_N_INSNS (1);
21670 if (!FLOAT_MODE_P (mode))
21672 *total = COSTS_N_INSNS (1);
21678 case UNSIGNED_FLOAT:
21681 case FLOAT_TRUNCATE:
21682 *total = rs6000_cost->fp;
21686 if (mode == DFmode)
21689 *total = rs6000_cost->fp;
21693 switch (XINT (x, 1))
21696 *total = rs6000_cost->fp;
21708 *total = COSTS_N_INSNS (1);
21711 else if (FLOAT_MODE_P (mode)
21712 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
21714 *total = rs6000_cost->fp;
21722 /* Carry bit requires mode == Pmode.
21723 NEG or PLUS already counted so only add one. */
21725 && (outer_code == NEG || outer_code == PLUS))
21727 *total = COSTS_N_INSNS (1);
21730 if (outer_code == SET)
21732 if (XEXP (x, 1) == const0_rtx)
21734 *total = COSTS_N_INSNS (2);
21737 else if (mode == Pmode)
21739 *total = COSTS_N_INSNS (3);
21748 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
21750 *total = COSTS_N_INSNS (2);
21754 if (outer_code == COMPARE)
21768 /* A C expression returning the cost of moving data from a register of class
21769 CLASS1 to one of CLASS2. */
21772 rs6000_register_move_cost (enum machine_mode mode,
21773 enum reg_class from, enum reg_class to)
21775 /* Moves from/to GENERAL_REGS. */
21776 if (reg_classes_intersect_p (to, GENERAL_REGS)
21777 || reg_classes_intersect_p (from, GENERAL_REGS))
21779 if (! reg_classes_intersect_p (to, GENERAL_REGS))
21782 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
21783 return (rs6000_memory_move_cost (mode, from, 0)
21784 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
21786 /* It's more expensive to move CR_REGS than CR0_REGS because of the
21788 else if (from == CR_REGS)
21791 /* Power6 has slower LR/CTR moves so make them more expensive than
21792 memory in order to bias spills to memory .*/
21793 else if (rs6000_cpu == PROCESSOR_POWER6
21794 && reg_classes_intersect_p (from, LINK_OR_CTR_REGS))
21795 return 6 * hard_regno_nregs[0][mode];
21798 /* A move will cost one instruction per GPR moved. */
21799 return 2 * hard_regno_nregs[0][mode];
21802 /* Moving between two similar registers is just one instruction. */
21803 else if (reg_classes_intersect_p (to, from))
21804 return (mode == TFmode || mode == TDmode) ? 4 : 2;
21806 /* Everything else has to go through GENERAL_REGS. */
21808 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
21809 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
21812 /* A C expressions returning the cost of moving data of MODE from a register to
21816 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
21817 int in ATTRIBUTE_UNUSED)
21819 if (reg_classes_intersect_p (class, GENERAL_REGS))
21820 return 4 * hard_regno_nregs[0][mode];
21821 else if (reg_classes_intersect_p (class, FLOAT_REGS))
21822 return 4 * hard_regno_nregs[32][mode];
21823 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
21824 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
21826 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
21829 /* Returns a code for a target-specific builtin that implements
21830 reciprocal of the function, or NULL_TREE if not available. */
21833 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
21834 bool sqrt ATTRIBUTE_UNUSED)
21836 if (! (TARGET_RECIP && TARGET_PPC_GFXOPT && !optimize_size
21837 && flag_finite_math_only && !flag_trapping_math
21838 && flag_unsafe_math_optimizations))
21846 case BUILT_IN_SQRTF:
21847 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
21854 /* Newton-Raphson approximation of single-precision floating point divide n/d.
21855 Assumes no trapping math and finite arguments. */
21858 rs6000_emit_swdivsf (rtx dst, rtx n, rtx d)
21860 rtx x0, e0, e1, y1, u0, v0, one;
21862 x0 = gen_reg_rtx (SFmode);
21863 e0 = gen_reg_rtx (SFmode);
21864 e1 = gen_reg_rtx (SFmode);
21865 y1 = gen_reg_rtx (SFmode);
21866 u0 = gen_reg_rtx (SFmode);
21867 v0 = gen_reg_rtx (SFmode);
21868 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21870 /* x0 = 1./d estimate */
21871 emit_insn (gen_rtx_SET (VOIDmode, x0,
21872 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
21874 /* e0 = 1. - d * x0 */
21875 emit_insn (gen_rtx_SET (VOIDmode, e0,
21876 gen_rtx_MINUS (SFmode, one,
21877 gen_rtx_MULT (SFmode, d, x0))));
21878 /* e1 = e0 + e0 * e0 */
21879 emit_insn (gen_rtx_SET (VOIDmode, e1,
21880 gen_rtx_PLUS (SFmode,
21881 gen_rtx_MULT (SFmode, e0, e0), e0)));
21882 /* y1 = x0 + e1 * x0 */
21883 emit_insn (gen_rtx_SET (VOIDmode, y1,
21884 gen_rtx_PLUS (SFmode,
21885 gen_rtx_MULT (SFmode, e1, x0), x0)));
21887 emit_insn (gen_rtx_SET (VOIDmode, u0,
21888 gen_rtx_MULT (SFmode, n, y1)));
21889 /* v0 = n - d * u0 */
21890 emit_insn (gen_rtx_SET (VOIDmode, v0,
21891 gen_rtx_MINUS (SFmode, n,
21892 gen_rtx_MULT (SFmode, d, u0))));
21893 /* dst = u0 + v0 * y1 */
21894 emit_insn (gen_rtx_SET (VOIDmode, dst,
21895 gen_rtx_PLUS (SFmode,
21896 gen_rtx_MULT (SFmode, v0, y1), u0)));
21899 /* Newton-Raphson approximation of double-precision floating point divide n/d.
21900 Assumes no trapping math and finite arguments. */
21903 rs6000_emit_swdivdf (rtx dst, rtx n, rtx d)
21905 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
21907 x0 = gen_reg_rtx (DFmode);
21908 e0 = gen_reg_rtx (DFmode);
21909 e1 = gen_reg_rtx (DFmode);
21910 e2 = gen_reg_rtx (DFmode);
21911 y1 = gen_reg_rtx (DFmode);
21912 y2 = gen_reg_rtx (DFmode);
21913 y3 = gen_reg_rtx (DFmode);
21914 u0 = gen_reg_rtx (DFmode);
21915 v0 = gen_reg_rtx (DFmode);
21916 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
21918 /* x0 = 1./d estimate */
21919 emit_insn (gen_rtx_SET (VOIDmode, x0,
21920 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
21922 /* e0 = 1. - d * x0 */
21923 emit_insn (gen_rtx_SET (VOIDmode, e0,
21924 gen_rtx_MINUS (DFmode, one,
21925 gen_rtx_MULT (SFmode, d, x0))));
21926 /* y1 = x0 + e0 * x0 */
21927 emit_insn (gen_rtx_SET (VOIDmode, y1,
21928 gen_rtx_PLUS (DFmode,
21929 gen_rtx_MULT (DFmode, e0, x0), x0)));
21931 emit_insn (gen_rtx_SET (VOIDmode, e1,
21932 gen_rtx_MULT (DFmode, e0, e0)));
21933 /* y2 = y1 + e1 * y1 */
21934 emit_insn (gen_rtx_SET (VOIDmode, y2,
21935 gen_rtx_PLUS (DFmode,
21936 gen_rtx_MULT (DFmode, e1, y1), y1)));
21938 emit_insn (gen_rtx_SET (VOIDmode, e2,
21939 gen_rtx_MULT (DFmode, e1, e1)));
21940 /* y3 = y2 + e2 * y2 */
21941 emit_insn (gen_rtx_SET (VOIDmode, y3,
21942 gen_rtx_PLUS (DFmode,
21943 gen_rtx_MULT (DFmode, e2, y2), y2)));
21945 emit_insn (gen_rtx_SET (VOIDmode, u0,
21946 gen_rtx_MULT (DFmode, n, y3)));
21947 /* v0 = n - d * u0 */
21948 emit_insn (gen_rtx_SET (VOIDmode, v0,
21949 gen_rtx_MINUS (DFmode, n,
21950 gen_rtx_MULT (DFmode, d, u0))));
21951 /* dst = u0 + v0 * y3 */
21952 emit_insn (gen_rtx_SET (VOIDmode, dst,
21953 gen_rtx_PLUS (DFmode,
21954 gen_rtx_MULT (DFmode, v0, y3), u0)));
21958 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21959 Assumes no trapping math and finite arguments. */
21962 rs6000_emit_swrsqrtsf (rtx dst, rtx src)
21964 rtx x0, x1, x2, y1, u0, u1, u2, v0, v1, v2, t0,
21965 half, one, halfthree, c1, cond, label;
21967 x0 = gen_reg_rtx (SFmode);
21968 x1 = gen_reg_rtx (SFmode);
21969 x2 = gen_reg_rtx (SFmode);
21970 y1 = gen_reg_rtx (SFmode);
21971 u0 = gen_reg_rtx (SFmode);
21972 u1 = gen_reg_rtx (SFmode);
21973 u2 = gen_reg_rtx (SFmode);
21974 v0 = gen_reg_rtx (SFmode);
21975 v1 = gen_reg_rtx (SFmode);
21976 v2 = gen_reg_rtx (SFmode);
21977 t0 = gen_reg_rtx (SFmode);
21978 halfthree = gen_reg_rtx (SFmode);
21979 cond = gen_rtx_REG (CCFPmode, CR1_REGNO);
21980 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
21982 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
21983 emit_insn (gen_rtx_SET (VOIDmode, t0,
21984 gen_rtx_MULT (SFmode, src, src)));
21986 emit_insn (gen_rtx_SET (VOIDmode, cond,
21987 gen_rtx_COMPARE (CCFPmode, t0, src)));
21988 c1 = gen_rtx_EQ (VOIDmode, cond, const0_rtx);
21989 emit_unlikely_jump (c1, label);
21991 half = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode));
21992 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21994 /* halfthree = 1.5 = 1.0 + 0.5 */
21995 emit_insn (gen_rtx_SET (VOIDmode, halfthree,
21996 gen_rtx_PLUS (SFmode, one, half)));
21998 /* x0 = rsqrt estimate */
21999 emit_insn (gen_rtx_SET (VOIDmode, x0,
22000 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, src),
22003 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
22004 emit_insn (gen_rtx_SET (VOIDmode, y1,
22005 gen_rtx_MINUS (SFmode,
22006 gen_rtx_MULT (SFmode, src, halfthree),
22009 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
22010 emit_insn (gen_rtx_SET (VOIDmode, u0,
22011 gen_rtx_MULT (SFmode, x0, x0)));
22012 emit_insn (gen_rtx_SET (VOIDmode, v0,
22013 gen_rtx_MINUS (SFmode,
22015 gen_rtx_MULT (SFmode, y1, u0))));
22016 emit_insn (gen_rtx_SET (VOIDmode, x1,
22017 gen_rtx_MULT (SFmode, x0, v0)));
22019 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
22020 emit_insn (gen_rtx_SET (VOIDmode, u1,
22021 gen_rtx_MULT (SFmode, x1, x1)));
22022 emit_insn (gen_rtx_SET (VOIDmode, v1,
22023 gen_rtx_MINUS (SFmode,
22025 gen_rtx_MULT (SFmode, y1, u1))));
22026 emit_insn (gen_rtx_SET (VOIDmode, x2,
22027 gen_rtx_MULT (SFmode, x1, v1)));
22029 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
22030 emit_insn (gen_rtx_SET (VOIDmode, u2,
22031 gen_rtx_MULT (SFmode, x2, x2)));
22032 emit_insn (gen_rtx_SET (VOIDmode, v2,
22033 gen_rtx_MINUS (SFmode,
22035 gen_rtx_MULT (SFmode, y1, u2))));
22036 emit_insn (gen_rtx_SET (VOIDmode, dst,
22037 gen_rtx_MULT (SFmode, x2, v2)));
22039 emit_label (XEXP (label, 0));
22042 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
22043 target, and SRC is the argument operand. */
22046 rs6000_emit_popcount (rtx dst, rtx src)
22048 enum machine_mode mode = GET_MODE (dst);
22051 tmp1 = gen_reg_rtx (mode);
22053 if (mode == SImode)
22055 emit_insn (gen_popcntbsi2 (tmp1, src));
22056 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
22058 tmp2 = force_reg (SImode, tmp2);
22059 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
22063 emit_insn (gen_popcntbdi2 (tmp1, src));
22064 tmp2 = expand_mult (DImode, tmp1,
22065 GEN_INT ((HOST_WIDE_INT)
22066 0x01010101 << 32 | 0x01010101),
22068 tmp2 = force_reg (DImode, tmp2);
22069 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
22074 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
22075 target, and SRC is the argument operand. */
22078 rs6000_emit_parity (rtx dst, rtx src)
22080 enum machine_mode mode = GET_MODE (dst);
22083 tmp = gen_reg_rtx (mode);
22084 if (mode == SImode)
22086 /* Is mult+shift >= shift+xor+shift+xor? */
22087 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
22089 rtx tmp1, tmp2, tmp3, tmp4;
22091 tmp1 = gen_reg_rtx (SImode);
22092 emit_insn (gen_popcntbsi2 (tmp1, src));
22094 tmp2 = gen_reg_rtx (SImode);
22095 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
22096 tmp3 = gen_reg_rtx (SImode);
22097 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
22099 tmp4 = gen_reg_rtx (SImode);
22100 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
22101 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
22104 rs6000_emit_popcount (tmp, src);
22105 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
22109 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
22110 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
22112 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
22114 tmp1 = gen_reg_rtx (DImode);
22115 emit_insn (gen_popcntbdi2 (tmp1, src));
22117 tmp2 = gen_reg_rtx (DImode);
22118 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
22119 tmp3 = gen_reg_rtx (DImode);
22120 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
22122 tmp4 = gen_reg_rtx (DImode);
22123 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
22124 tmp5 = gen_reg_rtx (DImode);
22125 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
22127 tmp6 = gen_reg_rtx (DImode);
22128 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
22129 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
22132 rs6000_emit_popcount (tmp, src);
22133 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
22137 /* Return an RTX representing where to find the function value of a
22138 function returning MODE. */
22140 rs6000_complex_function_value (enum machine_mode mode)
22142 unsigned int regno;
22144 enum machine_mode inner = GET_MODE_INNER (mode);
22145 unsigned int inner_bytes = GET_MODE_SIZE (inner);
22147 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22148 regno = FP_ARG_RETURN;
22151 regno = GP_ARG_RETURN;
22153 /* 32-bit is OK since it'll go in r3/r4. */
22154 if (TARGET_32BIT && inner_bytes >= 4)
22155 return gen_rtx_REG (mode, regno);
22158 if (inner_bytes >= 8)
22159 return gen_rtx_REG (mode, regno);
22161 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
22163 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
22164 GEN_INT (inner_bytes));
22165 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
22168 /* Define how to find the value returned by a function.
22169 VALTYPE is the data type of the value (as a tree).
22170 If the precise function being called is known, FUNC is its FUNCTION_DECL;
22171 otherwise, FUNC is 0.
22173 On the SPE, both FPs and vectors are returned in r3.
22175 On RS/6000 an integer value is in r3 and a floating-point value is in
22176 fp1, unless -msoft-float. */
22179 rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
22181 enum machine_mode mode;
22182 unsigned int regno;
22184 /* Special handling for structs in darwin64. */
22185 if (rs6000_darwin64_abi
22186 && TYPE_MODE (valtype) == BLKmode
22187 && TREE_CODE (valtype) == RECORD_TYPE
22188 && int_size_in_bytes (valtype) > 0)
22190 CUMULATIVE_ARGS valcum;
22194 valcum.fregno = FP_ARG_MIN_REG;
22195 valcum.vregno = ALTIVEC_ARG_MIN_REG;
22196 /* Do a trial code generation as if this were going to be passed as
22197 an argument; if any part goes in memory, we return NULL. */
22198 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
22201 /* Otherwise fall through to standard ABI rules. */
22204 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
22206 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22207 return gen_rtx_PARALLEL (DImode,
22209 gen_rtx_EXPR_LIST (VOIDmode,
22210 gen_rtx_REG (SImode, GP_ARG_RETURN),
22212 gen_rtx_EXPR_LIST (VOIDmode,
22213 gen_rtx_REG (SImode,
22214 GP_ARG_RETURN + 1),
22217 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
22219 return gen_rtx_PARALLEL (DCmode,
22221 gen_rtx_EXPR_LIST (VOIDmode,
22222 gen_rtx_REG (SImode, GP_ARG_RETURN),
22224 gen_rtx_EXPR_LIST (VOIDmode,
22225 gen_rtx_REG (SImode,
22226 GP_ARG_RETURN + 1),
22228 gen_rtx_EXPR_LIST (VOIDmode,
22229 gen_rtx_REG (SImode,
22230 GP_ARG_RETURN + 2),
22232 gen_rtx_EXPR_LIST (VOIDmode,
22233 gen_rtx_REG (SImode,
22234 GP_ARG_RETURN + 3),
22238 mode = TYPE_MODE (valtype);
22239 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
22240 || POINTER_TYPE_P (valtype))
22241 mode = TARGET_32BIT ? SImode : DImode;
22243 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22244 /* _Decimal128 must use an even/odd register pair. */
22245 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
22246 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
22247 regno = FP_ARG_RETURN;
22248 else if (TREE_CODE (valtype) == COMPLEX_TYPE
22249 && targetm.calls.split_complex_arg)
22250 return rs6000_complex_function_value (mode);
22251 else if (TREE_CODE (valtype) == VECTOR_TYPE
22252 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
22253 && ALTIVEC_VECTOR_MODE (mode))
22254 regno = ALTIVEC_ARG_RETURN;
22255 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
22256 && (mode == DFmode || mode == DCmode
22257 || mode == TFmode || mode == TCmode))
22258 return spe_build_register_parallel (mode, GP_ARG_RETURN);
22260 regno = GP_ARG_RETURN;
22262 return gen_rtx_REG (mode, regno);
22265 /* Define how to find the value returned by a library function
22266 assuming the value has mode MODE. */
22268 rs6000_libcall_value (enum machine_mode mode)
22270 unsigned int regno;
22272 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
22274 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22275 return gen_rtx_PARALLEL (DImode,
22277 gen_rtx_EXPR_LIST (VOIDmode,
22278 gen_rtx_REG (SImode, GP_ARG_RETURN),
22280 gen_rtx_EXPR_LIST (VOIDmode,
22281 gen_rtx_REG (SImode,
22282 GP_ARG_RETURN + 1),
22286 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22287 /* _Decimal128 must use an even/odd register pair. */
22288 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
22289 else if (SCALAR_FLOAT_MODE_P (mode)
22290 && TARGET_HARD_FLOAT && TARGET_FPRS)
22291 regno = FP_ARG_RETURN;
22292 else if (ALTIVEC_VECTOR_MODE (mode)
22293 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
22294 regno = ALTIVEC_ARG_RETURN;
22295 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
22296 return rs6000_complex_function_value (mode);
22297 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
22298 && (mode == DFmode || mode == DCmode
22299 || mode == TFmode || mode == TCmode))
22300 return spe_build_register_parallel (mode, GP_ARG_RETURN);
22302 regno = GP_ARG_RETURN;
22304 return gen_rtx_REG (mode, regno);
22307 /* Define the offset between two registers, FROM to be eliminated and its
22308 replacement TO, at the start of a routine. */
22310 rs6000_initial_elimination_offset (int from, int to)
22312 rs6000_stack_t *info = rs6000_stack_info ();
22313 HOST_WIDE_INT offset;
22315 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22316 offset = info->push_p ? 0 : -info->total_size;
22317 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22319 offset = info->push_p ? 0 : -info->total_size;
22320 if (FRAME_GROWS_DOWNWARD)
22321 offset += info->fixed_size + info->vars_size + info->parm_size;
22323 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
22324 offset = FRAME_GROWS_DOWNWARD
22325 ? info->fixed_size + info->vars_size + info->parm_size
22327 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
22328 offset = info->total_size;
22329 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22330 offset = info->push_p ? info->total_size : 0;
22331 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
22334 gcc_unreachable ();
22339 /* Return true if TYPE is a SPE or AltiVec opaque type. */
22342 rs6000_is_opaque_type (const_tree type)
22344 return (type == opaque_V2SI_type_node
22345 || type == opaque_V2SF_type_node
22346 || type == opaque_V4SI_type_node);
22350 rs6000_dwarf_register_span (rtx reg)
22355 && (SPE_VECTOR_MODE (GET_MODE (reg))
22356 || (TARGET_E500_DOUBLE
22357 && (GET_MODE (reg) == DFmode || GET_MODE (reg) == DDmode))))
22362 regno = REGNO (reg);
22364 /* The duality of the SPE register size wreaks all kinds of havoc.
22365 This is a way of distinguishing r0 in 32-bits from r0 in
22368 gen_rtx_PARALLEL (VOIDmode,
22371 gen_rtx_REG (SImode, regno + 1200),
22372 gen_rtx_REG (SImode, regno))
22374 gen_rtx_REG (SImode, regno),
22375 gen_rtx_REG (SImode, regno + 1200)));
22378 /* Fill in sizes for SPE register high parts in table used by unwinder. */
22381 rs6000_init_dwarf_reg_sizes_extra (tree address)
22386 enum machine_mode mode = TYPE_MODE (char_type_node);
22387 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
22388 rtx mem = gen_rtx_MEM (BLKmode, addr);
22389 rtx value = gen_int_mode (4, mode);
22391 for (i = 1201; i < 1232; i++)
22393 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
22394 HOST_WIDE_INT offset
22395 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
22397 emit_move_insn (adjust_address (mem, mode, offset), value);
22402 /* Map internal gcc register numbers to DWARF2 register numbers. */
22405 rs6000_dbx_register_number (unsigned int regno)
22407 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
22409 if (regno == MQ_REGNO)
22411 if (regno == LR_REGNO)
22413 if (regno == CTR_REGNO)
22415 if (CR_REGNO_P (regno))
22416 return regno - CR0_REGNO + 86;
22417 if (regno == XER_REGNO)
22419 if (ALTIVEC_REGNO_P (regno))
22420 return regno - FIRST_ALTIVEC_REGNO + 1124;
22421 if (regno == VRSAVE_REGNO)
22423 if (regno == VSCR_REGNO)
22425 if (regno == SPE_ACC_REGNO)
22427 if (regno == SPEFSCR_REGNO)
22429 /* SPE high reg number. We get these values of regno from
22430 rs6000_dwarf_register_span. */
22431 gcc_assert (regno >= 1200 && regno < 1232);
22435 /* target hook eh_return_filter_mode */
22436 static enum machine_mode
22437 rs6000_eh_return_filter_mode (void)
22439 return TARGET_32BIT ? SImode : word_mode;
22442 /* Target hook for scalar_mode_supported_p. */
22444 rs6000_scalar_mode_supported_p (enum machine_mode mode)
22446 if (DECIMAL_FLOAT_MODE_P (mode))
22449 return default_scalar_mode_supported_p (mode);
22452 /* Target hook for vector_mode_supported_p. */
22454 rs6000_vector_mode_supported_p (enum machine_mode mode)
22457 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
22460 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
22463 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
22470 /* Target hook for invalid_arg_for_unprototyped_fn. */
22471 static const char *
22472 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
22474 return (!rs6000_darwin64_abi
22476 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
22477 && (funcdecl == NULL_TREE
22478 || (TREE_CODE (funcdecl) == FUNCTION_DECL
22479 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
22480 ? N_("AltiVec argument passed to unprototyped function")
22484 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
22485 setup by using __stack_chk_fail_local hidden function instead of
22486 calling __stack_chk_fail directly. Otherwise it is better to call
22487 __stack_chk_fail directly. */
22490 rs6000_stack_protect_fail (void)
22492 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
22493 ? default_hidden_stack_protect_fail ()
22494 : default_external_stack_protect_fail ();
22497 #include "gt-rs6000.h"