1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "tm-constrs.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 static GTY(()) bool rs6000_cell_dont_microcode;
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups;
149 /* Align branch targets. */
150 static GTY(()) bool rs6000_align_branch_targets;
152 /* Support for -msched-costly-dep option. */
153 const char *rs6000_sched_costly_dep_str;
154 enum rs6000_dependence_cost rs6000_sched_costly_dep;
156 /* Support for -minsert-sched-nops option. */
157 const char *rs6000_sched_insert_nops_str;
158 enum rs6000_nop_insertion rs6000_sched_insert_nops;
160 /* Support targetm.vectorize.builtin_mask_for_load. */
161 static GTY(()) tree altivec_builtin_mask_for_load;
163 /* Size of long double. */
164 int rs6000_long_double_type_size;
166 /* IEEE quad extended precision long double. */
169 /* Whether -mabi=altivec has appeared. */
170 int rs6000_altivec_abi;
172 /* Nonzero if we want SPE ABI extensions. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
179 int rs6000_darwin64_abi;
181 /* Set to nonzero once AIX common-mode calls have been defined. */
182 static GTY(()) int common_mode_defined;
184 /* Save information from a "cmpxx" operation until the branch or scc is
186 rtx rs6000_compare_op0, rs6000_compare_op1;
187 int rs6000_compare_fp_p;
189 /* Label number of label created for -mrelocatable, to call to so we can
190 get the address of the GOT section */
191 int rs6000_pic_labelno;
194 /* Which abi to adhere to */
195 const char *rs6000_abi_name;
197 /* Semantics of the small data area */
198 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
200 /* Which small data model to use */
201 const char *rs6000_sdata_name = (char *)0;
203 /* Counter for labels which are to be placed in .fixup. */
204 int fixuplabelno = 0;
207 /* Bit size of immediate TLS offsets and string from which it is decoded. */
208 int rs6000_tls_size = 32;
209 const char *rs6000_tls_size_string;
211 /* ABI enumeration available for subtarget to use. */
212 enum rs6000_abi rs6000_current_abi;
214 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
218 const char *rs6000_debug_name;
219 int rs6000_debug_stack; /* debug stack applications */
220 int rs6000_debug_arg; /* debug argument handling */
222 /* Value is TRUE if register/mode pair is acceptable. */
223 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
225 /* Built in types. */
227 tree rs6000_builtin_types[RS6000_BTI_MAX];
228 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
230 const char *rs6000_traceback_name;
232 traceback_default = 0,
238 /* Flag to say the TOC is initialized */
240 char toc_label_name[10];
242 /* Cached value of rs6000_variable_issue. This is cached in
243 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
244 static short cached_can_issue_more;
246 static GTY(()) section *read_only_data_section;
247 static GTY(()) section *private_data_section;
248 static GTY(()) section *read_only_private_data_section;
249 static GTY(()) section *sdata2_section;
250 static GTY(()) section *toc_section;
252 /* Control alignment for fields within structures. */
253 /* String from -malign-XXXXX. */
254 int rs6000_alignment_flags;
256 /* True for any options that were explicitly set. */
258 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
259 bool alignment; /* True if -malign- was used. */
260 bool abi; /* True if -mabi=spe/nospe was used. */
261 bool spe; /* True if -mspe= was used. */
262 bool float_gprs; /* True if -mfloat-gprs= was used. */
263 bool isel; /* True if -misel was used. */
264 bool long_double; /* True if -mlong-double- was used. */
265 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
266 } rs6000_explicit_options;
268 struct builtin_description
270 /* mask is not const because we're going to alter it below. This
271 nonsense will go away when we rewrite the -march infrastructure
272 to give us more target flag bits. */
274 const enum insn_code icode;
275 const char *const name;
276 const enum rs6000_builtins code;
279 /* Target cpu costs. */
281 struct processor_costs {
282 const int mulsi; /* cost of SImode multiplication. */
283 const int mulsi_const; /* cost of SImode multiplication by constant. */
284 const int mulsi_const9; /* cost of SImode mult by short constant. */
285 const int muldi; /* cost of DImode multiplication. */
286 const int divsi; /* cost of SImode division. */
287 const int divdi; /* cost of DImode division. */
288 const int fp; /* cost of simple SFmode and DFmode insns. */
289 const int dmul; /* cost of DFmode multiplication (and fmadd). */
290 const int sdiv; /* cost of SFmode division (fdivs). */
291 const int ddiv; /* cost of DFmode division (fdiv). */
292 const int cache_line_size; /* cache line size in bytes. */
293 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
294 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
295 const int simultaneous_prefetches; /* number of parallel prefetch
299 const struct processor_costs *rs6000_cost;
301 /* Processor costs (relative to an add) */
303 /* Instruction size costs on 32bit processors. */
305 struct processor_costs size32_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
322 /* Instruction size costs on 64bit processors. */
324 struct processor_costs size64_cost = {
325 COSTS_N_INSNS (1), /* mulsi */
326 COSTS_N_INSNS (1), /* mulsi_const */
327 COSTS_N_INSNS (1), /* mulsi_const9 */
328 COSTS_N_INSNS (1), /* muldi */
329 COSTS_N_INSNS (1), /* divsi */
330 COSTS_N_INSNS (1), /* divdi */
331 COSTS_N_INSNS (1), /* fp */
332 COSTS_N_INSNS (1), /* dmul */
333 COSTS_N_INSNS (1), /* sdiv */
334 COSTS_N_INSNS (1), /* ddiv */
341 /* Instruction costs on RIOS1 processors. */
343 struct processor_costs rios1_cost = {
344 COSTS_N_INSNS (5), /* mulsi */
345 COSTS_N_INSNS (4), /* mulsi_const */
346 COSTS_N_INSNS (3), /* mulsi_const9 */
347 COSTS_N_INSNS (5), /* muldi */
348 COSTS_N_INSNS (19), /* divsi */
349 COSTS_N_INSNS (19), /* divdi */
350 COSTS_N_INSNS (2), /* fp */
351 COSTS_N_INSNS (2), /* dmul */
352 COSTS_N_INSNS (19), /* sdiv */
353 COSTS_N_INSNS (19), /* ddiv */
360 /* Instruction costs on RIOS2 processors. */
362 struct processor_costs rios2_cost = {
363 COSTS_N_INSNS (2), /* mulsi */
364 COSTS_N_INSNS (2), /* mulsi_const */
365 COSTS_N_INSNS (2), /* mulsi_const9 */
366 COSTS_N_INSNS (2), /* muldi */
367 COSTS_N_INSNS (13), /* divsi */
368 COSTS_N_INSNS (13), /* divdi */
369 COSTS_N_INSNS (2), /* fp */
370 COSTS_N_INSNS (2), /* dmul */
371 COSTS_N_INSNS (17), /* sdiv */
372 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
398 /* Instruction costs on MPCCORE processors. */
400 struct processor_costs mpccore_cost = {
401 COSTS_N_INSNS (2), /* mulsi */
402 COSTS_N_INSNS (2), /* mulsi_const */
403 COSTS_N_INSNS (2), /* mulsi_const9 */
404 COSTS_N_INSNS (2), /* muldi */
405 COSTS_N_INSNS (6), /* divsi */
406 COSTS_N_INSNS (6), /* divdi */
407 COSTS_N_INSNS (4), /* fp */
408 COSTS_N_INSNS (5), /* dmul */
409 COSTS_N_INSNS (10), /* sdiv */
410 COSTS_N_INSNS (17), /* ddiv */
417 /* Instruction costs on PPC403 processors. */
419 struct processor_costs ppc403_cost = {
420 COSTS_N_INSNS (4), /* mulsi */
421 COSTS_N_INSNS (4), /* mulsi_const */
422 COSTS_N_INSNS (4), /* mulsi_const9 */
423 COSTS_N_INSNS (4), /* muldi */
424 COSTS_N_INSNS (33), /* divsi */
425 COSTS_N_INSNS (33), /* divdi */
426 COSTS_N_INSNS (11), /* fp */
427 COSTS_N_INSNS (11), /* dmul */
428 COSTS_N_INSNS (11), /* sdiv */
429 COSTS_N_INSNS (11), /* ddiv */
436 /* Instruction costs on PPC405 processors. */
438 struct processor_costs ppc405_cost = {
439 COSTS_N_INSNS (5), /* mulsi */
440 COSTS_N_INSNS (4), /* mulsi_const */
441 COSTS_N_INSNS (3), /* mulsi_const9 */
442 COSTS_N_INSNS (5), /* muldi */
443 COSTS_N_INSNS (35), /* divsi */
444 COSTS_N_INSNS (35), /* divdi */
445 COSTS_N_INSNS (11), /* fp */
446 COSTS_N_INSNS (11), /* dmul */
447 COSTS_N_INSNS (11), /* sdiv */
448 COSTS_N_INSNS (11), /* ddiv */
455 /* Instruction costs on PPC440 processors. */
457 struct processor_costs ppc440_cost = {
458 COSTS_N_INSNS (3), /* mulsi */
459 COSTS_N_INSNS (2), /* mulsi_const */
460 COSTS_N_INSNS (2), /* mulsi_const9 */
461 COSTS_N_INSNS (3), /* muldi */
462 COSTS_N_INSNS (34), /* divsi */
463 COSTS_N_INSNS (34), /* divdi */
464 COSTS_N_INSNS (5), /* fp */
465 COSTS_N_INSNS (5), /* dmul */
466 COSTS_N_INSNS (19), /* sdiv */
467 COSTS_N_INSNS (33), /* ddiv */
474 /* Instruction costs on PPC601 processors. */
476 struct processor_costs ppc601_cost = {
477 COSTS_N_INSNS (5), /* mulsi */
478 COSTS_N_INSNS (5), /* mulsi_const */
479 COSTS_N_INSNS (5), /* mulsi_const9 */
480 COSTS_N_INSNS (5), /* muldi */
481 COSTS_N_INSNS (36), /* divsi */
482 COSTS_N_INSNS (36), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (5), /* dmul */
485 COSTS_N_INSNS (17), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
493 /* Instruction costs on PPC603 processors. */
495 struct processor_costs ppc603_cost = {
496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (37), /* divsi */
501 COSTS_N_INSNS (37), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (4), /* dmul */
504 COSTS_N_INSNS (18), /* sdiv */
505 COSTS_N_INSNS (33), /* ddiv */
512 /* Instruction costs on PPC604 processors. */
514 struct processor_costs ppc604_cost = {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (20), /* divsi */
520 COSTS_N_INSNS (20), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
531 /* Instruction costs on PPC604e processors. */
533 struct processor_costs ppc604e_cost = {
534 COSTS_N_INSNS (2), /* mulsi */
535 COSTS_N_INSNS (2), /* mulsi_const */
536 COSTS_N_INSNS (2), /* mulsi_const9 */
537 COSTS_N_INSNS (2), /* muldi */
538 COSTS_N_INSNS (20), /* divsi */
539 COSTS_N_INSNS (20), /* divdi */
540 COSTS_N_INSNS (3), /* fp */
541 COSTS_N_INSNS (3), /* dmul */
542 COSTS_N_INSNS (18), /* sdiv */
543 COSTS_N_INSNS (32), /* ddiv */
550 /* Instruction costs on PPC620 processors. */
552 struct processor_costs ppc620_cost = {
553 COSTS_N_INSNS (5), /* mulsi */
554 COSTS_N_INSNS (4), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (7), /* muldi */
557 COSTS_N_INSNS (21), /* divsi */
558 COSTS_N_INSNS (37), /* divdi */
559 COSTS_N_INSNS (3), /* fp */
560 COSTS_N_INSNS (3), /* dmul */
561 COSTS_N_INSNS (18), /* sdiv */
562 COSTS_N_INSNS (32), /* ddiv */
569 /* Instruction costs on PPC630 processors. */
571 struct processor_costs ppc630_cost = {
572 COSTS_N_INSNS (5), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (3), /* mulsi_const9 */
575 COSTS_N_INSNS (7), /* muldi */
576 COSTS_N_INSNS (21), /* divsi */
577 COSTS_N_INSNS (37), /* divdi */
578 COSTS_N_INSNS (3), /* fp */
579 COSTS_N_INSNS (3), /* dmul */
580 COSTS_N_INSNS (17), /* sdiv */
581 COSTS_N_INSNS (21), /* ddiv */
588 /* Instruction costs on Cell processor. */
589 /* COSTS_N_INSNS (1) ~ one add. */
591 struct processor_costs ppccell_cost = {
592 COSTS_N_INSNS (9/2)+2, /* mulsi */
593 COSTS_N_INSNS (6/2), /* mulsi_const */
594 COSTS_N_INSNS (6/2), /* mulsi_const9 */
595 COSTS_N_INSNS (15/2)+2, /* muldi */
596 COSTS_N_INSNS (38/2), /* divsi */
597 COSTS_N_INSNS (70/2), /* divdi */
598 COSTS_N_INSNS (10/2), /* fp */
599 COSTS_N_INSNS (10/2), /* dmul */
600 COSTS_N_INSNS (74/2), /* sdiv */
601 COSTS_N_INSNS (74/2), /* ddiv */
608 /* Instruction costs on PPC750 and PPC7400 processors. */
610 struct processor_costs ppc750_cost = {
611 COSTS_N_INSNS (5), /* mulsi */
612 COSTS_N_INSNS (3), /* mulsi_const */
613 COSTS_N_INSNS (2), /* mulsi_const9 */
614 COSTS_N_INSNS (5), /* muldi */
615 COSTS_N_INSNS (17), /* divsi */
616 COSTS_N_INSNS (17), /* divdi */
617 COSTS_N_INSNS (3), /* fp */
618 COSTS_N_INSNS (3), /* dmul */
619 COSTS_N_INSNS (17), /* sdiv */
620 COSTS_N_INSNS (31), /* ddiv */
627 /* Instruction costs on PPC7450 processors. */
629 struct processor_costs ppc7450_cost = {
630 COSTS_N_INSNS (4), /* mulsi */
631 COSTS_N_INSNS (3), /* mulsi_const */
632 COSTS_N_INSNS (3), /* mulsi_const9 */
633 COSTS_N_INSNS (4), /* muldi */
634 COSTS_N_INSNS (23), /* divsi */
635 COSTS_N_INSNS (23), /* divdi */
636 COSTS_N_INSNS (5), /* fp */
637 COSTS_N_INSNS (5), /* dmul */
638 COSTS_N_INSNS (21), /* sdiv */
639 COSTS_N_INSNS (35), /* ddiv */
646 /* Instruction costs on PPC8540 processors. */
648 struct processor_costs ppc8540_cost = {
649 COSTS_N_INSNS (4), /* mulsi */
650 COSTS_N_INSNS (4), /* mulsi_const */
651 COSTS_N_INSNS (4), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (19), /* divsi */
654 COSTS_N_INSNS (19), /* divdi */
655 COSTS_N_INSNS (4), /* fp */
656 COSTS_N_INSNS (4), /* dmul */
657 COSTS_N_INSNS (29), /* sdiv */
658 COSTS_N_INSNS (29), /* ddiv */
662 1, /* prefetch streams /*/
665 /* Instruction costs on POWER4 and POWER5 processors. */
667 struct processor_costs power4_cost = {
668 COSTS_N_INSNS (3), /* mulsi */
669 COSTS_N_INSNS (2), /* mulsi_const */
670 COSTS_N_INSNS (2), /* mulsi_const9 */
671 COSTS_N_INSNS (4), /* muldi */
672 COSTS_N_INSNS (18), /* divsi */
673 COSTS_N_INSNS (34), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (17), /* sdiv */
677 COSTS_N_INSNS (17), /* ddiv */
681 8, /* prefetch streams /*/
684 /* Instruction costs on POWER6 processors. */
686 struct processor_costs power6_cost = {
687 COSTS_N_INSNS (8), /* mulsi */
688 COSTS_N_INSNS (8), /* mulsi_const */
689 COSTS_N_INSNS (8), /* mulsi_const9 */
690 COSTS_N_INSNS (8), /* muldi */
691 COSTS_N_INSNS (22), /* divsi */
692 COSTS_N_INSNS (28), /* divdi */
693 COSTS_N_INSNS (3), /* fp */
694 COSTS_N_INSNS (3), /* dmul */
695 COSTS_N_INSNS (13), /* sdiv */
696 COSTS_N_INSNS (16), /* ddiv */
700 16, /* prefetch streams */
704 static bool rs6000_function_ok_for_sibcall (tree, tree);
705 static const char *rs6000_invalid_within_doloop (rtx);
706 static rtx rs6000_generate_compare (enum rtx_code);
707 static void rs6000_emit_stack_tie (void);
708 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
709 static rtx spe_synthesize_frame_save (rtx);
710 static bool spe_func_has_64bit_regs_p (void);
711 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
713 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
714 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
715 static unsigned rs6000_hash_constant (rtx);
716 static unsigned toc_hash_function (const void *);
717 static int toc_hash_eq (const void *, const void *);
718 static int constant_pool_expr_1 (rtx, int *, int *);
719 static bool constant_pool_expr_p (rtx);
720 static bool legitimate_small_data_p (enum machine_mode, rtx);
721 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
722 static struct machine_function * rs6000_init_machine_status (void);
723 static bool rs6000_assemble_integer (rtx, unsigned int, int);
724 static bool no_global_regs_above (int);
725 #ifdef HAVE_GAS_HIDDEN
726 static void rs6000_assemble_visibility (tree, int);
728 static int rs6000_ra_ever_killed (void);
729 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
730 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
731 static bool rs6000_ms_bitfield_layout_p (tree);
732 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
733 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
734 static const char *rs6000_mangle_type (tree);
735 extern const struct attribute_spec rs6000_attribute_table[];
736 static void rs6000_set_default_type_attributes (tree);
737 static bool rs6000_reg_live_or_pic_offset_p (int);
738 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
739 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
740 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
742 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
743 static bool rs6000_return_in_memory (tree, tree);
744 static void rs6000_file_start (void);
746 static int rs6000_elf_reloc_rw_mask (void);
747 static void rs6000_elf_asm_out_constructor (rtx, int);
748 static void rs6000_elf_asm_out_destructor (rtx, int);
749 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
750 static void rs6000_elf_asm_init_sections (void);
751 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
752 unsigned HOST_WIDE_INT);
753 static void rs6000_elf_encode_section_info (tree, rtx, int)
756 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
758 static void rs6000_xcoff_asm_output_anchor (rtx);
759 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
760 static void rs6000_xcoff_asm_init_sections (void);
761 static int rs6000_xcoff_reloc_rw_mask (void);
762 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
763 static section *rs6000_xcoff_select_section (tree, int,
764 unsigned HOST_WIDE_INT);
765 static void rs6000_xcoff_unique_section (tree, int);
766 static section *rs6000_xcoff_select_rtx_section
767 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
768 static const char * rs6000_xcoff_strip_name_encoding (const char *);
769 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
770 static void rs6000_xcoff_file_start (void);
771 static void rs6000_xcoff_file_end (void);
773 static int rs6000_variable_issue (FILE *, int, rtx, int);
774 static bool rs6000_rtx_costs (rtx, int, int, int *);
775 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
776 static void rs6000_sched_init (FILE *, int, int);
777 static bool is_microcoded_insn (rtx);
778 static bool is_nonpipeline_insn (rtx);
779 static bool is_cracked_insn (rtx);
780 static bool is_branch_slot_insn (rtx);
781 static bool is_load_insn (rtx);
782 static rtx get_store_dest (rtx pat);
783 static bool is_store_insn (rtx);
784 static bool set_to_load_agen (rtx,rtx);
785 static bool adjacent_mem_locations (rtx,rtx);
786 static int rs6000_adjust_priority (rtx, int);
787 static int rs6000_issue_rate (void);
788 static bool rs6000_is_costly_dependence (dep_t, int, int);
789 static rtx get_next_active_insn (rtx, rtx);
790 static bool insn_terminates_group_p (rtx , enum group_termination);
791 static bool insn_must_be_first_in_group (rtx);
792 static bool insn_must_be_last_in_group (rtx);
793 static bool is_costly_group (rtx *, rtx);
794 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
795 static int redefine_groups (FILE *, int, rtx, rtx);
796 static int pad_groups (FILE *, int, rtx, rtx);
797 static void rs6000_sched_finish (FILE *, int);
798 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
799 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
800 static int rs6000_use_sched_lookahead (void);
801 static int rs6000_use_sched_lookahead_guard (rtx);
802 static tree rs6000_builtin_mask_for_load (void);
803 static tree rs6000_builtin_mul_widen_even (tree);
804 static tree rs6000_builtin_mul_widen_odd (tree);
805 static tree rs6000_builtin_conversion (enum tree_code, tree);
807 static void def_builtin (int, const char *, tree, int);
808 static bool rs6000_vector_alignment_reachable (tree, bool);
809 static void rs6000_init_builtins (void);
810 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
811 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
812 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
813 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
814 static void altivec_init_builtins (void);
815 static void rs6000_common_init_builtins (void);
816 static void rs6000_init_libfuncs (void);
818 static void enable_mask_for_builtins (struct builtin_description *, int,
819 enum rs6000_builtins,
820 enum rs6000_builtins);
821 static tree build_opaque_vector_type (tree, int);
822 static void spe_init_builtins (void);
823 static rtx spe_expand_builtin (tree, rtx, bool *);
824 static rtx spe_expand_stv_builtin (enum insn_code, tree);
825 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
826 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
827 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
828 static rs6000_stack_t *rs6000_stack_info (void);
829 static void debug_stack_info (rs6000_stack_t *);
831 static rtx altivec_expand_builtin (tree, rtx, bool *);
832 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
833 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
834 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
835 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
836 static rtx altivec_expand_predicate_builtin (enum insn_code,
837 const char *, tree, rtx);
838 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
839 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
840 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
841 static rtx altivec_expand_vec_set_builtin (tree);
842 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
843 static int get_element_number (tree, tree);
844 static bool rs6000_handle_option (size_t, const char *, int);
845 static void rs6000_parse_tls_size_option (void);
846 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
847 static int first_altivec_reg_to_save (void);
848 static unsigned int compute_vrsave_mask (void);
849 static void compute_save_world_info (rs6000_stack_t *info_ptr);
850 static void is_altivec_return_reg (rtx, void *);
851 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
852 int easy_vector_constant (rtx, enum machine_mode);
853 static bool rs6000_is_opaque_type (tree);
854 static rtx rs6000_dwarf_register_span (rtx);
855 static void rs6000_init_dwarf_reg_sizes_extra (tree);
856 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
857 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
858 static rtx rs6000_tls_get_addr (void);
859 static rtx rs6000_got_sym (void);
860 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
861 static const char *rs6000_get_some_local_dynamic_name (void);
862 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
863 static rtx rs6000_complex_function_value (enum machine_mode);
864 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
865 enum machine_mode, tree);
866 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
868 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
869 tree, HOST_WIDE_INT);
870 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
873 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
876 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
877 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
878 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
879 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
880 enum machine_mode, tree,
882 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
884 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
886 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
888 static void macho_branch_islands (void);
889 static int no_previous_def (tree function_name);
890 static tree get_prev_label (tree function_name);
891 static void rs6000_darwin_file_start (void);
894 static tree rs6000_build_builtin_va_list (void);
895 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
896 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
897 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
898 static bool rs6000_vector_mode_supported_p (enum machine_mode);
899 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
901 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
903 static int get_vsel_insn (enum machine_mode);
904 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
905 static tree rs6000_stack_protect_fail (void);
907 const int INSN_NOT_AVAILABLE = -1;
908 static enum machine_mode rs6000_eh_return_filter_mode (void);
910 /* Hash table stuff for keeping track of TOC entries. */
912 struct toc_hash_struct GTY(())
914 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
915 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
917 enum machine_mode key_mode;
921 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
923 /* Default register names. */
924 char rs6000_reg_names[][8] =
926 "0", "1", "2", "3", "4", "5", "6", "7",
927 "8", "9", "10", "11", "12", "13", "14", "15",
928 "16", "17", "18", "19", "20", "21", "22", "23",
929 "24", "25", "26", "27", "28", "29", "30", "31",
930 "0", "1", "2", "3", "4", "5", "6", "7",
931 "8", "9", "10", "11", "12", "13", "14", "15",
932 "16", "17", "18", "19", "20", "21", "22", "23",
933 "24", "25", "26", "27", "28", "29", "30", "31",
934 "mq", "lr", "ctr","ap",
935 "0", "1", "2", "3", "4", "5", "6", "7",
937 /* AltiVec registers. */
938 "0", "1", "2", "3", "4", "5", "6", "7",
939 "8", "9", "10", "11", "12", "13", "14", "15",
940 "16", "17", "18", "19", "20", "21", "22", "23",
941 "24", "25", "26", "27", "28", "29", "30", "31",
944 "spe_acc", "spefscr",
945 /* Soft frame pointer. */
949 #ifdef TARGET_REGNAMES
950 static const char alt_reg_names[][8] =
952 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
953 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
954 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
955 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
956 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
957 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
958 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
959 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
960 "mq", "lr", "ctr", "ap",
961 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
963 /* AltiVec registers. */
964 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
965 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
966 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
967 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
970 "spe_acc", "spefscr",
971 /* Soft frame pointer. */
976 #ifndef MASK_STRICT_ALIGN
977 #define MASK_STRICT_ALIGN 0
979 #ifndef TARGET_PROFILE_KERNEL
980 #define TARGET_PROFILE_KERNEL 0
983 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
984 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
986 /* Initialize the GCC target structure. */
987 #undef TARGET_ATTRIBUTE_TABLE
988 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
989 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
990 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
992 #undef TARGET_ASM_ALIGNED_DI_OP
993 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
995 /* Default unaligned ops are only provided for ELF. Find the ops needed
996 for non-ELF systems. */
997 #ifndef OBJECT_FORMAT_ELF
999 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1001 #undef TARGET_ASM_UNALIGNED_HI_OP
1002 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1003 #undef TARGET_ASM_UNALIGNED_SI_OP
1004 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1005 #undef TARGET_ASM_UNALIGNED_DI_OP
1006 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1009 #undef TARGET_ASM_UNALIGNED_HI_OP
1010 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1011 #undef TARGET_ASM_UNALIGNED_SI_OP
1012 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1013 #undef TARGET_ASM_UNALIGNED_DI_OP
1014 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1015 #undef TARGET_ASM_ALIGNED_DI_OP
1016 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1020 /* This hook deals with fixups for relocatable code and DI-mode objects
1022 #undef TARGET_ASM_INTEGER
1023 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1025 #ifdef HAVE_GAS_HIDDEN
1026 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1027 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1030 #undef TARGET_HAVE_TLS
1031 #define TARGET_HAVE_TLS HAVE_AS_TLS
1033 #undef TARGET_CANNOT_FORCE_CONST_MEM
1034 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1036 #undef TARGET_ASM_FUNCTION_PROLOGUE
1037 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1038 #undef TARGET_ASM_FUNCTION_EPILOGUE
1039 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1041 #undef TARGET_SCHED_VARIABLE_ISSUE
1042 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1044 #undef TARGET_SCHED_ISSUE_RATE
1045 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1046 #undef TARGET_SCHED_ADJUST_COST
1047 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1048 #undef TARGET_SCHED_ADJUST_PRIORITY
1049 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1050 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1051 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1052 #undef TARGET_SCHED_INIT
1053 #define TARGET_SCHED_INIT rs6000_sched_init
1054 #undef TARGET_SCHED_FINISH
1055 #define TARGET_SCHED_FINISH rs6000_sched_finish
1056 #undef TARGET_SCHED_REORDER
1057 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1058 #undef TARGET_SCHED_REORDER2
1059 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1061 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1062 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1064 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1065 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1067 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1068 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1069 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1070 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1071 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1072 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1073 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1074 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1076 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1077 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1079 #undef TARGET_INIT_BUILTINS
1080 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1082 #undef TARGET_EXPAND_BUILTIN
1083 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1085 #undef TARGET_MANGLE_TYPE
1086 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1088 #undef TARGET_INIT_LIBFUNCS
1089 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1092 #undef TARGET_BINDS_LOCAL_P
1093 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1096 #undef TARGET_MS_BITFIELD_LAYOUT_P
1097 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1099 #undef TARGET_ASM_OUTPUT_MI_THUNK
1100 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1102 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1103 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1105 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1106 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1108 #undef TARGET_INVALID_WITHIN_DOLOOP
1109 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1111 #undef TARGET_RTX_COSTS
1112 #define TARGET_RTX_COSTS rs6000_rtx_costs
1113 #undef TARGET_ADDRESS_COST
1114 #define TARGET_ADDRESS_COST hook_int_rtx_0
1116 #undef TARGET_VECTOR_OPAQUE_P
1117 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1119 #undef TARGET_DWARF_REGISTER_SPAN
1120 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1122 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1123 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1125 /* On rs6000, function arguments are promoted, as are function return
1127 #undef TARGET_PROMOTE_FUNCTION_ARGS
1128 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1129 #undef TARGET_PROMOTE_FUNCTION_RETURN
1130 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1132 #undef TARGET_RETURN_IN_MEMORY
1133 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1135 #undef TARGET_SETUP_INCOMING_VARARGS
1136 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1138 /* Always strict argument naming on rs6000. */
1139 #undef TARGET_STRICT_ARGUMENT_NAMING
1140 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1141 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1142 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1143 #undef TARGET_SPLIT_COMPLEX_ARG
1144 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1145 #undef TARGET_MUST_PASS_IN_STACK
1146 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1147 #undef TARGET_PASS_BY_REFERENCE
1148 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1149 #undef TARGET_ARG_PARTIAL_BYTES
1150 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1152 #undef TARGET_BUILD_BUILTIN_VA_LIST
1153 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1155 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1156 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1158 #undef TARGET_EH_RETURN_FILTER_MODE
1159 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1161 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1162 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1164 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1165 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1167 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1168 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1170 #undef TARGET_HANDLE_OPTION
1171 #define TARGET_HANDLE_OPTION rs6000_handle_option
1173 #undef TARGET_DEFAULT_TARGET_FLAGS
1174 #define TARGET_DEFAULT_TARGET_FLAGS \
1177 #undef TARGET_STACK_PROTECT_FAIL
1178 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1180 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1181 The PowerPC architecture requires only weak consistency among
1182 processors--that is, memory accesses between processors need not be
1183 sequentially consistent and memory accesses among processors can occur
1184 in any order. The ability to order memory accesses weakly provides
1185 opportunities for more efficient use of the system bus. Unless a
1186 dependency exists, the 604e allows read operations to precede store
1188 #undef TARGET_RELAXED_ORDERING
1189 #define TARGET_RELAXED_ORDERING true
1192 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1193 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1196 /* Use a 32-bit anchor range. This leads to sequences like:
1198 addis tmp,anchor,high
1201 where tmp itself acts as an anchor, and can be shared between
1202 accesses to the same 64k page. */
1203 #undef TARGET_MIN_ANCHOR_OFFSET
1204 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1205 #undef TARGET_MAX_ANCHOR_OFFSET
1206 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1207 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1208 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1210 struct gcc_target targetm = TARGET_INITIALIZER;
1213 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1216 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1218 /* The GPRs can hold any mode, but values bigger than one register
1219 cannot go past R31. */
1220 if (INT_REGNO_P (regno))
1221 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1223 /* The float registers can only hold floating modes and DImode.
1224 This excludes the 32-bit decimal float mode for now. */
1225 if (FP_REGNO_P (regno))
1227 (SCALAR_FLOAT_MODE_P (mode)
1228 && (mode != TDmode || (regno % 2) == 0)
1230 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1231 || (GET_MODE_CLASS (mode) == MODE_INT
1232 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1234 /* The CR register can only hold CC modes. */
1235 if (CR_REGNO_P (regno))
1236 return GET_MODE_CLASS (mode) == MODE_CC;
1238 if (XER_REGNO_P (regno))
1239 return mode == PSImode;
1241 /* AltiVec only in AldyVec registers. */
1242 if (ALTIVEC_REGNO_P (regno))
1243 return ALTIVEC_VECTOR_MODE (mode);
1245 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1246 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1249 /* We cannot put TImode anywhere except general register and it must be
1250 able to fit within the register set. */
1252 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1255 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1257 rs6000_init_hard_regno_mode_ok (void)
1261 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1262 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1263 if (rs6000_hard_regno_mode_ok (r, m))
1264 rs6000_hard_regno_mode_ok_p[m][r] = true;
1268 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1271 darwin_rs6000_override_options (void)
1273 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1275 rs6000_altivec_abi = 1;
1276 TARGET_ALTIVEC_VRSAVE = 1;
1277 if (DEFAULT_ABI == ABI_DARWIN)
1279 if (MACHO_DYNAMIC_NO_PIC_P)
1282 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1285 else if (flag_pic == 1)
1290 if (TARGET_64BIT && ! TARGET_POWERPC64)
1292 target_flags |= MASK_POWERPC64;
1293 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1297 rs6000_default_long_calls = 1;
1298 target_flags |= MASK_SOFT_FLOAT;
1301 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1303 if (!flag_mkernel && !flag_apple_kext
1305 && ! (target_flags_explicit & MASK_ALTIVEC))
1306 target_flags |= MASK_ALTIVEC;
1308 /* Unless the user (not the configurer) has explicitly overridden
1309 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1310 G4 unless targetting the kernel. */
1313 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1314 && ! (target_flags_explicit & MASK_ALTIVEC)
1315 && ! rs6000_select[1].string)
1317 target_flags |= MASK_ALTIVEC;
1322 /* If not otherwise specified by a target, make 'long double' equivalent to
1325 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1326 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1329 /* Override command line options. Mostly we process the processor
1330 type and sometimes adjust other TARGET_ options. */
1333 rs6000_override_options (const char *default_cpu)
1336 struct rs6000_cpu_select *ptr;
1339 /* Simplifications for entries below. */
1342 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1343 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1346 /* This table occasionally claims that a processor does not support
1347 a particular feature even though it does, but the feature is slower
1348 than the alternative. Thus, it shouldn't be relied on as a
1349 complete description of the processor's support.
1351 Please keep this list in order, and don't forget to update the
1352 documentation in invoke.texi when adding a new processor or
1356 const char *const name; /* Canonical processor name. */
1357 const enum processor_type processor; /* Processor type enum value. */
1358 const int target_enable; /* Target flags to enable. */
1359 } const processor_target_table[]
1360 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1361 {"403", PROCESSOR_PPC403,
1362 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1363 {"405", PROCESSOR_PPC405,
1364 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1365 {"405fp", PROCESSOR_PPC405,
1366 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1367 {"440", PROCESSOR_PPC440,
1368 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1369 {"440fp", PROCESSOR_PPC440,
1370 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1371 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1372 {"601", PROCESSOR_PPC601,
1373 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1374 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1375 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1376 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1377 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1378 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1379 {"620", PROCESSOR_PPC620,
1380 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1381 {"630", PROCESSOR_PPC630,
1382 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1383 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1384 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1385 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1386 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1387 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1388 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1389 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1390 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1391 /* 8548 has a dummy entry for now. */
1392 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1393 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1394 {"970", PROCESSOR_POWER4,
1395 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1396 {"cell", PROCESSOR_CELL,
1397 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1398 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1399 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1400 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1401 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1402 {"G5", PROCESSOR_POWER4,
1403 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1404 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1405 {"power2", PROCESSOR_POWER,
1406 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1407 {"power3", PROCESSOR_PPC630,
1408 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1409 {"power4", PROCESSOR_POWER4,
1410 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1411 {"power5", PROCESSOR_POWER5,
1412 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1413 | MASK_MFCRF | MASK_POPCNTB},
1414 {"power5+", PROCESSOR_POWER5,
1415 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1416 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1417 {"power6", PROCESSOR_POWER6,
1418 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1419 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1420 {"power6x", PROCESSOR_POWER6,
1421 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1422 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1423 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1424 {"powerpc64", PROCESSOR_POWERPC64,
1425 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1426 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1427 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1428 {"rios2", PROCESSOR_RIOS2,
1429 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1430 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1431 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1432 {"rs64", PROCESSOR_RS64A,
1433 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1436 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1438 /* Some OSs don't support saving the high part of 64-bit registers on
1439 context switch. Other OSs don't support saving Altivec registers.
1440 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1441 settings; if the user wants either, the user must explicitly specify
1442 them and we won't interfere with the user's specification. */
1445 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1446 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1447 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1448 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1449 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1452 rs6000_init_hard_regno_mode_ok ();
1454 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1455 #ifdef OS_MISSING_POWERPC64
1456 if (OS_MISSING_POWERPC64)
1457 set_masks &= ~MASK_POWERPC64;
1459 #ifdef OS_MISSING_ALTIVEC
1460 if (OS_MISSING_ALTIVEC)
1461 set_masks &= ~MASK_ALTIVEC;
1464 /* Don't override by the processor default if given explicitly. */
1465 set_masks &= ~target_flags_explicit;
1467 /* Identify the processor type. */
1468 rs6000_select[0].string = default_cpu;
1469 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1471 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1473 ptr = &rs6000_select[i];
1474 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1476 for (j = 0; j < ptt_size; j++)
1477 if (! strcmp (ptr->string, processor_target_table[j].name))
1479 if (ptr->set_tune_p)
1480 rs6000_cpu = processor_target_table[j].processor;
1482 if (ptr->set_arch_p)
1484 target_flags &= ~set_masks;
1485 target_flags |= (processor_target_table[j].target_enable
1492 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1499 /* If we are optimizing big endian systems for space, use the load/store
1500 multiple and string instructions. */
1501 if (BYTES_BIG_ENDIAN && optimize_size)
1502 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1504 /* Don't allow -mmultiple or -mstring on little endian systems
1505 unless the cpu is a 750, because the hardware doesn't support the
1506 instructions used in little endian mode, and causes an alignment
1507 trap. The 750 does not cause an alignment trap (except when the
1508 target is unaligned). */
1510 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1512 if (TARGET_MULTIPLE)
1514 target_flags &= ~MASK_MULTIPLE;
1515 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1516 warning (0, "-mmultiple is not supported on little endian systems");
1521 target_flags &= ~MASK_STRING;
1522 if ((target_flags_explicit & MASK_STRING) != 0)
1523 warning (0, "-mstring is not supported on little endian systems");
1527 /* Set debug flags */
1528 if (rs6000_debug_name)
1530 if (! strcmp (rs6000_debug_name, "all"))
1531 rs6000_debug_stack = rs6000_debug_arg = 1;
1532 else if (! strcmp (rs6000_debug_name, "stack"))
1533 rs6000_debug_stack = 1;
1534 else if (! strcmp (rs6000_debug_name, "arg"))
1535 rs6000_debug_arg = 1;
1537 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1540 if (rs6000_traceback_name)
1542 if (! strncmp (rs6000_traceback_name, "full", 4))
1543 rs6000_traceback = traceback_full;
1544 else if (! strncmp (rs6000_traceback_name, "part", 4))
1545 rs6000_traceback = traceback_part;
1546 else if (! strncmp (rs6000_traceback_name, "no", 2))
1547 rs6000_traceback = traceback_none;
1549 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1550 rs6000_traceback_name);
1553 if (!rs6000_explicit_options.long_double)
1554 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1556 #ifndef POWERPC_LINUX
1557 if (!rs6000_explicit_options.ieee)
1558 rs6000_ieeequad = 1;
1561 /* Set Altivec ABI as default for powerpc64 linux. */
1562 if (TARGET_ELF && TARGET_64BIT)
1564 rs6000_altivec_abi = 1;
1565 TARGET_ALTIVEC_VRSAVE = 1;
1568 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1569 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1571 rs6000_darwin64_abi = 1;
1573 darwin_one_byte_bool = 1;
1575 /* Default to natural alignment, for better performance. */
1576 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1579 /* Place FP constants in the constant pool instead of TOC
1580 if section anchors enabled. */
1581 if (flag_section_anchors)
1582 TARGET_NO_FP_IN_TOC = 1;
1584 /* Handle -mtls-size option. */
1585 rs6000_parse_tls_size_option ();
1587 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1588 SUBTARGET_OVERRIDE_OPTIONS;
1590 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1591 SUBSUBTARGET_OVERRIDE_OPTIONS;
1593 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1594 SUB3TARGET_OVERRIDE_OPTIONS;
1599 /* The e500 does not have string instructions, and we set
1600 MASK_STRING above when optimizing for size. */
1601 if ((target_flags & MASK_STRING) != 0)
1602 target_flags = target_flags & ~MASK_STRING;
1604 else if (rs6000_select[1].string != NULL)
1606 /* For the powerpc-eabispe configuration, we set all these by
1607 default, so let's unset them if we manually set another
1608 CPU that is not the E500. */
1609 if (!rs6000_explicit_options.abi)
1611 if (!rs6000_explicit_options.spe)
1613 if (!rs6000_explicit_options.float_gprs)
1614 rs6000_float_gprs = 0;
1615 if (!rs6000_explicit_options.isel)
1619 /* Detect invalid option combinations with E500. */
1622 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1623 && rs6000_cpu != PROCESSOR_POWER5
1624 && rs6000_cpu != PROCESSOR_POWER6
1625 && rs6000_cpu != PROCESSOR_CELL);
1626 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1627 || rs6000_cpu == PROCESSOR_POWER5);
1628 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1629 || rs6000_cpu == PROCESSOR_POWER5
1630 || rs6000_cpu == PROCESSOR_POWER6);
1632 rs6000_sched_restricted_insns_priority
1633 = (rs6000_sched_groups ? 1 : 0);
1635 /* Handle -msched-costly-dep option. */
1636 rs6000_sched_costly_dep
1637 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1639 if (rs6000_sched_costly_dep_str)
1641 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1642 rs6000_sched_costly_dep = no_dep_costly;
1643 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1644 rs6000_sched_costly_dep = all_deps_costly;
1645 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1646 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1647 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1648 rs6000_sched_costly_dep = store_to_load_dep_costly;
1650 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1653 /* Handle -minsert-sched-nops option. */
1654 rs6000_sched_insert_nops
1655 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1657 if (rs6000_sched_insert_nops_str)
1659 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1660 rs6000_sched_insert_nops = sched_finish_none;
1661 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1662 rs6000_sched_insert_nops = sched_finish_pad_groups;
1663 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1664 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1666 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1669 #ifdef TARGET_REGNAMES
1670 /* If the user desires alternate register names, copy in the
1671 alternate names now. */
1672 if (TARGET_REGNAMES)
1673 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1676 /* Set aix_struct_return last, after the ABI is determined.
1677 If -maix-struct-return or -msvr4-struct-return was explicitly
1678 used, don't override with the ABI default. */
1679 if (!rs6000_explicit_options.aix_struct_ret)
1680 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1682 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1683 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1686 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1688 /* We can only guarantee the availability of DI pseudo-ops when
1689 assembling for 64-bit targets. */
1692 targetm.asm_out.aligned_op.di = NULL;
1693 targetm.asm_out.unaligned_op.di = NULL;
1696 /* Set branch target alignment, if not optimizing for size. */
1699 /* Cell wants to be aligned 8byte for dual issue. */
1700 if (rs6000_cpu == PROCESSOR_CELL)
1702 if (align_functions <= 0)
1703 align_functions = 8;
1704 if (align_jumps <= 0)
1706 if (align_loops <= 0)
1709 if (rs6000_align_branch_targets)
1711 if (align_functions <= 0)
1712 align_functions = 16;
1713 if (align_jumps <= 0)
1715 if (align_loops <= 0)
1718 if (align_jumps_max_skip <= 0)
1719 align_jumps_max_skip = 15;
1720 if (align_loops_max_skip <= 0)
1721 align_loops_max_skip = 15;
1724 /* Arrange to save and restore machine status around nested functions. */
1725 init_machine_status = rs6000_init_machine_status;
1727 /* We should always be splitting complex arguments, but we can't break
1728 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1729 if (DEFAULT_ABI != ABI_AIX)
1730 targetm.calls.split_complex_arg = NULL;
1732 /* Initialize rs6000_cost with the appropriate target costs. */
1734 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1738 case PROCESSOR_RIOS1:
1739 rs6000_cost = &rios1_cost;
1742 case PROCESSOR_RIOS2:
1743 rs6000_cost = &rios2_cost;
1746 case PROCESSOR_RS64A:
1747 rs6000_cost = &rs64a_cost;
1750 case PROCESSOR_MPCCORE:
1751 rs6000_cost = &mpccore_cost;
1754 case PROCESSOR_PPC403:
1755 rs6000_cost = &ppc403_cost;
1758 case PROCESSOR_PPC405:
1759 rs6000_cost = &ppc405_cost;
1762 case PROCESSOR_PPC440:
1763 rs6000_cost = &ppc440_cost;
1766 case PROCESSOR_PPC601:
1767 rs6000_cost = &ppc601_cost;
1770 case PROCESSOR_PPC603:
1771 rs6000_cost = &ppc603_cost;
1774 case PROCESSOR_PPC604:
1775 rs6000_cost = &ppc604_cost;
1778 case PROCESSOR_PPC604e:
1779 rs6000_cost = &ppc604e_cost;
1782 case PROCESSOR_PPC620:
1783 rs6000_cost = &ppc620_cost;
1786 case PROCESSOR_PPC630:
1787 rs6000_cost = &ppc630_cost;
1790 case PROCESSOR_CELL:
1791 rs6000_cost = &ppccell_cost;
1794 case PROCESSOR_PPC750:
1795 case PROCESSOR_PPC7400:
1796 rs6000_cost = &ppc750_cost;
1799 case PROCESSOR_PPC7450:
1800 rs6000_cost = &ppc7450_cost;
1803 case PROCESSOR_PPC8540:
1804 rs6000_cost = &ppc8540_cost;
1807 case PROCESSOR_POWER4:
1808 case PROCESSOR_POWER5:
1809 rs6000_cost = &power4_cost;
1812 case PROCESSOR_POWER6:
1813 rs6000_cost = &power6_cost;
1820 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1821 set_param_value ("simultaneous-prefetches",
1822 rs6000_cost->simultaneous_prefetches);
1823 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1824 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1825 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1826 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1827 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1828 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1831 /* Implement targetm.vectorize.builtin_mask_for_load. */
1833 rs6000_builtin_mask_for_load (void)
1836 return altivec_builtin_mask_for_load;
1841 /* Implement targetm.vectorize.builtin_conversion. */
1843 rs6000_builtin_conversion (enum tree_code code, tree type)
1845 if (!TARGET_ALTIVEC)
1851 switch (TYPE_MODE (type))
1854 return TYPE_UNSIGNED (type) ?
1855 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1856 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1865 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1867 rs6000_builtin_mul_widen_even (tree type)
1869 if (!TARGET_ALTIVEC)
1872 switch (TYPE_MODE (type))
1875 return TYPE_UNSIGNED (type) ?
1876 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1877 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1880 return TYPE_UNSIGNED (type) ?
1881 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1882 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1888 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1890 rs6000_builtin_mul_widen_odd (tree type)
1892 if (!TARGET_ALTIVEC)
1895 switch (TYPE_MODE (type))
1898 return TYPE_UNSIGNED (type) ?
1899 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1900 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1903 return TYPE_UNSIGNED (type) ?
1904 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1905 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1912 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1913 after applying N number of iterations. This routine does not determine
1914 how may iterations are required to reach desired alignment. */
1917 rs6000_vector_alignment_reachable (tree type ATTRIBUTE_UNUSED, bool is_packed)
1924 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
1927 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
1937 /* Assuming that all other types are naturally aligned. CHECKME! */
1942 /* Handle generic options of the form -mfoo=yes/no.
1943 NAME is the option name.
1944 VALUE is the option value.
1945 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1946 whether the option value is 'yes' or 'no' respectively. */
1948 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1952 else if (!strcmp (value, "yes"))
1954 else if (!strcmp (value, "no"))
1957 error ("unknown -m%s= option specified: '%s'", name, value);
1960 /* Validate and record the size specified with the -mtls-size option. */
1963 rs6000_parse_tls_size_option (void)
1965 if (rs6000_tls_size_string == 0)
1967 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1968 rs6000_tls_size = 16;
1969 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1970 rs6000_tls_size = 32;
1971 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1972 rs6000_tls_size = 64;
1974 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1978 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1980 if (DEFAULT_ABI == ABI_DARWIN)
1981 /* The Darwin libraries never set errno, so we might as well
1982 avoid calling them when that's the only reason we would. */
1983 flag_errno_math = 0;
1985 /* Double growth factor to counter reduced min jump length. */
1986 set_param_value ("max-grow-copy-bb-insns", 16);
1988 /* Enable section anchors by default.
1989 Skip section anchors for Objective C and Objective C++
1990 until front-ends fixed. */
1991 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1992 flag_section_anchors = 1;
1995 /* Implement TARGET_HANDLE_OPTION. */
1998 rs6000_handle_option (size_t code, const char *arg, int value)
2003 target_flags &= ~(MASK_POWER | MASK_POWER2
2004 | MASK_MULTIPLE | MASK_STRING);
2005 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2006 | MASK_MULTIPLE | MASK_STRING);
2008 case OPT_mno_powerpc:
2009 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2010 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2011 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2012 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2015 target_flags &= ~MASK_MINIMAL_TOC;
2016 TARGET_NO_FP_IN_TOC = 0;
2017 TARGET_NO_SUM_IN_TOC = 0;
2018 target_flags_explicit |= MASK_MINIMAL_TOC;
2019 #ifdef TARGET_USES_SYSV4_OPT
2020 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2021 just the same as -mminimal-toc. */
2022 target_flags |= MASK_MINIMAL_TOC;
2023 target_flags_explicit |= MASK_MINIMAL_TOC;
2027 #ifdef TARGET_USES_SYSV4_OPT
2029 /* Make -mtoc behave like -mminimal-toc. */
2030 target_flags |= MASK_MINIMAL_TOC;
2031 target_flags_explicit |= MASK_MINIMAL_TOC;
2035 #ifdef TARGET_USES_AIX64_OPT
2040 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2041 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2042 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2045 #ifdef TARGET_USES_AIX64_OPT
2050 target_flags &= ~MASK_POWERPC64;
2051 target_flags_explicit |= MASK_POWERPC64;
2054 case OPT_minsert_sched_nops_:
2055 rs6000_sched_insert_nops_str = arg;
2058 case OPT_mminimal_toc:
2061 TARGET_NO_FP_IN_TOC = 0;
2062 TARGET_NO_SUM_IN_TOC = 0;
2069 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2070 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2077 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2078 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2082 case OPT_mpowerpc_gpopt:
2083 case OPT_mpowerpc_gfxopt:
2086 target_flags |= MASK_POWERPC;
2087 target_flags_explicit |= MASK_POWERPC;
2091 case OPT_maix_struct_return:
2092 case OPT_msvr4_struct_return:
2093 rs6000_explicit_options.aix_struct_ret = true;
2097 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2101 rs6000_explicit_options.isel = true;
2102 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2106 rs6000_explicit_options.spe = true;
2107 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2111 rs6000_debug_name = arg;
2114 #ifdef TARGET_USES_SYSV4_OPT
2116 rs6000_abi_name = arg;
2120 rs6000_sdata_name = arg;
2123 case OPT_mtls_size_:
2124 rs6000_tls_size_string = arg;
2127 case OPT_mrelocatable:
2130 target_flags |= MASK_MINIMAL_TOC;
2131 target_flags_explicit |= MASK_MINIMAL_TOC;
2132 TARGET_NO_FP_IN_TOC = 1;
2136 case OPT_mrelocatable_lib:
2139 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2140 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2141 TARGET_NO_FP_IN_TOC = 1;
2145 target_flags &= ~MASK_RELOCATABLE;
2146 target_flags_explicit |= MASK_RELOCATABLE;
2152 if (!strcmp (arg, "altivec"))
2154 rs6000_explicit_options.abi = true;
2155 rs6000_altivec_abi = 1;
2158 else if (! strcmp (arg, "no-altivec"))
2160 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2161 the default for rs6000_spe_abi to be chosen later. */
2162 rs6000_altivec_abi = 0;
2164 else if (! strcmp (arg, "spe"))
2166 rs6000_explicit_options.abi = true;
2168 rs6000_altivec_abi = 0;
2169 if (!TARGET_SPE_ABI)
2170 error ("not configured for ABI: '%s'", arg);
2172 else if (! strcmp (arg, "no-spe"))
2174 rs6000_explicit_options.abi = true;
2178 /* These are here for testing during development only, do not
2179 document in the manual please. */
2180 else if (! strcmp (arg, "d64"))
2182 rs6000_darwin64_abi = 1;
2183 warning (0, "Using darwin64 ABI");
2185 else if (! strcmp (arg, "d32"))
2187 rs6000_darwin64_abi = 0;
2188 warning (0, "Using old darwin ABI");
2191 else if (! strcmp (arg, "ibmlongdouble"))
2193 rs6000_explicit_options.ieee = true;
2194 rs6000_ieeequad = 0;
2195 warning (0, "Using IBM extended precision long double");
2197 else if (! strcmp (arg, "ieeelongdouble"))
2199 rs6000_explicit_options.ieee = true;
2200 rs6000_ieeequad = 1;
2201 warning (0, "Using IEEE extended precision long double");
2206 error ("unknown ABI specified: '%s'", arg);
2212 rs6000_select[1].string = arg;
2216 rs6000_select[2].string = arg;
2219 case OPT_mtraceback_:
2220 rs6000_traceback_name = arg;
2223 case OPT_mfloat_gprs_:
2224 rs6000_explicit_options.float_gprs = true;
2225 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2226 rs6000_float_gprs = 1;
2227 else if (! strcmp (arg, "double"))
2228 rs6000_float_gprs = 2;
2229 else if (! strcmp (arg, "no"))
2230 rs6000_float_gprs = 0;
2233 error ("invalid option for -mfloat-gprs: '%s'", arg);
2238 case OPT_mlong_double_:
2239 rs6000_explicit_options.long_double = true;
2240 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2241 if (value != 64 && value != 128)
2243 error ("Unknown switch -mlong-double-%s", arg);
2244 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2248 rs6000_long_double_type_size = value;
2251 case OPT_msched_costly_dep_:
2252 rs6000_sched_costly_dep_str = arg;
2256 rs6000_explicit_options.alignment = true;
2257 if (! strcmp (arg, "power"))
2259 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2260 some C library functions, so warn about it. The flag may be
2261 useful for performance studies from time to time though, so
2262 don't disable it entirely. */
2263 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2264 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2265 " it is incompatible with the installed C and C++ libraries");
2266 rs6000_alignment_flags = MASK_ALIGN_POWER;
2268 else if (! strcmp (arg, "natural"))
2269 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2272 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2280 /* Do anything needed at the start of the asm file. */
2283 rs6000_file_start (void)
2287 const char *start = buffer;
2288 struct rs6000_cpu_select *ptr;
2289 const char *default_cpu = TARGET_CPU_DEFAULT;
2290 FILE *file = asm_out_file;
2292 default_file_start ();
2294 #ifdef TARGET_BI_ARCH
2295 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2299 if (flag_verbose_asm)
2301 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2302 rs6000_select[0].string = default_cpu;
2304 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2306 ptr = &rs6000_select[i];
2307 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2309 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2314 if (PPC405_ERRATUM77)
2316 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2320 #ifdef USING_ELFOS_H
2321 switch (rs6000_sdata)
2323 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2324 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2325 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2326 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2329 if (rs6000_sdata && g_switch_value)
2331 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2341 #ifdef HAVE_AS_GNU_ATTRIBUTE
2342 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2343 fprintf (file, "\t.gnu_attribute 4, %d\n",
2344 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2347 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2349 switch_to_section (toc_section);
2350 switch_to_section (text_section);
2355 /* Return nonzero if this function is known to have a null epilogue. */
2358 direct_return (void)
2360 if (reload_completed)
2362 rs6000_stack_t *info = rs6000_stack_info ();
2364 if (info->first_gp_reg_save == 32
2365 && info->first_fp_reg_save == 64
2366 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2367 && ! info->lr_save_p
2368 && ! info->cr_save_p
2369 && info->vrsave_mask == 0
2377 /* Return the number of instructions it takes to form a constant in an
2378 integer register. */
2381 num_insns_constant_wide (HOST_WIDE_INT value)
2383 /* signed constant loadable with {cal|addi} */
2384 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2387 /* constant loadable with {cau|addis} */
2388 else if ((value & 0xffff) == 0
2389 && (value >> 31 == -1 || value >> 31 == 0))
2392 #if HOST_BITS_PER_WIDE_INT == 64
2393 else if (TARGET_POWERPC64)
2395 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2396 HOST_WIDE_INT high = value >> 31;
2398 if (high == 0 || high == -1)
2404 return num_insns_constant_wide (high) + 1;
2406 return (num_insns_constant_wide (high)
2407 + num_insns_constant_wide (low) + 1);
2416 num_insns_constant (rtx op, enum machine_mode mode)
2418 HOST_WIDE_INT low, high;
2420 switch (GET_CODE (op))
2423 #if HOST_BITS_PER_WIDE_INT == 64
2424 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2425 && mask64_operand (op, mode))
2429 return num_insns_constant_wide (INTVAL (op));
2437 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2438 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2439 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2442 if (mode == VOIDmode || mode == DImode)
2444 high = CONST_DOUBLE_HIGH (op);
2445 low = CONST_DOUBLE_LOW (op);
2452 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2453 if (DECIMAL_FLOAT_MODE_P (mode))
2454 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2456 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2457 high = l[WORDS_BIG_ENDIAN == 0];
2458 low = l[WORDS_BIG_ENDIAN != 0];
2462 return (num_insns_constant_wide (low)
2463 + num_insns_constant_wide (high));
2466 if ((high == 0 && low >= 0)
2467 || (high == -1 && low < 0))
2468 return num_insns_constant_wide (low);
2470 else if (mask64_operand (op, mode))
2474 return num_insns_constant_wide (high) + 1;
2477 return (num_insns_constant_wide (high)
2478 + num_insns_constant_wide (low) + 1);
2486 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2487 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2488 corresponding element of the vector, but for V4SFmode and V2SFmode,
2489 the corresponding "float" is interpreted as an SImode integer. */
2491 static HOST_WIDE_INT
2492 const_vector_elt_as_int (rtx op, unsigned int elt)
2494 rtx tmp = CONST_VECTOR_ELT (op, elt);
2495 if (GET_MODE (op) == V4SFmode
2496 || GET_MODE (op) == V2SFmode)
2497 tmp = gen_lowpart (SImode, tmp);
2498 return INTVAL (tmp);
2501 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2502 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2503 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2504 all items are set to the same value and contain COPIES replicas of the
2505 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2506 operand and the others are set to the value of the operand's msb. */
2509 vspltis_constant (rtx op, unsigned step, unsigned copies)
2511 enum machine_mode mode = GET_MODE (op);
2512 enum machine_mode inner = GET_MODE_INNER (mode);
2515 unsigned nunits = GET_MODE_NUNITS (mode);
2516 unsigned bitsize = GET_MODE_BITSIZE (inner);
2517 unsigned mask = GET_MODE_MASK (inner);
2519 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2520 HOST_WIDE_INT splat_val = val;
2521 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2523 /* Construct the value to be splatted, if possible. If not, return 0. */
2524 for (i = 2; i <= copies; i *= 2)
2526 HOST_WIDE_INT small_val;
2528 small_val = splat_val >> bitsize;
2530 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2532 splat_val = small_val;
2535 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2536 if (EASY_VECTOR_15 (splat_val))
2539 /* Also check if we can splat, and then add the result to itself. Do so if
2540 the value is positive, of if the splat instruction is using OP's mode;
2541 for splat_val < 0, the splat and the add should use the same mode. */
2542 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2543 && (splat_val >= 0 || (step == 1 && copies == 1)))
2549 /* Check if VAL is present in every STEP-th element, and the
2550 other elements are filled with its most significant bit. */
2551 for (i = 0; i < nunits - 1; ++i)
2553 HOST_WIDE_INT desired_val;
2554 if (((i + 1) & (step - 1)) == 0)
2557 desired_val = msb_val;
2559 if (desired_val != const_vector_elt_as_int (op, i))
2567 /* Return true if OP is of the given MODE and can be synthesized
2568 with a vspltisb, vspltish or vspltisw. */
2571 easy_altivec_constant (rtx op, enum machine_mode mode)
2573 unsigned step, copies;
2575 if (mode == VOIDmode)
2576 mode = GET_MODE (op);
2577 else if (mode != GET_MODE (op))
2580 /* Start with a vspltisw. */
2581 step = GET_MODE_NUNITS (mode) / 4;
2584 if (vspltis_constant (op, step, copies))
2587 /* Then try with a vspltish. */
2593 if (vspltis_constant (op, step, copies))
2596 /* And finally a vspltisb. */
2602 if (vspltis_constant (op, step, copies))
2608 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2609 result is OP. Abort if it is not possible. */
2612 gen_easy_altivec_constant (rtx op)
2614 enum machine_mode mode = GET_MODE (op);
2615 int nunits = GET_MODE_NUNITS (mode);
2616 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2617 unsigned step = nunits / 4;
2618 unsigned copies = 1;
2620 /* Start with a vspltisw. */
2621 if (vspltis_constant (op, step, copies))
2622 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2624 /* Then try with a vspltish. */
2630 if (vspltis_constant (op, step, copies))
2631 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2633 /* And finally a vspltisb. */
2639 if (vspltis_constant (op, step, copies))
2640 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2646 output_vec_const_move (rtx *operands)
2649 enum machine_mode mode;
2654 mode = GET_MODE (dest);
2659 if (zero_constant (vec, mode))
2660 return "vxor %0,%0,%0";
2662 splat_vec = gen_easy_altivec_constant (vec);
2663 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2664 operands[1] = XEXP (splat_vec, 0);
2665 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2668 switch (GET_MODE (splat_vec))
2671 return "vspltisw %0,%1";
2674 return "vspltish %0,%1";
2677 return "vspltisb %0,%1";
2684 gcc_assert (TARGET_SPE);
2686 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2687 pattern of V1DI, V4HI, and V2SF.
2689 FIXME: We should probably return # and add post reload
2690 splitters for these, but this way is so easy ;-). */
2691 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2692 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2693 operands[1] = CONST_VECTOR_ELT (vec, 0);
2694 operands[2] = CONST_VECTOR_ELT (vec, 1);
2696 return "li %0,%1\n\tevmergelo %0,%0,%0";
2698 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2701 /* Initialize vector TARGET to VALS. */
2704 rs6000_expand_vector_init (rtx target, rtx vals)
2706 enum machine_mode mode = GET_MODE (target);
2707 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2708 int n_elts = GET_MODE_NUNITS (mode);
2709 int n_var = 0, one_var = -1;
2710 bool all_same = true, all_const_zero = true;
2714 for (i = 0; i < n_elts; ++i)
2716 x = XVECEXP (vals, 0, i);
2717 if (!CONSTANT_P (x))
2718 ++n_var, one_var = i;
2719 else if (x != CONST0_RTX (inner_mode))
2720 all_const_zero = false;
2722 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2728 if (mode != V4SFmode && all_const_zero)
2730 /* Zero register. */
2731 emit_insn (gen_rtx_SET (VOIDmode, target,
2732 gen_rtx_XOR (mode, target, target)));
2735 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2737 /* Splat immediate. */
2738 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2742 ; /* Splat vector element. */
2745 /* Load from constant pool. */
2746 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2751 /* Store value to stack temp. Load vector element. Splat. */
2754 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2755 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2756 XVECEXP (vals, 0, 0));
2757 x = gen_rtx_UNSPEC (VOIDmode,
2758 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2759 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2761 gen_rtx_SET (VOIDmode,
2764 x = gen_rtx_VEC_SELECT (inner_mode, target,
2765 gen_rtx_PARALLEL (VOIDmode,
2766 gen_rtvec (1, const0_rtx)));
2767 emit_insn (gen_rtx_SET (VOIDmode, target,
2768 gen_rtx_VEC_DUPLICATE (mode, x)));
2772 /* One field is non-constant. Load constant then overwrite
2776 rtx copy = copy_rtx (vals);
2778 /* Load constant part of vector, substitute neighboring value for
2780 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2781 rs6000_expand_vector_init (target, copy);
2783 /* Insert variable. */
2784 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2788 /* Construct the vector in memory one field at a time
2789 and load the whole vector. */
2790 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2791 for (i = 0; i < n_elts; i++)
2792 emit_move_insn (adjust_address_nv (mem, inner_mode,
2793 i * GET_MODE_SIZE (inner_mode)),
2794 XVECEXP (vals, 0, i));
2795 emit_move_insn (target, mem);
2798 /* Set field ELT of TARGET to VAL. */
2801 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2803 enum machine_mode mode = GET_MODE (target);
2804 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2805 rtx reg = gen_reg_rtx (mode);
2807 int width = GET_MODE_SIZE (inner_mode);
2810 /* Load single variable value. */
2811 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2812 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2813 x = gen_rtx_UNSPEC (VOIDmode,
2814 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2815 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2817 gen_rtx_SET (VOIDmode,
2821 /* Linear sequence. */
2822 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2823 for (i = 0; i < 16; ++i)
2824 XVECEXP (mask, 0, i) = GEN_INT (i);
2826 /* Set permute mask to insert element into target. */
2827 for (i = 0; i < width; ++i)
2828 XVECEXP (mask, 0, elt*width + i)
2829 = GEN_INT (i + 0x10);
2830 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2831 x = gen_rtx_UNSPEC (mode,
2832 gen_rtvec (3, target, reg,
2833 force_reg (V16QImode, x)),
2835 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2838 /* Extract field ELT from VEC into TARGET. */
2841 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2843 enum machine_mode mode = GET_MODE (vec);
2844 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2847 /* Allocate mode-sized buffer. */
2848 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2850 /* Add offset to field within buffer matching vector element. */
2851 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2853 /* Store single field into mode-sized buffer. */
2854 x = gen_rtx_UNSPEC (VOIDmode,
2855 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2856 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2858 gen_rtx_SET (VOIDmode,
2861 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2864 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2865 implement ANDing by the mask IN. */
2867 build_mask64_2_operands (rtx in, rtx *out)
2869 #if HOST_BITS_PER_WIDE_INT >= 64
2870 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2873 gcc_assert (GET_CODE (in) == CONST_INT);
2878 /* Assume c initially something like 0x00fff000000fffff. The idea
2879 is to rotate the word so that the middle ^^^^^^ group of zeros
2880 is at the MS end and can be cleared with an rldicl mask. We then
2881 rotate back and clear off the MS ^^ group of zeros with a
2883 c = ~c; /* c == 0xff000ffffff00000 */
2884 lsb = c & -c; /* lsb == 0x0000000000100000 */
2885 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2886 c = ~c; /* c == 0x00fff000000fffff */
2887 c &= -lsb; /* c == 0x00fff00000000000 */
2888 lsb = c & -c; /* lsb == 0x0000100000000000 */
2889 c = ~c; /* c == 0xff000fffffffffff */
2890 c &= -lsb; /* c == 0xff00000000000000 */
2892 while ((lsb >>= 1) != 0)
2893 shift++; /* shift == 44 on exit from loop */
2894 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2895 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2896 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2900 /* Assume c initially something like 0xff000f0000000000. The idea
2901 is to rotate the word so that the ^^^ middle group of zeros
2902 is at the LS end and can be cleared with an rldicr mask. We then
2903 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2905 lsb = c & -c; /* lsb == 0x0000010000000000 */
2906 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2907 c = ~c; /* c == 0x00fff0ffffffffff */
2908 c &= -lsb; /* c == 0x00fff00000000000 */
2909 lsb = c & -c; /* lsb == 0x0000100000000000 */
2910 c = ~c; /* c == 0xff000fffffffffff */
2911 c &= -lsb; /* c == 0xff00000000000000 */
2913 while ((lsb >>= 1) != 0)
2914 shift++; /* shift == 44 on exit from loop */
2915 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2916 m1 >>= shift; /* m1 == 0x0000000000000fff */
2917 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2920 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2921 masks will be all 1's. We are guaranteed more than one transition. */
2922 out[0] = GEN_INT (64 - shift);
2923 out[1] = GEN_INT (m1);
2924 out[2] = GEN_INT (shift);
2925 out[3] = GEN_INT (m2);
2933 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2936 invalid_e500_subreg (rtx op, enum machine_mode mode)
2938 if (TARGET_E500_DOUBLE)
2940 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2941 subreg:TI and reg:TF. */
2942 if (GET_CODE (op) == SUBREG
2943 && (mode == SImode || mode == DImode || mode == TImode)
2944 && REG_P (SUBREG_REG (op))
2945 && (GET_MODE (SUBREG_REG (op)) == DFmode
2946 || GET_MODE (SUBREG_REG (op)) == TFmode))
2949 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2951 if (GET_CODE (op) == SUBREG
2952 && (mode == DFmode || mode == TFmode)
2953 && REG_P (SUBREG_REG (op))
2954 && (GET_MODE (SUBREG_REG (op)) == DImode
2955 || GET_MODE (SUBREG_REG (op)) == TImode))
2960 && GET_CODE (op) == SUBREG
2962 && REG_P (SUBREG_REG (op))
2963 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2969 /* AIX increases natural record alignment to doubleword if the first
2970 field is an FP double while the FP fields remain word aligned. */
2973 rs6000_special_round_type_align (tree type, unsigned int computed,
2974 unsigned int specified)
2976 unsigned int align = MAX (computed, specified);
2977 tree field = TYPE_FIELDS (type);
2979 /* Skip all non field decls */
2980 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2981 field = TREE_CHAIN (field);
2983 if (field != NULL && field != type)
2985 type = TREE_TYPE (field);
2986 while (TREE_CODE (type) == ARRAY_TYPE)
2987 type = TREE_TYPE (type);
2989 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2990 align = MAX (align, 64);
2996 /* Darwin increases record alignment to the natural alignment of
3000 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3001 unsigned int specified)
3003 unsigned int align = MAX (computed, specified);
3005 if (TYPE_PACKED (type))
3008 /* Find the first field, looking down into aggregates. */
3010 tree field = TYPE_FIELDS (type);
3011 /* Skip all non field decls */
3012 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3013 field = TREE_CHAIN (field);
3016 type = TREE_TYPE (field);
3017 while (TREE_CODE (type) == ARRAY_TYPE)
3018 type = TREE_TYPE (type);
3019 } while (AGGREGATE_TYPE_P (type));
3021 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3022 align = MAX (align, TYPE_ALIGN (type));
3027 /* Return 1 for an operand in small memory on V.4/eabi. */
3030 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3031 enum machine_mode mode ATTRIBUTE_UNUSED)
3036 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3039 if (DEFAULT_ABI != ABI_V4)
3042 if (GET_CODE (op) == SYMBOL_REF)
3045 else if (GET_CODE (op) != CONST
3046 || GET_CODE (XEXP (op, 0)) != PLUS
3047 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3048 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3053 rtx sum = XEXP (op, 0);
3054 HOST_WIDE_INT summand;
3056 /* We have to be careful here, because it is the referenced address
3057 that must be 32k from _SDA_BASE_, not just the symbol. */
3058 summand = INTVAL (XEXP (sum, 1));
3059 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3062 sym_ref = XEXP (sum, 0);
3065 return SYMBOL_REF_SMALL_P (sym_ref);
3071 /* Return true if either operand is a general purpose register. */
3074 gpr_or_gpr_p (rtx op0, rtx op1)
3076 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3077 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3081 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3084 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3086 switch (GET_CODE (op))
3089 if (RS6000_SYMBOL_REF_TLS_P (op))
3091 else if (CONSTANT_POOL_ADDRESS_P (op))
3093 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3101 else if (! strcmp (XSTR (op, 0), toc_label_name))
3110 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3111 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3113 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3122 constant_pool_expr_p (rtx op)
3126 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3130 toc_relative_expr_p (rtx op)
3134 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3138 legitimate_constant_pool_address_p (rtx x)
3141 && GET_CODE (x) == PLUS
3142 && GET_CODE (XEXP (x, 0)) == REG
3143 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3144 && constant_pool_expr_p (XEXP (x, 1)));
3148 legitimate_small_data_p (enum machine_mode mode, rtx x)
3150 return (DEFAULT_ABI == ABI_V4
3151 && !flag_pic && !TARGET_TOC
3152 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3153 && small_data_operand (x, mode));
3156 /* SPE offset addressing is limited to 5-bits worth of double words. */
3157 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3160 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3162 unsigned HOST_WIDE_INT offset, extra;
3164 if (GET_CODE (x) != PLUS)
3166 if (GET_CODE (XEXP (x, 0)) != REG)
3168 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3170 if (legitimate_constant_pool_address_p (x))
3172 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3175 offset = INTVAL (XEXP (x, 1));
3183 /* AltiVec vector modes. Only reg+reg addressing is valid and
3184 constant offset zero should not occur due to canonicalization.
3185 Allow any offset when not strict before reload. */
3192 /* SPE vector modes. */
3193 return SPE_CONST_OFFSET_OK (offset);
3197 if (TARGET_E500_DOUBLE)
3198 return SPE_CONST_OFFSET_OK (offset);
3201 /* On e500v2, we may have:
3203 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3205 Which gets addressed with evldd instructions. */
3206 if (TARGET_E500_DOUBLE)
3207 return SPE_CONST_OFFSET_OK (offset);
3209 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3211 else if (offset & 3)
3216 if (TARGET_E500_DOUBLE)
3217 return (SPE_CONST_OFFSET_OK (offset)
3218 && SPE_CONST_OFFSET_OK (offset + 8));
3222 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3224 else if (offset & 3)
3235 return (offset < 0x10000) && (offset + extra < 0x10000);
3239 legitimate_indexed_address_p (rtx x, int strict)
3243 if (GET_CODE (x) != PLUS)
3249 /* Recognize the rtl generated by reload which we know will later be
3250 replaced with proper base and index regs. */
3252 && reload_in_progress
3253 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3257 return (REG_P (op0) && REG_P (op1)
3258 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3259 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3260 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3261 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3265 legitimate_indirect_address_p (rtx x, int strict)
3267 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3271 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3273 if (!TARGET_MACHO || !flag_pic
3274 || mode != SImode || GET_CODE (x) != MEM)
3278 if (GET_CODE (x) != LO_SUM)
3280 if (GET_CODE (XEXP (x, 0)) != REG)
3282 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3286 return CONSTANT_P (x);
3290 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3292 if (GET_CODE (x) != LO_SUM)
3294 if (GET_CODE (XEXP (x, 0)) != REG)
3296 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3298 /* Restrict addressing for DI because of our SUBREG hackery. */
3299 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3304 if (TARGET_ELF || TARGET_MACHO)
3306 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3310 if (GET_MODE_NUNITS (mode) != 1)
3312 if (GET_MODE_BITSIZE (mode) > 64
3313 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3314 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3317 return CONSTANT_P (x);
3324 /* Try machine-dependent ways of modifying an illegitimate address
3325 to be legitimate. If we find one, return the new, valid address.
3326 This is used from only one place: `memory_address' in explow.c.
3328 OLDX is the address as it was before break_out_memory_refs was
3329 called. In some cases it is useful to look at this to decide what
3332 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3334 It is always safe for this function to do nothing. It exists to
3335 recognize opportunities to optimize the output.
3337 On RS/6000, first check for the sum of a register with a constant
3338 integer that is out of range. If so, generate code to add the
3339 constant with the low-order 16 bits masked to the register and force
3340 this result into another register (this can be done with `cau').
3341 Then generate an address of REG+(CONST&0xffff), allowing for the
3342 possibility of bit 16 being a one.
3344 Then check for the sum of a register and something not constant, try to
3345 load the other things into a register and return the sum. */
3348 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3349 enum machine_mode mode)
3351 if (GET_CODE (x) == SYMBOL_REF)
3353 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3355 return rs6000_legitimize_tls_address (x, model);
3358 if (GET_CODE (x) == PLUS
3359 && GET_CODE (XEXP (x, 0)) == REG
3360 && GET_CODE (XEXP (x, 1)) == CONST_INT
3361 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3363 HOST_WIDE_INT high_int, low_int;
3365 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3366 high_int = INTVAL (XEXP (x, 1)) - low_int;
3367 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3368 GEN_INT (high_int)), 0);
3369 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3371 else if (GET_CODE (x) == PLUS
3372 && GET_CODE (XEXP (x, 0)) == REG
3373 && GET_CODE (XEXP (x, 1)) != CONST_INT
3374 && GET_MODE_NUNITS (mode) == 1
3375 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3377 || (((mode != DImode && mode != DFmode && mode != DDmode)
3378 || TARGET_E500_DOUBLE)
3379 && mode != TFmode && mode != TDmode))
3380 && (TARGET_POWERPC64 || mode != DImode)
3383 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3384 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3386 else if (ALTIVEC_VECTOR_MODE (mode))
3390 /* Make sure both operands are registers. */
3391 if (GET_CODE (x) == PLUS)
3392 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3393 force_reg (Pmode, XEXP (x, 1)));
3395 reg = force_reg (Pmode, x);
3398 else if (SPE_VECTOR_MODE (mode)
3399 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3400 || mode == DDmode || mode == TDmode
3401 || mode == DImode)))
3405 /* We accept [reg + reg] and [reg + OFFSET]. */
3407 if (GET_CODE (x) == PLUS)
3409 rtx op1 = XEXP (x, 0);
3410 rtx op2 = XEXP (x, 1);
3412 op1 = force_reg (Pmode, op1);
3414 if (GET_CODE (op2) != REG
3415 && (GET_CODE (op2) != CONST_INT
3416 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3417 op2 = force_reg (Pmode, op2);
3419 return gen_rtx_PLUS (Pmode, op1, op2);
3422 return force_reg (Pmode, x);
3428 && GET_CODE (x) != CONST_INT
3429 && GET_CODE (x) != CONST_DOUBLE
3431 && GET_MODE_NUNITS (mode) == 1
3432 && (GET_MODE_BITSIZE (mode) <= 32
3433 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3435 rtx reg = gen_reg_rtx (Pmode);
3436 emit_insn (gen_elf_high (reg, x));
3437 return gen_rtx_LO_SUM (Pmode, reg, x);
3439 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3442 && ! MACHO_DYNAMIC_NO_PIC_P
3444 && GET_CODE (x) != CONST_INT
3445 && GET_CODE (x) != CONST_DOUBLE
3447 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3451 rtx reg = gen_reg_rtx (Pmode);
3452 emit_insn (gen_macho_high (reg, x));
3453 return gen_rtx_LO_SUM (Pmode, reg, x);
3456 && constant_pool_expr_p (x)
3457 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3459 return create_TOC_reference (x);
3465 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3466 We need to emit DTP-relative relocations. */
3469 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3474 fputs ("\t.long\t", file);
3477 fputs (DOUBLE_INT_ASM_OP, file);
3482 output_addr_const (file, x);
3483 fputs ("@dtprel+0x8000", file);
3486 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3488 static GTY(()) rtx rs6000_tls_symbol;
3490 rs6000_tls_get_addr (void)
3492 if (!rs6000_tls_symbol)
3493 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3495 return rs6000_tls_symbol;
3498 /* Construct the SYMBOL_REF for TLS GOT references. */
3500 static GTY(()) rtx rs6000_got_symbol;
3502 rs6000_got_sym (void)
3504 if (!rs6000_got_symbol)
3506 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3507 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3508 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3511 return rs6000_got_symbol;
3514 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3515 this (thread-local) address. */
3518 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3522 dest = gen_reg_rtx (Pmode);
3523 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3529 tlsreg = gen_rtx_REG (Pmode, 13);
3530 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3534 tlsreg = gen_rtx_REG (Pmode, 2);
3535 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3539 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3543 tmp = gen_reg_rtx (Pmode);
3546 tlsreg = gen_rtx_REG (Pmode, 13);
3547 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3551 tlsreg = gen_rtx_REG (Pmode, 2);
3552 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3556 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3558 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3563 rtx r3, got, tga, tmp1, tmp2, eqv;
3565 /* We currently use relocations like @got@tlsgd for tls, which
3566 means the linker will handle allocation of tls entries, placing
3567 them in the .got section. So use a pointer to the .got section,
3568 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3569 or to secondary GOT sections used by 32-bit -fPIC. */
3571 got = gen_rtx_REG (Pmode, 2);
3575 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3578 rtx gsym = rs6000_got_sym ();
3579 got = gen_reg_rtx (Pmode);
3581 rs6000_emit_move (got, gsym, Pmode);
3587 tmp1 = gen_reg_rtx (Pmode);
3588 tmp2 = gen_reg_rtx (Pmode);
3589 tmp3 = gen_reg_rtx (Pmode);
3590 mem = gen_const_mem (Pmode, tmp1);
3592 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3593 emit_move_insn (tmp1,
3594 gen_rtx_REG (Pmode, LR_REGNO));
3595 emit_move_insn (tmp2, mem);
3596 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3597 last = emit_move_insn (got, tmp3);
3598 set_unique_reg_note (last, REG_EQUAL, gsym);
3599 maybe_encapsulate_block (first, last, gsym);
3604 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3606 r3 = gen_rtx_REG (Pmode, 3);
3608 insn = gen_tls_gd_64 (r3, got, addr);
3610 insn = gen_tls_gd_32 (r3, got, addr);
3613 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3614 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3615 insn = emit_call_insn (insn);
3616 CONST_OR_PURE_CALL_P (insn) = 1;
3617 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3618 insn = get_insns ();
3620 emit_libcall_block (insn, dest, r3, addr);
3622 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3624 r3 = gen_rtx_REG (Pmode, 3);
3626 insn = gen_tls_ld_64 (r3, got);
3628 insn = gen_tls_ld_32 (r3, got);
3631 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3632 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3633 insn = emit_call_insn (insn);
3634 CONST_OR_PURE_CALL_P (insn) = 1;
3635 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3636 insn = get_insns ();
3638 tmp1 = gen_reg_rtx (Pmode);
3639 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3641 emit_libcall_block (insn, tmp1, r3, eqv);
3642 if (rs6000_tls_size == 16)
3645 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3647 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3649 else if (rs6000_tls_size == 32)
3651 tmp2 = gen_reg_rtx (Pmode);
3653 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3655 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3658 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3660 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3664 tmp2 = gen_reg_rtx (Pmode);
3666 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3668 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3670 insn = gen_rtx_SET (Pmode, dest,
3671 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3677 /* IE, or 64-bit offset LE. */
3678 tmp2 = gen_reg_rtx (Pmode);
3680 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3682 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3685 insn = gen_tls_tls_64 (dest, tmp2, addr);
3687 insn = gen_tls_tls_32 (dest, tmp2, addr);
3695 /* Return 1 if X contains a thread-local symbol. */
3698 rs6000_tls_referenced_p (rtx x)
3700 if (! TARGET_HAVE_TLS)
3703 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3706 /* Return 1 if *X is a thread-local symbol. This is the same as
3707 rs6000_tls_symbol_ref except for the type of the unused argument. */
3710 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3712 return RS6000_SYMBOL_REF_TLS_P (*x);
3715 /* The convention appears to be to define this wherever it is used.
3716 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3717 is now used here. */
3718 #ifndef REG_MODE_OK_FOR_BASE_P
3719 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3722 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3723 replace the input X, or the original X if no replacement is called for.
3724 The output parameter *WIN is 1 if the calling macro should goto WIN,
3727 For RS/6000, we wish to handle large displacements off a base
3728 register by splitting the addend across an addiu/addis and the mem insn.
3729 This cuts number of extra insns needed from 3 to 1.
3731 On Darwin, we use this to generate code for floating point constants.
3732 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3733 The Darwin code is inside #if TARGET_MACHO because only then is
3734 machopic_function_base_name() defined. */
3736 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3737 int opnum, int type,
3738 int ind_levels ATTRIBUTE_UNUSED, int *win)
3740 /* We must recognize output that we have already generated ourselves. */
3741 if (GET_CODE (x) == PLUS
3742 && GET_CODE (XEXP (x, 0)) == PLUS
3743 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3744 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3745 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3747 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3748 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3749 opnum, (enum reload_type)type);
3755 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3756 && GET_CODE (x) == LO_SUM
3757 && GET_CODE (XEXP (x, 0)) == PLUS
3758 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3759 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3760 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3761 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3762 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3763 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3764 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3766 /* Result of previous invocation of this function on Darwin
3767 floating point constant. */
3768 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3769 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3770 opnum, (enum reload_type)type);
3776 /* Force ld/std non-word aligned offset into base register by wrapping
3778 if (GET_CODE (x) == PLUS
3779 && GET_CODE (XEXP (x, 0)) == REG
3780 && REGNO (XEXP (x, 0)) < 32
3781 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3782 && GET_CODE (XEXP (x, 1)) == CONST_INT
3783 && (INTVAL (XEXP (x, 1)) & 3) != 0
3784 && !ALTIVEC_VECTOR_MODE (mode)
3785 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3786 && TARGET_POWERPC64)
3788 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3789 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3790 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3791 opnum, (enum reload_type) type);
3796 if (GET_CODE (x) == PLUS
3797 && GET_CODE (XEXP (x, 0)) == REG
3798 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3799 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3800 && GET_CODE (XEXP (x, 1)) == CONST_INT
3801 && !SPE_VECTOR_MODE (mode)
3802 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3804 && !ALTIVEC_VECTOR_MODE (mode))
3806 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3807 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3809 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3811 /* Check for 32-bit overflow. */
3812 if (high + low != val)
3818 /* Reload the high part into a base reg; leave the low part
3819 in the mem directly. */
3821 x = gen_rtx_PLUS (GET_MODE (x),
3822 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3826 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3827 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3828 opnum, (enum reload_type)type);
3833 if (GET_CODE (x) == SYMBOL_REF
3834 && !ALTIVEC_VECTOR_MODE (mode)
3835 && !SPE_VECTOR_MODE (mode)
3837 && DEFAULT_ABI == ABI_DARWIN
3838 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3840 && DEFAULT_ABI == ABI_V4
3843 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3844 The same goes for DImode without 64-bit gprs and DFmode
3848 && (mode != DImode || TARGET_POWERPC64)
3849 && (mode != DFmode || TARGET_POWERPC64
3850 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3855 rtx offset = gen_rtx_CONST (Pmode,
3856 gen_rtx_MINUS (Pmode, x,
3857 machopic_function_base_sym ()));
3858 x = gen_rtx_LO_SUM (GET_MODE (x),
3859 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3860 gen_rtx_HIGH (Pmode, offset)), offset);
3864 x = gen_rtx_LO_SUM (GET_MODE (x),
3865 gen_rtx_HIGH (Pmode, x), x);
3867 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3868 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3869 opnum, (enum reload_type)type);
3874 /* Reload an offset address wrapped by an AND that represents the
3875 masking of the lower bits. Strip the outer AND and let reload
3876 convert the offset address into an indirect address. */
3878 && ALTIVEC_VECTOR_MODE (mode)
3879 && GET_CODE (x) == AND
3880 && GET_CODE (XEXP (x, 0)) == PLUS
3881 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3882 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3883 && GET_CODE (XEXP (x, 1)) == CONST_INT
3884 && INTVAL (XEXP (x, 1)) == -16)
3892 && constant_pool_expr_p (x)
3893 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3895 x = create_TOC_reference (x);
3903 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3904 that is a valid memory address for an instruction.
3905 The MODE argument is the machine mode for the MEM expression
3906 that wants to use this address.
3908 On the RS/6000, there are four valid address: a SYMBOL_REF that
3909 refers to a constant pool entry of an address (or the sum of it
3910 plus a constant), a short (16-bit signed) constant plus a register,
3911 the sum of two registers, or a register indirect, possibly with an
3912 auto-increment. For DFmode and DImode with a constant plus register,
3913 we must ensure that both words are addressable or PowerPC64 with offset
3916 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3917 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3918 because adjacent memory cells are accessed by adding word-sized offsets
3919 during assembly output. */
3921 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3923 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3925 && ALTIVEC_VECTOR_MODE (mode)
3926 && GET_CODE (x) == AND
3927 && GET_CODE (XEXP (x, 1)) == CONST_INT
3928 && INTVAL (XEXP (x, 1)) == -16)
3931 if (RS6000_SYMBOL_REF_TLS_P (x))
3933 if (legitimate_indirect_address_p (x, reg_ok_strict))
3935 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3936 && !ALTIVEC_VECTOR_MODE (mode)
3937 && !SPE_VECTOR_MODE (mode)
3940 /* Restrict addressing for DI because of our SUBREG hackery. */
3941 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3944 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3946 if (legitimate_small_data_p (mode, x))
3948 if (legitimate_constant_pool_address_p (x))
3950 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3952 && GET_CODE (x) == PLUS
3953 && GET_CODE (XEXP (x, 0)) == REG
3954 && (XEXP (x, 0) == virtual_stack_vars_rtx
3955 || XEXP (x, 0) == arg_pointer_rtx)
3956 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3958 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3963 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3965 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3966 && (TARGET_POWERPC64 || mode != DImode)
3967 && legitimate_indexed_address_p (x, reg_ok_strict))
3969 if (GET_CODE (x) == PRE_MODIFY
3973 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3975 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3976 && (TARGET_POWERPC64 || mode != DImode)
3977 && !ALTIVEC_VECTOR_MODE (mode)
3978 && !SPE_VECTOR_MODE (mode)
3979 /* Restrict addressing for DI because of our SUBREG hackery. */
3980 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3982 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
3983 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
3984 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
3985 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3987 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3992 /* Go to LABEL if ADDR (a legitimate address expression)
3993 has an effect that depends on the machine mode it is used for.
3995 On the RS/6000 this is true of all integral offsets (since AltiVec
3996 modes don't allow them) or is a pre-increment or decrement.
3998 ??? Except that due to conceptual problems in offsettable_address_p
3999 we can't really report the problems of integral offsets. So leave
4000 this assuming that the adjustable offset must be valid for the
4001 sub-words of a TFmode operand, which is what we had before. */
4004 rs6000_mode_dependent_address (rtx addr)
4006 switch (GET_CODE (addr))
4009 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4011 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4012 return val + 12 + 0x8000 >= 0x10000;
4022 return TARGET_UPDATE;
4031 /* More elaborate version of recog's offsettable_memref_p predicate
4032 that works around the ??? note of rs6000_mode_dependent_address.
4033 In particular it accepts
4035 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4037 in 32-bit mode, that the recog predicate rejects. */
4040 rs6000_offsettable_memref_p (rtx op)
4045 /* First mimic offsettable_memref_p. */
4046 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4049 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4050 the latter predicate knows nothing about the mode of the memory
4051 reference and, therefore, assumes that it is the largest supported
4052 mode (TFmode). As a consequence, legitimate offsettable memory
4053 references are rejected. rs6000_legitimate_offset_address_p contains
4054 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4055 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4058 /* Return number of consecutive hard regs needed starting at reg REGNO
4059 to hold something of mode MODE.
4060 This is ordinarily the length in words of a value of mode MODE
4061 but can be less for certain modes in special long registers.
4063 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4064 scalar instructions. The upper 32 bits are only available to the
4067 POWER and PowerPC GPRs hold 32 bits worth;
4068 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4071 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4073 if (FP_REGNO_P (regno))
4074 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4076 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4077 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4079 if (ALTIVEC_REGNO_P (regno))
4081 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4083 /* The value returned for SCmode in the E500 double case is 2 for
4084 ABI compatibility; storing an SCmode value in a single register
4085 would require function_arg and rs6000_spe_function_arg to handle
4086 SCmode so as to pass the value correctly in a pair of
4088 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
4089 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4091 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4094 /* Change register usage conditional on target flags. */
4096 rs6000_conditional_register_usage (void)
4100 /* Set MQ register fixed (already call_used) if not POWER
4101 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4106 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4108 fixed_regs[13] = call_used_regs[13]
4109 = call_really_used_regs[13] = 1;
4111 /* Conditionally disable FPRs. */
4112 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4113 for (i = 32; i < 64; i++)
4114 fixed_regs[i] = call_used_regs[i]
4115 = call_really_used_regs[i] = 1;
4117 /* The TOC register is not killed across calls in a way that is
4118 visible to the compiler. */
4119 if (DEFAULT_ABI == ABI_AIX)
4120 call_really_used_regs[2] = 0;
4122 if (DEFAULT_ABI == ABI_V4
4123 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4125 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4127 if (DEFAULT_ABI == ABI_V4
4128 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4130 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4131 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4132 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4134 if (DEFAULT_ABI == ABI_DARWIN
4135 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4136 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4137 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4138 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4140 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4141 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4142 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4145 global_regs[VSCR_REGNO] = 1;
4149 global_regs[SPEFSCR_REGNO] = 1;
4150 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4151 registers in prologues and epilogues. We no longer use r14
4152 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4153 pool for link-compatibility with older versions of GCC. Once
4154 "old" code has died out, we can return r14 to the allocation
4157 = call_used_regs[14]
4158 = call_really_used_regs[14] = 1;
4161 if (! TARGET_ALTIVEC)
4163 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4164 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4165 call_really_used_regs[VRSAVE_REGNO] = 1;
4168 if (TARGET_ALTIVEC_ABI)
4169 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4170 call_used_regs[i] = call_really_used_regs[i] = 1;
4173 /* Try to output insns to set TARGET equal to the constant C if it can
4174 be done in less than N insns. Do all computations in MODE.
4175 Returns the place where the output has been placed if it can be
4176 done and the insns have been emitted. If it would take more than N
4177 insns, zero is returned and no insns and emitted. */
4180 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4181 rtx source, int n ATTRIBUTE_UNUSED)
4183 rtx result, insn, set;
4184 HOST_WIDE_INT c0, c1;
4191 dest = gen_reg_rtx (mode);
4192 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4196 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4198 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4199 GEN_INT (INTVAL (source)
4200 & (~ (HOST_WIDE_INT) 0xffff))));
4201 emit_insn (gen_rtx_SET (VOIDmode, dest,
4202 gen_rtx_IOR (SImode, copy_rtx (result),
4203 GEN_INT (INTVAL (source) & 0xffff))));
4208 switch (GET_CODE (source))
4211 c0 = INTVAL (source);
4216 #if HOST_BITS_PER_WIDE_INT >= 64
4217 c0 = CONST_DOUBLE_LOW (source);
4220 c0 = CONST_DOUBLE_LOW (source);
4221 c1 = CONST_DOUBLE_HIGH (source);
4229 result = rs6000_emit_set_long_const (dest, c0, c1);
4236 insn = get_last_insn ();
4237 set = single_set (insn);
4238 if (! CONSTANT_P (SET_SRC (set)))
4239 set_unique_reg_note (insn, REG_EQUAL, source);
4244 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4245 fall back to a straight forward decomposition. We do this to avoid
4246 exponential run times encountered when looking for longer sequences
4247 with rs6000_emit_set_const. */
4249 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4251 if (!TARGET_POWERPC64)
4253 rtx operand1, operand2;
4255 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4257 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4259 emit_move_insn (operand1, GEN_INT (c1));
4260 emit_move_insn (operand2, GEN_INT (c2));
4264 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4267 ud2 = (c1 & 0xffff0000) >> 16;
4268 #if HOST_BITS_PER_WIDE_INT >= 64
4272 ud4 = (c2 & 0xffff0000) >> 16;
4274 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4275 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4278 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4280 emit_move_insn (dest, GEN_INT (ud1));
4283 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4284 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4287 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4290 emit_move_insn (dest, GEN_INT (ud2 << 16));
4292 emit_move_insn (copy_rtx (dest),
4293 gen_rtx_IOR (DImode, copy_rtx (dest),
4296 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4297 || (ud4 == 0 && ! (ud3 & 0x8000)))
4300 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4303 emit_move_insn (dest, GEN_INT (ud3 << 16));
4306 emit_move_insn (copy_rtx (dest),
4307 gen_rtx_IOR (DImode, copy_rtx (dest),
4309 emit_move_insn (copy_rtx (dest),
4310 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4313 emit_move_insn (copy_rtx (dest),
4314 gen_rtx_IOR (DImode, copy_rtx (dest),
4320 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4323 emit_move_insn (dest, GEN_INT (ud4 << 16));
4326 emit_move_insn (copy_rtx (dest),
4327 gen_rtx_IOR (DImode, copy_rtx (dest),
4330 emit_move_insn (copy_rtx (dest),
4331 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4334 emit_move_insn (copy_rtx (dest),
4335 gen_rtx_IOR (DImode, copy_rtx (dest),
4336 GEN_INT (ud2 << 16)));
4338 emit_move_insn (copy_rtx (dest),
4339 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4345 /* Helper for the following. Get rid of [r+r] memory refs
4346 in cases where it won't work (TImode, TFmode, TDmode). */
4349 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4351 if (GET_CODE (operands[0]) == MEM
4352 && GET_CODE (XEXP (operands[0], 0)) != REG
4353 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4354 && ! reload_in_progress)
4356 = replace_equiv_address (operands[0],
4357 copy_addr_to_reg (XEXP (operands[0], 0)));
4359 if (GET_CODE (operands[1]) == MEM
4360 && GET_CODE (XEXP (operands[1], 0)) != REG
4361 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4362 && ! reload_in_progress)
4364 = replace_equiv_address (operands[1],
4365 copy_addr_to_reg (XEXP (operands[1], 0)));
4368 /* Emit a move from SOURCE to DEST in mode MODE. */
4370 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4374 operands[1] = source;
4376 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4377 if (GET_CODE (operands[1]) == CONST_DOUBLE
4378 && ! FLOAT_MODE_P (mode)
4379 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4381 /* FIXME. This should never happen. */
4382 /* Since it seems that it does, do the safe thing and convert
4384 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4386 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4387 || FLOAT_MODE_P (mode)
4388 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4389 || CONST_DOUBLE_LOW (operands[1]) < 0)
4390 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4391 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4393 /* Check if GCC is setting up a block move that will end up using FP
4394 registers as temporaries. We must make sure this is acceptable. */
4395 if (GET_CODE (operands[0]) == MEM
4396 && GET_CODE (operands[1]) == MEM
4398 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4399 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4400 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4401 ? 32 : MEM_ALIGN (operands[0])))
4402 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4404 : MEM_ALIGN (operands[1]))))
4405 && ! MEM_VOLATILE_P (operands [0])
4406 && ! MEM_VOLATILE_P (operands [1]))
4408 emit_move_insn (adjust_address (operands[0], SImode, 0),
4409 adjust_address (operands[1], SImode, 0));
4410 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4411 adjust_address (copy_rtx (operands[1]), SImode, 4));
4415 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4416 && !gpc_reg_operand (operands[1], mode))
4417 operands[1] = force_reg (mode, operands[1]);
4419 if (mode == SFmode && ! TARGET_POWERPC
4420 && TARGET_HARD_FLOAT && TARGET_FPRS
4421 && GET_CODE (operands[0]) == MEM)
4425 if (reload_in_progress || reload_completed)
4426 regnum = true_regnum (operands[1]);
4427 else if (GET_CODE (operands[1]) == REG)
4428 regnum = REGNO (operands[1]);
4432 /* If operands[1] is a register, on POWER it may have
4433 double-precision data in it, so truncate it to single
4435 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4438 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4439 : gen_reg_rtx (mode));
4440 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4441 operands[1] = newreg;
4445 /* Recognize the case where operand[1] is a reference to thread-local
4446 data and load its address to a register. */
4447 if (rs6000_tls_referenced_p (operands[1]))
4449 enum tls_model model;
4450 rtx tmp = operands[1];
4453 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4455 addend = XEXP (XEXP (tmp, 0), 1);
4456 tmp = XEXP (XEXP (tmp, 0), 0);
4459 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4460 model = SYMBOL_REF_TLS_MODEL (tmp);
4461 gcc_assert (model != 0);
4463 tmp = rs6000_legitimize_tls_address (tmp, model);
4466 tmp = gen_rtx_PLUS (mode, tmp, addend);
4467 tmp = force_operand (tmp, operands[0]);
4472 /* Handle the case where reload calls us with an invalid address. */
4473 if (reload_in_progress && mode == Pmode
4474 && (! general_operand (operands[1], mode)
4475 || ! nonimmediate_operand (operands[0], mode)))
4478 /* 128-bit constant floating-point values on Darwin should really be
4479 loaded as two parts. */
4480 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4481 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4483 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4484 know how to get a DFmode SUBREG of a TFmode. */
4485 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4486 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4487 simplify_gen_subreg (imode, operands[1], mode, 0),
4489 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4490 GET_MODE_SIZE (imode)),
4491 simplify_gen_subreg (imode, operands[1], mode,
4492 GET_MODE_SIZE (imode)),
4497 /* FIXME: In the long term, this switch statement should go away
4498 and be replaced by a sequence of tests based on things like
4504 if (CONSTANT_P (operands[1])
4505 && GET_CODE (operands[1]) != CONST_INT)
4506 operands[1] = force_const_mem (mode, operands[1]);
4511 rs6000_eliminate_indexed_memrefs (operands);
4517 if (CONSTANT_P (operands[1])
4518 && ! easy_fp_constant (operands[1], mode))
4519 operands[1] = force_const_mem (mode, operands[1]);
4530 if (CONSTANT_P (operands[1])
4531 && !easy_vector_constant (operands[1], mode))
4532 operands[1] = force_const_mem (mode, operands[1]);
4537 /* Use default pattern for address of ELF small data */
4540 && DEFAULT_ABI == ABI_V4
4541 && (GET_CODE (operands[1]) == SYMBOL_REF
4542 || GET_CODE (operands[1]) == CONST)
4543 && small_data_operand (operands[1], mode))
4545 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4549 if (DEFAULT_ABI == ABI_V4
4550 && mode == Pmode && mode == SImode
4551 && flag_pic == 1 && got_operand (operands[1], mode))
4553 emit_insn (gen_movsi_got (operands[0], operands[1]));
4557 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4561 && CONSTANT_P (operands[1])
4562 && GET_CODE (operands[1]) != HIGH
4563 && GET_CODE (operands[1]) != CONST_INT)
4565 rtx target = (!can_create_pseudo_p ()
4567 : gen_reg_rtx (mode));
4569 /* If this is a function address on -mcall-aixdesc,
4570 convert it to the address of the descriptor. */
4571 if (DEFAULT_ABI == ABI_AIX
4572 && GET_CODE (operands[1]) == SYMBOL_REF
4573 && XSTR (operands[1], 0)[0] == '.')
4575 const char *name = XSTR (operands[1], 0);
4577 while (*name == '.')
4579 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4580 CONSTANT_POOL_ADDRESS_P (new_ref)
4581 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4582 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4583 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4584 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4585 operands[1] = new_ref;
4588 if (DEFAULT_ABI == ABI_DARWIN)
4591 if (MACHO_DYNAMIC_NO_PIC_P)
4593 /* Take care of any required data indirection. */
4594 operands[1] = rs6000_machopic_legitimize_pic_address (
4595 operands[1], mode, operands[0]);
4596 if (operands[0] != operands[1])
4597 emit_insn (gen_rtx_SET (VOIDmode,
4598 operands[0], operands[1]));
4602 emit_insn (gen_macho_high (target, operands[1]));
4603 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4607 emit_insn (gen_elf_high (target, operands[1]));
4608 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4612 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4613 and we have put it in the TOC, we just need to make a TOC-relative
4616 && GET_CODE (operands[1]) == SYMBOL_REF
4617 && constant_pool_expr_p (operands[1])
4618 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4619 get_pool_mode (operands[1])))
4621 operands[1] = create_TOC_reference (operands[1]);
4623 else if (mode == Pmode
4624 && CONSTANT_P (operands[1])
4625 && ((GET_CODE (operands[1]) != CONST_INT
4626 && ! easy_fp_constant (operands[1], mode))
4627 || (GET_CODE (operands[1]) == CONST_INT
4628 && num_insns_constant (operands[1], mode) > 2)
4629 || (GET_CODE (operands[0]) == REG
4630 && FP_REGNO_P (REGNO (operands[0]))))
4631 && GET_CODE (operands[1]) != HIGH
4632 && ! legitimate_constant_pool_address_p (operands[1])
4633 && ! toc_relative_expr_p (operands[1]))
4635 /* Emit a USE operation so that the constant isn't deleted if
4636 expensive optimizations are turned on because nobody
4637 references it. This should only be done for operands that
4638 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4639 This should not be done for operands that contain LABEL_REFs.
4640 For now, we just handle the obvious case. */
4641 if (GET_CODE (operands[1]) != LABEL_REF)
4642 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4645 /* Darwin uses a special PIC legitimizer. */
4646 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4649 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4651 if (operands[0] != operands[1])
4652 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4657 /* If we are to limit the number of things we put in the TOC and
4658 this is a symbol plus a constant we can add in one insn,
4659 just put the symbol in the TOC and add the constant. Don't do
4660 this if reload is in progress. */
4661 if (GET_CODE (operands[1]) == CONST
4662 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4663 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4664 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4665 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4666 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4667 && ! side_effects_p (operands[0]))
4670 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4671 rtx other = XEXP (XEXP (operands[1], 0), 1);
4673 sym = force_reg (mode, sym);
4675 emit_insn (gen_addsi3 (operands[0], sym, other));
4677 emit_insn (gen_adddi3 (operands[0], sym, other));
4681 operands[1] = force_const_mem (mode, operands[1]);
4684 && constant_pool_expr_p (XEXP (operands[1], 0))
4685 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4686 get_pool_constant (XEXP (operands[1], 0)),
4687 get_pool_mode (XEXP (operands[1], 0))))
4690 = gen_const_mem (mode,
4691 create_TOC_reference (XEXP (operands[1], 0)));
4692 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4698 rs6000_eliminate_indexed_memrefs (operands);
4702 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4704 gen_rtx_SET (VOIDmode,
4705 operands[0], operands[1]),
4706 gen_rtx_CLOBBER (VOIDmode,
4707 gen_rtx_SCRATCH (SImode)))));
4716 /* Above, we may have called force_const_mem which may have returned
4717 an invalid address. If we can, fix this up; otherwise, reload will
4718 have to deal with it. */
4719 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4720 operands[1] = validize_mem (operands[1]);
4723 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4726 /* Nonzero if we can use a floating-point register to pass this arg. */
4727 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4728 (SCALAR_FLOAT_MODE_P (MODE) \
4729 && (MODE) != SDmode \
4730 && (CUM)->fregno <= FP_ARG_MAX_REG \
4731 && TARGET_HARD_FLOAT && TARGET_FPRS)
4733 /* Nonzero if we can use an AltiVec register to pass this arg. */
4734 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4735 (ALTIVEC_VECTOR_MODE (MODE) \
4736 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4737 && TARGET_ALTIVEC_ABI \
4740 /* Return a nonzero value to say to return the function value in
4741 memory, just as large structures are always returned. TYPE will be
4742 the data type of the value, and FNTYPE will be the type of the
4743 function doing the returning, or @code{NULL} for libcalls.
4745 The AIX ABI for the RS/6000 specifies that all structures are
4746 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4747 specifies that structures <= 8 bytes are returned in r3/r4, but a
4748 draft put them in memory, and GCC used to implement the draft
4749 instead of the final standard. Therefore, aix_struct_return
4750 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4751 compatibility can change DRAFT_V4_STRUCT_RET to override the
4752 default, and -m switches get the final word. See
4753 rs6000_override_options for more details.
4755 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4756 long double support is enabled. These values are returned in memory.
4758 int_size_in_bytes returns -1 for variable size objects, which go in
4759 memory always. The cast to unsigned makes -1 > 8. */
4762 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4764 /* In the darwin64 abi, try to use registers for larger structs
4766 if (rs6000_darwin64_abi
4767 && TREE_CODE (type) == RECORD_TYPE
4768 && int_size_in_bytes (type) > 0)
4770 CUMULATIVE_ARGS valcum;
4774 valcum.fregno = FP_ARG_MIN_REG;
4775 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4776 /* Do a trial code generation as if this were going to be passed
4777 as an argument; if any part goes in memory, we return NULL. */
4778 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4781 /* Otherwise fall through to more conventional ABI rules. */
4784 if (AGGREGATE_TYPE_P (type)
4785 && (aix_struct_return
4786 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4789 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4790 modes only exist for GCC vector types if -maltivec. */
4791 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4792 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4795 /* Return synthetic vectors in memory. */
4796 if (TREE_CODE (type) == VECTOR_TYPE
4797 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4799 static bool warned_for_return_big_vectors = false;
4800 if (!warned_for_return_big_vectors)
4802 warning (0, "GCC vector returned by reference: "
4803 "non-standard ABI extension with no compatibility guarantee");
4804 warned_for_return_big_vectors = true;
4809 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4815 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4816 for a call to a function whose data type is FNTYPE.
4817 For a library call, FNTYPE is 0.
4819 For incoming args we set the number of arguments in the prototype large
4820 so we never return a PARALLEL. */
4823 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4824 rtx libname ATTRIBUTE_UNUSED, int incoming,
4825 int libcall, int n_named_args)
4827 static CUMULATIVE_ARGS zero_cumulative;
4829 *cum = zero_cumulative;
4831 cum->fregno = FP_ARG_MIN_REG;
4832 cum->vregno = ALTIVEC_ARG_MIN_REG;
4833 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4834 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4835 ? CALL_LIBCALL : CALL_NORMAL);
4836 cum->sysv_gregno = GP_ARG_MIN_REG;
4837 cum->stdarg = fntype
4838 && (TYPE_ARG_TYPES (fntype) != 0
4839 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4840 != void_type_node));
4842 cum->nargs_prototype = 0;
4843 if (incoming || cum->prototype)
4844 cum->nargs_prototype = n_named_args;
4846 /* Check for a longcall attribute. */
4847 if ((!fntype && rs6000_default_long_calls)
4849 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4850 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4851 cum->call_cookie |= CALL_LONG;
4853 if (TARGET_DEBUG_ARG)
4855 fprintf (stderr, "\ninit_cumulative_args:");
4858 tree ret_type = TREE_TYPE (fntype);
4859 fprintf (stderr, " ret code = %s,",
4860 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4863 if (cum->call_cookie & CALL_LONG)
4864 fprintf (stderr, " longcall,");
4866 fprintf (stderr, " proto = %d, nargs = %d\n",
4867 cum->prototype, cum->nargs_prototype);
4872 && TARGET_ALTIVEC_ABI
4873 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4875 error ("cannot return value in vector register because"
4876 " altivec instructions are disabled, use -maltivec"
4881 /* Return true if TYPE must be passed on the stack and not in registers. */
4884 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4886 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4887 return must_pass_in_stack_var_size (mode, type);
4889 return must_pass_in_stack_var_size_or_pad (mode, type);
4892 /* If defined, a C expression which determines whether, and in which
4893 direction, to pad out an argument with extra space. The value
4894 should be of type `enum direction': either `upward' to pad above
4895 the argument, `downward' to pad below, or `none' to inhibit
4898 For the AIX ABI structs are always stored left shifted in their
4902 function_arg_padding (enum machine_mode mode, tree type)
4904 #ifndef AGGREGATE_PADDING_FIXED
4905 #define AGGREGATE_PADDING_FIXED 0
4907 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4908 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4911 if (!AGGREGATE_PADDING_FIXED)
4913 /* GCC used to pass structures of the same size as integer types as
4914 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4915 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4916 passed padded downward, except that -mstrict-align further
4917 muddied the water in that multi-component structures of 2 and 4
4918 bytes in size were passed padded upward.
4920 The following arranges for best compatibility with previous
4921 versions of gcc, but removes the -mstrict-align dependency. */
4922 if (BYTES_BIG_ENDIAN)
4924 HOST_WIDE_INT size = 0;
4926 if (mode == BLKmode)
4928 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4929 size = int_size_in_bytes (type);
4932 size = GET_MODE_SIZE (mode);
4934 if (size == 1 || size == 2 || size == 4)
4940 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4942 if (type != 0 && AGGREGATE_TYPE_P (type))
4946 /* Fall back to the default. */
4947 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4950 /* If defined, a C expression that gives the alignment boundary, in bits,
4951 of an argument with the specified mode and type. If it is not defined,
4952 PARM_BOUNDARY is used for all arguments.
4954 V.4 wants long longs and doubles to be double word aligned. Just
4955 testing the mode size is a boneheaded way to do this as it means
4956 that other types such as complex int are also double word aligned.
4957 However, we're stuck with this because changing the ABI might break
4958 existing library interfaces.
4960 Doubleword align SPE vectors.
4961 Quadword align Altivec vectors.
4962 Quadword align large synthetic vector types. */
4965 function_arg_boundary (enum machine_mode mode, tree type)
4967 if (DEFAULT_ABI == ABI_V4
4968 && (GET_MODE_SIZE (mode) == 8
4969 || (TARGET_HARD_FLOAT
4971 && (mode == TFmode || mode == TDmode))))
4973 else if (SPE_VECTOR_MODE (mode)
4974 || (type && TREE_CODE (type) == VECTOR_TYPE
4975 && int_size_in_bytes (type) >= 8
4976 && int_size_in_bytes (type) < 16))
4978 else if (ALTIVEC_VECTOR_MODE (mode)
4979 || (type && TREE_CODE (type) == VECTOR_TYPE
4980 && int_size_in_bytes (type) >= 16))
4982 else if (rs6000_darwin64_abi && mode == BLKmode
4983 && type && TYPE_ALIGN (type) > 64)
4986 return PARM_BOUNDARY;
4989 /* For a function parm of MODE and TYPE, return the starting word in
4990 the parameter area. NWORDS of the parameter area are already used. */
4993 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4996 unsigned int parm_offset;
4998 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4999 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5000 return nwords + (-(parm_offset + nwords) & align);
5003 /* Compute the size (in words) of a function argument. */
5005 static unsigned long
5006 rs6000_arg_size (enum machine_mode mode, tree type)
5010 if (mode != BLKmode)
5011 size = GET_MODE_SIZE (mode);
5013 size = int_size_in_bytes (type);
5016 return (size + 3) >> 2;
5018 return (size + 7) >> 3;
5021 /* Use this to flush pending int fields. */
5024 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5025 HOST_WIDE_INT bitpos)
5027 unsigned int startbit, endbit;
5028 int intregs, intoffset;
5029 enum machine_mode mode;
5031 if (cum->intoffset == -1)
5034 intoffset = cum->intoffset;
5035 cum->intoffset = -1;
5037 if (intoffset % BITS_PER_WORD != 0)
5039 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5041 if (mode == BLKmode)
5043 /* We couldn't find an appropriate mode, which happens,
5044 e.g., in packed structs when there are 3 bytes to load.
5045 Back intoffset back to the beginning of the word in this
5047 intoffset = intoffset & -BITS_PER_WORD;
5051 startbit = intoffset & -BITS_PER_WORD;
5052 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5053 intregs = (endbit - startbit) / BITS_PER_WORD;
5054 cum->words += intregs;
5057 /* The darwin64 ABI calls for us to recurse down through structs,
5058 looking for elements passed in registers. Unfortunately, we have
5059 to track int register count here also because of misalignments
5060 in powerpc alignment mode. */
5063 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5065 HOST_WIDE_INT startbitpos)
5069 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5070 if (TREE_CODE (f) == FIELD_DECL)
5072 HOST_WIDE_INT bitpos = startbitpos;
5073 tree ftype = TREE_TYPE (f);
5074 enum machine_mode mode;
5075 if (ftype == error_mark_node)
5077 mode = TYPE_MODE (ftype);
5079 if (DECL_SIZE (f) != 0
5080 && host_integerp (bit_position (f), 1))
5081 bitpos += int_bit_position (f);
5083 /* ??? FIXME: else assume zero offset. */
5085 if (TREE_CODE (ftype) == RECORD_TYPE)
5086 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5087 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5089 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5090 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5091 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5093 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5095 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5099 else if (cum->intoffset == -1)
5100 cum->intoffset = bitpos;
5104 /* Update the data in CUM to advance over an argument
5105 of mode MODE and data type TYPE.
5106 (TYPE is null for libcalls where that information may not be available.)
5108 Note that for args passed by reference, function_arg will be called
5109 with MODE and TYPE set to that of the pointer to the arg, not the arg
5113 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5114 tree type, int named, int depth)
5118 /* Only tick off an argument if we're not recursing. */
5120 cum->nargs_prototype--;
5122 if (TARGET_ALTIVEC_ABI
5123 && (ALTIVEC_VECTOR_MODE (mode)
5124 || (type && TREE_CODE (type) == VECTOR_TYPE
5125 && int_size_in_bytes (type) == 16)))
5129 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5132 if (!TARGET_ALTIVEC)
5133 error ("cannot pass argument in vector register because"
5134 " altivec instructions are disabled, use -maltivec"
5137 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5138 even if it is going to be passed in a vector register.
5139 Darwin does the same for variable-argument functions. */
5140 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5141 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5151 /* Vector parameters must be 16-byte aligned. This places
5152 them at 2 mod 4 in terms of words in 32-bit mode, since
5153 the parameter save area starts at offset 24 from the
5154 stack. In 64-bit mode, they just have to start on an
5155 even word, since the parameter save area is 16-byte
5156 aligned. Space for GPRs is reserved even if the argument
5157 will be passed in memory. */
5159 align = (2 - cum->words) & 3;
5161 align = cum->words & 1;
5162 cum->words += align + rs6000_arg_size (mode, type);
5164 if (TARGET_DEBUG_ARG)
5166 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5168 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5169 cum->nargs_prototype, cum->prototype,
5170 GET_MODE_NAME (mode));
5174 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5176 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5179 else if (rs6000_darwin64_abi
5181 && TREE_CODE (type) == RECORD_TYPE
5182 && (size = int_size_in_bytes (type)) > 0)
5184 /* Variable sized types have size == -1 and are
5185 treated as if consisting entirely of ints.
5186 Pad to 16 byte boundary if needed. */
5187 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5188 && (cum->words % 2) != 0)
5190 /* For varargs, we can just go up by the size of the struct. */
5192 cum->words += (size + 7) / 8;
5195 /* It is tempting to say int register count just goes up by
5196 sizeof(type)/8, but this is wrong in a case such as
5197 { int; double; int; } [powerpc alignment]. We have to
5198 grovel through the fields for these too. */
5200 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5201 rs6000_darwin64_record_arg_advance_flush (cum,
5202 size * BITS_PER_UNIT);
5205 else if (DEFAULT_ABI == ABI_V4)
5207 if (TARGET_HARD_FLOAT && TARGET_FPRS
5208 && (mode == SFmode || mode == DFmode
5209 || mode == DDmode || mode == TDmode
5210 || (mode == TFmode && !TARGET_IEEEQUAD)))
5212 /* _Decimal128 must use an even/odd register pair. This assumes
5213 that the register number is odd when fregno is odd. */
5214 if (mode == TDmode && (cum->fregno % 2) == 1)
5217 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5218 <= FP_ARG_V4_MAX_REG)
5219 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5222 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5223 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5224 cum->words += cum->words & 1;
5225 cum->words += rs6000_arg_size (mode, type);
5230 int n_words = rs6000_arg_size (mode, type);
5231 int gregno = cum->sysv_gregno;
5233 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5234 (r7,r8) or (r9,r10). As does any other 2 word item such
5235 as complex int due to a historical mistake. */
5237 gregno += (1 - gregno) & 1;
5239 /* Multi-reg args are not split between registers and stack. */
5240 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5242 /* Long long and SPE vectors are aligned on the stack.
5243 So are other 2 word items such as complex int due to
5244 a historical mistake. */
5246 cum->words += cum->words & 1;
5247 cum->words += n_words;
5250 /* Note: continuing to accumulate gregno past when we've started
5251 spilling to the stack indicates the fact that we've started
5252 spilling to the stack to expand_builtin_saveregs. */
5253 cum->sysv_gregno = gregno + n_words;
5256 if (TARGET_DEBUG_ARG)
5258 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5259 cum->words, cum->fregno);
5260 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5261 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5262 fprintf (stderr, "mode = %4s, named = %d\n",
5263 GET_MODE_NAME (mode), named);
5268 int n_words = rs6000_arg_size (mode, type);
5269 int start_words = cum->words;
5270 int align_words = rs6000_parm_start (mode, type, start_words);
5272 cum->words = align_words + n_words;
5274 if (SCALAR_FLOAT_MODE_P (mode)
5276 && TARGET_HARD_FLOAT && TARGET_FPRS)
5278 /* _Decimal128 must be passed in an even/odd float register pair.
5279 This assumes that the register number is odd when fregno is
5281 if (mode == TDmode && (cum->fregno % 2) == 1)
5283 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5286 if (TARGET_DEBUG_ARG)
5288 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5289 cum->words, cum->fregno);
5290 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5291 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5292 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5293 named, align_words - start_words, depth);
5299 spe_build_register_parallel (enum machine_mode mode, int gregno)
5306 r1 = gen_rtx_REG (DImode, gregno);
5307 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5308 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5312 r1 = gen_rtx_REG (DImode, gregno);
5313 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5314 r3 = gen_rtx_REG (DImode, gregno + 2);
5315 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5316 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5319 r1 = gen_rtx_REG (DImode, gregno);
5320 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5321 r3 = gen_rtx_REG (DImode, gregno + 2);
5322 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5323 r5 = gen_rtx_REG (DImode, gregno + 4);
5324 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5325 r7 = gen_rtx_REG (DImode, gregno + 6);
5326 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5327 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5334 /* Determine where to put a SIMD argument on the SPE. */
5336 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5339 int gregno = cum->sysv_gregno;
5341 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5342 are passed and returned in a pair of GPRs for ABI compatibility. */
5343 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5344 || mode == TFmode || mode == TCmode))
5346 int n_words = rs6000_arg_size (mode, type);
5348 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5350 gregno += (1 - gregno) & 1;
5352 /* Multi-reg args are not split between registers and stack. */
5353 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5356 return spe_build_register_parallel (mode, gregno);
5360 int n_words = rs6000_arg_size (mode, type);
5362 /* SPE vectors are put in odd registers. */
5363 if (n_words == 2 && (gregno & 1) == 0)
5366 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5369 enum machine_mode m = SImode;
5371 r1 = gen_rtx_REG (m, gregno);
5372 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5373 r2 = gen_rtx_REG (m, gregno + 1);
5374 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5375 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5382 if (gregno <= GP_ARG_MAX_REG)
5383 return gen_rtx_REG (mode, gregno);
5389 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5390 structure between cum->intoffset and bitpos to integer registers. */
5393 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5394 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5396 enum machine_mode mode;
5398 unsigned int startbit, endbit;
5399 int this_regno, intregs, intoffset;
5402 if (cum->intoffset == -1)
5405 intoffset = cum->intoffset;
5406 cum->intoffset = -1;
5408 /* If this is the trailing part of a word, try to only load that
5409 much into the register. Otherwise load the whole register. Note
5410 that in the latter case we may pick up unwanted bits. It's not a
5411 problem at the moment but may wish to revisit. */
5413 if (intoffset % BITS_PER_WORD != 0)
5415 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5417 if (mode == BLKmode)
5419 /* We couldn't find an appropriate mode, which happens,
5420 e.g., in packed structs when there are 3 bytes to load.
5421 Back intoffset back to the beginning of the word in this
5423 intoffset = intoffset & -BITS_PER_WORD;
5430 startbit = intoffset & -BITS_PER_WORD;
5431 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5432 intregs = (endbit - startbit) / BITS_PER_WORD;
5433 this_regno = cum->words + intoffset / BITS_PER_WORD;
5435 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5438 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5442 intoffset /= BITS_PER_UNIT;
5445 regno = GP_ARG_MIN_REG + this_regno;
5446 reg = gen_rtx_REG (mode, regno);
5448 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5451 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5455 while (intregs > 0);
5458 /* Recursive workhorse for the following. */
5461 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5462 HOST_WIDE_INT startbitpos, rtx rvec[],
5467 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5468 if (TREE_CODE (f) == FIELD_DECL)
5470 HOST_WIDE_INT bitpos = startbitpos;
5471 tree ftype = TREE_TYPE (f);
5472 enum machine_mode mode;
5473 if (ftype == error_mark_node)
5475 mode = TYPE_MODE (ftype);
5477 if (DECL_SIZE (f) != 0
5478 && host_integerp (bit_position (f), 1))
5479 bitpos += int_bit_position (f);
5481 /* ??? FIXME: else assume zero offset. */
5483 if (TREE_CODE (ftype) == RECORD_TYPE)
5484 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5485 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5490 case SCmode: mode = SFmode; break;
5491 case DCmode: mode = DFmode; break;
5492 case TCmode: mode = TFmode; break;
5496 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5498 = gen_rtx_EXPR_LIST (VOIDmode,
5499 gen_rtx_REG (mode, cum->fregno++),
5500 GEN_INT (bitpos / BITS_PER_UNIT));
5501 if (mode == TFmode || mode == TDmode)
5504 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5506 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5508 = gen_rtx_EXPR_LIST (VOIDmode,
5509 gen_rtx_REG (mode, cum->vregno++),
5510 GEN_INT (bitpos / BITS_PER_UNIT));
5512 else if (cum->intoffset == -1)
5513 cum->intoffset = bitpos;
5517 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5518 the register(s) to be used for each field and subfield of a struct
5519 being passed by value, along with the offset of where the
5520 register's value may be found in the block. FP fields go in FP
5521 register, vector fields go in vector registers, and everything
5522 else goes in int registers, packed as in memory.
5524 This code is also used for function return values. RETVAL indicates
5525 whether this is the case.
5527 Much of this is taken from the SPARC V9 port, which has a similar
5528 calling convention. */
5531 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5532 int named, bool retval)
5534 rtx rvec[FIRST_PSEUDO_REGISTER];
5535 int k = 1, kbase = 1;
5536 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5537 /* This is a copy; modifications are not visible to our caller. */
5538 CUMULATIVE_ARGS copy_cum = *orig_cum;
5539 CUMULATIVE_ARGS *cum = ©_cum;
5541 /* Pad to 16 byte boundary if needed. */
5542 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5543 && (cum->words % 2) != 0)
5550 /* Put entries into rvec[] for individual FP and vector fields, and
5551 for the chunks of memory that go in int regs. Note we start at
5552 element 1; 0 is reserved for an indication of using memory, and
5553 may or may not be filled in below. */
5554 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5555 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5557 /* If any part of the struct went on the stack put all of it there.
5558 This hack is because the generic code for
5559 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5560 parts of the struct are not at the beginning. */
5564 return NULL_RTX; /* doesn't go in registers at all */
5566 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5568 if (k > 1 || cum->use_stack)
5569 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5574 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5577 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5581 rtx rvec[GP_ARG_NUM_REG + 1];
5583 if (align_words >= GP_ARG_NUM_REG)
5586 n_units = rs6000_arg_size (mode, type);
5588 /* Optimize the simple case where the arg fits in one gpr, except in
5589 the case of BLKmode due to assign_parms assuming that registers are
5590 BITS_PER_WORD wide. */
5592 || (n_units == 1 && mode != BLKmode))
5593 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5596 if (align_words + n_units > GP_ARG_NUM_REG)
5597 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5598 using a magic NULL_RTX component.
5599 This is not strictly correct. Only some of the arg belongs in
5600 memory, not all of it. However, the normal scheme using
5601 function_arg_partial_nregs can result in unusual subregs, eg.
5602 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5603 store the whole arg to memory is often more efficient than code
5604 to store pieces, and we know that space is available in the right
5605 place for the whole arg. */
5606 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5611 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5612 rtx off = GEN_INT (i++ * 4);
5613 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5615 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5617 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5620 /* Determine where to put an argument to a function.
5621 Value is zero to push the argument on the stack,
5622 or a hard register in which to store the argument.
5624 MODE is the argument's machine mode.
5625 TYPE is the data type of the argument (as a tree).
5626 This is null for libcalls where that information may
5628 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5629 the preceding args and about the function being called. It is
5630 not modified in this routine.
5631 NAMED is nonzero if this argument is a named parameter
5632 (otherwise it is an extra parameter matching an ellipsis).
5634 On RS/6000 the first eight words of non-FP are normally in registers
5635 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5636 Under V.4, the first 8 FP args are in registers.
5638 If this is floating-point and no prototype is specified, we use
5639 both an FP and integer register (or possibly FP reg and stack). Library
5640 functions (when CALL_LIBCALL is set) always have the proper types for args,
5641 so we can pass the FP value just in one register. emit_library_function
5642 doesn't support PARALLEL anyway.
5644 Note that for args passed by reference, function_arg will be called
5645 with MODE and TYPE set to that of the pointer to the arg, not the arg
5649 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5650 tree type, int named)
5652 enum rs6000_abi abi = DEFAULT_ABI;
5654 /* Return a marker to indicate whether CR1 needs to set or clear the
5655 bit that V.4 uses to say fp args were passed in registers.
5656 Assume that we don't need the marker for software floating point,
5657 or compiler generated library calls. */
5658 if (mode == VOIDmode)
5661 && (cum->call_cookie & CALL_LIBCALL) == 0
5663 || (cum->nargs_prototype < 0
5664 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5666 /* For the SPE, we need to crxor CR6 always. */
5668 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5669 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5670 return GEN_INT (cum->call_cookie
5671 | ((cum->fregno == FP_ARG_MIN_REG)
5672 ? CALL_V4_SET_FP_ARGS
5673 : CALL_V4_CLEAR_FP_ARGS));
5676 return GEN_INT (cum->call_cookie);
5679 if (rs6000_darwin64_abi && mode == BLKmode
5680 && TREE_CODE (type) == RECORD_TYPE)
5682 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5683 if (rslt != NULL_RTX)
5685 /* Else fall through to usual handling. */
5688 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5689 if (TARGET_64BIT && ! cum->prototype)
5691 /* Vector parameters get passed in vector register
5692 and also in GPRs or memory, in absence of prototype. */
5695 align_words = (cum->words + 1) & ~1;
5697 if (align_words >= GP_ARG_NUM_REG)
5703 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5705 return gen_rtx_PARALLEL (mode,
5707 gen_rtx_EXPR_LIST (VOIDmode,
5709 gen_rtx_EXPR_LIST (VOIDmode,
5710 gen_rtx_REG (mode, cum->vregno),
5714 return gen_rtx_REG (mode, cum->vregno);
5715 else if (TARGET_ALTIVEC_ABI
5716 && (ALTIVEC_VECTOR_MODE (mode)
5717 || (type && TREE_CODE (type) == VECTOR_TYPE
5718 && int_size_in_bytes (type) == 16)))
5720 if (named || abi == ABI_V4)
5724 /* Vector parameters to varargs functions under AIX or Darwin
5725 get passed in memory and possibly also in GPRs. */
5726 int align, align_words, n_words;
5727 enum machine_mode part_mode;
5729 /* Vector parameters must be 16-byte aligned. This places them at
5730 2 mod 4 in terms of words in 32-bit mode, since the parameter
5731 save area starts at offset 24 from the stack. In 64-bit mode,
5732 they just have to start on an even word, since the parameter
5733 save area is 16-byte aligned. */
5735 align = (2 - cum->words) & 3;
5737 align = cum->words & 1;
5738 align_words = cum->words + align;
5740 /* Out of registers? Memory, then. */
5741 if (align_words >= GP_ARG_NUM_REG)
5744 if (TARGET_32BIT && TARGET_POWERPC64)
5745 return rs6000_mixed_function_arg (mode, type, align_words);
5747 /* The vector value goes in GPRs. Only the part of the
5748 value in GPRs is reported here. */
5750 n_words = rs6000_arg_size (mode, type);
5751 if (align_words + n_words > GP_ARG_NUM_REG)
5752 /* Fortunately, there are only two possibilities, the value
5753 is either wholly in GPRs or half in GPRs and half not. */
5756 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5759 else if (TARGET_SPE_ABI && TARGET_SPE
5760 && (SPE_VECTOR_MODE (mode)
5761 || (TARGET_E500_DOUBLE && (mode == DFmode
5766 || mode == TCmode))))
5767 return rs6000_spe_function_arg (cum, mode, type);
5769 else if (abi == ABI_V4)
5771 if (TARGET_HARD_FLOAT && TARGET_FPRS
5772 && (mode == SFmode || mode == DFmode
5773 || (mode == TFmode && !TARGET_IEEEQUAD)
5774 || mode == DDmode || mode == TDmode))
5776 /* _Decimal128 must use an even/odd register pair. This assumes
5777 that the register number is odd when fregno is odd. */
5778 if (mode == TDmode && (cum->fregno % 2) == 1)
5781 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5782 <= FP_ARG_V4_MAX_REG)
5783 return gen_rtx_REG (mode, cum->fregno);
5789 int n_words = rs6000_arg_size (mode, type);
5790 int gregno = cum->sysv_gregno;
5792 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5793 (r7,r8) or (r9,r10). As does any other 2 word item such
5794 as complex int due to a historical mistake. */
5796 gregno += (1 - gregno) & 1;
5798 /* Multi-reg args are not split between registers and stack. */
5799 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5802 if (TARGET_32BIT && TARGET_POWERPC64)
5803 return rs6000_mixed_function_arg (mode, type,
5804 gregno - GP_ARG_MIN_REG);
5805 return gen_rtx_REG (mode, gregno);
5810 int align_words = rs6000_parm_start (mode, type, cum->words);
5812 /* _Decimal128 must be passed in an even/odd float register pair.
5813 This assumes that the register number is odd when fregno is odd. */
5814 if (mode == TDmode && (cum->fregno % 2) == 1)
5817 if (USE_FP_FOR_ARG_P (cum, mode, type))
5819 rtx rvec[GP_ARG_NUM_REG + 1];
5823 enum machine_mode fmode = mode;
5824 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5826 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5828 /* Currently, we only ever need one reg here because complex
5829 doubles are split. */
5830 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5831 && (fmode == TFmode || fmode == TDmode));
5833 /* Long double or _Decimal128 split over regs and memory. */
5834 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5837 /* Do we also need to pass this arg in the parameter save
5840 && (cum->nargs_prototype <= 0
5841 || (DEFAULT_ABI == ABI_AIX
5843 && align_words >= GP_ARG_NUM_REG)));
5845 if (!needs_psave && mode == fmode)
5846 return gen_rtx_REG (fmode, cum->fregno);
5851 /* Describe the part that goes in gprs or the stack.
5852 This piece must come first, before the fprs. */
5853 if (align_words < GP_ARG_NUM_REG)
5855 unsigned long n_words = rs6000_arg_size (mode, type);
5857 if (align_words + n_words > GP_ARG_NUM_REG
5858 || (TARGET_32BIT && TARGET_POWERPC64))
5860 /* If this is partially on the stack, then we only
5861 include the portion actually in registers here. */
5862 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5865 if (align_words + n_words > GP_ARG_NUM_REG)
5866 /* Not all of the arg fits in gprs. Say that it
5867 goes in memory too, using a magic NULL_RTX
5868 component. Also see comment in
5869 rs6000_mixed_function_arg for why the normal
5870 function_arg_partial_nregs scheme doesn't work
5872 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5876 r = gen_rtx_REG (rmode,
5877 GP_ARG_MIN_REG + align_words);
5878 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5879 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5881 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5885 /* The whole arg fits in gprs. */
5886 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5887 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5891 /* It's entirely in memory. */
5892 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5895 /* Describe where this piece goes in the fprs. */
5896 r = gen_rtx_REG (fmode, cum->fregno);
5897 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5899 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5901 else if (align_words < GP_ARG_NUM_REG)
5903 if (TARGET_32BIT && TARGET_POWERPC64)
5904 return rs6000_mixed_function_arg (mode, type, align_words);
5906 if (mode == BLKmode)
5909 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5916 /* For an arg passed partly in registers and partly in memory, this is
5917 the number of bytes passed in registers. For args passed entirely in
5918 registers or entirely in memory, zero. When an arg is described by a
5919 PARALLEL, perhaps using more than one register type, this function
5920 returns the number of bytes used by the first element of the PARALLEL. */
5923 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5924 tree type, bool named)
5929 if (DEFAULT_ABI == ABI_V4)
5932 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5933 && cum->nargs_prototype >= 0)
5936 /* In this complicated case we just disable the partial_nregs code. */
5937 if (rs6000_darwin64_abi && mode == BLKmode
5938 && TREE_CODE (type) == RECORD_TYPE
5939 && int_size_in_bytes (type) > 0)
5942 align_words = rs6000_parm_start (mode, type, cum->words);
5944 if (USE_FP_FOR_ARG_P (cum, mode, type))
5946 /* If we are passing this arg in the fixed parameter save area
5947 (gprs or memory) as well as fprs, then this function should
5948 return the number of partial bytes passed in the parameter
5949 save area rather than partial bytes passed in fprs. */
5951 && (cum->nargs_prototype <= 0
5952 || (DEFAULT_ABI == ABI_AIX
5954 && align_words >= GP_ARG_NUM_REG)))
5956 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5957 > FP_ARG_MAX_REG + 1)
5958 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5959 else if (cum->nargs_prototype >= 0)
5963 if (align_words < GP_ARG_NUM_REG
5964 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5965 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5967 if (ret != 0 && TARGET_DEBUG_ARG)
5968 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5973 /* A C expression that indicates when an argument must be passed by
5974 reference. If nonzero for an argument, a copy of that argument is
5975 made in memory and a pointer to the argument is passed instead of
5976 the argument itself. The pointer is passed in whatever way is
5977 appropriate for passing a pointer to that type.
5979 Under V.4, aggregates and long double are passed by reference.
5981 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5982 reference unless the AltiVec vector extension ABI is in force.
5984 As an extension to all ABIs, variable sized types are passed by
5988 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5989 enum machine_mode mode, tree type,
5990 bool named ATTRIBUTE_UNUSED)
5992 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5994 if (TARGET_DEBUG_ARG)
5995 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6002 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6004 if (TARGET_DEBUG_ARG)
6005 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6009 if (int_size_in_bytes (type) < 0)
6011 if (TARGET_DEBUG_ARG)
6012 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6016 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6017 modes only exist for GCC vector types if -maltivec. */
6018 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6020 if (TARGET_DEBUG_ARG)
6021 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6025 /* Pass synthetic vectors in memory. */
6026 if (TREE_CODE (type) == VECTOR_TYPE
6027 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6029 static bool warned_for_pass_big_vectors = false;
6030 if (TARGET_DEBUG_ARG)
6031 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6032 if (!warned_for_pass_big_vectors)
6034 warning (0, "GCC vector passed by reference: "
6035 "non-standard ABI extension with no compatibility guarantee");
6036 warned_for_pass_big_vectors = true;
6045 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6048 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6053 for (i = 0; i < nregs; i++)
6055 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6056 if (reload_completed)
6058 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6061 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6062 i * GET_MODE_SIZE (reg_mode));
6065 tem = replace_equiv_address (tem, XEXP (tem, 0));
6069 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6073 /* Perform any needed actions needed for a function that is receiving a
6074 variable number of arguments.
6078 MODE and TYPE are the mode and type of the current parameter.
6080 PRETEND_SIZE is a variable that should be set to the amount of stack
6081 that must be pushed by the prolog to pretend that our caller pushed
6084 Normally, this macro will push all remaining incoming registers on the
6085 stack and set PRETEND_SIZE to the length of the registers pushed. */
6088 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6089 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6092 CUMULATIVE_ARGS next_cum;
6093 int reg_size = TARGET_32BIT ? 4 : 8;
6094 rtx save_area = NULL_RTX, mem;
6095 int first_reg_offset;
6098 /* Skip the last named argument. */
6100 function_arg_advance (&next_cum, mode, type, 1, 0);
6102 if (DEFAULT_ABI == ABI_V4)
6104 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6108 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6109 HOST_WIDE_INT offset = 0;
6111 /* Try to optimize the size of the varargs save area.
6112 The ABI requires that ap.reg_save_area is doubleword
6113 aligned, but we don't need to allocate space for all
6114 the bytes, only those to which we actually will save
6116 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6117 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6118 if (TARGET_HARD_FLOAT && TARGET_FPRS
6119 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6120 && cfun->va_list_fpr_size)
6123 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6124 * UNITS_PER_FP_WORD;
6125 if (cfun->va_list_fpr_size
6126 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6127 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6129 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6130 * UNITS_PER_FP_WORD;
6134 offset = -((first_reg_offset * reg_size) & ~7);
6135 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6137 gpr_reg_num = cfun->va_list_gpr_size;
6138 if (reg_size == 4 && (first_reg_offset & 1))
6141 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6144 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6146 - (int) (GP_ARG_NUM_REG * reg_size);
6148 if (gpr_size + fpr_size)
6151 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6152 gcc_assert (GET_CODE (reg_save_area) == MEM);
6153 reg_save_area = XEXP (reg_save_area, 0);
6154 if (GET_CODE (reg_save_area) == PLUS)
6156 gcc_assert (XEXP (reg_save_area, 0)
6157 == virtual_stack_vars_rtx);
6158 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6159 offset += INTVAL (XEXP (reg_save_area, 1));
6162 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6165 cfun->machine->varargs_save_offset = offset;
6166 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6171 first_reg_offset = next_cum.words;
6172 save_area = virtual_incoming_args_rtx;
6174 if (targetm.calls.must_pass_in_stack (mode, type))
6175 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6178 set = get_varargs_alias_set ();
6179 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6180 && cfun->va_list_gpr_size)
6182 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6184 if (va_list_gpr_counter_field)
6186 /* V4 va_list_gpr_size counts number of registers needed. */
6187 if (nregs > cfun->va_list_gpr_size)
6188 nregs = cfun->va_list_gpr_size;
6192 /* char * va_list instead counts number of bytes needed. */
6193 if (nregs > cfun->va_list_gpr_size / reg_size)
6194 nregs = cfun->va_list_gpr_size / reg_size;
6197 mem = gen_rtx_MEM (BLKmode,
6198 plus_constant (save_area,
6199 first_reg_offset * reg_size));
6200 MEM_NOTRAP_P (mem) = 1;
6201 set_mem_alias_set (mem, set);
6202 set_mem_align (mem, BITS_PER_WORD);
6204 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6208 /* Save FP registers if needed. */
6209 if (DEFAULT_ABI == ABI_V4
6210 && TARGET_HARD_FLOAT && TARGET_FPRS
6212 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6213 && cfun->va_list_fpr_size)
6215 int fregno = next_cum.fregno, nregs;
6216 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6217 rtx lab = gen_label_rtx ();
6218 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6219 * UNITS_PER_FP_WORD);
6222 (gen_rtx_SET (VOIDmode,
6224 gen_rtx_IF_THEN_ELSE (VOIDmode,
6225 gen_rtx_NE (VOIDmode, cr1,
6227 gen_rtx_LABEL_REF (VOIDmode, lab),
6231 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6232 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6234 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6235 MEM_NOTRAP_P (mem) = 1;
6236 set_mem_alias_set (mem, set);
6237 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6238 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6245 /* Create the va_list data type. */
6248 rs6000_build_builtin_va_list (void)
6250 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6252 /* For AIX, prefer 'char *' because that's what the system
6253 header files like. */
6254 if (DEFAULT_ABI != ABI_V4)
6255 return build_pointer_type (char_type_node);
6257 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6258 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6260 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6261 unsigned_char_type_node);
6262 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6263 unsigned_char_type_node);
6264 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6266 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6267 short_unsigned_type_node);
6268 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6270 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6273 va_list_gpr_counter_field = f_gpr;
6274 va_list_fpr_counter_field = f_fpr;
6276 DECL_FIELD_CONTEXT (f_gpr) = record;
6277 DECL_FIELD_CONTEXT (f_fpr) = record;
6278 DECL_FIELD_CONTEXT (f_res) = record;
6279 DECL_FIELD_CONTEXT (f_ovf) = record;
6280 DECL_FIELD_CONTEXT (f_sav) = record;
6282 TREE_CHAIN (record) = type_decl;
6283 TYPE_NAME (record) = type_decl;
6284 TYPE_FIELDS (record) = f_gpr;
6285 TREE_CHAIN (f_gpr) = f_fpr;
6286 TREE_CHAIN (f_fpr) = f_res;
6287 TREE_CHAIN (f_res) = f_ovf;
6288 TREE_CHAIN (f_ovf) = f_sav;
6290 layout_type (record);
6292 /* The correct type is an array type of one element. */
6293 return build_array_type (record, build_index_type (size_zero_node));
6296 /* Implement va_start. */
6299 rs6000_va_start (tree valist, rtx nextarg)
6301 HOST_WIDE_INT words, n_gpr, n_fpr;
6302 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6303 tree gpr, fpr, ovf, sav, t;
6305 /* Only SVR4 needs something special. */
6306 if (DEFAULT_ABI != ABI_V4)
6308 std_expand_builtin_va_start (valist, nextarg);
6312 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6313 f_fpr = TREE_CHAIN (f_gpr);
6314 f_res = TREE_CHAIN (f_fpr);
6315 f_ovf = TREE_CHAIN (f_res);
6316 f_sav = TREE_CHAIN (f_ovf);
6318 valist = build_va_arg_indirect_ref (valist);
6319 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6320 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6321 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6322 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6324 /* Count number of gp and fp argument registers used. */
6325 words = current_function_args_info.words;
6326 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6328 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6331 if (TARGET_DEBUG_ARG)
6332 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6333 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6334 words, n_gpr, n_fpr);
6336 if (cfun->va_list_gpr_size)
6338 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6339 build_int_cst (NULL_TREE, n_gpr));
6340 TREE_SIDE_EFFECTS (t) = 1;
6341 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6344 if (cfun->va_list_fpr_size)
6346 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6347 build_int_cst (NULL_TREE, n_fpr));
6348 TREE_SIDE_EFFECTS (t) = 1;
6349 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6352 /* Find the overflow area. */
6353 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6355 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6356 size_int (words * UNITS_PER_WORD));
6357 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6358 TREE_SIDE_EFFECTS (t) = 1;
6359 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6361 /* If there were no va_arg invocations, don't set up the register
6363 if (!cfun->va_list_gpr_size
6364 && !cfun->va_list_fpr_size
6365 && n_gpr < GP_ARG_NUM_REG
6366 && n_fpr < FP_ARG_V4_MAX_REG)
6369 /* Find the register save area. */
6370 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6371 if (cfun->machine->varargs_save_offset)
6372 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6373 size_int (cfun->machine->varargs_save_offset));
6374 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6375 TREE_SIDE_EFFECTS (t) = 1;
6376 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6379 /* Implement va_arg. */
6382 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6384 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6385 tree gpr, fpr, ovf, sav, reg, t, u;
6386 int size, rsize, n_reg, sav_ofs, sav_scale;
6387 tree lab_false, lab_over, addr;
6389 tree ptrtype = build_pointer_type (type);
6392 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6394 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6395 return build_va_arg_indirect_ref (t);
6398 if (DEFAULT_ABI != ABI_V4)
6400 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6402 tree elem_type = TREE_TYPE (type);
6403 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6404 int elem_size = GET_MODE_SIZE (elem_mode);
6406 if (elem_size < UNITS_PER_WORD)
6408 tree real_part, imag_part;
6409 tree post = NULL_TREE;
6411 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6413 /* Copy the value into a temporary, lest the formal temporary
6414 be reused out from under us. */
6415 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6416 append_to_statement_list (post, pre_p);
6418 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6421 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6425 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6428 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6429 f_fpr = TREE_CHAIN (f_gpr);
6430 f_res = TREE_CHAIN (f_fpr);
6431 f_ovf = TREE_CHAIN (f_res);
6432 f_sav = TREE_CHAIN (f_ovf);
6434 valist = build_va_arg_indirect_ref (valist);
6435 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6436 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6437 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6438 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6440 size = int_size_in_bytes (type);
6441 rsize = (size + 3) / 4;
6444 if (TARGET_HARD_FLOAT && TARGET_FPRS
6445 && (TYPE_MODE (type) == SFmode
6446 || TYPE_MODE (type) == DFmode
6447 || TYPE_MODE (type) == TFmode
6448 || TYPE_MODE (type) == DDmode
6449 || TYPE_MODE (type) == TDmode))
6451 /* FP args go in FP registers, if present. */
6453 n_reg = (size + 7) / 8;
6456 if (TYPE_MODE (type) != SFmode)
6461 /* Otherwise into GP registers. */
6470 /* Pull the value out of the saved registers.... */
6473 addr = create_tmp_var (ptr_type_node, "addr");
6474 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6476 /* AltiVec vectors never go in registers when -mabi=altivec. */
6477 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6481 lab_false = create_artificial_label ();
6482 lab_over = create_artificial_label ();
6484 /* Long long and SPE vectors are aligned in the registers.
6485 As are any other 2 gpr item such as complex int due to a
6486 historical mistake. */
6488 if (n_reg == 2 && reg == gpr)
6491 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6492 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6493 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6495 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6496 reg number is 0 for f1, so we want to make it odd. */
6497 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6500 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6501 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6504 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6505 t = build2 (GE_EXPR, boolean_type_node, u, t);
6506 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6507 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6508 gimplify_and_add (t, pre_p);
6512 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6514 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
6515 build_int_cst (TREE_TYPE (reg), n_reg));
6516 u = fold_convert (sizetype, u);
6517 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6518 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6520 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6521 gimplify_and_add (t, pre_p);
6523 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6524 gimplify_and_add (t, pre_p);
6526 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6527 append_to_statement_list (t, pre_p);
6529 if ((n_reg == 2 && !regalign) || n_reg > 2)
6531 /* Ensure that we don't find any more args in regs.
6532 Alignment has taken care of for special cases. */
6533 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6534 gimplify_and_add (t, pre_p);
6538 /* ... otherwise out of the overflow area. */
6540 /* Care for on-stack alignment if needed. */
6544 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6545 t = fold_convert (sizetype, t);
6546 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6548 t = fold_convert (TREE_TYPE (ovf), t);
6550 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6552 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6553 gimplify_and_add (u, pre_p);
6555 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6556 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6557 gimplify_and_add (t, pre_p);
6561 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6562 append_to_statement_list (t, pre_p);
6565 if (STRICT_ALIGNMENT
6566 && (TYPE_ALIGN (type)
6567 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6569 /* The value (of type complex double, for example) may not be
6570 aligned in memory in the saved registers, so copy via a
6571 temporary. (This is the same code as used for SPARC.) */
6572 tree tmp = create_tmp_var (type, "va_arg_tmp");
6573 tree dest_addr = build_fold_addr_expr (tmp);
6575 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6576 3, dest_addr, addr, size_int (rsize * 4));
6578 gimplify_and_add (copy, pre_p);
6582 addr = fold_convert (ptrtype, addr);
6583 return build_va_arg_indirect_ref (addr);
6589 def_builtin (int mask, const char *name, tree type, int code)
6591 if (mask & target_flags)
6593 if (rs6000_builtin_decls[code])
6596 rs6000_builtin_decls[code] =
6597 add_builtin_function (name, type, code, BUILT_IN_MD,
6602 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6604 static const struct builtin_description bdesc_3arg[] =
6606 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6607 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6608 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6609 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6610 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6611 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6613 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6614 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6615 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6616 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6617 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6618 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6619 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6620 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6621 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6622 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6624 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6625 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6626 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6627 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6628 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6630 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6631 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6632 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6633 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6634 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6635 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6636 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6637 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6638 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6639 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6640 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6641 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6642 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6643 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6644 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6647 /* DST operations: void foo (void *, const int, const char). */
6649 static const struct builtin_description bdesc_dst[] =
6651 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6652 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6653 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6654 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6662 /* Simple binary operations: VECc = foo (VECa, VECb). */
6664 static struct builtin_description bdesc_2arg[] =
6666 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6667 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6668 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6669 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6670 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6671 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6672 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6673 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6674 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6675 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6676 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6677 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6678 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6679 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6680 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6681 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6682 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6683 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6684 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6685 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6686 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6687 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6688 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6689 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6690 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6691 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6692 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6693 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6694 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6695 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6696 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6697 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6698 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6699 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6700 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6701 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6702 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6703 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6704 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6705 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6706 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6707 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6708 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6709 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6710 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6711 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6712 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6713 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6714 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6715 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6716 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6717 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6718 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6719 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6720 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6721 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6722 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6723 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6724 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6725 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6726 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6727 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6728 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6729 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6730 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6731 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6732 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6733 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6734 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6735 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6736 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6737 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6738 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6739 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6740 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6741 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6742 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6743 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6744 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6745 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6746 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6747 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6748 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6749 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6750 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6751 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6752 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6753 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6754 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6755 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6756 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6757 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6758 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6759 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6760 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6761 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6762 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6763 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6764 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6765 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6766 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6767 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6768 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6769 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6770 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6771 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6772 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6773 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6774 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6775 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6776 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6778 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6779 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6780 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6781 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6782 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6783 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6784 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6785 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6786 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6787 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6788 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6789 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6790 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6791 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6792 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6793 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6794 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6856 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6857 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6858 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6859 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6860 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6861 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6862 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6863 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6864 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6865 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6866 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6884 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6885 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6886 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6887 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6888 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6889 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6890 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6891 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6892 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6893 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6894 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6899 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6900 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6901 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6902 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6903 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6904 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6906 /* Place holder, leave as first spe builtin. */
6907 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6908 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6909 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6910 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6911 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6912 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6913 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6914 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6915 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6916 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6917 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6918 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6919 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6920 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6921 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6922 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6923 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6924 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6925 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6926 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6927 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6928 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6929 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6930 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6931 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6932 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6933 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6934 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6935 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6936 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6937 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6938 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6939 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6940 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6941 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6942 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6943 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6944 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6945 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6946 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6947 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6948 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6949 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6950 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6951 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6952 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6953 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6954 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6955 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6956 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6957 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6958 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6959 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6960 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6961 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6962 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6963 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6964 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6965 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6966 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6967 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6968 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6969 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6970 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6971 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6972 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6973 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6974 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6975 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6976 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6977 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6978 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6979 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6980 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6981 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6982 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6983 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6984 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6985 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6986 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6987 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6988 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6989 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6990 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6991 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6992 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6993 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6994 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6995 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6996 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6997 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6998 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6999 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7000 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7001 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7002 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7003 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7004 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7005 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7006 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7007 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7008 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7009 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7010 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7011 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7012 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7013 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7014 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7015 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7017 /* SPE binary operations expecting a 5-bit unsigned literal. */
7018 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7020 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7021 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7022 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7023 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7024 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7025 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7026 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7027 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7028 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7029 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7030 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7031 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7032 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7033 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7034 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7035 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7036 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7037 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7038 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7039 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7040 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7041 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7042 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7043 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7044 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7045 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7047 /* Place-holder. Leave as last binary SPE builtin. */
7048 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7051 /* AltiVec predicates. */
7053 struct builtin_description_predicates
7055 const unsigned int mask;
7056 const enum insn_code icode;
7058 const char *const name;
7059 const enum rs6000_builtins code;
7062 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7064 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7065 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7066 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7067 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7068 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7069 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7070 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7071 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7072 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7073 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7074 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7075 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7076 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7078 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7079 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7080 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7083 /* SPE predicates. */
7084 static struct builtin_description bdesc_spe_predicates[] =
7086 /* Place-holder. Leave as first. */
7087 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7088 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7089 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7090 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7091 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7092 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7093 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7094 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7095 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7096 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7097 /* Place-holder. Leave as last. */
7098 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7101 /* SPE evsel predicates. */
7102 static struct builtin_description bdesc_spe_evsel[] =
7104 /* Place-holder. Leave as first. */
7105 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7106 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7107 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7108 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7109 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7110 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7111 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7112 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7113 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7114 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7115 /* Place-holder. Leave as last. */
7116 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7119 /* ABS* operations. */
7121 static const struct builtin_description bdesc_abs[] =
7123 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7124 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7125 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7126 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7127 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7128 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7129 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7132 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7135 static struct builtin_description bdesc_1arg[] =
7137 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7138 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7139 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7140 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7141 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7142 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7143 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7144 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7145 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7146 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7147 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7148 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7149 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7150 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7151 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7152 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7153 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7175 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7176 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7177 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7178 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7179 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7180 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7181 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7182 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7183 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7184 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7185 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7186 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7187 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7188 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7189 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7190 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7191 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7192 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7193 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7194 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7195 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7196 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7197 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7198 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7199 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7200 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7201 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7202 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7203 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7204 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7206 /* Place-holder. Leave as last unary SPE builtin. */
7207 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7211 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7214 tree arg0 = CALL_EXPR_ARG (exp, 0);
7215 rtx op0 = expand_normal (arg0);
7216 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7217 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7219 if (icode == CODE_FOR_nothing)
7220 /* Builtin not supported on this processor. */
7223 /* If we got invalid arguments bail out before generating bad rtl. */
7224 if (arg0 == error_mark_node)
7227 if (icode == CODE_FOR_altivec_vspltisb
7228 || icode == CODE_FOR_altivec_vspltish
7229 || icode == CODE_FOR_altivec_vspltisw
7230 || icode == CODE_FOR_spe_evsplatfi
7231 || icode == CODE_FOR_spe_evsplati)
7233 /* Only allow 5-bit *signed* literals. */
7234 if (GET_CODE (op0) != CONST_INT
7235 || INTVAL (op0) > 15
7236 || INTVAL (op0) < -16)
7238 error ("argument 1 must be a 5-bit signed literal");
7244 || GET_MODE (target) != tmode
7245 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7246 target = gen_reg_rtx (tmode);
7248 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7249 op0 = copy_to_mode_reg (mode0, op0);
7251 pat = GEN_FCN (icode) (target, op0);
7260 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7262 rtx pat, scratch1, scratch2;
7263 tree arg0 = CALL_EXPR_ARG (exp, 0);
7264 rtx op0 = expand_normal (arg0);
7265 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7266 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7268 /* If we have invalid arguments, bail out before generating bad rtl. */
7269 if (arg0 == error_mark_node)
7273 || GET_MODE (target) != tmode
7274 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7275 target = gen_reg_rtx (tmode);
7277 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7278 op0 = copy_to_mode_reg (mode0, op0);
7280 scratch1 = gen_reg_rtx (mode0);
7281 scratch2 = gen_reg_rtx (mode0);
7283 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7292 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7295 tree arg0 = CALL_EXPR_ARG (exp, 0);
7296 tree arg1 = CALL_EXPR_ARG (exp, 1);
7297 rtx op0 = expand_normal (arg0);
7298 rtx op1 = expand_normal (arg1);
7299 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7300 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7301 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7303 if (icode == CODE_FOR_nothing)
7304 /* Builtin not supported on this processor. */
7307 /* If we got invalid arguments bail out before generating bad rtl. */
7308 if (arg0 == error_mark_node || arg1 == error_mark_node)
7311 if (icode == CODE_FOR_altivec_vcfux
7312 || icode == CODE_FOR_altivec_vcfsx
7313 || icode == CODE_FOR_altivec_vctsxs
7314 || icode == CODE_FOR_altivec_vctuxs
7315 || icode == CODE_FOR_altivec_vspltb
7316 || icode == CODE_FOR_altivec_vsplth
7317 || icode == CODE_FOR_altivec_vspltw
7318 || icode == CODE_FOR_spe_evaddiw
7319 || icode == CODE_FOR_spe_evldd
7320 || icode == CODE_FOR_spe_evldh
7321 || icode == CODE_FOR_spe_evldw
7322 || icode == CODE_FOR_spe_evlhhesplat
7323 || icode == CODE_FOR_spe_evlhhossplat
7324 || icode == CODE_FOR_spe_evlhhousplat
7325 || icode == CODE_FOR_spe_evlwhe
7326 || icode == CODE_FOR_spe_evlwhos
7327 || icode == CODE_FOR_spe_evlwhou
7328 || icode == CODE_FOR_spe_evlwhsplat
7329 || icode == CODE_FOR_spe_evlwwsplat
7330 || icode == CODE_FOR_spe_evrlwi
7331 || icode == CODE_FOR_spe_evslwi
7332 || icode == CODE_FOR_spe_evsrwis
7333 || icode == CODE_FOR_spe_evsubifw
7334 || icode == CODE_FOR_spe_evsrwiu)
7336 /* Only allow 5-bit unsigned literals. */
7338 if (TREE_CODE (arg1) != INTEGER_CST
7339 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7341 error ("argument 2 must be a 5-bit unsigned literal");
7347 || GET_MODE (target) != tmode
7348 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7349 target = gen_reg_rtx (tmode);
7351 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7352 op0 = copy_to_mode_reg (mode0, op0);
7353 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7354 op1 = copy_to_mode_reg (mode1, op1);
7356 pat = GEN_FCN (icode) (target, op0, op1);
7365 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7366 tree exp, rtx target)
7369 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7370 tree arg0 = CALL_EXPR_ARG (exp, 1);
7371 tree arg1 = CALL_EXPR_ARG (exp, 2);
7372 rtx op0 = expand_normal (arg0);
7373 rtx op1 = expand_normal (arg1);
7374 enum machine_mode tmode = SImode;
7375 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7376 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7379 if (TREE_CODE (cr6_form) != INTEGER_CST)
7381 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7385 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7387 gcc_assert (mode0 == mode1);
7389 /* If we have invalid arguments, bail out before generating bad rtl. */
7390 if (arg0 == error_mark_node || arg1 == error_mark_node)
7394 || GET_MODE (target) != tmode
7395 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7396 target = gen_reg_rtx (tmode);
7398 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7399 op0 = copy_to_mode_reg (mode0, op0);
7400 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7401 op1 = copy_to_mode_reg (mode1, op1);
7403 scratch = gen_reg_rtx (mode0);
7405 pat = GEN_FCN (icode) (scratch, op0, op1,
7406 gen_rtx_SYMBOL_REF (Pmode, opcode));
7411 /* The vec_any* and vec_all* predicates use the same opcodes for two
7412 different operations, but the bits in CR6 will be different
7413 depending on what information we want. So we have to play tricks
7414 with CR6 to get the right bits out.
7416 If you think this is disgusting, look at the specs for the
7417 AltiVec predicates. */
7419 switch (cr6_form_int)
7422 emit_insn (gen_cr6_test_for_zero (target));
7425 emit_insn (gen_cr6_test_for_zero_reverse (target));
7428 emit_insn (gen_cr6_test_for_lt (target));
7431 emit_insn (gen_cr6_test_for_lt_reverse (target));
7434 error ("argument 1 of __builtin_altivec_predicate is out of range");
7442 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7445 tree arg0 = CALL_EXPR_ARG (exp, 0);
7446 tree arg1 = CALL_EXPR_ARG (exp, 1);
7447 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7448 enum machine_mode mode0 = Pmode;
7449 enum machine_mode mode1 = Pmode;
7450 rtx op0 = expand_normal (arg0);
7451 rtx op1 = expand_normal (arg1);
7453 if (icode == CODE_FOR_nothing)
7454 /* Builtin not supported on this processor. */
7457 /* If we got invalid arguments bail out before generating bad rtl. */
7458 if (arg0 == error_mark_node || arg1 == error_mark_node)
7462 || GET_MODE (target) != tmode
7463 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7464 target = gen_reg_rtx (tmode);
7466 op1 = copy_to_mode_reg (mode1, op1);
7468 if (op0 == const0_rtx)
7470 addr = gen_rtx_MEM (tmode, op1);
7474 op0 = copy_to_mode_reg (mode0, op0);
7475 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7478 pat = GEN_FCN (icode) (target, addr);
7488 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7490 tree arg0 = CALL_EXPR_ARG (exp, 0);
7491 tree arg1 = CALL_EXPR_ARG (exp, 1);
7492 tree arg2 = CALL_EXPR_ARG (exp, 2);
7493 rtx op0 = expand_normal (arg0);
7494 rtx op1 = expand_normal (arg1);
7495 rtx op2 = expand_normal (arg2);
7497 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7498 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7499 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7501 /* Invalid arguments. Bail before doing anything stoopid! */
7502 if (arg0 == error_mark_node
7503 || arg1 == error_mark_node
7504 || arg2 == error_mark_node)
7507 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7508 op0 = copy_to_mode_reg (mode2, op0);
7509 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7510 op1 = copy_to_mode_reg (mode0, op1);
7511 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7512 op2 = copy_to_mode_reg (mode1, op2);
7514 pat = GEN_FCN (icode) (op1, op2, op0);
7521 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7523 tree arg0 = CALL_EXPR_ARG (exp, 0);
7524 tree arg1 = CALL_EXPR_ARG (exp, 1);
7525 tree arg2 = CALL_EXPR_ARG (exp, 2);
7526 rtx op0 = expand_normal (arg0);
7527 rtx op1 = expand_normal (arg1);
7528 rtx op2 = expand_normal (arg2);
7530 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7531 enum machine_mode mode1 = Pmode;
7532 enum machine_mode mode2 = Pmode;
7534 /* Invalid arguments. Bail before doing anything stoopid! */
7535 if (arg0 == error_mark_node
7536 || arg1 == error_mark_node
7537 || arg2 == error_mark_node)
7540 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7541 op0 = copy_to_mode_reg (tmode, op0);
7543 op2 = copy_to_mode_reg (mode2, op2);
7545 if (op1 == const0_rtx)
7547 addr = gen_rtx_MEM (tmode, op2);
7551 op1 = copy_to_mode_reg (mode1, op1);
7552 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7555 pat = GEN_FCN (icode) (addr, op0);
7562 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7565 tree arg0 = CALL_EXPR_ARG (exp, 0);
7566 tree arg1 = CALL_EXPR_ARG (exp, 1);
7567 tree arg2 = CALL_EXPR_ARG (exp, 2);
7568 rtx op0 = expand_normal (arg0);
7569 rtx op1 = expand_normal (arg1);
7570 rtx op2 = expand_normal (arg2);
7571 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7572 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7573 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7574 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7576 if (icode == CODE_FOR_nothing)
7577 /* Builtin not supported on this processor. */
7580 /* If we got invalid arguments bail out before generating bad rtl. */
7581 if (arg0 == error_mark_node
7582 || arg1 == error_mark_node
7583 || arg2 == error_mark_node)
7586 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7587 || icode == CODE_FOR_altivec_vsldoi_v4si
7588 || icode == CODE_FOR_altivec_vsldoi_v8hi
7589 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7591 /* Only allow 4-bit unsigned literals. */
7593 if (TREE_CODE (arg2) != INTEGER_CST
7594 || TREE_INT_CST_LOW (arg2) & ~0xf)
7596 error ("argument 3 must be a 4-bit unsigned literal");
7602 || GET_MODE (target) != tmode
7603 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7604 target = gen_reg_rtx (tmode);
7606 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7607 op0 = copy_to_mode_reg (mode0, op0);
7608 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7609 op1 = copy_to_mode_reg (mode1, op1);
7610 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7611 op2 = copy_to_mode_reg (mode2, op2);
7613 pat = GEN_FCN (icode) (target, op0, op1, op2);
7621 /* Expand the lvx builtins. */
7623 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7625 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7626 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7628 enum machine_mode tmode, mode0;
7630 enum insn_code icode;
7634 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7635 icode = CODE_FOR_altivec_lvx_v16qi;
7637 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7638 icode = CODE_FOR_altivec_lvx_v8hi;
7640 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7641 icode = CODE_FOR_altivec_lvx_v4si;
7643 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7644 icode = CODE_FOR_altivec_lvx_v4sf;
7653 arg0 = CALL_EXPR_ARG (exp, 0);
7654 op0 = expand_normal (arg0);
7655 tmode = insn_data[icode].operand[0].mode;
7656 mode0 = insn_data[icode].operand[1].mode;
7659 || GET_MODE (target) != tmode
7660 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7661 target = gen_reg_rtx (tmode);
7663 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7664 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7666 pat = GEN_FCN (icode) (target, op0);
7673 /* Expand the stvx builtins. */
7675 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7678 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7679 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7681 enum machine_mode mode0, mode1;
7683 enum insn_code icode;
7687 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7688 icode = CODE_FOR_altivec_stvx_v16qi;
7690 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7691 icode = CODE_FOR_altivec_stvx_v8hi;
7693 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7694 icode = CODE_FOR_altivec_stvx_v4si;
7696 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7697 icode = CODE_FOR_altivec_stvx_v4sf;
7704 arg0 = CALL_EXPR_ARG (exp, 0);
7705 arg1 = CALL_EXPR_ARG (exp, 1);
7706 op0 = expand_normal (arg0);
7707 op1 = expand_normal (arg1);
7708 mode0 = insn_data[icode].operand[0].mode;
7709 mode1 = insn_data[icode].operand[1].mode;
7711 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7712 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7713 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7714 op1 = copy_to_mode_reg (mode1, op1);
7716 pat = GEN_FCN (icode) (op0, op1);
7724 /* Expand the dst builtins. */
7726 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7729 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7730 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7731 tree arg0, arg1, arg2;
7732 enum machine_mode mode0, mode1, mode2;
7733 rtx pat, op0, op1, op2;
7734 struct builtin_description *d;
7739 /* Handle DST variants. */
7740 d = (struct builtin_description *) bdesc_dst;
7741 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7742 if (d->code == fcode)
7744 arg0 = CALL_EXPR_ARG (exp, 0);
7745 arg1 = CALL_EXPR_ARG (exp, 1);
7746 arg2 = CALL_EXPR_ARG (exp, 2);
7747 op0 = expand_normal (arg0);
7748 op1 = expand_normal (arg1);
7749 op2 = expand_normal (arg2);
7750 mode0 = insn_data[d->icode].operand[0].mode;
7751 mode1 = insn_data[d->icode].operand[1].mode;
7752 mode2 = insn_data[d->icode].operand[2].mode;
7754 /* Invalid arguments, bail out before generating bad rtl. */
7755 if (arg0 == error_mark_node
7756 || arg1 == error_mark_node
7757 || arg2 == error_mark_node)
7762 if (TREE_CODE (arg2) != INTEGER_CST
7763 || TREE_INT_CST_LOW (arg2) & ~0x3)
7765 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7769 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7770 op0 = copy_to_mode_reg (Pmode, op0);
7771 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7772 op1 = copy_to_mode_reg (mode1, op1);
7774 pat = GEN_FCN (d->icode) (op0, op1, op2);
7784 /* Expand vec_init builtin. */
7786 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7788 enum machine_mode tmode = TYPE_MODE (type);
7789 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7790 int i, n_elt = GET_MODE_NUNITS (tmode);
7791 rtvec v = rtvec_alloc (n_elt);
7793 gcc_assert (VECTOR_MODE_P (tmode));
7794 gcc_assert (n_elt == call_expr_nargs (exp));
7796 for (i = 0; i < n_elt; ++i)
7798 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7799 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7802 if (!target || !register_operand (target, tmode))
7803 target = gen_reg_rtx (tmode);
7805 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7809 /* Return the integer constant in ARG. Constrain it to be in the range
7810 of the subparts of VEC_TYPE; issue an error if not. */
7813 get_element_number (tree vec_type, tree arg)
7815 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7817 if (!host_integerp (arg, 1)
7818 || (elt = tree_low_cst (arg, 1), elt > max))
7820 error ("selector must be an integer constant in the range 0..%wi", max);
7827 /* Expand vec_set builtin. */
7829 altivec_expand_vec_set_builtin (tree exp)
7831 enum machine_mode tmode, mode1;
7832 tree arg0, arg1, arg2;
7836 arg0 = CALL_EXPR_ARG (exp, 0);
7837 arg1 = CALL_EXPR_ARG (exp, 1);
7838 arg2 = CALL_EXPR_ARG (exp, 2);
7840 tmode = TYPE_MODE (TREE_TYPE (arg0));
7841 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7842 gcc_assert (VECTOR_MODE_P (tmode));
7844 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7845 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7846 elt = get_element_number (TREE_TYPE (arg0), arg2);
7848 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7849 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7851 op0 = force_reg (tmode, op0);
7852 op1 = force_reg (mode1, op1);
7854 rs6000_expand_vector_set (op0, op1, elt);
7859 /* Expand vec_ext builtin. */
7861 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7863 enum machine_mode tmode, mode0;
7868 arg0 = CALL_EXPR_ARG (exp, 0);
7869 arg1 = CALL_EXPR_ARG (exp, 1);
7871 op0 = expand_normal (arg0);
7872 elt = get_element_number (TREE_TYPE (arg0), arg1);
7874 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7875 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7876 gcc_assert (VECTOR_MODE_P (mode0));
7878 op0 = force_reg (mode0, op0);
7880 if (optimize || !target || !register_operand (target, tmode))
7881 target = gen_reg_rtx (tmode);
7883 rs6000_expand_vector_extract (target, op0, elt);
7888 /* Expand the builtin in EXP and store the result in TARGET. Store
7889 true in *EXPANDEDP if we found a builtin to expand. */
7891 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7893 struct builtin_description *d;
7894 struct builtin_description_predicates *dp;
7896 enum insn_code icode;
7897 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7900 enum machine_mode tmode, mode0;
7901 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7903 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7904 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7907 error ("unresolved overload for Altivec builtin %qF", fndecl);
7911 target = altivec_expand_ld_builtin (exp, target, expandedp);
7915 target = altivec_expand_st_builtin (exp, target, expandedp);
7919 target = altivec_expand_dst_builtin (exp, target, expandedp);
7927 case ALTIVEC_BUILTIN_STVX:
7928 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7929 case ALTIVEC_BUILTIN_STVEBX:
7930 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7931 case ALTIVEC_BUILTIN_STVEHX:
7932 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7933 case ALTIVEC_BUILTIN_STVEWX:
7934 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7935 case ALTIVEC_BUILTIN_STVXL:
7936 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7938 case ALTIVEC_BUILTIN_MFVSCR:
7939 icode = CODE_FOR_altivec_mfvscr;
7940 tmode = insn_data[icode].operand[0].mode;
7943 || GET_MODE (target) != tmode
7944 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7945 target = gen_reg_rtx (tmode);
7947 pat = GEN_FCN (icode) (target);
7953 case ALTIVEC_BUILTIN_MTVSCR:
7954 icode = CODE_FOR_altivec_mtvscr;
7955 arg0 = CALL_EXPR_ARG (exp, 0);
7956 op0 = expand_normal (arg0);
7957 mode0 = insn_data[icode].operand[0].mode;
7959 /* If we got invalid arguments bail out before generating bad rtl. */
7960 if (arg0 == error_mark_node)
7963 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7964 op0 = copy_to_mode_reg (mode0, op0);
7966 pat = GEN_FCN (icode) (op0);
7971 case ALTIVEC_BUILTIN_DSSALL:
7972 emit_insn (gen_altivec_dssall ());
7975 case ALTIVEC_BUILTIN_DSS:
7976 icode = CODE_FOR_altivec_dss;
7977 arg0 = CALL_EXPR_ARG (exp, 0);
7979 op0 = expand_normal (arg0);
7980 mode0 = insn_data[icode].operand[0].mode;
7982 /* If we got invalid arguments bail out before generating bad rtl. */
7983 if (arg0 == error_mark_node)
7986 if (TREE_CODE (arg0) != INTEGER_CST
7987 || TREE_INT_CST_LOW (arg0) & ~0x3)
7989 error ("argument to dss must be a 2-bit unsigned literal");
7993 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7994 op0 = copy_to_mode_reg (mode0, op0);
7996 emit_insn (gen_altivec_dss (op0));
7999 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8000 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8001 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8002 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8003 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8005 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8006 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8007 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8008 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8009 return altivec_expand_vec_set_builtin (exp);
8011 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8012 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8013 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8014 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8015 return altivec_expand_vec_ext_builtin (exp, target);
8022 /* Expand abs* operations. */
8023 d = (struct builtin_description *) bdesc_abs;
8024 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8025 if (d->code == fcode)
8026 return altivec_expand_abs_builtin (d->icode, exp, target);
8028 /* Expand the AltiVec predicates. */
8029 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8030 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8031 if (dp->code == fcode)
8032 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8035 /* LV* are funky. We initialized them differently. */
8038 case ALTIVEC_BUILTIN_LVSL:
8039 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8041 case ALTIVEC_BUILTIN_LVSR:
8042 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8044 case ALTIVEC_BUILTIN_LVEBX:
8045 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8047 case ALTIVEC_BUILTIN_LVEHX:
8048 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8050 case ALTIVEC_BUILTIN_LVEWX:
8051 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8053 case ALTIVEC_BUILTIN_LVXL:
8054 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8056 case ALTIVEC_BUILTIN_LVX:
8057 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8068 /* Binops that need to be initialized manually, but can be expanded
8069 automagically by rs6000_expand_binop_builtin. */
8070 static struct builtin_description bdesc_2arg_spe[] =
8072 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8073 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8074 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8075 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8076 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8077 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8078 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8079 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8080 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8081 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8082 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8083 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8084 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8085 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8086 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8087 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8088 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8089 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8090 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8091 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8092 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8093 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8096 /* Expand the builtin in EXP and store the result in TARGET. Store
8097 true in *EXPANDEDP if we found a builtin to expand.
8099 This expands the SPE builtins that are not simple unary and binary
8102 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8104 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8106 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8107 enum insn_code icode;
8108 enum machine_mode tmode, mode0;
8110 struct builtin_description *d;
8115 /* Syntax check for a 5-bit unsigned immediate. */
8118 case SPE_BUILTIN_EVSTDD:
8119 case SPE_BUILTIN_EVSTDH:
8120 case SPE_BUILTIN_EVSTDW:
8121 case SPE_BUILTIN_EVSTWHE:
8122 case SPE_BUILTIN_EVSTWHO:
8123 case SPE_BUILTIN_EVSTWWE:
8124 case SPE_BUILTIN_EVSTWWO:
8125 arg1 = CALL_EXPR_ARG (exp, 2);
8126 if (TREE_CODE (arg1) != INTEGER_CST
8127 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8129 error ("argument 2 must be a 5-bit unsigned literal");
8137 /* The evsplat*i instructions are not quite generic. */
8140 case SPE_BUILTIN_EVSPLATFI:
8141 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8143 case SPE_BUILTIN_EVSPLATI:
8144 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8150 d = (struct builtin_description *) bdesc_2arg_spe;
8151 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8152 if (d->code == fcode)
8153 return rs6000_expand_binop_builtin (d->icode, exp, target);
8155 d = (struct builtin_description *) bdesc_spe_predicates;
8156 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8157 if (d->code == fcode)
8158 return spe_expand_predicate_builtin (d->icode, exp, target);
8160 d = (struct builtin_description *) bdesc_spe_evsel;
8161 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8162 if (d->code == fcode)
8163 return spe_expand_evsel_builtin (d->icode, exp, target);
8167 case SPE_BUILTIN_EVSTDDX:
8168 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8169 case SPE_BUILTIN_EVSTDHX:
8170 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8171 case SPE_BUILTIN_EVSTDWX:
8172 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8173 case SPE_BUILTIN_EVSTWHEX:
8174 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8175 case SPE_BUILTIN_EVSTWHOX:
8176 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8177 case SPE_BUILTIN_EVSTWWEX:
8178 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8179 case SPE_BUILTIN_EVSTWWOX:
8180 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8181 case SPE_BUILTIN_EVSTDD:
8182 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8183 case SPE_BUILTIN_EVSTDH:
8184 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8185 case SPE_BUILTIN_EVSTDW:
8186 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8187 case SPE_BUILTIN_EVSTWHE:
8188 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8189 case SPE_BUILTIN_EVSTWHO:
8190 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8191 case SPE_BUILTIN_EVSTWWE:
8192 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8193 case SPE_BUILTIN_EVSTWWO:
8194 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8195 case SPE_BUILTIN_MFSPEFSCR:
8196 icode = CODE_FOR_spe_mfspefscr;
8197 tmode = insn_data[icode].operand[0].mode;
8200 || GET_MODE (target) != tmode
8201 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8202 target = gen_reg_rtx (tmode);
8204 pat = GEN_FCN (icode) (target);
8209 case SPE_BUILTIN_MTSPEFSCR:
8210 icode = CODE_FOR_spe_mtspefscr;
8211 arg0 = CALL_EXPR_ARG (exp, 0);
8212 op0 = expand_normal (arg0);
8213 mode0 = insn_data[icode].operand[0].mode;
8215 if (arg0 == error_mark_node)
8218 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8219 op0 = copy_to_mode_reg (mode0, op0);
8221 pat = GEN_FCN (icode) (op0);
8234 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8236 rtx pat, scratch, tmp;
8237 tree form = CALL_EXPR_ARG (exp, 0);
8238 tree arg0 = CALL_EXPR_ARG (exp, 1);
8239 tree arg1 = CALL_EXPR_ARG (exp, 2);
8240 rtx op0 = expand_normal (arg0);
8241 rtx op1 = expand_normal (arg1);
8242 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8243 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8247 if (TREE_CODE (form) != INTEGER_CST)
8249 error ("argument 1 of __builtin_spe_predicate must be a constant");
8253 form_int = TREE_INT_CST_LOW (form);
8255 gcc_assert (mode0 == mode1);
8257 if (arg0 == error_mark_node || arg1 == error_mark_node)
8261 || GET_MODE (target) != SImode
8262 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8263 target = gen_reg_rtx (SImode);
8265 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8266 op0 = copy_to_mode_reg (mode0, op0);
8267 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8268 op1 = copy_to_mode_reg (mode1, op1);
8270 scratch = gen_reg_rtx (CCmode);
8272 pat = GEN_FCN (icode) (scratch, op0, op1);
8277 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8278 _lower_. We use one compare, but look in different bits of the
8279 CR for each variant.
8281 There are 2 elements in each SPE simd type (upper/lower). The CR
8282 bits are set as follows:
8284 BIT0 | BIT 1 | BIT 2 | BIT 3
8285 U | L | (U | L) | (U & L)
8287 So, for an "all" relationship, BIT 3 would be set.
8288 For an "any" relationship, BIT 2 would be set. Etc.
8290 Following traditional nomenclature, these bits map to:
8292 BIT0 | BIT 1 | BIT 2 | BIT 3
8295 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8300 /* All variant. OV bit. */
8302 /* We need to get to the OV bit, which is the ORDERED bit. We
8303 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8304 that's ugly and will make validate_condition_mode die.
8305 So let's just use another pattern. */
8306 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8308 /* Any variant. EQ bit. */
8312 /* Upper variant. LT bit. */
8316 /* Lower variant. GT bit. */
8321 error ("argument 1 of __builtin_spe_predicate is out of range");
8325 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8326 emit_move_insn (target, tmp);
8331 /* The evsel builtins look like this:
8333 e = __builtin_spe_evsel_OP (a, b, c, d);
8337 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8338 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8342 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8345 tree arg0 = CALL_EXPR_ARG (exp, 0);
8346 tree arg1 = CALL_EXPR_ARG (exp, 1);
8347 tree arg2 = CALL_EXPR_ARG (exp, 2);
8348 tree arg3 = CALL_EXPR_ARG (exp, 3);
8349 rtx op0 = expand_normal (arg0);
8350 rtx op1 = expand_normal (arg1);
8351 rtx op2 = expand_normal (arg2);
8352 rtx op3 = expand_normal (arg3);
8353 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8354 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8356 gcc_assert (mode0 == mode1);
8358 if (arg0 == error_mark_node || arg1 == error_mark_node
8359 || arg2 == error_mark_node || arg3 == error_mark_node)
8363 || GET_MODE (target) != mode0
8364 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8365 target = gen_reg_rtx (mode0);
8367 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8368 op0 = copy_to_mode_reg (mode0, op0);
8369 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8370 op1 = copy_to_mode_reg (mode0, op1);
8371 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8372 op2 = copy_to_mode_reg (mode0, op2);
8373 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8374 op3 = copy_to_mode_reg (mode0, op3);
8376 /* Generate the compare. */
8377 scratch = gen_reg_rtx (CCmode);
8378 pat = GEN_FCN (icode) (scratch, op0, op1);
8383 if (mode0 == V2SImode)
8384 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8386 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8391 /* Expand an expression EXP that calls a built-in function,
8392 with result going to TARGET if that's convenient
8393 (and in mode MODE if that's convenient).
8394 SUBTARGET may be used as the target for computing one of EXP's operands.
8395 IGNORE is nonzero if the value is to be ignored. */
8398 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8399 enum machine_mode mode ATTRIBUTE_UNUSED,
8400 int ignore ATTRIBUTE_UNUSED)
8402 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8403 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8404 struct builtin_description *d;
8409 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8410 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8412 int icode = (int) CODE_FOR_altivec_lvsr;
8413 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8414 enum machine_mode mode = insn_data[icode].operand[1].mode;
8418 gcc_assert (TARGET_ALTIVEC);
8420 arg = CALL_EXPR_ARG (exp, 0);
8421 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8422 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8423 addr = memory_address (mode, op);
8424 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8428 /* For the load case need to negate the address. */
8429 op = gen_reg_rtx (GET_MODE (addr));
8430 emit_insn (gen_rtx_SET (VOIDmode, op,
8431 gen_rtx_NEG (GET_MODE (addr), addr)));
8433 op = gen_rtx_MEM (mode, op);
8436 || GET_MODE (target) != tmode
8437 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8438 target = gen_reg_rtx (tmode);
8440 /*pat = gen_altivec_lvsr (target, op);*/
8441 pat = GEN_FCN (icode) (target, op);
8449 /* FIXME: There's got to be a nicer way to handle this case than
8450 constructing a new CALL_EXPR. */
8451 if (fcode == ALTIVEC_BUILTIN_VCFUX
8452 || fcode == ALTIVEC_BUILTIN_VCFSX)
8454 if (call_expr_nargs (exp) == 1)
8455 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8456 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8461 ret = altivec_expand_builtin (exp, target, &success);
8468 ret = spe_expand_builtin (exp, target, &success);
8474 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8476 /* Handle simple unary operations. */
8477 d = (struct builtin_description *) bdesc_1arg;
8478 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8479 if (d->code == fcode)
8480 return rs6000_expand_unop_builtin (d->icode, exp, target);
8482 /* Handle simple binary operations. */
8483 d = (struct builtin_description *) bdesc_2arg;
8484 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8485 if (d->code == fcode)
8486 return rs6000_expand_binop_builtin (d->icode, exp, target);
8488 /* Handle simple ternary operations. */
8489 d = (struct builtin_description *) bdesc_3arg;
8490 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8491 if (d->code == fcode)
8492 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8498 build_opaque_vector_type (tree node, int nunits)
8500 node = copy_node (node);
8501 TYPE_MAIN_VARIANT (node) = node;
8502 return build_vector_type (node, nunits);
8506 rs6000_init_builtins (void)
8508 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8509 V2SF_type_node = build_vector_type (float_type_node, 2);
8510 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8511 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8512 V4SF_type_node = build_vector_type (float_type_node, 4);
8513 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8514 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8516 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8517 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8518 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8520 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8521 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8522 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8523 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8525 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8526 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8527 'vector unsigned short'. */
8529 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8530 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8531 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8532 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8534 long_integer_type_internal_node = long_integer_type_node;
8535 long_unsigned_type_internal_node = long_unsigned_type_node;
8536 intQI_type_internal_node = intQI_type_node;
8537 uintQI_type_internal_node = unsigned_intQI_type_node;
8538 intHI_type_internal_node = intHI_type_node;
8539 uintHI_type_internal_node = unsigned_intHI_type_node;
8540 intSI_type_internal_node = intSI_type_node;
8541 uintSI_type_internal_node = unsigned_intSI_type_node;
8542 float_type_internal_node = float_type_node;
8543 void_type_internal_node = void_type_node;
8545 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8546 get_identifier ("__bool char"),
8547 bool_char_type_node));
8548 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8549 get_identifier ("__bool short"),
8550 bool_short_type_node));
8551 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8552 get_identifier ("__bool int"),
8553 bool_int_type_node));
8554 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8555 get_identifier ("__pixel"),
8558 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8559 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8560 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8561 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8563 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8564 get_identifier ("__vector unsigned char"),
8565 unsigned_V16QI_type_node));
8566 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8567 get_identifier ("__vector signed char"),
8569 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8570 get_identifier ("__vector __bool char"),
8571 bool_V16QI_type_node));
8573 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8574 get_identifier ("__vector unsigned short"),
8575 unsigned_V8HI_type_node));
8576 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8577 get_identifier ("__vector signed short"),
8579 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8580 get_identifier ("__vector __bool short"),
8581 bool_V8HI_type_node));
8583 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8584 get_identifier ("__vector unsigned int"),
8585 unsigned_V4SI_type_node));
8586 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8587 get_identifier ("__vector signed int"),
8589 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8590 get_identifier ("__vector __bool int"),
8591 bool_V4SI_type_node));
8593 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8594 get_identifier ("__vector float"),
8596 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8597 get_identifier ("__vector __pixel"),
8598 pixel_V8HI_type_node));
8601 spe_init_builtins ();
8603 altivec_init_builtins ();
8604 if (TARGET_ALTIVEC || TARGET_SPE)
8605 rs6000_common_init_builtins ();
8608 /* AIX libm provides clog as __clog. */
8609 if (built_in_decls [BUILT_IN_CLOG])
8610 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8614 /* Search through a set of builtins and enable the mask bits.
8615 DESC is an array of builtins.
8616 SIZE is the total number of builtins.
8617 START is the builtin enum at which to start.
8618 END is the builtin enum at which to end. */
8620 enable_mask_for_builtins (struct builtin_description *desc, int size,
8621 enum rs6000_builtins start,
8622 enum rs6000_builtins end)
8626 for (i = 0; i < size; ++i)
8627 if (desc[i].code == start)
8633 for (; i < size; ++i)
8635 /* Flip all the bits on. */
8636 desc[i].mask = target_flags;
8637 if (desc[i].code == end)
8643 spe_init_builtins (void)
8645 tree endlink = void_list_node;
8646 tree puint_type_node = build_pointer_type (unsigned_type_node);
8647 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8648 struct builtin_description *d;
8651 tree v2si_ftype_4_v2si
8652 = build_function_type
8653 (opaque_V2SI_type_node,
8654 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8655 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8656 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8657 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8660 tree v2sf_ftype_4_v2sf
8661 = build_function_type
8662 (opaque_V2SF_type_node,
8663 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8664 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8665 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8666 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8669 tree int_ftype_int_v2si_v2si
8670 = build_function_type
8672 tree_cons (NULL_TREE, integer_type_node,
8673 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8674 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8677 tree int_ftype_int_v2sf_v2sf
8678 = build_function_type
8680 tree_cons (NULL_TREE, integer_type_node,
8681 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8682 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8685 tree void_ftype_v2si_puint_int
8686 = build_function_type (void_type_node,
8687 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8688 tree_cons (NULL_TREE, puint_type_node,
8689 tree_cons (NULL_TREE,
8693 tree void_ftype_v2si_puint_char
8694 = build_function_type (void_type_node,
8695 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8696 tree_cons (NULL_TREE, puint_type_node,
8697 tree_cons (NULL_TREE,
8701 tree void_ftype_v2si_pv2si_int
8702 = build_function_type (void_type_node,
8703 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8704 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8705 tree_cons (NULL_TREE,
8709 tree void_ftype_v2si_pv2si_char
8710 = build_function_type (void_type_node,
8711 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8712 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8713 tree_cons (NULL_TREE,
8718 = build_function_type (void_type_node,
8719 tree_cons (NULL_TREE, integer_type_node, endlink));
8722 = build_function_type (integer_type_node, endlink);
8724 tree v2si_ftype_pv2si_int
8725 = build_function_type (opaque_V2SI_type_node,
8726 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8727 tree_cons (NULL_TREE, integer_type_node,
8730 tree v2si_ftype_puint_int
8731 = build_function_type (opaque_V2SI_type_node,
8732 tree_cons (NULL_TREE, puint_type_node,
8733 tree_cons (NULL_TREE, integer_type_node,
8736 tree v2si_ftype_pushort_int
8737 = build_function_type (opaque_V2SI_type_node,
8738 tree_cons (NULL_TREE, pushort_type_node,
8739 tree_cons (NULL_TREE, integer_type_node,
8742 tree v2si_ftype_signed_char
8743 = build_function_type (opaque_V2SI_type_node,
8744 tree_cons (NULL_TREE, signed_char_type_node,
8747 /* The initialization of the simple binary and unary builtins is
8748 done in rs6000_common_init_builtins, but we have to enable the
8749 mask bits here manually because we have run out of `target_flags'
8750 bits. We really need to redesign this mask business. */
8752 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8753 ARRAY_SIZE (bdesc_2arg),
8756 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8757 ARRAY_SIZE (bdesc_1arg),
8759 SPE_BUILTIN_EVSUBFUSIAAW);
8760 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8761 ARRAY_SIZE (bdesc_spe_predicates),
8762 SPE_BUILTIN_EVCMPEQ,
8763 SPE_BUILTIN_EVFSTSTLT);
8764 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8765 ARRAY_SIZE (bdesc_spe_evsel),
8766 SPE_BUILTIN_EVSEL_CMPGTS,
8767 SPE_BUILTIN_EVSEL_FSTSTEQ);
8769 (*lang_hooks.decls.pushdecl)
8770 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8771 opaque_V2SI_type_node));
8773 /* Initialize irregular SPE builtins. */
8775 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8776 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8777 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8778 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8779 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8780 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8781 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8782 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8783 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8784 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8785 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8786 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8787 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8788 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8789 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8790 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8791 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8792 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8795 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8796 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8797 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8798 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8799 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8800 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8801 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8802 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8803 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8804 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8805 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8806 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8807 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8808 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8809 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8810 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8811 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8812 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8813 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8814 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8815 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8816 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8819 d = (struct builtin_description *) bdesc_spe_predicates;
8820 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8824 switch (insn_data[d->icode].operand[1].mode)
8827 type = int_ftype_int_v2si_v2si;
8830 type = int_ftype_int_v2sf_v2sf;
8836 def_builtin (d->mask, d->name, type, d->code);
8839 /* Evsel predicates. */
8840 d = (struct builtin_description *) bdesc_spe_evsel;
8841 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8845 switch (insn_data[d->icode].operand[1].mode)
8848 type = v2si_ftype_4_v2si;
8851 type = v2sf_ftype_4_v2sf;
8857 def_builtin (d->mask, d->name, type, d->code);
8862 altivec_init_builtins (void)
8864 struct builtin_description *d;
8865 struct builtin_description_predicates *dp;
8869 tree pfloat_type_node = build_pointer_type (float_type_node);
8870 tree pint_type_node = build_pointer_type (integer_type_node);
8871 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8872 tree pchar_type_node = build_pointer_type (char_type_node);
8874 tree pvoid_type_node = build_pointer_type (void_type_node);
8876 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8877 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8878 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8879 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8881 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8883 tree int_ftype_opaque
8884 = build_function_type_list (integer_type_node,
8885 opaque_V4SI_type_node, NULL_TREE);
8887 tree opaque_ftype_opaque_int
8888 = build_function_type_list (opaque_V4SI_type_node,
8889 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8890 tree opaque_ftype_opaque_opaque_int
8891 = build_function_type_list (opaque_V4SI_type_node,
8892 opaque_V4SI_type_node, opaque_V4SI_type_node,
8893 integer_type_node, NULL_TREE);
8894 tree int_ftype_int_opaque_opaque
8895 = build_function_type_list (integer_type_node,
8896 integer_type_node, opaque_V4SI_type_node,
8897 opaque_V4SI_type_node, NULL_TREE);
8898 tree int_ftype_int_v4si_v4si
8899 = build_function_type_list (integer_type_node,
8900 integer_type_node, V4SI_type_node,
8901 V4SI_type_node, NULL_TREE);
8902 tree v4sf_ftype_pcfloat
8903 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8904 tree void_ftype_pfloat_v4sf
8905 = build_function_type_list (void_type_node,
8906 pfloat_type_node, V4SF_type_node, NULL_TREE);
8907 tree v4si_ftype_pcint
8908 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8909 tree void_ftype_pint_v4si
8910 = build_function_type_list (void_type_node,
8911 pint_type_node, V4SI_type_node, NULL_TREE);
8912 tree v8hi_ftype_pcshort
8913 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8914 tree void_ftype_pshort_v8hi
8915 = build_function_type_list (void_type_node,
8916 pshort_type_node, V8HI_type_node, NULL_TREE);
8917 tree v16qi_ftype_pcchar
8918 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8919 tree void_ftype_pchar_v16qi
8920 = build_function_type_list (void_type_node,
8921 pchar_type_node, V16QI_type_node, NULL_TREE);
8922 tree void_ftype_v4si
8923 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8924 tree v8hi_ftype_void
8925 = build_function_type (V8HI_type_node, void_list_node);
8926 tree void_ftype_void
8927 = build_function_type (void_type_node, void_list_node);
8929 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8931 tree opaque_ftype_long_pcvoid
8932 = build_function_type_list (opaque_V4SI_type_node,
8933 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8934 tree v16qi_ftype_long_pcvoid
8935 = build_function_type_list (V16QI_type_node,
8936 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8937 tree v8hi_ftype_long_pcvoid
8938 = build_function_type_list (V8HI_type_node,
8939 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8940 tree v4si_ftype_long_pcvoid
8941 = build_function_type_list (V4SI_type_node,
8942 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8944 tree void_ftype_opaque_long_pvoid
8945 = build_function_type_list (void_type_node,
8946 opaque_V4SI_type_node, long_integer_type_node,
8947 pvoid_type_node, NULL_TREE);
8948 tree void_ftype_v4si_long_pvoid
8949 = build_function_type_list (void_type_node,
8950 V4SI_type_node, long_integer_type_node,
8951 pvoid_type_node, NULL_TREE);
8952 tree void_ftype_v16qi_long_pvoid
8953 = build_function_type_list (void_type_node,
8954 V16QI_type_node, long_integer_type_node,
8955 pvoid_type_node, NULL_TREE);
8956 tree void_ftype_v8hi_long_pvoid
8957 = build_function_type_list (void_type_node,
8958 V8HI_type_node, long_integer_type_node,
8959 pvoid_type_node, NULL_TREE);
8960 tree int_ftype_int_v8hi_v8hi
8961 = build_function_type_list (integer_type_node,
8962 integer_type_node, V8HI_type_node,
8963 V8HI_type_node, NULL_TREE);
8964 tree int_ftype_int_v16qi_v16qi
8965 = build_function_type_list (integer_type_node,
8966 integer_type_node, V16QI_type_node,
8967 V16QI_type_node, NULL_TREE);
8968 tree int_ftype_int_v4sf_v4sf
8969 = build_function_type_list (integer_type_node,
8970 integer_type_node, V4SF_type_node,
8971 V4SF_type_node, NULL_TREE);
8972 tree v4si_ftype_v4si
8973 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8974 tree v8hi_ftype_v8hi
8975 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8976 tree v16qi_ftype_v16qi
8977 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8978 tree v4sf_ftype_v4sf
8979 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8980 tree void_ftype_pcvoid_int_int
8981 = build_function_type_list (void_type_node,
8982 pcvoid_type_node, integer_type_node,
8983 integer_type_node, NULL_TREE);
8985 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8986 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8987 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8988 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8989 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8990 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8991 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8992 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8993 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8994 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8995 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8996 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8997 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8998 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8999 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9000 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9001 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9002 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9003 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9004 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9005 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9006 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9007 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9008 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9009 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9010 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9011 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9012 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9013 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9014 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9015 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9016 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9017 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9018 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9019 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9020 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9021 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9022 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9023 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9024 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9025 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9026 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9027 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9028 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9029 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9030 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9032 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9034 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9035 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9036 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9037 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9038 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9039 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9040 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9041 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9042 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9043 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9045 /* Add the DST variants. */
9046 d = (struct builtin_description *) bdesc_dst;
9047 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9048 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9050 /* Initialize the predicates. */
9051 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
9052 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9054 enum machine_mode mode1;
9056 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9057 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9062 mode1 = insn_data[dp->icode].operand[1].mode;
9067 type = int_ftype_int_opaque_opaque;
9070 type = int_ftype_int_v4si_v4si;
9073 type = int_ftype_int_v8hi_v8hi;
9076 type = int_ftype_int_v16qi_v16qi;
9079 type = int_ftype_int_v4sf_v4sf;
9085 def_builtin (dp->mask, dp->name, type, dp->code);
9088 /* Initialize the abs* operators. */
9089 d = (struct builtin_description *) bdesc_abs;
9090 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9092 enum machine_mode mode0;
9095 mode0 = insn_data[d->icode].operand[0].mode;
9100 type = v4si_ftype_v4si;
9103 type = v8hi_ftype_v8hi;
9106 type = v16qi_ftype_v16qi;
9109 type = v4sf_ftype_v4sf;
9115 def_builtin (d->mask, d->name, type, d->code);
9122 /* Initialize target builtin that implements
9123 targetm.vectorize.builtin_mask_for_load. */
9125 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9126 v16qi_ftype_long_pcvoid,
9127 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9128 BUILT_IN_MD, NULL, NULL_TREE);
9129 TREE_READONLY (decl) = 1;
9130 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9131 altivec_builtin_mask_for_load = decl;
9134 /* Access to the vec_init patterns. */
9135 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9136 integer_type_node, integer_type_node,
9137 integer_type_node, NULL_TREE);
9138 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9139 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9141 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9142 short_integer_type_node,
9143 short_integer_type_node,
9144 short_integer_type_node,
9145 short_integer_type_node,
9146 short_integer_type_node,
9147 short_integer_type_node,
9148 short_integer_type_node, NULL_TREE);
9149 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9150 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9152 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9153 char_type_node, char_type_node,
9154 char_type_node, char_type_node,
9155 char_type_node, char_type_node,
9156 char_type_node, char_type_node,
9157 char_type_node, char_type_node,
9158 char_type_node, char_type_node,
9159 char_type_node, char_type_node,
9160 char_type_node, NULL_TREE);
9161 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9162 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9164 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9165 float_type_node, float_type_node,
9166 float_type_node, NULL_TREE);
9167 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9168 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9170 /* Access to the vec_set patterns. */
9171 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9173 integer_type_node, NULL_TREE);
9174 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9175 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9177 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9179 integer_type_node, NULL_TREE);
9180 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9181 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9183 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9185 integer_type_node, NULL_TREE);
9186 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9187 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9189 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9191 integer_type_node, NULL_TREE);
9192 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9193 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9195 /* Access to the vec_extract patterns. */
9196 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9197 integer_type_node, NULL_TREE);
9198 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9199 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9201 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9202 integer_type_node, NULL_TREE);
9203 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9204 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9206 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9207 integer_type_node, NULL_TREE);
9208 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9209 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9211 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9212 integer_type_node, NULL_TREE);
9213 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9214 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9218 rs6000_common_init_builtins (void)
9220 struct builtin_description *d;
9223 tree v4sf_ftype_v4sf_v4sf_v16qi
9224 = build_function_type_list (V4SF_type_node,
9225 V4SF_type_node, V4SF_type_node,
9226 V16QI_type_node, NULL_TREE);
9227 tree v4si_ftype_v4si_v4si_v16qi
9228 = build_function_type_list (V4SI_type_node,
9229 V4SI_type_node, V4SI_type_node,
9230 V16QI_type_node, NULL_TREE);
9231 tree v8hi_ftype_v8hi_v8hi_v16qi
9232 = build_function_type_list (V8HI_type_node,
9233 V8HI_type_node, V8HI_type_node,
9234 V16QI_type_node, NULL_TREE);
9235 tree v16qi_ftype_v16qi_v16qi_v16qi
9236 = build_function_type_list (V16QI_type_node,
9237 V16QI_type_node, V16QI_type_node,
9238 V16QI_type_node, NULL_TREE);
9240 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9242 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9243 tree v16qi_ftype_int
9244 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9245 tree v8hi_ftype_v16qi
9246 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9247 tree v4sf_ftype_v4sf
9248 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9250 tree v2si_ftype_v2si_v2si
9251 = build_function_type_list (opaque_V2SI_type_node,
9252 opaque_V2SI_type_node,
9253 opaque_V2SI_type_node, NULL_TREE);
9255 tree v2sf_ftype_v2sf_v2sf
9256 = build_function_type_list (opaque_V2SF_type_node,
9257 opaque_V2SF_type_node,
9258 opaque_V2SF_type_node, NULL_TREE);
9260 tree v2si_ftype_int_int
9261 = build_function_type_list (opaque_V2SI_type_node,
9262 integer_type_node, integer_type_node,
9265 tree opaque_ftype_opaque
9266 = build_function_type_list (opaque_V4SI_type_node,
9267 opaque_V4SI_type_node, NULL_TREE);
9269 tree v2si_ftype_v2si
9270 = build_function_type_list (opaque_V2SI_type_node,
9271 opaque_V2SI_type_node, NULL_TREE);
9273 tree v2sf_ftype_v2sf
9274 = build_function_type_list (opaque_V2SF_type_node,
9275 opaque_V2SF_type_node, NULL_TREE);
9277 tree v2sf_ftype_v2si
9278 = build_function_type_list (opaque_V2SF_type_node,
9279 opaque_V2SI_type_node, NULL_TREE);
9281 tree v2si_ftype_v2sf
9282 = build_function_type_list (opaque_V2SI_type_node,
9283 opaque_V2SF_type_node, NULL_TREE);
9285 tree v2si_ftype_v2si_char
9286 = build_function_type_list (opaque_V2SI_type_node,
9287 opaque_V2SI_type_node,
9288 char_type_node, NULL_TREE);
9290 tree v2si_ftype_int_char
9291 = build_function_type_list (opaque_V2SI_type_node,
9292 integer_type_node, char_type_node, NULL_TREE);
9294 tree v2si_ftype_char
9295 = build_function_type_list (opaque_V2SI_type_node,
9296 char_type_node, NULL_TREE);
9298 tree int_ftype_int_int
9299 = build_function_type_list (integer_type_node,
9300 integer_type_node, integer_type_node,
9303 tree opaque_ftype_opaque_opaque
9304 = build_function_type_list (opaque_V4SI_type_node,
9305 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9306 tree v4si_ftype_v4si_v4si
9307 = build_function_type_list (V4SI_type_node,
9308 V4SI_type_node, V4SI_type_node, NULL_TREE);
9309 tree v4sf_ftype_v4si_int
9310 = build_function_type_list (V4SF_type_node,
9311 V4SI_type_node, integer_type_node, NULL_TREE);
9312 tree v4si_ftype_v4sf_int
9313 = build_function_type_list (V4SI_type_node,
9314 V4SF_type_node, integer_type_node, NULL_TREE);
9315 tree v4si_ftype_v4si_int
9316 = build_function_type_list (V4SI_type_node,
9317 V4SI_type_node, integer_type_node, NULL_TREE);
9318 tree v8hi_ftype_v8hi_int
9319 = build_function_type_list (V8HI_type_node,
9320 V8HI_type_node, integer_type_node, NULL_TREE);
9321 tree v16qi_ftype_v16qi_int
9322 = build_function_type_list (V16QI_type_node,
9323 V16QI_type_node, integer_type_node, NULL_TREE);
9324 tree v16qi_ftype_v16qi_v16qi_int
9325 = build_function_type_list (V16QI_type_node,
9326 V16QI_type_node, V16QI_type_node,
9327 integer_type_node, NULL_TREE);
9328 tree v8hi_ftype_v8hi_v8hi_int
9329 = build_function_type_list (V8HI_type_node,
9330 V8HI_type_node, V8HI_type_node,
9331 integer_type_node, NULL_TREE);
9332 tree v4si_ftype_v4si_v4si_int
9333 = build_function_type_list (V4SI_type_node,
9334 V4SI_type_node, V4SI_type_node,
9335 integer_type_node, NULL_TREE);
9336 tree v4sf_ftype_v4sf_v4sf_int
9337 = build_function_type_list (V4SF_type_node,
9338 V4SF_type_node, V4SF_type_node,
9339 integer_type_node, NULL_TREE);
9340 tree v4sf_ftype_v4sf_v4sf
9341 = build_function_type_list (V4SF_type_node,
9342 V4SF_type_node, V4SF_type_node, NULL_TREE);
9343 tree opaque_ftype_opaque_opaque_opaque
9344 = build_function_type_list (opaque_V4SI_type_node,
9345 opaque_V4SI_type_node, opaque_V4SI_type_node,
9346 opaque_V4SI_type_node, NULL_TREE);
9347 tree v4sf_ftype_v4sf_v4sf_v4si
9348 = build_function_type_list (V4SF_type_node,
9349 V4SF_type_node, V4SF_type_node,
9350 V4SI_type_node, NULL_TREE);
9351 tree v4sf_ftype_v4sf_v4sf_v4sf
9352 = build_function_type_list (V4SF_type_node,
9353 V4SF_type_node, V4SF_type_node,
9354 V4SF_type_node, NULL_TREE);
9355 tree v4si_ftype_v4si_v4si_v4si
9356 = build_function_type_list (V4SI_type_node,
9357 V4SI_type_node, V4SI_type_node,
9358 V4SI_type_node, NULL_TREE);
9359 tree v8hi_ftype_v8hi_v8hi
9360 = build_function_type_list (V8HI_type_node,
9361 V8HI_type_node, V8HI_type_node, NULL_TREE);
9362 tree v8hi_ftype_v8hi_v8hi_v8hi
9363 = build_function_type_list (V8HI_type_node,
9364 V8HI_type_node, V8HI_type_node,
9365 V8HI_type_node, NULL_TREE);
9366 tree v4si_ftype_v8hi_v8hi_v4si
9367 = build_function_type_list (V4SI_type_node,
9368 V8HI_type_node, V8HI_type_node,
9369 V4SI_type_node, NULL_TREE);
9370 tree v4si_ftype_v16qi_v16qi_v4si
9371 = build_function_type_list (V4SI_type_node,
9372 V16QI_type_node, V16QI_type_node,
9373 V4SI_type_node, NULL_TREE);
9374 tree v16qi_ftype_v16qi_v16qi
9375 = build_function_type_list (V16QI_type_node,
9376 V16QI_type_node, V16QI_type_node, NULL_TREE);
9377 tree v4si_ftype_v4sf_v4sf
9378 = build_function_type_list (V4SI_type_node,
9379 V4SF_type_node, V4SF_type_node, NULL_TREE);
9380 tree v8hi_ftype_v16qi_v16qi
9381 = build_function_type_list (V8HI_type_node,
9382 V16QI_type_node, V16QI_type_node, NULL_TREE);
9383 tree v4si_ftype_v8hi_v8hi
9384 = build_function_type_list (V4SI_type_node,
9385 V8HI_type_node, V8HI_type_node, NULL_TREE);
9386 tree v8hi_ftype_v4si_v4si
9387 = build_function_type_list (V8HI_type_node,
9388 V4SI_type_node, V4SI_type_node, NULL_TREE);
9389 tree v16qi_ftype_v8hi_v8hi
9390 = build_function_type_list (V16QI_type_node,
9391 V8HI_type_node, V8HI_type_node, NULL_TREE);
9392 tree v4si_ftype_v16qi_v4si
9393 = build_function_type_list (V4SI_type_node,
9394 V16QI_type_node, V4SI_type_node, NULL_TREE);
9395 tree v4si_ftype_v16qi_v16qi
9396 = build_function_type_list (V4SI_type_node,
9397 V16QI_type_node, V16QI_type_node, NULL_TREE);
9398 tree v4si_ftype_v8hi_v4si
9399 = build_function_type_list (V4SI_type_node,
9400 V8HI_type_node, V4SI_type_node, NULL_TREE);
9401 tree v4si_ftype_v8hi
9402 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9403 tree int_ftype_v4si_v4si
9404 = build_function_type_list (integer_type_node,
9405 V4SI_type_node, V4SI_type_node, NULL_TREE);
9406 tree int_ftype_v4sf_v4sf
9407 = build_function_type_list (integer_type_node,
9408 V4SF_type_node, V4SF_type_node, NULL_TREE);
9409 tree int_ftype_v16qi_v16qi
9410 = build_function_type_list (integer_type_node,
9411 V16QI_type_node, V16QI_type_node, NULL_TREE);
9412 tree int_ftype_v8hi_v8hi
9413 = build_function_type_list (integer_type_node,
9414 V8HI_type_node, V8HI_type_node, NULL_TREE);
9416 /* Add the simple ternary operators. */
9417 d = (struct builtin_description *) bdesc_3arg;
9418 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9420 enum machine_mode mode0, mode1, mode2, mode3;
9422 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9423 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9434 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9437 mode0 = insn_data[d->icode].operand[0].mode;
9438 mode1 = insn_data[d->icode].operand[1].mode;
9439 mode2 = insn_data[d->icode].operand[2].mode;
9440 mode3 = insn_data[d->icode].operand[3].mode;
9443 /* When all four are of the same mode. */
9444 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9449 type = opaque_ftype_opaque_opaque_opaque;
9452 type = v4si_ftype_v4si_v4si_v4si;
9455 type = v4sf_ftype_v4sf_v4sf_v4sf;
9458 type = v8hi_ftype_v8hi_v8hi_v8hi;
9461 type = v16qi_ftype_v16qi_v16qi_v16qi;
9467 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9472 type = v4si_ftype_v4si_v4si_v16qi;
9475 type = v4sf_ftype_v4sf_v4sf_v16qi;
9478 type = v8hi_ftype_v8hi_v8hi_v16qi;
9481 type = v16qi_ftype_v16qi_v16qi_v16qi;
9487 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9488 && mode3 == V4SImode)
9489 type = v4si_ftype_v16qi_v16qi_v4si;
9490 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9491 && mode3 == V4SImode)
9492 type = v4si_ftype_v8hi_v8hi_v4si;
9493 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9494 && mode3 == V4SImode)
9495 type = v4sf_ftype_v4sf_v4sf_v4si;
9497 /* vchar, vchar, vchar, 4-bit literal. */
9498 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9500 type = v16qi_ftype_v16qi_v16qi_int;
9502 /* vshort, vshort, vshort, 4-bit literal. */
9503 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9505 type = v8hi_ftype_v8hi_v8hi_int;
9507 /* vint, vint, vint, 4-bit literal. */
9508 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9510 type = v4si_ftype_v4si_v4si_int;
9512 /* vfloat, vfloat, vfloat, 4-bit literal. */
9513 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9515 type = v4sf_ftype_v4sf_v4sf_int;
9520 def_builtin (d->mask, d->name, type, d->code);
9523 /* Add the simple binary operators. */
9524 d = (struct builtin_description *) bdesc_2arg;
9525 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9527 enum machine_mode mode0, mode1, mode2;
9529 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9530 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9540 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9543 mode0 = insn_data[d->icode].operand[0].mode;
9544 mode1 = insn_data[d->icode].operand[1].mode;
9545 mode2 = insn_data[d->icode].operand[2].mode;
9548 /* When all three operands are of the same mode. */
9549 if (mode0 == mode1 && mode1 == mode2)
9554 type = opaque_ftype_opaque_opaque;
9557 type = v4sf_ftype_v4sf_v4sf;
9560 type = v4si_ftype_v4si_v4si;
9563 type = v16qi_ftype_v16qi_v16qi;
9566 type = v8hi_ftype_v8hi_v8hi;
9569 type = v2si_ftype_v2si_v2si;
9572 type = v2sf_ftype_v2sf_v2sf;
9575 type = int_ftype_int_int;
9582 /* A few other combos we really don't want to do manually. */
9584 /* vint, vfloat, vfloat. */
9585 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9586 type = v4si_ftype_v4sf_v4sf;
9588 /* vshort, vchar, vchar. */
9589 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9590 type = v8hi_ftype_v16qi_v16qi;
9592 /* vint, vshort, vshort. */
9593 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9594 type = v4si_ftype_v8hi_v8hi;
9596 /* vshort, vint, vint. */
9597 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9598 type = v8hi_ftype_v4si_v4si;
9600 /* vchar, vshort, vshort. */
9601 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9602 type = v16qi_ftype_v8hi_v8hi;
9604 /* vint, vchar, vint. */
9605 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9606 type = v4si_ftype_v16qi_v4si;
9608 /* vint, vchar, vchar. */
9609 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9610 type = v4si_ftype_v16qi_v16qi;
9612 /* vint, vshort, vint. */
9613 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9614 type = v4si_ftype_v8hi_v4si;
9616 /* vint, vint, 5-bit literal. */
9617 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9618 type = v4si_ftype_v4si_int;
9620 /* vshort, vshort, 5-bit literal. */
9621 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9622 type = v8hi_ftype_v8hi_int;
9624 /* vchar, vchar, 5-bit literal. */
9625 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9626 type = v16qi_ftype_v16qi_int;
9628 /* vfloat, vint, 5-bit literal. */
9629 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9630 type = v4sf_ftype_v4si_int;
9632 /* vint, vfloat, 5-bit literal. */
9633 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9634 type = v4si_ftype_v4sf_int;
9636 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9637 type = v2si_ftype_int_int;
9639 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9640 type = v2si_ftype_v2si_char;
9642 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9643 type = v2si_ftype_int_char;
9648 gcc_assert (mode0 == SImode);
9652 type = int_ftype_v4si_v4si;
9655 type = int_ftype_v4sf_v4sf;
9658 type = int_ftype_v16qi_v16qi;
9661 type = int_ftype_v8hi_v8hi;
9668 def_builtin (d->mask, d->name, type, d->code);
9671 /* Add the simple unary operators. */
9672 d = (struct builtin_description *) bdesc_1arg;
9673 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9675 enum machine_mode mode0, mode1;
9677 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9678 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9687 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9690 mode0 = insn_data[d->icode].operand[0].mode;
9691 mode1 = insn_data[d->icode].operand[1].mode;
9694 if (mode0 == V4SImode && mode1 == QImode)
9695 type = v4si_ftype_int;
9696 else if (mode0 == V8HImode && mode1 == QImode)
9697 type = v8hi_ftype_int;
9698 else if (mode0 == V16QImode && mode1 == QImode)
9699 type = v16qi_ftype_int;
9700 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9701 type = opaque_ftype_opaque;
9702 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9703 type = v4sf_ftype_v4sf;
9704 else if (mode0 == V8HImode && mode1 == V16QImode)
9705 type = v8hi_ftype_v16qi;
9706 else if (mode0 == V4SImode && mode1 == V8HImode)
9707 type = v4si_ftype_v8hi;
9708 else if (mode0 == V2SImode && mode1 == V2SImode)
9709 type = v2si_ftype_v2si;
9710 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9711 type = v2sf_ftype_v2sf;
9712 else if (mode0 == V2SFmode && mode1 == V2SImode)
9713 type = v2sf_ftype_v2si;
9714 else if (mode0 == V2SImode && mode1 == V2SFmode)
9715 type = v2si_ftype_v2sf;
9716 else if (mode0 == V2SImode && mode1 == QImode)
9717 type = v2si_ftype_char;
9721 def_builtin (d->mask, d->name, type, d->code);
9726 rs6000_init_libfuncs (void)
9728 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9729 && !TARGET_POWER2 && !TARGET_POWERPC)
9731 /* AIX library routines for float->int conversion. */
9732 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9733 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9734 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9735 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9738 if (!TARGET_IEEEQUAD)
9739 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9740 if (!TARGET_XL_COMPAT)
9742 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9743 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9744 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9745 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9747 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9749 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9750 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9751 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9752 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9753 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9754 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9755 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9757 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9758 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9759 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9760 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9761 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9762 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9763 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9764 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9767 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
9768 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9772 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9773 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9774 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9775 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9779 /* 32-bit SVR4 quad floating point routines. */
9781 set_optab_libfunc (add_optab, TFmode, "_q_add");
9782 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9783 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9784 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9785 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9786 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9787 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9789 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9790 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9791 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9792 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9793 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9794 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9796 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9797 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9798 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9799 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9800 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9801 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9802 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9803 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9808 /* Expand a block clear operation, and return 1 if successful. Return 0
9809 if we should let the compiler generate normal code.
9811 operands[0] is the destination
9812 operands[1] is the length
9813 operands[3] is the alignment */
9816 expand_block_clear (rtx operands[])
9818 rtx orig_dest = operands[0];
9819 rtx bytes_rtx = operands[1];
9820 rtx align_rtx = operands[3];
9821 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9822 HOST_WIDE_INT align;
9823 HOST_WIDE_INT bytes;
9828 /* If this is not a fixed size move, just call memcpy */
9832 /* This must be a fixed size alignment */
9833 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9834 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9836 /* Anything to clear? */
9837 bytes = INTVAL (bytes_rtx);
9841 /* Use the builtin memset after a point, to avoid huge code bloat.
9842 When optimize_size, avoid any significant code bloat; calling
9843 memset is about 4 instructions, so allow for one instruction to
9844 load zero and three to do clearing. */
9845 if (TARGET_ALTIVEC && align >= 128)
9847 else if (TARGET_POWERPC64 && align >= 32)
9852 if (optimize_size && bytes > 3 * clear_step)
9854 if (! optimize_size && bytes > 8 * clear_step)
9857 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9859 enum machine_mode mode = BLKmode;
9862 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9867 else if (bytes >= 8 && TARGET_POWERPC64
9868 /* 64-bit loads and stores require word-aligned
9870 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9875 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9876 { /* move 4 bytes */
9880 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9881 { /* move 2 bytes */
9885 else /* move 1 byte at a time */
9891 dest = adjust_address (orig_dest, mode, offset);
9893 emit_move_insn (dest, CONST0_RTX (mode));
9900 /* Expand a block move operation, and return 1 if successful. Return 0
9901 if we should let the compiler generate normal code.
9903 operands[0] is the destination
9904 operands[1] is the source
9905 operands[2] is the length
9906 operands[3] is the alignment */
9908 #define MAX_MOVE_REG 4
9911 expand_block_move (rtx operands[])
9913 rtx orig_dest = operands[0];
9914 rtx orig_src = operands[1];
9915 rtx bytes_rtx = operands[2];
9916 rtx align_rtx = operands[3];
9917 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9922 rtx stores[MAX_MOVE_REG];
9925 /* If this is not a fixed size move, just call memcpy */
9929 /* This must be a fixed size alignment */
9930 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9931 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9933 /* Anything to move? */
9934 bytes = INTVAL (bytes_rtx);
9938 /* store_one_arg depends on expand_block_move to handle at least the size of
9939 reg_parm_stack_space. */
9940 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9943 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9946 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9947 rtx (*mov) (rtx, rtx);
9949 enum machine_mode mode = BLKmode;
9952 /* Altivec first, since it will be faster than a string move
9953 when it applies, and usually not significantly larger. */
9954 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9958 gen_func.mov = gen_movv4si;
9960 else if (TARGET_STRING
9961 && bytes > 24 /* move up to 32 bytes at a time */
9969 && ! fixed_regs[12])
9971 move_bytes = (bytes > 32) ? 32 : bytes;
9972 gen_func.movmemsi = gen_movmemsi_8reg;
9974 else if (TARGET_STRING
9975 && bytes > 16 /* move up to 24 bytes at a time */
9981 && ! fixed_regs[10])
9983 move_bytes = (bytes > 24) ? 24 : bytes;
9984 gen_func.movmemsi = gen_movmemsi_6reg;
9986 else if (TARGET_STRING
9987 && bytes > 8 /* move up to 16 bytes at a time */
9993 move_bytes = (bytes > 16) ? 16 : bytes;
9994 gen_func.movmemsi = gen_movmemsi_4reg;
9996 else if (bytes >= 8 && TARGET_POWERPC64
9997 /* 64-bit loads and stores require word-aligned
9999 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10003 gen_func.mov = gen_movdi;
10005 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10006 { /* move up to 8 bytes at a time */
10007 move_bytes = (bytes > 8) ? 8 : bytes;
10008 gen_func.movmemsi = gen_movmemsi_2reg;
10010 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10011 { /* move 4 bytes */
10014 gen_func.mov = gen_movsi;
10016 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10017 { /* move 2 bytes */
10020 gen_func.mov = gen_movhi;
10022 else if (TARGET_STRING && bytes > 1)
10023 { /* move up to 4 bytes at a time */
10024 move_bytes = (bytes > 4) ? 4 : bytes;
10025 gen_func.movmemsi = gen_movmemsi_1reg;
10027 else /* move 1 byte at a time */
10031 gen_func.mov = gen_movqi;
10034 src = adjust_address (orig_src, mode, offset);
10035 dest = adjust_address (orig_dest, mode, offset);
10037 if (mode != BLKmode)
10039 rtx tmp_reg = gen_reg_rtx (mode);
10041 emit_insn ((*gen_func.mov) (tmp_reg, src));
10042 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10045 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10048 for (i = 0; i < num_reg; i++)
10049 emit_insn (stores[i]);
10053 if (mode == BLKmode)
10055 /* Move the address into scratch registers. The movmemsi
10056 patterns require zero offset. */
10057 if (!REG_P (XEXP (src, 0)))
10059 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10060 src = replace_equiv_address (src, src_reg);
10062 set_mem_size (src, GEN_INT (move_bytes));
10064 if (!REG_P (XEXP (dest, 0)))
10066 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10067 dest = replace_equiv_address (dest, dest_reg);
10069 set_mem_size (dest, GEN_INT (move_bytes));
10071 emit_insn ((*gen_func.movmemsi) (dest, src,
10072 GEN_INT (move_bytes & 31),
10081 /* Return a string to perform a load_multiple operation.
10082 operands[0] is the vector.
10083 operands[1] is the source address.
10084 operands[2] is the first destination register. */
10087 rs6000_output_load_multiple (rtx operands[3])
10089 /* We have to handle the case where the pseudo used to contain the address
10090 is assigned to one of the output registers. */
10092 int words = XVECLEN (operands[0], 0);
10095 if (XVECLEN (operands[0], 0) == 1)
10096 return "{l|lwz} %2,0(%1)";
10098 for (i = 0; i < words; i++)
10099 if (refers_to_regno_p (REGNO (operands[2]) + i,
10100 REGNO (operands[2]) + i + 1, operands[1], 0))
10104 xop[0] = GEN_INT (4 * (words-1));
10105 xop[1] = operands[1];
10106 xop[2] = operands[2];
10107 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10112 xop[0] = GEN_INT (4 * (words-1));
10113 xop[1] = operands[1];
10114 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10115 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10120 for (j = 0; j < words; j++)
10123 xop[0] = GEN_INT (j * 4);
10124 xop[1] = operands[1];
10125 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10126 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10128 xop[0] = GEN_INT (i * 4);
10129 xop[1] = operands[1];
10130 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10135 return "{lsi|lswi} %2,%1,%N0";
10139 /* A validation routine: say whether CODE, a condition code, and MODE
10140 match. The other alternatives either don't make sense or should
10141 never be generated. */
10144 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10146 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10147 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10148 && GET_MODE_CLASS (mode) == MODE_CC);
10150 /* These don't make sense. */
10151 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10152 || mode != CCUNSmode);
10154 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10155 || mode == CCUNSmode);
10157 gcc_assert (mode == CCFPmode
10158 || (code != ORDERED && code != UNORDERED
10159 && code != UNEQ && code != LTGT
10160 && code != UNGT && code != UNLT
10161 && code != UNGE && code != UNLE));
10163 /* These should never be generated except for
10164 flag_finite_math_only. */
10165 gcc_assert (mode != CCFPmode
10166 || flag_finite_math_only
10167 || (code != LE && code != GE
10168 && code != UNEQ && code != LTGT
10169 && code != UNGT && code != UNLT));
10171 /* These are invalid; the information is not there. */
10172 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10176 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10177 mask required to convert the result of a rotate insn into a shift
10178 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10181 includes_lshift_p (rtx shiftop, rtx andop)
10183 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10185 shift_mask <<= INTVAL (shiftop);
10187 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10190 /* Similar, but for right shift. */
10193 includes_rshift_p (rtx shiftop, rtx andop)
10195 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10197 shift_mask >>= INTVAL (shiftop);
10199 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10202 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10203 to perform a left shift. It must have exactly SHIFTOP least
10204 significant 0's, then one or more 1's, then zero or more 0's. */
10207 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10209 if (GET_CODE (andop) == CONST_INT)
10211 HOST_WIDE_INT c, lsb, shift_mask;
10213 c = INTVAL (andop);
10214 if (c == 0 || c == ~0)
10218 shift_mask <<= INTVAL (shiftop);
10220 /* Find the least significant one bit. */
10223 /* It must coincide with the LSB of the shift mask. */
10224 if (-lsb != shift_mask)
10227 /* Invert to look for the next transition (if any). */
10230 /* Remove the low group of ones (originally low group of zeros). */
10233 /* Again find the lsb, and check we have all 1's above. */
10237 else if (GET_CODE (andop) == CONST_DOUBLE
10238 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10240 HOST_WIDE_INT low, high, lsb;
10241 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10243 low = CONST_DOUBLE_LOW (andop);
10244 if (HOST_BITS_PER_WIDE_INT < 64)
10245 high = CONST_DOUBLE_HIGH (andop);
10247 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10248 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10251 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10253 shift_mask_high = ~0;
10254 if (INTVAL (shiftop) > 32)
10255 shift_mask_high <<= INTVAL (shiftop) - 32;
10257 lsb = high & -high;
10259 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10265 lsb = high & -high;
10266 return high == -lsb;
10269 shift_mask_low = ~0;
10270 shift_mask_low <<= INTVAL (shiftop);
10274 if (-lsb != shift_mask_low)
10277 if (HOST_BITS_PER_WIDE_INT < 64)
10282 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10284 lsb = high & -high;
10285 return high == -lsb;
10289 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10295 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10296 to perform a left shift. It must have SHIFTOP or more least
10297 significant 0's, with the remainder of the word 1's. */
10300 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10302 if (GET_CODE (andop) == CONST_INT)
10304 HOST_WIDE_INT c, lsb, shift_mask;
10307 shift_mask <<= INTVAL (shiftop);
10308 c = INTVAL (andop);
10310 /* Find the least significant one bit. */
10313 /* It must be covered by the shift mask.
10314 This test also rejects c == 0. */
10315 if ((lsb & shift_mask) == 0)
10318 /* Check we have all 1's above the transition, and reject all 1's. */
10319 return c == -lsb && lsb != 1;
10321 else if (GET_CODE (andop) == CONST_DOUBLE
10322 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10324 HOST_WIDE_INT low, lsb, shift_mask_low;
10326 low = CONST_DOUBLE_LOW (andop);
10328 if (HOST_BITS_PER_WIDE_INT < 64)
10330 HOST_WIDE_INT high, shift_mask_high;
10332 high = CONST_DOUBLE_HIGH (andop);
10336 shift_mask_high = ~0;
10337 if (INTVAL (shiftop) > 32)
10338 shift_mask_high <<= INTVAL (shiftop) - 32;
10340 lsb = high & -high;
10342 if ((lsb & shift_mask_high) == 0)
10345 return high == -lsb;
10351 shift_mask_low = ~0;
10352 shift_mask_low <<= INTVAL (shiftop);
10356 if ((lsb & shift_mask_low) == 0)
10359 return low == -lsb && lsb != 1;
10365 /* Return 1 if operands will generate a valid arguments to rlwimi
10366 instruction for insert with right shift in 64-bit mode. The mask may
10367 not start on the first bit or stop on the last bit because wrap-around
10368 effects of instruction do not correspond to semantics of RTL insn. */
10371 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10373 if (INTVAL (startop) > 32
10374 && INTVAL (startop) < 64
10375 && INTVAL (sizeop) > 1
10376 && INTVAL (sizeop) + INTVAL (startop) < 64
10377 && INTVAL (shiftop) > 0
10378 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10379 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10385 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10386 for lfq and stfq insns iff the registers are hard registers. */
10389 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10391 /* We might have been passed a SUBREG. */
10392 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10395 /* We might have been passed non floating point registers. */
10396 if (!FP_REGNO_P (REGNO (reg1))
10397 || !FP_REGNO_P (REGNO (reg2)))
10400 return (REGNO (reg1) == REGNO (reg2) - 1);
10403 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10404 addr1 and addr2 must be in consecutive memory locations
10405 (addr2 == addr1 + 8). */
10408 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10411 unsigned int reg1, reg2;
10412 int offset1, offset2;
10414 /* The mems cannot be volatile. */
10415 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10418 addr1 = XEXP (mem1, 0);
10419 addr2 = XEXP (mem2, 0);
10421 /* Extract an offset (if used) from the first addr. */
10422 if (GET_CODE (addr1) == PLUS)
10424 /* If not a REG, return zero. */
10425 if (GET_CODE (XEXP (addr1, 0)) != REG)
10429 reg1 = REGNO (XEXP (addr1, 0));
10430 /* The offset must be constant! */
10431 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10433 offset1 = INTVAL (XEXP (addr1, 1));
10436 else if (GET_CODE (addr1) != REG)
10440 reg1 = REGNO (addr1);
10441 /* This was a simple (mem (reg)) expression. Offset is 0. */
10445 /* And now for the second addr. */
10446 if (GET_CODE (addr2) == PLUS)
10448 /* If not a REG, return zero. */
10449 if (GET_CODE (XEXP (addr2, 0)) != REG)
10453 reg2 = REGNO (XEXP (addr2, 0));
10454 /* The offset must be constant. */
10455 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10457 offset2 = INTVAL (XEXP (addr2, 1));
10460 else if (GET_CODE (addr2) != REG)
10464 reg2 = REGNO (addr2);
10465 /* This was a simple (mem (reg)) expression. Offset is 0. */
10469 /* Both of these must have the same base register. */
10473 /* The offset for the second addr must be 8 more than the first addr. */
10474 if (offset2 != offset1 + 8)
10477 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10482 /* Return the register class of a scratch register needed to copy IN into
10483 or out of a register in CLASS in MODE. If it can be done directly,
10484 NO_REGS is returned. */
10487 rs6000_secondary_reload_class (enum reg_class class,
10488 enum machine_mode mode ATTRIBUTE_UNUSED,
10493 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10495 && MACHOPIC_INDIRECT
10499 /* We cannot copy a symbolic operand directly into anything
10500 other than BASE_REGS for TARGET_ELF. So indicate that a
10501 register from BASE_REGS is needed as an intermediate
10504 On Darwin, pic addresses require a load from memory, which
10505 needs a base register. */
10506 if (class != BASE_REGS
10507 && (GET_CODE (in) == SYMBOL_REF
10508 || GET_CODE (in) == HIGH
10509 || GET_CODE (in) == LABEL_REF
10510 || GET_CODE (in) == CONST))
10514 if (GET_CODE (in) == REG)
10516 regno = REGNO (in);
10517 if (regno >= FIRST_PSEUDO_REGISTER)
10519 regno = true_regnum (in);
10520 if (regno >= FIRST_PSEUDO_REGISTER)
10524 else if (GET_CODE (in) == SUBREG)
10526 regno = true_regnum (in);
10527 if (regno >= FIRST_PSEUDO_REGISTER)
10533 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10535 if (class == GENERAL_REGS || class == BASE_REGS
10536 || (regno >= 0 && INT_REGNO_P (regno)))
10539 /* Constants, memory, and FP registers can go into FP registers. */
10540 if ((regno == -1 || FP_REGNO_P (regno))
10541 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10544 /* Memory, and AltiVec registers can go into AltiVec registers. */
10545 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10546 && class == ALTIVEC_REGS)
10549 /* We can copy among the CR registers. */
10550 if ((class == CR_REGS || class == CR0_REGS)
10551 && regno >= 0 && CR_REGNO_P (regno))
10554 /* Otherwise, we need GENERAL_REGS. */
10555 return GENERAL_REGS;
10558 /* Given a comparison operation, return the bit number in CCR to test. We
10559 know this is a valid comparison.
10561 SCC_P is 1 if this is for an scc. That means that %D will have been
10562 used instead of %C, so the bits will be in different places.
10564 Return -1 if OP isn't a valid comparison for some reason. */
10567 ccr_bit (rtx op, int scc_p)
10569 enum rtx_code code = GET_CODE (op);
10570 enum machine_mode cc_mode;
10575 if (!COMPARISON_P (op))
10578 reg = XEXP (op, 0);
10580 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10582 cc_mode = GET_MODE (reg);
10583 cc_regnum = REGNO (reg);
10584 base_bit = 4 * (cc_regnum - CR0_REGNO);
10586 validate_condition_mode (code, cc_mode);
10588 /* When generating a sCOND operation, only positive conditions are
10591 || code == EQ || code == GT || code == LT || code == UNORDERED
10592 || code == GTU || code == LTU);
10597 return scc_p ? base_bit + 3 : base_bit + 2;
10599 return base_bit + 2;
10600 case GT: case GTU: case UNLE:
10601 return base_bit + 1;
10602 case LT: case LTU: case UNGE:
10604 case ORDERED: case UNORDERED:
10605 return base_bit + 3;
10608 /* If scc, we will have done a cror to put the bit in the
10609 unordered position. So test that bit. For integer, this is ! LT
10610 unless this is an scc insn. */
10611 return scc_p ? base_bit + 3 : base_bit;
10614 return scc_p ? base_bit + 3 : base_bit + 1;
10617 gcc_unreachable ();
10621 /* Return the GOT register. */
10624 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10626 /* The second flow pass currently (June 1999) can't update
10627 regs_ever_live without disturbing other parts of the compiler, so
10628 update it here to make the prolog/epilogue code happy. */
10629 if (!can_create_pseudo_p ()
10630 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
10631 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
10633 current_function_uses_pic_offset_table = 1;
10635 return pic_offset_table_rtx;
10638 /* Function to init struct machine_function.
10639 This will be called, via a pointer variable,
10640 from push_function_context. */
10642 static struct machine_function *
10643 rs6000_init_machine_status (void)
10645 return ggc_alloc_cleared (sizeof (machine_function));
10648 /* These macros test for integers and extract the low-order bits. */
10650 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10651 && GET_MODE (X) == VOIDmode)
10653 #define INT_LOWPART(X) \
10654 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10657 extract_MB (rtx op)
10660 unsigned long val = INT_LOWPART (op);
10662 /* If the high bit is zero, the value is the first 1 bit we find
10664 if ((val & 0x80000000) == 0)
10666 gcc_assert (val & 0xffffffff);
10669 while (((val <<= 1) & 0x80000000) == 0)
10674 /* If the high bit is set and the low bit is not, or the mask is all
10675 1's, the value is zero. */
10676 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10679 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10682 while (((val >>= 1) & 1) != 0)
10689 extract_ME (rtx op)
10692 unsigned long val = INT_LOWPART (op);
10694 /* If the low bit is zero, the value is the first 1 bit we find from
10696 if ((val & 1) == 0)
10698 gcc_assert (val & 0xffffffff);
10701 while (((val >>= 1) & 1) == 0)
10707 /* If the low bit is set and the high bit is not, or the mask is all
10708 1's, the value is 31. */
10709 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10712 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10715 while (((val <<= 1) & 0x80000000) != 0)
10721 /* Locate some local-dynamic symbol still in use by this function
10722 so that we can print its name in some tls_ld pattern. */
10724 static const char *
10725 rs6000_get_some_local_dynamic_name (void)
10729 if (cfun->machine->some_ld_name)
10730 return cfun->machine->some_ld_name;
10732 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10734 && for_each_rtx (&PATTERN (insn),
10735 rs6000_get_some_local_dynamic_name_1, 0))
10736 return cfun->machine->some_ld_name;
10738 gcc_unreachable ();
10741 /* Helper function for rs6000_get_some_local_dynamic_name. */
10744 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10748 if (GET_CODE (x) == SYMBOL_REF)
10750 const char *str = XSTR (x, 0);
10751 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10753 cfun->machine->some_ld_name = str;
10761 /* Write out a function code label. */
10764 rs6000_output_function_entry (FILE *file, const char *fname)
10766 if (fname[0] != '.')
10768 switch (DEFAULT_ABI)
10771 gcc_unreachable ();
10777 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10786 RS6000_OUTPUT_BASENAME (file, fname);
10788 assemble_name (file, fname);
10791 /* Print an operand. Recognize special options, documented below. */
10794 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10795 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10797 #define SMALL_DATA_RELOC "sda21"
10798 #define SMALL_DATA_REG 0
10802 print_operand (FILE *file, rtx x, int code)
10806 unsigned HOST_WIDE_INT uval;
10811 /* Write out an instruction after the call which may be replaced
10812 with glue code by the loader. This depends on the AIX version. */
10813 asm_fprintf (file, RS6000_CALL_GLUE);
10816 /* %a is output_address. */
10819 /* If X is a constant integer whose low-order 5 bits are zero,
10820 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10821 in the AIX assembler where "sri" with a zero shift count
10822 writes a trash instruction. */
10823 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10830 /* If constant, low-order 16 bits of constant, unsigned.
10831 Otherwise, write normally. */
10833 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10835 print_operand (file, x, 0);
10839 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10840 for 64-bit mask direction. */
10841 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10844 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10848 /* X is a CR register. Print the number of the GT bit of the CR. */
10849 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10850 output_operand_lossage ("invalid %%E value");
10852 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10856 /* Like 'J' but get to the GT bit only. */
10857 gcc_assert (GET_CODE (x) == REG);
10859 /* Bit 1 is GT bit. */
10860 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10862 /* Add one for shift count in rlinm for scc. */
10863 fprintf (file, "%d", i + 1);
10867 /* X is a CR register. Print the number of the EQ bit of the CR */
10868 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10869 output_operand_lossage ("invalid %%E value");
10871 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10875 /* X is a CR register. Print the shift count needed to move it
10876 to the high-order four bits. */
10877 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10878 output_operand_lossage ("invalid %%f value");
10880 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10884 /* Similar, but print the count for the rotate in the opposite
10886 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10887 output_operand_lossage ("invalid %%F value");
10889 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10893 /* X is a constant integer. If it is negative, print "m",
10894 otherwise print "z". This is to make an aze or ame insn. */
10895 if (GET_CODE (x) != CONST_INT)
10896 output_operand_lossage ("invalid %%G value");
10897 else if (INTVAL (x) >= 0)
10904 /* If constant, output low-order five bits. Otherwise, write
10907 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10909 print_operand (file, x, 0);
10913 /* If constant, output low-order six bits. Otherwise, write
10916 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10918 print_operand (file, x, 0);
10922 /* Print `i' if this is a constant, else nothing. */
10928 /* Write the bit number in CCR for jump. */
10929 i = ccr_bit (x, 0);
10931 output_operand_lossage ("invalid %%j code");
10933 fprintf (file, "%d", i);
10937 /* Similar, but add one for shift count in rlinm for scc and pass
10938 scc flag to `ccr_bit'. */
10939 i = ccr_bit (x, 1);
10941 output_operand_lossage ("invalid %%J code");
10943 /* If we want bit 31, write a shift count of zero, not 32. */
10944 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10948 /* X must be a constant. Write the 1's complement of the
10951 output_operand_lossage ("invalid %%k value");
10953 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10957 /* X must be a symbolic constant on ELF. Write an
10958 expression suitable for an 'addi' that adds in the low 16
10959 bits of the MEM. */
10960 if (GET_CODE (x) != CONST)
10962 print_operand_address (file, x);
10963 fputs ("@l", file);
10967 if (GET_CODE (XEXP (x, 0)) != PLUS
10968 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10969 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10970 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10971 output_operand_lossage ("invalid %%K value");
10972 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10973 fputs ("@l", file);
10974 /* For GNU as, there must be a non-alphanumeric character
10975 between 'l' and the number. The '-' is added by
10976 print_operand() already. */
10977 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10979 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10983 /* %l is output_asm_label. */
10986 /* Write second word of DImode or DFmode reference. Works on register
10987 or non-indexed memory only. */
10988 if (GET_CODE (x) == REG)
10989 fputs (reg_names[REGNO (x) + 1], file);
10990 else if (GET_CODE (x) == MEM)
10992 /* Handle possible auto-increment. Since it is pre-increment and
10993 we have already done it, we can just use an offset of word. */
10994 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10995 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10996 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10998 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
10999 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11002 output_address (XEXP (adjust_address_nv (x, SImode,
11006 if (small_data_operand (x, GET_MODE (x)))
11007 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11008 reg_names[SMALL_DATA_REG]);
11013 /* MB value for a mask operand. */
11014 if (! mask_operand (x, SImode))
11015 output_operand_lossage ("invalid %%m value");
11017 fprintf (file, "%d", extract_MB (x));
11021 /* ME value for a mask operand. */
11022 if (! mask_operand (x, SImode))
11023 output_operand_lossage ("invalid %%M value");
11025 fprintf (file, "%d", extract_ME (x));
11028 /* %n outputs the negative of its operand. */
11031 /* Write the number of elements in the vector times 4. */
11032 if (GET_CODE (x) != PARALLEL)
11033 output_operand_lossage ("invalid %%N value");
11035 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11039 /* Similar, but subtract 1 first. */
11040 if (GET_CODE (x) != PARALLEL)
11041 output_operand_lossage ("invalid %%O value");
11043 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11047 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11049 || INT_LOWPART (x) < 0
11050 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11051 output_operand_lossage ("invalid %%p value");
11053 fprintf (file, "%d", i);
11057 /* The operand must be an indirect memory reference. The result
11058 is the register name. */
11059 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11060 || REGNO (XEXP (x, 0)) >= 32)
11061 output_operand_lossage ("invalid %%P value");
11063 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11067 /* This outputs the logical code corresponding to a boolean
11068 expression. The expression may have one or both operands
11069 negated (if one, only the first one). For condition register
11070 logical operations, it will also treat the negated
11071 CR codes as NOTs, but not handle NOTs of them. */
11073 const char *const *t = 0;
11075 enum rtx_code code = GET_CODE (x);
11076 static const char * const tbl[3][3] = {
11077 { "and", "andc", "nor" },
11078 { "or", "orc", "nand" },
11079 { "xor", "eqv", "xor" } };
11083 else if (code == IOR)
11085 else if (code == XOR)
11088 output_operand_lossage ("invalid %%q value");
11090 if (GET_CODE (XEXP (x, 0)) != NOT)
11094 if (GET_CODE (XEXP (x, 1)) == NOT)
11112 /* X is a CR register. Print the mask for `mtcrf'. */
11113 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11114 output_operand_lossage ("invalid %%R value");
11116 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11120 /* Low 5 bits of 32 - value */
11122 output_operand_lossage ("invalid %%s value");
11124 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11128 /* PowerPC64 mask position. All 0's is excluded.
11129 CONST_INT 32-bit mask is considered sign-extended so any
11130 transition must occur within the CONST_INT, not on the boundary. */
11131 if (! mask64_operand (x, DImode))
11132 output_operand_lossage ("invalid %%S value");
11134 uval = INT_LOWPART (x);
11136 if (uval & 1) /* Clear Left */
11138 #if HOST_BITS_PER_WIDE_INT > 64
11139 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11143 else /* Clear Right */
11146 #if HOST_BITS_PER_WIDE_INT > 64
11147 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11153 gcc_assert (i >= 0);
11154 fprintf (file, "%d", i);
11158 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11159 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11161 /* Bit 3 is OV bit. */
11162 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11164 /* If we want bit 31, write a shift count of zero, not 32. */
11165 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11169 /* Print the symbolic name of a branch target register. */
11170 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11171 && REGNO (x) != CTR_REGNO))
11172 output_operand_lossage ("invalid %%T value");
11173 else if (REGNO (x) == LR_REGNO)
11174 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11176 fputs ("ctr", file);
11180 /* High-order 16 bits of constant for use in unsigned operand. */
11182 output_operand_lossage ("invalid %%u value");
11184 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11185 (INT_LOWPART (x) >> 16) & 0xffff);
11189 /* High-order 16 bits of constant for use in signed operand. */
11191 output_operand_lossage ("invalid %%v value");
11193 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11194 (INT_LOWPART (x) >> 16) & 0xffff);
11198 /* Print `u' if this has an auto-increment or auto-decrement. */
11199 if (GET_CODE (x) == MEM
11200 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11201 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11202 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11207 /* Print the trap code for this operand. */
11208 switch (GET_CODE (x))
11211 fputs ("eq", file); /* 4 */
11214 fputs ("ne", file); /* 24 */
11217 fputs ("lt", file); /* 16 */
11220 fputs ("le", file); /* 20 */
11223 fputs ("gt", file); /* 8 */
11226 fputs ("ge", file); /* 12 */
11229 fputs ("llt", file); /* 2 */
11232 fputs ("lle", file); /* 6 */
11235 fputs ("lgt", file); /* 1 */
11238 fputs ("lge", file); /* 5 */
11241 gcc_unreachable ();
11246 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11249 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11250 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11252 print_operand (file, x, 0);
11256 /* MB value for a PowerPC64 rldic operand. */
11257 val = (GET_CODE (x) == CONST_INT
11258 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11263 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11264 if ((val <<= 1) < 0)
11267 #if HOST_BITS_PER_WIDE_INT == 32
11268 if (GET_CODE (x) == CONST_INT && i >= 0)
11269 i += 32; /* zero-extend high-part was all 0's */
11270 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11272 val = CONST_DOUBLE_LOW (x);
11278 for ( ; i < 64; i++)
11279 if ((val <<= 1) < 0)
11284 fprintf (file, "%d", i + 1);
11288 if (GET_CODE (x) == MEM
11289 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11290 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11291 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11296 /* Like 'L', for third word of TImode */
11297 if (GET_CODE (x) == REG)
11298 fputs (reg_names[REGNO (x) + 2], file);
11299 else if (GET_CODE (x) == MEM)
11301 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11302 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11303 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11304 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11305 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11307 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11308 if (small_data_operand (x, GET_MODE (x)))
11309 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11310 reg_names[SMALL_DATA_REG]);
11315 /* X is a SYMBOL_REF. Write out the name preceded by a
11316 period and without any trailing data in brackets. Used for function
11317 names. If we are configured for System V (or the embedded ABI) on
11318 the PowerPC, do not emit the period, since those systems do not use
11319 TOCs and the like. */
11320 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11322 /* Mark the decl as referenced so that cgraph will output the
11324 if (SYMBOL_REF_DECL (x))
11325 mark_decl_referenced (SYMBOL_REF_DECL (x));
11327 /* For macho, check to see if we need a stub. */
11330 const char *name = XSTR (x, 0);
11332 if (MACHOPIC_INDIRECT
11333 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11334 name = machopic_indirection_name (x, /*stub_p=*/true);
11336 assemble_name (file, name);
11338 else if (!DOT_SYMBOLS)
11339 assemble_name (file, XSTR (x, 0));
11341 rs6000_output_function_entry (file, XSTR (x, 0));
11345 /* Like 'L', for last word of TImode. */
11346 if (GET_CODE (x) == REG)
11347 fputs (reg_names[REGNO (x) + 3], file);
11348 else if (GET_CODE (x) == MEM)
11350 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11351 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11352 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11353 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11354 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11356 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11357 if (small_data_operand (x, GET_MODE (x)))
11358 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11359 reg_names[SMALL_DATA_REG]);
11363 /* Print AltiVec or SPE memory operand. */
11368 gcc_assert (GET_CODE (x) == MEM);
11372 /* Ugly hack because %y is overloaded. */
11373 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11374 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11375 || GET_MODE (x) == TFmode
11376 || GET_MODE (x) == TImode))
11378 /* Handle [reg]. */
11379 if (GET_CODE (tmp) == REG)
11381 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11384 /* Handle [reg+UIMM]. */
11385 else if (GET_CODE (tmp) == PLUS &&
11386 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11390 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11392 x = INTVAL (XEXP (tmp, 1));
11393 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11397 /* Fall through. Must be [reg+reg]. */
11400 && GET_CODE (tmp) == AND
11401 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11402 && INTVAL (XEXP (tmp, 1)) == -16)
11403 tmp = XEXP (tmp, 0);
11404 if (GET_CODE (tmp) == REG)
11405 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11408 gcc_assert (GET_CODE (tmp) == PLUS
11409 && REG_P (XEXP (tmp, 0))
11410 && REG_P (XEXP (tmp, 1)));
11412 if (REGNO (XEXP (tmp, 0)) == 0)
11413 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11414 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11416 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11417 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11423 if (GET_CODE (x) == REG)
11424 fprintf (file, "%s", reg_names[REGNO (x)]);
11425 else if (GET_CODE (x) == MEM)
11427 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11428 know the width from the mode. */
11429 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11430 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11431 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11432 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11433 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11434 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11435 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11436 output_address (XEXP (XEXP (x, 0), 1));
11438 output_address (XEXP (x, 0));
11441 output_addr_const (file, x);
11445 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11449 output_operand_lossage ("invalid %%xn code");
11453 /* Print the address of an operand. */
11456 print_operand_address (FILE *file, rtx x)
11458 if (GET_CODE (x) == REG)
11459 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11460 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11461 || GET_CODE (x) == LABEL_REF)
11463 output_addr_const (file, x);
11464 if (small_data_operand (x, GET_MODE (x)))
11465 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11466 reg_names[SMALL_DATA_REG]);
11468 gcc_assert (!TARGET_TOC);
11470 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11472 gcc_assert (REG_P (XEXP (x, 0)));
11473 if (REGNO (XEXP (x, 0)) == 0)
11474 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11475 reg_names[ REGNO (XEXP (x, 0)) ]);
11477 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11478 reg_names[ REGNO (XEXP (x, 1)) ]);
11480 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11481 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11482 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11484 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11485 && CONSTANT_P (XEXP (x, 1)))
11487 output_addr_const (file, XEXP (x, 1));
11488 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11492 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11493 && CONSTANT_P (XEXP (x, 1)))
11495 fprintf (file, "lo16(");
11496 output_addr_const (file, XEXP (x, 1));
11497 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11500 else if (legitimate_constant_pool_address_p (x))
11502 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11504 rtx contains_minus = XEXP (x, 1);
11508 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11509 turn it into (sym) for output_addr_const. */
11510 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11511 contains_minus = XEXP (contains_minus, 0);
11513 minus = XEXP (contains_minus, 0);
11514 symref = XEXP (minus, 0);
11515 XEXP (contains_minus, 0) = symref;
11520 name = XSTR (symref, 0);
11521 newname = alloca (strlen (name) + sizeof ("@toc"));
11522 strcpy (newname, name);
11523 strcat (newname, "@toc");
11524 XSTR (symref, 0) = newname;
11526 output_addr_const (file, XEXP (x, 1));
11528 XSTR (symref, 0) = name;
11529 XEXP (contains_minus, 0) = minus;
11532 output_addr_const (file, XEXP (x, 1));
11534 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11537 gcc_unreachable ();
11540 /* Target hook for assembling integer objects. The PowerPC version has
11541 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11542 is defined. It also needs to handle DI-mode objects on 64-bit
11546 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11548 #ifdef RELOCATABLE_NEEDS_FIXUP
11549 /* Special handling for SI values. */
11550 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11552 static int recurse = 0;
11554 /* For -mrelocatable, we mark all addresses that need to be fixed up
11555 in the .fixup section. */
11556 if (TARGET_RELOCATABLE
11557 && in_section != toc_section
11558 && in_section != text_section
11559 && !unlikely_text_section_p (in_section)
11561 && GET_CODE (x) != CONST_INT
11562 && GET_CODE (x) != CONST_DOUBLE
11568 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11570 ASM_OUTPUT_LABEL (asm_out_file, buf);
11571 fprintf (asm_out_file, "\t.long\t(");
11572 output_addr_const (asm_out_file, x);
11573 fprintf (asm_out_file, ")@fixup\n");
11574 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11575 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11576 fprintf (asm_out_file, "\t.long\t");
11577 assemble_name (asm_out_file, buf);
11578 fprintf (asm_out_file, "\n\t.previous\n");
11582 /* Remove initial .'s to turn a -mcall-aixdesc function
11583 address into the address of the descriptor, not the function
11585 else if (GET_CODE (x) == SYMBOL_REF
11586 && XSTR (x, 0)[0] == '.'
11587 && DEFAULT_ABI == ABI_AIX)
11589 const char *name = XSTR (x, 0);
11590 while (*name == '.')
11593 fprintf (asm_out_file, "\t.long\t%s\n", name);
11597 #endif /* RELOCATABLE_NEEDS_FIXUP */
11598 return default_assemble_integer (x, size, aligned_p);
11601 #ifdef HAVE_GAS_HIDDEN
11602 /* Emit an assembler directive to set symbol visibility for DECL to
11603 VISIBILITY_TYPE. */
11606 rs6000_assemble_visibility (tree decl, int vis)
11608 /* Functions need to have their entry point symbol visibility set as
11609 well as their descriptor symbol visibility. */
11610 if (DEFAULT_ABI == ABI_AIX
11612 && TREE_CODE (decl) == FUNCTION_DECL)
11614 static const char * const visibility_types[] = {
11615 NULL, "internal", "hidden", "protected"
11618 const char *name, *type;
11620 name = ((* targetm.strip_name_encoding)
11621 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11622 type = visibility_types[vis];
11624 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11625 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11628 default_assemble_visibility (decl, vis);
11633 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11635 /* Reversal of FP compares takes care -- an ordered compare
11636 becomes an unordered compare and vice versa. */
11637 if (mode == CCFPmode
11638 && (!flag_finite_math_only
11639 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11640 || code == UNEQ || code == LTGT))
11641 return reverse_condition_maybe_unordered (code);
11643 return reverse_condition (code);
11646 /* Generate a compare for CODE. Return a brand-new rtx that
11647 represents the result of the compare. */
11650 rs6000_generate_compare (enum rtx_code code)
11652 enum machine_mode comp_mode;
11653 rtx compare_result;
11655 if (rs6000_compare_fp_p)
11656 comp_mode = CCFPmode;
11657 else if (code == GTU || code == LTU
11658 || code == GEU || code == LEU)
11659 comp_mode = CCUNSmode;
11660 else if ((code == EQ || code == NE)
11661 && GET_CODE (rs6000_compare_op0) == SUBREG
11662 && GET_CODE (rs6000_compare_op1) == SUBREG
11663 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11664 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11665 /* These are unsigned values, perhaps there will be a later
11666 ordering compare that can be shared with this one.
11667 Unfortunately we cannot detect the signedness of the operands
11668 for non-subregs. */
11669 comp_mode = CCUNSmode;
11671 comp_mode = CCmode;
11673 /* First, the compare. */
11674 compare_result = gen_reg_rtx (comp_mode);
11676 /* E500 FP compare instructions on the GPRs. Yuck! */
11677 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11678 && rs6000_compare_fp_p)
11680 rtx cmp, or_result, compare_result2;
11681 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11683 if (op_mode == VOIDmode)
11684 op_mode = GET_MODE (rs6000_compare_op1);
11686 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11687 This explains the following mess. */
11691 case EQ: case UNEQ: case NE: case LTGT:
11695 cmp = flag_unsafe_math_optimizations
11696 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11697 rs6000_compare_op1)
11698 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11699 rs6000_compare_op1);
11703 cmp = flag_unsafe_math_optimizations
11704 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11705 rs6000_compare_op1)
11706 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11707 rs6000_compare_op1);
11711 cmp = flag_unsafe_math_optimizations
11712 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11713 rs6000_compare_op1)
11714 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11715 rs6000_compare_op1);
11719 gcc_unreachable ();
11723 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11727 cmp = flag_unsafe_math_optimizations
11728 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11729 rs6000_compare_op1)
11730 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11731 rs6000_compare_op1);
11735 cmp = flag_unsafe_math_optimizations
11736 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11737 rs6000_compare_op1)
11738 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11739 rs6000_compare_op1);
11743 cmp = flag_unsafe_math_optimizations
11744 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11745 rs6000_compare_op1)
11746 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11747 rs6000_compare_op1);
11751 gcc_unreachable ();
11755 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11759 cmp = flag_unsafe_math_optimizations
11760 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11761 rs6000_compare_op1)
11762 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11763 rs6000_compare_op1);
11767 cmp = flag_unsafe_math_optimizations
11768 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11769 rs6000_compare_op1)
11770 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11771 rs6000_compare_op1);
11775 cmp = flag_unsafe_math_optimizations
11776 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11777 rs6000_compare_op1)
11778 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11779 rs6000_compare_op1);
11783 gcc_unreachable ();
11787 gcc_unreachable ();
11790 /* Synthesize LE and GE from LT/GT || EQ. */
11791 if (code == LE || code == GE || code == LEU || code == GEU)
11797 case LE: code = LT; break;
11798 case GE: code = GT; break;
11799 case LEU: code = LT; break;
11800 case GEU: code = GT; break;
11801 default: gcc_unreachable ();
11804 compare_result2 = gen_reg_rtx (CCFPmode);
11810 cmp = flag_unsafe_math_optimizations
11811 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11812 rs6000_compare_op1)
11813 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11814 rs6000_compare_op1);
11818 cmp = flag_unsafe_math_optimizations
11819 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11820 rs6000_compare_op1)
11821 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11822 rs6000_compare_op1);
11826 cmp = flag_unsafe_math_optimizations
11827 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11828 rs6000_compare_op1)
11829 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11830 rs6000_compare_op1);
11834 gcc_unreachable ();
11838 /* OR them together. */
11839 or_result = gen_reg_rtx (CCFPmode);
11840 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11842 compare_result = or_result;
11847 if (code == NE || code == LTGT)
11857 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11858 CLOBBERs to match cmptf_internal2 pattern. */
11859 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11860 && GET_MODE (rs6000_compare_op0) == TFmode
11861 && !TARGET_IEEEQUAD
11862 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11863 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11865 gen_rtx_SET (VOIDmode,
11867 gen_rtx_COMPARE (comp_mode,
11868 rs6000_compare_op0,
11869 rs6000_compare_op1)),
11870 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11871 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11872 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11873 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11874 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11875 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11876 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11877 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11878 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11879 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11881 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11882 comp_mode = CCEQmode;
11883 compare_result = gen_reg_rtx (CCEQmode);
11885 emit_insn (gen_stack_protect_testdi (compare_result,
11886 rs6000_compare_op0, op1));
11888 emit_insn (gen_stack_protect_testsi (compare_result,
11889 rs6000_compare_op0, op1));
11892 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11893 gen_rtx_COMPARE (comp_mode,
11894 rs6000_compare_op0,
11895 rs6000_compare_op1)));
11898 /* Some kinds of FP comparisons need an OR operation;
11899 under flag_finite_math_only we don't bother. */
11900 if (rs6000_compare_fp_p
11901 && !flag_finite_math_only
11902 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11903 && (code == LE || code == GE
11904 || code == UNEQ || code == LTGT
11905 || code == UNGT || code == UNLT))
11907 enum rtx_code or1, or2;
11908 rtx or1_rtx, or2_rtx, compare2_rtx;
11909 rtx or_result = gen_reg_rtx (CCEQmode);
11913 case LE: or1 = LT; or2 = EQ; break;
11914 case GE: or1 = GT; or2 = EQ; break;
11915 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11916 case LTGT: or1 = LT; or2 = GT; break;
11917 case UNGT: or1 = UNORDERED; or2 = GT; break;
11918 case UNLT: or1 = UNORDERED; or2 = LT; break;
11919 default: gcc_unreachable ();
11921 validate_condition_mode (or1, comp_mode);
11922 validate_condition_mode (or2, comp_mode);
11923 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11924 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11925 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11926 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11928 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11930 compare_result = or_result;
11934 validate_condition_mode (code, GET_MODE (compare_result));
11936 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11940 /* Emit the RTL for an sCOND pattern. */
11943 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11946 enum machine_mode op_mode;
11947 enum rtx_code cond_code;
11949 condition_rtx = rs6000_generate_compare (code);
11950 cond_code = GET_CODE (condition_rtx);
11952 if (rs6000_compare_fp_p
11953 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11957 PUT_MODE (condition_rtx, SImode);
11958 t = XEXP (condition_rtx, 0);
11960 gcc_assert (cond_code == NE || cond_code == EQ);
11962 if (cond_code == NE)
11963 emit_insn (gen_e500_flip_gt_bit (t, t));
11965 emit_insn (gen_move_from_CR_gt_bit (result, t));
11969 if (cond_code == NE
11970 || cond_code == GE || cond_code == LE
11971 || cond_code == GEU || cond_code == LEU
11972 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11974 rtx not_result = gen_reg_rtx (CCEQmode);
11975 rtx not_op, rev_cond_rtx;
11976 enum machine_mode cc_mode;
11978 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11980 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11981 SImode, XEXP (condition_rtx, 0), const0_rtx);
11982 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11983 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11984 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11987 op_mode = GET_MODE (rs6000_compare_op0);
11988 if (op_mode == VOIDmode)
11989 op_mode = GET_MODE (rs6000_compare_op1);
11991 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11993 PUT_MODE (condition_rtx, DImode);
11994 convert_move (result, condition_rtx, 0);
11998 PUT_MODE (condition_rtx, SImode);
11999 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12003 /* Emit a branch of kind CODE to location LOC. */
12006 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12008 rtx condition_rtx, loc_ref;
12010 condition_rtx = rs6000_generate_compare (code);
12011 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12012 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12013 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12014 loc_ref, pc_rtx)));
12017 /* Return the string to output a conditional branch to LABEL, which is
12018 the operand number of the label, or -1 if the branch is really a
12019 conditional return.
12021 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12022 condition code register and its mode specifies what kind of
12023 comparison we made.
12025 REVERSED is nonzero if we should reverse the sense of the comparison.
12027 INSN is the insn. */
12030 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12032 static char string[64];
12033 enum rtx_code code = GET_CODE (op);
12034 rtx cc_reg = XEXP (op, 0);
12035 enum machine_mode mode = GET_MODE (cc_reg);
12036 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12037 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12038 int really_reversed = reversed ^ need_longbranch;
12044 validate_condition_mode (code, mode);
12046 /* Work out which way this really branches. We could use
12047 reverse_condition_maybe_unordered here always but this
12048 makes the resulting assembler clearer. */
12049 if (really_reversed)
12051 /* Reversal of FP compares takes care -- an ordered compare
12052 becomes an unordered compare and vice versa. */
12053 if (mode == CCFPmode)
12054 code = reverse_condition_maybe_unordered (code);
12056 code = reverse_condition (code);
12059 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12061 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12066 /* Opposite of GT. */
12075 gcc_unreachable ();
12081 /* Not all of these are actually distinct opcodes, but
12082 we distinguish them for clarity of the resulting assembler. */
12083 case NE: case LTGT:
12084 ccode = "ne"; break;
12085 case EQ: case UNEQ:
12086 ccode = "eq"; break;
12088 ccode = "ge"; break;
12089 case GT: case GTU: case UNGT:
12090 ccode = "gt"; break;
12092 ccode = "le"; break;
12093 case LT: case LTU: case UNLT:
12094 ccode = "lt"; break;
12095 case UNORDERED: ccode = "un"; break;
12096 case ORDERED: ccode = "nu"; break;
12097 case UNGE: ccode = "nl"; break;
12098 case UNLE: ccode = "ng"; break;
12100 gcc_unreachable ();
12103 /* Maybe we have a guess as to how likely the branch is.
12104 The old mnemonics don't have a way to specify this information. */
12106 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12107 if (note != NULL_RTX)
12109 /* PROB is the difference from 50%. */
12110 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12112 /* Only hint for highly probable/improbable branches on newer
12113 cpus as static prediction overrides processor dynamic
12114 prediction. For older cpus we may as well always hint, but
12115 assume not taken for branches that are very close to 50% as a
12116 mispredicted taken branch is more expensive than a
12117 mispredicted not-taken branch. */
12118 if (rs6000_always_hint
12119 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12120 && br_prob_note_reliable_p (note)))
12122 if (abs (prob) > REG_BR_PROB_BASE / 20
12123 && ((prob > 0) ^ need_longbranch))
12131 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12133 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12135 /* We need to escape any '%' characters in the reg_names string.
12136 Assume they'd only be the first character.... */
12137 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12139 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12143 /* If the branch distance was too far, we may have to use an
12144 unconditional branch to go the distance. */
12145 if (need_longbranch)
12146 s += sprintf (s, ",$+8\n\tb %s", label);
12148 s += sprintf (s, ",%s", label);
12154 /* Return the string to flip the GT bit on a CR. */
12156 output_e500_flip_gt_bit (rtx dst, rtx src)
12158 static char string[64];
12161 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12162 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12165 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12166 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12168 sprintf (string, "crnot %d,%d", a, b);
12172 /* Return insn index for the vector compare instruction for given CODE,
12173 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12177 get_vec_cmp_insn (enum rtx_code code,
12178 enum machine_mode dest_mode,
12179 enum machine_mode op_mode)
12181 if (!TARGET_ALTIVEC)
12182 return INSN_NOT_AVAILABLE;
12187 if (dest_mode == V16QImode && op_mode == V16QImode)
12188 return UNSPEC_VCMPEQUB;
12189 if (dest_mode == V8HImode && op_mode == V8HImode)
12190 return UNSPEC_VCMPEQUH;
12191 if (dest_mode == V4SImode && op_mode == V4SImode)
12192 return UNSPEC_VCMPEQUW;
12193 if (dest_mode == V4SImode && op_mode == V4SFmode)
12194 return UNSPEC_VCMPEQFP;
12197 if (dest_mode == V4SImode && op_mode == V4SFmode)
12198 return UNSPEC_VCMPGEFP;
12200 if (dest_mode == V16QImode && op_mode == V16QImode)
12201 return UNSPEC_VCMPGTSB;
12202 if (dest_mode == V8HImode && op_mode == V8HImode)
12203 return UNSPEC_VCMPGTSH;
12204 if (dest_mode == V4SImode && op_mode == V4SImode)
12205 return UNSPEC_VCMPGTSW;
12206 if (dest_mode == V4SImode && op_mode == V4SFmode)
12207 return UNSPEC_VCMPGTFP;
12210 if (dest_mode == V16QImode && op_mode == V16QImode)
12211 return UNSPEC_VCMPGTUB;
12212 if (dest_mode == V8HImode && op_mode == V8HImode)
12213 return UNSPEC_VCMPGTUH;
12214 if (dest_mode == V4SImode && op_mode == V4SImode)
12215 return UNSPEC_VCMPGTUW;
12220 return INSN_NOT_AVAILABLE;
12223 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12224 DMODE is expected destination mode. This is a recursive function. */
12227 rs6000_emit_vector_compare (enum rtx_code rcode,
12229 enum machine_mode dmode)
12233 enum machine_mode dest_mode;
12234 enum machine_mode op_mode = GET_MODE (op1);
12236 gcc_assert (TARGET_ALTIVEC);
12237 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12239 /* Floating point vector compare instructions uses destination V4SImode.
12240 Move destination to appropriate mode later. */
12241 if (dmode == V4SFmode)
12242 dest_mode = V4SImode;
12246 mask = gen_reg_rtx (dest_mode);
12247 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12249 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12251 bool swap_operands = false;
12252 bool try_again = false;
12257 swap_operands = true;
12262 swap_operands = true;
12270 /* Invert condition and try again.
12271 e.g., A != B becomes ~(A==B). */
12273 enum rtx_code rev_code;
12274 enum insn_code nor_code;
12277 rev_code = reverse_condition_maybe_unordered (rcode);
12278 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12281 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
12282 gcc_assert (nor_code != CODE_FOR_nothing);
12283 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12285 if (dmode != dest_mode)
12287 rtx temp = gen_reg_rtx (dest_mode);
12288 convert_move (temp, mask, 0);
12298 /* Try GT/GTU/LT/LTU OR EQ */
12301 enum insn_code ior_code;
12302 enum rtx_code new_code;
12323 gcc_unreachable ();
12326 c_rtx = rs6000_emit_vector_compare (new_code,
12327 op0, op1, dest_mode);
12328 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12331 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
12332 gcc_assert (ior_code != CODE_FOR_nothing);
12333 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12334 if (dmode != dest_mode)
12336 rtx temp = gen_reg_rtx (dest_mode);
12337 convert_move (temp, mask, 0);
12344 gcc_unreachable ();
12349 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12350 /* You only get two chances. */
12351 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12363 emit_insn (gen_rtx_SET (VOIDmode, mask,
12364 gen_rtx_UNSPEC (dest_mode,
12365 gen_rtvec (2, op0, op1),
12367 if (dmode != dest_mode)
12369 rtx temp = gen_reg_rtx (dest_mode);
12370 convert_move (temp, mask, 0);
12376 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12377 valid insn doesn exist for given mode. */
12380 get_vsel_insn (enum machine_mode mode)
12385 return UNSPEC_VSEL4SI;
12388 return UNSPEC_VSEL4SF;
12391 return UNSPEC_VSEL8HI;
12394 return UNSPEC_VSEL16QI;
12397 return INSN_NOT_AVAILABLE;
12400 return INSN_NOT_AVAILABLE;
12403 /* Emit vector select insn where DEST is destination using
12404 operands OP1, OP2 and MASK. */
12407 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12410 enum machine_mode dest_mode = GET_MODE (dest);
12411 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12413 temp = gen_reg_rtx (dest_mode);
12415 /* For each vector element, select op1 when mask is 1 otherwise
12417 t = gen_rtx_SET (VOIDmode, temp,
12418 gen_rtx_UNSPEC (dest_mode,
12419 gen_rtvec (3, op2, op1, mask),
12422 emit_move_insn (dest, temp);
12426 /* Emit vector conditional expression.
12427 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12428 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12431 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12432 rtx cond, rtx cc_op0, rtx cc_op1)
12434 enum machine_mode dest_mode = GET_MODE (dest);
12435 enum rtx_code rcode = GET_CODE (cond);
12438 if (!TARGET_ALTIVEC)
12441 /* Get the vector mask for the given relational operations. */
12442 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12444 rs6000_emit_vector_select (dest, op1, op2, mask);
12449 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12450 operands of the last comparison is nonzero/true, FALSE_COND if it
12451 is zero/false. Return 0 if the hardware has no such operation. */
12454 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12456 enum rtx_code code = GET_CODE (op);
12457 rtx op0 = rs6000_compare_op0;
12458 rtx op1 = rs6000_compare_op1;
12459 REAL_VALUE_TYPE c1;
12460 enum machine_mode compare_mode = GET_MODE (op0);
12461 enum machine_mode result_mode = GET_MODE (dest);
12463 bool is_against_zero;
12465 /* These modes should always match. */
12466 if (GET_MODE (op1) != compare_mode
12467 /* In the isel case however, we can use a compare immediate, so
12468 op1 may be a small constant. */
12469 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12471 if (GET_MODE (true_cond) != result_mode)
12473 if (GET_MODE (false_cond) != result_mode)
12476 /* First, work out if the hardware can do this at all, or
12477 if it's too slow.... */
12478 if (! rs6000_compare_fp_p)
12481 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12484 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12485 && SCALAR_FLOAT_MODE_P (compare_mode))
12488 is_against_zero = op1 == CONST0_RTX (compare_mode);
12490 /* A floating-point subtract might overflow, underflow, or produce
12491 an inexact result, thus changing the floating-point flags, so it
12492 can't be generated if we care about that. It's safe if one side
12493 of the construct is zero, since then no subtract will be
12495 if (SCALAR_FLOAT_MODE_P (compare_mode)
12496 && flag_trapping_math && ! is_against_zero)
12499 /* Eliminate half of the comparisons by switching operands, this
12500 makes the remaining code simpler. */
12501 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12502 || code == LTGT || code == LT || code == UNLE)
12504 code = reverse_condition_maybe_unordered (code);
12506 true_cond = false_cond;
12510 /* UNEQ and LTGT take four instructions for a comparison with zero,
12511 it'll probably be faster to use a branch here too. */
12512 if (code == UNEQ && HONOR_NANS (compare_mode))
12515 if (GET_CODE (op1) == CONST_DOUBLE)
12516 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12518 /* We're going to try to implement comparisons by performing
12519 a subtract, then comparing against zero. Unfortunately,
12520 Inf - Inf is NaN which is not zero, and so if we don't
12521 know that the operand is finite and the comparison
12522 would treat EQ different to UNORDERED, we can't do it. */
12523 if (HONOR_INFINITIES (compare_mode)
12524 && code != GT && code != UNGE
12525 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12526 /* Constructs of the form (a OP b ? a : b) are safe. */
12527 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12528 || (! rtx_equal_p (op0, true_cond)
12529 && ! rtx_equal_p (op1, true_cond))))
12532 /* At this point we know we can use fsel. */
12534 /* Reduce the comparison to a comparison against zero. */
12535 if (! is_against_zero)
12537 temp = gen_reg_rtx (compare_mode);
12538 emit_insn (gen_rtx_SET (VOIDmode, temp,
12539 gen_rtx_MINUS (compare_mode, op0, op1)));
12541 op1 = CONST0_RTX (compare_mode);
12544 /* If we don't care about NaNs we can reduce some of the comparisons
12545 down to faster ones. */
12546 if (! HONOR_NANS (compare_mode))
12552 true_cond = false_cond;
12565 /* Now, reduce everything down to a GE. */
12572 temp = gen_reg_rtx (compare_mode);
12573 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12578 temp = gen_reg_rtx (compare_mode);
12579 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12584 temp = gen_reg_rtx (compare_mode);
12585 emit_insn (gen_rtx_SET (VOIDmode, temp,
12586 gen_rtx_NEG (compare_mode,
12587 gen_rtx_ABS (compare_mode, op0))));
12592 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12593 temp = gen_reg_rtx (result_mode);
12594 emit_insn (gen_rtx_SET (VOIDmode, temp,
12595 gen_rtx_IF_THEN_ELSE (result_mode,
12596 gen_rtx_GE (VOIDmode,
12598 true_cond, false_cond)));
12599 false_cond = true_cond;
12602 temp = gen_reg_rtx (compare_mode);
12603 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12608 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12609 temp = gen_reg_rtx (result_mode);
12610 emit_insn (gen_rtx_SET (VOIDmode, temp,
12611 gen_rtx_IF_THEN_ELSE (result_mode,
12612 gen_rtx_GE (VOIDmode,
12614 true_cond, false_cond)));
12615 true_cond = false_cond;
12618 temp = gen_reg_rtx (compare_mode);
12619 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12624 gcc_unreachable ();
12627 emit_insn (gen_rtx_SET (VOIDmode, dest,
12628 gen_rtx_IF_THEN_ELSE (result_mode,
12629 gen_rtx_GE (VOIDmode,
12631 true_cond, false_cond)));
12635 /* Same as above, but for ints (isel). */
12638 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12640 rtx condition_rtx, cr;
12642 /* All isel implementations thus far are 32-bits. */
12643 if (GET_MODE (rs6000_compare_op0) != SImode)
12646 /* We still have to do the compare, because isel doesn't do a
12647 compare, it just looks at the CRx bits set by a previous compare
12649 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12650 cr = XEXP (condition_rtx, 0);
12652 if (GET_MODE (cr) == CCmode)
12653 emit_insn (gen_isel_signed (dest, condition_rtx,
12654 true_cond, false_cond, cr));
12656 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12657 true_cond, false_cond, cr));
12663 output_isel (rtx *operands)
12665 enum rtx_code code;
12667 code = GET_CODE (operands[1]);
12668 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12670 PUT_CODE (operands[1], reverse_condition (code));
12671 return "isel %0,%3,%2,%j1";
12674 return "isel %0,%2,%3,%j1";
12678 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12680 enum machine_mode mode = GET_MODE (op0);
12684 if (code == SMAX || code == SMIN)
12689 if (code == SMAX || code == UMAX)
12690 target = emit_conditional_move (dest, c, op0, op1, mode,
12691 op0, op1, mode, 0);
12693 target = emit_conditional_move (dest, c, op0, op1, mode,
12694 op1, op0, mode, 0);
12695 gcc_assert (target);
12696 if (target != dest)
12697 emit_move_insn (dest, target);
12700 /* Emit instructions to perform a load-reserved/store-conditional operation.
12701 The operation performed is an atomic
12702 (set M (CODE:MODE M OP))
12703 If not NULL, BEFORE is atomically set to M before the operation, and
12704 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12705 If SYNC_P then a memory barrier is emitted before the operation.
12706 Either OP or M may be wrapped in a NOT operation. */
12709 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12710 rtx m, rtx op, rtx before_param, rtx after_param,
12713 enum machine_mode used_mode;
12714 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12717 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12718 rtx shift = NULL_RTX;
12721 emit_insn (gen_memory_barrier ());
12723 if (GET_CODE (m) == NOT)
12724 used_m = XEXP (m, 0);
12728 /* If this is smaller than SImode, we'll have to use SImode with
12730 if (mode == QImode || mode == HImode)
12734 if (MEM_ALIGN (used_m) >= 32)
12737 if (BYTES_BIG_ENDIAN)
12738 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12740 shift = GEN_INT (ishift);
12744 rtx addrSI, aligned_addr;
12745 int shift_mask = mode == QImode ? 0x18 : 0x10;
12747 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12748 XEXP (used_m, 0)));
12749 shift = gen_reg_rtx (SImode);
12751 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12752 GEN_INT (shift_mask)));
12753 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12755 aligned_addr = expand_binop (Pmode, and_optab,
12757 GEN_INT (-4), NULL_RTX,
12758 1, OPTAB_LIB_WIDEN);
12759 used_m = change_address (used_m, SImode, aligned_addr);
12760 set_mem_align (used_m, 32);
12761 /* It's safe to keep the old alias set of USED_M, because
12762 the operation is atomic and only affects the original
12764 if (GET_CODE (m) == NOT)
12765 m = gen_rtx_NOT (SImode, used_m);
12770 if (GET_CODE (op) == NOT)
12772 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12773 oldop = gen_rtx_NOT (SImode, oldop);
12776 oldop = lowpart_subreg (SImode, op, mode);
12782 newop = expand_binop (SImode, and_optab,
12783 oldop, GEN_INT (imask), NULL_RTX,
12784 1, OPTAB_LIB_WIDEN);
12785 emit_insn (gen_ashlsi3 (newop, newop, shift));
12789 newop = expand_binop (SImode, ior_optab,
12790 oldop, GEN_INT (~imask), NULL_RTX,
12791 1, OPTAB_LIB_WIDEN);
12792 emit_insn (gen_rotlsi3 (newop, newop, shift));
12800 newop = expand_binop (SImode, and_optab,
12801 oldop, GEN_INT (imask), NULL_RTX,
12802 1, OPTAB_LIB_WIDEN);
12803 emit_insn (gen_ashlsi3 (newop, newop, shift));
12805 mask = gen_reg_rtx (SImode);
12806 emit_move_insn (mask, GEN_INT (imask));
12807 emit_insn (gen_ashlsi3 (mask, mask, shift));
12810 newop = gen_rtx_PLUS (SImode, m, newop);
12812 newop = gen_rtx_MINUS (SImode, m, newop);
12813 newop = gen_rtx_AND (SImode, newop, mask);
12814 newop = gen_rtx_IOR (SImode, newop,
12815 gen_rtx_AND (SImode,
12816 gen_rtx_NOT (SImode, mask),
12822 gcc_unreachable ();
12825 if (GET_CODE (m) == NOT)
12829 mask = gen_reg_rtx (SImode);
12830 emit_move_insn (mask, GEN_INT (imask));
12831 emit_insn (gen_ashlsi3 (mask, mask, shift));
12833 xorm = gen_rtx_XOR (SImode, used_m, mask);
12834 /* Depending on the value of 'op', the XOR or the operation might
12835 be able to be simplified away. */
12836 newop = simplify_gen_binary (code, SImode, xorm, newop);
12839 used_mode = SImode;
12840 before = gen_reg_rtx (used_mode);
12841 after = gen_reg_rtx (used_mode);
12846 before = before_param;
12847 after = after_param;
12849 if (before == NULL_RTX)
12850 before = gen_reg_rtx (used_mode);
12851 if (after == NULL_RTX)
12852 after = gen_reg_rtx (used_mode);
12855 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12856 && used_mode != mode)
12857 the_op = op; /* Computed above. */
12858 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12859 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12861 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12863 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12864 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12865 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12866 gen_rtx_UNSPEC (used_mode,
12867 gen_rtvec (1, the_op),
12869 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12871 if ((code == PLUS || code == MINUS) && used_mode != mode)
12872 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12873 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12875 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12876 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12878 /* Shift and mask the return values properly. */
12879 if (used_mode != mode && before_param)
12881 emit_insn (gen_lshrsi3 (before, before, shift));
12882 convert_move (before_param, before, 1);
12885 if (used_mode != mode && after_param)
12887 emit_insn (gen_lshrsi3 (after, after, shift));
12888 convert_move (after_param, after, 1);
12891 /* The previous sequence will end with a branch that's dependent on
12892 the conditional store, so placing an isync will ensure that no
12893 other instructions (especially, no load or store instructions)
12894 can start before the atomic operation completes. */
12896 emit_insn (gen_isync ());
12899 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12900 COND is true. Mark the jump as unlikely to be taken. */
12903 emit_unlikely_jump (rtx cond, rtx label)
12905 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12908 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12909 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12910 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12913 /* A subroutine of the atomic operation splitters. Emit a load-locked
12914 instruction in MODE. */
12917 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12919 rtx (*fn) (rtx, rtx) = NULL;
12920 if (mode == SImode)
12921 fn = gen_load_locked_si;
12922 else if (mode == DImode)
12923 fn = gen_load_locked_di;
12924 emit_insn (fn (reg, mem));
12927 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12928 instruction in MODE. */
12931 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12933 rtx (*fn) (rtx, rtx, rtx) = NULL;
12934 if (mode == SImode)
12935 fn = gen_store_conditional_si;
12936 else if (mode == DImode)
12937 fn = gen_store_conditional_di;
12939 /* Emit sync before stwcx. to address PPC405 Erratum. */
12940 if (PPC405_ERRATUM77)
12941 emit_insn (gen_memory_barrier ());
12943 emit_insn (fn (res, mem, val));
12946 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12947 to perform. MEM is the memory on which to operate. VAL is the second
12948 operand of the binary operator. BEFORE and AFTER are optional locations to
12949 return the value of MEM either before of after the operation. SCRATCH is
12950 a scratch register. */
12953 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12954 rtx before, rtx after, rtx scratch)
12956 enum machine_mode mode = GET_MODE (mem);
12957 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12959 emit_insn (gen_memory_barrier ());
12961 label = gen_label_rtx ();
12962 emit_label (label);
12963 label = gen_rtx_LABEL_REF (VOIDmode, label);
12965 if (before == NULL_RTX)
12967 emit_load_locked (mode, before, mem);
12970 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12971 else if (code == AND)
12972 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12974 x = gen_rtx_fmt_ee (code, mode, before, val);
12976 if (after != NULL_RTX)
12977 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12978 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12980 emit_store_conditional (mode, cond, mem, scratch);
12982 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12983 emit_unlikely_jump (x, label);
12985 emit_insn (gen_isync ());
12988 /* Expand an atomic compare and swap operation. MEM is the memory on which
12989 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12990 value to be stored. SCRATCH is a scratch GPR. */
12993 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12996 enum machine_mode mode = GET_MODE (mem);
12997 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12999 emit_insn (gen_memory_barrier ());
13001 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13002 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13003 emit_label (XEXP (label1, 0));
13005 emit_load_locked (mode, retval, mem);
13007 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13008 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13010 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13011 emit_unlikely_jump (x, label2);
13013 emit_move_insn (scratch, newval);
13014 emit_store_conditional (mode, cond, mem, scratch);
13016 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13017 emit_unlikely_jump (x, label1);
13019 emit_insn (gen_isync ());
13020 emit_label (XEXP (label2, 0));
13023 /* Expand an atomic test and set operation. MEM is the memory on which
13024 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13027 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13029 enum machine_mode mode = GET_MODE (mem);
13030 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13032 emit_insn (gen_memory_barrier ());
13034 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13035 emit_label (XEXP (label, 0));
13037 emit_load_locked (mode, retval, mem);
13038 emit_move_insn (scratch, val);
13039 emit_store_conditional (mode, cond, mem, scratch);
13041 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13042 emit_unlikely_jump (x, label);
13044 emit_insn (gen_isync ());
13048 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13050 enum machine_mode mode = GET_MODE (mem);
13051 rtx addrSI, align, wdst, shift, mask;
13052 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13053 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13055 /* Shift amount for subword relative to aligned word. */
13056 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13057 shift = gen_reg_rtx (SImode);
13058 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13059 GEN_INT (shift_mask)));
13060 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13062 /* Shift and mask old value into position within word. */
13063 oldval = convert_modes (SImode, mode, oldval, 1);
13064 oldval = expand_binop (SImode, and_optab,
13065 oldval, GEN_INT (imask), NULL_RTX,
13066 1, OPTAB_LIB_WIDEN);
13067 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13069 /* Shift and mask new value into position within word. */
13070 newval = convert_modes (SImode, mode, newval, 1);
13071 newval = expand_binop (SImode, and_optab,
13072 newval, GEN_INT (imask), NULL_RTX,
13073 1, OPTAB_LIB_WIDEN);
13074 emit_insn (gen_ashlsi3 (newval, newval, shift));
13076 /* Mask for insertion. */
13077 mask = gen_reg_rtx (SImode);
13078 emit_move_insn (mask, GEN_INT (imask));
13079 emit_insn (gen_ashlsi3 (mask, mask, shift));
13081 /* Address of aligned word containing subword. */
13082 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13083 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13084 mem = change_address (mem, SImode, align);
13085 set_mem_align (mem, 32);
13086 MEM_VOLATILE_P (mem) = 1;
13088 wdst = gen_reg_rtx (SImode);
13089 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13090 oldval, newval, mem));
13092 emit_move_insn (dst, gen_lowpart (mode, wdst));
13096 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13097 rtx oldval, rtx newval, rtx mem,
13100 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13102 emit_insn (gen_memory_barrier ());
13103 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13104 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13105 emit_label (XEXP (label1, 0));
13107 emit_load_locked (SImode, scratch, mem);
13109 /* Mask subword within loaded value for comparison with oldval.
13110 Use UNSPEC_AND to avoid clobber.*/
13111 emit_insn (gen_rtx_SET (SImode, dest,
13112 gen_rtx_UNSPEC (SImode,
13113 gen_rtvec (2, scratch, mask),
13116 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13117 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13119 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13120 emit_unlikely_jump (x, label2);
13122 /* Clear subword within loaded value for insertion of new value. */
13123 emit_insn (gen_rtx_SET (SImode, scratch,
13124 gen_rtx_AND (SImode,
13125 gen_rtx_NOT (SImode, mask), scratch)));
13126 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13127 emit_store_conditional (SImode, cond, mem, scratch);
13129 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13130 emit_unlikely_jump (x, label1);
13132 emit_insn (gen_isync ());
13133 emit_label (XEXP (label2, 0));
13137 /* Emit instructions to move SRC to DST. Called by splitters for
13138 multi-register moves. It will emit at most one instruction for
13139 each register that is accessed; that is, it won't emit li/lis pairs
13140 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13144 rs6000_split_multireg_move (rtx dst, rtx src)
13146 /* The register number of the first register being moved. */
13148 /* The mode that is to be moved. */
13149 enum machine_mode mode;
13150 /* The mode that the move is being done in, and its size. */
13151 enum machine_mode reg_mode;
13153 /* The number of registers that will be moved. */
13156 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13157 mode = GET_MODE (dst);
13158 nregs = hard_regno_nregs[reg][mode];
13159 if (FP_REGNO_P (reg))
13160 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13161 else if (ALTIVEC_REGNO_P (reg))
13162 reg_mode = V16QImode;
13163 else if (TARGET_E500_DOUBLE && mode == TFmode)
13166 reg_mode = word_mode;
13167 reg_mode_size = GET_MODE_SIZE (reg_mode);
13169 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13171 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13173 /* Move register range backwards, if we might have destructive
13176 for (i = nregs - 1; i >= 0; i--)
13177 emit_insn (gen_rtx_SET (VOIDmode,
13178 simplify_gen_subreg (reg_mode, dst, mode,
13179 i * reg_mode_size),
13180 simplify_gen_subreg (reg_mode, src, mode,
13181 i * reg_mode_size)));
13187 bool used_update = false;
13189 if (MEM_P (src) && INT_REGNO_P (reg))
13193 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13194 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13197 breg = XEXP (XEXP (src, 0), 0);
13198 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13199 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13200 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13201 emit_insn (TARGET_32BIT
13202 ? gen_addsi3 (breg, breg, delta_rtx)
13203 : gen_adddi3 (breg, breg, delta_rtx));
13204 src = replace_equiv_address (src, breg);
13206 else if (! rs6000_offsettable_memref_p (src))
13209 basereg = gen_rtx_REG (Pmode, reg);
13210 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13211 src = replace_equiv_address (src, basereg);
13214 breg = XEXP (src, 0);
13215 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13216 breg = XEXP (breg, 0);
13218 /* If the base register we are using to address memory is
13219 also a destination reg, then change that register last. */
13221 && REGNO (breg) >= REGNO (dst)
13222 && REGNO (breg) < REGNO (dst) + nregs)
13223 j = REGNO (breg) - REGNO (dst);
13226 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13230 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13231 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13234 breg = XEXP (XEXP (dst, 0), 0);
13235 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13236 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13237 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13239 /* We have to update the breg before doing the store.
13240 Use store with update, if available. */
13244 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13245 emit_insn (TARGET_32BIT
13246 ? (TARGET_POWERPC64
13247 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13248 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13249 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13250 used_update = true;
13253 emit_insn (TARGET_32BIT
13254 ? gen_addsi3 (breg, breg, delta_rtx)
13255 : gen_adddi3 (breg, breg, delta_rtx));
13256 dst = replace_equiv_address (dst, breg);
13259 gcc_assert (rs6000_offsettable_memref_p (dst));
13262 for (i = 0; i < nregs; i++)
13264 /* Calculate index to next subword. */
13269 /* If compiler already emitted move of first word by
13270 store with update, no need to do anything. */
13271 if (j == 0 && used_update)
13274 emit_insn (gen_rtx_SET (VOIDmode,
13275 simplify_gen_subreg (reg_mode, dst, mode,
13276 j * reg_mode_size),
13277 simplify_gen_subreg (reg_mode, src, mode,
13278 j * reg_mode_size)));
13284 /* This page contains routines that are used to determine what the
13285 function prologue and epilogue code will do and write them out. */
13287 /* Return the first fixed-point register that is required to be
13288 saved. 32 if none. */
13291 first_reg_to_save (void)
13295 /* Find lowest numbered live register. */
13296 for (first_reg = 13; first_reg <= 31; first_reg++)
13297 if (df_regs_ever_live_p (first_reg)
13298 && (! call_used_regs[first_reg]
13299 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13300 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13301 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13302 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13307 && current_function_uses_pic_offset_table
13308 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13309 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13315 /* Similar, for FP regs. */
13318 first_fp_reg_to_save (void)
13322 /* Find lowest numbered live register. */
13323 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13324 if (df_regs_ever_live_p (first_reg))
13330 /* Similar, for AltiVec regs. */
13333 first_altivec_reg_to_save (void)
13337 /* Stack frame remains as is unless we are in AltiVec ABI. */
13338 if (! TARGET_ALTIVEC_ABI)
13339 return LAST_ALTIVEC_REGNO + 1;
13341 /* On Darwin, the unwind routines are compiled without
13342 TARGET_ALTIVEC, and use save_world to save/restore the
13343 altivec registers when necessary. */
13344 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13345 && ! TARGET_ALTIVEC)
13346 return FIRST_ALTIVEC_REGNO + 20;
13348 /* Find lowest numbered live register. */
13349 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13350 if (df_regs_ever_live_p (i))
13356 /* Return a 32-bit mask of the AltiVec registers we need to set in
13357 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13358 the 32-bit word is 0. */
13360 static unsigned int
13361 compute_vrsave_mask (void)
13363 unsigned int i, mask = 0;
13365 /* On Darwin, the unwind routines are compiled without
13366 TARGET_ALTIVEC, and use save_world to save/restore the
13367 call-saved altivec registers when necessary. */
13368 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13369 && ! TARGET_ALTIVEC)
13372 /* First, find out if we use _any_ altivec registers. */
13373 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13374 if (df_regs_ever_live_p (i))
13375 mask |= ALTIVEC_REG_BIT (i);
13380 /* Next, remove the argument registers from the set. These must
13381 be in the VRSAVE mask set by the caller, so we don't need to add
13382 them in again. More importantly, the mask we compute here is
13383 used to generate CLOBBERs in the set_vrsave insn, and we do not
13384 wish the argument registers to die. */
13385 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13386 mask &= ~ALTIVEC_REG_BIT (i);
13388 /* Similarly, remove the return value from the set. */
13391 diddle_return_value (is_altivec_return_reg, &yes);
13393 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13399 /* For a very restricted set of circumstances, we can cut down the
13400 size of prologues/epilogues by calling our own save/restore-the-world
13404 compute_save_world_info (rs6000_stack_t *info_ptr)
13406 info_ptr->world_save_p = 1;
13407 info_ptr->world_save_p
13408 = (WORLD_SAVE_P (info_ptr)
13409 && DEFAULT_ABI == ABI_DARWIN
13410 && ! (current_function_calls_setjmp && flag_exceptions)
13411 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13412 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13413 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13414 && info_ptr->cr_save_p);
13416 /* This will not work in conjunction with sibcalls. Make sure there
13417 are none. (This check is expensive, but seldom executed.) */
13418 if (WORLD_SAVE_P (info_ptr))
13421 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13422 if ( GET_CODE (insn) == CALL_INSN
13423 && SIBLING_CALL_P (insn))
13425 info_ptr->world_save_p = 0;
13430 if (WORLD_SAVE_P (info_ptr))
13432 /* Even if we're not touching VRsave, make sure there's room on the
13433 stack for it, if it looks like we're calling SAVE_WORLD, which
13434 will attempt to save it. */
13435 info_ptr->vrsave_size = 4;
13437 /* "Save" the VRsave register too if we're saving the world. */
13438 if (info_ptr->vrsave_mask == 0)
13439 info_ptr->vrsave_mask = compute_vrsave_mask ();
13441 /* Because the Darwin register save/restore routines only handle
13442 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13444 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13445 && (info_ptr->first_altivec_reg_save
13446 >= FIRST_SAVED_ALTIVEC_REGNO));
13453 is_altivec_return_reg (rtx reg, void *xyes)
13455 bool *yes = (bool *) xyes;
13456 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13461 /* Calculate the stack information for the current function. This is
13462 complicated by having two separate calling sequences, the AIX calling
13463 sequence and the V.4 calling sequence.
13465 AIX (and Darwin/Mac OS X) stack frames look like:
13467 SP----> +---------------------------------------+
13468 | back chain to caller | 0 0
13469 +---------------------------------------+
13470 | saved CR | 4 8 (8-11)
13471 +---------------------------------------+
13473 +---------------------------------------+
13474 | reserved for compilers | 12 24
13475 +---------------------------------------+
13476 | reserved for binders | 16 32
13477 +---------------------------------------+
13478 | saved TOC pointer | 20 40
13479 +---------------------------------------+
13480 | Parameter save area (P) | 24 48
13481 +---------------------------------------+
13482 | Alloca space (A) | 24+P etc.
13483 +---------------------------------------+
13484 | Local variable space (L) | 24+P+A
13485 +---------------------------------------+
13486 | Float/int conversion temporary (X) | 24+P+A+L
13487 +---------------------------------------+
13488 | Save area for AltiVec registers (W) | 24+P+A+L+X
13489 +---------------------------------------+
13490 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13491 +---------------------------------------+
13492 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13493 +---------------------------------------+
13494 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13495 +---------------------------------------+
13496 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13497 +---------------------------------------+
13498 old SP->| back chain to caller's caller |
13499 +---------------------------------------+
13501 The required alignment for AIX configurations is two words (i.e., 8
13505 V.4 stack frames look like:
13507 SP----> +---------------------------------------+
13508 | back chain to caller | 0
13509 +---------------------------------------+
13510 | caller's saved LR | 4
13511 +---------------------------------------+
13512 | Parameter save area (P) | 8
13513 +---------------------------------------+
13514 | Alloca space (A) | 8+P
13515 +---------------------------------------+
13516 | Varargs save area (V) | 8+P+A
13517 +---------------------------------------+
13518 | Local variable space (L) | 8+P+A+V
13519 +---------------------------------------+
13520 | Float/int conversion temporary (X) | 8+P+A+V+L
13521 +---------------------------------------+
13522 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13523 +---------------------------------------+
13524 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13525 +---------------------------------------+
13526 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13527 +---------------------------------------+
13528 | SPE: area for 64-bit GP registers |
13529 +---------------------------------------+
13530 | SPE alignment padding |
13531 +---------------------------------------+
13532 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13533 +---------------------------------------+
13534 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13535 +---------------------------------------+
13536 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13537 +---------------------------------------+
13538 old SP->| back chain to caller's caller |
13539 +---------------------------------------+
13541 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13542 given. (But note below and in sysv4.h that we require only 8 and
13543 may round up the size of our stack frame anyways. The historical
13544 reason is early versions of powerpc-linux which didn't properly
13545 align the stack at program startup. A happy side-effect is that
13546 -mno-eabi libraries can be used with -meabi programs.)
13548 The EABI configuration defaults to the V.4 layout. However,
13549 the stack alignment requirements may differ. If -mno-eabi is not
13550 given, the required stack alignment is 8 bytes; if -mno-eabi is
13551 given, the required alignment is 16 bytes. (But see V.4 comment
13554 #ifndef ABI_STACK_BOUNDARY
13555 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13558 static rs6000_stack_t *
13559 rs6000_stack_info (void)
13561 static rs6000_stack_t info;
13562 rs6000_stack_t *info_ptr = &info;
13563 int reg_size = TARGET_32BIT ? 4 : 8;
13566 HOST_WIDE_INT non_fixed_size;
13568 memset (&info, 0, sizeof (info));
13572 /* Cache value so we don't rescan instruction chain over and over. */
13573 if (cfun->machine->insn_chain_scanned_p == 0)
13574 cfun->machine->insn_chain_scanned_p
13575 = spe_func_has_64bit_regs_p () + 1;
13576 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13579 /* Select which calling sequence. */
13580 info_ptr->abi = DEFAULT_ABI;
13582 /* Calculate which registers need to be saved & save area size. */
13583 info_ptr->first_gp_reg_save = first_reg_to_save ();
13584 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13585 even if it currently looks like we won't. */
13586 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13587 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13588 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13589 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13590 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13592 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13594 /* For the SPE, we have an additional upper 32-bits on each GPR.
13595 Ideally we should save the entire 64-bits only when the upper
13596 half is used in SIMD instructions. Since we only record
13597 registers live (not the size they are used in), this proves
13598 difficult because we'd have to traverse the instruction chain at
13599 the right time, taking reload into account. This is a real pain,
13600 so we opt to save the GPRs in 64-bits always if but one register
13601 gets used in 64-bits. Otherwise, all the registers in the frame
13602 get saved in 32-bits.
13604 So... since when we save all GPRs (except the SP) in 64-bits, the
13605 traditional GP save area will be empty. */
13606 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13607 info_ptr->gp_size = 0;
13609 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13610 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13612 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13613 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13614 - info_ptr->first_altivec_reg_save);
13616 /* Does this function call anything? */
13617 info_ptr->calls_p = (! current_function_is_leaf
13618 || cfun->machine->ra_needs_full_frame);
13620 /* Determine if we need to save the link register. */
13621 if ((DEFAULT_ABI == ABI_AIX
13622 && current_function_profile
13623 && !TARGET_PROFILE_KERNEL)
13624 #ifdef TARGET_RELOCATABLE
13625 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13627 || (info_ptr->first_fp_reg_save != 64
13628 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13629 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13630 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13631 || info_ptr->calls_p
13632 || rs6000_ra_ever_killed ())
13634 info_ptr->lr_save_p = 1;
13635 df_set_regs_ever_live (LR_REGNO, true);
13638 /* Determine if we need to save the condition code registers. */
13639 if (df_regs_ever_live_p (CR2_REGNO)
13640 || df_regs_ever_live_p (CR3_REGNO)
13641 || df_regs_ever_live_p (CR4_REGNO))
13643 info_ptr->cr_save_p = 1;
13644 if (DEFAULT_ABI == ABI_V4)
13645 info_ptr->cr_size = reg_size;
13648 /* If the current function calls __builtin_eh_return, then we need
13649 to allocate stack space for registers that will hold data for
13650 the exception handler. */
13651 if (current_function_calls_eh_return)
13654 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13657 /* SPE saves EH registers in 64-bits. */
13658 ehrd_size = i * (TARGET_SPE_ABI
13659 && info_ptr->spe_64bit_regs_used != 0
13660 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13665 /* Determine various sizes. */
13666 info_ptr->reg_size = reg_size;
13667 info_ptr->fixed_size = RS6000_SAVE_AREA;
13668 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13669 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13670 TARGET_ALTIVEC ? 16 : 8);
13671 if (FRAME_GROWS_DOWNWARD)
13672 info_ptr->vars_size
13673 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13674 + info_ptr->parm_size,
13675 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13676 - (info_ptr->fixed_size + info_ptr->vars_size
13677 + info_ptr->parm_size);
13679 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13680 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13682 info_ptr->spe_gp_size = 0;
13684 if (TARGET_ALTIVEC_ABI)
13685 info_ptr->vrsave_mask = compute_vrsave_mask ();
13687 info_ptr->vrsave_mask = 0;
13689 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13690 info_ptr->vrsave_size = 4;
13692 info_ptr->vrsave_size = 0;
13694 compute_save_world_info (info_ptr);
13696 /* Calculate the offsets. */
13697 switch (DEFAULT_ABI)
13701 gcc_unreachable ();
13705 info_ptr->fp_save_offset = - info_ptr->fp_size;
13706 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13708 if (TARGET_ALTIVEC_ABI)
13710 info_ptr->vrsave_save_offset
13711 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13713 /* Align stack so vector save area is on a quadword boundary.
13714 The padding goes above the vectors. */
13715 if (info_ptr->altivec_size != 0)
13716 info_ptr->altivec_padding_size
13717 = info_ptr->vrsave_save_offset & 0xF;
13719 info_ptr->altivec_padding_size = 0;
13721 info_ptr->altivec_save_offset
13722 = info_ptr->vrsave_save_offset
13723 - info_ptr->altivec_padding_size
13724 - info_ptr->altivec_size;
13725 gcc_assert (info_ptr->altivec_size == 0
13726 || info_ptr->altivec_save_offset % 16 == 0);
13728 /* Adjust for AltiVec case. */
13729 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13732 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13733 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13734 info_ptr->lr_save_offset = 2*reg_size;
13738 info_ptr->fp_save_offset = - info_ptr->fp_size;
13739 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13740 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13742 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13744 /* Align stack so SPE GPR save area is aligned on a
13745 double-word boundary. */
13746 if (info_ptr->spe_gp_size != 0)
13747 info_ptr->spe_padding_size
13748 = 8 - (-info_ptr->cr_save_offset % 8);
13750 info_ptr->spe_padding_size = 0;
13752 info_ptr->spe_gp_save_offset
13753 = info_ptr->cr_save_offset
13754 - info_ptr->spe_padding_size
13755 - info_ptr->spe_gp_size;
13757 /* Adjust for SPE case. */
13758 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13760 else if (TARGET_ALTIVEC_ABI)
13762 info_ptr->vrsave_save_offset
13763 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13765 /* Align stack so vector save area is on a quadword boundary. */
13766 if (info_ptr->altivec_size != 0)
13767 info_ptr->altivec_padding_size
13768 = 16 - (-info_ptr->vrsave_save_offset % 16);
13770 info_ptr->altivec_padding_size = 0;
13772 info_ptr->altivec_save_offset
13773 = info_ptr->vrsave_save_offset
13774 - info_ptr->altivec_padding_size
13775 - info_ptr->altivec_size;
13777 /* Adjust for AltiVec case. */
13778 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13781 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13782 info_ptr->ehrd_offset -= ehrd_size;
13783 info_ptr->lr_save_offset = reg_size;
13787 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13788 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13789 + info_ptr->gp_size
13790 + info_ptr->altivec_size
13791 + info_ptr->altivec_padding_size
13792 + info_ptr->spe_gp_size
13793 + info_ptr->spe_padding_size
13795 + info_ptr->cr_size
13796 + info_ptr->vrsave_size,
13799 non_fixed_size = (info_ptr->vars_size
13800 + info_ptr->parm_size
13801 + info_ptr->save_size);
13803 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13804 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13806 /* Determine if we need to allocate any stack frame:
13808 For AIX we need to push the stack if a frame pointer is needed
13809 (because the stack might be dynamically adjusted), if we are
13810 debugging, if we make calls, or if the sum of fp_save, gp_save,
13811 and local variables are more than the space needed to save all
13812 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13813 + 18*8 = 288 (GPR13 reserved).
13815 For V.4 we don't have the stack cushion that AIX uses, but assume
13816 that the debugger can handle stackless frames. */
13818 if (info_ptr->calls_p)
13819 info_ptr->push_p = 1;
13821 else if (DEFAULT_ABI == ABI_V4)
13822 info_ptr->push_p = non_fixed_size != 0;
13824 else if (frame_pointer_needed)
13825 info_ptr->push_p = 1;
13827 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13828 info_ptr->push_p = 1;
13831 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13833 /* Zero offsets if we're not saving those registers. */
13834 if (info_ptr->fp_size == 0)
13835 info_ptr->fp_save_offset = 0;
13837 if (info_ptr->gp_size == 0)
13838 info_ptr->gp_save_offset = 0;
13840 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13841 info_ptr->altivec_save_offset = 0;
13843 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13844 info_ptr->vrsave_save_offset = 0;
13846 if (! TARGET_SPE_ABI
13847 || info_ptr->spe_64bit_regs_used == 0
13848 || info_ptr->spe_gp_size == 0)
13849 info_ptr->spe_gp_save_offset = 0;
13851 if (! info_ptr->lr_save_p)
13852 info_ptr->lr_save_offset = 0;
13854 if (! info_ptr->cr_save_p)
13855 info_ptr->cr_save_offset = 0;
13860 /* Return true if the current function uses any GPRs in 64-bit SIMD
13864 spe_func_has_64bit_regs_p (void)
13868 /* Functions that save and restore all the call-saved registers will
13869 need to save/restore the registers in 64-bits. */
13870 if (current_function_calls_eh_return
13871 || current_function_calls_setjmp
13872 || current_function_has_nonlocal_goto)
13875 insns = get_insns ();
13877 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13883 /* FIXME: This should be implemented with attributes...
13885 (set_attr "spe64" "true")....then,
13886 if (get_spe64(insn)) return true;
13888 It's the only reliable way to do the stuff below. */
13890 i = PATTERN (insn);
13891 if (GET_CODE (i) == SET)
13893 enum machine_mode mode = GET_MODE (SET_SRC (i));
13895 if (SPE_VECTOR_MODE (mode))
13897 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13907 debug_stack_info (rs6000_stack_t *info)
13909 const char *abi_string;
13912 info = rs6000_stack_info ();
13914 fprintf (stderr, "\nStack information for function %s:\n",
13915 ((current_function_decl && DECL_NAME (current_function_decl))
13916 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13921 default: abi_string = "Unknown"; break;
13922 case ABI_NONE: abi_string = "NONE"; break;
13923 case ABI_AIX: abi_string = "AIX"; break;
13924 case ABI_DARWIN: abi_string = "Darwin"; break;
13925 case ABI_V4: abi_string = "V.4"; break;
13928 fprintf (stderr, "\tABI = %5s\n", abi_string);
13930 if (TARGET_ALTIVEC_ABI)
13931 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13933 if (TARGET_SPE_ABI)
13934 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13936 if (info->first_gp_reg_save != 32)
13937 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13939 if (info->first_fp_reg_save != 64)
13940 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13942 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13943 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13944 info->first_altivec_reg_save);
13946 if (info->lr_save_p)
13947 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13949 if (info->cr_save_p)
13950 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13952 if (info->vrsave_mask)
13953 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13956 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13959 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13961 if (info->gp_save_offset)
13962 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13964 if (info->fp_save_offset)
13965 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13967 if (info->altivec_save_offset)
13968 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13969 info->altivec_save_offset);
13971 if (info->spe_gp_save_offset)
13972 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13973 info->spe_gp_save_offset);
13975 if (info->vrsave_save_offset)
13976 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13977 info->vrsave_save_offset);
13979 if (info->lr_save_offset)
13980 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13982 if (info->cr_save_offset)
13983 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13985 if (info->varargs_save_offset)
13986 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13988 if (info->total_size)
13989 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13992 if (info->vars_size)
13993 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13996 if (info->parm_size)
13997 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13999 if (info->fixed_size)
14000 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14003 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14005 if (info->spe_gp_size)
14006 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14009 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14011 if (info->altivec_size)
14012 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14014 if (info->vrsave_size)
14015 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14017 if (info->altivec_padding_size)
14018 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14019 info->altivec_padding_size);
14021 if (info->spe_padding_size)
14022 fprintf (stderr, "\tspe_padding_size = %5d\n",
14023 info->spe_padding_size);
14026 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14028 if (info->save_size)
14029 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14031 if (info->reg_size != 4)
14032 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14034 fprintf (stderr, "\n");
14038 rs6000_return_addr (int count, rtx frame)
14040 /* Currently we don't optimize very well between prolog and body
14041 code and for PIC code the code can be actually quite bad, so
14042 don't try to be too clever here. */
14043 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14045 cfun->machine->ra_needs_full_frame = 1;
14052 plus_constant (copy_to_reg
14053 (gen_rtx_MEM (Pmode,
14054 memory_address (Pmode, frame))),
14055 RETURN_ADDRESS_OFFSET)));
14058 cfun->machine->ra_need_lr = 1;
14059 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14062 /* Say whether a function is a candidate for sibcall handling or not.
14063 We do not allow indirect calls to be optimized into sibling calls.
14064 Also, we can't do it if there are any vector parameters; there's
14065 nowhere to put the VRsave code so it works; note that functions with
14066 vector parameters are required to have a prototype, so the argument
14067 type info must be available here. (The tail recursion case can work
14068 with vector parameters, but there's no way to distinguish here.) */
14070 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14075 if (TARGET_ALTIVEC_VRSAVE)
14077 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14078 type; type = TREE_CHAIN (type))
14080 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14084 if (DEFAULT_ABI == ABI_DARWIN
14085 || ((*targetm.binds_local_p) (decl)
14086 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14088 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14090 if (!lookup_attribute ("longcall", attr_list)
14091 || lookup_attribute ("shortcall", attr_list))
14098 /* NULL if INSN insn is valid within a low-overhead loop.
14099 Otherwise return why doloop cannot be applied.
14100 PowerPC uses the COUNT register for branch on table instructions. */
14102 static const char *
14103 rs6000_invalid_within_doloop (rtx insn)
14106 return "Function call in the loop.";
14109 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14110 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14111 return "Computed branch in the loop.";
14117 rs6000_ra_ever_killed (void)
14123 if (current_function_is_thunk)
14126 /* regs_ever_live has LR marked as used if any sibcalls are present,
14127 but this should not force saving and restoring in the
14128 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14129 clobbers LR, so that is inappropriate. */
14131 /* Also, the prologue can generate a store into LR that
14132 doesn't really count, like this:
14135 bcl to set PIC register
14139 When we're called from the epilogue, we need to avoid counting
14140 this as a store. */
14142 push_topmost_sequence ();
14143 top = get_insns ();
14144 pop_topmost_sequence ();
14145 reg = gen_rtx_REG (Pmode, LR_REGNO);
14147 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14153 if (!SIBLING_CALL_P (insn))
14156 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14158 else if (set_of (reg, insn) != NULL_RTX
14159 && !prologue_epilogue_contains (insn))
14166 /* Emit instructions needed to load the TOC register.
14167 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14168 a constant pool; or for SVR4 -fpic. */
14171 rs6000_emit_load_toc_table (int fromprolog)
14174 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14176 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14179 rtx lab, tmp1, tmp2, got;
14181 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14182 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14184 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14186 got = rs6000_got_sym ();
14187 tmp1 = tmp2 = dest;
14190 tmp1 = gen_reg_rtx (Pmode);
14191 tmp2 = gen_reg_rtx (Pmode);
14193 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14194 emit_move_insn (tmp1,
14195 gen_rtx_REG (Pmode, LR_REGNO));
14196 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14197 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14199 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14201 emit_insn (gen_load_toc_v4_pic_si ());
14202 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
14204 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14207 rtx temp0 = (fromprolog
14208 ? gen_rtx_REG (Pmode, 0)
14209 : gen_reg_rtx (Pmode));
14215 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14216 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14218 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14219 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14221 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14222 emit_move_insn (dest,
14223 gen_rtx_REG (Pmode, LR_REGNO));
14224 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14230 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14231 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14232 emit_move_insn (dest,
14233 gen_rtx_REG (Pmode, LR_REGNO));
14234 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14236 emit_insn (gen_addsi3 (dest, temp0, dest));
14238 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14240 /* This is for AIX code running in non-PIC ELF32. */
14243 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14244 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14246 emit_insn (gen_elf_high (dest, realsym));
14247 emit_insn (gen_elf_low (dest, dest, realsym));
14251 gcc_assert (DEFAULT_ABI == ABI_AIX);
14254 emit_insn (gen_load_toc_aix_si (dest));
14256 emit_insn (gen_load_toc_aix_di (dest));
14260 /* Emit instructions to restore the link register after determining where
14261 its value has been stored. */
14264 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14266 rs6000_stack_t *info = rs6000_stack_info ();
14269 operands[0] = source;
14270 operands[1] = scratch;
14272 if (info->lr_save_p)
14274 rtx frame_rtx = stack_pointer_rtx;
14275 HOST_WIDE_INT sp_offset = 0;
14278 if (frame_pointer_needed
14279 || current_function_calls_alloca
14280 || info->total_size > 32767)
14282 tmp = gen_frame_mem (Pmode, frame_rtx);
14283 emit_move_insn (operands[1], tmp);
14284 frame_rtx = operands[1];
14286 else if (info->push_p)
14287 sp_offset = info->total_size;
14289 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14290 tmp = gen_frame_mem (Pmode, tmp);
14291 emit_move_insn (tmp, operands[0]);
14294 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
14297 static GTY(()) alias_set_type set = -1;
14300 get_TOC_alias_set (void)
14303 set = new_alias_set ();
14307 /* This returns nonzero if the current function uses the TOC. This is
14308 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14309 is generated by the ABI_V4 load_toc_* patterns. */
14316 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14319 rtx pat = PATTERN (insn);
14322 if (GET_CODE (pat) == PARALLEL)
14323 for (i = 0; i < XVECLEN (pat, 0); i++)
14325 rtx sub = XVECEXP (pat, 0, i);
14326 if (GET_CODE (sub) == USE)
14328 sub = XEXP (sub, 0);
14329 if (GET_CODE (sub) == UNSPEC
14330 && XINT (sub, 1) == UNSPEC_TOC)
14340 create_TOC_reference (rtx symbol)
14342 if (!can_create_pseudo_p ())
14343 df_set_regs_ever_live (TOC_REGISTER, true);
14344 return gen_rtx_PLUS (Pmode,
14345 gen_rtx_REG (Pmode, TOC_REGISTER),
14346 gen_rtx_CONST (Pmode,
14347 gen_rtx_MINUS (Pmode, symbol,
14348 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14351 /* If _Unwind_* has been called from within the same module,
14352 toc register is not guaranteed to be saved to 40(1) on function
14353 entry. Save it there in that case. */
14356 rs6000_aix_emit_builtin_unwind_init (void)
14359 rtx stack_top = gen_reg_rtx (Pmode);
14360 rtx opcode_addr = gen_reg_rtx (Pmode);
14361 rtx opcode = gen_reg_rtx (SImode);
14362 rtx tocompare = gen_reg_rtx (SImode);
14363 rtx no_toc_save_needed = gen_label_rtx ();
14365 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14366 emit_move_insn (stack_top, mem);
14368 mem = gen_frame_mem (Pmode,
14369 gen_rtx_PLUS (Pmode, stack_top,
14370 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14371 emit_move_insn (opcode_addr, mem);
14372 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14373 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14374 : 0xE8410028, SImode));
14376 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14377 SImode, NULL_RTX, NULL_RTX,
14378 no_toc_save_needed);
14380 mem = gen_frame_mem (Pmode,
14381 gen_rtx_PLUS (Pmode, stack_top,
14382 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14383 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14384 emit_label (no_toc_save_needed);
14387 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14388 and the change to the stack pointer. */
14391 rs6000_emit_stack_tie (void)
14393 rtx mem = gen_frame_mem (BLKmode,
14394 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14396 emit_insn (gen_stack_tie (mem));
14399 /* Emit the correct code for allocating stack space, as insns.
14400 If COPY_R12, make sure a copy of the old frame is left in r12.
14401 The generated code may use hard register 0 as a temporary. */
14404 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14407 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14408 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14409 rtx todec = gen_int_mode (-size, Pmode);
14411 if (INTVAL (todec) != -size)
14413 warning (0, "stack frame too large");
14414 emit_insn (gen_trap ());
14418 if (current_function_limit_stack)
14420 if (REG_P (stack_limit_rtx)
14421 && REGNO (stack_limit_rtx) > 1
14422 && REGNO (stack_limit_rtx) <= 31)
14424 emit_insn (TARGET_32BIT
14425 ? gen_addsi3 (tmp_reg,
14428 : gen_adddi3 (tmp_reg,
14432 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14435 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14437 && DEFAULT_ABI == ABI_V4)
14439 rtx toload = gen_rtx_CONST (VOIDmode,
14440 gen_rtx_PLUS (Pmode,
14444 emit_insn (gen_elf_high (tmp_reg, toload));
14445 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14446 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14450 warning (0, "stack limit expression is not supported");
14453 if (copy_r12 || ! TARGET_UPDATE)
14454 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14460 /* Need a note here so that try_split doesn't get confused. */
14461 if (get_last_insn () == NULL_RTX)
14462 emit_note (NOTE_INSN_DELETED);
14463 insn = emit_move_insn (tmp_reg, todec);
14464 try_split (PATTERN (insn), insn, 0);
14468 insn = emit_insn (TARGET_32BIT
14469 ? gen_movsi_update (stack_reg, stack_reg,
14471 : gen_movdi_di_update (stack_reg, stack_reg,
14472 todec, stack_reg));
14476 insn = emit_insn (TARGET_32BIT
14477 ? gen_addsi3 (stack_reg, stack_reg, todec)
14478 : gen_adddi3 (stack_reg, stack_reg, todec));
14479 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14480 gen_rtx_REG (Pmode, 12));
14483 RTX_FRAME_RELATED_P (insn) = 1;
14485 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14486 gen_rtx_SET (VOIDmode, stack_reg,
14487 gen_rtx_PLUS (Pmode, stack_reg,
14492 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14493 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14494 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14495 deduce these equivalences by itself so it wasn't necessary to hold
14496 its hand so much. */
14499 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14500 rtx reg2, rtx rreg)
14504 /* copy_rtx will not make unique copies of registers, so we need to
14505 ensure we don't have unwanted sharing here. */
14507 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14510 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14512 real = copy_rtx (PATTERN (insn));
14514 if (reg2 != NULL_RTX)
14515 real = replace_rtx (real, reg2, rreg);
14517 real = replace_rtx (real, reg,
14518 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14519 STACK_POINTER_REGNUM),
14522 /* We expect that 'real' is either a SET or a PARALLEL containing
14523 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14524 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14526 if (GET_CODE (real) == SET)
14530 temp = simplify_rtx (SET_SRC (set));
14532 SET_SRC (set) = temp;
14533 temp = simplify_rtx (SET_DEST (set));
14535 SET_DEST (set) = temp;
14536 if (GET_CODE (SET_DEST (set)) == MEM)
14538 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14540 XEXP (SET_DEST (set), 0) = temp;
14547 gcc_assert (GET_CODE (real) == PARALLEL);
14548 for (i = 0; i < XVECLEN (real, 0); i++)
14549 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14551 rtx set = XVECEXP (real, 0, i);
14553 temp = simplify_rtx (SET_SRC (set));
14555 SET_SRC (set) = temp;
14556 temp = simplify_rtx (SET_DEST (set));
14558 SET_DEST (set) = temp;
14559 if (GET_CODE (SET_DEST (set)) == MEM)
14561 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14563 XEXP (SET_DEST (set), 0) = temp;
14565 RTX_FRAME_RELATED_P (set) = 1;
14570 real = spe_synthesize_frame_save (real);
14572 RTX_FRAME_RELATED_P (insn) = 1;
14573 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14578 /* Given an SPE frame note, return a PARALLEL of SETs with the
14579 original note, plus a synthetic register save. */
14582 spe_synthesize_frame_save (rtx real)
14584 rtx synth, offset, reg, real2;
14586 if (GET_CODE (real) != SET
14587 || GET_MODE (SET_SRC (real)) != V2SImode)
14590 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14591 frame related note. The parallel contains a set of the register
14592 being saved, and another set to a synthetic register (n+1200).
14593 This is so we can differentiate between 64-bit and 32-bit saves.
14594 Words cannot describe this nastiness. */
14596 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14597 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14598 && GET_CODE (SET_SRC (real)) == REG);
14601 (set (mem (plus (reg x) (const y)))
14604 (set (mem (plus (reg x) (const y+4)))
14608 real2 = copy_rtx (real);
14609 PUT_MODE (SET_DEST (real2), SImode);
14610 reg = SET_SRC (real2);
14611 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14612 synth = copy_rtx (real2);
14614 if (BYTES_BIG_ENDIAN)
14616 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14617 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14620 reg = SET_SRC (synth);
14622 synth = replace_rtx (synth, reg,
14623 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14625 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14626 synth = replace_rtx (synth, offset,
14627 GEN_INT (INTVAL (offset)
14628 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14630 RTX_FRAME_RELATED_P (synth) = 1;
14631 RTX_FRAME_RELATED_P (real2) = 1;
14632 if (BYTES_BIG_ENDIAN)
14633 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14635 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14640 /* Returns an insn that has a vrsave set operation with the
14641 appropriate CLOBBERs. */
14644 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14647 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14648 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14651 = gen_rtx_SET (VOIDmode,
14653 gen_rtx_UNSPEC_VOLATILE (SImode,
14654 gen_rtvec (2, reg, vrsave),
14655 UNSPECV_SET_VRSAVE));
14659 /* We need to clobber the registers in the mask so the scheduler
14660 does not move sets to VRSAVE before sets of AltiVec registers.
14662 However, if the function receives nonlocal gotos, reload will set
14663 all call saved registers live. We will end up with:
14665 (set (reg 999) (mem))
14666 (parallel [ (set (reg vrsave) (unspec blah))
14667 (clobber (reg 999))])
14669 The clobber will cause the store into reg 999 to be dead, and
14670 flow will attempt to delete an epilogue insn. In this case, we
14671 need an unspec use/set of the register. */
14673 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14674 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14676 if (!epiloguep || call_used_regs [i])
14677 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14678 gen_rtx_REG (V4SImode, i));
14681 rtx reg = gen_rtx_REG (V4SImode, i);
14684 = gen_rtx_SET (VOIDmode,
14686 gen_rtx_UNSPEC (V4SImode,
14687 gen_rtvec (1, reg), 27));
14691 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14693 for (i = 0; i < nclobs; ++i)
14694 XVECEXP (insn, 0, i) = clobs[i];
14699 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14700 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14703 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14704 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14706 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14707 rtx replacea, replaceb;
14709 int_rtx = GEN_INT (offset);
14711 /* Some cases that need register indexed addressing. */
14712 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14713 || (TARGET_E500_DOUBLE && mode == DFmode)
14715 && SPE_VECTOR_MODE (mode)
14716 && !SPE_CONST_OFFSET_OK (offset)))
14718 /* Whomever calls us must make sure r11 is available in the
14719 flow path of instructions in the prologue. */
14720 offset_rtx = gen_rtx_REG (Pmode, 11);
14721 emit_move_insn (offset_rtx, int_rtx);
14723 replacea = offset_rtx;
14724 replaceb = int_rtx;
14728 offset_rtx = int_rtx;
14729 replacea = NULL_RTX;
14730 replaceb = NULL_RTX;
14733 reg = gen_rtx_REG (mode, regno);
14734 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14735 mem = gen_frame_mem (mode, addr);
14737 insn = emit_move_insn (mem, reg);
14739 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14742 /* Emit an offset memory reference suitable for a frame store, while
14743 converting to a valid addressing mode. */
14746 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14748 rtx int_rtx, offset_rtx;
14750 int_rtx = GEN_INT (offset);
14752 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14753 || (TARGET_E500_DOUBLE && mode == DFmode))
14755 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14756 emit_move_insn (offset_rtx, int_rtx);
14759 offset_rtx = int_rtx;
14761 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14764 /* Look for user-defined global regs. We should not save and restore these,
14765 and cannot use stmw/lmw if there are any in its range. */
14768 no_global_regs_above (int first_greg)
14771 for (i = 0; i < 32 - first_greg; i++)
14772 if (global_regs[first_greg + i])
14777 #ifndef TARGET_FIX_AND_CONTINUE
14778 #define TARGET_FIX_AND_CONTINUE 0
14781 /* Determine whether the gp REG is really used. */
14784 rs6000_reg_live_or_pic_offset_p (int reg)
14786 return ((df_regs_ever_live_p (reg)
14787 && (!call_used_regs[reg]
14788 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14789 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14790 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14791 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14792 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
14795 /* Emit function prologue as insns. */
14798 rs6000_emit_prologue (void)
14800 rs6000_stack_t *info = rs6000_stack_info ();
14801 enum machine_mode reg_mode = Pmode;
14802 int reg_size = TARGET_32BIT ? 4 : 8;
14803 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14804 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14805 rtx frame_reg_rtx = sp_reg_rtx;
14806 rtx cr_save_rtx = NULL_RTX;
14808 int saving_FPRs_inline;
14809 int using_store_multiple;
14810 HOST_WIDE_INT sp_offset = 0;
14812 if (TARGET_FIX_AND_CONTINUE)
14814 /* gdb on darwin arranges to forward a function from the old
14815 address by modifying the first 5 instructions of the function
14816 to branch to the overriding function. This is necessary to
14817 permit function pointers that point to the old function to
14818 actually forward to the new function. */
14819 emit_insn (gen_nop ());
14820 emit_insn (gen_nop ());
14821 emit_insn (gen_nop ());
14822 emit_insn (gen_nop ());
14823 emit_insn (gen_nop ());
14826 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14828 reg_mode = V2SImode;
14832 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14833 && (!TARGET_SPE_ABI
14834 || info->spe_64bit_regs_used == 0)
14835 && info->first_gp_reg_save < 31
14836 && no_global_regs_above (info->first_gp_reg_save));
14837 saving_FPRs_inline = (info->first_fp_reg_save == 64
14838 || FP_SAVE_INLINE (info->first_fp_reg_save)
14839 || current_function_calls_eh_return
14840 || cfun->machine->ra_need_lr);
14842 /* For V.4, update stack before we do any saving and set back pointer. */
14843 if (! WORLD_SAVE_P (info)
14845 && (DEFAULT_ABI == ABI_V4
14846 || current_function_calls_eh_return))
14848 if (info->total_size < 32767)
14849 sp_offset = info->total_size;
14851 frame_reg_rtx = frame_ptr_rtx;
14852 rs6000_emit_allocate_stack (info->total_size,
14853 (frame_reg_rtx != sp_reg_rtx
14854 && (info->cr_save_p
14856 || info->first_fp_reg_save < 64
14857 || info->first_gp_reg_save < 32
14859 if (frame_reg_rtx != sp_reg_rtx)
14860 rs6000_emit_stack_tie ();
14863 /* Handle world saves specially here. */
14864 if (WORLD_SAVE_P (info))
14871 /* save_world expects lr in r0. */
14872 reg0 = gen_rtx_REG (Pmode, 0);
14873 if (info->lr_save_p)
14875 insn = emit_move_insn (reg0,
14876 gen_rtx_REG (Pmode, LR_REGNO));
14877 RTX_FRAME_RELATED_P (insn) = 1;
14880 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14881 assumptions about the offsets of various bits of the stack
14883 gcc_assert (info->gp_save_offset == -220
14884 && info->fp_save_offset == -144
14885 && info->lr_save_offset == 8
14886 && info->cr_save_offset == 4
14889 && (!current_function_calls_eh_return
14890 || info->ehrd_offset == -432)
14891 && info->vrsave_save_offset == -224
14892 && info->altivec_save_offset == -416);
14894 treg = gen_rtx_REG (SImode, 11);
14895 emit_move_insn (treg, GEN_INT (-info->total_size));
14897 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14898 in R11. It also clobbers R12, so beware! */
14900 /* Preserve CR2 for save_world prologues */
14902 sz += 32 - info->first_gp_reg_save;
14903 sz += 64 - info->first_fp_reg_save;
14904 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14905 p = rtvec_alloc (sz);
14907 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14908 gen_rtx_REG (SImode,
14910 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14911 gen_rtx_SYMBOL_REF (Pmode,
14913 /* We do floats first so that the instruction pattern matches
14915 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14917 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14918 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14919 GEN_INT (info->fp_save_offset
14920 + sp_offset + 8 * i));
14921 rtx mem = gen_frame_mem (DFmode, addr);
14923 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14925 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14927 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14928 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14929 GEN_INT (info->altivec_save_offset
14930 + sp_offset + 16 * i));
14931 rtx mem = gen_frame_mem (V4SImode, addr);
14933 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14935 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14937 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14938 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14939 GEN_INT (info->gp_save_offset
14940 + sp_offset + reg_size * i));
14941 rtx mem = gen_frame_mem (reg_mode, addr);
14943 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14947 /* CR register traditionally saved as CR2. */
14948 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14949 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14950 GEN_INT (info->cr_save_offset
14952 rtx mem = gen_frame_mem (reg_mode, addr);
14954 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14956 /* Explain about use of R0. */
14957 if (info->lr_save_p)
14959 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14960 GEN_INT (info->lr_save_offset
14962 rtx mem = gen_frame_mem (reg_mode, addr);
14964 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14966 /* Explain what happens to the stack pointer. */
14968 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14969 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14972 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14973 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14974 treg, GEN_INT (-info->total_size));
14975 sp_offset = info->total_size;
14978 /* If we use the link register, get it into r0. */
14979 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14981 rtx addr, reg, mem;
14983 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14984 gen_rtx_REG (Pmode, LR_REGNO));
14985 RTX_FRAME_RELATED_P (insn) = 1;
14987 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14988 GEN_INT (info->lr_save_offset + sp_offset));
14989 reg = gen_rtx_REG (Pmode, 0);
14990 mem = gen_rtx_MEM (Pmode, addr);
14991 /* This should not be of rs6000_sr_alias_set, because of
14992 __builtin_return_address. */
14994 insn = emit_move_insn (mem, reg);
14995 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14996 NULL_RTX, NULL_RTX);
14999 /* If we need to save CR, put it into r12. */
15000 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
15004 cr_save_rtx = gen_rtx_REG (SImode, 12);
15005 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15006 RTX_FRAME_RELATED_P (insn) = 1;
15007 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15008 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15009 But that's OK. All we have to do is specify that _one_ condition
15010 code register is saved in this stack slot. The thrower's epilogue
15011 will then restore all the call-saved registers.
15012 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15013 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
15014 gen_rtx_REG (SImode, CR2_REGNO));
15015 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15020 /* Do any required saving of fpr's. If only one or two to save, do
15021 it ourselves. Otherwise, call function. */
15022 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
15025 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15026 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15027 && ! call_used_regs[info->first_fp_reg_save+i]))
15028 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
15029 info->first_fp_reg_save + i,
15030 info->fp_save_offset + sp_offset + 8 * i,
15033 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
15037 const char *alloc_rname;
15039 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
15041 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
15042 gen_rtx_REG (Pmode,
15044 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
15045 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
15046 alloc_rname = ggc_strdup (rname);
15047 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15048 gen_rtx_SYMBOL_REF (Pmode,
15050 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15052 rtx addr, reg, mem;
15053 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15054 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15055 GEN_INT (info->fp_save_offset
15056 + sp_offset + 8*i));
15057 mem = gen_frame_mem (DFmode, addr);
15059 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
15061 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15062 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15063 NULL_RTX, NULL_RTX);
15066 /* Save GPRs. This is done as a PARALLEL if we are using
15067 the store-multiple instructions. */
15068 if (!WORLD_SAVE_P (info) && using_store_multiple)
15072 p = rtvec_alloc (32 - info->first_gp_reg_save);
15073 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15075 rtx addr, reg, mem;
15076 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15077 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15078 GEN_INT (info->gp_save_offset
15081 mem = gen_frame_mem (reg_mode, addr);
15083 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
15085 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15086 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15087 NULL_RTX, NULL_RTX);
15089 else if (!WORLD_SAVE_P (info)
15091 && info->spe_64bit_regs_used != 0
15092 && info->first_gp_reg_save != 32)
15095 rtx spe_save_area_ptr;
15096 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15097 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15098 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15100 /* Determine whether we can address all of the registers that need
15101 to be saved with an offset from the stack pointer that fits in
15102 the small const field for SPE memory instructions. */
15103 int spe_regs_addressable_via_sp
15104 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15105 + (32 - info->first_gp_reg_save - 1) * reg_size);
15108 if (spe_regs_addressable_via_sp)
15110 spe_save_area_ptr = sp_reg_rtx;
15111 spe_offset = info->spe_gp_save_offset + sp_offset;
15115 /* Make r11 point to the start of the SPE save area. We need
15116 to be careful here if r11 is holding the static chain. If
15117 it is, then temporarily save it in r0. We would use r0 as
15118 our base register here, but using r0 as a base register in
15119 loads and stores means something different from what we
15121 if (using_static_chain_p)
15123 rtx r0 = gen_rtx_REG (Pmode, 0);
15125 gcc_assert (info->first_gp_reg_save > 11);
15127 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15130 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15131 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
15132 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15137 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15138 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15140 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15141 rtx offset, addr, mem;
15143 /* We're doing all this to ensure that the offset fits into
15144 the immediate offset of 'evstdd'. */
15145 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15147 offset = GEN_INT (reg_size * i + spe_offset);
15148 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15149 mem = gen_rtx_MEM (V2SImode, addr);
15151 insn = emit_move_insn (mem, reg);
15153 rs6000_frame_related (insn, spe_save_area_ptr,
15154 info->spe_gp_save_offset
15155 + sp_offset + reg_size * i,
15156 offset, const0_rtx);
15159 /* Move the static chain pointer back. */
15160 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15161 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15163 else if (!WORLD_SAVE_P (info))
15166 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15167 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15169 rtx addr, reg, mem;
15170 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15172 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15173 GEN_INT (info->gp_save_offset
15176 mem = gen_frame_mem (reg_mode, addr);
15178 insn = emit_move_insn (mem, reg);
15179 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15180 NULL_RTX, NULL_RTX);
15184 /* ??? There's no need to emit actual instructions here, but it's the
15185 easiest way to get the frame unwind information emitted. */
15186 if (current_function_calls_eh_return)
15188 unsigned int i, regno;
15190 /* In AIX ABI we need to pretend we save r2 here. */
15193 rtx addr, reg, mem;
15195 reg = gen_rtx_REG (reg_mode, 2);
15196 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15197 GEN_INT (sp_offset + 5 * reg_size));
15198 mem = gen_frame_mem (reg_mode, addr);
15200 insn = emit_move_insn (mem, reg);
15201 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15202 NULL_RTX, NULL_RTX);
15203 PATTERN (insn) = gen_blockage ();
15208 regno = EH_RETURN_DATA_REGNO (i);
15209 if (regno == INVALID_REGNUM)
15212 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15213 info->ehrd_offset + sp_offset
15214 + reg_size * (int) i,
15219 /* Save CR if we use any that must be preserved. */
15220 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15222 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15223 GEN_INT (info->cr_save_offset + sp_offset));
15224 rtx mem = gen_frame_mem (SImode, addr);
15225 /* See the large comment above about why CR2_REGNO is used. */
15226 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15228 /* If r12 was used to hold the original sp, copy cr into r0 now
15230 if (REGNO (frame_reg_rtx) == 12)
15234 cr_save_rtx = gen_rtx_REG (SImode, 0);
15235 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15236 RTX_FRAME_RELATED_P (insn) = 1;
15237 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15238 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15243 insn = emit_move_insn (mem, cr_save_rtx);
15245 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15246 NULL_RTX, NULL_RTX);
15249 /* Update stack and set back pointer unless this is V.4,
15250 for which it was done previously. */
15251 if (!WORLD_SAVE_P (info) && info->push_p
15252 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15254 if (info->total_size < 32767)
15255 sp_offset = info->total_size;
15257 frame_reg_rtx = frame_ptr_rtx;
15258 rs6000_emit_allocate_stack (info->total_size,
15259 (frame_reg_rtx != sp_reg_rtx
15260 && ((info->altivec_size != 0)
15261 || (info->vrsave_mask != 0)
15263 if (frame_reg_rtx != sp_reg_rtx)
15264 rs6000_emit_stack_tie ();
15267 /* Set frame pointer, if needed. */
15268 if (frame_pointer_needed)
15270 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15272 RTX_FRAME_RELATED_P (insn) = 1;
15275 /* Save AltiVec registers if needed. Save here because the red zone does
15276 not include AltiVec registers. */
15277 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15281 /* There should be a non inline version of this, for when we
15282 are saving lots of vector registers. */
15283 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15284 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15286 rtx areg, savereg, mem;
15289 offset = info->altivec_save_offset + sp_offset
15290 + 16 * (i - info->first_altivec_reg_save);
15292 savereg = gen_rtx_REG (V4SImode, i);
15294 areg = gen_rtx_REG (Pmode, 0);
15295 emit_move_insn (areg, GEN_INT (offset));
15297 /* AltiVec addressing mode is [reg+reg]. */
15298 mem = gen_frame_mem (V4SImode,
15299 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15301 insn = emit_move_insn (mem, savereg);
15303 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15304 areg, GEN_INT (offset));
15308 /* VRSAVE is a bit vector representing which AltiVec registers
15309 are used. The OS uses this to determine which vector
15310 registers to save on a context switch. We need to save
15311 VRSAVE on the stack frame, add whatever AltiVec registers we
15312 used in this function, and do the corresponding magic in the
15315 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15316 && info->vrsave_mask != 0)
15318 rtx reg, mem, vrsave;
15321 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15322 as frame_reg_rtx and r11 as the static chain pointer for
15323 nested functions. */
15324 reg = gen_rtx_REG (SImode, 0);
15325 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15327 emit_insn (gen_get_vrsave_internal (reg));
15329 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15331 if (!WORLD_SAVE_P (info))
15334 offset = info->vrsave_save_offset + sp_offset;
15335 mem = gen_frame_mem (SImode,
15336 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15337 GEN_INT (offset)));
15338 insn = emit_move_insn (mem, reg);
15341 /* Include the registers in the mask. */
15342 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15344 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15347 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15348 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15349 || (DEFAULT_ABI == ABI_V4
15350 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15351 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15353 /* If emit_load_toc_table will use the link register, we need to save
15354 it. We use R12 for this purpose because emit_load_toc_table
15355 can use register 0. This allows us to use a plain 'blr' to return
15356 from the procedure more often. */
15357 int save_LR_around_toc_setup = (TARGET_ELF
15358 && DEFAULT_ABI != ABI_AIX
15360 && ! info->lr_save_p
15361 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15362 if (save_LR_around_toc_setup)
15364 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15366 insn = emit_move_insn (frame_ptr_rtx, lr);
15367 RTX_FRAME_RELATED_P (insn) = 1;
15369 rs6000_emit_load_toc_table (TRUE);
15371 insn = emit_move_insn (lr, frame_ptr_rtx);
15372 RTX_FRAME_RELATED_P (insn) = 1;
15375 rs6000_emit_load_toc_table (TRUE);
15379 if (DEFAULT_ABI == ABI_DARWIN
15380 && flag_pic && current_function_uses_pic_offset_table)
15382 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15383 rtx src = machopic_function_base_sym ();
15385 /* Save and restore LR locally around this call (in R0). */
15386 if (!info->lr_save_p)
15387 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15389 emit_insn (gen_load_macho_picbase (src));
15391 emit_move_insn (gen_rtx_REG (Pmode,
15392 RS6000_PIC_OFFSET_TABLE_REGNUM),
15395 if (!info->lr_save_p)
15396 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15401 /* Write function prologue. */
15404 rs6000_output_function_prologue (FILE *file,
15405 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15407 rs6000_stack_t *info = rs6000_stack_info ();
15409 if (TARGET_DEBUG_STACK)
15410 debug_stack_info (info);
15412 /* Write .extern for any function we will call to save and restore
15414 if (info->first_fp_reg_save < 64
15415 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15416 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15417 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15418 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15419 RESTORE_FP_SUFFIX);
15421 /* Write .extern for AIX common mode routines, if needed. */
15422 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15424 fputs ("\t.extern __mulh\n", file);
15425 fputs ("\t.extern __mull\n", file);
15426 fputs ("\t.extern __divss\n", file);
15427 fputs ("\t.extern __divus\n", file);
15428 fputs ("\t.extern __quoss\n", file);
15429 fputs ("\t.extern __quous\n", file);
15430 common_mode_defined = 1;
15433 if (! HAVE_prologue)
15437 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15438 the "toplevel" insn chain. */
15439 emit_note (NOTE_INSN_DELETED);
15440 rs6000_emit_prologue ();
15441 emit_note (NOTE_INSN_DELETED);
15443 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15447 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15449 INSN_ADDRESSES_NEW (insn, addr);
15454 if (TARGET_DEBUG_STACK)
15455 debug_rtx_list (get_insns (), 100);
15456 final (get_insns (), file, FALSE);
15460 rs6000_pic_labelno++;
15463 /* Emit function epilogue as insns.
15465 At present, dwarf2out_frame_debug_expr doesn't understand
15466 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15467 anywhere in the epilogue. Most of the insns below would in any case
15468 need special notes to explain where r11 is in relation to the stack. */
15471 rs6000_emit_epilogue (int sibcall)
15473 rs6000_stack_t *info;
15474 int restoring_FPRs_inline;
15475 int using_load_multiple;
15476 int using_mtcr_multiple;
15477 int use_backchain_to_restore_sp;
15479 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15480 rtx frame_reg_rtx = sp_reg_rtx;
15481 enum machine_mode reg_mode = Pmode;
15482 int reg_size = TARGET_32BIT ? 4 : 8;
15485 info = rs6000_stack_info ();
15487 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15489 reg_mode = V2SImode;
15493 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15494 && (!TARGET_SPE_ABI
15495 || info->spe_64bit_regs_used == 0)
15496 && info->first_gp_reg_save < 31
15497 && no_global_regs_above (info->first_gp_reg_save));
15498 restoring_FPRs_inline = (sibcall
15499 || current_function_calls_eh_return
15500 || info->first_fp_reg_save == 64
15501 || FP_SAVE_INLINE (info->first_fp_reg_save));
15502 use_backchain_to_restore_sp = (frame_pointer_needed
15503 || current_function_calls_alloca
15504 || info->total_size > 32767);
15505 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15506 || rs6000_cpu == PROCESSOR_PPC603
15507 || rs6000_cpu == PROCESSOR_PPC750
15510 if (WORLD_SAVE_P (info))
15514 const char *alloc_rname;
15517 /* eh_rest_world_r10 will return to the location saved in the LR
15518 stack slot (which is not likely to be our caller.)
15519 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15520 rest_world is similar, except any R10 parameter is ignored.
15521 The exception-handling stuff that was here in 2.95 is no
15522 longer necessary. */
15526 + 32 - info->first_gp_reg_save
15527 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15528 + 63 + 1 - info->first_fp_reg_save);
15530 strcpy (rname, ((current_function_calls_eh_return) ?
15531 "*eh_rest_world_r10" : "*rest_world"));
15532 alloc_rname = ggc_strdup (rname);
15535 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15536 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15537 gen_rtx_REG (Pmode,
15540 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15541 /* The instruction pattern requires a clobber here;
15542 it is shared with the restVEC helper. */
15544 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15547 /* CR register traditionally saved as CR2. */
15548 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15549 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15550 GEN_INT (info->cr_save_offset));
15551 rtx mem = gen_frame_mem (reg_mode, addr);
15553 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15556 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15558 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15559 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15560 GEN_INT (info->gp_save_offset
15562 rtx mem = gen_frame_mem (reg_mode, addr);
15564 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15566 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15568 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15569 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15570 GEN_INT (info->altivec_save_offset
15572 rtx mem = gen_frame_mem (V4SImode, addr);
15574 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15576 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15578 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15579 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15580 GEN_INT (info->fp_save_offset
15582 rtx mem = gen_frame_mem (DFmode, addr);
15584 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15587 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15589 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15591 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15593 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15595 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15596 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15601 /* Set sp_offset based on the stack push from the prologue. */
15602 if (info->total_size < 32767)
15603 sp_offset = info->total_size;
15605 /* Restore AltiVec registers if needed. */
15606 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15610 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15611 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15613 rtx addr, areg, mem;
15615 areg = gen_rtx_REG (Pmode, 0);
15617 (areg, GEN_INT (info->altivec_save_offset
15619 + 16 * (i - info->first_altivec_reg_save)));
15621 /* AltiVec addressing mode is [reg+reg]. */
15622 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15623 mem = gen_frame_mem (V4SImode, addr);
15625 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15629 /* Restore VRSAVE if needed. */
15630 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15631 && info->vrsave_mask != 0)
15633 rtx addr, mem, reg;
15635 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15636 GEN_INT (info->vrsave_save_offset + sp_offset));
15637 mem = gen_frame_mem (SImode, addr);
15638 reg = gen_rtx_REG (SImode, 12);
15639 emit_move_insn (reg, mem);
15641 emit_insn (generate_set_vrsave (reg, info, 1));
15646 /* If we have a frame pointer, a call to alloca, or a large stack
15647 frame, restore the old stack pointer using the backchain. Otherwise,
15648 we know what size to update it with. */
15649 if (use_backchain_to_restore_sp)
15651 /* Under V.4, don't reset the stack pointer until after we're done
15652 loading the saved registers. */
15653 if (DEFAULT_ABI == ABI_V4)
15654 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15656 emit_move_insn (frame_reg_rtx,
15657 gen_rtx_MEM (Pmode, sp_reg_rtx));
15659 else if (info->push_p)
15661 if (DEFAULT_ABI == ABI_V4
15662 || current_function_calls_eh_return)
15663 sp_offset = info->total_size;
15666 emit_insn (TARGET_32BIT
15667 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15668 GEN_INT (info->total_size))
15669 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15670 GEN_INT (info->total_size)));
15674 /* Get the old lr if we saved it. */
15675 if (info->lr_save_p)
15677 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15678 info->lr_save_offset + sp_offset);
15680 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15683 /* Get the old cr if we saved it. */
15684 if (info->cr_save_p)
15686 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15687 GEN_INT (info->cr_save_offset + sp_offset));
15688 rtx mem = gen_frame_mem (SImode, addr);
15690 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15693 /* Set LR here to try to overlap restores below. */
15694 if (info->lr_save_p)
15695 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
15696 gen_rtx_REG (Pmode, 0));
15698 /* Load exception handler data registers, if needed. */
15699 if (current_function_calls_eh_return)
15701 unsigned int i, regno;
15705 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15706 GEN_INT (sp_offset + 5 * reg_size));
15707 rtx mem = gen_frame_mem (reg_mode, addr);
15709 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15716 regno = EH_RETURN_DATA_REGNO (i);
15717 if (regno == INVALID_REGNUM)
15720 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15721 info->ehrd_offset + sp_offset
15722 + reg_size * (int) i);
15724 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15728 /* Restore GPRs. This is done as a PARALLEL if we are using
15729 the load-multiple instructions. */
15730 if (using_load_multiple)
15733 p = rtvec_alloc (32 - info->first_gp_reg_save);
15734 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15736 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15737 GEN_INT (info->gp_save_offset
15740 rtx mem = gen_frame_mem (reg_mode, addr);
15743 gen_rtx_SET (VOIDmode,
15744 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15747 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15749 else if (TARGET_SPE_ABI
15750 && info->spe_64bit_regs_used != 0
15751 && info->first_gp_reg_save != 32)
15753 rtx spe_save_area_ptr;
15754 /* Determine whether we can address all of the registers that need
15755 to be saved with an offset from the stack pointer that fits in
15756 the small const field for SPE memory instructions. */
15757 int spe_regs_addressable_via_sp
15758 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15759 + (32 - info->first_gp_reg_save - 1) * reg_size);
15762 if (spe_regs_addressable_via_sp)
15764 spe_save_area_ptr = frame_reg_rtx;
15765 spe_offset = info->spe_gp_save_offset + sp_offset;
15769 /* Make r11 point to the start of the SPE save area. We worried about
15770 not clobbering it when we were saving registers in the prologue.
15771 There's no need to worry here because the static chain is passed
15772 anew to every function. */
15773 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15775 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15776 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15781 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15782 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15784 rtx offset, addr, mem;
15786 /* We're doing all this to ensure that the immediate offset
15787 fits into the immediate field of 'evldd'. */
15788 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
15790 offset = GEN_INT (spe_offset + reg_size * i);
15791 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15792 mem = gen_rtx_MEM (V2SImode, addr);
15794 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15799 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15800 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15802 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15803 GEN_INT (info->gp_save_offset
15806 rtx mem = gen_frame_mem (reg_mode, addr);
15808 emit_move_insn (gen_rtx_REG (reg_mode,
15809 info->first_gp_reg_save + i), mem);
15812 /* Restore fpr's if we need to do it without calling a function. */
15813 if (restoring_FPRs_inline)
15814 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15815 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15816 && ! call_used_regs[info->first_fp_reg_save+i]))
15819 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15820 GEN_INT (info->fp_save_offset
15823 mem = gen_frame_mem (DFmode, addr);
15825 emit_move_insn (gen_rtx_REG (DFmode,
15826 info->first_fp_reg_save + i),
15830 /* If we saved cr, restore it here. Just those that were used. */
15831 if (info->cr_save_p)
15833 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15836 if (using_mtcr_multiple)
15838 for (i = 0; i < 8; i++)
15839 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15841 gcc_assert (count);
15844 if (using_mtcr_multiple && count > 1)
15849 p = rtvec_alloc (count);
15852 for (i = 0; i < 8; i++)
15853 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15855 rtvec r = rtvec_alloc (2);
15856 RTVEC_ELT (r, 0) = r12_rtx;
15857 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15858 RTVEC_ELT (p, ndx) =
15859 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15860 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15863 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15864 gcc_assert (ndx == count);
15867 for (i = 0; i < 8; i++)
15868 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15870 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15876 /* If this is V.4, unwind the stack pointer after all of the loads
15878 if (frame_reg_rtx != sp_reg_rtx)
15880 /* This blockage is needed so that sched doesn't decide to move
15881 the sp change before the register restores. */
15882 rs6000_emit_stack_tie ();
15884 && info->spe_64bit_regs_used != 0
15885 && info->first_gp_reg_save != 32)
15886 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
15887 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
15889 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15891 else if (sp_offset != 0)
15892 emit_insn (TARGET_32BIT
15893 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15894 GEN_INT (sp_offset))
15895 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15896 GEN_INT (sp_offset)));
15898 if (current_function_calls_eh_return)
15900 rtx sa = EH_RETURN_STACKADJ_RTX;
15901 emit_insn (TARGET_32BIT
15902 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15903 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15909 if (! restoring_FPRs_inline)
15910 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15912 p = rtvec_alloc (2);
15914 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15915 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15916 gen_rtx_REG (Pmode,
15919 /* If we have to restore more than two FP registers, branch to the
15920 restore function. It will return to our caller. */
15921 if (! restoring_FPRs_inline)
15925 const char *alloc_rname;
15927 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15928 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15929 alloc_rname = ggc_strdup (rname);
15930 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15931 gen_rtx_SYMBOL_REF (Pmode,
15934 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15937 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15938 GEN_INT (info->fp_save_offset + 8*i));
15939 mem = gen_frame_mem (DFmode, addr);
15941 RTVEC_ELT (p, i+3) =
15942 gen_rtx_SET (VOIDmode,
15943 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15948 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15952 /* Write function epilogue. */
15955 rs6000_output_function_epilogue (FILE *file,
15956 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15958 if (! HAVE_epilogue)
15960 rtx insn = get_last_insn ();
15961 /* If the last insn was a BARRIER, we don't have to write anything except
15962 the trace table. */
15963 if (GET_CODE (insn) == NOTE)
15964 insn = prev_nonnote_insn (insn);
15965 if (insn == 0 || GET_CODE (insn) != BARRIER)
15967 /* This is slightly ugly, but at least we don't have two
15968 copies of the epilogue-emitting code. */
15971 /* A NOTE_INSN_DELETED is supposed to be at the start
15972 and end of the "toplevel" insn chain. */
15973 emit_note (NOTE_INSN_DELETED);
15974 rs6000_emit_epilogue (FALSE);
15975 emit_note (NOTE_INSN_DELETED);
15977 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15981 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15983 INSN_ADDRESSES_NEW (insn, addr);
15988 if (TARGET_DEBUG_STACK)
15989 debug_rtx_list (get_insns (), 100);
15990 final (get_insns (), file, FALSE);
15996 macho_branch_islands ();
15997 /* Mach-O doesn't support labels at the end of objects, so if
15998 it looks like we might want one, insert a NOP. */
16000 rtx insn = get_last_insn ();
16003 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
16004 insn = PREV_INSN (insn);
16008 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
16009 fputs ("\tnop\n", file);
16013 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16016 We don't output a traceback table if -finhibit-size-directive was
16017 used. The documentation for -finhibit-size-directive reads
16018 ``don't output a @code{.size} assembler directive, or anything
16019 else that would cause trouble if the function is split in the
16020 middle, and the two halves are placed at locations far apart in
16021 memory.'' The traceback table has this property, since it
16022 includes the offset from the start of the function to the
16023 traceback table itself.
16025 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16026 different traceback table. */
16027 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
16028 && rs6000_traceback != traceback_none && !current_function_is_thunk)
16030 const char *fname = NULL;
16031 const char *language_string = lang_hooks.name;
16032 int fixed_parms = 0, float_parms = 0, parm_info = 0;
16034 int optional_tbtab;
16035 rs6000_stack_t *info = rs6000_stack_info ();
16037 if (rs6000_traceback == traceback_full)
16038 optional_tbtab = 1;
16039 else if (rs6000_traceback == traceback_part)
16040 optional_tbtab = 0;
16042 optional_tbtab = !optimize_size && !TARGET_ELF;
16044 if (optional_tbtab)
16046 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
16047 while (*fname == '.') /* V.4 encodes . in the name */
16050 /* Need label immediately before tbtab, so we can compute
16051 its offset from the function start. */
16052 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16053 ASM_OUTPUT_LABEL (file, fname);
16056 /* The .tbtab pseudo-op can only be used for the first eight
16057 expressions, since it can't handle the possibly variable
16058 length fields that follow. However, if you omit the optional
16059 fields, the assembler outputs zeros for all optional fields
16060 anyways, giving each variable length field is minimum length
16061 (as defined in sys/debug.h). Thus we can not use the .tbtab
16062 pseudo-op at all. */
16064 /* An all-zero word flags the start of the tbtab, for debuggers
16065 that have to find it by searching forward from the entry
16066 point or from the current pc. */
16067 fputs ("\t.long 0\n", file);
16069 /* Tbtab format type. Use format type 0. */
16070 fputs ("\t.byte 0,", file);
16072 /* Language type. Unfortunately, there does not seem to be any
16073 official way to discover the language being compiled, so we
16074 use language_string.
16075 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16076 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16077 a number, so for now use 9. */
16078 if (! strcmp (language_string, "GNU C"))
16080 else if (! strcmp (language_string, "GNU F77")
16081 || ! strcmp (language_string, "GNU F95"))
16083 else if (! strcmp (language_string, "GNU Pascal"))
16085 else if (! strcmp (language_string, "GNU Ada"))
16087 else if (! strcmp (language_string, "GNU C++")
16088 || ! strcmp (language_string, "GNU Objective-C++"))
16090 else if (! strcmp (language_string, "GNU Java"))
16092 else if (! strcmp (language_string, "GNU Objective-C"))
16095 gcc_unreachable ();
16096 fprintf (file, "%d,", i);
16098 /* 8 single bit fields: global linkage (not set for C extern linkage,
16099 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16100 from start of procedure stored in tbtab, internal function, function
16101 has controlled storage, function has no toc, function uses fp,
16102 function logs/aborts fp operations. */
16103 /* Assume that fp operations are used if any fp reg must be saved. */
16104 fprintf (file, "%d,",
16105 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16107 /* 6 bitfields: function is interrupt handler, name present in
16108 proc table, function calls alloca, on condition directives
16109 (controls stack walks, 3 bits), saves condition reg, saves
16111 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16112 set up as a frame pointer, even when there is no alloca call. */
16113 fprintf (file, "%d,",
16114 ((optional_tbtab << 6)
16115 | ((optional_tbtab & frame_pointer_needed) << 5)
16116 | (info->cr_save_p << 1)
16117 | (info->lr_save_p)));
16119 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16121 fprintf (file, "%d,",
16122 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16124 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16125 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16127 if (optional_tbtab)
16129 /* Compute the parameter info from the function decl argument
16132 int next_parm_info_bit = 31;
16134 for (decl = DECL_ARGUMENTS (current_function_decl);
16135 decl; decl = TREE_CHAIN (decl))
16137 rtx parameter = DECL_INCOMING_RTL (decl);
16138 enum machine_mode mode = GET_MODE (parameter);
16140 if (GET_CODE (parameter) == REG)
16142 if (SCALAR_FLOAT_MODE_P (mode))
16162 gcc_unreachable ();
16165 /* If only one bit will fit, don't or in this entry. */
16166 if (next_parm_info_bit > 0)
16167 parm_info |= (bits << (next_parm_info_bit - 1));
16168 next_parm_info_bit -= 2;
16172 fixed_parms += ((GET_MODE_SIZE (mode)
16173 + (UNITS_PER_WORD - 1))
16175 next_parm_info_bit -= 1;
16181 /* Number of fixed point parameters. */
16182 /* This is actually the number of words of fixed point parameters; thus
16183 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16184 fprintf (file, "%d,", fixed_parms);
16186 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16188 /* This is actually the number of fp registers that hold parameters;
16189 and thus the maximum value is 13. */
16190 /* Set parameters on stack bit if parameters are not in their original
16191 registers, regardless of whether they are on the stack? Xlc
16192 seems to set the bit when not optimizing. */
16193 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16195 if (! optional_tbtab)
16198 /* Optional fields follow. Some are variable length. */
16200 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16201 11 double float. */
16202 /* There is an entry for each parameter in a register, in the order that
16203 they occur in the parameter list. Any intervening arguments on the
16204 stack are ignored. If the list overflows a long (max possible length
16205 34 bits) then completely leave off all elements that don't fit. */
16206 /* Only emit this long if there was at least one parameter. */
16207 if (fixed_parms || float_parms)
16208 fprintf (file, "\t.long %d\n", parm_info);
16210 /* Offset from start of code to tb table. */
16211 fputs ("\t.long ", file);
16212 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16214 RS6000_OUTPUT_BASENAME (file, fname);
16216 assemble_name (file, fname);
16218 rs6000_output_function_entry (file, fname);
16221 /* Interrupt handler mask. */
16222 /* Omit this long, since we never set the interrupt handler bit
16225 /* Number of CTL (controlled storage) anchors. */
16226 /* Omit this long, since the has_ctl bit is never set above. */
16228 /* Displacement into stack of each CTL anchor. */
16229 /* Omit this list of longs, because there are no CTL anchors. */
16231 /* Length of function name. */
16234 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16236 /* Function name. */
16237 assemble_string (fname, strlen (fname));
16239 /* Register for alloca automatic storage; this is always reg 31.
16240 Only emit this if the alloca bit was set above. */
16241 if (frame_pointer_needed)
16242 fputs ("\t.byte 31\n", file);
16244 fputs ("\t.align 2\n", file);
16248 /* A C compound statement that outputs the assembler code for a thunk
16249 function, used to implement C++ virtual function calls with
16250 multiple inheritance. The thunk acts as a wrapper around a virtual
16251 function, adjusting the implicit object parameter before handing
16252 control off to the real function.
16254 First, emit code to add the integer DELTA to the location that
16255 contains the incoming first argument. Assume that this argument
16256 contains a pointer, and is the one used to pass the `this' pointer
16257 in C++. This is the incoming argument *before* the function
16258 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16259 values of all other incoming arguments.
16261 After the addition, emit code to jump to FUNCTION, which is a
16262 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16263 not touch the return address. Hence returning from FUNCTION will
16264 return to whoever called the current `thunk'.
16266 The effect must be as if FUNCTION had been called directly with the
16267 adjusted first argument. This macro is responsible for emitting
16268 all of the code for a thunk function; output_function_prologue()
16269 and output_function_epilogue() are not invoked.
16271 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16272 been extracted from it.) It might possibly be useful on some
16273 targets, but probably not.
16275 If you do not define this macro, the target-independent code in the
16276 C++ frontend will generate a less efficient heavyweight thunk that
16277 calls FUNCTION instead of jumping to it. The generic approach does
16278 not support varargs. */
16281 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16282 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16285 rtx this, insn, funexp;
16287 reload_completed = 1;
16288 epilogue_completed = 1;
16290 /* Mark the end of the (empty) prologue. */
16291 emit_note (NOTE_INSN_PROLOGUE_END);
16293 /* Find the "this" pointer. If the function returns a structure,
16294 the structure return pointer is in r3. */
16295 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16296 this = gen_rtx_REG (Pmode, 4);
16298 this = gen_rtx_REG (Pmode, 3);
16300 /* Apply the constant offset, if required. */
16303 rtx delta_rtx = GEN_INT (delta);
16304 emit_insn (TARGET_32BIT
16305 ? gen_addsi3 (this, this, delta_rtx)
16306 : gen_adddi3 (this, this, delta_rtx));
16309 /* Apply the offset from the vtable, if required. */
16312 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16313 rtx tmp = gen_rtx_REG (Pmode, 12);
16315 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16316 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16318 emit_insn (TARGET_32BIT
16319 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16320 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16321 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16325 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16327 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16329 emit_insn (TARGET_32BIT
16330 ? gen_addsi3 (this, this, tmp)
16331 : gen_adddi3 (this, this, tmp));
16334 /* Generate a tail call to the target function. */
16335 if (!TREE_USED (function))
16337 assemble_external (function);
16338 TREE_USED (function) = 1;
16340 funexp = XEXP (DECL_RTL (function), 0);
16341 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16344 if (MACHOPIC_INDIRECT)
16345 funexp = machopic_indirect_call_target (funexp);
16348 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16349 generate sibcall RTL explicitly. */
16350 insn = emit_call_insn (
16351 gen_rtx_PARALLEL (VOIDmode,
16353 gen_rtx_CALL (VOIDmode,
16354 funexp, const0_rtx),
16355 gen_rtx_USE (VOIDmode, const0_rtx),
16356 gen_rtx_USE (VOIDmode,
16357 gen_rtx_REG (SImode,
16359 gen_rtx_RETURN (VOIDmode))));
16360 SIBLING_CALL_P (insn) = 1;
16363 /* Run just enough of rest_of_compilation to get the insns emitted.
16364 There's not really enough bulk here to make other passes such as
16365 instruction scheduling worth while. Note that use_thunk calls
16366 assemble_start_function and assemble_end_function. */
16367 insn = get_insns ();
16368 insn_locators_alloc ();
16369 shorten_branches (insn);
16370 final_start_function (insn, file, 1);
16371 final (insn, file, 1);
16372 final_end_function ();
16374 reload_completed = 0;
16375 epilogue_completed = 0;
16378 /* A quick summary of the various types of 'constant-pool tables'
16381 Target Flags Name One table per
16382 AIX (none) AIX TOC object file
16383 AIX -mfull-toc AIX TOC object file
16384 AIX -mminimal-toc AIX minimal TOC translation unit
16385 SVR4/EABI (none) SVR4 SDATA object file
16386 SVR4/EABI -fpic SVR4 pic object file
16387 SVR4/EABI -fPIC SVR4 PIC translation unit
16388 SVR4/EABI -mrelocatable EABI TOC function
16389 SVR4/EABI -maix AIX TOC object file
16390 SVR4/EABI -maix -mminimal-toc
16391 AIX minimal TOC translation unit
16393 Name Reg. Set by entries contains:
16394 made by addrs? fp? sum?
16396 AIX TOC 2 crt0 as Y option option
16397 AIX minimal TOC 30 prolog gcc Y Y option
16398 SVR4 SDATA 13 crt0 gcc N Y N
16399 SVR4 pic 30 prolog ld Y not yet N
16400 SVR4 PIC 30 prolog gcc Y option option
16401 EABI TOC 30 prolog gcc Y option option
16405 /* Hash functions for the hash table. */
16408 rs6000_hash_constant (rtx k)
16410 enum rtx_code code = GET_CODE (k);
16411 enum machine_mode mode = GET_MODE (k);
16412 unsigned result = (code << 3) ^ mode;
16413 const char *format;
16416 format = GET_RTX_FORMAT (code);
16417 flen = strlen (format);
16423 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16426 if (mode != VOIDmode)
16427 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16439 for (; fidx < flen; fidx++)
16440 switch (format[fidx])
16445 const char *str = XSTR (k, fidx);
16446 len = strlen (str);
16447 result = result * 613 + len;
16448 for (i = 0; i < len; i++)
16449 result = result * 613 + (unsigned) str[i];
16454 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16458 result = result * 613 + (unsigned) XINT (k, fidx);
16461 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16462 result = result * 613 + (unsigned) XWINT (k, fidx);
16466 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16467 result = result * 613 + (unsigned) (XWINT (k, fidx)
16474 gcc_unreachable ();
16481 toc_hash_function (const void *hash_entry)
16483 const struct toc_hash_struct *thc =
16484 (const struct toc_hash_struct *) hash_entry;
16485 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16488 /* Compare H1 and H2 for equivalence. */
16491 toc_hash_eq (const void *h1, const void *h2)
16493 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16494 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16496 if (((const struct toc_hash_struct *) h1)->key_mode
16497 != ((const struct toc_hash_struct *) h2)->key_mode)
16500 return rtx_equal_p (r1, r2);
16503 /* These are the names given by the C++ front-end to vtables, and
16504 vtable-like objects. Ideally, this logic should not be here;
16505 instead, there should be some programmatic way of inquiring as
16506 to whether or not an object is a vtable. */
16508 #define VTABLE_NAME_P(NAME) \
16509 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16510 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16511 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16512 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16513 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16516 rs6000_output_symbol_ref (FILE *file, rtx x)
16518 /* Currently C++ toc references to vtables can be emitted before it
16519 is decided whether the vtable is public or private. If this is
16520 the case, then the linker will eventually complain that there is
16521 a reference to an unknown section. Thus, for vtables only,
16522 we emit the TOC reference to reference the symbol and not the
16524 const char *name = XSTR (x, 0);
16526 if (VTABLE_NAME_P (name))
16528 RS6000_OUTPUT_BASENAME (file, name);
16531 assemble_name (file, name);
16534 /* Output a TOC entry. We derive the entry name from what is being
16538 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16541 const char *name = buf;
16542 const char *real_name;
16544 HOST_WIDE_INT offset = 0;
16546 gcc_assert (!TARGET_NO_TOC);
16548 /* When the linker won't eliminate them, don't output duplicate
16549 TOC entries (this happens on AIX if there is any kind of TOC,
16550 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16552 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16554 struct toc_hash_struct *h;
16557 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16558 time because GGC is not initialized at that point. */
16559 if (toc_hash_table == NULL)
16560 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16561 toc_hash_eq, NULL);
16563 h = ggc_alloc (sizeof (*h));
16565 h->key_mode = mode;
16566 h->labelno = labelno;
16568 found = htab_find_slot (toc_hash_table, h, 1);
16569 if (*found == NULL)
16571 else /* This is indeed a duplicate.
16572 Set this label equal to that label. */
16574 fputs ("\t.set ", file);
16575 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16576 fprintf (file, "%d,", labelno);
16577 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16578 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16584 /* If we're going to put a double constant in the TOC, make sure it's
16585 aligned properly when strict alignment is on. */
16586 if (GET_CODE (x) == CONST_DOUBLE
16587 && STRICT_ALIGNMENT
16588 && GET_MODE_BITSIZE (mode) >= 64
16589 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16590 ASM_OUTPUT_ALIGN (file, 3);
16593 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16595 /* Handle FP constants specially. Note that if we have a minimal
16596 TOC, things we put here aren't actually in the TOC, so we can allow
16598 if (GET_CODE (x) == CONST_DOUBLE &&
16599 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16601 REAL_VALUE_TYPE rv;
16604 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16605 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16606 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16608 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16612 if (TARGET_MINIMAL_TOC)
16613 fputs (DOUBLE_INT_ASM_OP, file);
16615 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16616 k[0] & 0xffffffff, k[1] & 0xffffffff,
16617 k[2] & 0xffffffff, k[3] & 0xffffffff);
16618 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16619 k[0] & 0xffffffff, k[1] & 0xffffffff,
16620 k[2] & 0xffffffff, k[3] & 0xffffffff);
16625 if (TARGET_MINIMAL_TOC)
16626 fputs ("\t.long ", file);
16628 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16629 k[0] & 0xffffffff, k[1] & 0xffffffff,
16630 k[2] & 0xffffffff, k[3] & 0xffffffff);
16631 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16632 k[0] & 0xffffffff, k[1] & 0xffffffff,
16633 k[2] & 0xffffffff, k[3] & 0xffffffff);
16637 else if (GET_CODE (x) == CONST_DOUBLE &&
16638 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16640 REAL_VALUE_TYPE rv;
16643 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16645 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16646 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16648 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16652 if (TARGET_MINIMAL_TOC)
16653 fputs (DOUBLE_INT_ASM_OP, file);
16655 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16656 k[0] & 0xffffffff, k[1] & 0xffffffff);
16657 fprintf (file, "0x%lx%08lx\n",
16658 k[0] & 0xffffffff, k[1] & 0xffffffff);
16663 if (TARGET_MINIMAL_TOC)
16664 fputs ("\t.long ", file);
16666 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16667 k[0] & 0xffffffff, k[1] & 0xffffffff);
16668 fprintf (file, "0x%lx,0x%lx\n",
16669 k[0] & 0xffffffff, k[1] & 0xffffffff);
16673 else if (GET_CODE (x) == CONST_DOUBLE &&
16674 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16676 REAL_VALUE_TYPE rv;
16679 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16680 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16681 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16683 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16687 if (TARGET_MINIMAL_TOC)
16688 fputs (DOUBLE_INT_ASM_OP, file);
16690 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16691 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16696 if (TARGET_MINIMAL_TOC)
16697 fputs ("\t.long ", file);
16699 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16700 fprintf (file, "0x%lx\n", l & 0xffffffff);
16704 else if (GET_MODE (x) == VOIDmode
16705 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16707 unsigned HOST_WIDE_INT low;
16708 HOST_WIDE_INT high;
16710 if (GET_CODE (x) == CONST_DOUBLE)
16712 low = CONST_DOUBLE_LOW (x);
16713 high = CONST_DOUBLE_HIGH (x);
16716 #if HOST_BITS_PER_WIDE_INT == 32
16719 high = (low & 0x80000000) ? ~0 : 0;
16723 low = INTVAL (x) & 0xffffffff;
16724 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16728 /* TOC entries are always Pmode-sized, but since this
16729 is a bigendian machine then if we're putting smaller
16730 integer constants in the TOC we have to pad them.
16731 (This is still a win over putting the constants in
16732 a separate constant pool, because then we'd have
16733 to have both a TOC entry _and_ the actual constant.)
16735 For a 32-bit target, CONST_INT values are loaded and shifted
16736 entirely within `low' and can be stored in one TOC entry. */
16738 /* It would be easy to make this work, but it doesn't now. */
16739 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16741 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16743 #if HOST_BITS_PER_WIDE_INT == 32
16744 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16745 POINTER_SIZE, &low, &high, 0);
16748 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16749 high = (HOST_WIDE_INT) low >> 32;
16756 if (TARGET_MINIMAL_TOC)
16757 fputs (DOUBLE_INT_ASM_OP, file);
16759 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16760 (long) high & 0xffffffff, (long) low & 0xffffffff);
16761 fprintf (file, "0x%lx%08lx\n",
16762 (long) high & 0xffffffff, (long) low & 0xffffffff);
16767 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16769 if (TARGET_MINIMAL_TOC)
16770 fputs ("\t.long ", file);
16772 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16773 (long) high & 0xffffffff, (long) low & 0xffffffff);
16774 fprintf (file, "0x%lx,0x%lx\n",
16775 (long) high & 0xffffffff, (long) low & 0xffffffff);
16779 if (TARGET_MINIMAL_TOC)
16780 fputs ("\t.long ", file);
16782 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16783 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16789 if (GET_CODE (x) == CONST)
16791 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16793 base = XEXP (XEXP (x, 0), 0);
16794 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16797 switch (GET_CODE (base))
16800 name = XSTR (base, 0);
16804 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16805 CODE_LABEL_NUMBER (XEXP (base, 0)));
16809 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16813 gcc_unreachable ();
16816 real_name = (*targetm.strip_name_encoding) (name);
16817 if (TARGET_MINIMAL_TOC)
16818 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16821 fprintf (file, "\t.tc %s", real_name);
16824 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16826 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16828 fputs ("[TC],", file);
16831 /* Currently C++ toc references to vtables can be emitted before it
16832 is decided whether the vtable is public or private. If this is
16833 the case, then the linker will eventually complain that there is
16834 a TOC reference to an unknown section. Thus, for vtables only,
16835 we emit the TOC reference to reference the symbol and not the
16837 if (VTABLE_NAME_P (name))
16839 RS6000_OUTPUT_BASENAME (file, name);
16841 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16842 else if (offset > 0)
16843 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16846 output_addr_const (file, x);
16850 /* Output an assembler pseudo-op to write an ASCII string of N characters
16851 starting at P to FILE.
16853 On the RS/6000, we have to do this using the .byte operation and
16854 write out special characters outside the quoted string.
16855 Also, the assembler is broken; very long strings are truncated,
16856 so we must artificially break them up early. */
16859 output_ascii (FILE *file, const char *p, int n)
16862 int i, count_string;
16863 const char *for_string = "\t.byte \"";
16864 const char *for_decimal = "\t.byte ";
16865 const char *to_close = NULL;
16868 for (i = 0; i < n; i++)
16871 if (c >= ' ' && c < 0177)
16874 fputs (for_string, file);
16877 /* Write two quotes to get one. */
16885 for_decimal = "\"\n\t.byte ";
16889 if (count_string >= 512)
16891 fputs (to_close, file);
16893 for_string = "\t.byte \"";
16894 for_decimal = "\t.byte ";
16902 fputs (for_decimal, file);
16903 fprintf (file, "%d", c);
16905 for_string = "\n\t.byte \"";
16906 for_decimal = ", ";
16912 /* Now close the string if we have written one. Then end the line. */
16914 fputs (to_close, file);
16917 /* Generate a unique section name for FILENAME for a section type
16918 represented by SECTION_DESC. Output goes into BUF.
16920 SECTION_DESC can be any string, as long as it is different for each
16921 possible section type.
16923 We name the section in the same manner as xlc. The name begins with an
16924 underscore followed by the filename (after stripping any leading directory
16925 names) with the last period replaced by the string SECTION_DESC. If
16926 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16930 rs6000_gen_section_name (char **buf, const char *filename,
16931 const char *section_desc)
16933 const char *q, *after_last_slash, *last_period = 0;
16937 after_last_slash = filename;
16938 for (q = filename; *q; q++)
16941 after_last_slash = q + 1;
16942 else if (*q == '.')
16946 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16947 *buf = (char *) xmalloc (len);
16952 for (q = after_last_slash; *q; q++)
16954 if (q == last_period)
16956 strcpy (p, section_desc);
16957 p += strlen (section_desc);
16961 else if (ISALNUM (*q))
16965 if (last_period == 0)
16966 strcpy (p, section_desc);
16971 /* Emit profile function. */
16974 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16976 /* Non-standard profiling for kernels, which just saves LR then calls
16977 _mcount without worrying about arg saves. The idea is to change
16978 the function prologue as little as possible as it isn't easy to
16979 account for arg save/restore code added just for _mcount. */
16980 if (TARGET_PROFILE_KERNEL)
16983 if (DEFAULT_ABI == ABI_AIX)
16985 #ifndef NO_PROFILE_COUNTERS
16986 # define NO_PROFILE_COUNTERS 0
16988 if (NO_PROFILE_COUNTERS)
16989 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16993 const char *label_name;
16996 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16997 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16998 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
17000 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
17004 else if (DEFAULT_ABI == ABI_DARWIN)
17006 const char *mcount_name = RS6000_MCOUNT;
17007 int caller_addr_regno = LR_REGNO;
17009 /* Be conservative and always set this, at least for now. */
17010 current_function_uses_pic_offset_table = 1;
17013 /* For PIC code, set up a stub and collect the caller's address
17014 from r0, which is where the prologue puts it. */
17015 if (MACHOPIC_INDIRECT
17016 && current_function_uses_pic_offset_table)
17017 caller_addr_regno = 0;
17019 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
17021 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
17025 /* Write function profiler code. */
17028 output_function_profiler (FILE *file, int labelno)
17032 switch (DEFAULT_ABI)
17035 gcc_unreachable ();
17040 warning (0, "no profiling of 64-bit code for this ABI");
17043 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17044 fprintf (file, "\tmflr %s\n", reg_names[0]);
17045 if (NO_PROFILE_COUNTERS)
17047 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17048 reg_names[0], reg_names[1]);
17050 else if (TARGET_SECURE_PLT && flag_pic)
17052 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17053 reg_names[0], reg_names[1]);
17054 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17055 asm_fprintf (file, "\t{cau|addis} %s,%s,",
17056 reg_names[12], reg_names[12]);
17057 assemble_name (file, buf);
17058 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
17059 assemble_name (file, buf);
17060 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
17062 else if (flag_pic == 1)
17064 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
17065 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17066 reg_names[0], reg_names[1]);
17067 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17068 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
17069 assemble_name (file, buf);
17070 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
17072 else if (flag_pic > 1)
17074 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17075 reg_names[0], reg_names[1]);
17076 /* Now, we need to get the address of the label. */
17077 fputs ("\tbcl 20,31,1f\n\t.long ", file);
17078 assemble_name (file, buf);
17079 fputs ("-.\n1:", file);
17080 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
17081 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
17082 reg_names[0], reg_names[11]);
17083 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
17084 reg_names[0], reg_names[0], reg_names[11]);
17088 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
17089 assemble_name (file, buf);
17090 fputs ("@ha\n", file);
17091 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17092 reg_names[0], reg_names[1]);
17093 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
17094 assemble_name (file, buf);
17095 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
17098 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17099 fprintf (file, "\tbl %s%s\n",
17100 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17105 if (!TARGET_PROFILE_KERNEL)
17107 /* Don't do anything, done in output_profile_hook (). */
17111 gcc_assert (!TARGET_32BIT);
17113 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17114 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17116 if (cfun->static_chain_decl != NULL)
17118 asm_fprintf (file, "\tstd %s,24(%s)\n",
17119 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17120 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17121 asm_fprintf (file, "\tld %s,24(%s)\n",
17122 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17125 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17133 /* The following variable value is the last issued insn. */
17135 static rtx last_scheduled_insn;
17137 /* The following variable helps to balance issuing of load and
17138 store instructions */
17140 static int load_store_pendulum;
17142 /* Power4 load update and store update instructions are cracked into a
17143 load or store and an integer insn which are executed in the same cycle.
17144 Branches have their own dispatch slot which does not count against the
17145 GCC issue rate, but it changes the program flow so there are no other
17146 instructions to issue in this cycle. */
17149 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17150 int verbose ATTRIBUTE_UNUSED,
17151 rtx insn, int more)
17153 last_scheduled_insn = insn;
17154 if (GET_CODE (PATTERN (insn)) == USE
17155 || GET_CODE (PATTERN (insn)) == CLOBBER)
17157 cached_can_issue_more = more;
17158 return cached_can_issue_more;
17161 if (insn_terminates_group_p (insn, current_group))
17163 cached_can_issue_more = 0;
17164 return cached_can_issue_more;
17167 /* If no reservation, but reach here */
17168 if (recog_memoized (insn) < 0)
17171 if (rs6000_sched_groups)
17173 if (is_microcoded_insn (insn))
17174 cached_can_issue_more = 0;
17175 else if (is_cracked_insn (insn))
17176 cached_can_issue_more = more > 2 ? more - 2 : 0;
17178 cached_can_issue_more = more - 1;
17180 return cached_can_issue_more;
17183 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17186 cached_can_issue_more = more - 1;
17187 return cached_can_issue_more;
17190 /* Adjust the cost of a scheduling dependency. Return the new cost of
17191 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17194 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17196 enum attr_type attr_type;
17198 if (! recog_memoized (insn))
17201 switch (REG_NOTE_KIND (link))
17205 /* Data dependency; DEP_INSN writes a register that INSN reads
17206 some cycles later. */
17208 /* Separate a load from a narrower, dependent store. */
17209 if (rs6000_sched_groups
17210 && GET_CODE (PATTERN (insn)) == SET
17211 && GET_CODE (PATTERN (dep_insn)) == SET
17212 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17213 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17214 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17215 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17218 attr_type = get_attr_type (insn);
17223 /* Tell the first scheduling pass about the latency between
17224 a mtctr and bctr (and mtlr and br/blr). The first
17225 scheduling pass will not know about this latency since
17226 the mtctr instruction, which has the latency associated
17227 to it, will be generated by reload. */
17228 return TARGET_POWER ? 5 : 4;
17230 /* Leave some extra cycles between a compare and its
17231 dependent branch, to inhibit expensive mispredicts. */
17232 if ((rs6000_cpu_attr == CPU_PPC603
17233 || rs6000_cpu_attr == CPU_PPC604
17234 || rs6000_cpu_attr == CPU_PPC604E
17235 || rs6000_cpu_attr == CPU_PPC620
17236 || rs6000_cpu_attr == CPU_PPC630
17237 || rs6000_cpu_attr == CPU_PPC750
17238 || rs6000_cpu_attr == CPU_PPC7400
17239 || rs6000_cpu_attr == CPU_PPC7450
17240 || rs6000_cpu_attr == CPU_POWER4
17241 || rs6000_cpu_attr == CPU_POWER5
17242 || rs6000_cpu_attr == CPU_CELL)
17243 && recog_memoized (dep_insn)
17244 && (INSN_CODE (dep_insn) >= 0))
17246 switch (get_attr_type (dep_insn))
17250 case TYPE_DELAYED_COMPARE:
17251 case TYPE_IMUL_COMPARE:
17252 case TYPE_LMUL_COMPARE:
17253 case TYPE_FPCOMPARE:
17254 case TYPE_CR_LOGICAL:
17255 case TYPE_DELAYED_CR:
17264 case TYPE_STORE_UX:
17266 case TYPE_FPSTORE_U:
17267 case TYPE_FPSTORE_UX:
17268 if ((rs6000_cpu == PROCESSOR_POWER6)
17269 && recog_memoized (dep_insn)
17270 && (INSN_CODE (dep_insn) >= 0))
17273 if (GET_CODE (PATTERN (insn)) != SET)
17274 /* If this happens, we have to extend this to schedule
17275 optimally. Return default for now. */
17278 /* Adjust the cost for the case where the value written
17279 by a fixed point operation is used as the address
17280 gen value on a store. */
17281 switch (get_attr_type (dep_insn))
17288 if (! store_data_bypass_p (dep_insn, insn))
17292 case TYPE_LOAD_EXT:
17293 case TYPE_LOAD_EXT_U:
17294 case TYPE_LOAD_EXT_UX:
17295 case TYPE_VAR_SHIFT_ROTATE:
17296 case TYPE_VAR_DELAYED_COMPARE:
17298 if (! store_data_bypass_p (dep_insn, insn))
17304 case TYPE_FAST_COMPARE:
17307 case TYPE_INSERT_WORD:
17308 case TYPE_INSERT_DWORD:
17309 case TYPE_FPLOAD_U:
17310 case TYPE_FPLOAD_UX:
17312 case TYPE_STORE_UX:
17313 case TYPE_FPSTORE_U:
17314 case TYPE_FPSTORE_UX:
17316 if (! store_data_bypass_p (dep_insn, insn))
17324 case TYPE_IMUL_COMPARE:
17325 case TYPE_LMUL_COMPARE:
17327 if (! store_data_bypass_p (dep_insn, insn))
17333 if (! store_data_bypass_p (dep_insn, insn))
17339 if (! store_data_bypass_p (dep_insn, insn))
17352 case TYPE_LOAD_EXT:
17353 case TYPE_LOAD_EXT_U:
17354 case TYPE_LOAD_EXT_UX:
17355 if ((rs6000_cpu == PROCESSOR_POWER6)
17356 && recog_memoized (dep_insn)
17357 && (INSN_CODE (dep_insn) >= 0))
17360 /* Adjust the cost for the case where the value written
17361 by a fixed point instruction is used within the address
17362 gen portion of a subsequent load(u)(x) */
17363 switch (get_attr_type (dep_insn))
17370 if (set_to_load_agen (dep_insn, insn))
17374 case TYPE_LOAD_EXT:
17375 case TYPE_LOAD_EXT_U:
17376 case TYPE_LOAD_EXT_UX:
17377 case TYPE_VAR_SHIFT_ROTATE:
17378 case TYPE_VAR_DELAYED_COMPARE:
17380 if (set_to_load_agen (dep_insn, insn))
17386 case TYPE_FAST_COMPARE:
17389 case TYPE_INSERT_WORD:
17390 case TYPE_INSERT_DWORD:
17391 case TYPE_FPLOAD_U:
17392 case TYPE_FPLOAD_UX:
17394 case TYPE_STORE_UX:
17395 case TYPE_FPSTORE_U:
17396 case TYPE_FPSTORE_UX:
17398 if (set_to_load_agen (dep_insn, insn))
17406 case TYPE_IMUL_COMPARE:
17407 case TYPE_LMUL_COMPARE:
17409 if (set_to_load_agen (dep_insn, insn))
17415 if (set_to_load_agen (dep_insn, insn))
17421 if (set_to_load_agen (dep_insn, insn))
17432 if ((rs6000_cpu == PROCESSOR_POWER6)
17433 && recog_memoized (dep_insn)
17434 && (INSN_CODE (dep_insn) >= 0)
17435 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17442 /* Fall out to return default cost. */
17446 case REG_DEP_OUTPUT:
17447 /* Output dependency; DEP_INSN writes a register that INSN writes some
17449 if ((rs6000_cpu == PROCESSOR_POWER6)
17450 && recog_memoized (dep_insn)
17451 && (INSN_CODE (dep_insn) >= 0))
17453 attr_type = get_attr_type (insn);
17458 if (get_attr_type (dep_insn) == TYPE_FP)
17462 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17470 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17475 gcc_unreachable ();
17481 /* The function returns a true if INSN is microcoded.
17482 Return false otherwise. */
17485 is_microcoded_insn (rtx insn)
17487 if (!insn || !INSN_P (insn)
17488 || GET_CODE (PATTERN (insn)) == USE
17489 || GET_CODE (PATTERN (insn)) == CLOBBER)
17492 if (rs6000_cpu_attr == CPU_CELL)
17493 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17495 if (rs6000_sched_groups)
17497 enum attr_type type = get_attr_type (insn);
17498 if (type == TYPE_LOAD_EXT_U
17499 || type == TYPE_LOAD_EXT_UX
17500 || type == TYPE_LOAD_UX
17501 || type == TYPE_STORE_UX
17502 || type == TYPE_MFCR)
17509 /* The function returns true if INSN is cracked into 2 instructions
17510 by the processor (and therefore occupies 2 issue slots). */
17513 is_cracked_insn (rtx insn)
17515 if (!insn || !INSN_P (insn)
17516 || GET_CODE (PATTERN (insn)) == USE
17517 || GET_CODE (PATTERN (insn)) == CLOBBER)
17520 if (rs6000_sched_groups)
17522 enum attr_type type = get_attr_type (insn);
17523 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17524 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17525 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17526 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17527 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17528 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17529 || type == TYPE_IDIV || type == TYPE_LDIV
17530 || type == TYPE_INSERT_WORD)
17537 /* The function returns true if INSN can be issued only from
17538 the branch slot. */
17541 is_branch_slot_insn (rtx insn)
17543 if (!insn || !INSN_P (insn)
17544 || GET_CODE (PATTERN (insn)) == USE
17545 || GET_CODE (PATTERN (insn)) == CLOBBER)
17548 if (rs6000_sched_groups)
17550 enum attr_type type = get_attr_type (insn);
17551 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17559 /* The function returns true if out_inst sets a value that is
17560 used in the address generation computation of in_insn */
17562 set_to_load_agen (rtx out_insn, rtx in_insn)
17564 rtx out_set, in_set;
17566 /* For performance reasons, only handle the simple case where
17567 both loads are a single_set. */
17568 out_set = single_set (out_insn);
17571 in_set = single_set (in_insn);
17573 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17579 /* The function returns true if the target storage location of
17580 out_insn is adjacent to the target storage location of in_insn */
17581 /* Return 1 if memory locations are adjacent. */
17584 adjacent_mem_locations (rtx insn1, rtx insn2)
17587 rtx a = get_store_dest (PATTERN (insn1));
17588 rtx b = get_store_dest (PATTERN (insn2));
17590 if ((GET_CODE (XEXP (a, 0)) == REG
17591 || (GET_CODE (XEXP (a, 0)) == PLUS
17592 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17593 && (GET_CODE (XEXP (b, 0)) == REG
17594 || (GET_CODE (XEXP (b, 0)) == PLUS
17595 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17597 HOST_WIDE_INT val0 = 0, val1 = 0;
17601 if (GET_CODE (XEXP (a, 0)) == PLUS)
17603 reg0 = XEXP (XEXP (a, 0), 0);
17604 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17607 reg0 = XEXP (a, 0);
17609 if (GET_CODE (XEXP (b, 0)) == PLUS)
17611 reg1 = XEXP (XEXP (b, 0), 0);
17612 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17615 reg1 = XEXP (b, 0);
17617 val_diff = val1 - val0;
17619 return ((REGNO (reg0) == REGNO (reg1))
17620 && (val_diff == INTVAL (MEM_SIZE (a))
17621 || val_diff == -INTVAL (MEM_SIZE (b))));
17627 /* A C statement (sans semicolon) to update the integer scheduling
17628 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17629 INSN earlier, reduce the priority to execute INSN later. Do not
17630 define this macro if you do not need to adjust the scheduling
17631 priorities of insns. */
17634 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17636 /* On machines (like the 750) which have asymmetric integer units,
17637 where one integer unit can do multiply and divides and the other
17638 can't, reduce the priority of multiply/divide so it is scheduled
17639 before other integer operations. */
17642 if (! INSN_P (insn))
17645 if (GET_CODE (PATTERN (insn)) == USE)
17648 switch (rs6000_cpu_attr) {
17650 switch (get_attr_type (insn))
17657 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17658 priority, priority);
17659 if (priority >= 0 && priority < 0x01000000)
17666 if (insn_must_be_first_in_group (insn)
17667 && reload_completed
17668 && current_sched_info->sched_max_insns_priority
17669 && rs6000_sched_restricted_insns_priority)
17672 /* Prioritize insns that can be dispatched only in the first
17674 if (rs6000_sched_restricted_insns_priority == 1)
17675 /* Attach highest priority to insn. This means that in
17676 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17677 precede 'priority' (critical path) considerations. */
17678 return current_sched_info->sched_max_insns_priority;
17679 else if (rs6000_sched_restricted_insns_priority == 2)
17680 /* Increase priority of insn by a minimal amount. This means that in
17681 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17682 considerations precede dispatch-slot restriction considerations. */
17683 return (priority + 1);
17686 if (rs6000_cpu == PROCESSOR_POWER6
17687 && ((load_store_pendulum == -2 && is_load_insn (insn))
17688 || (load_store_pendulum == 2 && is_store_insn (insn))))
17689 /* Attach highest priority to insn if the scheduler has just issued two
17690 stores and this instruction is a load, or two loads and this instruction
17691 is a store. Power6 wants loads and stores scheduled alternately
17693 return current_sched_info->sched_max_insns_priority;
17698 /* Return true if the instruction is nonpipelined on the Cell. */
17700 is_nonpipeline_insn (rtx insn)
17702 enum attr_type type;
17703 if (!insn || !INSN_P (insn)
17704 || GET_CODE (PATTERN (insn)) == USE
17705 || GET_CODE (PATTERN (insn)) == CLOBBER)
17708 type = get_attr_type (insn);
17709 if (type == TYPE_IMUL
17710 || type == TYPE_IMUL2
17711 || type == TYPE_IMUL3
17712 || type == TYPE_LMUL
17713 || type == TYPE_IDIV
17714 || type == TYPE_LDIV
17715 || type == TYPE_SDIV
17716 || type == TYPE_DDIV
17717 || type == TYPE_SSQRT
17718 || type == TYPE_DSQRT
17719 || type == TYPE_MFCR
17720 || type == TYPE_MFCRF
17721 || type == TYPE_MFJMPR)
17729 /* Return how many instructions the machine can issue per cycle. */
17732 rs6000_issue_rate (void)
17734 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17735 if (!reload_completed)
17738 switch (rs6000_cpu_attr) {
17739 case CPU_RIOS1: /* ? */
17741 case CPU_PPC601: /* ? */
17766 /* Return how many instructions to look ahead for better insn
17770 rs6000_use_sched_lookahead (void)
17772 if (rs6000_cpu_attr == CPU_PPC8540)
17774 if (rs6000_cpu_attr == CPU_CELL)
17775 return (reload_completed ? 8 : 0);
17779 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17781 rs6000_use_sched_lookahead_guard (rtx insn)
17783 if (rs6000_cpu_attr != CPU_CELL)
17786 if (insn == NULL_RTX || !INSN_P (insn))
17789 if (!reload_completed
17790 || is_nonpipeline_insn (insn)
17791 || is_microcoded_insn (insn))
17797 /* Determine is PAT refers to memory. */
17800 is_mem_ref (rtx pat)
17806 if (GET_CODE (pat) == MEM)
17809 /* Recursively process the pattern. */
17810 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17812 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17815 ret |= is_mem_ref (XEXP (pat, i));
17816 else if (fmt[i] == 'E')
17817 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17818 ret |= is_mem_ref (XVECEXP (pat, i, j));
17824 /* Determine if PAT is a PATTERN of a load insn. */
17827 is_load_insn1 (rtx pat)
17829 if (!pat || pat == NULL_RTX)
17832 if (GET_CODE (pat) == SET)
17833 return is_mem_ref (SET_SRC (pat));
17835 if (GET_CODE (pat) == PARALLEL)
17839 for (i = 0; i < XVECLEN (pat, 0); i++)
17840 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17847 /* Determine if INSN loads from memory. */
17850 is_load_insn (rtx insn)
17852 if (!insn || !INSN_P (insn))
17855 if (GET_CODE (insn) == CALL_INSN)
17858 return is_load_insn1 (PATTERN (insn));
17861 /* Determine if PAT is a PATTERN of a store insn. */
17864 is_store_insn1 (rtx pat)
17866 if (!pat || pat == NULL_RTX)
17869 if (GET_CODE (pat) == SET)
17870 return is_mem_ref (SET_DEST (pat));
17872 if (GET_CODE (pat) == PARALLEL)
17876 for (i = 0; i < XVECLEN (pat, 0); i++)
17877 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17884 /* Determine if INSN stores to memory. */
17887 is_store_insn (rtx insn)
17889 if (!insn || !INSN_P (insn))
17892 return is_store_insn1 (PATTERN (insn));
17895 /* Return the dest of a store insn. */
17898 get_store_dest (rtx pat)
17900 gcc_assert (is_store_insn1 (pat));
17902 if (GET_CODE (pat) == SET)
17903 return SET_DEST (pat);
17904 else if (GET_CODE (pat) == PARALLEL)
17908 for (i = 0; i < XVECLEN (pat, 0); i++)
17910 rtx inner_pat = XVECEXP (pat, 0, i);
17911 if (GET_CODE (inner_pat) == SET
17912 && is_mem_ref (SET_DEST (inner_pat)))
17916 /* We shouldn't get here, because we should have either a simple
17917 store insn or a store with update which are covered above. */
17921 /* Returns whether the dependence between INSN and NEXT is considered
17922 costly by the given target. */
17925 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17930 /* If the flag is not enabled - no dependence is considered costly;
17931 allow all dependent insns in the same group.
17932 This is the most aggressive option. */
17933 if (rs6000_sched_costly_dep == no_dep_costly)
17936 /* If the flag is set to 1 - a dependence is always considered costly;
17937 do not allow dependent instructions in the same group.
17938 This is the most conservative option. */
17939 if (rs6000_sched_costly_dep == all_deps_costly)
17942 insn = DEP_PRO (dep);
17943 next = DEP_CON (dep);
17945 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17946 && is_load_insn (next)
17947 && is_store_insn (insn))
17948 /* Prevent load after store in the same group. */
17951 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17952 && is_load_insn (next)
17953 && is_store_insn (insn)
17954 && DEP_TYPE (dep) == REG_DEP_TRUE)
17955 /* Prevent load after store in the same group if it is a true
17959 /* The flag is set to X; dependences with latency >= X are considered costly,
17960 and will not be scheduled in the same group. */
17961 if (rs6000_sched_costly_dep <= max_dep_latency
17962 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17968 /* Return the next insn after INSN that is found before TAIL is reached,
17969 skipping any "non-active" insns - insns that will not actually occupy
17970 an issue slot. Return NULL_RTX if such an insn is not found. */
17973 get_next_active_insn (rtx insn, rtx tail)
17975 if (insn == NULL_RTX || insn == tail)
17980 insn = NEXT_INSN (insn);
17981 if (insn == NULL_RTX || insn == tail)
17986 || (NONJUMP_INSN_P (insn)
17987 && GET_CODE (PATTERN (insn)) != USE
17988 && GET_CODE (PATTERN (insn)) != CLOBBER
17989 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17995 /* We are about to begin issuing insns for this clock cycle. */
17998 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17999 rtx *ready ATTRIBUTE_UNUSED,
18000 int *pn_ready ATTRIBUTE_UNUSED,
18001 int clock_var ATTRIBUTE_UNUSED)
18003 int n_ready = *pn_ready;
18006 fprintf (dump, "// rs6000_sched_reorder :\n");
18008 /* Reorder the ready list, if the second to last ready insn
18009 is a nonepipeline insn. */
18010 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
18012 if (is_nonpipeline_insn (ready[n_ready - 1])
18013 && (recog_memoized (ready[n_ready - 2]) > 0))
18014 /* Simply swap first two insns. */
18016 rtx tmp = ready[n_ready - 1];
18017 ready[n_ready - 1] = ready[n_ready - 2];
18018 ready[n_ready - 2] = tmp;
18022 if (rs6000_cpu == PROCESSOR_POWER6)
18023 load_store_pendulum = 0;
18025 return rs6000_issue_rate ();
18028 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18031 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
18032 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
18035 fprintf (dump, "// rs6000_sched_reorder2 :\n");
18037 /* For Power6, we need to handle some special cases to try and keep the
18038 store queue from overflowing and triggering expensive flushes.
18040 This code monitors how load and store instructions are being issued
18041 and skews the ready list one way or the other to increase the likelihood
18042 that a desired instruction is issued at the proper time.
18044 A couple of things are done. First, we maintain a "load_store_pendulum"
18045 to track the current state of load/store issue.
18047 - If the pendulum is at zero, then no loads or stores have been
18048 issued in the current cycle so we do nothing.
18050 - If the pendulum is 1, then a single load has been issued in this
18051 cycle and we attempt to locate another load in the ready list to
18054 - If the pendulum is -2, then two stores have already been
18055 issued in this cycle, so we increase the priority of the first load
18056 in the ready list to increase it's likelihood of being chosen first
18059 - If the pendulum is -1, then a single store has been issued in this
18060 cycle and we attempt to locate another store in the ready list to
18061 issue with it, preferring a store to an adjacent memory location to
18062 facilitate store pairing in the store queue.
18064 - If the pendulum is 2, then two loads have already been
18065 issued in this cycle, so we increase the priority of the first store
18066 in the ready list to increase it's likelihood of being chosen first
18069 - If the pendulum < -2 or > 2, then do nothing.
18071 Note: This code covers the most common scenarios. There exist non
18072 load/store instructions which make use of the LSU and which
18073 would need to be accounted for to strictly model the behavior
18074 of the machine. Those instructions are currently unaccounted
18075 for to help minimize compile time overhead of this code.
18077 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
18083 if (is_store_insn (last_scheduled_insn))
18084 /* Issuing a store, swing the load_store_pendulum to the left */
18085 load_store_pendulum--;
18086 else if (is_load_insn (last_scheduled_insn))
18087 /* Issuing a load, swing the load_store_pendulum to the right */
18088 load_store_pendulum++;
18090 return cached_can_issue_more;
18092 /* If the pendulum is balanced, or there is only one instruction on
18093 the ready list, then all is well, so return. */
18094 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
18095 return cached_can_issue_more;
18097 if (load_store_pendulum == 1)
18099 /* A load has been issued in this cycle. Scan the ready list
18100 for another load to issue with it */
18105 if (is_load_insn (ready[pos]))
18107 /* Found a load. Move it to the head of the ready list,
18108 and adjust it's priority so that it is more likely to
18111 for (i=pos; i<*pn_ready-1; i++)
18112 ready[i] = ready[i + 1];
18113 ready[*pn_ready-1] = tmp;
18114 if INSN_PRIORITY_KNOWN (tmp)
18115 INSN_PRIORITY (tmp)++;
18121 else if (load_store_pendulum == -2)
18123 /* Two stores have been issued in this cycle. Increase the
18124 priority of the first load in the ready list to favor it for
18125 issuing in the next cycle. */
18130 if (is_load_insn (ready[pos])
18131 && INSN_PRIORITY_KNOWN (ready[pos]))
18133 INSN_PRIORITY (ready[pos])++;
18135 /* Adjust the pendulum to account for the fact that a load
18136 was found and increased in priority. This is to prevent
18137 increasing the priority of multiple loads */
18138 load_store_pendulum--;
18145 else if (load_store_pendulum == -1)
18147 /* A store has been issued in this cycle. Scan the ready list for
18148 another store to issue with it, preferring a store to an adjacent
18150 int first_store_pos = -1;
18156 if (is_store_insn (ready[pos]))
18158 /* Maintain the index of the first store found on the
18160 if (first_store_pos == -1)
18161 first_store_pos = pos;
18163 if (is_store_insn (last_scheduled_insn)
18164 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18166 /* Found an adjacent store. Move it to the head of the
18167 ready list, and adjust it's priority so that it is
18168 more likely to stay there */
18170 for (i=pos; i<*pn_ready-1; i++)
18171 ready[i] = ready[i + 1];
18172 ready[*pn_ready-1] = tmp;
18173 if INSN_PRIORITY_KNOWN (tmp)
18174 INSN_PRIORITY (tmp)++;
18175 first_store_pos = -1;
18183 if (first_store_pos >= 0)
18185 /* An adjacent store wasn't found, but a non-adjacent store was,
18186 so move the non-adjacent store to the front of the ready
18187 list, and adjust its priority so that it is more likely to
18189 tmp = ready[first_store_pos];
18190 for (i=first_store_pos; i<*pn_ready-1; i++)
18191 ready[i] = ready[i + 1];
18192 ready[*pn_ready-1] = tmp;
18193 if INSN_PRIORITY_KNOWN (tmp)
18194 INSN_PRIORITY (tmp)++;
18197 else if (load_store_pendulum == 2)
18199 /* Two loads have been issued in this cycle. Increase the priority
18200 of the first store in the ready list to favor it for issuing in
18206 if (is_store_insn (ready[pos])
18207 && INSN_PRIORITY_KNOWN (ready[pos]))
18209 INSN_PRIORITY (ready[pos])++;
18211 /* Adjust the pendulum to account for the fact that a store
18212 was found and increased in priority. This is to prevent
18213 increasing the priority of multiple stores */
18214 load_store_pendulum++;
18223 return cached_can_issue_more;
18226 /* Return whether the presence of INSN causes a dispatch group termination
18227 of group WHICH_GROUP.
18229 If WHICH_GROUP == current_group, this function will return true if INSN
18230 causes the termination of the current group (i.e, the dispatch group to
18231 which INSN belongs). This means that INSN will be the last insn in the
18232 group it belongs to.
18234 If WHICH_GROUP == previous_group, this function will return true if INSN
18235 causes the termination of the previous group (i.e, the dispatch group that
18236 precedes the group to which INSN belongs). This means that INSN will be
18237 the first insn in the group it belongs to). */
18240 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18247 first = insn_must_be_first_in_group (insn);
18248 last = insn_must_be_last_in_group (insn);
18253 if (which_group == current_group)
18255 else if (which_group == previous_group)
18263 insn_must_be_first_in_group (rtx insn)
18265 enum attr_type type;
18268 || insn == NULL_RTX
18269 || GET_CODE (insn) == NOTE
18270 || GET_CODE (PATTERN (insn)) == USE
18271 || GET_CODE (PATTERN (insn)) == CLOBBER)
18274 switch (rs6000_cpu)
18276 case PROCESSOR_POWER5:
18277 if (is_cracked_insn (insn))
18279 case PROCESSOR_POWER4:
18280 if (is_microcoded_insn (insn))
18283 if (!rs6000_sched_groups)
18286 type = get_attr_type (insn);
18293 case TYPE_DELAYED_CR:
18294 case TYPE_CR_LOGICAL:
18308 case PROCESSOR_POWER6:
18309 type = get_attr_type (insn);
18313 case TYPE_INSERT_DWORD:
18317 case TYPE_VAR_SHIFT_ROTATE:
18324 case TYPE_INSERT_WORD:
18325 case TYPE_DELAYED_COMPARE:
18326 case TYPE_IMUL_COMPARE:
18327 case TYPE_LMUL_COMPARE:
18328 case TYPE_FPCOMPARE:
18339 case TYPE_LOAD_EXT_UX:
18341 case TYPE_STORE_UX:
18342 case TYPE_FPLOAD_U:
18343 case TYPE_FPLOAD_UX:
18344 case TYPE_FPSTORE_U:
18345 case TYPE_FPSTORE_UX:
18359 insn_must_be_last_in_group (rtx insn)
18361 enum attr_type type;
18364 || insn == NULL_RTX
18365 || GET_CODE (insn) == NOTE
18366 || GET_CODE (PATTERN (insn)) == USE
18367 || GET_CODE (PATTERN (insn)) == CLOBBER)
18370 switch (rs6000_cpu) {
18371 case PROCESSOR_POWER4:
18372 case PROCESSOR_POWER5:
18373 if (is_microcoded_insn (insn))
18376 if (is_branch_slot_insn (insn))
18380 case PROCESSOR_POWER6:
18381 type = get_attr_type (insn);
18388 case TYPE_VAR_SHIFT_ROTATE:
18395 case TYPE_DELAYED_COMPARE:
18396 case TYPE_IMUL_COMPARE:
18397 case TYPE_LMUL_COMPARE:
18398 case TYPE_FPCOMPARE:
18419 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18420 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18423 is_costly_group (rtx *group_insns, rtx next_insn)
18426 int issue_rate = rs6000_issue_rate ();
18428 for (i = 0; i < issue_rate; i++)
18430 sd_iterator_def sd_it;
18432 rtx insn = group_insns[i];
18437 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
18439 rtx next = DEP_CON (dep);
18441 if (next == next_insn
18442 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18450 /* Utility of the function redefine_groups.
18451 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18452 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18453 to keep it "far" (in a separate group) from GROUP_INSNS, following
18454 one of the following schemes, depending on the value of the flag
18455 -minsert_sched_nops = X:
18456 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18457 in order to force NEXT_INSN into a separate group.
18458 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18459 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18460 insertion (has a group just ended, how many vacant issue slots remain in the
18461 last group, and how many dispatch groups were encountered so far). */
18464 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18465 rtx next_insn, bool *group_end, int can_issue_more,
18470 int issue_rate = rs6000_issue_rate ();
18471 bool end = *group_end;
18474 if (next_insn == NULL_RTX)
18475 return can_issue_more;
18477 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18478 return can_issue_more;
18480 force = is_costly_group (group_insns, next_insn);
18482 return can_issue_more;
18484 if (sched_verbose > 6)
18485 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18486 *group_count ,can_issue_more);
18488 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18491 can_issue_more = 0;
18493 /* Since only a branch can be issued in the last issue_slot, it is
18494 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18495 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18496 in this case the last nop will start a new group and the branch
18497 will be forced to the new group. */
18498 if (can_issue_more && !is_branch_slot_insn (next_insn))
18501 while (can_issue_more > 0)
18504 emit_insn_before (nop, next_insn);
18512 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18514 int n_nops = rs6000_sched_insert_nops;
18516 /* Nops can't be issued from the branch slot, so the effective
18517 issue_rate for nops is 'issue_rate - 1'. */
18518 if (can_issue_more == 0)
18519 can_issue_more = issue_rate;
18521 if (can_issue_more == 0)
18523 can_issue_more = issue_rate - 1;
18526 for (i = 0; i < issue_rate; i++)
18528 group_insns[i] = 0;
18535 emit_insn_before (nop, next_insn);
18536 if (can_issue_more == issue_rate - 1) /* new group begins */
18539 if (can_issue_more == 0)
18541 can_issue_more = issue_rate - 1;
18544 for (i = 0; i < issue_rate; i++)
18546 group_insns[i] = 0;
18552 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18555 /* Is next_insn going to start a new group? */
18558 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18559 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18560 || (can_issue_more < issue_rate &&
18561 insn_terminates_group_p (next_insn, previous_group)));
18562 if (*group_end && end)
18565 if (sched_verbose > 6)
18566 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18567 *group_count, can_issue_more);
18568 return can_issue_more;
18571 return can_issue_more;
18574 /* This function tries to synch the dispatch groups that the compiler "sees"
18575 with the dispatch groups that the processor dispatcher is expected to
18576 form in practice. It tries to achieve this synchronization by forcing the
18577 estimated processor grouping on the compiler (as opposed to the function
18578 'pad_goups' which tries to force the scheduler's grouping on the processor).
18580 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18581 examines the (estimated) dispatch groups that will be formed by the processor
18582 dispatcher. It marks these group boundaries to reflect the estimated
18583 processor grouping, overriding the grouping that the scheduler had marked.
18584 Depending on the value of the flag '-minsert-sched-nops' this function can
18585 force certain insns into separate groups or force a certain distance between
18586 them by inserting nops, for example, if there exists a "costly dependence"
18589 The function estimates the group boundaries that the processor will form as
18590 follows: It keeps track of how many vacant issue slots are available after
18591 each insn. A subsequent insn will start a new group if one of the following
18593 - no more vacant issue slots remain in the current dispatch group.
18594 - only the last issue slot, which is the branch slot, is vacant, but the next
18595 insn is not a branch.
18596 - only the last 2 or less issue slots, including the branch slot, are vacant,
18597 which means that a cracked insn (which occupies two issue slots) can't be
18598 issued in this group.
18599 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18600 start a new group. */
18603 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18605 rtx insn, next_insn;
18607 int can_issue_more;
18610 int group_count = 0;
18614 issue_rate = rs6000_issue_rate ();
18615 group_insns = alloca (issue_rate * sizeof (rtx));
18616 for (i = 0; i < issue_rate; i++)
18618 group_insns[i] = 0;
18620 can_issue_more = issue_rate;
18622 insn = get_next_active_insn (prev_head_insn, tail);
18625 while (insn != NULL_RTX)
18627 slot = (issue_rate - can_issue_more);
18628 group_insns[slot] = insn;
18630 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18631 if (insn_terminates_group_p (insn, current_group))
18632 can_issue_more = 0;
18634 next_insn = get_next_active_insn (insn, tail);
18635 if (next_insn == NULL_RTX)
18636 return group_count + 1;
18638 /* Is next_insn going to start a new group? */
18640 = (can_issue_more == 0
18641 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18642 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18643 || (can_issue_more < issue_rate &&
18644 insn_terminates_group_p (next_insn, previous_group)));
18646 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18647 next_insn, &group_end, can_issue_more,
18653 can_issue_more = 0;
18654 for (i = 0; i < issue_rate; i++)
18656 group_insns[i] = 0;
18660 if (GET_MODE (next_insn) == TImode && can_issue_more)
18661 PUT_MODE (next_insn, VOIDmode);
18662 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18663 PUT_MODE (next_insn, TImode);
18666 if (can_issue_more == 0)
18667 can_issue_more = issue_rate;
18670 return group_count;
18673 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18674 dispatch group boundaries that the scheduler had marked. Pad with nops
18675 any dispatch groups which have vacant issue slots, in order to force the
18676 scheduler's grouping on the processor dispatcher. The function
18677 returns the number of dispatch groups found. */
18680 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18682 rtx insn, next_insn;
18685 int can_issue_more;
18687 int group_count = 0;
18689 /* Initialize issue_rate. */
18690 issue_rate = rs6000_issue_rate ();
18691 can_issue_more = issue_rate;
18693 insn = get_next_active_insn (prev_head_insn, tail);
18694 next_insn = get_next_active_insn (insn, tail);
18696 while (insn != NULL_RTX)
18699 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18701 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18703 if (next_insn == NULL_RTX)
18708 /* If the scheduler had marked group termination at this location
18709 (between insn and next_indn), and neither insn nor next_insn will
18710 force group termination, pad the group with nops to force group
18713 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18714 && !insn_terminates_group_p (insn, current_group)
18715 && !insn_terminates_group_p (next_insn, previous_group))
18717 if (!is_branch_slot_insn (next_insn))
18720 while (can_issue_more)
18723 emit_insn_before (nop, next_insn);
18728 can_issue_more = issue_rate;
18733 next_insn = get_next_active_insn (insn, tail);
18736 return group_count;
18739 /* We're beginning a new block. Initialize data structures as necessary. */
18742 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18743 int sched_verbose ATTRIBUTE_UNUSED,
18744 int max_ready ATTRIBUTE_UNUSED)
18746 last_scheduled_insn = NULL_RTX;
18747 load_store_pendulum = 0;
18750 /* The following function is called at the end of scheduling BB.
18751 After reload, it inserts nops at insn group bundling. */
18754 rs6000_sched_finish (FILE *dump, int sched_verbose)
18759 fprintf (dump, "=== Finishing schedule.\n");
18761 if (reload_completed && rs6000_sched_groups)
18763 if (rs6000_sched_insert_nops == sched_finish_none)
18766 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18767 n_groups = pad_groups (dump, sched_verbose,
18768 current_sched_info->prev_head,
18769 current_sched_info->next_tail);
18771 n_groups = redefine_groups (dump, sched_verbose,
18772 current_sched_info->prev_head,
18773 current_sched_info->next_tail);
18775 if (sched_verbose >= 6)
18777 fprintf (dump, "ngroups = %d\n", n_groups);
18778 print_rtl (dump, current_sched_info->prev_head);
18779 fprintf (dump, "Done finish_sched\n");
18784 /* Length in units of the trampoline for entering a nested function. */
18787 rs6000_trampoline_size (void)
18791 switch (DEFAULT_ABI)
18794 gcc_unreachable ();
18797 ret = (TARGET_32BIT) ? 12 : 24;
18802 ret = (TARGET_32BIT) ? 40 : 48;
18809 /* Emit RTL insns to initialize the variable parts of a trampoline.
18810 FNADDR is an RTX for the address of the function's pure code.
18811 CXT is an RTX for the static chain value for the function. */
18814 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18816 int regsize = (TARGET_32BIT) ? 4 : 8;
18817 rtx ctx_reg = force_reg (Pmode, cxt);
18819 switch (DEFAULT_ABI)
18822 gcc_unreachable ();
18824 /* Macros to shorten the code expansions below. */
18825 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18826 #define MEM_PLUS(addr,offset) \
18827 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18829 /* Under AIX, just build the 3 word function descriptor */
18832 rtx fn_reg = gen_reg_rtx (Pmode);
18833 rtx toc_reg = gen_reg_rtx (Pmode);
18834 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18835 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18836 emit_move_insn (MEM_DEREF (addr), fn_reg);
18837 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18838 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18842 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18845 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18846 FALSE, VOIDmode, 4,
18848 GEN_INT (rs6000_trampoline_size ()), SImode,
18858 /* Table of valid machine attributes. */
18860 const struct attribute_spec rs6000_attribute_table[] =
18862 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18863 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18864 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18865 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18866 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18867 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18868 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18869 SUBTARGET_ATTRIBUTE_TABLE,
18871 { NULL, 0, 0, false, false, false, NULL }
18874 /* Handle the "altivec" attribute. The attribute may have
18875 arguments as follows:
18877 __attribute__((altivec(vector__)))
18878 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18879 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18881 and may appear more than once (e.g., 'vector bool char') in a
18882 given declaration. */
18885 rs6000_handle_altivec_attribute (tree *node,
18886 tree name ATTRIBUTE_UNUSED,
18888 int flags ATTRIBUTE_UNUSED,
18889 bool *no_add_attrs)
18891 tree type = *node, result = NULL_TREE;
18892 enum machine_mode mode;
18895 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18896 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18897 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18900 while (POINTER_TYPE_P (type)
18901 || TREE_CODE (type) == FUNCTION_TYPE
18902 || TREE_CODE (type) == METHOD_TYPE
18903 || TREE_CODE (type) == ARRAY_TYPE)
18904 type = TREE_TYPE (type);
18906 mode = TYPE_MODE (type);
18908 /* Check for invalid AltiVec type qualifiers. */
18909 if (type == long_unsigned_type_node || type == long_integer_type_node)
18912 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18913 else if (rs6000_warn_altivec_long)
18914 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18916 else if (type == long_long_unsigned_type_node
18917 || type == long_long_integer_type_node)
18918 error ("use of %<long long%> in AltiVec types is invalid");
18919 else if (type == double_type_node)
18920 error ("use of %<double%> in AltiVec types is invalid");
18921 else if (type == long_double_type_node)
18922 error ("use of %<long double%> in AltiVec types is invalid");
18923 else if (type == boolean_type_node)
18924 error ("use of boolean types in AltiVec types is invalid");
18925 else if (TREE_CODE (type) == COMPLEX_TYPE)
18926 error ("use of %<complex%> in AltiVec types is invalid");
18927 else if (DECIMAL_FLOAT_MODE_P (mode))
18928 error ("use of decimal floating point types in AltiVec types is invalid");
18930 switch (altivec_type)
18933 unsigned_p = TYPE_UNSIGNED (type);
18937 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18940 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18943 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18945 case SFmode: result = V4SF_type_node; break;
18946 /* If the user says 'vector int bool', we may be handed the 'bool'
18947 attribute _before_ the 'vector' attribute, and so select the
18948 proper type in the 'b' case below. */
18949 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18957 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18958 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18959 case QImode: case V16QImode: result = bool_V16QI_type_node;
18966 case V8HImode: result = pixel_V8HI_type_node;
18972 if (result && result != type && TYPE_READONLY (type))
18973 result = build_qualified_type (result, TYPE_QUAL_CONST);
18975 *no_add_attrs = true; /* No need to hang on to the attribute. */
18978 *node = reconstruct_complex_type (*node, result);
18983 /* AltiVec defines four built-in scalar types that serve as vector
18984 elements; we must teach the compiler how to mangle them. */
18986 static const char *
18987 rs6000_mangle_type (tree type)
18989 type = TYPE_MAIN_VARIANT (type);
18991 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
18992 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
18995 if (type == bool_char_type_node) return "U6__boolc";
18996 if (type == bool_short_type_node) return "U6__bools";
18997 if (type == pixel_type_node) return "u7__pixel";
18998 if (type == bool_int_type_node) return "U6__booli";
19000 /* Mangle IBM extended float long double as `g' (__float128) on
19001 powerpc*-linux where long-double-64 previously was the default. */
19002 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
19004 && TARGET_LONG_DOUBLE_128
19005 && !TARGET_IEEEQUAD)
19008 /* For all other types, use normal C++ mangling. */
19012 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19013 struct attribute_spec.handler. */
19016 rs6000_handle_longcall_attribute (tree *node, tree name,
19017 tree args ATTRIBUTE_UNUSED,
19018 int flags ATTRIBUTE_UNUSED,
19019 bool *no_add_attrs)
19021 if (TREE_CODE (*node) != FUNCTION_TYPE
19022 && TREE_CODE (*node) != FIELD_DECL
19023 && TREE_CODE (*node) != TYPE_DECL)
19025 warning (OPT_Wattributes, "%qs attribute only applies to functions",
19026 IDENTIFIER_POINTER (name));
19027 *no_add_attrs = true;
19033 /* Set longcall attributes on all functions declared when
19034 rs6000_default_long_calls is true. */
19036 rs6000_set_default_type_attributes (tree type)
19038 if (rs6000_default_long_calls
19039 && (TREE_CODE (type) == FUNCTION_TYPE
19040 || TREE_CODE (type) == METHOD_TYPE))
19041 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
19043 TYPE_ATTRIBUTES (type));
19046 darwin_set_default_type_attributes (type);
19050 /* Return a reference suitable for calling a function with the
19051 longcall attribute. */
19054 rs6000_longcall_ref (rtx call_ref)
19056 const char *call_name;
19059 if (GET_CODE (call_ref) != SYMBOL_REF)
19062 /* System V adds '.' to the internal name, so skip them. */
19063 call_name = XSTR (call_ref, 0);
19064 if (*call_name == '.')
19066 while (*call_name == '.')
19069 node = get_identifier (call_name);
19070 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
19073 return force_reg (Pmode, call_ref);
19076 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19077 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19080 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19081 struct attribute_spec.handler. */
19083 rs6000_handle_struct_attribute (tree *node, tree name,
19084 tree args ATTRIBUTE_UNUSED,
19085 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
19088 if (DECL_P (*node))
19090 if (TREE_CODE (*node) == TYPE_DECL)
19091 type = &TREE_TYPE (*node);
19096 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
19097 || TREE_CODE (*type) == UNION_TYPE)))
19099 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
19100 *no_add_attrs = true;
19103 else if ((is_attribute_p ("ms_struct", name)
19104 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
19105 || ((is_attribute_p ("gcc_struct", name)
19106 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19108 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19109 IDENTIFIER_POINTER (name));
19110 *no_add_attrs = true;
19117 rs6000_ms_bitfield_layout_p (tree record_type)
19119 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19120 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19121 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19124 #ifdef USING_ELFOS_H
19126 /* A get_unnamed_section callback, used for switching to toc_section. */
19129 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19131 if (DEFAULT_ABI == ABI_AIX
19132 && TARGET_MINIMAL_TOC
19133 && !TARGET_RELOCATABLE)
19135 if (!toc_initialized)
19137 toc_initialized = 1;
19138 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19139 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19140 fprintf (asm_out_file, "\t.tc ");
19141 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19142 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19143 fprintf (asm_out_file, "\n");
19145 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19146 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19147 fprintf (asm_out_file, " = .+32768\n");
19150 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19152 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19153 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19156 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19157 if (!toc_initialized)
19159 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19160 fprintf (asm_out_file, " = .+32768\n");
19161 toc_initialized = 1;
19166 /* Implement TARGET_ASM_INIT_SECTIONS. */
19169 rs6000_elf_asm_init_sections (void)
19172 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19175 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19176 SDATA2_SECTION_ASM_OP);
19179 /* Implement TARGET_SELECT_RTX_SECTION. */
19182 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19183 unsigned HOST_WIDE_INT align)
19185 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19186 return toc_section;
19188 return default_elf_select_rtx_section (mode, x, align);
19191 /* For a SYMBOL_REF, set generic flags and then perform some
19192 target-specific processing.
19194 When the AIX ABI is requested on a non-AIX system, replace the
19195 function name with the real name (with a leading .) rather than the
19196 function descriptor name. This saves a lot of overriding code to
19197 read the prefixes. */
19200 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19202 default_encode_section_info (decl, rtl, first);
19205 && TREE_CODE (decl) == FUNCTION_DECL
19207 && DEFAULT_ABI == ABI_AIX)
19209 rtx sym_ref = XEXP (rtl, 0);
19210 size_t len = strlen (XSTR (sym_ref, 0));
19211 char *str = alloca (len + 2);
19213 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19214 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19219 rs6000_elf_in_small_data_p (tree decl)
19221 if (rs6000_sdata == SDATA_NONE)
19224 /* We want to merge strings, so we never consider them small data. */
19225 if (TREE_CODE (decl) == STRING_CST)
19228 /* Functions are never in the small data area. */
19229 if (TREE_CODE (decl) == FUNCTION_DECL)
19232 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19234 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19235 if (strcmp (section, ".sdata") == 0
19236 || strcmp (section, ".sdata2") == 0
19237 || strcmp (section, ".sbss") == 0
19238 || strcmp (section, ".sbss2") == 0
19239 || strcmp (section, ".PPC.EMB.sdata0") == 0
19240 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19245 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19248 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19249 /* If it's not public, and we're not going to reference it there,
19250 there's no need to put it in the small data section. */
19251 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19258 #endif /* USING_ELFOS_H */
19260 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19263 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
19265 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19268 /* Return a REG that occurs in ADDR with coefficient 1.
19269 ADDR can be effectively incremented by incrementing REG.
19271 r0 is special and we must not select it as an address
19272 register by this routine since our caller will try to
19273 increment the returned register via an "la" instruction. */
19276 find_addr_reg (rtx addr)
19278 while (GET_CODE (addr) == PLUS)
19280 if (GET_CODE (XEXP (addr, 0)) == REG
19281 && REGNO (XEXP (addr, 0)) != 0)
19282 addr = XEXP (addr, 0);
19283 else if (GET_CODE (XEXP (addr, 1)) == REG
19284 && REGNO (XEXP (addr, 1)) != 0)
19285 addr = XEXP (addr, 1);
19286 else if (CONSTANT_P (XEXP (addr, 0)))
19287 addr = XEXP (addr, 1);
19288 else if (CONSTANT_P (XEXP (addr, 1)))
19289 addr = XEXP (addr, 0);
19291 gcc_unreachable ();
19293 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19298 rs6000_fatal_bad_address (rtx op)
19300 fatal_insn ("bad address", op);
19305 static tree branch_island_list = 0;
19307 /* Remember to generate a branch island for far calls to the given
19311 add_compiler_branch_island (tree label_name, tree function_name,
19314 tree branch_island = build_tree_list (function_name, label_name);
19315 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19316 TREE_CHAIN (branch_island) = branch_island_list;
19317 branch_island_list = branch_island;
19320 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19321 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19322 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19323 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19325 /* Generate far-jump branch islands for everything on the
19326 branch_island_list. Invoked immediately after the last instruction
19327 of the epilogue has been emitted; the branch-islands must be
19328 appended to, and contiguous with, the function body. Mach-O stubs
19329 are generated in machopic_output_stub(). */
19332 macho_branch_islands (void)
19335 tree branch_island;
19337 for (branch_island = branch_island_list;
19339 branch_island = TREE_CHAIN (branch_island))
19341 const char *label =
19342 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19344 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19345 char name_buf[512];
19346 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19347 if (name[0] == '*' || name[0] == '&')
19348 strcpy (name_buf, name+1);
19352 strcpy (name_buf+1, name);
19354 strcpy (tmp_buf, "\n");
19355 strcat (tmp_buf, label);
19356 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19357 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19358 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19359 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19362 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19363 strcat (tmp_buf, label);
19364 strcat (tmp_buf, "_pic\n");
19365 strcat (tmp_buf, label);
19366 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19368 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19369 strcat (tmp_buf, name_buf);
19370 strcat (tmp_buf, " - ");
19371 strcat (tmp_buf, label);
19372 strcat (tmp_buf, "_pic)\n");
19374 strcat (tmp_buf, "\tmtlr r0\n");
19376 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19377 strcat (tmp_buf, name_buf);
19378 strcat (tmp_buf, " - ");
19379 strcat (tmp_buf, label);
19380 strcat (tmp_buf, "_pic)\n");
19382 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19386 strcat (tmp_buf, ":\nlis r12,hi16(");
19387 strcat (tmp_buf, name_buf);
19388 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19389 strcat (tmp_buf, name_buf);
19390 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19392 output_asm_insn (tmp_buf, 0);
19393 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19394 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19395 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19396 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19399 branch_island_list = 0;
19402 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19403 already there or not. */
19406 no_previous_def (tree function_name)
19408 tree branch_island;
19409 for (branch_island = branch_island_list;
19411 branch_island = TREE_CHAIN (branch_island))
19412 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19417 /* GET_PREV_LABEL gets the label name from the previous definition of
19421 get_prev_label (tree function_name)
19423 tree branch_island;
19424 for (branch_island = branch_island_list;
19426 branch_island = TREE_CHAIN (branch_island))
19427 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19428 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19432 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19433 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19436 /* KEXTs still need branch islands. */
19437 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19438 || flag_mkernel || flag_apple_kext)
19440 /* INSN is either a function call or a millicode call. It may have an
19441 unconditional jump in its delay slot.
19443 CALL_DEST is the routine we are calling. */
19446 output_call (rtx insn, rtx *operands, int dest_operand_number,
19447 int cookie_operand_number)
19449 static char buf[256];
19450 if (DARWIN_GENERATE_ISLANDS
19451 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19452 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19455 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19457 if (no_previous_def (funname))
19459 rtx label_rtx = gen_label_rtx ();
19460 char *label_buf, temp_buf[256];
19461 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19462 CODE_LABEL_NUMBER (label_rtx));
19463 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19464 labelname = get_identifier (label_buf);
19465 add_compiler_branch_island (labelname, funname, insn_line (insn));
19468 labelname = get_prev_label (funname);
19470 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19471 instruction will reach 'foo', otherwise link as 'bl L42'".
19472 "L42" should be a 'branch island', that will do a far jump to
19473 'foo'. Branch islands are generated in
19474 macho_branch_islands(). */
19475 sprintf (buf, "jbsr %%z%d,%.246s",
19476 dest_operand_number, IDENTIFIER_POINTER (labelname));
19479 sprintf (buf, "bl %%z%d", dest_operand_number);
19483 /* Generate PIC and indirect symbol stubs. */
19486 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19488 unsigned int length;
19489 char *symbol_name, *lazy_ptr_name;
19490 char *local_label_0;
19491 static int label = 0;
19493 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19494 symb = (*targetm.strip_name_encoding) (symb);
19497 length = strlen (symb);
19498 symbol_name = alloca (length + 32);
19499 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19501 lazy_ptr_name = alloca (length + 32);
19502 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19505 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19507 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19511 fprintf (file, "\t.align 5\n");
19513 fprintf (file, "%s:\n", stub);
19514 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19517 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19518 sprintf (local_label_0, "\"L%011d$spb\"", label);
19520 fprintf (file, "\tmflr r0\n");
19521 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19522 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19523 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19524 lazy_ptr_name, local_label_0);
19525 fprintf (file, "\tmtlr r0\n");
19526 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19527 (TARGET_64BIT ? "ldu" : "lwzu"),
19528 lazy_ptr_name, local_label_0);
19529 fprintf (file, "\tmtctr r12\n");
19530 fprintf (file, "\tbctr\n");
19534 fprintf (file, "\t.align 4\n");
19536 fprintf (file, "%s:\n", stub);
19537 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19539 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19540 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19541 (TARGET_64BIT ? "ldu" : "lwzu"),
19543 fprintf (file, "\tmtctr r12\n");
19544 fprintf (file, "\tbctr\n");
19547 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19548 fprintf (file, "%s:\n", lazy_ptr_name);
19549 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19550 fprintf (file, "%sdyld_stub_binding_helper\n",
19551 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19554 /* Legitimize PIC addresses. If the address is already
19555 position-independent, we return ORIG. Newly generated
19556 position-independent addresses go into a reg. This is REG if non
19557 zero, otherwise we allocate register(s) as necessary. */
19559 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19562 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19567 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19568 reg = gen_reg_rtx (Pmode);
19570 if (GET_CODE (orig) == CONST)
19574 if (GET_CODE (XEXP (orig, 0)) == PLUS
19575 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19578 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19580 /* Use a different reg for the intermediate value, as
19581 it will be marked UNCHANGING. */
19582 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
19583 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19586 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19589 if (GET_CODE (offset) == CONST_INT)
19591 if (SMALL_INT (offset))
19592 return plus_constant (base, INTVAL (offset));
19593 else if (! reload_in_progress && ! reload_completed)
19594 offset = force_reg (Pmode, offset);
19597 rtx mem = force_const_mem (Pmode, orig);
19598 return machopic_legitimize_pic_address (mem, Pmode, reg);
19601 return gen_rtx_PLUS (Pmode, base, offset);
19604 /* Fall back on generic machopic code. */
19605 return machopic_legitimize_pic_address (orig, mode, reg);
19608 /* Output a .machine directive for the Darwin assembler, and call
19609 the generic start_file routine. */
19612 rs6000_darwin_file_start (void)
19614 static const struct
19620 { "ppc64", "ppc64", MASK_64BIT },
19621 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19622 { "power4", "ppc970", 0 },
19623 { "G5", "ppc970", 0 },
19624 { "7450", "ppc7450", 0 },
19625 { "7400", "ppc7400", MASK_ALTIVEC },
19626 { "G4", "ppc7400", 0 },
19627 { "750", "ppc750", 0 },
19628 { "740", "ppc750", 0 },
19629 { "G3", "ppc750", 0 },
19630 { "604e", "ppc604e", 0 },
19631 { "604", "ppc604", 0 },
19632 { "603e", "ppc603", 0 },
19633 { "603", "ppc603", 0 },
19634 { "601", "ppc601", 0 },
19635 { NULL, "ppc", 0 } };
19636 const char *cpu_id = "";
19639 rs6000_file_start ();
19640 darwin_file_start ();
19642 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19643 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19644 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19645 && rs6000_select[i].string[0] != '\0')
19646 cpu_id = rs6000_select[i].string;
19648 /* Look through the mapping array. Pick the first name that either
19649 matches the argument, has a bit set in IF_SET that is also set
19650 in the target flags, or has a NULL name. */
19653 while (mapping[i].arg != NULL
19654 && strcmp (mapping[i].arg, cpu_id) != 0
19655 && (mapping[i].if_set & target_flags) == 0)
19658 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19661 #endif /* TARGET_MACHO */
19665 rs6000_elf_reloc_rw_mask (void)
19669 else if (DEFAULT_ABI == ABI_AIX)
19675 /* Record an element in the table of global constructors. SYMBOL is
19676 a SYMBOL_REF of the function to be called; PRIORITY is a number
19677 between 0 and MAX_INIT_PRIORITY.
19679 This differs from default_named_section_asm_out_constructor in
19680 that we have special handling for -mrelocatable. */
19683 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19685 const char *section = ".ctors";
19688 if (priority != DEFAULT_INIT_PRIORITY)
19690 sprintf (buf, ".ctors.%.5u",
19691 /* Invert the numbering so the linker puts us in the proper
19692 order; constructors are run from right to left, and the
19693 linker sorts in increasing order. */
19694 MAX_INIT_PRIORITY - priority);
19698 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19699 assemble_align (POINTER_SIZE);
19701 if (TARGET_RELOCATABLE)
19703 fputs ("\t.long (", asm_out_file);
19704 output_addr_const (asm_out_file, symbol);
19705 fputs (")@fixup\n", asm_out_file);
19708 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19712 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19714 const char *section = ".dtors";
19717 if (priority != DEFAULT_INIT_PRIORITY)
19719 sprintf (buf, ".dtors.%.5u",
19720 /* Invert the numbering so the linker puts us in the proper
19721 order; constructors are run from right to left, and the
19722 linker sorts in increasing order. */
19723 MAX_INIT_PRIORITY - priority);
19727 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19728 assemble_align (POINTER_SIZE);
19730 if (TARGET_RELOCATABLE)
19732 fputs ("\t.long (", asm_out_file);
19733 output_addr_const (asm_out_file, symbol);
19734 fputs (")@fixup\n", asm_out_file);
19737 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19741 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19745 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19746 ASM_OUTPUT_LABEL (file, name);
19747 fputs (DOUBLE_INT_ASM_OP, file);
19748 rs6000_output_function_entry (file, name);
19749 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19752 fputs ("\t.size\t", file);
19753 assemble_name (file, name);
19754 fputs (",24\n\t.type\t.", file);
19755 assemble_name (file, name);
19756 fputs (",@function\n", file);
19757 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19759 fputs ("\t.globl\t.", file);
19760 assemble_name (file, name);
19765 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19766 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19767 rs6000_output_function_entry (file, name);
19768 fputs (":\n", file);
19772 if (TARGET_RELOCATABLE
19773 && !TARGET_SECURE_PLT
19774 && (get_pool_size () != 0 || current_function_profile)
19779 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19781 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19782 fprintf (file, "\t.long ");
19783 assemble_name (file, buf);
19785 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19786 assemble_name (file, buf);
19790 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19791 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19793 if (DEFAULT_ABI == ABI_AIX)
19795 const char *desc_name, *orig_name;
19797 orig_name = (*targetm.strip_name_encoding) (name);
19798 desc_name = orig_name;
19799 while (*desc_name == '.')
19802 if (TREE_PUBLIC (decl))
19803 fprintf (file, "\t.globl %s\n", desc_name);
19805 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19806 fprintf (file, "%s:\n", desc_name);
19807 fprintf (file, "\t.long %s\n", orig_name);
19808 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19809 if (DEFAULT_ABI == ABI_AIX)
19810 fputs ("\t.long 0\n", file);
19811 fprintf (file, "\t.previous\n");
19813 ASM_OUTPUT_LABEL (file, name);
19817 rs6000_elf_end_indicate_exec_stack (void)
19820 file_end_indicate_exec_stack ();
19826 rs6000_xcoff_asm_output_anchor (rtx symbol)
19830 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19831 SYMBOL_REF_BLOCK_OFFSET (symbol));
19832 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19836 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19838 fputs (GLOBAL_ASM_OP, stream);
19839 RS6000_OUTPUT_BASENAME (stream, name);
19840 putc ('\n', stream);
19843 /* A get_unnamed_decl callback, used for read-only sections. PTR
19844 points to the section string variable. */
19847 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19849 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19850 *(const char *const *) directive);
19853 /* Likewise for read-write sections. */
19856 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19858 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19859 *(const char *const *) directive);
19862 /* A get_unnamed_section callback, used for switching to toc_section. */
19865 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19867 if (TARGET_MINIMAL_TOC)
19869 /* toc_section is always selected at least once from
19870 rs6000_xcoff_file_start, so this is guaranteed to
19871 always be defined once and only once in each file. */
19872 if (!toc_initialized)
19874 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19875 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19876 toc_initialized = 1;
19878 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19879 (TARGET_32BIT ? "" : ",3"));
19882 fputs ("\t.toc\n", asm_out_file);
19885 /* Implement TARGET_ASM_INIT_SECTIONS. */
19888 rs6000_xcoff_asm_init_sections (void)
19890 read_only_data_section
19891 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19892 &xcoff_read_only_section_name);
19894 private_data_section
19895 = get_unnamed_section (SECTION_WRITE,
19896 rs6000_xcoff_output_readwrite_section_asm_op,
19897 &xcoff_private_data_section_name);
19899 read_only_private_data_section
19900 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19901 &xcoff_private_data_section_name);
19904 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19906 readonly_data_section = read_only_data_section;
19907 exception_section = data_section;
19911 rs6000_xcoff_reloc_rw_mask (void)
19917 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19918 tree decl ATTRIBUTE_UNUSED)
19921 static const char * const suffix[3] = { "PR", "RO", "RW" };
19923 if (flags & SECTION_CODE)
19925 else if (flags & SECTION_WRITE)
19930 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19931 (flags & SECTION_CODE) ? "." : "",
19932 name, suffix[smclass], flags & SECTION_ENTSIZE);
19936 rs6000_xcoff_select_section (tree decl, int reloc,
19937 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19939 if (decl_readonly_section (decl, reloc))
19941 if (TREE_PUBLIC (decl))
19942 return read_only_data_section;
19944 return read_only_private_data_section;
19948 if (TREE_PUBLIC (decl))
19949 return data_section;
19951 return private_data_section;
19956 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19960 /* Use select_section for private and uninitialized data. */
19961 if (!TREE_PUBLIC (decl)
19962 || DECL_COMMON (decl)
19963 || DECL_INITIAL (decl) == NULL_TREE
19964 || DECL_INITIAL (decl) == error_mark_node
19965 || (flag_zero_initialized_in_bss
19966 && initializer_zerop (DECL_INITIAL (decl))))
19969 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19970 name = (*targetm.strip_name_encoding) (name);
19971 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19974 /* Select section for constant in constant pool.
19976 On RS/6000, all constants are in the private read-only data area.
19977 However, if this is being placed in the TOC it must be output as a
19981 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19982 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19984 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19985 return toc_section;
19987 return read_only_private_data_section;
19990 /* Remove any trailing [DS] or the like from the symbol name. */
19992 static const char *
19993 rs6000_xcoff_strip_name_encoding (const char *name)
19998 len = strlen (name);
19999 if (name[len - 1] == ']')
20000 return ggc_alloc_string (name, len - 4);
20005 /* Section attributes. AIX is always PIC. */
20007 static unsigned int
20008 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
20010 unsigned int align;
20011 unsigned int flags = default_section_type_flags (decl, name, reloc);
20013 /* Align to at least UNIT size. */
20014 if (flags & SECTION_CODE)
20015 align = MIN_UNITS_PER_WORD;
20017 /* Increase alignment of large objects if not already stricter. */
20018 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
20019 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
20020 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
20022 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
20025 /* Output at beginning of assembler file.
20027 Initialize the section names for the RS/6000 at this point.
20029 Specify filename, including full path, to assembler.
20031 We want to go into the TOC section so at least one .toc will be emitted.
20032 Also, in order to output proper .bs/.es pairs, we need at least one static
20033 [RW] section emitted.
20035 Finally, declare mcount when profiling to make the assembler happy. */
20038 rs6000_xcoff_file_start (void)
20040 rs6000_gen_section_name (&xcoff_bss_section_name,
20041 main_input_filename, ".bss_");
20042 rs6000_gen_section_name (&xcoff_private_data_section_name,
20043 main_input_filename, ".rw_");
20044 rs6000_gen_section_name (&xcoff_read_only_section_name,
20045 main_input_filename, ".ro_");
20047 fputs ("\t.file\t", asm_out_file);
20048 output_quoted_string (asm_out_file, main_input_filename);
20049 fputc ('\n', asm_out_file);
20050 if (write_symbols != NO_DEBUG)
20051 switch_to_section (private_data_section);
20052 switch_to_section (text_section);
20054 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
20055 rs6000_file_start ();
20058 /* Output at end of assembler file.
20059 On the RS/6000, referencing data should automatically pull in text. */
20062 rs6000_xcoff_file_end (void)
20064 switch_to_section (text_section);
20065 fputs ("_section_.text:\n", asm_out_file);
20066 switch_to_section (data_section);
20067 fputs (TARGET_32BIT
20068 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20071 #endif /* TARGET_XCOFF */
20073 /* Compute a (partial) cost for rtx X. Return true if the complete
20074 cost has been computed, and false if subexpressions should be
20075 scanned. In either case, *TOTAL contains the cost result. */
20078 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
20080 enum machine_mode mode = GET_MODE (x);
20084 /* On the RS/6000, if it is valid in the insn, it is free. */
20086 if (((outer_code == SET
20087 || outer_code == PLUS
20088 || outer_code == MINUS)
20089 && (satisfies_constraint_I (x)
20090 || satisfies_constraint_L (x)))
20091 || (outer_code == AND
20092 && (satisfies_constraint_K (x)
20094 ? satisfies_constraint_L (x)
20095 : satisfies_constraint_J (x))
20096 || mask_operand (x, mode)
20098 && mask64_operand (x, DImode))))
20099 || ((outer_code == IOR || outer_code == XOR)
20100 && (satisfies_constraint_K (x)
20102 ? satisfies_constraint_L (x)
20103 : satisfies_constraint_J (x))))
20104 || outer_code == ASHIFT
20105 || outer_code == ASHIFTRT
20106 || outer_code == LSHIFTRT
20107 || outer_code == ROTATE
20108 || outer_code == ROTATERT
20109 || outer_code == ZERO_EXTRACT
20110 || (outer_code == MULT
20111 && satisfies_constraint_I (x))
20112 || ((outer_code == DIV || outer_code == UDIV
20113 || outer_code == MOD || outer_code == UMOD)
20114 && exact_log2 (INTVAL (x)) >= 0)
20115 || (outer_code == COMPARE
20116 && (satisfies_constraint_I (x)
20117 || satisfies_constraint_K (x)))
20118 || (outer_code == EQ
20119 && (satisfies_constraint_I (x)
20120 || satisfies_constraint_K (x)
20122 ? satisfies_constraint_L (x)
20123 : satisfies_constraint_J (x))))
20124 || (outer_code == GTU
20125 && satisfies_constraint_I (x))
20126 || (outer_code == LTU
20127 && satisfies_constraint_P (x)))
20132 else if ((outer_code == PLUS
20133 && reg_or_add_cint_operand (x, VOIDmode))
20134 || (outer_code == MINUS
20135 && reg_or_sub_cint_operand (x, VOIDmode))
20136 || ((outer_code == SET
20137 || outer_code == IOR
20138 || outer_code == XOR)
20140 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20142 *total = COSTS_N_INSNS (1);
20148 if (mode == DImode && code == CONST_DOUBLE)
20150 if ((outer_code == IOR || outer_code == XOR)
20151 && CONST_DOUBLE_HIGH (x) == 0
20152 && (CONST_DOUBLE_LOW (x)
20153 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20158 else if ((outer_code == AND && and64_2_operand (x, DImode))
20159 || ((outer_code == SET
20160 || outer_code == IOR
20161 || outer_code == XOR)
20162 && CONST_DOUBLE_HIGH (x) == 0))
20164 *total = COSTS_N_INSNS (1);
20174 /* When optimizing for size, MEM should be slightly more expensive
20175 than generating address, e.g., (plus (reg) (const)).
20176 L1 cache latency is about two instructions. */
20177 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20185 if (mode == DFmode)
20187 if (GET_CODE (XEXP (x, 0)) == MULT)
20189 /* FNMA accounted in outer NEG. */
20190 if (outer_code == NEG)
20191 *total = rs6000_cost->dmul - rs6000_cost->fp;
20193 *total = rs6000_cost->dmul;
20196 *total = rs6000_cost->fp;
20198 else if (mode == SFmode)
20200 /* FNMA accounted in outer NEG. */
20201 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20204 *total = rs6000_cost->fp;
20207 *total = COSTS_N_INSNS (1);
20211 if (mode == DFmode)
20213 if (GET_CODE (XEXP (x, 0)) == MULT
20214 || GET_CODE (XEXP (x, 1)) == MULT)
20216 /* FNMA accounted in outer NEG. */
20217 if (outer_code == NEG)
20218 *total = rs6000_cost->dmul - rs6000_cost->fp;
20220 *total = rs6000_cost->dmul;
20223 *total = rs6000_cost->fp;
20225 else if (mode == SFmode)
20227 /* FNMA accounted in outer NEG. */
20228 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20231 *total = rs6000_cost->fp;
20234 *total = COSTS_N_INSNS (1);
20238 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20239 && satisfies_constraint_I (XEXP (x, 1)))
20241 if (INTVAL (XEXP (x, 1)) >= -256
20242 && INTVAL (XEXP (x, 1)) <= 255)
20243 *total = rs6000_cost->mulsi_const9;
20245 *total = rs6000_cost->mulsi_const;
20247 /* FMA accounted in outer PLUS/MINUS. */
20248 else if ((mode == DFmode || mode == SFmode)
20249 && (outer_code == PLUS || outer_code == MINUS))
20251 else if (mode == DFmode)
20252 *total = rs6000_cost->dmul;
20253 else if (mode == SFmode)
20254 *total = rs6000_cost->fp;
20255 else if (mode == DImode)
20256 *total = rs6000_cost->muldi;
20258 *total = rs6000_cost->mulsi;
20263 if (FLOAT_MODE_P (mode))
20265 *total = mode == DFmode ? rs6000_cost->ddiv
20266 : rs6000_cost->sdiv;
20273 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20274 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20276 if (code == DIV || code == MOD)
20278 *total = COSTS_N_INSNS (2);
20281 *total = COSTS_N_INSNS (1);
20285 if (GET_MODE (XEXP (x, 1)) == DImode)
20286 *total = rs6000_cost->divdi;
20288 *total = rs6000_cost->divsi;
20290 /* Add in shift and subtract for MOD. */
20291 if (code == MOD || code == UMOD)
20292 *total += COSTS_N_INSNS (2);
20296 *total = COSTS_N_INSNS (4);
20300 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20311 *total = COSTS_N_INSNS (1);
20319 /* Handle mul_highpart. */
20320 if (outer_code == TRUNCATE
20321 && GET_CODE (XEXP (x, 0)) == MULT)
20323 if (mode == DImode)
20324 *total = rs6000_cost->muldi;
20326 *total = rs6000_cost->mulsi;
20329 else if (outer_code == AND)
20332 *total = COSTS_N_INSNS (1);
20337 if (GET_CODE (XEXP (x, 0)) == MEM)
20340 *total = COSTS_N_INSNS (1);
20346 if (!FLOAT_MODE_P (mode))
20348 *total = COSTS_N_INSNS (1);
20354 case UNSIGNED_FLOAT:
20357 case FLOAT_TRUNCATE:
20358 *total = rs6000_cost->fp;
20362 if (mode == DFmode)
20365 *total = rs6000_cost->fp;
20369 switch (XINT (x, 1))
20372 *total = rs6000_cost->fp;
20384 *total = COSTS_N_INSNS (1);
20387 else if (FLOAT_MODE_P (mode)
20388 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20390 *total = rs6000_cost->fp;
20398 /* Carry bit requires mode == Pmode.
20399 NEG or PLUS already counted so only add one. */
20401 && (outer_code == NEG || outer_code == PLUS))
20403 *total = COSTS_N_INSNS (1);
20406 if (outer_code == SET)
20408 if (XEXP (x, 1) == const0_rtx)
20410 *total = COSTS_N_INSNS (2);
20413 else if (mode == Pmode)
20415 *total = COSTS_N_INSNS (3);
20424 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20426 *total = COSTS_N_INSNS (2);
20430 if (outer_code == COMPARE)
20444 /* A C expression returning the cost of moving data from a register of class
20445 CLASS1 to one of CLASS2. */
20448 rs6000_register_move_cost (enum machine_mode mode,
20449 enum reg_class from, enum reg_class to)
20451 /* Moves from/to GENERAL_REGS. */
20452 if (reg_classes_intersect_p (to, GENERAL_REGS)
20453 || reg_classes_intersect_p (from, GENERAL_REGS))
20455 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20458 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20459 return (rs6000_memory_move_cost (mode, from, 0)
20460 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20462 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20464 else if (from == CR_REGS)
20468 /* A move will cost one instruction per GPR moved. */
20469 return 2 * hard_regno_nregs[0][mode];
20472 /* Moving between two similar registers is just one instruction. */
20473 else if (reg_classes_intersect_p (to, from))
20474 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20476 /* Everything else has to go through GENERAL_REGS. */
20478 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20479 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20482 /* A C expressions returning the cost of moving data of MODE from a register to
20486 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20487 int in ATTRIBUTE_UNUSED)
20489 if (reg_classes_intersect_p (class, GENERAL_REGS))
20490 return 4 * hard_regno_nregs[0][mode];
20491 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20492 return 4 * hard_regno_nregs[32][mode];
20493 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20494 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20496 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20499 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20500 Assumes no trapping math and finite arguments. */
20503 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20505 rtx x0, e0, e1, y1, u0, v0, one;
20507 x0 = gen_reg_rtx (SFmode);
20508 e0 = gen_reg_rtx (SFmode);
20509 e1 = gen_reg_rtx (SFmode);
20510 y1 = gen_reg_rtx (SFmode);
20511 u0 = gen_reg_rtx (SFmode);
20512 v0 = gen_reg_rtx (SFmode);
20513 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20515 /* x0 = 1./d estimate */
20516 emit_insn (gen_rtx_SET (VOIDmode, x0,
20517 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20519 /* e0 = 1. - d * x0 */
20520 emit_insn (gen_rtx_SET (VOIDmode, e0,
20521 gen_rtx_MINUS (SFmode, one,
20522 gen_rtx_MULT (SFmode, d, x0))));
20523 /* e1 = e0 + e0 * e0 */
20524 emit_insn (gen_rtx_SET (VOIDmode, e1,
20525 gen_rtx_PLUS (SFmode,
20526 gen_rtx_MULT (SFmode, e0, e0), e0)));
20527 /* y1 = x0 + e1 * x0 */
20528 emit_insn (gen_rtx_SET (VOIDmode, y1,
20529 gen_rtx_PLUS (SFmode,
20530 gen_rtx_MULT (SFmode, e1, x0), x0)));
20532 emit_insn (gen_rtx_SET (VOIDmode, u0,
20533 gen_rtx_MULT (SFmode, n, y1)));
20534 /* v0 = n - d * u0 */
20535 emit_insn (gen_rtx_SET (VOIDmode, v0,
20536 gen_rtx_MINUS (SFmode, n,
20537 gen_rtx_MULT (SFmode, d, u0))));
20538 /* res = u0 + v0 * y1 */
20539 emit_insn (gen_rtx_SET (VOIDmode, res,
20540 gen_rtx_PLUS (SFmode,
20541 gen_rtx_MULT (SFmode, v0, y1), u0)));
20544 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20545 Assumes no trapping math and finite arguments. */
20548 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20550 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20552 x0 = gen_reg_rtx (DFmode);
20553 e0 = gen_reg_rtx (DFmode);
20554 e1 = gen_reg_rtx (DFmode);
20555 e2 = gen_reg_rtx (DFmode);
20556 y1 = gen_reg_rtx (DFmode);
20557 y2 = gen_reg_rtx (DFmode);
20558 y3 = gen_reg_rtx (DFmode);
20559 u0 = gen_reg_rtx (DFmode);
20560 v0 = gen_reg_rtx (DFmode);
20561 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20563 /* x0 = 1./d estimate */
20564 emit_insn (gen_rtx_SET (VOIDmode, x0,
20565 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20567 /* e0 = 1. - d * x0 */
20568 emit_insn (gen_rtx_SET (VOIDmode, e0,
20569 gen_rtx_MINUS (DFmode, one,
20570 gen_rtx_MULT (SFmode, d, x0))));
20571 /* y1 = x0 + e0 * x0 */
20572 emit_insn (gen_rtx_SET (VOIDmode, y1,
20573 gen_rtx_PLUS (DFmode,
20574 gen_rtx_MULT (DFmode, e0, x0), x0)));
20576 emit_insn (gen_rtx_SET (VOIDmode, e1,
20577 gen_rtx_MULT (DFmode, e0, e0)));
20578 /* y2 = y1 + e1 * y1 */
20579 emit_insn (gen_rtx_SET (VOIDmode, y2,
20580 gen_rtx_PLUS (DFmode,
20581 gen_rtx_MULT (DFmode, e1, y1), y1)));
20583 emit_insn (gen_rtx_SET (VOIDmode, e2,
20584 gen_rtx_MULT (DFmode, e1, e1)));
20585 /* y3 = y2 + e2 * y2 */
20586 emit_insn (gen_rtx_SET (VOIDmode, y3,
20587 gen_rtx_PLUS (DFmode,
20588 gen_rtx_MULT (DFmode, e2, y2), y2)));
20590 emit_insn (gen_rtx_SET (VOIDmode, u0,
20591 gen_rtx_MULT (DFmode, n, y3)));
20592 /* v0 = n - d * u0 */
20593 emit_insn (gen_rtx_SET (VOIDmode, v0,
20594 gen_rtx_MINUS (DFmode, n,
20595 gen_rtx_MULT (DFmode, d, u0))));
20596 /* res = u0 + v0 * y3 */
20597 emit_insn (gen_rtx_SET (VOIDmode, res,
20598 gen_rtx_PLUS (DFmode,
20599 gen_rtx_MULT (DFmode, v0, y3), u0)));
20603 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20604 target, and SRC is the argument operand. */
20607 rs6000_emit_popcount (rtx dst, rtx src)
20609 enum machine_mode mode = GET_MODE (dst);
20612 tmp1 = gen_reg_rtx (mode);
20614 if (mode == SImode)
20616 emit_insn (gen_popcntbsi2 (tmp1, src));
20617 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20619 tmp2 = force_reg (SImode, tmp2);
20620 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20624 emit_insn (gen_popcntbdi2 (tmp1, src));
20625 tmp2 = expand_mult (DImode, tmp1,
20626 GEN_INT ((HOST_WIDE_INT)
20627 0x01010101 << 32 | 0x01010101),
20629 tmp2 = force_reg (DImode, tmp2);
20630 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20635 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20636 target, and SRC is the argument operand. */
20639 rs6000_emit_parity (rtx dst, rtx src)
20641 enum machine_mode mode = GET_MODE (dst);
20644 tmp = gen_reg_rtx (mode);
20645 if (mode == SImode)
20647 /* Is mult+shift >= shift+xor+shift+xor? */
20648 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20650 rtx tmp1, tmp2, tmp3, tmp4;
20652 tmp1 = gen_reg_rtx (SImode);
20653 emit_insn (gen_popcntbsi2 (tmp1, src));
20655 tmp2 = gen_reg_rtx (SImode);
20656 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20657 tmp3 = gen_reg_rtx (SImode);
20658 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20660 tmp4 = gen_reg_rtx (SImode);
20661 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20662 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20665 rs6000_emit_popcount (tmp, src);
20666 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20670 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20671 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20673 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20675 tmp1 = gen_reg_rtx (DImode);
20676 emit_insn (gen_popcntbdi2 (tmp1, src));
20678 tmp2 = gen_reg_rtx (DImode);
20679 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20680 tmp3 = gen_reg_rtx (DImode);
20681 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20683 tmp4 = gen_reg_rtx (DImode);
20684 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20685 tmp5 = gen_reg_rtx (DImode);
20686 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20688 tmp6 = gen_reg_rtx (DImode);
20689 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20690 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20693 rs6000_emit_popcount (tmp, src);
20694 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20698 /* Return an RTX representing where to find the function value of a
20699 function returning MODE. */
20701 rs6000_complex_function_value (enum machine_mode mode)
20703 unsigned int regno;
20705 enum machine_mode inner = GET_MODE_INNER (mode);
20706 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20708 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20709 regno = FP_ARG_RETURN;
20712 regno = GP_ARG_RETURN;
20714 /* 32-bit is OK since it'll go in r3/r4. */
20715 if (TARGET_32BIT && inner_bytes >= 4)
20716 return gen_rtx_REG (mode, regno);
20719 if (inner_bytes >= 8)
20720 return gen_rtx_REG (mode, regno);
20722 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20724 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20725 GEN_INT (inner_bytes));
20726 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20729 /* Define how to find the value returned by a function.
20730 VALTYPE is the data type of the value (as a tree).
20731 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20732 otherwise, FUNC is 0.
20734 On the SPE, both FPs and vectors are returned in r3.
20736 On RS/6000 an integer value is in r3 and a floating-point value is in
20737 fp1, unless -msoft-float. */
20740 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20742 enum machine_mode mode;
20743 unsigned int regno;
20745 /* Special handling for structs in darwin64. */
20746 if (rs6000_darwin64_abi
20747 && TYPE_MODE (valtype) == BLKmode
20748 && TREE_CODE (valtype) == RECORD_TYPE
20749 && int_size_in_bytes (valtype) > 0)
20751 CUMULATIVE_ARGS valcum;
20755 valcum.fregno = FP_ARG_MIN_REG;
20756 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20757 /* Do a trial code generation as if this were going to be passed as
20758 an argument; if any part goes in memory, we return NULL. */
20759 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20762 /* Otherwise fall through to standard ABI rules. */
20765 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20767 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20768 return gen_rtx_PARALLEL (DImode,
20770 gen_rtx_EXPR_LIST (VOIDmode,
20771 gen_rtx_REG (SImode, GP_ARG_RETURN),
20773 gen_rtx_EXPR_LIST (VOIDmode,
20774 gen_rtx_REG (SImode,
20775 GP_ARG_RETURN + 1),
20778 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20780 return gen_rtx_PARALLEL (DCmode,
20782 gen_rtx_EXPR_LIST (VOIDmode,
20783 gen_rtx_REG (SImode, GP_ARG_RETURN),
20785 gen_rtx_EXPR_LIST (VOIDmode,
20786 gen_rtx_REG (SImode,
20787 GP_ARG_RETURN + 1),
20789 gen_rtx_EXPR_LIST (VOIDmode,
20790 gen_rtx_REG (SImode,
20791 GP_ARG_RETURN + 2),
20793 gen_rtx_EXPR_LIST (VOIDmode,
20794 gen_rtx_REG (SImode,
20795 GP_ARG_RETURN + 3),
20799 mode = TYPE_MODE (valtype);
20800 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20801 || POINTER_TYPE_P (valtype))
20802 mode = TARGET_32BIT ? SImode : DImode;
20804 if (DECIMAL_FLOAT_MODE_P (mode))
20806 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20811 gcc_unreachable ();
20813 regno = GP_ARG_RETURN;
20816 regno = FP_ARG_RETURN;
20819 /* Use f2:f3 specified by the ABI. */
20820 regno = FP_ARG_RETURN + 1;
20825 regno = GP_ARG_RETURN;
20827 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20828 regno = FP_ARG_RETURN;
20829 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20830 && targetm.calls.split_complex_arg)
20831 return rs6000_complex_function_value (mode);
20832 else if (TREE_CODE (valtype) == VECTOR_TYPE
20833 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20834 && ALTIVEC_VECTOR_MODE (mode))
20835 regno = ALTIVEC_ARG_RETURN;
20836 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20837 && (mode == DFmode || mode == DCmode
20838 || mode == TFmode || mode == TCmode))
20839 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20841 regno = GP_ARG_RETURN;
20843 return gen_rtx_REG (mode, regno);
20846 /* Define how to find the value returned by a library function
20847 assuming the value has mode MODE. */
20849 rs6000_libcall_value (enum machine_mode mode)
20851 unsigned int regno;
20853 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20855 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20856 return gen_rtx_PARALLEL (DImode,
20858 gen_rtx_EXPR_LIST (VOIDmode,
20859 gen_rtx_REG (SImode, GP_ARG_RETURN),
20861 gen_rtx_EXPR_LIST (VOIDmode,
20862 gen_rtx_REG (SImode,
20863 GP_ARG_RETURN + 1),
20867 if (DECIMAL_FLOAT_MODE_P (mode))
20869 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20874 gcc_unreachable ();
20876 regno = GP_ARG_RETURN;
20879 regno = FP_ARG_RETURN;
20882 /* Use f2:f3 specified by the ABI. */
20883 regno = FP_ARG_RETURN + 1;
20888 regno = GP_ARG_RETURN;
20890 else if (SCALAR_FLOAT_MODE_P (mode)
20891 && TARGET_HARD_FLOAT && TARGET_FPRS)
20892 regno = FP_ARG_RETURN;
20893 else if (ALTIVEC_VECTOR_MODE (mode)
20894 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20895 regno = ALTIVEC_ARG_RETURN;
20896 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20897 return rs6000_complex_function_value (mode);
20898 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20899 && (mode == DFmode || mode == DCmode
20900 || mode == TFmode || mode == TCmode))
20901 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20903 regno = GP_ARG_RETURN;
20905 return gen_rtx_REG (mode, regno);
20908 /* Define the offset between two registers, FROM to be eliminated and its
20909 replacement TO, at the start of a routine. */
20911 rs6000_initial_elimination_offset (int from, int to)
20913 rs6000_stack_t *info = rs6000_stack_info ();
20914 HOST_WIDE_INT offset;
20916 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20917 offset = info->push_p ? 0 : -info->total_size;
20918 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20920 offset = info->push_p ? 0 : -info->total_size;
20921 if (FRAME_GROWS_DOWNWARD)
20922 offset += info->fixed_size + info->vars_size + info->parm_size;
20924 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20925 offset = FRAME_GROWS_DOWNWARD
20926 ? info->fixed_size + info->vars_size + info->parm_size
20928 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20929 offset = info->total_size;
20930 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20931 offset = info->push_p ? info->total_size : 0;
20932 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20935 gcc_unreachable ();
20940 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20943 rs6000_is_opaque_type (tree type)
20945 return (type == opaque_V2SI_type_node
20946 || type == opaque_V2SF_type_node
20947 || type == opaque_p_V2SI_type_node
20948 || type == opaque_V4SI_type_node);
20952 rs6000_dwarf_register_span (rtx reg)
20957 && (SPE_VECTOR_MODE (GET_MODE (reg))
20958 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20963 regno = REGNO (reg);
20965 /* The duality of the SPE register size wreaks all kinds of havoc.
20966 This is a way of distinguishing r0 in 32-bits from r0 in
20969 gen_rtx_PARALLEL (VOIDmode,
20972 gen_rtx_REG (SImode, regno + 1200),
20973 gen_rtx_REG (SImode, regno))
20975 gen_rtx_REG (SImode, regno),
20976 gen_rtx_REG (SImode, regno + 1200)));
20979 /* Fill in sizes for SPE register high parts in table used by unwinder. */
20982 rs6000_init_dwarf_reg_sizes_extra (tree address)
20987 enum machine_mode mode = TYPE_MODE (char_type_node);
20988 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
20989 rtx mem = gen_rtx_MEM (BLKmode, addr);
20990 rtx value = gen_int_mode (4, mode);
20992 for (i = 1201; i < 1232; i++)
20994 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
20995 HOST_WIDE_INT offset
20996 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
20998 emit_move_insn (adjust_address (mem, mode, offset), value);
21003 /* Map internal gcc register numbers to DWARF2 register numbers. */
21006 rs6000_dbx_register_number (unsigned int regno)
21008 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
21010 if (regno == MQ_REGNO)
21012 if (regno == LR_REGNO)
21014 if (regno == CTR_REGNO)
21016 if (CR_REGNO_P (regno))
21017 return regno - CR0_REGNO + 86;
21018 if (regno == XER_REGNO)
21020 if (ALTIVEC_REGNO_P (regno))
21021 return regno - FIRST_ALTIVEC_REGNO + 1124;
21022 if (regno == VRSAVE_REGNO)
21024 if (regno == VSCR_REGNO)
21026 if (regno == SPE_ACC_REGNO)
21028 if (regno == SPEFSCR_REGNO)
21030 /* SPE high reg number. We get these values of regno from
21031 rs6000_dwarf_register_span. */
21032 gcc_assert (regno >= 1200 && regno < 1232);
21036 /* target hook eh_return_filter_mode */
21037 static enum machine_mode
21038 rs6000_eh_return_filter_mode (void)
21040 return TARGET_32BIT ? SImode : word_mode;
21043 /* Target hook for scalar_mode_supported_p. */
21045 rs6000_scalar_mode_supported_p (enum machine_mode mode)
21047 if (DECIMAL_FLOAT_MODE_P (mode))
21050 return default_scalar_mode_supported_p (mode);
21053 /* Target hook for vector_mode_supported_p. */
21055 rs6000_vector_mode_supported_p (enum machine_mode mode)
21058 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
21061 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
21068 /* Target hook for invalid_arg_for_unprototyped_fn. */
21069 static const char *
21070 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
21072 return (!rs6000_darwin64_abi
21074 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
21075 && (funcdecl == NULL_TREE
21076 || (TREE_CODE (funcdecl) == FUNCTION_DECL
21077 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
21078 ? N_("AltiVec argument passed to unprototyped function")
21082 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21083 setup by using __stack_chk_fail_local hidden function instead of
21084 calling __stack_chk_fail directly. Otherwise it is better to call
21085 __stack_chk_fail directly. */
21088 rs6000_stack_protect_fail (void)
21090 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
21091 ? default_hidden_stack_protect_fail ()
21092 : default_external_stack_protect_fail ();
21095 #include "gt-rs6000.h"