1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "tm-constrs.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 static GTY(()) bool rs6000_cell_dont_microcode;
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups;
149 /* Align branch targets. */
150 static GTY(()) bool rs6000_align_branch_targets;
152 /* Support for -msched-costly-dep option. */
153 const char *rs6000_sched_costly_dep_str;
154 enum rs6000_dependence_cost rs6000_sched_costly_dep;
156 /* Support for -minsert-sched-nops option. */
157 const char *rs6000_sched_insert_nops_str;
158 enum rs6000_nop_insertion rs6000_sched_insert_nops;
160 /* Support targetm.vectorize.builtin_mask_for_load. */
161 static GTY(()) tree altivec_builtin_mask_for_load;
163 /* Size of long double. */
164 int rs6000_long_double_type_size;
166 /* IEEE quad extended precision long double. */
169 /* Whether -mabi=altivec has appeared. */
170 int rs6000_altivec_abi;
172 /* Nonzero if we want SPE ABI extensions. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
179 int rs6000_darwin64_abi;
181 /* Set to nonzero once AIX common-mode calls have been defined. */
182 static GTY(()) int common_mode_defined;
184 /* Save information from a "cmpxx" operation until the branch or scc is
186 rtx rs6000_compare_op0, rs6000_compare_op1;
187 int rs6000_compare_fp_p;
189 /* Label number of label created for -mrelocatable, to call to so we can
190 get the address of the GOT section */
191 int rs6000_pic_labelno;
194 /* Which abi to adhere to */
195 const char *rs6000_abi_name;
197 /* Semantics of the small data area */
198 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
200 /* Which small data model to use */
201 const char *rs6000_sdata_name = (char *)0;
203 /* Counter for labels which are to be placed in .fixup. */
204 int fixuplabelno = 0;
207 /* Bit size of immediate TLS offsets and string from which it is decoded. */
208 int rs6000_tls_size = 32;
209 const char *rs6000_tls_size_string;
211 /* ABI enumeration available for subtarget to use. */
212 enum rs6000_abi rs6000_current_abi;
214 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
218 const char *rs6000_debug_name;
219 int rs6000_debug_stack; /* debug stack applications */
220 int rs6000_debug_arg; /* debug argument handling */
222 /* Value is TRUE if register/mode pair is acceptable. */
223 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
225 /* Built in types. */
227 tree rs6000_builtin_types[RS6000_BTI_MAX];
228 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
230 const char *rs6000_traceback_name;
232 traceback_default = 0,
238 /* Flag to say the TOC is initialized */
240 char toc_label_name[10];
242 /* Cached value of rs6000_variable_issue. This is cached in
243 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
244 static short cached_can_issue_more;
246 static GTY(()) section *read_only_data_section;
247 static GTY(()) section *private_data_section;
248 static GTY(()) section *read_only_private_data_section;
249 static GTY(()) section *sdata2_section;
250 static GTY(()) section *toc_section;
252 /* Control alignment for fields within structures. */
253 /* String from -malign-XXXXX. */
254 int rs6000_alignment_flags;
256 /* True for any options that were explicitly set. */
258 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
259 bool alignment; /* True if -malign- was used. */
260 bool abi; /* True if -mabi=spe/nospe was used. */
261 bool spe; /* True if -mspe= was used. */
262 bool float_gprs; /* True if -mfloat-gprs= was used. */
263 bool isel; /* True if -misel was used. */
264 bool long_double; /* True if -mlong-double- was used. */
265 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
266 } rs6000_explicit_options;
268 struct builtin_description
270 /* mask is not const because we're going to alter it below. This
271 nonsense will go away when we rewrite the -march infrastructure
272 to give us more target flag bits. */
274 const enum insn_code icode;
275 const char *const name;
276 const enum rs6000_builtins code;
279 /* Target cpu costs. */
281 struct processor_costs {
282 const int mulsi; /* cost of SImode multiplication. */
283 const int mulsi_const; /* cost of SImode multiplication by constant. */
284 const int mulsi_const9; /* cost of SImode mult by short constant. */
285 const int muldi; /* cost of DImode multiplication. */
286 const int divsi; /* cost of SImode division. */
287 const int divdi; /* cost of DImode division. */
288 const int fp; /* cost of simple SFmode and DFmode insns. */
289 const int dmul; /* cost of DFmode multiplication (and fmadd). */
290 const int sdiv; /* cost of SFmode division (fdivs). */
291 const int ddiv; /* cost of DFmode division (fdiv). */
292 const int cache_line_size; /* cache line size in bytes. */
293 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
294 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
295 const int simultaneous_prefetches; /* number of parallel prefetch
299 const struct processor_costs *rs6000_cost;
301 /* Processor costs (relative to an add) */
303 /* Instruction size costs on 32bit processors. */
305 struct processor_costs size32_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
322 /* Instruction size costs on 64bit processors. */
324 struct processor_costs size64_cost = {
325 COSTS_N_INSNS (1), /* mulsi */
326 COSTS_N_INSNS (1), /* mulsi_const */
327 COSTS_N_INSNS (1), /* mulsi_const9 */
328 COSTS_N_INSNS (1), /* muldi */
329 COSTS_N_INSNS (1), /* divsi */
330 COSTS_N_INSNS (1), /* divdi */
331 COSTS_N_INSNS (1), /* fp */
332 COSTS_N_INSNS (1), /* dmul */
333 COSTS_N_INSNS (1), /* sdiv */
334 COSTS_N_INSNS (1), /* ddiv */
341 /* Instruction costs on RIOS1 processors. */
343 struct processor_costs rios1_cost = {
344 COSTS_N_INSNS (5), /* mulsi */
345 COSTS_N_INSNS (4), /* mulsi_const */
346 COSTS_N_INSNS (3), /* mulsi_const9 */
347 COSTS_N_INSNS (5), /* muldi */
348 COSTS_N_INSNS (19), /* divsi */
349 COSTS_N_INSNS (19), /* divdi */
350 COSTS_N_INSNS (2), /* fp */
351 COSTS_N_INSNS (2), /* dmul */
352 COSTS_N_INSNS (19), /* sdiv */
353 COSTS_N_INSNS (19), /* ddiv */
360 /* Instruction costs on RIOS2 processors. */
362 struct processor_costs rios2_cost = {
363 COSTS_N_INSNS (2), /* mulsi */
364 COSTS_N_INSNS (2), /* mulsi_const */
365 COSTS_N_INSNS (2), /* mulsi_const9 */
366 COSTS_N_INSNS (2), /* muldi */
367 COSTS_N_INSNS (13), /* divsi */
368 COSTS_N_INSNS (13), /* divdi */
369 COSTS_N_INSNS (2), /* fp */
370 COSTS_N_INSNS (2), /* dmul */
371 COSTS_N_INSNS (17), /* sdiv */
372 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
398 /* Instruction costs on MPCCORE processors. */
400 struct processor_costs mpccore_cost = {
401 COSTS_N_INSNS (2), /* mulsi */
402 COSTS_N_INSNS (2), /* mulsi_const */
403 COSTS_N_INSNS (2), /* mulsi_const9 */
404 COSTS_N_INSNS (2), /* muldi */
405 COSTS_N_INSNS (6), /* divsi */
406 COSTS_N_INSNS (6), /* divdi */
407 COSTS_N_INSNS (4), /* fp */
408 COSTS_N_INSNS (5), /* dmul */
409 COSTS_N_INSNS (10), /* sdiv */
410 COSTS_N_INSNS (17), /* ddiv */
417 /* Instruction costs on PPC403 processors. */
419 struct processor_costs ppc403_cost = {
420 COSTS_N_INSNS (4), /* mulsi */
421 COSTS_N_INSNS (4), /* mulsi_const */
422 COSTS_N_INSNS (4), /* mulsi_const9 */
423 COSTS_N_INSNS (4), /* muldi */
424 COSTS_N_INSNS (33), /* divsi */
425 COSTS_N_INSNS (33), /* divdi */
426 COSTS_N_INSNS (11), /* fp */
427 COSTS_N_INSNS (11), /* dmul */
428 COSTS_N_INSNS (11), /* sdiv */
429 COSTS_N_INSNS (11), /* ddiv */
436 /* Instruction costs on PPC405 processors. */
438 struct processor_costs ppc405_cost = {
439 COSTS_N_INSNS (5), /* mulsi */
440 COSTS_N_INSNS (4), /* mulsi_const */
441 COSTS_N_INSNS (3), /* mulsi_const9 */
442 COSTS_N_INSNS (5), /* muldi */
443 COSTS_N_INSNS (35), /* divsi */
444 COSTS_N_INSNS (35), /* divdi */
445 COSTS_N_INSNS (11), /* fp */
446 COSTS_N_INSNS (11), /* dmul */
447 COSTS_N_INSNS (11), /* sdiv */
448 COSTS_N_INSNS (11), /* ddiv */
455 /* Instruction costs on PPC440 processors. */
457 struct processor_costs ppc440_cost = {
458 COSTS_N_INSNS (3), /* mulsi */
459 COSTS_N_INSNS (2), /* mulsi_const */
460 COSTS_N_INSNS (2), /* mulsi_const9 */
461 COSTS_N_INSNS (3), /* muldi */
462 COSTS_N_INSNS (34), /* divsi */
463 COSTS_N_INSNS (34), /* divdi */
464 COSTS_N_INSNS (5), /* fp */
465 COSTS_N_INSNS (5), /* dmul */
466 COSTS_N_INSNS (19), /* sdiv */
467 COSTS_N_INSNS (33), /* ddiv */
474 /* Instruction costs on PPC601 processors. */
476 struct processor_costs ppc601_cost = {
477 COSTS_N_INSNS (5), /* mulsi */
478 COSTS_N_INSNS (5), /* mulsi_const */
479 COSTS_N_INSNS (5), /* mulsi_const9 */
480 COSTS_N_INSNS (5), /* muldi */
481 COSTS_N_INSNS (36), /* divsi */
482 COSTS_N_INSNS (36), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (5), /* dmul */
485 COSTS_N_INSNS (17), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
493 /* Instruction costs on PPC603 processors. */
495 struct processor_costs ppc603_cost = {
496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (37), /* divsi */
501 COSTS_N_INSNS (37), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (4), /* dmul */
504 COSTS_N_INSNS (18), /* sdiv */
505 COSTS_N_INSNS (33), /* ddiv */
512 /* Instruction costs on PPC604 processors. */
514 struct processor_costs ppc604_cost = {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (20), /* divsi */
520 COSTS_N_INSNS (20), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
531 /* Instruction costs on PPC604e processors. */
533 struct processor_costs ppc604e_cost = {
534 COSTS_N_INSNS (2), /* mulsi */
535 COSTS_N_INSNS (2), /* mulsi_const */
536 COSTS_N_INSNS (2), /* mulsi_const9 */
537 COSTS_N_INSNS (2), /* muldi */
538 COSTS_N_INSNS (20), /* divsi */
539 COSTS_N_INSNS (20), /* divdi */
540 COSTS_N_INSNS (3), /* fp */
541 COSTS_N_INSNS (3), /* dmul */
542 COSTS_N_INSNS (18), /* sdiv */
543 COSTS_N_INSNS (32), /* ddiv */
550 /* Instruction costs on PPC620 processors. */
552 struct processor_costs ppc620_cost = {
553 COSTS_N_INSNS (5), /* mulsi */
554 COSTS_N_INSNS (4), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (7), /* muldi */
557 COSTS_N_INSNS (21), /* divsi */
558 COSTS_N_INSNS (37), /* divdi */
559 COSTS_N_INSNS (3), /* fp */
560 COSTS_N_INSNS (3), /* dmul */
561 COSTS_N_INSNS (18), /* sdiv */
562 COSTS_N_INSNS (32), /* ddiv */
569 /* Instruction costs on PPC630 processors. */
571 struct processor_costs ppc630_cost = {
572 COSTS_N_INSNS (5), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (3), /* mulsi_const9 */
575 COSTS_N_INSNS (7), /* muldi */
576 COSTS_N_INSNS (21), /* divsi */
577 COSTS_N_INSNS (37), /* divdi */
578 COSTS_N_INSNS (3), /* fp */
579 COSTS_N_INSNS (3), /* dmul */
580 COSTS_N_INSNS (17), /* sdiv */
581 COSTS_N_INSNS (21), /* ddiv */
588 /* Instruction costs on Cell processor. */
589 /* COSTS_N_INSNS (1) ~ one add. */
591 struct processor_costs ppccell_cost = {
592 COSTS_N_INSNS (9/2)+2, /* mulsi */
593 COSTS_N_INSNS (6/2), /* mulsi_const */
594 COSTS_N_INSNS (6/2), /* mulsi_const9 */
595 COSTS_N_INSNS (15/2)+2, /* muldi */
596 COSTS_N_INSNS (38/2), /* divsi */
597 COSTS_N_INSNS (70/2), /* divdi */
598 COSTS_N_INSNS (10/2), /* fp */
599 COSTS_N_INSNS (10/2), /* dmul */
600 COSTS_N_INSNS (74/2), /* sdiv */
601 COSTS_N_INSNS (74/2), /* ddiv */
608 /* Instruction costs on PPC750 and PPC7400 processors. */
610 struct processor_costs ppc750_cost = {
611 COSTS_N_INSNS (5), /* mulsi */
612 COSTS_N_INSNS (3), /* mulsi_const */
613 COSTS_N_INSNS (2), /* mulsi_const9 */
614 COSTS_N_INSNS (5), /* muldi */
615 COSTS_N_INSNS (17), /* divsi */
616 COSTS_N_INSNS (17), /* divdi */
617 COSTS_N_INSNS (3), /* fp */
618 COSTS_N_INSNS (3), /* dmul */
619 COSTS_N_INSNS (17), /* sdiv */
620 COSTS_N_INSNS (31), /* ddiv */
627 /* Instruction costs on PPC7450 processors. */
629 struct processor_costs ppc7450_cost = {
630 COSTS_N_INSNS (4), /* mulsi */
631 COSTS_N_INSNS (3), /* mulsi_const */
632 COSTS_N_INSNS (3), /* mulsi_const9 */
633 COSTS_N_INSNS (4), /* muldi */
634 COSTS_N_INSNS (23), /* divsi */
635 COSTS_N_INSNS (23), /* divdi */
636 COSTS_N_INSNS (5), /* fp */
637 COSTS_N_INSNS (5), /* dmul */
638 COSTS_N_INSNS (21), /* sdiv */
639 COSTS_N_INSNS (35), /* ddiv */
646 /* Instruction costs on PPC8540 processors. */
648 struct processor_costs ppc8540_cost = {
649 COSTS_N_INSNS (4), /* mulsi */
650 COSTS_N_INSNS (4), /* mulsi_const */
651 COSTS_N_INSNS (4), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (19), /* divsi */
654 COSTS_N_INSNS (19), /* divdi */
655 COSTS_N_INSNS (4), /* fp */
656 COSTS_N_INSNS (4), /* dmul */
657 COSTS_N_INSNS (29), /* sdiv */
658 COSTS_N_INSNS (29), /* ddiv */
662 1, /* prefetch streams /*/
665 /* Instruction costs on POWER4 and POWER5 processors. */
667 struct processor_costs power4_cost = {
668 COSTS_N_INSNS (3), /* mulsi */
669 COSTS_N_INSNS (2), /* mulsi_const */
670 COSTS_N_INSNS (2), /* mulsi_const9 */
671 COSTS_N_INSNS (4), /* muldi */
672 COSTS_N_INSNS (18), /* divsi */
673 COSTS_N_INSNS (34), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (17), /* sdiv */
677 COSTS_N_INSNS (17), /* ddiv */
681 8, /* prefetch streams /*/
684 /* Instruction costs on POWER6 processors. */
686 struct processor_costs power6_cost = {
687 COSTS_N_INSNS (8), /* mulsi */
688 COSTS_N_INSNS (8), /* mulsi_const */
689 COSTS_N_INSNS (8), /* mulsi_const9 */
690 COSTS_N_INSNS (8), /* muldi */
691 COSTS_N_INSNS (22), /* divsi */
692 COSTS_N_INSNS (28), /* divdi */
693 COSTS_N_INSNS (3), /* fp */
694 COSTS_N_INSNS (3), /* dmul */
695 COSTS_N_INSNS (13), /* sdiv */
696 COSTS_N_INSNS (16), /* ddiv */
700 16, /* prefetch streams */
704 static bool rs6000_function_ok_for_sibcall (tree, tree);
705 static const char *rs6000_invalid_within_doloop (rtx);
706 static rtx rs6000_generate_compare (enum rtx_code);
707 static void rs6000_emit_stack_tie (void);
708 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
709 static rtx spe_synthesize_frame_save (rtx);
710 static bool spe_func_has_64bit_regs_p (void);
711 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
713 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
714 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
715 static unsigned rs6000_hash_constant (rtx);
716 static unsigned toc_hash_function (const void *);
717 static int toc_hash_eq (const void *, const void *);
718 static int constant_pool_expr_1 (rtx, int *, int *);
719 static bool constant_pool_expr_p (rtx);
720 static bool legitimate_small_data_p (enum machine_mode, rtx);
721 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
722 static struct machine_function * rs6000_init_machine_status (void);
723 static bool rs6000_assemble_integer (rtx, unsigned int, int);
724 static bool no_global_regs_above (int);
725 #ifdef HAVE_GAS_HIDDEN
726 static void rs6000_assemble_visibility (tree, int);
728 static int rs6000_ra_ever_killed (void);
729 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
730 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
731 static bool rs6000_ms_bitfield_layout_p (tree);
732 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
733 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
734 static const char *rs6000_mangle_type (tree);
735 extern const struct attribute_spec rs6000_attribute_table[];
736 static void rs6000_set_default_type_attributes (tree);
737 static bool rs6000_reg_live_or_pic_offset_p (int);
738 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
739 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
740 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
742 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
743 static bool rs6000_return_in_memory (tree, tree);
744 static void rs6000_file_start (void);
746 static int rs6000_elf_reloc_rw_mask (void);
747 static void rs6000_elf_asm_out_constructor (rtx, int);
748 static void rs6000_elf_asm_out_destructor (rtx, int);
749 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
750 static void rs6000_elf_asm_init_sections (void);
751 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
752 unsigned HOST_WIDE_INT);
753 static void rs6000_elf_encode_section_info (tree, rtx, int)
756 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
758 static void rs6000_xcoff_asm_output_anchor (rtx);
759 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
760 static void rs6000_xcoff_asm_init_sections (void);
761 static int rs6000_xcoff_reloc_rw_mask (void);
762 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
763 static section *rs6000_xcoff_select_section (tree, int,
764 unsigned HOST_WIDE_INT);
765 static void rs6000_xcoff_unique_section (tree, int);
766 static section *rs6000_xcoff_select_rtx_section
767 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
768 static const char * rs6000_xcoff_strip_name_encoding (const char *);
769 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
770 static void rs6000_xcoff_file_start (void);
771 static void rs6000_xcoff_file_end (void);
773 static int rs6000_variable_issue (FILE *, int, rtx, int);
774 static bool rs6000_rtx_costs (rtx, int, int, int *);
775 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
776 static void rs6000_sched_init (FILE *, int, int);
777 static bool is_microcoded_insn (rtx);
778 static bool is_nonpipeline_insn (rtx);
779 static bool is_cracked_insn (rtx);
780 static bool is_branch_slot_insn (rtx);
781 static bool is_load_insn (rtx);
782 static rtx get_store_dest (rtx pat);
783 static bool is_store_insn (rtx);
784 static bool set_to_load_agen (rtx,rtx);
785 static bool adjacent_mem_locations (rtx,rtx);
786 static int rs6000_adjust_priority (rtx, int);
787 static int rs6000_issue_rate (void);
788 static bool rs6000_is_costly_dependence (dep_t, int, int);
789 static rtx get_next_active_insn (rtx, rtx);
790 static bool insn_terminates_group_p (rtx , enum group_termination);
791 static bool insn_must_be_first_in_group (rtx);
792 static bool insn_must_be_last_in_group (rtx);
793 static bool is_costly_group (rtx *, rtx);
794 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
795 static int redefine_groups (FILE *, int, rtx, rtx);
796 static int pad_groups (FILE *, int, rtx, rtx);
797 static void rs6000_sched_finish (FILE *, int);
798 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
799 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
800 static int rs6000_use_sched_lookahead (void);
801 static int rs6000_use_sched_lookahead_guard (rtx);
802 static tree rs6000_builtin_mask_for_load (void);
803 static tree rs6000_builtin_mul_widen_even (tree);
804 static tree rs6000_builtin_mul_widen_odd (tree);
805 static tree rs6000_builtin_conversion (enum tree_code, tree);
807 static void def_builtin (int, const char *, tree, int);
808 static bool rs6000_vector_alignment_reachable (tree, bool);
809 static void rs6000_init_builtins (void);
810 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
811 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
812 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
813 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
814 static void altivec_init_builtins (void);
815 static void rs6000_common_init_builtins (void);
816 static void rs6000_init_libfuncs (void);
818 static void enable_mask_for_builtins (struct builtin_description *, int,
819 enum rs6000_builtins,
820 enum rs6000_builtins);
821 static tree build_opaque_vector_type (tree, int);
822 static void spe_init_builtins (void);
823 static rtx spe_expand_builtin (tree, rtx, bool *);
824 static rtx spe_expand_stv_builtin (enum insn_code, tree);
825 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
826 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
827 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
828 static rs6000_stack_t *rs6000_stack_info (void);
829 static void debug_stack_info (rs6000_stack_t *);
831 static rtx altivec_expand_builtin (tree, rtx, bool *);
832 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
833 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
834 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
835 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
836 static rtx altivec_expand_predicate_builtin (enum insn_code,
837 const char *, tree, rtx);
838 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
839 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
840 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
841 static rtx altivec_expand_vec_set_builtin (tree);
842 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
843 static int get_element_number (tree, tree);
844 static bool rs6000_handle_option (size_t, const char *, int);
845 static void rs6000_parse_tls_size_option (void);
846 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
847 static int first_altivec_reg_to_save (void);
848 static unsigned int compute_vrsave_mask (void);
849 static void compute_save_world_info (rs6000_stack_t *info_ptr);
850 static void is_altivec_return_reg (rtx, void *);
851 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
852 int easy_vector_constant (rtx, enum machine_mode);
853 static bool rs6000_is_opaque_type (tree);
854 static rtx rs6000_dwarf_register_span (rtx);
855 static void rs6000_init_dwarf_reg_sizes_extra (tree);
856 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
857 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
858 static rtx rs6000_tls_get_addr (void);
859 static rtx rs6000_got_sym (void);
860 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
861 static const char *rs6000_get_some_local_dynamic_name (void);
862 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
863 static rtx rs6000_complex_function_value (enum machine_mode);
864 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
865 enum machine_mode, tree);
866 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
868 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
869 tree, HOST_WIDE_INT);
870 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
873 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
876 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
877 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
878 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
879 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
880 enum machine_mode, tree,
882 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
884 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
886 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
888 static void macho_branch_islands (void);
889 static int no_previous_def (tree function_name);
890 static tree get_prev_label (tree function_name);
891 static void rs6000_darwin_file_start (void);
894 static tree rs6000_build_builtin_va_list (void);
895 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
896 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
897 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
898 static bool rs6000_vector_mode_supported_p (enum machine_mode);
899 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
901 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
903 static int get_vsel_insn (enum machine_mode);
904 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
905 static tree rs6000_stack_protect_fail (void);
907 const int INSN_NOT_AVAILABLE = -1;
908 static enum machine_mode rs6000_eh_return_filter_mode (void);
910 /* Hash table stuff for keeping track of TOC entries. */
912 struct toc_hash_struct GTY(())
914 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
915 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
917 enum machine_mode key_mode;
921 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
923 /* Default register names. */
924 char rs6000_reg_names[][8] =
926 "0", "1", "2", "3", "4", "5", "6", "7",
927 "8", "9", "10", "11", "12", "13", "14", "15",
928 "16", "17", "18", "19", "20", "21", "22", "23",
929 "24", "25", "26", "27", "28", "29", "30", "31",
930 "0", "1", "2", "3", "4", "5", "6", "7",
931 "8", "9", "10", "11", "12", "13", "14", "15",
932 "16", "17", "18", "19", "20", "21", "22", "23",
933 "24", "25", "26", "27", "28", "29", "30", "31",
934 "mq", "lr", "ctr","ap",
935 "0", "1", "2", "3", "4", "5", "6", "7",
937 /* AltiVec registers. */
938 "0", "1", "2", "3", "4", "5", "6", "7",
939 "8", "9", "10", "11", "12", "13", "14", "15",
940 "16", "17", "18", "19", "20", "21", "22", "23",
941 "24", "25", "26", "27", "28", "29", "30", "31",
944 "spe_acc", "spefscr",
945 /* Soft frame pointer. */
949 #ifdef TARGET_REGNAMES
950 static const char alt_reg_names[][8] =
952 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
953 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
954 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
955 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
956 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
957 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
958 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
959 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
960 "mq", "lr", "ctr", "ap",
961 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
963 /* AltiVec registers. */
964 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
965 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
966 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
967 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
970 "spe_acc", "spefscr",
971 /* Soft frame pointer. */
976 #ifndef MASK_STRICT_ALIGN
977 #define MASK_STRICT_ALIGN 0
979 #ifndef TARGET_PROFILE_KERNEL
980 #define TARGET_PROFILE_KERNEL 0
983 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
984 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
986 /* Initialize the GCC target structure. */
987 #undef TARGET_ATTRIBUTE_TABLE
988 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
989 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
990 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
992 #undef TARGET_ASM_ALIGNED_DI_OP
993 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
995 /* Default unaligned ops are only provided for ELF. Find the ops needed
996 for non-ELF systems. */
997 #ifndef OBJECT_FORMAT_ELF
999 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1001 #undef TARGET_ASM_UNALIGNED_HI_OP
1002 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1003 #undef TARGET_ASM_UNALIGNED_SI_OP
1004 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1005 #undef TARGET_ASM_UNALIGNED_DI_OP
1006 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1009 #undef TARGET_ASM_UNALIGNED_HI_OP
1010 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1011 #undef TARGET_ASM_UNALIGNED_SI_OP
1012 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1013 #undef TARGET_ASM_UNALIGNED_DI_OP
1014 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1015 #undef TARGET_ASM_ALIGNED_DI_OP
1016 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1020 /* This hook deals with fixups for relocatable code and DI-mode objects
1022 #undef TARGET_ASM_INTEGER
1023 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1025 #ifdef HAVE_GAS_HIDDEN
1026 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1027 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1030 #undef TARGET_HAVE_TLS
1031 #define TARGET_HAVE_TLS HAVE_AS_TLS
1033 #undef TARGET_CANNOT_FORCE_CONST_MEM
1034 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1036 #undef TARGET_ASM_FUNCTION_PROLOGUE
1037 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1038 #undef TARGET_ASM_FUNCTION_EPILOGUE
1039 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1041 #undef TARGET_SCHED_VARIABLE_ISSUE
1042 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1044 #undef TARGET_SCHED_ISSUE_RATE
1045 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1046 #undef TARGET_SCHED_ADJUST_COST
1047 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1048 #undef TARGET_SCHED_ADJUST_PRIORITY
1049 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1050 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1051 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1052 #undef TARGET_SCHED_INIT
1053 #define TARGET_SCHED_INIT rs6000_sched_init
1054 #undef TARGET_SCHED_FINISH
1055 #define TARGET_SCHED_FINISH rs6000_sched_finish
1056 #undef TARGET_SCHED_REORDER
1057 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1058 #undef TARGET_SCHED_REORDER2
1059 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1061 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1062 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1064 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1065 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1067 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1068 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1069 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1070 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1071 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1072 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1073 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1074 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1076 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1077 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1079 #undef TARGET_INIT_BUILTINS
1080 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1082 #undef TARGET_EXPAND_BUILTIN
1083 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1085 #undef TARGET_MANGLE_TYPE
1086 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1088 #undef TARGET_INIT_LIBFUNCS
1089 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1092 #undef TARGET_BINDS_LOCAL_P
1093 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1096 #undef TARGET_MS_BITFIELD_LAYOUT_P
1097 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1099 #undef TARGET_ASM_OUTPUT_MI_THUNK
1100 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1102 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1103 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1105 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1106 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1108 #undef TARGET_INVALID_WITHIN_DOLOOP
1109 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1111 #undef TARGET_RTX_COSTS
1112 #define TARGET_RTX_COSTS rs6000_rtx_costs
1113 #undef TARGET_ADDRESS_COST
1114 #define TARGET_ADDRESS_COST hook_int_rtx_0
1116 #undef TARGET_VECTOR_OPAQUE_P
1117 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1119 #undef TARGET_DWARF_REGISTER_SPAN
1120 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1122 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1123 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1125 /* On rs6000, function arguments are promoted, as are function return
1127 #undef TARGET_PROMOTE_FUNCTION_ARGS
1128 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1129 #undef TARGET_PROMOTE_FUNCTION_RETURN
1130 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1132 #undef TARGET_RETURN_IN_MEMORY
1133 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1135 #undef TARGET_SETUP_INCOMING_VARARGS
1136 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1138 /* Always strict argument naming on rs6000. */
1139 #undef TARGET_STRICT_ARGUMENT_NAMING
1140 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1141 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1142 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1143 #undef TARGET_SPLIT_COMPLEX_ARG
1144 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1145 #undef TARGET_MUST_PASS_IN_STACK
1146 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1147 #undef TARGET_PASS_BY_REFERENCE
1148 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1149 #undef TARGET_ARG_PARTIAL_BYTES
1150 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1152 #undef TARGET_BUILD_BUILTIN_VA_LIST
1153 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1155 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1156 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1158 #undef TARGET_EH_RETURN_FILTER_MODE
1159 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1161 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1162 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1164 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1165 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1167 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1168 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1170 #undef TARGET_HANDLE_OPTION
1171 #define TARGET_HANDLE_OPTION rs6000_handle_option
1173 #undef TARGET_DEFAULT_TARGET_FLAGS
1174 #define TARGET_DEFAULT_TARGET_FLAGS \
1177 #undef TARGET_STACK_PROTECT_FAIL
1178 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1180 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1181 The PowerPC architecture requires only weak consistency among
1182 processors--that is, memory accesses between processors need not be
1183 sequentially consistent and memory accesses among processors can occur
1184 in any order. The ability to order memory accesses weakly provides
1185 opportunities for more efficient use of the system bus. Unless a
1186 dependency exists, the 604e allows read operations to precede store
1188 #undef TARGET_RELAXED_ORDERING
1189 #define TARGET_RELAXED_ORDERING true
1192 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1193 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1196 /* Use a 32-bit anchor range. This leads to sequences like:
1198 addis tmp,anchor,high
1201 where tmp itself acts as an anchor, and can be shared between
1202 accesses to the same 64k page. */
1203 #undef TARGET_MIN_ANCHOR_OFFSET
1204 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1205 #undef TARGET_MAX_ANCHOR_OFFSET
1206 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1207 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1208 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1210 struct gcc_target targetm = TARGET_INITIALIZER;
1213 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1216 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1218 /* The GPRs can hold any mode, but values bigger than one register
1219 cannot go past R31. */
1220 if (INT_REGNO_P (regno))
1221 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1223 /* The float registers can only hold floating modes and DImode.
1224 This excludes the 32-bit decimal float mode for now. */
1225 if (FP_REGNO_P (regno))
1227 (SCALAR_FLOAT_MODE_P (mode)
1228 && (mode != TDmode || (regno % 2) == 0)
1230 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1231 || (GET_MODE_CLASS (mode) == MODE_INT
1232 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1234 /* The CR register can only hold CC modes. */
1235 if (CR_REGNO_P (regno))
1236 return GET_MODE_CLASS (mode) == MODE_CC;
1238 if (XER_REGNO_P (regno))
1239 return mode == PSImode;
1241 /* AltiVec only in AldyVec registers. */
1242 if (ALTIVEC_REGNO_P (regno))
1243 return ALTIVEC_VECTOR_MODE (mode);
1245 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1246 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1249 /* We cannot put TImode anywhere except general register and it must be
1250 able to fit within the register set. */
1252 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1255 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1257 rs6000_init_hard_regno_mode_ok (void)
1261 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1262 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1263 if (rs6000_hard_regno_mode_ok (r, m))
1264 rs6000_hard_regno_mode_ok_p[m][r] = true;
1268 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1271 darwin_rs6000_override_options (void)
1273 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1275 rs6000_altivec_abi = 1;
1276 TARGET_ALTIVEC_VRSAVE = 1;
1277 if (DEFAULT_ABI == ABI_DARWIN)
1279 if (MACHO_DYNAMIC_NO_PIC_P)
1282 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1285 else if (flag_pic == 1)
1290 if (TARGET_64BIT && ! TARGET_POWERPC64)
1292 target_flags |= MASK_POWERPC64;
1293 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1297 rs6000_default_long_calls = 1;
1298 target_flags |= MASK_SOFT_FLOAT;
1301 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1303 if (!flag_mkernel && !flag_apple_kext
1305 && ! (target_flags_explicit & MASK_ALTIVEC))
1306 target_flags |= MASK_ALTIVEC;
1308 /* Unless the user (not the configurer) has explicitly overridden
1309 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1310 G4 unless targetting the kernel. */
1313 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1314 && ! (target_flags_explicit & MASK_ALTIVEC)
1315 && ! rs6000_select[1].string)
1317 target_flags |= MASK_ALTIVEC;
1322 /* If not otherwise specified by a target, make 'long double' equivalent to
1325 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1326 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1329 /* Override command line options. Mostly we process the processor
1330 type and sometimes adjust other TARGET_ options. */
1333 rs6000_override_options (const char *default_cpu)
1336 struct rs6000_cpu_select *ptr;
1339 /* Simplifications for entries below. */
1342 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1343 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1346 /* This table occasionally claims that a processor does not support
1347 a particular feature even though it does, but the feature is slower
1348 than the alternative. Thus, it shouldn't be relied on as a
1349 complete description of the processor's support.
1351 Please keep this list in order, and don't forget to update the
1352 documentation in invoke.texi when adding a new processor or
1356 const char *const name; /* Canonical processor name. */
1357 const enum processor_type processor; /* Processor type enum value. */
1358 const int target_enable; /* Target flags to enable. */
1359 } const processor_target_table[]
1360 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1361 {"403", PROCESSOR_PPC403,
1362 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1363 {"405", PROCESSOR_PPC405,
1364 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1365 {"405fp", PROCESSOR_PPC405,
1366 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1367 {"440", PROCESSOR_PPC440,
1368 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1369 {"440fp", PROCESSOR_PPC440,
1370 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1371 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1372 {"601", PROCESSOR_PPC601,
1373 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1374 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1375 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1376 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1377 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1378 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1379 {"620", PROCESSOR_PPC620,
1380 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1381 {"630", PROCESSOR_PPC630,
1382 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1383 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1384 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1385 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1386 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1387 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1388 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1389 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1390 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1391 /* 8548 has a dummy entry for now. */
1392 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1393 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1394 {"970", PROCESSOR_POWER4,
1395 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1396 {"cell", PROCESSOR_CELL,
1397 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1398 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1399 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1400 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1401 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1402 {"G5", PROCESSOR_POWER4,
1403 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1404 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1405 {"power2", PROCESSOR_POWER,
1406 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1407 {"power3", PROCESSOR_PPC630,
1408 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1409 {"power4", PROCESSOR_POWER4,
1410 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1411 {"power5", PROCESSOR_POWER5,
1412 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1413 | MASK_MFCRF | MASK_POPCNTB},
1414 {"power5+", PROCESSOR_POWER5,
1415 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1416 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1417 {"power6", PROCESSOR_POWER6,
1418 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1419 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1420 {"power6x", PROCESSOR_POWER6,
1421 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1422 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1423 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1424 {"powerpc64", PROCESSOR_POWERPC64,
1425 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1426 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1427 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1428 {"rios2", PROCESSOR_RIOS2,
1429 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1430 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1431 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1432 {"rs64", PROCESSOR_RS64A,
1433 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1436 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1438 /* Some OSs don't support saving the high part of 64-bit registers on
1439 context switch. Other OSs don't support saving Altivec registers.
1440 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1441 settings; if the user wants either, the user must explicitly specify
1442 them and we won't interfere with the user's specification. */
1445 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1446 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1447 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1448 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1449 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1452 rs6000_init_hard_regno_mode_ok ();
1454 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1455 #ifdef OS_MISSING_POWERPC64
1456 if (OS_MISSING_POWERPC64)
1457 set_masks &= ~MASK_POWERPC64;
1459 #ifdef OS_MISSING_ALTIVEC
1460 if (OS_MISSING_ALTIVEC)
1461 set_masks &= ~MASK_ALTIVEC;
1464 /* Don't override by the processor default if given explicitly. */
1465 set_masks &= ~target_flags_explicit;
1467 /* Identify the processor type. */
1468 rs6000_select[0].string = default_cpu;
1469 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1471 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1473 ptr = &rs6000_select[i];
1474 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1476 for (j = 0; j < ptt_size; j++)
1477 if (! strcmp (ptr->string, processor_target_table[j].name))
1479 if (ptr->set_tune_p)
1480 rs6000_cpu = processor_target_table[j].processor;
1482 if (ptr->set_arch_p)
1484 target_flags &= ~set_masks;
1485 target_flags |= (processor_target_table[j].target_enable
1492 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1499 /* If we are optimizing big endian systems for space, use the load/store
1500 multiple and string instructions. */
1501 if (BYTES_BIG_ENDIAN && optimize_size)
1502 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1504 /* Don't allow -mmultiple or -mstring on little endian systems
1505 unless the cpu is a 750, because the hardware doesn't support the
1506 instructions used in little endian mode, and causes an alignment
1507 trap. The 750 does not cause an alignment trap (except when the
1508 target is unaligned). */
1510 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1512 if (TARGET_MULTIPLE)
1514 target_flags &= ~MASK_MULTIPLE;
1515 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1516 warning (0, "-mmultiple is not supported on little endian systems");
1521 target_flags &= ~MASK_STRING;
1522 if ((target_flags_explicit & MASK_STRING) != 0)
1523 warning (0, "-mstring is not supported on little endian systems");
1527 /* Set debug flags */
1528 if (rs6000_debug_name)
1530 if (! strcmp (rs6000_debug_name, "all"))
1531 rs6000_debug_stack = rs6000_debug_arg = 1;
1532 else if (! strcmp (rs6000_debug_name, "stack"))
1533 rs6000_debug_stack = 1;
1534 else if (! strcmp (rs6000_debug_name, "arg"))
1535 rs6000_debug_arg = 1;
1537 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1540 if (rs6000_traceback_name)
1542 if (! strncmp (rs6000_traceback_name, "full", 4))
1543 rs6000_traceback = traceback_full;
1544 else if (! strncmp (rs6000_traceback_name, "part", 4))
1545 rs6000_traceback = traceback_part;
1546 else if (! strncmp (rs6000_traceback_name, "no", 2))
1547 rs6000_traceback = traceback_none;
1549 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1550 rs6000_traceback_name);
1553 if (!rs6000_explicit_options.long_double)
1554 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1556 #ifndef POWERPC_LINUX
1557 if (!rs6000_explicit_options.ieee)
1558 rs6000_ieeequad = 1;
1561 /* Set Altivec ABI as default for powerpc64 linux. */
1562 if (TARGET_ELF && TARGET_64BIT)
1564 rs6000_altivec_abi = 1;
1565 TARGET_ALTIVEC_VRSAVE = 1;
1568 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1569 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1571 rs6000_darwin64_abi = 1;
1573 darwin_one_byte_bool = 1;
1575 /* Default to natural alignment, for better performance. */
1576 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1579 /* Place FP constants in the constant pool instead of TOC
1580 if section anchors enabled. */
1581 if (flag_section_anchors)
1582 TARGET_NO_FP_IN_TOC = 1;
1584 /* Handle -mtls-size option. */
1585 rs6000_parse_tls_size_option ();
1587 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1588 SUBTARGET_OVERRIDE_OPTIONS;
1590 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1591 SUBSUBTARGET_OVERRIDE_OPTIONS;
1593 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1594 SUB3TARGET_OVERRIDE_OPTIONS;
1599 /* The e500 does not have string instructions, and we set
1600 MASK_STRING above when optimizing for size. */
1601 if ((target_flags & MASK_STRING) != 0)
1602 target_flags = target_flags & ~MASK_STRING;
1604 else if (rs6000_select[1].string != NULL)
1606 /* For the powerpc-eabispe configuration, we set all these by
1607 default, so let's unset them if we manually set another
1608 CPU that is not the E500. */
1609 if (!rs6000_explicit_options.abi)
1611 if (!rs6000_explicit_options.spe)
1613 if (!rs6000_explicit_options.float_gprs)
1614 rs6000_float_gprs = 0;
1615 if (!rs6000_explicit_options.isel)
1619 /* Detect invalid option combinations with E500. */
1622 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1623 && rs6000_cpu != PROCESSOR_POWER5
1624 && rs6000_cpu != PROCESSOR_POWER6
1625 && rs6000_cpu != PROCESSOR_CELL);
1626 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1627 || rs6000_cpu == PROCESSOR_POWER5);
1628 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1629 || rs6000_cpu == PROCESSOR_POWER5
1630 || rs6000_cpu == PROCESSOR_POWER6);
1632 rs6000_sched_restricted_insns_priority
1633 = (rs6000_sched_groups ? 1 : 0);
1635 /* Handle -msched-costly-dep option. */
1636 rs6000_sched_costly_dep
1637 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1639 if (rs6000_sched_costly_dep_str)
1641 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1642 rs6000_sched_costly_dep = no_dep_costly;
1643 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1644 rs6000_sched_costly_dep = all_deps_costly;
1645 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1646 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1647 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1648 rs6000_sched_costly_dep = store_to_load_dep_costly;
1650 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1653 /* Handle -minsert-sched-nops option. */
1654 rs6000_sched_insert_nops
1655 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1657 if (rs6000_sched_insert_nops_str)
1659 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1660 rs6000_sched_insert_nops = sched_finish_none;
1661 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1662 rs6000_sched_insert_nops = sched_finish_pad_groups;
1663 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1664 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1666 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1669 #ifdef TARGET_REGNAMES
1670 /* If the user desires alternate register names, copy in the
1671 alternate names now. */
1672 if (TARGET_REGNAMES)
1673 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1676 /* Set aix_struct_return last, after the ABI is determined.
1677 If -maix-struct-return or -msvr4-struct-return was explicitly
1678 used, don't override with the ABI default. */
1679 if (!rs6000_explicit_options.aix_struct_ret)
1680 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1682 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1683 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1686 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1688 /* We can only guarantee the availability of DI pseudo-ops when
1689 assembling for 64-bit targets. */
1692 targetm.asm_out.aligned_op.di = NULL;
1693 targetm.asm_out.unaligned_op.di = NULL;
1696 /* Set branch target alignment, if not optimizing for size. */
1699 /* Cell wants to be aligned 8byte for dual issue. */
1700 if (rs6000_cpu == PROCESSOR_CELL)
1702 if (align_functions <= 0)
1703 align_functions = 8;
1704 if (align_jumps <= 0)
1706 if (align_loops <= 0)
1709 if (rs6000_align_branch_targets)
1711 if (align_functions <= 0)
1712 align_functions = 16;
1713 if (align_jumps <= 0)
1715 if (align_loops <= 0)
1718 if (align_jumps_max_skip <= 0)
1719 align_jumps_max_skip = 15;
1720 if (align_loops_max_skip <= 0)
1721 align_loops_max_skip = 15;
1724 /* Arrange to save and restore machine status around nested functions. */
1725 init_machine_status = rs6000_init_machine_status;
1727 /* We should always be splitting complex arguments, but we can't break
1728 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1729 if (DEFAULT_ABI != ABI_AIX)
1730 targetm.calls.split_complex_arg = NULL;
1732 /* Initialize rs6000_cost with the appropriate target costs. */
1734 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1738 case PROCESSOR_RIOS1:
1739 rs6000_cost = &rios1_cost;
1742 case PROCESSOR_RIOS2:
1743 rs6000_cost = &rios2_cost;
1746 case PROCESSOR_RS64A:
1747 rs6000_cost = &rs64a_cost;
1750 case PROCESSOR_MPCCORE:
1751 rs6000_cost = &mpccore_cost;
1754 case PROCESSOR_PPC403:
1755 rs6000_cost = &ppc403_cost;
1758 case PROCESSOR_PPC405:
1759 rs6000_cost = &ppc405_cost;
1762 case PROCESSOR_PPC440:
1763 rs6000_cost = &ppc440_cost;
1766 case PROCESSOR_PPC601:
1767 rs6000_cost = &ppc601_cost;
1770 case PROCESSOR_PPC603:
1771 rs6000_cost = &ppc603_cost;
1774 case PROCESSOR_PPC604:
1775 rs6000_cost = &ppc604_cost;
1778 case PROCESSOR_PPC604e:
1779 rs6000_cost = &ppc604e_cost;
1782 case PROCESSOR_PPC620:
1783 rs6000_cost = &ppc620_cost;
1786 case PROCESSOR_PPC630:
1787 rs6000_cost = &ppc630_cost;
1790 case PROCESSOR_CELL:
1791 rs6000_cost = &ppccell_cost;
1794 case PROCESSOR_PPC750:
1795 case PROCESSOR_PPC7400:
1796 rs6000_cost = &ppc750_cost;
1799 case PROCESSOR_PPC7450:
1800 rs6000_cost = &ppc7450_cost;
1803 case PROCESSOR_PPC8540:
1804 rs6000_cost = &ppc8540_cost;
1807 case PROCESSOR_POWER4:
1808 case PROCESSOR_POWER5:
1809 rs6000_cost = &power4_cost;
1812 case PROCESSOR_POWER6:
1813 rs6000_cost = &power6_cost;
1820 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1821 set_param_value ("simultaneous-prefetches",
1822 rs6000_cost->simultaneous_prefetches);
1823 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1824 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1825 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1826 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1827 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1828 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1831 /* Implement targetm.vectorize.builtin_mask_for_load. */
1833 rs6000_builtin_mask_for_load (void)
1836 return altivec_builtin_mask_for_load;
1841 /* Implement targetm.vectorize.builtin_conversion. */
1843 rs6000_builtin_conversion (enum tree_code code, tree type)
1845 if (!TARGET_ALTIVEC)
1851 switch (TYPE_MODE (type))
1854 return TYPE_UNSIGNED (type) ?
1855 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1856 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1865 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1867 rs6000_builtin_mul_widen_even (tree type)
1869 if (!TARGET_ALTIVEC)
1872 switch (TYPE_MODE (type))
1875 return TYPE_UNSIGNED (type) ?
1876 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1877 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1880 return TYPE_UNSIGNED (type) ?
1881 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1882 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1888 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1890 rs6000_builtin_mul_widen_odd (tree type)
1892 if (!TARGET_ALTIVEC)
1895 switch (TYPE_MODE (type))
1898 return TYPE_UNSIGNED (type) ?
1899 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1900 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1903 return TYPE_UNSIGNED (type) ?
1904 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1905 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1912 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1913 after applying N number of iterations. This routine does not determine
1914 how may iterations are required to reach desired alignment. */
1917 rs6000_vector_alignment_reachable (tree type ATTRIBUTE_UNUSED, bool is_packed)
1924 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
1927 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
1937 /* Assuming that all other types are naturally aligned. CHECKME! */
1942 /* Handle generic options of the form -mfoo=yes/no.
1943 NAME is the option name.
1944 VALUE is the option value.
1945 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1946 whether the option value is 'yes' or 'no' respectively. */
1948 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1952 else if (!strcmp (value, "yes"))
1954 else if (!strcmp (value, "no"))
1957 error ("unknown -m%s= option specified: '%s'", name, value);
1960 /* Validate and record the size specified with the -mtls-size option. */
1963 rs6000_parse_tls_size_option (void)
1965 if (rs6000_tls_size_string == 0)
1967 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1968 rs6000_tls_size = 16;
1969 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1970 rs6000_tls_size = 32;
1971 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1972 rs6000_tls_size = 64;
1974 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1978 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1980 if (DEFAULT_ABI == ABI_DARWIN)
1981 /* The Darwin libraries never set errno, so we might as well
1982 avoid calling them when that's the only reason we would. */
1983 flag_errno_math = 0;
1985 /* Double growth factor to counter reduced min jump length. */
1986 set_param_value ("max-grow-copy-bb-insns", 16);
1988 /* Enable section anchors by default.
1989 Skip section anchors for Objective C and Objective C++
1990 until front-ends fixed. */
1991 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1992 flag_section_anchors = 1;
1995 /* Implement TARGET_HANDLE_OPTION. */
1998 rs6000_handle_option (size_t code, const char *arg, int value)
2003 target_flags &= ~(MASK_POWER | MASK_POWER2
2004 | MASK_MULTIPLE | MASK_STRING);
2005 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2006 | MASK_MULTIPLE | MASK_STRING);
2008 case OPT_mno_powerpc:
2009 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2010 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2011 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2012 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2015 target_flags &= ~MASK_MINIMAL_TOC;
2016 TARGET_NO_FP_IN_TOC = 0;
2017 TARGET_NO_SUM_IN_TOC = 0;
2018 target_flags_explicit |= MASK_MINIMAL_TOC;
2019 #ifdef TARGET_USES_SYSV4_OPT
2020 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2021 just the same as -mminimal-toc. */
2022 target_flags |= MASK_MINIMAL_TOC;
2023 target_flags_explicit |= MASK_MINIMAL_TOC;
2027 #ifdef TARGET_USES_SYSV4_OPT
2029 /* Make -mtoc behave like -mminimal-toc. */
2030 target_flags |= MASK_MINIMAL_TOC;
2031 target_flags_explicit |= MASK_MINIMAL_TOC;
2035 #ifdef TARGET_USES_AIX64_OPT
2040 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2041 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2042 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2045 #ifdef TARGET_USES_AIX64_OPT
2050 target_flags &= ~MASK_POWERPC64;
2051 target_flags_explicit |= MASK_POWERPC64;
2054 case OPT_minsert_sched_nops_:
2055 rs6000_sched_insert_nops_str = arg;
2058 case OPT_mminimal_toc:
2061 TARGET_NO_FP_IN_TOC = 0;
2062 TARGET_NO_SUM_IN_TOC = 0;
2069 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2070 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2077 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2078 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2082 case OPT_mpowerpc_gpopt:
2083 case OPT_mpowerpc_gfxopt:
2086 target_flags |= MASK_POWERPC;
2087 target_flags_explicit |= MASK_POWERPC;
2091 case OPT_maix_struct_return:
2092 case OPT_msvr4_struct_return:
2093 rs6000_explicit_options.aix_struct_ret = true;
2097 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2101 rs6000_explicit_options.isel = true;
2102 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2106 rs6000_explicit_options.spe = true;
2107 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2111 rs6000_debug_name = arg;
2114 #ifdef TARGET_USES_SYSV4_OPT
2116 rs6000_abi_name = arg;
2120 rs6000_sdata_name = arg;
2123 case OPT_mtls_size_:
2124 rs6000_tls_size_string = arg;
2127 case OPT_mrelocatable:
2130 target_flags |= MASK_MINIMAL_TOC;
2131 target_flags_explicit |= MASK_MINIMAL_TOC;
2132 TARGET_NO_FP_IN_TOC = 1;
2136 case OPT_mrelocatable_lib:
2139 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2140 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2141 TARGET_NO_FP_IN_TOC = 1;
2145 target_flags &= ~MASK_RELOCATABLE;
2146 target_flags_explicit |= MASK_RELOCATABLE;
2152 if (!strcmp (arg, "altivec"))
2154 rs6000_explicit_options.abi = true;
2155 rs6000_altivec_abi = 1;
2158 else if (! strcmp (arg, "no-altivec"))
2160 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2161 the default for rs6000_spe_abi to be chosen later. */
2162 rs6000_altivec_abi = 0;
2164 else if (! strcmp (arg, "spe"))
2166 rs6000_explicit_options.abi = true;
2168 rs6000_altivec_abi = 0;
2169 if (!TARGET_SPE_ABI)
2170 error ("not configured for ABI: '%s'", arg);
2172 else if (! strcmp (arg, "no-spe"))
2174 rs6000_explicit_options.abi = true;
2178 /* These are here for testing during development only, do not
2179 document in the manual please. */
2180 else if (! strcmp (arg, "d64"))
2182 rs6000_darwin64_abi = 1;
2183 warning (0, "Using darwin64 ABI");
2185 else if (! strcmp (arg, "d32"))
2187 rs6000_darwin64_abi = 0;
2188 warning (0, "Using old darwin ABI");
2191 else if (! strcmp (arg, "ibmlongdouble"))
2193 rs6000_explicit_options.ieee = true;
2194 rs6000_ieeequad = 0;
2195 warning (0, "Using IBM extended precision long double");
2197 else if (! strcmp (arg, "ieeelongdouble"))
2199 rs6000_explicit_options.ieee = true;
2200 rs6000_ieeequad = 1;
2201 warning (0, "Using IEEE extended precision long double");
2206 error ("unknown ABI specified: '%s'", arg);
2212 rs6000_select[1].string = arg;
2216 rs6000_select[2].string = arg;
2219 case OPT_mtraceback_:
2220 rs6000_traceback_name = arg;
2223 case OPT_mfloat_gprs_:
2224 rs6000_explicit_options.float_gprs = true;
2225 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2226 rs6000_float_gprs = 1;
2227 else if (! strcmp (arg, "double"))
2228 rs6000_float_gprs = 2;
2229 else if (! strcmp (arg, "no"))
2230 rs6000_float_gprs = 0;
2233 error ("invalid option for -mfloat-gprs: '%s'", arg);
2238 case OPT_mlong_double_:
2239 rs6000_explicit_options.long_double = true;
2240 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2241 if (value != 64 && value != 128)
2243 error ("Unknown switch -mlong-double-%s", arg);
2244 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2248 rs6000_long_double_type_size = value;
2251 case OPT_msched_costly_dep_:
2252 rs6000_sched_costly_dep_str = arg;
2256 rs6000_explicit_options.alignment = true;
2257 if (! strcmp (arg, "power"))
2259 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2260 some C library functions, so warn about it. The flag may be
2261 useful for performance studies from time to time though, so
2262 don't disable it entirely. */
2263 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2264 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2265 " it is incompatible with the installed C and C++ libraries");
2266 rs6000_alignment_flags = MASK_ALIGN_POWER;
2268 else if (! strcmp (arg, "natural"))
2269 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2272 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2280 /* Do anything needed at the start of the asm file. */
2283 rs6000_file_start (void)
2287 const char *start = buffer;
2288 struct rs6000_cpu_select *ptr;
2289 const char *default_cpu = TARGET_CPU_DEFAULT;
2290 FILE *file = asm_out_file;
2292 default_file_start ();
2294 #ifdef TARGET_BI_ARCH
2295 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2299 if (flag_verbose_asm)
2301 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2302 rs6000_select[0].string = default_cpu;
2304 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2306 ptr = &rs6000_select[i];
2307 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2309 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2314 if (PPC405_ERRATUM77)
2316 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2320 #ifdef USING_ELFOS_H
2321 switch (rs6000_sdata)
2323 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2324 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2325 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2326 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2329 if (rs6000_sdata && g_switch_value)
2331 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2341 #ifdef HAVE_AS_GNU_ATTRIBUTE
2342 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2343 fprintf (file, "\t.gnu_attribute 4, %d\n",
2344 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2347 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2349 switch_to_section (toc_section);
2350 switch_to_section (text_section);
2355 /* Return nonzero if this function is known to have a null epilogue. */
2358 direct_return (void)
2360 if (reload_completed)
2362 rs6000_stack_t *info = rs6000_stack_info ();
2364 if (info->first_gp_reg_save == 32
2365 && info->first_fp_reg_save == 64
2366 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2367 && ! info->lr_save_p
2368 && ! info->cr_save_p
2369 && info->vrsave_mask == 0
2377 /* Return the number of instructions it takes to form a constant in an
2378 integer register. */
2381 num_insns_constant_wide (HOST_WIDE_INT value)
2383 /* signed constant loadable with {cal|addi} */
2384 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2387 /* constant loadable with {cau|addis} */
2388 else if ((value & 0xffff) == 0
2389 && (value >> 31 == -1 || value >> 31 == 0))
2392 #if HOST_BITS_PER_WIDE_INT == 64
2393 else if (TARGET_POWERPC64)
2395 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2396 HOST_WIDE_INT high = value >> 31;
2398 if (high == 0 || high == -1)
2404 return num_insns_constant_wide (high) + 1;
2406 return (num_insns_constant_wide (high)
2407 + num_insns_constant_wide (low) + 1);
2416 num_insns_constant (rtx op, enum machine_mode mode)
2418 HOST_WIDE_INT low, high;
2420 switch (GET_CODE (op))
2423 #if HOST_BITS_PER_WIDE_INT == 64
2424 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2425 && mask64_operand (op, mode))
2429 return num_insns_constant_wide (INTVAL (op));
2437 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2438 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2439 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2442 if (mode == VOIDmode || mode == DImode)
2444 high = CONST_DOUBLE_HIGH (op);
2445 low = CONST_DOUBLE_LOW (op);
2452 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2453 if (DECIMAL_FLOAT_MODE_P (mode))
2454 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2456 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2457 high = l[WORDS_BIG_ENDIAN == 0];
2458 low = l[WORDS_BIG_ENDIAN != 0];
2462 return (num_insns_constant_wide (low)
2463 + num_insns_constant_wide (high));
2466 if ((high == 0 && low >= 0)
2467 || (high == -1 && low < 0))
2468 return num_insns_constant_wide (low);
2470 else if (mask64_operand (op, mode))
2474 return num_insns_constant_wide (high) + 1;
2477 return (num_insns_constant_wide (high)
2478 + num_insns_constant_wide (low) + 1);
2486 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2487 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2488 corresponding element of the vector, but for V4SFmode and V2SFmode,
2489 the corresponding "float" is interpreted as an SImode integer. */
2491 static HOST_WIDE_INT
2492 const_vector_elt_as_int (rtx op, unsigned int elt)
2494 rtx tmp = CONST_VECTOR_ELT (op, elt);
2495 if (GET_MODE (op) == V4SFmode
2496 || GET_MODE (op) == V2SFmode)
2497 tmp = gen_lowpart (SImode, tmp);
2498 return INTVAL (tmp);
2501 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2502 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2503 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2504 all items are set to the same value and contain COPIES replicas of the
2505 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2506 operand and the others are set to the value of the operand's msb. */
2509 vspltis_constant (rtx op, unsigned step, unsigned copies)
2511 enum machine_mode mode = GET_MODE (op);
2512 enum machine_mode inner = GET_MODE_INNER (mode);
2515 unsigned nunits = GET_MODE_NUNITS (mode);
2516 unsigned bitsize = GET_MODE_BITSIZE (inner);
2517 unsigned mask = GET_MODE_MASK (inner);
2519 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2520 HOST_WIDE_INT splat_val = val;
2521 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2523 /* Construct the value to be splatted, if possible. If not, return 0. */
2524 for (i = 2; i <= copies; i *= 2)
2526 HOST_WIDE_INT small_val;
2528 small_val = splat_val >> bitsize;
2530 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2532 splat_val = small_val;
2535 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2536 if (EASY_VECTOR_15 (splat_val))
2539 /* Also check if we can splat, and then add the result to itself. Do so if
2540 the value is positive, of if the splat instruction is using OP's mode;
2541 for splat_val < 0, the splat and the add should use the same mode. */
2542 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2543 && (splat_val >= 0 || (step == 1 && copies == 1)))
2549 /* Check if VAL is present in every STEP-th element, and the
2550 other elements are filled with its most significant bit. */
2551 for (i = 0; i < nunits - 1; ++i)
2553 HOST_WIDE_INT desired_val;
2554 if (((i + 1) & (step - 1)) == 0)
2557 desired_val = msb_val;
2559 if (desired_val != const_vector_elt_as_int (op, i))
2567 /* Return true if OP is of the given MODE and can be synthesized
2568 with a vspltisb, vspltish or vspltisw. */
2571 easy_altivec_constant (rtx op, enum machine_mode mode)
2573 unsigned step, copies;
2575 if (mode == VOIDmode)
2576 mode = GET_MODE (op);
2577 else if (mode != GET_MODE (op))
2580 /* Start with a vspltisw. */
2581 step = GET_MODE_NUNITS (mode) / 4;
2584 if (vspltis_constant (op, step, copies))
2587 /* Then try with a vspltish. */
2593 if (vspltis_constant (op, step, copies))
2596 /* And finally a vspltisb. */
2602 if (vspltis_constant (op, step, copies))
2608 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2609 result is OP. Abort if it is not possible. */
2612 gen_easy_altivec_constant (rtx op)
2614 enum machine_mode mode = GET_MODE (op);
2615 int nunits = GET_MODE_NUNITS (mode);
2616 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2617 unsigned step = nunits / 4;
2618 unsigned copies = 1;
2620 /* Start with a vspltisw. */
2621 if (vspltis_constant (op, step, copies))
2622 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2624 /* Then try with a vspltish. */
2630 if (vspltis_constant (op, step, copies))
2631 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2633 /* And finally a vspltisb. */
2639 if (vspltis_constant (op, step, copies))
2640 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2646 output_vec_const_move (rtx *operands)
2649 enum machine_mode mode;
2654 mode = GET_MODE (dest);
2659 if (zero_constant (vec, mode))
2660 return "vxor %0,%0,%0";
2662 splat_vec = gen_easy_altivec_constant (vec);
2663 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2664 operands[1] = XEXP (splat_vec, 0);
2665 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2668 switch (GET_MODE (splat_vec))
2671 return "vspltisw %0,%1";
2674 return "vspltish %0,%1";
2677 return "vspltisb %0,%1";
2684 gcc_assert (TARGET_SPE);
2686 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2687 pattern of V1DI, V4HI, and V2SF.
2689 FIXME: We should probably return # and add post reload
2690 splitters for these, but this way is so easy ;-). */
2691 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2692 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2693 operands[1] = CONST_VECTOR_ELT (vec, 0);
2694 operands[2] = CONST_VECTOR_ELT (vec, 1);
2696 return "li %0,%1\n\tevmergelo %0,%0,%0";
2698 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2701 /* Initialize vector TARGET to VALS. */
2704 rs6000_expand_vector_init (rtx target, rtx vals)
2706 enum machine_mode mode = GET_MODE (target);
2707 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2708 int n_elts = GET_MODE_NUNITS (mode);
2709 int n_var = 0, one_var = -1;
2710 bool all_same = true, all_const_zero = true;
2714 for (i = 0; i < n_elts; ++i)
2716 x = XVECEXP (vals, 0, i);
2717 if (!CONSTANT_P (x))
2718 ++n_var, one_var = i;
2719 else if (x != CONST0_RTX (inner_mode))
2720 all_const_zero = false;
2722 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2728 if (mode != V4SFmode && all_const_zero)
2730 /* Zero register. */
2731 emit_insn (gen_rtx_SET (VOIDmode, target,
2732 gen_rtx_XOR (mode, target, target)));
2735 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2737 /* Splat immediate. */
2738 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2742 ; /* Splat vector element. */
2745 /* Load from constant pool. */
2746 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2751 /* Store value to stack temp. Load vector element. Splat. */
2754 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2755 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2756 XVECEXP (vals, 0, 0));
2757 x = gen_rtx_UNSPEC (VOIDmode,
2758 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2759 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2761 gen_rtx_SET (VOIDmode,
2764 x = gen_rtx_VEC_SELECT (inner_mode, target,
2765 gen_rtx_PARALLEL (VOIDmode,
2766 gen_rtvec (1, const0_rtx)));
2767 emit_insn (gen_rtx_SET (VOIDmode, target,
2768 gen_rtx_VEC_DUPLICATE (mode, x)));
2772 /* One field is non-constant. Load constant then overwrite
2776 rtx copy = copy_rtx (vals);
2778 /* Load constant part of vector, substitute neighboring value for
2780 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2781 rs6000_expand_vector_init (target, copy);
2783 /* Insert variable. */
2784 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2788 /* Construct the vector in memory one field at a time
2789 and load the whole vector. */
2790 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2791 for (i = 0; i < n_elts; i++)
2792 emit_move_insn (adjust_address_nv (mem, inner_mode,
2793 i * GET_MODE_SIZE (inner_mode)),
2794 XVECEXP (vals, 0, i));
2795 emit_move_insn (target, mem);
2798 /* Set field ELT of TARGET to VAL. */
2801 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2803 enum machine_mode mode = GET_MODE (target);
2804 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2805 rtx reg = gen_reg_rtx (mode);
2807 int width = GET_MODE_SIZE (inner_mode);
2810 /* Load single variable value. */
2811 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2812 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2813 x = gen_rtx_UNSPEC (VOIDmode,
2814 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2815 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2817 gen_rtx_SET (VOIDmode,
2821 /* Linear sequence. */
2822 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2823 for (i = 0; i < 16; ++i)
2824 XVECEXP (mask, 0, i) = GEN_INT (i);
2826 /* Set permute mask to insert element into target. */
2827 for (i = 0; i < width; ++i)
2828 XVECEXP (mask, 0, elt*width + i)
2829 = GEN_INT (i + 0x10);
2830 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2831 x = gen_rtx_UNSPEC (mode,
2832 gen_rtvec (3, target, reg,
2833 force_reg (V16QImode, x)),
2835 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2838 /* Extract field ELT from VEC into TARGET. */
2841 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2843 enum machine_mode mode = GET_MODE (vec);
2844 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2847 /* Allocate mode-sized buffer. */
2848 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2850 /* Add offset to field within buffer matching vector element. */
2851 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2853 /* Store single field into mode-sized buffer. */
2854 x = gen_rtx_UNSPEC (VOIDmode,
2855 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2856 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2858 gen_rtx_SET (VOIDmode,
2861 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2864 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2865 implement ANDing by the mask IN. */
2867 build_mask64_2_operands (rtx in, rtx *out)
2869 #if HOST_BITS_PER_WIDE_INT >= 64
2870 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2873 gcc_assert (GET_CODE (in) == CONST_INT);
2878 /* Assume c initially something like 0x00fff000000fffff. The idea
2879 is to rotate the word so that the middle ^^^^^^ group of zeros
2880 is at the MS end and can be cleared with an rldicl mask. We then
2881 rotate back and clear off the MS ^^ group of zeros with a
2883 c = ~c; /* c == 0xff000ffffff00000 */
2884 lsb = c & -c; /* lsb == 0x0000000000100000 */
2885 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2886 c = ~c; /* c == 0x00fff000000fffff */
2887 c &= -lsb; /* c == 0x00fff00000000000 */
2888 lsb = c & -c; /* lsb == 0x0000100000000000 */
2889 c = ~c; /* c == 0xff000fffffffffff */
2890 c &= -lsb; /* c == 0xff00000000000000 */
2892 while ((lsb >>= 1) != 0)
2893 shift++; /* shift == 44 on exit from loop */
2894 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2895 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2896 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2900 /* Assume c initially something like 0xff000f0000000000. The idea
2901 is to rotate the word so that the ^^^ middle group of zeros
2902 is at the LS end and can be cleared with an rldicr mask. We then
2903 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2905 lsb = c & -c; /* lsb == 0x0000010000000000 */
2906 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2907 c = ~c; /* c == 0x00fff0ffffffffff */
2908 c &= -lsb; /* c == 0x00fff00000000000 */
2909 lsb = c & -c; /* lsb == 0x0000100000000000 */
2910 c = ~c; /* c == 0xff000fffffffffff */
2911 c &= -lsb; /* c == 0xff00000000000000 */
2913 while ((lsb >>= 1) != 0)
2914 shift++; /* shift == 44 on exit from loop */
2915 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2916 m1 >>= shift; /* m1 == 0x0000000000000fff */
2917 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2920 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2921 masks will be all 1's. We are guaranteed more than one transition. */
2922 out[0] = GEN_INT (64 - shift);
2923 out[1] = GEN_INT (m1);
2924 out[2] = GEN_INT (shift);
2925 out[3] = GEN_INT (m2);
2933 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2936 invalid_e500_subreg (rtx op, enum machine_mode mode)
2938 if (TARGET_E500_DOUBLE)
2940 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2941 subreg:TI and reg:TF. */
2942 if (GET_CODE (op) == SUBREG
2943 && (mode == SImode || mode == DImode || mode == TImode)
2944 && REG_P (SUBREG_REG (op))
2945 && (GET_MODE (SUBREG_REG (op)) == DFmode
2946 || GET_MODE (SUBREG_REG (op)) == TFmode))
2949 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2951 if (GET_CODE (op) == SUBREG
2952 && (mode == DFmode || mode == TFmode)
2953 && REG_P (SUBREG_REG (op))
2954 && (GET_MODE (SUBREG_REG (op)) == DImode
2955 || GET_MODE (SUBREG_REG (op)) == TImode))
2960 && GET_CODE (op) == SUBREG
2962 && REG_P (SUBREG_REG (op))
2963 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2969 /* AIX increases natural record alignment to doubleword if the first
2970 field is an FP double while the FP fields remain word aligned. */
2973 rs6000_special_round_type_align (tree type, unsigned int computed,
2974 unsigned int specified)
2976 unsigned int align = MAX (computed, specified);
2977 tree field = TYPE_FIELDS (type);
2979 /* Skip all non field decls */
2980 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2981 field = TREE_CHAIN (field);
2983 if (field != NULL && field != type)
2985 type = TREE_TYPE (field);
2986 while (TREE_CODE (type) == ARRAY_TYPE)
2987 type = TREE_TYPE (type);
2989 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2990 align = MAX (align, 64);
2996 /* Darwin increases record alignment to the natural alignment of
3000 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3001 unsigned int specified)
3003 unsigned int align = MAX (computed, specified);
3005 if (TYPE_PACKED (type))
3008 /* Find the first field, looking down into aggregates. */
3010 tree field = TYPE_FIELDS (type);
3011 /* Skip all non field decls */
3012 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3013 field = TREE_CHAIN (field);
3016 type = TREE_TYPE (field);
3017 while (TREE_CODE (type) == ARRAY_TYPE)
3018 type = TREE_TYPE (type);
3019 } while (AGGREGATE_TYPE_P (type));
3021 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3022 align = MAX (align, TYPE_ALIGN (type));
3027 /* Return 1 for an operand in small memory on V.4/eabi. */
3030 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3031 enum machine_mode mode ATTRIBUTE_UNUSED)
3036 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3039 if (DEFAULT_ABI != ABI_V4)
3042 if (GET_CODE (op) == SYMBOL_REF)
3045 else if (GET_CODE (op) != CONST
3046 || GET_CODE (XEXP (op, 0)) != PLUS
3047 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3048 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3053 rtx sum = XEXP (op, 0);
3054 HOST_WIDE_INT summand;
3056 /* We have to be careful here, because it is the referenced address
3057 that must be 32k from _SDA_BASE_, not just the symbol. */
3058 summand = INTVAL (XEXP (sum, 1));
3059 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3062 sym_ref = XEXP (sum, 0);
3065 return SYMBOL_REF_SMALL_P (sym_ref);
3071 /* Return true if either operand is a general purpose register. */
3074 gpr_or_gpr_p (rtx op0, rtx op1)
3076 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3077 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3081 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3084 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3086 switch (GET_CODE (op))
3089 if (RS6000_SYMBOL_REF_TLS_P (op))
3091 else if (CONSTANT_POOL_ADDRESS_P (op))
3093 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3101 else if (! strcmp (XSTR (op, 0), toc_label_name))
3110 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3111 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3113 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3122 constant_pool_expr_p (rtx op)
3126 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3130 toc_relative_expr_p (rtx op)
3134 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3138 legitimate_constant_pool_address_p (rtx x)
3141 && GET_CODE (x) == PLUS
3142 && GET_CODE (XEXP (x, 0)) == REG
3143 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3144 && constant_pool_expr_p (XEXP (x, 1)));
3148 legitimate_small_data_p (enum machine_mode mode, rtx x)
3150 return (DEFAULT_ABI == ABI_V4
3151 && !flag_pic && !TARGET_TOC
3152 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3153 && small_data_operand (x, mode));
3156 /* SPE offset addressing is limited to 5-bits worth of double words. */
3157 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3160 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3162 unsigned HOST_WIDE_INT offset, extra;
3164 if (GET_CODE (x) != PLUS)
3166 if (GET_CODE (XEXP (x, 0)) != REG)
3168 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3170 if (legitimate_constant_pool_address_p (x))
3172 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3175 offset = INTVAL (XEXP (x, 1));
3183 /* AltiVec vector modes. Only reg+reg addressing is valid and
3184 constant offset zero should not occur due to canonicalization.
3185 Allow any offset when not strict before reload. */
3192 /* SPE vector modes. */
3193 return SPE_CONST_OFFSET_OK (offset);
3197 if (TARGET_E500_DOUBLE)
3198 return SPE_CONST_OFFSET_OK (offset);
3201 /* On e500v2, we may have:
3203 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3205 Which gets addressed with evldd instructions. */
3206 if (TARGET_E500_DOUBLE)
3207 return SPE_CONST_OFFSET_OK (offset);
3209 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3211 else if (offset & 3)
3216 if (TARGET_E500_DOUBLE)
3217 return (SPE_CONST_OFFSET_OK (offset)
3218 && SPE_CONST_OFFSET_OK (offset + 8));
3222 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3224 else if (offset & 3)
3235 return (offset < 0x10000) && (offset + extra < 0x10000);
3239 legitimate_indexed_address_p (rtx x, int strict)
3243 if (GET_CODE (x) != PLUS)
3249 /* Recognize the rtl generated by reload which we know will later be
3250 replaced with proper base and index regs. */
3252 && reload_in_progress
3253 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3257 return (REG_P (op0) && REG_P (op1)
3258 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3259 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3260 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3261 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3265 legitimate_indirect_address_p (rtx x, int strict)
3267 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3271 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3273 if (!TARGET_MACHO || !flag_pic
3274 || mode != SImode || GET_CODE (x) != MEM)
3278 if (GET_CODE (x) != LO_SUM)
3280 if (GET_CODE (XEXP (x, 0)) != REG)
3282 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3286 return CONSTANT_P (x);
3290 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3292 if (GET_CODE (x) != LO_SUM)
3294 if (GET_CODE (XEXP (x, 0)) != REG)
3296 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3298 /* Restrict addressing for DI because of our SUBREG hackery. */
3299 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3304 if (TARGET_ELF || TARGET_MACHO)
3306 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3310 if (GET_MODE_NUNITS (mode) != 1)
3312 if (GET_MODE_BITSIZE (mode) > 64
3313 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3314 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3317 return CONSTANT_P (x);
3324 /* Try machine-dependent ways of modifying an illegitimate address
3325 to be legitimate. If we find one, return the new, valid address.
3326 This is used from only one place: `memory_address' in explow.c.
3328 OLDX is the address as it was before break_out_memory_refs was
3329 called. In some cases it is useful to look at this to decide what
3332 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3334 It is always safe for this function to do nothing. It exists to
3335 recognize opportunities to optimize the output.
3337 On RS/6000, first check for the sum of a register with a constant
3338 integer that is out of range. If so, generate code to add the
3339 constant with the low-order 16 bits masked to the register and force
3340 this result into another register (this can be done with `cau').
3341 Then generate an address of REG+(CONST&0xffff), allowing for the
3342 possibility of bit 16 being a one.
3344 Then check for the sum of a register and something not constant, try to
3345 load the other things into a register and return the sum. */
3348 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3349 enum machine_mode mode)
3351 if (GET_CODE (x) == SYMBOL_REF)
3353 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3355 return rs6000_legitimize_tls_address (x, model);
3358 if (GET_CODE (x) == PLUS
3359 && GET_CODE (XEXP (x, 0)) == REG
3360 && GET_CODE (XEXP (x, 1)) == CONST_INT
3361 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3363 HOST_WIDE_INT high_int, low_int;
3365 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3366 high_int = INTVAL (XEXP (x, 1)) - low_int;
3367 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3368 GEN_INT (high_int)), 0);
3369 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3371 else if (GET_CODE (x) == PLUS
3372 && GET_CODE (XEXP (x, 0)) == REG
3373 && GET_CODE (XEXP (x, 1)) != CONST_INT
3374 && GET_MODE_NUNITS (mode) == 1
3375 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3377 || (((mode != DImode && mode != DFmode && mode != DDmode)
3378 || TARGET_E500_DOUBLE)
3379 && mode != TFmode && mode != TDmode))
3380 && (TARGET_POWERPC64 || mode != DImode)
3383 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3384 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3386 else if (ALTIVEC_VECTOR_MODE (mode))
3390 /* Make sure both operands are registers. */
3391 if (GET_CODE (x) == PLUS)
3392 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3393 force_reg (Pmode, XEXP (x, 1)));
3395 reg = force_reg (Pmode, x);
3398 else if (SPE_VECTOR_MODE (mode)
3399 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3400 || mode == DDmode || mode == TDmode
3401 || mode == DImode)))
3405 /* We accept [reg + reg] and [reg + OFFSET]. */
3407 if (GET_CODE (x) == PLUS)
3409 rtx op1 = XEXP (x, 0);
3410 rtx op2 = XEXP (x, 1);
3412 op1 = force_reg (Pmode, op1);
3414 if (GET_CODE (op2) != REG
3415 && (GET_CODE (op2) != CONST_INT
3416 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3417 op2 = force_reg (Pmode, op2);
3419 return gen_rtx_PLUS (Pmode, op1, op2);
3422 return force_reg (Pmode, x);
3428 && GET_CODE (x) != CONST_INT
3429 && GET_CODE (x) != CONST_DOUBLE
3431 && GET_MODE_NUNITS (mode) == 1
3432 && (GET_MODE_BITSIZE (mode) <= 32
3433 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3435 rtx reg = gen_reg_rtx (Pmode);
3436 emit_insn (gen_elf_high (reg, x));
3437 return gen_rtx_LO_SUM (Pmode, reg, x);
3439 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3442 && ! MACHO_DYNAMIC_NO_PIC_P
3444 && GET_CODE (x) != CONST_INT
3445 && GET_CODE (x) != CONST_DOUBLE
3447 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3451 rtx reg = gen_reg_rtx (Pmode);
3452 emit_insn (gen_macho_high (reg, x));
3453 return gen_rtx_LO_SUM (Pmode, reg, x);
3456 && constant_pool_expr_p (x)
3457 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3459 return create_TOC_reference (x);
3465 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3466 We need to emit DTP-relative relocations. */
3469 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3474 fputs ("\t.long\t", file);
3477 fputs (DOUBLE_INT_ASM_OP, file);
3482 output_addr_const (file, x);
3483 fputs ("@dtprel+0x8000", file);
3486 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3488 static GTY(()) rtx rs6000_tls_symbol;
3490 rs6000_tls_get_addr (void)
3492 if (!rs6000_tls_symbol)
3493 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3495 return rs6000_tls_symbol;
3498 /* Construct the SYMBOL_REF for TLS GOT references. */
3500 static GTY(()) rtx rs6000_got_symbol;
3502 rs6000_got_sym (void)
3504 if (!rs6000_got_symbol)
3506 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3507 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3508 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3511 return rs6000_got_symbol;
3514 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3515 this (thread-local) address. */
3518 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3522 dest = gen_reg_rtx (Pmode);
3523 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3529 tlsreg = gen_rtx_REG (Pmode, 13);
3530 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3534 tlsreg = gen_rtx_REG (Pmode, 2);
3535 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3539 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3543 tmp = gen_reg_rtx (Pmode);
3546 tlsreg = gen_rtx_REG (Pmode, 13);
3547 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3551 tlsreg = gen_rtx_REG (Pmode, 2);
3552 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3556 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3558 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3563 rtx r3, got, tga, tmp1, tmp2, eqv;
3565 /* We currently use relocations like @got@tlsgd for tls, which
3566 means the linker will handle allocation of tls entries, placing
3567 them in the .got section. So use a pointer to the .got section,
3568 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3569 or to secondary GOT sections used by 32-bit -fPIC. */
3571 got = gen_rtx_REG (Pmode, 2);
3575 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3578 rtx gsym = rs6000_got_sym ();
3579 got = gen_reg_rtx (Pmode);
3581 rs6000_emit_move (got, gsym, Pmode);
3587 tmp1 = gen_reg_rtx (Pmode);
3588 tmp2 = gen_reg_rtx (Pmode);
3589 tmp3 = gen_reg_rtx (Pmode);
3590 mem = gen_const_mem (Pmode, tmp1);
3592 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3593 emit_move_insn (tmp1,
3594 gen_rtx_REG (Pmode, LR_REGNO));
3595 emit_move_insn (tmp2, mem);
3596 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3597 last = emit_move_insn (got, tmp3);
3598 set_unique_reg_note (last, REG_EQUAL, gsym);
3599 maybe_encapsulate_block (first, last, gsym);
3604 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3606 r3 = gen_rtx_REG (Pmode, 3);
3608 insn = gen_tls_gd_64 (r3, got, addr);
3610 insn = gen_tls_gd_32 (r3, got, addr);
3613 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3614 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3615 insn = emit_call_insn (insn);
3616 CONST_OR_PURE_CALL_P (insn) = 1;
3617 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3618 insn = get_insns ();
3620 emit_libcall_block (insn, dest, r3, addr);
3622 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3624 r3 = gen_rtx_REG (Pmode, 3);
3626 insn = gen_tls_ld_64 (r3, got);
3628 insn = gen_tls_ld_32 (r3, got);
3631 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3632 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3633 insn = emit_call_insn (insn);
3634 CONST_OR_PURE_CALL_P (insn) = 1;
3635 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3636 insn = get_insns ();
3638 tmp1 = gen_reg_rtx (Pmode);
3639 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3641 emit_libcall_block (insn, tmp1, r3, eqv);
3642 if (rs6000_tls_size == 16)
3645 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3647 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3649 else if (rs6000_tls_size == 32)
3651 tmp2 = gen_reg_rtx (Pmode);
3653 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3655 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3658 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3660 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3664 tmp2 = gen_reg_rtx (Pmode);
3666 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3668 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3670 insn = gen_rtx_SET (Pmode, dest,
3671 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3677 /* IE, or 64-bit offset LE. */
3678 tmp2 = gen_reg_rtx (Pmode);
3680 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3682 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3685 insn = gen_tls_tls_64 (dest, tmp2, addr);
3687 insn = gen_tls_tls_32 (dest, tmp2, addr);
3695 /* Return 1 if X contains a thread-local symbol. */
3698 rs6000_tls_referenced_p (rtx x)
3700 if (! TARGET_HAVE_TLS)
3703 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3706 /* Return 1 if *X is a thread-local symbol. This is the same as
3707 rs6000_tls_symbol_ref except for the type of the unused argument. */
3710 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3712 return RS6000_SYMBOL_REF_TLS_P (*x);
3715 /* The convention appears to be to define this wherever it is used.
3716 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3717 is now used here. */
3718 #ifndef REG_MODE_OK_FOR_BASE_P
3719 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3722 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3723 replace the input X, or the original X if no replacement is called for.
3724 The output parameter *WIN is 1 if the calling macro should goto WIN,
3727 For RS/6000, we wish to handle large displacements off a base
3728 register by splitting the addend across an addiu/addis and the mem insn.
3729 This cuts number of extra insns needed from 3 to 1.
3731 On Darwin, we use this to generate code for floating point constants.
3732 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3733 The Darwin code is inside #if TARGET_MACHO because only then is
3734 machopic_function_base_name() defined. */
3736 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3737 int opnum, int type,
3738 int ind_levels ATTRIBUTE_UNUSED, int *win)
3740 /* We must recognize output that we have already generated ourselves. */
3741 if (GET_CODE (x) == PLUS
3742 && GET_CODE (XEXP (x, 0)) == PLUS
3743 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3744 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3745 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3747 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3748 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3749 opnum, (enum reload_type)type);
3755 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3756 && GET_CODE (x) == LO_SUM
3757 && GET_CODE (XEXP (x, 0)) == PLUS
3758 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3759 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3760 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3761 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3762 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3763 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3764 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3766 /* Result of previous invocation of this function on Darwin
3767 floating point constant. */
3768 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3769 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3770 opnum, (enum reload_type)type);
3776 /* Force ld/std non-word aligned offset into base register by wrapping
3778 if (GET_CODE (x) == PLUS
3779 && GET_CODE (XEXP (x, 0)) == REG
3780 && REGNO (XEXP (x, 0)) < 32
3781 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3782 && GET_CODE (XEXP (x, 1)) == CONST_INT
3783 && (INTVAL (XEXP (x, 1)) & 3) != 0
3784 && !ALTIVEC_VECTOR_MODE (mode)
3785 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3786 && TARGET_POWERPC64)
3788 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3789 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3790 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3791 opnum, (enum reload_type) type);
3796 if (GET_CODE (x) == PLUS
3797 && GET_CODE (XEXP (x, 0)) == REG
3798 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3799 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3800 && GET_CODE (XEXP (x, 1)) == CONST_INT
3801 && !SPE_VECTOR_MODE (mode)
3802 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3804 && !ALTIVEC_VECTOR_MODE (mode))
3806 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3807 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3809 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3811 /* Check for 32-bit overflow. */
3812 if (high + low != val)
3818 /* Reload the high part into a base reg; leave the low part
3819 in the mem directly. */
3821 x = gen_rtx_PLUS (GET_MODE (x),
3822 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3826 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3827 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3828 opnum, (enum reload_type)type);
3833 if (GET_CODE (x) == SYMBOL_REF
3834 && !ALTIVEC_VECTOR_MODE (mode)
3835 && !SPE_VECTOR_MODE (mode)
3837 && DEFAULT_ABI == ABI_DARWIN
3838 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3840 && DEFAULT_ABI == ABI_V4
3843 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3844 The same goes for DImode without 64-bit gprs and DFmode
3848 && (mode != DImode || TARGET_POWERPC64)
3849 && (mode != DFmode || TARGET_POWERPC64
3850 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3855 rtx offset = gen_rtx_CONST (Pmode,
3856 gen_rtx_MINUS (Pmode, x,
3857 machopic_function_base_sym ()));
3858 x = gen_rtx_LO_SUM (GET_MODE (x),
3859 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3860 gen_rtx_HIGH (Pmode, offset)), offset);
3864 x = gen_rtx_LO_SUM (GET_MODE (x),
3865 gen_rtx_HIGH (Pmode, x), x);
3867 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3868 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3869 opnum, (enum reload_type)type);
3874 /* Reload an offset address wrapped by an AND that represents the
3875 masking of the lower bits. Strip the outer AND and let reload
3876 convert the offset address into an indirect address. */
3878 && ALTIVEC_VECTOR_MODE (mode)
3879 && GET_CODE (x) == AND
3880 && GET_CODE (XEXP (x, 0)) == PLUS
3881 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3882 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3883 && GET_CODE (XEXP (x, 1)) == CONST_INT
3884 && INTVAL (XEXP (x, 1)) == -16)
3892 && constant_pool_expr_p (x)
3893 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3895 x = create_TOC_reference (x);
3903 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3904 that is a valid memory address for an instruction.
3905 The MODE argument is the machine mode for the MEM expression
3906 that wants to use this address.
3908 On the RS/6000, there are four valid address: a SYMBOL_REF that
3909 refers to a constant pool entry of an address (or the sum of it
3910 plus a constant), a short (16-bit signed) constant plus a register,
3911 the sum of two registers, or a register indirect, possibly with an
3912 auto-increment. For DFmode and DImode with a constant plus register,
3913 we must ensure that both words are addressable or PowerPC64 with offset
3916 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3917 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3918 because adjacent memory cells are accessed by adding word-sized offsets
3919 during assembly output. */
3921 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3923 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3925 && ALTIVEC_VECTOR_MODE (mode)
3926 && GET_CODE (x) == AND
3927 && GET_CODE (XEXP (x, 1)) == CONST_INT
3928 && INTVAL (XEXP (x, 1)) == -16)
3931 if (RS6000_SYMBOL_REF_TLS_P (x))
3933 if (legitimate_indirect_address_p (x, reg_ok_strict))
3935 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3936 && !ALTIVEC_VECTOR_MODE (mode)
3937 && !SPE_VECTOR_MODE (mode)
3940 /* Restrict addressing for DI because of our SUBREG hackery. */
3941 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3944 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3946 if (legitimate_small_data_p (mode, x))
3948 if (legitimate_constant_pool_address_p (x))
3950 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3952 && GET_CODE (x) == PLUS
3953 && GET_CODE (XEXP (x, 0)) == REG
3954 && (XEXP (x, 0) == virtual_stack_vars_rtx
3955 || XEXP (x, 0) == arg_pointer_rtx)
3956 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3958 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3963 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3965 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3966 && (TARGET_POWERPC64 || mode != DImode)
3967 && legitimate_indexed_address_p (x, reg_ok_strict))
3969 if (GET_CODE (x) == PRE_MODIFY
3973 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3975 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3976 && (TARGET_POWERPC64 || mode != DImode)
3977 && !ALTIVEC_VECTOR_MODE (mode)
3978 && !SPE_VECTOR_MODE (mode)
3979 /* Restrict addressing for DI because of our SUBREG hackery. */
3980 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3982 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
3983 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
3984 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
3985 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3987 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3992 /* Go to LABEL if ADDR (a legitimate address expression)
3993 has an effect that depends on the machine mode it is used for.
3995 On the RS/6000 this is true of all integral offsets (since AltiVec
3996 modes don't allow them) or is a pre-increment or decrement.
3998 ??? Except that due to conceptual problems in offsettable_address_p
3999 we can't really report the problems of integral offsets. So leave
4000 this assuming that the adjustable offset must be valid for the
4001 sub-words of a TFmode operand, which is what we had before. */
4004 rs6000_mode_dependent_address (rtx addr)
4006 switch (GET_CODE (addr))
4009 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4011 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4012 return val + 12 + 0x8000 >= 0x10000;
4022 return TARGET_UPDATE;
4031 /* More elaborate version of recog's offsettable_memref_p predicate
4032 that works around the ??? note of rs6000_mode_dependent_address.
4033 In particular it accepts
4035 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4037 in 32-bit mode, that the recog predicate rejects. */
4040 rs6000_offsettable_memref_p (rtx op)
4045 /* First mimic offsettable_memref_p. */
4046 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4049 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4050 the latter predicate knows nothing about the mode of the memory
4051 reference and, therefore, assumes that it is the largest supported
4052 mode (TFmode). As a consequence, legitimate offsettable memory
4053 references are rejected. rs6000_legitimate_offset_address_p contains
4054 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4055 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4058 /* Return number of consecutive hard regs needed starting at reg REGNO
4059 to hold something of mode MODE.
4060 This is ordinarily the length in words of a value of mode MODE
4061 but can be less for certain modes in special long registers.
4063 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4064 scalar instructions. The upper 32 bits are only available to the
4067 POWER and PowerPC GPRs hold 32 bits worth;
4068 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4071 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4073 if (FP_REGNO_P (regno))
4074 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4076 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4077 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4079 if (ALTIVEC_REGNO_P (regno))
4081 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4083 /* The value returned for SCmode in the E500 double case is 2 for
4084 ABI compatibility; storing an SCmode value in a single register
4085 would require function_arg and rs6000_spe_function_arg to handle
4086 SCmode so as to pass the value correctly in a pair of
4088 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
4089 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4091 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4094 /* Change register usage conditional on target flags. */
4096 rs6000_conditional_register_usage (void)
4100 /* Set MQ register fixed (already call_used) if not POWER
4101 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4106 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4108 fixed_regs[13] = call_used_regs[13]
4109 = call_really_used_regs[13] = 1;
4111 /* Conditionally disable FPRs. */
4112 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4113 for (i = 32; i < 64; i++)
4114 fixed_regs[i] = call_used_regs[i]
4115 = call_really_used_regs[i] = 1;
4117 /* The TOC register is not killed across calls in a way that is
4118 visible to the compiler. */
4119 if (DEFAULT_ABI == ABI_AIX)
4120 call_really_used_regs[2] = 0;
4122 if (DEFAULT_ABI == ABI_V4
4123 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4125 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4127 if (DEFAULT_ABI == ABI_V4
4128 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4130 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4131 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4132 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4134 if (DEFAULT_ABI == ABI_DARWIN
4135 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4136 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4137 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4138 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4140 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4141 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4142 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4145 global_regs[VSCR_REGNO] = 1;
4149 global_regs[SPEFSCR_REGNO] = 1;
4150 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4151 registers in prologues and epilogues. We no longer use r14
4152 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4153 pool for link-compatibility with older versions of GCC. Once
4154 "old" code has died out, we can return r14 to the allocation
4157 = call_used_regs[14]
4158 = call_really_used_regs[14] = 1;
4161 if (! TARGET_ALTIVEC)
4163 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4164 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4165 call_really_used_regs[VRSAVE_REGNO] = 1;
4168 if (TARGET_ALTIVEC_ABI)
4169 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4170 call_used_regs[i] = call_really_used_regs[i] = 1;
4173 /* Try to output insns to set TARGET equal to the constant C if it can
4174 be done in less than N insns. Do all computations in MODE.
4175 Returns the place where the output has been placed if it can be
4176 done and the insns have been emitted. If it would take more than N
4177 insns, zero is returned and no insns and emitted. */
4180 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4181 rtx source, int n ATTRIBUTE_UNUSED)
4183 rtx result, insn, set;
4184 HOST_WIDE_INT c0, c1;
4191 dest = gen_reg_rtx (mode);
4192 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4196 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4198 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4199 GEN_INT (INTVAL (source)
4200 & (~ (HOST_WIDE_INT) 0xffff))));
4201 emit_insn (gen_rtx_SET (VOIDmode, dest,
4202 gen_rtx_IOR (SImode, copy_rtx (result),
4203 GEN_INT (INTVAL (source) & 0xffff))));
4208 switch (GET_CODE (source))
4211 c0 = INTVAL (source);
4216 #if HOST_BITS_PER_WIDE_INT >= 64
4217 c0 = CONST_DOUBLE_LOW (source);
4220 c0 = CONST_DOUBLE_LOW (source);
4221 c1 = CONST_DOUBLE_HIGH (source);
4229 result = rs6000_emit_set_long_const (dest, c0, c1);
4236 insn = get_last_insn ();
4237 set = single_set (insn);
4238 if (! CONSTANT_P (SET_SRC (set)))
4239 set_unique_reg_note (insn, REG_EQUAL, source);
4244 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4245 fall back to a straight forward decomposition. We do this to avoid
4246 exponential run times encountered when looking for longer sequences
4247 with rs6000_emit_set_const. */
4249 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4251 if (!TARGET_POWERPC64)
4253 rtx operand1, operand2;
4255 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4257 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4259 emit_move_insn (operand1, GEN_INT (c1));
4260 emit_move_insn (operand2, GEN_INT (c2));
4264 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4267 ud2 = (c1 & 0xffff0000) >> 16;
4268 #if HOST_BITS_PER_WIDE_INT >= 64
4272 ud4 = (c2 & 0xffff0000) >> 16;
4274 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4275 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4278 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4280 emit_move_insn (dest, GEN_INT (ud1));
4283 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4284 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4287 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4290 emit_move_insn (dest, GEN_INT (ud2 << 16));
4292 emit_move_insn (copy_rtx (dest),
4293 gen_rtx_IOR (DImode, copy_rtx (dest),
4296 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4297 || (ud4 == 0 && ! (ud3 & 0x8000)))
4300 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4303 emit_move_insn (dest, GEN_INT (ud3 << 16));
4306 emit_move_insn (copy_rtx (dest),
4307 gen_rtx_IOR (DImode, copy_rtx (dest),
4309 emit_move_insn (copy_rtx (dest),
4310 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4313 emit_move_insn (copy_rtx (dest),
4314 gen_rtx_IOR (DImode, copy_rtx (dest),
4320 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4323 emit_move_insn (dest, GEN_INT (ud4 << 16));
4326 emit_move_insn (copy_rtx (dest),
4327 gen_rtx_IOR (DImode, copy_rtx (dest),
4330 emit_move_insn (copy_rtx (dest),
4331 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4334 emit_move_insn (copy_rtx (dest),
4335 gen_rtx_IOR (DImode, copy_rtx (dest),
4336 GEN_INT (ud2 << 16)));
4338 emit_move_insn (copy_rtx (dest),
4339 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4345 /* Helper for the following. Get rid of [r+r] memory refs
4346 in cases where it won't work (TImode, TFmode, TDmode). */
4349 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4351 if (GET_CODE (operands[0]) == MEM
4352 && GET_CODE (XEXP (operands[0], 0)) != REG
4353 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4354 && ! reload_in_progress)
4356 = replace_equiv_address (operands[0],
4357 copy_addr_to_reg (XEXP (operands[0], 0)));
4359 if (GET_CODE (operands[1]) == MEM
4360 && GET_CODE (XEXP (operands[1], 0)) != REG
4361 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4362 && ! reload_in_progress)
4364 = replace_equiv_address (operands[1],
4365 copy_addr_to_reg (XEXP (operands[1], 0)));
4368 /* Emit a move from SOURCE to DEST in mode MODE. */
4370 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4374 operands[1] = source;
4376 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4377 if (GET_CODE (operands[1]) == CONST_DOUBLE
4378 && ! FLOAT_MODE_P (mode)
4379 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4381 /* FIXME. This should never happen. */
4382 /* Since it seems that it does, do the safe thing and convert
4384 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4386 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4387 || FLOAT_MODE_P (mode)
4388 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4389 || CONST_DOUBLE_LOW (operands[1]) < 0)
4390 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4391 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4393 /* Check if GCC is setting up a block move that will end up using FP
4394 registers as temporaries. We must make sure this is acceptable. */
4395 if (GET_CODE (operands[0]) == MEM
4396 && GET_CODE (operands[1]) == MEM
4398 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4399 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4400 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4401 ? 32 : MEM_ALIGN (operands[0])))
4402 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4404 : MEM_ALIGN (operands[1]))))
4405 && ! MEM_VOLATILE_P (operands [0])
4406 && ! MEM_VOLATILE_P (operands [1]))
4408 emit_move_insn (adjust_address (operands[0], SImode, 0),
4409 adjust_address (operands[1], SImode, 0));
4410 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4411 adjust_address (copy_rtx (operands[1]), SImode, 4));
4415 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4416 && !gpc_reg_operand (operands[1], mode))
4417 operands[1] = force_reg (mode, operands[1]);
4419 if (mode == SFmode && ! TARGET_POWERPC
4420 && TARGET_HARD_FLOAT && TARGET_FPRS
4421 && GET_CODE (operands[0]) == MEM)
4425 if (reload_in_progress || reload_completed)
4426 regnum = true_regnum (operands[1]);
4427 else if (GET_CODE (operands[1]) == REG)
4428 regnum = REGNO (operands[1]);
4432 /* If operands[1] is a register, on POWER it may have
4433 double-precision data in it, so truncate it to single
4435 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4438 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4439 : gen_reg_rtx (mode));
4440 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4441 operands[1] = newreg;
4445 /* Recognize the case where operand[1] is a reference to thread-local
4446 data and load its address to a register. */
4447 if (rs6000_tls_referenced_p (operands[1]))
4449 enum tls_model model;
4450 rtx tmp = operands[1];
4453 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4455 addend = XEXP (XEXP (tmp, 0), 1);
4456 tmp = XEXP (XEXP (tmp, 0), 0);
4459 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4460 model = SYMBOL_REF_TLS_MODEL (tmp);
4461 gcc_assert (model != 0);
4463 tmp = rs6000_legitimize_tls_address (tmp, model);
4466 tmp = gen_rtx_PLUS (mode, tmp, addend);
4467 tmp = force_operand (tmp, operands[0]);
4472 /* Handle the case where reload calls us with an invalid address. */
4473 if (reload_in_progress && mode == Pmode
4474 && (! general_operand (operands[1], mode)
4475 || ! nonimmediate_operand (operands[0], mode)))
4478 /* 128-bit constant floating-point values on Darwin should really be
4479 loaded as two parts. */
4480 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4481 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4483 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4484 know how to get a DFmode SUBREG of a TFmode. */
4485 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4486 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4487 simplify_gen_subreg (imode, operands[1], mode, 0),
4489 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4490 GET_MODE_SIZE (imode)),
4491 simplify_gen_subreg (imode, operands[1], mode,
4492 GET_MODE_SIZE (imode)),
4497 /* FIXME: In the long term, this switch statement should go away
4498 and be replaced by a sequence of tests based on things like
4504 if (CONSTANT_P (operands[1])
4505 && GET_CODE (operands[1]) != CONST_INT)
4506 operands[1] = force_const_mem (mode, operands[1]);
4511 rs6000_eliminate_indexed_memrefs (operands);
4517 if (CONSTANT_P (operands[1])
4518 && ! easy_fp_constant (operands[1], mode))
4519 operands[1] = force_const_mem (mode, operands[1]);
4530 if (CONSTANT_P (operands[1])
4531 && !easy_vector_constant (operands[1], mode))
4532 operands[1] = force_const_mem (mode, operands[1]);
4537 /* Use default pattern for address of ELF small data */
4540 && DEFAULT_ABI == ABI_V4
4541 && (GET_CODE (operands[1]) == SYMBOL_REF
4542 || GET_CODE (operands[1]) == CONST)
4543 && small_data_operand (operands[1], mode))
4545 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4549 if (DEFAULT_ABI == ABI_V4
4550 && mode == Pmode && mode == SImode
4551 && flag_pic == 1 && got_operand (operands[1], mode))
4553 emit_insn (gen_movsi_got (operands[0], operands[1]));
4557 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4561 && CONSTANT_P (operands[1])
4562 && GET_CODE (operands[1]) != HIGH
4563 && GET_CODE (operands[1]) != CONST_INT)
4565 rtx target = (!can_create_pseudo_p ()
4567 : gen_reg_rtx (mode));
4569 /* If this is a function address on -mcall-aixdesc,
4570 convert it to the address of the descriptor. */
4571 if (DEFAULT_ABI == ABI_AIX
4572 && GET_CODE (operands[1]) == SYMBOL_REF
4573 && XSTR (operands[1], 0)[0] == '.')
4575 const char *name = XSTR (operands[1], 0);
4577 while (*name == '.')
4579 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4580 CONSTANT_POOL_ADDRESS_P (new_ref)
4581 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4582 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4583 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4584 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4585 operands[1] = new_ref;
4588 if (DEFAULT_ABI == ABI_DARWIN)
4591 if (MACHO_DYNAMIC_NO_PIC_P)
4593 /* Take care of any required data indirection. */
4594 operands[1] = rs6000_machopic_legitimize_pic_address (
4595 operands[1], mode, operands[0]);
4596 if (operands[0] != operands[1])
4597 emit_insn (gen_rtx_SET (VOIDmode,
4598 operands[0], operands[1]));
4602 emit_insn (gen_macho_high (target, operands[1]));
4603 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4607 emit_insn (gen_elf_high (target, operands[1]));
4608 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4612 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4613 and we have put it in the TOC, we just need to make a TOC-relative
4616 && GET_CODE (operands[1]) == SYMBOL_REF
4617 && constant_pool_expr_p (operands[1])
4618 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4619 get_pool_mode (operands[1])))
4621 operands[1] = create_TOC_reference (operands[1]);
4623 else if (mode == Pmode
4624 && CONSTANT_P (operands[1])
4625 && ((GET_CODE (operands[1]) != CONST_INT
4626 && ! easy_fp_constant (operands[1], mode))
4627 || (GET_CODE (operands[1]) == CONST_INT
4628 && num_insns_constant (operands[1], mode) > 2)
4629 || (GET_CODE (operands[0]) == REG
4630 && FP_REGNO_P (REGNO (operands[0]))))
4631 && GET_CODE (operands[1]) != HIGH
4632 && ! legitimate_constant_pool_address_p (operands[1])
4633 && ! toc_relative_expr_p (operands[1]))
4635 /* Emit a USE operation so that the constant isn't deleted if
4636 expensive optimizations are turned on because nobody
4637 references it. This should only be done for operands that
4638 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4639 This should not be done for operands that contain LABEL_REFs.
4640 For now, we just handle the obvious case. */
4641 if (GET_CODE (operands[1]) != LABEL_REF)
4642 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4645 /* Darwin uses a special PIC legitimizer. */
4646 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4649 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4651 if (operands[0] != operands[1])
4652 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4657 /* If we are to limit the number of things we put in the TOC and
4658 this is a symbol plus a constant we can add in one insn,
4659 just put the symbol in the TOC and add the constant. Don't do
4660 this if reload is in progress. */
4661 if (GET_CODE (operands[1]) == CONST
4662 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4663 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4664 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4665 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4666 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4667 && ! side_effects_p (operands[0]))
4670 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4671 rtx other = XEXP (XEXP (operands[1], 0), 1);
4673 sym = force_reg (mode, sym);
4675 emit_insn (gen_addsi3 (operands[0], sym, other));
4677 emit_insn (gen_adddi3 (operands[0], sym, other));
4681 operands[1] = force_const_mem (mode, operands[1]);
4684 && constant_pool_expr_p (XEXP (operands[1], 0))
4685 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4686 get_pool_constant (XEXP (operands[1], 0)),
4687 get_pool_mode (XEXP (operands[1], 0))))
4690 = gen_const_mem (mode,
4691 create_TOC_reference (XEXP (operands[1], 0)));
4692 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4698 rs6000_eliminate_indexed_memrefs (operands);
4702 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4704 gen_rtx_SET (VOIDmode,
4705 operands[0], operands[1]),
4706 gen_rtx_CLOBBER (VOIDmode,
4707 gen_rtx_SCRATCH (SImode)))));
4716 /* Above, we may have called force_const_mem which may have returned
4717 an invalid address. If we can, fix this up; otherwise, reload will
4718 have to deal with it. */
4719 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4720 operands[1] = validize_mem (operands[1]);
4723 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4726 /* Nonzero if we can use a floating-point register to pass this arg. */
4727 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4728 (SCALAR_FLOAT_MODE_P (MODE) \
4729 && (MODE) != SDmode \
4730 && (CUM)->fregno <= FP_ARG_MAX_REG \
4731 && TARGET_HARD_FLOAT && TARGET_FPRS)
4733 /* Nonzero if we can use an AltiVec register to pass this arg. */
4734 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4735 (ALTIVEC_VECTOR_MODE (MODE) \
4736 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4737 && TARGET_ALTIVEC_ABI \
4740 /* Return a nonzero value to say to return the function value in
4741 memory, just as large structures are always returned. TYPE will be
4742 the data type of the value, and FNTYPE will be the type of the
4743 function doing the returning, or @code{NULL} for libcalls.
4745 The AIX ABI for the RS/6000 specifies that all structures are
4746 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4747 specifies that structures <= 8 bytes are returned in r3/r4, but a
4748 draft put them in memory, and GCC used to implement the draft
4749 instead of the final standard. Therefore, aix_struct_return
4750 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4751 compatibility can change DRAFT_V4_STRUCT_RET to override the
4752 default, and -m switches get the final word. See
4753 rs6000_override_options for more details.
4755 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4756 long double support is enabled. These values are returned in memory.
4758 int_size_in_bytes returns -1 for variable size objects, which go in
4759 memory always. The cast to unsigned makes -1 > 8. */
4762 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4764 /* In the darwin64 abi, try to use registers for larger structs
4766 if (rs6000_darwin64_abi
4767 && TREE_CODE (type) == RECORD_TYPE
4768 && int_size_in_bytes (type) > 0)
4770 CUMULATIVE_ARGS valcum;
4774 valcum.fregno = FP_ARG_MIN_REG;
4775 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4776 /* Do a trial code generation as if this were going to be passed
4777 as an argument; if any part goes in memory, we return NULL. */
4778 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4781 /* Otherwise fall through to more conventional ABI rules. */
4784 if (AGGREGATE_TYPE_P (type)
4785 && (aix_struct_return
4786 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4789 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4790 modes only exist for GCC vector types if -maltivec. */
4791 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4792 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4795 /* Return synthetic vectors in memory. */
4796 if (TREE_CODE (type) == VECTOR_TYPE
4797 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4799 static bool warned_for_return_big_vectors = false;
4800 if (!warned_for_return_big_vectors)
4802 warning (0, "GCC vector returned by reference: "
4803 "non-standard ABI extension with no compatibility guarantee");
4804 warned_for_return_big_vectors = true;
4809 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4815 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4816 for a call to a function whose data type is FNTYPE.
4817 For a library call, FNTYPE is 0.
4819 For incoming args we set the number of arguments in the prototype large
4820 so we never return a PARALLEL. */
4823 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4824 rtx libname ATTRIBUTE_UNUSED, int incoming,
4825 int libcall, int n_named_args)
4827 static CUMULATIVE_ARGS zero_cumulative;
4829 *cum = zero_cumulative;
4831 cum->fregno = FP_ARG_MIN_REG;
4832 cum->vregno = ALTIVEC_ARG_MIN_REG;
4833 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4834 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4835 ? CALL_LIBCALL : CALL_NORMAL);
4836 cum->sysv_gregno = GP_ARG_MIN_REG;
4837 cum->stdarg = fntype
4838 && (TYPE_ARG_TYPES (fntype) != 0
4839 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4840 != void_type_node));
4842 cum->nargs_prototype = 0;
4843 if (incoming || cum->prototype)
4844 cum->nargs_prototype = n_named_args;
4846 /* Check for a longcall attribute. */
4847 if ((!fntype && rs6000_default_long_calls)
4849 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4850 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4851 cum->call_cookie |= CALL_LONG;
4853 if (TARGET_DEBUG_ARG)
4855 fprintf (stderr, "\ninit_cumulative_args:");
4858 tree ret_type = TREE_TYPE (fntype);
4859 fprintf (stderr, " ret code = %s,",
4860 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4863 if (cum->call_cookie & CALL_LONG)
4864 fprintf (stderr, " longcall,");
4866 fprintf (stderr, " proto = %d, nargs = %d\n",
4867 cum->prototype, cum->nargs_prototype);
4872 && TARGET_ALTIVEC_ABI
4873 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4875 error ("cannot return value in vector register because"
4876 " altivec instructions are disabled, use -maltivec"
4881 /* Return true if TYPE must be passed on the stack and not in registers. */
4884 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4886 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4887 return must_pass_in_stack_var_size (mode, type);
4889 return must_pass_in_stack_var_size_or_pad (mode, type);
4892 /* If defined, a C expression which determines whether, and in which
4893 direction, to pad out an argument with extra space. The value
4894 should be of type `enum direction': either `upward' to pad above
4895 the argument, `downward' to pad below, or `none' to inhibit
4898 For the AIX ABI structs are always stored left shifted in their
4902 function_arg_padding (enum machine_mode mode, tree type)
4904 #ifndef AGGREGATE_PADDING_FIXED
4905 #define AGGREGATE_PADDING_FIXED 0
4907 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4908 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4911 if (!AGGREGATE_PADDING_FIXED)
4913 /* GCC used to pass structures of the same size as integer types as
4914 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4915 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4916 passed padded downward, except that -mstrict-align further
4917 muddied the water in that multi-component structures of 2 and 4
4918 bytes in size were passed padded upward.
4920 The following arranges for best compatibility with previous
4921 versions of gcc, but removes the -mstrict-align dependency. */
4922 if (BYTES_BIG_ENDIAN)
4924 HOST_WIDE_INT size = 0;
4926 if (mode == BLKmode)
4928 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4929 size = int_size_in_bytes (type);
4932 size = GET_MODE_SIZE (mode);
4934 if (size == 1 || size == 2 || size == 4)
4940 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4942 if (type != 0 && AGGREGATE_TYPE_P (type))
4946 /* Fall back to the default. */
4947 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4950 /* If defined, a C expression that gives the alignment boundary, in bits,
4951 of an argument with the specified mode and type. If it is not defined,
4952 PARM_BOUNDARY is used for all arguments.
4954 V.4 wants long longs and doubles to be double word aligned. Just
4955 testing the mode size is a boneheaded way to do this as it means
4956 that other types such as complex int are also double word aligned.
4957 However, we're stuck with this because changing the ABI might break
4958 existing library interfaces.
4960 Doubleword align SPE vectors.
4961 Quadword align Altivec vectors.
4962 Quadword align large synthetic vector types. */
4965 function_arg_boundary (enum machine_mode mode, tree type)
4967 if (DEFAULT_ABI == ABI_V4
4968 && (GET_MODE_SIZE (mode) == 8
4969 || (TARGET_HARD_FLOAT
4971 && (mode == TFmode || mode == TDmode))))
4973 else if (SPE_VECTOR_MODE (mode)
4974 || (type && TREE_CODE (type) == VECTOR_TYPE
4975 && int_size_in_bytes (type) >= 8
4976 && int_size_in_bytes (type) < 16))
4978 else if (ALTIVEC_VECTOR_MODE (mode)
4979 || (type && TREE_CODE (type) == VECTOR_TYPE
4980 && int_size_in_bytes (type) >= 16))
4982 else if (rs6000_darwin64_abi && mode == BLKmode
4983 && type && TYPE_ALIGN (type) > 64)
4986 return PARM_BOUNDARY;
4989 /* For a function parm of MODE and TYPE, return the starting word in
4990 the parameter area. NWORDS of the parameter area are already used. */
4993 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4996 unsigned int parm_offset;
4998 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4999 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5000 return nwords + (-(parm_offset + nwords) & align);
5003 /* Compute the size (in words) of a function argument. */
5005 static unsigned long
5006 rs6000_arg_size (enum machine_mode mode, tree type)
5010 if (mode != BLKmode)
5011 size = GET_MODE_SIZE (mode);
5013 size = int_size_in_bytes (type);
5016 return (size + 3) >> 2;
5018 return (size + 7) >> 3;
5021 /* Use this to flush pending int fields. */
5024 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5025 HOST_WIDE_INT bitpos)
5027 unsigned int startbit, endbit;
5028 int intregs, intoffset;
5029 enum machine_mode mode;
5031 if (cum->intoffset == -1)
5034 intoffset = cum->intoffset;
5035 cum->intoffset = -1;
5037 if (intoffset % BITS_PER_WORD != 0)
5039 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5041 if (mode == BLKmode)
5043 /* We couldn't find an appropriate mode, which happens,
5044 e.g., in packed structs when there are 3 bytes to load.
5045 Back intoffset back to the beginning of the word in this
5047 intoffset = intoffset & -BITS_PER_WORD;
5051 startbit = intoffset & -BITS_PER_WORD;
5052 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5053 intregs = (endbit - startbit) / BITS_PER_WORD;
5054 cum->words += intregs;
5057 /* The darwin64 ABI calls for us to recurse down through structs,
5058 looking for elements passed in registers. Unfortunately, we have
5059 to track int register count here also because of misalignments
5060 in powerpc alignment mode. */
5063 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5065 HOST_WIDE_INT startbitpos)
5069 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5070 if (TREE_CODE (f) == FIELD_DECL)
5072 HOST_WIDE_INT bitpos = startbitpos;
5073 tree ftype = TREE_TYPE (f);
5074 enum machine_mode mode;
5075 if (ftype == error_mark_node)
5077 mode = TYPE_MODE (ftype);
5079 if (DECL_SIZE (f) != 0
5080 && host_integerp (bit_position (f), 1))
5081 bitpos += int_bit_position (f);
5083 /* ??? FIXME: else assume zero offset. */
5085 if (TREE_CODE (ftype) == RECORD_TYPE)
5086 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5087 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5089 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5090 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5091 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5093 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5095 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5099 else if (cum->intoffset == -1)
5100 cum->intoffset = bitpos;
5104 /* Update the data in CUM to advance over an argument
5105 of mode MODE and data type TYPE.
5106 (TYPE is null for libcalls where that information may not be available.)
5108 Note that for args passed by reference, function_arg will be called
5109 with MODE and TYPE set to that of the pointer to the arg, not the arg
5113 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5114 tree type, int named, int depth)
5118 /* Only tick off an argument if we're not recursing. */
5120 cum->nargs_prototype--;
5122 if (TARGET_ALTIVEC_ABI
5123 && (ALTIVEC_VECTOR_MODE (mode)
5124 || (type && TREE_CODE (type) == VECTOR_TYPE
5125 && int_size_in_bytes (type) == 16)))
5129 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5132 if (!TARGET_ALTIVEC)
5133 error ("cannot pass argument in vector register because"
5134 " altivec instructions are disabled, use -maltivec"
5137 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5138 even if it is going to be passed in a vector register.
5139 Darwin does the same for variable-argument functions. */
5140 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5141 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5151 /* Vector parameters must be 16-byte aligned. This places
5152 them at 2 mod 4 in terms of words in 32-bit mode, since
5153 the parameter save area starts at offset 24 from the
5154 stack. In 64-bit mode, they just have to start on an
5155 even word, since the parameter save area is 16-byte
5156 aligned. Space for GPRs is reserved even if the argument
5157 will be passed in memory. */
5159 align = (2 - cum->words) & 3;
5161 align = cum->words & 1;
5162 cum->words += align + rs6000_arg_size (mode, type);
5164 if (TARGET_DEBUG_ARG)
5166 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5168 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5169 cum->nargs_prototype, cum->prototype,
5170 GET_MODE_NAME (mode));
5174 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5176 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5179 else if (rs6000_darwin64_abi
5181 && TREE_CODE (type) == RECORD_TYPE
5182 && (size = int_size_in_bytes (type)) > 0)
5184 /* Variable sized types have size == -1 and are
5185 treated as if consisting entirely of ints.
5186 Pad to 16 byte boundary if needed. */
5187 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5188 && (cum->words % 2) != 0)
5190 /* For varargs, we can just go up by the size of the struct. */
5192 cum->words += (size + 7) / 8;
5195 /* It is tempting to say int register count just goes up by
5196 sizeof(type)/8, but this is wrong in a case such as
5197 { int; double; int; } [powerpc alignment]. We have to
5198 grovel through the fields for these too. */
5200 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5201 rs6000_darwin64_record_arg_advance_flush (cum,
5202 size * BITS_PER_UNIT);
5205 else if (DEFAULT_ABI == ABI_V4)
5207 if (TARGET_HARD_FLOAT && TARGET_FPRS
5208 && (mode == SFmode || mode == DFmode
5209 || mode == DDmode || mode == TDmode
5210 || (mode == TFmode && !TARGET_IEEEQUAD)))
5212 /* _Decimal128 must use an even/odd register pair. This assumes
5213 that the register number is odd when fregno is odd. */
5214 if (mode == TDmode && (cum->fregno % 2) == 1)
5217 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5218 <= FP_ARG_V4_MAX_REG)
5219 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5222 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5223 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5224 cum->words += cum->words & 1;
5225 cum->words += rs6000_arg_size (mode, type);
5230 int n_words = rs6000_arg_size (mode, type);
5231 int gregno = cum->sysv_gregno;
5233 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5234 (r7,r8) or (r9,r10). As does any other 2 word item such
5235 as complex int due to a historical mistake. */
5237 gregno += (1 - gregno) & 1;
5239 /* Multi-reg args are not split between registers and stack. */
5240 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5242 /* Long long and SPE vectors are aligned on the stack.
5243 So are other 2 word items such as complex int due to
5244 a historical mistake. */
5246 cum->words += cum->words & 1;
5247 cum->words += n_words;
5250 /* Note: continuing to accumulate gregno past when we've started
5251 spilling to the stack indicates the fact that we've started
5252 spilling to the stack to expand_builtin_saveregs. */
5253 cum->sysv_gregno = gregno + n_words;
5256 if (TARGET_DEBUG_ARG)
5258 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5259 cum->words, cum->fregno);
5260 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5261 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5262 fprintf (stderr, "mode = %4s, named = %d\n",
5263 GET_MODE_NAME (mode), named);
5268 int n_words = rs6000_arg_size (mode, type);
5269 int start_words = cum->words;
5270 int align_words = rs6000_parm_start (mode, type, start_words);
5272 cum->words = align_words + n_words;
5274 if (SCALAR_FLOAT_MODE_P (mode)
5276 && TARGET_HARD_FLOAT && TARGET_FPRS)
5278 /* _Decimal128 must be passed in an even/odd float register pair.
5279 This assumes that the register number is odd when fregno is
5281 if (mode == TDmode && (cum->fregno % 2) == 1)
5283 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5286 if (TARGET_DEBUG_ARG)
5288 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5289 cum->words, cum->fregno);
5290 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5291 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5292 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5293 named, align_words - start_words, depth);
5299 spe_build_register_parallel (enum machine_mode mode, int gregno)
5306 r1 = gen_rtx_REG (DImode, gregno);
5307 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5308 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5312 r1 = gen_rtx_REG (DImode, gregno);
5313 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5314 r3 = gen_rtx_REG (DImode, gregno + 2);
5315 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5316 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5319 r1 = gen_rtx_REG (DImode, gregno);
5320 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5321 r3 = gen_rtx_REG (DImode, gregno + 2);
5322 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5323 r5 = gen_rtx_REG (DImode, gregno + 4);
5324 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5325 r7 = gen_rtx_REG (DImode, gregno + 6);
5326 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5327 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5334 /* Determine where to put a SIMD argument on the SPE. */
5336 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5339 int gregno = cum->sysv_gregno;
5341 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5342 are passed and returned in a pair of GPRs for ABI compatibility. */
5343 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5344 || mode == TFmode || mode == TCmode))
5346 int n_words = rs6000_arg_size (mode, type);
5348 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5350 gregno += (1 - gregno) & 1;
5352 /* Multi-reg args are not split between registers and stack. */
5353 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5356 return spe_build_register_parallel (mode, gregno);
5360 int n_words = rs6000_arg_size (mode, type);
5362 /* SPE vectors are put in odd registers. */
5363 if (n_words == 2 && (gregno & 1) == 0)
5366 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5369 enum machine_mode m = SImode;
5371 r1 = gen_rtx_REG (m, gregno);
5372 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5373 r2 = gen_rtx_REG (m, gregno + 1);
5374 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5375 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5382 if (gregno <= GP_ARG_MAX_REG)
5383 return gen_rtx_REG (mode, gregno);
5389 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5390 structure between cum->intoffset and bitpos to integer registers. */
5393 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5394 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5396 enum machine_mode mode;
5398 unsigned int startbit, endbit;
5399 int this_regno, intregs, intoffset;
5402 if (cum->intoffset == -1)
5405 intoffset = cum->intoffset;
5406 cum->intoffset = -1;
5408 /* If this is the trailing part of a word, try to only load that
5409 much into the register. Otherwise load the whole register. Note
5410 that in the latter case we may pick up unwanted bits. It's not a
5411 problem at the moment but may wish to revisit. */
5413 if (intoffset % BITS_PER_WORD != 0)
5415 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5417 if (mode == BLKmode)
5419 /* We couldn't find an appropriate mode, which happens,
5420 e.g., in packed structs when there are 3 bytes to load.
5421 Back intoffset back to the beginning of the word in this
5423 intoffset = intoffset & -BITS_PER_WORD;
5430 startbit = intoffset & -BITS_PER_WORD;
5431 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5432 intregs = (endbit - startbit) / BITS_PER_WORD;
5433 this_regno = cum->words + intoffset / BITS_PER_WORD;
5435 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5438 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5442 intoffset /= BITS_PER_UNIT;
5445 regno = GP_ARG_MIN_REG + this_regno;
5446 reg = gen_rtx_REG (mode, regno);
5448 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5451 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5455 while (intregs > 0);
5458 /* Recursive workhorse for the following. */
5461 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5462 HOST_WIDE_INT startbitpos, rtx rvec[],
5467 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5468 if (TREE_CODE (f) == FIELD_DECL)
5470 HOST_WIDE_INT bitpos = startbitpos;
5471 tree ftype = TREE_TYPE (f);
5472 enum machine_mode mode;
5473 if (ftype == error_mark_node)
5475 mode = TYPE_MODE (ftype);
5477 if (DECL_SIZE (f) != 0
5478 && host_integerp (bit_position (f), 1))
5479 bitpos += int_bit_position (f);
5481 /* ??? FIXME: else assume zero offset. */
5483 if (TREE_CODE (ftype) == RECORD_TYPE)
5484 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5485 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5490 case SCmode: mode = SFmode; break;
5491 case DCmode: mode = DFmode; break;
5492 case TCmode: mode = TFmode; break;
5496 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5498 = gen_rtx_EXPR_LIST (VOIDmode,
5499 gen_rtx_REG (mode, cum->fregno++),
5500 GEN_INT (bitpos / BITS_PER_UNIT));
5501 if (mode == TFmode || mode == TDmode)
5504 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5506 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5508 = gen_rtx_EXPR_LIST (VOIDmode,
5509 gen_rtx_REG (mode, cum->vregno++),
5510 GEN_INT (bitpos / BITS_PER_UNIT));
5512 else if (cum->intoffset == -1)
5513 cum->intoffset = bitpos;
5517 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5518 the register(s) to be used for each field and subfield of a struct
5519 being passed by value, along with the offset of where the
5520 register's value may be found in the block. FP fields go in FP
5521 register, vector fields go in vector registers, and everything
5522 else goes in int registers, packed as in memory.
5524 This code is also used for function return values. RETVAL indicates
5525 whether this is the case.
5527 Much of this is taken from the SPARC V9 port, which has a similar
5528 calling convention. */
5531 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5532 int named, bool retval)
5534 rtx rvec[FIRST_PSEUDO_REGISTER];
5535 int k = 1, kbase = 1;
5536 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5537 /* This is a copy; modifications are not visible to our caller. */
5538 CUMULATIVE_ARGS copy_cum = *orig_cum;
5539 CUMULATIVE_ARGS *cum = ©_cum;
5541 /* Pad to 16 byte boundary if needed. */
5542 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5543 && (cum->words % 2) != 0)
5550 /* Put entries into rvec[] for individual FP and vector fields, and
5551 for the chunks of memory that go in int regs. Note we start at
5552 element 1; 0 is reserved for an indication of using memory, and
5553 may or may not be filled in below. */
5554 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5555 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5557 /* If any part of the struct went on the stack put all of it there.
5558 This hack is because the generic code for
5559 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5560 parts of the struct are not at the beginning. */
5564 return NULL_RTX; /* doesn't go in registers at all */
5566 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5568 if (k > 1 || cum->use_stack)
5569 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5574 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5577 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5581 rtx rvec[GP_ARG_NUM_REG + 1];
5583 if (align_words >= GP_ARG_NUM_REG)
5586 n_units = rs6000_arg_size (mode, type);
5588 /* Optimize the simple case where the arg fits in one gpr, except in
5589 the case of BLKmode due to assign_parms assuming that registers are
5590 BITS_PER_WORD wide. */
5592 || (n_units == 1 && mode != BLKmode))
5593 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5596 if (align_words + n_units > GP_ARG_NUM_REG)
5597 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5598 using a magic NULL_RTX component.
5599 This is not strictly correct. Only some of the arg belongs in
5600 memory, not all of it. However, the normal scheme using
5601 function_arg_partial_nregs can result in unusual subregs, eg.
5602 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5603 store the whole arg to memory is often more efficient than code
5604 to store pieces, and we know that space is available in the right
5605 place for the whole arg. */
5606 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5611 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5612 rtx off = GEN_INT (i++ * 4);
5613 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5615 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5617 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5620 /* Determine where to put an argument to a function.
5621 Value is zero to push the argument on the stack,
5622 or a hard register in which to store the argument.
5624 MODE is the argument's machine mode.
5625 TYPE is the data type of the argument (as a tree).
5626 This is null for libcalls where that information may
5628 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5629 the preceding args and about the function being called. It is
5630 not modified in this routine.
5631 NAMED is nonzero if this argument is a named parameter
5632 (otherwise it is an extra parameter matching an ellipsis).
5634 On RS/6000 the first eight words of non-FP are normally in registers
5635 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5636 Under V.4, the first 8 FP args are in registers.
5638 If this is floating-point and no prototype is specified, we use
5639 both an FP and integer register (or possibly FP reg and stack). Library
5640 functions (when CALL_LIBCALL is set) always have the proper types for args,
5641 so we can pass the FP value just in one register. emit_library_function
5642 doesn't support PARALLEL anyway.
5644 Note that for args passed by reference, function_arg will be called
5645 with MODE and TYPE set to that of the pointer to the arg, not the arg
5649 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5650 tree type, int named)
5652 enum rs6000_abi abi = DEFAULT_ABI;
5654 /* Return a marker to indicate whether CR1 needs to set or clear the
5655 bit that V.4 uses to say fp args were passed in registers.
5656 Assume that we don't need the marker for software floating point,
5657 or compiler generated library calls. */
5658 if (mode == VOIDmode)
5661 && (cum->call_cookie & CALL_LIBCALL) == 0
5663 || (cum->nargs_prototype < 0
5664 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5666 /* For the SPE, we need to crxor CR6 always. */
5668 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5669 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5670 return GEN_INT (cum->call_cookie
5671 | ((cum->fregno == FP_ARG_MIN_REG)
5672 ? CALL_V4_SET_FP_ARGS
5673 : CALL_V4_CLEAR_FP_ARGS));
5676 return GEN_INT (cum->call_cookie);
5679 if (rs6000_darwin64_abi && mode == BLKmode
5680 && TREE_CODE (type) == RECORD_TYPE)
5682 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5683 if (rslt != NULL_RTX)
5685 /* Else fall through to usual handling. */
5688 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5689 if (TARGET_64BIT && ! cum->prototype)
5691 /* Vector parameters get passed in vector register
5692 and also in GPRs or memory, in absence of prototype. */
5695 align_words = (cum->words + 1) & ~1;
5697 if (align_words >= GP_ARG_NUM_REG)
5703 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5705 return gen_rtx_PARALLEL (mode,
5707 gen_rtx_EXPR_LIST (VOIDmode,
5709 gen_rtx_EXPR_LIST (VOIDmode,
5710 gen_rtx_REG (mode, cum->vregno),
5714 return gen_rtx_REG (mode, cum->vregno);
5715 else if (TARGET_ALTIVEC_ABI
5716 && (ALTIVEC_VECTOR_MODE (mode)
5717 || (type && TREE_CODE (type) == VECTOR_TYPE
5718 && int_size_in_bytes (type) == 16)))
5720 if (named || abi == ABI_V4)
5724 /* Vector parameters to varargs functions under AIX or Darwin
5725 get passed in memory and possibly also in GPRs. */
5726 int align, align_words, n_words;
5727 enum machine_mode part_mode;
5729 /* Vector parameters must be 16-byte aligned. This places them at
5730 2 mod 4 in terms of words in 32-bit mode, since the parameter
5731 save area starts at offset 24 from the stack. In 64-bit mode,
5732 they just have to start on an even word, since the parameter
5733 save area is 16-byte aligned. */
5735 align = (2 - cum->words) & 3;
5737 align = cum->words & 1;
5738 align_words = cum->words + align;
5740 /* Out of registers? Memory, then. */
5741 if (align_words >= GP_ARG_NUM_REG)
5744 if (TARGET_32BIT && TARGET_POWERPC64)
5745 return rs6000_mixed_function_arg (mode, type, align_words);
5747 /* The vector value goes in GPRs. Only the part of the
5748 value in GPRs is reported here. */
5750 n_words = rs6000_arg_size (mode, type);
5751 if (align_words + n_words > GP_ARG_NUM_REG)
5752 /* Fortunately, there are only two possibilities, the value
5753 is either wholly in GPRs or half in GPRs and half not. */
5756 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5759 else if (TARGET_SPE_ABI && TARGET_SPE
5760 && (SPE_VECTOR_MODE (mode)
5761 || (TARGET_E500_DOUBLE && (mode == DFmode
5766 || mode == TCmode))))
5767 return rs6000_spe_function_arg (cum, mode, type);
5769 else if (abi == ABI_V4)
5771 if (TARGET_HARD_FLOAT && TARGET_FPRS
5772 && (mode == SFmode || mode == DFmode
5773 || (mode == TFmode && !TARGET_IEEEQUAD)
5774 || mode == DDmode || mode == TDmode))
5776 /* _Decimal128 must use an even/odd register pair. This assumes
5777 that the register number is odd when fregno is odd. */
5778 if (mode == TDmode && (cum->fregno % 2) == 1)
5781 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5782 <= FP_ARG_V4_MAX_REG)
5783 return gen_rtx_REG (mode, cum->fregno);
5789 int n_words = rs6000_arg_size (mode, type);
5790 int gregno = cum->sysv_gregno;
5792 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5793 (r7,r8) or (r9,r10). As does any other 2 word item such
5794 as complex int due to a historical mistake. */
5796 gregno += (1 - gregno) & 1;
5798 /* Multi-reg args are not split between registers and stack. */
5799 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5802 if (TARGET_32BIT && TARGET_POWERPC64)
5803 return rs6000_mixed_function_arg (mode, type,
5804 gregno - GP_ARG_MIN_REG);
5805 return gen_rtx_REG (mode, gregno);
5810 int align_words = rs6000_parm_start (mode, type, cum->words);
5812 /* _Decimal128 must be passed in an even/odd float register pair.
5813 This assumes that the register number is odd when fregno is odd. */
5814 if (mode == TDmode && (cum->fregno % 2) == 1)
5817 if (USE_FP_FOR_ARG_P (cum, mode, type))
5819 rtx rvec[GP_ARG_NUM_REG + 1];
5823 enum machine_mode fmode = mode;
5824 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5826 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5828 /* Currently, we only ever need one reg here because complex
5829 doubles are split. */
5830 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5831 && (fmode == TFmode || fmode == TDmode));
5833 /* Long double or _Decimal128 split over regs and memory. */
5834 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5837 /* Do we also need to pass this arg in the parameter save
5840 && (cum->nargs_prototype <= 0
5841 || (DEFAULT_ABI == ABI_AIX
5843 && align_words >= GP_ARG_NUM_REG)));
5845 if (!needs_psave && mode == fmode)
5846 return gen_rtx_REG (fmode, cum->fregno);
5851 /* Describe the part that goes in gprs or the stack.
5852 This piece must come first, before the fprs. */
5853 if (align_words < GP_ARG_NUM_REG)
5855 unsigned long n_words = rs6000_arg_size (mode, type);
5857 if (align_words + n_words > GP_ARG_NUM_REG
5858 || (TARGET_32BIT && TARGET_POWERPC64))
5860 /* If this is partially on the stack, then we only
5861 include the portion actually in registers here. */
5862 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5865 if (align_words + n_words > GP_ARG_NUM_REG)
5866 /* Not all of the arg fits in gprs. Say that it
5867 goes in memory too, using a magic NULL_RTX
5868 component. Also see comment in
5869 rs6000_mixed_function_arg for why the normal
5870 function_arg_partial_nregs scheme doesn't work
5872 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5876 r = gen_rtx_REG (rmode,
5877 GP_ARG_MIN_REG + align_words);
5878 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5879 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5881 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5885 /* The whole arg fits in gprs. */
5886 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5887 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5891 /* It's entirely in memory. */
5892 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5895 /* Describe where this piece goes in the fprs. */
5896 r = gen_rtx_REG (fmode, cum->fregno);
5897 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5899 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5901 else if (align_words < GP_ARG_NUM_REG)
5903 if (TARGET_32BIT && TARGET_POWERPC64)
5904 return rs6000_mixed_function_arg (mode, type, align_words);
5906 if (mode == BLKmode)
5909 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5916 /* For an arg passed partly in registers and partly in memory, this is
5917 the number of bytes passed in registers. For args passed entirely in
5918 registers or entirely in memory, zero. When an arg is described by a
5919 PARALLEL, perhaps using more than one register type, this function
5920 returns the number of bytes used by the first element of the PARALLEL. */
5923 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5924 tree type, bool named)
5929 if (DEFAULT_ABI == ABI_V4)
5932 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5933 && cum->nargs_prototype >= 0)
5936 /* In this complicated case we just disable the partial_nregs code. */
5937 if (rs6000_darwin64_abi && mode == BLKmode
5938 && TREE_CODE (type) == RECORD_TYPE
5939 && int_size_in_bytes (type) > 0)
5942 align_words = rs6000_parm_start (mode, type, cum->words);
5944 if (USE_FP_FOR_ARG_P (cum, mode, type))
5946 /* If we are passing this arg in the fixed parameter save area
5947 (gprs or memory) as well as fprs, then this function should
5948 return the number of partial bytes passed in the parameter
5949 save area rather than partial bytes passed in fprs. */
5951 && (cum->nargs_prototype <= 0
5952 || (DEFAULT_ABI == ABI_AIX
5954 && align_words >= GP_ARG_NUM_REG)))
5956 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5957 > FP_ARG_MAX_REG + 1)
5958 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5959 else if (cum->nargs_prototype >= 0)
5963 if (align_words < GP_ARG_NUM_REG
5964 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5965 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5967 if (ret != 0 && TARGET_DEBUG_ARG)
5968 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5973 /* A C expression that indicates when an argument must be passed by
5974 reference. If nonzero for an argument, a copy of that argument is
5975 made in memory and a pointer to the argument is passed instead of
5976 the argument itself. The pointer is passed in whatever way is
5977 appropriate for passing a pointer to that type.
5979 Under V.4, aggregates and long double are passed by reference.
5981 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5982 reference unless the AltiVec vector extension ABI is in force.
5984 As an extension to all ABIs, variable sized types are passed by
5988 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5989 enum machine_mode mode, tree type,
5990 bool named ATTRIBUTE_UNUSED)
5992 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5994 if (TARGET_DEBUG_ARG)
5995 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6002 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6004 if (TARGET_DEBUG_ARG)
6005 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6009 if (int_size_in_bytes (type) < 0)
6011 if (TARGET_DEBUG_ARG)
6012 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6016 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6017 modes only exist for GCC vector types if -maltivec. */
6018 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6020 if (TARGET_DEBUG_ARG)
6021 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6025 /* Pass synthetic vectors in memory. */
6026 if (TREE_CODE (type) == VECTOR_TYPE
6027 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6029 static bool warned_for_pass_big_vectors = false;
6030 if (TARGET_DEBUG_ARG)
6031 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6032 if (!warned_for_pass_big_vectors)
6034 warning (0, "GCC vector passed by reference: "
6035 "non-standard ABI extension with no compatibility guarantee");
6036 warned_for_pass_big_vectors = true;
6045 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6048 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6053 for (i = 0; i < nregs; i++)
6055 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6056 if (reload_completed)
6058 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6061 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6062 i * GET_MODE_SIZE (reg_mode));
6065 tem = replace_equiv_address (tem, XEXP (tem, 0));
6069 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6073 /* Perform any needed actions needed for a function that is receiving a
6074 variable number of arguments.
6078 MODE and TYPE are the mode and type of the current parameter.
6080 PRETEND_SIZE is a variable that should be set to the amount of stack
6081 that must be pushed by the prolog to pretend that our caller pushed
6084 Normally, this macro will push all remaining incoming registers on the
6085 stack and set PRETEND_SIZE to the length of the registers pushed. */
6088 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6089 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6092 CUMULATIVE_ARGS next_cum;
6093 int reg_size = TARGET_32BIT ? 4 : 8;
6094 rtx save_area = NULL_RTX, mem;
6095 int first_reg_offset, set;
6097 /* Skip the last named argument. */
6099 function_arg_advance (&next_cum, mode, type, 1, 0);
6101 if (DEFAULT_ABI == ABI_V4)
6103 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6107 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6108 HOST_WIDE_INT offset = 0;
6110 /* Try to optimize the size of the varargs save area.
6111 The ABI requires that ap.reg_save_area is doubleword
6112 aligned, but we don't need to allocate space for all
6113 the bytes, only those to which we actually will save
6115 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6116 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6117 if (TARGET_HARD_FLOAT && TARGET_FPRS
6118 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6119 && cfun->va_list_fpr_size)
6122 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6123 * UNITS_PER_FP_WORD;
6124 if (cfun->va_list_fpr_size
6125 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6126 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6128 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6129 * UNITS_PER_FP_WORD;
6133 offset = -((first_reg_offset * reg_size) & ~7);
6134 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6136 gpr_reg_num = cfun->va_list_gpr_size;
6137 if (reg_size == 4 && (first_reg_offset & 1))
6140 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6143 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6145 - (int) (GP_ARG_NUM_REG * reg_size);
6147 if (gpr_size + fpr_size)
6150 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6151 gcc_assert (GET_CODE (reg_save_area) == MEM);
6152 reg_save_area = XEXP (reg_save_area, 0);
6153 if (GET_CODE (reg_save_area) == PLUS)
6155 gcc_assert (XEXP (reg_save_area, 0)
6156 == virtual_stack_vars_rtx);
6157 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6158 offset += INTVAL (XEXP (reg_save_area, 1));
6161 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6164 cfun->machine->varargs_save_offset = offset;
6165 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6170 first_reg_offset = next_cum.words;
6171 save_area = virtual_incoming_args_rtx;
6173 if (targetm.calls.must_pass_in_stack (mode, type))
6174 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6177 set = get_varargs_alias_set ();
6178 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6179 && cfun->va_list_gpr_size)
6181 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6183 if (va_list_gpr_counter_field)
6185 /* V4 va_list_gpr_size counts number of registers needed. */
6186 if (nregs > cfun->va_list_gpr_size)
6187 nregs = cfun->va_list_gpr_size;
6191 /* char * va_list instead counts number of bytes needed. */
6192 if (nregs > cfun->va_list_gpr_size / reg_size)
6193 nregs = cfun->va_list_gpr_size / reg_size;
6196 mem = gen_rtx_MEM (BLKmode,
6197 plus_constant (save_area,
6198 first_reg_offset * reg_size));
6199 MEM_NOTRAP_P (mem) = 1;
6200 set_mem_alias_set (mem, set);
6201 set_mem_align (mem, BITS_PER_WORD);
6203 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6207 /* Save FP registers if needed. */
6208 if (DEFAULT_ABI == ABI_V4
6209 && TARGET_HARD_FLOAT && TARGET_FPRS
6211 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6212 && cfun->va_list_fpr_size)
6214 int fregno = next_cum.fregno, nregs;
6215 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6216 rtx lab = gen_label_rtx ();
6217 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6218 * UNITS_PER_FP_WORD);
6221 (gen_rtx_SET (VOIDmode,
6223 gen_rtx_IF_THEN_ELSE (VOIDmode,
6224 gen_rtx_NE (VOIDmode, cr1,
6226 gen_rtx_LABEL_REF (VOIDmode, lab),
6230 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6231 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6233 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6234 MEM_NOTRAP_P (mem) = 1;
6235 set_mem_alias_set (mem, set);
6236 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6237 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6244 /* Create the va_list data type. */
6247 rs6000_build_builtin_va_list (void)
6249 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6251 /* For AIX, prefer 'char *' because that's what the system
6252 header files like. */
6253 if (DEFAULT_ABI != ABI_V4)
6254 return build_pointer_type (char_type_node);
6256 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6257 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6259 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6260 unsigned_char_type_node);
6261 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6262 unsigned_char_type_node);
6263 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6265 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6266 short_unsigned_type_node);
6267 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6269 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6272 va_list_gpr_counter_field = f_gpr;
6273 va_list_fpr_counter_field = f_fpr;
6275 DECL_FIELD_CONTEXT (f_gpr) = record;
6276 DECL_FIELD_CONTEXT (f_fpr) = record;
6277 DECL_FIELD_CONTEXT (f_res) = record;
6278 DECL_FIELD_CONTEXT (f_ovf) = record;
6279 DECL_FIELD_CONTEXT (f_sav) = record;
6281 TREE_CHAIN (record) = type_decl;
6282 TYPE_NAME (record) = type_decl;
6283 TYPE_FIELDS (record) = f_gpr;
6284 TREE_CHAIN (f_gpr) = f_fpr;
6285 TREE_CHAIN (f_fpr) = f_res;
6286 TREE_CHAIN (f_res) = f_ovf;
6287 TREE_CHAIN (f_ovf) = f_sav;
6289 layout_type (record);
6291 /* The correct type is an array type of one element. */
6292 return build_array_type (record, build_index_type (size_zero_node));
6295 /* Implement va_start. */
6298 rs6000_va_start (tree valist, rtx nextarg)
6300 HOST_WIDE_INT words, n_gpr, n_fpr;
6301 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6302 tree gpr, fpr, ovf, sav, t;
6304 /* Only SVR4 needs something special. */
6305 if (DEFAULT_ABI != ABI_V4)
6307 std_expand_builtin_va_start (valist, nextarg);
6311 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6312 f_fpr = TREE_CHAIN (f_gpr);
6313 f_res = TREE_CHAIN (f_fpr);
6314 f_ovf = TREE_CHAIN (f_res);
6315 f_sav = TREE_CHAIN (f_ovf);
6317 valist = build_va_arg_indirect_ref (valist);
6318 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6319 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6320 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6321 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6323 /* Count number of gp and fp argument registers used. */
6324 words = current_function_args_info.words;
6325 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6327 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6330 if (TARGET_DEBUG_ARG)
6331 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6332 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6333 words, n_gpr, n_fpr);
6335 if (cfun->va_list_gpr_size)
6337 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6338 build_int_cst (NULL_TREE, n_gpr));
6339 TREE_SIDE_EFFECTS (t) = 1;
6340 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6343 if (cfun->va_list_fpr_size)
6345 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6346 build_int_cst (NULL_TREE, n_fpr));
6347 TREE_SIDE_EFFECTS (t) = 1;
6348 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6351 /* Find the overflow area. */
6352 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6354 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6355 size_int (words * UNITS_PER_WORD));
6356 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6357 TREE_SIDE_EFFECTS (t) = 1;
6358 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6360 /* If there were no va_arg invocations, don't set up the register
6362 if (!cfun->va_list_gpr_size
6363 && !cfun->va_list_fpr_size
6364 && n_gpr < GP_ARG_NUM_REG
6365 && n_fpr < FP_ARG_V4_MAX_REG)
6368 /* Find the register save area. */
6369 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6370 if (cfun->machine->varargs_save_offset)
6371 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6372 size_int (cfun->machine->varargs_save_offset));
6373 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6374 TREE_SIDE_EFFECTS (t) = 1;
6375 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6378 /* Implement va_arg. */
6381 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6383 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6384 tree gpr, fpr, ovf, sav, reg, t, u;
6385 int size, rsize, n_reg, sav_ofs, sav_scale;
6386 tree lab_false, lab_over, addr;
6388 tree ptrtype = build_pointer_type (type);
6391 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6393 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6394 return build_va_arg_indirect_ref (t);
6397 if (DEFAULT_ABI != ABI_V4)
6399 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6401 tree elem_type = TREE_TYPE (type);
6402 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6403 int elem_size = GET_MODE_SIZE (elem_mode);
6405 if (elem_size < UNITS_PER_WORD)
6407 tree real_part, imag_part;
6408 tree post = NULL_TREE;
6410 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6412 /* Copy the value into a temporary, lest the formal temporary
6413 be reused out from under us. */
6414 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6415 append_to_statement_list (post, pre_p);
6417 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6420 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6424 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6427 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6428 f_fpr = TREE_CHAIN (f_gpr);
6429 f_res = TREE_CHAIN (f_fpr);
6430 f_ovf = TREE_CHAIN (f_res);
6431 f_sav = TREE_CHAIN (f_ovf);
6433 valist = build_va_arg_indirect_ref (valist);
6434 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6435 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6436 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6437 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6439 size = int_size_in_bytes (type);
6440 rsize = (size + 3) / 4;
6443 if (TARGET_HARD_FLOAT && TARGET_FPRS
6444 && (TYPE_MODE (type) == SFmode
6445 || TYPE_MODE (type) == DFmode
6446 || TYPE_MODE (type) == TFmode
6447 || TYPE_MODE (type) == DDmode
6448 || TYPE_MODE (type) == TDmode))
6450 /* FP args go in FP registers, if present. */
6452 n_reg = (size + 7) / 8;
6455 if (TYPE_MODE (type) != SFmode)
6460 /* Otherwise into GP registers. */
6469 /* Pull the value out of the saved registers.... */
6472 addr = create_tmp_var (ptr_type_node, "addr");
6473 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6475 /* AltiVec vectors never go in registers when -mabi=altivec. */
6476 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6480 lab_false = create_artificial_label ();
6481 lab_over = create_artificial_label ();
6483 /* Long long and SPE vectors are aligned in the registers.
6484 As are any other 2 gpr item such as complex int due to a
6485 historical mistake. */
6487 if (n_reg == 2 && reg == gpr)
6490 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6491 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6492 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6494 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6495 reg number is 0 for f1, so we want to make it odd. */
6496 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6499 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6500 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6503 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6504 t = build2 (GE_EXPR, boolean_type_node, u, t);
6505 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6506 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6507 gimplify_and_add (t, pre_p);
6511 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6513 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
6514 build_int_cst (TREE_TYPE (reg), n_reg));
6515 u = fold_convert (sizetype, u);
6516 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6517 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6519 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6520 gimplify_and_add (t, pre_p);
6522 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6523 gimplify_and_add (t, pre_p);
6525 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6526 append_to_statement_list (t, pre_p);
6528 if ((n_reg == 2 && !regalign) || n_reg > 2)
6530 /* Ensure that we don't find any more args in regs.
6531 Alignment has taken care of for special cases. */
6532 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6533 gimplify_and_add (t, pre_p);
6537 /* ... otherwise out of the overflow area. */
6539 /* Care for on-stack alignment if needed. */
6543 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6544 t = fold_convert (sizetype, t);
6545 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6547 t = fold_convert (TREE_TYPE (ovf), t);
6549 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6551 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6552 gimplify_and_add (u, pre_p);
6554 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6555 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6556 gimplify_and_add (t, pre_p);
6560 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6561 append_to_statement_list (t, pre_p);
6564 if (STRICT_ALIGNMENT
6565 && (TYPE_ALIGN (type)
6566 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6568 /* The value (of type complex double, for example) may not be
6569 aligned in memory in the saved registers, so copy via a
6570 temporary. (This is the same code as used for SPARC.) */
6571 tree tmp = create_tmp_var (type, "va_arg_tmp");
6572 tree dest_addr = build_fold_addr_expr (tmp);
6574 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6575 3, dest_addr, addr, size_int (rsize * 4));
6577 gimplify_and_add (copy, pre_p);
6581 addr = fold_convert (ptrtype, addr);
6582 return build_va_arg_indirect_ref (addr);
6588 def_builtin (int mask, const char *name, tree type, int code)
6590 if (mask & target_flags)
6592 if (rs6000_builtin_decls[code])
6595 rs6000_builtin_decls[code] =
6596 add_builtin_function (name, type, code, BUILT_IN_MD,
6601 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6603 static const struct builtin_description bdesc_3arg[] =
6605 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6606 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6607 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6608 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6609 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6610 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6611 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6613 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6614 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6615 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6616 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6617 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6618 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6619 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6620 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6621 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6622 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6624 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6625 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6626 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6627 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6629 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6630 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6631 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6632 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6633 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6634 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6635 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6636 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6637 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6638 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6639 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6640 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6641 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6642 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6643 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6646 /* DST operations: void foo (void *, const int, const char). */
6648 static const struct builtin_description bdesc_dst[] =
6650 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6651 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6652 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6653 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6661 /* Simple binary operations: VECc = foo (VECa, VECb). */
6663 static struct builtin_description bdesc_2arg[] =
6665 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6666 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6667 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6668 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6669 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6670 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6671 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6672 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6673 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6674 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6675 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6676 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6677 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6678 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6679 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6680 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6681 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6682 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6683 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6684 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6685 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6686 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6687 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6688 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6689 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6690 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6691 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6692 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6693 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6694 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6695 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6696 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6697 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6698 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6699 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6700 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6701 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6702 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6703 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6704 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6705 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6706 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6707 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6708 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6709 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6710 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6711 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6712 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6713 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6714 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6715 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6716 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6717 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6718 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6719 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6720 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6721 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6722 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6723 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6724 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6725 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6726 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6727 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6728 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6729 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6730 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6731 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6732 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6733 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6734 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6735 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6736 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6737 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6738 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6739 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6740 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6741 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6742 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6743 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6744 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6745 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6746 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6747 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6748 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6749 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6750 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6751 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6752 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6753 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6754 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6755 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6756 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6757 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6758 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6759 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6760 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6761 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6762 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6763 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6764 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6765 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6766 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6767 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6768 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6769 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6770 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6771 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6772 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6773 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6774 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6775 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6777 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6778 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6779 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6780 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6781 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6782 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6783 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6784 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6785 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6786 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6787 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6788 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6789 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6790 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6791 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6792 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6793 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6794 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6856 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6857 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6858 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6859 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6860 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6861 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6862 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6863 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6864 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6865 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6866 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6884 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6885 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6886 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6887 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6888 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6889 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6890 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6891 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6892 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6893 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6894 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6899 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6900 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6901 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6902 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6903 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6905 /* Place holder, leave as first spe builtin. */
6906 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6907 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6908 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6909 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6910 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6911 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6912 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6913 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6914 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6915 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6916 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6917 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6918 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6919 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6920 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6921 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6922 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6923 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6924 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6925 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6926 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6927 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6928 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6929 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6930 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6931 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6932 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6933 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6934 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6935 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6936 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6937 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6938 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6939 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6940 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6941 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6942 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6943 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6944 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6945 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6946 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6947 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6948 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6949 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6950 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6951 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6952 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6953 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6954 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6955 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6956 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6957 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6958 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6959 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6960 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6961 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6962 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6963 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6964 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6965 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6966 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6967 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6968 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6969 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6970 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6971 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6972 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6973 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6974 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6975 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6976 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6977 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6978 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6979 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6980 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6981 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6982 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6983 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6984 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6985 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6986 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6987 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6988 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6989 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6990 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6991 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6992 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6993 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6994 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6995 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6996 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6997 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6998 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6999 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7000 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7001 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7002 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7003 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7004 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7005 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7006 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7007 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7008 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7009 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7010 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7011 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7012 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7013 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7014 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7016 /* SPE binary operations expecting a 5-bit unsigned literal. */
7017 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7019 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7020 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7021 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7022 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7023 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7024 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7025 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7026 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7027 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7028 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7029 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7030 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7031 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7032 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7033 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7034 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7035 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7036 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7037 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7038 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7039 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7040 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7041 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7042 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7043 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7044 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7046 /* Place-holder. Leave as last binary SPE builtin. */
7047 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7050 /* AltiVec predicates. */
7052 struct builtin_description_predicates
7054 const unsigned int mask;
7055 const enum insn_code icode;
7057 const char *const name;
7058 const enum rs6000_builtins code;
7061 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7063 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7064 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7065 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7066 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7067 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7068 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7069 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7070 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7071 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7072 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7073 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7074 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7075 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7077 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7078 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7079 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7082 /* SPE predicates. */
7083 static struct builtin_description bdesc_spe_predicates[] =
7085 /* Place-holder. Leave as first. */
7086 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7087 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7088 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7089 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7090 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7091 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7092 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7093 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7094 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7095 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7096 /* Place-holder. Leave as last. */
7097 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7100 /* SPE evsel predicates. */
7101 static struct builtin_description bdesc_spe_evsel[] =
7103 /* Place-holder. Leave as first. */
7104 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7105 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7106 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7107 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7108 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7109 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7110 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7111 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7112 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7113 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7114 /* Place-holder. Leave as last. */
7115 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7118 /* ABS* operations. */
7120 static const struct builtin_description bdesc_abs[] =
7122 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7123 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7124 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7125 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7126 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7127 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7128 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7131 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7134 static struct builtin_description bdesc_1arg[] =
7136 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7137 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7138 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7139 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7140 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7141 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7142 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7143 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7144 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7145 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7146 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7147 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7148 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7149 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7150 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7151 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7152 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7174 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7175 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7176 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7177 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7178 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7179 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7180 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7181 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7182 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7183 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7184 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7185 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7186 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7187 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7188 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7189 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7190 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7191 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7192 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7193 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7194 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7195 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7196 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7197 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7198 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7199 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7200 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7201 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7202 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7203 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7205 /* Place-holder. Leave as last unary SPE builtin. */
7206 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7210 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7213 tree arg0 = CALL_EXPR_ARG (exp, 0);
7214 rtx op0 = expand_normal (arg0);
7215 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7216 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7218 if (icode == CODE_FOR_nothing)
7219 /* Builtin not supported on this processor. */
7222 /* If we got invalid arguments bail out before generating bad rtl. */
7223 if (arg0 == error_mark_node)
7226 if (icode == CODE_FOR_altivec_vspltisb
7227 || icode == CODE_FOR_altivec_vspltish
7228 || icode == CODE_FOR_altivec_vspltisw
7229 || icode == CODE_FOR_spe_evsplatfi
7230 || icode == CODE_FOR_spe_evsplati)
7232 /* Only allow 5-bit *signed* literals. */
7233 if (GET_CODE (op0) != CONST_INT
7234 || INTVAL (op0) > 15
7235 || INTVAL (op0) < -16)
7237 error ("argument 1 must be a 5-bit signed literal");
7243 || GET_MODE (target) != tmode
7244 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7245 target = gen_reg_rtx (tmode);
7247 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7248 op0 = copy_to_mode_reg (mode0, op0);
7250 pat = GEN_FCN (icode) (target, op0);
7259 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7261 rtx pat, scratch1, scratch2;
7262 tree arg0 = CALL_EXPR_ARG (exp, 0);
7263 rtx op0 = expand_normal (arg0);
7264 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7265 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7267 /* If we have invalid arguments, bail out before generating bad rtl. */
7268 if (arg0 == error_mark_node)
7272 || GET_MODE (target) != tmode
7273 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7274 target = gen_reg_rtx (tmode);
7276 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7277 op0 = copy_to_mode_reg (mode0, op0);
7279 scratch1 = gen_reg_rtx (mode0);
7280 scratch2 = gen_reg_rtx (mode0);
7282 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7291 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7294 tree arg0 = CALL_EXPR_ARG (exp, 0);
7295 tree arg1 = CALL_EXPR_ARG (exp, 1);
7296 rtx op0 = expand_normal (arg0);
7297 rtx op1 = expand_normal (arg1);
7298 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7299 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7300 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7302 if (icode == CODE_FOR_nothing)
7303 /* Builtin not supported on this processor. */
7306 /* If we got invalid arguments bail out before generating bad rtl. */
7307 if (arg0 == error_mark_node || arg1 == error_mark_node)
7310 if (icode == CODE_FOR_altivec_vcfux
7311 || icode == CODE_FOR_altivec_vcfsx
7312 || icode == CODE_FOR_altivec_vctsxs
7313 || icode == CODE_FOR_altivec_vctuxs
7314 || icode == CODE_FOR_altivec_vspltb
7315 || icode == CODE_FOR_altivec_vsplth
7316 || icode == CODE_FOR_altivec_vspltw
7317 || icode == CODE_FOR_spe_evaddiw
7318 || icode == CODE_FOR_spe_evldd
7319 || icode == CODE_FOR_spe_evldh
7320 || icode == CODE_FOR_spe_evldw
7321 || icode == CODE_FOR_spe_evlhhesplat
7322 || icode == CODE_FOR_spe_evlhhossplat
7323 || icode == CODE_FOR_spe_evlhhousplat
7324 || icode == CODE_FOR_spe_evlwhe
7325 || icode == CODE_FOR_spe_evlwhos
7326 || icode == CODE_FOR_spe_evlwhou
7327 || icode == CODE_FOR_spe_evlwhsplat
7328 || icode == CODE_FOR_spe_evlwwsplat
7329 || icode == CODE_FOR_spe_evrlwi
7330 || icode == CODE_FOR_spe_evslwi
7331 || icode == CODE_FOR_spe_evsrwis
7332 || icode == CODE_FOR_spe_evsubifw
7333 || icode == CODE_FOR_spe_evsrwiu)
7335 /* Only allow 5-bit unsigned literals. */
7337 if (TREE_CODE (arg1) != INTEGER_CST
7338 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7340 error ("argument 2 must be a 5-bit unsigned literal");
7346 || GET_MODE (target) != tmode
7347 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7348 target = gen_reg_rtx (tmode);
7350 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7351 op0 = copy_to_mode_reg (mode0, op0);
7352 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7353 op1 = copy_to_mode_reg (mode1, op1);
7355 pat = GEN_FCN (icode) (target, op0, op1);
7364 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7365 tree exp, rtx target)
7368 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7369 tree arg0 = CALL_EXPR_ARG (exp, 1);
7370 tree arg1 = CALL_EXPR_ARG (exp, 2);
7371 rtx op0 = expand_normal (arg0);
7372 rtx op1 = expand_normal (arg1);
7373 enum machine_mode tmode = SImode;
7374 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7375 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7378 if (TREE_CODE (cr6_form) != INTEGER_CST)
7380 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7384 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7386 gcc_assert (mode0 == mode1);
7388 /* If we have invalid arguments, bail out before generating bad rtl. */
7389 if (arg0 == error_mark_node || arg1 == error_mark_node)
7393 || GET_MODE (target) != tmode
7394 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7395 target = gen_reg_rtx (tmode);
7397 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7398 op0 = copy_to_mode_reg (mode0, op0);
7399 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7400 op1 = copy_to_mode_reg (mode1, op1);
7402 scratch = gen_reg_rtx (mode0);
7404 pat = GEN_FCN (icode) (scratch, op0, op1,
7405 gen_rtx_SYMBOL_REF (Pmode, opcode));
7410 /* The vec_any* and vec_all* predicates use the same opcodes for two
7411 different operations, but the bits in CR6 will be different
7412 depending on what information we want. So we have to play tricks
7413 with CR6 to get the right bits out.
7415 If you think this is disgusting, look at the specs for the
7416 AltiVec predicates. */
7418 switch (cr6_form_int)
7421 emit_insn (gen_cr6_test_for_zero (target));
7424 emit_insn (gen_cr6_test_for_zero_reverse (target));
7427 emit_insn (gen_cr6_test_for_lt (target));
7430 emit_insn (gen_cr6_test_for_lt_reverse (target));
7433 error ("argument 1 of __builtin_altivec_predicate is out of range");
7441 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7444 tree arg0 = CALL_EXPR_ARG (exp, 0);
7445 tree arg1 = CALL_EXPR_ARG (exp, 1);
7446 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7447 enum machine_mode mode0 = Pmode;
7448 enum machine_mode mode1 = Pmode;
7449 rtx op0 = expand_normal (arg0);
7450 rtx op1 = expand_normal (arg1);
7452 if (icode == CODE_FOR_nothing)
7453 /* Builtin not supported on this processor. */
7456 /* If we got invalid arguments bail out before generating bad rtl. */
7457 if (arg0 == error_mark_node || arg1 == error_mark_node)
7461 || GET_MODE (target) != tmode
7462 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7463 target = gen_reg_rtx (tmode);
7465 op1 = copy_to_mode_reg (mode1, op1);
7467 if (op0 == const0_rtx)
7469 addr = gen_rtx_MEM (tmode, op1);
7473 op0 = copy_to_mode_reg (mode0, op0);
7474 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7477 pat = GEN_FCN (icode) (target, addr);
7487 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7489 tree arg0 = CALL_EXPR_ARG (exp, 0);
7490 tree arg1 = CALL_EXPR_ARG (exp, 1);
7491 tree arg2 = CALL_EXPR_ARG (exp, 2);
7492 rtx op0 = expand_normal (arg0);
7493 rtx op1 = expand_normal (arg1);
7494 rtx op2 = expand_normal (arg2);
7496 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7497 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7498 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7500 /* Invalid arguments. Bail before doing anything stoopid! */
7501 if (arg0 == error_mark_node
7502 || arg1 == error_mark_node
7503 || arg2 == error_mark_node)
7506 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7507 op0 = copy_to_mode_reg (mode2, op0);
7508 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7509 op1 = copy_to_mode_reg (mode0, op1);
7510 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7511 op2 = copy_to_mode_reg (mode1, op2);
7513 pat = GEN_FCN (icode) (op1, op2, op0);
7520 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7522 tree arg0 = CALL_EXPR_ARG (exp, 0);
7523 tree arg1 = CALL_EXPR_ARG (exp, 1);
7524 tree arg2 = CALL_EXPR_ARG (exp, 2);
7525 rtx op0 = expand_normal (arg0);
7526 rtx op1 = expand_normal (arg1);
7527 rtx op2 = expand_normal (arg2);
7529 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7530 enum machine_mode mode1 = Pmode;
7531 enum machine_mode mode2 = Pmode;
7533 /* Invalid arguments. Bail before doing anything stoopid! */
7534 if (arg0 == error_mark_node
7535 || arg1 == error_mark_node
7536 || arg2 == error_mark_node)
7539 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7540 op0 = copy_to_mode_reg (tmode, op0);
7542 op2 = copy_to_mode_reg (mode2, op2);
7544 if (op1 == const0_rtx)
7546 addr = gen_rtx_MEM (tmode, op2);
7550 op1 = copy_to_mode_reg (mode1, op1);
7551 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7554 pat = GEN_FCN (icode) (addr, op0);
7561 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7564 tree arg0 = CALL_EXPR_ARG (exp, 0);
7565 tree arg1 = CALL_EXPR_ARG (exp, 1);
7566 tree arg2 = CALL_EXPR_ARG (exp, 2);
7567 rtx op0 = expand_normal (arg0);
7568 rtx op1 = expand_normal (arg1);
7569 rtx op2 = expand_normal (arg2);
7570 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7571 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7572 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7573 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7575 if (icode == CODE_FOR_nothing)
7576 /* Builtin not supported on this processor. */
7579 /* If we got invalid arguments bail out before generating bad rtl. */
7580 if (arg0 == error_mark_node
7581 || arg1 == error_mark_node
7582 || arg2 == error_mark_node)
7585 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7586 || icode == CODE_FOR_altivec_vsldoi_v4si
7587 || icode == CODE_FOR_altivec_vsldoi_v8hi
7588 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7590 /* Only allow 4-bit unsigned literals. */
7592 if (TREE_CODE (arg2) != INTEGER_CST
7593 || TREE_INT_CST_LOW (arg2) & ~0xf)
7595 error ("argument 3 must be a 4-bit unsigned literal");
7601 || GET_MODE (target) != tmode
7602 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7603 target = gen_reg_rtx (tmode);
7605 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7606 op0 = copy_to_mode_reg (mode0, op0);
7607 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7608 op1 = copy_to_mode_reg (mode1, op1);
7609 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7610 op2 = copy_to_mode_reg (mode2, op2);
7612 pat = GEN_FCN (icode) (target, op0, op1, op2);
7620 /* Expand the lvx builtins. */
7622 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7624 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7625 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7627 enum machine_mode tmode, mode0;
7629 enum insn_code icode;
7633 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7634 icode = CODE_FOR_altivec_lvx_v16qi;
7636 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7637 icode = CODE_FOR_altivec_lvx_v8hi;
7639 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7640 icode = CODE_FOR_altivec_lvx_v4si;
7642 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7643 icode = CODE_FOR_altivec_lvx_v4sf;
7652 arg0 = CALL_EXPR_ARG (exp, 0);
7653 op0 = expand_normal (arg0);
7654 tmode = insn_data[icode].operand[0].mode;
7655 mode0 = insn_data[icode].operand[1].mode;
7658 || GET_MODE (target) != tmode
7659 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7660 target = gen_reg_rtx (tmode);
7662 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7663 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7665 pat = GEN_FCN (icode) (target, op0);
7672 /* Expand the stvx builtins. */
7674 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7677 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7678 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7680 enum machine_mode mode0, mode1;
7682 enum insn_code icode;
7686 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7687 icode = CODE_FOR_altivec_stvx_v16qi;
7689 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7690 icode = CODE_FOR_altivec_stvx_v8hi;
7692 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7693 icode = CODE_FOR_altivec_stvx_v4si;
7695 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7696 icode = CODE_FOR_altivec_stvx_v4sf;
7703 arg0 = CALL_EXPR_ARG (exp, 0);
7704 arg1 = CALL_EXPR_ARG (exp, 1);
7705 op0 = expand_normal (arg0);
7706 op1 = expand_normal (arg1);
7707 mode0 = insn_data[icode].operand[0].mode;
7708 mode1 = insn_data[icode].operand[1].mode;
7710 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7711 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7712 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7713 op1 = copy_to_mode_reg (mode1, op1);
7715 pat = GEN_FCN (icode) (op0, op1);
7723 /* Expand the dst builtins. */
7725 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7728 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7729 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7730 tree arg0, arg1, arg2;
7731 enum machine_mode mode0, mode1, mode2;
7732 rtx pat, op0, op1, op2;
7733 struct builtin_description *d;
7738 /* Handle DST variants. */
7739 d = (struct builtin_description *) bdesc_dst;
7740 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7741 if (d->code == fcode)
7743 arg0 = CALL_EXPR_ARG (exp, 0);
7744 arg1 = CALL_EXPR_ARG (exp, 1);
7745 arg2 = CALL_EXPR_ARG (exp, 2);
7746 op0 = expand_normal (arg0);
7747 op1 = expand_normal (arg1);
7748 op2 = expand_normal (arg2);
7749 mode0 = insn_data[d->icode].operand[0].mode;
7750 mode1 = insn_data[d->icode].operand[1].mode;
7751 mode2 = insn_data[d->icode].operand[2].mode;
7753 /* Invalid arguments, bail out before generating bad rtl. */
7754 if (arg0 == error_mark_node
7755 || arg1 == error_mark_node
7756 || arg2 == error_mark_node)
7761 if (TREE_CODE (arg2) != INTEGER_CST
7762 || TREE_INT_CST_LOW (arg2) & ~0x3)
7764 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7768 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7769 op0 = copy_to_mode_reg (Pmode, op0);
7770 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7771 op1 = copy_to_mode_reg (mode1, op1);
7773 pat = GEN_FCN (d->icode) (op0, op1, op2);
7783 /* Expand vec_init builtin. */
7785 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7787 enum machine_mode tmode = TYPE_MODE (type);
7788 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7789 int i, n_elt = GET_MODE_NUNITS (tmode);
7790 rtvec v = rtvec_alloc (n_elt);
7792 gcc_assert (VECTOR_MODE_P (tmode));
7793 gcc_assert (n_elt == call_expr_nargs (exp));
7795 for (i = 0; i < n_elt; ++i)
7797 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7798 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7801 if (!target || !register_operand (target, tmode))
7802 target = gen_reg_rtx (tmode);
7804 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7808 /* Return the integer constant in ARG. Constrain it to be in the range
7809 of the subparts of VEC_TYPE; issue an error if not. */
7812 get_element_number (tree vec_type, tree arg)
7814 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7816 if (!host_integerp (arg, 1)
7817 || (elt = tree_low_cst (arg, 1), elt > max))
7819 error ("selector must be an integer constant in the range 0..%wi", max);
7826 /* Expand vec_set builtin. */
7828 altivec_expand_vec_set_builtin (tree exp)
7830 enum machine_mode tmode, mode1;
7831 tree arg0, arg1, arg2;
7835 arg0 = CALL_EXPR_ARG (exp, 0);
7836 arg1 = CALL_EXPR_ARG (exp, 1);
7837 arg2 = CALL_EXPR_ARG (exp, 2);
7839 tmode = TYPE_MODE (TREE_TYPE (arg0));
7840 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7841 gcc_assert (VECTOR_MODE_P (tmode));
7843 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7844 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7845 elt = get_element_number (TREE_TYPE (arg0), arg2);
7847 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7848 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7850 op0 = force_reg (tmode, op0);
7851 op1 = force_reg (mode1, op1);
7853 rs6000_expand_vector_set (op0, op1, elt);
7858 /* Expand vec_ext builtin. */
7860 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7862 enum machine_mode tmode, mode0;
7867 arg0 = CALL_EXPR_ARG (exp, 0);
7868 arg1 = CALL_EXPR_ARG (exp, 1);
7870 op0 = expand_normal (arg0);
7871 elt = get_element_number (TREE_TYPE (arg0), arg1);
7873 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7874 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7875 gcc_assert (VECTOR_MODE_P (mode0));
7877 op0 = force_reg (mode0, op0);
7879 if (optimize || !target || !register_operand (target, tmode))
7880 target = gen_reg_rtx (tmode);
7882 rs6000_expand_vector_extract (target, op0, elt);
7887 /* Expand the builtin in EXP and store the result in TARGET. Store
7888 true in *EXPANDEDP if we found a builtin to expand. */
7890 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7892 struct builtin_description *d;
7893 struct builtin_description_predicates *dp;
7895 enum insn_code icode;
7896 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7899 enum machine_mode tmode, mode0;
7900 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7902 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7903 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7906 error ("unresolved overload for Altivec builtin %qF", fndecl);
7910 target = altivec_expand_ld_builtin (exp, target, expandedp);
7914 target = altivec_expand_st_builtin (exp, target, expandedp);
7918 target = altivec_expand_dst_builtin (exp, target, expandedp);
7926 case ALTIVEC_BUILTIN_STVX:
7927 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7928 case ALTIVEC_BUILTIN_STVEBX:
7929 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7930 case ALTIVEC_BUILTIN_STVEHX:
7931 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7932 case ALTIVEC_BUILTIN_STVEWX:
7933 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7934 case ALTIVEC_BUILTIN_STVXL:
7935 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7937 case ALTIVEC_BUILTIN_MFVSCR:
7938 icode = CODE_FOR_altivec_mfvscr;
7939 tmode = insn_data[icode].operand[0].mode;
7942 || GET_MODE (target) != tmode
7943 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7944 target = gen_reg_rtx (tmode);
7946 pat = GEN_FCN (icode) (target);
7952 case ALTIVEC_BUILTIN_MTVSCR:
7953 icode = CODE_FOR_altivec_mtvscr;
7954 arg0 = CALL_EXPR_ARG (exp, 0);
7955 op0 = expand_normal (arg0);
7956 mode0 = insn_data[icode].operand[0].mode;
7958 /* If we got invalid arguments bail out before generating bad rtl. */
7959 if (arg0 == error_mark_node)
7962 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7963 op0 = copy_to_mode_reg (mode0, op0);
7965 pat = GEN_FCN (icode) (op0);
7970 case ALTIVEC_BUILTIN_DSSALL:
7971 emit_insn (gen_altivec_dssall ());
7974 case ALTIVEC_BUILTIN_DSS:
7975 icode = CODE_FOR_altivec_dss;
7976 arg0 = CALL_EXPR_ARG (exp, 0);
7978 op0 = expand_normal (arg0);
7979 mode0 = insn_data[icode].operand[0].mode;
7981 /* If we got invalid arguments bail out before generating bad rtl. */
7982 if (arg0 == error_mark_node)
7985 if (TREE_CODE (arg0) != INTEGER_CST
7986 || TREE_INT_CST_LOW (arg0) & ~0x3)
7988 error ("argument to dss must be a 2-bit unsigned literal");
7992 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7993 op0 = copy_to_mode_reg (mode0, op0);
7995 emit_insn (gen_altivec_dss (op0));
7998 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7999 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8000 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8001 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8002 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8004 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8005 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8006 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8007 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8008 return altivec_expand_vec_set_builtin (exp);
8010 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8011 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8012 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8013 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8014 return altivec_expand_vec_ext_builtin (exp, target);
8021 /* Expand abs* operations. */
8022 d = (struct builtin_description *) bdesc_abs;
8023 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8024 if (d->code == fcode)
8025 return altivec_expand_abs_builtin (d->icode, exp, target);
8027 /* Expand the AltiVec predicates. */
8028 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8029 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8030 if (dp->code == fcode)
8031 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8034 /* LV* are funky. We initialized them differently. */
8037 case ALTIVEC_BUILTIN_LVSL:
8038 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8040 case ALTIVEC_BUILTIN_LVSR:
8041 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8043 case ALTIVEC_BUILTIN_LVEBX:
8044 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8046 case ALTIVEC_BUILTIN_LVEHX:
8047 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8049 case ALTIVEC_BUILTIN_LVEWX:
8050 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8052 case ALTIVEC_BUILTIN_LVXL:
8053 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8055 case ALTIVEC_BUILTIN_LVX:
8056 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8067 /* Binops that need to be initialized manually, but can be expanded
8068 automagically by rs6000_expand_binop_builtin. */
8069 static struct builtin_description bdesc_2arg_spe[] =
8071 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8072 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8073 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8074 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8075 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8076 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8077 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8078 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8079 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8080 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8081 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8082 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8083 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8084 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8085 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8086 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8087 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8088 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8089 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8090 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8091 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8092 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8095 /* Expand the builtin in EXP and store the result in TARGET. Store
8096 true in *EXPANDEDP if we found a builtin to expand.
8098 This expands the SPE builtins that are not simple unary and binary
8101 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8103 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8105 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8106 enum insn_code icode;
8107 enum machine_mode tmode, mode0;
8109 struct builtin_description *d;
8114 /* Syntax check for a 5-bit unsigned immediate. */
8117 case SPE_BUILTIN_EVSTDD:
8118 case SPE_BUILTIN_EVSTDH:
8119 case SPE_BUILTIN_EVSTDW:
8120 case SPE_BUILTIN_EVSTWHE:
8121 case SPE_BUILTIN_EVSTWHO:
8122 case SPE_BUILTIN_EVSTWWE:
8123 case SPE_BUILTIN_EVSTWWO:
8124 arg1 = CALL_EXPR_ARG (exp, 2);
8125 if (TREE_CODE (arg1) != INTEGER_CST
8126 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8128 error ("argument 2 must be a 5-bit unsigned literal");
8136 /* The evsplat*i instructions are not quite generic. */
8139 case SPE_BUILTIN_EVSPLATFI:
8140 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8142 case SPE_BUILTIN_EVSPLATI:
8143 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8149 d = (struct builtin_description *) bdesc_2arg_spe;
8150 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8151 if (d->code == fcode)
8152 return rs6000_expand_binop_builtin (d->icode, exp, target);
8154 d = (struct builtin_description *) bdesc_spe_predicates;
8155 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8156 if (d->code == fcode)
8157 return spe_expand_predicate_builtin (d->icode, exp, target);
8159 d = (struct builtin_description *) bdesc_spe_evsel;
8160 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8161 if (d->code == fcode)
8162 return spe_expand_evsel_builtin (d->icode, exp, target);
8166 case SPE_BUILTIN_EVSTDDX:
8167 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8168 case SPE_BUILTIN_EVSTDHX:
8169 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8170 case SPE_BUILTIN_EVSTDWX:
8171 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8172 case SPE_BUILTIN_EVSTWHEX:
8173 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8174 case SPE_BUILTIN_EVSTWHOX:
8175 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8176 case SPE_BUILTIN_EVSTWWEX:
8177 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8178 case SPE_BUILTIN_EVSTWWOX:
8179 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8180 case SPE_BUILTIN_EVSTDD:
8181 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8182 case SPE_BUILTIN_EVSTDH:
8183 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8184 case SPE_BUILTIN_EVSTDW:
8185 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8186 case SPE_BUILTIN_EVSTWHE:
8187 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8188 case SPE_BUILTIN_EVSTWHO:
8189 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8190 case SPE_BUILTIN_EVSTWWE:
8191 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8192 case SPE_BUILTIN_EVSTWWO:
8193 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8194 case SPE_BUILTIN_MFSPEFSCR:
8195 icode = CODE_FOR_spe_mfspefscr;
8196 tmode = insn_data[icode].operand[0].mode;
8199 || GET_MODE (target) != tmode
8200 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8201 target = gen_reg_rtx (tmode);
8203 pat = GEN_FCN (icode) (target);
8208 case SPE_BUILTIN_MTSPEFSCR:
8209 icode = CODE_FOR_spe_mtspefscr;
8210 arg0 = CALL_EXPR_ARG (exp, 0);
8211 op0 = expand_normal (arg0);
8212 mode0 = insn_data[icode].operand[0].mode;
8214 if (arg0 == error_mark_node)
8217 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8218 op0 = copy_to_mode_reg (mode0, op0);
8220 pat = GEN_FCN (icode) (op0);
8233 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8235 rtx pat, scratch, tmp;
8236 tree form = CALL_EXPR_ARG (exp, 0);
8237 tree arg0 = CALL_EXPR_ARG (exp, 1);
8238 tree arg1 = CALL_EXPR_ARG (exp, 2);
8239 rtx op0 = expand_normal (arg0);
8240 rtx op1 = expand_normal (arg1);
8241 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8242 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8246 if (TREE_CODE (form) != INTEGER_CST)
8248 error ("argument 1 of __builtin_spe_predicate must be a constant");
8252 form_int = TREE_INT_CST_LOW (form);
8254 gcc_assert (mode0 == mode1);
8256 if (arg0 == error_mark_node || arg1 == error_mark_node)
8260 || GET_MODE (target) != SImode
8261 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8262 target = gen_reg_rtx (SImode);
8264 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8265 op0 = copy_to_mode_reg (mode0, op0);
8266 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8267 op1 = copy_to_mode_reg (mode1, op1);
8269 scratch = gen_reg_rtx (CCmode);
8271 pat = GEN_FCN (icode) (scratch, op0, op1);
8276 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8277 _lower_. We use one compare, but look in different bits of the
8278 CR for each variant.
8280 There are 2 elements in each SPE simd type (upper/lower). The CR
8281 bits are set as follows:
8283 BIT0 | BIT 1 | BIT 2 | BIT 3
8284 U | L | (U | L) | (U & L)
8286 So, for an "all" relationship, BIT 3 would be set.
8287 For an "any" relationship, BIT 2 would be set. Etc.
8289 Following traditional nomenclature, these bits map to:
8291 BIT0 | BIT 1 | BIT 2 | BIT 3
8294 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8299 /* All variant. OV bit. */
8301 /* We need to get to the OV bit, which is the ORDERED bit. We
8302 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8303 that's ugly and will make validate_condition_mode die.
8304 So let's just use another pattern. */
8305 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8307 /* Any variant. EQ bit. */
8311 /* Upper variant. LT bit. */
8315 /* Lower variant. GT bit. */
8320 error ("argument 1 of __builtin_spe_predicate is out of range");
8324 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8325 emit_move_insn (target, tmp);
8330 /* The evsel builtins look like this:
8332 e = __builtin_spe_evsel_OP (a, b, c, d);
8336 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8337 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8341 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8344 tree arg0 = CALL_EXPR_ARG (exp, 0);
8345 tree arg1 = CALL_EXPR_ARG (exp, 1);
8346 tree arg2 = CALL_EXPR_ARG (exp, 2);
8347 tree arg3 = CALL_EXPR_ARG (exp, 3);
8348 rtx op0 = expand_normal (arg0);
8349 rtx op1 = expand_normal (arg1);
8350 rtx op2 = expand_normal (arg2);
8351 rtx op3 = expand_normal (arg3);
8352 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8353 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8355 gcc_assert (mode0 == mode1);
8357 if (arg0 == error_mark_node || arg1 == error_mark_node
8358 || arg2 == error_mark_node || arg3 == error_mark_node)
8362 || GET_MODE (target) != mode0
8363 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8364 target = gen_reg_rtx (mode0);
8366 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8367 op0 = copy_to_mode_reg (mode0, op0);
8368 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8369 op1 = copy_to_mode_reg (mode0, op1);
8370 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8371 op2 = copy_to_mode_reg (mode0, op2);
8372 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8373 op3 = copy_to_mode_reg (mode0, op3);
8375 /* Generate the compare. */
8376 scratch = gen_reg_rtx (CCmode);
8377 pat = GEN_FCN (icode) (scratch, op0, op1);
8382 if (mode0 == V2SImode)
8383 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8385 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8390 /* Expand an expression EXP that calls a built-in function,
8391 with result going to TARGET if that's convenient
8392 (and in mode MODE if that's convenient).
8393 SUBTARGET may be used as the target for computing one of EXP's operands.
8394 IGNORE is nonzero if the value is to be ignored. */
8397 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8398 enum machine_mode mode ATTRIBUTE_UNUSED,
8399 int ignore ATTRIBUTE_UNUSED)
8401 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8402 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8403 struct builtin_description *d;
8408 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8409 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8411 int icode = (int) CODE_FOR_altivec_lvsr;
8412 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8413 enum machine_mode mode = insn_data[icode].operand[1].mode;
8417 gcc_assert (TARGET_ALTIVEC);
8419 arg = CALL_EXPR_ARG (exp, 0);
8420 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8421 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8422 addr = memory_address (mode, op);
8423 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8427 /* For the load case need to negate the address. */
8428 op = gen_reg_rtx (GET_MODE (addr));
8429 emit_insn (gen_rtx_SET (VOIDmode, op,
8430 gen_rtx_NEG (GET_MODE (addr), addr)));
8432 op = gen_rtx_MEM (mode, op);
8435 || GET_MODE (target) != tmode
8436 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8437 target = gen_reg_rtx (tmode);
8439 /*pat = gen_altivec_lvsr (target, op);*/
8440 pat = GEN_FCN (icode) (target, op);
8448 /* FIXME: There's got to be a nicer way to handle this case than
8449 constructing a new CALL_EXPR. */
8450 if (fcode == ALTIVEC_BUILTIN_VCFUX
8451 || fcode == ALTIVEC_BUILTIN_VCFSX)
8453 if (call_expr_nargs (exp) == 1)
8454 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8455 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8460 ret = altivec_expand_builtin (exp, target, &success);
8467 ret = spe_expand_builtin (exp, target, &success);
8473 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8475 /* Handle simple unary operations. */
8476 d = (struct builtin_description *) bdesc_1arg;
8477 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8478 if (d->code == fcode)
8479 return rs6000_expand_unop_builtin (d->icode, exp, target);
8481 /* Handle simple binary operations. */
8482 d = (struct builtin_description *) bdesc_2arg;
8483 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8484 if (d->code == fcode)
8485 return rs6000_expand_binop_builtin (d->icode, exp, target);
8487 /* Handle simple ternary operations. */
8488 d = (struct builtin_description *) bdesc_3arg;
8489 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8490 if (d->code == fcode)
8491 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8497 build_opaque_vector_type (tree node, int nunits)
8499 node = copy_node (node);
8500 TYPE_MAIN_VARIANT (node) = node;
8501 return build_vector_type (node, nunits);
8505 rs6000_init_builtins (void)
8507 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8508 V2SF_type_node = build_vector_type (float_type_node, 2);
8509 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8510 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8511 V4SF_type_node = build_vector_type (float_type_node, 4);
8512 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8513 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8515 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8516 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8517 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8519 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8520 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8521 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8522 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8524 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8525 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8526 'vector unsigned short'. */
8528 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8529 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8530 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8531 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8533 long_integer_type_internal_node = long_integer_type_node;
8534 long_unsigned_type_internal_node = long_unsigned_type_node;
8535 intQI_type_internal_node = intQI_type_node;
8536 uintQI_type_internal_node = unsigned_intQI_type_node;
8537 intHI_type_internal_node = intHI_type_node;
8538 uintHI_type_internal_node = unsigned_intHI_type_node;
8539 intSI_type_internal_node = intSI_type_node;
8540 uintSI_type_internal_node = unsigned_intSI_type_node;
8541 float_type_internal_node = float_type_node;
8542 void_type_internal_node = void_type_node;
8544 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8545 get_identifier ("__bool char"),
8546 bool_char_type_node));
8547 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8548 get_identifier ("__bool short"),
8549 bool_short_type_node));
8550 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8551 get_identifier ("__bool int"),
8552 bool_int_type_node));
8553 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8554 get_identifier ("__pixel"),
8557 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8558 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8559 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8560 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8562 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8563 get_identifier ("__vector unsigned char"),
8564 unsigned_V16QI_type_node));
8565 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8566 get_identifier ("__vector signed char"),
8568 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8569 get_identifier ("__vector __bool char"),
8570 bool_V16QI_type_node));
8572 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8573 get_identifier ("__vector unsigned short"),
8574 unsigned_V8HI_type_node));
8575 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8576 get_identifier ("__vector signed short"),
8578 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8579 get_identifier ("__vector __bool short"),
8580 bool_V8HI_type_node));
8582 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8583 get_identifier ("__vector unsigned int"),
8584 unsigned_V4SI_type_node));
8585 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8586 get_identifier ("__vector signed int"),
8588 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8589 get_identifier ("__vector __bool int"),
8590 bool_V4SI_type_node));
8592 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8593 get_identifier ("__vector float"),
8595 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8596 get_identifier ("__vector __pixel"),
8597 pixel_V8HI_type_node));
8600 spe_init_builtins ();
8602 altivec_init_builtins ();
8603 if (TARGET_ALTIVEC || TARGET_SPE)
8604 rs6000_common_init_builtins ();
8607 /* AIX libm provides clog as __clog. */
8608 if (built_in_decls [BUILT_IN_CLOG])
8609 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8613 /* Search through a set of builtins and enable the mask bits.
8614 DESC is an array of builtins.
8615 SIZE is the total number of builtins.
8616 START is the builtin enum at which to start.
8617 END is the builtin enum at which to end. */
8619 enable_mask_for_builtins (struct builtin_description *desc, int size,
8620 enum rs6000_builtins start,
8621 enum rs6000_builtins end)
8625 for (i = 0; i < size; ++i)
8626 if (desc[i].code == start)
8632 for (; i < size; ++i)
8634 /* Flip all the bits on. */
8635 desc[i].mask = target_flags;
8636 if (desc[i].code == end)
8642 spe_init_builtins (void)
8644 tree endlink = void_list_node;
8645 tree puint_type_node = build_pointer_type (unsigned_type_node);
8646 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8647 struct builtin_description *d;
8650 tree v2si_ftype_4_v2si
8651 = build_function_type
8652 (opaque_V2SI_type_node,
8653 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8654 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8655 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8656 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8659 tree v2sf_ftype_4_v2sf
8660 = build_function_type
8661 (opaque_V2SF_type_node,
8662 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8663 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8664 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8665 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8668 tree int_ftype_int_v2si_v2si
8669 = build_function_type
8671 tree_cons (NULL_TREE, integer_type_node,
8672 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8673 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8676 tree int_ftype_int_v2sf_v2sf
8677 = build_function_type
8679 tree_cons (NULL_TREE, integer_type_node,
8680 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8681 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8684 tree void_ftype_v2si_puint_int
8685 = build_function_type (void_type_node,
8686 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8687 tree_cons (NULL_TREE, puint_type_node,
8688 tree_cons (NULL_TREE,
8692 tree void_ftype_v2si_puint_char
8693 = build_function_type (void_type_node,
8694 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8695 tree_cons (NULL_TREE, puint_type_node,
8696 tree_cons (NULL_TREE,
8700 tree void_ftype_v2si_pv2si_int
8701 = build_function_type (void_type_node,
8702 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8703 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8704 tree_cons (NULL_TREE,
8708 tree void_ftype_v2si_pv2si_char
8709 = build_function_type (void_type_node,
8710 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8711 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8712 tree_cons (NULL_TREE,
8717 = build_function_type (void_type_node,
8718 tree_cons (NULL_TREE, integer_type_node, endlink));
8721 = build_function_type (integer_type_node, endlink);
8723 tree v2si_ftype_pv2si_int
8724 = build_function_type (opaque_V2SI_type_node,
8725 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8726 tree_cons (NULL_TREE, integer_type_node,
8729 tree v2si_ftype_puint_int
8730 = build_function_type (opaque_V2SI_type_node,
8731 tree_cons (NULL_TREE, puint_type_node,
8732 tree_cons (NULL_TREE, integer_type_node,
8735 tree v2si_ftype_pushort_int
8736 = build_function_type (opaque_V2SI_type_node,
8737 tree_cons (NULL_TREE, pushort_type_node,
8738 tree_cons (NULL_TREE, integer_type_node,
8741 tree v2si_ftype_signed_char
8742 = build_function_type (opaque_V2SI_type_node,
8743 tree_cons (NULL_TREE, signed_char_type_node,
8746 /* The initialization of the simple binary and unary builtins is
8747 done in rs6000_common_init_builtins, but we have to enable the
8748 mask bits here manually because we have run out of `target_flags'
8749 bits. We really need to redesign this mask business. */
8751 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8752 ARRAY_SIZE (bdesc_2arg),
8755 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8756 ARRAY_SIZE (bdesc_1arg),
8758 SPE_BUILTIN_EVSUBFUSIAAW);
8759 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8760 ARRAY_SIZE (bdesc_spe_predicates),
8761 SPE_BUILTIN_EVCMPEQ,
8762 SPE_BUILTIN_EVFSTSTLT);
8763 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8764 ARRAY_SIZE (bdesc_spe_evsel),
8765 SPE_BUILTIN_EVSEL_CMPGTS,
8766 SPE_BUILTIN_EVSEL_FSTSTEQ);
8768 (*lang_hooks.decls.pushdecl)
8769 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8770 opaque_V2SI_type_node));
8772 /* Initialize irregular SPE builtins. */
8774 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8775 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8776 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8777 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8778 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8779 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8780 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8781 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8782 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8783 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8784 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8785 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8786 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8787 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8788 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8789 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8790 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8791 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8794 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8795 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8796 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8797 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8798 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8799 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8800 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8801 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8802 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8803 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8804 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8805 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8806 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8807 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8808 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8809 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8810 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8811 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8812 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8813 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8814 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8815 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8818 d = (struct builtin_description *) bdesc_spe_predicates;
8819 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8823 switch (insn_data[d->icode].operand[1].mode)
8826 type = int_ftype_int_v2si_v2si;
8829 type = int_ftype_int_v2sf_v2sf;
8835 def_builtin (d->mask, d->name, type, d->code);
8838 /* Evsel predicates. */
8839 d = (struct builtin_description *) bdesc_spe_evsel;
8840 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8844 switch (insn_data[d->icode].operand[1].mode)
8847 type = v2si_ftype_4_v2si;
8850 type = v2sf_ftype_4_v2sf;
8856 def_builtin (d->mask, d->name, type, d->code);
8861 altivec_init_builtins (void)
8863 struct builtin_description *d;
8864 struct builtin_description_predicates *dp;
8868 tree pfloat_type_node = build_pointer_type (float_type_node);
8869 tree pint_type_node = build_pointer_type (integer_type_node);
8870 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8871 tree pchar_type_node = build_pointer_type (char_type_node);
8873 tree pvoid_type_node = build_pointer_type (void_type_node);
8875 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8876 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8877 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8878 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8880 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8882 tree int_ftype_opaque
8883 = build_function_type_list (integer_type_node,
8884 opaque_V4SI_type_node, NULL_TREE);
8886 tree opaque_ftype_opaque_int
8887 = build_function_type_list (opaque_V4SI_type_node,
8888 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8889 tree opaque_ftype_opaque_opaque_int
8890 = build_function_type_list (opaque_V4SI_type_node,
8891 opaque_V4SI_type_node, opaque_V4SI_type_node,
8892 integer_type_node, NULL_TREE);
8893 tree int_ftype_int_opaque_opaque
8894 = build_function_type_list (integer_type_node,
8895 integer_type_node, opaque_V4SI_type_node,
8896 opaque_V4SI_type_node, NULL_TREE);
8897 tree int_ftype_int_v4si_v4si
8898 = build_function_type_list (integer_type_node,
8899 integer_type_node, V4SI_type_node,
8900 V4SI_type_node, NULL_TREE);
8901 tree v4sf_ftype_pcfloat
8902 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8903 tree void_ftype_pfloat_v4sf
8904 = build_function_type_list (void_type_node,
8905 pfloat_type_node, V4SF_type_node, NULL_TREE);
8906 tree v4si_ftype_pcint
8907 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8908 tree void_ftype_pint_v4si
8909 = build_function_type_list (void_type_node,
8910 pint_type_node, V4SI_type_node, NULL_TREE);
8911 tree v8hi_ftype_pcshort
8912 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8913 tree void_ftype_pshort_v8hi
8914 = build_function_type_list (void_type_node,
8915 pshort_type_node, V8HI_type_node, NULL_TREE);
8916 tree v16qi_ftype_pcchar
8917 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8918 tree void_ftype_pchar_v16qi
8919 = build_function_type_list (void_type_node,
8920 pchar_type_node, V16QI_type_node, NULL_TREE);
8921 tree void_ftype_v4si
8922 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8923 tree v8hi_ftype_void
8924 = build_function_type (V8HI_type_node, void_list_node);
8925 tree void_ftype_void
8926 = build_function_type (void_type_node, void_list_node);
8928 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8930 tree opaque_ftype_long_pcvoid
8931 = build_function_type_list (opaque_V4SI_type_node,
8932 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8933 tree v16qi_ftype_long_pcvoid
8934 = build_function_type_list (V16QI_type_node,
8935 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8936 tree v8hi_ftype_long_pcvoid
8937 = build_function_type_list (V8HI_type_node,
8938 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8939 tree v4si_ftype_long_pcvoid
8940 = build_function_type_list (V4SI_type_node,
8941 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8943 tree void_ftype_opaque_long_pvoid
8944 = build_function_type_list (void_type_node,
8945 opaque_V4SI_type_node, long_integer_type_node,
8946 pvoid_type_node, NULL_TREE);
8947 tree void_ftype_v4si_long_pvoid
8948 = build_function_type_list (void_type_node,
8949 V4SI_type_node, long_integer_type_node,
8950 pvoid_type_node, NULL_TREE);
8951 tree void_ftype_v16qi_long_pvoid
8952 = build_function_type_list (void_type_node,
8953 V16QI_type_node, long_integer_type_node,
8954 pvoid_type_node, NULL_TREE);
8955 tree void_ftype_v8hi_long_pvoid
8956 = build_function_type_list (void_type_node,
8957 V8HI_type_node, long_integer_type_node,
8958 pvoid_type_node, NULL_TREE);
8959 tree int_ftype_int_v8hi_v8hi
8960 = build_function_type_list (integer_type_node,
8961 integer_type_node, V8HI_type_node,
8962 V8HI_type_node, NULL_TREE);
8963 tree int_ftype_int_v16qi_v16qi
8964 = build_function_type_list (integer_type_node,
8965 integer_type_node, V16QI_type_node,
8966 V16QI_type_node, NULL_TREE);
8967 tree int_ftype_int_v4sf_v4sf
8968 = build_function_type_list (integer_type_node,
8969 integer_type_node, V4SF_type_node,
8970 V4SF_type_node, NULL_TREE);
8971 tree v4si_ftype_v4si
8972 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8973 tree v8hi_ftype_v8hi
8974 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8975 tree v16qi_ftype_v16qi
8976 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8977 tree v4sf_ftype_v4sf
8978 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8979 tree void_ftype_pcvoid_int_int
8980 = build_function_type_list (void_type_node,
8981 pcvoid_type_node, integer_type_node,
8982 integer_type_node, NULL_TREE);
8984 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8985 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8986 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8987 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8988 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8989 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8990 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8991 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8992 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8993 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8994 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8995 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8996 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8997 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8998 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8999 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9000 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9001 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9002 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9003 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9004 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9005 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9006 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9007 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9008 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9009 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9010 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9011 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9012 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9013 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9014 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9015 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9016 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9017 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9018 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9019 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9020 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9021 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9022 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9023 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9024 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9025 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9026 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9027 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9028 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9029 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9031 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9033 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9034 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9035 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9036 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9037 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9038 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9039 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9040 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9041 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9042 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9044 /* Add the DST variants. */
9045 d = (struct builtin_description *) bdesc_dst;
9046 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9047 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9049 /* Initialize the predicates. */
9050 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
9051 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9053 enum machine_mode mode1;
9055 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9056 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9061 mode1 = insn_data[dp->icode].operand[1].mode;
9066 type = int_ftype_int_opaque_opaque;
9069 type = int_ftype_int_v4si_v4si;
9072 type = int_ftype_int_v8hi_v8hi;
9075 type = int_ftype_int_v16qi_v16qi;
9078 type = int_ftype_int_v4sf_v4sf;
9084 def_builtin (dp->mask, dp->name, type, dp->code);
9087 /* Initialize the abs* operators. */
9088 d = (struct builtin_description *) bdesc_abs;
9089 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9091 enum machine_mode mode0;
9094 mode0 = insn_data[d->icode].operand[0].mode;
9099 type = v4si_ftype_v4si;
9102 type = v8hi_ftype_v8hi;
9105 type = v16qi_ftype_v16qi;
9108 type = v4sf_ftype_v4sf;
9114 def_builtin (d->mask, d->name, type, d->code);
9121 /* Initialize target builtin that implements
9122 targetm.vectorize.builtin_mask_for_load. */
9124 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9125 v16qi_ftype_long_pcvoid,
9126 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9127 BUILT_IN_MD, NULL, NULL_TREE);
9128 TREE_READONLY (decl) = 1;
9129 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9130 altivec_builtin_mask_for_load = decl;
9133 /* Access to the vec_init patterns. */
9134 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9135 integer_type_node, integer_type_node,
9136 integer_type_node, NULL_TREE);
9137 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9138 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9140 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9141 short_integer_type_node,
9142 short_integer_type_node,
9143 short_integer_type_node,
9144 short_integer_type_node,
9145 short_integer_type_node,
9146 short_integer_type_node,
9147 short_integer_type_node, NULL_TREE);
9148 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9149 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9151 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9152 char_type_node, char_type_node,
9153 char_type_node, char_type_node,
9154 char_type_node, char_type_node,
9155 char_type_node, char_type_node,
9156 char_type_node, char_type_node,
9157 char_type_node, char_type_node,
9158 char_type_node, char_type_node,
9159 char_type_node, NULL_TREE);
9160 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9161 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9163 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9164 float_type_node, float_type_node,
9165 float_type_node, NULL_TREE);
9166 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9167 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9169 /* Access to the vec_set patterns. */
9170 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9172 integer_type_node, NULL_TREE);
9173 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9174 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9176 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9178 integer_type_node, NULL_TREE);
9179 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9180 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9182 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9184 integer_type_node, NULL_TREE);
9185 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9186 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9188 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9190 integer_type_node, NULL_TREE);
9191 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9192 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9194 /* Access to the vec_extract patterns. */
9195 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9196 integer_type_node, NULL_TREE);
9197 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9198 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9200 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9201 integer_type_node, NULL_TREE);
9202 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9203 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9205 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9206 integer_type_node, NULL_TREE);
9207 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9208 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9210 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9211 integer_type_node, NULL_TREE);
9212 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9213 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9217 rs6000_common_init_builtins (void)
9219 struct builtin_description *d;
9222 tree v4sf_ftype_v4sf_v4sf_v16qi
9223 = build_function_type_list (V4SF_type_node,
9224 V4SF_type_node, V4SF_type_node,
9225 V16QI_type_node, NULL_TREE);
9226 tree v4si_ftype_v4si_v4si_v16qi
9227 = build_function_type_list (V4SI_type_node,
9228 V4SI_type_node, V4SI_type_node,
9229 V16QI_type_node, NULL_TREE);
9230 tree v8hi_ftype_v8hi_v8hi_v16qi
9231 = build_function_type_list (V8HI_type_node,
9232 V8HI_type_node, V8HI_type_node,
9233 V16QI_type_node, NULL_TREE);
9234 tree v16qi_ftype_v16qi_v16qi_v16qi
9235 = build_function_type_list (V16QI_type_node,
9236 V16QI_type_node, V16QI_type_node,
9237 V16QI_type_node, NULL_TREE);
9239 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9241 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9242 tree v16qi_ftype_int
9243 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9244 tree v8hi_ftype_v16qi
9245 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9246 tree v4sf_ftype_v4sf
9247 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9249 tree v2si_ftype_v2si_v2si
9250 = build_function_type_list (opaque_V2SI_type_node,
9251 opaque_V2SI_type_node,
9252 opaque_V2SI_type_node, NULL_TREE);
9254 tree v2sf_ftype_v2sf_v2sf
9255 = build_function_type_list (opaque_V2SF_type_node,
9256 opaque_V2SF_type_node,
9257 opaque_V2SF_type_node, NULL_TREE);
9259 tree v2si_ftype_int_int
9260 = build_function_type_list (opaque_V2SI_type_node,
9261 integer_type_node, integer_type_node,
9264 tree opaque_ftype_opaque
9265 = build_function_type_list (opaque_V4SI_type_node,
9266 opaque_V4SI_type_node, NULL_TREE);
9268 tree v2si_ftype_v2si
9269 = build_function_type_list (opaque_V2SI_type_node,
9270 opaque_V2SI_type_node, NULL_TREE);
9272 tree v2sf_ftype_v2sf
9273 = build_function_type_list (opaque_V2SF_type_node,
9274 opaque_V2SF_type_node, NULL_TREE);
9276 tree v2sf_ftype_v2si
9277 = build_function_type_list (opaque_V2SF_type_node,
9278 opaque_V2SI_type_node, NULL_TREE);
9280 tree v2si_ftype_v2sf
9281 = build_function_type_list (opaque_V2SI_type_node,
9282 opaque_V2SF_type_node, NULL_TREE);
9284 tree v2si_ftype_v2si_char
9285 = build_function_type_list (opaque_V2SI_type_node,
9286 opaque_V2SI_type_node,
9287 char_type_node, NULL_TREE);
9289 tree v2si_ftype_int_char
9290 = build_function_type_list (opaque_V2SI_type_node,
9291 integer_type_node, char_type_node, NULL_TREE);
9293 tree v2si_ftype_char
9294 = build_function_type_list (opaque_V2SI_type_node,
9295 char_type_node, NULL_TREE);
9297 tree int_ftype_int_int
9298 = build_function_type_list (integer_type_node,
9299 integer_type_node, integer_type_node,
9302 tree opaque_ftype_opaque_opaque
9303 = build_function_type_list (opaque_V4SI_type_node,
9304 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9305 tree v4si_ftype_v4si_v4si
9306 = build_function_type_list (V4SI_type_node,
9307 V4SI_type_node, V4SI_type_node, NULL_TREE);
9308 tree v4sf_ftype_v4si_int
9309 = build_function_type_list (V4SF_type_node,
9310 V4SI_type_node, integer_type_node, NULL_TREE);
9311 tree v4si_ftype_v4sf_int
9312 = build_function_type_list (V4SI_type_node,
9313 V4SF_type_node, integer_type_node, NULL_TREE);
9314 tree v4si_ftype_v4si_int
9315 = build_function_type_list (V4SI_type_node,
9316 V4SI_type_node, integer_type_node, NULL_TREE);
9317 tree v8hi_ftype_v8hi_int
9318 = build_function_type_list (V8HI_type_node,
9319 V8HI_type_node, integer_type_node, NULL_TREE);
9320 tree v16qi_ftype_v16qi_int
9321 = build_function_type_list (V16QI_type_node,
9322 V16QI_type_node, integer_type_node, NULL_TREE);
9323 tree v16qi_ftype_v16qi_v16qi_int
9324 = build_function_type_list (V16QI_type_node,
9325 V16QI_type_node, V16QI_type_node,
9326 integer_type_node, NULL_TREE);
9327 tree v8hi_ftype_v8hi_v8hi_int
9328 = build_function_type_list (V8HI_type_node,
9329 V8HI_type_node, V8HI_type_node,
9330 integer_type_node, NULL_TREE);
9331 tree v4si_ftype_v4si_v4si_int
9332 = build_function_type_list (V4SI_type_node,
9333 V4SI_type_node, V4SI_type_node,
9334 integer_type_node, NULL_TREE);
9335 tree v4sf_ftype_v4sf_v4sf_int
9336 = build_function_type_list (V4SF_type_node,
9337 V4SF_type_node, V4SF_type_node,
9338 integer_type_node, NULL_TREE);
9339 tree v4sf_ftype_v4sf_v4sf
9340 = build_function_type_list (V4SF_type_node,
9341 V4SF_type_node, V4SF_type_node, NULL_TREE);
9342 tree opaque_ftype_opaque_opaque_opaque
9343 = build_function_type_list (opaque_V4SI_type_node,
9344 opaque_V4SI_type_node, opaque_V4SI_type_node,
9345 opaque_V4SI_type_node, NULL_TREE);
9346 tree v4sf_ftype_v4sf_v4sf_v4si
9347 = build_function_type_list (V4SF_type_node,
9348 V4SF_type_node, V4SF_type_node,
9349 V4SI_type_node, NULL_TREE);
9350 tree v4sf_ftype_v4sf_v4sf_v4sf
9351 = build_function_type_list (V4SF_type_node,
9352 V4SF_type_node, V4SF_type_node,
9353 V4SF_type_node, NULL_TREE);
9354 tree v4si_ftype_v4si_v4si_v4si
9355 = build_function_type_list (V4SI_type_node,
9356 V4SI_type_node, V4SI_type_node,
9357 V4SI_type_node, NULL_TREE);
9358 tree v8hi_ftype_v8hi_v8hi
9359 = build_function_type_list (V8HI_type_node,
9360 V8HI_type_node, V8HI_type_node, NULL_TREE);
9361 tree v8hi_ftype_v8hi_v8hi_v8hi
9362 = build_function_type_list (V8HI_type_node,
9363 V8HI_type_node, V8HI_type_node,
9364 V8HI_type_node, NULL_TREE);
9365 tree v4si_ftype_v8hi_v8hi_v4si
9366 = build_function_type_list (V4SI_type_node,
9367 V8HI_type_node, V8HI_type_node,
9368 V4SI_type_node, NULL_TREE);
9369 tree v4si_ftype_v16qi_v16qi_v4si
9370 = build_function_type_list (V4SI_type_node,
9371 V16QI_type_node, V16QI_type_node,
9372 V4SI_type_node, NULL_TREE);
9373 tree v16qi_ftype_v16qi_v16qi
9374 = build_function_type_list (V16QI_type_node,
9375 V16QI_type_node, V16QI_type_node, NULL_TREE);
9376 tree v4si_ftype_v4sf_v4sf
9377 = build_function_type_list (V4SI_type_node,
9378 V4SF_type_node, V4SF_type_node, NULL_TREE);
9379 tree v8hi_ftype_v16qi_v16qi
9380 = build_function_type_list (V8HI_type_node,
9381 V16QI_type_node, V16QI_type_node, NULL_TREE);
9382 tree v4si_ftype_v8hi_v8hi
9383 = build_function_type_list (V4SI_type_node,
9384 V8HI_type_node, V8HI_type_node, NULL_TREE);
9385 tree v8hi_ftype_v4si_v4si
9386 = build_function_type_list (V8HI_type_node,
9387 V4SI_type_node, V4SI_type_node, NULL_TREE);
9388 tree v16qi_ftype_v8hi_v8hi
9389 = build_function_type_list (V16QI_type_node,
9390 V8HI_type_node, V8HI_type_node, NULL_TREE);
9391 tree v4si_ftype_v16qi_v4si
9392 = build_function_type_list (V4SI_type_node,
9393 V16QI_type_node, V4SI_type_node, NULL_TREE);
9394 tree v4si_ftype_v16qi_v16qi
9395 = build_function_type_list (V4SI_type_node,
9396 V16QI_type_node, V16QI_type_node, NULL_TREE);
9397 tree v4si_ftype_v8hi_v4si
9398 = build_function_type_list (V4SI_type_node,
9399 V8HI_type_node, V4SI_type_node, NULL_TREE);
9400 tree v4si_ftype_v8hi
9401 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9402 tree int_ftype_v4si_v4si
9403 = build_function_type_list (integer_type_node,
9404 V4SI_type_node, V4SI_type_node, NULL_TREE);
9405 tree int_ftype_v4sf_v4sf
9406 = build_function_type_list (integer_type_node,
9407 V4SF_type_node, V4SF_type_node, NULL_TREE);
9408 tree int_ftype_v16qi_v16qi
9409 = build_function_type_list (integer_type_node,
9410 V16QI_type_node, V16QI_type_node, NULL_TREE);
9411 tree int_ftype_v8hi_v8hi
9412 = build_function_type_list (integer_type_node,
9413 V8HI_type_node, V8HI_type_node, NULL_TREE);
9415 /* Add the simple ternary operators. */
9416 d = (struct builtin_description *) bdesc_3arg;
9417 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9419 enum machine_mode mode0, mode1, mode2, mode3;
9421 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9422 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9433 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9436 mode0 = insn_data[d->icode].operand[0].mode;
9437 mode1 = insn_data[d->icode].operand[1].mode;
9438 mode2 = insn_data[d->icode].operand[2].mode;
9439 mode3 = insn_data[d->icode].operand[3].mode;
9442 /* When all four are of the same mode. */
9443 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9448 type = opaque_ftype_opaque_opaque_opaque;
9451 type = v4si_ftype_v4si_v4si_v4si;
9454 type = v4sf_ftype_v4sf_v4sf_v4sf;
9457 type = v8hi_ftype_v8hi_v8hi_v8hi;
9460 type = v16qi_ftype_v16qi_v16qi_v16qi;
9466 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9471 type = v4si_ftype_v4si_v4si_v16qi;
9474 type = v4sf_ftype_v4sf_v4sf_v16qi;
9477 type = v8hi_ftype_v8hi_v8hi_v16qi;
9480 type = v16qi_ftype_v16qi_v16qi_v16qi;
9486 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9487 && mode3 == V4SImode)
9488 type = v4si_ftype_v16qi_v16qi_v4si;
9489 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9490 && mode3 == V4SImode)
9491 type = v4si_ftype_v8hi_v8hi_v4si;
9492 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9493 && mode3 == V4SImode)
9494 type = v4sf_ftype_v4sf_v4sf_v4si;
9496 /* vchar, vchar, vchar, 4-bit literal. */
9497 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9499 type = v16qi_ftype_v16qi_v16qi_int;
9501 /* vshort, vshort, vshort, 4-bit literal. */
9502 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9504 type = v8hi_ftype_v8hi_v8hi_int;
9506 /* vint, vint, vint, 4-bit literal. */
9507 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9509 type = v4si_ftype_v4si_v4si_int;
9511 /* vfloat, vfloat, vfloat, 4-bit literal. */
9512 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9514 type = v4sf_ftype_v4sf_v4sf_int;
9519 def_builtin (d->mask, d->name, type, d->code);
9522 /* Add the simple binary operators. */
9523 d = (struct builtin_description *) bdesc_2arg;
9524 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9526 enum machine_mode mode0, mode1, mode2;
9528 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9529 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9539 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9542 mode0 = insn_data[d->icode].operand[0].mode;
9543 mode1 = insn_data[d->icode].operand[1].mode;
9544 mode2 = insn_data[d->icode].operand[2].mode;
9547 /* When all three operands are of the same mode. */
9548 if (mode0 == mode1 && mode1 == mode2)
9553 type = opaque_ftype_opaque_opaque;
9556 type = v4sf_ftype_v4sf_v4sf;
9559 type = v4si_ftype_v4si_v4si;
9562 type = v16qi_ftype_v16qi_v16qi;
9565 type = v8hi_ftype_v8hi_v8hi;
9568 type = v2si_ftype_v2si_v2si;
9571 type = v2sf_ftype_v2sf_v2sf;
9574 type = int_ftype_int_int;
9581 /* A few other combos we really don't want to do manually. */
9583 /* vint, vfloat, vfloat. */
9584 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9585 type = v4si_ftype_v4sf_v4sf;
9587 /* vshort, vchar, vchar. */
9588 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9589 type = v8hi_ftype_v16qi_v16qi;
9591 /* vint, vshort, vshort. */
9592 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9593 type = v4si_ftype_v8hi_v8hi;
9595 /* vshort, vint, vint. */
9596 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9597 type = v8hi_ftype_v4si_v4si;
9599 /* vchar, vshort, vshort. */
9600 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9601 type = v16qi_ftype_v8hi_v8hi;
9603 /* vint, vchar, vint. */
9604 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9605 type = v4si_ftype_v16qi_v4si;
9607 /* vint, vchar, vchar. */
9608 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9609 type = v4si_ftype_v16qi_v16qi;
9611 /* vint, vshort, vint. */
9612 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9613 type = v4si_ftype_v8hi_v4si;
9615 /* vint, vint, 5-bit literal. */
9616 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9617 type = v4si_ftype_v4si_int;
9619 /* vshort, vshort, 5-bit literal. */
9620 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9621 type = v8hi_ftype_v8hi_int;
9623 /* vchar, vchar, 5-bit literal. */
9624 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9625 type = v16qi_ftype_v16qi_int;
9627 /* vfloat, vint, 5-bit literal. */
9628 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9629 type = v4sf_ftype_v4si_int;
9631 /* vint, vfloat, 5-bit literal. */
9632 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9633 type = v4si_ftype_v4sf_int;
9635 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9636 type = v2si_ftype_int_int;
9638 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9639 type = v2si_ftype_v2si_char;
9641 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9642 type = v2si_ftype_int_char;
9647 gcc_assert (mode0 == SImode);
9651 type = int_ftype_v4si_v4si;
9654 type = int_ftype_v4sf_v4sf;
9657 type = int_ftype_v16qi_v16qi;
9660 type = int_ftype_v8hi_v8hi;
9667 def_builtin (d->mask, d->name, type, d->code);
9670 /* Add the simple unary operators. */
9671 d = (struct builtin_description *) bdesc_1arg;
9672 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9674 enum machine_mode mode0, mode1;
9676 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9677 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9686 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9689 mode0 = insn_data[d->icode].operand[0].mode;
9690 mode1 = insn_data[d->icode].operand[1].mode;
9693 if (mode0 == V4SImode && mode1 == QImode)
9694 type = v4si_ftype_int;
9695 else if (mode0 == V8HImode && mode1 == QImode)
9696 type = v8hi_ftype_int;
9697 else if (mode0 == V16QImode && mode1 == QImode)
9698 type = v16qi_ftype_int;
9699 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9700 type = opaque_ftype_opaque;
9701 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9702 type = v4sf_ftype_v4sf;
9703 else if (mode0 == V8HImode && mode1 == V16QImode)
9704 type = v8hi_ftype_v16qi;
9705 else if (mode0 == V4SImode && mode1 == V8HImode)
9706 type = v4si_ftype_v8hi;
9707 else if (mode0 == V2SImode && mode1 == V2SImode)
9708 type = v2si_ftype_v2si;
9709 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9710 type = v2sf_ftype_v2sf;
9711 else if (mode0 == V2SFmode && mode1 == V2SImode)
9712 type = v2sf_ftype_v2si;
9713 else if (mode0 == V2SImode && mode1 == V2SFmode)
9714 type = v2si_ftype_v2sf;
9715 else if (mode0 == V2SImode && mode1 == QImode)
9716 type = v2si_ftype_char;
9720 def_builtin (d->mask, d->name, type, d->code);
9725 rs6000_init_libfuncs (void)
9727 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9728 && !TARGET_POWER2 && !TARGET_POWERPC)
9730 /* AIX library routines for float->int conversion. */
9731 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9732 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9733 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9734 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9737 if (!TARGET_IEEEQUAD)
9738 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9739 if (!TARGET_XL_COMPAT)
9741 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9742 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9743 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9744 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9746 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9748 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9749 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9750 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9751 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9752 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9753 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9754 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9756 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9757 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9758 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9759 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9760 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9761 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9762 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9763 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9766 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
9767 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9771 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9772 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9773 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9774 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9778 /* 32-bit SVR4 quad floating point routines. */
9780 set_optab_libfunc (add_optab, TFmode, "_q_add");
9781 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9782 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9783 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9784 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9785 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9786 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9788 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9789 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9790 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9791 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9792 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9793 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9795 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9796 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9797 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9798 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9799 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9800 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9801 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9802 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9807 /* Expand a block clear operation, and return 1 if successful. Return 0
9808 if we should let the compiler generate normal code.
9810 operands[0] is the destination
9811 operands[1] is the length
9812 operands[3] is the alignment */
9815 expand_block_clear (rtx operands[])
9817 rtx orig_dest = operands[0];
9818 rtx bytes_rtx = operands[1];
9819 rtx align_rtx = operands[3];
9820 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9821 HOST_WIDE_INT align;
9822 HOST_WIDE_INT bytes;
9827 /* If this is not a fixed size move, just call memcpy */
9831 /* This must be a fixed size alignment */
9832 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9833 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9835 /* Anything to clear? */
9836 bytes = INTVAL (bytes_rtx);
9840 /* Use the builtin memset after a point, to avoid huge code bloat.
9841 When optimize_size, avoid any significant code bloat; calling
9842 memset is about 4 instructions, so allow for one instruction to
9843 load zero and three to do clearing. */
9844 if (TARGET_ALTIVEC && align >= 128)
9846 else if (TARGET_POWERPC64 && align >= 32)
9851 if (optimize_size && bytes > 3 * clear_step)
9853 if (! optimize_size && bytes > 8 * clear_step)
9856 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9858 enum machine_mode mode = BLKmode;
9861 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9866 else if (bytes >= 8 && TARGET_POWERPC64
9867 /* 64-bit loads and stores require word-aligned
9869 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9874 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9875 { /* move 4 bytes */
9879 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9880 { /* move 2 bytes */
9884 else /* move 1 byte at a time */
9890 dest = adjust_address (orig_dest, mode, offset);
9892 emit_move_insn (dest, CONST0_RTX (mode));
9899 /* Expand a block move operation, and return 1 if successful. Return 0
9900 if we should let the compiler generate normal code.
9902 operands[0] is the destination
9903 operands[1] is the source
9904 operands[2] is the length
9905 operands[3] is the alignment */
9907 #define MAX_MOVE_REG 4
9910 expand_block_move (rtx operands[])
9912 rtx orig_dest = operands[0];
9913 rtx orig_src = operands[1];
9914 rtx bytes_rtx = operands[2];
9915 rtx align_rtx = operands[3];
9916 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9921 rtx stores[MAX_MOVE_REG];
9924 /* If this is not a fixed size move, just call memcpy */
9928 /* This must be a fixed size alignment */
9929 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9930 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9932 /* Anything to move? */
9933 bytes = INTVAL (bytes_rtx);
9937 /* store_one_arg depends on expand_block_move to handle at least the size of
9938 reg_parm_stack_space. */
9939 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9942 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9945 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9946 rtx (*mov) (rtx, rtx);
9948 enum machine_mode mode = BLKmode;
9951 /* Altivec first, since it will be faster than a string move
9952 when it applies, and usually not significantly larger. */
9953 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9957 gen_func.mov = gen_movv4si;
9959 else if (TARGET_STRING
9960 && bytes > 24 /* move up to 32 bytes at a time */
9968 && ! fixed_regs[12])
9970 move_bytes = (bytes > 32) ? 32 : bytes;
9971 gen_func.movmemsi = gen_movmemsi_8reg;
9973 else if (TARGET_STRING
9974 && bytes > 16 /* move up to 24 bytes at a time */
9980 && ! fixed_regs[10])
9982 move_bytes = (bytes > 24) ? 24 : bytes;
9983 gen_func.movmemsi = gen_movmemsi_6reg;
9985 else if (TARGET_STRING
9986 && bytes > 8 /* move up to 16 bytes at a time */
9992 move_bytes = (bytes > 16) ? 16 : bytes;
9993 gen_func.movmemsi = gen_movmemsi_4reg;
9995 else if (bytes >= 8 && TARGET_POWERPC64
9996 /* 64-bit loads and stores require word-aligned
9998 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10002 gen_func.mov = gen_movdi;
10004 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10005 { /* move up to 8 bytes at a time */
10006 move_bytes = (bytes > 8) ? 8 : bytes;
10007 gen_func.movmemsi = gen_movmemsi_2reg;
10009 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10010 { /* move 4 bytes */
10013 gen_func.mov = gen_movsi;
10015 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10016 { /* move 2 bytes */
10019 gen_func.mov = gen_movhi;
10021 else if (TARGET_STRING && bytes > 1)
10022 { /* move up to 4 bytes at a time */
10023 move_bytes = (bytes > 4) ? 4 : bytes;
10024 gen_func.movmemsi = gen_movmemsi_1reg;
10026 else /* move 1 byte at a time */
10030 gen_func.mov = gen_movqi;
10033 src = adjust_address (orig_src, mode, offset);
10034 dest = adjust_address (orig_dest, mode, offset);
10036 if (mode != BLKmode)
10038 rtx tmp_reg = gen_reg_rtx (mode);
10040 emit_insn ((*gen_func.mov) (tmp_reg, src));
10041 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10044 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10047 for (i = 0; i < num_reg; i++)
10048 emit_insn (stores[i]);
10052 if (mode == BLKmode)
10054 /* Move the address into scratch registers. The movmemsi
10055 patterns require zero offset. */
10056 if (!REG_P (XEXP (src, 0)))
10058 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10059 src = replace_equiv_address (src, src_reg);
10061 set_mem_size (src, GEN_INT (move_bytes));
10063 if (!REG_P (XEXP (dest, 0)))
10065 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10066 dest = replace_equiv_address (dest, dest_reg);
10068 set_mem_size (dest, GEN_INT (move_bytes));
10070 emit_insn ((*gen_func.movmemsi) (dest, src,
10071 GEN_INT (move_bytes & 31),
10080 /* Return a string to perform a load_multiple operation.
10081 operands[0] is the vector.
10082 operands[1] is the source address.
10083 operands[2] is the first destination register. */
10086 rs6000_output_load_multiple (rtx operands[3])
10088 /* We have to handle the case where the pseudo used to contain the address
10089 is assigned to one of the output registers. */
10091 int words = XVECLEN (operands[0], 0);
10094 if (XVECLEN (operands[0], 0) == 1)
10095 return "{l|lwz} %2,0(%1)";
10097 for (i = 0; i < words; i++)
10098 if (refers_to_regno_p (REGNO (operands[2]) + i,
10099 REGNO (operands[2]) + i + 1, operands[1], 0))
10103 xop[0] = GEN_INT (4 * (words-1));
10104 xop[1] = operands[1];
10105 xop[2] = operands[2];
10106 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10111 xop[0] = GEN_INT (4 * (words-1));
10112 xop[1] = operands[1];
10113 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10114 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10119 for (j = 0; j < words; j++)
10122 xop[0] = GEN_INT (j * 4);
10123 xop[1] = operands[1];
10124 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10125 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10127 xop[0] = GEN_INT (i * 4);
10128 xop[1] = operands[1];
10129 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10134 return "{lsi|lswi} %2,%1,%N0";
10138 /* A validation routine: say whether CODE, a condition code, and MODE
10139 match. The other alternatives either don't make sense or should
10140 never be generated. */
10143 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10145 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10146 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10147 && GET_MODE_CLASS (mode) == MODE_CC);
10149 /* These don't make sense. */
10150 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10151 || mode != CCUNSmode);
10153 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10154 || mode == CCUNSmode);
10156 gcc_assert (mode == CCFPmode
10157 || (code != ORDERED && code != UNORDERED
10158 && code != UNEQ && code != LTGT
10159 && code != UNGT && code != UNLT
10160 && code != UNGE && code != UNLE));
10162 /* These should never be generated except for
10163 flag_finite_math_only. */
10164 gcc_assert (mode != CCFPmode
10165 || flag_finite_math_only
10166 || (code != LE && code != GE
10167 && code != UNEQ && code != LTGT
10168 && code != UNGT && code != UNLT));
10170 /* These are invalid; the information is not there. */
10171 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10175 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10176 mask required to convert the result of a rotate insn into a shift
10177 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10180 includes_lshift_p (rtx shiftop, rtx andop)
10182 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10184 shift_mask <<= INTVAL (shiftop);
10186 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10189 /* Similar, but for right shift. */
10192 includes_rshift_p (rtx shiftop, rtx andop)
10194 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10196 shift_mask >>= INTVAL (shiftop);
10198 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10201 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10202 to perform a left shift. It must have exactly SHIFTOP least
10203 significant 0's, then one or more 1's, then zero or more 0's. */
10206 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10208 if (GET_CODE (andop) == CONST_INT)
10210 HOST_WIDE_INT c, lsb, shift_mask;
10212 c = INTVAL (andop);
10213 if (c == 0 || c == ~0)
10217 shift_mask <<= INTVAL (shiftop);
10219 /* Find the least significant one bit. */
10222 /* It must coincide with the LSB of the shift mask. */
10223 if (-lsb != shift_mask)
10226 /* Invert to look for the next transition (if any). */
10229 /* Remove the low group of ones (originally low group of zeros). */
10232 /* Again find the lsb, and check we have all 1's above. */
10236 else if (GET_CODE (andop) == CONST_DOUBLE
10237 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10239 HOST_WIDE_INT low, high, lsb;
10240 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10242 low = CONST_DOUBLE_LOW (andop);
10243 if (HOST_BITS_PER_WIDE_INT < 64)
10244 high = CONST_DOUBLE_HIGH (andop);
10246 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10247 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10250 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10252 shift_mask_high = ~0;
10253 if (INTVAL (shiftop) > 32)
10254 shift_mask_high <<= INTVAL (shiftop) - 32;
10256 lsb = high & -high;
10258 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10264 lsb = high & -high;
10265 return high == -lsb;
10268 shift_mask_low = ~0;
10269 shift_mask_low <<= INTVAL (shiftop);
10273 if (-lsb != shift_mask_low)
10276 if (HOST_BITS_PER_WIDE_INT < 64)
10281 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10283 lsb = high & -high;
10284 return high == -lsb;
10288 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10294 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10295 to perform a left shift. It must have SHIFTOP or more least
10296 significant 0's, with the remainder of the word 1's. */
10299 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10301 if (GET_CODE (andop) == CONST_INT)
10303 HOST_WIDE_INT c, lsb, shift_mask;
10306 shift_mask <<= INTVAL (shiftop);
10307 c = INTVAL (andop);
10309 /* Find the least significant one bit. */
10312 /* It must be covered by the shift mask.
10313 This test also rejects c == 0. */
10314 if ((lsb & shift_mask) == 0)
10317 /* Check we have all 1's above the transition, and reject all 1's. */
10318 return c == -lsb && lsb != 1;
10320 else if (GET_CODE (andop) == CONST_DOUBLE
10321 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10323 HOST_WIDE_INT low, lsb, shift_mask_low;
10325 low = CONST_DOUBLE_LOW (andop);
10327 if (HOST_BITS_PER_WIDE_INT < 64)
10329 HOST_WIDE_INT high, shift_mask_high;
10331 high = CONST_DOUBLE_HIGH (andop);
10335 shift_mask_high = ~0;
10336 if (INTVAL (shiftop) > 32)
10337 shift_mask_high <<= INTVAL (shiftop) - 32;
10339 lsb = high & -high;
10341 if ((lsb & shift_mask_high) == 0)
10344 return high == -lsb;
10350 shift_mask_low = ~0;
10351 shift_mask_low <<= INTVAL (shiftop);
10355 if ((lsb & shift_mask_low) == 0)
10358 return low == -lsb && lsb != 1;
10364 /* Return 1 if operands will generate a valid arguments to rlwimi
10365 instruction for insert with right shift in 64-bit mode. The mask may
10366 not start on the first bit or stop on the last bit because wrap-around
10367 effects of instruction do not correspond to semantics of RTL insn. */
10370 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10372 if (INTVAL (startop) > 32
10373 && INTVAL (startop) < 64
10374 && INTVAL (sizeop) > 1
10375 && INTVAL (sizeop) + INTVAL (startop) < 64
10376 && INTVAL (shiftop) > 0
10377 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10378 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10384 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10385 for lfq and stfq insns iff the registers are hard registers. */
10388 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10390 /* We might have been passed a SUBREG. */
10391 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10394 /* We might have been passed non floating point registers. */
10395 if (!FP_REGNO_P (REGNO (reg1))
10396 || !FP_REGNO_P (REGNO (reg2)))
10399 return (REGNO (reg1) == REGNO (reg2) - 1);
10402 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10403 addr1 and addr2 must be in consecutive memory locations
10404 (addr2 == addr1 + 8). */
10407 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10410 unsigned int reg1, reg2;
10411 int offset1, offset2;
10413 /* The mems cannot be volatile. */
10414 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10417 addr1 = XEXP (mem1, 0);
10418 addr2 = XEXP (mem2, 0);
10420 /* Extract an offset (if used) from the first addr. */
10421 if (GET_CODE (addr1) == PLUS)
10423 /* If not a REG, return zero. */
10424 if (GET_CODE (XEXP (addr1, 0)) != REG)
10428 reg1 = REGNO (XEXP (addr1, 0));
10429 /* The offset must be constant! */
10430 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10432 offset1 = INTVAL (XEXP (addr1, 1));
10435 else if (GET_CODE (addr1) != REG)
10439 reg1 = REGNO (addr1);
10440 /* This was a simple (mem (reg)) expression. Offset is 0. */
10444 /* And now for the second addr. */
10445 if (GET_CODE (addr2) == PLUS)
10447 /* If not a REG, return zero. */
10448 if (GET_CODE (XEXP (addr2, 0)) != REG)
10452 reg2 = REGNO (XEXP (addr2, 0));
10453 /* The offset must be constant. */
10454 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10456 offset2 = INTVAL (XEXP (addr2, 1));
10459 else if (GET_CODE (addr2) != REG)
10463 reg2 = REGNO (addr2);
10464 /* This was a simple (mem (reg)) expression. Offset is 0. */
10468 /* Both of these must have the same base register. */
10472 /* The offset for the second addr must be 8 more than the first addr. */
10473 if (offset2 != offset1 + 8)
10476 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10481 /* Return the register class of a scratch register needed to copy IN into
10482 or out of a register in CLASS in MODE. If it can be done directly,
10483 NO_REGS is returned. */
10486 rs6000_secondary_reload_class (enum reg_class class,
10487 enum machine_mode mode ATTRIBUTE_UNUSED,
10492 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10494 && MACHOPIC_INDIRECT
10498 /* We cannot copy a symbolic operand directly into anything
10499 other than BASE_REGS for TARGET_ELF. So indicate that a
10500 register from BASE_REGS is needed as an intermediate
10503 On Darwin, pic addresses require a load from memory, which
10504 needs a base register. */
10505 if (class != BASE_REGS
10506 && (GET_CODE (in) == SYMBOL_REF
10507 || GET_CODE (in) == HIGH
10508 || GET_CODE (in) == LABEL_REF
10509 || GET_CODE (in) == CONST))
10513 if (GET_CODE (in) == REG)
10515 regno = REGNO (in);
10516 if (regno >= FIRST_PSEUDO_REGISTER)
10518 regno = true_regnum (in);
10519 if (regno >= FIRST_PSEUDO_REGISTER)
10523 else if (GET_CODE (in) == SUBREG)
10525 regno = true_regnum (in);
10526 if (regno >= FIRST_PSEUDO_REGISTER)
10532 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10534 if (class == GENERAL_REGS || class == BASE_REGS
10535 || (regno >= 0 && INT_REGNO_P (regno)))
10538 /* Constants, memory, and FP registers can go into FP registers. */
10539 if ((regno == -1 || FP_REGNO_P (regno))
10540 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10543 /* Memory, and AltiVec registers can go into AltiVec registers. */
10544 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10545 && class == ALTIVEC_REGS)
10548 /* We can copy among the CR registers. */
10549 if ((class == CR_REGS || class == CR0_REGS)
10550 && regno >= 0 && CR_REGNO_P (regno))
10553 /* Otherwise, we need GENERAL_REGS. */
10554 return GENERAL_REGS;
10557 /* Given a comparison operation, return the bit number in CCR to test. We
10558 know this is a valid comparison.
10560 SCC_P is 1 if this is for an scc. That means that %D will have been
10561 used instead of %C, so the bits will be in different places.
10563 Return -1 if OP isn't a valid comparison for some reason. */
10566 ccr_bit (rtx op, int scc_p)
10568 enum rtx_code code = GET_CODE (op);
10569 enum machine_mode cc_mode;
10574 if (!COMPARISON_P (op))
10577 reg = XEXP (op, 0);
10579 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10581 cc_mode = GET_MODE (reg);
10582 cc_regnum = REGNO (reg);
10583 base_bit = 4 * (cc_regnum - CR0_REGNO);
10585 validate_condition_mode (code, cc_mode);
10587 /* When generating a sCOND operation, only positive conditions are
10590 || code == EQ || code == GT || code == LT || code == UNORDERED
10591 || code == GTU || code == LTU);
10596 return scc_p ? base_bit + 3 : base_bit + 2;
10598 return base_bit + 2;
10599 case GT: case GTU: case UNLE:
10600 return base_bit + 1;
10601 case LT: case LTU: case UNGE:
10603 case ORDERED: case UNORDERED:
10604 return base_bit + 3;
10607 /* If scc, we will have done a cror to put the bit in the
10608 unordered position. So test that bit. For integer, this is ! LT
10609 unless this is an scc insn. */
10610 return scc_p ? base_bit + 3 : base_bit;
10613 return scc_p ? base_bit + 3 : base_bit + 1;
10616 gcc_unreachable ();
10620 /* Return the GOT register. */
10623 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10625 /* The second flow pass currently (June 1999) can't update
10626 regs_ever_live without disturbing other parts of the compiler, so
10627 update it here to make the prolog/epilogue code happy. */
10628 if (!can_create_pseudo_p ()
10629 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
10630 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
10632 current_function_uses_pic_offset_table = 1;
10634 return pic_offset_table_rtx;
10637 /* Function to init struct machine_function.
10638 This will be called, via a pointer variable,
10639 from push_function_context. */
10641 static struct machine_function *
10642 rs6000_init_machine_status (void)
10644 return ggc_alloc_cleared (sizeof (machine_function));
10647 /* These macros test for integers and extract the low-order bits. */
10649 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10650 && GET_MODE (X) == VOIDmode)
10652 #define INT_LOWPART(X) \
10653 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10656 extract_MB (rtx op)
10659 unsigned long val = INT_LOWPART (op);
10661 /* If the high bit is zero, the value is the first 1 bit we find
10663 if ((val & 0x80000000) == 0)
10665 gcc_assert (val & 0xffffffff);
10668 while (((val <<= 1) & 0x80000000) == 0)
10673 /* If the high bit is set and the low bit is not, or the mask is all
10674 1's, the value is zero. */
10675 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10678 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10681 while (((val >>= 1) & 1) != 0)
10688 extract_ME (rtx op)
10691 unsigned long val = INT_LOWPART (op);
10693 /* If the low bit is zero, the value is the first 1 bit we find from
10695 if ((val & 1) == 0)
10697 gcc_assert (val & 0xffffffff);
10700 while (((val >>= 1) & 1) == 0)
10706 /* If the low bit is set and the high bit is not, or the mask is all
10707 1's, the value is 31. */
10708 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10711 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10714 while (((val <<= 1) & 0x80000000) != 0)
10720 /* Locate some local-dynamic symbol still in use by this function
10721 so that we can print its name in some tls_ld pattern. */
10723 static const char *
10724 rs6000_get_some_local_dynamic_name (void)
10728 if (cfun->machine->some_ld_name)
10729 return cfun->machine->some_ld_name;
10731 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10733 && for_each_rtx (&PATTERN (insn),
10734 rs6000_get_some_local_dynamic_name_1, 0))
10735 return cfun->machine->some_ld_name;
10737 gcc_unreachable ();
10740 /* Helper function for rs6000_get_some_local_dynamic_name. */
10743 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10747 if (GET_CODE (x) == SYMBOL_REF)
10749 const char *str = XSTR (x, 0);
10750 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10752 cfun->machine->some_ld_name = str;
10760 /* Write out a function code label. */
10763 rs6000_output_function_entry (FILE *file, const char *fname)
10765 if (fname[0] != '.')
10767 switch (DEFAULT_ABI)
10770 gcc_unreachable ();
10776 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10785 RS6000_OUTPUT_BASENAME (file, fname);
10787 assemble_name (file, fname);
10790 /* Print an operand. Recognize special options, documented below. */
10793 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10794 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10796 #define SMALL_DATA_RELOC "sda21"
10797 #define SMALL_DATA_REG 0
10801 print_operand (FILE *file, rtx x, int code)
10805 unsigned HOST_WIDE_INT uval;
10810 /* Write out an instruction after the call which may be replaced
10811 with glue code by the loader. This depends on the AIX version. */
10812 asm_fprintf (file, RS6000_CALL_GLUE);
10815 /* %a is output_address. */
10818 /* If X is a constant integer whose low-order 5 bits are zero,
10819 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10820 in the AIX assembler where "sri" with a zero shift count
10821 writes a trash instruction. */
10822 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10829 /* If constant, low-order 16 bits of constant, unsigned.
10830 Otherwise, write normally. */
10832 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10834 print_operand (file, x, 0);
10838 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10839 for 64-bit mask direction. */
10840 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10843 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10847 /* X is a CR register. Print the number of the GT bit of the CR. */
10848 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10849 output_operand_lossage ("invalid %%E value");
10851 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10855 /* Like 'J' but get to the GT bit only. */
10856 gcc_assert (GET_CODE (x) == REG);
10858 /* Bit 1 is GT bit. */
10859 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10861 /* Add one for shift count in rlinm for scc. */
10862 fprintf (file, "%d", i + 1);
10866 /* X is a CR register. Print the number of the EQ bit of the CR */
10867 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10868 output_operand_lossage ("invalid %%E value");
10870 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10874 /* X is a CR register. Print the shift count needed to move it
10875 to the high-order four bits. */
10876 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10877 output_operand_lossage ("invalid %%f value");
10879 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10883 /* Similar, but print the count for the rotate in the opposite
10885 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10886 output_operand_lossage ("invalid %%F value");
10888 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10892 /* X is a constant integer. If it is negative, print "m",
10893 otherwise print "z". This is to make an aze or ame insn. */
10894 if (GET_CODE (x) != CONST_INT)
10895 output_operand_lossage ("invalid %%G value");
10896 else if (INTVAL (x) >= 0)
10903 /* If constant, output low-order five bits. Otherwise, write
10906 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10908 print_operand (file, x, 0);
10912 /* If constant, output low-order six bits. Otherwise, write
10915 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10917 print_operand (file, x, 0);
10921 /* Print `i' if this is a constant, else nothing. */
10927 /* Write the bit number in CCR for jump. */
10928 i = ccr_bit (x, 0);
10930 output_operand_lossage ("invalid %%j code");
10932 fprintf (file, "%d", i);
10936 /* Similar, but add one for shift count in rlinm for scc and pass
10937 scc flag to `ccr_bit'. */
10938 i = ccr_bit (x, 1);
10940 output_operand_lossage ("invalid %%J code");
10942 /* If we want bit 31, write a shift count of zero, not 32. */
10943 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10947 /* X must be a constant. Write the 1's complement of the
10950 output_operand_lossage ("invalid %%k value");
10952 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10956 /* X must be a symbolic constant on ELF. Write an
10957 expression suitable for an 'addi' that adds in the low 16
10958 bits of the MEM. */
10959 if (GET_CODE (x) != CONST)
10961 print_operand_address (file, x);
10962 fputs ("@l", file);
10966 if (GET_CODE (XEXP (x, 0)) != PLUS
10967 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10968 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10969 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10970 output_operand_lossage ("invalid %%K value");
10971 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10972 fputs ("@l", file);
10973 /* For GNU as, there must be a non-alphanumeric character
10974 between 'l' and the number. The '-' is added by
10975 print_operand() already. */
10976 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10978 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10982 /* %l is output_asm_label. */
10985 /* Write second word of DImode or DFmode reference. Works on register
10986 or non-indexed memory only. */
10987 if (GET_CODE (x) == REG)
10988 fputs (reg_names[REGNO (x) + 1], file);
10989 else if (GET_CODE (x) == MEM)
10991 /* Handle possible auto-increment. Since it is pre-increment and
10992 we have already done it, we can just use an offset of word. */
10993 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10994 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10995 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10997 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
10998 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11001 output_address (XEXP (adjust_address_nv (x, SImode,
11005 if (small_data_operand (x, GET_MODE (x)))
11006 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11007 reg_names[SMALL_DATA_REG]);
11012 /* MB value for a mask operand. */
11013 if (! mask_operand (x, SImode))
11014 output_operand_lossage ("invalid %%m value");
11016 fprintf (file, "%d", extract_MB (x));
11020 /* ME value for a mask operand. */
11021 if (! mask_operand (x, SImode))
11022 output_operand_lossage ("invalid %%M value");
11024 fprintf (file, "%d", extract_ME (x));
11027 /* %n outputs the negative of its operand. */
11030 /* Write the number of elements in the vector times 4. */
11031 if (GET_CODE (x) != PARALLEL)
11032 output_operand_lossage ("invalid %%N value");
11034 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11038 /* Similar, but subtract 1 first. */
11039 if (GET_CODE (x) != PARALLEL)
11040 output_operand_lossage ("invalid %%O value");
11042 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11046 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11048 || INT_LOWPART (x) < 0
11049 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11050 output_operand_lossage ("invalid %%p value");
11052 fprintf (file, "%d", i);
11056 /* The operand must be an indirect memory reference. The result
11057 is the register name. */
11058 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11059 || REGNO (XEXP (x, 0)) >= 32)
11060 output_operand_lossage ("invalid %%P value");
11062 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11066 /* This outputs the logical code corresponding to a boolean
11067 expression. The expression may have one or both operands
11068 negated (if one, only the first one). For condition register
11069 logical operations, it will also treat the negated
11070 CR codes as NOTs, but not handle NOTs of them. */
11072 const char *const *t = 0;
11074 enum rtx_code code = GET_CODE (x);
11075 static const char * const tbl[3][3] = {
11076 { "and", "andc", "nor" },
11077 { "or", "orc", "nand" },
11078 { "xor", "eqv", "xor" } };
11082 else if (code == IOR)
11084 else if (code == XOR)
11087 output_operand_lossage ("invalid %%q value");
11089 if (GET_CODE (XEXP (x, 0)) != NOT)
11093 if (GET_CODE (XEXP (x, 1)) == NOT)
11111 /* X is a CR register. Print the mask for `mtcrf'. */
11112 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11113 output_operand_lossage ("invalid %%R value");
11115 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11119 /* Low 5 bits of 32 - value */
11121 output_operand_lossage ("invalid %%s value");
11123 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11127 /* PowerPC64 mask position. All 0's is excluded.
11128 CONST_INT 32-bit mask is considered sign-extended so any
11129 transition must occur within the CONST_INT, not on the boundary. */
11130 if (! mask64_operand (x, DImode))
11131 output_operand_lossage ("invalid %%S value");
11133 uval = INT_LOWPART (x);
11135 if (uval & 1) /* Clear Left */
11137 #if HOST_BITS_PER_WIDE_INT > 64
11138 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11142 else /* Clear Right */
11145 #if HOST_BITS_PER_WIDE_INT > 64
11146 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11152 gcc_assert (i >= 0);
11153 fprintf (file, "%d", i);
11157 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11158 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11160 /* Bit 3 is OV bit. */
11161 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11163 /* If we want bit 31, write a shift count of zero, not 32. */
11164 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11168 /* Print the symbolic name of a branch target register. */
11169 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11170 && REGNO (x) != CTR_REGNO))
11171 output_operand_lossage ("invalid %%T value");
11172 else if (REGNO (x) == LR_REGNO)
11173 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11175 fputs ("ctr", file);
11179 /* High-order 16 bits of constant for use in unsigned operand. */
11181 output_operand_lossage ("invalid %%u value");
11183 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11184 (INT_LOWPART (x) >> 16) & 0xffff);
11188 /* High-order 16 bits of constant for use in signed operand. */
11190 output_operand_lossage ("invalid %%v value");
11192 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11193 (INT_LOWPART (x) >> 16) & 0xffff);
11197 /* Print `u' if this has an auto-increment or auto-decrement. */
11198 if (GET_CODE (x) == MEM
11199 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11200 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11201 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11206 /* Print the trap code for this operand. */
11207 switch (GET_CODE (x))
11210 fputs ("eq", file); /* 4 */
11213 fputs ("ne", file); /* 24 */
11216 fputs ("lt", file); /* 16 */
11219 fputs ("le", file); /* 20 */
11222 fputs ("gt", file); /* 8 */
11225 fputs ("ge", file); /* 12 */
11228 fputs ("llt", file); /* 2 */
11231 fputs ("lle", file); /* 6 */
11234 fputs ("lgt", file); /* 1 */
11237 fputs ("lge", file); /* 5 */
11240 gcc_unreachable ();
11245 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11248 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11249 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11251 print_operand (file, x, 0);
11255 /* MB value for a PowerPC64 rldic operand. */
11256 val = (GET_CODE (x) == CONST_INT
11257 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11262 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11263 if ((val <<= 1) < 0)
11266 #if HOST_BITS_PER_WIDE_INT == 32
11267 if (GET_CODE (x) == CONST_INT && i >= 0)
11268 i += 32; /* zero-extend high-part was all 0's */
11269 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11271 val = CONST_DOUBLE_LOW (x);
11277 for ( ; i < 64; i++)
11278 if ((val <<= 1) < 0)
11283 fprintf (file, "%d", i + 1);
11287 if (GET_CODE (x) == MEM
11288 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11289 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11290 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11295 /* Like 'L', for third word of TImode */
11296 if (GET_CODE (x) == REG)
11297 fputs (reg_names[REGNO (x) + 2], file);
11298 else if (GET_CODE (x) == MEM)
11300 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11301 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11302 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11303 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11304 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11306 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11307 if (small_data_operand (x, GET_MODE (x)))
11308 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11309 reg_names[SMALL_DATA_REG]);
11314 /* X is a SYMBOL_REF. Write out the name preceded by a
11315 period and without any trailing data in brackets. Used for function
11316 names. If we are configured for System V (or the embedded ABI) on
11317 the PowerPC, do not emit the period, since those systems do not use
11318 TOCs and the like. */
11319 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11321 /* Mark the decl as referenced so that cgraph will output the
11323 if (SYMBOL_REF_DECL (x))
11324 mark_decl_referenced (SYMBOL_REF_DECL (x));
11326 /* For macho, check to see if we need a stub. */
11329 const char *name = XSTR (x, 0);
11331 if (MACHOPIC_INDIRECT
11332 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11333 name = machopic_indirection_name (x, /*stub_p=*/true);
11335 assemble_name (file, name);
11337 else if (!DOT_SYMBOLS)
11338 assemble_name (file, XSTR (x, 0));
11340 rs6000_output_function_entry (file, XSTR (x, 0));
11344 /* Like 'L', for last word of TImode. */
11345 if (GET_CODE (x) == REG)
11346 fputs (reg_names[REGNO (x) + 3], file);
11347 else if (GET_CODE (x) == MEM)
11349 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11350 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11351 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11352 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11353 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11355 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11356 if (small_data_operand (x, GET_MODE (x)))
11357 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11358 reg_names[SMALL_DATA_REG]);
11362 /* Print AltiVec or SPE memory operand. */
11367 gcc_assert (GET_CODE (x) == MEM);
11371 /* Ugly hack because %y is overloaded. */
11372 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11373 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11374 || GET_MODE (x) == TFmode
11375 || GET_MODE (x) == TImode))
11377 /* Handle [reg]. */
11378 if (GET_CODE (tmp) == REG)
11380 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11383 /* Handle [reg+UIMM]. */
11384 else if (GET_CODE (tmp) == PLUS &&
11385 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11389 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11391 x = INTVAL (XEXP (tmp, 1));
11392 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11396 /* Fall through. Must be [reg+reg]. */
11399 && GET_CODE (tmp) == AND
11400 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11401 && INTVAL (XEXP (tmp, 1)) == -16)
11402 tmp = XEXP (tmp, 0);
11403 if (GET_CODE (tmp) == REG)
11404 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11407 gcc_assert (GET_CODE (tmp) == PLUS
11408 && REG_P (XEXP (tmp, 0))
11409 && REG_P (XEXP (tmp, 1)));
11411 if (REGNO (XEXP (tmp, 0)) == 0)
11412 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11413 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11415 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11416 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11422 if (GET_CODE (x) == REG)
11423 fprintf (file, "%s", reg_names[REGNO (x)]);
11424 else if (GET_CODE (x) == MEM)
11426 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11427 know the width from the mode. */
11428 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11429 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11430 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11431 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11432 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11433 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11434 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11435 output_address (XEXP (XEXP (x, 0), 1));
11437 output_address (XEXP (x, 0));
11440 output_addr_const (file, x);
11444 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11448 output_operand_lossage ("invalid %%xn code");
11452 /* Print the address of an operand. */
11455 print_operand_address (FILE *file, rtx x)
11457 if (GET_CODE (x) == REG)
11458 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11459 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11460 || GET_CODE (x) == LABEL_REF)
11462 output_addr_const (file, x);
11463 if (small_data_operand (x, GET_MODE (x)))
11464 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11465 reg_names[SMALL_DATA_REG]);
11467 gcc_assert (!TARGET_TOC);
11469 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11471 gcc_assert (REG_P (XEXP (x, 0)));
11472 if (REGNO (XEXP (x, 0)) == 0)
11473 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11474 reg_names[ REGNO (XEXP (x, 0)) ]);
11476 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11477 reg_names[ REGNO (XEXP (x, 1)) ]);
11479 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11480 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11481 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11483 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11484 && CONSTANT_P (XEXP (x, 1)))
11486 output_addr_const (file, XEXP (x, 1));
11487 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11491 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11492 && CONSTANT_P (XEXP (x, 1)))
11494 fprintf (file, "lo16(");
11495 output_addr_const (file, XEXP (x, 1));
11496 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11499 else if (legitimate_constant_pool_address_p (x))
11501 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11503 rtx contains_minus = XEXP (x, 1);
11507 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11508 turn it into (sym) for output_addr_const. */
11509 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11510 contains_minus = XEXP (contains_minus, 0);
11512 minus = XEXP (contains_minus, 0);
11513 symref = XEXP (minus, 0);
11514 XEXP (contains_minus, 0) = symref;
11519 name = XSTR (symref, 0);
11520 newname = alloca (strlen (name) + sizeof ("@toc"));
11521 strcpy (newname, name);
11522 strcat (newname, "@toc");
11523 XSTR (symref, 0) = newname;
11525 output_addr_const (file, XEXP (x, 1));
11527 XSTR (symref, 0) = name;
11528 XEXP (contains_minus, 0) = minus;
11531 output_addr_const (file, XEXP (x, 1));
11533 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11536 gcc_unreachable ();
11539 /* Target hook for assembling integer objects. The PowerPC version has
11540 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11541 is defined. It also needs to handle DI-mode objects on 64-bit
11545 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11547 #ifdef RELOCATABLE_NEEDS_FIXUP
11548 /* Special handling for SI values. */
11549 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11551 static int recurse = 0;
11553 /* For -mrelocatable, we mark all addresses that need to be fixed up
11554 in the .fixup section. */
11555 if (TARGET_RELOCATABLE
11556 && in_section != toc_section
11557 && in_section != text_section
11558 && !unlikely_text_section_p (in_section)
11560 && GET_CODE (x) != CONST_INT
11561 && GET_CODE (x) != CONST_DOUBLE
11567 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11569 ASM_OUTPUT_LABEL (asm_out_file, buf);
11570 fprintf (asm_out_file, "\t.long\t(");
11571 output_addr_const (asm_out_file, x);
11572 fprintf (asm_out_file, ")@fixup\n");
11573 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11574 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11575 fprintf (asm_out_file, "\t.long\t");
11576 assemble_name (asm_out_file, buf);
11577 fprintf (asm_out_file, "\n\t.previous\n");
11581 /* Remove initial .'s to turn a -mcall-aixdesc function
11582 address into the address of the descriptor, not the function
11584 else if (GET_CODE (x) == SYMBOL_REF
11585 && XSTR (x, 0)[0] == '.'
11586 && DEFAULT_ABI == ABI_AIX)
11588 const char *name = XSTR (x, 0);
11589 while (*name == '.')
11592 fprintf (asm_out_file, "\t.long\t%s\n", name);
11596 #endif /* RELOCATABLE_NEEDS_FIXUP */
11597 return default_assemble_integer (x, size, aligned_p);
11600 #ifdef HAVE_GAS_HIDDEN
11601 /* Emit an assembler directive to set symbol visibility for DECL to
11602 VISIBILITY_TYPE. */
11605 rs6000_assemble_visibility (tree decl, int vis)
11607 /* Functions need to have their entry point symbol visibility set as
11608 well as their descriptor symbol visibility. */
11609 if (DEFAULT_ABI == ABI_AIX
11611 && TREE_CODE (decl) == FUNCTION_DECL)
11613 static const char * const visibility_types[] = {
11614 NULL, "internal", "hidden", "protected"
11617 const char *name, *type;
11619 name = ((* targetm.strip_name_encoding)
11620 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11621 type = visibility_types[vis];
11623 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11624 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11627 default_assemble_visibility (decl, vis);
11632 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11634 /* Reversal of FP compares takes care -- an ordered compare
11635 becomes an unordered compare and vice versa. */
11636 if (mode == CCFPmode
11637 && (!flag_finite_math_only
11638 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11639 || code == UNEQ || code == LTGT))
11640 return reverse_condition_maybe_unordered (code);
11642 return reverse_condition (code);
11645 /* Generate a compare for CODE. Return a brand-new rtx that
11646 represents the result of the compare. */
11649 rs6000_generate_compare (enum rtx_code code)
11651 enum machine_mode comp_mode;
11652 rtx compare_result;
11654 if (rs6000_compare_fp_p)
11655 comp_mode = CCFPmode;
11656 else if (code == GTU || code == LTU
11657 || code == GEU || code == LEU)
11658 comp_mode = CCUNSmode;
11659 else if ((code == EQ || code == NE)
11660 && GET_CODE (rs6000_compare_op0) == SUBREG
11661 && GET_CODE (rs6000_compare_op1) == SUBREG
11662 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11663 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11664 /* These are unsigned values, perhaps there will be a later
11665 ordering compare that can be shared with this one.
11666 Unfortunately we cannot detect the signedness of the operands
11667 for non-subregs. */
11668 comp_mode = CCUNSmode;
11670 comp_mode = CCmode;
11672 /* First, the compare. */
11673 compare_result = gen_reg_rtx (comp_mode);
11675 /* E500 FP compare instructions on the GPRs. Yuck! */
11676 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11677 && rs6000_compare_fp_p)
11679 rtx cmp, or_result, compare_result2;
11680 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11682 if (op_mode == VOIDmode)
11683 op_mode = GET_MODE (rs6000_compare_op1);
11685 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11686 This explains the following mess. */
11690 case EQ: case UNEQ: case NE: case LTGT:
11694 cmp = flag_unsafe_math_optimizations
11695 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11696 rs6000_compare_op1)
11697 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11698 rs6000_compare_op1);
11702 cmp = flag_unsafe_math_optimizations
11703 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11704 rs6000_compare_op1)
11705 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11706 rs6000_compare_op1);
11710 cmp = flag_unsafe_math_optimizations
11711 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11712 rs6000_compare_op1)
11713 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11714 rs6000_compare_op1);
11718 gcc_unreachable ();
11722 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11726 cmp = flag_unsafe_math_optimizations
11727 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11728 rs6000_compare_op1)
11729 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11730 rs6000_compare_op1);
11734 cmp = flag_unsafe_math_optimizations
11735 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11736 rs6000_compare_op1)
11737 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11738 rs6000_compare_op1);
11742 cmp = flag_unsafe_math_optimizations
11743 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11744 rs6000_compare_op1)
11745 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11746 rs6000_compare_op1);
11750 gcc_unreachable ();
11754 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11758 cmp = flag_unsafe_math_optimizations
11759 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11760 rs6000_compare_op1)
11761 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11762 rs6000_compare_op1);
11766 cmp = flag_unsafe_math_optimizations
11767 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11768 rs6000_compare_op1)
11769 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11770 rs6000_compare_op1);
11774 cmp = flag_unsafe_math_optimizations
11775 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11776 rs6000_compare_op1)
11777 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11778 rs6000_compare_op1);
11782 gcc_unreachable ();
11786 gcc_unreachable ();
11789 /* Synthesize LE and GE from LT/GT || EQ. */
11790 if (code == LE || code == GE || code == LEU || code == GEU)
11796 case LE: code = LT; break;
11797 case GE: code = GT; break;
11798 case LEU: code = LT; break;
11799 case GEU: code = GT; break;
11800 default: gcc_unreachable ();
11803 compare_result2 = gen_reg_rtx (CCFPmode);
11809 cmp = flag_unsafe_math_optimizations
11810 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11811 rs6000_compare_op1)
11812 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11813 rs6000_compare_op1);
11817 cmp = flag_unsafe_math_optimizations
11818 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11819 rs6000_compare_op1)
11820 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11821 rs6000_compare_op1);
11825 cmp = flag_unsafe_math_optimizations
11826 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11827 rs6000_compare_op1)
11828 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11829 rs6000_compare_op1);
11833 gcc_unreachable ();
11837 /* OR them together. */
11838 or_result = gen_reg_rtx (CCFPmode);
11839 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11841 compare_result = or_result;
11846 if (code == NE || code == LTGT)
11856 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11857 CLOBBERs to match cmptf_internal2 pattern. */
11858 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11859 && GET_MODE (rs6000_compare_op0) == TFmode
11860 && !TARGET_IEEEQUAD
11861 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11862 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11864 gen_rtx_SET (VOIDmode,
11866 gen_rtx_COMPARE (comp_mode,
11867 rs6000_compare_op0,
11868 rs6000_compare_op1)),
11869 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11870 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11871 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11872 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11873 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11874 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11875 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11876 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11877 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11878 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11880 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11881 comp_mode = CCEQmode;
11882 compare_result = gen_reg_rtx (CCEQmode);
11884 emit_insn (gen_stack_protect_testdi (compare_result,
11885 rs6000_compare_op0, op1));
11887 emit_insn (gen_stack_protect_testsi (compare_result,
11888 rs6000_compare_op0, op1));
11891 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11892 gen_rtx_COMPARE (comp_mode,
11893 rs6000_compare_op0,
11894 rs6000_compare_op1)));
11897 /* Some kinds of FP comparisons need an OR operation;
11898 under flag_finite_math_only we don't bother. */
11899 if (rs6000_compare_fp_p
11900 && !flag_finite_math_only
11901 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11902 && (code == LE || code == GE
11903 || code == UNEQ || code == LTGT
11904 || code == UNGT || code == UNLT))
11906 enum rtx_code or1, or2;
11907 rtx or1_rtx, or2_rtx, compare2_rtx;
11908 rtx or_result = gen_reg_rtx (CCEQmode);
11912 case LE: or1 = LT; or2 = EQ; break;
11913 case GE: or1 = GT; or2 = EQ; break;
11914 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11915 case LTGT: or1 = LT; or2 = GT; break;
11916 case UNGT: or1 = UNORDERED; or2 = GT; break;
11917 case UNLT: or1 = UNORDERED; or2 = LT; break;
11918 default: gcc_unreachable ();
11920 validate_condition_mode (or1, comp_mode);
11921 validate_condition_mode (or2, comp_mode);
11922 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11923 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11924 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11925 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11927 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11929 compare_result = or_result;
11933 validate_condition_mode (code, GET_MODE (compare_result));
11935 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11939 /* Emit the RTL for an sCOND pattern. */
11942 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11945 enum machine_mode op_mode;
11946 enum rtx_code cond_code;
11948 condition_rtx = rs6000_generate_compare (code);
11949 cond_code = GET_CODE (condition_rtx);
11951 if (rs6000_compare_fp_p
11952 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11956 PUT_MODE (condition_rtx, SImode);
11957 t = XEXP (condition_rtx, 0);
11959 gcc_assert (cond_code == NE || cond_code == EQ);
11961 if (cond_code == NE)
11962 emit_insn (gen_e500_flip_gt_bit (t, t));
11964 emit_insn (gen_move_from_CR_gt_bit (result, t));
11968 if (cond_code == NE
11969 || cond_code == GE || cond_code == LE
11970 || cond_code == GEU || cond_code == LEU
11971 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11973 rtx not_result = gen_reg_rtx (CCEQmode);
11974 rtx not_op, rev_cond_rtx;
11975 enum machine_mode cc_mode;
11977 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11979 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11980 SImode, XEXP (condition_rtx, 0), const0_rtx);
11981 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11982 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11983 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11986 op_mode = GET_MODE (rs6000_compare_op0);
11987 if (op_mode == VOIDmode)
11988 op_mode = GET_MODE (rs6000_compare_op1);
11990 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11992 PUT_MODE (condition_rtx, DImode);
11993 convert_move (result, condition_rtx, 0);
11997 PUT_MODE (condition_rtx, SImode);
11998 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12002 /* Emit a branch of kind CODE to location LOC. */
12005 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12007 rtx condition_rtx, loc_ref;
12009 condition_rtx = rs6000_generate_compare (code);
12010 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12011 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12012 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12013 loc_ref, pc_rtx)));
12016 /* Return the string to output a conditional branch to LABEL, which is
12017 the operand number of the label, or -1 if the branch is really a
12018 conditional return.
12020 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12021 condition code register and its mode specifies what kind of
12022 comparison we made.
12024 REVERSED is nonzero if we should reverse the sense of the comparison.
12026 INSN is the insn. */
12029 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12031 static char string[64];
12032 enum rtx_code code = GET_CODE (op);
12033 rtx cc_reg = XEXP (op, 0);
12034 enum machine_mode mode = GET_MODE (cc_reg);
12035 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12036 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12037 int really_reversed = reversed ^ need_longbranch;
12043 validate_condition_mode (code, mode);
12045 /* Work out which way this really branches. We could use
12046 reverse_condition_maybe_unordered here always but this
12047 makes the resulting assembler clearer. */
12048 if (really_reversed)
12050 /* Reversal of FP compares takes care -- an ordered compare
12051 becomes an unordered compare and vice versa. */
12052 if (mode == CCFPmode)
12053 code = reverse_condition_maybe_unordered (code);
12055 code = reverse_condition (code);
12058 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12060 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12065 /* Opposite of GT. */
12074 gcc_unreachable ();
12080 /* Not all of these are actually distinct opcodes, but
12081 we distinguish them for clarity of the resulting assembler. */
12082 case NE: case LTGT:
12083 ccode = "ne"; break;
12084 case EQ: case UNEQ:
12085 ccode = "eq"; break;
12087 ccode = "ge"; break;
12088 case GT: case GTU: case UNGT:
12089 ccode = "gt"; break;
12091 ccode = "le"; break;
12092 case LT: case LTU: case UNLT:
12093 ccode = "lt"; break;
12094 case UNORDERED: ccode = "un"; break;
12095 case ORDERED: ccode = "nu"; break;
12096 case UNGE: ccode = "nl"; break;
12097 case UNLE: ccode = "ng"; break;
12099 gcc_unreachable ();
12102 /* Maybe we have a guess as to how likely the branch is.
12103 The old mnemonics don't have a way to specify this information. */
12105 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12106 if (note != NULL_RTX)
12108 /* PROB is the difference from 50%. */
12109 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12111 /* Only hint for highly probable/improbable branches on newer
12112 cpus as static prediction overrides processor dynamic
12113 prediction. For older cpus we may as well always hint, but
12114 assume not taken for branches that are very close to 50% as a
12115 mispredicted taken branch is more expensive than a
12116 mispredicted not-taken branch. */
12117 if (rs6000_always_hint
12118 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12119 && br_prob_note_reliable_p (note)))
12121 if (abs (prob) > REG_BR_PROB_BASE / 20
12122 && ((prob > 0) ^ need_longbranch))
12130 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12132 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12134 /* We need to escape any '%' characters in the reg_names string.
12135 Assume they'd only be the first character.... */
12136 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12138 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12142 /* If the branch distance was too far, we may have to use an
12143 unconditional branch to go the distance. */
12144 if (need_longbranch)
12145 s += sprintf (s, ",$+8\n\tb %s", label);
12147 s += sprintf (s, ",%s", label);
12153 /* Return the string to flip the GT bit on a CR. */
12155 output_e500_flip_gt_bit (rtx dst, rtx src)
12157 static char string[64];
12160 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12161 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12164 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12165 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12167 sprintf (string, "crnot %d,%d", a, b);
12171 /* Return insn index for the vector compare instruction for given CODE,
12172 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12176 get_vec_cmp_insn (enum rtx_code code,
12177 enum machine_mode dest_mode,
12178 enum machine_mode op_mode)
12180 if (!TARGET_ALTIVEC)
12181 return INSN_NOT_AVAILABLE;
12186 if (dest_mode == V16QImode && op_mode == V16QImode)
12187 return UNSPEC_VCMPEQUB;
12188 if (dest_mode == V8HImode && op_mode == V8HImode)
12189 return UNSPEC_VCMPEQUH;
12190 if (dest_mode == V4SImode && op_mode == V4SImode)
12191 return UNSPEC_VCMPEQUW;
12192 if (dest_mode == V4SImode && op_mode == V4SFmode)
12193 return UNSPEC_VCMPEQFP;
12196 if (dest_mode == V4SImode && op_mode == V4SFmode)
12197 return UNSPEC_VCMPGEFP;
12199 if (dest_mode == V16QImode && op_mode == V16QImode)
12200 return UNSPEC_VCMPGTSB;
12201 if (dest_mode == V8HImode && op_mode == V8HImode)
12202 return UNSPEC_VCMPGTSH;
12203 if (dest_mode == V4SImode && op_mode == V4SImode)
12204 return UNSPEC_VCMPGTSW;
12205 if (dest_mode == V4SImode && op_mode == V4SFmode)
12206 return UNSPEC_VCMPGTFP;
12209 if (dest_mode == V16QImode && op_mode == V16QImode)
12210 return UNSPEC_VCMPGTUB;
12211 if (dest_mode == V8HImode && op_mode == V8HImode)
12212 return UNSPEC_VCMPGTUH;
12213 if (dest_mode == V4SImode && op_mode == V4SImode)
12214 return UNSPEC_VCMPGTUW;
12219 return INSN_NOT_AVAILABLE;
12222 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12223 DMODE is expected destination mode. This is a recursive function. */
12226 rs6000_emit_vector_compare (enum rtx_code rcode,
12228 enum machine_mode dmode)
12232 enum machine_mode dest_mode;
12233 enum machine_mode op_mode = GET_MODE (op1);
12235 gcc_assert (TARGET_ALTIVEC);
12236 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12238 /* Floating point vector compare instructions uses destination V4SImode.
12239 Move destination to appropriate mode later. */
12240 if (dmode == V4SFmode)
12241 dest_mode = V4SImode;
12245 mask = gen_reg_rtx (dest_mode);
12246 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12248 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12250 bool swap_operands = false;
12251 bool try_again = false;
12256 swap_operands = true;
12261 swap_operands = true;
12269 /* Invert condition and try again.
12270 e.g., A != B becomes ~(A==B). */
12272 enum rtx_code rev_code;
12273 enum insn_code nor_code;
12276 rev_code = reverse_condition_maybe_unordered (rcode);
12277 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12280 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
12281 gcc_assert (nor_code != CODE_FOR_nothing);
12282 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12284 if (dmode != dest_mode)
12286 rtx temp = gen_reg_rtx (dest_mode);
12287 convert_move (temp, mask, 0);
12297 /* Try GT/GTU/LT/LTU OR EQ */
12300 enum insn_code ior_code;
12301 enum rtx_code new_code;
12322 gcc_unreachable ();
12325 c_rtx = rs6000_emit_vector_compare (new_code,
12326 op0, op1, dest_mode);
12327 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12330 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
12331 gcc_assert (ior_code != CODE_FOR_nothing);
12332 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12333 if (dmode != dest_mode)
12335 rtx temp = gen_reg_rtx (dest_mode);
12336 convert_move (temp, mask, 0);
12343 gcc_unreachable ();
12348 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12349 /* You only get two chances. */
12350 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12362 emit_insn (gen_rtx_SET (VOIDmode, mask,
12363 gen_rtx_UNSPEC (dest_mode,
12364 gen_rtvec (2, op0, op1),
12366 if (dmode != dest_mode)
12368 rtx temp = gen_reg_rtx (dest_mode);
12369 convert_move (temp, mask, 0);
12375 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12376 valid insn doesn exist for given mode. */
12379 get_vsel_insn (enum machine_mode mode)
12384 return UNSPEC_VSEL4SI;
12387 return UNSPEC_VSEL4SF;
12390 return UNSPEC_VSEL8HI;
12393 return UNSPEC_VSEL16QI;
12396 return INSN_NOT_AVAILABLE;
12399 return INSN_NOT_AVAILABLE;
12402 /* Emit vector select insn where DEST is destination using
12403 operands OP1, OP2 and MASK. */
12406 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12409 enum machine_mode dest_mode = GET_MODE (dest);
12410 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12412 temp = gen_reg_rtx (dest_mode);
12414 /* For each vector element, select op1 when mask is 1 otherwise
12416 t = gen_rtx_SET (VOIDmode, temp,
12417 gen_rtx_UNSPEC (dest_mode,
12418 gen_rtvec (3, op2, op1, mask),
12421 emit_move_insn (dest, temp);
12425 /* Emit vector conditional expression.
12426 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12427 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12430 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12431 rtx cond, rtx cc_op0, rtx cc_op1)
12433 enum machine_mode dest_mode = GET_MODE (dest);
12434 enum rtx_code rcode = GET_CODE (cond);
12437 if (!TARGET_ALTIVEC)
12440 /* Get the vector mask for the given relational operations. */
12441 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12443 rs6000_emit_vector_select (dest, op1, op2, mask);
12448 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12449 operands of the last comparison is nonzero/true, FALSE_COND if it
12450 is zero/false. Return 0 if the hardware has no such operation. */
12453 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12455 enum rtx_code code = GET_CODE (op);
12456 rtx op0 = rs6000_compare_op0;
12457 rtx op1 = rs6000_compare_op1;
12458 REAL_VALUE_TYPE c1;
12459 enum machine_mode compare_mode = GET_MODE (op0);
12460 enum machine_mode result_mode = GET_MODE (dest);
12462 bool is_against_zero;
12464 /* These modes should always match. */
12465 if (GET_MODE (op1) != compare_mode
12466 /* In the isel case however, we can use a compare immediate, so
12467 op1 may be a small constant. */
12468 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12470 if (GET_MODE (true_cond) != result_mode)
12472 if (GET_MODE (false_cond) != result_mode)
12475 /* First, work out if the hardware can do this at all, or
12476 if it's too slow.... */
12477 if (! rs6000_compare_fp_p)
12480 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12483 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12484 && SCALAR_FLOAT_MODE_P (compare_mode))
12487 is_against_zero = op1 == CONST0_RTX (compare_mode);
12489 /* A floating-point subtract might overflow, underflow, or produce
12490 an inexact result, thus changing the floating-point flags, so it
12491 can't be generated if we care about that. It's safe if one side
12492 of the construct is zero, since then no subtract will be
12494 if (SCALAR_FLOAT_MODE_P (compare_mode)
12495 && flag_trapping_math && ! is_against_zero)
12498 /* Eliminate half of the comparisons by switching operands, this
12499 makes the remaining code simpler. */
12500 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12501 || code == LTGT || code == LT || code == UNLE)
12503 code = reverse_condition_maybe_unordered (code);
12505 true_cond = false_cond;
12509 /* UNEQ and LTGT take four instructions for a comparison with zero,
12510 it'll probably be faster to use a branch here too. */
12511 if (code == UNEQ && HONOR_NANS (compare_mode))
12514 if (GET_CODE (op1) == CONST_DOUBLE)
12515 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12517 /* We're going to try to implement comparisons by performing
12518 a subtract, then comparing against zero. Unfortunately,
12519 Inf - Inf is NaN which is not zero, and so if we don't
12520 know that the operand is finite and the comparison
12521 would treat EQ different to UNORDERED, we can't do it. */
12522 if (HONOR_INFINITIES (compare_mode)
12523 && code != GT && code != UNGE
12524 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12525 /* Constructs of the form (a OP b ? a : b) are safe. */
12526 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12527 || (! rtx_equal_p (op0, true_cond)
12528 && ! rtx_equal_p (op1, true_cond))))
12531 /* At this point we know we can use fsel. */
12533 /* Reduce the comparison to a comparison against zero. */
12534 if (! is_against_zero)
12536 temp = gen_reg_rtx (compare_mode);
12537 emit_insn (gen_rtx_SET (VOIDmode, temp,
12538 gen_rtx_MINUS (compare_mode, op0, op1)));
12540 op1 = CONST0_RTX (compare_mode);
12543 /* If we don't care about NaNs we can reduce some of the comparisons
12544 down to faster ones. */
12545 if (! HONOR_NANS (compare_mode))
12551 true_cond = false_cond;
12564 /* Now, reduce everything down to a GE. */
12571 temp = gen_reg_rtx (compare_mode);
12572 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12577 temp = gen_reg_rtx (compare_mode);
12578 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12583 temp = gen_reg_rtx (compare_mode);
12584 emit_insn (gen_rtx_SET (VOIDmode, temp,
12585 gen_rtx_NEG (compare_mode,
12586 gen_rtx_ABS (compare_mode, op0))));
12591 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12592 temp = gen_reg_rtx (result_mode);
12593 emit_insn (gen_rtx_SET (VOIDmode, temp,
12594 gen_rtx_IF_THEN_ELSE (result_mode,
12595 gen_rtx_GE (VOIDmode,
12597 true_cond, false_cond)));
12598 false_cond = true_cond;
12601 temp = gen_reg_rtx (compare_mode);
12602 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12607 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12608 temp = gen_reg_rtx (result_mode);
12609 emit_insn (gen_rtx_SET (VOIDmode, temp,
12610 gen_rtx_IF_THEN_ELSE (result_mode,
12611 gen_rtx_GE (VOIDmode,
12613 true_cond, false_cond)));
12614 true_cond = false_cond;
12617 temp = gen_reg_rtx (compare_mode);
12618 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12623 gcc_unreachable ();
12626 emit_insn (gen_rtx_SET (VOIDmode, dest,
12627 gen_rtx_IF_THEN_ELSE (result_mode,
12628 gen_rtx_GE (VOIDmode,
12630 true_cond, false_cond)));
12634 /* Same as above, but for ints (isel). */
12637 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12639 rtx condition_rtx, cr;
12641 /* All isel implementations thus far are 32-bits. */
12642 if (GET_MODE (rs6000_compare_op0) != SImode)
12645 /* We still have to do the compare, because isel doesn't do a
12646 compare, it just looks at the CRx bits set by a previous compare
12648 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12649 cr = XEXP (condition_rtx, 0);
12651 if (GET_MODE (cr) == CCmode)
12652 emit_insn (gen_isel_signed (dest, condition_rtx,
12653 true_cond, false_cond, cr));
12655 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12656 true_cond, false_cond, cr));
12662 output_isel (rtx *operands)
12664 enum rtx_code code;
12666 code = GET_CODE (operands[1]);
12667 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12669 PUT_CODE (operands[1], reverse_condition (code));
12670 return "isel %0,%3,%2,%j1";
12673 return "isel %0,%2,%3,%j1";
12677 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12679 enum machine_mode mode = GET_MODE (op0);
12683 if (code == SMAX || code == SMIN)
12688 if (code == SMAX || code == UMAX)
12689 target = emit_conditional_move (dest, c, op0, op1, mode,
12690 op0, op1, mode, 0);
12692 target = emit_conditional_move (dest, c, op0, op1, mode,
12693 op1, op0, mode, 0);
12694 gcc_assert (target);
12695 if (target != dest)
12696 emit_move_insn (dest, target);
12699 /* Emit instructions to perform a load-reserved/store-conditional operation.
12700 The operation performed is an atomic
12701 (set M (CODE:MODE M OP))
12702 If not NULL, BEFORE is atomically set to M before the operation, and
12703 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12704 If SYNC_P then a memory barrier is emitted before the operation.
12705 Either OP or M may be wrapped in a NOT operation. */
12708 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12709 rtx m, rtx op, rtx before_param, rtx after_param,
12712 enum machine_mode used_mode;
12713 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12716 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12717 rtx shift = NULL_RTX;
12720 emit_insn (gen_memory_barrier ());
12722 if (GET_CODE (m) == NOT)
12723 used_m = XEXP (m, 0);
12727 /* If this is smaller than SImode, we'll have to use SImode with
12729 if (mode == QImode || mode == HImode)
12733 if (MEM_ALIGN (used_m) >= 32)
12736 if (BYTES_BIG_ENDIAN)
12737 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12739 shift = GEN_INT (ishift);
12743 rtx addrSI, aligned_addr;
12744 int shift_mask = mode == QImode ? 0x18 : 0x10;
12746 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12747 XEXP (used_m, 0)));
12748 shift = gen_reg_rtx (SImode);
12750 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12751 GEN_INT (shift_mask)));
12752 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12754 aligned_addr = expand_binop (Pmode, and_optab,
12756 GEN_INT (-4), NULL_RTX,
12757 1, OPTAB_LIB_WIDEN);
12758 used_m = change_address (used_m, SImode, aligned_addr);
12759 set_mem_align (used_m, 32);
12760 /* It's safe to keep the old alias set of USED_M, because
12761 the operation is atomic and only affects the original
12763 if (GET_CODE (m) == NOT)
12764 m = gen_rtx_NOT (SImode, used_m);
12769 if (GET_CODE (op) == NOT)
12771 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12772 oldop = gen_rtx_NOT (SImode, oldop);
12775 oldop = lowpart_subreg (SImode, op, mode);
12781 newop = expand_binop (SImode, and_optab,
12782 oldop, GEN_INT (imask), NULL_RTX,
12783 1, OPTAB_LIB_WIDEN);
12784 emit_insn (gen_ashlsi3 (newop, newop, shift));
12788 newop = expand_binop (SImode, ior_optab,
12789 oldop, GEN_INT (~imask), NULL_RTX,
12790 1, OPTAB_LIB_WIDEN);
12791 emit_insn (gen_rotlsi3 (newop, newop, shift));
12799 newop = expand_binop (SImode, and_optab,
12800 oldop, GEN_INT (imask), NULL_RTX,
12801 1, OPTAB_LIB_WIDEN);
12802 emit_insn (gen_ashlsi3 (newop, newop, shift));
12804 mask = gen_reg_rtx (SImode);
12805 emit_move_insn (mask, GEN_INT (imask));
12806 emit_insn (gen_ashlsi3 (mask, mask, shift));
12809 newop = gen_rtx_PLUS (SImode, m, newop);
12811 newop = gen_rtx_MINUS (SImode, m, newop);
12812 newop = gen_rtx_AND (SImode, newop, mask);
12813 newop = gen_rtx_IOR (SImode, newop,
12814 gen_rtx_AND (SImode,
12815 gen_rtx_NOT (SImode, mask),
12821 gcc_unreachable ();
12824 if (GET_CODE (m) == NOT)
12828 mask = gen_reg_rtx (SImode);
12829 emit_move_insn (mask, GEN_INT (imask));
12830 emit_insn (gen_ashlsi3 (mask, mask, shift));
12832 xorm = gen_rtx_XOR (SImode, used_m, mask);
12833 /* Depending on the value of 'op', the XOR or the operation might
12834 be able to be simplified away. */
12835 newop = simplify_gen_binary (code, SImode, xorm, newop);
12838 used_mode = SImode;
12839 before = gen_reg_rtx (used_mode);
12840 after = gen_reg_rtx (used_mode);
12845 before = before_param;
12846 after = after_param;
12848 if (before == NULL_RTX)
12849 before = gen_reg_rtx (used_mode);
12850 if (after == NULL_RTX)
12851 after = gen_reg_rtx (used_mode);
12854 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12855 && used_mode != mode)
12856 the_op = op; /* Computed above. */
12857 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12858 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12860 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12862 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12863 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12864 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12865 gen_rtx_UNSPEC (used_mode,
12866 gen_rtvec (1, the_op),
12868 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12870 if ((code == PLUS || code == MINUS) && used_mode != mode)
12871 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12872 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12874 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12875 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12877 /* Shift and mask the return values properly. */
12878 if (used_mode != mode && before_param)
12880 emit_insn (gen_lshrsi3 (before, before, shift));
12881 convert_move (before_param, before, 1);
12884 if (used_mode != mode && after_param)
12886 emit_insn (gen_lshrsi3 (after, after, shift));
12887 convert_move (after_param, after, 1);
12890 /* The previous sequence will end with a branch that's dependent on
12891 the conditional store, so placing an isync will ensure that no
12892 other instructions (especially, no load or store instructions)
12893 can start before the atomic operation completes. */
12895 emit_insn (gen_isync ());
12898 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12899 COND is true. Mark the jump as unlikely to be taken. */
12902 emit_unlikely_jump (rtx cond, rtx label)
12904 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12907 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12908 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12909 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12912 /* A subroutine of the atomic operation splitters. Emit a load-locked
12913 instruction in MODE. */
12916 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12918 rtx (*fn) (rtx, rtx) = NULL;
12919 if (mode == SImode)
12920 fn = gen_load_locked_si;
12921 else if (mode == DImode)
12922 fn = gen_load_locked_di;
12923 emit_insn (fn (reg, mem));
12926 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12927 instruction in MODE. */
12930 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12932 rtx (*fn) (rtx, rtx, rtx) = NULL;
12933 if (mode == SImode)
12934 fn = gen_store_conditional_si;
12935 else if (mode == DImode)
12936 fn = gen_store_conditional_di;
12938 /* Emit sync before stwcx. to address PPC405 Erratum. */
12939 if (PPC405_ERRATUM77)
12940 emit_insn (gen_memory_barrier ());
12942 emit_insn (fn (res, mem, val));
12945 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12946 to perform. MEM is the memory on which to operate. VAL is the second
12947 operand of the binary operator. BEFORE and AFTER are optional locations to
12948 return the value of MEM either before of after the operation. SCRATCH is
12949 a scratch register. */
12952 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12953 rtx before, rtx after, rtx scratch)
12955 enum machine_mode mode = GET_MODE (mem);
12956 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12958 emit_insn (gen_memory_barrier ());
12960 label = gen_label_rtx ();
12961 emit_label (label);
12962 label = gen_rtx_LABEL_REF (VOIDmode, label);
12964 if (before == NULL_RTX)
12966 emit_load_locked (mode, before, mem);
12969 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12970 else if (code == AND)
12971 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12973 x = gen_rtx_fmt_ee (code, mode, before, val);
12975 if (after != NULL_RTX)
12976 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12977 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12979 emit_store_conditional (mode, cond, mem, scratch);
12981 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12982 emit_unlikely_jump (x, label);
12984 emit_insn (gen_isync ());
12987 /* Expand an atomic compare and swap operation. MEM is the memory on which
12988 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12989 value to be stored. SCRATCH is a scratch GPR. */
12992 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12995 enum machine_mode mode = GET_MODE (mem);
12996 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12998 emit_insn (gen_memory_barrier ());
13000 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13001 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13002 emit_label (XEXP (label1, 0));
13004 emit_load_locked (mode, retval, mem);
13006 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13007 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13009 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13010 emit_unlikely_jump (x, label2);
13012 emit_move_insn (scratch, newval);
13013 emit_store_conditional (mode, cond, mem, scratch);
13015 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13016 emit_unlikely_jump (x, label1);
13018 emit_insn (gen_isync ());
13019 emit_label (XEXP (label2, 0));
13022 /* Expand an atomic test and set operation. MEM is the memory on which
13023 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13026 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13028 enum machine_mode mode = GET_MODE (mem);
13029 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13031 emit_insn (gen_memory_barrier ());
13033 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13034 emit_label (XEXP (label, 0));
13036 emit_load_locked (mode, retval, mem);
13037 emit_move_insn (scratch, val);
13038 emit_store_conditional (mode, cond, mem, scratch);
13040 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13041 emit_unlikely_jump (x, label);
13043 emit_insn (gen_isync ());
13047 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13049 enum machine_mode mode = GET_MODE (mem);
13050 rtx addrSI, align, wdst, shift, mask;
13051 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13052 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13054 /* Shift amount for subword relative to aligned word. */
13055 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13056 shift = gen_reg_rtx (SImode);
13057 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13058 GEN_INT (shift_mask)));
13059 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13061 /* Shift and mask old value into position within word. */
13062 oldval = convert_modes (SImode, mode, oldval, 1);
13063 oldval = expand_binop (SImode, and_optab,
13064 oldval, GEN_INT (imask), NULL_RTX,
13065 1, OPTAB_LIB_WIDEN);
13066 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13068 /* Shift and mask new value into position within word. */
13069 newval = convert_modes (SImode, mode, newval, 1);
13070 newval = expand_binop (SImode, and_optab,
13071 newval, GEN_INT (imask), NULL_RTX,
13072 1, OPTAB_LIB_WIDEN);
13073 emit_insn (gen_ashlsi3 (newval, newval, shift));
13075 /* Mask for insertion. */
13076 mask = gen_reg_rtx (SImode);
13077 emit_move_insn (mask, GEN_INT (imask));
13078 emit_insn (gen_ashlsi3 (mask, mask, shift));
13080 /* Address of aligned word containing subword. */
13081 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13082 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13083 mem = change_address (mem, SImode, align);
13084 set_mem_align (mem, 32);
13085 MEM_VOLATILE_P (mem) = 1;
13087 wdst = gen_reg_rtx (SImode);
13088 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13089 oldval, newval, mem));
13091 emit_move_insn (dst, gen_lowpart (mode, wdst));
13095 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13096 rtx oldval, rtx newval, rtx mem,
13099 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13101 emit_insn (gen_memory_barrier ());
13102 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13103 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13104 emit_label (XEXP (label1, 0));
13106 emit_load_locked (SImode, scratch, mem);
13108 /* Mask subword within loaded value for comparison with oldval.
13109 Use UNSPEC_AND to avoid clobber.*/
13110 emit_insn (gen_rtx_SET (SImode, dest,
13111 gen_rtx_UNSPEC (SImode,
13112 gen_rtvec (2, scratch, mask),
13115 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13116 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13118 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13119 emit_unlikely_jump (x, label2);
13121 /* Clear subword within loaded value for insertion of new value. */
13122 emit_insn (gen_rtx_SET (SImode, scratch,
13123 gen_rtx_AND (SImode,
13124 gen_rtx_NOT (SImode, mask), scratch)));
13125 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13126 emit_store_conditional (SImode, cond, mem, scratch);
13128 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13129 emit_unlikely_jump (x, label1);
13131 emit_insn (gen_isync ());
13132 emit_label (XEXP (label2, 0));
13136 /* Emit instructions to move SRC to DST. Called by splitters for
13137 multi-register moves. It will emit at most one instruction for
13138 each register that is accessed; that is, it won't emit li/lis pairs
13139 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13143 rs6000_split_multireg_move (rtx dst, rtx src)
13145 /* The register number of the first register being moved. */
13147 /* The mode that is to be moved. */
13148 enum machine_mode mode;
13149 /* The mode that the move is being done in, and its size. */
13150 enum machine_mode reg_mode;
13152 /* The number of registers that will be moved. */
13155 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13156 mode = GET_MODE (dst);
13157 nregs = hard_regno_nregs[reg][mode];
13158 if (FP_REGNO_P (reg))
13159 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13160 else if (ALTIVEC_REGNO_P (reg))
13161 reg_mode = V16QImode;
13162 else if (TARGET_E500_DOUBLE && mode == TFmode)
13165 reg_mode = word_mode;
13166 reg_mode_size = GET_MODE_SIZE (reg_mode);
13168 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13170 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13172 /* Move register range backwards, if we might have destructive
13175 for (i = nregs - 1; i >= 0; i--)
13176 emit_insn (gen_rtx_SET (VOIDmode,
13177 simplify_gen_subreg (reg_mode, dst, mode,
13178 i * reg_mode_size),
13179 simplify_gen_subreg (reg_mode, src, mode,
13180 i * reg_mode_size)));
13186 bool used_update = false;
13188 if (MEM_P (src) && INT_REGNO_P (reg))
13192 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13193 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13196 breg = XEXP (XEXP (src, 0), 0);
13197 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13198 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13199 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13200 emit_insn (TARGET_32BIT
13201 ? gen_addsi3 (breg, breg, delta_rtx)
13202 : gen_adddi3 (breg, breg, delta_rtx));
13203 src = replace_equiv_address (src, breg);
13205 else if (! rs6000_offsettable_memref_p (src))
13208 basereg = gen_rtx_REG (Pmode, reg);
13209 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13210 src = replace_equiv_address (src, basereg);
13213 breg = XEXP (src, 0);
13214 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13215 breg = XEXP (breg, 0);
13217 /* If the base register we are using to address memory is
13218 also a destination reg, then change that register last. */
13220 && REGNO (breg) >= REGNO (dst)
13221 && REGNO (breg) < REGNO (dst) + nregs)
13222 j = REGNO (breg) - REGNO (dst);
13225 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13229 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13230 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13233 breg = XEXP (XEXP (dst, 0), 0);
13234 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13235 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13236 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13238 /* We have to update the breg before doing the store.
13239 Use store with update, if available. */
13243 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13244 emit_insn (TARGET_32BIT
13245 ? (TARGET_POWERPC64
13246 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13247 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13248 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13249 used_update = true;
13252 emit_insn (TARGET_32BIT
13253 ? gen_addsi3 (breg, breg, delta_rtx)
13254 : gen_adddi3 (breg, breg, delta_rtx));
13255 dst = replace_equiv_address (dst, breg);
13258 gcc_assert (rs6000_offsettable_memref_p (dst));
13261 for (i = 0; i < nregs; i++)
13263 /* Calculate index to next subword. */
13268 /* If compiler already emitted move of first word by
13269 store with update, no need to do anything. */
13270 if (j == 0 && used_update)
13273 emit_insn (gen_rtx_SET (VOIDmode,
13274 simplify_gen_subreg (reg_mode, dst, mode,
13275 j * reg_mode_size),
13276 simplify_gen_subreg (reg_mode, src, mode,
13277 j * reg_mode_size)));
13283 /* This page contains routines that are used to determine what the
13284 function prologue and epilogue code will do and write them out. */
13286 /* Return the first fixed-point register that is required to be
13287 saved. 32 if none. */
13290 first_reg_to_save (void)
13294 /* Find lowest numbered live register. */
13295 for (first_reg = 13; first_reg <= 31; first_reg++)
13296 if (df_regs_ever_live_p (first_reg)
13297 && (! call_used_regs[first_reg]
13298 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13299 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13300 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13301 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13306 && current_function_uses_pic_offset_table
13307 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13308 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13314 /* Similar, for FP regs. */
13317 first_fp_reg_to_save (void)
13321 /* Find lowest numbered live register. */
13322 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13323 if (df_regs_ever_live_p (first_reg))
13329 /* Similar, for AltiVec regs. */
13332 first_altivec_reg_to_save (void)
13336 /* Stack frame remains as is unless we are in AltiVec ABI. */
13337 if (! TARGET_ALTIVEC_ABI)
13338 return LAST_ALTIVEC_REGNO + 1;
13340 /* On Darwin, the unwind routines are compiled without
13341 TARGET_ALTIVEC, and use save_world to save/restore the
13342 altivec registers when necessary. */
13343 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13344 && ! TARGET_ALTIVEC)
13345 return FIRST_ALTIVEC_REGNO + 20;
13347 /* Find lowest numbered live register. */
13348 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13349 if (df_regs_ever_live_p (i))
13355 /* Return a 32-bit mask of the AltiVec registers we need to set in
13356 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13357 the 32-bit word is 0. */
13359 static unsigned int
13360 compute_vrsave_mask (void)
13362 unsigned int i, mask = 0;
13364 /* On Darwin, the unwind routines are compiled without
13365 TARGET_ALTIVEC, and use save_world to save/restore the
13366 call-saved altivec registers when necessary. */
13367 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13368 && ! TARGET_ALTIVEC)
13371 /* First, find out if we use _any_ altivec registers. */
13372 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13373 if (df_regs_ever_live_p (i))
13374 mask |= ALTIVEC_REG_BIT (i);
13379 /* Next, remove the argument registers from the set. These must
13380 be in the VRSAVE mask set by the caller, so we don't need to add
13381 them in again. More importantly, the mask we compute here is
13382 used to generate CLOBBERs in the set_vrsave insn, and we do not
13383 wish the argument registers to die. */
13384 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13385 mask &= ~ALTIVEC_REG_BIT (i);
13387 /* Similarly, remove the return value from the set. */
13390 diddle_return_value (is_altivec_return_reg, &yes);
13392 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13398 /* For a very restricted set of circumstances, we can cut down the
13399 size of prologues/epilogues by calling our own save/restore-the-world
13403 compute_save_world_info (rs6000_stack_t *info_ptr)
13405 info_ptr->world_save_p = 1;
13406 info_ptr->world_save_p
13407 = (WORLD_SAVE_P (info_ptr)
13408 && DEFAULT_ABI == ABI_DARWIN
13409 && ! (current_function_calls_setjmp && flag_exceptions)
13410 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13411 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13412 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13413 && info_ptr->cr_save_p);
13415 /* This will not work in conjunction with sibcalls. Make sure there
13416 are none. (This check is expensive, but seldom executed.) */
13417 if (WORLD_SAVE_P (info_ptr))
13420 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13421 if ( GET_CODE (insn) == CALL_INSN
13422 && SIBLING_CALL_P (insn))
13424 info_ptr->world_save_p = 0;
13429 if (WORLD_SAVE_P (info_ptr))
13431 /* Even if we're not touching VRsave, make sure there's room on the
13432 stack for it, if it looks like we're calling SAVE_WORLD, which
13433 will attempt to save it. */
13434 info_ptr->vrsave_size = 4;
13436 /* "Save" the VRsave register too if we're saving the world. */
13437 if (info_ptr->vrsave_mask == 0)
13438 info_ptr->vrsave_mask = compute_vrsave_mask ();
13440 /* Because the Darwin register save/restore routines only handle
13441 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13443 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13444 && (info_ptr->first_altivec_reg_save
13445 >= FIRST_SAVED_ALTIVEC_REGNO));
13452 is_altivec_return_reg (rtx reg, void *xyes)
13454 bool *yes = (bool *) xyes;
13455 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13460 /* Calculate the stack information for the current function. This is
13461 complicated by having two separate calling sequences, the AIX calling
13462 sequence and the V.4 calling sequence.
13464 AIX (and Darwin/Mac OS X) stack frames look like:
13466 SP----> +---------------------------------------+
13467 | back chain to caller | 0 0
13468 +---------------------------------------+
13469 | saved CR | 4 8 (8-11)
13470 +---------------------------------------+
13472 +---------------------------------------+
13473 | reserved for compilers | 12 24
13474 +---------------------------------------+
13475 | reserved for binders | 16 32
13476 +---------------------------------------+
13477 | saved TOC pointer | 20 40
13478 +---------------------------------------+
13479 | Parameter save area (P) | 24 48
13480 +---------------------------------------+
13481 | Alloca space (A) | 24+P etc.
13482 +---------------------------------------+
13483 | Local variable space (L) | 24+P+A
13484 +---------------------------------------+
13485 | Float/int conversion temporary (X) | 24+P+A+L
13486 +---------------------------------------+
13487 | Save area for AltiVec registers (W) | 24+P+A+L+X
13488 +---------------------------------------+
13489 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13490 +---------------------------------------+
13491 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13492 +---------------------------------------+
13493 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13494 +---------------------------------------+
13495 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13496 +---------------------------------------+
13497 old SP->| back chain to caller's caller |
13498 +---------------------------------------+
13500 The required alignment for AIX configurations is two words (i.e., 8
13504 V.4 stack frames look like:
13506 SP----> +---------------------------------------+
13507 | back chain to caller | 0
13508 +---------------------------------------+
13509 | caller's saved LR | 4
13510 +---------------------------------------+
13511 | Parameter save area (P) | 8
13512 +---------------------------------------+
13513 | Alloca space (A) | 8+P
13514 +---------------------------------------+
13515 | Varargs save area (V) | 8+P+A
13516 +---------------------------------------+
13517 | Local variable space (L) | 8+P+A+V
13518 +---------------------------------------+
13519 | Float/int conversion temporary (X) | 8+P+A+V+L
13520 +---------------------------------------+
13521 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13522 +---------------------------------------+
13523 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13524 +---------------------------------------+
13525 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13526 +---------------------------------------+
13527 | SPE: area for 64-bit GP registers |
13528 +---------------------------------------+
13529 | SPE alignment padding |
13530 +---------------------------------------+
13531 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13532 +---------------------------------------+
13533 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13534 +---------------------------------------+
13535 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13536 +---------------------------------------+
13537 old SP->| back chain to caller's caller |
13538 +---------------------------------------+
13540 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13541 given. (But note below and in sysv4.h that we require only 8 and
13542 may round up the size of our stack frame anyways. The historical
13543 reason is early versions of powerpc-linux which didn't properly
13544 align the stack at program startup. A happy side-effect is that
13545 -mno-eabi libraries can be used with -meabi programs.)
13547 The EABI configuration defaults to the V.4 layout. However,
13548 the stack alignment requirements may differ. If -mno-eabi is not
13549 given, the required stack alignment is 8 bytes; if -mno-eabi is
13550 given, the required alignment is 16 bytes. (But see V.4 comment
13553 #ifndef ABI_STACK_BOUNDARY
13554 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13557 static rs6000_stack_t *
13558 rs6000_stack_info (void)
13560 static rs6000_stack_t info;
13561 rs6000_stack_t *info_ptr = &info;
13562 int reg_size = TARGET_32BIT ? 4 : 8;
13565 HOST_WIDE_INT non_fixed_size;
13567 memset (&info, 0, sizeof (info));
13571 /* Cache value so we don't rescan instruction chain over and over. */
13572 if (cfun->machine->insn_chain_scanned_p == 0)
13573 cfun->machine->insn_chain_scanned_p
13574 = spe_func_has_64bit_regs_p () + 1;
13575 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13578 /* Select which calling sequence. */
13579 info_ptr->abi = DEFAULT_ABI;
13581 /* Calculate which registers need to be saved & save area size. */
13582 info_ptr->first_gp_reg_save = first_reg_to_save ();
13583 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13584 even if it currently looks like we won't. */
13585 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13586 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13587 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13588 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13589 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13591 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13593 /* For the SPE, we have an additional upper 32-bits on each GPR.
13594 Ideally we should save the entire 64-bits only when the upper
13595 half is used in SIMD instructions. Since we only record
13596 registers live (not the size they are used in), this proves
13597 difficult because we'd have to traverse the instruction chain at
13598 the right time, taking reload into account. This is a real pain,
13599 so we opt to save the GPRs in 64-bits always if but one register
13600 gets used in 64-bits. Otherwise, all the registers in the frame
13601 get saved in 32-bits.
13603 So... since when we save all GPRs (except the SP) in 64-bits, the
13604 traditional GP save area will be empty. */
13605 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13606 info_ptr->gp_size = 0;
13608 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13609 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13611 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13612 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13613 - info_ptr->first_altivec_reg_save);
13615 /* Does this function call anything? */
13616 info_ptr->calls_p = (! current_function_is_leaf
13617 || cfun->machine->ra_needs_full_frame);
13619 /* Determine if we need to save the link register. */
13620 if ((DEFAULT_ABI == ABI_AIX
13621 && current_function_profile
13622 && !TARGET_PROFILE_KERNEL)
13623 #ifdef TARGET_RELOCATABLE
13624 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13626 || (info_ptr->first_fp_reg_save != 64
13627 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13628 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13629 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13630 || info_ptr->calls_p
13631 || rs6000_ra_ever_killed ())
13633 info_ptr->lr_save_p = 1;
13634 df_set_regs_ever_live (LR_REGNO, true);
13637 /* Determine if we need to save the condition code registers. */
13638 if (df_regs_ever_live_p (CR2_REGNO)
13639 || df_regs_ever_live_p (CR3_REGNO)
13640 || df_regs_ever_live_p (CR4_REGNO))
13642 info_ptr->cr_save_p = 1;
13643 if (DEFAULT_ABI == ABI_V4)
13644 info_ptr->cr_size = reg_size;
13647 /* If the current function calls __builtin_eh_return, then we need
13648 to allocate stack space for registers that will hold data for
13649 the exception handler. */
13650 if (current_function_calls_eh_return)
13653 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13656 /* SPE saves EH registers in 64-bits. */
13657 ehrd_size = i * (TARGET_SPE_ABI
13658 && info_ptr->spe_64bit_regs_used != 0
13659 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13664 /* Determine various sizes. */
13665 info_ptr->reg_size = reg_size;
13666 info_ptr->fixed_size = RS6000_SAVE_AREA;
13667 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13668 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13669 TARGET_ALTIVEC ? 16 : 8);
13670 if (FRAME_GROWS_DOWNWARD)
13671 info_ptr->vars_size
13672 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13673 + info_ptr->parm_size,
13674 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13675 - (info_ptr->fixed_size + info_ptr->vars_size
13676 + info_ptr->parm_size);
13678 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13679 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13681 info_ptr->spe_gp_size = 0;
13683 if (TARGET_ALTIVEC_ABI)
13684 info_ptr->vrsave_mask = compute_vrsave_mask ();
13686 info_ptr->vrsave_mask = 0;
13688 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13689 info_ptr->vrsave_size = 4;
13691 info_ptr->vrsave_size = 0;
13693 compute_save_world_info (info_ptr);
13695 /* Calculate the offsets. */
13696 switch (DEFAULT_ABI)
13700 gcc_unreachable ();
13704 info_ptr->fp_save_offset = - info_ptr->fp_size;
13705 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13707 if (TARGET_ALTIVEC_ABI)
13709 info_ptr->vrsave_save_offset
13710 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13712 /* Align stack so vector save area is on a quadword boundary.
13713 The padding goes above the vectors. */
13714 if (info_ptr->altivec_size != 0)
13715 info_ptr->altivec_padding_size
13716 = info_ptr->vrsave_save_offset & 0xF;
13718 info_ptr->altivec_padding_size = 0;
13720 info_ptr->altivec_save_offset
13721 = info_ptr->vrsave_save_offset
13722 - info_ptr->altivec_padding_size
13723 - info_ptr->altivec_size;
13724 gcc_assert (info_ptr->altivec_size == 0
13725 || info_ptr->altivec_save_offset % 16 == 0);
13727 /* Adjust for AltiVec case. */
13728 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13731 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13732 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13733 info_ptr->lr_save_offset = 2*reg_size;
13737 info_ptr->fp_save_offset = - info_ptr->fp_size;
13738 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13739 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13741 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13743 /* Align stack so SPE GPR save area is aligned on a
13744 double-word boundary. */
13745 if (info_ptr->spe_gp_size != 0)
13746 info_ptr->spe_padding_size
13747 = 8 - (-info_ptr->cr_save_offset % 8);
13749 info_ptr->spe_padding_size = 0;
13751 info_ptr->spe_gp_save_offset
13752 = info_ptr->cr_save_offset
13753 - info_ptr->spe_padding_size
13754 - info_ptr->spe_gp_size;
13756 /* Adjust for SPE case. */
13757 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13759 else if (TARGET_ALTIVEC_ABI)
13761 info_ptr->vrsave_save_offset
13762 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13764 /* Align stack so vector save area is on a quadword boundary. */
13765 if (info_ptr->altivec_size != 0)
13766 info_ptr->altivec_padding_size
13767 = 16 - (-info_ptr->vrsave_save_offset % 16);
13769 info_ptr->altivec_padding_size = 0;
13771 info_ptr->altivec_save_offset
13772 = info_ptr->vrsave_save_offset
13773 - info_ptr->altivec_padding_size
13774 - info_ptr->altivec_size;
13776 /* Adjust for AltiVec case. */
13777 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13780 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13781 info_ptr->ehrd_offset -= ehrd_size;
13782 info_ptr->lr_save_offset = reg_size;
13786 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13787 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13788 + info_ptr->gp_size
13789 + info_ptr->altivec_size
13790 + info_ptr->altivec_padding_size
13791 + info_ptr->spe_gp_size
13792 + info_ptr->spe_padding_size
13794 + info_ptr->cr_size
13795 + info_ptr->vrsave_size,
13798 non_fixed_size = (info_ptr->vars_size
13799 + info_ptr->parm_size
13800 + info_ptr->save_size);
13802 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13803 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13805 /* Determine if we need to allocate any stack frame:
13807 For AIX we need to push the stack if a frame pointer is needed
13808 (because the stack might be dynamically adjusted), if we are
13809 debugging, if we make calls, or if the sum of fp_save, gp_save,
13810 and local variables are more than the space needed to save all
13811 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13812 + 18*8 = 288 (GPR13 reserved).
13814 For V.4 we don't have the stack cushion that AIX uses, but assume
13815 that the debugger can handle stackless frames. */
13817 if (info_ptr->calls_p)
13818 info_ptr->push_p = 1;
13820 else if (DEFAULT_ABI == ABI_V4)
13821 info_ptr->push_p = non_fixed_size != 0;
13823 else if (frame_pointer_needed)
13824 info_ptr->push_p = 1;
13826 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13827 info_ptr->push_p = 1;
13830 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13832 /* Zero offsets if we're not saving those registers. */
13833 if (info_ptr->fp_size == 0)
13834 info_ptr->fp_save_offset = 0;
13836 if (info_ptr->gp_size == 0)
13837 info_ptr->gp_save_offset = 0;
13839 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13840 info_ptr->altivec_save_offset = 0;
13842 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13843 info_ptr->vrsave_save_offset = 0;
13845 if (! TARGET_SPE_ABI
13846 || info_ptr->spe_64bit_regs_used == 0
13847 || info_ptr->spe_gp_size == 0)
13848 info_ptr->spe_gp_save_offset = 0;
13850 if (! info_ptr->lr_save_p)
13851 info_ptr->lr_save_offset = 0;
13853 if (! info_ptr->cr_save_p)
13854 info_ptr->cr_save_offset = 0;
13859 /* Return true if the current function uses any GPRs in 64-bit SIMD
13863 spe_func_has_64bit_regs_p (void)
13867 /* Functions that save and restore all the call-saved registers will
13868 need to save/restore the registers in 64-bits. */
13869 if (current_function_calls_eh_return
13870 || current_function_calls_setjmp
13871 || current_function_has_nonlocal_goto)
13874 insns = get_insns ();
13876 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13882 /* FIXME: This should be implemented with attributes...
13884 (set_attr "spe64" "true")....then,
13885 if (get_spe64(insn)) return true;
13887 It's the only reliable way to do the stuff below. */
13889 i = PATTERN (insn);
13890 if (GET_CODE (i) == SET)
13892 enum machine_mode mode = GET_MODE (SET_SRC (i));
13894 if (SPE_VECTOR_MODE (mode))
13896 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13906 debug_stack_info (rs6000_stack_t *info)
13908 const char *abi_string;
13911 info = rs6000_stack_info ();
13913 fprintf (stderr, "\nStack information for function %s:\n",
13914 ((current_function_decl && DECL_NAME (current_function_decl))
13915 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13920 default: abi_string = "Unknown"; break;
13921 case ABI_NONE: abi_string = "NONE"; break;
13922 case ABI_AIX: abi_string = "AIX"; break;
13923 case ABI_DARWIN: abi_string = "Darwin"; break;
13924 case ABI_V4: abi_string = "V.4"; break;
13927 fprintf (stderr, "\tABI = %5s\n", abi_string);
13929 if (TARGET_ALTIVEC_ABI)
13930 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13932 if (TARGET_SPE_ABI)
13933 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13935 if (info->first_gp_reg_save != 32)
13936 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13938 if (info->first_fp_reg_save != 64)
13939 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13941 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13942 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13943 info->first_altivec_reg_save);
13945 if (info->lr_save_p)
13946 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13948 if (info->cr_save_p)
13949 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13951 if (info->vrsave_mask)
13952 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13955 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13958 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13960 if (info->gp_save_offset)
13961 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13963 if (info->fp_save_offset)
13964 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13966 if (info->altivec_save_offset)
13967 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13968 info->altivec_save_offset);
13970 if (info->spe_gp_save_offset)
13971 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13972 info->spe_gp_save_offset);
13974 if (info->vrsave_save_offset)
13975 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13976 info->vrsave_save_offset);
13978 if (info->lr_save_offset)
13979 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13981 if (info->cr_save_offset)
13982 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13984 if (info->varargs_save_offset)
13985 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13987 if (info->total_size)
13988 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13991 if (info->vars_size)
13992 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13995 if (info->parm_size)
13996 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13998 if (info->fixed_size)
13999 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14002 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14004 if (info->spe_gp_size)
14005 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14008 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14010 if (info->altivec_size)
14011 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14013 if (info->vrsave_size)
14014 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14016 if (info->altivec_padding_size)
14017 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14018 info->altivec_padding_size);
14020 if (info->spe_padding_size)
14021 fprintf (stderr, "\tspe_padding_size = %5d\n",
14022 info->spe_padding_size);
14025 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14027 if (info->save_size)
14028 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14030 if (info->reg_size != 4)
14031 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14033 fprintf (stderr, "\n");
14037 rs6000_return_addr (int count, rtx frame)
14039 /* Currently we don't optimize very well between prolog and body
14040 code and for PIC code the code can be actually quite bad, so
14041 don't try to be too clever here. */
14042 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14044 cfun->machine->ra_needs_full_frame = 1;
14051 plus_constant (copy_to_reg
14052 (gen_rtx_MEM (Pmode,
14053 memory_address (Pmode, frame))),
14054 RETURN_ADDRESS_OFFSET)));
14057 cfun->machine->ra_need_lr = 1;
14058 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14061 /* Say whether a function is a candidate for sibcall handling or not.
14062 We do not allow indirect calls to be optimized into sibling calls.
14063 Also, we can't do it if there are any vector parameters; there's
14064 nowhere to put the VRsave code so it works; note that functions with
14065 vector parameters are required to have a prototype, so the argument
14066 type info must be available here. (The tail recursion case can work
14067 with vector parameters, but there's no way to distinguish here.) */
14069 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14074 if (TARGET_ALTIVEC_VRSAVE)
14076 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14077 type; type = TREE_CHAIN (type))
14079 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14083 if (DEFAULT_ABI == ABI_DARWIN
14084 || ((*targetm.binds_local_p) (decl)
14085 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14087 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14089 if (!lookup_attribute ("longcall", attr_list)
14090 || lookup_attribute ("shortcall", attr_list))
14097 /* NULL if INSN insn is valid within a low-overhead loop.
14098 Otherwise return why doloop cannot be applied.
14099 PowerPC uses the COUNT register for branch on table instructions. */
14101 static const char *
14102 rs6000_invalid_within_doloop (rtx insn)
14105 return "Function call in the loop.";
14108 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14109 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14110 return "Computed branch in the loop.";
14116 rs6000_ra_ever_killed (void)
14122 if (current_function_is_thunk)
14125 /* regs_ever_live has LR marked as used if any sibcalls are present,
14126 but this should not force saving and restoring in the
14127 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14128 clobbers LR, so that is inappropriate. */
14130 /* Also, the prologue can generate a store into LR that
14131 doesn't really count, like this:
14134 bcl to set PIC register
14138 When we're called from the epilogue, we need to avoid counting
14139 this as a store. */
14141 push_topmost_sequence ();
14142 top = get_insns ();
14143 pop_topmost_sequence ();
14144 reg = gen_rtx_REG (Pmode, LR_REGNO);
14146 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14152 if (!SIBLING_CALL_P (insn))
14155 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14157 else if (set_of (reg, insn) != NULL_RTX
14158 && !prologue_epilogue_contains (insn))
14165 /* Emit instructions needed to load the TOC register.
14166 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14167 a constant pool; or for SVR4 -fpic. */
14170 rs6000_emit_load_toc_table (int fromprolog)
14173 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14175 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14178 rtx lab, tmp1, tmp2, got;
14180 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14181 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14183 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14185 got = rs6000_got_sym ();
14186 tmp1 = tmp2 = dest;
14189 tmp1 = gen_reg_rtx (Pmode);
14190 tmp2 = gen_reg_rtx (Pmode);
14192 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14193 emit_move_insn (tmp1,
14194 gen_rtx_REG (Pmode, LR_REGNO));
14195 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14196 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14198 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14200 emit_insn (gen_load_toc_v4_pic_si ());
14201 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
14203 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14206 rtx temp0 = (fromprolog
14207 ? gen_rtx_REG (Pmode, 0)
14208 : gen_reg_rtx (Pmode));
14214 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14215 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14217 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14218 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14220 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14221 emit_move_insn (dest,
14222 gen_rtx_REG (Pmode, LR_REGNO));
14223 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14229 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14230 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14231 emit_move_insn (dest,
14232 gen_rtx_REG (Pmode, LR_REGNO));
14233 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14235 emit_insn (gen_addsi3 (dest, temp0, dest));
14237 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14239 /* This is for AIX code running in non-PIC ELF32. */
14242 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14243 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14245 emit_insn (gen_elf_high (dest, realsym));
14246 emit_insn (gen_elf_low (dest, dest, realsym));
14250 gcc_assert (DEFAULT_ABI == ABI_AIX);
14253 emit_insn (gen_load_toc_aix_si (dest));
14255 emit_insn (gen_load_toc_aix_di (dest));
14259 /* Emit instructions to restore the link register after determining where
14260 its value has been stored. */
14263 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14265 rs6000_stack_t *info = rs6000_stack_info ();
14268 operands[0] = source;
14269 operands[1] = scratch;
14271 if (info->lr_save_p)
14273 rtx frame_rtx = stack_pointer_rtx;
14274 HOST_WIDE_INT sp_offset = 0;
14277 if (frame_pointer_needed
14278 || current_function_calls_alloca
14279 || info->total_size > 32767)
14281 tmp = gen_frame_mem (Pmode, frame_rtx);
14282 emit_move_insn (operands[1], tmp);
14283 frame_rtx = operands[1];
14285 else if (info->push_p)
14286 sp_offset = info->total_size;
14288 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14289 tmp = gen_frame_mem (Pmode, tmp);
14290 emit_move_insn (tmp, operands[0]);
14293 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
14296 static GTY(()) int set = -1;
14299 get_TOC_alias_set (void)
14302 set = new_alias_set ();
14306 /* This returns nonzero if the current function uses the TOC. This is
14307 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14308 is generated by the ABI_V4 load_toc_* patterns. */
14315 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14318 rtx pat = PATTERN (insn);
14321 if (GET_CODE (pat) == PARALLEL)
14322 for (i = 0; i < XVECLEN (pat, 0); i++)
14324 rtx sub = XVECEXP (pat, 0, i);
14325 if (GET_CODE (sub) == USE)
14327 sub = XEXP (sub, 0);
14328 if (GET_CODE (sub) == UNSPEC
14329 && XINT (sub, 1) == UNSPEC_TOC)
14339 create_TOC_reference (rtx symbol)
14341 if (!can_create_pseudo_p ())
14342 df_set_regs_ever_live (TOC_REGISTER, true);
14343 return gen_rtx_PLUS (Pmode,
14344 gen_rtx_REG (Pmode, TOC_REGISTER),
14345 gen_rtx_CONST (Pmode,
14346 gen_rtx_MINUS (Pmode, symbol,
14347 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14350 /* If _Unwind_* has been called from within the same module,
14351 toc register is not guaranteed to be saved to 40(1) on function
14352 entry. Save it there in that case. */
14355 rs6000_aix_emit_builtin_unwind_init (void)
14358 rtx stack_top = gen_reg_rtx (Pmode);
14359 rtx opcode_addr = gen_reg_rtx (Pmode);
14360 rtx opcode = gen_reg_rtx (SImode);
14361 rtx tocompare = gen_reg_rtx (SImode);
14362 rtx no_toc_save_needed = gen_label_rtx ();
14364 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14365 emit_move_insn (stack_top, mem);
14367 mem = gen_frame_mem (Pmode,
14368 gen_rtx_PLUS (Pmode, stack_top,
14369 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14370 emit_move_insn (opcode_addr, mem);
14371 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14372 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14373 : 0xE8410028, SImode));
14375 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14376 SImode, NULL_RTX, NULL_RTX,
14377 no_toc_save_needed);
14379 mem = gen_frame_mem (Pmode,
14380 gen_rtx_PLUS (Pmode, stack_top,
14381 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14382 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14383 emit_label (no_toc_save_needed);
14386 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14387 and the change to the stack pointer. */
14390 rs6000_emit_stack_tie (void)
14392 rtx mem = gen_frame_mem (BLKmode,
14393 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14395 emit_insn (gen_stack_tie (mem));
14398 /* Emit the correct code for allocating stack space, as insns.
14399 If COPY_R12, make sure a copy of the old frame is left in r12.
14400 The generated code may use hard register 0 as a temporary. */
14403 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14406 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14407 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14408 rtx todec = gen_int_mode (-size, Pmode);
14410 if (INTVAL (todec) != -size)
14412 warning (0, "stack frame too large");
14413 emit_insn (gen_trap ());
14417 if (current_function_limit_stack)
14419 if (REG_P (stack_limit_rtx)
14420 && REGNO (stack_limit_rtx) > 1
14421 && REGNO (stack_limit_rtx) <= 31)
14423 emit_insn (TARGET_32BIT
14424 ? gen_addsi3 (tmp_reg,
14427 : gen_adddi3 (tmp_reg,
14431 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14434 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14436 && DEFAULT_ABI == ABI_V4)
14438 rtx toload = gen_rtx_CONST (VOIDmode,
14439 gen_rtx_PLUS (Pmode,
14443 emit_insn (gen_elf_high (tmp_reg, toload));
14444 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14445 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14449 warning (0, "stack limit expression is not supported");
14452 if (copy_r12 || ! TARGET_UPDATE)
14453 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14459 /* Need a note here so that try_split doesn't get confused. */
14460 if (get_last_insn () == NULL_RTX)
14461 emit_note (NOTE_INSN_DELETED);
14462 insn = emit_move_insn (tmp_reg, todec);
14463 try_split (PATTERN (insn), insn, 0);
14467 insn = emit_insn (TARGET_32BIT
14468 ? gen_movsi_update (stack_reg, stack_reg,
14470 : gen_movdi_di_update (stack_reg, stack_reg,
14471 todec, stack_reg));
14475 insn = emit_insn (TARGET_32BIT
14476 ? gen_addsi3 (stack_reg, stack_reg, todec)
14477 : gen_adddi3 (stack_reg, stack_reg, todec));
14478 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14479 gen_rtx_REG (Pmode, 12));
14482 RTX_FRAME_RELATED_P (insn) = 1;
14484 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14485 gen_rtx_SET (VOIDmode, stack_reg,
14486 gen_rtx_PLUS (Pmode, stack_reg,
14491 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14492 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14493 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14494 deduce these equivalences by itself so it wasn't necessary to hold
14495 its hand so much. */
14498 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14499 rtx reg2, rtx rreg)
14503 /* copy_rtx will not make unique copies of registers, so we need to
14504 ensure we don't have unwanted sharing here. */
14506 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14509 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14511 real = copy_rtx (PATTERN (insn));
14513 if (reg2 != NULL_RTX)
14514 real = replace_rtx (real, reg2, rreg);
14516 real = replace_rtx (real, reg,
14517 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14518 STACK_POINTER_REGNUM),
14521 /* We expect that 'real' is either a SET or a PARALLEL containing
14522 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14523 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14525 if (GET_CODE (real) == SET)
14529 temp = simplify_rtx (SET_SRC (set));
14531 SET_SRC (set) = temp;
14532 temp = simplify_rtx (SET_DEST (set));
14534 SET_DEST (set) = temp;
14535 if (GET_CODE (SET_DEST (set)) == MEM)
14537 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14539 XEXP (SET_DEST (set), 0) = temp;
14546 gcc_assert (GET_CODE (real) == PARALLEL);
14547 for (i = 0; i < XVECLEN (real, 0); i++)
14548 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14550 rtx set = XVECEXP (real, 0, i);
14552 temp = simplify_rtx (SET_SRC (set));
14554 SET_SRC (set) = temp;
14555 temp = simplify_rtx (SET_DEST (set));
14557 SET_DEST (set) = temp;
14558 if (GET_CODE (SET_DEST (set)) == MEM)
14560 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14562 XEXP (SET_DEST (set), 0) = temp;
14564 RTX_FRAME_RELATED_P (set) = 1;
14569 real = spe_synthesize_frame_save (real);
14571 RTX_FRAME_RELATED_P (insn) = 1;
14572 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14577 /* Given an SPE frame note, return a PARALLEL of SETs with the
14578 original note, plus a synthetic register save. */
14581 spe_synthesize_frame_save (rtx real)
14583 rtx synth, offset, reg, real2;
14585 if (GET_CODE (real) != SET
14586 || GET_MODE (SET_SRC (real)) != V2SImode)
14589 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14590 frame related note. The parallel contains a set of the register
14591 being saved, and another set to a synthetic register (n+1200).
14592 This is so we can differentiate between 64-bit and 32-bit saves.
14593 Words cannot describe this nastiness. */
14595 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14596 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14597 && GET_CODE (SET_SRC (real)) == REG);
14600 (set (mem (plus (reg x) (const y)))
14603 (set (mem (plus (reg x) (const y+4)))
14607 real2 = copy_rtx (real);
14608 PUT_MODE (SET_DEST (real2), SImode);
14609 reg = SET_SRC (real2);
14610 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14611 synth = copy_rtx (real2);
14613 if (BYTES_BIG_ENDIAN)
14615 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14616 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14619 reg = SET_SRC (synth);
14621 synth = replace_rtx (synth, reg,
14622 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14624 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14625 synth = replace_rtx (synth, offset,
14626 GEN_INT (INTVAL (offset)
14627 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14629 RTX_FRAME_RELATED_P (synth) = 1;
14630 RTX_FRAME_RELATED_P (real2) = 1;
14631 if (BYTES_BIG_ENDIAN)
14632 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14634 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14639 /* Returns an insn that has a vrsave set operation with the
14640 appropriate CLOBBERs. */
14643 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14646 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14647 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14650 = gen_rtx_SET (VOIDmode,
14652 gen_rtx_UNSPEC_VOLATILE (SImode,
14653 gen_rtvec (2, reg, vrsave),
14654 UNSPECV_SET_VRSAVE));
14658 /* We need to clobber the registers in the mask so the scheduler
14659 does not move sets to VRSAVE before sets of AltiVec registers.
14661 However, if the function receives nonlocal gotos, reload will set
14662 all call saved registers live. We will end up with:
14664 (set (reg 999) (mem))
14665 (parallel [ (set (reg vrsave) (unspec blah))
14666 (clobber (reg 999))])
14668 The clobber will cause the store into reg 999 to be dead, and
14669 flow will attempt to delete an epilogue insn. In this case, we
14670 need an unspec use/set of the register. */
14672 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14673 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14675 if (!epiloguep || call_used_regs [i])
14676 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14677 gen_rtx_REG (V4SImode, i));
14680 rtx reg = gen_rtx_REG (V4SImode, i);
14683 = gen_rtx_SET (VOIDmode,
14685 gen_rtx_UNSPEC (V4SImode,
14686 gen_rtvec (1, reg), 27));
14690 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14692 for (i = 0; i < nclobs; ++i)
14693 XVECEXP (insn, 0, i) = clobs[i];
14698 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14699 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14702 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14703 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14705 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14706 rtx replacea, replaceb;
14708 int_rtx = GEN_INT (offset);
14710 /* Some cases that need register indexed addressing. */
14711 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14712 || (TARGET_E500_DOUBLE && mode == DFmode)
14714 && SPE_VECTOR_MODE (mode)
14715 && !SPE_CONST_OFFSET_OK (offset)))
14717 /* Whomever calls us must make sure r11 is available in the
14718 flow path of instructions in the prologue. */
14719 offset_rtx = gen_rtx_REG (Pmode, 11);
14720 emit_move_insn (offset_rtx, int_rtx);
14722 replacea = offset_rtx;
14723 replaceb = int_rtx;
14727 offset_rtx = int_rtx;
14728 replacea = NULL_RTX;
14729 replaceb = NULL_RTX;
14732 reg = gen_rtx_REG (mode, regno);
14733 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14734 mem = gen_frame_mem (mode, addr);
14736 insn = emit_move_insn (mem, reg);
14738 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14741 /* Emit an offset memory reference suitable for a frame store, while
14742 converting to a valid addressing mode. */
14745 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14747 rtx int_rtx, offset_rtx;
14749 int_rtx = GEN_INT (offset);
14751 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14752 || (TARGET_E500_DOUBLE && mode == DFmode))
14754 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14755 emit_move_insn (offset_rtx, int_rtx);
14758 offset_rtx = int_rtx;
14760 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14763 /* Look for user-defined global regs. We should not save and restore these,
14764 and cannot use stmw/lmw if there are any in its range. */
14767 no_global_regs_above (int first_greg)
14770 for (i = 0; i < 32 - first_greg; i++)
14771 if (global_regs[first_greg + i])
14776 #ifndef TARGET_FIX_AND_CONTINUE
14777 #define TARGET_FIX_AND_CONTINUE 0
14780 /* Determine whether the gp REG is really used. */
14783 rs6000_reg_live_or_pic_offset_p (int reg)
14785 return ((df_regs_ever_live_p (reg)
14786 && (!call_used_regs[reg]
14787 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14788 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14789 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14790 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14791 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
14794 /* Emit function prologue as insns. */
14797 rs6000_emit_prologue (void)
14799 rs6000_stack_t *info = rs6000_stack_info ();
14800 enum machine_mode reg_mode = Pmode;
14801 int reg_size = TARGET_32BIT ? 4 : 8;
14802 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14803 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14804 rtx frame_reg_rtx = sp_reg_rtx;
14805 rtx cr_save_rtx = NULL_RTX;
14807 int saving_FPRs_inline;
14808 int using_store_multiple;
14809 HOST_WIDE_INT sp_offset = 0;
14811 if (TARGET_FIX_AND_CONTINUE)
14813 /* gdb on darwin arranges to forward a function from the old
14814 address by modifying the first 5 instructions of the function
14815 to branch to the overriding function. This is necessary to
14816 permit function pointers that point to the old function to
14817 actually forward to the new function. */
14818 emit_insn (gen_nop ());
14819 emit_insn (gen_nop ());
14820 emit_insn (gen_nop ());
14821 emit_insn (gen_nop ());
14822 emit_insn (gen_nop ());
14825 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14827 reg_mode = V2SImode;
14831 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14832 && (!TARGET_SPE_ABI
14833 || info->spe_64bit_regs_used == 0)
14834 && info->first_gp_reg_save < 31
14835 && no_global_regs_above (info->first_gp_reg_save));
14836 saving_FPRs_inline = (info->first_fp_reg_save == 64
14837 || FP_SAVE_INLINE (info->first_fp_reg_save)
14838 || current_function_calls_eh_return
14839 || cfun->machine->ra_need_lr);
14841 /* For V.4, update stack before we do any saving and set back pointer. */
14842 if (! WORLD_SAVE_P (info)
14844 && (DEFAULT_ABI == ABI_V4
14845 || current_function_calls_eh_return))
14847 if (info->total_size < 32767)
14848 sp_offset = info->total_size;
14850 frame_reg_rtx = frame_ptr_rtx;
14851 rs6000_emit_allocate_stack (info->total_size,
14852 (frame_reg_rtx != sp_reg_rtx
14853 && (info->cr_save_p
14855 || info->first_fp_reg_save < 64
14856 || info->first_gp_reg_save < 32
14858 if (frame_reg_rtx != sp_reg_rtx)
14859 rs6000_emit_stack_tie ();
14862 /* Handle world saves specially here. */
14863 if (WORLD_SAVE_P (info))
14870 /* save_world expects lr in r0. */
14871 reg0 = gen_rtx_REG (Pmode, 0);
14872 if (info->lr_save_p)
14874 insn = emit_move_insn (reg0,
14875 gen_rtx_REG (Pmode, LR_REGNO));
14876 RTX_FRAME_RELATED_P (insn) = 1;
14879 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14880 assumptions about the offsets of various bits of the stack
14882 gcc_assert (info->gp_save_offset == -220
14883 && info->fp_save_offset == -144
14884 && info->lr_save_offset == 8
14885 && info->cr_save_offset == 4
14888 && (!current_function_calls_eh_return
14889 || info->ehrd_offset == -432)
14890 && info->vrsave_save_offset == -224
14891 && info->altivec_save_offset == -416);
14893 treg = gen_rtx_REG (SImode, 11);
14894 emit_move_insn (treg, GEN_INT (-info->total_size));
14896 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14897 in R11. It also clobbers R12, so beware! */
14899 /* Preserve CR2 for save_world prologues */
14901 sz += 32 - info->first_gp_reg_save;
14902 sz += 64 - info->first_fp_reg_save;
14903 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14904 p = rtvec_alloc (sz);
14906 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14907 gen_rtx_REG (SImode,
14909 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14910 gen_rtx_SYMBOL_REF (Pmode,
14912 /* We do floats first so that the instruction pattern matches
14914 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14916 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14917 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14918 GEN_INT (info->fp_save_offset
14919 + sp_offset + 8 * i));
14920 rtx mem = gen_frame_mem (DFmode, addr);
14922 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14924 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14926 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14927 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14928 GEN_INT (info->altivec_save_offset
14929 + sp_offset + 16 * i));
14930 rtx mem = gen_frame_mem (V4SImode, addr);
14932 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14934 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14936 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14937 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14938 GEN_INT (info->gp_save_offset
14939 + sp_offset + reg_size * i));
14940 rtx mem = gen_frame_mem (reg_mode, addr);
14942 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14946 /* CR register traditionally saved as CR2. */
14947 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14948 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14949 GEN_INT (info->cr_save_offset
14951 rtx mem = gen_frame_mem (reg_mode, addr);
14953 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14955 /* Explain about use of R0. */
14956 if (info->lr_save_p)
14958 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14959 GEN_INT (info->lr_save_offset
14961 rtx mem = gen_frame_mem (reg_mode, addr);
14963 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14965 /* Explain what happens to the stack pointer. */
14967 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14968 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14971 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14972 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14973 treg, GEN_INT (-info->total_size));
14974 sp_offset = info->total_size;
14977 /* If we use the link register, get it into r0. */
14978 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14980 rtx addr, reg, mem;
14982 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14983 gen_rtx_REG (Pmode, LR_REGNO));
14984 RTX_FRAME_RELATED_P (insn) = 1;
14986 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14987 GEN_INT (info->lr_save_offset + sp_offset));
14988 reg = gen_rtx_REG (Pmode, 0);
14989 mem = gen_rtx_MEM (Pmode, addr);
14990 /* This should not be of rs6000_sr_alias_set, because of
14991 __builtin_return_address. */
14993 insn = emit_move_insn (mem, reg);
14994 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14995 NULL_RTX, NULL_RTX);
14998 /* If we need to save CR, put it into r12. */
14999 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
15003 cr_save_rtx = gen_rtx_REG (SImode, 12);
15004 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15005 RTX_FRAME_RELATED_P (insn) = 1;
15006 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15007 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15008 But that's OK. All we have to do is specify that _one_ condition
15009 code register is saved in this stack slot. The thrower's epilogue
15010 will then restore all the call-saved registers.
15011 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15012 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
15013 gen_rtx_REG (SImode, CR2_REGNO));
15014 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15019 /* Do any required saving of fpr's. If only one or two to save, do
15020 it ourselves. Otherwise, call function. */
15021 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
15024 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15025 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15026 && ! call_used_regs[info->first_fp_reg_save+i]))
15027 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
15028 info->first_fp_reg_save + i,
15029 info->fp_save_offset + sp_offset + 8 * i,
15032 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
15036 const char *alloc_rname;
15038 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
15040 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
15041 gen_rtx_REG (Pmode,
15043 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
15044 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
15045 alloc_rname = ggc_strdup (rname);
15046 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15047 gen_rtx_SYMBOL_REF (Pmode,
15049 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15051 rtx addr, reg, mem;
15052 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15053 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15054 GEN_INT (info->fp_save_offset
15055 + sp_offset + 8*i));
15056 mem = gen_frame_mem (DFmode, addr);
15058 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
15060 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15061 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15062 NULL_RTX, NULL_RTX);
15065 /* Save GPRs. This is done as a PARALLEL if we are using
15066 the store-multiple instructions. */
15067 if (!WORLD_SAVE_P (info) && using_store_multiple)
15071 p = rtvec_alloc (32 - info->first_gp_reg_save);
15072 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15074 rtx addr, reg, mem;
15075 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15076 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15077 GEN_INT (info->gp_save_offset
15080 mem = gen_frame_mem (reg_mode, addr);
15082 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
15084 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15085 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15086 NULL_RTX, NULL_RTX);
15088 else if (!WORLD_SAVE_P (info)
15090 && info->spe_64bit_regs_used != 0
15091 && info->first_gp_reg_save != 32)
15094 rtx spe_save_area_ptr;
15095 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15096 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15097 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15099 /* Determine whether we can address all of the registers that need
15100 to be saved with an offset from the stack pointer that fits in
15101 the small const field for SPE memory instructions. */
15102 int spe_regs_addressable_via_sp
15103 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15104 + (32 - info->first_gp_reg_save - 1) * reg_size);
15107 if (spe_regs_addressable_via_sp)
15109 spe_save_area_ptr = sp_reg_rtx;
15110 spe_offset = info->spe_gp_save_offset + sp_offset;
15114 /* Make r11 point to the start of the SPE save area. We need
15115 to be careful here if r11 is holding the static chain. If
15116 it is, then temporarily save it in r0. We would use r0 as
15117 our base register here, but using r0 as a base register in
15118 loads and stores means something different from what we
15120 if (using_static_chain_p)
15122 rtx r0 = gen_rtx_REG (Pmode, 0);
15124 gcc_assert (info->first_gp_reg_save > 11);
15126 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15129 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15130 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
15131 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15136 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15137 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15139 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15140 rtx offset, addr, mem;
15142 /* We're doing all this to ensure that the offset fits into
15143 the immediate offset of 'evstdd'. */
15144 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15146 offset = GEN_INT (reg_size * i + spe_offset);
15147 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15148 mem = gen_rtx_MEM (V2SImode, addr);
15150 insn = emit_move_insn (mem, reg);
15152 rs6000_frame_related (insn, spe_save_area_ptr,
15153 info->spe_gp_save_offset
15154 + sp_offset + reg_size * i,
15155 offset, const0_rtx);
15158 /* Move the static chain pointer back. */
15159 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15160 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15162 else if (!WORLD_SAVE_P (info))
15165 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15166 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15168 rtx addr, reg, mem;
15169 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15171 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15172 GEN_INT (info->gp_save_offset
15175 mem = gen_frame_mem (reg_mode, addr);
15177 insn = emit_move_insn (mem, reg);
15178 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15179 NULL_RTX, NULL_RTX);
15183 /* ??? There's no need to emit actual instructions here, but it's the
15184 easiest way to get the frame unwind information emitted. */
15185 if (current_function_calls_eh_return)
15187 unsigned int i, regno;
15189 /* In AIX ABI we need to pretend we save r2 here. */
15192 rtx addr, reg, mem;
15194 reg = gen_rtx_REG (reg_mode, 2);
15195 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15196 GEN_INT (sp_offset + 5 * reg_size));
15197 mem = gen_frame_mem (reg_mode, addr);
15199 insn = emit_move_insn (mem, reg);
15200 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15201 NULL_RTX, NULL_RTX);
15202 PATTERN (insn) = gen_blockage ();
15207 regno = EH_RETURN_DATA_REGNO (i);
15208 if (regno == INVALID_REGNUM)
15211 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15212 info->ehrd_offset + sp_offset
15213 + reg_size * (int) i,
15218 /* Save CR if we use any that must be preserved. */
15219 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15221 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15222 GEN_INT (info->cr_save_offset + sp_offset));
15223 rtx mem = gen_frame_mem (SImode, addr);
15224 /* See the large comment above about why CR2_REGNO is used. */
15225 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15227 /* If r12 was used to hold the original sp, copy cr into r0 now
15229 if (REGNO (frame_reg_rtx) == 12)
15233 cr_save_rtx = gen_rtx_REG (SImode, 0);
15234 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15235 RTX_FRAME_RELATED_P (insn) = 1;
15236 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15237 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15242 insn = emit_move_insn (mem, cr_save_rtx);
15244 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15245 NULL_RTX, NULL_RTX);
15248 /* Update stack and set back pointer unless this is V.4,
15249 for which it was done previously. */
15250 if (!WORLD_SAVE_P (info) && info->push_p
15251 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15253 if (info->total_size < 32767)
15254 sp_offset = info->total_size;
15256 frame_reg_rtx = frame_ptr_rtx;
15257 rs6000_emit_allocate_stack (info->total_size,
15258 (frame_reg_rtx != sp_reg_rtx
15259 && ((info->altivec_size != 0)
15260 || (info->vrsave_mask != 0)
15262 if (frame_reg_rtx != sp_reg_rtx)
15263 rs6000_emit_stack_tie ();
15266 /* Set frame pointer, if needed. */
15267 if (frame_pointer_needed)
15269 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15271 RTX_FRAME_RELATED_P (insn) = 1;
15274 /* Save AltiVec registers if needed. Save here because the red zone does
15275 not include AltiVec registers. */
15276 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15280 /* There should be a non inline version of this, for when we
15281 are saving lots of vector registers. */
15282 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15283 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15285 rtx areg, savereg, mem;
15288 offset = info->altivec_save_offset + sp_offset
15289 + 16 * (i - info->first_altivec_reg_save);
15291 savereg = gen_rtx_REG (V4SImode, i);
15293 areg = gen_rtx_REG (Pmode, 0);
15294 emit_move_insn (areg, GEN_INT (offset));
15296 /* AltiVec addressing mode is [reg+reg]. */
15297 mem = gen_frame_mem (V4SImode,
15298 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15300 insn = emit_move_insn (mem, savereg);
15302 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15303 areg, GEN_INT (offset));
15307 /* VRSAVE is a bit vector representing which AltiVec registers
15308 are used. The OS uses this to determine which vector
15309 registers to save on a context switch. We need to save
15310 VRSAVE on the stack frame, add whatever AltiVec registers we
15311 used in this function, and do the corresponding magic in the
15314 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15315 && info->vrsave_mask != 0)
15317 rtx reg, mem, vrsave;
15320 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15321 as frame_reg_rtx and r11 as the static chain pointer for
15322 nested functions. */
15323 reg = gen_rtx_REG (SImode, 0);
15324 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15326 emit_insn (gen_get_vrsave_internal (reg));
15328 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15330 if (!WORLD_SAVE_P (info))
15333 offset = info->vrsave_save_offset + sp_offset;
15334 mem = gen_frame_mem (SImode,
15335 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15336 GEN_INT (offset)));
15337 insn = emit_move_insn (mem, reg);
15340 /* Include the registers in the mask. */
15341 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15343 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15346 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15347 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15348 || (DEFAULT_ABI == ABI_V4
15349 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15350 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15352 /* If emit_load_toc_table will use the link register, we need to save
15353 it. We use R12 for this purpose because emit_load_toc_table
15354 can use register 0. This allows us to use a plain 'blr' to return
15355 from the procedure more often. */
15356 int save_LR_around_toc_setup = (TARGET_ELF
15357 && DEFAULT_ABI != ABI_AIX
15359 && ! info->lr_save_p
15360 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15361 if (save_LR_around_toc_setup)
15363 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15365 insn = emit_move_insn (frame_ptr_rtx, lr);
15366 RTX_FRAME_RELATED_P (insn) = 1;
15368 rs6000_emit_load_toc_table (TRUE);
15370 insn = emit_move_insn (lr, frame_ptr_rtx);
15371 RTX_FRAME_RELATED_P (insn) = 1;
15374 rs6000_emit_load_toc_table (TRUE);
15378 if (DEFAULT_ABI == ABI_DARWIN
15379 && flag_pic && current_function_uses_pic_offset_table)
15381 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15382 rtx src = machopic_function_base_sym ();
15384 /* Save and restore LR locally around this call (in R0). */
15385 if (!info->lr_save_p)
15386 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15388 emit_insn (gen_load_macho_picbase (src));
15390 emit_move_insn (gen_rtx_REG (Pmode,
15391 RS6000_PIC_OFFSET_TABLE_REGNUM),
15394 if (!info->lr_save_p)
15395 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15400 /* Write function prologue. */
15403 rs6000_output_function_prologue (FILE *file,
15404 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15406 rs6000_stack_t *info = rs6000_stack_info ();
15408 if (TARGET_DEBUG_STACK)
15409 debug_stack_info (info);
15411 /* Write .extern for any function we will call to save and restore
15413 if (info->first_fp_reg_save < 64
15414 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15415 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15416 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15417 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15418 RESTORE_FP_SUFFIX);
15420 /* Write .extern for AIX common mode routines, if needed. */
15421 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15423 fputs ("\t.extern __mulh\n", file);
15424 fputs ("\t.extern __mull\n", file);
15425 fputs ("\t.extern __divss\n", file);
15426 fputs ("\t.extern __divus\n", file);
15427 fputs ("\t.extern __quoss\n", file);
15428 fputs ("\t.extern __quous\n", file);
15429 common_mode_defined = 1;
15432 if (! HAVE_prologue)
15436 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15437 the "toplevel" insn chain. */
15438 emit_note (NOTE_INSN_DELETED);
15439 rs6000_emit_prologue ();
15440 emit_note (NOTE_INSN_DELETED);
15442 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15446 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15448 INSN_ADDRESSES_NEW (insn, addr);
15453 if (TARGET_DEBUG_STACK)
15454 debug_rtx_list (get_insns (), 100);
15455 final (get_insns (), file, FALSE);
15459 rs6000_pic_labelno++;
15462 /* Emit function epilogue as insns.
15464 At present, dwarf2out_frame_debug_expr doesn't understand
15465 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15466 anywhere in the epilogue. Most of the insns below would in any case
15467 need special notes to explain where r11 is in relation to the stack. */
15470 rs6000_emit_epilogue (int sibcall)
15472 rs6000_stack_t *info;
15473 int restoring_FPRs_inline;
15474 int using_load_multiple;
15475 int using_mtcr_multiple;
15476 int use_backchain_to_restore_sp;
15478 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15479 rtx frame_reg_rtx = sp_reg_rtx;
15480 enum machine_mode reg_mode = Pmode;
15481 int reg_size = TARGET_32BIT ? 4 : 8;
15484 info = rs6000_stack_info ();
15486 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15488 reg_mode = V2SImode;
15492 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15493 && (!TARGET_SPE_ABI
15494 || info->spe_64bit_regs_used == 0)
15495 && info->first_gp_reg_save < 31
15496 && no_global_regs_above (info->first_gp_reg_save));
15497 restoring_FPRs_inline = (sibcall
15498 || current_function_calls_eh_return
15499 || info->first_fp_reg_save == 64
15500 || FP_SAVE_INLINE (info->first_fp_reg_save));
15501 use_backchain_to_restore_sp = (frame_pointer_needed
15502 || current_function_calls_alloca
15503 || info->total_size > 32767);
15504 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15505 || rs6000_cpu == PROCESSOR_PPC603
15506 || rs6000_cpu == PROCESSOR_PPC750
15509 if (WORLD_SAVE_P (info))
15513 const char *alloc_rname;
15516 /* eh_rest_world_r10 will return to the location saved in the LR
15517 stack slot (which is not likely to be our caller.)
15518 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15519 rest_world is similar, except any R10 parameter is ignored.
15520 The exception-handling stuff that was here in 2.95 is no
15521 longer necessary. */
15525 + 32 - info->first_gp_reg_save
15526 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15527 + 63 + 1 - info->first_fp_reg_save);
15529 strcpy (rname, ((current_function_calls_eh_return) ?
15530 "*eh_rest_world_r10" : "*rest_world"));
15531 alloc_rname = ggc_strdup (rname);
15534 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15535 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15536 gen_rtx_REG (Pmode,
15539 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15540 /* The instruction pattern requires a clobber here;
15541 it is shared with the restVEC helper. */
15543 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15546 /* CR register traditionally saved as CR2. */
15547 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15548 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15549 GEN_INT (info->cr_save_offset));
15550 rtx mem = gen_frame_mem (reg_mode, addr);
15552 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15555 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15557 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15558 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15559 GEN_INT (info->gp_save_offset
15561 rtx mem = gen_frame_mem (reg_mode, addr);
15563 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15565 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15567 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15568 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15569 GEN_INT (info->altivec_save_offset
15571 rtx mem = gen_frame_mem (V4SImode, addr);
15573 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15575 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15577 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15578 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15579 GEN_INT (info->fp_save_offset
15581 rtx mem = gen_frame_mem (DFmode, addr);
15583 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15586 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15588 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15590 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15592 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15594 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15595 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15600 /* Set sp_offset based on the stack push from the prologue. */
15601 if (info->total_size < 32767)
15602 sp_offset = info->total_size;
15604 /* Restore AltiVec registers if needed. */
15605 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15609 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15610 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15612 rtx addr, areg, mem;
15614 areg = gen_rtx_REG (Pmode, 0);
15616 (areg, GEN_INT (info->altivec_save_offset
15618 + 16 * (i - info->first_altivec_reg_save)));
15620 /* AltiVec addressing mode is [reg+reg]. */
15621 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15622 mem = gen_frame_mem (V4SImode, addr);
15624 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15628 /* Restore VRSAVE if needed. */
15629 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15630 && info->vrsave_mask != 0)
15632 rtx addr, mem, reg;
15634 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15635 GEN_INT (info->vrsave_save_offset + sp_offset));
15636 mem = gen_frame_mem (SImode, addr);
15637 reg = gen_rtx_REG (SImode, 12);
15638 emit_move_insn (reg, mem);
15640 emit_insn (generate_set_vrsave (reg, info, 1));
15645 /* If we have a frame pointer, a call to alloca, or a large stack
15646 frame, restore the old stack pointer using the backchain. Otherwise,
15647 we know what size to update it with. */
15648 if (use_backchain_to_restore_sp)
15650 /* Under V.4, don't reset the stack pointer until after we're done
15651 loading the saved registers. */
15652 if (DEFAULT_ABI == ABI_V4)
15653 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15655 emit_move_insn (frame_reg_rtx,
15656 gen_rtx_MEM (Pmode, sp_reg_rtx));
15658 else if (info->push_p)
15660 if (DEFAULT_ABI == ABI_V4
15661 || current_function_calls_eh_return)
15662 sp_offset = info->total_size;
15665 emit_insn (TARGET_32BIT
15666 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15667 GEN_INT (info->total_size))
15668 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15669 GEN_INT (info->total_size)));
15673 /* Get the old lr if we saved it. */
15674 if (info->lr_save_p)
15676 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15677 info->lr_save_offset + sp_offset);
15679 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15682 /* Get the old cr if we saved it. */
15683 if (info->cr_save_p)
15685 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15686 GEN_INT (info->cr_save_offset + sp_offset));
15687 rtx mem = gen_frame_mem (SImode, addr);
15689 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15692 /* Set LR here to try to overlap restores below. */
15693 if (info->lr_save_p)
15694 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
15695 gen_rtx_REG (Pmode, 0));
15697 /* Load exception handler data registers, if needed. */
15698 if (current_function_calls_eh_return)
15700 unsigned int i, regno;
15704 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15705 GEN_INT (sp_offset + 5 * reg_size));
15706 rtx mem = gen_frame_mem (reg_mode, addr);
15708 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15715 regno = EH_RETURN_DATA_REGNO (i);
15716 if (regno == INVALID_REGNUM)
15719 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15720 info->ehrd_offset + sp_offset
15721 + reg_size * (int) i);
15723 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15727 /* Restore GPRs. This is done as a PARALLEL if we are using
15728 the load-multiple instructions. */
15729 if (using_load_multiple)
15732 p = rtvec_alloc (32 - info->first_gp_reg_save);
15733 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15735 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15736 GEN_INT (info->gp_save_offset
15739 rtx mem = gen_frame_mem (reg_mode, addr);
15742 gen_rtx_SET (VOIDmode,
15743 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15746 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15748 else if (TARGET_SPE_ABI
15749 && info->spe_64bit_regs_used != 0
15750 && info->first_gp_reg_save != 32)
15752 rtx spe_save_area_ptr;
15753 /* Determine whether we can address all of the registers that need
15754 to be saved with an offset from the stack pointer that fits in
15755 the small const field for SPE memory instructions. */
15756 int spe_regs_addressable_via_sp
15757 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15758 + (32 - info->first_gp_reg_save - 1) * reg_size);
15761 if (spe_regs_addressable_via_sp)
15763 spe_save_area_ptr = frame_reg_rtx;
15764 spe_offset = info->spe_gp_save_offset + sp_offset;
15768 /* Make r11 point to the start of the SPE save area. We worried about
15769 not clobbering it when we were saving registers in the prologue.
15770 There's no need to worry here because the static chain is passed
15771 anew to every function. */
15772 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15774 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15775 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15780 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15781 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15783 rtx offset, addr, mem;
15785 /* We're doing all this to ensure that the immediate offset
15786 fits into the immediate field of 'evldd'. */
15787 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
15789 offset = GEN_INT (spe_offset + reg_size * i);
15790 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15791 mem = gen_rtx_MEM (V2SImode, addr);
15793 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15798 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15799 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15801 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15802 GEN_INT (info->gp_save_offset
15805 rtx mem = gen_frame_mem (reg_mode, addr);
15807 emit_move_insn (gen_rtx_REG (reg_mode,
15808 info->first_gp_reg_save + i), mem);
15811 /* Restore fpr's if we need to do it without calling a function. */
15812 if (restoring_FPRs_inline)
15813 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15814 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15815 && ! call_used_regs[info->first_fp_reg_save+i]))
15818 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15819 GEN_INT (info->fp_save_offset
15822 mem = gen_frame_mem (DFmode, addr);
15824 emit_move_insn (gen_rtx_REG (DFmode,
15825 info->first_fp_reg_save + i),
15829 /* If we saved cr, restore it here. Just those that were used. */
15830 if (info->cr_save_p)
15832 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15835 if (using_mtcr_multiple)
15837 for (i = 0; i < 8; i++)
15838 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15840 gcc_assert (count);
15843 if (using_mtcr_multiple && count > 1)
15848 p = rtvec_alloc (count);
15851 for (i = 0; i < 8; i++)
15852 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15854 rtvec r = rtvec_alloc (2);
15855 RTVEC_ELT (r, 0) = r12_rtx;
15856 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15857 RTVEC_ELT (p, ndx) =
15858 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15859 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15862 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15863 gcc_assert (ndx == count);
15866 for (i = 0; i < 8; i++)
15867 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15869 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15875 /* If this is V.4, unwind the stack pointer after all of the loads
15877 if (frame_reg_rtx != sp_reg_rtx)
15879 /* This blockage is needed so that sched doesn't decide to move
15880 the sp change before the register restores. */
15881 rs6000_emit_stack_tie ();
15883 && info->spe_64bit_regs_used != 0
15884 && info->first_gp_reg_save != 32)
15885 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
15886 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
15888 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15890 else if (sp_offset != 0)
15891 emit_insn (TARGET_32BIT
15892 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15893 GEN_INT (sp_offset))
15894 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15895 GEN_INT (sp_offset)));
15897 if (current_function_calls_eh_return)
15899 rtx sa = EH_RETURN_STACKADJ_RTX;
15900 emit_insn (TARGET_32BIT
15901 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15902 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15908 if (! restoring_FPRs_inline)
15909 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15911 p = rtvec_alloc (2);
15913 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15914 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15915 gen_rtx_REG (Pmode,
15918 /* If we have to restore more than two FP registers, branch to the
15919 restore function. It will return to our caller. */
15920 if (! restoring_FPRs_inline)
15924 const char *alloc_rname;
15926 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15927 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15928 alloc_rname = ggc_strdup (rname);
15929 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15930 gen_rtx_SYMBOL_REF (Pmode,
15933 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15936 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15937 GEN_INT (info->fp_save_offset + 8*i));
15938 mem = gen_frame_mem (DFmode, addr);
15940 RTVEC_ELT (p, i+3) =
15941 gen_rtx_SET (VOIDmode,
15942 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15947 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15951 /* Write function epilogue. */
15954 rs6000_output_function_epilogue (FILE *file,
15955 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15957 if (! HAVE_epilogue)
15959 rtx insn = get_last_insn ();
15960 /* If the last insn was a BARRIER, we don't have to write anything except
15961 the trace table. */
15962 if (GET_CODE (insn) == NOTE)
15963 insn = prev_nonnote_insn (insn);
15964 if (insn == 0 || GET_CODE (insn) != BARRIER)
15966 /* This is slightly ugly, but at least we don't have two
15967 copies of the epilogue-emitting code. */
15970 /* A NOTE_INSN_DELETED is supposed to be at the start
15971 and end of the "toplevel" insn chain. */
15972 emit_note (NOTE_INSN_DELETED);
15973 rs6000_emit_epilogue (FALSE);
15974 emit_note (NOTE_INSN_DELETED);
15976 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15980 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15982 INSN_ADDRESSES_NEW (insn, addr);
15987 if (TARGET_DEBUG_STACK)
15988 debug_rtx_list (get_insns (), 100);
15989 final (get_insns (), file, FALSE);
15995 macho_branch_islands ();
15996 /* Mach-O doesn't support labels at the end of objects, so if
15997 it looks like we might want one, insert a NOP. */
15999 rtx insn = get_last_insn ();
16002 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
16003 insn = PREV_INSN (insn);
16007 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
16008 fputs ("\tnop\n", file);
16012 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16015 We don't output a traceback table if -finhibit-size-directive was
16016 used. The documentation for -finhibit-size-directive reads
16017 ``don't output a @code{.size} assembler directive, or anything
16018 else that would cause trouble if the function is split in the
16019 middle, and the two halves are placed at locations far apart in
16020 memory.'' The traceback table has this property, since it
16021 includes the offset from the start of the function to the
16022 traceback table itself.
16024 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16025 different traceback table. */
16026 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
16027 && rs6000_traceback != traceback_none && !current_function_is_thunk)
16029 const char *fname = NULL;
16030 const char *language_string = lang_hooks.name;
16031 int fixed_parms = 0, float_parms = 0, parm_info = 0;
16033 int optional_tbtab;
16034 rs6000_stack_t *info = rs6000_stack_info ();
16036 if (rs6000_traceback == traceback_full)
16037 optional_tbtab = 1;
16038 else if (rs6000_traceback == traceback_part)
16039 optional_tbtab = 0;
16041 optional_tbtab = !optimize_size && !TARGET_ELF;
16043 if (optional_tbtab)
16045 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
16046 while (*fname == '.') /* V.4 encodes . in the name */
16049 /* Need label immediately before tbtab, so we can compute
16050 its offset from the function start. */
16051 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16052 ASM_OUTPUT_LABEL (file, fname);
16055 /* The .tbtab pseudo-op can only be used for the first eight
16056 expressions, since it can't handle the possibly variable
16057 length fields that follow. However, if you omit the optional
16058 fields, the assembler outputs zeros for all optional fields
16059 anyways, giving each variable length field is minimum length
16060 (as defined in sys/debug.h). Thus we can not use the .tbtab
16061 pseudo-op at all. */
16063 /* An all-zero word flags the start of the tbtab, for debuggers
16064 that have to find it by searching forward from the entry
16065 point or from the current pc. */
16066 fputs ("\t.long 0\n", file);
16068 /* Tbtab format type. Use format type 0. */
16069 fputs ("\t.byte 0,", file);
16071 /* Language type. Unfortunately, there does not seem to be any
16072 official way to discover the language being compiled, so we
16073 use language_string.
16074 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16075 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16076 a number, so for now use 9. */
16077 if (! strcmp (language_string, "GNU C"))
16079 else if (! strcmp (language_string, "GNU F77")
16080 || ! strcmp (language_string, "GNU F95"))
16082 else if (! strcmp (language_string, "GNU Pascal"))
16084 else if (! strcmp (language_string, "GNU Ada"))
16086 else if (! strcmp (language_string, "GNU C++")
16087 || ! strcmp (language_string, "GNU Objective-C++"))
16089 else if (! strcmp (language_string, "GNU Java"))
16091 else if (! strcmp (language_string, "GNU Objective-C"))
16094 gcc_unreachable ();
16095 fprintf (file, "%d,", i);
16097 /* 8 single bit fields: global linkage (not set for C extern linkage,
16098 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16099 from start of procedure stored in tbtab, internal function, function
16100 has controlled storage, function has no toc, function uses fp,
16101 function logs/aborts fp operations. */
16102 /* Assume that fp operations are used if any fp reg must be saved. */
16103 fprintf (file, "%d,",
16104 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16106 /* 6 bitfields: function is interrupt handler, name present in
16107 proc table, function calls alloca, on condition directives
16108 (controls stack walks, 3 bits), saves condition reg, saves
16110 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16111 set up as a frame pointer, even when there is no alloca call. */
16112 fprintf (file, "%d,",
16113 ((optional_tbtab << 6)
16114 | ((optional_tbtab & frame_pointer_needed) << 5)
16115 | (info->cr_save_p << 1)
16116 | (info->lr_save_p)));
16118 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16120 fprintf (file, "%d,",
16121 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16123 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16124 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16126 if (optional_tbtab)
16128 /* Compute the parameter info from the function decl argument
16131 int next_parm_info_bit = 31;
16133 for (decl = DECL_ARGUMENTS (current_function_decl);
16134 decl; decl = TREE_CHAIN (decl))
16136 rtx parameter = DECL_INCOMING_RTL (decl);
16137 enum machine_mode mode = GET_MODE (parameter);
16139 if (GET_CODE (parameter) == REG)
16141 if (SCALAR_FLOAT_MODE_P (mode))
16161 gcc_unreachable ();
16164 /* If only one bit will fit, don't or in this entry. */
16165 if (next_parm_info_bit > 0)
16166 parm_info |= (bits << (next_parm_info_bit - 1));
16167 next_parm_info_bit -= 2;
16171 fixed_parms += ((GET_MODE_SIZE (mode)
16172 + (UNITS_PER_WORD - 1))
16174 next_parm_info_bit -= 1;
16180 /* Number of fixed point parameters. */
16181 /* This is actually the number of words of fixed point parameters; thus
16182 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16183 fprintf (file, "%d,", fixed_parms);
16185 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16187 /* This is actually the number of fp registers that hold parameters;
16188 and thus the maximum value is 13. */
16189 /* Set parameters on stack bit if parameters are not in their original
16190 registers, regardless of whether they are on the stack? Xlc
16191 seems to set the bit when not optimizing. */
16192 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16194 if (! optional_tbtab)
16197 /* Optional fields follow. Some are variable length. */
16199 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16200 11 double float. */
16201 /* There is an entry for each parameter in a register, in the order that
16202 they occur in the parameter list. Any intervening arguments on the
16203 stack are ignored. If the list overflows a long (max possible length
16204 34 bits) then completely leave off all elements that don't fit. */
16205 /* Only emit this long if there was at least one parameter. */
16206 if (fixed_parms || float_parms)
16207 fprintf (file, "\t.long %d\n", parm_info);
16209 /* Offset from start of code to tb table. */
16210 fputs ("\t.long ", file);
16211 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16213 RS6000_OUTPUT_BASENAME (file, fname);
16215 assemble_name (file, fname);
16217 rs6000_output_function_entry (file, fname);
16220 /* Interrupt handler mask. */
16221 /* Omit this long, since we never set the interrupt handler bit
16224 /* Number of CTL (controlled storage) anchors. */
16225 /* Omit this long, since the has_ctl bit is never set above. */
16227 /* Displacement into stack of each CTL anchor. */
16228 /* Omit this list of longs, because there are no CTL anchors. */
16230 /* Length of function name. */
16233 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16235 /* Function name. */
16236 assemble_string (fname, strlen (fname));
16238 /* Register for alloca automatic storage; this is always reg 31.
16239 Only emit this if the alloca bit was set above. */
16240 if (frame_pointer_needed)
16241 fputs ("\t.byte 31\n", file);
16243 fputs ("\t.align 2\n", file);
16247 /* A C compound statement that outputs the assembler code for a thunk
16248 function, used to implement C++ virtual function calls with
16249 multiple inheritance. The thunk acts as a wrapper around a virtual
16250 function, adjusting the implicit object parameter before handing
16251 control off to the real function.
16253 First, emit code to add the integer DELTA to the location that
16254 contains the incoming first argument. Assume that this argument
16255 contains a pointer, and is the one used to pass the `this' pointer
16256 in C++. This is the incoming argument *before* the function
16257 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16258 values of all other incoming arguments.
16260 After the addition, emit code to jump to FUNCTION, which is a
16261 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16262 not touch the return address. Hence returning from FUNCTION will
16263 return to whoever called the current `thunk'.
16265 The effect must be as if FUNCTION had been called directly with the
16266 adjusted first argument. This macro is responsible for emitting
16267 all of the code for a thunk function; output_function_prologue()
16268 and output_function_epilogue() are not invoked.
16270 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16271 been extracted from it.) It might possibly be useful on some
16272 targets, but probably not.
16274 If you do not define this macro, the target-independent code in the
16275 C++ frontend will generate a less efficient heavyweight thunk that
16276 calls FUNCTION instead of jumping to it. The generic approach does
16277 not support varargs. */
16280 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16281 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16284 rtx this, insn, funexp;
16286 reload_completed = 1;
16287 epilogue_completed = 1;
16289 /* Mark the end of the (empty) prologue. */
16290 emit_note (NOTE_INSN_PROLOGUE_END);
16292 /* Find the "this" pointer. If the function returns a structure,
16293 the structure return pointer is in r3. */
16294 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16295 this = gen_rtx_REG (Pmode, 4);
16297 this = gen_rtx_REG (Pmode, 3);
16299 /* Apply the constant offset, if required. */
16302 rtx delta_rtx = GEN_INT (delta);
16303 emit_insn (TARGET_32BIT
16304 ? gen_addsi3 (this, this, delta_rtx)
16305 : gen_adddi3 (this, this, delta_rtx));
16308 /* Apply the offset from the vtable, if required. */
16311 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16312 rtx tmp = gen_rtx_REG (Pmode, 12);
16314 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16315 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16317 emit_insn (TARGET_32BIT
16318 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16319 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16320 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16324 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16326 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16328 emit_insn (TARGET_32BIT
16329 ? gen_addsi3 (this, this, tmp)
16330 : gen_adddi3 (this, this, tmp));
16333 /* Generate a tail call to the target function. */
16334 if (!TREE_USED (function))
16336 assemble_external (function);
16337 TREE_USED (function) = 1;
16339 funexp = XEXP (DECL_RTL (function), 0);
16340 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16343 if (MACHOPIC_INDIRECT)
16344 funexp = machopic_indirect_call_target (funexp);
16347 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16348 generate sibcall RTL explicitly. */
16349 insn = emit_call_insn (
16350 gen_rtx_PARALLEL (VOIDmode,
16352 gen_rtx_CALL (VOIDmode,
16353 funexp, const0_rtx),
16354 gen_rtx_USE (VOIDmode, const0_rtx),
16355 gen_rtx_USE (VOIDmode,
16356 gen_rtx_REG (SImode,
16358 gen_rtx_RETURN (VOIDmode))));
16359 SIBLING_CALL_P (insn) = 1;
16362 /* Run just enough of rest_of_compilation to get the insns emitted.
16363 There's not really enough bulk here to make other passes such as
16364 instruction scheduling worth while. Note that use_thunk calls
16365 assemble_start_function and assemble_end_function. */
16366 insn = get_insns ();
16367 insn_locators_alloc ();
16368 shorten_branches (insn);
16369 final_start_function (insn, file, 1);
16370 final (insn, file, 1);
16371 final_end_function ();
16373 reload_completed = 0;
16374 epilogue_completed = 0;
16377 /* A quick summary of the various types of 'constant-pool tables'
16380 Target Flags Name One table per
16381 AIX (none) AIX TOC object file
16382 AIX -mfull-toc AIX TOC object file
16383 AIX -mminimal-toc AIX minimal TOC translation unit
16384 SVR4/EABI (none) SVR4 SDATA object file
16385 SVR4/EABI -fpic SVR4 pic object file
16386 SVR4/EABI -fPIC SVR4 PIC translation unit
16387 SVR4/EABI -mrelocatable EABI TOC function
16388 SVR4/EABI -maix AIX TOC object file
16389 SVR4/EABI -maix -mminimal-toc
16390 AIX minimal TOC translation unit
16392 Name Reg. Set by entries contains:
16393 made by addrs? fp? sum?
16395 AIX TOC 2 crt0 as Y option option
16396 AIX minimal TOC 30 prolog gcc Y Y option
16397 SVR4 SDATA 13 crt0 gcc N Y N
16398 SVR4 pic 30 prolog ld Y not yet N
16399 SVR4 PIC 30 prolog gcc Y option option
16400 EABI TOC 30 prolog gcc Y option option
16404 /* Hash functions for the hash table. */
16407 rs6000_hash_constant (rtx k)
16409 enum rtx_code code = GET_CODE (k);
16410 enum machine_mode mode = GET_MODE (k);
16411 unsigned result = (code << 3) ^ mode;
16412 const char *format;
16415 format = GET_RTX_FORMAT (code);
16416 flen = strlen (format);
16422 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16425 if (mode != VOIDmode)
16426 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16438 for (; fidx < flen; fidx++)
16439 switch (format[fidx])
16444 const char *str = XSTR (k, fidx);
16445 len = strlen (str);
16446 result = result * 613 + len;
16447 for (i = 0; i < len; i++)
16448 result = result * 613 + (unsigned) str[i];
16453 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16457 result = result * 613 + (unsigned) XINT (k, fidx);
16460 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16461 result = result * 613 + (unsigned) XWINT (k, fidx);
16465 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16466 result = result * 613 + (unsigned) (XWINT (k, fidx)
16473 gcc_unreachable ();
16480 toc_hash_function (const void *hash_entry)
16482 const struct toc_hash_struct *thc =
16483 (const struct toc_hash_struct *) hash_entry;
16484 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16487 /* Compare H1 and H2 for equivalence. */
16490 toc_hash_eq (const void *h1, const void *h2)
16492 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16493 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16495 if (((const struct toc_hash_struct *) h1)->key_mode
16496 != ((const struct toc_hash_struct *) h2)->key_mode)
16499 return rtx_equal_p (r1, r2);
16502 /* These are the names given by the C++ front-end to vtables, and
16503 vtable-like objects. Ideally, this logic should not be here;
16504 instead, there should be some programmatic way of inquiring as
16505 to whether or not an object is a vtable. */
16507 #define VTABLE_NAME_P(NAME) \
16508 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16509 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16510 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16511 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16512 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16515 rs6000_output_symbol_ref (FILE *file, rtx x)
16517 /* Currently C++ toc references to vtables can be emitted before it
16518 is decided whether the vtable is public or private. If this is
16519 the case, then the linker will eventually complain that there is
16520 a reference to an unknown section. Thus, for vtables only,
16521 we emit the TOC reference to reference the symbol and not the
16523 const char *name = XSTR (x, 0);
16525 if (VTABLE_NAME_P (name))
16527 RS6000_OUTPUT_BASENAME (file, name);
16530 assemble_name (file, name);
16533 /* Output a TOC entry. We derive the entry name from what is being
16537 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16540 const char *name = buf;
16541 const char *real_name;
16543 HOST_WIDE_INT offset = 0;
16545 gcc_assert (!TARGET_NO_TOC);
16547 /* When the linker won't eliminate them, don't output duplicate
16548 TOC entries (this happens on AIX if there is any kind of TOC,
16549 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16551 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16553 struct toc_hash_struct *h;
16556 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16557 time because GGC is not initialized at that point. */
16558 if (toc_hash_table == NULL)
16559 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16560 toc_hash_eq, NULL);
16562 h = ggc_alloc (sizeof (*h));
16564 h->key_mode = mode;
16565 h->labelno = labelno;
16567 found = htab_find_slot (toc_hash_table, h, 1);
16568 if (*found == NULL)
16570 else /* This is indeed a duplicate.
16571 Set this label equal to that label. */
16573 fputs ("\t.set ", file);
16574 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16575 fprintf (file, "%d,", labelno);
16576 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16577 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16583 /* If we're going to put a double constant in the TOC, make sure it's
16584 aligned properly when strict alignment is on. */
16585 if (GET_CODE (x) == CONST_DOUBLE
16586 && STRICT_ALIGNMENT
16587 && GET_MODE_BITSIZE (mode) >= 64
16588 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16589 ASM_OUTPUT_ALIGN (file, 3);
16592 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16594 /* Handle FP constants specially. Note that if we have a minimal
16595 TOC, things we put here aren't actually in the TOC, so we can allow
16597 if (GET_CODE (x) == CONST_DOUBLE &&
16598 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16600 REAL_VALUE_TYPE rv;
16603 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16604 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16605 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16607 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16611 if (TARGET_MINIMAL_TOC)
16612 fputs (DOUBLE_INT_ASM_OP, file);
16614 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16615 k[0] & 0xffffffff, k[1] & 0xffffffff,
16616 k[2] & 0xffffffff, k[3] & 0xffffffff);
16617 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16618 k[0] & 0xffffffff, k[1] & 0xffffffff,
16619 k[2] & 0xffffffff, k[3] & 0xffffffff);
16624 if (TARGET_MINIMAL_TOC)
16625 fputs ("\t.long ", file);
16627 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16628 k[0] & 0xffffffff, k[1] & 0xffffffff,
16629 k[2] & 0xffffffff, k[3] & 0xffffffff);
16630 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16631 k[0] & 0xffffffff, k[1] & 0xffffffff,
16632 k[2] & 0xffffffff, k[3] & 0xffffffff);
16636 else if (GET_CODE (x) == CONST_DOUBLE &&
16637 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16639 REAL_VALUE_TYPE rv;
16642 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16644 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16645 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16647 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16651 if (TARGET_MINIMAL_TOC)
16652 fputs (DOUBLE_INT_ASM_OP, file);
16654 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16655 k[0] & 0xffffffff, k[1] & 0xffffffff);
16656 fprintf (file, "0x%lx%08lx\n",
16657 k[0] & 0xffffffff, k[1] & 0xffffffff);
16662 if (TARGET_MINIMAL_TOC)
16663 fputs ("\t.long ", file);
16665 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16666 k[0] & 0xffffffff, k[1] & 0xffffffff);
16667 fprintf (file, "0x%lx,0x%lx\n",
16668 k[0] & 0xffffffff, k[1] & 0xffffffff);
16672 else if (GET_CODE (x) == CONST_DOUBLE &&
16673 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16675 REAL_VALUE_TYPE rv;
16678 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16679 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16680 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16682 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16686 if (TARGET_MINIMAL_TOC)
16687 fputs (DOUBLE_INT_ASM_OP, file);
16689 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16690 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16695 if (TARGET_MINIMAL_TOC)
16696 fputs ("\t.long ", file);
16698 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16699 fprintf (file, "0x%lx\n", l & 0xffffffff);
16703 else if (GET_MODE (x) == VOIDmode
16704 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16706 unsigned HOST_WIDE_INT low;
16707 HOST_WIDE_INT high;
16709 if (GET_CODE (x) == CONST_DOUBLE)
16711 low = CONST_DOUBLE_LOW (x);
16712 high = CONST_DOUBLE_HIGH (x);
16715 #if HOST_BITS_PER_WIDE_INT == 32
16718 high = (low & 0x80000000) ? ~0 : 0;
16722 low = INTVAL (x) & 0xffffffff;
16723 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16727 /* TOC entries are always Pmode-sized, but since this
16728 is a bigendian machine then if we're putting smaller
16729 integer constants in the TOC we have to pad them.
16730 (This is still a win over putting the constants in
16731 a separate constant pool, because then we'd have
16732 to have both a TOC entry _and_ the actual constant.)
16734 For a 32-bit target, CONST_INT values are loaded and shifted
16735 entirely within `low' and can be stored in one TOC entry. */
16737 /* It would be easy to make this work, but it doesn't now. */
16738 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16740 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16742 #if HOST_BITS_PER_WIDE_INT == 32
16743 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16744 POINTER_SIZE, &low, &high, 0);
16747 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16748 high = (HOST_WIDE_INT) low >> 32;
16755 if (TARGET_MINIMAL_TOC)
16756 fputs (DOUBLE_INT_ASM_OP, file);
16758 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16759 (long) high & 0xffffffff, (long) low & 0xffffffff);
16760 fprintf (file, "0x%lx%08lx\n",
16761 (long) high & 0xffffffff, (long) low & 0xffffffff);
16766 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16768 if (TARGET_MINIMAL_TOC)
16769 fputs ("\t.long ", file);
16771 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16772 (long) high & 0xffffffff, (long) low & 0xffffffff);
16773 fprintf (file, "0x%lx,0x%lx\n",
16774 (long) high & 0xffffffff, (long) low & 0xffffffff);
16778 if (TARGET_MINIMAL_TOC)
16779 fputs ("\t.long ", file);
16781 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16782 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16788 if (GET_CODE (x) == CONST)
16790 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16792 base = XEXP (XEXP (x, 0), 0);
16793 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16796 switch (GET_CODE (base))
16799 name = XSTR (base, 0);
16803 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16804 CODE_LABEL_NUMBER (XEXP (base, 0)));
16808 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16812 gcc_unreachable ();
16815 real_name = (*targetm.strip_name_encoding) (name);
16816 if (TARGET_MINIMAL_TOC)
16817 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16820 fprintf (file, "\t.tc %s", real_name);
16823 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16825 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16827 fputs ("[TC],", file);
16830 /* Currently C++ toc references to vtables can be emitted before it
16831 is decided whether the vtable is public or private. If this is
16832 the case, then the linker will eventually complain that there is
16833 a TOC reference to an unknown section. Thus, for vtables only,
16834 we emit the TOC reference to reference the symbol and not the
16836 if (VTABLE_NAME_P (name))
16838 RS6000_OUTPUT_BASENAME (file, name);
16840 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16841 else if (offset > 0)
16842 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16845 output_addr_const (file, x);
16849 /* Output an assembler pseudo-op to write an ASCII string of N characters
16850 starting at P to FILE.
16852 On the RS/6000, we have to do this using the .byte operation and
16853 write out special characters outside the quoted string.
16854 Also, the assembler is broken; very long strings are truncated,
16855 so we must artificially break them up early. */
16858 output_ascii (FILE *file, const char *p, int n)
16861 int i, count_string;
16862 const char *for_string = "\t.byte \"";
16863 const char *for_decimal = "\t.byte ";
16864 const char *to_close = NULL;
16867 for (i = 0; i < n; i++)
16870 if (c >= ' ' && c < 0177)
16873 fputs (for_string, file);
16876 /* Write two quotes to get one. */
16884 for_decimal = "\"\n\t.byte ";
16888 if (count_string >= 512)
16890 fputs (to_close, file);
16892 for_string = "\t.byte \"";
16893 for_decimal = "\t.byte ";
16901 fputs (for_decimal, file);
16902 fprintf (file, "%d", c);
16904 for_string = "\n\t.byte \"";
16905 for_decimal = ", ";
16911 /* Now close the string if we have written one. Then end the line. */
16913 fputs (to_close, file);
16916 /* Generate a unique section name for FILENAME for a section type
16917 represented by SECTION_DESC. Output goes into BUF.
16919 SECTION_DESC can be any string, as long as it is different for each
16920 possible section type.
16922 We name the section in the same manner as xlc. The name begins with an
16923 underscore followed by the filename (after stripping any leading directory
16924 names) with the last period replaced by the string SECTION_DESC. If
16925 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16929 rs6000_gen_section_name (char **buf, const char *filename,
16930 const char *section_desc)
16932 const char *q, *after_last_slash, *last_period = 0;
16936 after_last_slash = filename;
16937 for (q = filename; *q; q++)
16940 after_last_slash = q + 1;
16941 else if (*q == '.')
16945 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16946 *buf = (char *) xmalloc (len);
16951 for (q = after_last_slash; *q; q++)
16953 if (q == last_period)
16955 strcpy (p, section_desc);
16956 p += strlen (section_desc);
16960 else if (ISALNUM (*q))
16964 if (last_period == 0)
16965 strcpy (p, section_desc);
16970 /* Emit profile function. */
16973 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16975 /* Non-standard profiling for kernels, which just saves LR then calls
16976 _mcount without worrying about arg saves. The idea is to change
16977 the function prologue as little as possible as it isn't easy to
16978 account for arg save/restore code added just for _mcount. */
16979 if (TARGET_PROFILE_KERNEL)
16982 if (DEFAULT_ABI == ABI_AIX)
16984 #ifndef NO_PROFILE_COUNTERS
16985 # define NO_PROFILE_COUNTERS 0
16987 if (NO_PROFILE_COUNTERS)
16988 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16992 const char *label_name;
16995 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16996 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16997 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16999 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
17003 else if (DEFAULT_ABI == ABI_DARWIN)
17005 const char *mcount_name = RS6000_MCOUNT;
17006 int caller_addr_regno = LR_REGNO;
17008 /* Be conservative and always set this, at least for now. */
17009 current_function_uses_pic_offset_table = 1;
17012 /* For PIC code, set up a stub and collect the caller's address
17013 from r0, which is where the prologue puts it. */
17014 if (MACHOPIC_INDIRECT
17015 && current_function_uses_pic_offset_table)
17016 caller_addr_regno = 0;
17018 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
17020 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
17024 /* Write function profiler code. */
17027 output_function_profiler (FILE *file, int labelno)
17031 switch (DEFAULT_ABI)
17034 gcc_unreachable ();
17039 warning (0, "no profiling of 64-bit code for this ABI");
17042 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17043 fprintf (file, "\tmflr %s\n", reg_names[0]);
17044 if (NO_PROFILE_COUNTERS)
17046 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17047 reg_names[0], reg_names[1]);
17049 else if (TARGET_SECURE_PLT && flag_pic)
17051 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17052 reg_names[0], reg_names[1]);
17053 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17054 asm_fprintf (file, "\t{cau|addis} %s,%s,",
17055 reg_names[12], reg_names[12]);
17056 assemble_name (file, buf);
17057 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
17058 assemble_name (file, buf);
17059 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
17061 else if (flag_pic == 1)
17063 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
17064 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17065 reg_names[0], reg_names[1]);
17066 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17067 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
17068 assemble_name (file, buf);
17069 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
17071 else if (flag_pic > 1)
17073 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17074 reg_names[0], reg_names[1]);
17075 /* Now, we need to get the address of the label. */
17076 fputs ("\tbcl 20,31,1f\n\t.long ", file);
17077 assemble_name (file, buf);
17078 fputs ("-.\n1:", file);
17079 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
17080 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
17081 reg_names[0], reg_names[11]);
17082 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
17083 reg_names[0], reg_names[0], reg_names[11]);
17087 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
17088 assemble_name (file, buf);
17089 fputs ("@ha\n", file);
17090 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17091 reg_names[0], reg_names[1]);
17092 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
17093 assemble_name (file, buf);
17094 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
17097 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17098 fprintf (file, "\tbl %s%s\n",
17099 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17104 if (!TARGET_PROFILE_KERNEL)
17106 /* Don't do anything, done in output_profile_hook (). */
17110 gcc_assert (!TARGET_32BIT);
17112 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17113 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17115 if (cfun->static_chain_decl != NULL)
17117 asm_fprintf (file, "\tstd %s,24(%s)\n",
17118 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17119 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17120 asm_fprintf (file, "\tld %s,24(%s)\n",
17121 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17124 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17132 /* The following variable value is the last issued insn. */
17134 static rtx last_scheduled_insn;
17136 /* The following variable helps to balance issuing of load and
17137 store instructions */
17139 static int load_store_pendulum;
17141 /* Power4 load update and store update instructions are cracked into a
17142 load or store and an integer insn which are executed in the same cycle.
17143 Branches have their own dispatch slot which does not count against the
17144 GCC issue rate, but it changes the program flow so there are no other
17145 instructions to issue in this cycle. */
17148 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17149 int verbose ATTRIBUTE_UNUSED,
17150 rtx insn, int more)
17152 last_scheduled_insn = insn;
17153 if (GET_CODE (PATTERN (insn)) == USE
17154 || GET_CODE (PATTERN (insn)) == CLOBBER)
17156 cached_can_issue_more = more;
17157 return cached_can_issue_more;
17160 if (insn_terminates_group_p (insn, current_group))
17162 cached_can_issue_more = 0;
17163 return cached_can_issue_more;
17166 /* If no reservation, but reach here */
17167 if (recog_memoized (insn) < 0)
17170 if (rs6000_sched_groups)
17172 if (is_microcoded_insn (insn))
17173 cached_can_issue_more = 0;
17174 else if (is_cracked_insn (insn))
17175 cached_can_issue_more = more > 2 ? more - 2 : 0;
17177 cached_can_issue_more = more - 1;
17179 return cached_can_issue_more;
17182 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17185 cached_can_issue_more = more - 1;
17186 return cached_can_issue_more;
17189 /* Adjust the cost of a scheduling dependency. Return the new cost of
17190 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17193 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17195 enum attr_type attr_type;
17197 if (! recog_memoized (insn))
17200 switch (REG_NOTE_KIND (link))
17204 /* Data dependency; DEP_INSN writes a register that INSN reads
17205 some cycles later. */
17207 /* Separate a load from a narrower, dependent store. */
17208 if (rs6000_sched_groups
17209 && GET_CODE (PATTERN (insn)) == SET
17210 && GET_CODE (PATTERN (dep_insn)) == SET
17211 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17212 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17213 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17214 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17217 attr_type = get_attr_type (insn);
17222 /* Tell the first scheduling pass about the latency between
17223 a mtctr and bctr (and mtlr and br/blr). The first
17224 scheduling pass will not know about this latency since
17225 the mtctr instruction, which has the latency associated
17226 to it, will be generated by reload. */
17227 return TARGET_POWER ? 5 : 4;
17229 /* Leave some extra cycles between a compare and its
17230 dependent branch, to inhibit expensive mispredicts. */
17231 if ((rs6000_cpu_attr == CPU_PPC603
17232 || rs6000_cpu_attr == CPU_PPC604
17233 || rs6000_cpu_attr == CPU_PPC604E
17234 || rs6000_cpu_attr == CPU_PPC620
17235 || rs6000_cpu_attr == CPU_PPC630
17236 || rs6000_cpu_attr == CPU_PPC750
17237 || rs6000_cpu_attr == CPU_PPC7400
17238 || rs6000_cpu_attr == CPU_PPC7450
17239 || rs6000_cpu_attr == CPU_POWER4
17240 || rs6000_cpu_attr == CPU_POWER5
17241 || rs6000_cpu_attr == CPU_CELL)
17242 && recog_memoized (dep_insn)
17243 && (INSN_CODE (dep_insn) >= 0))
17245 switch (get_attr_type (dep_insn))
17249 case TYPE_DELAYED_COMPARE:
17250 case TYPE_IMUL_COMPARE:
17251 case TYPE_LMUL_COMPARE:
17252 case TYPE_FPCOMPARE:
17253 case TYPE_CR_LOGICAL:
17254 case TYPE_DELAYED_CR:
17263 case TYPE_STORE_UX:
17265 case TYPE_FPSTORE_U:
17266 case TYPE_FPSTORE_UX:
17267 if ((rs6000_cpu == PROCESSOR_POWER6)
17268 && recog_memoized (dep_insn)
17269 && (INSN_CODE (dep_insn) >= 0))
17272 if (GET_CODE (PATTERN (insn)) != SET)
17273 /* If this happens, we have to extend this to schedule
17274 optimally. Return default for now. */
17277 /* Adjust the cost for the case where the value written
17278 by a fixed point operation is used as the address
17279 gen value on a store. */
17280 switch (get_attr_type (dep_insn))
17287 if (! store_data_bypass_p (dep_insn, insn))
17291 case TYPE_LOAD_EXT:
17292 case TYPE_LOAD_EXT_U:
17293 case TYPE_LOAD_EXT_UX:
17294 case TYPE_VAR_SHIFT_ROTATE:
17295 case TYPE_VAR_DELAYED_COMPARE:
17297 if (! store_data_bypass_p (dep_insn, insn))
17303 case TYPE_FAST_COMPARE:
17306 case TYPE_INSERT_WORD:
17307 case TYPE_INSERT_DWORD:
17308 case TYPE_FPLOAD_U:
17309 case TYPE_FPLOAD_UX:
17311 case TYPE_STORE_UX:
17312 case TYPE_FPSTORE_U:
17313 case TYPE_FPSTORE_UX:
17315 if (! store_data_bypass_p (dep_insn, insn))
17323 case TYPE_IMUL_COMPARE:
17324 case TYPE_LMUL_COMPARE:
17326 if (! store_data_bypass_p (dep_insn, insn))
17332 if (! store_data_bypass_p (dep_insn, insn))
17338 if (! store_data_bypass_p (dep_insn, insn))
17351 case TYPE_LOAD_EXT:
17352 case TYPE_LOAD_EXT_U:
17353 case TYPE_LOAD_EXT_UX:
17354 if ((rs6000_cpu == PROCESSOR_POWER6)
17355 && recog_memoized (dep_insn)
17356 && (INSN_CODE (dep_insn) >= 0))
17359 /* Adjust the cost for the case where the value written
17360 by a fixed point instruction is used within the address
17361 gen portion of a subsequent load(u)(x) */
17362 switch (get_attr_type (dep_insn))
17369 if (set_to_load_agen (dep_insn, insn))
17373 case TYPE_LOAD_EXT:
17374 case TYPE_LOAD_EXT_U:
17375 case TYPE_LOAD_EXT_UX:
17376 case TYPE_VAR_SHIFT_ROTATE:
17377 case TYPE_VAR_DELAYED_COMPARE:
17379 if (set_to_load_agen (dep_insn, insn))
17385 case TYPE_FAST_COMPARE:
17388 case TYPE_INSERT_WORD:
17389 case TYPE_INSERT_DWORD:
17390 case TYPE_FPLOAD_U:
17391 case TYPE_FPLOAD_UX:
17393 case TYPE_STORE_UX:
17394 case TYPE_FPSTORE_U:
17395 case TYPE_FPSTORE_UX:
17397 if (set_to_load_agen (dep_insn, insn))
17405 case TYPE_IMUL_COMPARE:
17406 case TYPE_LMUL_COMPARE:
17408 if (set_to_load_agen (dep_insn, insn))
17414 if (set_to_load_agen (dep_insn, insn))
17420 if (set_to_load_agen (dep_insn, insn))
17431 if ((rs6000_cpu == PROCESSOR_POWER6)
17432 && recog_memoized (dep_insn)
17433 && (INSN_CODE (dep_insn) >= 0)
17434 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17441 /* Fall out to return default cost. */
17445 case REG_DEP_OUTPUT:
17446 /* Output dependency; DEP_INSN writes a register that INSN writes some
17448 if ((rs6000_cpu == PROCESSOR_POWER6)
17449 && recog_memoized (dep_insn)
17450 && (INSN_CODE (dep_insn) >= 0))
17452 attr_type = get_attr_type (insn);
17457 if (get_attr_type (dep_insn) == TYPE_FP)
17461 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17469 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17474 gcc_unreachable ();
17480 /* The function returns a true if INSN is microcoded.
17481 Return false otherwise. */
17484 is_microcoded_insn (rtx insn)
17486 if (!insn || !INSN_P (insn)
17487 || GET_CODE (PATTERN (insn)) == USE
17488 || GET_CODE (PATTERN (insn)) == CLOBBER)
17491 if (rs6000_cpu_attr == CPU_CELL)
17492 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17494 if (rs6000_sched_groups)
17496 enum attr_type type = get_attr_type (insn);
17497 if (type == TYPE_LOAD_EXT_U
17498 || type == TYPE_LOAD_EXT_UX
17499 || type == TYPE_LOAD_UX
17500 || type == TYPE_STORE_UX
17501 || type == TYPE_MFCR)
17508 /* The function returns true if INSN is cracked into 2 instructions
17509 by the processor (and therefore occupies 2 issue slots). */
17512 is_cracked_insn (rtx insn)
17514 if (!insn || !INSN_P (insn)
17515 || GET_CODE (PATTERN (insn)) == USE
17516 || GET_CODE (PATTERN (insn)) == CLOBBER)
17519 if (rs6000_sched_groups)
17521 enum attr_type type = get_attr_type (insn);
17522 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17523 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17524 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17525 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17526 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17527 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17528 || type == TYPE_IDIV || type == TYPE_LDIV
17529 || type == TYPE_INSERT_WORD)
17536 /* The function returns true if INSN can be issued only from
17537 the branch slot. */
17540 is_branch_slot_insn (rtx insn)
17542 if (!insn || !INSN_P (insn)
17543 || GET_CODE (PATTERN (insn)) == USE
17544 || GET_CODE (PATTERN (insn)) == CLOBBER)
17547 if (rs6000_sched_groups)
17549 enum attr_type type = get_attr_type (insn);
17550 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17558 /* The function returns true if out_inst sets a value that is
17559 used in the address generation computation of in_insn */
17561 set_to_load_agen (rtx out_insn, rtx in_insn)
17563 rtx out_set, in_set;
17565 /* For performance reasons, only handle the simple case where
17566 both loads are a single_set. */
17567 out_set = single_set (out_insn);
17570 in_set = single_set (in_insn);
17572 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17578 /* The function returns true if the target storage location of
17579 out_insn is adjacent to the target storage location of in_insn */
17580 /* Return 1 if memory locations are adjacent. */
17583 adjacent_mem_locations (rtx insn1, rtx insn2)
17586 rtx a = get_store_dest (PATTERN (insn1));
17587 rtx b = get_store_dest (PATTERN (insn2));
17589 if ((GET_CODE (XEXP (a, 0)) == REG
17590 || (GET_CODE (XEXP (a, 0)) == PLUS
17591 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17592 && (GET_CODE (XEXP (b, 0)) == REG
17593 || (GET_CODE (XEXP (b, 0)) == PLUS
17594 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17596 HOST_WIDE_INT val0 = 0, val1 = 0;
17600 if (GET_CODE (XEXP (a, 0)) == PLUS)
17602 reg0 = XEXP (XEXP (a, 0), 0);
17603 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17606 reg0 = XEXP (a, 0);
17608 if (GET_CODE (XEXP (b, 0)) == PLUS)
17610 reg1 = XEXP (XEXP (b, 0), 0);
17611 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17614 reg1 = XEXP (b, 0);
17616 val_diff = val1 - val0;
17618 return ((REGNO (reg0) == REGNO (reg1))
17619 && (val_diff == INTVAL (MEM_SIZE (a))
17620 || val_diff == -INTVAL (MEM_SIZE (b))));
17626 /* A C statement (sans semicolon) to update the integer scheduling
17627 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17628 INSN earlier, reduce the priority to execute INSN later. Do not
17629 define this macro if you do not need to adjust the scheduling
17630 priorities of insns. */
17633 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17635 /* On machines (like the 750) which have asymmetric integer units,
17636 where one integer unit can do multiply and divides and the other
17637 can't, reduce the priority of multiply/divide so it is scheduled
17638 before other integer operations. */
17641 if (! INSN_P (insn))
17644 if (GET_CODE (PATTERN (insn)) == USE)
17647 switch (rs6000_cpu_attr) {
17649 switch (get_attr_type (insn))
17656 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17657 priority, priority);
17658 if (priority >= 0 && priority < 0x01000000)
17665 if (insn_must_be_first_in_group (insn)
17666 && reload_completed
17667 && current_sched_info->sched_max_insns_priority
17668 && rs6000_sched_restricted_insns_priority)
17671 /* Prioritize insns that can be dispatched only in the first
17673 if (rs6000_sched_restricted_insns_priority == 1)
17674 /* Attach highest priority to insn. This means that in
17675 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17676 precede 'priority' (critical path) considerations. */
17677 return current_sched_info->sched_max_insns_priority;
17678 else if (rs6000_sched_restricted_insns_priority == 2)
17679 /* Increase priority of insn by a minimal amount. This means that in
17680 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17681 considerations precede dispatch-slot restriction considerations. */
17682 return (priority + 1);
17685 if (rs6000_cpu == PROCESSOR_POWER6
17686 && ((load_store_pendulum == -2 && is_load_insn (insn))
17687 || (load_store_pendulum == 2 && is_store_insn (insn))))
17688 /* Attach highest priority to insn if the scheduler has just issued two
17689 stores and this instruction is a load, or two loads and this instruction
17690 is a store. Power6 wants loads and stores scheduled alternately
17692 return current_sched_info->sched_max_insns_priority;
17697 /* Return true if the instruction is nonpipelined on the Cell. */
17699 is_nonpipeline_insn (rtx insn)
17701 enum attr_type type;
17702 if (!insn || !INSN_P (insn)
17703 || GET_CODE (PATTERN (insn)) == USE
17704 || GET_CODE (PATTERN (insn)) == CLOBBER)
17707 type = get_attr_type (insn);
17708 if (type == TYPE_IMUL
17709 || type == TYPE_IMUL2
17710 || type == TYPE_IMUL3
17711 || type == TYPE_LMUL
17712 || type == TYPE_IDIV
17713 || type == TYPE_LDIV
17714 || type == TYPE_SDIV
17715 || type == TYPE_DDIV
17716 || type == TYPE_SSQRT
17717 || type == TYPE_DSQRT
17718 || type == TYPE_MFCR
17719 || type == TYPE_MFCRF
17720 || type == TYPE_MFJMPR)
17728 /* Return how many instructions the machine can issue per cycle. */
17731 rs6000_issue_rate (void)
17733 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17734 if (!reload_completed)
17737 switch (rs6000_cpu_attr) {
17738 case CPU_RIOS1: /* ? */
17740 case CPU_PPC601: /* ? */
17765 /* Return how many instructions to look ahead for better insn
17769 rs6000_use_sched_lookahead (void)
17771 if (rs6000_cpu_attr == CPU_PPC8540)
17773 if (rs6000_cpu_attr == CPU_CELL)
17774 return (reload_completed ? 8 : 0);
17778 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17780 rs6000_use_sched_lookahead_guard (rtx insn)
17782 if (rs6000_cpu_attr != CPU_CELL)
17785 if (insn == NULL_RTX || !INSN_P (insn))
17788 if (!reload_completed
17789 || is_nonpipeline_insn (insn)
17790 || is_microcoded_insn (insn))
17796 /* Determine is PAT refers to memory. */
17799 is_mem_ref (rtx pat)
17805 if (GET_CODE (pat) == MEM)
17808 /* Recursively process the pattern. */
17809 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17811 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17814 ret |= is_mem_ref (XEXP (pat, i));
17815 else if (fmt[i] == 'E')
17816 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17817 ret |= is_mem_ref (XVECEXP (pat, i, j));
17823 /* Determine if PAT is a PATTERN of a load insn. */
17826 is_load_insn1 (rtx pat)
17828 if (!pat || pat == NULL_RTX)
17831 if (GET_CODE (pat) == SET)
17832 return is_mem_ref (SET_SRC (pat));
17834 if (GET_CODE (pat) == PARALLEL)
17838 for (i = 0; i < XVECLEN (pat, 0); i++)
17839 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17846 /* Determine if INSN loads from memory. */
17849 is_load_insn (rtx insn)
17851 if (!insn || !INSN_P (insn))
17854 if (GET_CODE (insn) == CALL_INSN)
17857 return is_load_insn1 (PATTERN (insn));
17860 /* Determine if PAT is a PATTERN of a store insn. */
17863 is_store_insn1 (rtx pat)
17865 if (!pat || pat == NULL_RTX)
17868 if (GET_CODE (pat) == SET)
17869 return is_mem_ref (SET_DEST (pat));
17871 if (GET_CODE (pat) == PARALLEL)
17875 for (i = 0; i < XVECLEN (pat, 0); i++)
17876 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17883 /* Determine if INSN stores to memory. */
17886 is_store_insn (rtx insn)
17888 if (!insn || !INSN_P (insn))
17891 return is_store_insn1 (PATTERN (insn));
17894 /* Return the dest of a store insn. */
17897 get_store_dest (rtx pat)
17899 gcc_assert (is_store_insn1 (pat));
17901 if (GET_CODE (pat) == SET)
17902 return SET_DEST (pat);
17903 else if (GET_CODE (pat) == PARALLEL)
17907 for (i = 0; i < XVECLEN (pat, 0); i++)
17909 rtx inner_pat = XVECEXP (pat, 0, i);
17910 if (GET_CODE (inner_pat) == SET
17911 && is_mem_ref (SET_DEST (inner_pat)))
17915 /* We shouldn't get here, because we should have either a simple
17916 store insn or a store with update which are covered above. */
17920 /* Returns whether the dependence between INSN and NEXT is considered
17921 costly by the given target. */
17924 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17929 /* If the flag is not enabled - no dependence is considered costly;
17930 allow all dependent insns in the same group.
17931 This is the most aggressive option. */
17932 if (rs6000_sched_costly_dep == no_dep_costly)
17935 /* If the flag is set to 1 - a dependence is always considered costly;
17936 do not allow dependent instructions in the same group.
17937 This is the most conservative option. */
17938 if (rs6000_sched_costly_dep == all_deps_costly)
17941 insn = DEP_PRO (dep);
17942 next = DEP_CON (dep);
17944 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17945 && is_load_insn (next)
17946 && is_store_insn (insn))
17947 /* Prevent load after store in the same group. */
17950 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17951 && is_load_insn (next)
17952 && is_store_insn (insn)
17953 && DEP_KIND (dep) == REG_DEP_TRUE)
17954 /* Prevent load after store in the same group if it is a true
17958 /* The flag is set to X; dependences with latency >= X are considered costly,
17959 and will not be scheduled in the same group. */
17960 if (rs6000_sched_costly_dep <= max_dep_latency
17961 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17967 /* Return the next insn after INSN that is found before TAIL is reached,
17968 skipping any "non-active" insns - insns that will not actually occupy
17969 an issue slot. Return NULL_RTX if such an insn is not found. */
17972 get_next_active_insn (rtx insn, rtx tail)
17974 if (insn == NULL_RTX || insn == tail)
17979 insn = NEXT_INSN (insn);
17980 if (insn == NULL_RTX || insn == tail)
17985 || (NONJUMP_INSN_P (insn)
17986 && GET_CODE (PATTERN (insn)) != USE
17987 && GET_CODE (PATTERN (insn)) != CLOBBER
17988 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17994 /* We are about to begin issuing insns for this clock cycle. */
17997 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17998 rtx *ready ATTRIBUTE_UNUSED,
17999 int *pn_ready ATTRIBUTE_UNUSED,
18000 int clock_var ATTRIBUTE_UNUSED)
18002 int n_ready = *pn_ready;
18005 fprintf (dump, "// rs6000_sched_reorder :\n");
18007 /* Reorder the ready list, if the second to last ready insn
18008 is a nonepipeline insn. */
18009 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
18011 if (is_nonpipeline_insn (ready[n_ready - 1])
18012 && (recog_memoized (ready[n_ready - 2]) > 0))
18013 /* Simply swap first two insns. */
18015 rtx tmp = ready[n_ready - 1];
18016 ready[n_ready - 1] = ready[n_ready - 2];
18017 ready[n_ready - 2] = tmp;
18021 if (rs6000_cpu == PROCESSOR_POWER6)
18022 load_store_pendulum = 0;
18024 return rs6000_issue_rate ();
18027 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18030 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
18031 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
18034 fprintf (dump, "// rs6000_sched_reorder2 :\n");
18036 /* For Power6, we need to handle some special cases to try and keep the
18037 store queue from overflowing and triggering expensive flushes.
18039 This code monitors how load and store instructions are being issued
18040 and skews the ready list one way or the other to increase the likelihood
18041 that a desired instruction is issued at the proper time.
18043 A couple of things are done. First, we maintain a "load_store_pendulum"
18044 to track the current state of load/store issue.
18046 - If the pendulum is at zero, then no loads or stores have been
18047 issued in the current cycle so we do nothing.
18049 - If the pendulum is 1, then a single load has been issued in this
18050 cycle and we attempt to locate another load in the ready list to
18053 - If the pendulum is -2, then two stores have already been
18054 issued in this cycle, so we increase the priority of the first load
18055 in the ready list to increase it's likelihood of being chosen first
18058 - If the pendulum is -1, then a single store has been issued in this
18059 cycle and we attempt to locate another store in the ready list to
18060 issue with it, preferring a store to an adjacent memory location to
18061 facilitate store pairing in the store queue.
18063 - If the pendulum is 2, then two loads have already been
18064 issued in this cycle, so we increase the priority of the first store
18065 in the ready list to increase it's likelihood of being chosen first
18068 - If the pendulum < -2 or > 2, then do nothing.
18070 Note: This code covers the most common scenarios. There exist non
18071 load/store instructions which make use of the LSU and which
18072 would need to be accounted for to strictly model the behavior
18073 of the machine. Those instructions are currently unaccounted
18074 for to help minimize compile time overhead of this code.
18076 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
18082 if (is_store_insn (last_scheduled_insn))
18083 /* Issuing a store, swing the load_store_pendulum to the left */
18084 load_store_pendulum--;
18085 else if (is_load_insn (last_scheduled_insn))
18086 /* Issuing a load, swing the load_store_pendulum to the right */
18087 load_store_pendulum++;
18089 return cached_can_issue_more;
18091 /* If the pendulum is balanced, or there is only one instruction on
18092 the ready list, then all is well, so return. */
18093 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
18094 return cached_can_issue_more;
18096 if (load_store_pendulum == 1)
18098 /* A load has been issued in this cycle. Scan the ready list
18099 for another load to issue with it */
18104 if (is_load_insn (ready[pos]))
18106 /* Found a load. Move it to the head of the ready list,
18107 and adjust it's priority so that it is more likely to
18110 for (i=pos; i<*pn_ready-1; i++)
18111 ready[i] = ready[i + 1];
18112 ready[*pn_ready-1] = tmp;
18113 if INSN_PRIORITY_KNOWN (tmp)
18114 INSN_PRIORITY (tmp)++;
18120 else if (load_store_pendulum == -2)
18122 /* Two stores have been issued in this cycle. Increase the
18123 priority of the first load in the ready list to favor it for
18124 issuing in the next cycle. */
18129 if (is_load_insn (ready[pos])
18130 && INSN_PRIORITY_KNOWN (ready[pos]))
18132 INSN_PRIORITY (ready[pos])++;
18134 /* Adjust the pendulum to account for the fact that a load
18135 was found and increased in priority. This is to prevent
18136 increasing the priority of multiple loads */
18137 load_store_pendulum--;
18144 else if (load_store_pendulum == -1)
18146 /* A store has been issued in this cycle. Scan the ready list for
18147 another store to issue with it, preferring a store to an adjacent
18149 int first_store_pos = -1;
18155 if (is_store_insn (ready[pos]))
18157 /* Maintain the index of the first store found on the
18159 if (first_store_pos == -1)
18160 first_store_pos = pos;
18162 if (is_store_insn (last_scheduled_insn)
18163 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18165 /* Found an adjacent store. Move it to the head of the
18166 ready list, and adjust it's priority so that it is
18167 more likely to stay there */
18169 for (i=pos; i<*pn_ready-1; i++)
18170 ready[i] = ready[i + 1];
18171 ready[*pn_ready-1] = tmp;
18172 if INSN_PRIORITY_KNOWN (tmp)
18173 INSN_PRIORITY (tmp)++;
18174 first_store_pos = -1;
18182 if (first_store_pos >= 0)
18184 /* An adjacent store wasn't found, but a non-adjacent store was,
18185 so move the non-adjacent store to the front of the ready
18186 list, and adjust its priority so that it is more likely to
18188 tmp = ready[first_store_pos];
18189 for (i=first_store_pos; i<*pn_ready-1; i++)
18190 ready[i] = ready[i + 1];
18191 ready[*pn_ready-1] = tmp;
18192 if INSN_PRIORITY_KNOWN (tmp)
18193 INSN_PRIORITY (tmp)++;
18196 else if (load_store_pendulum == 2)
18198 /* Two loads have been issued in this cycle. Increase the priority
18199 of the first store in the ready list to favor it for issuing in
18205 if (is_store_insn (ready[pos])
18206 && INSN_PRIORITY_KNOWN (ready[pos]))
18208 INSN_PRIORITY (ready[pos])++;
18210 /* Adjust the pendulum to account for the fact that a store
18211 was found and increased in priority. This is to prevent
18212 increasing the priority of multiple stores */
18213 load_store_pendulum++;
18222 return cached_can_issue_more;
18225 /* Return whether the presence of INSN causes a dispatch group termination
18226 of group WHICH_GROUP.
18228 If WHICH_GROUP == current_group, this function will return true if INSN
18229 causes the termination of the current group (i.e, the dispatch group to
18230 which INSN belongs). This means that INSN will be the last insn in the
18231 group it belongs to.
18233 If WHICH_GROUP == previous_group, this function will return true if INSN
18234 causes the termination of the previous group (i.e, the dispatch group that
18235 precedes the group to which INSN belongs). This means that INSN will be
18236 the first insn in the group it belongs to). */
18239 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18246 first = insn_must_be_first_in_group (insn);
18247 last = insn_must_be_last_in_group (insn);
18252 if (which_group == current_group)
18254 else if (which_group == previous_group)
18262 insn_must_be_first_in_group (rtx insn)
18264 enum attr_type type;
18267 || insn == NULL_RTX
18268 || GET_CODE (insn) == NOTE
18269 || GET_CODE (PATTERN (insn)) == USE
18270 || GET_CODE (PATTERN (insn)) == CLOBBER)
18273 switch (rs6000_cpu)
18275 case PROCESSOR_POWER5:
18276 if (is_cracked_insn (insn))
18278 case PROCESSOR_POWER4:
18279 if (is_microcoded_insn (insn))
18282 if (!rs6000_sched_groups)
18285 type = get_attr_type (insn);
18292 case TYPE_DELAYED_CR:
18293 case TYPE_CR_LOGICAL:
18307 case PROCESSOR_POWER6:
18308 type = get_attr_type (insn);
18312 case TYPE_INSERT_DWORD:
18316 case TYPE_VAR_SHIFT_ROTATE:
18323 case TYPE_INSERT_WORD:
18324 case TYPE_DELAYED_COMPARE:
18325 case TYPE_IMUL_COMPARE:
18326 case TYPE_LMUL_COMPARE:
18327 case TYPE_FPCOMPARE:
18338 case TYPE_LOAD_EXT_UX:
18340 case TYPE_STORE_UX:
18341 case TYPE_FPLOAD_U:
18342 case TYPE_FPLOAD_UX:
18343 case TYPE_FPSTORE_U:
18344 case TYPE_FPSTORE_UX:
18358 insn_must_be_last_in_group (rtx insn)
18360 enum attr_type type;
18363 || insn == NULL_RTX
18364 || GET_CODE (insn) == NOTE
18365 || GET_CODE (PATTERN (insn)) == USE
18366 || GET_CODE (PATTERN (insn)) == CLOBBER)
18369 switch (rs6000_cpu) {
18370 case PROCESSOR_POWER4:
18371 case PROCESSOR_POWER5:
18372 if (is_microcoded_insn (insn))
18375 if (is_branch_slot_insn (insn))
18379 case PROCESSOR_POWER6:
18380 type = get_attr_type (insn);
18387 case TYPE_VAR_SHIFT_ROTATE:
18394 case TYPE_DELAYED_COMPARE:
18395 case TYPE_IMUL_COMPARE:
18396 case TYPE_LMUL_COMPARE:
18397 case TYPE_FPCOMPARE:
18418 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18419 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18422 is_costly_group (rtx *group_insns, rtx next_insn)
18425 int issue_rate = rs6000_issue_rate ();
18427 for (i = 0; i < issue_rate; i++)
18430 rtx insn = group_insns[i];
18435 FOR_EACH_DEP_LINK (link, INSN_FORW_DEPS (insn))
18437 dep_t dep = DEP_LINK_DEP (link);
18438 rtx next = DEP_CON (dep);
18440 if (next == next_insn
18441 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18449 /* Utility of the function redefine_groups.
18450 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18451 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18452 to keep it "far" (in a separate group) from GROUP_INSNS, following
18453 one of the following schemes, depending on the value of the flag
18454 -minsert_sched_nops = X:
18455 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18456 in order to force NEXT_INSN into a separate group.
18457 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18458 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18459 insertion (has a group just ended, how many vacant issue slots remain in the
18460 last group, and how many dispatch groups were encountered so far). */
18463 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18464 rtx next_insn, bool *group_end, int can_issue_more,
18469 int issue_rate = rs6000_issue_rate ();
18470 bool end = *group_end;
18473 if (next_insn == NULL_RTX)
18474 return can_issue_more;
18476 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18477 return can_issue_more;
18479 force = is_costly_group (group_insns, next_insn);
18481 return can_issue_more;
18483 if (sched_verbose > 6)
18484 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18485 *group_count ,can_issue_more);
18487 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18490 can_issue_more = 0;
18492 /* Since only a branch can be issued in the last issue_slot, it is
18493 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18494 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18495 in this case the last nop will start a new group and the branch
18496 will be forced to the new group. */
18497 if (can_issue_more && !is_branch_slot_insn (next_insn))
18500 while (can_issue_more > 0)
18503 emit_insn_before (nop, next_insn);
18511 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18513 int n_nops = rs6000_sched_insert_nops;
18515 /* Nops can't be issued from the branch slot, so the effective
18516 issue_rate for nops is 'issue_rate - 1'. */
18517 if (can_issue_more == 0)
18518 can_issue_more = issue_rate;
18520 if (can_issue_more == 0)
18522 can_issue_more = issue_rate - 1;
18525 for (i = 0; i < issue_rate; i++)
18527 group_insns[i] = 0;
18534 emit_insn_before (nop, next_insn);
18535 if (can_issue_more == issue_rate - 1) /* new group begins */
18538 if (can_issue_more == 0)
18540 can_issue_more = issue_rate - 1;
18543 for (i = 0; i < issue_rate; i++)
18545 group_insns[i] = 0;
18551 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18554 /* Is next_insn going to start a new group? */
18557 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18558 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18559 || (can_issue_more < issue_rate &&
18560 insn_terminates_group_p (next_insn, previous_group)));
18561 if (*group_end && end)
18564 if (sched_verbose > 6)
18565 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18566 *group_count, can_issue_more);
18567 return can_issue_more;
18570 return can_issue_more;
18573 /* This function tries to synch the dispatch groups that the compiler "sees"
18574 with the dispatch groups that the processor dispatcher is expected to
18575 form in practice. It tries to achieve this synchronization by forcing the
18576 estimated processor grouping on the compiler (as opposed to the function
18577 'pad_goups' which tries to force the scheduler's grouping on the processor).
18579 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18580 examines the (estimated) dispatch groups that will be formed by the processor
18581 dispatcher. It marks these group boundaries to reflect the estimated
18582 processor grouping, overriding the grouping that the scheduler had marked.
18583 Depending on the value of the flag '-minsert-sched-nops' this function can
18584 force certain insns into separate groups or force a certain distance between
18585 them by inserting nops, for example, if there exists a "costly dependence"
18588 The function estimates the group boundaries that the processor will form as
18589 follows: It keeps track of how many vacant issue slots are available after
18590 each insn. A subsequent insn will start a new group if one of the following
18592 - no more vacant issue slots remain in the current dispatch group.
18593 - only the last issue slot, which is the branch slot, is vacant, but the next
18594 insn is not a branch.
18595 - only the last 2 or less issue slots, including the branch slot, are vacant,
18596 which means that a cracked insn (which occupies two issue slots) can't be
18597 issued in this group.
18598 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18599 start a new group. */
18602 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18604 rtx insn, next_insn;
18606 int can_issue_more;
18609 int group_count = 0;
18613 issue_rate = rs6000_issue_rate ();
18614 group_insns = alloca (issue_rate * sizeof (rtx));
18615 for (i = 0; i < issue_rate; i++)
18617 group_insns[i] = 0;
18619 can_issue_more = issue_rate;
18621 insn = get_next_active_insn (prev_head_insn, tail);
18624 while (insn != NULL_RTX)
18626 slot = (issue_rate - can_issue_more);
18627 group_insns[slot] = insn;
18629 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18630 if (insn_terminates_group_p (insn, current_group))
18631 can_issue_more = 0;
18633 next_insn = get_next_active_insn (insn, tail);
18634 if (next_insn == NULL_RTX)
18635 return group_count + 1;
18637 /* Is next_insn going to start a new group? */
18639 = (can_issue_more == 0
18640 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18641 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18642 || (can_issue_more < issue_rate &&
18643 insn_terminates_group_p (next_insn, previous_group)));
18645 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18646 next_insn, &group_end, can_issue_more,
18652 can_issue_more = 0;
18653 for (i = 0; i < issue_rate; i++)
18655 group_insns[i] = 0;
18659 if (GET_MODE (next_insn) == TImode && can_issue_more)
18660 PUT_MODE (next_insn, VOIDmode);
18661 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18662 PUT_MODE (next_insn, TImode);
18665 if (can_issue_more == 0)
18666 can_issue_more = issue_rate;
18669 return group_count;
18672 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18673 dispatch group boundaries that the scheduler had marked. Pad with nops
18674 any dispatch groups which have vacant issue slots, in order to force the
18675 scheduler's grouping on the processor dispatcher. The function
18676 returns the number of dispatch groups found. */
18679 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18681 rtx insn, next_insn;
18684 int can_issue_more;
18686 int group_count = 0;
18688 /* Initialize issue_rate. */
18689 issue_rate = rs6000_issue_rate ();
18690 can_issue_more = issue_rate;
18692 insn = get_next_active_insn (prev_head_insn, tail);
18693 next_insn = get_next_active_insn (insn, tail);
18695 while (insn != NULL_RTX)
18698 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18700 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18702 if (next_insn == NULL_RTX)
18707 /* If the scheduler had marked group termination at this location
18708 (between insn and next_indn), and neither insn nor next_insn will
18709 force group termination, pad the group with nops to force group
18712 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18713 && !insn_terminates_group_p (insn, current_group)
18714 && !insn_terminates_group_p (next_insn, previous_group))
18716 if (!is_branch_slot_insn (next_insn))
18719 while (can_issue_more)
18722 emit_insn_before (nop, next_insn);
18727 can_issue_more = issue_rate;
18732 next_insn = get_next_active_insn (insn, tail);
18735 return group_count;
18738 /* We're beginning a new block. Initialize data structures as necessary. */
18741 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18742 int sched_verbose ATTRIBUTE_UNUSED,
18743 int max_ready ATTRIBUTE_UNUSED)
18745 last_scheduled_insn = NULL_RTX;
18746 load_store_pendulum = 0;
18749 /* The following function is called at the end of scheduling BB.
18750 After reload, it inserts nops at insn group bundling. */
18753 rs6000_sched_finish (FILE *dump, int sched_verbose)
18758 fprintf (dump, "=== Finishing schedule.\n");
18760 if (reload_completed && rs6000_sched_groups)
18762 if (rs6000_sched_insert_nops == sched_finish_none)
18765 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18766 n_groups = pad_groups (dump, sched_verbose,
18767 current_sched_info->prev_head,
18768 current_sched_info->next_tail);
18770 n_groups = redefine_groups (dump, sched_verbose,
18771 current_sched_info->prev_head,
18772 current_sched_info->next_tail);
18774 if (sched_verbose >= 6)
18776 fprintf (dump, "ngroups = %d\n", n_groups);
18777 print_rtl (dump, current_sched_info->prev_head);
18778 fprintf (dump, "Done finish_sched\n");
18783 /* Length in units of the trampoline for entering a nested function. */
18786 rs6000_trampoline_size (void)
18790 switch (DEFAULT_ABI)
18793 gcc_unreachable ();
18796 ret = (TARGET_32BIT) ? 12 : 24;
18801 ret = (TARGET_32BIT) ? 40 : 48;
18808 /* Emit RTL insns to initialize the variable parts of a trampoline.
18809 FNADDR is an RTX for the address of the function's pure code.
18810 CXT is an RTX for the static chain value for the function. */
18813 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18815 int regsize = (TARGET_32BIT) ? 4 : 8;
18816 rtx ctx_reg = force_reg (Pmode, cxt);
18818 switch (DEFAULT_ABI)
18821 gcc_unreachable ();
18823 /* Macros to shorten the code expansions below. */
18824 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18825 #define MEM_PLUS(addr,offset) \
18826 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18828 /* Under AIX, just build the 3 word function descriptor */
18831 rtx fn_reg = gen_reg_rtx (Pmode);
18832 rtx toc_reg = gen_reg_rtx (Pmode);
18833 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18834 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18835 emit_move_insn (MEM_DEREF (addr), fn_reg);
18836 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18837 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18841 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18844 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18845 FALSE, VOIDmode, 4,
18847 GEN_INT (rs6000_trampoline_size ()), SImode,
18857 /* Table of valid machine attributes. */
18859 const struct attribute_spec rs6000_attribute_table[] =
18861 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18862 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18863 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18864 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18865 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18866 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18867 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18868 SUBTARGET_ATTRIBUTE_TABLE,
18870 { NULL, 0, 0, false, false, false, NULL }
18873 /* Handle the "altivec" attribute. The attribute may have
18874 arguments as follows:
18876 __attribute__((altivec(vector__)))
18877 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18878 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18880 and may appear more than once (e.g., 'vector bool char') in a
18881 given declaration. */
18884 rs6000_handle_altivec_attribute (tree *node,
18885 tree name ATTRIBUTE_UNUSED,
18887 int flags ATTRIBUTE_UNUSED,
18888 bool *no_add_attrs)
18890 tree type = *node, result = NULL_TREE;
18891 enum machine_mode mode;
18894 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18895 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18896 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18899 while (POINTER_TYPE_P (type)
18900 || TREE_CODE (type) == FUNCTION_TYPE
18901 || TREE_CODE (type) == METHOD_TYPE
18902 || TREE_CODE (type) == ARRAY_TYPE)
18903 type = TREE_TYPE (type);
18905 mode = TYPE_MODE (type);
18907 /* Check for invalid AltiVec type qualifiers. */
18908 if (type == long_unsigned_type_node || type == long_integer_type_node)
18911 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18912 else if (rs6000_warn_altivec_long)
18913 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18915 else if (type == long_long_unsigned_type_node
18916 || type == long_long_integer_type_node)
18917 error ("use of %<long long%> in AltiVec types is invalid");
18918 else if (type == double_type_node)
18919 error ("use of %<double%> in AltiVec types is invalid");
18920 else if (type == long_double_type_node)
18921 error ("use of %<long double%> in AltiVec types is invalid");
18922 else if (type == boolean_type_node)
18923 error ("use of boolean types in AltiVec types is invalid");
18924 else if (TREE_CODE (type) == COMPLEX_TYPE)
18925 error ("use of %<complex%> in AltiVec types is invalid");
18926 else if (DECIMAL_FLOAT_MODE_P (mode))
18927 error ("use of decimal floating point types in AltiVec types is invalid");
18929 switch (altivec_type)
18932 unsigned_p = TYPE_UNSIGNED (type);
18936 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18939 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18942 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18944 case SFmode: result = V4SF_type_node; break;
18945 /* If the user says 'vector int bool', we may be handed the 'bool'
18946 attribute _before_ the 'vector' attribute, and so select the
18947 proper type in the 'b' case below. */
18948 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18956 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18957 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18958 case QImode: case V16QImode: result = bool_V16QI_type_node;
18965 case V8HImode: result = pixel_V8HI_type_node;
18971 if (result && result != type && TYPE_READONLY (type))
18972 result = build_qualified_type (result, TYPE_QUAL_CONST);
18974 *no_add_attrs = true; /* No need to hang on to the attribute. */
18977 *node = reconstruct_complex_type (*node, result);
18982 /* AltiVec defines four built-in scalar types that serve as vector
18983 elements; we must teach the compiler how to mangle them. */
18985 static const char *
18986 rs6000_mangle_type (tree type)
18988 type = TYPE_MAIN_VARIANT (type);
18990 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
18991 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
18994 if (type == bool_char_type_node) return "U6__boolc";
18995 if (type == bool_short_type_node) return "U6__bools";
18996 if (type == pixel_type_node) return "u7__pixel";
18997 if (type == bool_int_type_node) return "U6__booli";
18999 /* Mangle IBM extended float long double as `g' (__float128) on
19000 powerpc*-linux where long-double-64 previously was the default. */
19001 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
19003 && TARGET_LONG_DOUBLE_128
19004 && !TARGET_IEEEQUAD)
19007 /* For all other types, use normal C++ mangling. */
19011 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19012 struct attribute_spec.handler. */
19015 rs6000_handle_longcall_attribute (tree *node, tree name,
19016 tree args ATTRIBUTE_UNUSED,
19017 int flags ATTRIBUTE_UNUSED,
19018 bool *no_add_attrs)
19020 if (TREE_CODE (*node) != FUNCTION_TYPE
19021 && TREE_CODE (*node) != FIELD_DECL
19022 && TREE_CODE (*node) != TYPE_DECL)
19024 warning (OPT_Wattributes, "%qs attribute only applies to functions",
19025 IDENTIFIER_POINTER (name));
19026 *no_add_attrs = true;
19032 /* Set longcall attributes on all functions declared when
19033 rs6000_default_long_calls is true. */
19035 rs6000_set_default_type_attributes (tree type)
19037 if (rs6000_default_long_calls
19038 && (TREE_CODE (type) == FUNCTION_TYPE
19039 || TREE_CODE (type) == METHOD_TYPE))
19040 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
19042 TYPE_ATTRIBUTES (type));
19045 darwin_set_default_type_attributes (type);
19049 /* Return a reference suitable for calling a function with the
19050 longcall attribute. */
19053 rs6000_longcall_ref (rtx call_ref)
19055 const char *call_name;
19058 if (GET_CODE (call_ref) != SYMBOL_REF)
19061 /* System V adds '.' to the internal name, so skip them. */
19062 call_name = XSTR (call_ref, 0);
19063 if (*call_name == '.')
19065 while (*call_name == '.')
19068 node = get_identifier (call_name);
19069 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
19072 return force_reg (Pmode, call_ref);
19075 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19076 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19079 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19080 struct attribute_spec.handler. */
19082 rs6000_handle_struct_attribute (tree *node, tree name,
19083 tree args ATTRIBUTE_UNUSED,
19084 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
19087 if (DECL_P (*node))
19089 if (TREE_CODE (*node) == TYPE_DECL)
19090 type = &TREE_TYPE (*node);
19095 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
19096 || TREE_CODE (*type) == UNION_TYPE)))
19098 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
19099 *no_add_attrs = true;
19102 else if ((is_attribute_p ("ms_struct", name)
19103 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
19104 || ((is_attribute_p ("gcc_struct", name)
19105 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19107 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19108 IDENTIFIER_POINTER (name));
19109 *no_add_attrs = true;
19116 rs6000_ms_bitfield_layout_p (tree record_type)
19118 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19119 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19120 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19123 #ifdef USING_ELFOS_H
19125 /* A get_unnamed_section callback, used for switching to toc_section. */
19128 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19130 if (DEFAULT_ABI == ABI_AIX
19131 && TARGET_MINIMAL_TOC
19132 && !TARGET_RELOCATABLE)
19134 if (!toc_initialized)
19136 toc_initialized = 1;
19137 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19138 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19139 fprintf (asm_out_file, "\t.tc ");
19140 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19141 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19142 fprintf (asm_out_file, "\n");
19144 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19145 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19146 fprintf (asm_out_file, " = .+32768\n");
19149 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19151 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19152 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19155 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19156 if (!toc_initialized)
19158 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19159 fprintf (asm_out_file, " = .+32768\n");
19160 toc_initialized = 1;
19165 /* Implement TARGET_ASM_INIT_SECTIONS. */
19168 rs6000_elf_asm_init_sections (void)
19171 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19174 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19175 SDATA2_SECTION_ASM_OP);
19178 /* Implement TARGET_SELECT_RTX_SECTION. */
19181 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19182 unsigned HOST_WIDE_INT align)
19184 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19185 return toc_section;
19187 return default_elf_select_rtx_section (mode, x, align);
19190 /* For a SYMBOL_REF, set generic flags and then perform some
19191 target-specific processing.
19193 When the AIX ABI is requested on a non-AIX system, replace the
19194 function name with the real name (with a leading .) rather than the
19195 function descriptor name. This saves a lot of overriding code to
19196 read the prefixes. */
19199 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19201 default_encode_section_info (decl, rtl, first);
19204 && TREE_CODE (decl) == FUNCTION_DECL
19206 && DEFAULT_ABI == ABI_AIX)
19208 rtx sym_ref = XEXP (rtl, 0);
19209 size_t len = strlen (XSTR (sym_ref, 0));
19210 char *str = alloca (len + 2);
19212 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19213 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19218 rs6000_elf_in_small_data_p (tree decl)
19220 if (rs6000_sdata == SDATA_NONE)
19223 /* We want to merge strings, so we never consider them small data. */
19224 if (TREE_CODE (decl) == STRING_CST)
19227 /* Functions are never in the small data area. */
19228 if (TREE_CODE (decl) == FUNCTION_DECL)
19231 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19233 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19234 if (strcmp (section, ".sdata") == 0
19235 || strcmp (section, ".sdata2") == 0
19236 || strcmp (section, ".sbss") == 0
19237 || strcmp (section, ".sbss2") == 0
19238 || strcmp (section, ".PPC.EMB.sdata0") == 0
19239 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19244 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19247 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19248 /* If it's not public, and we're not going to reference it there,
19249 there's no need to put it in the small data section. */
19250 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19257 #endif /* USING_ELFOS_H */
19259 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19262 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
19264 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19267 /* Return a REG that occurs in ADDR with coefficient 1.
19268 ADDR can be effectively incremented by incrementing REG.
19270 r0 is special and we must not select it as an address
19271 register by this routine since our caller will try to
19272 increment the returned register via an "la" instruction. */
19275 find_addr_reg (rtx addr)
19277 while (GET_CODE (addr) == PLUS)
19279 if (GET_CODE (XEXP (addr, 0)) == REG
19280 && REGNO (XEXP (addr, 0)) != 0)
19281 addr = XEXP (addr, 0);
19282 else if (GET_CODE (XEXP (addr, 1)) == REG
19283 && REGNO (XEXP (addr, 1)) != 0)
19284 addr = XEXP (addr, 1);
19285 else if (CONSTANT_P (XEXP (addr, 0)))
19286 addr = XEXP (addr, 1);
19287 else if (CONSTANT_P (XEXP (addr, 1)))
19288 addr = XEXP (addr, 0);
19290 gcc_unreachable ();
19292 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19297 rs6000_fatal_bad_address (rtx op)
19299 fatal_insn ("bad address", op);
19304 static tree branch_island_list = 0;
19306 /* Remember to generate a branch island for far calls to the given
19310 add_compiler_branch_island (tree label_name, tree function_name,
19313 tree branch_island = build_tree_list (function_name, label_name);
19314 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19315 TREE_CHAIN (branch_island) = branch_island_list;
19316 branch_island_list = branch_island;
19319 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19320 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19321 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19322 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19324 /* Generate far-jump branch islands for everything on the
19325 branch_island_list. Invoked immediately after the last instruction
19326 of the epilogue has been emitted; the branch-islands must be
19327 appended to, and contiguous with, the function body. Mach-O stubs
19328 are generated in machopic_output_stub(). */
19331 macho_branch_islands (void)
19334 tree branch_island;
19336 for (branch_island = branch_island_list;
19338 branch_island = TREE_CHAIN (branch_island))
19340 const char *label =
19341 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19343 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19344 char name_buf[512];
19345 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19346 if (name[0] == '*' || name[0] == '&')
19347 strcpy (name_buf, name+1);
19351 strcpy (name_buf+1, name);
19353 strcpy (tmp_buf, "\n");
19354 strcat (tmp_buf, label);
19355 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19356 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19357 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19358 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19361 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19362 strcat (tmp_buf, label);
19363 strcat (tmp_buf, "_pic\n");
19364 strcat (tmp_buf, label);
19365 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19367 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19368 strcat (tmp_buf, name_buf);
19369 strcat (tmp_buf, " - ");
19370 strcat (tmp_buf, label);
19371 strcat (tmp_buf, "_pic)\n");
19373 strcat (tmp_buf, "\tmtlr r0\n");
19375 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19376 strcat (tmp_buf, name_buf);
19377 strcat (tmp_buf, " - ");
19378 strcat (tmp_buf, label);
19379 strcat (tmp_buf, "_pic)\n");
19381 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19385 strcat (tmp_buf, ":\nlis r12,hi16(");
19386 strcat (tmp_buf, name_buf);
19387 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19388 strcat (tmp_buf, name_buf);
19389 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19391 output_asm_insn (tmp_buf, 0);
19392 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19393 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19394 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19395 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19398 branch_island_list = 0;
19401 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19402 already there or not. */
19405 no_previous_def (tree function_name)
19407 tree branch_island;
19408 for (branch_island = branch_island_list;
19410 branch_island = TREE_CHAIN (branch_island))
19411 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19416 /* GET_PREV_LABEL gets the label name from the previous definition of
19420 get_prev_label (tree function_name)
19422 tree branch_island;
19423 for (branch_island = branch_island_list;
19425 branch_island = TREE_CHAIN (branch_island))
19426 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19427 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19431 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19432 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19435 /* KEXTs still need branch islands. */
19436 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19437 || flag_mkernel || flag_apple_kext)
19439 /* INSN is either a function call or a millicode call. It may have an
19440 unconditional jump in its delay slot.
19442 CALL_DEST is the routine we are calling. */
19445 output_call (rtx insn, rtx *operands, int dest_operand_number,
19446 int cookie_operand_number)
19448 static char buf[256];
19449 if (DARWIN_GENERATE_ISLANDS
19450 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19451 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19454 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19456 if (no_previous_def (funname))
19458 rtx label_rtx = gen_label_rtx ();
19459 char *label_buf, temp_buf[256];
19460 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19461 CODE_LABEL_NUMBER (label_rtx));
19462 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19463 labelname = get_identifier (label_buf);
19464 add_compiler_branch_island (labelname, funname, insn_line (insn));
19467 labelname = get_prev_label (funname);
19469 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19470 instruction will reach 'foo', otherwise link as 'bl L42'".
19471 "L42" should be a 'branch island', that will do a far jump to
19472 'foo'. Branch islands are generated in
19473 macho_branch_islands(). */
19474 sprintf (buf, "jbsr %%z%d,%.246s",
19475 dest_operand_number, IDENTIFIER_POINTER (labelname));
19478 sprintf (buf, "bl %%z%d", dest_operand_number);
19482 /* Generate PIC and indirect symbol stubs. */
19485 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19487 unsigned int length;
19488 char *symbol_name, *lazy_ptr_name;
19489 char *local_label_0;
19490 static int label = 0;
19492 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19493 symb = (*targetm.strip_name_encoding) (symb);
19496 length = strlen (symb);
19497 symbol_name = alloca (length + 32);
19498 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19500 lazy_ptr_name = alloca (length + 32);
19501 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19504 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19506 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19510 fprintf (file, "\t.align 5\n");
19512 fprintf (file, "%s:\n", stub);
19513 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19516 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19517 sprintf (local_label_0, "\"L%011d$spb\"", label);
19519 fprintf (file, "\tmflr r0\n");
19520 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19521 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19522 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19523 lazy_ptr_name, local_label_0);
19524 fprintf (file, "\tmtlr r0\n");
19525 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19526 (TARGET_64BIT ? "ldu" : "lwzu"),
19527 lazy_ptr_name, local_label_0);
19528 fprintf (file, "\tmtctr r12\n");
19529 fprintf (file, "\tbctr\n");
19533 fprintf (file, "\t.align 4\n");
19535 fprintf (file, "%s:\n", stub);
19536 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19538 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19539 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19540 (TARGET_64BIT ? "ldu" : "lwzu"),
19542 fprintf (file, "\tmtctr r12\n");
19543 fprintf (file, "\tbctr\n");
19546 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19547 fprintf (file, "%s:\n", lazy_ptr_name);
19548 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19549 fprintf (file, "%sdyld_stub_binding_helper\n",
19550 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19553 /* Legitimize PIC addresses. If the address is already
19554 position-independent, we return ORIG. Newly generated
19555 position-independent addresses go into a reg. This is REG if non
19556 zero, otherwise we allocate register(s) as necessary. */
19558 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19561 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19566 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19567 reg = gen_reg_rtx (Pmode);
19569 if (GET_CODE (orig) == CONST)
19573 if (GET_CODE (XEXP (orig, 0)) == PLUS
19574 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19577 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19579 /* Use a different reg for the intermediate value, as
19580 it will be marked UNCHANGING. */
19581 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
19582 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19585 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19588 if (GET_CODE (offset) == CONST_INT)
19590 if (SMALL_INT (offset))
19591 return plus_constant (base, INTVAL (offset));
19592 else if (! reload_in_progress && ! reload_completed)
19593 offset = force_reg (Pmode, offset);
19596 rtx mem = force_const_mem (Pmode, orig);
19597 return machopic_legitimize_pic_address (mem, Pmode, reg);
19600 return gen_rtx_PLUS (Pmode, base, offset);
19603 /* Fall back on generic machopic code. */
19604 return machopic_legitimize_pic_address (orig, mode, reg);
19607 /* Output a .machine directive for the Darwin assembler, and call
19608 the generic start_file routine. */
19611 rs6000_darwin_file_start (void)
19613 static const struct
19619 { "ppc64", "ppc64", MASK_64BIT },
19620 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19621 { "power4", "ppc970", 0 },
19622 { "G5", "ppc970", 0 },
19623 { "7450", "ppc7450", 0 },
19624 { "7400", "ppc7400", MASK_ALTIVEC },
19625 { "G4", "ppc7400", 0 },
19626 { "750", "ppc750", 0 },
19627 { "740", "ppc750", 0 },
19628 { "G3", "ppc750", 0 },
19629 { "604e", "ppc604e", 0 },
19630 { "604", "ppc604", 0 },
19631 { "603e", "ppc603", 0 },
19632 { "603", "ppc603", 0 },
19633 { "601", "ppc601", 0 },
19634 { NULL, "ppc", 0 } };
19635 const char *cpu_id = "";
19638 rs6000_file_start ();
19639 darwin_file_start ();
19641 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19642 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19643 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19644 && rs6000_select[i].string[0] != '\0')
19645 cpu_id = rs6000_select[i].string;
19647 /* Look through the mapping array. Pick the first name that either
19648 matches the argument, has a bit set in IF_SET that is also set
19649 in the target flags, or has a NULL name. */
19652 while (mapping[i].arg != NULL
19653 && strcmp (mapping[i].arg, cpu_id) != 0
19654 && (mapping[i].if_set & target_flags) == 0)
19657 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19660 #endif /* TARGET_MACHO */
19664 rs6000_elf_reloc_rw_mask (void)
19668 else if (DEFAULT_ABI == ABI_AIX)
19674 /* Record an element in the table of global constructors. SYMBOL is
19675 a SYMBOL_REF of the function to be called; PRIORITY is a number
19676 between 0 and MAX_INIT_PRIORITY.
19678 This differs from default_named_section_asm_out_constructor in
19679 that we have special handling for -mrelocatable. */
19682 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19684 const char *section = ".ctors";
19687 if (priority != DEFAULT_INIT_PRIORITY)
19689 sprintf (buf, ".ctors.%.5u",
19690 /* Invert the numbering so the linker puts us in the proper
19691 order; constructors are run from right to left, and the
19692 linker sorts in increasing order. */
19693 MAX_INIT_PRIORITY - priority);
19697 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19698 assemble_align (POINTER_SIZE);
19700 if (TARGET_RELOCATABLE)
19702 fputs ("\t.long (", asm_out_file);
19703 output_addr_const (asm_out_file, symbol);
19704 fputs (")@fixup\n", asm_out_file);
19707 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19711 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19713 const char *section = ".dtors";
19716 if (priority != DEFAULT_INIT_PRIORITY)
19718 sprintf (buf, ".dtors.%.5u",
19719 /* Invert the numbering so the linker puts us in the proper
19720 order; constructors are run from right to left, and the
19721 linker sorts in increasing order. */
19722 MAX_INIT_PRIORITY - priority);
19726 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19727 assemble_align (POINTER_SIZE);
19729 if (TARGET_RELOCATABLE)
19731 fputs ("\t.long (", asm_out_file);
19732 output_addr_const (asm_out_file, symbol);
19733 fputs (")@fixup\n", asm_out_file);
19736 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19740 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19744 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19745 ASM_OUTPUT_LABEL (file, name);
19746 fputs (DOUBLE_INT_ASM_OP, file);
19747 rs6000_output_function_entry (file, name);
19748 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19751 fputs ("\t.size\t", file);
19752 assemble_name (file, name);
19753 fputs (",24\n\t.type\t.", file);
19754 assemble_name (file, name);
19755 fputs (",@function\n", file);
19756 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19758 fputs ("\t.globl\t.", file);
19759 assemble_name (file, name);
19764 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19765 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19766 rs6000_output_function_entry (file, name);
19767 fputs (":\n", file);
19771 if (TARGET_RELOCATABLE
19772 && !TARGET_SECURE_PLT
19773 && (get_pool_size () != 0 || current_function_profile)
19778 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19780 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19781 fprintf (file, "\t.long ");
19782 assemble_name (file, buf);
19784 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19785 assemble_name (file, buf);
19789 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19790 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19792 if (DEFAULT_ABI == ABI_AIX)
19794 const char *desc_name, *orig_name;
19796 orig_name = (*targetm.strip_name_encoding) (name);
19797 desc_name = orig_name;
19798 while (*desc_name == '.')
19801 if (TREE_PUBLIC (decl))
19802 fprintf (file, "\t.globl %s\n", desc_name);
19804 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19805 fprintf (file, "%s:\n", desc_name);
19806 fprintf (file, "\t.long %s\n", orig_name);
19807 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19808 if (DEFAULT_ABI == ABI_AIX)
19809 fputs ("\t.long 0\n", file);
19810 fprintf (file, "\t.previous\n");
19812 ASM_OUTPUT_LABEL (file, name);
19816 rs6000_elf_end_indicate_exec_stack (void)
19819 file_end_indicate_exec_stack ();
19825 rs6000_xcoff_asm_output_anchor (rtx symbol)
19829 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19830 SYMBOL_REF_BLOCK_OFFSET (symbol));
19831 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19835 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19837 fputs (GLOBAL_ASM_OP, stream);
19838 RS6000_OUTPUT_BASENAME (stream, name);
19839 putc ('\n', stream);
19842 /* A get_unnamed_decl callback, used for read-only sections. PTR
19843 points to the section string variable. */
19846 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19848 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19849 *(const char *const *) directive);
19852 /* Likewise for read-write sections. */
19855 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19857 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19858 *(const char *const *) directive);
19861 /* A get_unnamed_section callback, used for switching to toc_section. */
19864 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19866 if (TARGET_MINIMAL_TOC)
19868 /* toc_section is always selected at least once from
19869 rs6000_xcoff_file_start, so this is guaranteed to
19870 always be defined once and only once in each file. */
19871 if (!toc_initialized)
19873 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19874 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19875 toc_initialized = 1;
19877 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19878 (TARGET_32BIT ? "" : ",3"));
19881 fputs ("\t.toc\n", asm_out_file);
19884 /* Implement TARGET_ASM_INIT_SECTIONS. */
19887 rs6000_xcoff_asm_init_sections (void)
19889 read_only_data_section
19890 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19891 &xcoff_read_only_section_name);
19893 private_data_section
19894 = get_unnamed_section (SECTION_WRITE,
19895 rs6000_xcoff_output_readwrite_section_asm_op,
19896 &xcoff_private_data_section_name);
19898 read_only_private_data_section
19899 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19900 &xcoff_private_data_section_name);
19903 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19905 readonly_data_section = read_only_data_section;
19906 exception_section = data_section;
19910 rs6000_xcoff_reloc_rw_mask (void)
19916 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19917 tree decl ATTRIBUTE_UNUSED)
19920 static const char * const suffix[3] = { "PR", "RO", "RW" };
19922 if (flags & SECTION_CODE)
19924 else if (flags & SECTION_WRITE)
19929 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19930 (flags & SECTION_CODE) ? "." : "",
19931 name, suffix[smclass], flags & SECTION_ENTSIZE);
19935 rs6000_xcoff_select_section (tree decl, int reloc,
19936 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19938 if (decl_readonly_section (decl, reloc))
19940 if (TREE_PUBLIC (decl))
19941 return read_only_data_section;
19943 return read_only_private_data_section;
19947 if (TREE_PUBLIC (decl))
19948 return data_section;
19950 return private_data_section;
19955 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19959 /* Use select_section for private and uninitialized data. */
19960 if (!TREE_PUBLIC (decl)
19961 || DECL_COMMON (decl)
19962 || DECL_INITIAL (decl) == NULL_TREE
19963 || DECL_INITIAL (decl) == error_mark_node
19964 || (flag_zero_initialized_in_bss
19965 && initializer_zerop (DECL_INITIAL (decl))))
19968 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19969 name = (*targetm.strip_name_encoding) (name);
19970 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19973 /* Select section for constant in constant pool.
19975 On RS/6000, all constants are in the private read-only data area.
19976 However, if this is being placed in the TOC it must be output as a
19980 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19981 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19983 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19984 return toc_section;
19986 return read_only_private_data_section;
19989 /* Remove any trailing [DS] or the like from the symbol name. */
19991 static const char *
19992 rs6000_xcoff_strip_name_encoding (const char *name)
19997 len = strlen (name);
19998 if (name[len - 1] == ']')
19999 return ggc_alloc_string (name, len - 4);
20004 /* Section attributes. AIX is always PIC. */
20006 static unsigned int
20007 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
20009 unsigned int align;
20010 unsigned int flags = default_section_type_flags (decl, name, reloc);
20012 /* Align to at least UNIT size. */
20013 if (flags & SECTION_CODE)
20014 align = MIN_UNITS_PER_WORD;
20016 /* Increase alignment of large objects if not already stricter. */
20017 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
20018 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
20019 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
20021 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
20024 /* Output at beginning of assembler file.
20026 Initialize the section names for the RS/6000 at this point.
20028 Specify filename, including full path, to assembler.
20030 We want to go into the TOC section so at least one .toc will be emitted.
20031 Also, in order to output proper .bs/.es pairs, we need at least one static
20032 [RW] section emitted.
20034 Finally, declare mcount when profiling to make the assembler happy. */
20037 rs6000_xcoff_file_start (void)
20039 rs6000_gen_section_name (&xcoff_bss_section_name,
20040 main_input_filename, ".bss_");
20041 rs6000_gen_section_name (&xcoff_private_data_section_name,
20042 main_input_filename, ".rw_");
20043 rs6000_gen_section_name (&xcoff_read_only_section_name,
20044 main_input_filename, ".ro_");
20046 fputs ("\t.file\t", asm_out_file);
20047 output_quoted_string (asm_out_file, main_input_filename);
20048 fputc ('\n', asm_out_file);
20049 if (write_symbols != NO_DEBUG)
20050 switch_to_section (private_data_section);
20051 switch_to_section (text_section);
20053 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
20054 rs6000_file_start ();
20057 /* Output at end of assembler file.
20058 On the RS/6000, referencing data should automatically pull in text. */
20061 rs6000_xcoff_file_end (void)
20063 switch_to_section (text_section);
20064 fputs ("_section_.text:\n", asm_out_file);
20065 switch_to_section (data_section);
20066 fputs (TARGET_32BIT
20067 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20070 #endif /* TARGET_XCOFF */
20072 /* Compute a (partial) cost for rtx X. Return true if the complete
20073 cost has been computed, and false if subexpressions should be
20074 scanned. In either case, *TOTAL contains the cost result. */
20077 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
20079 enum machine_mode mode = GET_MODE (x);
20083 /* On the RS/6000, if it is valid in the insn, it is free. */
20085 if (((outer_code == SET
20086 || outer_code == PLUS
20087 || outer_code == MINUS)
20088 && (satisfies_constraint_I (x)
20089 || satisfies_constraint_L (x)))
20090 || (outer_code == AND
20091 && (satisfies_constraint_K (x)
20093 ? satisfies_constraint_L (x)
20094 : satisfies_constraint_J (x))
20095 || mask_operand (x, mode)
20097 && mask64_operand (x, DImode))))
20098 || ((outer_code == IOR || outer_code == XOR)
20099 && (satisfies_constraint_K (x)
20101 ? satisfies_constraint_L (x)
20102 : satisfies_constraint_J (x))))
20103 || outer_code == ASHIFT
20104 || outer_code == ASHIFTRT
20105 || outer_code == LSHIFTRT
20106 || outer_code == ROTATE
20107 || outer_code == ROTATERT
20108 || outer_code == ZERO_EXTRACT
20109 || (outer_code == MULT
20110 && satisfies_constraint_I (x))
20111 || ((outer_code == DIV || outer_code == UDIV
20112 || outer_code == MOD || outer_code == UMOD)
20113 && exact_log2 (INTVAL (x)) >= 0)
20114 || (outer_code == COMPARE
20115 && (satisfies_constraint_I (x)
20116 || satisfies_constraint_K (x)))
20117 || (outer_code == EQ
20118 && (satisfies_constraint_I (x)
20119 || satisfies_constraint_K (x)
20121 ? satisfies_constraint_L (x)
20122 : satisfies_constraint_J (x))))
20123 || (outer_code == GTU
20124 && satisfies_constraint_I (x))
20125 || (outer_code == LTU
20126 && satisfies_constraint_P (x)))
20131 else if ((outer_code == PLUS
20132 && reg_or_add_cint_operand (x, VOIDmode))
20133 || (outer_code == MINUS
20134 && reg_or_sub_cint_operand (x, VOIDmode))
20135 || ((outer_code == SET
20136 || outer_code == IOR
20137 || outer_code == XOR)
20139 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20141 *total = COSTS_N_INSNS (1);
20147 if (mode == DImode && code == CONST_DOUBLE)
20149 if ((outer_code == IOR || outer_code == XOR)
20150 && CONST_DOUBLE_HIGH (x) == 0
20151 && (CONST_DOUBLE_LOW (x)
20152 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20157 else if ((outer_code == AND && and64_2_operand (x, DImode))
20158 || ((outer_code == SET
20159 || outer_code == IOR
20160 || outer_code == XOR)
20161 && CONST_DOUBLE_HIGH (x) == 0))
20163 *total = COSTS_N_INSNS (1);
20173 /* When optimizing for size, MEM should be slightly more expensive
20174 than generating address, e.g., (plus (reg) (const)).
20175 L1 cache latency is about two instructions. */
20176 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20184 if (mode == DFmode)
20186 if (GET_CODE (XEXP (x, 0)) == MULT)
20188 /* FNMA accounted in outer NEG. */
20189 if (outer_code == NEG)
20190 *total = rs6000_cost->dmul - rs6000_cost->fp;
20192 *total = rs6000_cost->dmul;
20195 *total = rs6000_cost->fp;
20197 else if (mode == SFmode)
20199 /* FNMA accounted in outer NEG. */
20200 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20203 *total = rs6000_cost->fp;
20206 *total = COSTS_N_INSNS (1);
20210 if (mode == DFmode)
20212 if (GET_CODE (XEXP (x, 0)) == MULT
20213 || GET_CODE (XEXP (x, 1)) == MULT)
20215 /* FNMA accounted in outer NEG. */
20216 if (outer_code == NEG)
20217 *total = rs6000_cost->dmul - rs6000_cost->fp;
20219 *total = rs6000_cost->dmul;
20222 *total = rs6000_cost->fp;
20224 else if (mode == SFmode)
20226 /* FNMA accounted in outer NEG. */
20227 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20230 *total = rs6000_cost->fp;
20233 *total = COSTS_N_INSNS (1);
20237 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20238 && satisfies_constraint_I (XEXP (x, 1)))
20240 if (INTVAL (XEXP (x, 1)) >= -256
20241 && INTVAL (XEXP (x, 1)) <= 255)
20242 *total = rs6000_cost->mulsi_const9;
20244 *total = rs6000_cost->mulsi_const;
20246 /* FMA accounted in outer PLUS/MINUS. */
20247 else if ((mode == DFmode || mode == SFmode)
20248 && (outer_code == PLUS || outer_code == MINUS))
20250 else if (mode == DFmode)
20251 *total = rs6000_cost->dmul;
20252 else if (mode == SFmode)
20253 *total = rs6000_cost->fp;
20254 else if (mode == DImode)
20255 *total = rs6000_cost->muldi;
20257 *total = rs6000_cost->mulsi;
20262 if (FLOAT_MODE_P (mode))
20264 *total = mode == DFmode ? rs6000_cost->ddiv
20265 : rs6000_cost->sdiv;
20272 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20273 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20275 if (code == DIV || code == MOD)
20277 *total = COSTS_N_INSNS (2);
20280 *total = COSTS_N_INSNS (1);
20284 if (GET_MODE (XEXP (x, 1)) == DImode)
20285 *total = rs6000_cost->divdi;
20287 *total = rs6000_cost->divsi;
20289 /* Add in shift and subtract for MOD. */
20290 if (code == MOD || code == UMOD)
20291 *total += COSTS_N_INSNS (2);
20295 *total = COSTS_N_INSNS (4);
20299 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20310 *total = COSTS_N_INSNS (1);
20318 /* Handle mul_highpart. */
20319 if (outer_code == TRUNCATE
20320 && GET_CODE (XEXP (x, 0)) == MULT)
20322 if (mode == DImode)
20323 *total = rs6000_cost->muldi;
20325 *total = rs6000_cost->mulsi;
20328 else if (outer_code == AND)
20331 *total = COSTS_N_INSNS (1);
20336 if (GET_CODE (XEXP (x, 0)) == MEM)
20339 *total = COSTS_N_INSNS (1);
20345 if (!FLOAT_MODE_P (mode))
20347 *total = COSTS_N_INSNS (1);
20353 case UNSIGNED_FLOAT:
20356 case FLOAT_TRUNCATE:
20357 *total = rs6000_cost->fp;
20361 if (mode == DFmode)
20364 *total = rs6000_cost->fp;
20368 switch (XINT (x, 1))
20371 *total = rs6000_cost->fp;
20383 *total = COSTS_N_INSNS (1);
20386 else if (FLOAT_MODE_P (mode)
20387 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20389 *total = rs6000_cost->fp;
20397 /* Carry bit requires mode == Pmode.
20398 NEG or PLUS already counted so only add one. */
20400 && (outer_code == NEG || outer_code == PLUS))
20402 *total = COSTS_N_INSNS (1);
20405 if (outer_code == SET)
20407 if (XEXP (x, 1) == const0_rtx)
20409 *total = COSTS_N_INSNS (2);
20412 else if (mode == Pmode)
20414 *total = COSTS_N_INSNS (3);
20423 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20425 *total = COSTS_N_INSNS (2);
20429 if (outer_code == COMPARE)
20443 /* A C expression returning the cost of moving data from a register of class
20444 CLASS1 to one of CLASS2. */
20447 rs6000_register_move_cost (enum machine_mode mode,
20448 enum reg_class from, enum reg_class to)
20450 /* Moves from/to GENERAL_REGS. */
20451 if (reg_classes_intersect_p (to, GENERAL_REGS)
20452 || reg_classes_intersect_p (from, GENERAL_REGS))
20454 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20457 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20458 return (rs6000_memory_move_cost (mode, from, 0)
20459 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20461 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20463 else if (from == CR_REGS)
20467 /* A move will cost one instruction per GPR moved. */
20468 return 2 * hard_regno_nregs[0][mode];
20471 /* Moving between two similar registers is just one instruction. */
20472 else if (reg_classes_intersect_p (to, from))
20473 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20475 /* Everything else has to go through GENERAL_REGS. */
20477 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20478 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20481 /* A C expressions returning the cost of moving data of MODE from a register to
20485 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20486 int in ATTRIBUTE_UNUSED)
20488 if (reg_classes_intersect_p (class, GENERAL_REGS))
20489 return 4 * hard_regno_nregs[0][mode];
20490 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20491 return 4 * hard_regno_nregs[32][mode];
20492 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20493 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20495 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20498 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20499 Assumes no trapping math and finite arguments. */
20502 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20504 rtx x0, e0, e1, y1, u0, v0, one;
20506 x0 = gen_reg_rtx (SFmode);
20507 e0 = gen_reg_rtx (SFmode);
20508 e1 = gen_reg_rtx (SFmode);
20509 y1 = gen_reg_rtx (SFmode);
20510 u0 = gen_reg_rtx (SFmode);
20511 v0 = gen_reg_rtx (SFmode);
20512 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20514 /* x0 = 1./d estimate */
20515 emit_insn (gen_rtx_SET (VOIDmode, x0,
20516 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20518 /* e0 = 1. - d * x0 */
20519 emit_insn (gen_rtx_SET (VOIDmode, e0,
20520 gen_rtx_MINUS (SFmode, one,
20521 gen_rtx_MULT (SFmode, d, x0))));
20522 /* e1 = e0 + e0 * e0 */
20523 emit_insn (gen_rtx_SET (VOIDmode, e1,
20524 gen_rtx_PLUS (SFmode,
20525 gen_rtx_MULT (SFmode, e0, e0), e0)));
20526 /* y1 = x0 + e1 * x0 */
20527 emit_insn (gen_rtx_SET (VOIDmode, y1,
20528 gen_rtx_PLUS (SFmode,
20529 gen_rtx_MULT (SFmode, e1, x0), x0)));
20531 emit_insn (gen_rtx_SET (VOIDmode, u0,
20532 gen_rtx_MULT (SFmode, n, y1)));
20533 /* v0 = n - d * u0 */
20534 emit_insn (gen_rtx_SET (VOIDmode, v0,
20535 gen_rtx_MINUS (SFmode, n,
20536 gen_rtx_MULT (SFmode, d, u0))));
20537 /* res = u0 + v0 * y1 */
20538 emit_insn (gen_rtx_SET (VOIDmode, res,
20539 gen_rtx_PLUS (SFmode,
20540 gen_rtx_MULT (SFmode, v0, y1), u0)));
20543 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20544 Assumes no trapping math and finite arguments. */
20547 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20549 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20551 x0 = gen_reg_rtx (DFmode);
20552 e0 = gen_reg_rtx (DFmode);
20553 e1 = gen_reg_rtx (DFmode);
20554 e2 = gen_reg_rtx (DFmode);
20555 y1 = gen_reg_rtx (DFmode);
20556 y2 = gen_reg_rtx (DFmode);
20557 y3 = gen_reg_rtx (DFmode);
20558 u0 = gen_reg_rtx (DFmode);
20559 v0 = gen_reg_rtx (DFmode);
20560 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20562 /* x0 = 1./d estimate */
20563 emit_insn (gen_rtx_SET (VOIDmode, x0,
20564 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20566 /* e0 = 1. - d * x0 */
20567 emit_insn (gen_rtx_SET (VOIDmode, e0,
20568 gen_rtx_MINUS (DFmode, one,
20569 gen_rtx_MULT (SFmode, d, x0))));
20570 /* y1 = x0 + e0 * x0 */
20571 emit_insn (gen_rtx_SET (VOIDmode, y1,
20572 gen_rtx_PLUS (DFmode,
20573 gen_rtx_MULT (DFmode, e0, x0), x0)));
20575 emit_insn (gen_rtx_SET (VOIDmode, e1,
20576 gen_rtx_MULT (DFmode, e0, e0)));
20577 /* y2 = y1 + e1 * y1 */
20578 emit_insn (gen_rtx_SET (VOIDmode, y2,
20579 gen_rtx_PLUS (DFmode,
20580 gen_rtx_MULT (DFmode, e1, y1), y1)));
20582 emit_insn (gen_rtx_SET (VOIDmode, e2,
20583 gen_rtx_MULT (DFmode, e1, e1)));
20584 /* y3 = y2 + e2 * y2 */
20585 emit_insn (gen_rtx_SET (VOIDmode, y3,
20586 gen_rtx_PLUS (DFmode,
20587 gen_rtx_MULT (DFmode, e2, y2), y2)));
20589 emit_insn (gen_rtx_SET (VOIDmode, u0,
20590 gen_rtx_MULT (DFmode, n, y3)));
20591 /* v0 = n - d * u0 */
20592 emit_insn (gen_rtx_SET (VOIDmode, v0,
20593 gen_rtx_MINUS (DFmode, n,
20594 gen_rtx_MULT (DFmode, d, u0))));
20595 /* res = u0 + v0 * y3 */
20596 emit_insn (gen_rtx_SET (VOIDmode, res,
20597 gen_rtx_PLUS (DFmode,
20598 gen_rtx_MULT (DFmode, v0, y3), u0)));
20602 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20603 target, and SRC is the argument operand. */
20606 rs6000_emit_popcount (rtx dst, rtx src)
20608 enum machine_mode mode = GET_MODE (dst);
20611 tmp1 = gen_reg_rtx (mode);
20613 if (mode == SImode)
20615 emit_insn (gen_popcntbsi2 (tmp1, src));
20616 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20618 tmp2 = force_reg (SImode, tmp2);
20619 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20623 emit_insn (gen_popcntbdi2 (tmp1, src));
20624 tmp2 = expand_mult (DImode, tmp1,
20625 GEN_INT ((HOST_WIDE_INT)
20626 0x01010101 << 32 | 0x01010101),
20628 tmp2 = force_reg (DImode, tmp2);
20629 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20634 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20635 target, and SRC is the argument operand. */
20638 rs6000_emit_parity (rtx dst, rtx src)
20640 enum machine_mode mode = GET_MODE (dst);
20643 tmp = gen_reg_rtx (mode);
20644 if (mode == SImode)
20646 /* Is mult+shift >= shift+xor+shift+xor? */
20647 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20649 rtx tmp1, tmp2, tmp3, tmp4;
20651 tmp1 = gen_reg_rtx (SImode);
20652 emit_insn (gen_popcntbsi2 (tmp1, src));
20654 tmp2 = gen_reg_rtx (SImode);
20655 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20656 tmp3 = gen_reg_rtx (SImode);
20657 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20659 tmp4 = gen_reg_rtx (SImode);
20660 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20661 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20664 rs6000_emit_popcount (tmp, src);
20665 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20669 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20670 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20672 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20674 tmp1 = gen_reg_rtx (DImode);
20675 emit_insn (gen_popcntbdi2 (tmp1, src));
20677 tmp2 = gen_reg_rtx (DImode);
20678 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20679 tmp3 = gen_reg_rtx (DImode);
20680 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20682 tmp4 = gen_reg_rtx (DImode);
20683 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20684 tmp5 = gen_reg_rtx (DImode);
20685 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20687 tmp6 = gen_reg_rtx (DImode);
20688 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20689 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20692 rs6000_emit_popcount (tmp, src);
20693 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20697 /* Return an RTX representing where to find the function value of a
20698 function returning MODE. */
20700 rs6000_complex_function_value (enum machine_mode mode)
20702 unsigned int regno;
20704 enum machine_mode inner = GET_MODE_INNER (mode);
20705 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20707 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20708 regno = FP_ARG_RETURN;
20711 regno = GP_ARG_RETURN;
20713 /* 32-bit is OK since it'll go in r3/r4. */
20714 if (TARGET_32BIT && inner_bytes >= 4)
20715 return gen_rtx_REG (mode, regno);
20718 if (inner_bytes >= 8)
20719 return gen_rtx_REG (mode, regno);
20721 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20723 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20724 GEN_INT (inner_bytes));
20725 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20728 /* Define how to find the value returned by a function.
20729 VALTYPE is the data type of the value (as a tree).
20730 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20731 otherwise, FUNC is 0.
20733 On the SPE, both FPs and vectors are returned in r3.
20735 On RS/6000 an integer value is in r3 and a floating-point value is in
20736 fp1, unless -msoft-float. */
20739 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20741 enum machine_mode mode;
20742 unsigned int regno;
20744 /* Special handling for structs in darwin64. */
20745 if (rs6000_darwin64_abi
20746 && TYPE_MODE (valtype) == BLKmode
20747 && TREE_CODE (valtype) == RECORD_TYPE
20748 && int_size_in_bytes (valtype) > 0)
20750 CUMULATIVE_ARGS valcum;
20754 valcum.fregno = FP_ARG_MIN_REG;
20755 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20756 /* Do a trial code generation as if this were going to be passed as
20757 an argument; if any part goes in memory, we return NULL. */
20758 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20761 /* Otherwise fall through to standard ABI rules. */
20764 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20766 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20767 return gen_rtx_PARALLEL (DImode,
20769 gen_rtx_EXPR_LIST (VOIDmode,
20770 gen_rtx_REG (SImode, GP_ARG_RETURN),
20772 gen_rtx_EXPR_LIST (VOIDmode,
20773 gen_rtx_REG (SImode,
20774 GP_ARG_RETURN + 1),
20777 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20779 return gen_rtx_PARALLEL (DCmode,
20781 gen_rtx_EXPR_LIST (VOIDmode,
20782 gen_rtx_REG (SImode, GP_ARG_RETURN),
20784 gen_rtx_EXPR_LIST (VOIDmode,
20785 gen_rtx_REG (SImode,
20786 GP_ARG_RETURN + 1),
20788 gen_rtx_EXPR_LIST (VOIDmode,
20789 gen_rtx_REG (SImode,
20790 GP_ARG_RETURN + 2),
20792 gen_rtx_EXPR_LIST (VOIDmode,
20793 gen_rtx_REG (SImode,
20794 GP_ARG_RETURN + 3),
20798 mode = TYPE_MODE (valtype);
20799 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20800 || POINTER_TYPE_P (valtype))
20801 mode = TARGET_32BIT ? SImode : DImode;
20803 if (DECIMAL_FLOAT_MODE_P (mode))
20805 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20810 gcc_unreachable ();
20812 regno = GP_ARG_RETURN;
20815 regno = FP_ARG_RETURN;
20818 /* Use f2:f3 specified by the ABI. */
20819 regno = FP_ARG_RETURN + 1;
20824 regno = GP_ARG_RETURN;
20826 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20827 regno = FP_ARG_RETURN;
20828 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20829 && targetm.calls.split_complex_arg)
20830 return rs6000_complex_function_value (mode);
20831 else if (TREE_CODE (valtype) == VECTOR_TYPE
20832 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20833 && ALTIVEC_VECTOR_MODE (mode))
20834 regno = ALTIVEC_ARG_RETURN;
20835 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20836 && (mode == DFmode || mode == DCmode
20837 || mode == TFmode || mode == TCmode))
20838 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20840 regno = GP_ARG_RETURN;
20842 return gen_rtx_REG (mode, regno);
20845 /* Define how to find the value returned by a library function
20846 assuming the value has mode MODE. */
20848 rs6000_libcall_value (enum machine_mode mode)
20850 unsigned int regno;
20852 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20854 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20855 return gen_rtx_PARALLEL (DImode,
20857 gen_rtx_EXPR_LIST (VOIDmode,
20858 gen_rtx_REG (SImode, GP_ARG_RETURN),
20860 gen_rtx_EXPR_LIST (VOIDmode,
20861 gen_rtx_REG (SImode,
20862 GP_ARG_RETURN + 1),
20866 if (DECIMAL_FLOAT_MODE_P (mode))
20868 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20873 gcc_unreachable ();
20875 regno = GP_ARG_RETURN;
20878 regno = FP_ARG_RETURN;
20881 /* Use f2:f3 specified by the ABI. */
20882 regno = FP_ARG_RETURN + 1;
20887 regno = GP_ARG_RETURN;
20889 else if (SCALAR_FLOAT_MODE_P (mode)
20890 && TARGET_HARD_FLOAT && TARGET_FPRS)
20891 regno = FP_ARG_RETURN;
20892 else if (ALTIVEC_VECTOR_MODE (mode)
20893 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20894 regno = ALTIVEC_ARG_RETURN;
20895 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20896 return rs6000_complex_function_value (mode);
20897 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20898 && (mode == DFmode || mode == DCmode
20899 || mode == TFmode || mode == TCmode))
20900 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20902 regno = GP_ARG_RETURN;
20904 return gen_rtx_REG (mode, regno);
20907 /* Define the offset between two registers, FROM to be eliminated and its
20908 replacement TO, at the start of a routine. */
20910 rs6000_initial_elimination_offset (int from, int to)
20912 rs6000_stack_t *info = rs6000_stack_info ();
20913 HOST_WIDE_INT offset;
20915 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20916 offset = info->push_p ? 0 : -info->total_size;
20917 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20919 offset = info->push_p ? 0 : -info->total_size;
20920 if (FRAME_GROWS_DOWNWARD)
20921 offset += info->fixed_size + info->vars_size + info->parm_size;
20923 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20924 offset = FRAME_GROWS_DOWNWARD
20925 ? info->fixed_size + info->vars_size + info->parm_size
20927 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20928 offset = info->total_size;
20929 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20930 offset = info->push_p ? info->total_size : 0;
20931 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20934 gcc_unreachable ();
20939 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20942 rs6000_is_opaque_type (tree type)
20944 return (type == opaque_V2SI_type_node
20945 || type == opaque_V2SF_type_node
20946 || type == opaque_p_V2SI_type_node
20947 || type == opaque_V4SI_type_node);
20951 rs6000_dwarf_register_span (rtx reg)
20956 && (SPE_VECTOR_MODE (GET_MODE (reg))
20957 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20962 regno = REGNO (reg);
20964 /* The duality of the SPE register size wreaks all kinds of havoc.
20965 This is a way of distinguishing r0 in 32-bits from r0 in
20968 gen_rtx_PARALLEL (VOIDmode,
20971 gen_rtx_REG (SImode, regno + 1200),
20972 gen_rtx_REG (SImode, regno))
20974 gen_rtx_REG (SImode, regno),
20975 gen_rtx_REG (SImode, regno + 1200)));
20978 /* Fill in sizes for SPE register high parts in table used by unwinder. */
20981 rs6000_init_dwarf_reg_sizes_extra (tree address)
20986 enum machine_mode mode = TYPE_MODE (char_type_node);
20987 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
20988 rtx mem = gen_rtx_MEM (BLKmode, addr);
20989 rtx value = gen_int_mode (4, mode);
20991 for (i = 1201; i < 1232; i++)
20993 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
20994 HOST_WIDE_INT offset
20995 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
20997 emit_move_insn (adjust_address (mem, mode, offset), value);
21002 /* Map internal gcc register numbers to DWARF2 register numbers. */
21005 rs6000_dbx_register_number (unsigned int regno)
21007 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
21009 if (regno == MQ_REGNO)
21011 if (regno == LR_REGNO)
21013 if (regno == CTR_REGNO)
21015 if (CR_REGNO_P (regno))
21016 return regno - CR0_REGNO + 86;
21017 if (regno == XER_REGNO)
21019 if (ALTIVEC_REGNO_P (regno))
21020 return regno - FIRST_ALTIVEC_REGNO + 1124;
21021 if (regno == VRSAVE_REGNO)
21023 if (regno == VSCR_REGNO)
21025 if (regno == SPE_ACC_REGNO)
21027 if (regno == SPEFSCR_REGNO)
21029 /* SPE high reg number. We get these values of regno from
21030 rs6000_dwarf_register_span. */
21031 gcc_assert (regno >= 1200 && regno < 1232);
21035 /* target hook eh_return_filter_mode */
21036 static enum machine_mode
21037 rs6000_eh_return_filter_mode (void)
21039 return TARGET_32BIT ? SImode : word_mode;
21042 /* Target hook for scalar_mode_supported_p. */
21044 rs6000_scalar_mode_supported_p (enum machine_mode mode)
21046 if (DECIMAL_FLOAT_MODE_P (mode))
21049 return default_scalar_mode_supported_p (mode);
21052 /* Target hook for vector_mode_supported_p. */
21054 rs6000_vector_mode_supported_p (enum machine_mode mode)
21057 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
21060 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
21067 /* Target hook for invalid_arg_for_unprototyped_fn. */
21068 static const char *
21069 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
21071 return (!rs6000_darwin64_abi
21073 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
21074 && (funcdecl == NULL_TREE
21075 || (TREE_CODE (funcdecl) == FUNCTION_DECL
21076 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
21077 ? N_("AltiVec argument passed to unprototyped function")
21081 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21082 setup by using __stack_chk_fail_local hidden function instead of
21083 calling __stack_chk_fail directly. Otherwise it is better to call
21084 __stack_chk_fail directly. */
21087 rs6000_stack_protect_fail (void)
21089 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
21090 ? default_hidden_stack_protect_fail ()
21091 : default_external_stack_protect_fail ();
21094 #include "gt-rs6000.h"