1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
44 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
56 #include "sched-int.h"
58 #include "tree-flow.h"
61 #include "tm-constrs.h"
64 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
67 #include "gstab.h" /* for N_SLINE */
70 #ifndef TARGET_NO_PROTOTYPE
71 #define TARGET_NO_PROTOTYPE 0
74 #define min(A,B) ((A) < (B) ? (A) : (B))
75 #define max(A,B) ((A) > (B) ? (A) : (B))
77 /* Structure used to define the rs6000 stack */
78 typedef struct rs6000_stack {
79 int reload_completed; /* stack info won't change from here on */
80 int first_gp_reg_save; /* first callee saved GP register used */
81 int first_fp_reg_save; /* first callee saved FP register used */
82 int first_altivec_reg_save; /* first callee saved AltiVec register used */
83 int lr_save_p; /* true if the link reg needs to be saved */
84 int cr_save_p; /* true if the CR reg needs to be saved */
85 unsigned int vrsave_mask; /* mask of vec registers to save */
86 int push_p; /* true if we need to allocate stack space */
87 int calls_p; /* true if the function makes any calls */
88 int world_save_p; /* true if we're saving *everything*:
89 r13-r31, cr, f14-f31, vrsave, v20-v31 */
90 enum rs6000_abi abi; /* which ABI to use */
91 int gp_save_offset; /* offset to save GP regs from initial SP */
92 int fp_save_offset; /* offset to save FP regs from initial SP */
93 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
94 int lr_save_offset; /* offset to save LR from initial SP */
95 int cr_save_offset; /* offset to save CR from initial SP */
96 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
97 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
98 int varargs_save_offset; /* offset to save the varargs registers */
99 int ehrd_offset; /* offset to EH return data */
100 int reg_size; /* register size (4 or 8) */
101 HOST_WIDE_INT vars_size; /* variable save area size */
102 int parm_size; /* outgoing parameter size */
103 int save_size; /* save area size */
104 int fixed_size; /* fixed size of stack frame */
105 int gp_size; /* size of saved GP registers */
106 int fp_size; /* size of saved FP registers */
107 int altivec_size; /* size of saved AltiVec registers */
108 int cr_size; /* size to hold CR if not in save_size */
109 int vrsave_size; /* size to hold VRSAVE if not in save_size */
110 int altivec_padding_size; /* size of altivec alignment padding if
112 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
113 int spe_padding_size;
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
119 /* A C structure for machine-specific, per-function data.
120 This is added to the cfun structure. */
121 typedef struct GTY(()) machine_function
123 /* Some local-dynamic symbol. */
124 const char *some_ld_name;
125 /* Whether the instruction chain has been scanned already. */
126 int insn_chain_scanned_p;
127 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
128 int ra_needs_full_frame;
129 /* Flags if __builtin_return_address (0) was used. */
131 /* Cache lr_save_p after expansion of builtin_eh_return. */
133 /* Whether we need to save the TOC to the reserved stack location in the
134 function prologue. */
135 bool save_toc_in_prologue;
136 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
137 varargs save area. */
138 HOST_WIDE_INT varargs_save_offset;
139 /* Temporary stack slot to use for SDmode copies. This slot is
140 64-bits wide and is allocated early enough so that the offset
141 does not overflow the 16-bit load/store offset field. */
142 rtx sdmode_stack_slot;
145 /* Support targetm.vectorize.builtin_mask_for_load. */
146 static GTY(()) tree altivec_builtin_mask_for_load;
148 /* Set to nonzero once AIX common-mode calls have been defined. */
149 static GTY(()) int common_mode_defined;
151 /* Label number of label created for -mrelocatable, to call to so we can
152 get the address of the GOT section */
153 static int rs6000_pic_labelno;
156 /* Counter for labels which are to be placed in .fixup. */
157 int fixuplabelno = 0;
160 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
163 /* Specify the machine mode that pointers have. After generation of rtl, the
164 compiler makes no further distinction between pointers and any other objects
165 of this machine mode. The type is unsigned since not all things that
166 include rs6000.h also include machmode.h. */
167 unsigned rs6000_pmode;
169 /* Width in bits of a pointer. */
170 unsigned rs6000_pointer_size;
172 #ifdef HAVE_AS_GNU_ATTRIBUTE
173 /* Flag whether floating point values have been passed/returned. */
174 static bool rs6000_passes_float;
175 /* Flag whether vector values have been passed/returned. */
176 static bool rs6000_passes_vector;
177 /* Flag whether small (<= 8 byte) structures have been returned. */
178 static bool rs6000_returns_struct;
181 /* Value is TRUE if register/mode pair is acceptable. */
182 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
184 /* Maximum number of registers needed for a given register class and mode. */
185 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
187 /* How many registers are needed for a given register and mode. */
188 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
190 /* Map register number to register class. */
191 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
193 /* Reload functions based on the type and the vector unit. */
194 static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
196 static int dbg_cost_ctrl;
198 /* Built in types. */
199 tree rs6000_builtin_types[RS6000_BTI_MAX];
200 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
202 /* Flag to say the TOC is initialized */
204 char toc_label_name[10];
206 /* Cached value of rs6000_variable_issue. This is cached in
207 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
208 static short cached_can_issue_more;
210 static GTY(()) section *read_only_data_section;
211 static GTY(()) section *private_data_section;
212 static GTY(()) section *read_only_private_data_section;
213 static GTY(()) section *sdata2_section;
214 static GTY(()) section *toc_section;
216 struct builtin_description
218 const unsigned int mask;
219 const enum insn_code icode;
220 const char *const name;
221 const enum rs6000_builtins code;
224 /* Describe the vector unit used for modes. */
225 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
226 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
228 /* Register classes for various constraints that are based on the target
230 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
232 /* Describe the alignment of a vector. */
233 int rs6000_vector_align[NUM_MACHINE_MODES];
235 /* Map selected modes to types for builtins. */
236 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
238 /* What modes to automatically generate reciprocal divide estimate (fre) and
239 reciprocal sqrt (frsqrte) for. */
240 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
242 /* Masks to determine which reciprocal esitmate instructions to generate
244 enum rs6000_recip_mask {
245 RECIP_SF_DIV = 0x001, /* Use divide estimate */
246 RECIP_DF_DIV = 0x002,
247 RECIP_V4SF_DIV = 0x004,
248 RECIP_V2DF_DIV = 0x008,
250 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
251 RECIP_DF_RSQRT = 0x020,
252 RECIP_V4SF_RSQRT = 0x040,
253 RECIP_V2DF_RSQRT = 0x080,
255 /* Various combination of flags for -mrecip=xxx. */
257 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
258 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
259 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
261 RECIP_HIGH_PRECISION = RECIP_ALL,
263 /* On low precision machines like the power5, don't enable double precision
264 reciprocal square root estimate, since it isn't accurate enough. */
265 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
268 /* -mrecip options. */
271 const char *string; /* option name */
272 unsigned int mask; /* mask bits to set */
273 } recip_options[] = {
274 { "all", RECIP_ALL },
275 { "none", RECIP_NONE },
276 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
278 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
279 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
280 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
281 | RECIP_V2DF_RSQRT) },
282 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
283 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
286 /* 2 argument gen function typedef. */
287 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
289 /* Pointer to function (in rs6000-c.c) that can define or undefine target
290 macros that have changed. Languages that don't support the preprocessor
291 don't link in rs6000-c.c, so we can't call it directly. */
292 void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
295 /* Target cpu costs. */
297 struct processor_costs {
298 const int mulsi; /* cost of SImode multiplication. */
299 const int mulsi_const; /* cost of SImode multiplication by constant. */
300 const int mulsi_const9; /* cost of SImode mult by short constant. */
301 const int muldi; /* cost of DImode multiplication. */
302 const int divsi; /* cost of SImode division. */
303 const int divdi; /* cost of DImode division. */
304 const int fp; /* cost of simple SFmode and DFmode insns. */
305 const int dmul; /* cost of DFmode multiplication (and fmadd). */
306 const int sdiv; /* cost of SFmode division (fdivs). */
307 const int ddiv; /* cost of DFmode division (fdiv). */
308 const int cache_line_size; /* cache line size in bytes. */
309 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
310 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
311 const int simultaneous_prefetches; /* number of parallel prefetch
315 const struct processor_costs *rs6000_cost;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost = {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
338 /* Instruction size costs on 64bit processors. */
340 struct processor_costs size64_cost = {
341 COSTS_N_INSNS (1), /* mulsi */
342 COSTS_N_INSNS (1), /* mulsi_const */
343 COSTS_N_INSNS (1), /* mulsi_const9 */
344 COSTS_N_INSNS (1), /* muldi */
345 COSTS_N_INSNS (1), /* divsi */
346 COSTS_N_INSNS (1), /* divdi */
347 COSTS_N_INSNS (1), /* fp */
348 COSTS_N_INSNS (1), /* dmul */
349 COSTS_N_INSNS (1), /* sdiv */
350 COSTS_N_INSNS (1), /* ddiv */
357 /* Instruction costs on RIOS1 processors. */
359 struct processor_costs rios1_cost = {
360 COSTS_N_INSNS (5), /* mulsi */
361 COSTS_N_INSNS (4), /* mulsi_const */
362 COSTS_N_INSNS (3), /* mulsi_const9 */
363 COSTS_N_INSNS (5), /* muldi */
364 COSTS_N_INSNS (19), /* divsi */
365 COSTS_N_INSNS (19), /* divdi */
366 COSTS_N_INSNS (2), /* fp */
367 COSTS_N_INSNS (2), /* dmul */
368 COSTS_N_INSNS (19), /* sdiv */
369 COSTS_N_INSNS (19), /* ddiv */
370 128, /* cache line size */
376 /* Instruction costs on RIOS2 processors. */
378 struct processor_costs rios2_cost = {
379 COSTS_N_INSNS (2), /* mulsi */
380 COSTS_N_INSNS (2), /* mulsi_const */
381 COSTS_N_INSNS (2), /* mulsi_const9 */
382 COSTS_N_INSNS (2), /* muldi */
383 COSTS_N_INSNS (13), /* divsi */
384 COSTS_N_INSNS (13), /* divdi */
385 COSTS_N_INSNS (2), /* fp */
386 COSTS_N_INSNS (2), /* dmul */
387 COSTS_N_INSNS (17), /* sdiv */
388 COSTS_N_INSNS (17), /* ddiv */
389 256, /* cache line size */
395 /* Instruction costs on RS64A processors. */
397 struct processor_costs rs64a_cost = {
398 COSTS_N_INSNS (20), /* mulsi */
399 COSTS_N_INSNS (12), /* mulsi_const */
400 COSTS_N_INSNS (8), /* mulsi_const9 */
401 COSTS_N_INSNS (34), /* muldi */
402 COSTS_N_INSNS (65), /* divsi */
403 COSTS_N_INSNS (67), /* divdi */
404 COSTS_N_INSNS (4), /* fp */
405 COSTS_N_INSNS (4), /* dmul */
406 COSTS_N_INSNS (31), /* sdiv */
407 COSTS_N_INSNS (31), /* ddiv */
408 128, /* cache line size */
414 /* Instruction costs on MPCCORE processors. */
416 struct processor_costs mpccore_cost = {
417 COSTS_N_INSNS (2), /* mulsi */
418 COSTS_N_INSNS (2), /* mulsi_const */
419 COSTS_N_INSNS (2), /* mulsi_const9 */
420 COSTS_N_INSNS (2), /* muldi */
421 COSTS_N_INSNS (6), /* divsi */
422 COSTS_N_INSNS (6), /* divdi */
423 COSTS_N_INSNS (4), /* fp */
424 COSTS_N_INSNS (5), /* dmul */
425 COSTS_N_INSNS (10), /* sdiv */
426 COSTS_N_INSNS (17), /* ddiv */
427 32, /* cache line size */
433 /* Instruction costs on PPC403 processors. */
435 struct processor_costs ppc403_cost = {
436 COSTS_N_INSNS (4), /* mulsi */
437 COSTS_N_INSNS (4), /* mulsi_const */
438 COSTS_N_INSNS (4), /* mulsi_const9 */
439 COSTS_N_INSNS (4), /* muldi */
440 COSTS_N_INSNS (33), /* divsi */
441 COSTS_N_INSNS (33), /* divdi */
442 COSTS_N_INSNS (11), /* fp */
443 COSTS_N_INSNS (11), /* dmul */
444 COSTS_N_INSNS (11), /* sdiv */
445 COSTS_N_INSNS (11), /* ddiv */
446 32, /* cache line size */
452 /* Instruction costs on PPC405 processors. */
454 struct processor_costs ppc405_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (4), /* mulsi_const */
457 COSTS_N_INSNS (3), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (35), /* divsi */
460 COSTS_N_INSNS (35), /* divdi */
461 COSTS_N_INSNS (11), /* fp */
462 COSTS_N_INSNS (11), /* dmul */
463 COSTS_N_INSNS (11), /* sdiv */
464 COSTS_N_INSNS (11), /* ddiv */
465 32, /* cache line size */
471 /* Instruction costs on PPC440 processors. */
473 struct processor_costs ppc440_cost = {
474 COSTS_N_INSNS (3), /* mulsi */
475 COSTS_N_INSNS (2), /* mulsi_const */
476 COSTS_N_INSNS (2), /* mulsi_const9 */
477 COSTS_N_INSNS (3), /* muldi */
478 COSTS_N_INSNS (34), /* divsi */
479 COSTS_N_INSNS (34), /* divdi */
480 COSTS_N_INSNS (5), /* fp */
481 COSTS_N_INSNS (5), /* dmul */
482 COSTS_N_INSNS (19), /* sdiv */
483 COSTS_N_INSNS (33), /* ddiv */
484 32, /* cache line size */
490 /* Instruction costs on PPC476 processors. */
492 struct processor_costs ppc476_cost = {
493 COSTS_N_INSNS (4), /* mulsi */
494 COSTS_N_INSNS (4), /* mulsi_const */
495 COSTS_N_INSNS (4), /* mulsi_const9 */
496 COSTS_N_INSNS (4), /* muldi */
497 COSTS_N_INSNS (11), /* divsi */
498 COSTS_N_INSNS (11), /* divdi */
499 COSTS_N_INSNS (6), /* fp */
500 COSTS_N_INSNS (6), /* dmul */
501 COSTS_N_INSNS (19), /* sdiv */
502 COSTS_N_INSNS (33), /* ddiv */
503 32, /* l1 cache line size */
509 /* Instruction costs on PPC601 processors. */
511 struct processor_costs ppc601_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (5), /* mulsi_const */
514 COSTS_N_INSNS (5), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (36), /* divsi */
517 COSTS_N_INSNS (36), /* divdi */
518 COSTS_N_INSNS (4), /* fp */
519 COSTS_N_INSNS (5), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (31), /* ddiv */
522 32, /* cache line size */
528 /* Instruction costs on PPC603 processors. */
530 struct processor_costs ppc603_cost = {
531 COSTS_N_INSNS (5), /* mulsi */
532 COSTS_N_INSNS (3), /* mulsi_const */
533 COSTS_N_INSNS (2), /* mulsi_const9 */
534 COSTS_N_INSNS (5), /* muldi */
535 COSTS_N_INSNS (37), /* divsi */
536 COSTS_N_INSNS (37), /* divdi */
537 COSTS_N_INSNS (3), /* fp */
538 COSTS_N_INSNS (4), /* dmul */
539 COSTS_N_INSNS (18), /* sdiv */
540 COSTS_N_INSNS (33), /* ddiv */
541 32, /* cache line size */
547 /* Instruction costs on PPC604 processors. */
549 struct processor_costs ppc604_cost = {
550 COSTS_N_INSNS (4), /* mulsi */
551 COSTS_N_INSNS (4), /* mulsi_const */
552 COSTS_N_INSNS (4), /* mulsi_const9 */
553 COSTS_N_INSNS (4), /* muldi */
554 COSTS_N_INSNS (20), /* divsi */
555 COSTS_N_INSNS (20), /* divdi */
556 COSTS_N_INSNS (3), /* fp */
557 COSTS_N_INSNS (3), /* dmul */
558 COSTS_N_INSNS (18), /* sdiv */
559 COSTS_N_INSNS (32), /* ddiv */
560 32, /* cache line size */
566 /* Instruction costs on PPC604e processors. */
568 struct processor_costs ppc604e_cost = {
569 COSTS_N_INSNS (2), /* mulsi */
570 COSTS_N_INSNS (2), /* mulsi_const */
571 COSTS_N_INSNS (2), /* mulsi_const9 */
572 COSTS_N_INSNS (2), /* muldi */
573 COSTS_N_INSNS (20), /* divsi */
574 COSTS_N_INSNS (20), /* divdi */
575 COSTS_N_INSNS (3), /* fp */
576 COSTS_N_INSNS (3), /* dmul */
577 COSTS_N_INSNS (18), /* sdiv */
578 COSTS_N_INSNS (32), /* ddiv */
579 32, /* cache line size */
585 /* Instruction costs on PPC620 processors. */
587 struct processor_costs ppc620_cost = {
588 COSTS_N_INSNS (5), /* mulsi */
589 COSTS_N_INSNS (4), /* mulsi_const */
590 COSTS_N_INSNS (3), /* mulsi_const9 */
591 COSTS_N_INSNS (7), /* muldi */
592 COSTS_N_INSNS (21), /* divsi */
593 COSTS_N_INSNS (37), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (18), /* sdiv */
597 COSTS_N_INSNS (32), /* ddiv */
598 128, /* cache line size */
604 /* Instruction costs on PPC630 processors. */
606 struct processor_costs ppc630_cost = {
607 COSTS_N_INSNS (5), /* mulsi */
608 COSTS_N_INSNS (4), /* mulsi_const */
609 COSTS_N_INSNS (3), /* mulsi_const9 */
610 COSTS_N_INSNS (7), /* muldi */
611 COSTS_N_INSNS (21), /* divsi */
612 COSTS_N_INSNS (37), /* divdi */
613 COSTS_N_INSNS (3), /* fp */
614 COSTS_N_INSNS (3), /* dmul */
615 COSTS_N_INSNS (17), /* sdiv */
616 COSTS_N_INSNS (21), /* ddiv */
617 128, /* cache line size */
623 /* Instruction costs on Cell processor. */
624 /* COSTS_N_INSNS (1) ~ one add. */
626 struct processor_costs ppccell_cost = {
627 COSTS_N_INSNS (9/2)+2, /* mulsi */
628 COSTS_N_INSNS (6/2), /* mulsi_const */
629 COSTS_N_INSNS (6/2), /* mulsi_const9 */
630 COSTS_N_INSNS (15/2)+2, /* muldi */
631 COSTS_N_INSNS (38/2), /* divsi */
632 COSTS_N_INSNS (70/2), /* divdi */
633 COSTS_N_INSNS (10/2), /* fp */
634 COSTS_N_INSNS (10/2), /* dmul */
635 COSTS_N_INSNS (74/2), /* sdiv */
636 COSTS_N_INSNS (74/2), /* ddiv */
637 128, /* cache line size */
643 /* Instruction costs on PPC750 and PPC7400 processors. */
645 struct processor_costs ppc750_cost = {
646 COSTS_N_INSNS (5), /* mulsi */
647 COSTS_N_INSNS (3), /* mulsi_const */
648 COSTS_N_INSNS (2), /* mulsi_const9 */
649 COSTS_N_INSNS (5), /* muldi */
650 COSTS_N_INSNS (17), /* divsi */
651 COSTS_N_INSNS (17), /* divdi */
652 COSTS_N_INSNS (3), /* fp */
653 COSTS_N_INSNS (3), /* dmul */
654 COSTS_N_INSNS (17), /* sdiv */
655 COSTS_N_INSNS (31), /* ddiv */
656 32, /* cache line size */
662 /* Instruction costs on PPC7450 processors. */
664 struct processor_costs ppc7450_cost = {
665 COSTS_N_INSNS (4), /* mulsi */
666 COSTS_N_INSNS (3), /* mulsi_const */
667 COSTS_N_INSNS (3), /* mulsi_const9 */
668 COSTS_N_INSNS (4), /* muldi */
669 COSTS_N_INSNS (23), /* divsi */
670 COSTS_N_INSNS (23), /* divdi */
671 COSTS_N_INSNS (5), /* fp */
672 COSTS_N_INSNS (5), /* dmul */
673 COSTS_N_INSNS (21), /* sdiv */
674 COSTS_N_INSNS (35), /* ddiv */
675 32, /* cache line size */
681 /* Instruction costs on PPC8540 processors. */
683 struct processor_costs ppc8540_cost = {
684 COSTS_N_INSNS (4), /* mulsi */
685 COSTS_N_INSNS (4), /* mulsi_const */
686 COSTS_N_INSNS (4), /* mulsi_const9 */
687 COSTS_N_INSNS (4), /* muldi */
688 COSTS_N_INSNS (19), /* divsi */
689 COSTS_N_INSNS (19), /* divdi */
690 COSTS_N_INSNS (4), /* fp */
691 COSTS_N_INSNS (4), /* dmul */
692 COSTS_N_INSNS (29), /* sdiv */
693 COSTS_N_INSNS (29), /* ddiv */
694 32, /* cache line size */
697 1, /* prefetch streams /*/
700 /* Instruction costs on E300C2 and E300C3 cores. */
702 struct processor_costs ppce300c2c3_cost = {
703 COSTS_N_INSNS (4), /* mulsi */
704 COSTS_N_INSNS (4), /* mulsi_const */
705 COSTS_N_INSNS (4), /* mulsi_const9 */
706 COSTS_N_INSNS (4), /* muldi */
707 COSTS_N_INSNS (19), /* divsi */
708 COSTS_N_INSNS (19), /* divdi */
709 COSTS_N_INSNS (3), /* fp */
710 COSTS_N_INSNS (4), /* dmul */
711 COSTS_N_INSNS (18), /* sdiv */
712 COSTS_N_INSNS (33), /* ddiv */
716 1, /* prefetch streams /*/
719 /* Instruction costs on PPCE500MC processors. */
721 struct processor_costs ppce500mc_cost = {
722 COSTS_N_INSNS (4), /* mulsi */
723 COSTS_N_INSNS (4), /* mulsi_const */
724 COSTS_N_INSNS (4), /* mulsi_const9 */
725 COSTS_N_INSNS (4), /* muldi */
726 COSTS_N_INSNS (14), /* divsi */
727 COSTS_N_INSNS (14), /* divdi */
728 COSTS_N_INSNS (8), /* fp */
729 COSTS_N_INSNS (10), /* dmul */
730 COSTS_N_INSNS (36), /* sdiv */
731 COSTS_N_INSNS (66), /* ddiv */
732 64, /* cache line size */
735 1, /* prefetch streams /*/
738 /* Instruction costs on PPCE500MC64 processors. */
740 struct processor_costs ppce500mc64_cost = {
741 COSTS_N_INSNS (4), /* mulsi */
742 COSTS_N_INSNS (4), /* mulsi_const */
743 COSTS_N_INSNS (4), /* mulsi_const9 */
744 COSTS_N_INSNS (4), /* muldi */
745 COSTS_N_INSNS (14), /* divsi */
746 COSTS_N_INSNS (14), /* divdi */
747 COSTS_N_INSNS (4), /* fp */
748 COSTS_N_INSNS (10), /* dmul */
749 COSTS_N_INSNS (36), /* sdiv */
750 COSTS_N_INSNS (66), /* ddiv */
751 64, /* cache line size */
754 1, /* prefetch streams /*/
757 /* Instruction costs on AppliedMicro Titan processors. */
759 struct processor_costs titan_cost = {
760 COSTS_N_INSNS (5), /* mulsi */
761 COSTS_N_INSNS (5), /* mulsi_const */
762 COSTS_N_INSNS (5), /* mulsi_const9 */
763 COSTS_N_INSNS (5), /* muldi */
764 COSTS_N_INSNS (18), /* divsi */
765 COSTS_N_INSNS (18), /* divdi */
766 COSTS_N_INSNS (10), /* fp */
767 COSTS_N_INSNS (10), /* dmul */
768 COSTS_N_INSNS (46), /* sdiv */
769 COSTS_N_INSNS (72), /* ddiv */
770 32, /* cache line size */
773 1, /* prefetch streams /*/
776 /* Instruction costs on POWER4 and POWER5 processors. */
778 struct processor_costs power4_cost = {
779 COSTS_N_INSNS (3), /* mulsi */
780 COSTS_N_INSNS (2), /* mulsi_const */
781 COSTS_N_INSNS (2), /* mulsi_const9 */
782 COSTS_N_INSNS (4), /* muldi */
783 COSTS_N_INSNS (18), /* divsi */
784 COSTS_N_INSNS (34), /* divdi */
785 COSTS_N_INSNS (3), /* fp */
786 COSTS_N_INSNS (3), /* dmul */
787 COSTS_N_INSNS (17), /* sdiv */
788 COSTS_N_INSNS (17), /* ddiv */
789 128, /* cache line size */
792 8, /* prefetch streams /*/
795 /* Instruction costs on POWER6 processors. */
797 struct processor_costs power6_cost = {
798 COSTS_N_INSNS (8), /* mulsi */
799 COSTS_N_INSNS (8), /* mulsi_const */
800 COSTS_N_INSNS (8), /* mulsi_const9 */
801 COSTS_N_INSNS (8), /* muldi */
802 COSTS_N_INSNS (22), /* divsi */
803 COSTS_N_INSNS (28), /* divdi */
804 COSTS_N_INSNS (3), /* fp */
805 COSTS_N_INSNS (3), /* dmul */
806 COSTS_N_INSNS (13), /* sdiv */
807 COSTS_N_INSNS (16), /* ddiv */
808 128, /* cache line size */
811 16, /* prefetch streams */
814 /* Instruction costs on POWER7 processors. */
816 struct processor_costs power7_cost = {
817 COSTS_N_INSNS (2), /* mulsi */
818 COSTS_N_INSNS (2), /* mulsi_const */
819 COSTS_N_INSNS (2), /* mulsi_const9 */
820 COSTS_N_INSNS (2), /* muldi */
821 COSTS_N_INSNS (18), /* divsi */
822 COSTS_N_INSNS (34), /* divdi */
823 COSTS_N_INSNS (3), /* fp */
824 COSTS_N_INSNS (3), /* dmul */
825 COSTS_N_INSNS (13), /* sdiv */
826 COSTS_N_INSNS (16), /* ddiv */
827 128, /* cache line size */
830 12, /* prefetch streams */
833 /* Instruction costs on POWER A2 processors. */
835 struct processor_costs ppca2_cost = {
836 COSTS_N_INSNS (16), /* mulsi */
837 COSTS_N_INSNS (16), /* mulsi_const */
838 COSTS_N_INSNS (16), /* mulsi_const9 */
839 COSTS_N_INSNS (16), /* muldi */
840 COSTS_N_INSNS (22), /* divsi */
841 COSTS_N_INSNS (28), /* divdi */
842 COSTS_N_INSNS (3), /* fp */
843 COSTS_N_INSNS (3), /* dmul */
844 COSTS_N_INSNS (59), /* sdiv */
845 COSTS_N_INSNS (72), /* ddiv */
849 16, /* prefetch streams */
853 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
854 #undef RS6000_BUILTIN_1
855 #undef RS6000_BUILTIN_2
856 #undef RS6000_BUILTIN_3
857 #undef RS6000_BUILTIN_A
858 #undef RS6000_BUILTIN_D
859 #undef RS6000_BUILTIN_E
860 #undef RS6000_BUILTIN_P
861 #undef RS6000_BUILTIN_Q
862 #undef RS6000_BUILTIN_S
863 #undef RS6000_BUILTIN_X
865 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
866 { NAME, ICODE, MASK, ATTR },
868 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
869 { NAME, ICODE, MASK, ATTR },
871 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
872 { NAME, ICODE, MASK, ATTR },
874 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
875 { NAME, ICODE, MASK, ATTR },
877 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
878 { NAME, ICODE, MASK, ATTR },
880 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
881 { NAME, ICODE, MASK, ATTR },
883 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
884 { NAME, ICODE, MASK, ATTR },
886 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
887 { NAME, ICODE, MASK, ATTR },
889 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
890 { NAME, ICODE, MASK, ATTR },
892 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
893 { NAME, ICODE, MASK, ATTR },
895 struct rs6000_builtin_info_type {
897 const enum insn_code icode;
902 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
904 #include "rs6000-builtin.def"
907 #undef RS6000_BUILTIN_1
908 #undef RS6000_BUILTIN_2
909 #undef RS6000_BUILTIN_3
910 #undef RS6000_BUILTIN_A
911 #undef RS6000_BUILTIN_D
912 #undef RS6000_BUILTIN_E
913 #undef RS6000_BUILTIN_P
914 #undef RS6000_BUILTIN_Q
915 #undef RS6000_BUILTIN_S
916 #undef RS6000_BUILTIN_X
918 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
919 static tree (*rs6000_veclib_handler) (tree, tree, tree);
922 static bool rs6000_function_ok_for_sibcall (tree, tree);
923 static const char *rs6000_invalid_within_doloop (const_rtx);
924 static bool rs6000_legitimate_address_p (enum machine_mode, rtx, bool);
925 static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
926 static rtx rs6000_generate_compare (rtx, enum machine_mode);
927 static void rs6000_emit_stack_tie (void);
928 static bool spe_func_has_64bit_regs_p (void);
929 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
930 static unsigned rs6000_hash_constant (rtx);
931 static unsigned toc_hash_function (const void *);
932 static int toc_hash_eq (const void *, const void *);
933 static bool reg_offset_addressing_ok_p (enum machine_mode);
934 static bool virtual_stack_registers_memory_p (rtx);
935 static bool constant_pool_expr_p (rtx);
936 static bool legitimate_small_data_p (enum machine_mode, rtx);
937 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
938 static struct machine_function * rs6000_init_machine_status (void);
939 static bool rs6000_assemble_integer (rtx, unsigned int, int);
940 static bool no_global_regs_above (int, bool);
941 #if defined (HAVE_GAS_HIDDEN) && !defined (TARGET_MACHO)
942 static void rs6000_assemble_visibility (tree, int);
944 static int rs6000_ra_ever_killed (void);
945 static bool rs6000_attribute_takes_identifier_p (const_tree);
946 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
947 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
948 static bool rs6000_ms_bitfield_layout_p (const_tree);
949 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
950 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
951 static const char *rs6000_mangle_type (const_tree);
952 static void rs6000_set_default_type_attributes (tree);
953 static rtx rs6000_savres_routine_sym (rs6000_stack_t *, bool, bool, bool);
954 static rtx rs6000_emit_stack_reset (rs6000_stack_t *, rtx, rtx, int, bool);
955 static bool rs6000_reg_live_or_pic_offset_p (int);
956 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
957 static tree rs6000_builtin_vectorized_function (tree, tree, tree);
958 static void rs6000_restore_saved_cr (rtx, int);
959 static bool rs6000_output_addr_const_extra (FILE *, rtx);
960 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
961 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
962 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
964 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
965 static bool rs6000_return_in_memory (const_tree, const_tree);
966 static rtx rs6000_function_value (const_tree, const_tree, bool);
967 static void rs6000_file_start (void);
969 static int rs6000_elf_reloc_rw_mask (void);
970 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
971 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
972 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
973 static void rs6000_elf_asm_init_sections (void);
974 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
975 unsigned HOST_WIDE_INT);
976 static void rs6000_elf_encode_section_info (tree, rtx, int)
979 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
980 static void rs6000_alloc_sdmode_stack_slot (void);
981 static void rs6000_instantiate_decls (void);
983 static void rs6000_xcoff_asm_output_anchor (rtx);
984 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
985 static void rs6000_xcoff_asm_init_sections (void);
986 static int rs6000_xcoff_reloc_rw_mask (void);
987 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
988 static section *rs6000_xcoff_select_section (tree, int,
989 unsigned HOST_WIDE_INT);
990 static void rs6000_xcoff_unique_section (tree, int);
991 static section *rs6000_xcoff_select_rtx_section
992 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
993 static const char * rs6000_xcoff_strip_name_encoding (const char *);
994 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
995 static void rs6000_xcoff_file_start (void);
996 static void rs6000_xcoff_file_end (void);
998 static int rs6000_variable_issue (FILE *, int, rtx, int);
999 static int rs6000_register_move_cost (enum machine_mode,
1000 reg_class_t, reg_class_t);
1001 static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
1002 static bool rs6000_rtx_costs (rtx, int, int, int, int *, bool);
1003 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
1004 static int rs6000_debug_address_cost (rtx, bool);
1005 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
1006 static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
1007 static void rs6000_sched_init (FILE *, int, int);
1008 static bool is_microcoded_insn (rtx);
1009 static bool is_nonpipeline_insn (rtx);
1010 static bool is_cracked_insn (rtx);
1011 static bool is_branch_slot_insn (rtx);
1012 static bool is_load_insn (rtx);
1013 static rtx get_store_dest (rtx pat);
1014 static bool is_store_insn (rtx);
1015 static bool set_to_load_agen (rtx,rtx);
1016 static bool adjacent_mem_locations (rtx,rtx);
1017 static int rs6000_adjust_priority (rtx, int);
1018 static int rs6000_issue_rate (void);
1019 static bool rs6000_is_costly_dependence (dep_t, int, int);
1020 static rtx get_next_active_insn (rtx, rtx);
1021 static bool insn_terminates_group_p (rtx , enum group_termination);
1022 static bool insn_must_be_first_in_group (rtx);
1023 static bool insn_must_be_last_in_group (rtx);
1024 static bool is_costly_group (rtx *, rtx);
1025 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
1026 static int redefine_groups (FILE *, int, rtx, rtx);
1027 static int pad_groups (FILE *, int, rtx, rtx);
1028 static void rs6000_sched_finish (FILE *, int);
1029 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
1030 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
1031 static int rs6000_use_sched_lookahead (void);
1032 static int rs6000_use_sched_lookahead_guard (rtx);
1033 static void * rs6000_alloc_sched_context (void);
1034 static void rs6000_init_sched_context (void *, bool);
1035 static void rs6000_set_sched_context (void *);
1036 static void rs6000_free_sched_context (void *);
1037 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
1038 static tree rs6000_builtin_mask_for_load (void);
1039 static tree rs6000_builtin_mul_widen_even (tree);
1040 static tree rs6000_builtin_mul_widen_odd (tree);
1041 static bool rs6000_builtin_support_vector_misalignment (enum
1045 static int rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt,
1047 static enum machine_mode rs6000_preferred_simd_mode (enum machine_mode);
1049 static void def_builtin (const char *, tree, enum rs6000_builtins);
1050 static bool rs6000_vector_alignment_reachable (const_tree, bool);
1051 static void rs6000_init_builtins (void);
1052 static tree rs6000_builtin_decl (unsigned, bool);
1054 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
1055 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
1056 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
1057 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
1058 static void altivec_init_builtins (void);
1059 static unsigned builtin_hash_function (const void *);
1060 static int builtin_hash_eq (const void *, const void *);
1061 static tree builtin_function_type (enum machine_mode, enum machine_mode,
1062 enum machine_mode, enum machine_mode,
1063 enum rs6000_builtins, const char *name);
1064 static void rs6000_common_init_builtins (void);
1065 static void rs6000_init_libfuncs (void);
1067 static void paired_init_builtins (void);
1068 static rtx paired_expand_builtin (tree, rtx, bool *);
1069 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
1070 static rtx paired_expand_stv_builtin (enum insn_code, tree);
1071 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1073 static void spe_init_builtins (void);
1074 static rtx spe_expand_builtin (tree, rtx, bool *);
1075 static rtx spe_expand_stv_builtin (enum insn_code, tree);
1076 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
1077 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
1078 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
1079 static rs6000_stack_t *rs6000_stack_info (void);
1080 static void debug_stack_info (rs6000_stack_t *);
1082 static rtx altivec_expand_builtin (tree, rtx, bool *);
1083 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
1084 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
1085 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
1086 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
1087 static rtx altivec_expand_predicate_builtin (enum insn_code, tree, rtx);
1088 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
1089 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
1090 static rtx altivec_expand_vec_set_builtin (tree);
1091 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
1092 static int get_element_number (tree, tree);
1093 static void rs6000_option_override (void);
1094 static int rs6000_loop_align_max_skip (rtx);
1095 static int first_altivec_reg_to_save (void);
1096 static unsigned int compute_vrsave_mask (void);
1097 static void compute_save_world_info (rs6000_stack_t *info_ptr);
1098 static void is_altivec_return_reg (rtx, void *);
1099 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
1100 int easy_vector_constant (rtx, enum machine_mode);
1101 static rtx rs6000_dwarf_register_span (rtx);
1102 static void rs6000_init_dwarf_reg_sizes_extra (tree);
1103 static rtx rs6000_legitimize_address (rtx, rtx, enum machine_mode);
1104 static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
1105 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1106 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1107 static rtx rs6000_delegitimize_address (rtx);
1108 static rtx rs6000_tls_get_addr (void);
1109 static rtx rs6000_got_sym (void);
1110 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
1111 static const char *rs6000_get_some_local_dynamic_name (void);
1112 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
1113 static rtx rs6000_complex_function_value (enum machine_mode);
1114 static rtx rs6000_spe_function_arg (const CUMULATIVE_ARGS *,
1115 enum machine_mode, const_tree);
1116 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
1117 HOST_WIDE_INT, int);
1118 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
1121 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
1124 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
1125 const_tree, HOST_WIDE_INT,
1127 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, bool, bool);
1128 static rtx rs6000_mixed_function_arg (enum machine_mode, const_tree, int);
1129 static void rs6000_function_arg_advance (cumulative_args_t, enum machine_mode,
1131 static rtx rs6000_function_arg (cumulative_args_t, enum machine_mode,
1133 static unsigned int rs6000_function_arg_boundary (enum machine_mode,
1135 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
1136 static void setup_incoming_varargs (cumulative_args_t,
1137 enum machine_mode, tree,
1139 static bool rs6000_pass_by_reference (cumulative_args_t, enum machine_mode,
1141 static int rs6000_arg_partial_bytes (cumulative_args_t, enum machine_mode,
1143 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
1145 static void macho_branch_islands (void);
1146 static int no_previous_def (tree function_name);
1147 static tree get_prev_label (tree function_name);
1148 static void rs6000_darwin_file_start (void);
1151 static tree rs6000_build_builtin_va_list (void);
1152 static void rs6000_va_start (tree, rtx);
1153 static tree rs6000_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
1154 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
1155 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
1156 static bool rs6000_vector_mode_supported_p (enum machine_mode);
1157 static rtx rs6000_emit_vector_compare_inner (enum rtx_code, rtx, rtx);
1158 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
1160 static tree rs6000_stack_protect_fail (void);
1162 static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
1165 static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
1168 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
1170 = rs6000_legitimize_reload_address;
1172 static bool rs6000_mode_dependent_address_p (const_rtx);
1173 static bool rs6000_mode_dependent_address (const_rtx);
1174 static bool rs6000_debug_mode_dependent_address (const_rtx);
1175 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1176 = rs6000_mode_dependent_address;
1178 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1179 enum machine_mode, rtx);
1180 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1183 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1184 enum machine_mode, rtx)
1185 = rs6000_secondary_reload_class;
1187 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1188 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1190 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1191 = rs6000_preferred_reload_class;
1193 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
1196 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
1200 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1202 = rs6000_secondary_memory_needed;
1204 static bool rs6000_cannot_change_mode_class (enum machine_mode,
1207 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
1211 bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
1214 = rs6000_cannot_change_mode_class;
1216 static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t,
1218 struct secondary_reload_info *);
1220 const int INSN_NOT_AVAILABLE = -1;
1221 static enum machine_mode rs6000_eh_return_filter_mode (void);
1222 static bool rs6000_can_eliminate (const int, const int);
1223 static void rs6000_conditional_register_usage (void);
1224 static void rs6000_trampoline_init (rtx, tree, rtx);
1225 static bool rs6000_cannot_force_const_mem (enum machine_mode, rtx);
1226 static bool rs6000_legitimate_constant_p (enum machine_mode, rtx);
1227 static bool rs6000_save_toc_in_prologue_p (void);
1228 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
1230 /* Hash table stuff for keeping track of TOC entries. */
1232 struct GTY(()) toc_hash_struct
1234 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1235 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1237 enum machine_mode key_mode;
1241 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
1243 /* Hash table to keep track of the argument types for builtin functions. */
1245 struct GTY(()) builtin_hash_struct
1248 enum machine_mode mode[4]; /* return value + 3 arguments. */
1249 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1252 static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
1254 static bool rs6000_valid_attribute_p (tree, tree, tree, int);
1255 static void rs6000_function_specific_save (struct cl_target_option *);
1256 static void rs6000_function_specific_restore (struct cl_target_option *);
1257 static void rs6000_function_specific_print (FILE *, int,
1258 struct cl_target_option *);
1259 static bool rs6000_can_inline_p (tree, tree);
1260 static void rs6000_set_current_function (tree);
1263 /* Default register names. */
1264 char rs6000_reg_names[][8] =
1266 "0", "1", "2", "3", "4", "5", "6", "7",
1267 "8", "9", "10", "11", "12", "13", "14", "15",
1268 "16", "17", "18", "19", "20", "21", "22", "23",
1269 "24", "25", "26", "27", "28", "29", "30", "31",
1270 "0", "1", "2", "3", "4", "5", "6", "7",
1271 "8", "9", "10", "11", "12", "13", "14", "15",
1272 "16", "17", "18", "19", "20", "21", "22", "23",
1273 "24", "25", "26", "27", "28", "29", "30", "31",
1274 "mq", "lr", "ctr","ap",
1275 "0", "1", "2", "3", "4", "5", "6", "7",
1277 /* AltiVec registers. */
1278 "0", "1", "2", "3", "4", "5", "6", "7",
1279 "8", "9", "10", "11", "12", "13", "14", "15",
1280 "16", "17", "18", "19", "20", "21", "22", "23",
1281 "24", "25", "26", "27", "28", "29", "30", "31",
1283 /* SPE registers. */
1284 "spe_acc", "spefscr",
1285 /* Soft frame pointer. */
1289 #ifdef TARGET_REGNAMES
1290 static const char alt_reg_names[][8] =
1292 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1293 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1294 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1295 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1296 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1297 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1298 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1299 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1300 "mq", "lr", "ctr", "ap",
1301 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1303 /* AltiVec registers. */
1304 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1305 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1306 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1307 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1309 /* SPE registers. */
1310 "spe_acc", "spefscr",
1311 /* Soft frame pointer. */
1316 /* Table of valid machine attributes. */
1318 static const struct attribute_spec rs6000_attribute_table[] =
1320 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1321 affects_type_identity } */
1322 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1324 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1326 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1328 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1330 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1332 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1333 SUBTARGET_ATTRIBUTE_TABLE,
1335 { NULL, 0, 0, false, false, false, NULL, false }
1338 #ifndef MASK_STRICT_ALIGN
1339 #define MASK_STRICT_ALIGN 0
1341 #ifndef TARGET_PROFILE_KERNEL
1342 #define TARGET_PROFILE_KERNEL 0
1345 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1346 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1348 /* Initialize the GCC target structure. */
1349 #undef TARGET_ATTRIBUTE_TABLE
1350 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1351 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1352 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1353 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1354 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1356 #undef TARGET_ASM_ALIGNED_DI_OP
1357 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1359 /* Default unaligned ops are only provided for ELF. Find the ops needed
1360 for non-ELF systems. */
1361 #ifndef OBJECT_FORMAT_ELF
1363 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1365 #undef TARGET_ASM_UNALIGNED_HI_OP
1366 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1367 #undef TARGET_ASM_UNALIGNED_SI_OP
1368 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1369 #undef TARGET_ASM_UNALIGNED_DI_OP
1370 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1373 #undef TARGET_ASM_UNALIGNED_HI_OP
1374 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1375 #undef TARGET_ASM_UNALIGNED_SI_OP
1376 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1377 #undef TARGET_ASM_UNALIGNED_DI_OP
1378 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1379 #undef TARGET_ASM_ALIGNED_DI_OP
1380 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1384 /* This hook deals with fixups for relocatable code and DI-mode objects
1386 #undef TARGET_ASM_INTEGER
1387 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1389 #if defined (HAVE_GAS_HIDDEN) && !defined (TARGET_MACHO)
1390 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1391 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1394 #undef TARGET_HAVE_TLS
1395 #define TARGET_HAVE_TLS HAVE_AS_TLS
1397 #undef TARGET_CANNOT_FORCE_CONST_MEM
1398 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1400 #undef TARGET_DELEGITIMIZE_ADDRESS
1401 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1403 #undef TARGET_ASM_FUNCTION_PROLOGUE
1404 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1405 #undef TARGET_ASM_FUNCTION_EPILOGUE
1406 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1408 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1409 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1411 #undef TARGET_LEGITIMIZE_ADDRESS
1412 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1414 #undef TARGET_SCHED_VARIABLE_ISSUE
1415 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1417 #undef TARGET_SCHED_ISSUE_RATE
1418 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1419 #undef TARGET_SCHED_ADJUST_COST
1420 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1421 #undef TARGET_SCHED_ADJUST_PRIORITY
1422 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1423 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1424 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1425 #undef TARGET_SCHED_INIT
1426 #define TARGET_SCHED_INIT rs6000_sched_init
1427 #undef TARGET_SCHED_FINISH
1428 #define TARGET_SCHED_FINISH rs6000_sched_finish
1429 #undef TARGET_SCHED_REORDER
1430 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1431 #undef TARGET_SCHED_REORDER2
1432 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1434 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1435 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1437 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1438 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1440 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1441 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1442 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1443 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1444 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1445 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1446 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1447 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1449 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1450 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1451 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1452 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1453 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1454 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1455 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1456 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1457 rs6000_builtin_support_vector_misalignment
1458 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1459 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1460 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1461 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1462 rs6000_builtin_vectorization_cost
1463 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1464 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1465 rs6000_preferred_simd_mode
1467 #undef TARGET_INIT_BUILTINS
1468 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1469 #undef TARGET_BUILTIN_DECL
1470 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1472 #undef TARGET_EXPAND_BUILTIN
1473 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1475 #undef TARGET_MANGLE_TYPE
1476 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1478 #undef TARGET_INIT_LIBFUNCS
1479 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1482 #undef TARGET_BINDS_LOCAL_P
1483 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1486 #undef TARGET_MS_BITFIELD_LAYOUT_P
1487 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1489 #undef TARGET_ASM_OUTPUT_MI_THUNK
1490 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1492 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1493 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1495 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1496 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1498 #undef TARGET_INVALID_WITHIN_DOLOOP
1499 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1501 #undef TARGET_REGISTER_MOVE_COST
1502 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1503 #undef TARGET_MEMORY_MOVE_COST
1504 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1505 #undef TARGET_RTX_COSTS
1506 #define TARGET_RTX_COSTS rs6000_rtx_costs
1507 #undef TARGET_ADDRESS_COST
1508 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1510 #undef TARGET_DWARF_REGISTER_SPAN
1511 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1513 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1514 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1516 /* On rs6000, function arguments are promoted, as are function return
1518 #undef TARGET_PROMOTE_FUNCTION_MODE
1519 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1521 #undef TARGET_RETURN_IN_MEMORY
1522 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1524 #undef TARGET_SETUP_INCOMING_VARARGS
1525 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1527 /* Always strict argument naming on rs6000. */
1528 #undef TARGET_STRICT_ARGUMENT_NAMING
1529 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1530 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1531 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1532 #undef TARGET_SPLIT_COMPLEX_ARG
1533 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1534 #undef TARGET_MUST_PASS_IN_STACK
1535 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1536 #undef TARGET_PASS_BY_REFERENCE
1537 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1538 #undef TARGET_ARG_PARTIAL_BYTES
1539 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1540 #undef TARGET_FUNCTION_ARG_ADVANCE
1541 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1542 #undef TARGET_FUNCTION_ARG
1543 #define TARGET_FUNCTION_ARG rs6000_function_arg
1544 #undef TARGET_FUNCTION_ARG_BOUNDARY
1545 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1547 #undef TARGET_BUILD_BUILTIN_VA_LIST
1548 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1550 #undef TARGET_EXPAND_BUILTIN_VA_START
1551 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1553 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1554 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1556 #undef TARGET_EH_RETURN_FILTER_MODE
1557 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1559 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1560 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1562 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1563 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1565 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1566 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1568 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1569 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1571 #undef TARGET_OPTION_OVERRIDE
1572 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1574 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1575 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1576 rs6000_builtin_vectorized_function
1578 #ifndef TARGET_MACHO
1579 #undef TARGET_STACK_PROTECT_FAIL
1580 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1583 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1584 The PowerPC architecture requires only weak consistency among
1585 processors--that is, memory accesses between processors need not be
1586 sequentially consistent and memory accesses among processors can occur
1587 in any order. The ability to order memory accesses weakly provides
1588 opportunities for more efficient use of the system bus. Unless a
1589 dependency exists, the 604e allows read operations to precede store
1591 #undef TARGET_RELAXED_ORDERING
1592 #define TARGET_RELAXED_ORDERING true
1595 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1596 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1599 /* Use a 32-bit anchor range. This leads to sequences like:
1601 addis tmp,anchor,high
1604 where tmp itself acts as an anchor, and can be shared between
1605 accesses to the same 64k page. */
1606 #undef TARGET_MIN_ANCHOR_OFFSET
1607 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1608 #undef TARGET_MAX_ANCHOR_OFFSET
1609 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1610 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1611 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1613 #undef TARGET_BUILTIN_RECIPROCAL
1614 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1616 #undef TARGET_EXPAND_TO_RTL_HOOK
1617 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1619 #undef TARGET_INSTANTIATE_DECLS
1620 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1622 #undef TARGET_SECONDARY_RELOAD
1623 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1625 #undef TARGET_LEGITIMATE_ADDRESS_P
1626 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1628 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1629 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1631 #undef TARGET_CAN_ELIMINATE
1632 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1634 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1635 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1637 #undef TARGET_TRAMPOLINE_INIT
1638 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1640 #undef TARGET_FUNCTION_VALUE
1641 #define TARGET_FUNCTION_VALUE rs6000_function_value
1643 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1644 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1646 #undef TARGET_OPTION_SAVE
1647 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1649 #undef TARGET_OPTION_RESTORE
1650 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1652 #undef TARGET_OPTION_PRINT
1653 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1655 #undef TARGET_CAN_INLINE_P
1656 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1658 #undef TARGET_SET_CURRENT_FUNCTION
1659 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1661 #undef TARGET_LEGITIMATE_CONSTANT_P
1662 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1666 /* Simplifications for entries below. */
1669 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1670 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1673 /* Some OSs don't support saving the high part of 64-bit registers on context
1674 switch. Other OSs don't support saving Altivec registers. On those OSs, we
1675 don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
1676 either, the user must explicitly specify them and we won't interfere with
1677 the user's specification. */
1680 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1681 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1682 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1683 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1684 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
1685 | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
1686 | MASK_RECIP_PRECISION)
1689 /* Masks for instructions set at various powerpc ISAs. */
1691 ISA_2_1_MASKS = MASK_MFCRF,
1692 ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
1693 ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
1695 /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
1696 ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
1697 fre, fsqrt, etc. were no longer documented as optional. Group masks by
1698 server and embedded. */
1699 ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION
1700 | MASK_PPC_GFXOPT | MASK_PPC_GPOPT),
1701 ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP),
1703 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
1704 altivec is a win so enable it. */
1705 ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD),
1706 ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC
1712 const char *const name; /* Canonical processor name. */
1713 const enum processor_type processor; /* Processor type enum value. */
1714 const int target_enable; /* Target flags to enable. */
1717 static struct rs6000_ptt const processor_target_table[] =
1719 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1720 #include "rs6000-cpus.def"
1724 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1728 rs6000_cpu_name_lookup (const char *name)
1734 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1735 if (! strcmp (name, processor_target_table[i].name))
1743 /* Return number of consecutive hard regs needed starting at reg REGNO
1744 to hold something of mode MODE.
1745 This is ordinarily the length in words of a value of mode MODE
1746 but can be less for certain modes in special long registers.
1748 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1749 scalar instructions. The upper 32 bits are only available to the
1752 POWER and PowerPC GPRs hold 32 bits worth;
1753 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1756 rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
1758 unsigned HOST_WIDE_INT reg_size;
1760 if (FP_REGNO_P (regno))
1761 reg_size = (VECTOR_MEM_VSX_P (mode)
1762 ? UNITS_PER_VSX_WORD
1763 : UNITS_PER_FP_WORD);
1765 else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1766 reg_size = UNITS_PER_SPE_WORD;
1768 else if (ALTIVEC_REGNO_P (regno))
1769 reg_size = UNITS_PER_ALTIVEC_WORD;
1771 /* The value returned for SCmode in the E500 double case is 2 for
1772 ABI compatibility; storing an SCmode value in a single register
1773 would require function_arg and rs6000_spe_function_arg to handle
1774 SCmode so as to pass the value correctly in a pair of
1776 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1777 && !DECIMAL_FLOAT_MODE_P (mode))
1778 reg_size = UNITS_PER_FP_WORD;
1781 reg_size = UNITS_PER_WORD;
1783 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1786 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1789 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1791 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1793 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1794 implementations. Don't allow an item to be split between a FP register
1795 and an Altivec register. */
1796 if (VECTOR_MEM_VSX_P (mode))
1798 if (FP_REGNO_P (regno))
1799 return FP_REGNO_P (last_regno);
1801 if (ALTIVEC_REGNO_P (regno))
1802 return ALTIVEC_REGNO_P (last_regno);
1805 /* The GPRs can hold any mode, but values bigger than one register
1806 cannot go past R31. */
1807 if (INT_REGNO_P (regno))
1808 return INT_REGNO_P (last_regno);
1810 /* The float registers (except for VSX vector modes) can only hold floating
1811 modes and DImode. This excludes the 32-bit decimal float mode for
1813 if (FP_REGNO_P (regno))
1815 if (SCALAR_FLOAT_MODE_P (mode)
1816 && (mode != TDmode || (regno % 2) == 0)
1817 && FP_REGNO_P (last_regno))
1820 if (GET_MODE_CLASS (mode) == MODE_INT
1821 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1824 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1825 && PAIRED_VECTOR_MODE (mode))
1831 /* The CR register can only hold CC modes. */
1832 if (CR_REGNO_P (regno))
1833 return GET_MODE_CLASS (mode) == MODE_CC;
1835 if (CA_REGNO_P (regno))
1836 return mode == BImode;
1838 /* AltiVec only in AldyVec registers. */
1839 if (ALTIVEC_REGNO_P (regno))
1840 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
1842 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1843 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1846 /* We cannot put TImode anywhere except general register and it must be able
1847 to fit within the register set. In the future, allow TImode in the
1848 Altivec or VSX registers. */
1850 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1853 /* Print interesting facts about registers. */
1855 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1859 for (r = first_regno; r <= last_regno; ++r)
1861 const char *comma = "";
1864 if (first_regno == last_regno)
1865 fprintf (stderr, "%s:\t", reg_name);
1867 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1870 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1871 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1875 fprintf (stderr, ",\n\t");
1880 if (rs6000_hard_regno_nregs[m][r] > 1)
1881 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1882 rs6000_hard_regno_nregs[m][r]);
1884 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1889 if (call_used_regs[r])
1893 fprintf (stderr, ",\n\t");
1898 len += fprintf (stderr, "%s%s", comma, "call-used");
1906 fprintf (stderr, ",\n\t");
1911 len += fprintf (stderr, "%s%s", comma, "fixed");
1917 fprintf (stderr, ",\n\t");
1921 fprintf (stderr, "%sregno = %d\n", comma, r);
1925 #define DEBUG_FMT_D "%-32s= %d\n"
1926 #define DEBUG_FMT_X "%-32s= 0x%x\n"
1927 #define DEBUG_FMT_S "%-32s= %s\n"
1929 /* Print various interesting information with -mdebug=reg. */
1931 rs6000_debug_reg_global (void)
1933 static const char *const tf[2] = { "false", "true" };
1934 const char *nl = (const char *)0;
1936 char costly_num[20];
1938 const char *costly_str;
1939 const char *nop_str;
1940 const char *trace_str;
1941 const char *abi_str;
1942 const char *cmodel_str;
1944 /* Map enum rs6000_vector to string. */
1945 static const char *rs6000_debug_vector_unit[] = {
1954 fprintf (stderr, "Register information: (last virtual reg = %d)\n",
1955 LAST_VIRTUAL_REGISTER);
1956 rs6000_debug_reg_print (0, 31, "gr");
1957 rs6000_debug_reg_print (32, 63, "fp");
1958 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
1961 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
1962 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
1963 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
1964 rs6000_debug_reg_print (MQ_REGNO, MQ_REGNO, "mq");
1965 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
1966 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
1967 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
1968 rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
1969 rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
1973 "d reg_class = %s\n"
1974 "f reg_class = %s\n"
1975 "v reg_class = %s\n"
1976 "wa reg_class = %s\n"
1977 "wd reg_class = %s\n"
1978 "wf reg_class = %s\n"
1979 "ws reg_class = %s\n\n",
1980 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
1981 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
1982 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
1983 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
1984 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
1985 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
1986 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
1988 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1989 if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
1992 fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1994 rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
1995 rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
2001 if (rs6000_recip_control)
2003 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2005 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2006 if (rs6000_recip_bits[m])
2009 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2011 (RS6000_RECIP_AUTO_RE_P (m)
2013 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2014 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2016 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2019 fputs ("\n", stderr);
2022 if (rs6000_cpu_index >= 0)
2023 fprintf (stderr, DEBUG_FMT_S, "cpu",
2024 processor_target_table[rs6000_cpu_index].name);
2026 if (rs6000_tune_index >= 0)
2027 fprintf (stderr, DEBUG_FMT_S, "tune",
2028 processor_target_table[rs6000_tune_index].name);
2030 switch (rs6000_sched_costly_dep)
2032 case max_dep_latency:
2033 costly_str = "max_dep_latency";
2037 costly_str = "no_dep_costly";
2040 case all_deps_costly:
2041 costly_str = "all_deps_costly";
2044 case true_store_to_load_dep_costly:
2045 costly_str = "true_store_to_load_dep_costly";
2048 case store_to_load_dep_costly:
2049 costly_str = "store_to_load_dep_costly";
2053 costly_str = costly_num;
2054 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2058 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2060 switch (rs6000_sched_insert_nops)
2062 case sched_finish_regroup_exact:
2063 nop_str = "sched_finish_regroup_exact";
2066 case sched_finish_pad_groups:
2067 nop_str = "sched_finish_pad_groups";
2070 case sched_finish_none:
2071 nop_str = "sched_finish_none";
2076 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2080 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2082 switch (rs6000_sdata)
2089 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2093 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2097 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2102 switch (rs6000_traceback)
2104 case traceback_default: trace_str = "default"; break;
2105 case traceback_none: trace_str = "none"; break;
2106 case traceback_part: trace_str = "part"; break;
2107 case traceback_full: trace_str = "full"; break;
2108 default: trace_str = "unknown"; break;
2111 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2113 switch (rs6000_current_cmodel)
2115 case CMODEL_SMALL: cmodel_str = "small"; break;
2116 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2117 case CMODEL_LARGE: cmodel_str = "large"; break;
2118 default: cmodel_str = "unknown"; break;
2121 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2123 switch (rs6000_current_abi)
2125 case ABI_NONE: abi_str = "none"; break;
2126 case ABI_AIX: abi_str = "aix"; break;
2127 case ABI_V4: abi_str = "V4"; break;
2128 case ABI_DARWIN: abi_str = "darwin"; break;
2129 default: abi_str = "unknown"; break;
2132 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2134 if (rs6000_altivec_abi)
2135 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2138 fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
2140 if (rs6000_darwin64_abi)
2141 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2143 if (rs6000_float_gprs)
2144 fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
2146 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2147 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2148 tf[!!rs6000_align_branch_targets]);
2149 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2150 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2151 rs6000_long_double_type_size);
2152 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2153 (int)rs6000_sched_restricted_insns_priority);
2154 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2156 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2157 (int)RS6000_BUILTIN_COUNT);
2158 fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask);
2161 /* Initialize the various global tables that are based on register size. */
2163 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2169 /* Precalculate REGNO_REG_CLASS. */
2170 rs6000_regno_regclass[0] = GENERAL_REGS;
2171 for (r = 1; r < 32; ++r)
2172 rs6000_regno_regclass[r] = BASE_REGS;
2174 for (r = 32; r < 64; ++r)
2175 rs6000_regno_regclass[r] = FLOAT_REGS;
2177 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
2178 rs6000_regno_regclass[r] = NO_REGS;
2180 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2181 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2183 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2184 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2185 rs6000_regno_regclass[r] = CR_REGS;
2187 rs6000_regno_regclass[MQ_REGNO] = MQ_REGS;
2188 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2189 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2190 rs6000_regno_regclass[CA_REGNO] = CA_REGS;
2191 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2192 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2193 rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
2194 rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
2195 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2196 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2198 /* Precalculate vector information, this must be set up before the
2199 rs6000_hard_regno_nregs_internal below. */
2200 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2202 rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
2203 rs6000_vector_reload[m][0] = CODE_FOR_nothing;
2204 rs6000_vector_reload[m][1] = CODE_FOR_nothing;
2207 for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
2208 rs6000_constraints[c] = NO_REGS;
2210 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2211 believes it can use native alignment or still uses 128-bit alignment. */
2212 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2223 /* V2DF mode, VSX only. */
2226 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2227 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2228 rs6000_vector_align[V2DFmode] = align64;
2231 /* V4SF mode, either VSX or Altivec. */
2234 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2235 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2236 rs6000_vector_align[V4SFmode] = align32;
2238 else if (TARGET_ALTIVEC)
2240 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2241 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2242 rs6000_vector_align[V4SFmode] = align32;
2245 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2249 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2250 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2251 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2252 rs6000_vector_align[V4SImode] = align32;
2253 rs6000_vector_align[V8HImode] = align32;
2254 rs6000_vector_align[V16QImode] = align32;
2258 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2259 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2260 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2264 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2265 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2266 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2270 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2271 Altivec doesn't have 64-bit support. */
2274 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2275 rs6000_vector_unit[V2DImode] = VECTOR_NONE;
2276 rs6000_vector_align[V2DImode] = align64;
2279 /* DFmode, see if we want to use the VSX unit. */
2280 if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2282 rs6000_vector_unit[DFmode] = VECTOR_VSX;
2283 rs6000_vector_mem[DFmode]
2284 = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
2285 rs6000_vector_align[DFmode] = align64;
2288 /* TODO add SPE and paired floating point vector support. */
2290 /* Register class constaints for the constraints that depend on compile
2292 if (TARGET_HARD_FLOAT && TARGET_FPRS)
2293 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
2295 if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2296 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
2300 /* At present, we just use VSX_REGS, but we have different constraints
2301 based on the use, in case we want to fine tune the default register
2302 class used. wa = any VSX register, wf = register class to use for
2303 V4SF, wd = register class to use for V2DF, and ws = register classs to
2304 use for DF scalars. */
2305 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2306 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
2307 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
2308 rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
2314 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2316 /* Set up the reload helper functions. */
2317 if (TARGET_VSX || TARGET_ALTIVEC)
2321 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
2322 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
2323 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
2324 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
2325 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
2326 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
2327 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
2328 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
2329 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
2330 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
2331 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
2332 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
2336 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
2337 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
2338 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
2339 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
2340 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
2341 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
2342 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
2343 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
2344 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
2345 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
2346 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
2347 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
2351 /* Precalculate HARD_REGNO_NREGS. */
2352 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2353 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2354 rs6000_hard_regno_nregs[m][r]
2355 = rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
2357 /* Precalculate HARD_REGNO_MODE_OK. */
2358 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2359 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2360 if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
2361 rs6000_hard_regno_mode_ok_p[m][r] = true;
2363 /* Precalculate CLASS_MAX_NREGS sizes. */
2364 for (c = 0; c < LIM_REG_CLASSES; ++c)
2368 if (TARGET_VSX && VSX_REG_CLASS_P (c))
2369 reg_size = UNITS_PER_VSX_WORD;
2371 else if (c == ALTIVEC_REGS)
2372 reg_size = UNITS_PER_ALTIVEC_WORD;
2374 else if (c == FLOAT_REGS)
2375 reg_size = UNITS_PER_FP_WORD;
2378 reg_size = UNITS_PER_WORD;
2380 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2381 rs6000_class_max_nregs[m][c]
2382 = (GET_MODE_SIZE (m) + reg_size - 1) / reg_size;
2385 if (TARGET_E500_DOUBLE)
2386 rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2388 /* Calculate which modes to automatically generate code to use a the
2389 reciprocal divide and square root instructions. In the future, possibly
2390 automatically generate the instructions even if the user did not specify
2391 -mrecip. The older machines double precision reciprocal sqrt estimate is
2392 not accurate enough. */
2393 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2395 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2397 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2398 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2399 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2400 if (VECTOR_UNIT_VSX_P (V2DFmode))
2401 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2403 if (TARGET_FRSQRTES)
2404 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2406 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2407 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2408 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2409 if (VECTOR_UNIT_VSX_P (V2DFmode))
2410 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2412 if (rs6000_recip_control)
2414 if (!flag_finite_math_only)
2415 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2416 if (flag_trapping_math)
2417 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2418 if (!flag_reciprocal_math)
2419 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2420 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2422 if (RS6000_RECIP_HAVE_RE_P (SFmode)
2423 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2424 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2426 if (RS6000_RECIP_HAVE_RE_P (DFmode)
2427 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2428 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2430 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
2431 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
2432 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2434 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
2435 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
2436 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2438 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
2439 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
2440 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2442 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
2443 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
2444 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2446 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
2447 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
2448 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2450 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
2451 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
2452 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2456 if (global_init_p || TARGET_DEBUG_TARGET)
2458 if (TARGET_DEBUG_REG)
2459 rs6000_debug_reg_global ();
2461 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
2463 "SImode variable mult cost = %d\n"
2464 "SImode constant mult cost = %d\n"
2465 "SImode short constant mult cost = %d\n"
2466 "DImode multipliciation cost = %d\n"
2467 "SImode division cost = %d\n"
2468 "DImode division cost = %d\n"
2469 "Simple fp operation cost = %d\n"
2470 "DFmode multiplication cost = %d\n"
2471 "SFmode division cost = %d\n"
2472 "DFmode division cost = %d\n"
2473 "cache line size = %d\n"
2474 "l1 cache size = %d\n"
2475 "l2 cache size = %d\n"
2476 "simultaneous prefetches = %d\n"
2479 rs6000_cost->mulsi_const,
2480 rs6000_cost->mulsi_const9,
2488 rs6000_cost->cache_line_size,
2489 rs6000_cost->l1_cache_size,
2490 rs6000_cost->l2_cache_size,
2491 rs6000_cost->simultaneous_prefetches);
2496 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2499 darwin_rs6000_override_options (void)
2501 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2503 rs6000_altivec_abi = 1;
2504 TARGET_ALTIVEC_VRSAVE = 1;
2506 if (DEFAULT_ABI == ABI_DARWIN
2508 darwin_one_byte_bool = 1;
2510 if (TARGET_64BIT && ! TARGET_POWERPC64)
2512 target_flags |= MASK_POWERPC64;
2513 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2517 rs6000_default_long_calls = 1;
2518 target_flags |= MASK_SOFT_FLOAT;
2521 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2523 if (!flag_mkernel && !flag_apple_kext
2525 && ! (target_flags_explicit & MASK_ALTIVEC))
2526 target_flags |= MASK_ALTIVEC;
2528 /* Unless the user (not the configurer) has explicitly overridden
2529 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2530 G4 unless targetting the kernel. */
2533 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
2534 && ! (target_flags_explicit & MASK_ALTIVEC)
2535 && ! global_options_set.x_rs6000_cpu_index)
2537 target_flags |= MASK_ALTIVEC;
2542 /* If not otherwise specified by a target, make 'long double' equivalent to
2545 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2546 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2549 /* Return the builtin mask of the various options used that could affect which
2550 builtins were used. In the past we used target_flags, but we've run out of
2551 bits, and some options like SPE and PAIRED are no longer in
2555 rs6000_builtin_mask_calculate (void)
2557 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
2558 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
2559 | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
2560 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
2561 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
2562 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
2563 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
2564 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
2565 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
2566 | ((TARGET_POWERPC) ? RS6000_BTM_POWERPC : 0)
2567 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
2570 /* Override command line options. Mostly we process the processor type and
2571 sometimes adjust other TARGET_ options. */
2574 rs6000_option_override_internal (bool global_init_p)
2577 const char *default_cpu = OPTION_TARGET_CPU_DEFAULT;
2581 struct cl_target_option *main_target_opt
2582 = ((global_init_p || target_option_default_node == NULL)
2583 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
2585 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2586 library functions, so warn about it. The flag may be useful for
2587 performance studies from time to time though, so don't disable it
2589 if (global_options_set.x_rs6000_alignment_flags
2590 && rs6000_alignment_flags == MASK_ALIGN_POWER
2591 && DEFAULT_ABI == ABI_DARWIN
2593 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2594 " it is incompatible with the installed C and C++ libraries");
2596 if (global_options_set.x_rs6000_spe_abi
2599 error ("not configured for SPE ABI");
2601 /* Numerous experiment shows that IRA based loop pressure
2602 calculation works better for RTL loop invariant motion on targets
2603 with enough (>= 32) registers. It is an expensive optimization.
2604 So it is on only for peak performance. */
2605 if (optimize >= 3 && global_init_p)
2606 flag_ira_loop_pressure = 1;
2608 /* Set the pointer size. */
2611 rs6000_pmode = (int)DImode;
2612 rs6000_pointer_size = 64;
2616 rs6000_pmode = (int)SImode;
2617 rs6000_pointer_size = 32;
2620 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
2621 #ifdef OS_MISSING_POWERPC64
2622 if (OS_MISSING_POWERPC64)
2623 set_masks &= ~MASK_POWERPC64;
2625 #ifdef OS_MISSING_ALTIVEC
2626 if (OS_MISSING_ALTIVEC)
2627 set_masks &= ~MASK_ALTIVEC;
2630 /* Don't override by the processor default if given explicitly. */
2631 set_masks &= ~target_flags_explicit;
2633 /* Identify the processor type. */
2636 if (TARGET_POWERPC64)
2637 default_cpu = "powerpc64";
2638 else if (TARGET_POWERPC)
2639 default_cpu = "powerpc";
2642 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2643 the cpu in a target attribute or pragma, but did not specify a tuning
2644 option, use the cpu for the tuning option rather than the option specified
2645 with -mtune on the command line. */
2646 if (rs6000_cpu_index > 0)
2647 cpu_index = rs6000_cpu_index;
2648 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index > 0)
2649 rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
2651 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
2653 if (rs6000_tune_index > 0)
2654 tune_index = rs6000_tune_index;
2656 rs6000_tune_index = tune_index = cpu_index;
2660 target_flags &= ~set_masks;
2661 target_flags |= (processor_target_table[cpu_index].target_enable
2665 rs6000_cpu = ((tune_index >= 0)
2666 ? processor_target_table[tune_index].processor
2668 ? PROCESSOR_DEFAULT64
2669 : PROCESSOR_DEFAULT));
2671 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
2672 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
2675 error ("AltiVec not supported in this target");
2677 error ("SPE not supported in this target");
2680 /* Disable Cell microcode if we are optimizing for the Cell
2681 and not optimizing for size. */
2682 if (rs6000_gen_cell_microcode == -1)
2683 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
2686 /* If we are optimizing big endian systems for space and it's OK to
2687 use instructions that would be microcoded on the Cell, use the
2688 load/store multiple and string instructions. */
2689 if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
2690 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
2692 /* Don't allow -mmultiple or -mstring on little endian systems
2693 unless the cpu is a 750, because the hardware doesn't support the
2694 instructions used in little endian mode, and causes an alignment
2695 trap. The 750 does not cause an alignment trap (except when the
2696 target is unaligned). */
2698 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
2700 if (TARGET_MULTIPLE)
2702 target_flags &= ~MASK_MULTIPLE;
2703 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
2704 warning (0, "-mmultiple is not supported on little endian systems");
2709 target_flags &= ~MASK_STRING;
2710 if ((target_flags_explicit & MASK_STRING) != 0)
2711 warning (0, "-mstring is not supported on little endian systems");
2715 /* Add some warnings for VSX. */
2718 const char *msg = NULL;
2719 if (!TARGET_HARD_FLOAT || !TARGET_FPRS
2720 || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
2722 if (target_flags_explicit & MASK_VSX)
2723 msg = N_("-mvsx requires hardware floating point");
2725 target_flags &= ~ MASK_VSX;
2727 else if (TARGET_PAIRED_FLOAT)
2728 msg = N_("-mvsx and -mpaired are incompatible");
2729 /* The hardware will allow VSX and little endian, but until we make sure
2730 things like vector select, etc. work don't allow VSX on little endian
2731 systems at this point. */
2732 else if (!BYTES_BIG_ENDIAN)
2733 msg = N_("-mvsx used with little endian code");
2734 else if (TARGET_AVOID_XFORM > 0)
2735 msg = N_("-mvsx needs indexed addressing");
2736 else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC))
2738 if (target_flags_explicit & MASK_VSX)
2739 msg = N_("-mvsx and -mno-altivec are incompatible");
2741 msg = N_("-mno-altivec disables vsx");
2747 target_flags &= ~ MASK_VSX;
2748 target_flags_explicit |= MASK_VSX;
2752 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2753 unless the user explicitly used the -mno-<option> to disable the code. */
2755 target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit);
2756 else if (TARGET_POPCNTD)
2757 target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit);
2758 else if (TARGET_DFP)
2759 target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
2760 else if (TARGET_CMPB)
2761 target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
2762 else if (TARGET_FPRND)
2763 target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
2764 else if (TARGET_POPCNTB)
2765 target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
2766 else if (TARGET_ALTIVEC)
2767 target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
2769 /* E500mc does "better" if we inline more aggressively. Respect the
2770 user's opinion, though. */
2771 if (rs6000_block_move_inline_limit == 0
2772 && (rs6000_cpu == PROCESSOR_PPCE500MC
2773 || rs6000_cpu == PROCESSOR_PPCE500MC64))
2774 rs6000_block_move_inline_limit = 128;
2776 /* store_one_arg depends on expand_block_move to handle at least the
2777 size of reg_parm_stack_space. */
2778 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
2779 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
2783 /* If the appropriate debug option is enabled, replace the target hooks
2784 with debug versions that call the real version and then prints
2785 debugging information. */
2786 if (TARGET_DEBUG_COST)
2788 targetm.rtx_costs = rs6000_debug_rtx_costs;
2789 targetm.address_cost = rs6000_debug_address_cost;
2790 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
2793 if (TARGET_DEBUG_ADDR)
2795 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
2796 targetm.legitimize_address = rs6000_debug_legitimize_address;
2797 rs6000_secondary_reload_class_ptr
2798 = rs6000_debug_secondary_reload_class;
2799 rs6000_secondary_memory_needed_ptr
2800 = rs6000_debug_secondary_memory_needed;
2801 rs6000_cannot_change_mode_class_ptr
2802 = rs6000_debug_cannot_change_mode_class;
2803 rs6000_preferred_reload_class_ptr
2804 = rs6000_debug_preferred_reload_class;
2805 rs6000_legitimize_reload_address_ptr
2806 = rs6000_debug_legitimize_reload_address;
2807 rs6000_mode_dependent_address_ptr
2808 = rs6000_debug_mode_dependent_address;
2811 if (rs6000_veclibabi_name)
2813 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
2814 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
2817 error ("unknown vectorization library ABI type (%s) for "
2818 "-mveclibabi= switch", rs6000_veclibabi_name);
2824 if (!global_options_set.x_rs6000_long_double_type_size)
2826 if (main_target_opt != NULL
2827 && (main_target_opt->x_rs6000_long_double_type_size
2828 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
2829 error ("target attribute or pragma changes long double size");
2831 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2834 #ifndef POWERPC_LINUX
2835 if (!global_options_set.x_rs6000_ieeequad)
2836 rs6000_ieeequad = 1;
2839 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2840 target attribute or pragma which automatically enables both options,
2841 unless the altivec ABI was set. This is set by default for 64-bit, but
2843 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2844 target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit);
2846 /* Enable Altivec ABI for AIX -maltivec. */
2847 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
2849 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2850 error ("target attribute or pragma changes AltiVec ABI");
2852 rs6000_altivec_abi = 1;
2855 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2856 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2857 be explicitly overridden in either case. */
2860 if (!global_options_set.x_rs6000_altivec_abi
2861 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
2863 if (main_target_opt != NULL &&
2864 !main_target_opt->x_rs6000_altivec_abi)
2865 error ("target attribute or pragma changes AltiVec ABI");
2867 rs6000_altivec_abi = 1;
2870 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
2871 if (!global_options_set.x_TARGET_ALTIVEC_VRSAVE)
2872 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
2875 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2876 So far, the only darwin64 targets are also MACH-O. */
2878 && DEFAULT_ABI == ABI_DARWIN
2881 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
2882 error ("target attribute or pragma changes darwin64 ABI");
2885 rs6000_darwin64_abi = 1;
2886 /* Default to natural alignment, for better performance. */
2887 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2891 /* Place FP constants in the constant pool instead of TOC
2892 if section anchors enabled. */
2893 if (flag_section_anchors)
2894 TARGET_NO_FP_IN_TOC = 1;
2896 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2897 SUBTARGET_OVERRIDE_OPTIONS;
2899 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2900 SUBSUBTARGET_OVERRIDE_OPTIONS;
2902 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2903 SUB3TARGET_OVERRIDE_OPTIONS;
2906 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
2907 || rs6000_cpu == PROCESSOR_PPCE500MC64)
2909 /* The e500 and e500mc do not have string instructions, and we set
2910 MASK_STRING above when optimizing for size. */
2911 if ((target_flags & MASK_STRING) != 0)
2912 target_flags = target_flags & ~MASK_STRING;
2914 else if (global_options_set.x_rs6000_cpu_index)
2916 /* For the powerpc-eabispe configuration, we set all these by
2917 default, so let's unset them if we manually set another
2918 CPU that is not the E500. */
2919 if (main_target_opt != NULL
2920 && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
2921 || (main_target_opt->x_rs6000_spe != rs6000_spe)
2922 || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
2923 error ("target attribute or pragma changes SPE ABI");
2926 if (!global_options_set.x_rs6000_spe_abi)
2928 if (!global_options_set.x_rs6000_spe)
2930 if (!global_options_set.x_rs6000_float_gprs)
2931 rs6000_float_gprs = 0;
2933 if (!(target_flags_explicit & MASK_ISEL))
2934 target_flags &= ~MASK_ISEL;
2937 /* Detect invalid option combinations with E500. */
2940 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
2941 && rs6000_cpu != PROCESSOR_POWER5
2942 && rs6000_cpu != PROCESSOR_POWER6
2943 && rs6000_cpu != PROCESSOR_POWER7
2944 && rs6000_cpu != PROCESSOR_PPCA2
2945 && rs6000_cpu != PROCESSOR_CELL);
2946 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
2947 || rs6000_cpu == PROCESSOR_POWER5
2948 || rs6000_cpu == PROCESSOR_POWER7);
2949 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
2950 || rs6000_cpu == PROCESSOR_POWER5
2951 || rs6000_cpu == PROCESSOR_POWER6
2952 || rs6000_cpu == PROCESSOR_POWER7
2953 || rs6000_cpu == PROCESSOR_PPCE500MC
2954 || rs6000_cpu == PROCESSOR_PPCE500MC64);
2956 /* Allow debug switches to override the above settings. These are set to -1
2957 in rs6000.opt to indicate the user hasn't directly set the switch. */
2958 if (TARGET_ALWAYS_HINT >= 0)
2959 rs6000_always_hint = TARGET_ALWAYS_HINT;
2961 if (TARGET_SCHED_GROUPS >= 0)
2962 rs6000_sched_groups = TARGET_SCHED_GROUPS;
2964 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
2965 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
2967 rs6000_sched_restricted_insns_priority
2968 = (rs6000_sched_groups ? 1 : 0);
2970 /* Handle -msched-costly-dep option. */
2971 rs6000_sched_costly_dep
2972 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
2974 if (rs6000_sched_costly_dep_str)
2976 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
2977 rs6000_sched_costly_dep = no_dep_costly;
2978 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
2979 rs6000_sched_costly_dep = all_deps_costly;
2980 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
2981 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
2982 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
2983 rs6000_sched_costly_dep = store_to_load_dep_costly;
2985 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
2986 atoi (rs6000_sched_costly_dep_str));
2989 /* Handle -minsert-sched-nops option. */
2990 rs6000_sched_insert_nops
2991 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
2993 if (rs6000_sched_insert_nops_str)
2995 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
2996 rs6000_sched_insert_nops = sched_finish_none;
2997 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
2998 rs6000_sched_insert_nops = sched_finish_pad_groups;
2999 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
3000 rs6000_sched_insert_nops = sched_finish_regroup_exact;
3002 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
3003 atoi (rs6000_sched_insert_nops_str));
3008 #ifdef TARGET_REGNAMES
3009 /* If the user desires alternate register names, copy in the
3010 alternate names now. */
3011 if (TARGET_REGNAMES)
3012 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
3015 /* Set aix_struct_return last, after the ABI is determined.
3016 If -maix-struct-return or -msvr4-struct-return was explicitly
3017 used, don't override with the ABI default. */
3018 if (!global_options_set.x_aix_struct_return)
3019 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
3022 /* IBM XL compiler defaults to unsigned bitfields. */
3023 if (TARGET_XL_COMPAT)
3024 flag_signed_bitfields = 0;
3027 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
3028 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
3031 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
3033 /* We can only guarantee the availability of DI pseudo-ops when
3034 assembling for 64-bit targets. */
3037 targetm.asm_out.aligned_op.di = NULL;
3038 targetm.asm_out.unaligned_op.di = NULL;
3042 /* Set branch target alignment, if not optimizing for size. */
3045 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3046 aligned 8byte to avoid misprediction by the branch predictor. */
3047 if (rs6000_cpu == PROCESSOR_TITAN
3048 || rs6000_cpu == PROCESSOR_CELL)
3050 if (align_functions <= 0)
3051 align_functions = 8;
3052 if (align_jumps <= 0)
3054 if (align_loops <= 0)
3057 if (rs6000_align_branch_targets)
3059 if (align_functions <= 0)
3060 align_functions = 16;
3061 if (align_jumps <= 0)
3063 if (align_loops <= 0)
3065 can_override_loop_align = 1;
3069 if (align_jumps_max_skip <= 0)
3070 align_jumps_max_skip = 15;
3071 if (align_loops_max_skip <= 0)
3072 align_loops_max_skip = 15;
3075 /* Arrange to save and restore machine status around nested functions. */
3076 init_machine_status = rs6000_init_machine_status;
3078 /* We should always be splitting complex arguments, but we can't break
3079 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3080 if (DEFAULT_ABI != ABI_AIX)
3081 targetm.calls.split_complex_arg = NULL;
3084 /* Initialize rs6000_cost with the appropriate target costs. */
3086 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
3090 case PROCESSOR_RIOS1:
3091 rs6000_cost = &rios1_cost;
3094 case PROCESSOR_RIOS2:
3095 rs6000_cost = &rios2_cost;
3098 case PROCESSOR_RS64A:
3099 rs6000_cost = &rs64a_cost;
3102 case PROCESSOR_MPCCORE:
3103 rs6000_cost = &mpccore_cost;
3106 case PROCESSOR_PPC403:
3107 rs6000_cost = &ppc403_cost;
3110 case PROCESSOR_PPC405:
3111 rs6000_cost = &ppc405_cost;
3114 case PROCESSOR_PPC440:
3115 rs6000_cost = &ppc440_cost;
3118 case PROCESSOR_PPC476:
3119 rs6000_cost = &ppc476_cost;
3122 case PROCESSOR_PPC601:
3123 rs6000_cost = &ppc601_cost;
3126 case PROCESSOR_PPC603:
3127 rs6000_cost = &ppc603_cost;
3130 case PROCESSOR_PPC604:
3131 rs6000_cost = &ppc604_cost;
3134 case PROCESSOR_PPC604e:
3135 rs6000_cost = &ppc604e_cost;
3138 case PROCESSOR_PPC620:
3139 rs6000_cost = &ppc620_cost;
3142 case PROCESSOR_PPC630:
3143 rs6000_cost = &ppc630_cost;
3146 case PROCESSOR_CELL:
3147 rs6000_cost = &ppccell_cost;
3150 case PROCESSOR_PPC750:
3151 case PROCESSOR_PPC7400:
3152 rs6000_cost = &ppc750_cost;
3155 case PROCESSOR_PPC7450:
3156 rs6000_cost = &ppc7450_cost;
3159 case PROCESSOR_PPC8540:
3160 rs6000_cost = &ppc8540_cost;
3163 case PROCESSOR_PPCE300C2:
3164 case PROCESSOR_PPCE300C3:
3165 rs6000_cost = &ppce300c2c3_cost;
3168 case PROCESSOR_PPCE500MC:
3169 rs6000_cost = &ppce500mc_cost;
3172 case PROCESSOR_PPCE500MC64:
3173 rs6000_cost = &ppce500mc64_cost;
3176 case PROCESSOR_TITAN:
3177 rs6000_cost = &titan_cost;
3180 case PROCESSOR_POWER4:
3181 case PROCESSOR_POWER5:
3182 rs6000_cost = &power4_cost;
3185 case PROCESSOR_POWER6:
3186 rs6000_cost = &power6_cost;
3189 case PROCESSOR_POWER7:
3190 rs6000_cost = &power7_cost;
3193 case PROCESSOR_PPCA2:
3194 rs6000_cost = &ppca2_cost;
3203 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3204 rs6000_cost->simultaneous_prefetches,
3205 global_options.x_param_values,
3206 global_options_set.x_param_values);
3207 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
3208 global_options.x_param_values,
3209 global_options_set.x_param_values);
3210 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
3211 rs6000_cost->cache_line_size,
3212 global_options.x_param_values,
3213 global_options_set.x_param_values);
3214 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
3215 global_options.x_param_values,
3216 global_options_set.x_param_values);
3218 /* If using typedef char *va_list, signal that
3219 __builtin_va_start (&ap, 0) can be optimized to
3220 ap = __builtin_next_arg (0). */
3221 if (DEFAULT_ABI != ABI_V4)
3222 targetm.expand_builtin_va_start = NULL;
3225 /* Set up single/double float flags.
3226 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3227 then set both flags. */
3228 if (TARGET_HARD_FLOAT && TARGET_FPRS
3229 && rs6000_single_float == 0 && rs6000_double_float == 0)
3230 rs6000_single_float = rs6000_double_float = 1;
3232 /* Reset single and double FP flags if target is E500. */
3235 rs6000_single_float = rs6000_double_float = 0;
3236 if (TARGET_E500_SINGLE)
3237 rs6000_single_float = 1;
3238 if (TARGET_E500_DOUBLE)
3239 rs6000_single_float = rs6000_double_float = 1;
3242 if (main_target_opt)
3244 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
3245 error ("target attribute or pragma changes single precision floating "
3247 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
3248 error ("target attribute or pragma changes double precision floating "
3252 /* If not explicitly specified via option, decide whether to generate indexed
3253 load/store instructions. */
3254 if (TARGET_AVOID_XFORM == -1)
3255 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3256 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3257 need indexed accesses and the type used is the scalar type of the element
3258 being loaded or stored. */
3259 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
3260 && !TARGET_ALTIVEC);
3262 /* Set the -mrecip options. */
3263 if (rs6000_recip_name)
3265 char *p = ASTRDUP (rs6000_recip_name);
3267 unsigned int mask, i;
3270 while ((q = strtok (p, ",")) != NULL)
3281 if (!strcmp (q, "default"))
3282 mask = ((TARGET_RECIP_PRECISION)
3283 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
3286 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3287 if (!strcmp (q, recip_options[i].string))
3289 mask = recip_options[i].mask;
3293 if (i == ARRAY_SIZE (recip_options))
3295 error ("unknown option for -mrecip=%s", q);
3303 rs6000_recip_control &= ~mask;
3305 rs6000_recip_control |= mask;
3309 /* Set the builtin mask of the various options used that could affect which
3310 builtins were used. In the past we used target_flags, but we've run out
3311 of bits, and some options like SPE and PAIRED are no longer in
3313 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
3314 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
3315 fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask,
3316 (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "",
3317 (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "",
3318 (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "",
3319 (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : "");
3321 /* Initialize all of the registers. */
3322 rs6000_init_hard_regno_mode_ok (global_init_p);
3324 /* Save the initial options in case the user does function specific options */
3326 target_option_default_node = target_option_current_node
3327 = build_target_option_node ();
3329 /* If not explicitly specified via option, decide whether to generate the
3330 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3331 if (TARGET_LINK_STACK == -1)
3332 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
3337 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3338 define the target cpu type. */
3341 rs6000_option_override (void)
3343 (void) rs6000_option_override_internal (true);
3347 /* Implement targetm.vectorize.builtin_mask_for_load. */
3349 rs6000_builtin_mask_for_load (void)
3351 if (TARGET_ALTIVEC || TARGET_VSX)
3352 return altivec_builtin_mask_for_load;
3357 /* Implement LOOP_ALIGN. */
3359 rs6000_loop_align (rtx label)
3364 /* Don't override loop alignment if -falign-loops was specified. */
3365 if (!can_override_loop_align)
3366 return align_loops_log;
3368 bb = BLOCK_FOR_INSN (label);
3369 ninsns = num_loop_insns(bb->loop_father);
3371 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3372 if (ninsns > 4 && ninsns <= 8
3373 && (rs6000_cpu == PROCESSOR_POWER4
3374 || rs6000_cpu == PROCESSOR_POWER5
3375 || rs6000_cpu == PROCESSOR_POWER6
3376 || rs6000_cpu == PROCESSOR_POWER7))
3379 return align_loops_log;
3382 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3384 rs6000_loop_align_max_skip (rtx label)
3386 return (1 << rs6000_loop_align (label)) - 1;
3389 /* Implement targetm.vectorize.builtin_mul_widen_even. */
3391 rs6000_builtin_mul_widen_even (tree type)
3393 if (!TARGET_ALTIVEC)
3396 switch (TYPE_MODE (type))
3399 return TYPE_UNSIGNED (type)
3400 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH_UNS]
3401 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
3404 return TYPE_UNSIGNED (type)
3405 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB_UNS]
3406 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
3412 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
3414 rs6000_builtin_mul_widen_odd (tree type)
3416 if (!TARGET_ALTIVEC)
3419 switch (TYPE_MODE (type))
3422 return TYPE_UNSIGNED (type)
3423 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH_UNS]
3424 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
3427 return TYPE_UNSIGNED (type)
3428 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB_UNS]
3429 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
3436 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3437 after applying N number of iterations. This routine does not determine
3438 how may iterations are required to reach desired alignment. */
3441 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
3448 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
3451 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
3461 /* Assuming that all other types are naturally aligned. CHECKME! */
3466 /* Return true if the vector misalignment factor is supported by the
3469 rs6000_builtin_support_vector_misalignment (enum machine_mode mode,
3476 /* Return if movmisalign pattern is not supported for this mode. */
3477 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
3480 if (misalignment == -1)
3482 /* Misalignment factor is unknown at compile time but we know
3483 it's word aligned. */
3484 if (rs6000_vector_alignment_reachable (type, is_packed))
3486 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
3488 if (element_size == 64 || element_size == 32)
3495 /* VSX supports word-aligned vector. */
3496 if (misalignment % 4 == 0)
3502 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3504 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
3505 tree vectype, int misalign)
3509 switch (type_of_cost)
3519 case cond_branch_not_taken:
3523 case cond_branch_taken:
3526 case unaligned_load:
3527 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3529 elements = TYPE_VECTOR_SUBPARTS (vectype);
3531 /* Double word aligned. */
3539 /* Double word aligned. */
3543 /* Unknown misalignment. */
3556 /* Misaligned loads are not supported. */
3561 case unaligned_store:
3562 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3564 elements = TYPE_VECTOR_SUBPARTS (vectype);
3566 /* Double word aligned. */
3574 /* Double word aligned. */
3578 /* Unknown misalignment. */
3591 /* Misaligned stores are not supported. */
3601 /* Implement targetm.vectorize.preferred_simd_mode. */
3603 static enum machine_mode
3604 rs6000_preferred_simd_mode (enum machine_mode mode)
3613 if (TARGET_ALTIVEC || TARGET_VSX)
3637 if (TARGET_PAIRED_FLOAT
3643 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3644 library with vectorized intrinsics. */
3647 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
3650 const char *suffix = NULL;
3651 tree fntype, new_fndecl, bdecl = NULL_TREE;
3654 enum machine_mode el_mode, in_mode;
3657 /* Libmass is suitable for unsafe math only as it does not correctly support
3658 parts of IEEE with the required precision such as denormals. Only support
3659 it if we have VSX to use the simd d2 or f4 functions.
3660 XXX: Add variable length support. */
3661 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
3664 el_mode = TYPE_MODE (TREE_TYPE (type_out));
3665 n = TYPE_VECTOR_SUBPARTS (type_out);
3666 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3667 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3668 if (el_mode != in_mode
3672 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3674 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3677 case BUILT_IN_ATAN2:
3678 case BUILT_IN_HYPOT:
3684 case BUILT_IN_ACOSH:
3686 case BUILT_IN_ASINH:
3688 case BUILT_IN_ATANH:
3696 case BUILT_IN_EXPM1:
3697 case BUILT_IN_LGAMMA:
3698 case BUILT_IN_LOG10:
3699 case BUILT_IN_LOG1P:
3707 bdecl = builtin_decl_implicit (fn);
3708 suffix = "d2"; /* pow -> powd2 */
3709 if (el_mode != DFmode
3714 case BUILT_IN_ATAN2F:
3715 case BUILT_IN_HYPOTF:
3720 case BUILT_IN_ACOSF:
3721 case BUILT_IN_ACOSHF:
3722 case BUILT_IN_ASINF:
3723 case BUILT_IN_ASINHF:
3724 case BUILT_IN_ATANF:
3725 case BUILT_IN_ATANHF:
3726 case BUILT_IN_CBRTF:
3728 case BUILT_IN_COSHF:
3730 case BUILT_IN_ERFCF:
3731 case BUILT_IN_EXP2F:
3733 case BUILT_IN_EXPM1F:
3734 case BUILT_IN_LGAMMAF:
3735 case BUILT_IN_LOG10F:
3736 case BUILT_IN_LOG1PF:
3737 case BUILT_IN_LOG2F:
3740 case BUILT_IN_SINHF:
3741 case BUILT_IN_SQRTF:
3743 case BUILT_IN_TANHF:
3744 bdecl = builtin_decl_implicit (fn);
3745 suffix = "4"; /* powf -> powf4 */
3746 if (el_mode != SFmode
3758 gcc_assert (suffix != NULL);
3759 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
3760 strcpy (name, bname + sizeof ("__builtin_") - 1);
3761 strcat (name, suffix);
3764 fntype = build_function_type_list (type_out, type_in, NULL);
3765 else if (n_args == 2)
3766 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
3770 /* Build a function declaration for the vectorized function. */
3771 new_fndecl = build_decl (BUILTINS_LOCATION,
3772 FUNCTION_DECL, get_identifier (name), fntype);
3773 TREE_PUBLIC (new_fndecl) = 1;
3774 DECL_EXTERNAL (new_fndecl) = 1;
3775 DECL_IS_NOVOPS (new_fndecl) = 1;
3776 TREE_READONLY (new_fndecl) = 1;
3781 /* Returns a function decl for a vectorized version of the builtin function
3782 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3783 if it is not available. */
3786 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
3789 enum machine_mode in_mode, out_mode;
3792 if (TARGET_DEBUG_BUILTIN)
3793 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3794 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
3795 GET_MODE_NAME (TYPE_MODE (type_out)),
3796 GET_MODE_NAME (TYPE_MODE (type_in)));
3798 if (TREE_CODE (type_out) != VECTOR_TYPE
3799 || TREE_CODE (type_in) != VECTOR_TYPE
3800 || !TARGET_VECTORIZE_BUILTINS)
3803 out_mode = TYPE_MODE (TREE_TYPE (type_out));
3804 out_n = TYPE_VECTOR_SUBPARTS (type_out);
3805 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3806 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3808 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3810 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3813 case BUILT_IN_COPYSIGN:
3814 if (VECTOR_UNIT_VSX_P (V2DFmode)
3815 && out_mode == DFmode && out_n == 2
3816 && in_mode == DFmode && in_n == 2)
3817 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
3819 case BUILT_IN_COPYSIGNF:
3820 if (out_mode != SFmode || out_n != 4
3821 || in_mode != SFmode || in_n != 4)
3823 if (VECTOR_UNIT_VSX_P (V4SFmode))
3824 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
3825 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3826 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
3829 if (VECTOR_UNIT_VSX_P (V2DFmode)
3830 && out_mode == DFmode && out_n == 2
3831 && in_mode == DFmode && in_n == 2)
3832 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
3834 case BUILT_IN_SQRTF:
3835 if (VECTOR_UNIT_VSX_P (V4SFmode)
3836 && out_mode == SFmode && out_n == 4
3837 && in_mode == SFmode && in_n == 4)
3838 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
3841 if (VECTOR_UNIT_VSX_P (V2DFmode)
3842 && out_mode == DFmode && out_n == 2
3843 && in_mode == DFmode && in_n == 2)
3844 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
3846 case BUILT_IN_CEILF:
3847 if (out_mode != SFmode || out_n != 4
3848 || in_mode != SFmode || in_n != 4)
3850 if (VECTOR_UNIT_VSX_P (V4SFmode))
3851 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
3852 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3853 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
3855 case BUILT_IN_FLOOR:
3856 if (VECTOR_UNIT_VSX_P (V2DFmode)
3857 && out_mode == DFmode && out_n == 2
3858 && in_mode == DFmode && in_n == 2)
3859 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
3861 case BUILT_IN_FLOORF:
3862 if (out_mode != SFmode || out_n != 4
3863 || in_mode != SFmode || in_n != 4)
3865 if (VECTOR_UNIT_VSX_P (V4SFmode))
3866 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
3867 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3868 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
3871 if (VECTOR_UNIT_VSX_P (V2DFmode)
3872 && out_mode == DFmode && out_n == 2
3873 && in_mode == DFmode && in_n == 2)
3874 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
3877 if (VECTOR_UNIT_VSX_P (V4SFmode)
3878 && out_mode == SFmode && out_n == 4
3879 && in_mode == SFmode && in_n == 4)
3880 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
3881 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
3882 && out_mode == SFmode && out_n == 4
3883 && in_mode == SFmode && in_n == 4)
3884 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
3886 case BUILT_IN_TRUNC:
3887 if (VECTOR_UNIT_VSX_P (V2DFmode)
3888 && out_mode == DFmode && out_n == 2
3889 && in_mode == DFmode && in_n == 2)
3890 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
3892 case BUILT_IN_TRUNCF:
3893 if (out_mode != SFmode || out_n != 4
3894 || in_mode != SFmode || in_n != 4)
3896 if (VECTOR_UNIT_VSX_P (V4SFmode))
3897 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
3898 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3899 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
3901 case BUILT_IN_NEARBYINT:
3902 if (VECTOR_UNIT_VSX_P (V2DFmode)
3903 && flag_unsafe_math_optimizations
3904 && out_mode == DFmode && out_n == 2
3905 && in_mode == DFmode && in_n == 2)
3906 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
3908 case BUILT_IN_NEARBYINTF:
3909 if (VECTOR_UNIT_VSX_P (V4SFmode)
3910 && flag_unsafe_math_optimizations
3911 && out_mode == SFmode && out_n == 4
3912 && in_mode == SFmode && in_n == 4)
3913 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
3916 if (VECTOR_UNIT_VSX_P (V2DFmode)
3917 && !flag_trapping_math
3918 && out_mode == DFmode && out_n == 2
3919 && in_mode == DFmode && in_n == 2)
3920 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
3922 case BUILT_IN_RINTF:
3923 if (VECTOR_UNIT_VSX_P (V4SFmode)
3924 && !flag_trapping_math
3925 && out_mode == SFmode && out_n == 4
3926 && in_mode == SFmode && in_n == 4)
3927 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
3934 else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
3936 enum rs6000_builtins fn
3937 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
3940 case RS6000_BUILTIN_RSQRTF:
3941 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3942 && out_mode == SFmode && out_n == 4
3943 && in_mode == SFmode && in_n == 4)
3944 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
3946 case RS6000_BUILTIN_RSQRT:
3947 if (VECTOR_UNIT_VSX_P (V2DFmode)
3948 && out_mode == DFmode && out_n == 2
3949 && in_mode == DFmode && in_n == 2)
3950 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
3952 case RS6000_BUILTIN_RECIPF:
3953 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3954 && out_mode == SFmode && out_n == 4
3955 && in_mode == SFmode && in_n == 4)
3956 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
3958 case RS6000_BUILTIN_RECIP:
3959 if (VECTOR_UNIT_VSX_P (V2DFmode)
3960 && out_mode == DFmode && out_n == 2
3961 && in_mode == DFmode && in_n == 2)
3962 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
3969 /* Generate calls to libmass if appropriate. */
3970 if (rs6000_veclib_handler)
3971 return rs6000_veclib_handler (fndecl, type_out, type_in);
3976 /* Default CPU string for rs6000*_file_start functions. */
3977 static const char *rs6000_default_cpu;
3979 /* Do anything needed at the start of the asm file. */
3982 rs6000_file_start (void)
3985 const char *start = buffer;
3986 FILE *file = asm_out_file;
3988 rs6000_default_cpu = TARGET_CPU_DEFAULT;
3990 default_file_start ();
3992 #ifdef TARGET_BI_ARCH
3993 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
3994 rs6000_default_cpu = 0;
3997 if (flag_verbose_asm)
3999 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
4001 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
4003 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
4007 if (global_options_set.x_rs6000_cpu_index)
4009 fprintf (file, "%s -mcpu=%s", start,
4010 processor_target_table[rs6000_cpu_index].name);
4014 if (global_options_set.x_rs6000_tune_index)
4016 fprintf (file, "%s -mtune=%s", start,
4017 processor_target_table[rs6000_tune_index].name);
4021 if (PPC405_ERRATUM77)
4023 fprintf (file, "%s PPC405CR_ERRATUM77", start);
4027 #ifdef USING_ELFOS_H
4028 switch (rs6000_sdata)
4030 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
4031 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
4032 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
4033 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
4036 if (rs6000_sdata && g_switch_value)
4038 fprintf (file, "%s -G %d", start,
4048 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
4050 switch_to_section (toc_section);
4051 switch_to_section (text_section);
4056 /* Return nonzero if this function is known to have a null epilogue. */
4059 direct_return (void)
4061 if (reload_completed)
4063 rs6000_stack_t *info = rs6000_stack_info ();
4065 if (info->first_gp_reg_save == 32
4066 && info->first_fp_reg_save == 64
4067 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
4068 && ! info->lr_save_p
4069 && ! info->cr_save_p
4070 && info->vrsave_mask == 0
4078 /* Return the number of instructions it takes to form a constant in an
4079 integer register. */
4082 num_insns_constant_wide (HOST_WIDE_INT value)
4084 /* signed constant loadable with {cal|addi} */
4085 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
4088 /* constant loadable with {cau|addis} */
4089 else if ((value & 0xffff) == 0
4090 && (value >> 31 == -1 || value >> 31 == 0))
4093 #if HOST_BITS_PER_WIDE_INT == 64
4094 else if (TARGET_POWERPC64)
4096 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
4097 HOST_WIDE_INT high = value >> 31;
4099 if (high == 0 || high == -1)
4105 return num_insns_constant_wide (high) + 1;
4107 return num_insns_constant_wide (low) + 1;
4109 return (num_insns_constant_wide (high)
4110 + num_insns_constant_wide (low) + 1);
4119 num_insns_constant (rtx op, enum machine_mode mode)
4121 HOST_WIDE_INT low, high;
4123 switch (GET_CODE (op))
4126 #if HOST_BITS_PER_WIDE_INT == 64
4127 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
4128 && mask64_operand (op, mode))
4132 return num_insns_constant_wide (INTVAL (op));
4135 if (mode == SFmode || mode == SDmode)
4140 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4141 if (DECIMAL_FLOAT_MODE_P (mode))
4142 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
4144 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4145 return num_insns_constant_wide ((HOST_WIDE_INT) l);
4148 if (mode == VOIDmode || mode == DImode)
4150 high = CONST_DOUBLE_HIGH (op);
4151 low = CONST_DOUBLE_LOW (op);
4158 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4159 if (DECIMAL_FLOAT_MODE_P (mode))
4160 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
4162 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
4163 high = l[WORDS_BIG_ENDIAN == 0];
4164 low = l[WORDS_BIG_ENDIAN != 0];
4168 return (num_insns_constant_wide (low)
4169 + num_insns_constant_wide (high));
4172 if ((high == 0 && low >= 0)
4173 || (high == -1 && low < 0))
4174 return num_insns_constant_wide (low);
4176 else if (mask64_operand (op, mode))
4180 return num_insns_constant_wide (high) + 1;
4183 return (num_insns_constant_wide (high)
4184 + num_insns_constant_wide (low) + 1);
4192 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4193 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4194 corresponding element of the vector, but for V4SFmode and V2SFmode,
4195 the corresponding "float" is interpreted as an SImode integer. */
4198 const_vector_elt_as_int (rtx op, unsigned int elt)
4202 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4203 gcc_assert (GET_MODE (op) != V2DImode
4204 && GET_MODE (op) != V2DFmode);
4206 tmp = CONST_VECTOR_ELT (op, elt);
4207 if (GET_MODE (op) == V4SFmode
4208 || GET_MODE (op) == V2SFmode)
4209 tmp = gen_lowpart (SImode, tmp);
4210 return INTVAL (tmp);
4213 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4214 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4215 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4216 all items are set to the same value and contain COPIES replicas of the
4217 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4218 operand and the others are set to the value of the operand's msb. */
4221 vspltis_constant (rtx op, unsigned step, unsigned copies)
4223 enum machine_mode mode = GET_MODE (op);
4224 enum machine_mode inner = GET_MODE_INNER (mode);
4232 HOST_WIDE_INT splat_val;
4233 HOST_WIDE_INT msb_val;
4235 if (mode == V2DImode || mode == V2DFmode)
4238 nunits = GET_MODE_NUNITS (mode);
4239 bitsize = GET_MODE_BITSIZE (inner);
4240 mask = GET_MODE_MASK (inner);
4242 val = const_vector_elt_as_int (op, nunits - 1);
4244 msb_val = val > 0 ? 0 : -1;
4246 /* Construct the value to be splatted, if possible. If not, return 0. */
4247 for (i = 2; i <= copies; i *= 2)
4249 HOST_WIDE_INT small_val;
4251 small_val = splat_val >> bitsize;
4253 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
4255 splat_val = small_val;
4258 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4259 if (EASY_VECTOR_15 (splat_val))
4262 /* Also check if we can splat, and then add the result to itself. Do so if
4263 the value is positive, of if the splat instruction is using OP's mode;
4264 for splat_val < 0, the splat and the add should use the same mode. */
4265 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
4266 && (splat_val >= 0 || (step == 1 && copies == 1)))
4269 /* Also check if are loading up the most significant bit which can be done by
4270 loading up -1 and shifting the value left by -1. */
4271 else if (EASY_VECTOR_MSB (splat_val, inner))
4277 /* Check if VAL is present in every STEP-th element, and the
4278 other elements are filled with its most significant bit. */
4279 for (i = 0; i < nunits - 1; ++i)
4281 HOST_WIDE_INT desired_val;
4282 if (((i + 1) & (step - 1)) == 0)
4285 desired_val = msb_val;
4287 if (desired_val != const_vector_elt_as_int (op, i))
4295 /* Return true if OP is of the given MODE and can be synthesized
4296 with a vspltisb, vspltish or vspltisw. */
4299 easy_altivec_constant (rtx op, enum machine_mode mode)
4301 unsigned step, copies;
4303 if (mode == VOIDmode)
4304 mode = GET_MODE (op);
4305 else if (mode != GET_MODE (op))
4308 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4310 if (mode == V2DFmode)
4311 return zero_constant (op, mode);
4313 if (mode == V2DImode)
4315 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4317 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
4318 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
4321 if (zero_constant (op, mode))
4324 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
4325 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
4331 /* Start with a vspltisw. */
4332 step = GET_MODE_NUNITS (mode) / 4;
4335 if (vspltis_constant (op, step, copies))
4338 /* Then try with a vspltish. */
4344 if (vspltis_constant (op, step, copies))
4347 /* And finally a vspltisb. */
4353 if (vspltis_constant (op, step, copies))
4359 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4360 result is OP. Abort if it is not possible. */
4363 gen_easy_altivec_constant (rtx op)
4365 enum machine_mode mode = GET_MODE (op);
4366 int nunits = GET_MODE_NUNITS (mode);
4367 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
4368 unsigned step = nunits / 4;
4369 unsigned copies = 1;
4371 /* Start with a vspltisw. */
4372 if (vspltis_constant (op, step, copies))
4373 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
4375 /* Then try with a vspltish. */
4381 if (vspltis_constant (op, step, copies))
4382 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
4384 /* And finally a vspltisb. */
4390 if (vspltis_constant (op, step, copies))
4391 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
4397 output_vec_const_move (rtx *operands)
4400 enum machine_mode mode;
4405 mode = GET_MODE (dest);
4409 if (zero_constant (vec, mode))
4410 return "xxlxor %x0,%x0,%x0";
4412 if (mode == V2DImode
4413 && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
4414 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
4415 return "vspltisw %0,-1";
4421 if (zero_constant (vec, mode))
4422 return "vxor %0,%0,%0";
4424 splat_vec = gen_easy_altivec_constant (vec);
4425 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
4426 operands[1] = XEXP (splat_vec, 0);
4427 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
4430 switch (GET_MODE (splat_vec))
4433 return "vspltisw %0,%1";
4436 return "vspltish %0,%1";
4439 return "vspltisb %0,%1";
4446 gcc_assert (TARGET_SPE);
4448 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4449 pattern of V1DI, V4HI, and V2SF.
4451 FIXME: We should probably return # and add post reload
4452 splitters for these, but this way is so easy ;-). */
4453 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
4454 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
4455 operands[1] = CONST_VECTOR_ELT (vec, 0);
4456 operands[2] = CONST_VECTOR_ELT (vec, 1);
4458 return "li %0,%1\n\tevmergelo %0,%0,%0";
4460 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4463 /* Initialize TARGET of vector PAIRED to VALS. */
4466 paired_expand_vector_init (rtx target, rtx vals)
4468 enum machine_mode mode = GET_MODE (target);
4469 int n_elts = GET_MODE_NUNITS (mode);
4471 rtx x, new_rtx, tmp, constant_op, op1, op2;
4474 for (i = 0; i < n_elts; ++i)
4476 x = XVECEXP (vals, 0, i);
4477 if (!(CONST_INT_P (x)
4478 || GET_CODE (x) == CONST_DOUBLE
4479 || GET_CODE (x) == CONST_FIXED))
4484 /* Load from constant pool. */
4485 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
4491 /* The vector is initialized only with non-constants. */
4492 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
4493 XVECEXP (vals, 0, 1));
4495 emit_move_insn (target, new_rtx);
4499 /* One field is non-constant and the other one is a constant. Load the
4500 constant from the constant pool and use ps_merge instruction to
4501 construct the whole vector. */
4502 op1 = XVECEXP (vals, 0, 0);
4503 op2 = XVECEXP (vals, 0, 1);
4505 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
4507 tmp = gen_reg_rtx (GET_MODE (constant_op));
4508 emit_move_insn (tmp, constant_op);
4510 if (CONSTANT_P (op1))
4511 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
4513 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
4515 emit_move_insn (target, new_rtx);
4519 paired_expand_vector_move (rtx operands[])
4521 rtx op0 = operands[0], op1 = operands[1];
4523 emit_move_insn (op0, op1);
4526 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4527 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4528 operands for the relation operation COND. This is a recursive
4532 paired_emit_vector_compare (enum rtx_code rcode,
4533 rtx dest, rtx op0, rtx op1,
4534 rtx cc_op0, rtx cc_op1)
4536 rtx tmp = gen_reg_rtx (V2SFmode);
4539 gcc_assert (TARGET_PAIRED_FLOAT);
4540 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
4546 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4550 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4551 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
4555 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
4558 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4561 tmp1 = gen_reg_rtx (V2SFmode);
4562 max = gen_reg_rtx (V2SFmode);
4563 min = gen_reg_rtx (V2SFmode);
4564 gen_reg_rtx (V2SFmode);
4566 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4567 emit_insn (gen_selv2sf4
4568 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4569 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
4570 emit_insn (gen_selv2sf4
4571 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4572 emit_insn (gen_subv2sf3 (tmp1, min, max));
4573 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
4576 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
4579 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4582 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
4585 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4588 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
4597 /* Emit vector conditional expression.
4598 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4599 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4602 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
4603 rtx cond, rtx cc_op0, rtx cc_op1)
4605 enum rtx_code rcode = GET_CODE (cond);
4607 if (!TARGET_PAIRED_FLOAT)
4610 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
4615 /* Initialize vector TARGET to VALS. */
4618 rs6000_expand_vector_init (rtx target, rtx vals)
4620 enum machine_mode mode = GET_MODE (target);
4621 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4622 int n_elts = GET_MODE_NUNITS (mode);
4623 int n_var = 0, one_var = -1;
4624 bool all_same = true, all_const_zero = true;
4628 for (i = 0; i < n_elts; ++i)
4630 x = XVECEXP (vals, 0, i);
4631 if (!(CONST_INT_P (x)
4632 || GET_CODE (x) == CONST_DOUBLE
4633 || GET_CODE (x) == CONST_FIXED))
4634 ++n_var, one_var = i;
4635 else if (x != CONST0_RTX (inner_mode))
4636 all_const_zero = false;
4638 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
4644 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
4645 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
4646 if ((int_vector_p || TARGET_VSX) && all_const_zero)
4648 /* Zero register. */
4649 emit_insn (gen_rtx_SET (VOIDmode, target,
4650 gen_rtx_XOR (mode, target, target)));
4653 else if (int_vector_p && easy_vector_constant (const_vec, mode))
4655 /* Splat immediate. */
4656 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
4661 /* Load from constant pool. */
4662 emit_move_insn (target, const_vec);
4667 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4668 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4672 rtx element = XVECEXP (vals, 0, 0);
4673 if (mode == V2DFmode)
4674 emit_insn (gen_vsx_splat_v2df (target, element));
4676 emit_insn (gen_vsx_splat_v2di (target, element));
4680 if (mode == V2DFmode)
4682 rtx op0 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 0));
4683 rtx op1 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 1));
4684 emit_insn (gen_vsx_concat_v2df (target, op0, op1));
4688 rtx op0 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 0));
4689 rtx op1 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 1));
4690 emit_insn (gen_vsx_concat_v2di (target, op0, op1));
4696 /* With single precision floating point on VSX, know that internally single
4697 precision is actually represented as a double, and either make 2 V2DF
4698 vectors, and convert these vectors to single precision, or do one
4699 conversion, and splat the result to the other elements. */
4700 if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
4704 rtx freg = gen_reg_rtx (V4SFmode);
4705 rtx sreg = copy_to_reg (XVECEXP (vals, 0, 0));
4707 emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
4708 emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
4712 rtx dbl_even = gen_reg_rtx (V2DFmode);
4713 rtx dbl_odd = gen_reg_rtx (V2DFmode);
4714 rtx flt_even = gen_reg_rtx (V4SFmode);
4715 rtx flt_odd = gen_reg_rtx (V4SFmode);
4717 emit_insn (gen_vsx_concat_v2sf (dbl_even,
4718 copy_to_reg (XVECEXP (vals, 0, 0)),
4719 copy_to_reg (XVECEXP (vals, 0, 1))));
4720 emit_insn (gen_vsx_concat_v2sf (dbl_odd,
4721 copy_to_reg (XVECEXP (vals, 0, 2)),
4722 copy_to_reg (XVECEXP (vals, 0, 3))));
4723 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
4724 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
4725 emit_insn (gen_vec_extract_evenv4sf (target, flt_even, flt_odd));
4730 /* Store value to stack temp. Load vector element. Splat. However, splat
4731 of 64-bit items is not supported on Altivec. */
4732 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
4734 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4735 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
4736 XVECEXP (vals, 0, 0));
4737 x = gen_rtx_UNSPEC (VOIDmode,
4738 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4739 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4741 gen_rtx_SET (VOIDmode,
4744 x = gen_rtx_VEC_SELECT (inner_mode, target,
4745 gen_rtx_PARALLEL (VOIDmode,
4746 gen_rtvec (1, const0_rtx)));
4747 emit_insn (gen_rtx_SET (VOIDmode, target,
4748 gen_rtx_VEC_DUPLICATE (mode, x)));
4752 /* One field is non-constant. Load constant then overwrite
4756 rtx copy = copy_rtx (vals);
4758 /* Load constant part of vector, substitute neighboring value for
4760 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
4761 rs6000_expand_vector_init (target, copy);
4763 /* Insert variable. */
4764 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
4768 /* Construct the vector in memory one field at a time
4769 and load the whole vector. */
4770 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4771 for (i = 0; i < n_elts; i++)
4772 emit_move_insn (adjust_address_nv (mem, inner_mode,
4773 i * GET_MODE_SIZE (inner_mode)),
4774 XVECEXP (vals, 0, i));
4775 emit_move_insn (target, mem);
4778 /* Set field ELT of TARGET to VAL. */
4781 rs6000_expand_vector_set (rtx target, rtx val, int elt)
4783 enum machine_mode mode = GET_MODE (target);
4784 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4785 rtx reg = gen_reg_rtx (mode);
4787 int width = GET_MODE_SIZE (inner_mode);
4790 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4792 rtx (*set_func) (rtx, rtx, rtx, rtx)
4793 = ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
4794 emit_insn (set_func (target, target, val, GEN_INT (elt)));
4798 /* Load single variable value. */
4799 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4800 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
4801 x = gen_rtx_UNSPEC (VOIDmode,
4802 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4803 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4805 gen_rtx_SET (VOIDmode,
4809 /* Linear sequence. */
4810 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
4811 for (i = 0; i < 16; ++i)
4812 XVECEXP (mask, 0, i) = GEN_INT (i);
4814 /* Set permute mask to insert element into target. */
4815 for (i = 0; i < width; ++i)
4816 XVECEXP (mask, 0, elt*width + i)
4817 = GEN_INT (i + 0x10);
4818 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
4819 x = gen_rtx_UNSPEC (mode,
4820 gen_rtvec (3, target, reg,
4821 force_reg (V16QImode, x)),
4823 emit_insn (gen_rtx_SET (VOIDmode, target, x));
4826 /* Extract field ELT from VEC into TARGET. */
4829 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
4831 enum machine_mode mode = GET_MODE (vec);
4832 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4835 if (VECTOR_MEM_VSX_P (mode))
4842 emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
4845 emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
4848 emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
4853 /* Allocate mode-sized buffer. */
4854 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4856 emit_move_insn (mem, vec);
4858 /* Add offset to field within buffer matching vector element. */
4859 mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
4861 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
4864 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4865 implement ANDing by the mask IN. */
4867 build_mask64_2_operands (rtx in, rtx *out)
4869 #if HOST_BITS_PER_WIDE_INT >= 64
4870 unsigned HOST_WIDE_INT c, lsb, m1, m2;
4873 gcc_assert (GET_CODE (in) == CONST_INT);
4878 /* Assume c initially something like 0x00fff000000fffff. The idea
4879 is to rotate the word so that the middle ^^^^^^ group of zeros
4880 is at the MS end and can be cleared with an rldicl mask. We then
4881 rotate back and clear off the MS ^^ group of zeros with a
4883 c = ~c; /* c == 0xff000ffffff00000 */
4884 lsb = c & -c; /* lsb == 0x0000000000100000 */
4885 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
4886 c = ~c; /* c == 0x00fff000000fffff */
4887 c &= -lsb; /* c == 0x00fff00000000000 */
4888 lsb = c & -c; /* lsb == 0x0000100000000000 */
4889 c = ~c; /* c == 0xff000fffffffffff */
4890 c &= -lsb; /* c == 0xff00000000000000 */
4892 while ((lsb >>= 1) != 0)
4893 shift++; /* shift == 44 on exit from loop */
4894 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
4895 m1 = ~m1; /* m1 == 0x000000ffffffffff */
4896 m2 = ~c; /* m2 == 0x00ffffffffffffff */
4900 /* Assume c initially something like 0xff000f0000000000. The idea
4901 is to rotate the word so that the ^^^ middle group of zeros
4902 is at the LS end and can be cleared with an rldicr mask. We then
4903 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4905 lsb = c & -c; /* lsb == 0x0000010000000000 */
4906 m2 = -lsb; /* m2 == 0xffffff0000000000 */
4907 c = ~c; /* c == 0x00fff0ffffffffff */
4908 c &= -lsb; /* c == 0x00fff00000000000 */
4909 lsb = c & -c; /* lsb == 0x0000100000000000 */
4910 c = ~c; /* c == 0xff000fffffffffff */
4911 c &= -lsb; /* c == 0xff00000000000000 */
4913 while ((lsb >>= 1) != 0)
4914 shift++; /* shift == 44 on exit from loop */
4915 m1 = ~c; /* m1 == 0x00ffffffffffffff */
4916 m1 >>= shift; /* m1 == 0x0000000000000fff */
4917 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
4920 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4921 masks will be all 1's. We are guaranteed more than one transition. */
4922 out[0] = GEN_INT (64 - shift);
4923 out[1] = GEN_INT (m1);
4924 out[2] = GEN_INT (shift);
4925 out[3] = GEN_INT (m2);
4933 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4936 invalid_e500_subreg (rtx op, enum machine_mode mode)
4938 if (TARGET_E500_DOUBLE)
4940 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4941 subreg:TI and reg:TF. Decimal float modes are like integer
4942 modes (only low part of each register used) for this
4944 if (GET_CODE (op) == SUBREG
4945 && (mode == SImode || mode == DImode || mode == TImode
4946 || mode == DDmode || mode == TDmode)
4947 && REG_P (SUBREG_REG (op))
4948 && (GET_MODE (SUBREG_REG (op)) == DFmode
4949 || GET_MODE (SUBREG_REG (op)) == TFmode))
4952 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4954 if (GET_CODE (op) == SUBREG
4955 && (mode == DFmode || mode == TFmode)
4956 && REG_P (SUBREG_REG (op))
4957 && (GET_MODE (SUBREG_REG (op)) == DImode
4958 || GET_MODE (SUBREG_REG (op)) == TImode
4959 || GET_MODE (SUBREG_REG (op)) == DDmode
4960 || GET_MODE (SUBREG_REG (op)) == TDmode))
4965 && GET_CODE (op) == SUBREG
4967 && REG_P (SUBREG_REG (op))
4968 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
4974 /* AIX increases natural record alignment to doubleword if the first
4975 field is an FP double while the FP fields remain word aligned. */
4978 rs6000_special_round_type_align (tree type, unsigned int computed,
4979 unsigned int specified)
4981 unsigned int align = MAX (computed, specified);
4982 tree field = TYPE_FIELDS (type);
4984 /* Skip all non field decls */
4985 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4986 field = DECL_CHAIN (field);
4988 if (field != NULL && field != type)
4990 type = TREE_TYPE (field);
4991 while (TREE_CODE (type) == ARRAY_TYPE)
4992 type = TREE_TYPE (type);
4994 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
4995 align = MAX (align, 64);
5001 /* Darwin increases record alignment to the natural alignment of
5005 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
5006 unsigned int specified)
5008 unsigned int align = MAX (computed, specified);
5010 if (TYPE_PACKED (type))
5013 /* Find the first field, looking down into aggregates. */
5015 tree field = TYPE_FIELDS (type);
5016 /* Skip all non field decls */
5017 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
5018 field = DECL_CHAIN (field);
5021 /* A packed field does not contribute any extra alignment. */
5022 if (DECL_PACKED (field))
5024 type = TREE_TYPE (field);
5025 while (TREE_CODE (type) == ARRAY_TYPE)
5026 type = TREE_TYPE (type);
5027 } while (AGGREGATE_TYPE_P (type));
5029 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
5030 align = MAX (align, TYPE_ALIGN (type));
5035 /* Return 1 for an operand in small memory on V.4/eabi. */
5038 small_data_operand (rtx op ATTRIBUTE_UNUSED,
5039 enum machine_mode mode ATTRIBUTE_UNUSED)
5044 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
5047 if (DEFAULT_ABI != ABI_V4)
5050 /* Vector and float memory instructions have a limited offset on the
5051 SPE, so using a vector or float variable directly as an operand is
5054 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
5057 if (GET_CODE (op) == SYMBOL_REF)
5060 else if (GET_CODE (op) != CONST
5061 || GET_CODE (XEXP (op, 0)) != PLUS
5062 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
5063 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
5068 rtx sum = XEXP (op, 0);
5069 HOST_WIDE_INT summand;
5071 /* We have to be careful here, because it is the referenced address
5072 that must be 32k from _SDA_BASE_, not just the symbol. */
5073 summand = INTVAL (XEXP (sum, 1));
5074 if (summand < 0 || summand > g_switch_value)
5077 sym_ref = XEXP (sum, 0);
5080 return SYMBOL_REF_SMALL_P (sym_ref);
5086 /* Return true if either operand is a general purpose register. */
5089 gpr_or_gpr_p (rtx op0, rtx op1)
5091 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
5092 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
5096 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5099 reg_offset_addressing_ok_p (enum machine_mode mode)
5109 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5110 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
5118 /* Paired vector modes. Only reg+reg addressing is valid. */
5119 if (TARGET_PAIRED_FLOAT)
5131 virtual_stack_registers_memory_p (rtx op)
5135 if (GET_CODE (op) == REG)
5136 regnum = REGNO (op);
5138 else if (GET_CODE (op) == PLUS
5139 && GET_CODE (XEXP (op, 0)) == REG
5140 && GET_CODE (XEXP (op, 1)) == CONST_INT)
5141 regnum = REGNO (XEXP (op, 0));
5146 return (regnum >= FIRST_VIRTUAL_REGISTER
5147 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
5150 /* Return true if memory accesses to OP are known to never straddle
5154 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
5155 enum machine_mode mode)
5158 unsigned HOST_WIDE_INT dsize, dalign;
5160 if (GET_CODE (op) != SYMBOL_REF)
5163 decl = SYMBOL_REF_DECL (op);
5166 if (GET_MODE_SIZE (mode) == 0)
5169 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5170 replacing memory addresses with an anchor plus offset. We
5171 could find the decl by rummaging around in the block->objects
5172 VEC for the given offset but that seems like too much work. */
5174 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
5175 && SYMBOL_REF_ANCHOR_P (op)
5176 && SYMBOL_REF_BLOCK (op) != NULL)
5178 struct object_block *block = SYMBOL_REF_BLOCK (op);
5179 HOST_WIDE_INT lsb, mask;
5181 /* Given the alignment of the block.. */
5182 dalign = block->alignment;
5183 mask = dalign / BITS_PER_UNIT - 1;
5185 /* ..and the combined offset of the anchor and any offset
5186 to this block object.. */
5187 offset += SYMBOL_REF_BLOCK_OFFSET (op);
5188 lsb = offset & -offset;
5190 /* ..find how many bits of the alignment we know for the
5195 return dalign >= GET_MODE_SIZE (mode);
5200 if (TREE_CODE (decl) == FUNCTION_DECL)
5203 if (!DECL_SIZE_UNIT (decl))
5206 if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
5209 dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
5213 dalign = DECL_ALIGN_UNIT (decl);
5214 return dalign >= dsize;
5217 type = TREE_TYPE (decl);
5219 if (TREE_CODE (decl) == STRING_CST)
5220 dsize = TREE_STRING_LENGTH (decl);
5221 else if (TYPE_SIZE_UNIT (type)
5222 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5223 dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
5229 dalign = TYPE_ALIGN (type);
5230 if (CONSTANT_CLASS_P (decl))
5231 dalign = CONSTANT_ALIGNMENT (decl, dalign);
5233 dalign = DATA_ALIGNMENT (decl, dalign);
5234 dalign /= BITS_PER_UNIT;
5235 return dalign >= dsize;
5239 constant_pool_expr_p (rtx op)
5243 split_const (op, &base, &offset);
5244 return (GET_CODE (base) == SYMBOL_REF
5245 && CONSTANT_POOL_ADDRESS_P (base)
5246 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
5249 static rtx tocrel_base, tocrel_offset;
5252 toc_relative_expr_p (rtx op)
5254 if (GET_CODE (op) != CONST)
5257 split_const (op, &tocrel_base, &tocrel_offset);
5258 return (GET_CODE (tocrel_base) == UNSPEC
5259 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
5262 /* Return true if X is a constant pool address, and also for cmodel=medium
5263 if X is a toc-relative address known to be offsettable within MODE. */
5266 legitimate_constant_pool_address_p (const_rtx x, enum machine_mode mode,
5270 && (GET_CODE (x) == PLUS || GET_CODE (x) == LO_SUM)
5271 && GET_CODE (XEXP (x, 0)) == REG
5272 && (REGNO (XEXP (x, 0)) == TOC_REGISTER
5273 || ((TARGET_MINIMAL_TOC
5274 || TARGET_CMODEL != CMODEL_SMALL)
5275 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)))
5276 && toc_relative_expr_p (XEXP (x, 1))
5277 && (TARGET_CMODEL != CMODEL_MEDIUM
5278 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
5280 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
5281 INTVAL (tocrel_offset), mode)));
5285 legitimate_small_data_p (enum machine_mode mode, rtx x)
5287 return (DEFAULT_ABI == ABI_V4
5288 && !flag_pic && !TARGET_TOC
5289 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
5290 && small_data_operand (x, mode));
5293 /* SPE offset addressing is limited to 5-bits worth of double words. */
5294 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5297 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
5299 unsigned HOST_WIDE_INT offset, extra;
5301 if (GET_CODE (x) != PLUS)
5303 if (GET_CODE (XEXP (x, 0)) != REG)
5305 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5307 if (!reg_offset_addressing_ok_p (mode))
5308 return virtual_stack_registers_memory_p (x);
5309 if (legitimate_constant_pool_address_p (x, mode, strict))
5311 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5314 offset = INTVAL (XEXP (x, 1));
5322 /* SPE vector modes. */
5323 return SPE_CONST_OFFSET_OK (offset);
5326 if (TARGET_E500_DOUBLE)
5327 return SPE_CONST_OFFSET_OK (offset);
5329 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5331 if (VECTOR_MEM_VSX_P (DFmode))
5336 /* On e500v2, we may have:
5338 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5340 Which gets addressed with evldd instructions. */
5341 if (TARGET_E500_DOUBLE)
5342 return SPE_CONST_OFFSET_OK (offset);
5344 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
5346 else if (offset & 3)
5351 if (TARGET_E500_DOUBLE)
5352 return (SPE_CONST_OFFSET_OK (offset)
5353 && SPE_CONST_OFFSET_OK (offset + 8));
5357 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
5359 else if (offset & 3)
5370 return offset < 0x10000 - extra;
5374 legitimate_indexed_address_p (rtx x, int strict)
5378 if (GET_CODE (x) != PLUS)
5384 /* Recognize the rtl generated by reload which we know will later be
5385 replaced with proper base and index regs. */
5387 && reload_in_progress
5388 && (REG_P (op0) || GET_CODE (op0) == PLUS)
5392 return (REG_P (op0) && REG_P (op1)
5393 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
5394 && INT_REG_OK_FOR_INDEX_P (op1, strict))
5395 || (INT_REG_OK_FOR_BASE_P (op1, strict)
5396 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
5400 avoiding_indexed_address_p (enum machine_mode mode)
5402 /* Avoid indexed addressing for modes that have non-indexed
5403 load/store instruction forms. */
5404 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
5408 legitimate_indirect_address_p (rtx x, int strict)
5410 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
5414 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
5416 if (!TARGET_MACHO || !flag_pic
5417 || mode != SImode || GET_CODE (x) != MEM)
5421 if (GET_CODE (x) != LO_SUM)
5423 if (GET_CODE (XEXP (x, 0)) != REG)
5425 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
5429 return CONSTANT_P (x);
5433 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
5435 if (GET_CODE (x) != LO_SUM)
5437 if (GET_CODE (XEXP (x, 0)) != REG)
5439 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5441 /* Restrict addressing for DI because of our SUBREG hackery. */
5442 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5443 || mode == DDmode || mode == TDmode
5448 if (TARGET_ELF || TARGET_MACHO)
5450 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
5454 if (GET_MODE_NUNITS (mode) != 1)
5456 if (GET_MODE_BITSIZE (mode) > 64
5457 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
5458 && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5459 && (mode == DFmode || mode == DDmode))))
5462 return CONSTANT_P (x);
5469 /* Try machine-dependent ways of modifying an illegitimate address
5470 to be legitimate. If we find one, return the new, valid address.
5471 This is used from only one place: `memory_address' in explow.c.
5473 OLDX is the address as it was before break_out_memory_refs was
5474 called. In some cases it is useful to look at this to decide what
5477 It is always safe for this function to do nothing. It exists to
5478 recognize opportunities to optimize the output.
5480 On RS/6000, first check for the sum of a register with a constant
5481 integer that is out of range. If so, generate code to add the
5482 constant with the low-order 16 bits masked to the register and force
5483 this result into another register (this can be done with `cau').
5484 Then generate an address of REG+(CONST&0xffff), allowing for the
5485 possibility of bit 16 being a one.
5487 Then check for the sum of a register and something not constant, try to
5488 load the other things into a register and return the sum. */
5491 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
5492 enum machine_mode mode)
5494 unsigned int extra = 0;
5496 if (!reg_offset_addressing_ok_p (mode))
5498 if (virtual_stack_registers_memory_p (x))
5501 /* In theory we should not be seeing addresses of the form reg+0,
5502 but just in case it is generated, optimize it away. */
5503 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
5504 return force_reg (Pmode, XEXP (x, 0));
5506 /* Make sure both operands are registers. */
5507 else if (GET_CODE (x) == PLUS)
5508 return gen_rtx_PLUS (Pmode,
5509 force_reg (Pmode, XEXP (x, 0)),
5510 force_reg (Pmode, XEXP (x, 1)));
5512 return force_reg (Pmode, x);
5514 if (GET_CODE (x) == SYMBOL_REF)
5516 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
5518 return rs6000_legitimize_tls_address (x, model);
5528 if (!TARGET_POWERPC64)
5536 extra = TARGET_POWERPC64 ? 8 : 12;
5542 if (GET_CODE (x) == PLUS
5543 && GET_CODE (XEXP (x, 0)) == REG
5544 && GET_CODE (XEXP (x, 1)) == CONST_INT
5545 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
5547 && !((TARGET_POWERPC64
5548 && (mode == DImode || mode == TImode)
5549 && (INTVAL (XEXP (x, 1)) & 3) != 0)
5550 || SPE_VECTOR_MODE (mode)
5551 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5552 || mode == DImode || mode == DDmode
5553 || mode == TDmode))))
5555 HOST_WIDE_INT high_int, low_int;
5557 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5558 if (low_int >= 0x8000 - extra)
5560 high_int = INTVAL (XEXP (x, 1)) - low_int;
5561 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
5562 GEN_INT (high_int)), 0);
5563 return plus_constant (sum, low_int);
5565 else if (GET_CODE (x) == PLUS
5566 && GET_CODE (XEXP (x, 0)) == REG
5567 && GET_CODE (XEXP (x, 1)) != CONST_INT
5568 && GET_MODE_NUNITS (mode) == 1
5569 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5571 || ((mode != DImode && mode != DFmode && mode != DDmode)
5572 || (TARGET_E500_DOUBLE && mode != DDmode)))
5573 && (TARGET_POWERPC64 || mode != DImode)
5574 && !avoiding_indexed_address_p (mode)
5579 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
5580 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
5582 else if (SPE_VECTOR_MODE (mode)
5583 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5584 || mode == DDmode || mode == TDmode
5585 || mode == DImode)))
5589 /* We accept [reg + reg] and [reg + OFFSET]. */
5591 if (GET_CODE (x) == PLUS)
5593 rtx op1 = XEXP (x, 0);
5594 rtx op2 = XEXP (x, 1);
5597 op1 = force_reg (Pmode, op1);
5599 if (GET_CODE (op2) != REG
5600 && (GET_CODE (op2) != CONST_INT
5601 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
5602 || (GET_MODE_SIZE (mode) > 8
5603 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
5604 op2 = force_reg (Pmode, op2);
5606 /* We can't always do [reg + reg] for these, because [reg +
5607 reg + offset] is not a legitimate addressing mode. */
5608 y = gen_rtx_PLUS (Pmode, op1, op2);
5610 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
5611 return force_reg (Pmode, y);
5616 return force_reg (Pmode, x);
5622 && GET_CODE (x) != CONST_INT
5623 && GET_CODE (x) != CONST_DOUBLE
5625 && GET_MODE_NUNITS (mode) == 1
5626 && (GET_MODE_BITSIZE (mode) <= 32
5627 || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5628 && (mode == DFmode || mode == DDmode))))
5630 rtx reg = gen_reg_rtx (Pmode);
5631 emit_insn (gen_elf_high (reg, x));
5632 return gen_rtx_LO_SUM (Pmode, reg, x);
5634 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
5637 && ! MACHO_DYNAMIC_NO_PIC_P
5639 && GET_CODE (x) != CONST_INT
5640 && GET_CODE (x) != CONST_DOUBLE
5642 && GET_MODE_NUNITS (mode) == 1
5643 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5644 || (mode != DFmode && mode != DDmode))
5648 rtx reg = gen_reg_rtx (Pmode);
5649 emit_insn (gen_macho_high (reg, x));
5650 return gen_rtx_LO_SUM (Pmode, reg, x);
5653 && GET_CODE (x) == SYMBOL_REF
5654 && constant_pool_expr_p (x)
5655 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
5657 rtx reg = TARGET_CMODEL != CMODEL_SMALL ? gen_reg_rtx (Pmode) : NULL_RTX;
5658 return create_TOC_reference (x, reg);
5664 /* Debug version of rs6000_legitimize_address. */
5666 rs6000_debug_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
5672 ret = rs6000_legitimize_address (x, oldx, mode);
5673 insns = get_insns ();
5679 "\nrs6000_legitimize_address: mode %s, old code %s, "
5680 "new code %s, modified\n",
5681 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
5682 GET_RTX_NAME (GET_CODE (ret)));
5684 fprintf (stderr, "Original address:\n");
5687 fprintf (stderr, "oldx:\n");
5690 fprintf (stderr, "New address:\n");
5695 fprintf (stderr, "Insns added:\n");
5696 debug_rtx_list (insns, 20);
5702 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5703 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
5714 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5715 We need to emit DTP-relative relocations. */
5718 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
5723 fputs ("\t.long\t", file);
5726 fputs (DOUBLE_INT_ASM_OP, file);
5731 output_addr_const (file, x);
5732 fputs ("@dtprel+0x8000", file);
5735 /* In the name of slightly smaller debug output, and to cater to
5736 general assembler lossage, recognize various UNSPEC sequences
5737 and turn them back into a direct symbol reference. */
5740 rs6000_delegitimize_address (rtx orig_x)
5744 orig_x = delegitimize_mem_from_attrs (orig_x);
5749 if (GET_CODE (x) == (TARGET_CMODEL != CMODEL_SMALL ? LO_SUM : PLUS)
5750 && GET_CODE (XEXP (x, 1)) == CONST)
5752 rtx offset = NULL_RTX;
5754 y = XEXP (XEXP (x, 1), 0);
5755 if (GET_CODE (y) == PLUS
5756 && GET_MODE (y) == Pmode
5757 && CONST_INT_P (XEXP (y, 1)))
5759 offset = XEXP (y, 1);
5762 if (GET_CODE (y) == UNSPEC
5763 && XINT (y, 1) == UNSPEC_TOCREL
5764 && ((GET_CODE (XEXP (x, 0)) == REG
5765 && (REGNO (XEXP (x, 0)) == TOC_REGISTER
5766 || TARGET_MINIMAL_TOC
5767 || TARGET_CMODEL != CMODEL_SMALL))
5768 || (TARGET_CMODEL != CMODEL_SMALL
5769 && GET_CODE (XEXP (x, 0)) == CONST
5770 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5771 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == REG
5772 && REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0)) == TOC_REGISTER
5773 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == HIGH
5774 && rtx_equal_p (XEXP (x, 1),
5775 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 1), 0)))))
5777 y = XVECEXP (y, 0, 0);
5778 if (offset != NULL_RTX)
5779 y = gen_rtx_PLUS (Pmode, y, offset);
5780 if (!MEM_P (orig_x))
5783 return replace_equiv_address_nv (orig_x, y);
5788 && GET_CODE (orig_x) == LO_SUM
5789 && GET_CODE (XEXP (orig_x, 1)) == CONST)
5791 y = XEXP (XEXP (orig_x, 1), 0);
5792 if (GET_CODE (y) == UNSPEC
5793 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
5794 return XVECEXP (y, 0, 0);
5800 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5802 static GTY(()) rtx rs6000_tls_symbol;
5804 rs6000_tls_get_addr (void)
5806 if (!rs6000_tls_symbol)
5807 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
5809 return rs6000_tls_symbol;
5812 /* Construct the SYMBOL_REF for TLS GOT references. */
5814 static GTY(()) rtx rs6000_got_symbol;
5816 rs6000_got_sym (void)
5818 if (!rs6000_got_symbol)
5820 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5821 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
5822 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
5825 return rs6000_got_symbol;
5828 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5829 this (thread-local) address. */
5832 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
5836 dest = gen_reg_rtx (Pmode);
5837 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
5843 tlsreg = gen_rtx_REG (Pmode, 13);
5844 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
5848 tlsreg = gen_rtx_REG (Pmode, 2);
5849 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
5853 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
5857 tmp = gen_reg_rtx (Pmode);
5860 tlsreg = gen_rtx_REG (Pmode, 13);
5861 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
5865 tlsreg = gen_rtx_REG (Pmode, 2);
5866 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
5870 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
5872 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
5877 rtx r3, got, tga, tmp1, tmp2, call_insn;
5879 /* We currently use relocations like @got@tlsgd for tls, which
5880 means the linker will handle allocation of tls entries, placing
5881 them in the .got section. So use a pointer to the .got section,
5882 not one to secondary TOC sections used by 64-bit -mminimal-toc,
5883 or to secondary GOT sections used by 32-bit -fPIC. */
5885 got = gen_rtx_REG (Pmode, 2);
5889 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
5892 rtx gsym = rs6000_got_sym ();
5893 got = gen_reg_rtx (Pmode);
5895 rs6000_emit_move (got, gsym, Pmode);
5900 tmp1 = gen_reg_rtx (Pmode);
5901 tmp2 = gen_reg_rtx (Pmode);
5902 mem = gen_const_mem (Pmode, tmp1);
5903 lab = gen_label_rtx ();
5904 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
5905 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
5906 if (TARGET_LINK_STACK)
5907 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
5908 emit_move_insn (tmp2, mem);
5909 last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
5910 set_unique_reg_note (last, REG_EQUAL, gsym);
5915 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
5917 tga = rs6000_tls_get_addr ();
5918 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
5919 1, const0_rtx, Pmode);
5921 r3 = gen_rtx_REG (Pmode, 3);
5922 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5923 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
5924 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5925 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
5926 else if (DEFAULT_ABI == ABI_V4)
5927 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
5930 call_insn = last_call_insn ();
5931 PATTERN (call_insn) = insn;
5932 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5933 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5934 pic_offset_table_rtx);
5936 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
5938 tga = rs6000_tls_get_addr ();
5939 tmp1 = gen_reg_rtx (Pmode);
5940 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
5941 1, const0_rtx, Pmode);
5943 r3 = gen_rtx_REG (Pmode, 3);
5944 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5945 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
5946 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5947 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
5948 else if (DEFAULT_ABI == ABI_V4)
5949 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
5952 call_insn = last_call_insn ();
5953 PATTERN (call_insn) = insn;
5954 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5955 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5956 pic_offset_table_rtx);
5958 if (rs6000_tls_size == 16)
5961 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
5963 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
5965 else if (rs6000_tls_size == 32)
5967 tmp2 = gen_reg_rtx (Pmode);
5969 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
5971 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
5974 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
5976 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
5980 tmp2 = gen_reg_rtx (Pmode);
5982 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
5984 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
5986 insn = gen_rtx_SET (Pmode, dest,
5987 gen_rtx_PLUS (Pmode, tmp2, tmp1));
5993 /* IE, or 64-bit offset LE. */
5994 tmp2 = gen_reg_rtx (Pmode);
5996 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
5998 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
6001 insn = gen_tls_tls_64 (dest, tmp2, addr);
6003 insn = gen_tls_tls_32 (dest, tmp2, addr);
6011 /* Return 1 if X contains a thread-local symbol. */
6014 rs6000_tls_referenced_p (rtx x)
6016 if (! TARGET_HAVE_TLS)
6019 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
6022 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6025 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
6027 if (GET_CODE (x) == CONST
6028 && GET_CODE (XEXP (x, 0)) == PLUS
6029 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH)
6032 return rs6000_tls_referenced_p (x);
6035 /* Return 1 if *X is a thread-local symbol. This is the same as
6036 rs6000_tls_symbol_ref except for the type of the unused argument. */
6039 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6041 return RS6000_SYMBOL_REF_TLS_P (*x);
6044 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6045 replace the input X, or the original X if no replacement is called for.
6046 The output parameter *WIN is 1 if the calling macro should goto WIN,
6049 For RS/6000, we wish to handle large displacements off a base
6050 register by splitting the addend across an addiu/addis and the mem insn.
6051 This cuts number of extra insns needed from 3 to 1.
6053 On Darwin, we use this to generate code for floating point constants.
6054 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6055 The Darwin code is inside #if TARGET_MACHO because only then are the
6056 machopic_* functions defined. */
6058 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
6059 int opnum, int type,
6060 int ind_levels ATTRIBUTE_UNUSED, int *win)
6062 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6064 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6065 DFmode/DImode MEM. */
6068 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
6069 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
6070 reg_offset_p = false;
6072 /* We must recognize output that we have already generated ourselves. */
6073 if (GET_CODE (x) == PLUS
6074 && GET_CODE (XEXP (x, 0)) == PLUS
6075 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6076 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6077 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6079 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6080 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6081 opnum, (enum reload_type)type);
6086 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6087 if (GET_CODE (x) == LO_SUM
6088 && GET_CODE (XEXP (x, 0)) == HIGH)
6090 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6091 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6092 opnum, (enum reload_type)type);
6098 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
6099 && GET_CODE (x) == LO_SUM
6100 && GET_CODE (XEXP (x, 0)) == PLUS
6101 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
6102 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
6103 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
6104 && machopic_operand_p (XEXP (x, 1)))
6106 /* Result of previous invocation of this function on Darwin
6107 floating point constant. */
6108 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6109 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6110 opnum, (enum reload_type)type);
6116 if (TARGET_CMODEL != CMODEL_SMALL
6117 && GET_CODE (x) == LO_SUM
6118 && GET_CODE (XEXP (x, 0)) == PLUS
6119 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6120 && REGNO (XEXP (XEXP (x, 0), 0)) == TOC_REGISTER
6121 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST
6122 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == HIGH
6123 && GET_CODE (XEXP (x, 1)) == CONST
6124 && GET_CODE (XEXP (XEXP (x, 1), 0)) == UNSPEC
6125 && XINT (XEXP (XEXP (x, 1), 0), 1) == UNSPEC_TOCREL
6126 && rtx_equal_p (XEXP (XEXP (XEXP (XEXP (x, 0), 1), 0), 0), XEXP (x, 1)))
6128 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6129 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6130 opnum, (enum reload_type) type);
6135 /* Force ld/std non-word aligned offset into base register by wrapping
6137 if (GET_CODE (x) == PLUS
6138 && GET_CODE (XEXP (x, 0)) == REG
6139 && REGNO (XEXP (x, 0)) < 32
6140 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6141 && GET_CODE (XEXP (x, 1)) == CONST_INT
6143 && (INTVAL (XEXP (x, 1)) & 3) != 0
6144 && VECTOR_MEM_NONE_P (mode)
6145 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
6146 && TARGET_POWERPC64)
6148 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
6149 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6150 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6151 opnum, (enum reload_type) type);
6156 if (GET_CODE (x) == PLUS
6157 && GET_CODE (XEXP (x, 0)) == REG
6158 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
6159 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6160 && GET_CODE (XEXP (x, 1)) == CONST_INT
6162 && !SPE_VECTOR_MODE (mode)
6163 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
6164 || mode == DDmode || mode == TDmode
6166 && VECTOR_MEM_NONE_P (mode))
6168 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
6169 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6171 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6173 /* Check for 32-bit overflow. */
6174 if (high + low != val)
6180 /* Reload the high part into a base reg; leave the low part
6181 in the mem directly. */
6183 x = gen_rtx_PLUS (GET_MODE (x),
6184 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
6188 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6189 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6190 opnum, (enum reload_type)type);
6195 if (GET_CODE (x) == SYMBOL_REF
6197 && VECTOR_MEM_NONE_P (mode)
6198 && !SPE_VECTOR_MODE (mode)
6200 && DEFAULT_ABI == ABI_DARWIN
6201 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
6202 && machopic_symbol_defined_p (x)
6204 && DEFAULT_ABI == ABI_V4
6207 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6208 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6212 && (mode != DImode || TARGET_POWERPC64)
6213 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
6214 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
6219 rtx offset = machopic_gen_offset (x);
6220 x = gen_rtx_LO_SUM (GET_MODE (x),
6221 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
6222 gen_rtx_HIGH (Pmode, offset)), offset);
6226 x = gen_rtx_LO_SUM (GET_MODE (x),
6227 gen_rtx_HIGH (Pmode, x), x);
6229 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6230 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6231 opnum, (enum reload_type)type);
6236 /* Reload an offset address wrapped by an AND that represents the
6237 masking of the lower bits. Strip the outer AND and let reload
6238 convert the offset address into an indirect address. For VSX,
6239 force reload to create the address with an AND in a separate
6240 register, because we can't guarantee an altivec register will
6242 if (VECTOR_MEM_ALTIVEC_P (mode)
6243 && GET_CODE (x) == AND
6244 && GET_CODE (XEXP (x, 0)) == PLUS
6245 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6246 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6247 && GET_CODE (XEXP (x, 1)) == CONST_INT
6248 && INTVAL (XEXP (x, 1)) == -16)
6257 && GET_CODE (x) == SYMBOL_REF
6258 && constant_pool_expr_p (x)
6259 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
6261 x = create_TOC_reference (x, NULL_RTX);
6262 if (TARGET_CMODEL != CMODEL_SMALL)
6263 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6264 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6265 opnum, (enum reload_type) type);
6273 /* Debug version of rs6000_legitimize_reload_address. */
6275 rs6000_debug_legitimize_reload_address (rtx x, enum machine_mode mode,
6276 int opnum, int type,
6277 int ind_levels, int *win)
6279 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
6282 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6283 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6284 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
6288 fprintf (stderr, "Same address returned\n");
6290 fprintf (stderr, "NULL returned\n");
6293 fprintf (stderr, "New address:\n");
6300 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6301 that is a valid memory address for an instruction.
6302 The MODE argument is the machine mode for the MEM expression
6303 that wants to use this address.
6305 On the RS/6000, there are four valid address: a SYMBOL_REF that
6306 refers to a constant pool entry of an address (or the sum of it
6307 plus a constant), a short (16-bit signed) constant plus a register,
6308 the sum of two registers, or a register indirect, possibly with an
6309 auto-increment. For DFmode, DDmode and DImode with a constant plus
6310 register, we must ensure that both words are addressable or PowerPC64
6311 with offset word aligned.
6313 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6314 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6315 because adjacent memory cells are accessed by adding word-sized offsets
6316 during assembly output. */
6318 rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
6320 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6322 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6323 if (VECTOR_MEM_ALTIVEC_P (mode)
6324 && GET_CODE (x) == AND
6325 && GET_CODE (XEXP (x, 1)) == CONST_INT
6326 && INTVAL (XEXP (x, 1)) == -16)
6329 if (RS6000_SYMBOL_REF_TLS_P (x))
6331 if (legitimate_indirect_address_p (x, reg_ok_strict))
6333 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
6334 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6335 && !SPE_VECTOR_MODE (mode)
6338 /* Restrict addressing for DI because of our SUBREG hackery. */
6339 && !(TARGET_E500_DOUBLE
6340 && (mode == DFmode || mode == DDmode || mode == DImode))
6342 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
6344 if (virtual_stack_registers_memory_p (x))
6346 if (reg_offset_p && legitimate_small_data_p (mode, x))
6349 && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
6351 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6354 && GET_CODE (x) == PLUS
6355 && GET_CODE (XEXP (x, 0)) == REG
6356 && (XEXP (x, 0) == virtual_stack_vars_rtx
6357 || XEXP (x, 0) == arg_pointer_rtx)
6358 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6360 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
6365 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6367 || (mode != DFmode && mode != DDmode)
6368 || (TARGET_E500_DOUBLE && mode != DDmode))
6369 && (TARGET_POWERPC64 || mode != DImode)
6370 && !avoiding_indexed_address_p (mode)
6371 && legitimate_indexed_address_p (x, reg_ok_strict))
6373 if (GET_CODE (x) == PRE_MODIFY
6377 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6379 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
6380 && (TARGET_POWERPC64 || mode != DImode)
6381 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6382 && !SPE_VECTOR_MODE (mode)
6383 /* Restrict addressing for DI because of our SUBREG hackery. */
6384 && !(TARGET_E500_DOUBLE
6385 && (mode == DFmode || mode == DDmode || mode == DImode))
6387 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
6388 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
6389 || (!avoiding_indexed_address_p (mode)
6390 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
6391 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6393 if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
6398 /* Debug version of rs6000_legitimate_address_p. */
6400 rs6000_debug_legitimate_address_p (enum machine_mode mode, rtx x,
6403 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
6405 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6406 "strict = %d, code = %s\n",
6407 ret ? "true" : "false",
6408 GET_MODE_NAME (mode),
6410 GET_RTX_NAME (GET_CODE (x)));
6416 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6419 rs6000_mode_dependent_address_p (const_rtx addr)
6421 return rs6000_mode_dependent_address_ptr (addr);
6424 /* Go to LABEL if ADDR (a legitimate address expression)
6425 has an effect that depends on the machine mode it is used for.
6427 On the RS/6000 this is true of all integral offsets (since AltiVec
6428 and VSX modes don't allow them) or is a pre-increment or decrement.
6430 ??? Except that due to conceptual problems in offsettable_address_p
6431 we can't really report the problems of integral offsets. So leave
6432 this assuming that the adjustable offset must be valid for the
6433 sub-words of a TFmode operand, which is what we had before. */
6436 rs6000_mode_dependent_address (const_rtx addr)
6438 switch (GET_CODE (addr))
6441 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6442 is considered a legitimate address before reload, so there
6443 are no offset restrictions in that case. Note that this
6444 condition is safe in strict mode because any address involving
6445 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6446 been rejected as illegitimate. */
6447 if (XEXP (addr, 0) != virtual_stack_vars_rtx
6448 && XEXP (addr, 0) != arg_pointer_rtx
6449 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
6451 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
6452 return val + 12 + 0x8000 >= 0x10000;
6457 /* Anything in the constant pool is sufficiently aligned that
6458 all bytes have the same high part address. */
6459 return !legitimate_constant_pool_address_p (addr, QImode, false);
6461 /* Auto-increment cases are now treated generically in recog.c. */
6463 return TARGET_UPDATE;
6465 /* AND is only allowed in Altivec loads. */
6476 /* Debug version of rs6000_mode_dependent_address. */
6478 rs6000_debug_mode_dependent_address (const_rtx addr)
6480 bool ret = rs6000_mode_dependent_address (addr);
6482 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
6483 ret ? "true" : "false");
6489 /* Implement FIND_BASE_TERM. */
6492 rs6000_find_base_term (rtx op)
6496 split_const (op, &base, &offset);
6497 if (GET_CODE (base) == UNSPEC)
6498 switch (XINT (base, 1))
6501 case UNSPEC_MACHOPIC_OFFSET:
6502 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6503 for aliasing purposes. */
6504 return XVECEXP (base, 0, 0);
6510 /* More elaborate version of recog's offsettable_memref_p predicate
6511 that works around the ??? note of rs6000_mode_dependent_address.
6512 In particular it accepts
6514 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6516 in 32-bit mode, that the recog predicate rejects. */
6519 rs6000_offsettable_memref_p (rtx op)
6524 /* First mimic offsettable_memref_p. */
6525 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
6528 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6529 the latter predicate knows nothing about the mode of the memory
6530 reference and, therefore, assumes that it is the largest supported
6531 mode (TFmode). As a consequence, legitimate offsettable memory
6532 references are rejected. rs6000_legitimate_offset_address_p contains
6533 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
6534 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
6537 /* Change register usage conditional on target flags. */
6539 rs6000_conditional_register_usage (void)
6543 if (TARGET_DEBUG_TARGET)
6544 fprintf (stderr, "rs6000_conditional_register_usage called\n");
6546 /* Set MQ register fixed (already call_used) if not POWER
6547 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
6552 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6554 fixed_regs[13] = call_used_regs[13]
6555 = call_really_used_regs[13] = 1;
6557 /* Conditionally disable FPRs. */
6558 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6559 for (i = 32; i < 64; i++)
6560 fixed_regs[i] = call_used_regs[i]
6561 = call_really_used_regs[i] = 1;
6563 /* The TOC register is not killed across calls in a way that is
6564 visible to the compiler. */
6565 if (DEFAULT_ABI == ABI_AIX)
6566 call_really_used_regs[2] = 0;
6568 if (DEFAULT_ABI == ABI_V4
6569 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6571 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6573 if (DEFAULT_ABI == ABI_V4
6574 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6576 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6577 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6578 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6580 if (DEFAULT_ABI == ABI_DARWIN
6581 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6582 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6583 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6584 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6586 if (TARGET_TOC && TARGET_MINIMAL_TOC)
6587 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6588 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6592 global_regs[SPEFSCR_REGNO] = 1;
6593 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6594 registers in prologues and epilogues. We no longer use r14
6595 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6596 pool for link-compatibility with older versions of GCC. Once
6597 "old" code has died out, we can return r14 to the allocation
6600 = call_used_regs[14]
6601 = call_really_used_regs[14] = 1;
6604 if (!TARGET_ALTIVEC && !TARGET_VSX)
6606 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
6607 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6608 call_really_used_regs[VRSAVE_REGNO] = 1;
6611 if (TARGET_ALTIVEC || TARGET_VSX)
6612 global_regs[VSCR_REGNO] = 1;
6614 if (TARGET_ALTIVEC_ABI)
6616 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
6617 call_used_regs[i] = call_really_used_regs[i] = 1;
6619 /* AIX reserves VR20:31 in non-extended ABI mode. */
6621 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
6622 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6626 /* Try to output insns to set TARGET equal to the constant C if it can
6627 be done in less than N insns. Do all computations in MODE.
6628 Returns the place where the output has been placed if it can be
6629 done and the insns have been emitted. If it would take more than N
6630 insns, zero is returned and no insns and emitted. */
6633 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
6634 rtx source, int n ATTRIBUTE_UNUSED)
6636 rtx result, insn, set;
6637 HOST_WIDE_INT c0, c1;
6644 dest = gen_reg_rtx (mode);
6645 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
6649 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
6651 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
6652 GEN_INT (INTVAL (source)
6653 & (~ (HOST_WIDE_INT) 0xffff))));
6654 emit_insn (gen_rtx_SET (VOIDmode, dest,
6655 gen_rtx_IOR (SImode, copy_rtx (result),
6656 GEN_INT (INTVAL (source) & 0xffff))));
6661 switch (GET_CODE (source))
6664 c0 = INTVAL (source);
6669 #if HOST_BITS_PER_WIDE_INT >= 64
6670 c0 = CONST_DOUBLE_LOW (source);
6673 c0 = CONST_DOUBLE_LOW (source);
6674 c1 = CONST_DOUBLE_HIGH (source);
6682 result = rs6000_emit_set_long_const (dest, c0, c1);
6689 insn = get_last_insn ();
6690 set = single_set (insn);
6691 if (! CONSTANT_P (SET_SRC (set)))
6692 set_unique_reg_note (insn, REG_EQUAL, source);
6697 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6698 fall back to a straight forward decomposition. We do this to avoid
6699 exponential run times encountered when looking for longer sequences
6700 with rs6000_emit_set_const. */
6702 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
6704 if (!TARGET_POWERPC64)
6706 rtx operand1, operand2;
6708 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
6710 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
6712 emit_move_insn (operand1, GEN_INT (c1));
6713 emit_move_insn (operand2, GEN_INT (c2));
6717 HOST_WIDE_INT ud1, ud2, ud3, ud4;
6720 ud2 = (c1 & 0xffff0000) >> 16;
6721 #if HOST_BITS_PER_WIDE_INT >= 64
6725 ud4 = (c2 & 0xffff0000) >> 16;
6727 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
6728 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
6731 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
6733 emit_move_insn (dest, GEN_INT (ud1));
6736 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
6737 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
6740 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6743 emit_move_insn (dest, GEN_INT (ud2 << 16));
6745 emit_move_insn (copy_rtx (dest),
6746 gen_rtx_IOR (DImode, copy_rtx (dest),
6749 else if (ud3 == 0 && ud4 == 0)
6751 gcc_assert (ud2 & 0x8000);
6752 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6755 emit_move_insn (copy_rtx (dest),
6756 gen_rtx_IOR (DImode, copy_rtx (dest),
6758 emit_move_insn (copy_rtx (dest),
6759 gen_rtx_ZERO_EXTEND (DImode,
6760 gen_lowpart (SImode,
6763 else if ((ud4 == 0xffff && (ud3 & 0x8000))
6764 || (ud4 == 0 && ! (ud3 & 0x8000)))
6767 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
6770 emit_move_insn (dest, GEN_INT (ud3 << 16));
6773 emit_move_insn (copy_rtx (dest),
6774 gen_rtx_IOR (DImode, copy_rtx (dest),
6776 emit_move_insn (copy_rtx (dest),
6777 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6780 emit_move_insn (copy_rtx (dest),
6781 gen_rtx_IOR (DImode, copy_rtx (dest),
6787 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
6790 emit_move_insn (dest, GEN_INT (ud4 << 16));
6793 emit_move_insn (copy_rtx (dest),
6794 gen_rtx_IOR (DImode, copy_rtx (dest),
6797 emit_move_insn (copy_rtx (dest),
6798 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6801 emit_move_insn (copy_rtx (dest),
6802 gen_rtx_IOR (DImode, copy_rtx (dest),
6803 GEN_INT (ud2 << 16)));
6805 emit_move_insn (copy_rtx (dest),
6806 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
6812 /* Helper for the following. Get rid of [r+r] memory refs
6813 in cases where it won't work (TImode, TFmode, TDmode). */
6816 rs6000_eliminate_indexed_memrefs (rtx operands[2])
6818 if (reload_in_progress)
6821 if (GET_CODE (operands[0]) == MEM
6822 && GET_CODE (XEXP (operands[0], 0)) != REG
6823 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
6824 GET_MODE (operands[0]), false))
6826 = replace_equiv_address (operands[0],
6827 copy_addr_to_reg (XEXP (operands[0], 0)));
6829 if (GET_CODE (operands[1]) == MEM
6830 && GET_CODE (XEXP (operands[1], 0)) != REG
6831 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
6832 GET_MODE (operands[1]), false))
6834 = replace_equiv_address (operands[1],
6835 copy_addr_to_reg (XEXP (operands[1], 0)));
6838 /* Emit a move from SOURCE to DEST in mode MODE. */
6840 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
6844 operands[1] = source;
6846 if (TARGET_DEBUG_ADDR)
6849 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
6850 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
6851 GET_MODE_NAME (mode),
6854 can_create_pseudo_p ());
6856 fprintf (stderr, "source:\n");
6860 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
6861 if (GET_CODE (operands[1]) == CONST_DOUBLE
6862 && ! FLOAT_MODE_P (mode)
6863 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6865 /* FIXME. This should never happen. */
6866 /* Since it seems that it does, do the safe thing and convert
6868 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
6870 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
6871 || FLOAT_MODE_P (mode)
6872 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
6873 || CONST_DOUBLE_LOW (operands[1]) < 0)
6874 && (CONST_DOUBLE_HIGH (operands[1]) != -1
6875 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
6877 /* Check if GCC is setting up a block move that will end up using FP
6878 registers as temporaries. We must make sure this is acceptable. */
6879 if (GET_CODE (operands[0]) == MEM
6880 && GET_CODE (operands[1]) == MEM
6882 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
6883 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
6884 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
6885 ? 32 : MEM_ALIGN (operands[0])))
6886 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
6888 : MEM_ALIGN (operands[1]))))
6889 && ! MEM_VOLATILE_P (operands [0])
6890 && ! MEM_VOLATILE_P (operands [1]))
6892 emit_move_insn (adjust_address (operands[0], SImode, 0),
6893 adjust_address (operands[1], SImode, 0));
6894 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
6895 adjust_address (copy_rtx (operands[1]), SImode, 4));
6899 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
6900 && !gpc_reg_operand (operands[1], mode))
6901 operands[1] = force_reg (mode, operands[1]);
6903 if (mode == SFmode && ! TARGET_POWERPC
6904 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6905 && GET_CODE (operands[0]) == MEM)
6909 if (reload_in_progress || reload_completed)
6910 regnum = true_regnum (operands[1]);
6911 else if (GET_CODE (operands[1]) == REG)
6912 regnum = REGNO (operands[1]);
6916 /* If operands[1] is a register, on POWER it may have
6917 double-precision data in it, so truncate it to single
6919 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
6922 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
6923 : gen_reg_rtx (mode));
6924 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
6925 operands[1] = newreg;
6929 /* Recognize the case where operand[1] is a reference to thread-local
6930 data and load its address to a register. */
6931 if (rs6000_tls_referenced_p (operands[1]))
6933 enum tls_model model;
6934 rtx tmp = operands[1];
6937 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
6939 addend = XEXP (XEXP (tmp, 0), 1);
6940 tmp = XEXP (XEXP (tmp, 0), 0);
6943 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
6944 model = SYMBOL_REF_TLS_MODEL (tmp);
6945 gcc_assert (model != 0);
6947 tmp = rs6000_legitimize_tls_address (tmp, model);
6950 tmp = gen_rtx_PLUS (mode, tmp, addend);
6951 tmp = force_operand (tmp, operands[0]);
6956 /* Handle the case where reload calls us with an invalid address. */
6957 if (reload_in_progress && mode == Pmode
6958 && (! general_operand (operands[1], mode)
6959 || ! nonimmediate_operand (operands[0], mode)))
6962 /* 128-bit constant floating-point values on Darwin should really be
6963 loaded as two parts. */
6964 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
6965 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
6967 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
6968 know how to get a DFmode SUBREG of a TFmode. */
6969 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
6970 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
6971 simplify_gen_subreg (imode, operands[1], mode, 0),
6973 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
6974 GET_MODE_SIZE (imode)),
6975 simplify_gen_subreg (imode, operands[1], mode,
6976 GET_MODE_SIZE (imode)),
6981 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
6982 cfun->machine->sdmode_stack_slot =
6983 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
6985 if (reload_in_progress
6987 && MEM_P (operands[0])
6988 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
6989 && REG_P (operands[1]))
6991 if (FP_REGNO_P (REGNO (operands[1])))
6993 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
6994 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6995 emit_insn (gen_movsd_store (mem, operands[1]));
6997 else if (INT_REGNO_P (REGNO (operands[1])))
6999 rtx mem = adjust_address_nv (operands[0], mode, 4);
7000 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7001 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
7007 if (reload_in_progress
7009 && REG_P (operands[0])
7010 && MEM_P (operands[1])
7011 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
7013 if (FP_REGNO_P (REGNO (operands[0])))
7015 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
7016 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7017 emit_insn (gen_movsd_load (operands[0], mem));
7019 else if (INT_REGNO_P (REGNO (operands[0])))
7021 rtx mem = adjust_address_nv (operands[1], mode, 4);
7022 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7023 emit_insn (gen_movsd_hardfloat (operands[0], mem));
7030 /* FIXME: In the long term, this switch statement should go away
7031 and be replaced by a sequence of tests based on things like
7037 if (CONSTANT_P (operands[1])
7038 && GET_CODE (operands[1]) != CONST_INT)
7039 operands[1] = force_const_mem (mode, operands[1]);
7044 rs6000_eliminate_indexed_memrefs (operands);
7051 if (CONSTANT_P (operands[1])
7052 && ! easy_fp_constant (operands[1], mode))
7053 operands[1] = force_const_mem (mode, operands[1]);
7066 if (CONSTANT_P (operands[1])
7067 && !easy_vector_constant (operands[1], mode))
7068 operands[1] = force_const_mem (mode, operands[1]);
7073 /* Use default pattern for address of ELF small data */
7076 && DEFAULT_ABI == ABI_V4
7077 && (GET_CODE (operands[1]) == SYMBOL_REF
7078 || GET_CODE (operands[1]) == CONST)
7079 && small_data_operand (operands[1], mode))
7081 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7085 if (DEFAULT_ABI == ABI_V4
7086 && mode == Pmode && mode == SImode
7087 && flag_pic == 1 && got_operand (operands[1], mode))
7089 emit_insn (gen_movsi_got (operands[0], operands[1]));
7093 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
7097 && CONSTANT_P (operands[1])
7098 && GET_CODE (operands[1]) != HIGH
7099 && GET_CODE (operands[1]) != CONST_INT)
7101 rtx target = (!can_create_pseudo_p ()
7103 : gen_reg_rtx (mode));
7105 /* If this is a function address on -mcall-aixdesc,
7106 convert it to the address of the descriptor. */
7107 if (DEFAULT_ABI == ABI_AIX
7108 && GET_CODE (operands[1]) == SYMBOL_REF
7109 && XSTR (operands[1], 0)[0] == '.')
7111 const char *name = XSTR (operands[1], 0);
7113 while (*name == '.')
7115 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
7116 CONSTANT_POOL_ADDRESS_P (new_ref)
7117 = CONSTANT_POOL_ADDRESS_P (operands[1]);
7118 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
7119 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
7120 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
7121 operands[1] = new_ref;
7124 if (DEFAULT_ABI == ABI_DARWIN)
7127 if (MACHO_DYNAMIC_NO_PIC_P)
7129 /* Take care of any required data indirection. */
7130 operands[1] = rs6000_machopic_legitimize_pic_address (
7131 operands[1], mode, operands[0]);
7132 if (operands[0] != operands[1])
7133 emit_insn (gen_rtx_SET (VOIDmode,
7134 operands[0], operands[1]));
7138 emit_insn (gen_macho_high (target, operands[1]));
7139 emit_insn (gen_macho_low (operands[0], target, operands[1]));
7143 emit_insn (gen_elf_high (target, operands[1]));
7144 emit_insn (gen_elf_low (operands[0], target, operands[1]));
7148 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7149 and we have put it in the TOC, we just need to make a TOC-relative
7152 && GET_CODE (operands[1]) == SYMBOL_REF
7153 && constant_pool_expr_p (operands[1])
7154 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
7155 get_pool_mode (operands[1])))
7156 || (TARGET_CMODEL == CMODEL_MEDIUM
7157 && GET_CODE (operands[1]) == SYMBOL_REF
7158 && !CONSTANT_POOL_ADDRESS_P (operands[1])
7159 && SYMBOL_REF_LOCAL_P (operands[1])))
7162 if (TARGET_CMODEL != CMODEL_SMALL)
7164 if (can_create_pseudo_p ())
7165 reg = gen_reg_rtx (Pmode);
7169 operands[1] = create_TOC_reference (operands[1], reg);
7171 else if (mode == Pmode
7172 && CONSTANT_P (operands[1])
7173 && GET_CODE (operands[1]) != HIGH
7174 && !(TARGET_CMODEL != CMODEL_SMALL
7175 && GET_CODE (operands[1]) == CONST
7176 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7177 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == HIGH)
7178 && ((GET_CODE (operands[1]) != CONST_INT
7179 && ! easy_fp_constant (operands[1], mode))
7180 || (GET_CODE (operands[1]) == CONST_INT
7181 && (num_insns_constant (operands[1], mode)
7182 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
7183 || (GET_CODE (operands[0]) == REG
7184 && FP_REGNO_P (REGNO (operands[0]))))
7185 && ! legitimate_constant_pool_address_p (operands[1], mode,
7187 && ! toc_relative_expr_p (operands[1])
7188 && (TARGET_CMODEL == CMODEL_SMALL
7189 || can_create_pseudo_p ()
7190 || (REG_P (operands[0])
7191 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
7195 /* Darwin uses a special PIC legitimizer. */
7196 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
7199 rs6000_machopic_legitimize_pic_address (operands[1], mode,
7201 if (operands[0] != operands[1])
7202 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7207 /* If we are to limit the number of things we put in the TOC and
7208 this is a symbol plus a constant we can add in one insn,
7209 just put the symbol in the TOC and add the constant. Don't do
7210 this if reload is in progress. */
7211 if (GET_CODE (operands[1]) == CONST
7212 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
7213 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7214 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
7215 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
7216 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
7217 && ! side_effects_p (operands[0]))
7220 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
7221 rtx other = XEXP (XEXP (operands[1], 0), 1);
7223 sym = force_reg (mode, sym);
7224 emit_insn (gen_add3_insn (operands[0], sym, other));
7228 operands[1] = force_const_mem (mode, operands[1]);
7231 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7232 && constant_pool_expr_p (XEXP (operands[1], 0))
7233 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7234 get_pool_constant (XEXP (operands[1], 0)),
7235 get_pool_mode (XEXP (operands[1], 0))))
7239 if (TARGET_CMODEL != CMODEL_SMALL)
7241 if (can_create_pseudo_p ())
7242 reg = gen_reg_rtx (Pmode);
7246 tocref = create_TOC_reference (XEXP (operands[1], 0), reg);
7247 operands[1] = gen_const_mem (mode, tocref);
7248 set_mem_alias_set (operands[1], get_TOC_alias_set ());
7254 rs6000_eliminate_indexed_memrefs (operands);
7258 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7260 gen_rtx_SET (VOIDmode,
7261 operands[0], operands[1]),
7262 gen_rtx_CLOBBER (VOIDmode,
7263 gen_rtx_SCRATCH (SImode)))));
7269 fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
7272 /* Above, we may have called force_const_mem which may have returned
7273 an invalid address. If we can, fix this up; otherwise, reload will
7274 have to deal with it. */
7275 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
7276 operands[1] = validize_mem (operands[1]);
7279 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7282 /* Nonzero if we can use a floating-point register to pass this arg. */
7283 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7284 (SCALAR_FLOAT_MODE_P (MODE) \
7285 && (CUM)->fregno <= FP_ARG_MAX_REG \
7286 && TARGET_HARD_FLOAT && TARGET_FPRS)
7288 /* Nonzero if we can use an AltiVec register to pass this arg. */
7289 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7290 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7291 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7292 && TARGET_ALTIVEC_ABI \
7295 /* Return a nonzero value to say to return the function value in
7296 memory, just as large structures are always returned. TYPE will be
7297 the data type of the value, and FNTYPE will be the type of the
7298 function doing the returning, or @code{NULL} for libcalls.
7300 The AIX ABI for the RS/6000 specifies that all structures are
7301 returned in memory. The Darwin ABI does the same.
7303 For the Darwin 64 Bit ABI, a function result can be returned in
7304 registers or in memory, depending on the size of the return data
7305 type. If it is returned in registers, the value occupies the same
7306 registers as it would if it were the first and only function
7307 argument. Otherwise, the function places its result in memory at
7308 the location pointed to by GPR3.
7310 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7311 but a draft put them in memory, and GCC used to implement the draft
7312 instead of the final standard. Therefore, aix_struct_return
7313 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7314 compatibility can change DRAFT_V4_STRUCT_RET to override the
7315 default, and -m switches get the final word. See
7316 rs6000_option_override_internal for more details.
7318 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7319 long double support is enabled. These values are returned in memory.
7321 int_size_in_bytes returns -1 for variable size objects, which go in
7322 memory always. The cast to unsigned makes -1 > 8. */
7325 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7327 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7329 && rs6000_darwin64_abi
7330 && TREE_CODE (type) == RECORD_TYPE
7331 && int_size_in_bytes (type) > 0)
7333 CUMULATIVE_ARGS valcum;
7337 valcum.fregno = FP_ARG_MIN_REG;
7338 valcum.vregno = ALTIVEC_ARG_MIN_REG;
7339 /* Do a trial code generation as if this were going to be passed
7340 as an argument; if any part goes in memory, we return NULL. */
7341 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
7344 /* Otherwise fall through to more conventional ABI rules. */
7347 if (AGGREGATE_TYPE_P (type)
7348 && (aix_struct_return
7349 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
7352 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7353 modes only exist for GCC vector types if -maltivec. */
7354 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
7355 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7358 /* Return synthetic vectors in memory. */
7359 if (TREE_CODE (type) == VECTOR_TYPE
7360 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
7362 static bool warned_for_return_big_vectors = false;
7363 if (!warned_for_return_big_vectors)
7365 warning (0, "GCC vector returned by reference: "
7366 "non-standard ABI extension with no compatibility guarantee");
7367 warned_for_return_big_vectors = true;
7372 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
7378 #ifdef HAVE_AS_GNU_ATTRIBUTE
7379 /* Return TRUE if a call to function FNDECL may be one that
7380 potentially affects the function calling ABI of the object file. */
7383 call_ABI_of_interest (tree fndecl)
7385 if (cgraph_state == CGRAPH_STATE_EXPANSION)
7387 struct cgraph_node *c_node;
7389 /* Libcalls are always interesting. */
7390 if (fndecl == NULL_TREE)
7393 /* Any call to an external function is interesting. */
7394 if (DECL_EXTERNAL (fndecl))
7397 /* Interesting functions that we are emitting in this object file. */
7398 c_node = cgraph_get_node (fndecl);
7399 c_node = cgraph_function_or_thunk_node (c_node, NULL);
7400 return !cgraph_only_called_directly_p (c_node);
7406 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7407 for a call to a function whose data type is FNTYPE.
7408 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7410 For incoming args we set the number of arguments in the prototype large
7411 so we never return a PARALLEL. */
7414 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
7415 rtx libname ATTRIBUTE_UNUSED, int incoming,
7416 int libcall, int n_named_args,
7417 tree fndecl ATTRIBUTE_UNUSED,
7418 enum machine_mode return_mode ATTRIBUTE_UNUSED)
7420 static CUMULATIVE_ARGS zero_cumulative;
7422 *cum = zero_cumulative;
7424 cum->fregno = FP_ARG_MIN_REG;
7425 cum->vregno = ALTIVEC_ARG_MIN_REG;
7426 cum->prototype = (fntype && prototype_p (fntype));
7427 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
7428 ? CALL_LIBCALL : CALL_NORMAL);
7429 cum->sysv_gregno = GP_ARG_MIN_REG;
7430 cum->stdarg = stdarg_p (fntype);
7432 cum->nargs_prototype = 0;
7433 if (incoming || cum->prototype)
7434 cum->nargs_prototype = n_named_args;
7436 /* Check for a longcall attribute. */
7437 if ((!fntype && rs6000_default_long_calls)
7439 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
7440 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
7441 cum->call_cookie |= CALL_LONG;
7443 if (TARGET_DEBUG_ARG)
7445 fprintf (stderr, "\ninit_cumulative_args:");
7448 tree ret_type = TREE_TYPE (fntype);
7449 fprintf (stderr, " ret code = %s,",
7450 tree_code_name[ (int)TREE_CODE (ret_type) ]);
7453 if (cum->call_cookie & CALL_LONG)
7454 fprintf (stderr, " longcall,");
7456 fprintf (stderr, " proto = %d, nargs = %d\n",
7457 cum->prototype, cum->nargs_prototype);
7460 #ifdef HAVE_AS_GNU_ATTRIBUTE
7461 if (DEFAULT_ABI == ABI_V4)
7463 cum->escapes = call_ABI_of_interest (fndecl);
7470 return_type = TREE_TYPE (fntype);
7471 return_mode = TYPE_MODE (return_type);
7474 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
7476 if (return_type != NULL)
7478 if (TREE_CODE (return_type) == RECORD_TYPE
7479 && TYPE_TRANSPARENT_AGGR (return_type))
7481 return_type = TREE_TYPE (first_field (return_type));
7482 return_mode = TYPE_MODE (return_type);
7484 if (AGGREGATE_TYPE_P (return_type)
7485 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
7487 rs6000_returns_struct = true;
7489 if (SCALAR_FLOAT_MODE_P (return_mode))
7490 rs6000_passes_float = true;
7491 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
7492 || SPE_VECTOR_MODE (return_mode))
7493 rs6000_passes_vector = true;
7500 && TARGET_ALTIVEC_ABI
7501 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
7503 error ("cannot return value in vector register because"
7504 " altivec instructions are disabled, use -maltivec"
7509 /* Return true if TYPE must be passed on the stack and not in registers. */
7512 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
7514 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
7515 return must_pass_in_stack_var_size (mode, type);
7517 return must_pass_in_stack_var_size_or_pad (mode, type);
7520 /* If defined, a C expression which determines whether, and in which
7521 direction, to pad out an argument with extra space. The value
7522 should be of type `enum direction': either `upward' to pad above
7523 the argument, `downward' to pad below, or `none' to inhibit
7526 For the AIX ABI structs are always stored left shifted in their
7530 function_arg_padding (enum machine_mode mode, const_tree type)
7532 #ifndef AGGREGATE_PADDING_FIXED
7533 #define AGGREGATE_PADDING_FIXED 0
7535 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7536 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7539 if (!AGGREGATE_PADDING_FIXED)
7541 /* GCC used to pass structures of the same size as integer types as
7542 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7543 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7544 passed padded downward, except that -mstrict-align further
7545 muddied the water in that multi-component structures of 2 and 4
7546 bytes in size were passed padded upward.
7548 The following arranges for best compatibility with previous
7549 versions of gcc, but removes the -mstrict-align dependency. */
7550 if (BYTES_BIG_ENDIAN)
7552 HOST_WIDE_INT size = 0;
7554 if (mode == BLKmode)
7556 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
7557 size = int_size_in_bytes (type);
7560 size = GET_MODE_SIZE (mode);
7562 if (size == 1 || size == 2 || size == 4)
7568 if (AGGREGATES_PAD_UPWARD_ALWAYS)
7570 if (type != 0 && AGGREGATE_TYPE_P (type))
7574 /* Fall back to the default. */
7575 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7578 /* If defined, a C expression that gives the alignment boundary, in bits,
7579 of an argument with the specified mode and type. If it is not defined,
7580 PARM_BOUNDARY is used for all arguments.
7582 V.4 wants long longs and doubles to be double word aligned. Just
7583 testing the mode size is a boneheaded way to do this as it means
7584 that other types such as complex int are also double word aligned.
7585 However, we're stuck with this because changing the ABI might break
7586 existing library interfaces.
7588 Doubleword align SPE vectors.
7589 Quadword align Altivec/VSX vectors.
7590 Quadword align large synthetic vector types. */
7593 rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
7595 if (DEFAULT_ABI == ABI_V4
7596 && (GET_MODE_SIZE (mode) == 8
7597 || (TARGET_HARD_FLOAT
7599 && (mode == TFmode || mode == TDmode))))
7601 else if (SPE_VECTOR_MODE (mode)
7602 || (type && TREE_CODE (type) == VECTOR_TYPE
7603 && int_size_in_bytes (type) >= 8
7604 && int_size_in_bytes (type) < 16))
7606 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7607 || (type && TREE_CODE (type) == VECTOR_TYPE
7608 && int_size_in_bytes (type) >= 16))
7610 else if (TARGET_MACHO
7611 && rs6000_darwin64_abi
7613 && type && TYPE_ALIGN (type) > 64)
7616 return PARM_BOUNDARY;
7619 /* For a function parm of MODE and TYPE, return the starting word in
7620 the parameter area. NWORDS of the parameter area are already used. */
7623 rs6000_parm_start (enum machine_mode mode, const_tree type,
7624 unsigned int nwords)
7627 unsigned int parm_offset;
7629 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
7630 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
7631 return nwords + (-(parm_offset + nwords) & align);
7634 /* Compute the size (in words) of a function argument. */
7636 static unsigned long
7637 rs6000_arg_size (enum machine_mode mode, const_tree type)
7641 if (mode != BLKmode)
7642 size = GET_MODE_SIZE (mode);
7644 size = int_size_in_bytes (type);
7647 return (size + 3) >> 2;
7649 return (size + 7) >> 3;
7652 /* Use this to flush pending int fields. */
7655 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7656 HOST_WIDE_INT bitpos, int final)
7658 unsigned int startbit, endbit;
7659 int intregs, intoffset;
7660 enum machine_mode mode;
7662 /* Handle the situations where a float is taking up the first half
7663 of the GPR, and the other half is empty (typically due to
7664 alignment restrictions). We can detect this by a 8-byte-aligned
7665 int field, or by seeing that this is the final flush for this
7666 argument. Count the word and continue on. */
7667 if (cum->floats_in_gpr == 1
7668 && (cum->intoffset % 64 == 0
7669 || (cum->intoffset == -1 && final)))
7672 cum->floats_in_gpr = 0;
7675 if (cum->intoffset == -1)
7678 intoffset = cum->intoffset;
7679 cum->intoffset = -1;
7680 cum->floats_in_gpr = 0;
7682 if (intoffset % BITS_PER_WORD != 0)
7684 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
7686 if (mode == BLKmode)
7688 /* We couldn't find an appropriate mode, which happens,
7689 e.g., in packed structs when there are 3 bytes to load.
7690 Back intoffset back to the beginning of the word in this
7692 intoffset = intoffset & -BITS_PER_WORD;
7696 startbit = intoffset & -BITS_PER_WORD;
7697 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
7698 intregs = (endbit - startbit) / BITS_PER_WORD;
7699 cum->words += intregs;
7700 /* words should be unsigned. */
7701 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7703 int pad = (endbit/BITS_PER_WORD) - cum->words;
7708 /* The darwin64 ABI calls for us to recurse down through structs,
7709 looking for elements passed in registers. Unfortunately, we have
7710 to track int register count here also because of misalignments
7711 in powerpc alignment mode. */
7714 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7716 HOST_WIDE_INT startbitpos)
7720 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7721 if (TREE_CODE (f) == FIELD_DECL)
7723 HOST_WIDE_INT bitpos = startbitpos;
7724 tree ftype = TREE_TYPE (f);
7725 enum machine_mode mode;
7726 if (ftype == error_mark_node)
7728 mode = TYPE_MODE (ftype);
7730 if (DECL_SIZE (f) != 0
7731 && host_integerp (bit_position (f), 1))
7732 bitpos += int_bit_position (f);
7734 /* ??? FIXME: else assume zero offset. */
7736 if (TREE_CODE (ftype) == RECORD_TYPE)
7737 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7738 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
7740 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7741 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7742 cum->fregno += n_fpregs;
7743 /* Single-precision floats present a special problem for
7744 us, because they are smaller than an 8-byte GPR, and so
7745 the structure-packing rules combined with the standard
7746 varargs behavior mean that we want to pack float/float
7747 and float/int combinations into a single register's
7748 space. This is complicated by the arg advance flushing,
7749 which works on arbitrarily large groups of int-type
7753 if (cum->floats_in_gpr == 1)
7755 /* Two floats in a word; count the word and reset
7758 cum->floats_in_gpr = 0;
7760 else if (bitpos % 64 == 0)
7762 /* A float at the beginning of an 8-byte word;
7763 count it and put off adjusting cum->words until
7764 we see if a arg advance flush is going to do it
7766 cum->floats_in_gpr++;
7770 /* The float is at the end of a word, preceded
7771 by integer fields, so the arg advance flush
7772 just above has already set cum->words and
7773 everything is taken care of. */
7777 cum->words += n_fpregs;
7779 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
7781 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7785 else if (cum->intoffset == -1)
7786 cum->intoffset = bitpos;
7790 /* Check for an item that needs to be considered specially under the darwin 64
7791 bit ABI. These are record types where the mode is BLK or the structure is
7794 rs6000_darwin64_struct_check_p (enum machine_mode mode, const_tree type)
7796 return rs6000_darwin64_abi
7797 && ((mode == BLKmode
7798 && TREE_CODE (type) == RECORD_TYPE
7799 && int_size_in_bytes (type) > 0)
7800 || (type && TREE_CODE (type) == RECORD_TYPE
7801 && int_size_in_bytes (type) == 8)) ? 1 : 0;
7804 /* Update the data in CUM to advance over an argument
7805 of mode MODE and data type TYPE.
7806 (TYPE is null for libcalls where that information may not be available.)
7808 Note that for args passed by reference, function_arg will be called
7809 with MODE and TYPE set to that of the pointer to the arg, not the arg
7813 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7814 const_tree type, bool named, int depth)
7816 /* Only tick off an argument if we're not recursing. */
7818 cum->nargs_prototype--;
7820 #ifdef HAVE_AS_GNU_ATTRIBUTE
7821 if (DEFAULT_ABI == ABI_V4
7824 if (SCALAR_FLOAT_MODE_P (mode))
7825 rs6000_passes_float = true;
7826 else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7827 rs6000_passes_vector = true;
7828 else if (SPE_VECTOR_MODE (mode)
7830 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7831 rs6000_passes_vector = true;
7835 if (TARGET_ALTIVEC_ABI
7836 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7837 || (type && TREE_CODE (type) == VECTOR_TYPE
7838 && int_size_in_bytes (type) == 16)))
7842 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
7845 if (!TARGET_ALTIVEC)
7846 error ("cannot pass argument in vector register because"
7847 " altivec instructions are disabled, use -maltivec"
7850 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7851 even if it is going to be passed in a vector register.
7852 Darwin does the same for variable-argument functions. */
7853 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
7854 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7864 /* Vector parameters must be 16-byte aligned. This places
7865 them at 2 mod 4 in terms of words in 32-bit mode, since
7866 the parameter save area starts at offset 24 from the
7867 stack. In 64-bit mode, they just have to start on an
7868 even word, since the parameter save area is 16-byte
7869 aligned. Space for GPRs is reserved even if the argument
7870 will be passed in memory. */
7872 align = (2 - cum->words) & 3;
7874 align = cum->words & 1;
7875 cum->words += align + rs6000_arg_size (mode, type);
7877 if (TARGET_DEBUG_ARG)
7879 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7881 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7882 cum->nargs_prototype, cum->prototype,
7883 GET_MODE_NAME (mode));
7887 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
7889 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7892 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7894 int size = int_size_in_bytes (type);
7895 /* Variable sized types have size == -1 and are
7896 treated as if consisting entirely of ints.
7897 Pad to 16 byte boundary if needed. */
7898 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7899 && (cum->words % 2) != 0)
7901 /* For varargs, we can just go up by the size of the struct. */
7903 cum->words += (size + 7) / 8;
7906 /* It is tempting to say int register count just goes up by
7907 sizeof(type)/8, but this is wrong in a case such as
7908 { int; double; int; } [powerpc alignment]. We have to
7909 grovel through the fields for these too. */
7911 cum->floats_in_gpr = 0;
7912 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
7913 rs6000_darwin64_record_arg_advance_flush (cum,
7914 size * BITS_PER_UNIT, 1);
7916 if (TARGET_DEBUG_ARG)
7918 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
7919 cum->words, TYPE_ALIGN (type), size);
7921 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7922 cum->nargs_prototype, cum->prototype,
7923 GET_MODE_NAME (mode));
7926 else if (DEFAULT_ABI == ABI_V4)
7928 if (TARGET_HARD_FLOAT && TARGET_FPRS
7929 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
7930 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
7931 || (mode == TFmode && !TARGET_IEEEQUAD)
7932 || mode == SDmode || mode == DDmode || mode == TDmode))
7934 /* _Decimal128 must use an even/odd register pair. This assumes
7935 that the register number is odd when fregno is odd. */
7936 if (mode == TDmode && (cum->fregno % 2) == 1)
7939 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
7940 <= FP_ARG_V4_MAX_REG)
7941 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7944 cum->fregno = FP_ARG_V4_MAX_REG + 1;
7945 if (mode == DFmode || mode == TFmode
7946 || mode == DDmode || mode == TDmode)
7947 cum->words += cum->words & 1;
7948 cum->words += rs6000_arg_size (mode, type);
7953 int n_words = rs6000_arg_size (mode, type);
7954 int gregno = cum->sysv_gregno;
7956 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
7957 (r7,r8) or (r9,r10). As does any other 2 word item such
7958 as complex int due to a historical mistake. */
7960 gregno += (1 - gregno) & 1;
7962 /* Multi-reg args are not split between registers and stack. */
7963 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7965 /* Long long and SPE vectors are aligned on the stack.
7966 So are other 2 word items such as complex int due to
7967 a historical mistake. */
7969 cum->words += cum->words & 1;
7970 cum->words += n_words;
7973 /* Note: continuing to accumulate gregno past when we've started
7974 spilling to the stack indicates the fact that we've started
7975 spilling to the stack to expand_builtin_saveregs. */
7976 cum->sysv_gregno = gregno + n_words;
7979 if (TARGET_DEBUG_ARG)
7981 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7982 cum->words, cum->fregno);
7983 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
7984 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
7985 fprintf (stderr, "mode = %4s, named = %d\n",
7986 GET_MODE_NAME (mode), named);
7991 int n_words = rs6000_arg_size (mode, type);
7992 int start_words = cum->words;
7993 int align_words = rs6000_parm_start (mode, type, start_words);
7995 cum->words = align_words + n_words;
7997 if (SCALAR_FLOAT_MODE_P (mode)
7998 && TARGET_HARD_FLOAT && TARGET_FPRS)
8000 /* _Decimal128 must be passed in an even/odd float register pair.
8001 This assumes that the register number is odd when fregno is
8003 if (mode == TDmode && (cum->fregno % 2) == 1)
8005 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
8008 if (TARGET_DEBUG_ARG)
8010 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8011 cum->words, cum->fregno);
8012 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
8013 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
8014 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
8015 named, align_words - start_words, depth);
8021 rs6000_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
8022 const_tree type, bool named)
8024 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
8029 spe_build_register_parallel (enum machine_mode mode, int gregno)
8036 r1 = gen_rtx_REG (DImode, gregno);
8037 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8038 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
8042 r1 = gen_rtx_REG (DImode, gregno);
8043 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8044 r3 = gen_rtx_REG (DImode, gregno + 2);
8045 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8046 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
8049 r1 = gen_rtx_REG (DImode, gregno);
8050 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8051 r3 = gen_rtx_REG (DImode, gregno + 2);
8052 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8053 r5 = gen_rtx_REG (DImode, gregno + 4);
8054 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
8055 r7 = gen_rtx_REG (DImode, gregno + 6);
8056 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
8057 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
8064 /* Determine where to put a SIMD argument on the SPE. */
8066 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8069 int gregno = cum->sysv_gregno;
8071 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8072 are passed and returned in a pair of GPRs for ABI compatibility. */
8073 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
8074 || mode == DCmode || mode == TCmode))
8076 int n_words = rs6000_arg_size (mode, type);
8078 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8080 gregno += (1 - gregno) & 1;
8082 /* Multi-reg args are not split between registers and stack. */
8083 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8086 return spe_build_register_parallel (mode, gregno);
8090 int n_words = rs6000_arg_size (mode, type);
8092 /* SPE vectors are put in odd registers. */
8093 if (n_words == 2 && (gregno & 1) == 0)
8096 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
8099 enum machine_mode m = SImode;
8101 r1 = gen_rtx_REG (m, gregno);
8102 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
8103 r2 = gen_rtx_REG (m, gregno + 1);
8104 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
8105 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
8112 if (gregno <= GP_ARG_MAX_REG)
8113 return gen_rtx_REG (mode, gregno);
8119 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8120 structure between cum->intoffset and bitpos to integer registers. */
8123 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
8124 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
8126 enum machine_mode mode;
8128 unsigned int startbit, endbit;
8129 int this_regno, intregs, intoffset;
8132 if (cum->intoffset == -1)
8135 intoffset = cum->intoffset;
8136 cum->intoffset = -1;
8138 /* If this is the trailing part of a word, try to only load that
8139 much into the register. Otherwise load the whole register. Note
8140 that in the latter case we may pick up unwanted bits. It's not a
8141 problem at the moment but may wish to revisit. */
8143 if (intoffset % BITS_PER_WORD != 0)
8145 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
8147 if (mode == BLKmode)
8149 /* We couldn't find an appropriate mode, which happens,
8150 e.g., in packed structs when there are 3 bytes to load.
8151 Back intoffset back to the beginning of the word in this
8153 intoffset = intoffset & -BITS_PER_WORD;
8160 startbit = intoffset & -BITS_PER_WORD;
8161 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
8162 intregs = (endbit - startbit) / BITS_PER_WORD;
8163 this_regno = cum->words + intoffset / BITS_PER_WORD;
8165 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
8168 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
8172 intoffset /= BITS_PER_UNIT;
8175 regno = GP_ARG_MIN_REG + this_regno;
8176 reg = gen_rtx_REG (mode, regno);
8178 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8181 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
8185 while (intregs > 0);
8188 /* Recursive workhorse for the following. */
8191 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
8192 HOST_WIDE_INT startbitpos, rtx rvec[],
8197 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
8198 if (TREE_CODE (f) == FIELD_DECL)
8200 HOST_WIDE_INT bitpos = startbitpos;
8201 tree ftype = TREE_TYPE (f);
8202 enum machine_mode mode;
8203 if (ftype == error_mark_node)
8205 mode = TYPE_MODE (ftype);
8207 if (DECL_SIZE (f) != 0
8208 && host_integerp (bit_position (f), 1))
8209 bitpos += int_bit_position (f);
8211 /* ??? FIXME: else assume zero offset. */
8213 if (TREE_CODE (ftype) == RECORD_TYPE)
8214 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
8215 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
8217 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8221 case SCmode: mode = SFmode; break;
8222 case DCmode: mode = DFmode; break;
8223 case TCmode: mode = TFmode; break;
8227 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8228 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8230 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8231 && (mode == TFmode || mode == TDmode));
8232 /* Long double or _Decimal128 split over regs and memory. */
8233 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
8237 = gen_rtx_EXPR_LIST (VOIDmode,
8238 gen_rtx_REG (mode, cum->fregno++),
8239 GEN_INT (bitpos / BITS_PER_UNIT));
8240 if (mode == TFmode || mode == TDmode)
8243 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
8245 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8247 = gen_rtx_EXPR_LIST (VOIDmode,
8248 gen_rtx_REG (mode, cum->vregno++),
8249 GEN_INT (bitpos / BITS_PER_UNIT));
8251 else if (cum->intoffset == -1)
8252 cum->intoffset = bitpos;
8256 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8257 the register(s) to be used for each field and subfield of a struct
8258 being passed by value, along with the offset of where the
8259 register's value may be found in the block. FP fields go in FP
8260 register, vector fields go in vector registers, and everything
8261 else goes in int registers, packed as in memory.
8263 This code is also used for function return values. RETVAL indicates
8264 whether this is the case.
8266 Much of this is taken from the SPARC V9 port, which has a similar
8267 calling convention. */
8270 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
8271 bool named, bool retval)
8273 rtx rvec[FIRST_PSEUDO_REGISTER];
8274 int k = 1, kbase = 1;
8275 HOST_WIDE_INT typesize = int_size_in_bytes (type);
8276 /* This is a copy; modifications are not visible to our caller. */
8277 CUMULATIVE_ARGS copy_cum = *orig_cum;
8278 CUMULATIVE_ARGS *cum = ©_cum;
8280 /* Pad to 16 byte boundary if needed. */
8281 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8282 && (cum->words % 2) != 0)
8289 /* Put entries into rvec[] for individual FP and vector fields, and
8290 for the chunks of memory that go in int regs. Note we start at
8291 element 1; 0 is reserved for an indication of using memory, and
8292 may or may not be filled in below. */
8293 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
8294 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
8296 /* If any part of the struct went on the stack put all of it there.
8297 This hack is because the generic code for
8298 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8299 parts of the struct are not at the beginning. */
8303 return NULL_RTX; /* doesn't go in registers at all */
8305 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8307 if (k > 1 || cum->use_stack)
8308 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
8313 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8316 rs6000_mixed_function_arg (enum machine_mode mode, const_tree type,
8321 rtx rvec[GP_ARG_NUM_REG + 1];
8323 if (align_words >= GP_ARG_NUM_REG)
8326 n_units = rs6000_arg_size (mode, type);
8328 /* Optimize the simple case where the arg fits in one gpr, except in
8329 the case of BLKmode due to assign_parms assuming that registers are
8330 BITS_PER_WORD wide. */
8332 || (n_units == 1 && mode != BLKmode))
8333 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8336 if (align_words + n_units > GP_ARG_NUM_REG)
8337 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8338 using a magic NULL_RTX component.
8339 This is not strictly correct. Only some of the arg belongs in
8340 memory, not all of it. However, the normal scheme using
8341 function_arg_partial_nregs can result in unusual subregs, eg.
8342 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8343 store the whole arg to memory is often more efficient than code
8344 to store pieces, and we know that space is available in the right
8345 place for the whole arg. */
8346 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8351 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
8352 rtx off = GEN_INT (i++ * 4);
8353 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8355 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
8357 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8360 /* Determine where to put an argument to a function.
8361 Value is zero to push the argument on the stack,
8362 or a hard register in which to store the argument.
8364 MODE is the argument's machine mode.
8365 TYPE is the data type of the argument (as a tree).
8366 This is null for libcalls where that information may
8368 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8369 the preceding args and about the function being called. It is
8370 not modified in this routine.
8371 NAMED is nonzero if this argument is a named parameter
8372 (otherwise it is an extra parameter matching an ellipsis).
8374 On RS/6000 the first eight words of non-FP are normally in registers
8375 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8376 Under V.4, the first 8 FP args are in registers.
8378 If this is floating-point and no prototype is specified, we use
8379 both an FP and integer register (or possibly FP reg and stack). Library
8380 functions (when CALL_LIBCALL is set) always have the proper types for args,
8381 so we can pass the FP value just in one register. emit_library_function
8382 doesn't support PARALLEL anyway.
8384 Note that for args passed by reference, function_arg will be called
8385 with MODE and TYPE set to that of the pointer to the arg, not the arg
8389 rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8390 const_tree type, bool named)
8392 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8393 enum rs6000_abi abi = DEFAULT_ABI;
8395 /* Return a marker to indicate whether CR1 needs to set or clear the
8396 bit that V.4 uses to say fp args were passed in registers.
8397 Assume that we don't need the marker for software floating point,
8398 or compiler generated library calls. */
8399 if (mode == VOIDmode)
8402 && (cum->call_cookie & CALL_LIBCALL) == 0
8404 || (cum->nargs_prototype < 0
8405 && (cum->prototype || TARGET_NO_PROTOTYPE))))
8407 /* For the SPE, we need to crxor CR6 always. */
8409 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
8410 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
8411 return GEN_INT (cum->call_cookie
8412 | ((cum->fregno == FP_ARG_MIN_REG)
8413 ? CALL_V4_SET_FP_ARGS
8414 : CALL_V4_CLEAR_FP_ARGS));
8417 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
8420 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8422 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
8423 if (rslt != NULL_RTX)
8425 /* Else fall through to usual handling. */
8428 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
8429 if (TARGET_64BIT && ! cum->prototype)
8431 /* Vector parameters get passed in vector register
8432 and also in GPRs or memory, in absence of prototype. */
8435 align_words = (cum->words + 1) & ~1;
8437 if (align_words >= GP_ARG_NUM_REG)
8443 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8445 return gen_rtx_PARALLEL (mode,
8447 gen_rtx_EXPR_LIST (VOIDmode,
8449 gen_rtx_EXPR_LIST (VOIDmode,
8450 gen_rtx_REG (mode, cum->vregno),
8454 return gen_rtx_REG (mode, cum->vregno);
8455 else if (TARGET_ALTIVEC_ABI
8456 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
8457 || (type && TREE_CODE (type) == VECTOR_TYPE
8458 && int_size_in_bytes (type) == 16)))
8460 if (named || abi == ABI_V4)
8464 /* Vector parameters to varargs functions under AIX or Darwin
8465 get passed in memory and possibly also in GPRs. */
8466 int align, align_words, n_words;
8467 enum machine_mode part_mode;
8469 /* Vector parameters must be 16-byte aligned. This places them at
8470 2 mod 4 in terms of words in 32-bit mode, since the parameter
8471 save area starts at offset 24 from the stack. In 64-bit mode,
8472 they just have to start on an even word, since the parameter
8473 save area is 16-byte aligned. */
8475 align = (2 - cum->words) & 3;
8477 align = cum->words & 1;
8478 align_words = cum->words + align;
8480 /* Out of registers? Memory, then. */
8481 if (align_words >= GP_ARG_NUM_REG)
8484 if (TARGET_32BIT && TARGET_POWERPC64)
8485 return rs6000_mixed_function_arg (mode, type, align_words);
8487 /* The vector value goes in GPRs. Only the part of the
8488 value in GPRs is reported here. */
8490 n_words = rs6000_arg_size (mode, type);
8491 if (align_words + n_words > GP_ARG_NUM_REG)
8492 /* Fortunately, there are only two possibilities, the value
8493 is either wholly in GPRs or half in GPRs and half not. */
8496 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
8499 else if (TARGET_SPE_ABI && TARGET_SPE
8500 && (SPE_VECTOR_MODE (mode)
8501 || (TARGET_E500_DOUBLE && (mode == DFmode
8504 || mode == TCmode))))
8505 return rs6000_spe_function_arg (cum, mode, type);
8507 else if (abi == ABI_V4)
8509 if (TARGET_HARD_FLOAT && TARGET_FPRS
8510 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8511 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8512 || (mode == TFmode && !TARGET_IEEEQUAD)
8513 || mode == SDmode || mode == DDmode || mode == TDmode))
8515 /* _Decimal128 must use an even/odd register pair. This assumes
8516 that the register number is odd when fregno is odd. */
8517 if (mode == TDmode && (cum->fregno % 2) == 1)
8520 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8521 <= FP_ARG_V4_MAX_REG)
8522 return gen_rtx_REG (mode, cum->fregno);
8528 int n_words = rs6000_arg_size (mode, type);
8529 int gregno = cum->sysv_gregno;
8531 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8532 (r7,r8) or (r9,r10). As does any other 2 word item such
8533 as complex int due to a historical mistake. */
8535 gregno += (1 - gregno) & 1;
8537 /* Multi-reg args are not split between registers and stack. */
8538 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8541 if (TARGET_32BIT && TARGET_POWERPC64)
8542 return rs6000_mixed_function_arg (mode, type,
8543 gregno - GP_ARG_MIN_REG);
8544 return gen_rtx_REG (mode, gregno);
8549 int align_words = rs6000_parm_start (mode, type, cum->words);
8551 /* _Decimal128 must be passed in an even/odd float register pair.
8552 This assumes that the register number is odd when fregno is odd. */
8553 if (mode == TDmode && (cum->fregno % 2) == 1)
8556 if (USE_FP_FOR_ARG_P (cum, mode, type))
8558 rtx rvec[GP_ARG_NUM_REG + 1];
8562 enum machine_mode fmode = mode;
8563 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8565 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8567 /* Currently, we only ever need one reg here because complex
8568 doubles are split. */
8569 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8570 && (fmode == TFmode || fmode == TDmode));
8572 /* Long double or _Decimal128 split over regs and memory. */
8573 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
8576 /* Do we also need to pass this arg in the parameter save
8579 && (cum->nargs_prototype <= 0
8580 || (DEFAULT_ABI == ABI_AIX
8582 && align_words >= GP_ARG_NUM_REG)));
8584 if (!needs_psave && mode == fmode)
8585 return gen_rtx_REG (fmode, cum->fregno);
8590 /* Describe the part that goes in gprs or the stack.
8591 This piece must come first, before the fprs. */
8592 if (align_words < GP_ARG_NUM_REG)
8594 unsigned long n_words = rs6000_arg_size (mode, type);
8596 if (align_words + n_words > GP_ARG_NUM_REG
8597 || (TARGET_32BIT && TARGET_POWERPC64))
8599 /* If this is partially on the stack, then we only
8600 include the portion actually in registers here. */
8601 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
8604 if (align_words + n_words > GP_ARG_NUM_REG)
8605 /* Not all of the arg fits in gprs. Say that it
8606 goes in memory too, using a magic NULL_RTX
8607 component. Also see comment in
8608 rs6000_mixed_function_arg for why the normal
8609 function_arg_partial_nregs scheme doesn't work
8611 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
8615 r = gen_rtx_REG (rmode,
8616 GP_ARG_MIN_REG + align_words);
8617 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
8618 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8620 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
8624 /* The whole arg fits in gprs. */
8625 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8626 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8630 /* It's entirely in memory. */
8631 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8634 /* Describe where this piece goes in the fprs. */
8635 r = gen_rtx_REG (fmode, cum->fregno);
8636 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8638 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8640 else if (align_words < GP_ARG_NUM_REG)
8642 if (TARGET_32BIT && TARGET_POWERPC64)
8643 return rs6000_mixed_function_arg (mode, type, align_words);
8645 if (mode == BLKmode)
8648 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8655 /* For an arg passed partly in registers and partly in memory, this is
8656 the number of bytes passed in registers. For args passed entirely in
8657 registers or entirely in memory, zero. When an arg is described by a
8658 PARALLEL, perhaps using more than one register type, this function
8659 returns the number of bytes used by the first element of the PARALLEL. */
8662 rs6000_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8663 tree type, bool named)
8665 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8669 if (DEFAULT_ABI == ABI_V4)
8672 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
8673 && cum->nargs_prototype >= 0)
8676 /* In this complicated case we just disable the partial_nregs code. */
8677 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8680 align_words = rs6000_parm_start (mode, type, cum->words);
8682 if (USE_FP_FOR_ARG_P (cum, mode, type))
8684 /* If we are passing this arg in the fixed parameter save area
8685 (gprs or memory) as well as fprs, then this function should
8686 return the number of partial bytes passed in the parameter
8687 save area rather than partial bytes passed in fprs. */
8689 && (cum->nargs_prototype <= 0
8690 || (DEFAULT_ABI == ABI_AIX
8692 && align_words >= GP_ARG_NUM_REG)))
8694 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
8695 > FP_ARG_MAX_REG + 1)
8696 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
8697 else if (cum->nargs_prototype >= 0)
8701 if (align_words < GP_ARG_NUM_REG
8702 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
8703 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8705 if (ret != 0 && TARGET_DEBUG_ARG)
8706 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8711 /* A C expression that indicates when an argument must be passed by
8712 reference. If nonzero for an argument, a copy of that argument is
8713 made in memory and a pointer to the argument is passed instead of
8714 the argument itself. The pointer is passed in whatever way is
8715 appropriate for passing a pointer to that type.
8717 Under V.4, aggregates and long double are passed by reference.
8719 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8720 reference unless the AltiVec vector extension ABI is in force.
8722 As an extension to all ABIs, variable sized types are passed by
8726 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
8727 enum machine_mode mode, const_tree type,
8728 bool named ATTRIBUTE_UNUSED)
8730 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
8732 if (TARGET_DEBUG_ARG)
8733 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
8740 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
8742 if (TARGET_DEBUG_ARG)
8743 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8747 if (int_size_in_bytes (type) < 0)
8749 if (TARGET_DEBUG_ARG)
8750 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8754 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8755 modes only exist for GCC vector types if -maltivec. */
8756 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8758 if (TARGET_DEBUG_ARG)
8759 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8763 /* Pass synthetic vectors in memory. */
8764 if (TREE_CODE (type) == VECTOR_TYPE
8765 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8767 static bool warned_for_pass_big_vectors = false;
8768 if (TARGET_DEBUG_ARG)
8769 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8770 if (!warned_for_pass_big_vectors)
8772 warning (0, "GCC vector passed by reference: "
8773 "non-standard ABI extension with no compatibility guarantee");
8774 warned_for_pass_big_vectors = true;
8783 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8786 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8791 for (i = 0; i < nregs; i++)
8793 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8794 if (reload_completed)
8796 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8799 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8800 i * GET_MODE_SIZE (reg_mode));
8803 tem = replace_equiv_address (tem, XEXP (tem, 0));
8807 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8811 /* Perform any needed actions needed for a function that is receiving a
8812 variable number of arguments.
8816 MODE and TYPE are the mode and type of the current parameter.
8818 PRETEND_SIZE is a variable that should be set to the amount of stack
8819 that must be pushed by the prolog to pretend that our caller pushed
8822 Normally, this macro will push all remaining incoming registers on the
8823 stack and set PRETEND_SIZE to the length of the registers pushed. */
8826 setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
8827 tree type, int *pretend_size ATTRIBUTE_UNUSED,
8830 CUMULATIVE_ARGS next_cum;
8831 int reg_size = TARGET_32BIT ? 4 : 8;
8832 rtx save_area = NULL_RTX, mem;
8833 int first_reg_offset;
8836 /* Skip the last named argument. */
8837 next_cum = *get_cumulative_args (cum);
8838 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
8840 if (DEFAULT_ABI == ABI_V4)
8842 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8846 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8847 HOST_WIDE_INT offset = 0;
8849 /* Try to optimize the size of the varargs save area.
8850 The ABI requires that ap.reg_save_area is doubleword
8851 aligned, but we don't need to allocate space for all
8852 the bytes, only those to which we actually will save
8854 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8855 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8856 if (TARGET_HARD_FLOAT && TARGET_FPRS
8857 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8858 && cfun->va_list_fpr_size)
8861 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8862 * UNITS_PER_FP_WORD;
8863 if (cfun->va_list_fpr_size
8864 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8865 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8867 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8868 * UNITS_PER_FP_WORD;
8872 offset = -((first_reg_offset * reg_size) & ~7);
8873 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8875 gpr_reg_num = cfun->va_list_gpr_size;
8876 if (reg_size == 4 && (first_reg_offset & 1))
8879 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8882 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8884 - (int) (GP_ARG_NUM_REG * reg_size);
8886 if (gpr_size + fpr_size)
8889 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
8890 gcc_assert (GET_CODE (reg_save_area) == MEM);
8891 reg_save_area = XEXP (reg_save_area, 0);
8892 if (GET_CODE (reg_save_area) == PLUS)
8894 gcc_assert (XEXP (reg_save_area, 0)
8895 == virtual_stack_vars_rtx);
8896 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
8897 offset += INTVAL (XEXP (reg_save_area, 1));
8900 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
8903 cfun->machine->varargs_save_offset = offset;
8904 save_area = plus_constant (virtual_stack_vars_rtx, offset);
8909 first_reg_offset = next_cum.words;
8910 save_area = virtual_incoming_args_rtx;
8912 if (targetm.calls.must_pass_in_stack (mode, type))
8913 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
8916 set = get_varargs_alias_set ();
8917 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
8918 && cfun->va_list_gpr_size)
8920 int nregs = GP_ARG_NUM_REG - first_reg_offset;
8922 if (va_list_gpr_counter_field)
8924 /* V4 va_list_gpr_size counts number of registers needed. */
8925 if (nregs > cfun->va_list_gpr_size)
8926 nregs = cfun->va_list_gpr_size;
8930 /* char * va_list instead counts number of bytes needed. */
8931 if (nregs > cfun->va_list_gpr_size / reg_size)
8932 nregs = cfun->va_list_gpr_size / reg_size;
8935 mem = gen_rtx_MEM (BLKmode,
8936 plus_constant (save_area,
8937 first_reg_offset * reg_size));
8938 MEM_NOTRAP_P (mem) = 1;
8939 set_mem_alias_set (mem, set);
8940 set_mem_align (mem, BITS_PER_WORD);
8942 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
8946 /* Save FP registers if needed. */
8947 if (DEFAULT_ABI == ABI_V4
8948 && TARGET_HARD_FLOAT && TARGET_FPRS
8950 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8951 && cfun->va_list_fpr_size)
8953 int fregno = next_cum.fregno, nregs;
8954 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
8955 rtx lab = gen_label_rtx ();
8956 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
8957 * UNITS_PER_FP_WORD);
8960 (gen_rtx_SET (VOIDmode,
8962 gen_rtx_IF_THEN_ELSE (VOIDmode,
8963 gen_rtx_NE (VOIDmode, cr1,
8965 gen_rtx_LABEL_REF (VOIDmode, lab),
8969 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
8970 fregno++, off += UNITS_PER_FP_WORD, nregs++)
8972 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8974 plus_constant (save_area, off));
8975 MEM_NOTRAP_P (mem) = 1;
8976 set_mem_alias_set (mem, set);
8977 set_mem_align (mem, GET_MODE_ALIGNMENT (
8978 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8979 ? DFmode : SFmode));
8980 emit_move_insn (mem, gen_rtx_REG (
8981 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8982 ? DFmode : SFmode, fregno));
8989 /* Create the va_list data type. */
8992 rs6000_build_builtin_va_list (void)
8994 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
8996 /* For AIX, prefer 'char *' because that's what the system
8997 header files like. */
8998 if (DEFAULT_ABI != ABI_V4)
8999 return build_pointer_type (char_type_node);
9001 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
9002 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
9003 get_identifier ("__va_list_tag"), record);
9005 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
9006 unsigned_char_type_node);
9007 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
9008 unsigned_char_type_node);
9009 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9011 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9012 get_identifier ("reserved"), short_unsigned_type_node);
9013 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9014 get_identifier ("overflow_arg_area"),
9016 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9017 get_identifier ("reg_save_area"),
9020 va_list_gpr_counter_field = f_gpr;
9021 va_list_fpr_counter_field = f_fpr;
9023 DECL_FIELD_CONTEXT (f_gpr) = record;
9024 DECL_FIELD_CONTEXT (f_fpr) = record;
9025 DECL_FIELD_CONTEXT (f_res) = record;
9026 DECL_FIELD_CONTEXT (f_ovf) = record;
9027 DECL_FIELD_CONTEXT (f_sav) = record;
9029 TYPE_STUB_DECL (record) = type_decl;
9030 TYPE_NAME (record) = type_decl;
9031 TYPE_FIELDS (record) = f_gpr;
9032 DECL_CHAIN (f_gpr) = f_fpr;
9033 DECL_CHAIN (f_fpr) = f_res;
9034 DECL_CHAIN (f_res) = f_ovf;
9035 DECL_CHAIN (f_ovf) = f_sav;
9037 layout_type (record);
9039 /* The correct type is an array type of one element. */
9040 return build_array_type (record, build_index_type (size_zero_node));
9043 /* Implement va_start. */
9046 rs6000_va_start (tree valist, rtx nextarg)
9048 HOST_WIDE_INT words, n_gpr, n_fpr;
9049 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9050 tree gpr, fpr, ovf, sav, t;
9052 /* Only SVR4 needs something special. */
9053 if (DEFAULT_ABI != ABI_V4)
9055 std_expand_builtin_va_start (valist, nextarg);
9059 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9060 f_fpr = DECL_CHAIN (f_gpr);
9061 f_res = DECL_CHAIN (f_fpr);
9062 f_ovf = DECL_CHAIN (f_res);
9063 f_sav = DECL_CHAIN (f_ovf);
9065 valist = build_simple_mem_ref (valist);
9066 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9067 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9069 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9071 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9074 /* Count number of gp and fp argument registers used. */
9075 words = crtl->args.info.words;
9076 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
9078 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
9081 if (TARGET_DEBUG_ARG)
9082 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
9083 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
9084 words, n_gpr, n_fpr);
9086 if (cfun->va_list_gpr_size)
9088 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9089 build_int_cst (NULL_TREE, n_gpr));
9090 TREE_SIDE_EFFECTS (t) = 1;
9091 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9094 if (cfun->va_list_fpr_size)
9096 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9097 build_int_cst (NULL_TREE, n_fpr));
9098 TREE_SIDE_EFFECTS (t) = 1;
9099 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9101 #ifdef HAVE_AS_GNU_ATTRIBUTE
9102 if (call_ABI_of_interest (cfun->decl))
9103 rs6000_passes_float = true;
9107 /* Find the overflow area. */
9108 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9110 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
9111 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9112 TREE_SIDE_EFFECTS (t) = 1;
9113 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9115 /* If there were no va_arg invocations, don't set up the register
9117 if (!cfun->va_list_gpr_size
9118 && !cfun->va_list_fpr_size
9119 && n_gpr < GP_ARG_NUM_REG
9120 && n_fpr < FP_ARG_V4_MAX_REG)
9123 /* Find the register save area. */
9124 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
9125 if (cfun->machine->varargs_save_offset)
9126 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
9127 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9128 TREE_SIDE_EFFECTS (t) = 1;
9129 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9132 /* Implement va_arg. */
9135 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9138 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9139 tree gpr, fpr, ovf, sav, reg, t, u;
9140 int size, rsize, n_reg, sav_ofs, sav_scale;
9141 tree lab_false, lab_over, addr;
9143 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
9147 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9149 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
9150 return build_va_arg_indirect_ref (t);
9153 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9154 earlier version of gcc, with the property that it always applied alignment
9155 adjustments to the va-args (even for zero-sized types). The cheapest way
9156 to deal with this is to replicate the effect of the part of
9157 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9159 We don't need to check for pass-by-reference because of the test above.
9160 We can return a simplifed answer, since we know there's no offset to add. */
9163 && rs6000_darwin64_abi
9164 && integer_zerop (TYPE_SIZE (type)))
9166 unsigned HOST_WIDE_INT align, boundary;
9167 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
9168 align = PARM_BOUNDARY / BITS_PER_UNIT;
9169 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
9170 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
9171 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
9172 boundary /= BITS_PER_UNIT;
9173 if (boundary > align)
9176 /* This updates arg ptr by the amount that would be necessary
9177 to align the zero-sized (but not zero-alignment) item. */
9178 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9179 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
9180 gimplify_and_add (t, pre_p);
9182 t = fold_convert (sizetype, valist_tmp);
9183 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9184 fold_convert (TREE_TYPE (valist),
9185 fold_build2 (BIT_AND_EXPR, sizetype, t,
9186 size_int (-boundary))));
9187 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
9188 gimplify_and_add (t, pre_p);
9190 /* Since it is zero-sized there's no increment for the item itself. */
9191 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
9192 return build_va_arg_indirect_ref (valist_tmp);
9195 if (DEFAULT_ABI != ABI_V4)
9197 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
9199 tree elem_type = TREE_TYPE (type);
9200 enum machine_mode elem_mode = TYPE_MODE (elem_type);
9201 int elem_size = GET_MODE_SIZE (elem_mode);
9203 if (elem_size < UNITS_PER_WORD)
9205 tree real_part, imag_part;
9206 gimple_seq post = NULL;
9208 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9210 /* Copy the value into a temporary, lest the formal temporary
9211 be reused out from under us. */
9212 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
9213 gimple_seq_add_seq (pre_p, post);
9215 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9218 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
9222 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
9225 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9226 f_fpr = DECL_CHAIN (f_gpr);
9227 f_res = DECL_CHAIN (f_fpr);
9228 f_ovf = DECL_CHAIN (f_res);
9229 f_sav = DECL_CHAIN (f_ovf);
9231 valist = build_va_arg_indirect_ref (valist);
9232 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9233 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9235 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9237 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9240 size = int_size_in_bytes (type);
9241 rsize = (size + 3) / 4;
9244 if (TARGET_HARD_FLOAT && TARGET_FPRS
9245 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
9246 || (TARGET_DOUBLE_FLOAT
9247 && (TYPE_MODE (type) == DFmode
9248 || TYPE_MODE (type) == TFmode
9249 || TYPE_MODE (type) == SDmode
9250 || TYPE_MODE (type) == DDmode
9251 || TYPE_MODE (type) == TDmode))))
9253 /* FP args go in FP registers, if present. */
9255 n_reg = (size + 7) / 8;
9256 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
9257 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
9258 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
9263 /* Otherwise into GP registers. */
9272 /* Pull the value out of the saved registers.... */
9275 addr = create_tmp_var (ptr_type_node, "addr");
9277 /* AltiVec vectors never go in registers when -mabi=altivec. */
9278 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9282 lab_false = create_artificial_label (input_location);
9283 lab_over = create_artificial_label (input_location);
9285 /* Long long and SPE vectors are aligned in the registers.
9286 As are any other 2 gpr item such as complex int due to a
9287 historical mistake. */
9289 if (n_reg == 2 && reg == gpr)
9292 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9293 build_int_cst (TREE_TYPE (reg), n_reg - 1));
9294 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
9295 unshare_expr (reg), u);
9297 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9298 reg number is 0 for f1, so we want to make it odd. */
9299 else if (reg == fpr && TYPE_MODE (type) == TDmode)
9301 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9302 build_int_cst (TREE_TYPE (reg), 1));
9303 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
9306 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
9307 t = build2 (GE_EXPR, boolean_type_node, u, t);
9308 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9309 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9310 gimplify_and_add (t, pre_p);
9314 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9316 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9317 build_int_cst (TREE_TYPE (reg), n_reg));
9318 u = fold_convert (sizetype, u);
9319 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
9320 t = fold_build_pointer_plus (t, u);
9322 /* _Decimal32 varargs are located in the second word of the 64-bit
9323 FP register for 32-bit binaries. */
9324 if (!TARGET_POWERPC64
9325 && TARGET_HARD_FLOAT && TARGET_FPRS
9326 && TYPE_MODE (type) == SDmode)
9327 t = fold_build_pointer_plus_hwi (t, size);
9329 gimplify_assign (addr, t, pre_p);
9331 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9333 stmt = gimple_build_label (lab_false);
9334 gimple_seq_add_stmt (pre_p, stmt);
9336 if ((n_reg == 2 && !regalign) || n_reg > 2)
9338 /* Ensure that we don't find any more args in regs.
9339 Alignment has taken care of for special cases. */
9340 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
9344 /* ... otherwise out of the overflow area. */
9346 /* Care for on-stack alignment if needed. */
9350 t = fold_build_pointer_plus_hwi (t, align - 1);
9351 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
9352 build_int_cst (TREE_TYPE (t), -align));
9354 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9356 gimplify_assign (unshare_expr (addr), t, pre_p);
9358 t = fold_build_pointer_plus_hwi (t, size);
9359 gimplify_assign (unshare_expr (ovf), t, pre_p);
9363 stmt = gimple_build_label (lab_over);
9364 gimple_seq_add_stmt (pre_p, stmt);
9367 if (STRICT_ALIGNMENT
9368 && (TYPE_ALIGN (type)
9369 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
9371 /* The value (of type complex double, for example) may not be
9372 aligned in memory in the saved registers, so copy via a
9373 temporary. (This is the same code as used for SPARC.) */
9374 tree tmp = create_tmp_var (type, "va_arg_tmp");
9375 tree dest_addr = build_fold_addr_expr (tmp);
9377 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
9378 3, dest_addr, addr, size_int (rsize * 4));
9380 gimplify_and_add (copy, pre_p);
9384 addr = fold_convert (ptrtype, addr);
9385 return build_va_arg_indirect_ref (addr);
9391 def_builtin (const char *name, tree type, enum rs6000_builtins code)
9394 unsigned classify = rs6000_builtin_info[(int)code].attr;
9395 const char *attr_string = "";
9397 gcc_assert (name != NULL);
9398 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
9400 if (rs6000_builtin_decls[(int)code])
9401 fatal_error ("internal error: builtin function %s already processed", name);
9403 rs6000_builtin_decls[(int)code] = t =
9404 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
9406 /* Set any special attributes. */
9407 if ((classify & RS6000_BTC_CONST) != 0)
9409 /* const function, function only depends on the inputs. */
9410 TREE_READONLY (t) = 1;
9411 TREE_NOTHROW (t) = 1;
9412 attr_string = ", pure";
9414 else if ((classify & RS6000_BTC_PURE) != 0)
9416 /* pure function, function can read global memory, but does not set any
9418 DECL_PURE_P (t) = 1;
9419 TREE_NOTHROW (t) = 1;
9420 attr_string = ", const";
9422 else if ((classify & RS6000_BTC_FP) != 0)
9424 /* Function is a math function. If rounding mode is on, then treat the
9425 function as not reading global memory, but it can have arbitrary side
9426 effects. If it is off, then assume the function is a const function.
9427 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9428 builtin-attribute.def that is used for the math functions. */
9429 TREE_NOTHROW (t) = 1;
9430 if (flag_rounding_math)
9432 DECL_PURE_P (t) = 1;
9433 DECL_IS_NOVOPS (t) = 1;
9434 attr_string = ", fp, pure";
9438 TREE_READONLY (t) = 1;
9439 attr_string = ", fp, const";
9442 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
9445 if (TARGET_DEBUG_BUILTIN)
9446 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
9447 (int)code, name, attr_string);
9450 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9452 #undef RS6000_BUILTIN_1
9453 #undef RS6000_BUILTIN_2
9454 #undef RS6000_BUILTIN_3
9455 #undef RS6000_BUILTIN_A
9456 #undef RS6000_BUILTIN_D
9457 #undef RS6000_BUILTIN_E
9458 #undef RS6000_BUILTIN_P
9459 #undef RS6000_BUILTIN_Q
9460 #undef RS6000_BUILTIN_S
9461 #undef RS6000_BUILTIN_X
9463 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9464 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9465 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9466 { MASK, ICODE, NAME, ENUM },
9468 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9469 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9470 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9471 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9472 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9473 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9474 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9476 static const struct builtin_description bdesc_3arg[] =
9478 #include "rs6000-builtin.def"
9481 /* DST operations: void foo (void *, const int, const char). */
9483 #undef RS6000_BUILTIN_1
9484 #undef RS6000_BUILTIN_2
9485 #undef RS6000_BUILTIN_3
9486 #undef RS6000_BUILTIN_A
9487 #undef RS6000_BUILTIN_D
9488 #undef RS6000_BUILTIN_E
9489 #undef RS6000_BUILTIN_P
9490 #undef RS6000_BUILTIN_Q
9491 #undef RS6000_BUILTIN_S
9492 #undef RS6000_BUILTIN_X
9494 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9495 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9496 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9497 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9498 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9499 { MASK, ICODE, NAME, ENUM },
9501 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9502 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9503 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9504 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9505 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9507 static const struct builtin_description bdesc_dst[] =
9509 #include "rs6000-builtin.def"
9512 /* Simple binary operations: VECc = foo (VECa, VECb). */
9514 #undef RS6000_BUILTIN_1
9515 #undef RS6000_BUILTIN_2
9516 #undef RS6000_BUILTIN_3
9517 #undef RS6000_BUILTIN_A
9518 #undef RS6000_BUILTIN_D
9519 #undef RS6000_BUILTIN_E
9520 #undef RS6000_BUILTIN_P
9521 #undef RS6000_BUILTIN_Q
9522 #undef RS6000_BUILTIN_S
9523 #undef RS6000_BUILTIN_X
9525 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9526 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9527 { MASK, ICODE, NAME, ENUM },
9529 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9530 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9531 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9532 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9533 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9534 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9535 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9536 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9538 static const struct builtin_description bdesc_2arg[] =
9540 #include "rs6000-builtin.def"
9543 #undef RS6000_BUILTIN_1
9544 #undef RS6000_BUILTIN_2
9545 #undef RS6000_BUILTIN_3
9546 #undef RS6000_BUILTIN_A
9547 #undef RS6000_BUILTIN_D
9548 #undef RS6000_BUILTIN_E
9549 #undef RS6000_BUILTIN_P
9550 #undef RS6000_BUILTIN_Q
9551 #undef RS6000_BUILTIN_S
9552 #undef RS6000_BUILTIN_X
9554 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9555 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9556 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9557 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9558 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9559 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9560 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9561 { MASK, ICODE, NAME, ENUM },
9563 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9564 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9565 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9567 /* AltiVec predicates. */
9569 static const struct builtin_description bdesc_altivec_preds[] =
9571 #include "rs6000-builtin.def"
9574 /* SPE predicates. */
9575 #undef RS6000_BUILTIN_1
9576 #undef RS6000_BUILTIN_2
9577 #undef RS6000_BUILTIN_3
9578 #undef RS6000_BUILTIN_A
9579 #undef RS6000_BUILTIN_D
9580 #undef RS6000_BUILTIN_E
9581 #undef RS6000_BUILTIN_P
9582 #undef RS6000_BUILTIN_Q
9583 #undef RS6000_BUILTIN_S
9584 #undef RS6000_BUILTIN_X
9586 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9587 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9588 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9589 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9590 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9591 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9592 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9593 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9594 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9595 { MASK, ICODE, NAME, ENUM },
9597 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9599 static const struct builtin_description bdesc_spe_predicates[] =
9601 #include "rs6000-builtin.def"
9604 /* SPE evsel predicates. */
9605 #undef RS6000_BUILTIN_1
9606 #undef RS6000_BUILTIN_2
9607 #undef RS6000_BUILTIN_3
9608 #undef RS6000_BUILTIN_A
9609 #undef RS6000_BUILTIN_D
9610 #undef RS6000_BUILTIN_E
9611 #undef RS6000_BUILTIN_P
9612 #undef RS6000_BUILTIN_Q
9613 #undef RS6000_BUILTIN_S
9614 #undef RS6000_BUILTIN_X
9616 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9617 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9618 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9619 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9620 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9621 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9622 { MASK, ICODE, NAME, ENUM },
9624 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9625 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9626 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9627 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9629 static const struct builtin_description bdesc_spe_evsel[] =
9631 #include "rs6000-builtin.def"
9634 /* PAIRED predicates. */
9635 #undef RS6000_BUILTIN_1
9636 #undef RS6000_BUILTIN_2
9637 #undef RS6000_BUILTIN_3
9638 #undef RS6000_BUILTIN_A
9639 #undef RS6000_BUILTIN_D
9640 #undef RS6000_BUILTIN_E
9641 #undef RS6000_BUILTIN_P
9642 #undef RS6000_BUILTIN_Q
9643 #undef RS6000_BUILTIN_S
9644 #undef RS6000_BUILTIN_X
9646 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9647 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9648 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9649 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9650 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9651 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9652 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9653 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9654 { MASK, ICODE, NAME, ENUM },
9656 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9657 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9659 static const struct builtin_description bdesc_paired_preds[] =
9661 #include "rs6000-builtin.def"
9664 /* ABS* operations. */
9666 #undef RS6000_BUILTIN_1
9667 #undef RS6000_BUILTIN_2
9668 #undef RS6000_BUILTIN_3
9669 #undef RS6000_BUILTIN_A
9670 #undef RS6000_BUILTIN_D
9671 #undef RS6000_BUILTIN_E
9672 #undef RS6000_BUILTIN_P
9673 #undef RS6000_BUILTIN_Q
9674 #undef RS6000_BUILTIN_S
9675 #undef RS6000_BUILTIN_X
9677 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9678 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9679 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9680 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9681 { MASK, ICODE, NAME, ENUM },
9683 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9684 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9685 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9686 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9687 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9688 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9690 static const struct builtin_description bdesc_abs[] =
9692 #include "rs6000-builtin.def"
9695 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9698 #undef RS6000_BUILTIN_1
9699 #undef RS6000_BUILTIN_2
9700 #undef RS6000_BUILTIN_3
9701 #undef RS6000_BUILTIN_A
9702 #undef RS6000_BUILTIN_E
9703 #undef RS6000_BUILTIN_D
9704 #undef RS6000_BUILTIN_P
9705 #undef RS6000_BUILTIN_Q
9706 #undef RS6000_BUILTIN_S
9707 #undef RS6000_BUILTIN_X
9709 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9710 { MASK, ICODE, NAME, ENUM },
9712 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9713 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9714 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9715 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9716 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9717 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9718 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9719 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9720 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9722 static const struct builtin_description bdesc_1arg[] =
9724 #include "rs6000-builtin.def"
9727 #undef RS6000_BUILTIN_1
9728 #undef RS6000_BUILTIN_2
9729 #undef RS6000_BUILTIN_3
9730 #undef RS6000_BUILTIN_A
9731 #undef RS6000_BUILTIN_D
9732 #undef RS6000_BUILTIN_E
9733 #undef RS6000_BUILTIN_P
9734 #undef RS6000_BUILTIN_Q
9735 #undef RS6000_BUILTIN_S
9736 #undef RS6000_BUILTIN_X
9738 /* Return true if a builtin function is overloaded. */
9740 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9742 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9747 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9750 tree arg0 = CALL_EXPR_ARG (exp, 0);
9751 rtx op0 = expand_normal (arg0);
9752 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9753 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9755 if (icode == CODE_FOR_nothing)
9756 /* Builtin not supported on this processor. */
9759 /* If we got invalid arguments bail out before generating bad rtl. */
9760 if (arg0 == error_mark_node)
9763 if (icode == CODE_FOR_altivec_vspltisb
9764 || icode == CODE_FOR_altivec_vspltish
9765 || icode == CODE_FOR_altivec_vspltisw
9766 || icode == CODE_FOR_spe_evsplatfi
9767 || icode == CODE_FOR_spe_evsplati)
9769 /* Only allow 5-bit *signed* literals. */
9770 if (GET_CODE (op0) != CONST_INT
9771 || INTVAL (op0) > 15
9772 || INTVAL (op0) < -16)
9774 error ("argument 1 must be a 5-bit signed literal");
9780 || GET_MODE (target) != tmode
9781 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9782 target = gen_reg_rtx (tmode);
9784 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9785 op0 = copy_to_mode_reg (mode0, op0);
9787 pat = GEN_FCN (icode) (target, op0);
9796 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9798 rtx pat, scratch1, scratch2;
9799 tree arg0 = CALL_EXPR_ARG (exp, 0);
9800 rtx op0 = expand_normal (arg0);
9801 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9802 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9804 /* If we have invalid arguments, bail out before generating bad rtl. */
9805 if (arg0 == error_mark_node)
9809 || GET_MODE (target) != tmode
9810 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9811 target = gen_reg_rtx (tmode);
9813 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9814 op0 = copy_to_mode_reg (mode0, op0);
9816 scratch1 = gen_reg_rtx (mode0);
9817 scratch2 = gen_reg_rtx (mode0);
9819 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9828 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9831 tree arg0 = CALL_EXPR_ARG (exp, 0);
9832 tree arg1 = CALL_EXPR_ARG (exp, 1);
9833 rtx op0 = expand_normal (arg0);
9834 rtx op1 = expand_normal (arg1);
9835 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9836 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9837 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9839 if (icode == CODE_FOR_nothing)
9840 /* Builtin not supported on this processor. */
9843 /* If we got invalid arguments bail out before generating bad rtl. */
9844 if (arg0 == error_mark_node || arg1 == error_mark_node)
9847 if (icode == CODE_FOR_altivec_vcfux
9848 || icode == CODE_FOR_altivec_vcfsx
9849 || icode == CODE_FOR_altivec_vctsxs
9850 || icode == CODE_FOR_altivec_vctuxs
9851 || icode == CODE_FOR_altivec_vspltb
9852 || icode == CODE_FOR_altivec_vsplth
9853 || icode == CODE_FOR_altivec_vspltw
9854 || icode == CODE_FOR_spe_evaddiw
9855 || icode == CODE_FOR_spe_evldd
9856 || icode == CODE_FOR_spe_evldh
9857 || icode == CODE_FOR_spe_evldw
9858 || icode == CODE_FOR_spe_evlhhesplat
9859 || icode == CODE_FOR_spe_evlhhossplat
9860 || icode == CODE_FOR_spe_evlhhousplat
9861 || icode == CODE_FOR_spe_evlwhe
9862 || icode == CODE_FOR_spe_evlwhos
9863 || icode == CODE_FOR_spe_evlwhou
9864 || icode == CODE_FOR_spe_evlwhsplat
9865 || icode == CODE_FOR_spe_evlwwsplat
9866 || icode == CODE_FOR_spe_evrlwi
9867 || icode == CODE_FOR_spe_evslwi
9868 || icode == CODE_FOR_spe_evsrwis
9869 || icode == CODE_FOR_spe_evsubifw
9870 || icode == CODE_FOR_spe_evsrwiu)
9872 /* Only allow 5-bit unsigned literals. */
9874 if (TREE_CODE (arg1) != INTEGER_CST
9875 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9877 error ("argument 2 must be a 5-bit unsigned literal");
9883 || GET_MODE (target) != tmode
9884 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9885 target = gen_reg_rtx (tmode);
9887 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9888 op0 = copy_to_mode_reg (mode0, op0);
9889 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9890 op1 = copy_to_mode_reg (mode1, op1);
9892 pat = GEN_FCN (icode) (target, op0, op1);
9901 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9904 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9905 tree arg0 = CALL_EXPR_ARG (exp, 1);
9906 tree arg1 = CALL_EXPR_ARG (exp, 2);
9907 rtx op0 = expand_normal (arg0);
9908 rtx op1 = expand_normal (arg1);
9909 enum machine_mode tmode = SImode;
9910 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9911 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9914 if (TREE_CODE (cr6_form) != INTEGER_CST)
9916 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9920 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9922 gcc_assert (mode0 == mode1);
9924 /* If we have invalid arguments, bail out before generating bad rtl. */
9925 if (arg0 == error_mark_node || arg1 == error_mark_node)
9929 || GET_MODE (target) != tmode
9930 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9931 target = gen_reg_rtx (tmode);
9933 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9934 op0 = copy_to_mode_reg (mode0, op0);
9935 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9936 op1 = copy_to_mode_reg (mode1, op1);
9938 scratch = gen_reg_rtx (mode0);
9940 pat = GEN_FCN (icode) (scratch, op0, op1);
9945 /* The vec_any* and vec_all* predicates use the same opcodes for two
9946 different operations, but the bits in CR6 will be different
9947 depending on what information we want. So we have to play tricks
9948 with CR6 to get the right bits out.
9950 If you think this is disgusting, look at the specs for the
9951 AltiVec predicates. */
9953 switch (cr6_form_int)
9956 emit_insn (gen_cr6_test_for_zero (target));
9959 emit_insn (gen_cr6_test_for_zero_reverse (target));
9962 emit_insn (gen_cr6_test_for_lt (target));
9965 emit_insn (gen_cr6_test_for_lt_reverse (target));
9968 error ("argument 1 of __builtin_altivec_predicate is out of range");
9976 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
9979 tree arg0 = CALL_EXPR_ARG (exp, 0);
9980 tree arg1 = CALL_EXPR_ARG (exp, 1);
9981 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9982 enum machine_mode mode0 = Pmode;
9983 enum machine_mode mode1 = Pmode;
9984 rtx op0 = expand_normal (arg0);
9985 rtx op1 = expand_normal (arg1);
9987 if (icode == CODE_FOR_nothing)
9988 /* Builtin not supported on this processor. */
9991 /* If we got invalid arguments bail out before generating bad rtl. */
9992 if (arg0 == error_mark_node || arg1 == error_mark_node)
9996 || GET_MODE (target) != tmode
9997 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9998 target = gen_reg_rtx (tmode);
10000 op1 = copy_to_mode_reg (mode1, op1);
10002 if (op0 == const0_rtx)
10004 addr = gen_rtx_MEM (tmode, op1);
10008 op0 = copy_to_mode_reg (mode0, op0);
10009 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
10012 pat = GEN_FCN (icode) (target, addr);
10022 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
10025 tree arg0 = CALL_EXPR_ARG (exp, 0);
10026 tree arg1 = CALL_EXPR_ARG (exp, 1);
10027 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10028 enum machine_mode mode0 = Pmode;
10029 enum machine_mode mode1 = Pmode;
10030 rtx op0 = expand_normal (arg0);
10031 rtx op1 = expand_normal (arg1);
10033 if (icode == CODE_FOR_nothing)
10034 /* Builtin not supported on this processor. */
10037 /* If we got invalid arguments bail out before generating bad rtl. */
10038 if (arg0 == error_mark_node || arg1 == error_mark_node)
10042 || GET_MODE (target) != tmode
10043 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10044 target = gen_reg_rtx (tmode);
10046 op1 = copy_to_mode_reg (mode1, op1);
10048 if (op0 == const0_rtx)
10050 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
10054 op0 = copy_to_mode_reg (mode0, op0);
10055 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
10058 pat = GEN_FCN (icode) (target, addr);
10068 spe_expand_stv_builtin (enum insn_code icode, tree exp)
10070 tree arg0 = CALL_EXPR_ARG (exp, 0);
10071 tree arg1 = CALL_EXPR_ARG (exp, 1);
10072 tree arg2 = CALL_EXPR_ARG (exp, 2);
10073 rtx op0 = expand_normal (arg0);
10074 rtx op1 = expand_normal (arg1);
10075 rtx op2 = expand_normal (arg2);
10077 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10078 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
10079 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
10081 /* Invalid arguments. Bail before doing anything stoopid! */
10082 if (arg0 == error_mark_node
10083 || arg1 == error_mark_node
10084 || arg2 == error_mark_node)
10087 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
10088 op0 = copy_to_mode_reg (mode2, op0);
10089 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
10090 op1 = copy_to_mode_reg (mode0, op1);
10091 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
10092 op2 = copy_to_mode_reg (mode1, op2);
10094 pat = GEN_FCN (icode) (op1, op2, op0);
10101 paired_expand_stv_builtin (enum insn_code icode, tree exp)
10103 tree arg0 = CALL_EXPR_ARG (exp, 0);
10104 tree arg1 = CALL_EXPR_ARG (exp, 1);
10105 tree arg2 = CALL_EXPR_ARG (exp, 2);
10106 rtx op0 = expand_normal (arg0);
10107 rtx op1 = expand_normal (arg1);
10108 rtx op2 = expand_normal (arg2);
10110 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10111 enum machine_mode mode1 = Pmode;
10112 enum machine_mode mode2 = Pmode;
10114 /* Invalid arguments. Bail before doing anything stoopid! */
10115 if (arg0 == error_mark_node
10116 || arg1 == error_mark_node
10117 || arg2 == error_mark_node)
10120 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
10121 op0 = copy_to_mode_reg (tmode, op0);
10123 op2 = copy_to_mode_reg (mode2, op2);
10125 if (op1 == const0_rtx)
10127 addr = gen_rtx_MEM (tmode, op2);
10131 op1 = copy_to_mode_reg (mode1, op1);
10132 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10135 pat = GEN_FCN (icode) (addr, op0);
10142 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10144 tree arg0 = CALL_EXPR_ARG (exp, 0);
10145 tree arg1 = CALL_EXPR_ARG (exp, 1);
10146 tree arg2 = CALL_EXPR_ARG (exp, 2);
10147 rtx op0 = expand_normal (arg0);
10148 rtx op1 = expand_normal (arg1);
10149 rtx op2 = expand_normal (arg2);
10151 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10152 enum machine_mode smode = insn_data[icode].operand[1].mode;
10153 enum machine_mode mode1 = Pmode;
10154 enum machine_mode mode2 = Pmode;
10156 /* Invalid arguments. Bail before doing anything stoopid! */
10157 if (arg0 == error_mark_node
10158 || arg1 == error_mark_node
10159 || arg2 == error_mark_node)
10162 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10163 op0 = copy_to_mode_reg (smode, op0);
10165 op2 = copy_to_mode_reg (mode2, op2);
10167 if (op1 == const0_rtx)
10169 addr = gen_rtx_MEM (tmode, op2);
10173 op1 = copy_to_mode_reg (mode1, op1);
10174 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10177 pat = GEN_FCN (icode) (addr, op0);
10184 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10187 tree arg0 = CALL_EXPR_ARG (exp, 0);
10188 tree arg1 = CALL_EXPR_ARG (exp, 1);
10189 tree arg2 = CALL_EXPR_ARG (exp, 2);
10190 rtx op0 = expand_normal (arg0);
10191 rtx op1 = expand_normal (arg1);
10192 rtx op2 = expand_normal (arg2);
10193 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10194 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10195 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10196 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
10198 if (icode == CODE_FOR_nothing)
10199 /* Builtin not supported on this processor. */
10202 /* If we got invalid arguments bail out before generating bad rtl. */
10203 if (arg0 == error_mark_node
10204 || arg1 == error_mark_node
10205 || arg2 == error_mark_node)
10208 /* Check and prepare argument depending on the instruction code.
10210 Note that a switch statement instead of the sequence of tests
10211 would be incorrect as many of the CODE_FOR values could be
10212 CODE_FOR_nothing and that would yield multiple alternatives
10213 with identical values. We'd never reach here at runtime in
10215 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10216 || icode == CODE_FOR_altivec_vsldoi_v4si
10217 || icode == CODE_FOR_altivec_vsldoi_v8hi
10218 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10220 /* Only allow 4-bit unsigned literals. */
10222 if (TREE_CODE (arg2) != INTEGER_CST
10223 || TREE_INT_CST_LOW (arg2) & ~0xf)
10225 error ("argument 3 must be a 4-bit unsigned literal");
10229 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10230 || icode == CODE_FOR_vsx_xxpermdi_v2di
10231 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10232 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10233 || icode == CODE_FOR_vsx_xxsldwi_v4si
10234 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10235 || icode == CODE_FOR_vsx_xxsldwi_v2di
10236 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10238 /* Only allow 2-bit unsigned literals. */
10240 if (TREE_CODE (arg2) != INTEGER_CST
10241 || TREE_INT_CST_LOW (arg2) & ~0x3)
10243 error ("argument 3 must be a 2-bit unsigned literal");
10247 else if (icode == CODE_FOR_vsx_set_v2df
10248 || icode == CODE_FOR_vsx_set_v2di)
10250 /* Only allow 1-bit unsigned literals. */
10252 if (TREE_CODE (arg2) != INTEGER_CST
10253 || TREE_INT_CST_LOW (arg2) & ~0x1)
10255 error ("argument 3 must be a 1-bit unsigned literal");
10261 || GET_MODE (target) != tmode
10262 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10263 target = gen_reg_rtx (tmode);
10265 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10266 op0 = copy_to_mode_reg (mode0, op0);
10267 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10268 op1 = copy_to_mode_reg (mode1, op1);
10269 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10270 op2 = copy_to_mode_reg (mode2, op2);
10272 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
10273 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
10275 pat = GEN_FCN (icode) (target, op0, op1, op2);
10283 /* Expand the lvx builtins. */
10285 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
10287 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10288 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10290 enum machine_mode tmode, mode0;
10292 enum insn_code icode;
10296 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10297 icode = CODE_FOR_vector_altivec_load_v16qi;
10299 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10300 icode = CODE_FOR_vector_altivec_load_v8hi;
10302 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10303 icode = CODE_FOR_vector_altivec_load_v4si;
10305 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10306 icode = CODE_FOR_vector_altivec_load_v4sf;
10308 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10309 icode = CODE_FOR_vector_altivec_load_v2df;
10311 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10312 icode = CODE_FOR_vector_altivec_load_v2di;
10315 *expandedp = false;
10321 arg0 = CALL_EXPR_ARG (exp, 0);
10322 op0 = expand_normal (arg0);
10323 tmode = insn_data[icode].operand[0].mode;
10324 mode0 = insn_data[icode].operand[1].mode;
10327 || GET_MODE (target) != tmode
10328 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10329 target = gen_reg_rtx (tmode);
10331 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10332 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10334 pat = GEN_FCN (icode) (target, op0);
10341 /* Expand the stvx builtins. */
10343 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10346 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10347 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10349 enum machine_mode mode0, mode1;
10351 enum insn_code icode;
10355 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10356 icode = CODE_FOR_vector_altivec_store_v16qi;
10358 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10359 icode = CODE_FOR_vector_altivec_store_v8hi;
10361 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10362 icode = CODE_FOR_vector_altivec_store_v4si;
10364 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10365 icode = CODE_FOR_vector_altivec_store_v4sf;
10367 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10368 icode = CODE_FOR_vector_altivec_store_v2df;
10370 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10371 icode = CODE_FOR_vector_altivec_store_v2di;
10374 *expandedp = false;
10378 arg0 = CALL_EXPR_ARG (exp, 0);
10379 arg1 = CALL_EXPR_ARG (exp, 1);
10380 op0 = expand_normal (arg0);
10381 op1 = expand_normal (arg1);
10382 mode0 = insn_data[icode].operand[0].mode;
10383 mode1 = insn_data[icode].operand[1].mode;
10385 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10386 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10387 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
10388 op1 = copy_to_mode_reg (mode1, op1);
10390 pat = GEN_FCN (icode) (op0, op1);
10398 /* Expand the dst builtins. */
10400 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10403 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10404 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10405 tree arg0, arg1, arg2;
10406 enum machine_mode mode0, mode1;
10407 rtx pat, op0, op1, op2;
10408 const struct builtin_description *d;
10411 *expandedp = false;
10413 /* Handle DST variants. */
10415 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10416 if (d->code == fcode)
10418 arg0 = CALL_EXPR_ARG (exp, 0);
10419 arg1 = CALL_EXPR_ARG (exp, 1);
10420 arg2 = CALL_EXPR_ARG (exp, 2);
10421 op0 = expand_normal (arg0);
10422 op1 = expand_normal (arg1);
10423 op2 = expand_normal (arg2);
10424 mode0 = insn_data[d->icode].operand[0].mode;
10425 mode1 = insn_data[d->icode].operand[1].mode;
10427 /* Invalid arguments, bail out before generating bad rtl. */
10428 if (arg0 == error_mark_node
10429 || arg1 == error_mark_node
10430 || arg2 == error_mark_node)
10435 if (TREE_CODE (arg2) != INTEGER_CST
10436 || TREE_INT_CST_LOW (arg2) & ~0x3)
10438 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10442 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10443 op0 = copy_to_mode_reg (Pmode, op0);
10444 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10445 op1 = copy_to_mode_reg (mode1, op1);
10447 pat = GEN_FCN (d->icode) (op0, op1, op2);
10457 /* Expand vec_init builtin. */
10459 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10461 enum machine_mode tmode = TYPE_MODE (type);
10462 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
10463 int i, n_elt = GET_MODE_NUNITS (tmode);
10464 rtvec v = rtvec_alloc (n_elt);
10466 gcc_assert (VECTOR_MODE_P (tmode));
10467 gcc_assert (n_elt == call_expr_nargs (exp));
10469 for (i = 0; i < n_elt; ++i)
10471 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10472 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10475 if (!target || !register_operand (target, tmode))
10476 target = gen_reg_rtx (tmode);
10478 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10482 /* Return the integer constant in ARG. Constrain it to be in the range
10483 of the subparts of VEC_TYPE; issue an error if not. */
10486 get_element_number (tree vec_type, tree arg)
10488 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10490 if (!host_integerp (arg, 1)
10491 || (elt = tree_low_cst (arg, 1), elt > max))
10493 error ("selector must be an integer constant in the range 0..%wi", max);
10500 /* Expand vec_set builtin. */
10502 altivec_expand_vec_set_builtin (tree exp)
10504 enum machine_mode tmode, mode1;
10505 tree arg0, arg1, arg2;
10509 arg0 = CALL_EXPR_ARG (exp, 0);
10510 arg1 = CALL_EXPR_ARG (exp, 1);
10511 arg2 = CALL_EXPR_ARG (exp, 2);
10513 tmode = TYPE_MODE (TREE_TYPE (arg0));
10514 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10515 gcc_assert (VECTOR_MODE_P (tmode));
10517 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10518 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10519 elt = get_element_number (TREE_TYPE (arg0), arg2);
10521 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10522 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10524 op0 = force_reg (tmode, op0);
10525 op1 = force_reg (mode1, op1);
10527 rs6000_expand_vector_set (op0, op1, elt);
10532 /* Expand vec_ext builtin. */
10534 altivec_expand_vec_ext_builtin (tree exp, rtx target)
10536 enum machine_mode tmode, mode0;
10541 arg0 = CALL_EXPR_ARG (exp, 0);
10542 arg1 = CALL_EXPR_ARG (exp, 1);
10544 op0 = expand_normal (arg0);
10545 elt = get_element_number (TREE_TYPE (arg0), arg1);
10547 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10548 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10549 gcc_assert (VECTOR_MODE_P (mode0));
10551 op0 = force_reg (mode0, op0);
10553 if (optimize || !target || !register_operand (target, tmode))
10554 target = gen_reg_rtx (tmode);
10556 rs6000_expand_vector_extract (target, op0, elt);
10561 /* Expand the builtin in EXP and store the result in TARGET. Store
10562 true in *EXPANDEDP if we found a builtin to expand. */
10564 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10566 const struct builtin_description *d;
10568 enum insn_code icode;
10569 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10572 enum machine_mode tmode, mode0;
10573 enum rs6000_builtins fcode
10574 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10576 if (rs6000_overloaded_builtin_p (fcode))
10579 error ("unresolved overload for Altivec builtin %qF", fndecl);
10583 target = altivec_expand_ld_builtin (exp, target, expandedp);
10587 target = altivec_expand_st_builtin (exp, target, expandedp);
10591 target = altivec_expand_dst_builtin (exp, target, expandedp);
10599 case ALTIVEC_BUILTIN_STVX:
10600 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10601 case ALTIVEC_BUILTIN_STVEBX:
10602 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10603 case ALTIVEC_BUILTIN_STVEHX:
10604 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10605 case ALTIVEC_BUILTIN_STVEWX:
10606 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10607 case ALTIVEC_BUILTIN_STVXL:
10608 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
10610 case ALTIVEC_BUILTIN_STVLX:
10611 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10612 case ALTIVEC_BUILTIN_STVLXL:
10613 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10614 case ALTIVEC_BUILTIN_STVRX:
10615 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10616 case ALTIVEC_BUILTIN_STVRXL:
10617 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10619 case VSX_BUILTIN_STXVD2X_V2DF:
10620 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10621 case VSX_BUILTIN_STXVD2X_V2DI:
10622 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10623 case VSX_BUILTIN_STXVW4X_V4SF:
10624 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10625 case VSX_BUILTIN_STXVW4X_V4SI:
10626 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10627 case VSX_BUILTIN_STXVW4X_V8HI:
10628 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10629 case VSX_BUILTIN_STXVW4X_V16QI:
10630 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10632 case ALTIVEC_BUILTIN_MFVSCR:
10633 icode = CODE_FOR_altivec_mfvscr;
10634 tmode = insn_data[icode].operand[0].mode;
10637 || GET_MODE (target) != tmode
10638 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10639 target = gen_reg_rtx (tmode);
10641 pat = GEN_FCN (icode) (target);
10647 case ALTIVEC_BUILTIN_MTVSCR:
10648 icode = CODE_FOR_altivec_mtvscr;
10649 arg0 = CALL_EXPR_ARG (exp, 0);
10650 op0 = expand_normal (arg0);
10651 mode0 = insn_data[icode].operand[0].mode;
10653 /* If we got invalid arguments bail out before generating bad rtl. */
10654 if (arg0 == error_mark_node)
10657 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10658 op0 = copy_to_mode_reg (mode0, op0);
10660 pat = GEN_FCN (icode) (op0);
10665 case ALTIVEC_BUILTIN_DSSALL:
10666 emit_insn (gen_altivec_dssall ());
10669 case ALTIVEC_BUILTIN_DSS:
10670 icode = CODE_FOR_altivec_dss;
10671 arg0 = CALL_EXPR_ARG (exp, 0);
10673 op0 = expand_normal (arg0);
10674 mode0 = insn_data[icode].operand[0].mode;
10676 /* If we got invalid arguments bail out before generating bad rtl. */
10677 if (arg0 == error_mark_node)
10680 if (TREE_CODE (arg0) != INTEGER_CST
10681 || TREE_INT_CST_LOW (arg0) & ~0x3)
10683 error ("argument to dss must be a 2-bit unsigned literal");
10687 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10688 op0 = copy_to_mode_reg (mode0, op0);
10690 emit_insn (gen_altivec_dss (op0));
10693 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10694 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10695 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10696 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10697 case VSX_BUILTIN_VEC_INIT_V2DF:
10698 case VSX_BUILTIN_VEC_INIT_V2DI:
10699 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10701 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10702 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10703 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10704 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10705 case VSX_BUILTIN_VEC_SET_V2DF:
10706 case VSX_BUILTIN_VEC_SET_V2DI:
10707 return altivec_expand_vec_set_builtin (exp);
10709 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10710 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10711 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10712 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10713 case VSX_BUILTIN_VEC_EXT_V2DF:
10714 case VSX_BUILTIN_VEC_EXT_V2DI:
10715 return altivec_expand_vec_ext_builtin (exp, target);
10719 /* Fall through. */
10722 /* Expand abs* operations. */
10724 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10725 if (d->code == fcode)
10726 return altivec_expand_abs_builtin (d->icode, exp, target);
10728 /* Expand the AltiVec predicates. */
10729 d = bdesc_altivec_preds;
10730 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10731 if (d->code == fcode)
10732 return altivec_expand_predicate_builtin (d->icode, exp, target);
10734 /* LV* are funky. We initialized them differently. */
10737 case ALTIVEC_BUILTIN_LVSL:
10738 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10739 exp, target, false);
10740 case ALTIVEC_BUILTIN_LVSR:
10741 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10742 exp, target, false);
10743 case ALTIVEC_BUILTIN_LVEBX:
10744 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10745 exp, target, false);
10746 case ALTIVEC_BUILTIN_LVEHX:
10747 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10748 exp, target, false);
10749 case ALTIVEC_BUILTIN_LVEWX:
10750 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10751 exp, target, false);
10752 case ALTIVEC_BUILTIN_LVXL:
10753 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10754 exp, target, false);
10755 case ALTIVEC_BUILTIN_LVX:
10756 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10757 exp, target, false);
10758 case ALTIVEC_BUILTIN_LVLX:
10759 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10760 exp, target, true);
10761 case ALTIVEC_BUILTIN_LVLXL:
10762 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10763 exp, target, true);
10764 case ALTIVEC_BUILTIN_LVRX:
10765 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10766 exp, target, true);
10767 case ALTIVEC_BUILTIN_LVRXL:
10768 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10769 exp, target, true);
10770 case VSX_BUILTIN_LXVD2X_V2DF:
10771 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10772 exp, target, false);
10773 case VSX_BUILTIN_LXVD2X_V2DI:
10774 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10775 exp, target, false);
10776 case VSX_BUILTIN_LXVW4X_V4SF:
10777 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10778 exp, target, false);
10779 case VSX_BUILTIN_LXVW4X_V4SI:
10780 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10781 exp, target, false);
10782 case VSX_BUILTIN_LXVW4X_V8HI:
10783 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10784 exp, target, false);
10785 case VSX_BUILTIN_LXVW4X_V16QI:
10786 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10787 exp, target, false);
10791 /* Fall through. */
10794 *expandedp = false;
10798 /* Expand the builtin in EXP and store the result in TARGET. Store
10799 true in *EXPANDEDP if we found a builtin to expand. */
10801 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
10803 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10804 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10805 const struct builtin_description *d;
10812 case PAIRED_BUILTIN_STX:
10813 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
10814 case PAIRED_BUILTIN_LX:
10815 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
10818 /* Fall through. */
10821 /* Expand the paired predicates. */
10822 d = bdesc_paired_preds;
10823 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
10824 if (d->code == fcode)
10825 return paired_expand_predicate_builtin (d->icode, exp, target);
10827 *expandedp = false;
10831 /* Binops that need to be initialized manually, but can be expanded
10832 automagically by rs6000_expand_binop_builtin. */
10833 static const struct builtin_description bdesc_2arg_spe[] =
10835 { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
10836 { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
10837 { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
10838 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
10839 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
10840 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
10841 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
10842 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
10843 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
10844 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
10845 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
10846 { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
10847 { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
10848 { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
10849 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
10850 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
10851 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
10852 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
10853 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
10854 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
10855 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
10856 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
10859 /* Expand the builtin in EXP and store the result in TARGET. Store
10860 true in *EXPANDEDP if we found a builtin to expand.
10862 This expands the SPE builtins that are not simple unary and binary
10865 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
10867 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10869 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10870 enum insn_code icode;
10871 enum machine_mode tmode, mode0;
10873 const struct builtin_description *d;
10878 /* Syntax check for a 5-bit unsigned immediate. */
10881 case SPE_BUILTIN_EVSTDD:
10882 case SPE_BUILTIN_EVSTDH:
10883 case SPE_BUILTIN_EVSTDW:
10884 case SPE_BUILTIN_EVSTWHE:
10885 case SPE_BUILTIN_EVSTWHO:
10886 case SPE_BUILTIN_EVSTWWE:
10887 case SPE_BUILTIN_EVSTWWO:
10888 arg1 = CALL_EXPR_ARG (exp, 2);
10889 if (TREE_CODE (arg1) != INTEGER_CST
10890 || TREE_INT_CST_LOW (arg1) & ~0x1f)
10892 error ("argument 2 must be a 5-bit unsigned literal");
10900 /* The evsplat*i instructions are not quite generic. */
10903 case SPE_BUILTIN_EVSPLATFI:
10904 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
10906 case SPE_BUILTIN_EVSPLATI:
10907 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
10913 d = bdesc_2arg_spe;
10914 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
10915 if (d->code == fcode)
10916 return rs6000_expand_binop_builtin (d->icode, exp, target);
10918 d = bdesc_spe_predicates;
10919 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
10920 if (d->code == fcode)
10921 return spe_expand_predicate_builtin (d->icode, exp, target);
10923 d = bdesc_spe_evsel;
10924 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
10925 if (d->code == fcode)
10926 return spe_expand_evsel_builtin (d->icode, exp, target);
10930 case SPE_BUILTIN_EVSTDDX:
10931 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
10932 case SPE_BUILTIN_EVSTDHX:
10933 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
10934 case SPE_BUILTIN_EVSTDWX:
10935 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
10936 case SPE_BUILTIN_EVSTWHEX:
10937 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
10938 case SPE_BUILTIN_EVSTWHOX:
10939 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
10940 case SPE_BUILTIN_EVSTWWEX:
10941 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
10942 case SPE_BUILTIN_EVSTWWOX:
10943 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
10944 case SPE_BUILTIN_EVSTDD:
10945 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
10946 case SPE_BUILTIN_EVSTDH:
10947 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
10948 case SPE_BUILTIN_EVSTDW:
10949 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
10950 case SPE_BUILTIN_EVSTWHE:
10951 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
10952 case SPE_BUILTIN_EVSTWHO:
10953 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
10954 case SPE_BUILTIN_EVSTWWE:
10955 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
10956 case SPE_BUILTIN_EVSTWWO:
10957 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
10958 case SPE_BUILTIN_MFSPEFSCR:
10959 icode = CODE_FOR_spe_mfspefscr;
10960 tmode = insn_data[icode].operand[0].mode;
10963 || GET_MODE (target) != tmode
10964 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10965 target = gen_reg_rtx (tmode);
10967 pat = GEN_FCN (icode) (target);
10972 case SPE_BUILTIN_MTSPEFSCR:
10973 icode = CODE_FOR_spe_mtspefscr;
10974 arg0 = CALL_EXPR_ARG (exp, 0);
10975 op0 = expand_normal (arg0);
10976 mode0 = insn_data[icode].operand[0].mode;
10978 if (arg0 == error_mark_node)
10981 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10982 op0 = copy_to_mode_reg (mode0, op0);
10984 pat = GEN_FCN (icode) (op0);
10992 *expandedp = false;
10997 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
10999 rtx pat, scratch, tmp;
11000 tree form = CALL_EXPR_ARG (exp, 0);
11001 tree arg0 = CALL_EXPR_ARG (exp, 1);
11002 tree arg1 = CALL_EXPR_ARG (exp, 2);
11003 rtx op0 = expand_normal (arg0);
11004 rtx op1 = expand_normal (arg1);
11005 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11006 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11008 enum rtx_code code;
11010 if (TREE_CODE (form) != INTEGER_CST)
11012 error ("argument 1 of __builtin_paired_predicate must be a constant");
11016 form_int = TREE_INT_CST_LOW (form);
11018 gcc_assert (mode0 == mode1);
11020 if (arg0 == error_mark_node || arg1 == error_mark_node)
11024 || GET_MODE (target) != SImode
11025 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
11026 target = gen_reg_rtx (SImode);
11027 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
11028 op0 = copy_to_mode_reg (mode0, op0);
11029 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
11030 op1 = copy_to_mode_reg (mode1, op1);
11032 scratch = gen_reg_rtx (CCFPmode);
11034 pat = GEN_FCN (icode) (scratch, op0, op1);
11056 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11059 error ("argument 1 of __builtin_paired_predicate is out of range");
11063 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11064 emit_move_insn (target, tmp);
11069 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11071 rtx pat, scratch, tmp;
11072 tree form = CALL_EXPR_ARG (exp, 0);
11073 tree arg0 = CALL_EXPR_ARG (exp, 1);
11074 tree arg1 = CALL_EXPR_ARG (exp, 2);
11075 rtx op0 = expand_normal (arg0);
11076 rtx op1 = expand_normal (arg1);
11077 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11078 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11080 enum rtx_code code;
11082 if (TREE_CODE (form) != INTEGER_CST)
11084 error ("argument 1 of __builtin_spe_predicate must be a constant");
11088 form_int = TREE_INT_CST_LOW (form);
11090 gcc_assert (mode0 == mode1);
11092 if (arg0 == error_mark_node || arg1 == error_mark_node)
11096 || GET_MODE (target) != SImode
11097 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
11098 target = gen_reg_rtx (SImode);
11100 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11101 op0 = copy_to_mode_reg (mode0, op0);
11102 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11103 op1 = copy_to_mode_reg (mode1, op1);
11105 scratch = gen_reg_rtx (CCmode);
11107 pat = GEN_FCN (icode) (scratch, op0, op1);
11112 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11113 _lower_. We use one compare, but look in different bits of the
11114 CR for each variant.
11116 There are 2 elements in each SPE simd type (upper/lower). The CR
11117 bits are set as follows:
11119 BIT0 | BIT 1 | BIT 2 | BIT 3
11120 U | L | (U | L) | (U & L)
11122 So, for an "all" relationship, BIT 3 would be set.
11123 For an "any" relationship, BIT 2 would be set. Etc.
11125 Following traditional nomenclature, these bits map to:
11127 BIT0 | BIT 1 | BIT 2 | BIT 3
11130 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11135 /* All variant. OV bit. */
11137 /* We need to get to the OV bit, which is the ORDERED bit. We
11138 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11139 that's ugly and will make validate_condition_mode die.
11140 So let's just use another pattern. */
11141 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11143 /* Any variant. EQ bit. */
11147 /* Upper variant. LT bit. */
11151 /* Lower variant. GT bit. */
11156 error ("argument 1 of __builtin_spe_predicate is out of range");
11160 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11161 emit_move_insn (target, tmp);
11166 /* The evsel builtins look like this:
11168 e = __builtin_spe_evsel_OP (a, b, c, d);
11170 and work like this:
11172 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11173 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11177 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
11180 tree arg0 = CALL_EXPR_ARG (exp, 0);
11181 tree arg1 = CALL_EXPR_ARG (exp, 1);
11182 tree arg2 = CALL_EXPR_ARG (exp, 2);
11183 tree arg3 = CALL_EXPR_ARG (exp, 3);
11184 rtx op0 = expand_normal (arg0);
11185 rtx op1 = expand_normal (arg1);
11186 rtx op2 = expand_normal (arg2);
11187 rtx op3 = expand_normal (arg3);
11188 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11189 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11191 gcc_assert (mode0 == mode1);
11193 if (arg0 == error_mark_node || arg1 == error_mark_node
11194 || arg2 == error_mark_node || arg3 == error_mark_node)
11198 || GET_MODE (target) != mode0
11199 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
11200 target = gen_reg_rtx (mode0);
11202 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11203 op0 = copy_to_mode_reg (mode0, op0);
11204 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11205 op1 = copy_to_mode_reg (mode0, op1);
11206 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
11207 op2 = copy_to_mode_reg (mode0, op2);
11208 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
11209 op3 = copy_to_mode_reg (mode0, op3);
11211 /* Generate the compare. */
11212 scratch = gen_reg_rtx (CCmode);
11213 pat = GEN_FCN (icode) (scratch, op0, op1);
11218 if (mode0 == V2SImode)
11219 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
11221 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
11226 /* Raise an error message for a builtin function that is called without the
11227 appropriate target options being set. */
11230 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11232 size_t uns_fncode = (size_t)fncode;
11233 const char *name = rs6000_builtin_info[uns_fncode].name;
11234 unsigned fnmask = rs6000_builtin_info[uns_fncode].mask;
11236 gcc_assert (name != NULL);
11237 if ((fnmask & RS6000_BTM_CELL) != 0)
11238 error ("Builtin function %s is only valid for the cell processor", name);
11239 else if ((fnmask & RS6000_BTM_VSX) != 0)
11240 error ("Builtin function %s requires the -mvsx option", name);
11241 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11242 error ("Builtin function %s requires the -maltivec option", name);
11243 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
11244 error ("Builtin function %s requires the -mpaired option", name);
11245 else if ((fnmask & RS6000_BTM_SPE) != 0)
11246 error ("Builtin function %s requires the -mspe option", name);
11248 error ("Builtin function %s is not supported with the current options",
11252 /* Expand an expression EXP that calls a built-in function,
11253 with result going to TARGET if that's convenient
11254 (and in mode MODE if that's convenient).
11255 SUBTARGET may be used as the target for computing one of EXP's operands.
11256 IGNORE is nonzero if the value is to be ignored. */
11259 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11260 enum machine_mode mode ATTRIBUTE_UNUSED,
11261 int ignore ATTRIBUTE_UNUSED)
11263 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11264 enum rs6000_builtins fcode
11265 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
11266 size_t uns_fcode = (size_t)fcode;
11267 const struct builtin_description *d;
11271 unsigned mask = rs6000_builtin_info[uns_fcode].mask;
11272 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11274 if (TARGET_DEBUG_BUILTIN)
11276 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11277 const char *name1 = rs6000_builtin_info[uns_fcode].name;
11278 const char *name2 = ((icode != CODE_FOR_nothing)
11279 ? get_insn_name ((int)icode)
11283 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11285 default: name3 = "unknown"; break;
11286 case RS6000_BTC_SPECIAL: name3 = "special"; break;
11287 case RS6000_BTC_UNARY: name3 = "unary"; break;
11288 case RS6000_BTC_BINARY: name3 = "binary"; break;
11289 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
11290 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
11291 case RS6000_BTC_ABS: name3 = "abs"; break;
11292 case RS6000_BTC_EVSEL: name3 = "evsel"; break;
11293 case RS6000_BTC_DST: name3 = "dst"; break;
11298 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11299 (name1) ? name1 : "---", fcode,
11300 (name2) ? name2 : "---", (int)icode,
11302 func_valid_p ? "" : ", not valid");
11307 rs6000_invalid_builtin (fcode);
11313 case RS6000_BUILTIN_RECIP:
11314 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11316 case RS6000_BUILTIN_RECIPF:
11317 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11319 case RS6000_BUILTIN_RSQRTF:
11320 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11322 case RS6000_BUILTIN_RSQRT:
11323 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11325 case RS6000_BUILTIN_BSWAP_HI:
11326 return rs6000_expand_unop_builtin (CODE_FOR_bswaphi2, exp, target);
11328 case POWER7_BUILTIN_BPERMD:
11329 return rs6000_expand_binop_builtin (((TARGET_64BIT)
11330 ? CODE_FOR_bpermd_di
11331 : CODE_FOR_bpermd_si), exp, target);
11333 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11334 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11336 int icode = (int) CODE_FOR_altivec_lvsr;
11337 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11338 enum machine_mode mode = insn_data[icode].operand[1].mode;
11342 gcc_assert (TARGET_ALTIVEC);
11344 arg = CALL_EXPR_ARG (exp, 0);
11345 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11346 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11347 addr = memory_address (mode, op);
11348 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11352 /* For the load case need to negate the address. */
11353 op = gen_reg_rtx (GET_MODE (addr));
11354 emit_insn (gen_rtx_SET (VOIDmode, op,
11355 gen_rtx_NEG (GET_MODE (addr), addr)));
11357 op = gen_rtx_MEM (mode, op);
11360 || GET_MODE (target) != tmode
11361 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11362 target = gen_reg_rtx (tmode);
11364 /*pat = gen_altivec_lvsr (target, op);*/
11365 pat = GEN_FCN (icode) (target, op);
11373 case ALTIVEC_BUILTIN_VCFUX:
11374 case ALTIVEC_BUILTIN_VCFSX:
11375 case ALTIVEC_BUILTIN_VCTUXS:
11376 case ALTIVEC_BUILTIN_VCTSXS:
11377 /* FIXME: There's got to be a nicer way to handle this case than
11378 constructing a new CALL_EXPR. */
11379 if (call_expr_nargs (exp) == 1)
11381 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11382 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11390 if (TARGET_ALTIVEC)
11392 ret = altivec_expand_builtin (exp, target, &success);
11399 ret = spe_expand_builtin (exp, target, &success);
11404 if (TARGET_PAIRED_FLOAT)
11406 ret = paired_expand_builtin (exp, target, &success);
11412 gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
11414 /* Handle simple unary operations. */
11416 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11417 if (d->code == fcode)
11418 return rs6000_expand_unop_builtin (d->icode, exp, target);
11420 /* Handle simple binary operations. */
11422 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11423 if (d->code == fcode)
11424 return rs6000_expand_binop_builtin (d->icode, exp, target);
11426 /* Handle simple ternary operations. */
11428 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
11429 if (d->code == fcode)
11430 return rs6000_expand_ternop_builtin (d->icode, exp, target);
11432 gcc_unreachable ();
11436 rs6000_init_builtins (void)
11440 enum machine_mode mode;
11442 if (TARGET_DEBUG_BUILTIN)
11443 fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
11444 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
11445 (TARGET_SPE) ? ", spe" : "",
11446 (TARGET_ALTIVEC) ? ", altivec" : "",
11447 (TARGET_VSX) ? ", vsx" : "");
11449 V2SI_type_node = build_vector_type (intSI_type_node, 2);
11450 V2SF_type_node = build_vector_type (float_type_node, 2);
11451 V2DI_type_node = build_vector_type (intDI_type_node, 2);
11452 V2DF_type_node = build_vector_type (double_type_node, 2);
11453 V4HI_type_node = build_vector_type (intHI_type_node, 4);
11454 V4SI_type_node = build_vector_type (intSI_type_node, 4);
11455 V4SF_type_node = build_vector_type (float_type_node, 4);
11456 V8HI_type_node = build_vector_type (intHI_type_node, 8);
11457 V16QI_type_node = build_vector_type (intQI_type_node, 16);
11459 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
11460 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
11461 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
11462 unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
11464 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
11465 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
11466 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
11467 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11469 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11470 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11471 'vector unsigned short'. */
11473 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11474 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11475 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11476 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11477 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11479 long_integer_type_internal_node = long_integer_type_node;
11480 long_unsigned_type_internal_node = long_unsigned_type_node;
11481 long_long_integer_type_internal_node = long_long_integer_type_node;
11482 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11483 intQI_type_internal_node = intQI_type_node;
11484 uintQI_type_internal_node = unsigned_intQI_type_node;
11485 intHI_type_internal_node = intHI_type_node;
11486 uintHI_type_internal_node = unsigned_intHI_type_node;
11487 intSI_type_internal_node = intSI_type_node;
11488 uintSI_type_internal_node = unsigned_intSI_type_node;
11489 intDI_type_internal_node = intDI_type_node;
11490 uintDI_type_internal_node = unsigned_intDI_type_node;
11491 float_type_internal_node = float_type_node;
11492 double_type_internal_node = double_type_node;
11493 void_type_internal_node = void_type_node;
11495 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11497 builtin_mode_to_type[QImode][0] = integer_type_node;
11498 builtin_mode_to_type[HImode][0] = integer_type_node;
11499 builtin_mode_to_type[SImode][0] = intSI_type_node;
11500 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11501 builtin_mode_to_type[DImode][0] = intDI_type_node;
11502 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11503 builtin_mode_to_type[SFmode][0] = float_type_node;
11504 builtin_mode_to_type[DFmode][0] = double_type_node;
11505 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
11506 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
11507 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11508 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11509 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11510 builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
11511 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11512 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11513 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11514 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11515 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11516 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11517 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11519 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11520 get_identifier ("__bool char"),
11521 bool_char_type_node);
11522 TYPE_NAME (bool_char_type_node) = tdecl;
11523 (*lang_hooks.decls.pushdecl) (tdecl);
11524 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11525 get_identifier ("__bool short"),
11526 bool_short_type_node);
11527 TYPE_NAME (bool_short_type_node) = tdecl;
11528 (*lang_hooks.decls.pushdecl) (tdecl);
11529 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11530 get_identifier ("__bool int"),
11531 bool_int_type_node);
11532 TYPE_NAME (bool_int_type_node) = tdecl;
11533 (*lang_hooks.decls.pushdecl) (tdecl);
11534 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("__pixel"),
11536 TYPE_NAME (pixel_type_node) = tdecl;
11537 (*lang_hooks.decls.pushdecl) (tdecl);
11539 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
11540 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
11541 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
11542 bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
11543 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
11545 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11546 get_identifier ("__vector unsigned char"),
11547 unsigned_V16QI_type_node);
11548 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
11549 (*lang_hooks.decls.pushdecl) (tdecl);
11550 tdecl = build_decl (BUILTINS_LOCATION,
11551 TYPE_DECL, get_identifier ("__vector signed char"),
11553 TYPE_NAME (V16QI_type_node) = tdecl;
11554 (*lang_hooks.decls.pushdecl) (tdecl);
11555 tdecl = build_decl (BUILTINS_LOCATION,
11556 TYPE_DECL, get_identifier ("__vector __bool char"),
11557 bool_V16QI_type_node);
11558 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
11559 (*lang_hooks.decls.pushdecl) (tdecl);
11561 tdecl = build_decl (BUILTINS_LOCATION,
11562 TYPE_DECL, get_identifier ("__vector unsigned short"),
11563 unsigned_V8HI_type_node);
11564 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
11565 (*lang_hooks.decls.pushdecl) (tdecl);
11566 tdecl = build_decl (BUILTINS_LOCATION,
11567 TYPE_DECL, get_identifier ("__vector signed short"),
11569 TYPE_NAME (V8HI_type_node) = tdecl;
11570 (*lang_hooks.decls.pushdecl) (tdecl);
11571 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11572 get_identifier ("__vector __bool short"),
11573 bool_V8HI_type_node);
11574 TYPE_NAME (bool_V8HI_type_node) = tdecl;
11575 (*lang_hooks.decls.pushdecl) (tdecl);
11577 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11578 get_identifier ("__vector unsigned int"),
11579 unsigned_V4SI_type_node);
11580 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
11581 (*lang_hooks.decls.pushdecl) (tdecl);
11582 tdecl = build_decl (BUILTINS_LOCATION,
11583 TYPE_DECL, get_identifier ("__vector signed int"),
11585 TYPE_NAME (V4SI_type_node) = tdecl;
11586 (*lang_hooks.decls.pushdecl) (tdecl);
11587 tdecl = build_decl (BUILTINS_LOCATION,
11588 TYPE_DECL, get_identifier ("__vector __bool int"),
11589 bool_V4SI_type_node);
11590 TYPE_NAME (bool_V4SI_type_node) = tdecl;
11591 (*lang_hooks.decls.pushdecl) (tdecl);
11593 tdecl = build_decl (BUILTINS_LOCATION,
11594 TYPE_DECL, get_identifier ("__vector float"),
11596 TYPE_NAME (V4SF_type_node) = tdecl;
11597 (*lang_hooks.decls.pushdecl) (tdecl);
11598 tdecl = build_decl (BUILTINS_LOCATION,
11599 TYPE_DECL, get_identifier ("__vector __pixel"),
11600 pixel_V8HI_type_node);
11601 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
11602 (*lang_hooks.decls.pushdecl) (tdecl);
11604 tdecl = build_decl (BUILTINS_LOCATION,
11605 TYPE_DECL, get_identifier ("__vector double"),
11607 TYPE_NAME (V2DF_type_node) = tdecl;
11608 (*lang_hooks.decls.pushdecl) (tdecl);
11610 tdecl = build_decl (BUILTINS_LOCATION,
11611 TYPE_DECL, get_identifier ("__vector long"),
11613 TYPE_NAME (V2DI_type_node) = tdecl;
11614 (*lang_hooks.decls.pushdecl) (tdecl);
11616 tdecl = build_decl (BUILTINS_LOCATION,
11617 TYPE_DECL, get_identifier ("__vector unsigned long"),
11618 unsigned_V2DI_type_node);
11619 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
11620 (*lang_hooks.decls.pushdecl) (tdecl);
11622 tdecl = build_decl (BUILTINS_LOCATION,
11623 TYPE_DECL, get_identifier ("__vector __bool long"),
11624 bool_V2DI_type_node);
11625 TYPE_NAME (bool_V2DI_type_node) = tdecl;
11626 (*lang_hooks.decls.pushdecl) (tdecl);
11628 /* Paired and SPE builtins are only available if you build a compiler with
11629 the appropriate options, so only create those builtins with the
11630 appropriate compiler option. Create Altivec and VSX builtins on machines
11631 with at least the general purpose extensions (970 and newer) to allow the
11632 use of the target attribute. */
11633 if (TARGET_PAIRED_FLOAT)
11634 paired_init_builtins ();
11636 spe_init_builtins ();
11637 if (TARGET_EXTRA_BUILTINS)
11638 altivec_init_builtins ();
11639 if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
11640 rs6000_common_init_builtins ();
11642 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
11643 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
11644 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
11646 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
11647 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
11648 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
11650 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
11651 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
11652 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
11654 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
11655 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
11656 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
11658 mode = (TARGET_64BIT) ? DImode : SImode;
11659 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
11660 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
11661 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
11663 /* Don't use builtin_function_type here, as it maps HI/QI to SI. */
11664 ftype = build_function_type_list (unsigned_intHI_type_node,
11665 unsigned_intHI_type_node,
11667 def_builtin ("__builtin_bswap16", ftype, RS6000_BUILTIN_BSWAP_HI);
11670 /* AIX libm provides clog as __clog. */
11671 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
11672 set_user_assembler_name (tdecl, "__clog");
11675 #ifdef SUBTARGET_INIT_BUILTINS
11676 SUBTARGET_INIT_BUILTINS;
11680 /* Returns the rs6000 builtin decl for CODE. */
11683 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11687 if (code >= RS6000_BUILTIN_COUNT)
11688 return error_mark_node;
11690 fnmask = rs6000_builtin_info[code].mask;
11691 if ((fnmask & rs6000_builtin_mask) != fnmask)
11693 rs6000_invalid_builtin ((enum rs6000_builtins)code);
11694 return error_mark_node;
11697 return rs6000_builtin_decls[code];
11701 spe_init_builtins (void)
11703 tree puint_type_node = build_pointer_type (unsigned_type_node);
11704 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
11705 const struct builtin_description *d;
11708 tree v2si_ftype_4_v2si
11709 = build_function_type_list (opaque_V2SI_type_node,
11710 opaque_V2SI_type_node,
11711 opaque_V2SI_type_node,
11712 opaque_V2SI_type_node,
11713 opaque_V2SI_type_node,
11716 tree v2sf_ftype_4_v2sf
11717 = build_function_type_list (opaque_V2SF_type_node,
11718 opaque_V2SF_type_node,
11719 opaque_V2SF_type_node,
11720 opaque_V2SF_type_node,
11721 opaque_V2SF_type_node,
11724 tree int_ftype_int_v2si_v2si
11725 = build_function_type_list (integer_type_node,
11727 opaque_V2SI_type_node,
11728 opaque_V2SI_type_node,
11731 tree int_ftype_int_v2sf_v2sf
11732 = build_function_type_list (integer_type_node,
11734 opaque_V2SF_type_node,
11735 opaque_V2SF_type_node,
11738 tree void_ftype_v2si_puint_int
11739 = build_function_type_list (void_type_node,
11740 opaque_V2SI_type_node,
11745 tree void_ftype_v2si_puint_char
11746 = build_function_type_list (void_type_node,
11747 opaque_V2SI_type_node,
11752 tree void_ftype_v2si_pv2si_int
11753 = build_function_type_list (void_type_node,
11754 opaque_V2SI_type_node,
11755 opaque_p_V2SI_type_node,
11759 tree void_ftype_v2si_pv2si_char
11760 = build_function_type_list (void_type_node,
11761 opaque_V2SI_type_node,
11762 opaque_p_V2SI_type_node,
11766 tree void_ftype_int
11767 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11769 tree int_ftype_void
11770 = build_function_type_list (integer_type_node, NULL_TREE);
11772 tree v2si_ftype_pv2si_int
11773 = build_function_type_list (opaque_V2SI_type_node,
11774 opaque_p_V2SI_type_node,
11778 tree v2si_ftype_puint_int
11779 = build_function_type_list (opaque_V2SI_type_node,
11784 tree v2si_ftype_pushort_int
11785 = build_function_type_list (opaque_V2SI_type_node,
11790 tree v2si_ftype_signed_char
11791 = build_function_type_list (opaque_V2SI_type_node,
11792 signed_char_type_node,
11795 (*lang_hooks.decls.pushdecl)
11796 (build_decl (BUILTINS_LOCATION, TYPE_DECL,
11797 get_identifier ("__ev64_opaque__"),
11798 opaque_V2SI_type_node));
11800 /* Initialize irregular SPE builtins. */
11802 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
11803 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
11804 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
11805 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
11806 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
11807 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
11808 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
11809 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
11810 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
11811 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
11812 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
11813 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
11814 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
11815 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
11816 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
11817 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
11818 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
11819 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
11822 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
11823 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
11824 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
11825 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
11826 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
11827 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
11828 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
11829 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
11830 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
11831 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
11832 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
11833 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
11834 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
11835 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
11836 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
11837 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
11838 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
11839 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
11840 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
11841 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
11842 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
11843 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
11846 d = bdesc_spe_predicates;
11847 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
11851 switch (insn_data[d->icode].operand[1].mode)
11854 type = int_ftype_int_v2si_v2si;
11857 type = int_ftype_int_v2sf_v2sf;
11860 gcc_unreachable ();
11863 def_builtin (d->name, type, d->code);
11866 /* Evsel predicates. */
11867 d = bdesc_spe_evsel;
11868 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
11872 switch (insn_data[d->icode].operand[1].mode)
11875 type = v2si_ftype_4_v2si;
11878 type = v2sf_ftype_4_v2sf;
11881 gcc_unreachable ();
11884 def_builtin (d->name, type, d->code);
11889 paired_init_builtins (void)
11891 const struct builtin_description *d;
11894 tree int_ftype_int_v2sf_v2sf
11895 = build_function_type_list (integer_type_node,
11900 tree pcfloat_type_node =
11901 build_pointer_type (build_qualified_type
11902 (float_type_node, TYPE_QUAL_CONST));
11904 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
11905 long_integer_type_node,
11908 tree void_ftype_v2sf_long_pcfloat =
11909 build_function_type_list (void_type_node,
11911 long_integer_type_node,
11916 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
11917 PAIRED_BUILTIN_LX);
11920 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
11921 PAIRED_BUILTIN_STX);
11924 d = bdesc_paired_preds;
11925 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
11929 if (TARGET_DEBUG_BUILTIN)
11930 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
11931 (int)i, get_insn_name (d->icode), (int)d->icode,
11932 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
11934 switch (insn_data[d->icode].operand[1].mode)
11937 type = int_ftype_int_v2sf_v2sf;
11940 gcc_unreachable ();
11943 def_builtin (d->name, type, d->code);
11948 altivec_init_builtins (void)
11950 const struct builtin_description *d;
11955 tree pvoid_type_node = build_pointer_type (void_type_node);
11957 tree pcvoid_type_node
11958 = build_pointer_type (build_qualified_type (void_type_node,
11961 tree int_ftype_opaque
11962 = build_function_type_list (integer_type_node,
11963 opaque_V4SI_type_node, NULL_TREE);
11964 tree opaque_ftype_opaque
11965 = build_function_type_list (integer_type_node, NULL_TREE);
11966 tree opaque_ftype_opaque_int
11967 = build_function_type_list (opaque_V4SI_type_node,
11968 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
11969 tree opaque_ftype_opaque_opaque_int
11970 = build_function_type_list (opaque_V4SI_type_node,
11971 opaque_V4SI_type_node, opaque_V4SI_type_node,
11972 integer_type_node, NULL_TREE);
11973 tree int_ftype_int_opaque_opaque
11974 = build_function_type_list (integer_type_node,
11975 integer_type_node, opaque_V4SI_type_node,
11976 opaque_V4SI_type_node, NULL_TREE);
11977 tree int_ftype_int_v4si_v4si
11978 = build_function_type_list (integer_type_node,
11979 integer_type_node, V4SI_type_node,
11980 V4SI_type_node, NULL_TREE);
11981 tree void_ftype_v4si
11982 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
11983 tree v8hi_ftype_void
11984 = build_function_type_list (V8HI_type_node, NULL_TREE);
11985 tree void_ftype_void
11986 = build_function_type_list (void_type_node, NULL_TREE);
11987 tree void_ftype_int
11988 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11990 tree opaque_ftype_long_pcvoid
11991 = build_function_type_list (opaque_V4SI_type_node,
11992 long_integer_type_node, pcvoid_type_node,
11994 tree v16qi_ftype_long_pcvoid
11995 = build_function_type_list (V16QI_type_node,
11996 long_integer_type_node, pcvoid_type_node,
11998 tree v8hi_ftype_long_pcvoid
11999 = build_function_type_list (V8HI_type_node,
12000 long_integer_type_node, pcvoid_type_node,
12002 tree v4si_ftype_long_pcvoid
12003 = build_function_type_list (V4SI_type_node,
12004 long_integer_type_node, pcvoid_type_node,
12006 tree v4sf_ftype_long_pcvoid
12007 = build_function_type_list (V4SF_type_node,
12008 long_integer_type_node, pcvoid_type_node,
12010 tree v2df_ftype_long_pcvoid
12011 = build_function_type_list (V2DF_type_node,
12012 long_integer_type_node, pcvoid_type_node,
12014 tree v2di_ftype_long_pcvoid
12015 = build_function_type_list (V2DI_type_node,
12016 long_integer_type_node, pcvoid_type_node,
12019 tree void_ftype_opaque_long_pvoid
12020 = build_function_type_list (void_type_node,
12021 opaque_V4SI_type_node, long_integer_type_node,
12022 pvoid_type_node, NULL_TREE);
12023 tree void_ftype_v4si_long_pvoid
12024 = build_function_type_list (void_type_node,
12025 V4SI_type_node, long_integer_type_node,
12026 pvoid_type_node, NULL_TREE);
12027 tree void_ftype_v16qi_long_pvoid
12028 = build_function_type_list (void_type_node,
12029 V16QI_type_node, long_integer_type_node,
12030 pvoid_type_node, NULL_TREE);
12031 tree void_ftype_v8hi_long_pvoid
12032 = build_function_type_list (void_type_node,
12033 V8HI_type_node, long_integer_type_node,
12034 pvoid_type_node, NULL_TREE);
12035 tree void_ftype_v4sf_long_pvoid
12036 = build_function_type_list (void_type_node,
12037 V4SF_type_node, long_integer_type_node,
12038 pvoid_type_node, NULL_TREE);
12039 tree void_ftype_v2df_long_pvoid
12040 = build_function_type_list (void_type_node,
12041 V2DF_type_node, long_integer_type_node,
12042 pvoid_type_node, NULL_TREE);
12043 tree void_ftype_v2di_long_pvoid
12044 = build_function_type_list (void_type_node,
12045 V2DI_type_node, long_integer_type_node,
12046 pvoid_type_node, NULL_TREE);
12047 tree int_ftype_int_v8hi_v8hi
12048 = build_function_type_list (integer_type_node,
12049 integer_type_node, V8HI_type_node,
12050 V8HI_type_node, NULL_TREE);
12051 tree int_ftype_int_v16qi_v16qi
12052 = build_function_type_list (integer_type_node,
12053 integer_type_node, V16QI_type_node,
12054 V16QI_type_node, NULL_TREE);
12055 tree int_ftype_int_v4sf_v4sf
12056 = build_function_type_list (integer_type_node,
12057 integer_type_node, V4SF_type_node,
12058 V4SF_type_node, NULL_TREE);
12059 tree int_ftype_int_v2df_v2df
12060 = build_function_type_list (integer_type_node,
12061 integer_type_node, V2DF_type_node,
12062 V2DF_type_node, NULL_TREE);
12063 tree v4si_ftype_v4si
12064 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
12065 tree v8hi_ftype_v8hi
12066 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
12067 tree v16qi_ftype_v16qi
12068 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
12069 tree v4sf_ftype_v4sf
12070 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
12071 tree v2df_ftype_v2df
12072 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
12073 tree void_ftype_pcvoid_int_int
12074 = build_function_type_list (void_type_node,
12075 pcvoid_type_node, integer_type_node,
12076 integer_type_node, NULL_TREE);
12078 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
12079 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
12080 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
12081 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
12082 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
12083 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
12084 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
12085 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
12086 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
12087 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
12088 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
12089 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
12090 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
12091 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
12092 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
12093 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
12094 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
12095 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
12096 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
12097 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
12098 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
12099 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
12100 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
12101 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
12102 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
12103 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
12104 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
12105 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
12106 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
12107 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
12109 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
12110 VSX_BUILTIN_LXVD2X_V2DF);
12111 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
12112 VSX_BUILTIN_LXVD2X_V2DI);
12113 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
12114 VSX_BUILTIN_LXVW4X_V4SF);
12115 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
12116 VSX_BUILTIN_LXVW4X_V4SI);
12117 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
12118 VSX_BUILTIN_LXVW4X_V8HI);
12119 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
12120 VSX_BUILTIN_LXVW4X_V16QI);
12121 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
12122 VSX_BUILTIN_STXVD2X_V2DF);
12123 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
12124 VSX_BUILTIN_STXVD2X_V2DI);
12125 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
12126 VSX_BUILTIN_STXVW4X_V4SF);
12127 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
12128 VSX_BUILTIN_STXVW4X_V4SI);
12129 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
12130 VSX_BUILTIN_STXVW4X_V8HI);
12131 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
12132 VSX_BUILTIN_STXVW4X_V16QI);
12133 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
12134 VSX_BUILTIN_VEC_LD);
12135 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
12136 VSX_BUILTIN_VEC_ST);
12138 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
12139 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
12140 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
12142 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
12143 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
12144 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
12145 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
12146 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
12147 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
12148 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
12149 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
12150 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
12151 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
12152 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
12153 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
12155 /* Cell builtins. */
12156 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
12157 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
12158 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
12159 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
12161 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
12162 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
12163 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
12164 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
12166 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
12167 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
12168 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
12169 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
12171 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
12172 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
12173 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
12174 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
12176 /* Add the DST variants. */
12178 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12179 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
12181 /* Initialize the predicates. */
12182 d = bdesc_altivec_preds;
12183 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
12185 enum machine_mode mode1;
12188 if (rs6000_overloaded_builtin_p (d->code))
12191 mode1 = insn_data[d->icode].operand[1].mode;
12196 type = int_ftype_int_opaque_opaque;
12199 type = int_ftype_int_v4si_v4si;
12202 type = int_ftype_int_v8hi_v8hi;
12205 type = int_ftype_int_v16qi_v16qi;
12208 type = int_ftype_int_v4sf_v4sf;
12211 type = int_ftype_int_v2df_v2df;
12214 gcc_unreachable ();
12217 def_builtin (d->name, type, d->code);
12220 /* Initialize the abs* operators. */
12222 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12224 enum machine_mode mode0;
12227 mode0 = insn_data[d->icode].operand[0].mode;
12232 type = v4si_ftype_v4si;
12235 type = v8hi_ftype_v8hi;
12238 type = v16qi_ftype_v16qi;
12241 type = v4sf_ftype_v4sf;
12244 type = v2df_ftype_v2df;
12247 gcc_unreachable ();
12250 def_builtin (d->name, type, d->code);
12253 /* Initialize target builtin that implements
12254 targetm.vectorize.builtin_mask_for_load. */
12256 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12257 v16qi_ftype_long_pcvoid,
12258 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12259 BUILT_IN_MD, NULL, NULL_TREE);
12260 TREE_READONLY (decl) = 1;
12261 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12262 altivec_builtin_mask_for_load = decl;
12264 /* Access to the vec_init patterns. */
12265 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12266 integer_type_node, integer_type_node,
12267 integer_type_node, NULL_TREE);
12268 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12270 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12271 short_integer_type_node,
12272 short_integer_type_node,
12273 short_integer_type_node,
12274 short_integer_type_node,
12275 short_integer_type_node,
12276 short_integer_type_node,
12277 short_integer_type_node, NULL_TREE);
12278 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12280 ftype = build_function_type_list (V16QI_type_node, char_type_node,
12281 char_type_node, char_type_node,
12282 char_type_node, char_type_node,
12283 char_type_node, char_type_node,
12284 char_type_node, char_type_node,
12285 char_type_node, char_type_node,
12286 char_type_node, char_type_node,
12287 char_type_node, char_type_node,
12288 char_type_node, NULL_TREE);
12289 def_builtin ("__builtin_vec_init_v16qi", ftype,
12290 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12292 ftype = build_function_type_list (V4SF_type_node, float_type_node,
12293 float_type_node, float_type_node,
12294 float_type_node, NULL_TREE);
12295 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12297 /* VSX builtins. */
12298 ftype = build_function_type_list (V2DF_type_node, double_type_node,
12299 double_type_node, NULL_TREE);
12300 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12302 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12303 intDI_type_node, NULL_TREE);
12304 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12306 /* Access to the vec_set patterns. */
12307 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12309 integer_type_node, NULL_TREE);
12310 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12312 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12314 integer_type_node, NULL_TREE);
12315 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12317 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12319 integer_type_node, NULL_TREE);
12320 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12322 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12324 integer_type_node, NULL_TREE);
12325 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12327 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12329 integer_type_node, NULL_TREE);
12330 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12332 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12334 integer_type_node, NULL_TREE);
12335 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12337 /* Access to the vec_extract patterns. */
12338 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12339 integer_type_node, NULL_TREE);
12340 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12342 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12343 integer_type_node, NULL_TREE);
12344 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12346 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12347 integer_type_node, NULL_TREE);
12348 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12350 ftype = build_function_type_list (float_type_node, V4SF_type_node,
12351 integer_type_node, NULL_TREE);
12352 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12354 ftype = build_function_type_list (double_type_node, V2DF_type_node,
12355 integer_type_node, NULL_TREE);
12356 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12358 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12359 integer_type_node, NULL_TREE);
12360 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12363 /* Hash function for builtin functions with up to 3 arguments and a return
12366 builtin_hash_function (const void *hash_entry)
12370 const struct builtin_hash_struct *bh =
12371 (const struct builtin_hash_struct *) hash_entry;
12373 for (i = 0; i < 4; i++)
12375 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
12376 ret = (ret * 2) + bh->uns_p[i];
12382 /* Compare builtin hash entries H1 and H2 for equivalence. */
12384 builtin_hash_eq (const void *h1, const void *h2)
12386 const struct builtin_hash_struct *p1 = (const struct builtin_hash_struct *) h1;
12387 const struct builtin_hash_struct *p2 = (const struct builtin_hash_struct *) h2;
12389 return ((p1->mode[0] == p2->mode[0])
12390 && (p1->mode[1] == p2->mode[1])
12391 && (p1->mode[2] == p2->mode[2])
12392 && (p1->mode[3] == p2->mode[3])
12393 && (p1->uns_p[0] == p2->uns_p[0])
12394 && (p1->uns_p[1] == p2->uns_p[1])
12395 && (p1->uns_p[2] == p2->uns_p[2])
12396 && (p1->uns_p[3] == p2->uns_p[3]));
12399 /* Map types for builtin functions with an explicit return type and up to 3
12400 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12401 of the argument. */
12403 builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0,
12404 enum machine_mode mode_arg1, enum machine_mode mode_arg2,
12405 enum rs6000_builtins builtin, const char *name)
12407 struct builtin_hash_struct h;
12408 struct builtin_hash_struct *h2;
12412 tree ret_type = NULL_TREE;
12413 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12415 /* Create builtin_hash_table. */
12416 if (builtin_hash_table == NULL)
12417 builtin_hash_table = htab_create_ggc (1500, builtin_hash_function,
12418 builtin_hash_eq, NULL);
12420 h.type = NULL_TREE;
12421 h.mode[0] = mode_ret;
12422 h.mode[1] = mode_arg0;
12423 h.mode[2] = mode_arg1;
12424 h.mode[3] = mode_arg2;
12430 /* If the builtin is a type that produces unsigned results or takes unsigned
12431 arguments, and it is returned as a decl for the vectorizer (such as
12432 widening multiplies, permute), make sure the arguments and return value
12433 are type correct. */
12436 /* unsigned 2 argument functions. */
12437 case ALTIVEC_BUILTIN_VMULEUB_UNS:
12438 case ALTIVEC_BUILTIN_VMULEUH_UNS:
12439 case ALTIVEC_BUILTIN_VMULOUB_UNS:
12440 case ALTIVEC_BUILTIN_VMULOUH_UNS:
12446 /* unsigned 3 argument functions. */
12447 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12448 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12449 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12450 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12451 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12452 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12453 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12454 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12455 case VSX_BUILTIN_VPERM_16QI_UNS:
12456 case VSX_BUILTIN_VPERM_8HI_UNS:
12457 case VSX_BUILTIN_VPERM_4SI_UNS:
12458 case VSX_BUILTIN_VPERM_2DI_UNS:
12459 case VSX_BUILTIN_XXSEL_16QI_UNS:
12460 case VSX_BUILTIN_XXSEL_8HI_UNS:
12461 case VSX_BUILTIN_XXSEL_4SI_UNS:
12462 case VSX_BUILTIN_XXSEL_2DI_UNS:
12469 /* signed permute functions with unsigned char mask. */
12470 case ALTIVEC_BUILTIN_VPERM_16QI:
12471 case ALTIVEC_BUILTIN_VPERM_8HI:
12472 case ALTIVEC_BUILTIN_VPERM_4SI:
12473 case ALTIVEC_BUILTIN_VPERM_4SF:
12474 case ALTIVEC_BUILTIN_VPERM_2DI:
12475 case ALTIVEC_BUILTIN_VPERM_2DF:
12476 case VSX_BUILTIN_VPERM_16QI:
12477 case VSX_BUILTIN_VPERM_8HI:
12478 case VSX_BUILTIN_VPERM_4SI:
12479 case VSX_BUILTIN_VPERM_4SF:
12480 case VSX_BUILTIN_VPERM_2DI:
12481 case VSX_BUILTIN_VPERM_2DF:
12485 /* unsigned args, signed return. */
12486 case VSX_BUILTIN_XVCVUXDDP_UNS:
12487 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12491 /* signed args, unsigned return. */
12492 case VSX_BUILTIN_XVCVDPUXDS_UNS:
12493 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12501 /* Figure out how many args are present. */
12502 while (num_args > 0 && h.mode[num_args] == VOIDmode)
12506 fatal_error ("internal error: builtin function %s had no type", name);
12508 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
12509 if (!ret_type && h.uns_p[0])
12510 ret_type = builtin_mode_to_type[h.mode[0]][0];
12513 fatal_error ("internal error: builtin function %s had an unexpected "
12514 "return type %s", name, GET_MODE_NAME (h.mode[0]));
12516 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
12517 arg_type[i] = NULL_TREE;
12519 for (i = 0; i < num_args; i++)
12521 int m = (int) h.mode[i+1];
12522 int uns_p = h.uns_p[i+1];
12524 arg_type[i] = builtin_mode_to_type[m][uns_p];
12525 if (!arg_type[i] && uns_p)
12526 arg_type[i] = builtin_mode_to_type[m][0];
12529 fatal_error ("internal error: builtin function %s, argument %d "
12530 "had unexpected argument type %s", name, i,
12531 GET_MODE_NAME (m));
12534 found = htab_find_slot (builtin_hash_table, &h, INSERT);
12535 if (*found == NULL)
12537 h2 = ggc_alloc_builtin_hash_struct ();
12539 *found = (void *)h2;
12541 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
12542 arg_type[2], NULL_TREE);
12545 return ((struct builtin_hash_struct *)(*found))->type;
12549 rs6000_common_init_builtins (void)
12551 const struct builtin_description *d;
12554 tree opaque_ftype_opaque = NULL_TREE;
12555 tree opaque_ftype_opaque_opaque = NULL_TREE;
12556 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
12557 tree v2si_ftype_qi = NULL_TREE;
12558 tree v2si_ftype_v2si_qi = NULL_TREE;
12559 tree v2si_ftype_int_qi = NULL_TREE;
12560 unsigned builtin_mask = rs6000_builtin_mask;
12562 if (!TARGET_PAIRED_FLOAT)
12564 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
12565 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
12568 /* Paired and SPE builtins are only available if you build a compiler with
12569 the appropriate options, so only create those builtins with the
12570 appropriate compiler option. Create Altivec and VSX builtins on machines
12571 with at least the general purpose extensions (970 and newer) to allow the
12572 use of the target attribute.. */
12574 if (TARGET_EXTRA_BUILTINS)
12575 builtin_mask |= RS6000_BTM_COMMON;
12577 /* Add the ternary operators. */
12579 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12582 unsigned mask = d->mask;
12584 if ((mask & builtin_mask) != mask)
12586 if (TARGET_DEBUG_BUILTIN)
12587 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
12591 if (rs6000_overloaded_builtin_p (d->code))
12593 if (! (type = opaque_ftype_opaque_opaque_opaque))
12594 type = opaque_ftype_opaque_opaque_opaque
12595 = build_function_type_list (opaque_V4SI_type_node,
12596 opaque_V4SI_type_node,
12597 opaque_V4SI_type_node,
12598 opaque_V4SI_type_node,
12603 enum insn_code icode = d->icode;
12604 if (d->name == 0 || icode == CODE_FOR_nothing)
12607 type = builtin_function_type (insn_data[icode].operand[0].mode,
12608 insn_data[icode].operand[1].mode,
12609 insn_data[icode].operand[2].mode,
12610 insn_data[icode].operand[3].mode,
12614 def_builtin (d->name, type, d->code);
12617 /* Add the binary operators. */
12619 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12621 enum machine_mode mode0, mode1, mode2;
12623 unsigned mask = d->mask;
12625 if ((mask & builtin_mask) != mask)
12627 if (TARGET_DEBUG_BUILTIN)
12628 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
12632 if (rs6000_overloaded_builtin_p (d->code))
12634 if (! (type = opaque_ftype_opaque_opaque))
12635 type = opaque_ftype_opaque_opaque
12636 = build_function_type_list (opaque_V4SI_type_node,
12637 opaque_V4SI_type_node,
12638 opaque_V4SI_type_node,
12643 enum insn_code icode = d->icode;
12644 if (d->name == 0 || icode == CODE_FOR_nothing)
12647 mode0 = insn_data[icode].operand[0].mode;
12648 mode1 = insn_data[icode].operand[1].mode;
12649 mode2 = insn_data[icode].operand[2].mode;
12651 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
12653 if (! (type = v2si_ftype_v2si_qi))
12654 type = v2si_ftype_v2si_qi
12655 = build_function_type_list (opaque_V2SI_type_node,
12656 opaque_V2SI_type_node,
12661 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
12662 && mode2 == QImode)
12664 if (! (type = v2si_ftype_int_qi))
12665 type = v2si_ftype_int_qi
12666 = build_function_type_list (opaque_V2SI_type_node,
12673 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
12677 def_builtin (d->name, type, d->code);
12680 /* Add the simple unary operators. */
12682 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12684 enum machine_mode mode0, mode1;
12686 unsigned mask = d->mask;
12688 if ((mask & builtin_mask) != mask)
12690 if (TARGET_DEBUG_BUILTIN)
12691 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
12695 if (rs6000_overloaded_builtin_p (d->code))
12697 if (! (type = opaque_ftype_opaque))
12698 type = opaque_ftype_opaque
12699 = build_function_type_list (opaque_V4SI_type_node,
12700 opaque_V4SI_type_node,
12705 enum insn_code icode = d->icode;
12706 if (d->name == 0 || icode == CODE_FOR_nothing)
12709 mode0 = insn_data[icode].operand[0].mode;
12710 mode1 = insn_data[icode].operand[1].mode;
12712 if (mode0 == V2SImode && mode1 == QImode)
12714 if (! (type = v2si_ftype_qi))
12715 type = v2si_ftype_qi
12716 = build_function_type_list (opaque_V2SI_type_node,
12722 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
12726 def_builtin (d->name, type, d->code);
12731 rs6000_init_libfuncs (void)
12733 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
12734 && !TARGET_POWER2 && !TARGET_POWERPC)
12736 /* AIX library routines for float->int conversion. */
12737 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
12738 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
12739 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
12740 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
12743 if (!TARGET_IEEEQUAD)
12744 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12745 if (!TARGET_XL_COMPAT)
12747 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
12748 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
12749 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
12750 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
12752 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
12754 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
12755 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
12756 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
12757 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
12758 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
12759 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
12760 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
12762 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
12763 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
12764 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
12765 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
12766 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
12767 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
12768 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
12769 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
12772 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
12773 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
12777 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
12778 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
12779 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
12780 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
12784 /* 32-bit SVR4 quad floating point routines. */
12786 set_optab_libfunc (add_optab, TFmode, "_q_add");
12787 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
12788 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
12789 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
12790 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
12791 if (TARGET_PPC_GPOPT || TARGET_POWER2)
12792 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
12794 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
12795 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
12796 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
12797 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
12798 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
12799 set_optab_libfunc (le_optab, TFmode, "_q_fle");
12801 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
12802 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
12803 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
12804 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
12805 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
12806 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
12807 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
12808 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
12813 /* Expand a block clear operation, and return 1 if successful. Return 0
12814 if we should let the compiler generate normal code.
12816 operands[0] is the destination
12817 operands[1] is the length
12818 operands[3] is the alignment */
12821 expand_block_clear (rtx operands[])
12823 rtx orig_dest = operands[0];
12824 rtx bytes_rtx = operands[1];
12825 rtx align_rtx = operands[3];
12826 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
12827 HOST_WIDE_INT align;
12828 HOST_WIDE_INT bytes;
12833 /* If this is not a fixed size move, just call memcpy */
12837 /* This must be a fixed size alignment */
12838 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12839 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12841 /* Anything to clear? */
12842 bytes = INTVAL (bytes_rtx);
12846 /* Use the builtin memset after a point, to avoid huge code bloat.
12847 When optimize_size, avoid any significant code bloat; calling
12848 memset is about 4 instructions, so allow for one instruction to
12849 load zero and three to do clearing. */
12850 if (TARGET_ALTIVEC && align >= 128)
12852 else if (TARGET_POWERPC64 && align >= 32)
12854 else if (TARGET_SPE && align >= 64)
12859 if (optimize_size && bytes > 3 * clear_step)
12861 if (! optimize_size && bytes > 8 * clear_step)
12864 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
12866 enum machine_mode mode = BLKmode;
12869 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
12874 else if (bytes >= 8 && TARGET_SPE && align >= 64)
12879 else if (bytes >= 8 && TARGET_POWERPC64
12880 /* 64-bit loads and stores require word-aligned
12882 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12887 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12888 { /* move 4 bytes */
12892 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12893 { /* move 2 bytes */
12897 else /* move 1 byte at a time */
12903 dest = adjust_address (orig_dest, mode, offset);
12905 emit_move_insn (dest, CONST0_RTX (mode));
12912 /* Expand a block move operation, and return 1 if successful. Return 0
12913 if we should let the compiler generate normal code.
12915 operands[0] is the destination
12916 operands[1] is the source
12917 operands[2] is the length
12918 operands[3] is the alignment */
12920 #define MAX_MOVE_REG 4
12923 expand_block_move (rtx operands[])
12925 rtx orig_dest = operands[0];
12926 rtx orig_src = operands[1];
12927 rtx bytes_rtx = operands[2];
12928 rtx align_rtx = operands[3];
12929 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
12934 rtx stores[MAX_MOVE_REG];
12937 /* If this is not a fixed size move, just call memcpy */
12941 /* This must be a fixed size alignment */
12942 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12943 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12945 /* Anything to move? */
12946 bytes = INTVAL (bytes_rtx);
12950 if (bytes > rs6000_block_move_inline_limit)
12953 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
12956 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
12957 rtx (*mov) (rtx, rtx);
12959 enum machine_mode mode = BLKmode;
12962 /* Altivec first, since it will be faster than a string move
12963 when it applies, and usually not significantly larger. */
12964 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
12968 gen_func.mov = gen_movv4si;
12970 else if (TARGET_SPE && bytes >= 8 && align >= 64)
12974 gen_func.mov = gen_movv2si;
12976 else if (TARGET_STRING
12977 && bytes > 24 /* move up to 32 bytes at a time */
12983 && ! fixed_regs[10]
12984 && ! fixed_regs[11]
12985 && ! fixed_regs[12])
12987 move_bytes = (bytes > 32) ? 32 : bytes;
12988 gen_func.movmemsi = gen_movmemsi_8reg;
12990 else if (TARGET_STRING
12991 && bytes > 16 /* move up to 24 bytes at a time */
12997 && ! fixed_regs[10])
12999 move_bytes = (bytes > 24) ? 24 : bytes;
13000 gen_func.movmemsi = gen_movmemsi_6reg;
13002 else if (TARGET_STRING
13003 && bytes > 8 /* move up to 16 bytes at a time */
13007 && ! fixed_regs[8])
13009 move_bytes = (bytes > 16) ? 16 : bytes;
13010 gen_func.movmemsi = gen_movmemsi_4reg;
13012 else if (bytes >= 8 && TARGET_POWERPC64
13013 /* 64-bit loads and stores require word-aligned
13015 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
13019 gen_func.mov = gen_movdi;
13021 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
13022 { /* move up to 8 bytes at a time */
13023 move_bytes = (bytes > 8) ? 8 : bytes;
13024 gen_func.movmemsi = gen_movmemsi_2reg;
13026 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
13027 { /* move 4 bytes */
13030 gen_func.mov = gen_movsi;
13032 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
13033 { /* move 2 bytes */
13036 gen_func.mov = gen_movhi;
13038 else if (TARGET_STRING && bytes > 1)
13039 { /* move up to 4 bytes at a time */
13040 move_bytes = (bytes > 4) ? 4 : bytes;
13041 gen_func.movmemsi = gen_movmemsi_1reg;
13043 else /* move 1 byte at a time */
13047 gen_func.mov = gen_movqi;
13050 src = adjust_address (orig_src, mode, offset);
13051 dest = adjust_address (orig_dest, mode, offset);
13053 if (mode != BLKmode)
13055 rtx tmp_reg = gen_reg_rtx (mode);
13057 emit_insn ((*gen_func.mov) (tmp_reg, src));
13058 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
13061 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
13064 for (i = 0; i < num_reg; i++)
13065 emit_insn (stores[i]);
13069 if (mode == BLKmode)
13071 /* Move the address into scratch registers. The movmemsi
13072 patterns require zero offset. */
13073 if (!REG_P (XEXP (src, 0)))
13075 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
13076 src = replace_equiv_address (src, src_reg);
13078 set_mem_size (src, move_bytes);
13080 if (!REG_P (XEXP (dest, 0)))
13082 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
13083 dest = replace_equiv_address (dest, dest_reg);
13085 set_mem_size (dest, move_bytes);
13087 emit_insn ((*gen_func.movmemsi) (dest, src,
13088 GEN_INT (move_bytes & 31),
13097 /* Return a string to perform a load_multiple operation.
13098 operands[0] is the vector.
13099 operands[1] is the source address.
13100 operands[2] is the first destination register. */
13103 rs6000_output_load_multiple (rtx operands[3])
13105 /* We have to handle the case where the pseudo used to contain the address
13106 is assigned to one of the output registers. */
13108 int words = XVECLEN (operands[0], 0);
13111 if (XVECLEN (operands[0], 0) == 1)
13112 return "{l|lwz} %2,0(%1)";
13114 for (i = 0; i < words; i++)
13115 if (refers_to_regno_p (REGNO (operands[2]) + i,
13116 REGNO (operands[2]) + i + 1, operands[1], 0))
13120 xop[0] = GEN_INT (4 * (words-1));
13121 xop[1] = operands[1];
13122 xop[2] = operands[2];
13123 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
13128 xop[0] = GEN_INT (4 * (words-1));
13129 xop[1] = operands[1];
13130 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
13131 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
13136 for (j = 0; j < words; j++)
13139 xop[0] = GEN_INT (j * 4);
13140 xop[1] = operands[1];
13141 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
13142 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
13144 xop[0] = GEN_INT (i * 4);
13145 xop[1] = operands[1];
13146 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
13151 return "{lsi|lswi} %2,%1,%N0";
13155 /* A validation routine: say whether CODE, a condition code, and MODE
13156 match. The other alternatives either don't make sense or should
13157 never be generated. */
13160 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
13162 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
13163 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
13164 && GET_MODE_CLASS (mode) == MODE_CC);
13166 /* These don't make sense. */
13167 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
13168 || mode != CCUNSmode);
13170 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
13171 || mode == CCUNSmode);
13173 gcc_assert (mode == CCFPmode
13174 || (code != ORDERED && code != UNORDERED
13175 && code != UNEQ && code != LTGT
13176 && code != UNGT && code != UNLT
13177 && code != UNGE && code != UNLE));
13179 /* These should never be generated except for
13180 flag_finite_math_only. */
13181 gcc_assert (mode != CCFPmode
13182 || flag_finite_math_only
13183 || (code != LE && code != GE
13184 && code != UNEQ && code != LTGT
13185 && code != UNGT && code != UNLT));
13187 /* These are invalid; the information is not there. */
13188 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
13192 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13193 mask required to convert the result of a rotate insn into a shift
13194 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13197 includes_lshift_p (rtx shiftop, rtx andop)
13199 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13201 shift_mask <<= INTVAL (shiftop);
13203 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13206 /* Similar, but for right shift. */
13209 includes_rshift_p (rtx shiftop, rtx andop)
13211 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13213 shift_mask >>= INTVAL (shiftop);
13215 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13218 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13219 to perform a left shift. It must have exactly SHIFTOP least
13220 significant 0's, then one or more 1's, then zero or more 0's. */
13223 includes_rldic_lshift_p (rtx shiftop, rtx andop)
13225 if (GET_CODE (andop) == CONST_INT)
13227 HOST_WIDE_INT c, lsb, shift_mask;
13229 c = INTVAL (andop);
13230 if (c == 0 || c == ~0)
13234 shift_mask <<= INTVAL (shiftop);
13236 /* Find the least significant one bit. */
13239 /* It must coincide with the LSB of the shift mask. */
13240 if (-lsb != shift_mask)
13243 /* Invert to look for the next transition (if any). */
13246 /* Remove the low group of ones (originally low group of zeros). */
13249 /* Again find the lsb, and check we have all 1's above. */
13253 else if (GET_CODE (andop) == CONST_DOUBLE
13254 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13256 HOST_WIDE_INT low, high, lsb;
13257 HOST_WIDE_INT shift_mask_low, shift_mask_high;
13259 low = CONST_DOUBLE_LOW (andop);
13260 if (HOST_BITS_PER_WIDE_INT < 64)
13261 high = CONST_DOUBLE_HIGH (andop);
13263 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
13264 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
13267 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13269 shift_mask_high = ~0;
13270 if (INTVAL (shiftop) > 32)
13271 shift_mask_high <<= INTVAL (shiftop) - 32;
13273 lsb = high & -high;
13275 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
13281 lsb = high & -high;
13282 return high == -lsb;
13285 shift_mask_low = ~0;
13286 shift_mask_low <<= INTVAL (shiftop);
13290 if (-lsb != shift_mask_low)
13293 if (HOST_BITS_PER_WIDE_INT < 64)
13298 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13300 lsb = high & -high;
13301 return high == -lsb;
13305 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
13311 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13312 to perform a left shift. It must have SHIFTOP or more least
13313 significant 0's, with the remainder of the word 1's. */
13316 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
13318 if (GET_CODE (andop) == CONST_INT)
13320 HOST_WIDE_INT c, lsb, shift_mask;
13323 shift_mask <<= INTVAL (shiftop);
13324 c = INTVAL (andop);
13326 /* Find the least significant one bit. */
13329 /* It must be covered by the shift mask.
13330 This test also rejects c == 0. */
13331 if ((lsb & shift_mask) == 0)
13334 /* Check we have all 1's above the transition, and reject all 1's. */
13335 return c == -lsb && lsb != 1;
13337 else if (GET_CODE (andop) == CONST_DOUBLE
13338 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13340 HOST_WIDE_INT low, lsb, shift_mask_low;
13342 low = CONST_DOUBLE_LOW (andop);
13344 if (HOST_BITS_PER_WIDE_INT < 64)
13346 HOST_WIDE_INT high, shift_mask_high;
13348 high = CONST_DOUBLE_HIGH (andop);
13352 shift_mask_high = ~0;
13353 if (INTVAL (shiftop) > 32)
13354 shift_mask_high <<= INTVAL (shiftop) - 32;
13356 lsb = high & -high;
13358 if ((lsb & shift_mask_high) == 0)
13361 return high == -lsb;
13367 shift_mask_low = ~0;
13368 shift_mask_low <<= INTVAL (shiftop);
13372 if ((lsb & shift_mask_low) == 0)
13375 return low == -lsb && lsb != 1;
13381 /* Return 1 if operands will generate a valid arguments to rlwimi
13382 instruction for insert with right shift in 64-bit mode. The mask may
13383 not start on the first bit or stop on the last bit because wrap-around
13384 effects of instruction do not correspond to semantics of RTL insn. */
13387 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
13389 if (INTVAL (startop) > 32
13390 && INTVAL (startop) < 64
13391 && INTVAL (sizeop) > 1
13392 && INTVAL (sizeop) + INTVAL (startop) < 64
13393 && INTVAL (shiftop) > 0
13394 && INTVAL (sizeop) + INTVAL (shiftop) < 32
13395 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
13401 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13402 for lfq and stfq insns iff the registers are hard registers. */
13405 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
13407 /* We might have been passed a SUBREG. */
13408 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
13411 /* We might have been passed non floating point registers. */
13412 if (!FP_REGNO_P (REGNO (reg1))
13413 || !FP_REGNO_P (REGNO (reg2)))
13416 return (REGNO (reg1) == REGNO (reg2) - 1);
13419 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13420 addr1 and addr2 must be in consecutive memory locations
13421 (addr2 == addr1 + 8). */
13424 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
13427 unsigned int reg1, reg2;
13428 int offset1, offset2;
13430 /* The mems cannot be volatile. */
13431 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
13434 addr1 = XEXP (mem1, 0);
13435 addr2 = XEXP (mem2, 0);
13437 /* Extract an offset (if used) from the first addr. */
13438 if (GET_CODE (addr1) == PLUS)
13440 /* If not a REG, return zero. */
13441 if (GET_CODE (XEXP (addr1, 0)) != REG)
13445 reg1 = REGNO (XEXP (addr1, 0));
13446 /* The offset must be constant! */
13447 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
13449 offset1 = INTVAL (XEXP (addr1, 1));
13452 else if (GET_CODE (addr1) != REG)
13456 reg1 = REGNO (addr1);
13457 /* This was a simple (mem (reg)) expression. Offset is 0. */
13461 /* And now for the second addr. */
13462 if (GET_CODE (addr2) == PLUS)
13464 /* If not a REG, return zero. */
13465 if (GET_CODE (XEXP (addr2, 0)) != REG)
13469 reg2 = REGNO (XEXP (addr2, 0));
13470 /* The offset must be constant. */
13471 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
13473 offset2 = INTVAL (XEXP (addr2, 1));
13476 else if (GET_CODE (addr2) != REG)
13480 reg2 = REGNO (addr2);
13481 /* This was a simple (mem (reg)) expression. Offset is 0. */
13485 /* Both of these must have the same base register. */
13489 /* The offset for the second addr must be 8 more than the first addr. */
13490 if (offset2 != offset1 + 8)
13493 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13500 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
13502 static bool eliminated = false;
13505 if (mode != SDmode)
13506 ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13509 rtx mem = cfun->machine->sdmode_stack_slot;
13510 gcc_assert (mem != NULL_RTX);
13514 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
13515 cfun->machine->sdmode_stack_slot = mem;
13521 if (TARGET_DEBUG_ADDR)
13523 fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13524 GET_MODE_NAME (mode));
13526 fprintf (stderr, "\tNULL_RTX\n");
13535 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
13537 /* Don't walk into types. */
13538 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
13540 *walk_subtrees = 0;
13544 switch (TREE_CODE (*tp))
13553 case VIEW_CONVERT_EXPR:
13554 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
13564 enum reload_reg_type {
13566 VECTOR_REGISTER_TYPE,
13567 OTHER_REGISTER_TYPE
13570 static enum reload_reg_type
13571 rs6000_reload_register_type (enum reg_class rclass)
13577 return GPR_REGISTER_TYPE;
13582 return VECTOR_REGISTER_TYPE;
13585 return OTHER_REGISTER_TYPE;
13589 /* Inform reload about cases where moving X with a mode MODE to a register in
13590 RCLASS requires an extra scratch or immediate register. Return the class
13591 needed for the immediate register.
13593 For VSX and Altivec, we may need a register to convert sp+offset into
13596 For misaligned 64-bit gpr loads and stores we need a register to
13597 convert an offset address to indirect. */
13600 rs6000_secondary_reload (bool in_p,
13602 reg_class_t rclass_i,
13603 enum machine_mode mode,
13604 secondary_reload_info *sri)
13606 enum reg_class rclass = (enum reg_class) rclass_i;
13607 reg_class_t ret = ALL_REGS;
13608 enum insn_code icode;
13609 bool default_p = false;
13611 sri->icode = CODE_FOR_nothing;
13613 /* Convert vector loads and stores into gprs to use an additional base
13615 icode = rs6000_vector_reload[mode][in_p != false];
13616 if (icode != CODE_FOR_nothing)
13619 sri->icode = CODE_FOR_nothing;
13620 sri->extra_cost = 0;
13622 if (GET_CODE (x) == MEM)
13624 rtx addr = XEXP (x, 0);
13626 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13627 an extra register in that case, but it would need an extra
13628 register if the addressing is reg+reg or (reg+reg)&(-16). */
13629 if (rclass == GENERAL_REGS || rclass == BASE_REGS)
13631 if (!legitimate_indirect_address_p (addr, false)
13632 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13634 sri->icode = icode;
13635 /* account for splitting the loads, and converting the
13636 address from reg+reg to reg. */
13637 sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
13638 + ((GET_CODE (addr) == AND) ? 1 : 0));
13641 /* Loads to and stores from vector registers can only do reg+reg
13642 addressing. Altivec registers can also do (reg+reg)&(-16). */
13643 else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
13644 || rclass == FLOAT_REGS || rclass == NO_REGS)
13646 if (!VECTOR_MEM_ALTIVEC_P (mode)
13647 && GET_CODE (addr) == AND
13648 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13649 && INTVAL (XEXP (addr, 1)) == -16
13650 && (legitimate_indirect_address_p (XEXP (addr, 0), false)
13651 || legitimate_indexed_address_p (XEXP (addr, 0), false)))
13653 sri->icode = icode;
13654 sri->extra_cost = ((GET_CODE (XEXP (addr, 0)) == PLUS)
13657 else if (!legitimate_indirect_address_p (addr, false)
13658 && (rclass == NO_REGS
13659 || !legitimate_indexed_address_p (addr, false)))
13661 sri->icode = icode;
13662 sri->extra_cost = 1;
13665 icode = CODE_FOR_nothing;
13667 /* Any other loads, including to pseudo registers which haven't been
13668 assigned to a register yet, default to require a scratch
13672 sri->icode = icode;
13673 sri->extra_cost = 2;
13676 else if (REG_P (x))
13678 int regno = true_regnum (x);
13680 icode = CODE_FOR_nothing;
13681 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
13685 enum reg_class xclass = REGNO_REG_CLASS (regno);
13686 enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
13687 enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
13689 /* If memory is needed, use default_secondary_reload to create the
13691 if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
13700 else if (TARGET_POWERPC64
13701 && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13703 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
13705 rtx addr = XEXP (x, 0);
13707 if (GET_CODE (addr) == PRE_MODIFY)
13708 addr = XEXP (addr, 1);
13709 else if (GET_CODE (addr) == LO_SUM
13710 && GET_CODE (XEXP (addr, 0)) == REG
13711 && GET_CODE (XEXP (addr, 1)) == CONST)
13712 addr = XEXP (XEXP (addr, 1), 0);
13714 if (GET_CODE (addr) == PLUS
13715 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13716 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
13719 sri->icode = CODE_FOR_reload_di_load;
13721 sri->icode = CODE_FOR_reload_di_store;
13722 sri->extra_cost = 2;
13732 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
13734 gcc_assert (ret != ALL_REGS);
13736 if (TARGET_DEBUG_ADDR)
13739 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13741 reg_class_names[ret],
13742 in_p ? "true" : "false",
13743 reg_class_names[rclass],
13744 GET_MODE_NAME (mode));
13747 fprintf (stderr, ", default secondary reload");
13749 if (sri->icode != CODE_FOR_nothing)
13750 fprintf (stderr, ", reload func = %s, extra cost = %d\n",
13751 insn_data[sri->icode].name, sri->extra_cost);
13753 fprintf (stderr, "\n");
13761 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13762 to SP+reg addressing. */
13765 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
13767 int regno = true_regnum (reg);
13768 enum machine_mode mode = GET_MODE (reg);
13769 enum reg_class rclass;
13771 rtx and_op2 = NULL_RTX;
13774 rtx scratch_or_premodify = scratch;
13778 if (TARGET_DEBUG_ADDR)
13780 fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
13781 store_p ? "store" : "load");
13782 fprintf (stderr, "reg:\n");
13784 fprintf (stderr, "mem:\n");
13786 fprintf (stderr, "scratch:\n");
13787 debug_rtx (scratch);
13790 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13791 gcc_assert (GET_CODE (mem) == MEM);
13792 rclass = REGNO_REG_CLASS (regno);
13793 addr = XEXP (mem, 0);
13797 /* GPRs can handle reg + small constant, all other addresses need to use
13798 the scratch register. */
13801 if (GET_CODE (addr) == AND)
13803 and_op2 = XEXP (addr, 1);
13804 addr = XEXP (addr, 0);
13807 if (GET_CODE (addr) == PRE_MODIFY)
13809 scratch_or_premodify = XEXP (addr, 0);
13810 gcc_assert (REG_P (scratch_or_premodify));
13811 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13812 addr = XEXP (addr, 1);
13815 if (GET_CODE (addr) == PLUS
13816 && (!rs6000_legitimate_offset_address_p (TImode, addr, false)
13817 || and_op2 != NULL_RTX))
13819 addr_op1 = XEXP (addr, 0);
13820 addr_op2 = XEXP (addr, 1);
13821 gcc_assert (legitimate_indirect_address_p (addr_op1, false));
13823 if (!REG_P (addr_op2)
13824 && (GET_CODE (addr_op2) != CONST_INT
13825 || !satisfies_constraint_I (addr_op2)))
13827 if (TARGET_DEBUG_ADDR)
13830 "\nMove plus addr to register %s, mode = %s: ",
13831 rs6000_reg_names[REGNO (scratch)],
13832 GET_MODE_NAME (mode));
13833 debug_rtx (addr_op2);
13835 rs6000_emit_move (scratch, addr_op2, Pmode);
13836 addr_op2 = scratch;
13839 emit_insn (gen_rtx_SET (VOIDmode,
13840 scratch_or_premodify,
13841 gen_rtx_PLUS (Pmode,
13845 addr = scratch_or_premodify;
13846 scratch_or_premodify = scratch;
13848 else if (!legitimate_indirect_address_p (addr, false)
13849 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13851 if (TARGET_DEBUG_ADDR)
13853 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13854 rs6000_reg_names[REGNO (scratch_or_premodify)],
13855 GET_MODE_NAME (mode));
13858 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13859 addr = scratch_or_premodify;
13860 scratch_or_premodify = scratch;
13864 /* Float/Altivec registers can only handle reg+reg addressing. Move
13865 other addresses into a scratch register. */
13870 /* With float regs, we need to handle the AND ourselves, since we can't
13871 use the Altivec instruction with an implicit AND -16. Allow scalar
13872 loads to float registers to use reg+offset even if VSX. */
13873 if (GET_CODE (addr) == AND
13874 && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16
13875 || GET_CODE (XEXP (addr, 1)) != CONST_INT
13876 || INTVAL (XEXP (addr, 1)) != -16
13877 || !VECTOR_MEM_ALTIVEC_P (mode)))
13879 and_op2 = XEXP (addr, 1);
13880 addr = XEXP (addr, 0);
13883 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
13884 as the address later. */
13885 if (GET_CODE (addr) == PRE_MODIFY
13886 && (!VECTOR_MEM_VSX_P (mode)
13887 || and_op2 != NULL_RTX
13888 || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
13890 scratch_or_premodify = XEXP (addr, 0);
13891 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
13893 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13894 addr = XEXP (addr, 1);
13897 if (legitimate_indirect_address_p (addr, false) /* reg */
13898 || legitimate_indexed_address_p (addr, false) /* reg+reg */
13899 || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
13900 || (GET_CODE (addr) == AND /* Altivec memory */
13901 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13902 && INTVAL (XEXP (addr, 1)) == -16
13903 && VECTOR_MEM_ALTIVEC_P (mode))
13904 || (rclass == FLOAT_REGS /* legacy float mem */
13905 && GET_MODE_SIZE (mode) == 8
13906 && and_op2 == NULL_RTX
13907 && scratch_or_premodify == scratch
13908 && rs6000_legitimate_offset_address_p (mode, addr, false)))
13911 else if (GET_CODE (addr) == PLUS)
13913 addr_op1 = XEXP (addr, 0);
13914 addr_op2 = XEXP (addr, 1);
13915 gcc_assert (REG_P (addr_op1));
13917 if (TARGET_DEBUG_ADDR)
13919 fprintf (stderr, "\nMove plus addr to register %s, mode = %s: ",
13920 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13921 debug_rtx (addr_op2);
13923 rs6000_emit_move (scratch, addr_op2, Pmode);
13924 emit_insn (gen_rtx_SET (VOIDmode,
13925 scratch_or_premodify,
13926 gen_rtx_PLUS (Pmode,
13929 addr = scratch_or_premodify;
13930 scratch_or_premodify = scratch;
13933 else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
13934 || GET_CODE (addr) == CONST_INT || REG_P (addr))
13936 if (TARGET_DEBUG_ADDR)
13938 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13939 rs6000_reg_names[REGNO (scratch_or_premodify)],
13940 GET_MODE_NAME (mode));
13944 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13945 addr = scratch_or_premodify;
13946 scratch_or_premodify = scratch;
13950 gcc_unreachable ();
13955 gcc_unreachable ();
13958 /* If the original address involved a pre-modify that we couldn't use the VSX
13959 memory instruction with update, and we haven't taken care of already,
13960 store the address in the pre-modify register and use that as the
13962 if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
13964 emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
13965 addr = scratch_or_premodify;
13968 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
13969 memory instruction, recreate the AND now, including the clobber which is
13970 generated by the general ANDSI3/ANDDI3 patterns for the
13971 andi. instruction. */
13972 if (and_op2 != NULL_RTX)
13974 if (! legitimate_indirect_address_p (addr, false))
13976 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
13980 if (TARGET_DEBUG_ADDR)
13982 fprintf (stderr, "\nAnd addr to register %s, mode = %s: ",
13983 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13984 debug_rtx (and_op2);
13987 and_rtx = gen_rtx_SET (VOIDmode,
13989 gen_rtx_AND (Pmode,
13993 cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
13994 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13995 gen_rtvec (2, and_rtx, cc_clobber)));
13999 /* Adjust the address if it changed. */
14000 if (addr != XEXP (mem, 0))
14002 mem = change_address (mem, mode, addr);
14003 if (TARGET_DEBUG_ADDR)
14004 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14007 /* Now create the move. */
14009 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14011 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14016 /* Convert reloads involving 64-bit gprs and misaligned offset
14017 addressing to use indirect addressing. */
14020 rs6000_secondary_reload_ppc64 (rtx reg, rtx mem, rtx scratch, bool store_p)
14022 int regno = true_regnum (reg);
14023 enum reg_class rclass;
14025 rtx scratch_or_premodify = scratch;
14027 if (TARGET_DEBUG_ADDR)
14029 fprintf (stderr, "\nrs6000_secondary_reload_ppc64, type = %s\n",
14030 store_p ? "store" : "load");
14031 fprintf (stderr, "reg:\n");
14033 fprintf (stderr, "mem:\n");
14035 fprintf (stderr, "scratch:\n");
14036 debug_rtx (scratch);
14039 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
14040 gcc_assert (GET_CODE (mem) == MEM);
14041 rclass = REGNO_REG_CLASS (regno);
14042 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
14043 addr = XEXP (mem, 0);
14045 if (GET_CODE (addr) == PRE_MODIFY)
14047 scratch_or_premodify = XEXP (addr, 0);
14048 gcc_assert (REG_P (scratch_or_premodify));
14049 addr = XEXP (addr, 1);
14051 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
14053 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14055 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
14057 /* Now create the move. */
14059 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14061 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14066 /* Allocate a 64-bit stack slot to be used for copying SDmode
14067 values through if this function has any SDmode references. */
14070 rs6000_alloc_sdmode_stack_slot (void)
14074 gimple_stmt_iterator gsi;
14076 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
14079 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
14081 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
14084 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14085 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14091 /* Check for any SDmode parameters of the function. */
14092 for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
14094 if (TREE_TYPE (t) == error_mark_node)
14097 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
14098 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
14100 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14101 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14109 rs6000_instantiate_decls (void)
14111 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
14112 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
14115 /* Given an rtx X being reloaded into a reg required to be
14116 in class CLASS, return the class of reg to actually use.
14117 In general this is just CLASS; but on some machines
14118 in some cases it is preferable to use a more restrictive class.
14120 On the RS/6000, we have to return NO_REGS when we want to reload a
14121 floating-point CONST_DOUBLE to force it to be copied to memory.
14123 We also don't want to reload integer values into floating-point
14124 registers if we can at all help it. In fact, this can
14125 cause reload to die, if it tries to generate a reload of CTR
14126 into a FP register and discovers it doesn't have the memory location
14129 ??? Would it be a good idea to have reload do the converse, that is
14130 try to reload floating modes into FP registers if possible?
14133 static enum reg_class
14134 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
14136 enum machine_mode mode = GET_MODE (x);
14138 if (VECTOR_UNIT_VSX_P (mode)
14139 && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
14142 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
14143 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
14144 && easy_vector_constant (x, mode))
14145 return ALTIVEC_REGS;
14147 if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
14150 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
14151 return GENERAL_REGS;
14153 /* For VSX, prefer the traditional registers for 64-bit values because we can
14154 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14155 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14156 prefer Altivec loads.. */
14157 if (rclass == VSX_REGS)
14159 if (GET_MODE_SIZE (mode) <= 8)
14162 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
14163 return ALTIVEC_REGS;
14171 /* Debug version of rs6000_preferred_reload_class. */
14172 static enum reg_class
14173 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
14175 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
14178 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14180 reg_class_names[ret], reg_class_names[rclass],
14181 GET_MODE_NAME (GET_MODE (x)));
14187 /* If we are copying between FP or AltiVec registers and anything else, we need
14188 a memory location. The exception is when we are targeting ppc64 and the
14189 move to/from fpr to gpr instructions are available. Also, under VSX, you
14190 can copy vector registers from the FP register set to the Altivec register
14191 set and vice versa. */
14194 rs6000_secondary_memory_needed (enum reg_class class1,
14195 enum reg_class class2,
14196 enum machine_mode mode)
14198 if (class1 == class2)
14201 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14202 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14203 between these classes. But we need memory for other things that can go in
14204 FLOAT_REGS like SFmode. */
14206 && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
14207 && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
14208 || class1 == FLOAT_REGS))
14209 return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
14210 && class2 != FLOAT_REGS);
14212 if (class1 == VSX_REGS || class2 == VSX_REGS)
14215 if (class1 == FLOAT_REGS
14216 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14217 || ((mode != DFmode)
14218 && (mode != DDmode)
14219 && (mode != DImode))))
14222 if (class2 == FLOAT_REGS
14223 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14224 || ((mode != DFmode)
14225 && (mode != DDmode)
14226 && (mode != DImode))))
14229 if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
14235 /* Debug version of rs6000_secondary_memory_needed. */
14237 rs6000_debug_secondary_memory_needed (enum reg_class class1,
14238 enum reg_class class2,
14239 enum machine_mode mode)
14241 bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
14244 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14245 "class2 = %s, mode = %s\n",
14246 ret ? "true" : "false", reg_class_names[class1],
14247 reg_class_names[class2], GET_MODE_NAME (mode));
14252 /* Return the register class of a scratch register needed to copy IN into
14253 or out of a register in RCLASS in MODE. If it can be done directly,
14254 NO_REGS is returned. */
14256 static enum reg_class
14257 rs6000_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
14262 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
14264 && MACHOPIC_INDIRECT
14268 /* We cannot copy a symbolic operand directly into anything
14269 other than BASE_REGS for TARGET_ELF. So indicate that a
14270 register from BASE_REGS is needed as an intermediate
14273 On Darwin, pic addresses require a load from memory, which
14274 needs a base register. */
14275 if (rclass != BASE_REGS
14276 && (GET_CODE (in) == SYMBOL_REF
14277 || GET_CODE (in) == HIGH
14278 || GET_CODE (in) == LABEL_REF
14279 || GET_CODE (in) == CONST))
14283 if (GET_CODE (in) == REG)
14285 regno = REGNO (in);
14286 if (regno >= FIRST_PSEUDO_REGISTER)
14288 regno = true_regnum (in);
14289 if (regno >= FIRST_PSEUDO_REGISTER)
14293 else if (GET_CODE (in) == SUBREG)
14295 regno = true_regnum (in);
14296 if (regno >= FIRST_PSEUDO_REGISTER)
14302 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14304 if (rclass == GENERAL_REGS || rclass == BASE_REGS
14305 || (regno >= 0 && INT_REGNO_P (regno)))
14308 /* Constants, memory, and FP registers can go into FP registers. */
14309 if ((regno == -1 || FP_REGNO_P (regno))
14310 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
14311 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
14313 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14316 && (regno == -1 || VSX_REGNO_P (regno))
14317 && VSX_REG_CLASS_P (rclass))
14320 /* Memory, and AltiVec registers can go into AltiVec registers. */
14321 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
14322 && rclass == ALTIVEC_REGS)
14325 /* We can copy among the CR registers. */
14326 if ((rclass == CR_REGS || rclass == CR0_REGS)
14327 && regno >= 0 && CR_REGNO_P (regno))
14330 /* Otherwise, we need GENERAL_REGS. */
14331 return GENERAL_REGS;
14334 /* Debug version of rs6000_secondary_reload_class. */
14335 static enum reg_class
14336 rs6000_debug_secondary_reload_class (enum reg_class rclass,
14337 enum machine_mode mode, rtx in)
14339 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
14341 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14342 "mode = %s, input rtx:\n",
14343 reg_class_names[ret], reg_class_names[rclass],
14344 GET_MODE_NAME (mode));
14350 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14353 rs6000_cannot_change_mode_class (enum machine_mode from,
14354 enum machine_mode to,
14355 enum reg_class rclass)
14357 unsigned from_size = GET_MODE_SIZE (from);
14358 unsigned to_size = GET_MODE_SIZE (to);
14360 if (from_size != to_size)
14362 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
14363 return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
14364 && reg_classes_intersect_p (xclass, rclass));
14367 if (TARGET_E500_DOUBLE
14368 && ((((to) == DFmode) + ((from) == DFmode)) == 1
14369 || (((to) == TFmode) + ((from) == TFmode)) == 1
14370 || (((to) == DDmode) + ((from) == DDmode)) == 1
14371 || (((to) == TDmode) + ((from) == TDmode)) == 1
14372 || (((to) == DImode) + ((from) == DImode)) == 1))
14375 /* Since the VSX register set includes traditional floating point registers
14376 and altivec registers, just check for the size being different instead of
14377 trying to check whether the modes are vector modes. Otherwise it won't
14378 allow say DF and DI to change classes. */
14379 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
14380 return (from_size != 8 && from_size != 16);
14382 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
14383 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
14386 if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
14387 && reg_classes_intersect_p (GENERAL_REGS, rclass))
14393 /* Debug version of rs6000_cannot_change_mode_class. */
14395 rs6000_debug_cannot_change_mode_class (enum machine_mode from,
14396 enum machine_mode to,
14397 enum reg_class rclass)
14399 bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
14402 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14403 "to = %s, rclass = %s\n",
14404 ret ? "true" : "false",
14405 GET_MODE_NAME (from), GET_MODE_NAME (to),
14406 reg_class_names[rclass]);
14411 /* Given a comparison operation, return the bit number in CCR to test. We
14412 know this is a valid comparison.
14414 SCC_P is 1 if this is for an scc. That means that %D will have been
14415 used instead of %C, so the bits will be in different places.
14417 Return -1 if OP isn't a valid comparison for some reason. */
14420 ccr_bit (rtx op, int scc_p)
14422 enum rtx_code code = GET_CODE (op);
14423 enum machine_mode cc_mode;
14428 if (!COMPARISON_P (op))
14431 reg = XEXP (op, 0);
14433 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
14435 cc_mode = GET_MODE (reg);
14436 cc_regnum = REGNO (reg);
14437 base_bit = 4 * (cc_regnum - CR0_REGNO);
14439 validate_condition_mode (code, cc_mode);
14441 /* When generating a sCOND operation, only positive conditions are
14444 || code == EQ || code == GT || code == LT || code == UNORDERED
14445 || code == GTU || code == LTU);
14450 return scc_p ? base_bit + 3 : base_bit + 2;
14452 return base_bit + 2;
14453 case GT: case GTU: case UNLE:
14454 return base_bit + 1;
14455 case LT: case LTU: case UNGE:
14457 case ORDERED: case UNORDERED:
14458 return base_bit + 3;
14461 /* If scc, we will have done a cror to put the bit in the
14462 unordered position. So test that bit. For integer, this is ! LT
14463 unless this is an scc insn. */
14464 return scc_p ? base_bit + 3 : base_bit;
14467 return scc_p ? base_bit + 3 : base_bit + 1;
14470 gcc_unreachable ();
14474 /* Return the GOT register. */
14477 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
14479 /* The second flow pass currently (June 1999) can't update
14480 regs_ever_live without disturbing other parts of the compiler, so
14481 update it here to make the prolog/epilogue code happy. */
14482 if (!can_create_pseudo_p ()
14483 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
14484 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
14486 crtl->uses_pic_offset_table = 1;
14488 return pic_offset_table_rtx;
14491 static rs6000_stack_t stack_info;
14493 /* Function to init struct machine_function.
14494 This will be called, via a pointer variable,
14495 from push_function_context. */
14497 static struct machine_function *
14498 rs6000_init_machine_status (void)
14500 stack_info.reload_completed = 0;
14501 return ggc_alloc_cleared_machine_function ();
14504 /* These macros test for integers and extract the low-order bits. */
14506 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14507 && GET_MODE (X) == VOIDmode)
14509 #define INT_LOWPART(X) \
14510 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14513 extract_MB (rtx op)
14516 unsigned long val = INT_LOWPART (op);
14518 /* If the high bit is zero, the value is the first 1 bit we find
14520 if ((val & 0x80000000) == 0)
14522 gcc_assert (val & 0xffffffff);
14525 while (((val <<= 1) & 0x80000000) == 0)
14530 /* If the high bit is set and the low bit is not, or the mask is all
14531 1's, the value is zero. */
14532 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
14535 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14538 while (((val >>= 1) & 1) != 0)
14545 extract_ME (rtx op)
14548 unsigned long val = INT_LOWPART (op);
14550 /* If the low bit is zero, the value is the first 1 bit we find from
14552 if ((val & 1) == 0)
14554 gcc_assert (val & 0xffffffff);
14557 while (((val >>= 1) & 1) == 0)
14563 /* If the low bit is set and the high bit is not, or the mask is all
14564 1's, the value is 31. */
14565 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
14568 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14571 while (((val <<= 1) & 0x80000000) != 0)
14577 /* Locate some local-dynamic symbol still in use by this function
14578 so that we can print its name in some tls_ld pattern. */
14580 static const char *
14581 rs6000_get_some_local_dynamic_name (void)
14585 if (cfun->machine->some_ld_name)
14586 return cfun->machine->some_ld_name;
14588 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
14590 && for_each_rtx (&PATTERN (insn),
14591 rs6000_get_some_local_dynamic_name_1, 0))
14592 return cfun->machine->some_ld_name;
14594 gcc_unreachable ();
14597 /* Helper function for rs6000_get_some_local_dynamic_name. */
14600 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
14604 if (GET_CODE (x) == SYMBOL_REF)
14606 const char *str = XSTR (x, 0);
14607 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
14609 cfun->machine->some_ld_name = str;
14617 /* Write out a function code label. */
14620 rs6000_output_function_entry (FILE *file, const char *fname)
14622 if (fname[0] != '.')
14624 switch (DEFAULT_ABI)
14627 gcc_unreachable ();
14633 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
14642 RS6000_OUTPUT_BASENAME (file, fname);
14645 /* Print an operand. Recognize special options, documented below. */
14648 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14649 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14651 #define SMALL_DATA_RELOC "sda21"
14652 #define SMALL_DATA_REG 0
14656 print_operand (FILE *file, rtx x, int code)
14660 unsigned HOST_WIDE_INT uval;
14665 /* Write out an instruction after the call which may be replaced
14666 with glue code by the loader. This depends on the AIX version. */
14667 asm_fprintf (file, RS6000_CALL_GLUE);
14670 /* %a is output_address. */
14673 /* If X is a constant integer whose low-order 5 bits are zero,
14674 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
14675 in the AIX assembler where "sri" with a zero shift count
14676 writes a trash instruction. */
14677 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
14684 /* If constant, low-order 16 bits of constant, unsigned.
14685 Otherwise, write normally. */
14687 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
14689 print_operand (file, x, 0);
14693 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14694 for 64-bit mask direction. */
14695 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
14698 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14702 /* X is a CR register. Print the number of the GT bit of the CR. */
14703 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14704 output_operand_lossage ("invalid %%c value");
14706 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
14710 /* Like 'J' but get to the GT bit only. */
14711 gcc_assert (GET_CODE (x) == REG);
14713 /* Bit 1 is GT bit. */
14714 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
14716 /* Add one for shift count in rlinm for scc. */
14717 fprintf (file, "%d", i + 1);
14721 /* X is a CR register. Print the number of the EQ bit of the CR */
14722 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14723 output_operand_lossage ("invalid %%E value");
14725 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
14729 /* X is a CR register. Print the shift count needed to move it
14730 to the high-order four bits. */
14731 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14732 output_operand_lossage ("invalid %%f value");
14734 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
14738 /* Similar, but print the count for the rotate in the opposite
14740 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14741 output_operand_lossage ("invalid %%F value");
14743 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
14747 /* X is a constant integer. If it is negative, print "m",
14748 otherwise print "z". This is to make an aze or ame insn. */
14749 if (GET_CODE (x) != CONST_INT)
14750 output_operand_lossage ("invalid %%G value");
14751 else if (INTVAL (x) >= 0)
14758 /* If constant, output low-order five bits. Otherwise, write
14761 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
14763 print_operand (file, x, 0);
14767 /* If constant, output low-order six bits. Otherwise, write
14770 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
14772 print_operand (file, x, 0);
14776 /* Print `i' if this is a constant, else nothing. */
14782 /* Write the bit number in CCR for jump. */
14783 i = ccr_bit (x, 0);
14785 output_operand_lossage ("invalid %%j code");
14787 fprintf (file, "%d", i);
14791 /* Similar, but add one for shift count in rlinm for scc and pass
14792 scc flag to `ccr_bit'. */
14793 i = ccr_bit (x, 1);
14795 output_operand_lossage ("invalid %%J code");
14797 /* If we want bit 31, write a shift count of zero, not 32. */
14798 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14802 /* X must be a constant. Write the 1's complement of the
14805 output_operand_lossage ("invalid %%k value");
14807 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
14811 /* X must be a symbolic constant on ELF. Write an
14812 expression suitable for an 'addi' that adds in the low 16
14813 bits of the MEM. */
14814 if (GET_CODE (x) == CONST)
14816 if (GET_CODE (XEXP (x, 0)) != PLUS
14817 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
14818 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
14819 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
14820 output_operand_lossage ("invalid %%K value");
14822 print_operand_address (file, x);
14823 fputs ("@l", file);
14826 /* %l is output_asm_label. */
14829 /* Write second word of DImode or DFmode reference. Works on register
14830 or non-indexed memory only. */
14831 if (GET_CODE (x) == REG)
14832 fputs (reg_names[REGNO (x) + 1], file);
14833 else if (GET_CODE (x) == MEM)
14835 /* Handle possible auto-increment. Since it is pre-increment and
14836 we have already done it, we can just use an offset of word. */
14837 if (GET_CODE (XEXP (x, 0)) == PRE_INC
14838 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
14839 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
14841 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
14842 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
14845 output_address (XEXP (adjust_address_nv (x, SImode,
14849 if (small_data_operand (x, GET_MODE (x)))
14850 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
14851 reg_names[SMALL_DATA_REG]);
14856 /* MB value for a mask operand. */
14857 if (! mask_operand (x, SImode))
14858 output_operand_lossage ("invalid %%m value");
14860 fprintf (file, "%d", extract_MB (x));
14864 /* ME value for a mask operand. */
14865 if (! mask_operand (x, SImode))
14866 output_operand_lossage ("invalid %%M value");
14868 fprintf (file, "%d", extract_ME (x));
14871 /* %n outputs the negative of its operand. */
14874 /* Write the number of elements in the vector times 4. */
14875 if (GET_CODE (x) != PARALLEL)
14876 output_operand_lossage ("invalid %%N value");
14878 fprintf (file, "%d", XVECLEN (x, 0) * 4);
14882 /* Similar, but subtract 1 first. */
14883 if (GET_CODE (x) != PARALLEL)
14884 output_operand_lossage ("invalid %%O value");
14886 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
14890 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14892 || INT_LOWPART (x) < 0
14893 || (i = exact_log2 (INT_LOWPART (x))) < 0)
14894 output_operand_lossage ("invalid %%p value");
14896 fprintf (file, "%d", i);
14900 /* The operand must be an indirect memory reference. The result
14901 is the register name. */
14902 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
14903 || REGNO (XEXP (x, 0)) >= 32)
14904 output_operand_lossage ("invalid %%P value");
14906 fputs (reg_names[REGNO (XEXP (x, 0))], file);
14910 /* This outputs the logical code corresponding to a boolean
14911 expression. The expression may have one or both operands
14912 negated (if one, only the first one). For condition register
14913 logical operations, it will also treat the negated
14914 CR codes as NOTs, but not handle NOTs of them. */
14916 const char *const *t = 0;
14918 enum rtx_code code = GET_CODE (x);
14919 static const char * const tbl[3][3] = {
14920 { "and", "andc", "nor" },
14921 { "or", "orc", "nand" },
14922 { "xor", "eqv", "xor" } };
14926 else if (code == IOR)
14928 else if (code == XOR)
14931 output_operand_lossage ("invalid %%q value");
14933 if (GET_CODE (XEXP (x, 0)) != NOT)
14937 if (GET_CODE (XEXP (x, 1)) == NOT)
14955 /* X is a CR register. Print the mask for `mtcrf'. */
14956 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14957 output_operand_lossage ("invalid %%R value");
14959 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
14963 /* Low 5 bits of 32 - value */
14965 output_operand_lossage ("invalid %%s value");
14967 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
14971 /* PowerPC64 mask position. All 0's is excluded.
14972 CONST_INT 32-bit mask is considered sign-extended so any
14973 transition must occur within the CONST_INT, not on the boundary. */
14974 if (! mask64_operand (x, DImode))
14975 output_operand_lossage ("invalid %%S value");
14977 uval = INT_LOWPART (x);
14979 if (uval & 1) /* Clear Left */
14981 #if HOST_BITS_PER_WIDE_INT > 64
14982 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
14986 else /* Clear Right */
14989 #if HOST_BITS_PER_WIDE_INT > 64
14990 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
14996 gcc_assert (i >= 0);
14997 fprintf (file, "%d", i);
15001 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
15002 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
15004 /* Bit 3 is OV bit. */
15005 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
15007 /* If we want bit 31, write a shift count of zero, not 32. */
15008 fprintf (file, "%d", i == 31 ? 0 : i + 1);
15012 /* Print the symbolic name of a branch target register. */
15013 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
15014 && REGNO (x) != CTR_REGNO))
15015 output_operand_lossage ("invalid %%T value");
15016 else if (REGNO (x) == LR_REGNO)
15017 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
15019 fputs ("ctr", file);
15023 /* High-order 16 bits of constant for use in unsigned operand. */
15025 output_operand_lossage ("invalid %%u value");
15027 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15028 (INT_LOWPART (x) >> 16) & 0xffff);
15032 /* High-order 16 bits of constant for use in signed operand. */
15034 output_operand_lossage ("invalid %%v value");
15036 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15037 (INT_LOWPART (x) >> 16) & 0xffff);
15041 /* Print `u' if this has an auto-increment or auto-decrement. */
15042 if (GET_CODE (x) == MEM
15043 && (GET_CODE (XEXP (x, 0)) == PRE_INC
15044 || GET_CODE (XEXP (x, 0)) == PRE_DEC
15045 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
15050 /* Print the trap code for this operand. */
15051 switch (GET_CODE (x))
15054 fputs ("eq", file); /* 4 */
15057 fputs ("ne", file); /* 24 */
15060 fputs ("lt", file); /* 16 */
15063 fputs ("le", file); /* 20 */
15066 fputs ("gt", file); /* 8 */
15069 fputs ("ge", file); /* 12 */
15072 fputs ("llt", file); /* 2 */
15075 fputs ("lle", file); /* 6 */
15078 fputs ("lgt", file); /* 1 */
15081 fputs ("lge", file); /* 5 */
15084 gcc_unreachable ();
15089 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
15092 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
15093 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
15095 print_operand (file, x, 0);
15099 /* MB value for a PowerPC64 rldic operand. */
15100 val = (GET_CODE (x) == CONST_INT
15101 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
15106 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
15107 if ((val <<= 1) < 0)
15110 #if HOST_BITS_PER_WIDE_INT == 32
15111 if (GET_CODE (x) == CONST_INT && i >= 0)
15112 i += 32; /* zero-extend high-part was all 0's */
15113 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
15115 val = CONST_DOUBLE_LOW (x);
15121 for ( ; i < 64; i++)
15122 if ((val <<= 1) < 0)
15127 fprintf (file, "%d", i + 1);
15131 /* X is a FPR or Altivec register used in a VSX context. */
15132 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
15133 output_operand_lossage ("invalid %%x value");
15136 int reg = REGNO (x);
15137 int vsx_reg = (FP_REGNO_P (reg)
15139 : reg - FIRST_ALTIVEC_REGNO + 32);
15141 #ifdef TARGET_REGNAMES
15142 if (TARGET_REGNAMES)
15143 fprintf (file, "%%vs%d", vsx_reg);
15146 fprintf (file, "%d", vsx_reg);
15151 if (GET_CODE (x) == MEM
15152 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
15153 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
15154 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
15159 /* Like 'L', for third word of TImode */
15160 if (GET_CODE (x) == REG)
15161 fputs (reg_names[REGNO (x) + 2], file);
15162 else if (GET_CODE (x) == MEM)
15164 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15165 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15166 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
15167 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15168 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
15170 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
15171 if (small_data_operand (x, GET_MODE (x)))
15172 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15173 reg_names[SMALL_DATA_REG]);
15178 /* X is a SYMBOL_REF. Write out the name preceded by a
15179 period and without any trailing data in brackets. Used for function
15180 names. If we are configured for System V (or the embedded ABI) on
15181 the PowerPC, do not emit the period, since those systems do not use
15182 TOCs and the like. */
15183 gcc_assert (GET_CODE (x) == SYMBOL_REF);
15185 /* Mark the decl as referenced so that cgraph will output the
15187 if (SYMBOL_REF_DECL (x))
15188 mark_decl_referenced (SYMBOL_REF_DECL (x));
15190 /* For macho, check to see if we need a stub. */
15193 const char *name = XSTR (x, 0);
15195 if (darwin_emit_branch_islands
15196 && MACHOPIC_INDIRECT
15197 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
15198 name = machopic_indirection_name (x, /*stub_p=*/true);
15200 assemble_name (file, name);
15202 else if (!DOT_SYMBOLS)
15203 assemble_name (file, XSTR (x, 0));
15205 rs6000_output_function_entry (file, XSTR (x, 0));
15209 /* Like 'L', for last word of TImode. */
15210 if (GET_CODE (x) == REG)
15211 fputs (reg_names[REGNO (x) + 3], file);
15212 else if (GET_CODE (x) == MEM)
15214 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15215 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15216 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
15217 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15218 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
15220 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
15221 if (small_data_operand (x, GET_MODE (x)))
15222 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15223 reg_names[SMALL_DATA_REG]);
15227 /* Print AltiVec or SPE memory operand. */
15232 gcc_assert (GET_CODE (x) == MEM);
15236 /* Ugly hack because %y is overloaded. */
15237 if ((TARGET_SPE || TARGET_E500_DOUBLE)
15238 && (GET_MODE_SIZE (GET_MODE (x)) == 8
15239 || GET_MODE (x) == TFmode
15240 || GET_MODE (x) == TImode))
15242 /* Handle [reg]. */
15243 if (GET_CODE (tmp) == REG)
15245 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
15248 /* Handle [reg+UIMM]. */
15249 else if (GET_CODE (tmp) == PLUS &&
15250 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
15254 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
15256 x = INTVAL (XEXP (tmp, 1));
15257 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
15261 /* Fall through. Must be [reg+reg]. */
15263 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
15264 && GET_CODE (tmp) == AND
15265 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
15266 && INTVAL (XEXP (tmp, 1)) == -16)
15267 tmp = XEXP (tmp, 0);
15268 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
15269 && GET_CODE (tmp) == PRE_MODIFY)
15270 tmp = XEXP (tmp, 1);
15271 if (GET_CODE (tmp) == REG)
15272 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
15275 if (!GET_CODE (tmp) == PLUS
15276 || !REG_P (XEXP (tmp, 0))
15277 || !REG_P (XEXP (tmp, 1)))
15279 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15283 if (REGNO (XEXP (tmp, 0)) == 0)
15284 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
15285 reg_names[ REGNO (XEXP (tmp, 0)) ]);
15287 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
15288 reg_names[ REGNO (XEXP (tmp, 1)) ]);
15294 if (GET_CODE (x) == REG)
15295 fprintf (file, "%s", reg_names[REGNO (x)]);
15296 else if (GET_CODE (x) == MEM)
15298 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15299 know the width from the mode. */
15300 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
15301 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
15302 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15303 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
15304 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
15305 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15306 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15307 output_address (XEXP (XEXP (x, 0), 1));
15309 output_address (XEXP (x, 0));
15313 if (toc_relative_expr_p (x))
15314 /* This hack along with a corresponding hack in
15315 rs6000_output_addr_const_extra arranges to output addends
15316 where the assembler expects to find them. eg.
15317 (const (plus (unspec [symbol_ref ("x") tocrel]) 4))
15318 without this hack would be output as "x@toc+4". We
15320 output_addr_const (file, tocrel_base);
15322 output_addr_const (file, x);
15327 assemble_name (file, rs6000_get_some_local_dynamic_name ());
15331 output_operand_lossage ("invalid %%xn code");
15335 /* Print the address of an operand. */
15338 print_operand_address (FILE *file, rtx x)
15340 if (GET_CODE (x) == REG)
15341 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
15342 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
15343 || GET_CODE (x) == LABEL_REF)
15345 output_addr_const (file, x);
15346 if (small_data_operand (x, GET_MODE (x)))
15347 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15348 reg_names[SMALL_DATA_REG]);
15350 gcc_assert (!TARGET_TOC);
15352 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
15354 gcc_assert (REG_P (XEXP (x, 0)));
15355 if (REGNO (XEXP (x, 0)) == 0)
15356 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
15357 reg_names[ REGNO (XEXP (x, 0)) ]);
15359 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
15360 reg_names[ REGNO (XEXP (x, 1)) ]);
15362 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
15363 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
15364 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
15366 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
15367 && CONSTANT_P (XEXP (x, 1)))
15369 fprintf (file, "lo16(");
15370 output_addr_const (file, XEXP (x, 1));
15371 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15374 else if (legitimate_constant_pool_address_p (x, QImode, true))
15376 /* This hack along with a corresponding hack in
15377 rs6000_output_addr_const_extra arranges to output addends
15378 where the assembler expects to find them. eg.
15380 . (const (plus (unspec [symbol_ref ("x") tocrel]) 8)))
15381 without this hack would be output as "x@toc+8@l(9)". We
15382 want "x+8@toc@l(9)". */
15383 output_addr_const (file, tocrel_base);
15384 if (GET_CODE (x) == LO_SUM)
15385 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15387 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
15390 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
15391 && CONSTANT_P (XEXP (x, 1)))
15393 output_addr_const (file, XEXP (x, 1));
15394 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15398 gcc_unreachable ();
15401 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15404 rs6000_output_addr_const_extra (FILE *file, rtx x)
15406 if (GET_CODE (x) == UNSPEC)
15407 switch (XINT (x, 1))
15409 case UNSPEC_TOCREL:
15410 gcc_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF);
15411 output_addr_const (file, XVECEXP (x, 0, 0));
15412 if (x == tocrel_base && tocrel_offset != const0_rtx)
15414 if (INTVAL (tocrel_offset) >= 0)
15415 fprintf (file, "+");
15416 output_addr_const (file, tocrel_offset);
15418 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
15421 assemble_name (file, toc_label_name);
15423 else if (TARGET_ELF)
15424 fputs ("@toc", file);
15428 case UNSPEC_MACHOPIC_OFFSET:
15429 output_addr_const (file, XVECEXP (x, 0, 0));
15431 machopic_output_function_base_name (file);
15438 /* Target hook for assembling integer objects. The PowerPC version has
15439 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15440 is defined. It also needs to handle DI-mode objects on 64-bit
15444 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
15446 #ifdef RELOCATABLE_NEEDS_FIXUP
15447 /* Special handling for SI values. */
15448 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
15450 static int recurse = 0;
15452 /* For -mrelocatable, we mark all addresses that need to be fixed up
15453 in the .fixup section. */
15454 if (TARGET_RELOCATABLE
15455 && in_section != toc_section
15456 && in_section != text_section
15457 && !unlikely_text_section_p (in_section)
15459 && GET_CODE (x) != CONST_INT
15460 && GET_CODE (x) != CONST_DOUBLE
15466 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
15468 ASM_OUTPUT_LABEL (asm_out_file, buf);
15469 fprintf (asm_out_file, "\t.long\t(");
15470 output_addr_const (asm_out_file, x);
15471 fprintf (asm_out_file, ")@fixup\n");
15472 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
15473 ASM_OUTPUT_ALIGN (asm_out_file, 2);
15474 fprintf (asm_out_file, "\t.long\t");
15475 assemble_name (asm_out_file, buf);
15476 fprintf (asm_out_file, "\n\t.previous\n");
15480 /* Remove initial .'s to turn a -mcall-aixdesc function
15481 address into the address of the descriptor, not the function
15483 else if (GET_CODE (x) == SYMBOL_REF
15484 && XSTR (x, 0)[0] == '.'
15485 && DEFAULT_ABI == ABI_AIX)
15487 const char *name = XSTR (x, 0);
15488 while (*name == '.')
15491 fprintf (asm_out_file, "\t.long\t%s\n", name);
15495 #endif /* RELOCATABLE_NEEDS_FIXUP */
15496 return default_assemble_integer (x, size, aligned_p);
15499 #if defined (HAVE_GAS_HIDDEN) && !defined (TARGET_MACHO)
15500 /* Emit an assembler directive to set symbol visibility for DECL to
15501 VISIBILITY_TYPE. */
15504 rs6000_assemble_visibility (tree decl, int vis)
15506 /* Functions need to have their entry point symbol visibility set as
15507 well as their descriptor symbol visibility. */
15508 if (DEFAULT_ABI == ABI_AIX
15510 && TREE_CODE (decl) == FUNCTION_DECL)
15512 static const char * const visibility_types[] = {
15513 NULL, "internal", "hidden", "protected"
15516 const char *name, *type;
15518 name = ((* targetm.strip_name_encoding)
15519 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
15520 type = visibility_types[vis];
15522 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
15523 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
15526 default_assemble_visibility (decl, vis);
15531 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
15533 /* Reversal of FP compares takes care -- an ordered compare
15534 becomes an unordered compare and vice versa. */
15535 if (mode == CCFPmode
15536 && (!flag_finite_math_only
15537 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
15538 || code == UNEQ || code == LTGT))
15539 return reverse_condition_maybe_unordered (code);
15541 return reverse_condition (code);
15544 /* Generate a compare for CODE. Return a brand-new rtx that
15545 represents the result of the compare. */
15548 rs6000_generate_compare (rtx cmp, enum machine_mode mode)
15550 enum machine_mode comp_mode;
15551 rtx compare_result;
15552 enum rtx_code code = GET_CODE (cmp);
15553 rtx op0 = XEXP (cmp, 0);
15554 rtx op1 = XEXP (cmp, 1);
15556 if (FLOAT_MODE_P (mode))
15557 comp_mode = CCFPmode;
15558 else if (code == GTU || code == LTU
15559 || code == GEU || code == LEU)
15560 comp_mode = CCUNSmode;
15561 else if ((code == EQ || code == NE)
15562 && GET_CODE (op0) == SUBREG
15563 && GET_CODE (op1) == SUBREG
15564 && SUBREG_PROMOTED_UNSIGNED_P (op0)
15565 && SUBREG_PROMOTED_UNSIGNED_P (op1))
15566 /* These are unsigned values, perhaps there will be a later
15567 ordering compare that can be shared with this one.
15568 Unfortunately we cannot detect the signedness of the operands
15569 for non-subregs. */
15570 comp_mode = CCUNSmode;
15572 comp_mode = CCmode;
15574 /* First, the compare. */
15575 compare_result = gen_reg_rtx (comp_mode);
15577 /* E500 FP compare instructions on the GPRs. Yuck! */
15578 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
15579 && FLOAT_MODE_P (mode))
15581 rtx cmp, or_result, compare_result2;
15582 enum machine_mode op_mode = GET_MODE (op0);
15584 if (op_mode == VOIDmode)
15585 op_mode = GET_MODE (op1);
15587 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15588 This explains the following mess. */
15592 case EQ: case UNEQ: case NE: case LTGT:
15596 cmp = (flag_finite_math_only && !flag_trapping_math)
15597 ? gen_tstsfeq_gpr (compare_result, op0, op1)
15598 : gen_cmpsfeq_gpr (compare_result, op0, op1);
15602 cmp = (flag_finite_math_only && !flag_trapping_math)
15603 ? gen_tstdfeq_gpr (compare_result, op0, op1)
15604 : gen_cmpdfeq_gpr (compare_result, op0, op1);
15608 cmp = (flag_finite_math_only && !flag_trapping_math)
15609 ? gen_tsttfeq_gpr (compare_result, op0, op1)
15610 : gen_cmptfeq_gpr (compare_result, op0, op1);
15614 gcc_unreachable ();
15618 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
15622 cmp = (flag_finite_math_only && !flag_trapping_math)
15623 ? gen_tstsfgt_gpr (compare_result, op0, op1)
15624 : gen_cmpsfgt_gpr (compare_result, op0, op1);
15628 cmp = (flag_finite_math_only && !flag_trapping_math)
15629 ? gen_tstdfgt_gpr (compare_result, op0, op1)
15630 : gen_cmpdfgt_gpr (compare_result, op0, op1);
15634 cmp = (flag_finite_math_only && !flag_trapping_math)
15635 ? gen_tsttfgt_gpr (compare_result, op0, op1)
15636 : gen_cmptfgt_gpr (compare_result, op0, op1);
15640 gcc_unreachable ();
15644 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
15648 cmp = (flag_finite_math_only && !flag_trapping_math)
15649 ? gen_tstsflt_gpr (compare_result, op0, op1)
15650 : gen_cmpsflt_gpr (compare_result, op0, op1);
15654 cmp = (flag_finite_math_only && !flag_trapping_math)
15655 ? gen_tstdflt_gpr (compare_result, op0, op1)
15656 : gen_cmpdflt_gpr (compare_result, op0, op1);
15660 cmp = (flag_finite_math_only && !flag_trapping_math)
15661 ? gen_tsttflt_gpr (compare_result, op0, op1)
15662 : gen_cmptflt_gpr (compare_result, op0, op1);
15666 gcc_unreachable ();
15670 gcc_unreachable ();
15673 /* Synthesize LE and GE from LT/GT || EQ. */
15674 if (code == LE || code == GE || code == LEU || code == GEU)
15680 case LE: code = LT; break;
15681 case GE: code = GT; break;
15682 case LEU: code = LT; break;
15683 case GEU: code = GT; break;
15684 default: gcc_unreachable ();
15687 compare_result2 = gen_reg_rtx (CCFPmode);
15693 cmp = (flag_finite_math_only && !flag_trapping_math)
15694 ? gen_tstsfeq_gpr (compare_result2, op0, op1)
15695 : gen_cmpsfeq_gpr (compare_result2, op0, op1);
15699 cmp = (flag_finite_math_only && !flag_trapping_math)
15700 ? gen_tstdfeq_gpr (compare_result2, op0, op1)
15701 : gen_cmpdfeq_gpr (compare_result2, op0, op1);
15705 cmp = (flag_finite_math_only && !flag_trapping_math)
15706 ? gen_tsttfeq_gpr (compare_result2, op0, op1)
15707 : gen_cmptfeq_gpr (compare_result2, op0, op1);
15711 gcc_unreachable ();
15715 /* OR them together. */
15716 or_result = gen_reg_rtx (CCFPmode);
15717 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
15719 compare_result = or_result;
15724 if (code == NE || code == LTGT)
15734 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15735 CLOBBERs to match cmptf_internal2 pattern. */
15736 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
15737 && GET_MODE (op0) == TFmode
15738 && !TARGET_IEEEQUAD
15739 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
15740 emit_insn (gen_rtx_PARALLEL (VOIDmode,
15742 gen_rtx_SET (VOIDmode,
15744 gen_rtx_COMPARE (comp_mode, op0, op1)),
15745 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15746 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15747 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15748 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15749 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15750 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15751 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15752 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15753 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
15754 else if (GET_CODE (op1) == UNSPEC
15755 && XINT (op1, 1) == UNSPEC_SP_TEST)
15757 rtx op1b = XVECEXP (op1, 0, 0);
15758 comp_mode = CCEQmode;
15759 compare_result = gen_reg_rtx (CCEQmode);
15761 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
15763 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
15766 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
15767 gen_rtx_COMPARE (comp_mode, op0, op1)));
15770 /* Some kinds of FP comparisons need an OR operation;
15771 under flag_finite_math_only we don't bother. */
15772 if (FLOAT_MODE_P (mode)
15773 && !flag_finite_math_only
15774 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
15775 && (code == LE || code == GE
15776 || code == UNEQ || code == LTGT
15777 || code == UNGT || code == UNLT))
15779 enum rtx_code or1, or2;
15780 rtx or1_rtx, or2_rtx, compare2_rtx;
15781 rtx or_result = gen_reg_rtx (CCEQmode);
15785 case LE: or1 = LT; or2 = EQ; break;
15786 case GE: or1 = GT; or2 = EQ; break;
15787 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
15788 case LTGT: or1 = LT; or2 = GT; break;
15789 case UNGT: or1 = UNORDERED; or2 = GT; break;
15790 case UNLT: or1 = UNORDERED; or2 = LT; break;
15791 default: gcc_unreachable ();
15793 validate_condition_mode (or1, comp_mode);
15794 validate_condition_mode (or2, comp_mode);
15795 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
15796 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
15797 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
15798 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
15800 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
15802 compare_result = or_result;
15806 validate_condition_mode (code, GET_MODE (compare_result));
15808 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
15812 /* Emit the RTL for an sISEL pattern. */
15815 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
15817 rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
15821 rs6000_emit_sCOND (enum machine_mode mode, rtx operands[])
15824 enum machine_mode op_mode;
15825 enum rtx_code cond_code;
15826 rtx result = operands[0];
15828 if (TARGET_ISEL && (mode == SImode || mode == DImode))
15830 rs6000_emit_sISEL (mode, operands);
15834 condition_rtx = rs6000_generate_compare (operands[1], mode);
15835 cond_code = GET_CODE (condition_rtx);
15837 if (FLOAT_MODE_P (mode)
15838 && !TARGET_FPRS && TARGET_HARD_FLOAT)
15842 PUT_MODE (condition_rtx, SImode);
15843 t = XEXP (condition_rtx, 0);
15845 gcc_assert (cond_code == NE || cond_code == EQ);
15847 if (cond_code == NE)
15848 emit_insn (gen_e500_flip_gt_bit (t, t));
15850 emit_insn (gen_move_from_CR_gt_bit (result, t));
15854 if (cond_code == NE
15855 || cond_code == GE || cond_code == LE
15856 || cond_code == GEU || cond_code == LEU
15857 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
15859 rtx not_result = gen_reg_rtx (CCEQmode);
15860 rtx not_op, rev_cond_rtx;
15861 enum machine_mode cc_mode;
15863 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
15865 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
15866 SImode, XEXP (condition_rtx, 0), const0_rtx);
15867 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
15868 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
15869 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
15872 op_mode = GET_MODE (XEXP (operands[1], 0));
15873 if (op_mode == VOIDmode)
15874 op_mode = GET_MODE (XEXP (operands[1], 1));
15876 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
15878 PUT_MODE (condition_rtx, DImode);
15879 convert_move (result, condition_rtx, 0);
15883 PUT_MODE (condition_rtx, SImode);
15884 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
15888 /* Emit a branch of kind CODE to location LOC. */
15891 rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
15893 rtx condition_rtx, loc_ref;
15895 condition_rtx = rs6000_generate_compare (operands[0], mode);
15896 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
15897 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
15898 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
15899 loc_ref, pc_rtx)));
15902 /* Return the string to output a conditional branch to LABEL, which is
15903 the operand number of the label, or -1 if the branch is really a
15904 conditional return.
15906 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15907 condition code register and its mode specifies what kind of
15908 comparison we made.
15910 REVERSED is nonzero if we should reverse the sense of the comparison.
15912 INSN is the insn. */
15915 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
15917 static char string[64];
15918 enum rtx_code code = GET_CODE (op);
15919 rtx cc_reg = XEXP (op, 0);
15920 enum machine_mode mode = GET_MODE (cc_reg);
15921 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
15922 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
15923 int really_reversed = reversed ^ need_longbranch;
15929 validate_condition_mode (code, mode);
15931 /* Work out which way this really branches. We could use
15932 reverse_condition_maybe_unordered here always but this
15933 makes the resulting assembler clearer. */
15934 if (really_reversed)
15936 /* Reversal of FP compares takes care -- an ordered compare
15937 becomes an unordered compare and vice versa. */
15938 if (mode == CCFPmode)
15939 code = reverse_condition_maybe_unordered (code);
15941 code = reverse_condition (code);
15944 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
15946 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
15951 /* Opposite of GT. */
15960 gcc_unreachable ();
15966 /* Not all of these are actually distinct opcodes, but
15967 we distinguish them for clarity of the resulting assembler. */
15968 case NE: case LTGT:
15969 ccode = "ne"; break;
15970 case EQ: case UNEQ:
15971 ccode = "eq"; break;
15973 ccode = "ge"; break;
15974 case GT: case GTU: case UNGT:
15975 ccode = "gt"; break;
15977 ccode = "le"; break;
15978 case LT: case LTU: case UNLT:
15979 ccode = "lt"; break;
15980 case UNORDERED: ccode = "un"; break;
15981 case ORDERED: ccode = "nu"; break;
15982 case UNGE: ccode = "nl"; break;
15983 case UNLE: ccode = "ng"; break;
15985 gcc_unreachable ();
15988 /* Maybe we have a guess as to how likely the branch is.
15989 The old mnemonics don't have a way to specify this information. */
15991 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
15992 if (note != NULL_RTX)
15994 /* PROB is the difference from 50%. */
15995 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
15997 /* Only hint for highly probable/improbable branches on newer
15998 cpus as static prediction overrides processor dynamic
15999 prediction. For older cpus we may as well always hint, but
16000 assume not taken for branches that are very close to 50% as a
16001 mispredicted taken branch is more expensive than a
16002 mispredicted not-taken branch. */
16003 if (rs6000_always_hint
16004 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
16005 && br_prob_note_reliable_p (note)))
16007 if (abs (prob) > REG_BR_PROB_BASE / 20
16008 && ((prob > 0) ^ need_longbranch))
16016 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
16018 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
16020 /* We need to escape any '%' characters in the reg_names string.
16021 Assume they'd only be the first character.... */
16022 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
16024 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
16028 /* If the branch distance was too far, we may have to use an
16029 unconditional branch to go the distance. */
16030 if (need_longbranch)
16031 s += sprintf (s, ",$+8\n\tb %s", label);
16033 s += sprintf (s, ",%s", label);
16039 /* Return the string to flip the GT bit on a CR. */
16041 output_e500_flip_gt_bit (rtx dst, rtx src)
16043 static char string[64];
16046 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
16047 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
16050 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
16051 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
16053 sprintf (string, "crnot %d,%d", a, b);
16057 /* Return insn for VSX or Altivec comparisons. */
16060 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
16063 enum machine_mode mode = GET_MODE (op0);
16071 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
16077 mask = gen_reg_rtx (mode);
16078 emit_insn (gen_rtx_SET (VOIDmode,
16080 gen_rtx_fmt_ee (code, mode, op0, op1)));
16087 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16088 DMODE is expected destination mode. This is a recursive function. */
16091 rs6000_emit_vector_compare (enum rtx_code rcode,
16093 enum machine_mode dmode)
16096 bool swap_operands = false;
16097 bool try_again = false;
16099 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
16100 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
16102 /* See if the comparison works as is. */
16103 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16111 swap_operands = true;
16116 swap_operands = true;
16124 /* Invert condition and try again.
16125 e.g., A != B becomes ~(A==B). */
16127 enum rtx_code rev_code;
16128 enum insn_code nor_code;
16131 rev_code = reverse_condition_maybe_unordered (rcode);
16132 if (rev_code == UNKNOWN)
16135 nor_code = optab_handler (one_cmpl_optab, dmode);
16136 if (nor_code == CODE_FOR_nothing)
16139 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
16143 mask = gen_reg_rtx (dmode);
16144 emit_insn (GEN_FCN (nor_code) (mask, mask2));
16152 /* Try GT/GTU/LT/LTU OR EQ */
16155 enum insn_code ior_code;
16156 enum rtx_code new_code;
16177 gcc_unreachable ();
16180 ior_code = optab_handler (ior_optab, dmode);
16181 if (ior_code == CODE_FOR_nothing)
16184 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
16188 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
16192 mask = gen_reg_rtx (dmode);
16193 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
16211 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16216 /* You only get two chances. */
16220 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16221 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16222 operands for the relation operation COND. */
16225 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
16226 rtx cond, rtx cc_op0, rtx cc_op1)
16228 enum machine_mode dest_mode = GET_MODE (dest);
16229 enum machine_mode mask_mode = GET_MODE (cc_op0);
16230 enum rtx_code rcode = GET_CODE (cond);
16231 enum machine_mode cc_mode = CCmode;
16235 bool invert_move = false;
16237 if (VECTOR_UNIT_NONE_P (dest_mode))
16240 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
16241 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
16245 /* Swap operands if we can, and fall back to doing the operation as
16246 specified, and doing a NOR to invert the test. */
16252 /* Invert condition and try again.
16253 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16254 invert_move = true;
16255 rcode = reverse_condition_maybe_unordered (rcode);
16256 if (rcode == UNKNOWN)
16260 /* Mark unsigned tests with CCUNSmode. */
16265 cc_mode = CCUNSmode;
16272 /* Get the vector mask for the given relational operations. */
16273 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
16281 op_true = op_false;
16285 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
16286 CONST0_RTX (dest_mode));
16287 emit_insn (gen_rtx_SET (VOIDmode,
16289 gen_rtx_IF_THEN_ELSE (dest_mode,
16296 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16297 operands of the last comparison is nonzero/true, FALSE_COND if it
16298 is zero/false. Return 0 if the hardware has no such operation. */
16301 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16303 enum rtx_code code = GET_CODE (op);
16304 rtx op0 = XEXP (op, 0);
16305 rtx op1 = XEXP (op, 1);
16306 REAL_VALUE_TYPE c1;
16307 enum machine_mode compare_mode = GET_MODE (op0);
16308 enum machine_mode result_mode = GET_MODE (dest);
16310 bool is_against_zero;
16312 /* These modes should always match. */
16313 if (GET_MODE (op1) != compare_mode
16314 /* In the isel case however, we can use a compare immediate, so
16315 op1 may be a small constant. */
16316 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
16318 if (GET_MODE (true_cond) != result_mode)
16320 if (GET_MODE (false_cond) != result_mode)
16323 /* First, work out if the hardware can do this at all, or
16324 if it's too slow.... */
16325 if (!FLOAT_MODE_P (compare_mode))
16328 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
16331 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
16332 && SCALAR_FLOAT_MODE_P (compare_mode))
16335 is_against_zero = op1 == CONST0_RTX (compare_mode);
16337 /* A floating-point subtract might overflow, underflow, or produce
16338 an inexact result, thus changing the floating-point flags, so it
16339 can't be generated if we care about that. It's safe if one side
16340 of the construct is zero, since then no subtract will be
16342 if (SCALAR_FLOAT_MODE_P (compare_mode)
16343 && flag_trapping_math && ! is_against_zero)
16346 /* Eliminate half of the comparisons by switching operands, this
16347 makes the remaining code simpler. */
16348 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
16349 || code == LTGT || code == LT || code == UNLE)
16351 code = reverse_condition_maybe_unordered (code);
16353 true_cond = false_cond;
16357 /* UNEQ and LTGT take four instructions for a comparison with zero,
16358 it'll probably be faster to use a branch here too. */
16359 if (code == UNEQ && HONOR_NANS (compare_mode))
16362 if (GET_CODE (op1) == CONST_DOUBLE)
16363 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
16365 /* We're going to try to implement comparisons by performing
16366 a subtract, then comparing against zero. Unfortunately,
16367 Inf - Inf is NaN which is not zero, and so if we don't
16368 know that the operand is finite and the comparison
16369 would treat EQ different to UNORDERED, we can't do it. */
16370 if (HONOR_INFINITIES (compare_mode)
16371 && code != GT && code != UNGE
16372 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
16373 /* Constructs of the form (a OP b ? a : b) are safe. */
16374 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
16375 || (! rtx_equal_p (op0, true_cond)
16376 && ! rtx_equal_p (op1, true_cond))))
16379 /* At this point we know we can use fsel. */
16381 /* Reduce the comparison to a comparison against zero. */
16382 if (! is_against_zero)
16384 temp = gen_reg_rtx (compare_mode);
16385 emit_insn (gen_rtx_SET (VOIDmode, temp,
16386 gen_rtx_MINUS (compare_mode, op0, op1)));
16388 op1 = CONST0_RTX (compare_mode);
16391 /* If we don't care about NaNs we can reduce some of the comparisons
16392 down to faster ones. */
16393 if (! HONOR_NANS (compare_mode))
16399 true_cond = false_cond;
16412 /* Now, reduce everything down to a GE. */
16419 temp = gen_reg_rtx (compare_mode);
16420 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16425 temp = gen_reg_rtx (compare_mode);
16426 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
16431 temp = gen_reg_rtx (compare_mode);
16432 emit_insn (gen_rtx_SET (VOIDmode, temp,
16433 gen_rtx_NEG (compare_mode,
16434 gen_rtx_ABS (compare_mode, op0))));
16439 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16440 temp = gen_reg_rtx (result_mode);
16441 emit_insn (gen_rtx_SET (VOIDmode, temp,
16442 gen_rtx_IF_THEN_ELSE (result_mode,
16443 gen_rtx_GE (VOIDmode,
16445 true_cond, false_cond)));
16446 false_cond = true_cond;
16449 temp = gen_reg_rtx (compare_mode);
16450 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16455 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16456 temp = gen_reg_rtx (result_mode);
16457 emit_insn (gen_rtx_SET (VOIDmode, temp,
16458 gen_rtx_IF_THEN_ELSE (result_mode,
16459 gen_rtx_GE (VOIDmode,
16461 true_cond, false_cond)));
16462 true_cond = false_cond;
16465 temp = gen_reg_rtx (compare_mode);
16466 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16471 gcc_unreachable ();
16474 emit_insn (gen_rtx_SET (VOIDmode, dest,
16475 gen_rtx_IF_THEN_ELSE (result_mode,
16476 gen_rtx_GE (VOIDmode,
16478 true_cond, false_cond)));
16482 /* Same as above, but for ints (isel). */
16485 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16487 rtx condition_rtx, cr;
16488 enum machine_mode mode = GET_MODE (dest);
16489 enum rtx_code cond_code;
16490 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
16493 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
16496 /* We still have to do the compare, because isel doesn't do a
16497 compare, it just looks at the CRx bits set by a previous compare
16499 condition_rtx = rs6000_generate_compare (op, mode);
16500 cond_code = GET_CODE (condition_rtx);
16501 cr = XEXP (condition_rtx, 0);
16502 signedp = GET_MODE (cr) == CCmode;
16504 isel_func = (mode == SImode
16505 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
16506 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
16510 case LT: case GT: case LTU: case GTU: case EQ:
16511 /* isel handles these directly. */
16515 /* We need to swap the sense of the comparison. */
16518 true_cond = false_cond;
16520 PUT_CODE (condition_rtx, reverse_condition (cond_code));
16525 false_cond = force_reg (mode, false_cond);
16526 if (true_cond != const0_rtx)
16527 true_cond = force_reg (mode, true_cond);
16529 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
16535 output_isel (rtx *operands)
16537 enum rtx_code code;
16539 code = GET_CODE (operands[1]);
16541 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
16543 gcc_assert (GET_CODE (operands[2]) == REG
16544 && GET_CODE (operands[3]) == REG);
16545 PUT_CODE (operands[1], reverse_condition (code));
16546 return "isel %0,%3,%2,%j1";
16549 return "isel %0,%2,%3,%j1";
16553 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
16555 enum machine_mode mode = GET_MODE (op0);
16559 /* VSX/altivec have direct min/max insns. */
16560 if ((code == SMAX || code == SMIN)
16561 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
16562 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
16564 emit_insn (gen_rtx_SET (VOIDmode,
16566 gen_rtx_fmt_ee (code, mode, op0, op1)));
16570 if (code == SMAX || code == SMIN)
16575 if (code == SMAX || code == UMAX)
16576 target = emit_conditional_move (dest, c, op0, op1, mode,
16577 op0, op1, mode, 0);
16579 target = emit_conditional_move (dest, c, op0, op1, mode,
16580 op1, op0, mode, 0);
16581 gcc_assert (target);
16582 if (target != dest)
16583 emit_move_insn (dest, target);
16586 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16587 COND is true. Mark the jump as unlikely to be taken. */
16590 emit_unlikely_jump (rtx cond, rtx label)
16592 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
16595 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
16596 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
16597 add_reg_note (x, REG_BR_PROB, very_unlikely);
16600 /* A subroutine of the atomic operation splitters. Emit a load-locked
16601 instruction in MODE. */
16604 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
16606 rtx (*fn) (rtx, rtx) = NULL;
16611 fn = gen_load_lockedsi;
16614 fn = gen_load_lockeddi;
16617 gcc_unreachable ();
16619 emit_insn (fn (reg, mem));
16622 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16623 instruction in MODE. */
16626 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
16628 rtx (*fn) (rtx, rtx, rtx) = NULL;
16633 fn = gen_store_conditionalsi;
16636 fn = gen_store_conditionaldi;
16639 gcc_unreachable ();
16642 /* Emit sync before stwcx. to address PPC405 Erratum. */
16643 if (PPC405_ERRATUM77)
16644 emit_insn (gen_hwsync ());
16646 emit_insn (fn (res, mem, val));
16649 /* Expand barriers before and after a load_locked/store_cond sequence. */
16652 rs6000_pre_atomic_barrier (enum memmodel model)
16656 case MEMMODEL_RELAXED:
16657 case MEMMODEL_CONSUME:
16658 case MEMMODEL_ACQUIRE:
16660 case MEMMODEL_RELEASE:
16661 case MEMMODEL_ACQ_REL:
16662 emit_insn (gen_lwsync ());
16664 case MEMMODEL_SEQ_CST:
16665 emit_insn (gen_hwsync ());
16668 gcc_unreachable ();
16673 rs6000_post_atomic_barrier (enum memmodel model)
16677 case MEMMODEL_RELAXED:
16678 case MEMMODEL_CONSUME:
16679 case MEMMODEL_RELEASE:
16681 case MEMMODEL_ACQUIRE:
16682 case MEMMODEL_ACQ_REL:
16683 case MEMMODEL_SEQ_CST:
16684 emit_insn (gen_isync ());
16687 gcc_unreachable ();
16691 /* A subroutine of the various atomic expanders. For sub-word operations,
16692 we must adjust things to operate on SImode. Given the original MEM,
16693 return a new aligned memory. Also build and return the quantities by
16694 which to shift and mask. */
16697 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
16699 rtx addr, align, shift, mask, mem;
16700 HOST_WIDE_INT shift_mask;
16701 enum machine_mode mode = GET_MODE (orig_mem);
16703 /* For smaller modes, we have to implement this via SImode. */
16704 shift_mask = (mode == QImode ? 0x18 : 0x10);
16706 addr = XEXP (orig_mem, 0);
16707 addr = force_reg (GET_MODE (addr), addr);
16709 /* Aligned memory containing subword. Generate a new memory. We
16710 do not want any of the existing MEM_ATTR data, as we're now
16711 accessing memory outside the original object. */
16712 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
16713 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16714 mem = gen_rtx_MEM (SImode, align);
16715 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
16716 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
16717 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
16719 /* Shift amount for subword relative to aligned word. */
16720 shift = gen_reg_rtx (SImode);
16721 addr = gen_lowpart (SImode, addr);
16722 emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
16723 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
16724 shift, 1, OPTAB_LIB_WIDEN);
16727 /* Mask for insertion. */
16728 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
16729 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
16735 /* A subroutine of the various atomic expanders. For sub-word operands,
16736 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16739 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
16743 x = gen_reg_rtx (SImode);
16744 emit_insn (gen_rtx_SET (VOIDmode, x,
16745 gen_rtx_AND (SImode,
16746 gen_rtx_NOT (SImode, mask),
16749 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
16754 /* A subroutine of the various atomic expanders. For sub-word operands,
16755 extract WIDE to NARROW via SHIFT. */
16758 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
16760 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
16761 wide, 1, OPTAB_LIB_WIDEN);
16762 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
16765 /* Expand an atomic compare and swap operation. */
16768 rs6000_expand_atomic_compare_and_swap (rtx operands[])
16770 rtx boolval, retval, mem, oldval, newval, cond;
16771 rtx label1, label2, x, mask, shift;
16772 enum machine_mode mode;
16773 enum memmodel mod_s, mod_f;
16776 boolval = operands[0];
16777 retval = operands[1];
16779 oldval = operands[3];
16780 newval = operands[4];
16781 is_weak = (INTVAL (operands[5]) != 0);
16782 mod_s = (enum memmodel) INTVAL (operands[6]);
16783 mod_f = (enum memmodel) INTVAL (operands[7]);
16784 mode = GET_MODE (mem);
16786 mask = shift = NULL_RTX;
16787 if (mode == QImode || mode == HImode)
16789 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16791 /* Shift and mask OLDVAL into position with the word. */
16792 oldval = convert_modes (SImode, mode, oldval, 1);
16793 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
16794 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16796 /* Shift and mask NEWVAL into position within the word. */
16797 newval = convert_modes (SImode, mode, newval, 1);
16798 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
16799 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16801 /* Prepare to adjust the return value. */
16802 retval = gen_reg_rtx (SImode);
16805 else if (reg_overlap_mentioned_p (retval, oldval))
16806 oldval = copy_to_reg (oldval);
16808 rs6000_pre_atomic_barrier (mod_s);
16813 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16814 emit_label (XEXP (label1, 0));
16816 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16818 emit_load_locked (mode, retval, mem);
16823 x = expand_simple_binop (SImode, AND, retval, mask,
16824 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16827 cond = gen_reg_rtx (CCmode);
16828 x = gen_rtx_COMPARE (CCmode, x, oldval);
16829 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
16831 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16832 emit_unlikely_jump (x, label2);
16836 x = rs6000_mask_atomic_subword (retval, newval, mask);
16838 emit_store_conditional (mode, cond, mem, x);
16842 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16843 emit_unlikely_jump (x, label1);
16846 if (mod_f != MEMMODEL_RELAXED)
16847 emit_label (XEXP (label2, 0));
16849 rs6000_post_atomic_barrier (mod_s);
16851 if (mod_f == MEMMODEL_RELAXED)
16852 emit_label (XEXP (label2, 0));
16855 rs6000_finish_atomic_subword (operands[1], retval, shift);
16857 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16858 x = gen_rtx_EQ (SImode, cond, const0_rtx);
16859 emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
16862 /* Expand an atomic exchange operation. */
16865 rs6000_expand_atomic_exchange (rtx operands[])
16867 rtx retval, mem, val, cond;
16868 enum machine_mode mode;
16869 enum memmodel model;
16870 rtx label, x, mask, shift;
16872 retval = operands[0];
16875 model = (enum memmodel) INTVAL (operands[3]);
16876 mode = GET_MODE (mem);
16878 mask = shift = NULL_RTX;
16879 if (mode == QImode || mode == HImode)
16881 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16883 /* Shift and mask VAL into position with the word. */
16884 val = convert_modes (SImode, mode, val, 1);
16885 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16886 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16888 /* Prepare to adjust the return value. */
16889 retval = gen_reg_rtx (SImode);
16893 rs6000_pre_atomic_barrier (model);
16895 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16896 emit_label (XEXP (label, 0));
16898 emit_load_locked (mode, retval, mem);
16902 x = rs6000_mask_atomic_subword (retval, val, mask);
16904 cond = gen_reg_rtx (CCmode);
16905 emit_store_conditional (mode, cond, mem, x);
16907 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16908 emit_unlikely_jump (x, label);
16910 rs6000_post_atomic_barrier (model);
16913 rs6000_finish_atomic_subword (operands[0], retval, shift);
16916 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
16917 to perform. MEM is the memory on which to operate. VAL is the second
16918 operand of the binary operator. BEFORE and AFTER are optional locations to
16919 return the value of MEM either before of after the operation. MODEL_RTX
16920 is a CONST_INT containing the memory model to use. */
16923 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
16924 rtx orig_before, rtx orig_after, rtx model_rtx)
16926 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
16927 enum machine_mode mode = GET_MODE (mem);
16928 rtx label, x, cond, mask, shift;
16929 rtx before = orig_before, after = orig_after;
16931 mask = shift = NULL_RTX;
16932 if (mode == QImode || mode == HImode)
16934 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16936 /* Shift and mask VAL into position with the word. */
16937 val = convert_modes (SImode, mode, val, 1);
16938 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16939 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16945 /* We've already zero-extended VAL. That is sufficient to
16946 make certain that it does not affect other bits. */
16951 /* If we make certain that all of the other bits in VAL are
16952 set, that will be sufficient to not affect other bits. */
16953 x = gen_rtx_NOT (SImode, mask);
16954 x = gen_rtx_IOR (SImode, x, val);
16955 emit_insn (gen_rtx_SET (VOIDmode, val, x));
16962 /* These will all affect bits outside the field and need
16963 adjustment via MASK within the loop. */
16967 gcc_unreachable ();
16970 /* Prepare to adjust the return value. */
16971 before = gen_reg_rtx (SImode);
16973 after = gen_reg_rtx (SImode);
16977 rs6000_pre_atomic_barrier (model);
16979 label = gen_label_rtx ();
16980 emit_label (label);
16981 label = gen_rtx_LABEL_REF (VOIDmode, label);
16983 if (before == NULL_RTX)
16984 before = gen_reg_rtx (mode);
16986 emit_load_locked (mode, before, mem);
16990 x = expand_simple_binop (mode, AND, before, val,
16991 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16992 after = expand_simple_unop (mode, NOT, x, after, 1);
16996 after = expand_simple_binop (mode, code, before, val,
16997 after, 1, OPTAB_LIB_WIDEN);
17003 x = expand_simple_binop (SImode, AND, after, mask,
17004 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17005 x = rs6000_mask_atomic_subword (before, x, mask);
17008 cond = gen_reg_rtx (CCmode);
17009 emit_store_conditional (mode, cond, mem, x);
17011 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17012 emit_unlikely_jump (x, label);
17014 rs6000_post_atomic_barrier (model);
17019 rs6000_finish_atomic_subword (orig_before, before, shift);
17021 rs6000_finish_atomic_subword (orig_after, after, shift);
17023 else if (orig_after && after != orig_after)
17024 emit_move_insn (orig_after, after);
17027 /* Emit instructions to move SRC to DST. Called by splitters for
17028 multi-register moves. It will emit at most one instruction for
17029 each register that is accessed; that is, it won't emit li/lis pairs
17030 (or equivalent for 64-bit code). One of SRC or DST must be a hard
17034 rs6000_split_multireg_move (rtx dst, rtx src)
17036 /* The register number of the first register being moved. */
17038 /* The mode that is to be moved. */
17039 enum machine_mode mode;
17040 /* The mode that the move is being done in, and its size. */
17041 enum machine_mode reg_mode;
17043 /* The number of registers that will be moved. */
17046 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
17047 mode = GET_MODE (dst);
17048 nregs = hard_regno_nregs[reg][mode];
17049 if (FP_REGNO_P (reg))
17050 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
17051 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
17052 else if (ALTIVEC_REGNO_P (reg))
17053 reg_mode = V16QImode;
17054 else if (TARGET_E500_DOUBLE && mode == TFmode)
17057 reg_mode = word_mode;
17058 reg_mode_size = GET_MODE_SIZE (reg_mode);
17060 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
17062 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
17064 /* Move register range backwards, if we might have destructive
17067 for (i = nregs - 1; i >= 0; i--)
17068 emit_insn (gen_rtx_SET (VOIDmode,
17069 simplify_gen_subreg (reg_mode, dst, mode,
17070 i * reg_mode_size),
17071 simplify_gen_subreg (reg_mode, src, mode,
17072 i * reg_mode_size)));
17078 bool used_update = false;
17079 rtx restore_basereg = NULL_RTX;
17081 if (MEM_P (src) && INT_REGNO_P (reg))
17085 if (GET_CODE (XEXP (src, 0)) == PRE_INC
17086 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
17089 breg = XEXP (XEXP (src, 0), 0);
17090 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
17091 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
17092 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
17093 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17094 src = replace_equiv_address (src, breg);
17096 else if (! rs6000_offsettable_memref_p (src))
17098 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
17100 rtx basereg = XEXP (XEXP (src, 0), 0);
17103 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
17104 emit_insn (gen_rtx_SET (VOIDmode, ndst,
17105 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
17106 used_update = true;
17109 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17110 XEXP (XEXP (src, 0), 1)));
17111 src = replace_equiv_address (src, basereg);
17115 rtx basereg = gen_rtx_REG (Pmode, reg);
17116 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
17117 src = replace_equiv_address (src, basereg);
17121 breg = XEXP (src, 0);
17122 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
17123 breg = XEXP (breg, 0);
17125 /* If the base register we are using to address memory is
17126 also a destination reg, then change that register last. */
17128 && REGNO (breg) >= REGNO (dst)
17129 && REGNO (breg) < REGNO (dst) + nregs)
17130 j = REGNO (breg) - REGNO (dst);
17132 else if (MEM_P (dst) && INT_REGNO_P (reg))
17136 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
17137 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
17140 breg = XEXP (XEXP (dst, 0), 0);
17141 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
17142 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
17143 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
17145 /* We have to update the breg before doing the store.
17146 Use store with update, if available. */
17150 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17151 emit_insn (TARGET_32BIT
17152 ? (TARGET_POWERPC64
17153 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
17154 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
17155 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
17156 used_update = true;
17159 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17160 dst = replace_equiv_address (dst, breg);
17162 else if (!rs6000_offsettable_memref_p (dst)
17163 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
17165 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
17167 rtx basereg = XEXP (XEXP (dst, 0), 0);
17170 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17171 emit_insn (gen_rtx_SET (VOIDmode,
17172 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
17173 used_update = true;
17176 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17177 XEXP (XEXP (dst, 0), 1)));
17178 dst = replace_equiv_address (dst, basereg);
17182 rtx basereg = XEXP (XEXP (dst, 0), 0);
17183 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
17184 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
17186 && REG_P (offsetreg)
17187 && REGNO (basereg) != REGNO (offsetreg));
17188 if (REGNO (basereg) == 0)
17190 rtx tmp = offsetreg;
17191 offsetreg = basereg;
17194 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
17195 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
17196 dst = replace_equiv_address (dst, basereg);
17199 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
17200 gcc_assert (rs6000_offsettable_memref_p (dst));
17203 for (i = 0; i < nregs; i++)
17205 /* Calculate index to next subword. */
17210 /* If compiler already emitted move of first word by
17211 store with update, no need to do anything. */
17212 if (j == 0 && used_update)
17215 emit_insn (gen_rtx_SET (VOIDmode,
17216 simplify_gen_subreg (reg_mode, dst, mode,
17217 j * reg_mode_size),
17218 simplify_gen_subreg (reg_mode, src, mode,
17219 j * reg_mode_size)));
17221 if (restore_basereg != NULL_RTX)
17222 emit_insn (restore_basereg);
17227 /* This page contains routines that are used to determine what the
17228 function prologue and epilogue code will do and write them out. */
17230 /* Return the first fixed-point register that is required to be
17231 saved. 32 if none. */
17234 first_reg_to_save (void)
17238 /* Find lowest numbered live register. */
17239 for (first_reg = 13; first_reg <= 31; first_reg++)
17240 if (df_regs_ever_live_p (first_reg)
17241 && (! call_used_regs[first_reg]
17242 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
17243 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
17244 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
17245 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
17250 && crtl->uses_pic_offset_table
17251 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
17252 return RS6000_PIC_OFFSET_TABLE_REGNUM;
17258 /* Similar, for FP regs. */
17261 first_fp_reg_to_save (void)
17265 /* Find lowest numbered live register. */
17266 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
17267 if (df_regs_ever_live_p (first_reg))
17273 /* Similar, for AltiVec regs. */
17276 first_altivec_reg_to_save (void)
17280 /* Stack frame remains as is unless we are in AltiVec ABI. */
17281 if (! TARGET_ALTIVEC_ABI)
17282 return LAST_ALTIVEC_REGNO + 1;
17284 /* On Darwin, the unwind routines are compiled without
17285 TARGET_ALTIVEC, and use save_world to save/restore the
17286 altivec registers when necessary. */
17287 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17288 && ! TARGET_ALTIVEC)
17289 return FIRST_ALTIVEC_REGNO + 20;
17291 /* Find lowest numbered live register. */
17292 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
17293 if (df_regs_ever_live_p (i))
17299 /* Return a 32-bit mask of the AltiVec registers we need to set in
17300 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17301 the 32-bit word is 0. */
17303 static unsigned int
17304 compute_vrsave_mask (void)
17306 unsigned int i, mask = 0;
17308 /* On Darwin, the unwind routines are compiled without
17309 TARGET_ALTIVEC, and use save_world to save/restore the
17310 call-saved altivec registers when necessary. */
17311 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17312 && ! TARGET_ALTIVEC)
17315 /* First, find out if we use _any_ altivec registers. */
17316 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
17317 if (df_regs_ever_live_p (i))
17318 mask |= ALTIVEC_REG_BIT (i);
17323 /* Next, remove the argument registers from the set. These must
17324 be in the VRSAVE mask set by the caller, so we don't need to add
17325 them in again. More importantly, the mask we compute here is
17326 used to generate CLOBBERs in the set_vrsave insn, and we do not
17327 wish the argument registers to die. */
17328 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
17329 mask &= ~ALTIVEC_REG_BIT (i);
17331 /* Similarly, remove the return value from the set. */
17334 diddle_return_value (is_altivec_return_reg, &yes);
17336 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
17342 /* For a very restricted set of circumstances, we can cut down the
17343 size of prologues/epilogues by calling our own save/restore-the-world
17347 compute_save_world_info (rs6000_stack_t *info_ptr)
17349 info_ptr->world_save_p = 1;
17350 info_ptr->world_save_p
17351 = (WORLD_SAVE_P (info_ptr)
17352 && DEFAULT_ABI == ABI_DARWIN
17353 && !cfun->has_nonlocal_label
17354 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
17355 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
17356 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
17357 && info_ptr->cr_save_p);
17359 /* This will not work in conjunction with sibcalls. Make sure there
17360 are none. (This check is expensive, but seldom executed.) */
17361 if (WORLD_SAVE_P (info_ptr))
17364 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
17365 if ( GET_CODE (insn) == CALL_INSN
17366 && SIBLING_CALL_P (insn))
17368 info_ptr->world_save_p = 0;
17373 if (WORLD_SAVE_P (info_ptr))
17375 /* Even if we're not touching VRsave, make sure there's room on the
17376 stack for it, if it looks like we're calling SAVE_WORLD, which
17377 will attempt to save it. */
17378 info_ptr->vrsave_size = 4;
17380 /* If we are going to save the world, we need to save the link register too. */
17381 info_ptr->lr_save_p = 1;
17383 /* "Save" the VRsave register too if we're saving the world. */
17384 if (info_ptr->vrsave_mask == 0)
17385 info_ptr->vrsave_mask = compute_vrsave_mask ();
17387 /* Because the Darwin register save/restore routines only handle
17388 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17390 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
17391 && (info_ptr->first_altivec_reg_save
17392 >= FIRST_SAVED_ALTIVEC_REGNO));
17399 is_altivec_return_reg (rtx reg, void *xyes)
17401 bool *yes = (bool *) xyes;
17402 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
17407 /* Determine the strategy for savings/restoring registers. */
17410 SAVRES_MULTIPLE = 0x1,
17411 SAVE_INLINE_FPRS = 0x2,
17412 SAVE_INLINE_GPRS = 0x4,
17413 REST_INLINE_FPRS = 0x8,
17414 REST_INLINE_GPRS = 0x10,
17415 SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
17416 SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
17417 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80
17421 rs6000_savres_strategy (rs6000_stack_t *info,
17422 bool using_static_chain_p)
17426 if (TARGET_MULTIPLE
17427 && !TARGET_POWERPC64
17428 && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
17429 && info->first_gp_reg_save < 31
17430 && no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true))
17431 strategy |= SAVRES_MULTIPLE;
17433 if (crtl->calls_eh_return
17434 || cfun->machine->ra_need_lr
17435 || info->total_size > 32767)
17436 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
17437 | SAVE_INLINE_GPRS | REST_INLINE_GPRS);
17439 if (info->first_fp_reg_save == 64
17440 || FP_SAVE_INLINE (info->first_fp_reg_save)
17441 /* The out-of-line FP routines use double-precision stores;
17442 we can't use those routines if we don't have such stores. */
17443 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
17444 || !no_global_regs_above (info->first_fp_reg_save, /*gpr=*/false))
17445 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17447 if (info->first_gp_reg_save == 32
17448 || GP_SAVE_INLINE (info->first_gp_reg_save)
17449 || !((strategy & SAVRES_MULTIPLE)
17450 || no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true)))
17451 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17453 /* Don't bother to try to save things out-of-line if r11 is occupied
17454 by the static chain. It would require too much fiddling and the
17455 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17456 pointer on Darwin. */
17457 if (using_static_chain_p)
17458 strategy |= (DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
17459 | SAVE_INLINE_GPRS;
17461 /* If we are going to use store multiple, then don't even bother
17462 with the out-of-line routines, since the store-multiple
17463 instruction will always be smaller. */
17464 if ((strategy & SAVRES_MULTIPLE))
17465 strategy |= SAVE_INLINE_GPRS;
17467 /* The situation is more complicated with load multiple. We'd
17468 prefer to use the out-of-line routines for restores, since the
17469 "exit" out-of-line routines can handle the restore of LR and the
17470 frame teardown. However if doesn't make sense to use the
17471 out-of-line routine if that is the only reason we'd need to save
17472 LR, and we can't use the "exit" out-of-line gpr restore if we
17473 have saved some fprs; In those cases it is advantageous to use
17474 load multiple when available. */
17475 if ((strategy & SAVRES_MULTIPLE)
17476 && (!info->lr_save_p
17477 || info->first_fp_reg_save != 64))
17478 strategy |= REST_INLINE_GPRS;
17480 /* We can only use load multiple or the out-of-line routines to
17481 restore if we've used store multiple or out-of-line routines
17482 in the prologue, i.e. if we've saved all the registers from
17483 first_gp_reg_save. Otherwise, we risk loading garbage. */
17484 if ((strategy & (SAVE_INLINE_GPRS | SAVRES_MULTIPLE)) == SAVE_INLINE_GPRS)
17485 strategy |= REST_INLINE_GPRS;
17487 /* Saving CR interferes with the exit routines used on the SPE, so
17490 && info->spe_64bit_regs_used
17491 && info->cr_save_p)
17492 strategy |= REST_INLINE_GPRS;
17494 #ifdef POWERPC_LINUX
17497 if (!(strategy & SAVE_INLINE_FPRS))
17498 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17499 else if (!(strategy & SAVE_INLINE_GPRS)
17500 && info->first_fp_reg_save == 64)
17501 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
17504 if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
17505 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
17507 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
17508 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17513 /* Calculate the stack information for the current function. This is
17514 complicated by having two separate calling sequences, the AIX calling
17515 sequence and the V.4 calling sequence.
17517 AIX (and Darwin/Mac OS X) stack frames look like:
17519 SP----> +---------------------------------------+
17520 | back chain to caller | 0 0
17521 +---------------------------------------+
17522 | saved CR | 4 8 (8-11)
17523 +---------------------------------------+
17525 +---------------------------------------+
17526 | reserved for compilers | 12 24
17527 +---------------------------------------+
17528 | reserved for binders | 16 32
17529 +---------------------------------------+
17530 | saved TOC pointer | 20 40
17531 +---------------------------------------+
17532 | Parameter save area (P) | 24 48
17533 +---------------------------------------+
17534 | Alloca space (A) | 24+P etc.
17535 +---------------------------------------+
17536 | Local variable space (L) | 24+P+A
17537 +---------------------------------------+
17538 | Float/int conversion temporary (X) | 24+P+A+L
17539 +---------------------------------------+
17540 | Save area for AltiVec registers (W) | 24+P+A+L+X
17541 +---------------------------------------+
17542 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17543 +---------------------------------------+
17544 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17545 +---------------------------------------+
17546 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17547 +---------------------------------------+
17548 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17549 +---------------------------------------+
17550 old SP->| back chain to caller's caller |
17551 +---------------------------------------+
17553 The required alignment for AIX configurations is two words (i.e., 8
17557 V.4 stack frames look like:
17559 SP----> +---------------------------------------+
17560 | back chain to caller | 0
17561 +---------------------------------------+
17562 | caller's saved LR | 4
17563 +---------------------------------------+
17564 | Parameter save area (P) | 8
17565 +---------------------------------------+
17566 | Alloca space (A) | 8+P
17567 +---------------------------------------+
17568 | Varargs save area (V) | 8+P+A
17569 +---------------------------------------+
17570 | Local variable space (L) | 8+P+A+V
17571 +---------------------------------------+
17572 | Float/int conversion temporary (X) | 8+P+A+V+L
17573 +---------------------------------------+
17574 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17575 +---------------------------------------+
17576 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17577 +---------------------------------------+
17578 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17579 +---------------------------------------+
17580 | SPE: area for 64-bit GP registers |
17581 +---------------------------------------+
17582 | SPE alignment padding |
17583 +---------------------------------------+
17584 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17585 +---------------------------------------+
17586 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17587 +---------------------------------------+
17588 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17589 +---------------------------------------+
17590 old SP->| back chain to caller's caller |
17591 +---------------------------------------+
17593 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17594 given. (But note below and in sysv4.h that we require only 8 and
17595 may round up the size of our stack frame anyways. The historical
17596 reason is early versions of powerpc-linux which didn't properly
17597 align the stack at program startup. A happy side-effect is that
17598 -mno-eabi libraries can be used with -meabi programs.)
17600 The EABI configuration defaults to the V.4 layout. However,
17601 the stack alignment requirements may differ. If -mno-eabi is not
17602 given, the required stack alignment is 8 bytes; if -mno-eabi is
17603 given, the required alignment is 16 bytes. (But see V.4 comment
17606 #ifndef ABI_STACK_BOUNDARY
17607 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17610 static rs6000_stack_t *
17611 rs6000_stack_info (void)
17613 rs6000_stack_t *info_ptr = &stack_info;
17614 int reg_size = TARGET_32BIT ? 4 : 8;
17618 HOST_WIDE_INT non_fixed_size;
17619 bool using_static_chain_p;
17621 if (reload_completed && info_ptr->reload_completed)
17624 memset (info_ptr, 0, sizeof (*info_ptr));
17625 info_ptr->reload_completed = reload_completed;
17629 /* Cache value so we don't rescan instruction chain over and over. */
17630 if (cfun->machine->insn_chain_scanned_p == 0)
17631 cfun->machine->insn_chain_scanned_p
17632 = spe_func_has_64bit_regs_p () + 1;
17633 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
17636 /* Select which calling sequence. */
17637 info_ptr->abi = DEFAULT_ABI;
17639 /* Calculate which registers need to be saved & save area size. */
17640 info_ptr->first_gp_reg_save = first_reg_to_save ();
17641 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17642 even if it currently looks like we won't. Reload may need it to
17643 get at a constant; if so, it will have already created a constant
17644 pool entry for it. */
17645 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
17646 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
17647 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
17648 && crtl->uses_const_pool
17649 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
17650 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
17652 first_gp = info_ptr->first_gp_reg_save;
17654 info_ptr->gp_size = reg_size * (32 - first_gp);
17656 /* For the SPE, we have an additional upper 32-bits on each GPR.
17657 Ideally we should save the entire 64-bits only when the upper
17658 half is used in SIMD instructions. Since we only record
17659 registers live (not the size they are used in), this proves
17660 difficult because we'd have to traverse the instruction chain at
17661 the right time, taking reload into account. This is a real pain,
17662 so we opt to save the GPRs in 64-bits always if but one register
17663 gets used in 64-bits. Otherwise, all the registers in the frame
17664 get saved in 32-bits.
17666 So... since when we save all GPRs (except the SP) in 64-bits, the
17667 traditional GP save area will be empty. */
17668 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17669 info_ptr->gp_size = 0;
17671 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
17672 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
17674 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
17675 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
17676 - info_ptr->first_altivec_reg_save);
17678 /* Does this function call anything? */
17679 info_ptr->calls_p = (! current_function_is_leaf
17680 || cfun->machine->ra_needs_full_frame);
17682 /* Determine if we need to save the condition code registers. */
17683 if (df_regs_ever_live_p (CR2_REGNO)
17684 || df_regs_ever_live_p (CR3_REGNO)
17685 || df_regs_ever_live_p (CR4_REGNO))
17687 info_ptr->cr_save_p = 1;
17688 if (DEFAULT_ABI == ABI_V4)
17689 info_ptr->cr_size = reg_size;
17692 /* If the current function calls __builtin_eh_return, then we need
17693 to allocate stack space for registers that will hold data for
17694 the exception handler. */
17695 if (crtl->calls_eh_return)
17698 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
17701 /* SPE saves EH registers in 64-bits. */
17702 ehrd_size = i * (TARGET_SPE_ABI
17703 && info_ptr->spe_64bit_regs_used != 0
17704 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
17709 /* Determine various sizes. */
17710 info_ptr->reg_size = reg_size;
17711 info_ptr->fixed_size = RS6000_SAVE_AREA;
17712 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
17713 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
17714 TARGET_ALTIVEC ? 16 : 8);
17715 if (FRAME_GROWS_DOWNWARD)
17716 info_ptr->vars_size
17717 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
17718 + info_ptr->parm_size,
17719 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
17720 - (info_ptr->fixed_size + info_ptr->vars_size
17721 + info_ptr->parm_size);
17723 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17724 info_ptr->spe_gp_size = 8 * (32 - first_gp);
17726 info_ptr->spe_gp_size = 0;
17728 if (TARGET_ALTIVEC_ABI)
17729 info_ptr->vrsave_mask = compute_vrsave_mask ();
17731 info_ptr->vrsave_mask = 0;
17733 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
17734 info_ptr->vrsave_size = 4;
17736 info_ptr->vrsave_size = 0;
17738 compute_save_world_info (info_ptr);
17740 /* Calculate the offsets. */
17741 switch (DEFAULT_ABI)
17745 gcc_unreachable ();
17749 info_ptr->fp_save_offset = - info_ptr->fp_size;
17750 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17752 if (TARGET_ALTIVEC_ABI)
17754 info_ptr->vrsave_save_offset
17755 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
17757 /* Align stack so vector save area is on a quadword boundary.
17758 The padding goes above the vectors. */
17759 if (info_ptr->altivec_size != 0)
17760 info_ptr->altivec_padding_size
17761 = info_ptr->vrsave_save_offset & 0xF;
17763 info_ptr->altivec_padding_size = 0;
17765 info_ptr->altivec_save_offset
17766 = info_ptr->vrsave_save_offset
17767 - info_ptr->altivec_padding_size
17768 - info_ptr->altivec_size;
17769 gcc_assert (info_ptr->altivec_size == 0
17770 || info_ptr->altivec_save_offset % 16 == 0);
17772 /* Adjust for AltiVec case. */
17773 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
17776 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
17777 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
17778 info_ptr->lr_save_offset = 2*reg_size;
17782 info_ptr->fp_save_offset = - info_ptr->fp_size;
17783 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17784 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
17786 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17788 /* Align stack so SPE GPR save area is aligned on a
17789 double-word boundary. */
17790 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
17791 info_ptr->spe_padding_size
17792 = 8 - (-info_ptr->cr_save_offset % 8);
17794 info_ptr->spe_padding_size = 0;
17796 info_ptr->spe_gp_save_offset
17797 = info_ptr->cr_save_offset
17798 - info_ptr->spe_padding_size
17799 - info_ptr->spe_gp_size;
17801 /* Adjust for SPE case. */
17802 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
17804 else if (TARGET_ALTIVEC_ABI)
17806 info_ptr->vrsave_save_offset
17807 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
17809 /* Align stack so vector save area is on a quadword boundary. */
17810 if (info_ptr->altivec_size != 0)
17811 info_ptr->altivec_padding_size
17812 = 16 - (-info_ptr->vrsave_save_offset % 16);
17814 info_ptr->altivec_padding_size = 0;
17816 info_ptr->altivec_save_offset
17817 = info_ptr->vrsave_save_offset
17818 - info_ptr->altivec_padding_size
17819 - info_ptr->altivec_size;
17821 /* Adjust for AltiVec case. */
17822 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
17825 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
17826 info_ptr->ehrd_offset -= ehrd_size;
17827 info_ptr->lr_save_offset = reg_size;
17831 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
17832 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
17833 + info_ptr->gp_size
17834 + info_ptr->altivec_size
17835 + info_ptr->altivec_padding_size
17836 + info_ptr->spe_gp_size
17837 + info_ptr->spe_padding_size
17839 + info_ptr->cr_size
17840 + info_ptr->vrsave_size,
17843 non_fixed_size = (info_ptr->vars_size
17844 + info_ptr->parm_size
17845 + info_ptr->save_size);
17847 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
17848 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
17850 /* Determine if we need to save the link register. */
17851 if (info_ptr->calls_p
17852 || (DEFAULT_ABI == ABI_AIX
17854 && !TARGET_PROFILE_KERNEL)
17855 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
17856 #ifdef TARGET_RELOCATABLE
17857 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
17859 || rs6000_ra_ever_killed ())
17860 info_ptr->lr_save_p = 1;
17862 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
17863 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
17864 && call_used_regs[STATIC_CHAIN_REGNUM]);
17865 info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
17866 using_static_chain_p);
17868 if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
17869 || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
17870 || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
17871 || !(info_ptr->savres_strategy & REST_INLINE_FPRS))
17872 info_ptr->lr_save_p = 1;
17874 if (info_ptr->lr_save_p)
17875 df_set_regs_ever_live (LR_REGNO, true);
17877 /* Determine if we need to allocate any stack frame:
17879 For AIX we need to push the stack if a frame pointer is needed
17880 (because the stack might be dynamically adjusted), if we are
17881 debugging, if we make calls, or if the sum of fp_save, gp_save,
17882 and local variables are more than the space needed to save all
17883 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
17884 + 18*8 = 288 (GPR13 reserved).
17886 For V.4 we don't have the stack cushion that AIX uses, but assume
17887 that the debugger can handle stackless frames. */
17889 if (info_ptr->calls_p)
17890 info_ptr->push_p = 1;
17892 else if (DEFAULT_ABI == ABI_V4)
17893 info_ptr->push_p = non_fixed_size != 0;
17895 else if (frame_pointer_needed)
17896 info_ptr->push_p = 1;
17898 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
17899 info_ptr->push_p = 1;
17902 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
17904 /* Zero offsets if we're not saving those registers. */
17905 if (info_ptr->fp_size == 0)
17906 info_ptr->fp_save_offset = 0;
17908 if (info_ptr->gp_size == 0)
17909 info_ptr->gp_save_offset = 0;
17911 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
17912 info_ptr->altivec_save_offset = 0;
17914 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
17915 info_ptr->vrsave_save_offset = 0;
17917 if (! TARGET_SPE_ABI
17918 || info_ptr->spe_64bit_regs_used == 0
17919 || info_ptr->spe_gp_size == 0)
17920 info_ptr->spe_gp_save_offset = 0;
17922 if (! info_ptr->lr_save_p)
17923 info_ptr->lr_save_offset = 0;
17925 if (! info_ptr->cr_save_p)
17926 info_ptr->cr_save_offset = 0;
17931 /* Return true if the current function uses any GPRs in 64-bit SIMD
17935 spe_func_has_64bit_regs_p (void)
17939 /* Functions that save and restore all the call-saved registers will
17940 need to save/restore the registers in 64-bits. */
17941 if (crtl->calls_eh_return
17942 || cfun->calls_setjmp
17943 || crtl->has_nonlocal_goto)
17946 insns = get_insns ();
17948 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
17954 /* FIXME: This should be implemented with attributes...
17956 (set_attr "spe64" "true")....then,
17957 if (get_spe64(insn)) return true;
17959 It's the only reliable way to do the stuff below. */
17961 i = PATTERN (insn);
17962 if (GET_CODE (i) == SET)
17964 enum machine_mode mode = GET_MODE (SET_SRC (i));
17966 if (SPE_VECTOR_MODE (mode))
17968 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
17978 debug_stack_info (rs6000_stack_t *info)
17980 const char *abi_string;
17983 info = rs6000_stack_info ();
17985 fprintf (stderr, "\nStack information for function %s:\n",
17986 ((current_function_decl && DECL_NAME (current_function_decl))
17987 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
17992 default: abi_string = "Unknown"; break;
17993 case ABI_NONE: abi_string = "NONE"; break;
17994 case ABI_AIX: abi_string = "AIX"; break;
17995 case ABI_DARWIN: abi_string = "Darwin"; break;
17996 case ABI_V4: abi_string = "V.4"; break;
17999 fprintf (stderr, "\tABI = %5s\n", abi_string);
18001 if (TARGET_ALTIVEC_ABI)
18002 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
18004 if (TARGET_SPE_ABI)
18005 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
18007 if (info->first_gp_reg_save != 32)
18008 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
18010 if (info->first_fp_reg_save != 64)
18011 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
18013 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
18014 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
18015 info->first_altivec_reg_save);
18017 if (info->lr_save_p)
18018 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
18020 if (info->cr_save_p)
18021 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
18023 if (info->vrsave_mask)
18024 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
18027 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
18030 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
18032 if (info->gp_save_offset)
18033 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
18035 if (info->fp_save_offset)
18036 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
18038 if (info->altivec_save_offset)
18039 fprintf (stderr, "\taltivec_save_offset = %5d\n",
18040 info->altivec_save_offset);
18042 if (info->spe_gp_save_offset)
18043 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
18044 info->spe_gp_save_offset);
18046 if (info->vrsave_save_offset)
18047 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
18048 info->vrsave_save_offset);
18050 if (info->lr_save_offset)
18051 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
18053 if (info->cr_save_offset)
18054 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
18056 if (info->varargs_save_offset)
18057 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
18059 if (info->total_size)
18060 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18063 if (info->vars_size)
18064 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18067 if (info->parm_size)
18068 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
18070 if (info->fixed_size)
18071 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
18074 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
18076 if (info->spe_gp_size)
18077 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
18080 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
18082 if (info->altivec_size)
18083 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
18085 if (info->vrsave_size)
18086 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
18088 if (info->altivec_padding_size)
18089 fprintf (stderr, "\taltivec_padding_size= %5d\n",
18090 info->altivec_padding_size);
18092 if (info->spe_padding_size)
18093 fprintf (stderr, "\tspe_padding_size = %5d\n",
18094 info->spe_padding_size);
18097 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
18099 if (info->save_size)
18100 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
18102 if (info->reg_size != 4)
18103 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
18105 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
18107 fprintf (stderr, "\n");
18111 rs6000_return_addr (int count, rtx frame)
18113 /* Currently we don't optimize very well between prolog and body
18114 code and for PIC code the code can be actually quite bad, so
18115 don't try to be too clever here. */
18116 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
18118 cfun->machine->ra_needs_full_frame = 1;
18125 plus_constant (copy_to_reg
18126 (gen_rtx_MEM (Pmode,
18127 memory_address (Pmode, frame))),
18128 RETURN_ADDRESS_OFFSET)));
18131 cfun->machine->ra_need_lr = 1;
18132 return get_hard_reg_initial_val (Pmode, LR_REGNO);
18135 /* Say whether a function is a candidate for sibcall handling or not. */
18138 rs6000_function_ok_for_sibcall (tree decl, tree exp)
18143 fntype = TREE_TYPE (decl);
18145 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
18147 /* We can't do it if the called function has more vector parameters
18148 than the current function; there's nowhere to put the VRsave code. */
18149 if (TARGET_ALTIVEC_ABI
18150 && TARGET_ALTIVEC_VRSAVE
18151 && !(decl && decl == current_function_decl))
18153 function_args_iterator args_iter;
18157 /* Functions with vector parameters are required to have a
18158 prototype, so the argument type info must be available
18160 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
18161 if (TREE_CODE (type) == VECTOR_TYPE
18162 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18165 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
18166 if (TREE_CODE (type) == VECTOR_TYPE
18167 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18174 /* Under the AIX ABI we can't allow calls to non-local functions,
18175 because the callee may have a different TOC pointer to the
18176 caller and there's no way to ensure we restore the TOC when we
18177 return. With the secure-plt SYSV ABI we can't make non-local
18178 calls when -fpic/PIC because the plt call stubs use r30. */
18179 if (DEFAULT_ABI == ABI_DARWIN
18180 || (DEFAULT_ABI == ABI_AIX
18182 && !DECL_EXTERNAL (decl)
18183 && (*targetm.binds_local_p) (decl))
18184 || (DEFAULT_ABI == ABI_V4
18185 && (!TARGET_SECURE_PLT
18188 && (*targetm.binds_local_p) (decl)))))
18190 tree attr_list = TYPE_ATTRIBUTES (fntype);
18192 if (!lookup_attribute ("longcall", attr_list)
18193 || lookup_attribute ("shortcall", attr_list))
18200 /* NULL if INSN insn is valid within a low-overhead loop.
18201 Otherwise return why doloop cannot be applied.
18202 PowerPC uses the COUNT register for branch on table instructions. */
18204 static const char *
18205 rs6000_invalid_within_doloop (const_rtx insn)
18208 return "Function call in the loop.";
18211 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
18212 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
18213 return "Computed branch in the loop.";
18219 rs6000_ra_ever_killed (void)
18225 if (cfun->is_thunk)
18228 if (cfun->machine->lr_save_state)
18229 return cfun->machine->lr_save_state - 1;
18231 /* regs_ever_live has LR marked as used if any sibcalls are present,
18232 but this should not force saving and restoring in the
18233 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18234 clobbers LR, so that is inappropriate. */
18236 /* Also, the prologue can generate a store into LR that
18237 doesn't really count, like this:
18240 bcl to set PIC register
18244 When we're called from the epilogue, we need to avoid counting
18245 this as a store. */
18247 push_topmost_sequence ();
18248 top = get_insns ();
18249 pop_topmost_sequence ();
18250 reg = gen_rtx_REG (Pmode, LR_REGNO);
18252 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
18258 if (!SIBLING_CALL_P (insn))
18261 else if (find_regno_note (insn, REG_INC, LR_REGNO))
18263 else if (set_of (reg, insn) != NULL_RTX
18264 && !prologue_epilogue_contains (insn))
18271 /* Emit instructions needed to load the TOC register.
18272 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18273 a constant pool; or for SVR4 -fpic. */
18276 rs6000_emit_load_toc_table (int fromprolog)
18279 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
18281 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
18284 rtx lab, tmp1, tmp2, got;
18286 lab = gen_label_rtx ();
18287 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
18288 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18290 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18292 got = rs6000_got_sym ();
18293 tmp1 = tmp2 = dest;
18296 tmp1 = gen_reg_rtx (Pmode);
18297 tmp2 = gen_reg_rtx (Pmode);
18299 emit_insn (gen_load_toc_v4_PIC_1 (lab));
18300 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
18301 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
18302 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
18304 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
18306 emit_insn (gen_load_toc_v4_pic_si ());
18307 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18309 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
18312 rtx temp0 = (fromprolog
18313 ? gen_rtx_REG (Pmode, 0)
18314 : gen_reg_rtx (Pmode));
18320 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18321 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18323 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
18324 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18326 emit_insn (gen_load_toc_v4_PIC_1 (symF));
18327 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18328 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
18334 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18335 lab = gen_label_rtx ();
18336 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
18337 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18338 if (TARGET_LINK_STACK)
18339 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
18340 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
18342 emit_insn (gen_addsi3 (dest, temp0, dest));
18344 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
18346 /* This is for AIX code running in non-PIC ELF32. */
18349 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18350 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18352 emit_insn (gen_elf_high (dest, realsym));
18353 emit_insn (gen_elf_low (dest, dest, realsym));
18357 gcc_assert (DEFAULT_ABI == ABI_AIX);
18360 emit_insn (gen_load_toc_aix_si (dest));
18362 emit_insn (gen_load_toc_aix_di (dest));
18366 /* Emit instructions to restore the link register after determining where
18367 its value has been stored. */
18370 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
18372 rs6000_stack_t *info = rs6000_stack_info ();
18375 operands[0] = source;
18376 operands[1] = scratch;
18378 if (info->lr_save_p)
18380 rtx frame_rtx = stack_pointer_rtx;
18381 HOST_WIDE_INT sp_offset = 0;
18384 if (frame_pointer_needed
18385 || cfun->calls_alloca
18386 || info->total_size > 32767)
18388 tmp = gen_frame_mem (Pmode, frame_rtx);
18389 emit_move_insn (operands[1], tmp);
18390 frame_rtx = operands[1];
18392 else if (info->push_p)
18393 sp_offset = info->total_size;
18395 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
18396 tmp = gen_frame_mem (Pmode, tmp);
18397 emit_move_insn (tmp, operands[0]);
18400 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
18402 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18403 state of lr_save_p so any change from here on would be a bug. In
18404 particular, stop rs6000_ra_ever_killed from considering the SET
18405 of lr we may have added just above. */
18406 cfun->machine->lr_save_state = info->lr_save_p + 1;
18409 static GTY(()) alias_set_type set = -1;
18412 get_TOC_alias_set (void)
18415 set = new_alias_set ();
18419 /* This returns nonzero if the current function uses the TOC. This is
18420 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18421 is generated by the ABI_V4 load_toc_* patterns. */
18428 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18431 rtx pat = PATTERN (insn);
18434 if (GET_CODE (pat) == PARALLEL)
18435 for (i = 0; i < XVECLEN (pat, 0); i++)
18437 rtx sub = XVECEXP (pat, 0, i);
18438 if (GET_CODE (sub) == USE)
18440 sub = XEXP (sub, 0);
18441 if (GET_CODE (sub) == UNSPEC
18442 && XINT (sub, 1) == UNSPEC_TOC)
18452 create_TOC_reference (rtx symbol, rtx largetoc_reg)
18454 rtx tocrel, tocreg;
18456 if (TARGET_DEBUG_ADDR)
18458 if (GET_CODE (symbol) == SYMBOL_REF)
18459 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18463 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
18464 GET_RTX_NAME (GET_CODE (symbol)));
18465 debug_rtx (symbol);
18469 if (!can_create_pseudo_p ())
18470 df_set_regs_ever_live (TOC_REGISTER, true);
18472 tocrel = gen_rtx_CONST (Pmode,
18473 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol),
18475 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
18476 if (TARGET_CMODEL != CMODEL_SMALL)
18478 rtx hi = gen_rtx_CONST (Pmode,
18479 gen_rtx_PLUS (Pmode, tocreg,
18480 gen_rtx_HIGH (Pmode, tocrel)));
18481 if (largetoc_reg != NULL)
18483 emit_move_insn (largetoc_reg, hi);
18486 return gen_rtx_LO_SUM (Pmode, hi, copy_rtx (tocrel));
18489 return gen_rtx_PLUS (Pmode, tocreg, tocrel);
18492 /* Issue assembly directives that create a reference to the given DWARF
18493 FRAME_TABLE_LABEL from the current function section. */
18495 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
18497 fprintf (asm_out_file, "\t.ref %s\n",
18498 TARGET_STRIP_NAME_ENCODING (frame_table_label));
18501 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18502 and the change to the stack pointer. */
18505 rs6000_emit_stack_tie (void)
18507 rtx mem = gen_frame_mem (BLKmode,
18508 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
18510 emit_insn (gen_stack_tie (mem));
18513 /* Emit the correct code for allocating stack space, as insns.
18514 If COPY_REG, make sure a copy of the old frame is left there.
18515 The generated code may use hard register 0 as a temporary. */
18518 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg)
18521 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18522 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
18523 rtx todec = gen_int_mode (-size, Pmode);
18526 if (INTVAL (todec) != -size)
18528 warning (0, "stack frame too large");
18529 emit_insn (gen_trap ());
18533 if (crtl->limit_stack)
18535 if (REG_P (stack_limit_rtx)
18536 && REGNO (stack_limit_rtx) > 1
18537 && REGNO (stack_limit_rtx) <= 31)
18539 emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
18540 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18543 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
18545 && DEFAULT_ABI == ABI_V4)
18547 rtx toload = gen_rtx_CONST (VOIDmode,
18548 gen_rtx_PLUS (Pmode,
18552 emit_insn (gen_elf_high (tmp_reg, toload));
18553 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
18554 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18558 warning (0, "stack limit expression is not supported");
18562 emit_move_insn (copy_reg, stack_reg);
18566 /* Need a note here so that try_split doesn't get confused. */
18567 if (get_last_insn () == NULL_RTX)
18568 emit_note (NOTE_INSN_DELETED);
18569 insn = emit_move_insn (tmp_reg, todec);
18570 try_split (PATTERN (insn), insn, 0);
18574 insn = emit_insn (TARGET_32BIT
18575 ? gen_movsi_update_stack (stack_reg, stack_reg,
18577 : gen_movdi_di_update_stack (stack_reg, stack_reg,
18578 todec, stack_reg));
18579 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18580 it now and set the alias set/attributes. The above gen_*_update
18581 calls will generate a PARALLEL with the MEM set being the first
18583 par = PATTERN (insn);
18584 gcc_assert (GET_CODE (par) == PARALLEL);
18585 set = XVECEXP (par, 0, 0);
18586 gcc_assert (GET_CODE (set) == SET);
18587 mem = SET_DEST (set);
18588 gcc_assert (MEM_P (mem));
18589 MEM_NOTRAP_P (mem) = 1;
18590 set_mem_alias_set (mem, get_frame_alias_set ());
18592 RTX_FRAME_RELATED_P (insn) = 1;
18593 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
18594 gen_rtx_SET (VOIDmode, stack_reg,
18595 gen_rtx_PLUS (Pmode, stack_reg,
18596 GEN_INT (-size))));
18599 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18601 #if PROBE_INTERVAL > 32768
18602 #error Cannot use indexed addressing mode for stack probing
18605 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18606 inclusive. These are offsets from the current stack pointer. */
18609 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
18611 /* See if we have a constant small number of probes to generate. If so,
18612 that's the easy case. */
18613 if (first + size <= 32768)
18617 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18618 it exceeds SIZE. If only one probe is needed, this will not
18619 generate any code. Then probe at FIRST + SIZE. */
18620 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
18621 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + i)));
18623 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + size)));
18626 /* Otherwise, do the same as above, but in a loop. Note that we must be
18627 extra careful with variables wrapping around because we might be at
18628 the very top (or the very bottom) of the address space and we have
18629 to be able to handle this case properly; in particular, we use an
18630 equality test for the loop condition. */
18633 HOST_WIDE_INT rounded_size;
18634 rtx r12 = gen_rtx_REG (Pmode, 12);
18635 rtx r0 = gen_rtx_REG (Pmode, 0);
18637 /* Sanity check for the addressing mode we're going to use. */
18638 gcc_assert (first <= 32768);
18640 /* Step 1: round SIZE to the previous multiple of the interval. */
18642 rounded_size = size & -PROBE_INTERVAL;
18645 /* Step 2: compute initial and final value of the loop counter. */
18647 /* TEST_ADDR = SP + FIRST. */
18648 emit_insn (gen_rtx_SET (VOIDmode, r12,
18649 plus_constant (stack_pointer_rtx, -first)));
18651 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18652 if (rounded_size > 32768)
18654 emit_move_insn (r0, GEN_INT (-rounded_size));
18655 emit_insn (gen_rtx_SET (VOIDmode, r0,
18656 gen_rtx_PLUS (Pmode, r12, r0)));
18659 emit_insn (gen_rtx_SET (VOIDmode, r0,
18660 plus_constant (r12, -rounded_size)));
18663 /* Step 3: the loop
18665 while (TEST_ADDR != LAST_ADDR)
18667 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18671 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18672 until it is equal to ROUNDED_SIZE. */
18675 emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
18677 emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
18680 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18681 that SIZE is equal to ROUNDED_SIZE. */
18683 if (size != rounded_size)
18684 emit_stack_probe (plus_constant (r12, rounded_size - size));
18688 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18689 absolute addresses. */
18692 output_probe_stack_range (rtx reg1, rtx reg2)
18694 static int labelno = 0;
18695 char loop_lab[32], end_lab[32];
18698 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
18699 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
18701 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
18703 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18707 output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops);
18709 output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops);
18711 fputs ("\tbeq 0,", asm_out_file);
18712 assemble_name_raw (asm_out_file, end_lab);
18713 fputc ('\n', asm_out_file);
18715 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18716 xops[1] = GEN_INT (-PROBE_INTERVAL);
18717 output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops);
18719 /* Probe at TEST_ADDR and branch. */
18720 xops[1] = gen_rtx_REG (Pmode, 0);
18721 output_asm_insn ("{st|stw} %1,0(%0)", xops);
18722 fprintf (asm_out_file, "\tb ");
18723 assemble_name_raw (asm_out_file, loop_lab);
18724 fputc ('\n', asm_out_file);
18726 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
18731 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18732 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18733 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18734 deduce these equivalences by itself so it wasn't necessary to hold
18735 its hand so much. */
18738 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
18739 rtx reg2, rtx rreg)
18743 /* copy_rtx will not make unique copies of registers, so we need to
18744 ensure we don't have unwanted sharing here. */
18746 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18749 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18751 real = copy_rtx (PATTERN (insn));
18753 if (reg2 != NULL_RTX)
18754 real = replace_rtx (real, reg2, rreg);
18756 real = replace_rtx (real, reg,
18757 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
18758 STACK_POINTER_REGNUM),
18761 /* We expect that 'real' is either a SET or a PARALLEL containing
18762 SETs (and possibly other stuff). In a PARALLEL, all the SETs
18763 are important so they all have to be marked RTX_FRAME_RELATED_P. */
18765 if (GET_CODE (real) == SET)
18769 temp = simplify_rtx (SET_SRC (set));
18771 SET_SRC (set) = temp;
18772 temp = simplify_rtx (SET_DEST (set));
18774 SET_DEST (set) = temp;
18775 if (GET_CODE (SET_DEST (set)) == MEM)
18777 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18779 XEXP (SET_DEST (set), 0) = temp;
18786 gcc_assert (GET_CODE (real) == PARALLEL);
18787 for (i = 0; i < XVECLEN (real, 0); i++)
18788 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18790 rtx set = XVECEXP (real, 0, i);
18792 temp = simplify_rtx (SET_SRC (set));
18794 SET_SRC (set) = temp;
18795 temp = simplify_rtx (SET_DEST (set));
18797 SET_DEST (set) = temp;
18798 if (GET_CODE (SET_DEST (set)) == MEM)
18800 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18802 XEXP (SET_DEST (set), 0) = temp;
18804 RTX_FRAME_RELATED_P (set) = 1;
18808 RTX_FRAME_RELATED_P (insn) = 1;
18809 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
18814 /* Returns an insn that has a vrsave set operation with the
18815 appropriate CLOBBERs. */
18818 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
18821 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
18822 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
18825 = gen_rtx_SET (VOIDmode,
18827 gen_rtx_UNSPEC_VOLATILE (SImode,
18828 gen_rtvec (2, reg, vrsave),
18829 UNSPECV_SET_VRSAVE));
18833 /* We need to clobber the registers in the mask so the scheduler
18834 does not move sets to VRSAVE before sets of AltiVec registers.
18836 However, if the function receives nonlocal gotos, reload will set
18837 all call saved registers live. We will end up with:
18839 (set (reg 999) (mem))
18840 (parallel [ (set (reg vrsave) (unspec blah))
18841 (clobber (reg 999))])
18843 The clobber will cause the store into reg 999 to be dead, and
18844 flow will attempt to delete an epilogue insn. In this case, we
18845 need an unspec use/set of the register. */
18847 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
18848 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
18850 if (!epiloguep || call_used_regs [i])
18851 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
18852 gen_rtx_REG (V4SImode, i));
18855 rtx reg = gen_rtx_REG (V4SImode, i);
18858 = gen_rtx_SET (VOIDmode,
18860 gen_rtx_UNSPEC (V4SImode,
18861 gen_rtvec (1, reg), 27));
18865 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
18867 for (i = 0; i < nclobs; ++i)
18868 XVECEXP (insn, 0, i) = clobs[i];
18873 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
18874 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
18877 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
18878 unsigned int regno, int offset, HOST_WIDE_INT total_size)
18880 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
18881 rtx replacea, replaceb;
18883 int_rtx = GEN_INT (offset);
18885 /* Some cases that need register indexed addressing. */
18886 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
18887 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
18888 || (TARGET_E500_DOUBLE && mode == DFmode)
18890 && SPE_VECTOR_MODE (mode)
18891 && !SPE_CONST_OFFSET_OK (offset)))
18893 /* Whomever calls us must make sure r11 is available in the
18894 flow path of instructions in the prologue. */
18895 offset_rtx = gen_rtx_REG (Pmode, 11);
18896 emit_move_insn (offset_rtx, int_rtx);
18898 replacea = offset_rtx;
18899 replaceb = int_rtx;
18903 offset_rtx = int_rtx;
18904 replacea = NULL_RTX;
18905 replaceb = NULL_RTX;
18908 reg = gen_rtx_REG (mode, regno);
18909 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
18910 mem = gen_frame_mem (mode, addr);
18912 insn = emit_move_insn (mem, reg);
18914 return rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
18917 /* Emit an offset memory reference suitable for a frame store, while
18918 converting to a valid addressing mode. */
18921 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
18923 rtx int_rtx, offset_rtx;
18925 int_rtx = GEN_INT (offset);
18927 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
18928 || (TARGET_E500_DOUBLE && mode == DFmode))
18930 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
18931 emit_move_insn (offset_rtx, int_rtx);
18934 offset_rtx = int_rtx;
18936 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
18939 /* Look for user-defined global regs. We should not save and restore these,
18940 and cannot use stmw/lmw if there are any in its range. */
18943 no_global_regs_above (int first, bool gpr)
18946 int last = gpr ? 32 : 64;
18947 for (i = first; i < last; i++)
18948 if (global_regs[i])
18953 #ifndef TARGET_FIX_AND_CONTINUE
18954 #define TARGET_FIX_AND_CONTINUE 0
18957 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
18958 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
18959 #define LAST_SAVRES_REGISTER 31
18960 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
18962 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8];
18964 /* Temporary holding space for an out-of-line register save/restore
18966 static char savres_routine_name[30];
18968 /* Return the name for an out-of-line register save/restore routine.
18969 We are saving/restoring GPRs if GPR is true. */
18972 rs6000_savres_routine_name (rs6000_stack_t *info, int regno,
18973 bool savep, bool gpr, bool lr)
18975 const char *prefix = "";
18976 const char *suffix = "";
18978 /* Different targets are supposed to define
18979 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
18980 routine name could be defined with:
18982 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
18984 This is a nice idea in practice, but in reality, things are
18985 complicated in several ways:
18987 - ELF targets have save/restore routines for GPRs.
18989 - SPE targets use different prefixes for 32/64-bit registers, and
18990 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
18992 - PPC64 ELF targets have routines for save/restore of GPRs that
18993 differ in what they do with the link register, so having a set
18994 prefix doesn't work. (We only use one of the save routines at
18995 the moment, though.)
18997 - PPC32 elf targets have "exit" versions of the restore routines
18998 that restore the link register and can save some extra space.
18999 These require an extra suffix. (There are also "tail" versions
19000 of the restore routines and "GOT" versions of the save routines,
19001 but we don't generate those at present. Same problems apply,
19004 We deal with all this by synthesizing our own prefix/suffix and
19005 using that for the simple sprintf call shown above. */
19008 /* No floating point saves on the SPE. */
19012 prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
19014 prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
19019 else if (DEFAULT_ABI == ABI_V4)
19025 prefix = savep ? "_savegpr_" : "_restgpr_";
19027 prefix = savep ? "_savefpr_" : "_restfpr_";
19032 else if (DEFAULT_ABI == ABI_AIX)
19034 #ifndef POWERPC_LINUX
19035 /* No out-of-line save/restore routines for GPRs on AIX. */
19036 gcc_assert (!TARGET_AIX || !gpr);
19042 ? (lr ? "_savegpr0_" : "_savegpr1_")
19043 : (lr ? "_restgpr0_" : "_restgpr1_"));
19044 #ifdef POWERPC_LINUX
19046 prefix = (savep ? "_savefpr_" : "_restfpr_");
19050 prefix = savep ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
19051 suffix = savep ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
19055 if (DEFAULT_ABI == ABI_DARWIN)
19057 /* The Darwin approach is (slightly) different, in order to be
19058 compatible with code generated by the system toolchain. There is a
19059 single symbol for the start of save sequence, and the code here
19060 embeds an offset into that code on the basis of the first register
19062 prefix = savep ? "save" : "rest" ;
19064 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31",
19065 prefix, (lr ? "x" : ""), (regno == 13 ? "" : "+"),
19066 (regno-13) * 4, prefix, regno);
19068 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31",
19069 prefix, (regno == 14 ? "" : "+"), (regno-14) * 4, prefix, regno);
19072 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
19074 return savres_routine_name;
19077 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19078 We are saving/restoring GPRs if GPR is true. */
19081 rs6000_savres_routine_sym (rs6000_stack_t *info, bool savep,
19084 int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32);
19086 int select = ((savep ? 1 : 0) << 2
19088 /* On the SPE, we never have any FPRs, but we do have
19089 32/64-bit versions of the routines. */
19090 ? (info->spe_64bit_regs_used ? 1 : 0)
19091 : (gpr ? 1 : 0)) << 1)
19094 /* Don't generate bogus routine names. */
19095 gcc_assert (FIRST_SAVRES_REGISTER <= regno
19096 && regno <= LAST_SAVRES_REGISTER);
19098 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
19104 name = rs6000_savres_routine_name (info, regno, savep, gpr, lr);
19106 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19107 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19108 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19114 /* Emit a sequence of insns, including a stack tie if needed, for
19115 resetting the stack pointer. If SAVRES is true, then don't reset the
19116 stack pointer, but move the base of the frame into r11 for use by
19117 out-of-line register restore routines. */
19120 rs6000_emit_stack_reset (rs6000_stack_t *info,
19121 rtx sp_reg_rtx, rtx frame_reg_rtx,
19122 int sp_offset, bool savres)
19124 /* This blockage is needed so that sched doesn't decide to move
19125 the sp change before the register restores. */
19126 if (DEFAULT_ABI == ABI_V4
19128 && info->spe_64bit_regs_used != 0
19129 && info->first_gp_reg_save != 32))
19130 rs6000_emit_stack_tie ();
19132 if (frame_reg_rtx != sp_reg_rtx)
19134 if (sp_offset != 0)
19136 rtx dest_reg = savres ? gen_rtx_REG (Pmode, 11) : sp_reg_rtx;
19137 rtx insn = emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx,
19138 GEN_INT (sp_offset)));
19143 return emit_move_insn (sp_reg_rtx, frame_reg_rtx);
19145 else if (sp_offset != 0)
19147 /* If we are restoring registers out-of-line, we will be using the
19148 "exit" variants of the restore routines, which will reset the
19149 stack for us. But we do need to point r11 into the right place
19150 for those routines. */
19151 rtx dest_reg = (savres
19152 ? gen_rtx_REG (Pmode, 11)
19155 rtx insn = emit_insn (gen_add3_insn (dest_reg, sp_reg_rtx,
19156 GEN_INT (sp_offset)));
19163 /* Construct a parallel rtx describing the effect of a call to an
19164 out-of-line register save/restore routine, and emit the insn
19165 or jump_insn as appropriate. */
19168 rs6000_emit_savres_rtx (rs6000_stack_t *info,
19169 rtx frame_reg_rtx, int save_area_offset,
19170 enum machine_mode reg_mode,
19171 bool savep, bool gpr, bool lr)
19174 int offset, start_reg, end_reg, n_regs, use_reg;
19175 int reg_size = GET_MODE_SIZE (reg_mode);
19182 ? info->first_gp_reg_save
19183 : info->first_fp_reg_save);
19184 end_reg = gpr ? 32 : 64;
19185 n_regs = end_reg - start_reg;
19186 p = rtvec_alloc ((lr ? 4 : 3) + n_regs);
19189 RTVEC_ELT (p, offset++) = ret_rtx;
19191 RTVEC_ELT (p, offset++)
19192 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
19194 sym = rs6000_savres_routine_sym (info, savep, gpr, lr);
19195 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
19196 use_reg = DEFAULT_ABI == ABI_AIX ? (gpr && !lr ? 12 : 1)
19197 : DEFAULT_ABI == ABI_DARWIN && !gpr ? 1
19199 RTVEC_ELT (p, offset++)
19200 = gen_rtx_USE (VOIDmode,
19201 gen_rtx_REG (Pmode, use_reg));
19203 for (i = 0; i < end_reg - start_reg; i++)
19205 rtx addr, reg, mem;
19206 reg = gen_rtx_REG (reg_mode, start_reg + i);
19207 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19208 GEN_INT (save_area_offset + reg_size*i));
19209 mem = gen_frame_mem (reg_mode, addr);
19211 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode,
19213 savep ? reg : mem);
19218 rtx addr, reg, mem;
19219 reg = gen_rtx_REG (Pmode, 0);
19220 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19221 GEN_INT (info->lr_save_offset));
19222 mem = gen_frame_mem (Pmode, addr);
19223 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode, mem, reg);
19226 par = gen_rtx_PARALLEL (VOIDmode, p);
19230 insn = emit_jump_insn (par);
19231 JUMP_LABEL (insn) = ret_rtx;
19234 insn = emit_insn (par);
19238 /* Determine whether the gp REG is really used. */
19241 rs6000_reg_live_or_pic_offset_p (int reg)
19243 /* If the function calls eh_return, claim used all the registers that would
19244 be checked for liveness otherwise. This is required for the PIC offset
19245 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19246 register allocation purposes in this case. */
19248 return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
19249 && (!call_used_regs[reg]
19250 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19251 && !TARGET_SINGLE_PIC_BASE
19252 && TARGET_TOC && TARGET_MINIMAL_TOC)))
19253 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19254 && !TARGET_SINGLE_PIC_BASE
19255 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
19256 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
19259 /* Emit function prologue as insns. */
19262 rs6000_emit_prologue (void)
19264 rs6000_stack_t *info = rs6000_stack_info ();
19265 enum machine_mode reg_mode = Pmode;
19266 int reg_size = TARGET_32BIT ? 4 : 8;
19267 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
19268 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
19269 rtx frame_reg_rtx = sp_reg_rtx;
19270 rtx cr_save_rtx = NULL_RTX;
19273 int saving_FPRs_inline;
19274 int saving_GPRs_inline;
19275 int using_store_multiple;
19276 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19277 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19278 && call_used_regs[STATIC_CHAIN_REGNUM]);
19279 HOST_WIDE_INT sp_offset = 0;
19281 if (flag_stack_usage_info)
19282 current_function_static_stack_size = info->total_size;
19284 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && info->total_size)
19285 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, info->total_size);
19287 if (TARGET_FIX_AND_CONTINUE)
19289 /* gdb on darwin arranges to forward a function from the old
19290 address by modifying the first 5 instructions of the function
19291 to branch to the overriding function. This is necessary to
19292 permit function pointers that point to the old function to
19293 actually forward to the new function. */
19294 emit_insn (gen_nop ());
19295 emit_insn (gen_nop ());
19296 emit_insn (gen_nop ());
19297 emit_insn (gen_nop ());
19298 emit_insn (gen_nop ());
19301 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
19303 reg_mode = V2SImode;
19307 strategy = info->savres_strategy;
19308 using_store_multiple = strategy & SAVRES_MULTIPLE;
19309 saving_FPRs_inline = strategy & SAVE_INLINE_FPRS;
19310 saving_GPRs_inline = strategy & SAVE_INLINE_GPRS;
19312 /* For V.4, update stack before we do any saving and set back pointer. */
19313 if (! WORLD_SAVE_P (info)
19315 && (DEFAULT_ABI == ABI_V4
19316 || crtl->calls_eh_return))
19318 bool need_r11 = (TARGET_SPE
19319 ? (!saving_GPRs_inline
19320 && info->spe_64bit_regs_used == 0)
19321 : (!saving_FPRs_inline || !saving_GPRs_inline));
19322 rtx copy_reg = need_r11 ? gen_rtx_REG (Pmode, 11) : NULL;
19324 if (info->total_size < 32767)
19325 sp_offset = info->total_size;
19327 frame_reg_rtx = copy_reg;
19328 else if (info->cr_save_p
19330 || info->first_fp_reg_save < 64
19331 || info->first_gp_reg_save < 32
19332 || info->altivec_size != 0
19333 || info->vrsave_mask != 0
19334 || crtl->calls_eh_return)
19336 copy_reg = frame_ptr_rtx;
19337 frame_reg_rtx = copy_reg;
19341 /* The prologue won't be saving any regs so there is no need
19342 to set up a frame register to access any frame save area.
19343 We also won't be using sp_offset anywhere below, but set
19344 the correct value anyway to protect against future
19345 changes to this function. */
19346 sp_offset = info->total_size;
19348 rs6000_emit_allocate_stack (info->total_size, copy_reg);
19349 if (frame_reg_rtx != sp_reg_rtx)
19350 rs6000_emit_stack_tie ();
19353 /* Handle world saves specially here. */
19354 if (WORLD_SAVE_P (info))
19361 /* save_world expects lr in r0. */
19362 reg0 = gen_rtx_REG (Pmode, 0);
19363 if (info->lr_save_p)
19365 insn = emit_move_insn (reg0,
19366 gen_rtx_REG (Pmode, LR_REGNO));
19367 RTX_FRAME_RELATED_P (insn) = 1;
19370 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19371 assumptions about the offsets of various bits of the stack
19373 gcc_assert (info->gp_save_offset == -220
19374 && info->fp_save_offset == -144
19375 && info->lr_save_offset == 8
19376 && info->cr_save_offset == 4
19379 && (!crtl->calls_eh_return
19380 || info->ehrd_offset == -432)
19381 && info->vrsave_save_offset == -224
19382 && info->altivec_save_offset == -416);
19384 treg = gen_rtx_REG (SImode, 11);
19385 emit_move_insn (treg, GEN_INT (-info->total_size));
19387 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19388 in R11. It also clobbers R12, so beware! */
19390 /* Preserve CR2 for save_world prologues */
19392 sz += 32 - info->first_gp_reg_save;
19393 sz += 64 - info->first_fp_reg_save;
19394 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
19395 p = rtvec_alloc (sz);
19397 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
19398 gen_rtx_REG (SImode,
19400 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
19401 gen_rtx_SYMBOL_REF (Pmode,
19403 /* We do floats first so that the instruction pattern matches
19405 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19407 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19408 ? DFmode : SFmode),
19409 info->first_fp_reg_save + i);
19410 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19411 GEN_INT (info->fp_save_offset
19412 + sp_offset + 8 * i));
19413 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19414 ? DFmode : SFmode), addr);
19416 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19418 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
19420 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
19421 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19422 GEN_INT (info->altivec_save_offset
19423 + sp_offset + 16 * i));
19424 rtx mem = gen_frame_mem (V4SImode, addr);
19426 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19428 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19430 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19431 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19432 GEN_INT (info->gp_save_offset
19433 + sp_offset + reg_size * i));
19434 rtx mem = gen_frame_mem (reg_mode, addr);
19436 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19440 /* CR register traditionally saved as CR2. */
19441 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
19442 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19443 GEN_INT (info->cr_save_offset
19445 rtx mem = gen_frame_mem (reg_mode, addr);
19447 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19449 /* Explain about use of R0. */
19450 if (info->lr_save_p)
19452 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19453 GEN_INT (info->lr_save_offset
19455 rtx mem = gen_frame_mem (reg_mode, addr);
19457 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
19459 /* Explain what happens to the stack pointer. */
19461 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
19462 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
19465 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19466 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19467 treg, GEN_INT (-info->total_size));
19468 sp_offset = info->total_size;
19471 /* If we use the link register, get it into r0. */
19472 if (!WORLD_SAVE_P (info) && info->lr_save_p)
19474 rtx addr, reg, mem;
19476 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
19477 gen_rtx_REG (Pmode, LR_REGNO));
19478 RTX_FRAME_RELATED_P (insn) = 1;
19480 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
19481 | SAVE_NOINLINE_FPRS_SAVES_LR)))
19483 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19484 GEN_INT (info->lr_save_offset + sp_offset));
19485 reg = gen_rtx_REG (Pmode, 0);
19486 mem = gen_rtx_MEM (Pmode, addr);
19487 /* This should not be of rs6000_sr_alias_set, because of
19488 __builtin_return_address. */
19490 insn = emit_move_insn (mem, reg);
19491 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19492 NULL_RTX, NULL_RTX);
19496 /* If we need to save CR, put it into r12 or r11. */
19497 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
19502 = gen_rtx_REG (SImode, DEFAULT_ABI == ABI_AIX && !saving_GPRs_inline
19504 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19505 RTX_FRAME_RELATED_P (insn) = 1;
19506 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19507 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19508 But that's OK. All we have to do is specify that _one_ condition
19509 code register is saved in this stack slot. The thrower's epilogue
19510 will then restore all the call-saved registers.
19511 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19512 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
19513 gen_rtx_REG (SImode, CR2_REGNO));
19514 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19517 /* Do any required saving of fpr's. If only one or two to save, do
19518 it ourselves. Otherwise, call function. */
19519 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
19522 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19523 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
19524 && ! call_used_regs[info->first_fp_reg_save+i]))
19525 emit_frame_save (frame_reg_rtx, frame_ptr_rtx,
19526 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19528 info->first_fp_reg_save + i,
19529 info->fp_save_offset + sp_offset + 8 * i,
19532 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
19534 insn = rs6000_emit_savres_rtx (info, frame_reg_rtx,
19535 info->fp_save_offset + sp_offset,
19537 /*savep=*/true, /*gpr=*/false,
19539 & SAVE_NOINLINE_FPRS_SAVES_LR)
19541 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19542 NULL_RTX, NULL_RTX);
19545 /* Save GPRs. This is done as a PARALLEL if we are using
19546 the store-multiple instructions. */
19547 if (!WORLD_SAVE_P (info)
19549 && info->spe_64bit_regs_used != 0
19550 && info->first_gp_reg_save != 32)
19553 rtx spe_save_area_ptr;
19554 int save_ptr_to_sp;
19555 int ool_adjust = 0;
19557 /* Determine whether we can address all of the registers that need
19558 to be saved with an offset from frame_reg_rtx that fits in
19559 the small const field for SPE memory instructions. */
19560 int spe_regs_addressable
19561 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + sp_offset
19562 + reg_size * (32 - info->first_gp_reg_save - 1))
19563 && saving_GPRs_inline);
19566 if (spe_regs_addressable)
19568 spe_save_area_ptr = frame_reg_rtx;
19569 save_ptr_to_sp = info->total_size - sp_offset;
19570 spe_offset = info->spe_gp_save_offset + sp_offset;
19574 /* Make r11 point to the start of the SPE save area. We need
19575 to be careful here if r11 is holding the static chain. If
19576 it is, then temporarily save it in r0. */
19579 if (!saving_GPRs_inline)
19580 ool_adjust = 8 * (info->first_gp_reg_save
19581 - (FIRST_SAVRES_REGISTER + 1));
19582 offset = info->spe_gp_save_offset + sp_offset - ool_adjust;
19583 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
19584 save_ptr_to_sp = info->total_size - sp_offset + offset;
19587 if (using_static_chain_p)
19589 rtx r0 = gen_rtx_REG (Pmode, 0);
19590 gcc_assert (info->first_gp_reg_save > 11);
19592 emit_move_insn (r0, spe_save_area_ptr);
19594 emit_insn (gen_addsi3 (spe_save_area_ptr,
19595 frame_reg_rtx, GEN_INT (offset)));
19596 if (REGNO (frame_reg_rtx) == 11)
19597 sp_offset = -info->spe_gp_save_offset + ool_adjust;
19600 if (saving_GPRs_inline)
19602 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19603 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19605 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19606 rtx offset, addr, mem;
19608 /* We're doing all this to ensure that the offset fits into
19609 the immediate offset of 'evstdd'. */
19610 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
19612 offset = GEN_INT (reg_size * i + spe_offset);
19613 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
19614 mem = gen_rtx_MEM (V2SImode, addr);
19616 insn = emit_move_insn (mem, reg);
19618 rs6000_frame_related (insn,
19619 spe_save_area_ptr, save_ptr_to_sp,
19620 NULL_RTX, NULL_RTX);
19625 insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
19626 ool_adjust, reg_mode,
19627 /*savep=*/true, /*gpr=*/true,
19630 rs6000_frame_related (insn, spe_save_area_ptr, save_ptr_to_sp,
19631 NULL_RTX, NULL_RTX);
19634 /* Move the static chain pointer back. */
19635 if (using_static_chain_p && !spe_regs_addressable)
19636 emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
19638 else if (!WORLD_SAVE_P (info) && !saving_GPRs_inline)
19640 if (DEFAULT_ABI == ABI_DARWIN)
19642 rtx dest_reg = gen_rtx_REG (Pmode, 11);
19643 if (info->first_fp_reg_save == 64)
19645 /* we only need a copy, no fprs were saved. */
19646 if (dest_reg != frame_reg_rtx)
19647 emit_move_insn (dest_reg, frame_reg_rtx);
19651 int save_off = 8 * (64 - info->first_fp_reg_save);
19652 rtx offset = GEN_INT (sp_offset - save_off);
19654 if (REGNO (dest_reg) == REGNO (frame_reg_rtx))
19655 sp_offset = save_off;
19656 emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx, offset));
19659 /* Need to adjust r11 (r12) if we saved any FPRs. */
19660 else if (info->first_fp_reg_save != 64)
19662 rtx dest_reg = gen_rtx_REG (Pmode, DEFAULT_ABI == ABI_AIX ? 12 : 11);
19663 int save_off = 8 * (64 - info->first_fp_reg_save);
19664 rtx offset = GEN_INT (sp_offset - save_off);
19666 if (REGNO (dest_reg) == REGNO (frame_reg_rtx))
19667 sp_offset = save_off;
19668 emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx, offset));
19671 insn = rs6000_emit_savres_rtx (info, frame_reg_rtx,
19672 info->gp_save_offset + sp_offset,
19674 /*savep=*/true, /*gpr=*/true,
19676 & SAVE_NOINLINE_GPRS_SAVES_LR)
19678 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19679 NULL_RTX, NULL_RTX);
19681 else if (!WORLD_SAVE_P (info) && using_store_multiple)
19685 p = rtvec_alloc (32 - info->first_gp_reg_save);
19686 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19688 rtx addr, reg, mem;
19689 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19690 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19691 GEN_INT (info->gp_save_offset
19694 mem = gen_frame_mem (reg_mode, addr);
19696 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
19698 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19699 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19700 NULL_RTX, NULL_RTX);
19702 else if (!WORLD_SAVE_P (info))
19705 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19706 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19708 rtx addr, reg, mem;
19709 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19711 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19712 GEN_INT (info->gp_save_offset
19715 mem = gen_frame_mem (reg_mode, addr);
19717 insn = emit_move_insn (mem, reg);
19718 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19719 NULL_RTX, NULL_RTX);
19723 /* ??? There's no need to emit actual instructions here, but it's the
19724 easiest way to get the frame unwind information emitted. */
19725 if (crtl->calls_eh_return)
19727 unsigned int i, regno;
19731 regno = EH_RETURN_DATA_REGNO (i);
19732 if (regno == INVALID_REGNUM)
19735 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
19736 info->ehrd_offset + sp_offset
19737 + reg_size * (int) i,
19742 /* In AIX ABI we need to make sure r2 is really saved. */
19743 if (TARGET_AIX && crtl->calls_eh_return)
19745 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
19746 rtx save_insn, join_insn, note;
19747 long toc_restore_insn;
19749 gcc_assert (frame_reg_rtx == frame_ptr_rtx
19750 || frame_reg_rtx == sp_reg_rtx);
19751 tmp_reg = gen_rtx_REG (Pmode, 11);
19752 tmp_reg_si = gen_rtx_REG (SImode, 11);
19753 if (using_static_chain_p)
19754 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
19755 gcc_assert (saving_GPRs_inline && saving_FPRs_inline);
19756 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
19757 /* Peek at instruction to which this function returns. If it's
19758 restoring r2, then we know we've already saved r2. We can't
19759 unconditionally save r2 because the value we have will already
19760 be updated if we arrived at this function via a plt call or
19761 toc adjusting stub. */
19762 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
19763 toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
19764 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
19765 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
19766 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
19767 validate_condition_mode (EQ, CCUNSmode);
19768 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
19769 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
19770 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
19771 toc_save_done = gen_label_rtx ();
19772 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
19773 gen_rtx_EQ (VOIDmode, compare_result,
19775 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
19777 jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
19778 JUMP_LABEL (jump) = toc_save_done;
19779 LABEL_NUSES (toc_save_done) += 1;
19781 save_insn = emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode,
19782 TOC_REGNUM, sp_offset + 5 * reg_size,
19785 emit_label (toc_save_done);
19787 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
19788 have a CFG that has different saves along different paths.
19789 Move the note to a dummy blockage insn, which describes that
19790 R2 is unconditionally saved after the label. */
19791 /* ??? An alternate representation might be a special insn pattern
19792 containing both the branch and the store. That might let the
19793 code that minimizes the number of DW_CFA_advance opcodes better
19794 freedom in placing the annotations. */
19795 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
19797 remove_note (save_insn, note);
19798 RTX_FRAME_RELATED_P (save_insn) = 0;
19800 join_insn = emit_insn (gen_blockage ());
19801 REG_NOTES (join_insn) = note;
19802 RTX_FRAME_RELATED_P (join_insn) = 1;
19804 if (using_static_chain_p)
19805 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
19808 /* Save CR if we use any that must be preserved. */
19809 if (!WORLD_SAVE_P (info) && info->cr_save_p)
19811 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19812 GEN_INT (info->cr_save_offset + sp_offset));
19813 rtx mem = gen_frame_mem (SImode, addr);
19814 /* See the large comment above about why CR2_REGNO is used. */
19815 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
19817 /* If r12 was used to hold the original sp, copy cr into r0 now
19819 if (REGNO (frame_reg_rtx) == 12)
19823 cr_save_rtx = gen_rtx_REG (SImode, 0);
19824 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19825 RTX_FRAME_RELATED_P (insn) = 1;
19826 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
19827 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19829 insn = emit_move_insn (mem, cr_save_rtx);
19831 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19832 NULL_RTX, NULL_RTX);
19835 /* Update stack and set back pointer unless this is V.4,
19836 for which it was done previously. */
19837 if (!WORLD_SAVE_P (info) && info->push_p
19838 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
19840 rtx copy_reg = NULL;
19842 if (info->total_size < 32767)
19843 sp_offset = info->total_size;
19844 else if (info->altivec_size != 0
19845 || info->vrsave_mask != 0)
19847 copy_reg = frame_ptr_rtx;
19848 frame_reg_rtx = copy_reg;
19851 sp_offset = info->total_size;
19852 rs6000_emit_allocate_stack (info->total_size, copy_reg);
19853 if (frame_reg_rtx != sp_reg_rtx)
19854 rs6000_emit_stack_tie ();
19857 /* Set frame pointer, if needed. */
19858 if (frame_pointer_needed)
19860 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
19862 RTX_FRAME_RELATED_P (insn) = 1;
19865 /* Save AltiVec registers if needed. Save here because the red zone does
19866 not include AltiVec registers. */
19867 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
19871 /* There should be a non inline version of this, for when we
19872 are saving lots of vector registers. */
19873 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
19874 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
19876 rtx areg, savereg, mem;
19879 offset = info->altivec_save_offset + sp_offset
19880 + 16 * (i - info->first_altivec_reg_save);
19882 savereg = gen_rtx_REG (V4SImode, i);
19884 areg = gen_rtx_REG (Pmode, 0);
19885 emit_move_insn (areg, GEN_INT (offset));
19887 /* AltiVec addressing mode is [reg+reg]. */
19888 mem = gen_frame_mem (V4SImode,
19889 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
19891 insn = emit_move_insn (mem, savereg);
19893 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19894 areg, GEN_INT (offset));
19898 /* VRSAVE is a bit vector representing which AltiVec registers
19899 are used. The OS uses this to determine which vector
19900 registers to save on a context switch. We need to save
19901 VRSAVE on the stack frame, add whatever AltiVec registers we
19902 used in this function, and do the corresponding magic in the
19905 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
19906 && info->vrsave_mask != 0)
19908 rtx reg, mem, vrsave;
19911 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
19912 as frame_reg_rtx and r11 as the static chain pointer for
19913 nested functions. */
19914 reg = gen_rtx_REG (SImode, 0);
19915 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
19917 emit_insn (gen_get_vrsave_internal (reg));
19919 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
19921 if (!WORLD_SAVE_P (info))
19924 offset = info->vrsave_save_offset + sp_offset;
19925 mem = gen_frame_mem (SImode,
19926 gen_rtx_PLUS (Pmode, frame_reg_rtx,
19927 GEN_INT (offset)));
19928 insn = emit_move_insn (mem, reg);
19931 /* Include the registers in the mask. */
19932 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
19934 insn = emit_insn (generate_set_vrsave (reg, info, 0));
19937 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
19938 if (!TARGET_SINGLE_PIC_BASE
19939 && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
19940 || (DEFAULT_ABI == ABI_V4
19941 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
19942 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
19944 /* If emit_load_toc_table will use the link register, we need to save
19945 it. We use R12 for this purpose because emit_load_toc_table
19946 can use register 0. This allows us to use a plain 'blr' to return
19947 from the procedure more often. */
19948 int save_LR_around_toc_setup = (TARGET_ELF
19949 && DEFAULT_ABI != ABI_AIX
19951 && ! info->lr_save_p
19952 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
19953 if (save_LR_around_toc_setup)
19955 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
19957 insn = emit_move_insn (frame_ptr_rtx, lr);
19958 RTX_FRAME_RELATED_P (insn) = 1;
19960 rs6000_emit_load_toc_table (TRUE);
19962 insn = emit_move_insn (lr, frame_ptr_rtx);
19963 add_reg_note (insn, REG_CFA_RESTORE, lr);
19964 RTX_FRAME_RELATED_P (insn) = 1;
19967 rs6000_emit_load_toc_table (TRUE);
19971 if (!TARGET_SINGLE_PIC_BASE
19972 && DEFAULT_ABI == ABI_DARWIN
19973 && flag_pic && crtl->uses_pic_offset_table)
19975 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
19976 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
19978 /* Save and restore LR locally around this call (in R0). */
19979 if (!info->lr_save_p)
19980 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
19982 emit_insn (gen_load_macho_picbase (src));
19984 emit_move_insn (gen_rtx_REG (Pmode,
19985 RS6000_PIC_OFFSET_TABLE_REGNUM),
19988 if (!info->lr_save_p)
19989 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
19993 /* If we need to, save the TOC register after doing the stack setup.
19994 Do not emit eh frame info for this save. The unwinder wants info,
19995 conceptually attached to instructions in this function, about
19996 register values in the caller of this function. This R2 may have
19997 already been changed from the value in the caller.
19998 We don't attempt to write accurate DWARF EH frame info for R2
19999 because code emitted by gcc for a (non-pointer) function call
20000 doesn't save and restore R2. Instead, R2 is managed out-of-line
20001 by a linker generated plt call stub when the function resides in
20002 a shared library. This behaviour is costly to describe in DWARF,
20003 both in terms of the size of DWARF info and the time taken in the
20004 unwinder to interpret it. R2 changes, apart from the
20005 calls_eh_return case earlier in this function, are handled by
20006 linux-unwind.h frob_update_context. */
20007 if (rs6000_save_toc_in_prologue_p ())
20009 rtx addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, GEN_INT (5 * reg_size));
20010 rtx mem = gen_frame_mem (reg_mode, addr);
20011 emit_move_insn (mem, gen_rtx_REG (reg_mode, TOC_REGNUM));
20015 /* Write function prologue. */
20018 rs6000_output_function_prologue (FILE *file,
20019 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20021 rs6000_stack_t *info = rs6000_stack_info ();
20023 if (TARGET_DEBUG_STACK)
20024 debug_stack_info (info);
20026 /* Write .extern for any function we will call to save and restore
20028 if (info->first_fp_reg_save < 64
20032 int regno = info->first_fp_reg_save - 32;
20034 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
20036 name = rs6000_savres_routine_name (info, regno, /*savep=*/true,
20037 /*gpr=*/false, /*lr=*/false);
20038 fprintf (file, "\t.extern %s\n", name);
20040 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
20042 name = rs6000_savres_routine_name (info, regno, /*savep=*/false,
20043 /*gpr=*/false, /*lr=*/true);
20044 fprintf (file, "\t.extern %s\n", name);
20048 /* Write .extern for AIX common mode routines, if needed. */
20049 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
20051 fputs ("\t.extern __mulh\n", file);
20052 fputs ("\t.extern __mull\n", file);
20053 fputs ("\t.extern __divss\n", file);
20054 fputs ("\t.extern __divus\n", file);
20055 fputs ("\t.extern __quoss\n", file);
20056 fputs ("\t.extern __quous\n", file);
20057 common_mode_defined = 1;
20060 rs6000_pic_labelno++;
20063 /* Non-zero if vmx regs are restored before the frame pop, zero if
20064 we restore after the pop when possible. */
20065 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20067 /* Reload CR from REG. */
20070 rs6000_restore_saved_cr (rtx reg, int using_mfcr_multiple)
20075 if (using_mfcr_multiple)
20077 for (i = 0; i < 8; i++)
20078 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20080 gcc_assert (count);
20083 if (using_mfcr_multiple && count > 1)
20088 p = rtvec_alloc (count);
20091 for (i = 0; i < 8; i++)
20092 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20094 rtvec r = rtvec_alloc (2);
20095 RTVEC_ELT (r, 0) = reg;
20096 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
20097 RTVEC_ELT (p, ndx) =
20098 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
20099 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20102 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20103 gcc_assert (ndx == count);
20106 for (i = 0; i < 8; i++)
20107 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20109 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
20115 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20116 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20117 below stack pointer not cloberred by signals. */
20120 offset_below_red_zone_p (HOST_WIDE_INT offset)
20122 return offset < (DEFAULT_ABI == ABI_V4
20124 : TARGET_32BIT ? -220 : -288);
20127 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20130 emit_cfa_restores (rtx cfa_restores)
20132 rtx insn = get_last_insn ();
20133 rtx *loc = ®_NOTES (insn);
20136 loc = &XEXP (*loc, 1);
20137 *loc = cfa_restores;
20138 RTX_FRAME_RELATED_P (insn) = 1;
20141 /* Emit function epilogue as insns. */
20144 rs6000_emit_epilogue (int sibcall)
20146 rs6000_stack_t *info;
20147 int restoring_GPRs_inline;
20148 int restoring_FPRs_inline;
20149 int using_load_multiple;
20150 int using_mtcr_multiple;
20151 int use_backchain_to_restore_sp;
20155 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
20156 rtx frame_reg_rtx = sp_reg_rtx;
20157 rtx cfa_restores = NULL_RTX;
20159 rtx cr_save_reg = NULL_RTX;
20160 enum machine_mode reg_mode = Pmode;
20161 int reg_size = TARGET_32BIT ? 4 : 8;
20164 info = rs6000_stack_info ();
20166 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
20168 reg_mode = V2SImode;
20172 strategy = info->savres_strategy;
20173 using_load_multiple = strategy & SAVRES_MULTIPLE;
20174 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
20175 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
20176 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
20177 || rs6000_cpu == PROCESSOR_PPC603
20178 || rs6000_cpu == PROCESSOR_PPC750
20180 /* Restore via the backchain when we have a large frame, since this
20181 is more efficient than an addis, addi pair. The second condition
20182 here will not trigger at the moment; We don't actually need a
20183 frame pointer for alloca, but the generic parts of the compiler
20184 give us one anyway. */
20185 use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
20186 || (cfun->calls_alloca
20187 && !frame_pointer_needed));
20188 restore_lr = (info->lr_save_p
20189 && (restoring_FPRs_inline
20190 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
20191 && (restoring_GPRs_inline
20192 || info->first_fp_reg_save < 64));
20194 if (WORLD_SAVE_P (info))
20198 const char *alloc_rname;
20201 /* eh_rest_world_r10 will return to the location saved in the LR
20202 stack slot (which is not likely to be our caller.)
20203 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20204 rest_world is similar, except any R10 parameter is ignored.
20205 The exception-handling stuff that was here in 2.95 is no
20206 longer necessary. */
20210 + 32 - info->first_gp_reg_save
20211 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
20212 + 63 + 1 - info->first_fp_reg_save);
20214 strcpy (rname, ((crtl->calls_eh_return) ?
20215 "*eh_rest_world_r10" : "*rest_world"));
20216 alloc_rname = ggc_strdup (rname);
20219 RTVEC_ELT (p, j++) = ret_rtx;
20220 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
20221 gen_rtx_REG (Pmode,
20224 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
20225 /* The instruction pattern requires a clobber here;
20226 it is shared with the restVEC helper. */
20228 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
20231 /* CR register traditionally saved as CR2. */
20232 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
20233 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20234 GEN_INT (info->cr_save_offset));
20235 rtx mem = gen_frame_mem (reg_mode, addr);
20237 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20239 if (flag_shrink_wrap)
20241 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20242 gen_rtx_REG (Pmode, LR_REGNO),
20244 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20248 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20250 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20251 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20252 GEN_INT (info->gp_save_offset
20254 rtx mem = gen_frame_mem (reg_mode, addr);
20256 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20257 if (flag_shrink_wrap)
20258 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20260 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
20262 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
20263 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20264 GEN_INT (info->altivec_save_offset
20266 rtx mem = gen_frame_mem (V4SImode, addr);
20268 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20269 if (flag_shrink_wrap)
20270 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20272 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
20274 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20275 ? DFmode : SFmode),
20276 info->first_fp_reg_save + i);
20277 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20278 GEN_INT (info->fp_save_offset
20280 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20281 ? DFmode : SFmode), addr);
20283 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20284 if (flag_shrink_wrap)
20285 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20288 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
20290 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
20292 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
20294 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
20296 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
20297 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20299 if (flag_shrink_wrap)
20301 REG_NOTES (insn) = cfa_restores;
20302 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20303 RTX_FRAME_RELATED_P (insn) = 1;
20308 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
20310 sp_offset = info->total_size;
20312 /* Restore AltiVec registers if we must do so before adjusting the
20314 if (TARGET_ALTIVEC_ABI
20315 && info->altivec_size != 0
20316 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20317 || (DEFAULT_ABI != ABI_V4
20318 && offset_below_red_zone_p (info->altivec_save_offset))))
20322 if (use_backchain_to_restore_sp)
20324 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20325 emit_move_insn (frame_reg_rtx,
20326 gen_rtx_MEM (Pmode, sp_reg_rtx));
20329 else if (frame_pointer_needed)
20330 frame_reg_rtx = hard_frame_pointer_rtx;
20332 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20333 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20335 rtx addr, areg, mem, reg;
20337 areg = gen_rtx_REG (Pmode, 0);
20339 (areg, GEN_INT (info->altivec_save_offset
20341 + 16 * (i - info->first_altivec_reg_save)));
20343 /* AltiVec addressing mode is [reg+reg]. */
20344 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20345 mem = gen_frame_mem (V4SImode, addr);
20347 reg = gen_rtx_REG (V4SImode, i);
20348 emit_move_insn (reg, mem);
20349 if (flag_shrink_wrap
20350 || offset_below_red_zone_p (info->altivec_save_offset
20351 + (i - info->first_altivec_reg_save)
20353 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20358 /* Restore VRSAVE if we must do so before adjusting the stack. */
20360 && TARGET_ALTIVEC_VRSAVE
20361 && info->vrsave_mask != 0
20362 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20363 || (DEFAULT_ABI != ABI_V4
20364 && offset_below_red_zone_p (info->vrsave_save_offset))))
20366 rtx addr, mem, reg;
20368 if (frame_reg_rtx == sp_reg_rtx)
20370 if (use_backchain_to_restore_sp)
20372 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20373 emit_move_insn (frame_reg_rtx,
20374 gen_rtx_MEM (Pmode, sp_reg_rtx));
20377 else if (frame_pointer_needed)
20378 frame_reg_rtx = hard_frame_pointer_rtx;
20381 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20382 GEN_INT (info->vrsave_save_offset + sp_offset));
20383 mem = gen_frame_mem (SImode, addr);
20384 reg = gen_rtx_REG (SImode, 12);
20385 emit_move_insn (reg, mem);
20387 emit_insn (generate_set_vrsave (reg, info, 1));
20391 /* If we have a large stack frame, restore the old stack pointer
20392 using the backchain. */
20393 if (use_backchain_to_restore_sp)
20395 if (frame_reg_rtx == sp_reg_rtx)
20397 /* Under V.4, don't reset the stack pointer until after we're done
20398 loading the saved registers. */
20399 if (DEFAULT_ABI == ABI_V4)
20400 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20402 insn = emit_move_insn (frame_reg_rtx,
20403 gen_rtx_MEM (Pmode, sp_reg_rtx));
20406 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20407 && DEFAULT_ABI == ABI_V4)
20408 /* frame_reg_rtx has been set up by the altivec restore. */
20412 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
20413 frame_reg_rtx = sp_reg_rtx;
20416 /* If we have a frame pointer, we can restore the old stack pointer
20418 else if (frame_pointer_needed)
20420 frame_reg_rtx = sp_reg_rtx;
20421 if (DEFAULT_ABI == ABI_V4)
20422 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20423 /* Prevent reordering memory accesses against stack pointer restore. */
20424 else if (cfun->calls_alloca
20425 || offset_below_red_zone_p (-info->total_size))
20427 rtx mem1 = gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx);
20428 rtx mem2 = gen_rtx_MEM (BLKmode, sp_reg_rtx);
20429 MEM_NOTRAP_P (mem1) = 1;
20430 MEM_NOTRAP_P (mem2) = 1;
20431 emit_insn (gen_frame_tie (mem1, mem2));
20434 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
20435 GEN_INT (info->total_size)));
20438 else if (info->push_p
20439 && DEFAULT_ABI != ABI_V4
20440 && !crtl->calls_eh_return)
20442 /* Prevent reordering memory accesses against stack pointer restore. */
20443 if (cfun->calls_alloca
20444 || offset_below_red_zone_p (-info->total_size))
20446 rtx mem = gen_rtx_MEM (BLKmode, sp_reg_rtx);
20447 MEM_NOTRAP_P (mem) = 1;
20448 emit_insn (gen_stack_tie (mem));
20450 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
20451 GEN_INT (info->total_size)));
20454 if (insn && frame_reg_rtx == sp_reg_rtx)
20458 REG_NOTES (insn) = cfa_restores;
20459 cfa_restores = NULL_RTX;
20461 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20462 RTX_FRAME_RELATED_P (insn) = 1;
20465 /* Restore AltiVec registers if we have not done so already. */
20466 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20467 && TARGET_ALTIVEC_ABI
20468 && info->altivec_size != 0
20469 && (DEFAULT_ABI == ABI_V4
20470 || !offset_below_red_zone_p (info->altivec_save_offset)))
20474 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20475 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20477 rtx addr, areg, mem, reg;
20479 areg = gen_rtx_REG (Pmode, 0);
20481 (areg, GEN_INT (info->altivec_save_offset
20483 + 16 * (i - info->first_altivec_reg_save)));
20485 /* AltiVec addressing mode is [reg+reg]. */
20486 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20487 mem = gen_frame_mem (V4SImode, addr);
20489 reg = gen_rtx_REG (V4SImode, i);
20490 emit_move_insn (reg, mem);
20491 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20492 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20497 /* Restore VRSAVE if we have not done so already. */
20498 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20500 && TARGET_ALTIVEC_VRSAVE
20501 && info->vrsave_mask != 0
20502 && (DEFAULT_ABI == ABI_V4
20503 || !offset_below_red_zone_p (info->vrsave_save_offset)))
20505 rtx addr, mem, reg;
20507 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20508 GEN_INT (info->vrsave_save_offset + sp_offset));
20509 mem = gen_frame_mem (SImode, addr);
20510 reg = gen_rtx_REG (SImode, 12);
20511 emit_move_insn (reg, mem);
20513 emit_insn (generate_set_vrsave (reg, info, 1));
20516 /* Get the old lr if we saved it. If we are restoring registers
20517 out-of-line, then the out-of-line routines can do this for us. */
20518 if (restore_lr && restoring_GPRs_inline)
20520 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
20521 info->lr_save_offset + sp_offset);
20523 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
20526 /* Get the old cr if we saved it. */
20527 if (info->cr_save_p)
20529 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20530 GEN_INT (info->cr_save_offset + sp_offset));
20531 rtx mem = gen_frame_mem (SImode, addr);
20533 cr_save_reg = gen_rtx_REG (SImode,
20534 DEFAULT_ABI == ABI_AIX
20535 && !restoring_GPRs_inline
20536 && info->first_fp_reg_save < 64
20538 emit_move_insn (cr_save_reg, mem);
20541 /* Set LR here to try to overlap restores below. */
20542 if (restore_lr && restoring_GPRs_inline)
20543 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
20544 gen_rtx_REG (Pmode, 0));
20546 /* Load exception handler data registers, if needed. */
20547 if (crtl->calls_eh_return)
20549 unsigned int i, regno;
20553 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20554 GEN_INT (sp_offset + 5 * reg_size));
20555 rtx mem = gen_frame_mem (reg_mode, addr);
20557 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
20564 regno = EH_RETURN_DATA_REGNO (i);
20565 if (regno == INVALID_REGNUM)
20568 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
20569 info->ehrd_offset + sp_offset
20570 + reg_size * (int) i);
20572 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
20576 /* Restore GPRs. This is done as a PARALLEL if we are using
20577 the load-multiple instructions. */
20579 && info->spe_64bit_regs_used
20580 && info->first_gp_reg_save != 32)
20582 /* Determine whether we can address all of the registers that need
20583 to be saved with an offset from frame_reg_rtx that fits in
20584 the small const field for SPE memory instructions. */
20585 int spe_regs_addressable
20586 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + sp_offset
20587 + reg_size * (32 - info->first_gp_reg_save - 1))
20588 && restoring_GPRs_inline);
20590 int ool_adjust = 0;
20592 if (spe_regs_addressable)
20593 spe_offset = info->spe_gp_save_offset + sp_offset;
20596 rtx old_frame_reg_rtx = frame_reg_rtx;
20597 /* Make r11 point to the start of the SPE save area. We worried about
20598 not clobbering it when we were saving registers in the prologue.
20599 There's no need to worry here because the static chain is passed
20600 anew to every function. */
20602 if (!restoring_GPRs_inline)
20603 ool_adjust = 8 * (info->first_gp_reg_save
20604 - (FIRST_SAVRES_REGISTER + 1));
20605 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20606 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
20607 GEN_INT (info->spe_gp_save_offset
20610 /* Keep the invariant that frame_reg_rtx + sp_offset points
20611 at the top of the stack frame. */
20612 sp_offset = -info->spe_gp_save_offset + ool_adjust;
20617 if (restoring_GPRs_inline)
20619 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20620 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20622 rtx offset, addr, mem, reg;
20624 /* We're doing all this to ensure that the immediate offset
20625 fits into the immediate field of 'evldd'. */
20626 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
20628 offset = GEN_INT (spe_offset + reg_size * i);
20629 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
20630 mem = gen_rtx_MEM (V2SImode, addr);
20631 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20633 emit_move_insn (reg, mem);
20637 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20638 ool_adjust, reg_mode,
20639 /*savep=*/false, /*gpr=*/true,
20642 else if (!restoring_GPRs_inline)
20644 /* We are jumping to an out-of-line function. */
20645 bool can_use_exit = info->first_fp_reg_save == 64;
20647 /* Emit stack reset code if we need it. */
20650 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
20651 sp_offset, can_use_exit);
20652 if (DEFAULT_ABI == ABI_DARWIN)
20653 /* we only need a copy, no fprs were saved. */
20654 emit_move_insn (gen_rtx_REG (Pmode, 11), frame_reg_rtx);
20656 if (info->cr_save_p)
20657 rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
20661 rtx src_reg = gen_rtx_REG (Pmode, DEFAULT_ABI == ABI_AIX ? 12 : 11);
20663 emit_insn (gen_add3_insn (src_reg, frame_reg_rtx,
20664 GEN_INT (sp_offset - info->fp_size)));
20665 if (REGNO (frame_reg_rtx) == REGNO (src_reg))
20666 sp_offset = info->fp_size;
20669 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20670 info->gp_save_offset, reg_mode,
20671 /*savep=*/false, /*gpr=*/true,
20672 /*lr=*/can_use_exit);
20674 else if (using_load_multiple)
20677 p = rtvec_alloc (32 - info->first_gp_reg_save);
20678 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20680 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20681 GEN_INT (info->gp_save_offset
20684 rtx mem = gen_frame_mem (reg_mode, addr);
20685 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20687 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, reg, mem);
20689 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20693 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20694 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20696 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20697 GEN_INT (info->gp_save_offset
20700 rtx mem = gen_frame_mem (reg_mode, addr);
20701 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20703 emit_move_insn (reg, mem);
20707 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20709 /* If the frame pointer was used then we can't delay emitting
20710 a REG_CFA_DEF_CFA note. This must happen on the insn that
20711 restores the frame pointer, r31. We may have already emitted
20712 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
20713 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
20714 be harmless if emitted. */
20715 if (frame_pointer_needed)
20717 insn = get_last_insn ();
20718 add_reg_note (insn, REG_CFA_DEF_CFA,
20719 plus_constant (frame_reg_rtx, sp_offset));
20720 RTX_FRAME_RELATED_P (insn) = 1;
20723 /* Set up cfa_restores. We always need these when
20724 shrink-wrapping. If not shrink-wrapping then we only need
20725 the cfa_restore when the stack location is no longer valid.
20726 The cfa_restores must be emitted on or before the insn that
20727 invalidates the stack, and of course must not be emitted
20728 before the insn that actually does the restore. The latter
20729 is why the LR cfa_restore condition below is a little
20730 complicated. It's also why it is a bad idea to emit the
20731 cfa_restores as a group on the last instruction here that
20732 actually does a restore: That insn may be reordered with
20733 respect to others doing restores. */
20734 if (info->cr_save_p)
20735 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20736 gen_rtx_REG (SImode, CR2_REGNO),
20738 if (flag_shrink_wrap
20740 || (info->lr_save_p
20741 && !restoring_GPRs_inline
20742 && info->first_fp_reg_save == 64)))
20743 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20744 gen_rtx_REG (Pmode, LR_REGNO),
20747 for (i = info->first_gp_reg_save; i < 32; i++)
20748 if (!restoring_GPRs_inline
20749 || using_load_multiple
20750 || rs6000_reg_live_or_pic_offset_p (i))
20752 rtx reg = gen_rtx_REG (reg_mode, i);
20754 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20758 if (!restoring_GPRs_inline
20759 && info->first_fp_reg_save == 64)
20761 /* We are jumping to an out-of-line function. */
20763 emit_cfa_restores (cfa_restores);
20767 if (restore_lr && !restoring_GPRs_inline)
20769 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
20770 info->lr_save_offset + sp_offset);
20772 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
20773 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
20774 gen_rtx_REG (Pmode, 0));
20777 /* Restore fpr's if we need to do it without calling a function. */
20778 if (restoring_FPRs_inline)
20779 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20780 if ((df_regs_ever_live_p (info->first_fp_reg_save + i)
20781 && !call_used_regs[info->first_fp_reg_save + i]))
20783 rtx addr, mem, reg;
20784 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20785 GEN_INT (info->fp_save_offset
20788 mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20789 ? DFmode : SFmode), addr);
20790 reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20791 ? DFmode : SFmode),
20792 info->first_fp_reg_save + i);
20794 emit_move_insn (reg, mem);
20795 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20796 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20799 /* If we saved cr, restore it here. Just those that were used. */
20800 if (info->cr_save_p)
20801 rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
20803 /* If this is V.4, unwind the stack pointer after all of the loads
20805 insn = rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
20806 sp_offset, !restoring_FPRs_inline);
20811 REG_NOTES (insn) = cfa_restores;
20812 cfa_restores = NULL_RTX;
20814 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20815 RTX_FRAME_RELATED_P (insn) = 1;
20818 if (crtl->calls_eh_return)
20820 rtx sa = EH_RETURN_STACKADJ_RTX;
20821 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
20827 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20828 if (! restoring_FPRs_inline)
20830 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
20831 RTVEC_ELT (p, 0) = ret_rtx;
20837 /* We can't hang the cfa_restores off a simple return,
20838 since the shrink-wrap code sometimes uses an existing
20839 return. This means there might be a path from
20840 pre-prologue code to this return, and dwarf2cfi code
20841 wants the eh_frame unwinder state to be the same on
20842 all paths to any point. So we need to emit the
20843 cfa_restores before the return. For -m64 we really
20844 don't need epilogue cfa_restores at all, except for
20845 this irritating dwarf2cfi with shrink-wrap
20846 requirement; The stack red-zone means eh_frame info
20847 from the prologue telling the unwinder to restore
20848 from the stack is perfectly good right to the end of
20850 emit_insn (gen_blockage ());
20851 emit_cfa_restores (cfa_restores);
20852 cfa_restores = NULL_RTX;
20854 p = rtvec_alloc (2);
20855 RTVEC_ELT (p, 0) = simple_return_rtx;
20858 RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
20859 ? gen_rtx_USE (VOIDmode,
20860 gen_rtx_REG (Pmode, LR_REGNO))
20861 : gen_rtx_CLOBBER (VOIDmode,
20862 gen_rtx_REG (Pmode, LR_REGNO)));
20864 /* If we have to restore more than two FP registers, branch to the
20865 restore function. It will return to our caller. */
20866 if (! restoring_FPRs_inline)
20871 if ((DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20873 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20874 gen_rtx_REG (Pmode, LR_REGNO),
20877 sym = rs6000_savres_routine_sym (info,
20881 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
20882 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
20883 gen_rtx_REG (Pmode,
20884 DEFAULT_ABI == ABI_AIX
20886 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20888 rtx addr, mem, reg;
20890 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
20891 GEN_INT (info->fp_save_offset + 8 * i));
20892 mem = gen_frame_mem (DFmode, addr);
20893 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
20895 RTVEC_ELT (p, i + 4) = gen_rtx_SET (VOIDmode, reg, mem);
20896 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20897 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20902 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20908 /* Ensure the cfa_restores are hung off an insn that won't
20909 be reordered above other restores. */
20910 emit_insn (gen_blockage ());
20912 emit_cfa_restores (cfa_restores);
20916 /* Write function epilogue. */
20919 rs6000_output_function_epilogue (FILE *file,
20920 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20923 macho_branch_islands ();
20924 /* Mach-O doesn't support labels at the end of objects, so if
20925 it looks like we might want one, insert a NOP. */
20927 rtx insn = get_last_insn ();
20928 rtx deleted_debug_label = NULL_RTX;
20931 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
20933 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
20934 notes only, instead set their CODE_LABEL_NUMBER to -1,
20935 otherwise there would be code generation differences
20936 in between -g and -g0. */
20937 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
20938 deleted_debug_label = insn;
20939 insn = PREV_INSN (insn);
20944 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
20945 fputs ("\tnop\n", file);
20946 else if (deleted_debug_label)
20947 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
20948 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
20949 CODE_LABEL_NUMBER (insn) = -1;
20953 /* Output a traceback table here. See /usr/include/sys/debug.h for info
20956 We don't output a traceback table if -finhibit-size-directive was
20957 used. The documentation for -finhibit-size-directive reads
20958 ``don't output a @code{.size} assembler directive, or anything
20959 else that would cause trouble if the function is split in the
20960 middle, and the two halves are placed at locations far apart in
20961 memory.'' The traceback table has this property, since it
20962 includes the offset from the start of the function to the
20963 traceback table itself.
20965 System V.4 Powerpc's (and the embedded ABI derived from it) use a
20966 different traceback table. */
20967 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
20968 && rs6000_traceback != traceback_none && !cfun->is_thunk)
20970 const char *fname = NULL;
20971 const char *language_string = lang_hooks.name;
20972 int fixed_parms = 0, float_parms = 0, parm_info = 0;
20974 int optional_tbtab;
20975 rs6000_stack_t *info = rs6000_stack_info ();
20977 if (rs6000_traceback == traceback_full)
20978 optional_tbtab = 1;
20979 else if (rs6000_traceback == traceback_part)
20980 optional_tbtab = 0;
20982 optional_tbtab = !optimize_size && !TARGET_ELF;
20984 if (optional_tbtab)
20986 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
20987 while (*fname == '.') /* V.4 encodes . in the name */
20990 /* Need label immediately before tbtab, so we can compute
20991 its offset from the function start. */
20992 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
20993 ASM_OUTPUT_LABEL (file, fname);
20996 /* The .tbtab pseudo-op can only be used for the first eight
20997 expressions, since it can't handle the possibly variable
20998 length fields that follow. However, if you omit the optional
20999 fields, the assembler outputs zeros for all optional fields
21000 anyways, giving each variable length field is minimum length
21001 (as defined in sys/debug.h). Thus we can not use the .tbtab
21002 pseudo-op at all. */
21004 /* An all-zero word flags the start of the tbtab, for debuggers
21005 that have to find it by searching forward from the entry
21006 point or from the current pc. */
21007 fputs ("\t.long 0\n", file);
21009 /* Tbtab format type. Use format type 0. */
21010 fputs ("\t.byte 0,", file);
21012 /* Language type. Unfortunately, there does not seem to be any
21013 official way to discover the language being compiled, so we
21014 use language_string.
21015 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21016 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21017 a number, so for now use 9. LTO and Go aren't assigned numbers
21018 either, so for now use 0. */
21019 if (! strcmp (language_string, "GNU C")
21020 || ! strcmp (language_string, "GNU GIMPLE")
21021 || ! strcmp (language_string, "GNU Go"))
21023 else if (! strcmp (language_string, "GNU F77")
21024 || ! strcmp (language_string, "GNU Fortran"))
21026 else if (! strcmp (language_string, "GNU Pascal"))
21028 else if (! strcmp (language_string, "GNU Ada"))
21030 else if (! strcmp (language_string, "GNU C++")
21031 || ! strcmp (language_string, "GNU Objective-C++"))
21033 else if (! strcmp (language_string, "GNU Java"))
21035 else if (! strcmp (language_string, "GNU Objective-C"))
21038 gcc_unreachable ();
21039 fprintf (file, "%d,", i);
21041 /* 8 single bit fields: global linkage (not set for C extern linkage,
21042 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21043 from start of procedure stored in tbtab, internal function, function
21044 has controlled storage, function has no toc, function uses fp,
21045 function logs/aborts fp operations. */
21046 /* Assume that fp operations are used if any fp reg must be saved. */
21047 fprintf (file, "%d,",
21048 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
21050 /* 6 bitfields: function is interrupt handler, name present in
21051 proc table, function calls alloca, on condition directives
21052 (controls stack walks, 3 bits), saves condition reg, saves
21054 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21055 set up as a frame pointer, even when there is no alloca call. */
21056 fprintf (file, "%d,",
21057 ((optional_tbtab << 6)
21058 | ((optional_tbtab & frame_pointer_needed) << 5)
21059 | (info->cr_save_p << 1)
21060 | (info->lr_save_p)));
21062 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21064 fprintf (file, "%d,",
21065 (info->push_p << 7) | (64 - info->first_fp_reg_save));
21067 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21068 fprintf (file, "%d,", (32 - first_reg_to_save ()));
21070 if (optional_tbtab)
21072 /* Compute the parameter info from the function decl argument
21075 int next_parm_info_bit = 31;
21077 for (decl = DECL_ARGUMENTS (current_function_decl);
21078 decl; decl = DECL_CHAIN (decl))
21080 rtx parameter = DECL_INCOMING_RTL (decl);
21081 enum machine_mode mode = GET_MODE (parameter);
21083 if (GET_CODE (parameter) == REG)
21085 if (SCALAR_FLOAT_MODE_P (mode))
21106 gcc_unreachable ();
21109 /* If only one bit will fit, don't or in this entry. */
21110 if (next_parm_info_bit > 0)
21111 parm_info |= (bits << (next_parm_info_bit - 1));
21112 next_parm_info_bit -= 2;
21116 fixed_parms += ((GET_MODE_SIZE (mode)
21117 + (UNITS_PER_WORD - 1))
21119 next_parm_info_bit -= 1;
21125 /* Number of fixed point parameters. */
21126 /* This is actually the number of words of fixed point parameters; thus
21127 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21128 fprintf (file, "%d,", fixed_parms);
21130 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21132 /* This is actually the number of fp registers that hold parameters;
21133 and thus the maximum value is 13. */
21134 /* Set parameters on stack bit if parameters are not in their original
21135 registers, regardless of whether they are on the stack? Xlc
21136 seems to set the bit when not optimizing. */
21137 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
21139 if (! optional_tbtab)
21142 /* Optional fields follow. Some are variable length. */
21144 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21145 11 double float. */
21146 /* There is an entry for each parameter in a register, in the order that
21147 they occur in the parameter list. Any intervening arguments on the
21148 stack are ignored. If the list overflows a long (max possible length
21149 34 bits) then completely leave off all elements that don't fit. */
21150 /* Only emit this long if there was at least one parameter. */
21151 if (fixed_parms || float_parms)
21152 fprintf (file, "\t.long %d\n", parm_info);
21154 /* Offset from start of code to tb table. */
21155 fputs ("\t.long ", file);
21156 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21157 RS6000_OUTPUT_BASENAME (file, fname);
21159 rs6000_output_function_entry (file, fname);
21162 /* Interrupt handler mask. */
21163 /* Omit this long, since we never set the interrupt handler bit
21166 /* Number of CTL (controlled storage) anchors. */
21167 /* Omit this long, since the has_ctl bit is never set above. */
21169 /* Displacement into stack of each CTL anchor. */
21170 /* Omit this list of longs, because there are no CTL anchors. */
21172 /* Length of function name. */
21175 fprintf (file, "\t.short %d\n", (int) strlen (fname));
21177 /* Function name. */
21178 assemble_string (fname, strlen (fname));
21180 /* Register for alloca automatic storage; this is always reg 31.
21181 Only emit this if the alloca bit was set above. */
21182 if (frame_pointer_needed)
21183 fputs ("\t.byte 31\n", file);
21185 fputs ("\t.align 2\n", file);
21189 /* A C compound statement that outputs the assembler code for a thunk
21190 function, used to implement C++ virtual function calls with
21191 multiple inheritance. The thunk acts as a wrapper around a virtual
21192 function, adjusting the implicit object parameter before handing
21193 control off to the real function.
21195 First, emit code to add the integer DELTA to the location that
21196 contains the incoming first argument. Assume that this argument
21197 contains a pointer, and is the one used to pass the `this' pointer
21198 in C++. This is the incoming argument *before* the function
21199 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21200 values of all other incoming arguments.
21202 After the addition, emit code to jump to FUNCTION, which is a
21203 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21204 not touch the return address. Hence returning from FUNCTION will
21205 return to whoever called the current `thunk'.
21207 The effect must be as if FUNCTION had been called directly with the
21208 adjusted first argument. This macro is responsible for emitting
21209 all of the code for a thunk function; output_function_prologue()
21210 and output_function_epilogue() are not invoked.
21212 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21213 been extracted from it.) It might possibly be useful on some
21214 targets, but probably not.
21216 If you do not define this macro, the target-independent code in the
21217 C++ frontend will generate a less efficient heavyweight thunk that
21218 calls FUNCTION instead of jumping to it. The generic approach does
21219 not support varargs. */
21222 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
21223 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
21226 rtx this_rtx, insn, funexp;
21228 reload_completed = 1;
21229 epilogue_completed = 1;
21231 /* Mark the end of the (empty) prologue. */
21232 emit_note (NOTE_INSN_PROLOGUE_END);
21234 /* Find the "this" pointer. If the function returns a structure,
21235 the structure return pointer is in r3. */
21236 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
21237 this_rtx = gen_rtx_REG (Pmode, 4);
21239 this_rtx = gen_rtx_REG (Pmode, 3);
21241 /* Apply the constant offset, if required. */
21243 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
21245 /* Apply the offset from the vtable, if required. */
21248 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
21249 rtx tmp = gen_rtx_REG (Pmode, 12);
21251 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
21252 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
21254 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
21255 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
21259 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
21261 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
21263 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
21266 /* Generate a tail call to the target function. */
21267 if (!TREE_USED (function))
21269 assemble_external (function);
21270 TREE_USED (function) = 1;
21272 funexp = XEXP (DECL_RTL (function), 0);
21273 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
21276 if (MACHOPIC_INDIRECT)
21277 funexp = machopic_indirect_call_target (funexp);
21280 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21281 generate sibcall RTL explicitly. */
21282 insn = emit_call_insn (
21283 gen_rtx_PARALLEL (VOIDmode,
21285 gen_rtx_CALL (VOIDmode,
21286 funexp, const0_rtx),
21287 gen_rtx_USE (VOIDmode, const0_rtx),
21288 gen_rtx_USE (VOIDmode,
21289 gen_rtx_REG (SImode,
21291 simple_return_rtx)));
21292 SIBLING_CALL_P (insn) = 1;
21295 /* Run just enough of rest_of_compilation to get the insns emitted.
21296 There's not really enough bulk here to make other passes such as
21297 instruction scheduling worth while. Note that use_thunk calls
21298 assemble_start_function and assemble_end_function. */
21299 insn = get_insns ();
21300 insn_locators_alloc ();
21301 shorten_branches (insn);
21302 final_start_function (insn, file, 1);
21303 final (insn, file, 1);
21304 final_end_function ();
21306 reload_completed = 0;
21307 epilogue_completed = 0;
21310 /* A quick summary of the various types of 'constant-pool tables'
21313 Target Flags Name One table per
21314 AIX (none) AIX TOC object file
21315 AIX -mfull-toc AIX TOC object file
21316 AIX -mminimal-toc AIX minimal TOC translation unit
21317 SVR4/EABI (none) SVR4 SDATA object file
21318 SVR4/EABI -fpic SVR4 pic object file
21319 SVR4/EABI -fPIC SVR4 PIC translation unit
21320 SVR4/EABI -mrelocatable EABI TOC function
21321 SVR4/EABI -maix AIX TOC object file
21322 SVR4/EABI -maix -mminimal-toc
21323 AIX minimal TOC translation unit
21325 Name Reg. Set by entries contains:
21326 made by addrs? fp? sum?
21328 AIX TOC 2 crt0 as Y option option
21329 AIX minimal TOC 30 prolog gcc Y Y option
21330 SVR4 SDATA 13 crt0 gcc N Y N
21331 SVR4 pic 30 prolog ld Y not yet N
21332 SVR4 PIC 30 prolog gcc Y option option
21333 EABI TOC 30 prolog gcc Y option option
21337 /* Hash functions for the hash table. */
21340 rs6000_hash_constant (rtx k)
21342 enum rtx_code code = GET_CODE (k);
21343 enum machine_mode mode = GET_MODE (k);
21344 unsigned result = (code << 3) ^ mode;
21345 const char *format;
21348 format = GET_RTX_FORMAT (code);
21349 flen = strlen (format);
21355 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
21358 if (mode != VOIDmode)
21359 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
21371 for (; fidx < flen; fidx++)
21372 switch (format[fidx])
21377 const char *str = XSTR (k, fidx);
21378 len = strlen (str);
21379 result = result * 613 + len;
21380 for (i = 0; i < len; i++)
21381 result = result * 613 + (unsigned) str[i];
21386 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
21390 result = result * 613 + (unsigned) XINT (k, fidx);
21393 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
21394 result = result * 613 + (unsigned) XWINT (k, fidx);
21398 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
21399 result = result * 613 + (unsigned) (XWINT (k, fidx)
21406 gcc_unreachable ();
21413 toc_hash_function (const void *hash_entry)
21415 const struct toc_hash_struct *thc =
21416 (const struct toc_hash_struct *) hash_entry;
21417 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
21420 /* Compare H1 and H2 for equivalence. */
21423 toc_hash_eq (const void *h1, const void *h2)
21425 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
21426 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
21428 if (((const struct toc_hash_struct *) h1)->key_mode
21429 != ((const struct toc_hash_struct *) h2)->key_mode)
21432 return rtx_equal_p (r1, r2);
21435 /* These are the names given by the C++ front-end to vtables, and
21436 vtable-like objects. Ideally, this logic should not be here;
21437 instead, there should be some programmatic way of inquiring as
21438 to whether or not an object is a vtable. */
21440 #define VTABLE_NAME_P(NAME) \
21441 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21442 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21443 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21444 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21445 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21447 #ifdef NO_DOLLAR_IN_LABEL
21448 /* Return a GGC-allocated character string translating dollar signs in
21449 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21452 rs6000_xcoff_strip_dollar (const char *name)
21458 q = (const char *) strchr (name, '$');
21460 if (q == 0 || q == name)
21463 len = strlen (name);
21464 strip = XALLOCAVEC (char, len + 1);
21465 strcpy (strip, name);
21466 p = strip + (q - name);
21470 p = strchr (p + 1, '$');
21473 return ggc_alloc_string (strip, len);
21478 rs6000_output_symbol_ref (FILE *file, rtx x)
21480 /* Currently C++ toc references to vtables can be emitted before it
21481 is decided whether the vtable is public or private. If this is
21482 the case, then the linker will eventually complain that there is
21483 a reference to an unknown section. Thus, for vtables only,
21484 we emit the TOC reference to reference the symbol and not the
21486 const char *name = XSTR (x, 0);
21488 if (VTABLE_NAME_P (name))
21490 RS6000_OUTPUT_BASENAME (file, name);
21493 assemble_name (file, name);
21496 /* Output a TOC entry. We derive the entry name from what is being
21500 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
21503 const char *name = buf;
21505 HOST_WIDE_INT offset = 0;
21507 gcc_assert (!TARGET_NO_TOC);
21509 /* When the linker won't eliminate them, don't output duplicate
21510 TOC entries (this happens on AIX if there is any kind of TOC,
21511 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
21513 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
21515 struct toc_hash_struct *h;
21518 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
21519 time because GGC is not initialized at that point. */
21520 if (toc_hash_table == NULL)
21521 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
21522 toc_hash_eq, NULL);
21524 h = ggc_alloc_toc_hash_struct ();
21526 h->key_mode = mode;
21527 h->labelno = labelno;
21529 found = htab_find_slot (toc_hash_table, h, INSERT);
21530 if (*found == NULL)
21532 else /* This is indeed a duplicate.
21533 Set this label equal to that label. */
21535 fputs ("\t.set ", file);
21536 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21537 fprintf (file, "%d,", labelno);
21538 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21539 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
21545 /* If we're going to put a double constant in the TOC, make sure it's
21546 aligned properly when strict alignment is on. */
21547 if (GET_CODE (x) == CONST_DOUBLE
21548 && STRICT_ALIGNMENT
21549 && GET_MODE_BITSIZE (mode) >= 64
21550 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
21551 ASM_OUTPUT_ALIGN (file, 3);
21554 (*targetm.asm_out.internal_label) (file, "LC", labelno);
21556 /* Handle FP constants specially. Note that if we have a minimal
21557 TOC, things we put here aren't actually in the TOC, so we can allow
21559 if (GET_CODE (x) == CONST_DOUBLE &&
21560 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
21562 REAL_VALUE_TYPE rv;
21565 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21566 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21567 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
21569 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
21573 if (TARGET_MINIMAL_TOC)
21574 fputs (DOUBLE_INT_ASM_OP, file);
21576 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21577 k[0] & 0xffffffff, k[1] & 0xffffffff,
21578 k[2] & 0xffffffff, k[3] & 0xffffffff);
21579 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
21580 k[0] & 0xffffffff, k[1] & 0xffffffff,
21581 k[2] & 0xffffffff, k[3] & 0xffffffff);
21586 if (TARGET_MINIMAL_TOC)
21587 fputs ("\t.long ", file);
21589 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21590 k[0] & 0xffffffff, k[1] & 0xffffffff,
21591 k[2] & 0xffffffff, k[3] & 0xffffffff);
21592 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
21593 k[0] & 0xffffffff, k[1] & 0xffffffff,
21594 k[2] & 0xffffffff, k[3] & 0xffffffff);
21598 else if (GET_CODE (x) == CONST_DOUBLE &&
21599 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
21601 REAL_VALUE_TYPE rv;
21604 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21606 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21607 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
21609 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
21613 if (TARGET_MINIMAL_TOC)
21614 fputs (DOUBLE_INT_ASM_OP, file);
21616 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21617 k[0] & 0xffffffff, k[1] & 0xffffffff);
21618 fprintf (file, "0x%lx%08lx\n",
21619 k[0] & 0xffffffff, k[1] & 0xffffffff);
21624 if (TARGET_MINIMAL_TOC)
21625 fputs ("\t.long ", file);
21627 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21628 k[0] & 0xffffffff, k[1] & 0xffffffff);
21629 fprintf (file, "0x%lx,0x%lx\n",
21630 k[0] & 0xffffffff, k[1] & 0xffffffff);
21634 else if (GET_CODE (x) == CONST_DOUBLE &&
21635 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
21637 REAL_VALUE_TYPE rv;
21640 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21641 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21642 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
21644 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
21648 if (TARGET_MINIMAL_TOC)
21649 fputs (DOUBLE_INT_ASM_OP, file);
21651 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21652 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
21657 if (TARGET_MINIMAL_TOC)
21658 fputs ("\t.long ", file);
21660 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21661 fprintf (file, "0x%lx\n", l & 0xffffffff);
21665 else if (GET_MODE (x) == VOIDmode
21666 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
21668 unsigned HOST_WIDE_INT low;
21669 HOST_WIDE_INT high;
21671 if (GET_CODE (x) == CONST_DOUBLE)
21673 low = CONST_DOUBLE_LOW (x);
21674 high = CONST_DOUBLE_HIGH (x);
21677 #if HOST_BITS_PER_WIDE_INT == 32
21680 high = (low & 0x80000000) ? ~0 : 0;
21684 low = INTVAL (x) & 0xffffffff;
21685 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
21689 /* TOC entries are always Pmode-sized, but since this
21690 is a bigendian machine then if we're putting smaller
21691 integer constants in the TOC we have to pad them.
21692 (This is still a win over putting the constants in
21693 a separate constant pool, because then we'd have
21694 to have both a TOC entry _and_ the actual constant.)
21696 For a 32-bit target, CONST_INT values are loaded and shifted
21697 entirely within `low' and can be stored in one TOC entry. */
21699 /* It would be easy to make this work, but it doesn't now. */
21700 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
21702 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
21704 #if HOST_BITS_PER_WIDE_INT == 32
21705 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
21706 POINTER_SIZE, &low, &high, 0);
21709 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
21710 high = (HOST_WIDE_INT) low >> 32;
21717 if (TARGET_MINIMAL_TOC)
21718 fputs (DOUBLE_INT_ASM_OP, file);
21720 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21721 (long) high & 0xffffffff, (long) low & 0xffffffff);
21722 fprintf (file, "0x%lx%08lx\n",
21723 (long) high & 0xffffffff, (long) low & 0xffffffff);
21728 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
21730 if (TARGET_MINIMAL_TOC)
21731 fputs ("\t.long ", file);
21733 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21734 (long) high & 0xffffffff, (long) low & 0xffffffff);
21735 fprintf (file, "0x%lx,0x%lx\n",
21736 (long) high & 0xffffffff, (long) low & 0xffffffff);
21740 if (TARGET_MINIMAL_TOC)
21741 fputs ("\t.long ", file);
21743 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
21744 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
21750 if (GET_CODE (x) == CONST)
21752 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
21753 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
21755 base = XEXP (XEXP (x, 0), 0);
21756 offset = INTVAL (XEXP (XEXP (x, 0), 1));
21759 switch (GET_CODE (base))
21762 name = XSTR (base, 0);
21766 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
21767 CODE_LABEL_NUMBER (XEXP (base, 0)));
21771 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
21775 gcc_unreachable ();
21778 if (TARGET_MINIMAL_TOC)
21779 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
21782 fputs ("\t.tc ", file);
21783 RS6000_OUTPUT_BASENAME (file, name);
21786 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
21788 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
21790 fputs ("[TC],", file);
21793 /* Currently C++ toc references to vtables can be emitted before it
21794 is decided whether the vtable is public or private. If this is
21795 the case, then the linker will eventually complain that there is
21796 a TOC reference to an unknown section. Thus, for vtables only,
21797 we emit the TOC reference to reference the symbol and not the
21799 if (VTABLE_NAME_P (name))
21801 RS6000_OUTPUT_BASENAME (file, name);
21803 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
21804 else if (offset > 0)
21805 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
21808 output_addr_const (file, x);
21812 /* Output an assembler pseudo-op to write an ASCII string of N characters
21813 starting at P to FILE.
21815 On the RS/6000, we have to do this using the .byte operation and
21816 write out special characters outside the quoted string.
21817 Also, the assembler is broken; very long strings are truncated,
21818 so we must artificially break them up early. */
21821 output_ascii (FILE *file, const char *p, int n)
21824 int i, count_string;
21825 const char *for_string = "\t.byte \"";
21826 const char *for_decimal = "\t.byte ";
21827 const char *to_close = NULL;
21830 for (i = 0; i < n; i++)
21833 if (c >= ' ' && c < 0177)
21836 fputs (for_string, file);
21839 /* Write two quotes to get one. */
21847 for_decimal = "\"\n\t.byte ";
21851 if (count_string >= 512)
21853 fputs (to_close, file);
21855 for_string = "\t.byte \"";
21856 for_decimal = "\t.byte ";
21864 fputs (for_decimal, file);
21865 fprintf (file, "%d", c);
21867 for_string = "\n\t.byte \"";
21868 for_decimal = ", ";
21874 /* Now close the string if we have written one. Then end the line. */
21876 fputs (to_close, file);
21879 /* Generate a unique section name for FILENAME for a section type
21880 represented by SECTION_DESC. Output goes into BUF.
21882 SECTION_DESC can be any string, as long as it is different for each
21883 possible section type.
21885 We name the section in the same manner as xlc. The name begins with an
21886 underscore followed by the filename (after stripping any leading directory
21887 names) with the last period replaced by the string SECTION_DESC. If
21888 FILENAME does not contain a period, SECTION_DESC is appended to the end of
21892 rs6000_gen_section_name (char **buf, const char *filename,
21893 const char *section_desc)
21895 const char *q, *after_last_slash, *last_period = 0;
21899 after_last_slash = filename;
21900 for (q = filename; *q; q++)
21903 after_last_slash = q + 1;
21904 else if (*q == '.')
21908 len = strlen (after_last_slash) + strlen (section_desc) + 2;
21909 *buf = (char *) xmalloc (len);
21914 for (q = after_last_slash; *q; q++)
21916 if (q == last_period)
21918 strcpy (p, section_desc);
21919 p += strlen (section_desc);
21923 else if (ISALNUM (*q))
21927 if (last_period == 0)
21928 strcpy (p, section_desc);
21933 /* Emit profile function. */
21936 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
21938 /* Non-standard profiling for kernels, which just saves LR then calls
21939 _mcount without worrying about arg saves. The idea is to change
21940 the function prologue as little as possible as it isn't easy to
21941 account for arg save/restore code added just for _mcount. */
21942 if (TARGET_PROFILE_KERNEL)
21945 if (DEFAULT_ABI == ABI_AIX)
21947 #ifndef NO_PROFILE_COUNTERS
21948 # define NO_PROFILE_COUNTERS 0
21950 if (NO_PROFILE_COUNTERS)
21951 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
21952 LCT_NORMAL, VOIDmode, 0);
21956 const char *label_name;
21959 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
21960 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
21961 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
21963 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
21964 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
21967 else if (DEFAULT_ABI == ABI_DARWIN)
21969 const char *mcount_name = RS6000_MCOUNT;
21970 int caller_addr_regno = LR_REGNO;
21972 /* Be conservative and always set this, at least for now. */
21973 crtl->uses_pic_offset_table = 1;
21976 /* For PIC code, set up a stub and collect the caller's address
21977 from r0, which is where the prologue puts it. */
21978 if (MACHOPIC_INDIRECT
21979 && crtl->uses_pic_offset_table)
21980 caller_addr_regno = 0;
21982 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
21983 LCT_NORMAL, VOIDmode, 1,
21984 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
21988 /* Write function profiler code. */
21991 output_function_profiler (FILE *file, int labelno)
21995 switch (DEFAULT_ABI)
21998 gcc_unreachable ();
22003 warning (0, "no profiling of 64-bit code for this ABI");
22006 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22007 fprintf (file, "\tmflr %s\n", reg_names[0]);
22008 if (NO_PROFILE_COUNTERS)
22010 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22011 reg_names[0], reg_names[1]);
22013 else if (TARGET_SECURE_PLT && flag_pic)
22015 if (TARGET_LINK_STACK)
22018 get_ppc476_thunk_name (name);
22019 asm_fprintf (file, "\tbl %s\n", name);
22022 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
22023 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22024 reg_names[0], reg_names[1]);
22025 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22026 asm_fprintf (file, "\t{cau|addis} %s,%s,",
22027 reg_names[12], reg_names[12]);
22028 assemble_name (file, buf);
22029 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
22030 assemble_name (file, buf);
22031 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
22033 else if (flag_pic == 1)
22035 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
22036 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22037 reg_names[0], reg_names[1]);
22038 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22039 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
22040 assemble_name (file, buf);
22041 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
22043 else if (flag_pic > 1)
22045 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22046 reg_names[0], reg_names[1]);
22047 /* Now, we need to get the address of the label. */
22048 if (TARGET_LINK_STACK)
22051 get_ppc476_thunk_name (name);
22052 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
22053 assemble_name (file, buf);
22054 fputs ("-.\n1:", file);
22055 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22056 asm_fprintf (file, "\taddi %s,%s,4\n",
22057 reg_names[11], reg_names[11]);
22061 fputs ("\tbcl 20,31,1f\n\t.long ", file);
22062 assemble_name (file, buf);
22063 fputs ("-.\n1:", file);
22064 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22066 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
22067 reg_names[0], reg_names[11]);
22068 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
22069 reg_names[0], reg_names[0], reg_names[11]);
22073 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
22074 assemble_name (file, buf);
22075 fputs ("@ha\n", file);
22076 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22077 reg_names[0], reg_names[1]);
22078 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
22079 assemble_name (file, buf);
22080 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
22083 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22084 fprintf (file, "\tbl %s%s\n",
22085 RS6000_MCOUNT, flag_pic ? "@plt" : "");
22090 if (!TARGET_PROFILE_KERNEL)
22092 /* Don't do anything, done in output_profile_hook (). */
22096 gcc_assert (!TARGET_32BIT);
22098 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
22099 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
22101 if (cfun->static_chain_decl != NULL)
22103 asm_fprintf (file, "\tstd %s,24(%s)\n",
22104 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22105 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22106 asm_fprintf (file, "\tld %s,24(%s)\n",
22107 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22110 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22118 /* The following variable value is the last issued insn. */
22120 static rtx last_scheduled_insn;
22122 /* The following variable helps to balance issuing of load and
22123 store instructions */
22125 static int load_store_pendulum;
22127 /* Power4 load update and store update instructions are cracked into a
22128 load or store and an integer insn which are executed in the same cycle.
22129 Branches have their own dispatch slot which does not count against the
22130 GCC issue rate, but it changes the program flow so there are no other
22131 instructions to issue in this cycle. */
22134 rs6000_variable_issue_1 (rtx insn, int more)
22136 last_scheduled_insn = insn;
22137 if (GET_CODE (PATTERN (insn)) == USE
22138 || GET_CODE (PATTERN (insn)) == CLOBBER)
22140 cached_can_issue_more = more;
22141 return cached_can_issue_more;
22144 if (insn_terminates_group_p (insn, current_group))
22146 cached_can_issue_more = 0;
22147 return cached_can_issue_more;
22150 /* If no reservation, but reach here */
22151 if (recog_memoized (insn) < 0)
22154 if (rs6000_sched_groups)
22156 if (is_microcoded_insn (insn))
22157 cached_can_issue_more = 0;
22158 else if (is_cracked_insn (insn))
22159 cached_can_issue_more = more > 2 ? more - 2 : 0;
22161 cached_can_issue_more = more - 1;
22163 return cached_can_issue_more;
22166 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
22169 cached_can_issue_more = more - 1;
22170 return cached_can_issue_more;
22174 rs6000_variable_issue (FILE *stream, int verbose, rtx insn, int more)
22176 int r = rs6000_variable_issue_1 (insn, more);
22178 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
22182 /* Adjust the cost of a scheduling dependency. Return the new cost of
22183 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22186 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22188 enum attr_type attr_type;
22190 if (! recog_memoized (insn))
22193 switch (REG_NOTE_KIND (link))
22197 /* Data dependency; DEP_INSN writes a register that INSN reads
22198 some cycles later. */
22200 /* Separate a load from a narrower, dependent store. */
22201 if (rs6000_sched_groups
22202 && GET_CODE (PATTERN (insn)) == SET
22203 && GET_CODE (PATTERN (dep_insn)) == SET
22204 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
22205 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
22206 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
22207 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
22210 attr_type = get_attr_type (insn);
22215 /* Tell the first scheduling pass about the latency between
22216 a mtctr and bctr (and mtlr and br/blr). The first
22217 scheduling pass will not know about this latency since
22218 the mtctr instruction, which has the latency associated
22219 to it, will be generated by reload. */
22220 return TARGET_POWER ? 5 : 4;
22222 /* Leave some extra cycles between a compare and its
22223 dependent branch, to inhibit expensive mispredicts. */
22224 if ((rs6000_cpu_attr == CPU_PPC603
22225 || rs6000_cpu_attr == CPU_PPC604
22226 || rs6000_cpu_attr == CPU_PPC604E
22227 || rs6000_cpu_attr == CPU_PPC620
22228 || rs6000_cpu_attr == CPU_PPC630
22229 || rs6000_cpu_attr == CPU_PPC750
22230 || rs6000_cpu_attr == CPU_PPC7400
22231 || rs6000_cpu_attr == CPU_PPC7450
22232 || rs6000_cpu_attr == CPU_POWER4
22233 || rs6000_cpu_attr == CPU_POWER5
22234 || rs6000_cpu_attr == CPU_POWER7
22235 || rs6000_cpu_attr == CPU_CELL)
22236 && recog_memoized (dep_insn)
22237 && (INSN_CODE (dep_insn) >= 0))
22239 switch (get_attr_type (dep_insn))
22243 case TYPE_DELAYED_COMPARE:
22244 case TYPE_IMUL_COMPARE:
22245 case TYPE_LMUL_COMPARE:
22246 case TYPE_FPCOMPARE:
22247 case TYPE_CR_LOGICAL:
22248 case TYPE_DELAYED_CR:
22257 case TYPE_STORE_UX:
22259 case TYPE_FPSTORE_U:
22260 case TYPE_FPSTORE_UX:
22261 if ((rs6000_cpu == PROCESSOR_POWER6)
22262 && recog_memoized (dep_insn)
22263 && (INSN_CODE (dep_insn) >= 0))
22266 if (GET_CODE (PATTERN (insn)) != SET)
22267 /* If this happens, we have to extend this to schedule
22268 optimally. Return default for now. */
22271 /* Adjust the cost for the case where the value written
22272 by a fixed point operation is used as the address
22273 gen value on a store. */
22274 switch (get_attr_type (dep_insn))
22281 if (! store_data_bypass_p (dep_insn, insn))
22285 case TYPE_LOAD_EXT:
22286 case TYPE_LOAD_EXT_U:
22287 case TYPE_LOAD_EXT_UX:
22288 case TYPE_VAR_SHIFT_ROTATE:
22289 case TYPE_VAR_DELAYED_COMPARE:
22291 if (! store_data_bypass_p (dep_insn, insn))
22297 case TYPE_FAST_COMPARE:
22300 case TYPE_INSERT_WORD:
22301 case TYPE_INSERT_DWORD:
22302 case TYPE_FPLOAD_U:
22303 case TYPE_FPLOAD_UX:
22305 case TYPE_STORE_UX:
22306 case TYPE_FPSTORE_U:
22307 case TYPE_FPSTORE_UX:
22309 if (! store_data_bypass_p (dep_insn, insn))
22317 case TYPE_IMUL_COMPARE:
22318 case TYPE_LMUL_COMPARE:
22320 if (! store_data_bypass_p (dep_insn, insn))
22326 if (! store_data_bypass_p (dep_insn, insn))
22332 if (! store_data_bypass_p (dep_insn, insn))
22345 case TYPE_LOAD_EXT:
22346 case TYPE_LOAD_EXT_U:
22347 case TYPE_LOAD_EXT_UX:
22348 if ((rs6000_cpu == PROCESSOR_POWER6)
22349 && recog_memoized (dep_insn)
22350 && (INSN_CODE (dep_insn) >= 0))
22353 /* Adjust the cost for the case where the value written
22354 by a fixed point instruction is used within the address
22355 gen portion of a subsequent load(u)(x) */
22356 switch (get_attr_type (dep_insn))
22363 if (set_to_load_agen (dep_insn, insn))
22367 case TYPE_LOAD_EXT:
22368 case TYPE_LOAD_EXT_U:
22369 case TYPE_LOAD_EXT_UX:
22370 case TYPE_VAR_SHIFT_ROTATE:
22371 case TYPE_VAR_DELAYED_COMPARE:
22373 if (set_to_load_agen (dep_insn, insn))
22379 case TYPE_FAST_COMPARE:
22382 case TYPE_INSERT_WORD:
22383 case TYPE_INSERT_DWORD:
22384 case TYPE_FPLOAD_U:
22385 case TYPE_FPLOAD_UX:
22387 case TYPE_STORE_UX:
22388 case TYPE_FPSTORE_U:
22389 case TYPE_FPSTORE_UX:
22391 if (set_to_load_agen (dep_insn, insn))
22399 case TYPE_IMUL_COMPARE:
22400 case TYPE_LMUL_COMPARE:
22402 if (set_to_load_agen (dep_insn, insn))
22408 if (set_to_load_agen (dep_insn, insn))
22414 if (set_to_load_agen (dep_insn, insn))
22425 if ((rs6000_cpu == PROCESSOR_POWER6)
22426 && recog_memoized (dep_insn)
22427 && (INSN_CODE (dep_insn) >= 0)
22428 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
22435 /* Fall out to return default cost. */
22439 case REG_DEP_OUTPUT:
22440 /* Output dependency; DEP_INSN writes a register that INSN writes some
22442 if ((rs6000_cpu == PROCESSOR_POWER6)
22443 && recog_memoized (dep_insn)
22444 && (INSN_CODE (dep_insn) >= 0))
22446 attr_type = get_attr_type (insn);
22451 if (get_attr_type (dep_insn) == TYPE_FP)
22455 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
22463 /* Anti dependency; DEP_INSN reads a register that INSN writes some
22468 gcc_unreachable ();
22474 /* Debug version of rs6000_adjust_cost. */
22477 rs6000_debug_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22479 int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
22485 switch (REG_NOTE_KIND (link))
22487 default: dep = "unknown depencency"; break;
22488 case REG_DEP_TRUE: dep = "data dependency"; break;
22489 case REG_DEP_OUTPUT: dep = "output dependency"; break;
22490 case REG_DEP_ANTI: dep = "anti depencency"; break;
22494 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
22495 "%s, insn:\n", ret, cost, dep);
22503 /* The function returns a true if INSN is microcoded.
22504 Return false otherwise. */
22507 is_microcoded_insn (rtx insn)
22509 if (!insn || !NONDEBUG_INSN_P (insn)
22510 || GET_CODE (PATTERN (insn)) == USE
22511 || GET_CODE (PATTERN (insn)) == CLOBBER)
22514 if (rs6000_cpu_attr == CPU_CELL)
22515 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
22517 if (rs6000_sched_groups)
22519 enum attr_type type = get_attr_type (insn);
22520 if (type == TYPE_LOAD_EXT_U
22521 || type == TYPE_LOAD_EXT_UX
22522 || type == TYPE_LOAD_UX
22523 || type == TYPE_STORE_UX
22524 || type == TYPE_MFCR)
22531 /* The function returns true if INSN is cracked into 2 instructions
22532 by the processor (and therefore occupies 2 issue slots). */
22535 is_cracked_insn (rtx insn)
22537 if (!insn || !NONDEBUG_INSN_P (insn)
22538 || GET_CODE (PATTERN (insn)) == USE
22539 || GET_CODE (PATTERN (insn)) == CLOBBER)
22542 if (rs6000_sched_groups)
22544 enum attr_type type = get_attr_type (insn);
22545 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
22546 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
22547 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
22548 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
22549 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
22550 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
22551 || type == TYPE_IDIV || type == TYPE_LDIV
22552 || type == TYPE_INSERT_WORD)
22559 /* The function returns true if INSN can be issued only from
22560 the branch slot. */
22563 is_branch_slot_insn (rtx insn)
22565 if (!insn || !NONDEBUG_INSN_P (insn)
22566 || GET_CODE (PATTERN (insn)) == USE
22567 || GET_CODE (PATTERN (insn)) == CLOBBER)
22570 if (rs6000_sched_groups)
22572 enum attr_type type = get_attr_type (insn);
22573 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
22581 /* The function returns true if out_inst sets a value that is
22582 used in the address generation computation of in_insn */
22584 set_to_load_agen (rtx out_insn, rtx in_insn)
22586 rtx out_set, in_set;
22588 /* For performance reasons, only handle the simple case where
22589 both loads are a single_set. */
22590 out_set = single_set (out_insn);
22593 in_set = single_set (in_insn);
22595 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
22601 /* The function returns true if the target storage location of
22602 out_insn is adjacent to the target storage location of in_insn */
22603 /* Return 1 if memory locations are adjacent. */
22606 adjacent_mem_locations (rtx insn1, rtx insn2)
22609 rtx a = get_store_dest (PATTERN (insn1));
22610 rtx b = get_store_dest (PATTERN (insn2));
22612 if ((GET_CODE (XEXP (a, 0)) == REG
22613 || (GET_CODE (XEXP (a, 0)) == PLUS
22614 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
22615 && (GET_CODE (XEXP (b, 0)) == REG
22616 || (GET_CODE (XEXP (b, 0)) == PLUS
22617 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
22619 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
22622 if (GET_CODE (XEXP (a, 0)) == PLUS)
22624 reg0 = XEXP (XEXP (a, 0), 0);
22625 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
22628 reg0 = XEXP (a, 0);
22630 if (GET_CODE (XEXP (b, 0)) == PLUS)
22632 reg1 = XEXP (XEXP (b, 0), 0);
22633 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
22636 reg1 = XEXP (b, 0);
22638 val_diff = val1 - val0;
22640 return ((REGNO (reg0) == REGNO (reg1))
22641 && ((MEM_SIZE_KNOWN_P (a) && val_diff == MEM_SIZE (a))
22642 || (MEM_SIZE_KNOWN_P (b) && val_diff == -MEM_SIZE (b))));
22648 /* A C statement (sans semicolon) to update the integer scheduling
22649 priority INSN_PRIORITY (INSN). Increase the priority to execute the
22650 INSN earlier, reduce the priority to execute INSN later. Do not
22651 define this macro if you do not need to adjust the scheduling
22652 priorities of insns. */
22655 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
22657 /* On machines (like the 750) which have asymmetric integer units,
22658 where one integer unit can do multiply and divides and the other
22659 can't, reduce the priority of multiply/divide so it is scheduled
22660 before other integer operations. */
22663 if (! INSN_P (insn))
22666 if (GET_CODE (PATTERN (insn)) == USE)
22669 switch (rs6000_cpu_attr) {
22671 switch (get_attr_type (insn))
22678 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
22679 priority, priority);
22680 if (priority >= 0 && priority < 0x01000000)
22687 if (insn_must_be_first_in_group (insn)
22688 && reload_completed
22689 && current_sched_info->sched_max_insns_priority
22690 && rs6000_sched_restricted_insns_priority)
22693 /* Prioritize insns that can be dispatched only in the first
22695 if (rs6000_sched_restricted_insns_priority == 1)
22696 /* Attach highest priority to insn. This means that in
22697 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
22698 precede 'priority' (critical path) considerations. */
22699 return current_sched_info->sched_max_insns_priority;
22700 else if (rs6000_sched_restricted_insns_priority == 2)
22701 /* Increase priority of insn by a minimal amount. This means that in
22702 haifa-sched.c:ready_sort(), only 'priority' (critical path)
22703 considerations precede dispatch-slot restriction considerations. */
22704 return (priority + 1);
22707 if (rs6000_cpu == PROCESSOR_POWER6
22708 && ((load_store_pendulum == -2 && is_load_insn (insn))
22709 || (load_store_pendulum == 2 && is_store_insn (insn))))
22710 /* Attach highest priority to insn if the scheduler has just issued two
22711 stores and this instruction is a load, or two loads and this instruction
22712 is a store. Power6 wants loads and stores scheduled alternately
22714 return current_sched_info->sched_max_insns_priority;
22719 /* Return true if the instruction is nonpipelined on the Cell. */
22721 is_nonpipeline_insn (rtx insn)
22723 enum attr_type type;
22724 if (!insn || !NONDEBUG_INSN_P (insn)
22725 || GET_CODE (PATTERN (insn)) == USE
22726 || GET_CODE (PATTERN (insn)) == CLOBBER)
22729 type = get_attr_type (insn);
22730 if (type == TYPE_IMUL
22731 || type == TYPE_IMUL2
22732 || type == TYPE_IMUL3
22733 || type == TYPE_LMUL
22734 || type == TYPE_IDIV
22735 || type == TYPE_LDIV
22736 || type == TYPE_SDIV
22737 || type == TYPE_DDIV
22738 || type == TYPE_SSQRT
22739 || type == TYPE_DSQRT
22740 || type == TYPE_MFCR
22741 || type == TYPE_MFCRF
22742 || type == TYPE_MFJMPR)
22750 /* Return how many instructions the machine can issue per cycle. */
22753 rs6000_issue_rate (void)
22755 /* Unless scheduling for register pressure, use issue rate of 1 for
22756 first scheduling pass to decrease degradation. */
22757 if (!reload_completed && !flag_sched_pressure)
22760 switch (rs6000_cpu_attr) {
22761 case CPU_RIOS1: /* ? */
22763 case CPU_PPC601: /* ? */
22772 case CPU_PPCE300C2:
22773 case CPU_PPCE300C3:
22774 case CPU_PPCE500MC:
22775 case CPU_PPCE500MC64:
22795 /* Return how many instructions to look ahead for better insn
22799 rs6000_use_sched_lookahead (void)
22801 if (rs6000_cpu_attr == CPU_PPC8540)
22803 if (rs6000_cpu_attr == CPU_CELL)
22804 return (reload_completed ? 8 : 0);
22808 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
22810 rs6000_use_sched_lookahead_guard (rtx insn)
22812 if (rs6000_cpu_attr != CPU_CELL)
22815 if (insn == NULL_RTX || !INSN_P (insn))
22818 if (!reload_completed
22819 || is_nonpipeline_insn (insn)
22820 || is_microcoded_insn (insn))
22826 /* Determine is PAT refers to memory. */
22829 is_mem_ref (rtx pat)
22835 /* stack_tie does not produce any real memory traffic. */
22836 if (GET_CODE (pat) == UNSPEC
22837 && XINT (pat, 1) == UNSPEC_TIE)
22840 if (GET_CODE (pat) == MEM)
22843 /* Recursively process the pattern. */
22844 fmt = GET_RTX_FORMAT (GET_CODE (pat));
22846 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
22849 ret |= is_mem_ref (XEXP (pat, i));
22850 else if (fmt[i] == 'E')
22851 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
22852 ret |= is_mem_ref (XVECEXP (pat, i, j));
22858 /* Determine if PAT is a PATTERN of a load insn. */
22861 is_load_insn1 (rtx pat)
22863 if (!pat || pat == NULL_RTX)
22866 if (GET_CODE (pat) == SET)
22867 return is_mem_ref (SET_SRC (pat));
22869 if (GET_CODE (pat) == PARALLEL)
22873 for (i = 0; i < XVECLEN (pat, 0); i++)
22874 if (is_load_insn1 (XVECEXP (pat, 0, i)))
22881 /* Determine if INSN loads from memory. */
22884 is_load_insn (rtx insn)
22886 if (!insn || !INSN_P (insn))
22889 if (GET_CODE (insn) == CALL_INSN)
22892 return is_load_insn1 (PATTERN (insn));
22895 /* Determine if PAT is a PATTERN of a store insn. */
22898 is_store_insn1 (rtx pat)
22900 if (!pat || pat == NULL_RTX)
22903 if (GET_CODE (pat) == SET)
22904 return is_mem_ref (SET_DEST (pat));
22906 if (GET_CODE (pat) == PARALLEL)
22910 for (i = 0; i < XVECLEN (pat, 0); i++)
22911 if (is_store_insn1 (XVECEXP (pat, 0, i)))
22918 /* Determine if INSN stores to memory. */
22921 is_store_insn (rtx insn)
22923 if (!insn || !INSN_P (insn))
22926 return is_store_insn1 (PATTERN (insn));
22929 /* Return the dest of a store insn. */
22932 get_store_dest (rtx pat)
22934 gcc_assert (is_store_insn1 (pat));
22936 if (GET_CODE (pat) == SET)
22937 return SET_DEST (pat);
22938 else if (GET_CODE (pat) == PARALLEL)
22942 for (i = 0; i < XVECLEN (pat, 0); i++)
22944 rtx inner_pat = XVECEXP (pat, 0, i);
22945 if (GET_CODE (inner_pat) == SET
22946 && is_mem_ref (SET_DEST (inner_pat)))
22950 /* We shouldn't get here, because we should have either a simple
22951 store insn or a store with update which are covered above. */
22955 /* Returns whether the dependence between INSN and NEXT is considered
22956 costly by the given target. */
22959 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
22964 /* If the flag is not enabled - no dependence is considered costly;
22965 allow all dependent insns in the same group.
22966 This is the most aggressive option. */
22967 if (rs6000_sched_costly_dep == no_dep_costly)
22970 /* If the flag is set to 1 - a dependence is always considered costly;
22971 do not allow dependent instructions in the same group.
22972 This is the most conservative option. */
22973 if (rs6000_sched_costly_dep == all_deps_costly)
22976 insn = DEP_PRO (dep);
22977 next = DEP_CON (dep);
22979 if (rs6000_sched_costly_dep == store_to_load_dep_costly
22980 && is_load_insn (next)
22981 && is_store_insn (insn))
22982 /* Prevent load after store in the same group. */
22985 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
22986 && is_load_insn (next)
22987 && is_store_insn (insn)
22988 && DEP_TYPE (dep) == REG_DEP_TRUE)
22989 /* Prevent load after store in the same group if it is a true
22993 /* The flag is set to X; dependences with latency >= X are considered costly,
22994 and will not be scheduled in the same group. */
22995 if (rs6000_sched_costly_dep <= max_dep_latency
22996 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
23002 /* Return the next insn after INSN that is found before TAIL is reached,
23003 skipping any "non-active" insns - insns that will not actually occupy
23004 an issue slot. Return NULL_RTX if such an insn is not found. */
23007 get_next_active_insn (rtx insn, rtx tail)
23009 if (insn == NULL_RTX || insn == tail)
23014 insn = NEXT_INSN (insn);
23015 if (insn == NULL_RTX || insn == tail)
23020 || (NONJUMP_INSN_P (insn)
23021 && GET_CODE (PATTERN (insn)) != USE
23022 && GET_CODE (PATTERN (insn)) != CLOBBER
23023 && INSN_CODE (insn) != CODE_FOR_stack_tie))
23029 /* We are about to begin issuing insns for this clock cycle. */
23032 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
23033 rtx *ready ATTRIBUTE_UNUSED,
23034 int *pn_ready ATTRIBUTE_UNUSED,
23035 int clock_var ATTRIBUTE_UNUSED)
23037 int n_ready = *pn_ready;
23040 fprintf (dump, "// rs6000_sched_reorder :\n");
23042 /* Reorder the ready list, if the second to last ready insn
23043 is a nonepipeline insn. */
23044 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
23046 if (is_nonpipeline_insn (ready[n_ready - 1])
23047 && (recog_memoized (ready[n_ready - 2]) > 0))
23048 /* Simply swap first two insns. */
23050 rtx tmp = ready[n_ready - 1];
23051 ready[n_ready - 1] = ready[n_ready - 2];
23052 ready[n_ready - 2] = tmp;
23056 if (rs6000_cpu == PROCESSOR_POWER6)
23057 load_store_pendulum = 0;
23059 return rs6000_issue_rate ();
23062 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23065 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
23066 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
23069 fprintf (dump, "// rs6000_sched_reorder2 :\n");
23071 /* For Power6, we need to handle some special cases to try and keep the
23072 store queue from overflowing and triggering expensive flushes.
23074 This code monitors how load and store instructions are being issued
23075 and skews the ready list one way or the other to increase the likelihood
23076 that a desired instruction is issued at the proper time.
23078 A couple of things are done. First, we maintain a "load_store_pendulum"
23079 to track the current state of load/store issue.
23081 - If the pendulum is at zero, then no loads or stores have been
23082 issued in the current cycle so we do nothing.
23084 - If the pendulum is 1, then a single load has been issued in this
23085 cycle and we attempt to locate another load in the ready list to
23088 - If the pendulum is -2, then two stores have already been
23089 issued in this cycle, so we increase the priority of the first load
23090 in the ready list to increase it's likelihood of being chosen first
23093 - If the pendulum is -1, then a single store has been issued in this
23094 cycle and we attempt to locate another store in the ready list to
23095 issue with it, preferring a store to an adjacent memory location to
23096 facilitate store pairing in the store queue.
23098 - If the pendulum is 2, then two loads have already been
23099 issued in this cycle, so we increase the priority of the first store
23100 in the ready list to increase it's likelihood of being chosen first
23103 - If the pendulum < -2 or > 2, then do nothing.
23105 Note: This code covers the most common scenarios. There exist non
23106 load/store instructions which make use of the LSU and which
23107 would need to be accounted for to strictly model the behavior
23108 of the machine. Those instructions are currently unaccounted
23109 for to help minimize compile time overhead of this code.
23111 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
23117 if (is_store_insn (last_scheduled_insn))
23118 /* Issuing a store, swing the load_store_pendulum to the left */
23119 load_store_pendulum--;
23120 else if (is_load_insn (last_scheduled_insn))
23121 /* Issuing a load, swing the load_store_pendulum to the right */
23122 load_store_pendulum++;
23124 return cached_can_issue_more;
23126 /* If the pendulum is balanced, or there is only one instruction on
23127 the ready list, then all is well, so return. */
23128 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
23129 return cached_can_issue_more;
23131 if (load_store_pendulum == 1)
23133 /* A load has been issued in this cycle. Scan the ready list
23134 for another load to issue with it */
23139 if (is_load_insn (ready[pos]))
23141 /* Found a load. Move it to the head of the ready list,
23142 and adjust it's priority so that it is more likely to
23145 for (i=pos; i<*pn_ready-1; i++)
23146 ready[i] = ready[i + 1];
23147 ready[*pn_ready-1] = tmp;
23149 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23150 INSN_PRIORITY (tmp)++;
23156 else if (load_store_pendulum == -2)
23158 /* Two stores have been issued in this cycle. Increase the
23159 priority of the first load in the ready list to favor it for
23160 issuing in the next cycle. */
23165 if (is_load_insn (ready[pos])
23167 && INSN_PRIORITY_KNOWN (ready[pos]))
23169 INSN_PRIORITY (ready[pos])++;
23171 /* Adjust the pendulum to account for the fact that a load
23172 was found and increased in priority. This is to prevent
23173 increasing the priority of multiple loads */
23174 load_store_pendulum--;
23181 else if (load_store_pendulum == -1)
23183 /* A store has been issued in this cycle. Scan the ready list for
23184 another store to issue with it, preferring a store to an adjacent
23186 int first_store_pos = -1;
23192 if (is_store_insn (ready[pos]))
23194 /* Maintain the index of the first store found on the
23196 if (first_store_pos == -1)
23197 first_store_pos = pos;
23199 if (is_store_insn (last_scheduled_insn)
23200 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
23202 /* Found an adjacent store. Move it to the head of the
23203 ready list, and adjust it's priority so that it is
23204 more likely to stay there */
23206 for (i=pos; i<*pn_ready-1; i++)
23207 ready[i] = ready[i + 1];
23208 ready[*pn_ready-1] = tmp;
23210 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23211 INSN_PRIORITY (tmp)++;
23213 first_store_pos = -1;
23221 if (first_store_pos >= 0)
23223 /* An adjacent store wasn't found, but a non-adjacent store was,
23224 so move the non-adjacent store to the front of the ready
23225 list, and adjust its priority so that it is more likely to
23227 tmp = ready[first_store_pos];
23228 for (i=first_store_pos; i<*pn_ready-1; i++)
23229 ready[i] = ready[i + 1];
23230 ready[*pn_ready-1] = tmp;
23231 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23232 INSN_PRIORITY (tmp)++;
23235 else if (load_store_pendulum == 2)
23237 /* Two loads have been issued in this cycle. Increase the priority
23238 of the first store in the ready list to favor it for issuing in
23244 if (is_store_insn (ready[pos])
23246 && INSN_PRIORITY_KNOWN (ready[pos]))
23248 INSN_PRIORITY (ready[pos])++;
23250 /* Adjust the pendulum to account for the fact that a store
23251 was found and increased in priority. This is to prevent
23252 increasing the priority of multiple stores */
23253 load_store_pendulum++;
23262 return cached_can_issue_more;
23265 /* Return whether the presence of INSN causes a dispatch group termination
23266 of group WHICH_GROUP.
23268 If WHICH_GROUP == current_group, this function will return true if INSN
23269 causes the termination of the current group (i.e, the dispatch group to
23270 which INSN belongs). This means that INSN will be the last insn in the
23271 group it belongs to.
23273 If WHICH_GROUP == previous_group, this function will return true if INSN
23274 causes the termination of the previous group (i.e, the dispatch group that
23275 precedes the group to which INSN belongs). This means that INSN will be
23276 the first insn in the group it belongs to). */
23279 insn_terminates_group_p (rtx insn, enum group_termination which_group)
23286 first = insn_must_be_first_in_group (insn);
23287 last = insn_must_be_last_in_group (insn);
23292 if (which_group == current_group)
23294 else if (which_group == previous_group)
23302 insn_must_be_first_in_group (rtx insn)
23304 enum attr_type type;
23307 || GET_CODE (insn) == NOTE
23308 || DEBUG_INSN_P (insn)
23309 || GET_CODE (PATTERN (insn)) == USE
23310 || GET_CODE (PATTERN (insn)) == CLOBBER)
23313 switch (rs6000_cpu)
23315 case PROCESSOR_POWER5:
23316 if (is_cracked_insn (insn))
23318 case PROCESSOR_POWER4:
23319 if (is_microcoded_insn (insn))
23322 if (!rs6000_sched_groups)
23325 type = get_attr_type (insn);
23332 case TYPE_DELAYED_CR:
23333 case TYPE_CR_LOGICAL:
23347 case PROCESSOR_POWER6:
23348 type = get_attr_type (insn);
23352 case TYPE_INSERT_DWORD:
23356 case TYPE_VAR_SHIFT_ROTATE:
23363 case TYPE_INSERT_WORD:
23364 case TYPE_DELAYED_COMPARE:
23365 case TYPE_IMUL_COMPARE:
23366 case TYPE_LMUL_COMPARE:
23367 case TYPE_FPCOMPARE:
23378 case TYPE_LOAD_EXT_UX:
23380 case TYPE_STORE_UX:
23381 case TYPE_FPLOAD_U:
23382 case TYPE_FPLOAD_UX:
23383 case TYPE_FPSTORE_U:
23384 case TYPE_FPSTORE_UX:
23390 case PROCESSOR_POWER7:
23391 type = get_attr_type (insn);
23395 case TYPE_CR_LOGICAL:
23402 case TYPE_DELAYED_COMPARE:
23403 case TYPE_VAR_DELAYED_COMPARE:
23409 case TYPE_LOAD_EXT:
23410 case TYPE_LOAD_EXT_U:
23411 case TYPE_LOAD_EXT_UX:
23413 case TYPE_STORE_UX:
23414 case TYPE_FPLOAD_U:
23415 case TYPE_FPLOAD_UX:
23416 case TYPE_FPSTORE_U:
23417 case TYPE_FPSTORE_UX:
23433 insn_must_be_last_in_group (rtx insn)
23435 enum attr_type type;
23438 || GET_CODE (insn) == NOTE
23439 || DEBUG_INSN_P (insn)
23440 || GET_CODE (PATTERN (insn)) == USE
23441 || GET_CODE (PATTERN (insn)) == CLOBBER)
23444 switch (rs6000_cpu) {
23445 case PROCESSOR_POWER4:
23446 case PROCESSOR_POWER5:
23447 if (is_microcoded_insn (insn))
23450 if (is_branch_slot_insn (insn))
23454 case PROCESSOR_POWER6:
23455 type = get_attr_type (insn);
23462 case TYPE_VAR_SHIFT_ROTATE:
23469 case TYPE_DELAYED_COMPARE:
23470 case TYPE_IMUL_COMPARE:
23471 case TYPE_LMUL_COMPARE:
23472 case TYPE_FPCOMPARE:
23486 case PROCESSOR_POWER7:
23487 type = get_attr_type (insn);
23495 case TYPE_LOAD_EXT_U:
23496 case TYPE_LOAD_EXT_UX:
23497 case TYPE_STORE_UX:
23510 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
23511 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
23514 is_costly_group (rtx *group_insns, rtx next_insn)
23517 int issue_rate = rs6000_issue_rate ();
23519 for (i = 0; i < issue_rate; i++)
23521 sd_iterator_def sd_it;
23523 rtx insn = group_insns[i];
23528 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
23530 rtx next = DEP_CON (dep);
23532 if (next == next_insn
23533 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
23541 /* Utility of the function redefine_groups.
23542 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
23543 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
23544 to keep it "far" (in a separate group) from GROUP_INSNS, following
23545 one of the following schemes, depending on the value of the flag
23546 -minsert_sched_nops = X:
23547 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
23548 in order to force NEXT_INSN into a separate group.
23549 (2) X < sched_finish_regroup_exact: insert exactly X nops.
23550 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
23551 insertion (has a group just ended, how many vacant issue slots remain in the
23552 last group, and how many dispatch groups were encountered so far). */
23555 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
23556 rtx next_insn, bool *group_end, int can_issue_more,
23561 int issue_rate = rs6000_issue_rate ();
23562 bool end = *group_end;
23565 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
23566 return can_issue_more;
23568 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
23569 return can_issue_more;
23571 force = is_costly_group (group_insns, next_insn);
23573 return can_issue_more;
23575 if (sched_verbose > 6)
23576 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
23577 *group_count ,can_issue_more);
23579 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
23582 can_issue_more = 0;
23584 /* Since only a branch can be issued in the last issue_slot, it is
23585 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
23586 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
23587 in this case the last nop will start a new group and the branch
23588 will be forced to the new group. */
23589 if (can_issue_more && !is_branch_slot_insn (next_insn))
23592 while (can_issue_more > 0)
23595 emit_insn_before (nop, next_insn);
23603 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
23605 int n_nops = rs6000_sched_insert_nops;
23607 /* Nops can't be issued from the branch slot, so the effective
23608 issue_rate for nops is 'issue_rate - 1'. */
23609 if (can_issue_more == 0)
23610 can_issue_more = issue_rate;
23612 if (can_issue_more == 0)
23614 can_issue_more = issue_rate - 1;
23617 for (i = 0; i < issue_rate; i++)
23619 group_insns[i] = 0;
23626 emit_insn_before (nop, next_insn);
23627 if (can_issue_more == issue_rate - 1) /* new group begins */
23630 if (can_issue_more == 0)
23632 can_issue_more = issue_rate - 1;
23635 for (i = 0; i < issue_rate; i++)
23637 group_insns[i] = 0;
23643 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
23646 /* Is next_insn going to start a new group? */
23649 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23650 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23651 || (can_issue_more < issue_rate &&
23652 insn_terminates_group_p (next_insn, previous_group)));
23653 if (*group_end && end)
23656 if (sched_verbose > 6)
23657 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
23658 *group_count, can_issue_more);
23659 return can_issue_more;
23662 return can_issue_more;
23665 /* This function tries to synch the dispatch groups that the compiler "sees"
23666 with the dispatch groups that the processor dispatcher is expected to
23667 form in practice. It tries to achieve this synchronization by forcing the
23668 estimated processor grouping on the compiler (as opposed to the function
23669 'pad_goups' which tries to force the scheduler's grouping on the processor).
23671 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
23672 examines the (estimated) dispatch groups that will be formed by the processor
23673 dispatcher. It marks these group boundaries to reflect the estimated
23674 processor grouping, overriding the grouping that the scheduler had marked.
23675 Depending on the value of the flag '-minsert-sched-nops' this function can
23676 force certain insns into separate groups or force a certain distance between
23677 them by inserting nops, for example, if there exists a "costly dependence"
23680 The function estimates the group boundaries that the processor will form as
23681 follows: It keeps track of how many vacant issue slots are available after
23682 each insn. A subsequent insn will start a new group if one of the following
23684 - no more vacant issue slots remain in the current dispatch group.
23685 - only the last issue slot, which is the branch slot, is vacant, but the next
23686 insn is not a branch.
23687 - only the last 2 or less issue slots, including the branch slot, are vacant,
23688 which means that a cracked insn (which occupies two issue slots) can't be
23689 issued in this group.
23690 - less than 'issue_rate' slots are vacant, and the next insn always needs to
23691 start a new group. */
23694 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23696 rtx insn, next_insn;
23698 int can_issue_more;
23701 int group_count = 0;
23705 issue_rate = rs6000_issue_rate ();
23706 group_insns = XALLOCAVEC (rtx, issue_rate);
23707 for (i = 0; i < issue_rate; i++)
23709 group_insns[i] = 0;
23711 can_issue_more = issue_rate;
23713 insn = get_next_active_insn (prev_head_insn, tail);
23716 while (insn != NULL_RTX)
23718 slot = (issue_rate - can_issue_more);
23719 group_insns[slot] = insn;
23721 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23722 if (insn_terminates_group_p (insn, current_group))
23723 can_issue_more = 0;
23725 next_insn = get_next_active_insn (insn, tail);
23726 if (next_insn == NULL_RTX)
23727 return group_count + 1;
23729 /* Is next_insn going to start a new group? */
23731 = (can_issue_more == 0
23732 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23733 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23734 || (can_issue_more < issue_rate &&
23735 insn_terminates_group_p (next_insn, previous_group)));
23737 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
23738 next_insn, &group_end, can_issue_more,
23744 can_issue_more = 0;
23745 for (i = 0; i < issue_rate; i++)
23747 group_insns[i] = 0;
23751 if (GET_MODE (next_insn) == TImode && can_issue_more)
23752 PUT_MODE (next_insn, VOIDmode);
23753 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
23754 PUT_MODE (next_insn, TImode);
23757 if (can_issue_more == 0)
23758 can_issue_more = issue_rate;
23761 return group_count;
23764 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
23765 dispatch group boundaries that the scheduler had marked. Pad with nops
23766 any dispatch groups which have vacant issue slots, in order to force the
23767 scheduler's grouping on the processor dispatcher. The function
23768 returns the number of dispatch groups found. */
23771 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23773 rtx insn, next_insn;
23776 int can_issue_more;
23778 int group_count = 0;
23780 /* Initialize issue_rate. */
23781 issue_rate = rs6000_issue_rate ();
23782 can_issue_more = issue_rate;
23784 insn = get_next_active_insn (prev_head_insn, tail);
23785 next_insn = get_next_active_insn (insn, tail);
23787 while (insn != NULL_RTX)
23790 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23792 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
23794 if (next_insn == NULL_RTX)
23799 /* If the scheduler had marked group termination at this location
23800 (between insn and next_insn), and neither insn nor next_insn will
23801 force group termination, pad the group with nops to force group
23804 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
23805 && !insn_terminates_group_p (insn, current_group)
23806 && !insn_terminates_group_p (next_insn, previous_group))
23808 if (!is_branch_slot_insn (next_insn))
23811 while (can_issue_more)
23814 emit_insn_before (nop, next_insn);
23819 can_issue_more = issue_rate;
23824 next_insn = get_next_active_insn (insn, tail);
23827 return group_count;
23830 /* We're beginning a new block. Initialize data structures as necessary. */
23833 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
23834 int sched_verbose ATTRIBUTE_UNUSED,
23835 int max_ready ATTRIBUTE_UNUSED)
23837 last_scheduled_insn = NULL_RTX;
23838 load_store_pendulum = 0;
23841 /* The following function is called at the end of scheduling BB.
23842 After reload, it inserts nops at insn group bundling. */
23845 rs6000_sched_finish (FILE *dump, int sched_verbose)
23850 fprintf (dump, "=== Finishing schedule.\n");
23852 if (reload_completed && rs6000_sched_groups)
23854 /* Do not run sched_finish hook when selective scheduling enabled. */
23855 if (sel_sched_p ())
23858 if (rs6000_sched_insert_nops == sched_finish_none)
23861 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
23862 n_groups = pad_groups (dump, sched_verbose,
23863 current_sched_info->prev_head,
23864 current_sched_info->next_tail);
23866 n_groups = redefine_groups (dump, sched_verbose,
23867 current_sched_info->prev_head,
23868 current_sched_info->next_tail);
23870 if (sched_verbose >= 6)
23872 fprintf (dump, "ngroups = %d\n", n_groups);
23873 print_rtl (dump, current_sched_info->prev_head);
23874 fprintf (dump, "Done finish_sched\n");
23879 struct _rs6000_sched_context
23881 short cached_can_issue_more;
23882 rtx last_scheduled_insn;
23883 int load_store_pendulum;
23886 typedef struct _rs6000_sched_context rs6000_sched_context_def;
23887 typedef rs6000_sched_context_def *rs6000_sched_context_t;
23889 /* Allocate store for new scheduling context. */
23891 rs6000_alloc_sched_context (void)
23893 return xmalloc (sizeof (rs6000_sched_context_def));
23896 /* If CLEAN_P is true then initializes _SC with clean data,
23897 and from the global context otherwise. */
23899 rs6000_init_sched_context (void *_sc, bool clean_p)
23901 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
23905 sc->cached_can_issue_more = 0;
23906 sc->last_scheduled_insn = NULL_RTX;
23907 sc->load_store_pendulum = 0;
23911 sc->cached_can_issue_more = cached_can_issue_more;
23912 sc->last_scheduled_insn = last_scheduled_insn;
23913 sc->load_store_pendulum = load_store_pendulum;
23917 /* Sets the global scheduling context to the one pointed to by _SC. */
23919 rs6000_set_sched_context (void *_sc)
23921 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
23923 gcc_assert (sc != NULL);
23925 cached_can_issue_more = sc->cached_can_issue_more;
23926 last_scheduled_insn = sc->last_scheduled_insn;
23927 load_store_pendulum = sc->load_store_pendulum;
23932 rs6000_free_sched_context (void *_sc)
23934 gcc_assert (_sc != NULL);
23940 /* Length in units of the trampoline for entering a nested function. */
23943 rs6000_trampoline_size (void)
23947 switch (DEFAULT_ABI)
23950 gcc_unreachable ();
23953 ret = (TARGET_32BIT) ? 12 : 24;
23958 ret = (TARGET_32BIT) ? 40 : 48;
23965 /* Emit RTL insns to initialize the variable parts of a trampoline.
23966 FNADDR is an RTX for the address of the function's pure code.
23967 CXT is an RTX for the static chain value for the function. */
23970 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
23972 int regsize = (TARGET_32BIT) ? 4 : 8;
23973 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
23974 rtx ctx_reg = force_reg (Pmode, cxt);
23975 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
23977 switch (DEFAULT_ABI)
23980 gcc_unreachable ();
23982 /* Under AIX, just build the 3 word function descriptor */
23985 rtx fnmem, fn_reg, toc_reg;
23987 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
23988 error ("-mno-r11 must not be used if you have trampolines");
23990 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
23991 fn_reg = gen_reg_rtx (Pmode);
23992 toc_reg = gen_reg_rtx (Pmode);
23994 /* Macro to shorten the code expansions below. */
23995 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
23997 m_tramp = replace_equiv_address (m_tramp, addr);
23999 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
24000 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
24001 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
24002 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
24003 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
24009 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24012 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
24013 LCT_NORMAL, VOIDmode, 4,
24015 GEN_INT (rs6000_trampoline_size ()), SImode,
24023 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24024 identifier as an argument, so the front end shouldn't look it up. */
24027 rs6000_attribute_takes_identifier_p (const_tree attr_id)
24029 return is_attribute_p ("altivec", attr_id);
24032 /* Handle the "altivec" attribute. The attribute may have
24033 arguments as follows:
24035 __attribute__((altivec(vector__)))
24036 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24037 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24039 and may appear more than once (e.g., 'vector bool char') in a
24040 given declaration. */
24043 rs6000_handle_altivec_attribute (tree *node,
24044 tree name ATTRIBUTE_UNUSED,
24046 int flags ATTRIBUTE_UNUSED,
24047 bool *no_add_attrs)
24049 tree type = *node, result = NULL_TREE;
24050 enum machine_mode mode;
24053 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
24054 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
24055 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
24058 while (POINTER_TYPE_P (type)
24059 || TREE_CODE (type) == FUNCTION_TYPE
24060 || TREE_CODE (type) == METHOD_TYPE
24061 || TREE_CODE (type) == ARRAY_TYPE)
24062 type = TREE_TYPE (type);
24064 mode = TYPE_MODE (type);
24066 /* Check for invalid AltiVec type qualifiers. */
24067 if (type == long_double_type_node)
24068 error ("use of %<long double%> in AltiVec types is invalid");
24069 else if (type == boolean_type_node)
24070 error ("use of boolean types in AltiVec types is invalid");
24071 else if (TREE_CODE (type) == COMPLEX_TYPE)
24072 error ("use of %<complex%> in AltiVec types is invalid");
24073 else if (DECIMAL_FLOAT_MODE_P (mode))
24074 error ("use of decimal floating point types in AltiVec types is invalid");
24075 else if (!TARGET_VSX)
24077 if (type == long_unsigned_type_node || type == long_integer_type_node)
24080 error ("use of %<long%> in AltiVec types is invalid for "
24081 "64-bit code without -mvsx");
24082 else if (rs6000_warn_altivec_long)
24083 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24086 else if (type == long_long_unsigned_type_node
24087 || type == long_long_integer_type_node)
24088 error ("use of %<long long%> in AltiVec types is invalid without "
24090 else if (type == double_type_node)
24091 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24094 switch (altivec_type)
24097 unsigned_p = TYPE_UNSIGNED (type);
24101 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
24104 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
24107 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
24110 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
24112 case SFmode: result = V4SF_type_node; break;
24113 case DFmode: result = V2DF_type_node; break;
24114 /* If the user says 'vector int bool', we may be handed the 'bool'
24115 attribute _before_ the 'vector' attribute, and so select the
24116 proper type in the 'b' case below. */
24117 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
24118 case V2DImode: case V2DFmode:
24126 case DImode: case V2DImode: result = bool_V2DI_type_node; break;
24127 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
24128 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
24129 case QImode: case V16QImode: result = bool_V16QI_type_node;
24136 case V8HImode: result = pixel_V8HI_type_node;
24142 /* Propagate qualifiers attached to the element type
24143 onto the vector type. */
24144 if (result && result != type && TYPE_QUALS (type))
24145 result = build_qualified_type (result, TYPE_QUALS (type));
24147 *no_add_attrs = true; /* No need to hang on to the attribute. */
24150 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
24155 /* AltiVec defines four built-in scalar types that serve as vector
24156 elements; we must teach the compiler how to mangle them. */
24158 static const char *
24159 rs6000_mangle_type (const_tree type)
24161 type = TYPE_MAIN_VARIANT (type);
24163 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24164 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24167 if (type == bool_char_type_node) return "U6__boolc";
24168 if (type == bool_short_type_node) return "U6__bools";
24169 if (type == pixel_type_node) return "u7__pixel";
24170 if (type == bool_int_type_node) return "U6__booli";
24171 if (type == bool_long_type_node) return "U6__booll";
24173 /* Mangle IBM extended float long double as `g' (__float128) on
24174 powerpc*-linux where long-double-64 previously was the default. */
24175 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
24177 && TARGET_LONG_DOUBLE_128
24178 && !TARGET_IEEEQUAD)
24181 /* For all other types, use normal C++ mangling. */
24185 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24186 struct attribute_spec.handler. */
24189 rs6000_handle_longcall_attribute (tree *node, tree name,
24190 tree args ATTRIBUTE_UNUSED,
24191 int flags ATTRIBUTE_UNUSED,
24192 bool *no_add_attrs)
24194 if (TREE_CODE (*node) != FUNCTION_TYPE
24195 && TREE_CODE (*node) != FIELD_DECL
24196 && TREE_CODE (*node) != TYPE_DECL)
24198 warning (OPT_Wattributes, "%qE attribute only applies to functions",
24200 *no_add_attrs = true;
24206 /* Set longcall attributes on all functions declared when
24207 rs6000_default_long_calls is true. */
24209 rs6000_set_default_type_attributes (tree type)
24211 if (rs6000_default_long_calls
24212 && (TREE_CODE (type) == FUNCTION_TYPE
24213 || TREE_CODE (type) == METHOD_TYPE))
24214 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
24216 TYPE_ATTRIBUTES (type));
24219 darwin_set_default_type_attributes (type);
24223 /* Return a reference suitable for calling a function with the
24224 longcall attribute. */
24227 rs6000_longcall_ref (rtx call_ref)
24229 const char *call_name;
24232 if (GET_CODE (call_ref) != SYMBOL_REF)
24235 /* System V adds '.' to the internal name, so skip them. */
24236 call_name = XSTR (call_ref, 0);
24237 if (*call_name == '.')
24239 while (*call_name == '.')
24242 node = get_identifier (call_name);
24243 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
24246 return force_reg (Pmode, call_ref);
24249 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24250 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24253 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24254 struct attribute_spec.handler. */
24256 rs6000_handle_struct_attribute (tree *node, tree name,
24257 tree args ATTRIBUTE_UNUSED,
24258 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24261 if (DECL_P (*node))
24263 if (TREE_CODE (*node) == TYPE_DECL)
24264 type = &TREE_TYPE (*node);
24269 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24270 || TREE_CODE (*type) == UNION_TYPE)))
24272 warning (OPT_Wattributes, "%qE attribute ignored", name);
24273 *no_add_attrs = true;
24276 else if ((is_attribute_p ("ms_struct", name)
24277 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24278 || ((is_attribute_p ("gcc_struct", name)
24279 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24281 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
24283 *no_add_attrs = true;
24290 rs6000_ms_bitfield_layout_p (const_tree record_type)
24292 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
24293 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24294 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24297 #ifdef USING_ELFOS_H
24299 /* A get_unnamed_section callback, used for switching to toc_section. */
24302 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
24304 if (DEFAULT_ABI == ABI_AIX
24305 && TARGET_MINIMAL_TOC
24306 && !TARGET_RELOCATABLE)
24308 if (!toc_initialized)
24310 toc_initialized = 1;
24311 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24312 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
24313 fprintf (asm_out_file, "\t.tc ");
24314 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
24315 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24316 fprintf (asm_out_file, "\n");
24318 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24319 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24320 fprintf (asm_out_file, " = .+32768\n");
24323 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24325 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
24326 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24329 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24330 if (!toc_initialized)
24332 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24333 fprintf (asm_out_file, " = .+32768\n");
24334 toc_initialized = 1;
24339 /* Implement TARGET_ASM_INIT_SECTIONS. */
24342 rs6000_elf_asm_init_sections (void)
24345 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
24348 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
24349 SDATA2_SECTION_ASM_OP);
24352 /* Implement TARGET_SELECT_RTX_SECTION. */
24355 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
24356 unsigned HOST_WIDE_INT align)
24358 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
24359 return toc_section;
24361 return default_elf_select_rtx_section (mode, x, align);
24364 /* For a SYMBOL_REF, set generic flags and then perform some
24365 target-specific processing.
24367 When the AIX ABI is requested on a non-AIX system, replace the
24368 function name with the real name (with a leading .) rather than the
24369 function descriptor name. This saves a lot of overriding code to
24370 read the prefixes. */
24373 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
24375 default_encode_section_info (decl, rtl, first);
24378 && TREE_CODE (decl) == FUNCTION_DECL
24380 && DEFAULT_ABI == ABI_AIX)
24382 rtx sym_ref = XEXP (rtl, 0);
24383 size_t len = strlen (XSTR (sym_ref, 0));
24384 char *str = XALLOCAVEC (char, len + 2);
24386 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
24387 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
24392 compare_section_name (const char *section, const char *templ)
24396 len = strlen (templ);
24397 return (strncmp (section, templ, len) == 0
24398 && (section[len] == 0 || section[len] == '.'));
24402 rs6000_elf_in_small_data_p (const_tree decl)
24404 if (rs6000_sdata == SDATA_NONE)
24407 /* We want to merge strings, so we never consider them small data. */
24408 if (TREE_CODE (decl) == STRING_CST)
24411 /* Functions are never in the small data area. */
24412 if (TREE_CODE (decl) == FUNCTION_DECL)
24415 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
24417 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
24418 if (compare_section_name (section, ".sdata")
24419 || compare_section_name (section, ".sdata2")
24420 || compare_section_name (section, ".gnu.linkonce.s")
24421 || compare_section_name (section, ".sbss")
24422 || compare_section_name (section, ".sbss2")
24423 || compare_section_name (section, ".gnu.linkonce.sb")
24424 || strcmp (section, ".PPC.EMB.sdata0") == 0
24425 || strcmp (section, ".PPC.EMB.sbss0") == 0)
24430 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
24433 && size <= g_switch_value
24434 /* If it's not public, and we're not going to reference it there,
24435 there's no need to put it in the small data section. */
24436 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
24443 #endif /* USING_ELFOS_H */
24445 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
24448 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
24450 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
24453 /* Return a REG that occurs in ADDR with coefficient 1.
24454 ADDR can be effectively incremented by incrementing REG.
24456 r0 is special and we must not select it as an address
24457 register by this routine since our caller will try to
24458 increment the returned register via an "la" instruction. */
24461 find_addr_reg (rtx addr)
24463 while (GET_CODE (addr) == PLUS)
24465 if (GET_CODE (XEXP (addr, 0)) == REG
24466 && REGNO (XEXP (addr, 0)) != 0)
24467 addr = XEXP (addr, 0);
24468 else if (GET_CODE (XEXP (addr, 1)) == REG
24469 && REGNO (XEXP (addr, 1)) != 0)
24470 addr = XEXP (addr, 1);
24471 else if (CONSTANT_P (XEXP (addr, 0)))
24472 addr = XEXP (addr, 1);
24473 else if (CONSTANT_P (XEXP (addr, 1)))
24474 addr = XEXP (addr, 0);
24476 gcc_unreachable ();
24478 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
24483 rs6000_fatal_bad_address (rtx op)
24485 fatal_insn ("bad address", op);
24490 typedef struct branch_island_d {
24491 tree function_name;
24496 DEF_VEC_O(branch_island);
24497 DEF_VEC_ALLOC_O(branch_island,gc);
24499 static VEC(branch_island,gc) *branch_islands;
24501 /* Remember to generate a branch island for far calls to the given
24505 add_compiler_branch_island (tree label_name, tree function_name,
24508 branch_island *bi = VEC_safe_push (branch_island, gc, branch_islands, NULL);
24510 bi->function_name = function_name;
24511 bi->label_name = label_name;
24512 bi->line_number = line_number;
24515 /* Generate far-jump branch islands for everything recorded in
24516 branch_islands. Invoked immediately after the last instruction of
24517 the epilogue has been emitted; the branch islands must be appended
24518 to, and contiguous with, the function body. Mach-O stubs are
24519 generated in machopic_output_stub(). */
24522 macho_branch_islands (void)
24526 while (!VEC_empty (branch_island, branch_islands))
24528 branch_island *bi = VEC_last (branch_island, branch_islands);
24529 const char *label = IDENTIFIER_POINTER (bi->label_name);
24530 const char *name = IDENTIFIER_POINTER (bi->function_name);
24531 char name_buf[512];
24532 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
24533 if (name[0] == '*' || name[0] == '&')
24534 strcpy (name_buf, name+1);
24538 strcpy (name_buf+1, name);
24540 strcpy (tmp_buf, "\n");
24541 strcat (tmp_buf, label);
24542 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24543 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24544 dbxout_stabd (N_SLINE, bi->line_number);
24545 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24548 if (TARGET_LINK_STACK)
24551 get_ppc476_thunk_name (name);
24552 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
24553 strcat (tmp_buf, name);
24554 strcat (tmp_buf, "\n");
24555 strcat (tmp_buf, label);
24556 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24560 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
24561 strcat (tmp_buf, label);
24562 strcat (tmp_buf, "_pic\n");
24563 strcat (tmp_buf, label);
24564 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24567 strcat (tmp_buf, "\taddis r11,r11,ha16(");
24568 strcat (tmp_buf, name_buf);
24569 strcat (tmp_buf, " - ");
24570 strcat (tmp_buf, label);
24571 strcat (tmp_buf, "_pic)\n");
24573 strcat (tmp_buf, "\tmtlr r0\n");
24575 strcat (tmp_buf, "\taddi r12,r11,lo16(");
24576 strcat (tmp_buf, name_buf);
24577 strcat (tmp_buf, " - ");
24578 strcat (tmp_buf, label);
24579 strcat (tmp_buf, "_pic)\n");
24581 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
24585 strcat (tmp_buf, ":\nlis r12,hi16(");
24586 strcat (tmp_buf, name_buf);
24587 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
24588 strcat (tmp_buf, name_buf);
24589 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
24591 output_asm_insn (tmp_buf, 0);
24592 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24593 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24594 dbxout_stabd (N_SLINE, bi->line_number);
24595 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24596 VEC_pop (branch_island, branch_islands);
24600 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
24601 already there or not. */
24604 no_previous_def (tree function_name)
24609 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24610 if (function_name == bi->function_name)
24615 /* GET_PREV_LABEL gets the label name from the previous definition of
24619 get_prev_label (tree function_name)
24624 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24625 if (function_name == bi->function_name)
24626 return bi->label_name;
24630 /* INSN is either a function call or a millicode call. It may have an
24631 unconditional jump in its delay slot.
24633 CALL_DEST is the routine we are calling. */
24636 output_call (rtx insn, rtx *operands, int dest_operand_number,
24637 int cookie_operand_number)
24639 static char buf[256];
24640 if (darwin_emit_branch_islands
24641 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
24642 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
24645 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
24647 if (no_previous_def (funname))
24649 rtx label_rtx = gen_label_rtx ();
24650 char *label_buf, temp_buf[256];
24651 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
24652 CODE_LABEL_NUMBER (label_rtx));
24653 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
24654 labelname = get_identifier (label_buf);
24655 add_compiler_branch_island (labelname, funname, insn_line (insn));
24658 labelname = get_prev_label (funname);
24660 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
24661 instruction will reach 'foo', otherwise link as 'bl L42'".
24662 "L42" should be a 'branch island', that will do a far jump to
24663 'foo'. Branch islands are generated in
24664 macho_branch_islands(). */
24665 sprintf (buf, "jbsr %%z%d,%.246s",
24666 dest_operand_number, IDENTIFIER_POINTER (labelname));
24669 sprintf (buf, "bl %%z%d", dest_operand_number);
24673 /* Generate PIC and indirect symbol stubs. */
24676 machopic_output_stub (FILE *file, const char *symb, const char *stub)
24678 unsigned int length;
24679 char *symbol_name, *lazy_ptr_name;
24680 char *local_label_0;
24681 static int label = 0;
24683 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
24684 symb = (*targetm.strip_name_encoding) (symb);
24687 length = strlen (symb);
24688 symbol_name = XALLOCAVEC (char, length + 32);
24689 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
24691 lazy_ptr_name = XALLOCAVEC (char, length + 32);
24692 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
24695 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
24697 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
24701 fprintf (file, "\t.align 5\n");
24703 fprintf (file, "%s:\n", stub);
24704 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24707 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
24708 sprintf (local_label_0, "\"L%011d$spb\"", label);
24710 fprintf (file, "\tmflr r0\n");
24711 if (TARGET_LINK_STACK)
24714 get_ppc476_thunk_name (name);
24715 fprintf (file, "\tbl %s\n", name);
24716 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24720 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
24721 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24723 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
24724 lazy_ptr_name, local_label_0);
24725 fprintf (file, "\tmtlr r0\n");
24726 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
24727 (TARGET_64BIT ? "ldu" : "lwzu"),
24728 lazy_ptr_name, local_label_0);
24729 fprintf (file, "\tmtctr r12\n");
24730 fprintf (file, "\tbctr\n");
24734 fprintf (file, "\t.align 4\n");
24736 fprintf (file, "%s:\n", stub);
24737 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24739 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
24740 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
24741 (TARGET_64BIT ? "ldu" : "lwzu"),
24743 fprintf (file, "\tmtctr r12\n");
24744 fprintf (file, "\tbctr\n");
24747 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
24748 fprintf (file, "%s:\n", lazy_ptr_name);
24749 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24750 fprintf (file, "%sdyld_stub_binding_helper\n",
24751 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
24754 /* Legitimize PIC addresses. If the address is already
24755 position-independent, we return ORIG. Newly generated
24756 position-independent addresses go into a reg. This is REG if non
24757 zero, otherwise we allocate register(s) as necessary. */
24759 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
24762 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
24767 if (reg == NULL && ! reload_in_progress && ! reload_completed)
24768 reg = gen_reg_rtx (Pmode);
24770 if (GET_CODE (orig) == CONST)
24774 if (GET_CODE (XEXP (orig, 0)) == PLUS
24775 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
24778 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
24780 /* Use a different reg for the intermediate value, as
24781 it will be marked UNCHANGING. */
24782 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
24783 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
24786 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
24789 if (GET_CODE (offset) == CONST_INT)
24791 if (SMALL_INT (offset))
24792 return plus_constant (base, INTVAL (offset));
24793 else if (! reload_in_progress && ! reload_completed)
24794 offset = force_reg (Pmode, offset);
24797 rtx mem = force_const_mem (Pmode, orig);
24798 return machopic_legitimize_pic_address (mem, Pmode, reg);
24801 return gen_rtx_PLUS (Pmode, base, offset);
24804 /* Fall back on generic machopic code. */
24805 return machopic_legitimize_pic_address (orig, mode, reg);
24808 /* Output a .machine directive for the Darwin assembler, and call
24809 the generic start_file routine. */
24812 rs6000_darwin_file_start (void)
24814 static const struct
24820 { "ppc64", "ppc64", MASK_64BIT },
24821 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
24822 { "power4", "ppc970", 0 },
24823 { "G5", "ppc970", 0 },
24824 { "7450", "ppc7450", 0 },
24825 { "7400", "ppc7400", MASK_ALTIVEC },
24826 { "G4", "ppc7400", 0 },
24827 { "750", "ppc750", 0 },
24828 { "740", "ppc750", 0 },
24829 { "G3", "ppc750", 0 },
24830 { "604e", "ppc604e", 0 },
24831 { "604", "ppc604", 0 },
24832 { "603e", "ppc603", 0 },
24833 { "603", "ppc603", 0 },
24834 { "601", "ppc601", 0 },
24835 { NULL, "ppc", 0 } };
24836 const char *cpu_id = "";
24839 rs6000_file_start ();
24840 darwin_file_start ();
24842 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
24844 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
24845 cpu_id = rs6000_default_cpu;
24847 if (global_options_set.x_rs6000_cpu_index)
24848 cpu_id = processor_target_table[rs6000_cpu_index].name;
24850 /* Look through the mapping array. Pick the first name that either
24851 matches the argument, has a bit set in IF_SET that is also set
24852 in the target flags, or has a NULL name. */
24855 while (mapping[i].arg != NULL
24856 && strcmp (mapping[i].arg, cpu_id) != 0
24857 && (mapping[i].if_set & target_flags) == 0)
24860 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
24863 #endif /* TARGET_MACHO */
24867 rs6000_elf_reloc_rw_mask (void)
24871 else if (DEFAULT_ABI == ABI_AIX)
24877 /* Record an element in the table of global constructors. SYMBOL is
24878 a SYMBOL_REF of the function to be called; PRIORITY is a number
24879 between 0 and MAX_INIT_PRIORITY.
24881 This differs from default_named_section_asm_out_constructor in
24882 that we have special handling for -mrelocatable. */
24885 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
24887 const char *section = ".ctors";
24890 if (priority != DEFAULT_INIT_PRIORITY)
24892 sprintf (buf, ".ctors.%.5u",
24893 /* Invert the numbering so the linker puts us in the proper
24894 order; constructors are run from right to left, and the
24895 linker sorts in increasing order. */
24896 MAX_INIT_PRIORITY - priority);
24900 switch_to_section (get_section (section, SECTION_WRITE, NULL));
24901 assemble_align (POINTER_SIZE);
24903 if (TARGET_RELOCATABLE)
24905 fputs ("\t.long (", asm_out_file);
24906 output_addr_const (asm_out_file, symbol);
24907 fputs (")@fixup\n", asm_out_file);
24910 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
24914 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
24916 const char *section = ".dtors";
24919 if (priority != DEFAULT_INIT_PRIORITY)
24921 sprintf (buf, ".dtors.%.5u",
24922 /* Invert the numbering so the linker puts us in the proper
24923 order; constructors are run from right to left, and the
24924 linker sorts in increasing order. */
24925 MAX_INIT_PRIORITY - priority);
24929 switch_to_section (get_section (section, SECTION_WRITE, NULL));
24930 assemble_align (POINTER_SIZE);
24932 if (TARGET_RELOCATABLE)
24934 fputs ("\t.long (", asm_out_file);
24935 output_addr_const (asm_out_file, symbol);
24936 fputs (")@fixup\n", asm_out_file);
24939 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
24943 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
24947 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
24948 ASM_OUTPUT_LABEL (file, name);
24949 fputs (DOUBLE_INT_ASM_OP, file);
24950 rs6000_output_function_entry (file, name);
24951 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
24954 fputs ("\t.size\t", file);
24955 assemble_name (file, name);
24956 fputs (",24\n\t.type\t.", file);
24957 assemble_name (file, name);
24958 fputs (",@function\n", file);
24959 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
24961 fputs ("\t.globl\t.", file);
24962 assemble_name (file, name);
24967 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
24968 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
24969 rs6000_output_function_entry (file, name);
24970 fputs (":\n", file);
24974 if (TARGET_RELOCATABLE
24975 && !TARGET_SECURE_PLT
24976 && (get_pool_size () != 0 || crtl->profile)
24981 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
24983 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
24984 fprintf (file, "\t.long ");
24985 assemble_name (file, buf);
24987 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24988 assemble_name (file, buf);
24992 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
24993 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
24995 if (DEFAULT_ABI == ABI_AIX)
24997 const char *desc_name, *orig_name;
24999 orig_name = (*targetm.strip_name_encoding) (name);
25000 desc_name = orig_name;
25001 while (*desc_name == '.')
25004 if (TREE_PUBLIC (decl))
25005 fprintf (file, "\t.globl %s\n", desc_name);
25007 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
25008 fprintf (file, "%s:\n", desc_name);
25009 fprintf (file, "\t.long %s\n", orig_name);
25010 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
25011 if (DEFAULT_ABI == ABI_AIX)
25012 fputs ("\t.long 0\n", file);
25013 fprintf (file, "\t.previous\n");
25015 ASM_OUTPUT_LABEL (file, name);
25019 rs6000_elf_file_end (void)
25021 #ifdef HAVE_AS_GNU_ATTRIBUTE
25022 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
25024 if (rs6000_passes_float)
25025 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
25026 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
25027 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
25029 if (rs6000_passes_vector)
25030 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
25031 (TARGET_ALTIVEC_ABI ? 2
25032 : TARGET_SPE_ABI ? 3
25034 if (rs6000_returns_struct)
25035 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
25036 aix_struct_return ? 2 : 1);
25039 #ifdef POWERPC_LINUX
25041 file_end_indicate_exec_stack ();
25048 rs6000_xcoff_asm_output_anchor (rtx symbol)
25052 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
25053 SYMBOL_REF_BLOCK_OFFSET (symbol));
25054 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
25058 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
25060 fputs (GLOBAL_ASM_OP, stream);
25061 RS6000_OUTPUT_BASENAME (stream, name);
25062 putc ('\n', stream);
25065 /* A get_unnamed_decl callback, used for read-only sections. PTR
25066 points to the section string variable. */
25069 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
25071 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
25072 *(const char *const *) directive,
25073 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25076 /* Likewise for read-write sections. */
25079 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
25081 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
25082 *(const char *const *) directive,
25083 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25086 /* A get_unnamed_section callback, used for switching to toc_section. */
25089 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
25091 if (TARGET_MINIMAL_TOC)
25093 /* toc_section is always selected at least once from
25094 rs6000_xcoff_file_start, so this is guaranteed to
25095 always be defined once and only once in each file. */
25096 if (!toc_initialized)
25098 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
25099 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
25100 toc_initialized = 1;
25102 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
25103 (TARGET_32BIT ? "" : ",3"));
25106 fputs ("\t.toc\n", asm_out_file);
25109 /* Implement TARGET_ASM_INIT_SECTIONS. */
25112 rs6000_xcoff_asm_init_sections (void)
25114 read_only_data_section
25115 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25116 &xcoff_read_only_section_name);
25118 private_data_section
25119 = get_unnamed_section (SECTION_WRITE,
25120 rs6000_xcoff_output_readwrite_section_asm_op,
25121 &xcoff_private_data_section_name);
25123 read_only_private_data_section
25124 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25125 &xcoff_private_data_section_name);
25128 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
25130 readonly_data_section = read_only_data_section;
25131 exception_section = data_section;
25135 rs6000_xcoff_reloc_rw_mask (void)
25141 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
25142 tree decl ATTRIBUTE_UNUSED)
25145 static const char * const suffix[3] = { "PR", "RO", "RW" };
25147 if (flags & SECTION_CODE)
25149 else if (flags & SECTION_WRITE)
25154 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
25155 (flags & SECTION_CODE) ? "." : "",
25156 name, suffix[smclass], flags & SECTION_ENTSIZE);
25160 rs6000_xcoff_select_section (tree decl, int reloc,
25161 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25163 if (decl_readonly_section (decl, reloc))
25165 if (TREE_PUBLIC (decl))
25166 return read_only_data_section;
25168 return read_only_private_data_section;
25172 if (TREE_PUBLIC (decl))
25173 return data_section;
25175 return private_data_section;
25180 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
25184 /* Use select_section for private and uninitialized data. */
25185 if (!TREE_PUBLIC (decl)
25186 || DECL_COMMON (decl)
25187 || DECL_INITIAL (decl) == NULL_TREE
25188 || DECL_INITIAL (decl) == error_mark_node
25189 || (flag_zero_initialized_in_bss
25190 && initializer_zerop (DECL_INITIAL (decl))))
25193 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
25194 name = (*targetm.strip_name_encoding) (name);
25195 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
25198 /* Select section for constant in constant pool.
25200 On RS/6000, all constants are in the private read-only data area.
25201 However, if this is being placed in the TOC it must be output as a
25205 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
25206 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25208 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25209 return toc_section;
25211 return read_only_private_data_section;
25214 /* Remove any trailing [DS] or the like from the symbol name. */
25216 static const char *
25217 rs6000_xcoff_strip_name_encoding (const char *name)
25222 len = strlen (name);
25223 if (name[len - 1] == ']')
25224 return ggc_alloc_string (name, len - 4);
25229 /* Section attributes. AIX is always PIC. */
25231 static unsigned int
25232 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
25234 unsigned int align;
25235 unsigned int flags = default_section_type_flags (decl, name, reloc);
25237 /* Align to at least UNIT size. */
25238 if (flags & SECTION_CODE || !decl)
25239 align = MIN_UNITS_PER_WORD;
25241 /* Increase alignment of large objects if not already stricter. */
25242 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
25243 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
25244 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
25246 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
25249 /* Output at beginning of assembler file.
25251 Initialize the section names for the RS/6000 at this point.
25253 Specify filename, including full path, to assembler.
25255 We want to go into the TOC section so at least one .toc will be emitted.
25256 Also, in order to output proper .bs/.es pairs, we need at least one static
25257 [RW] section emitted.
25259 Finally, declare mcount when profiling to make the assembler happy. */
25262 rs6000_xcoff_file_start (void)
25264 rs6000_gen_section_name (&xcoff_bss_section_name,
25265 main_input_filename, ".bss_");
25266 rs6000_gen_section_name (&xcoff_private_data_section_name,
25267 main_input_filename, ".rw_");
25268 rs6000_gen_section_name (&xcoff_read_only_section_name,
25269 main_input_filename, ".ro_");
25271 fputs ("\t.file\t", asm_out_file);
25272 output_quoted_string (asm_out_file, main_input_filename);
25273 fputc ('\n', asm_out_file);
25274 if (write_symbols != NO_DEBUG)
25275 switch_to_section (private_data_section);
25276 switch_to_section (text_section);
25278 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
25279 rs6000_file_start ();
25282 /* Output at end of assembler file.
25283 On the RS/6000, referencing data should automatically pull in text. */
25286 rs6000_xcoff_file_end (void)
25288 switch_to_section (text_section);
25289 fputs ("_section_.text:\n", asm_out_file);
25290 switch_to_section (data_section);
25291 fputs (TARGET_32BIT
25292 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25295 #endif /* TARGET_XCOFF */
25297 /* Compute a (partial) cost for rtx X. Return true if the complete
25298 cost has been computed, and false if subexpressions should be
25299 scanned. In either case, *TOTAL contains the cost result. */
25302 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
25303 int *total, bool speed)
25305 enum machine_mode mode = GET_MODE (x);
25309 /* On the RS/6000, if it is valid in the insn, it is free. */
25311 if (((outer_code == SET
25312 || outer_code == PLUS
25313 || outer_code == MINUS)
25314 && (satisfies_constraint_I (x)
25315 || satisfies_constraint_L (x)))
25316 || (outer_code == AND
25317 && (satisfies_constraint_K (x)
25319 ? satisfies_constraint_L (x)
25320 : satisfies_constraint_J (x))
25321 || mask_operand (x, mode)
25323 && mask64_operand (x, DImode))))
25324 || ((outer_code == IOR || outer_code == XOR)
25325 && (satisfies_constraint_K (x)
25327 ? satisfies_constraint_L (x)
25328 : satisfies_constraint_J (x))))
25329 || outer_code == ASHIFT
25330 || outer_code == ASHIFTRT
25331 || outer_code == LSHIFTRT
25332 || outer_code == ROTATE
25333 || outer_code == ROTATERT
25334 || outer_code == ZERO_EXTRACT
25335 || (outer_code == MULT
25336 && satisfies_constraint_I (x))
25337 || ((outer_code == DIV || outer_code == UDIV
25338 || outer_code == MOD || outer_code == UMOD)
25339 && exact_log2 (INTVAL (x)) >= 0)
25340 || (outer_code == COMPARE
25341 && (satisfies_constraint_I (x)
25342 || satisfies_constraint_K (x)))
25343 || ((outer_code == EQ || outer_code == NE)
25344 && (satisfies_constraint_I (x)
25345 || satisfies_constraint_K (x)
25347 ? satisfies_constraint_L (x)
25348 : satisfies_constraint_J (x))))
25349 || (outer_code == GTU
25350 && satisfies_constraint_I (x))
25351 || (outer_code == LTU
25352 && satisfies_constraint_P (x)))
25357 else if ((outer_code == PLUS
25358 && reg_or_add_cint_operand (x, VOIDmode))
25359 || (outer_code == MINUS
25360 && reg_or_sub_cint_operand (x, VOIDmode))
25361 || ((outer_code == SET
25362 || outer_code == IOR
25363 || outer_code == XOR)
25365 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
25367 *total = COSTS_N_INSNS (1);
25373 if (mode == DImode && code == CONST_DOUBLE)
25375 if ((outer_code == IOR || outer_code == XOR)
25376 && CONST_DOUBLE_HIGH (x) == 0
25377 && (CONST_DOUBLE_LOW (x)
25378 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
25383 else if ((outer_code == AND && and64_2_operand (x, DImode))
25384 || ((outer_code == SET
25385 || outer_code == IOR
25386 || outer_code == XOR)
25387 && CONST_DOUBLE_HIGH (x) == 0))
25389 *total = COSTS_N_INSNS (1);
25399 /* When optimizing for size, MEM should be slightly more expensive
25400 than generating address, e.g., (plus (reg) (const)).
25401 L1 cache latency is about two instructions. */
25402 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
25411 if (FLOAT_MODE_P (mode))
25412 *total = rs6000_cost->fp;
25414 *total = COSTS_N_INSNS (1);
25418 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25419 && satisfies_constraint_I (XEXP (x, 1)))
25421 if (INTVAL (XEXP (x, 1)) >= -256
25422 && INTVAL (XEXP (x, 1)) <= 255)
25423 *total = rs6000_cost->mulsi_const9;
25425 *total = rs6000_cost->mulsi_const;
25427 else if (mode == SFmode)
25428 *total = rs6000_cost->fp;
25429 else if (FLOAT_MODE_P (mode))
25430 *total = rs6000_cost->dmul;
25431 else if (mode == DImode)
25432 *total = rs6000_cost->muldi;
25434 *total = rs6000_cost->mulsi;
25438 if (mode == SFmode)
25439 *total = rs6000_cost->fp;
25441 *total = rs6000_cost->dmul;
25446 if (FLOAT_MODE_P (mode))
25448 *total = mode == DFmode ? rs6000_cost->ddiv
25449 : rs6000_cost->sdiv;
25456 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25457 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
25459 if (code == DIV || code == MOD)
25461 *total = COSTS_N_INSNS (2);
25464 *total = COSTS_N_INSNS (1);
25468 if (GET_MODE (XEXP (x, 1)) == DImode)
25469 *total = rs6000_cost->divdi;
25471 *total = rs6000_cost->divsi;
25473 /* Add in shift and subtract for MOD. */
25474 if (code == MOD || code == UMOD)
25475 *total += COSTS_N_INSNS (2);
25480 *total = COSTS_N_INSNS (4);
25484 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
25488 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
25492 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
25504 *total = COSTS_N_INSNS (1);
25512 /* Handle mul_highpart. */
25513 if (outer_code == TRUNCATE
25514 && GET_CODE (XEXP (x, 0)) == MULT)
25516 if (mode == DImode)
25517 *total = rs6000_cost->muldi;
25519 *total = rs6000_cost->mulsi;
25522 else if (outer_code == AND)
25525 *total = COSTS_N_INSNS (1);
25530 if (GET_CODE (XEXP (x, 0)) == MEM)
25533 *total = COSTS_N_INSNS (1);
25539 if (!FLOAT_MODE_P (mode))
25541 *total = COSTS_N_INSNS (1);
25547 case UNSIGNED_FLOAT:
25550 case FLOAT_TRUNCATE:
25551 *total = rs6000_cost->fp;
25555 if (mode == DFmode)
25558 *total = rs6000_cost->fp;
25562 switch (XINT (x, 1))
25565 *total = rs6000_cost->fp;
25577 *total = COSTS_N_INSNS (1);
25580 else if (FLOAT_MODE_P (mode)
25581 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
25583 *total = rs6000_cost->fp;
25591 /* Carry bit requires mode == Pmode.
25592 NEG or PLUS already counted so only add one. */
25594 && (outer_code == NEG || outer_code == PLUS))
25596 *total = COSTS_N_INSNS (1);
25599 if (outer_code == SET)
25601 if (XEXP (x, 1) == const0_rtx)
25603 if (TARGET_ISEL && !TARGET_MFCRF)
25604 *total = COSTS_N_INSNS (8);
25606 *total = COSTS_N_INSNS (2);
25609 else if (mode == Pmode)
25611 *total = COSTS_N_INSNS (3);
25620 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
25622 if (TARGET_ISEL && !TARGET_MFCRF)
25623 *total = COSTS_N_INSNS (8);
25625 *total = COSTS_N_INSNS (2);
25629 if (outer_code == COMPARE)
25643 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
25646 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
25649 bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
25652 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
25653 "opno = %d, total = %d, speed = %s, x:\n",
25654 ret ? "complete" : "scan inner",
25655 GET_RTX_NAME (code),
25656 GET_RTX_NAME (outer_code),
25659 speed ? "true" : "false");
25666 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
25669 rs6000_debug_address_cost (rtx x, bool speed)
25671 int ret = TARGET_ADDRESS_COST (x, speed);
25673 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
25674 ret, speed ? "true" : "false");
25681 /* A C expression returning the cost of moving data from a register of class
25682 CLASS1 to one of CLASS2. */
25685 rs6000_register_move_cost (enum machine_mode mode,
25686 reg_class_t from, reg_class_t to)
25690 if (TARGET_DEBUG_COST)
25693 /* Moves from/to GENERAL_REGS. */
25694 if (reg_classes_intersect_p (to, GENERAL_REGS)
25695 || reg_classes_intersect_p (from, GENERAL_REGS))
25697 reg_class_t rclass = from;
25699 if (! reg_classes_intersect_p (to, GENERAL_REGS))
25702 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
25703 ret = (rs6000_memory_move_cost (mode, rclass, false)
25704 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
25706 /* It's more expensive to move CR_REGS than CR0_REGS because of the
25708 else if (rclass == CR_REGS)
25711 /* For those processors that have slow LR/CTR moves, make them more
25712 expensive than memory in order to bias spills to memory .*/
25713 else if ((rs6000_cpu == PROCESSOR_POWER6
25714 || rs6000_cpu == PROCESSOR_POWER7)
25715 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
25716 ret = 6 * hard_regno_nregs[0][mode];
25719 /* A move will cost one instruction per GPR moved. */
25720 ret = 2 * hard_regno_nregs[0][mode];
25723 /* If we have VSX, we can easily move between FPR or Altivec registers. */
25724 else if (VECTOR_UNIT_VSX_P (mode)
25725 && reg_classes_intersect_p (to, VSX_REGS)
25726 && reg_classes_intersect_p (from, VSX_REGS))
25727 ret = 2 * hard_regno_nregs[32][mode];
25729 /* Moving between two similar registers is just one instruction. */
25730 else if (reg_classes_intersect_p (to, from))
25731 ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
25733 /* Everything else has to go through GENERAL_REGS. */
25735 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
25736 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
25738 if (TARGET_DEBUG_COST)
25740 if (dbg_cost_ctrl == 1)
25742 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
25743 ret, GET_MODE_NAME (mode), reg_class_names[from],
25744 reg_class_names[to]);
25751 /* A C expressions returning the cost of moving data of MODE from a register to
25755 rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
25756 bool in ATTRIBUTE_UNUSED)
25760 if (TARGET_DEBUG_COST)
25763 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
25764 ret = 4 * hard_regno_nregs[0][mode];
25765 else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
25766 ret = 4 * hard_regno_nregs[32][mode];
25767 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
25768 ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
25770 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
25772 if (TARGET_DEBUG_COST)
25774 if (dbg_cost_ctrl == 1)
25776 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
25777 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
25784 /* Returns a code for a target-specific builtin that implements
25785 reciprocal of the function, or NULL_TREE if not available. */
25788 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
25789 bool sqrt ATTRIBUTE_UNUSED)
25791 if (optimize_insn_for_size_p ())
25797 case VSX_BUILTIN_XVSQRTDP:
25798 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
25801 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
25803 case VSX_BUILTIN_XVSQRTSP:
25804 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
25807 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
25816 case BUILT_IN_SQRT:
25817 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
25820 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
25822 case BUILT_IN_SQRTF:
25823 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
25826 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
25833 /* Load up a constant. If the mode is a vector mode, splat the value across
25834 all of the vector elements. */
25837 rs6000_load_constant_and_splat (enum machine_mode mode, REAL_VALUE_TYPE dconst)
25841 if (mode == SFmode || mode == DFmode)
25843 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
25844 reg = force_reg (mode, d);
25846 else if (mode == V4SFmode)
25848 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
25849 rtvec v = gen_rtvec (4, d, d, d, d);
25850 reg = gen_reg_rtx (mode);
25851 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
25853 else if (mode == V2DFmode)
25855 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
25856 rtvec v = gen_rtvec (2, d, d);
25857 reg = gen_reg_rtx (mode);
25858 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
25861 gcc_unreachable ();
25866 /* Generate an FMA instruction. */
25869 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
25871 enum machine_mode mode = GET_MODE (target);
25874 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
25875 gcc_assert (dst != NULL);
25878 emit_move_insn (target, dst);
25881 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
25884 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
25886 enum machine_mode mode = GET_MODE (target);
25889 /* Altivec does not support fms directly;
25890 generate in terms of fma in that case. */
25891 if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
25892 dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
25895 a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
25896 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
25898 gcc_assert (dst != NULL);
25901 emit_move_insn (target, dst);
25904 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
25907 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
25909 enum machine_mode mode = GET_MODE (dst);
25912 /* This is a tad more complicated, since the fnma_optab is for
25913 a different expression: fma(-m1, m2, a), which is the same
25914 thing except in the case of signed zeros.
25916 Fortunately we know that if FMA is supported that FNMSUB is
25917 also supported in the ISA. Just expand it directly. */
25919 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
25921 r = gen_rtx_NEG (mode, a);
25922 r = gen_rtx_FMA (mode, m1, m2, r);
25923 r = gen_rtx_NEG (mode, r);
25924 emit_insn (gen_rtx_SET (VOIDmode, dst, r));
25927 /* Newton-Raphson approximation of floating point divide with just 2 passes
25928 (either single precision floating point, or newer machines with higher
25929 accuracy estimates). Support both scalar and vector divide. Assumes no
25930 trapping math and finite arguments. */
25933 rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
25935 enum machine_mode mode = GET_MODE (dst);
25936 rtx x0, e0, e1, y1, u0, v0;
25937 enum insn_code code = optab_handler (smul_optab, mode);
25938 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
25939 rtx one = rs6000_load_constant_and_splat (mode, dconst1);
25941 gcc_assert (code != CODE_FOR_nothing);
25943 /* x0 = 1./d estimate */
25944 x0 = gen_reg_rtx (mode);
25945 emit_insn (gen_rtx_SET (VOIDmode, x0,
25946 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
25949 e0 = gen_reg_rtx (mode);
25950 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */
25952 e1 = gen_reg_rtx (mode);
25953 rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */
25955 y1 = gen_reg_rtx (mode);
25956 rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */
25958 u0 = gen_reg_rtx (mode);
25959 emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */
25961 v0 = gen_reg_rtx (mode);
25962 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */
25964 rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */
25967 /* Newton-Raphson approximation of floating point divide that has a low
25968 precision estimate. Assumes no trapping math and finite arguments. */
25971 rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
25973 enum machine_mode mode = GET_MODE (dst);
25974 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
25975 enum insn_code code = optab_handler (smul_optab, mode);
25976 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
25978 gcc_assert (code != CODE_FOR_nothing);
25980 one = rs6000_load_constant_and_splat (mode, dconst1);
25982 /* x0 = 1./d estimate */
25983 x0 = gen_reg_rtx (mode);
25984 emit_insn (gen_rtx_SET (VOIDmode, x0,
25985 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
25988 e0 = gen_reg_rtx (mode);
25989 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */
25991 y1 = gen_reg_rtx (mode);
25992 rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */
25994 e1 = gen_reg_rtx (mode);
25995 emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */
25997 y2 = gen_reg_rtx (mode);
25998 rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */
26000 e2 = gen_reg_rtx (mode);
26001 emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */
26003 y3 = gen_reg_rtx (mode);
26004 rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */
26006 u0 = gen_reg_rtx (mode);
26007 emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */
26009 v0 = gen_reg_rtx (mode);
26010 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */
26012 rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */
26015 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26016 add a reg_note saying that this was a division. Support both scalar and
26017 vector divide. Assumes no trapping math and finite arguments. */
26020 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
26022 enum machine_mode mode = GET_MODE (dst);
26024 if (RS6000_RECIP_HIGH_PRECISION_P (mode))
26025 rs6000_emit_swdiv_high_precision (dst, n, d);
26027 rs6000_emit_swdiv_low_precision (dst, n, d);
26030 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
26033 /* Newton-Raphson approximation of single/double-precision floating point
26034 rsqrt. Assumes no trapping math and finite arguments. */
26037 rs6000_emit_swrsqrt (rtx dst, rtx src)
26039 enum machine_mode mode = GET_MODE (src);
26040 rtx x0 = gen_reg_rtx (mode);
26041 rtx y = gen_reg_rtx (mode);
26042 int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
26043 REAL_VALUE_TYPE dconst3_2;
26046 enum insn_code code = optab_handler (smul_optab, mode);
26047 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26049 gcc_assert (code != CODE_FOR_nothing);
26051 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26052 real_from_integer (&dconst3_2, VOIDmode, 3, 0, 0);
26053 SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
26055 halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
26057 /* x0 = rsqrt estimate */
26058 emit_insn (gen_rtx_SET (VOIDmode, x0,
26059 gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
26062 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26063 rs6000_emit_msub (y, src, halfthree, src);
26065 for (i = 0; i < passes; i++)
26067 rtx x1 = gen_reg_rtx (mode);
26068 rtx u = gen_reg_rtx (mode);
26069 rtx v = gen_reg_rtx (mode);
26071 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26072 emit_insn (gen_mul (u, x0, x0));
26073 rs6000_emit_nmsub (v, y, u, halfthree);
26074 emit_insn (gen_mul (x1, x0, v));
26078 emit_move_insn (dst, x0);
26082 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26083 (Power7) targets. DST is the target, and SRC is the argument operand. */
26086 rs6000_emit_popcount (rtx dst, rtx src)
26088 enum machine_mode mode = GET_MODE (dst);
26091 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26092 if (TARGET_POPCNTD)
26094 if (mode == SImode)
26095 emit_insn (gen_popcntdsi2 (dst, src));
26097 emit_insn (gen_popcntddi2 (dst, src));
26101 tmp1 = gen_reg_rtx (mode);
26103 if (mode == SImode)
26105 emit_insn (gen_popcntbsi2 (tmp1, src));
26106 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
26108 tmp2 = force_reg (SImode, tmp2);
26109 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
26113 emit_insn (gen_popcntbdi2 (tmp1, src));
26114 tmp2 = expand_mult (DImode, tmp1,
26115 GEN_INT ((HOST_WIDE_INT)
26116 0x01010101 << 32 | 0x01010101),
26118 tmp2 = force_reg (DImode, tmp2);
26119 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
26124 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26125 target, and SRC is the argument operand. */
26128 rs6000_emit_parity (rtx dst, rtx src)
26130 enum machine_mode mode = GET_MODE (dst);
26133 tmp = gen_reg_rtx (mode);
26135 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26138 if (mode == SImode)
26140 emit_insn (gen_popcntbsi2 (tmp, src));
26141 emit_insn (gen_paritysi2_cmpb (dst, tmp));
26145 emit_insn (gen_popcntbdi2 (tmp, src));
26146 emit_insn (gen_paritydi2_cmpb (dst, tmp));
26151 if (mode == SImode)
26153 /* Is mult+shift >= shift+xor+shift+xor? */
26154 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
26156 rtx tmp1, tmp2, tmp3, tmp4;
26158 tmp1 = gen_reg_rtx (SImode);
26159 emit_insn (gen_popcntbsi2 (tmp1, src));
26161 tmp2 = gen_reg_rtx (SImode);
26162 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
26163 tmp3 = gen_reg_rtx (SImode);
26164 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
26166 tmp4 = gen_reg_rtx (SImode);
26167 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
26168 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
26171 rs6000_emit_popcount (tmp, src);
26172 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
26176 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26177 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
26179 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
26181 tmp1 = gen_reg_rtx (DImode);
26182 emit_insn (gen_popcntbdi2 (tmp1, src));
26184 tmp2 = gen_reg_rtx (DImode);
26185 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
26186 tmp3 = gen_reg_rtx (DImode);
26187 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
26189 tmp4 = gen_reg_rtx (DImode);
26190 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
26191 tmp5 = gen_reg_rtx (DImode);
26192 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
26194 tmp6 = gen_reg_rtx (DImode);
26195 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
26196 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
26199 rs6000_emit_popcount (tmp, src);
26200 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
26204 /* Return an RTX representing where to find the function value of a
26205 function returning MODE. */
26207 rs6000_complex_function_value (enum machine_mode mode)
26209 unsigned int regno;
26211 enum machine_mode inner = GET_MODE_INNER (mode);
26212 unsigned int inner_bytes = GET_MODE_SIZE (inner);
26214 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26215 regno = FP_ARG_RETURN;
26218 regno = GP_ARG_RETURN;
26220 /* 32-bit is OK since it'll go in r3/r4. */
26221 if (TARGET_32BIT && inner_bytes >= 4)
26222 return gen_rtx_REG (mode, regno);
26225 if (inner_bytes >= 8)
26226 return gen_rtx_REG (mode, regno);
26228 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
26230 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
26231 GEN_INT (inner_bytes));
26232 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
26235 /* Target hook for TARGET_FUNCTION_VALUE.
26237 On the SPE, both FPs and vectors are returned in r3.
26239 On RS/6000 an integer value is in r3 and a floating-point value is in
26240 fp1, unless -msoft-float. */
26243 rs6000_function_value (const_tree valtype,
26244 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
26245 bool outgoing ATTRIBUTE_UNUSED)
26247 enum machine_mode mode;
26248 unsigned int regno;
26250 /* Special handling for structs in darwin64. */
26252 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
26254 CUMULATIVE_ARGS valcum;
26258 valcum.fregno = FP_ARG_MIN_REG;
26259 valcum.vregno = ALTIVEC_ARG_MIN_REG;
26260 /* Do a trial code generation as if this were going to be passed as
26261 an argument; if any part goes in memory, we return NULL. */
26262 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
26265 /* Otherwise fall through to standard ABI rules. */
26268 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
26270 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26271 return gen_rtx_PARALLEL (DImode,
26273 gen_rtx_EXPR_LIST (VOIDmode,
26274 gen_rtx_REG (SImode, GP_ARG_RETURN),
26276 gen_rtx_EXPR_LIST (VOIDmode,
26277 gen_rtx_REG (SImode,
26278 GP_ARG_RETURN + 1),
26281 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
26283 return gen_rtx_PARALLEL (DCmode,
26285 gen_rtx_EXPR_LIST (VOIDmode,
26286 gen_rtx_REG (SImode, GP_ARG_RETURN),
26288 gen_rtx_EXPR_LIST (VOIDmode,
26289 gen_rtx_REG (SImode,
26290 GP_ARG_RETURN + 1),
26292 gen_rtx_EXPR_LIST (VOIDmode,
26293 gen_rtx_REG (SImode,
26294 GP_ARG_RETURN + 2),
26296 gen_rtx_EXPR_LIST (VOIDmode,
26297 gen_rtx_REG (SImode,
26298 GP_ARG_RETURN + 3),
26302 mode = TYPE_MODE (valtype);
26303 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
26304 || POINTER_TYPE_P (valtype))
26305 mode = TARGET_32BIT ? SImode : DImode;
26307 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26308 /* _Decimal128 must use an even/odd register pair. */
26309 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26310 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
26311 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
26312 regno = FP_ARG_RETURN;
26313 else if (TREE_CODE (valtype) == COMPLEX_TYPE
26314 && targetm.calls.split_complex_arg)
26315 return rs6000_complex_function_value (mode);
26316 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26317 return register is used in both cases, and we won't see V2DImode/V2DFmode
26318 for pure altivec, combine the two cases. */
26319 else if (TREE_CODE (valtype) == VECTOR_TYPE
26320 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
26321 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
26322 regno = ALTIVEC_ARG_RETURN;
26323 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26324 && (mode == DFmode || mode == DCmode
26325 || mode == TFmode || mode == TCmode))
26326 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26328 regno = GP_ARG_RETURN;
26330 return gen_rtx_REG (mode, regno);
26333 /* Define how to find the value returned by a library function
26334 assuming the value has mode MODE. */
26336 rs6000_libcall_value (enum machine_mode mode)
26338 unsigned int regno;
26340 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
26342 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26343 return gen_rtx_PARALLEL (DImode,
26345 gen_rtx_EXPR_LIST (VOIDmode,
26346 gen_rtx_REG (SImode, GP_ARG_RETURN),
26348 gen_rtx_EXPR_LIST (VOIDmode,
26349 gen_rtx_REG (SImode,
26350 GP_ARG_RETURN + 1),
26354 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26355 /* _Decimal128 must use an even/odd register pair. */
26356 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26357 else if (SCALAR_FLOAT_MODE_P (mode)
26358 && TARGET_HARD_FLOAT && TARGET_FPRS
26359 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
26360 regno = FP_ARG_RETURN;
26361 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26362 return register is used in both cases, and we won't see V2DImode/V2DFmode
26363 for pure altivec, combine the two cases. */
26364 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
26365 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
26366 regno = ALTIVEC_ARG_RETURN;
26367 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
26368 return rs6000_complex_function_value (mode);
26369 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26370 && (mode == DFmode || mode == DCmode
26371 || mode == TFmode || mode == TCmode))
26372 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26374 regno = GP_ARG_RETURN;
26376 return gen_rtx_REG (mode, regno);
26380 /* Given FROM and TO register numbers, say whether this elimination is allowed.
26381 Frame pointer elimination is automatically handled.
26383 For the RS/6000, if frame pointer elimination is being done, we would like
26384 to convert ap into fp, not sp.
26386 We need r30 if -mminimal-toc was specified, and there are constant pool
26390 rs6000_can_eliminate (const int from, const int to)
26392 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
26393 ? ! frame_pointer_needed
26394 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
26395 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
26399 /* Define the offset between two registers, FROM to be eliminated and its
26400 replacement TO, at the start of a routine. */
26402 rs6000_initial_elimination_offset (int from, int to)
26404 rs6000_stack_t *info = rs6000_stack_info ();
26405 HOST_WIDE_INT offset;
26407 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26408 offset = info->push_p ? 0 : -info->total_size;
26409 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26411 offset = info->push_p ? 0 : -info->total_size;
26412 if (FRAME_GROWS_DOWNWARD)
26413 offset += info->fixed_size + info->vars_size + info->parm_size;
26415 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26416 offset = FRAME_GROWS_DOWNWARD
26417 ? info->fixed_size + info->vars_size + info->parm_size
26419 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26420 offset = info->total_size;
26421 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26422 offset = info->push_p ? info->total_size : 0;
26423 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
26426 gcc_unreachable ();
26432 rs6000_dwarf_register_span (rtx reg)
26436 unsigned regno = REGNO (reg);
26437 enum machine_mode mode = GET_MODE (reg);
26441 && (SPE_VECTOR_MODE (GET_MODE (reg))
26442 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
26443 && mode != SFmode && mode != SDmode && mode != SCmode)))
26448 regno = REGNO (reg);
26450 /* The duality of the SPE register size wreaks all kinds of havoc.
26451 This is a way of distinguishing r0 in 32-bits from r0 in
26453 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
26454 gcc_assert (words <= 4);
26455 for (i = 0; i < words; i++, regno++)
26457 if (BYTES_BIG_ENDIAN)
26459 parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
26460 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
26464 parts[2 * i] = gen_rtx_REG (SImode, regno);
26465 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
26469 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
26472 /* Fill in sizes for SPE register high parts in table used by unwinder. */
26475 rs6000_init_dwarf_reg_sizes_extra (tree address)
26480 enum machine_mode mode = TYPE_MODE (char_type_node);
26481 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
26482 rtx mem = gen_rtx_MEM (BLKmode, addr);
26483 rtx value = gen_int_mode (4, mode);
26485 for (i = 1201; i < 1232; i++)
26487 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
26488 HOST_WIDE_INT offset
26489 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
26491 emit_move_insn (adjust_address (mem, mode, offset), value);
26496 /* Map internal gcc register numbers to DWARF2 register numbers. */
26499 rs6000_dbx_register_number (unsigned int regno)
26501 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
26503 if (regno == MQ_REGNO)
26505 if (regno == LR_REGNO)
26507 if (regno == CTR_REGNO)
26509 if (CR_REGNO_P (regno))
26510 return regno - CR0_REGNO + 86;
26511 if (regno == CA_REGNO)
26512 return 101; /* XER */
26513 if (ALTIVEC_REGNO_P (regno))
26514 return regno - FIRST_ALTIVEC_REGNO + 1124;
26515 if (regno == VRSAVE_REGNO)
26517 if (regno == VSCR_REGNO)
26519 if (regno == SPE_ACC_REGNO)
26521 if (regno == SPEFSCR_REGNO)
26523 /* SPE high reg number. We get these values of regno from
26524 rs6000_dwarf_register_span. */
26525 gcc_assert (regno >= 1200 && regno < 1232);
26529 /* target hook eh_return_filter_mode */
26530 static enum machine_mode
26531 rs6000_eh_return_filter_mode (void)
26533 return TARGET_32BIT ? SImode : word_mode;
26536 /* Target hook for scalar_mode_supported_p. */
26538 rs6000_scalar_mode_supported_p (enum machine_mode mode)
26540 if (DECIMAL_FLOAT_MODE_P (mode))
26541 return default_decimal_float_supported_p ();
26543 return default_scalar_mode_supported_p (mode);
26546 /* Target hook for vector_mode_supported_p. */
26548 rs6000_vector_mode_supported_p (enum machine_mode mode)
26551 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
26554 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
26557 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
26564 /* Target hook for invalid_arg_for_unprototyped_fn. */
26565 static const char *
26566 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
26568 return (!rs6000_darwin64_abi
26570 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
26571 && (funcdecl == NULL_TREE
26572 || (TREE_CODE (funcdecl) == FUNCTION_DECL
26573 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
26574 ? N_("AltiVec argument passed to unprototyped function")
26578 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
26579 setup by using __stack_chk_fail_local hidden function instead of
26580 calling __stack_chk_fail directly. Otherwise it is better to call
26581 __stack_chk_fail directly. */
26583 static tree ATTRIBUTE_UNUSED
26584 rs6000_stack_protect_fail (void)
26586 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
26587 ? default_hidden_stack_protect_fail ()
26588 : default_external_stack_protect_fail ();
26592 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
26593 int num_operands ATTRIBUTE_UNUSED)
26595 if (rs6000_warn_cell_microcode)
26598 int insn_code_number = recog_memoized (insn);
26599 location_t location = locator_location (INSN_LOCATOR (insn));
26601 /* Punt on insns we cannot recognize. */
26602 if (insn_code_number < 0)
26605 temp = get_insn_template (insn_code_number, insn);
26607 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
26608 warning_at (location, OPT_mwarn_cell_microcode,
26609 "emitting microcode insn %s\t[%s] #%d",
26610 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
26611 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
26612 warning_at (location, OPT_mwarn_cell_microcode,
26613 "emitting conditional microcode insn %s\t[%s] #%d",
26614 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
26619 /* Mask options that we want to support inside of attribute((target)) and
26620 #pragma GCC target operations. Note, we do not include things like
26621 64/32-bit, endianess, hard/soft floating point, etc. that would have
26622 different calling sequences. */
26624 struct rs6000_opt_mask {
26625 const char *name; /* option name */
26626 int mask; /* mask to set */
26627 bool invert; /* invert sense of mask */
26628 bool valid_target; /* option is a target option */
26631 static struct rs6000_opt_mask const rs6000_opt_masks[] =
26633 { "altivec", MASK_ALTIVEC, false, true },
26634 { "cmpb", MASK_CMPB, false, true },
26635 { "dlmzb", MASK_DLMZB, false, true },
26636 { "fprnd", MASK_FPRND, false, true },
26637 { "hard-dfp", MASK_DFP, false, true },
26638 { "isel", MASK_ISEL, false, true },
26639 { "mfcrf", MASK_MFCRF, false, true },
26640 { "mfpgpr", MASK_MFPGPR, false, true },
26641 { "mulhw", MASK_MULHW, false, true },
26642 { "multiple", MASK_MULTIPLE, false, true },
26643 { "update", MASK_NO_UPDATE, true , true },
26644 { "popcntb", MASK_POPCNTB, false, true },
26645 { "popcntd", MASK_POPCNTD, false, true },
26646 { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true },
26647 { "powerpc-gpopt", MASK_PPC_GPOPT, false, true },
26648 { "recip-precision", MASK_RECIP_PRECISION, false, true },
26649 { "string", MASK_STRING, false, true },
26650 { "vsx", MASK_VSX, false, true },
26653 { "aix64", MASK_64BIT, false, false },
26654 { "aix32", MASK_64BIT, true, false },
26656 { "64", MASK_64BIT, false, false },
26657 { "32", MASK_64BIT, true, false },
26661 { "eabi", MASK_EABI, false, false },
26663 #ifdef MASK_LITTLE_ENDIAN
26664 { "little", MASK_LITTLE_ENDIAN, false, false },
26665 { "big", MASK_LITTLE_ENDIAN, true, false },
26667 #ifdef MASK_RELOCATABLE
26668 { "relocatable", MASK_RELOCATABLE, false, false },
26670 #ifdef MASK_STRICT_ALIGN
26671 { "strict-align", MASK_STRICT_ALIGN, false, false },
26673 { "power", MASK_POWER, false, false },
26674 { "power2", MASK_POWER2, false, false },
26675 { "powerpc", MASK_POWERPC, false, false },
26676 { "soft-float", MASK_SOFT_FLOAT, false, false },
26677 { "string", MASK_STRING, false, false },
26680 /* Builtin mask mapping for printing the flags. */
26681 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
26683 { "altivec", RS6000_BTM_ALTIVEC, false, false },
26684 { "vsx", RS6000_BTM_VSX, false, false },
26685 { "spe", RS6000_BTM_SPE, false, false },
26686 { "paired", RS6000_BTM_PAIRED, false, false },
26687 { "fre", RS6000_BTM_FRE, false, false },
26688 { "fres", RS6000_BTM_FRES, false, false },
26689 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
26690 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
26691 { "popcntd", RS6000_BTM_POPCNTD, false, false },
26692 { "powerpc", RS6000_BTM_POWERPC, false, false },
26693 { "cell", RS6000_BTM_CELL, false, false },
26696 /* Option variables that we want to support inside attribute((target)) and
26697 #pragma GCC target operations. */
26699 struct rs6000_opt_var {
26700 const char *name; /* option name */
26701 size_t global_offset; /* offset of the option in global_options. */
26702 size_t target_offset; /* offset of the option in target optiosn. */
26705 static struct rs6000_opt_var const rs6000_opt_vars[] =
26708 offsetof (struct gcc_options, x_TARGET_FRIZ),
26709 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
26710 { "avoid-indexed-addresses",
26711 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
26712 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
26714 offsetof (struct gcc_options, x_rs6000_paired_float),
26715 offsetof (struct cl_target_option, x_rs6000_paired_float), },
26717 offsetof (struct gcc_options, x_rs6000_default_long_calls),
26718 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
26721 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
26722 parsing. Return true if there were no errors. */
26725 rs6000_inner_target_options (tree args, bool attr_p)
26729 if (args == NULL_TREE)
26732 else if (TREE_CODE (args) == STRING_CST)
26734 char *p = ASTRDUP (TREE_STRING_POINTER (args));
26737 while ((q = strtok (p, ",")) != NULL)
26739 bool error_p = false;
26740 bool not_valid_p = false;
26741 const char *cpu_opt = NULL;
26744 if (strncmp (q, "cpu=", 4) == 0)
26746 int cpu_index = rs6000_cpu_name_lookup (q+4);
26747 if (cpu_index >= 0)
26748 rs6000_cpu_index = cpu_index;
26755 else if (strncmp (q, "tune=", 5) == 0)
26757 int tune_index = rs6000_cpu_name_lookup (q+5);
26758 if (tune_index >= 0)
26759 rs6000_tune_index = tune_index;
26769 bool invert = false;
26773 if (strncmp (r, "no-", 3) == 0)
26779 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
26780 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
26782 int mask = rs6000_opt_masks[i].mask;
26784 if (!rs6000_opt_masks[i].valid_target)
26785 not_valid_p = true;
26789 target_flags_explicit |= mask;
26791 if (rs6000_opt_masks[i].invert)
26795 target_flags &= ~mask;
26797 target_flags |= mask;
26802 if (error_p && !not_valid_p)
26804 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
26805 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
26807 size_t j = rs6000_opt_vars[i].global_offset;
26808 ((int *) &global_options)[j] = !invert;
26817 const char *eprefix, *esuffix;
26822 eprefix = "__attribute__((__target__(";
26827 eprefix = "#pragma GCC target ";
26832 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
26834 else if (not_valid_p)
26835 error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
26837 error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
26842 else if (TREE_CODE (args) == TREE_LIST)
26846 tree value = TREE_VALUE (args);
26849 bool ret2 = rs6000_inner_target_options (value, attr_p);
26853 args = TREE_CHAIN (args);
26855 while (args != NULL_TREE);
26859 gcc_unreachable ();
26864 /* Print out the target options as a list for -mdebug=target. */
26867 rs6000_debug_target_options (tree args, const char *prefix)
26869 if (args == NULL_TREE)
26870 fprintf (stderr, "%s<NULL>", prefix);
26872 else if (TREE_CODE (args) == STRING_CST)
26874 char *p = ASTRDUP (TREE_STRING_POINTER (args));
26877 while ((q = strtok (p, ",")) != NULL)
26880 fprintf (stderr, "%s\"%s\"", prefix, q);
26885 else if (TREE_CODE (args) == TREE_LIST)
26889 tree value = TREE_VALUE (args);
26892 rs6000_debug_target_options (value, prefix);
26895 args = TREE_CHAIN (args);
26897 while (args != NULL_TREE);
26901 gcc_unreachable ();
26907 /* Hook to validate attribute((target("..."))). */
26910 rs6000_valid_attribute_p (tree fndecl,
26911 tree ARG_UNUSED (name),
26915 struct cl_target_option cur_target;
26917 tree old_optimize = build_optimization_node ();
26918 tree new_target, new_optimize;
26919 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
26921 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
26923 if (TARGET_DEBUG_TARGET)
26925 tree tname = DECL_NAME (fndecl);
26926 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
26928 fprintf (stderr, "function: %.*s\n",
26929 (int) IDENTIFIER_LENGTH (tname),
26930 IDENTIFIER_POINTER (tname));
26932 fprintf (stderr, "function: unknown\n");
26934 fprintf (stderr, "args:");
26935 rs6000_debug_target_options (args, " ");
26936 fprintf (stderr, "\n");
26939 fprintf (stderr, "flags: 0x%x\n", flags);
26941 fprintf (stderr, "--------------------\n");
26944 old_optimize = build_optimization_node ();
26945 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
26947 /* If the function changed the optimization levels as well as setting target
26948 options, start with the optimizations specified. */
26949 if (func_optimize && func_optimize != old_optimize)
26950 cl_optimization_restore (&global_options,
26951 TREE_OPTIMIZATION (func_optimize));
26953 /* The target attributes may also change some optimization flags, so update
26954 the optimization options if necessary. */
26955 cl_target_option_save (&cur_target, &global_options);
26956 rs6000_cpu_index = rs6000_tune_index = -1;
26957 ret = rs6000_inner_target_options (args, true);
26959 /* Set up any additional state. */
26962 ret = rs6000_option_override_internal (false);
26963 new_target = build_target_option_node ();
26968 new_optimize = build_optimization_node ();
26975 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
26977 if (old_optimize != new_optimize)
26978 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
26981 cl_target_option_restore (&global_options, &cur_target);
26983 if (old_optimize != new_optimize)
26984 cl_optimization_restore (&global_options,
26985 TREE_OPTIMIZATION (old_optimize));
26991 /* Hook to validate the current #pragma GCC target and set the state, and
26992 update the macros based on what was changed. If ARGS is NULL, then
26993 POP_TARGET is used to reset the options. */
26996 rs6000_pragma_target_parse (tree args, tree pop_target)
26998 tree prev_tree = build_target_option_node ();
27000 struct cl_target_option *prev_opt, *cur_opt;
27001 unsigned prev_bumask, cur_bumask, diff_bumask;
27002 int prev_flags, cur_flags, diff_flags;
27005 if (TARGET_DEBUG_TARGET)
27007 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
27008 fprintf (stderr, "args:");
27009 rs6000_debug_target_options (args, " ");
27010 fprintf (stderr, "\n");
27014 fprintf (stderr, "pop_target:\n");
27015 debug_tree (pop_target);
27018 fprintf (stderr, "pop_target: <NULL>\n");
27020 fprintf (stderr, "--------------------\n");
27026 cur_tree = ((pop_target)
27028 : target_option_default_node);
27029 cl_target_option_restore (&global_options,
27030 TREE_TARGET_OPTION (cur_tree));
27034 rs6000_cpu_index = rs6000_tune_index = -1;
27035 ret = rs6000_inner_target_options (args, false);
27036 cur_tree = build_target_option_node ();
27040 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
27041 fprintf (stderr, "build_target_option_node returned NULL\n");
27046 target_option_current_node = cur_tree;
27048 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
27049 change the macros that are defined. */
27050 if (rs6000_target_modify_macros_ptr)
27052 prev_opt = TREE_TARGET_OPTION (prev_tree);
27053 prev_bumask = prev_opt->x_rs6000_builtin_mask;
27054 prev_flags = prev_opt->x_target_flags;
27056 cur_opt = TREE_TARGET_OPTION (cur_tree);
27057 cur_flags = cur_opt->x_target_flags;
27058 cur_bumask = cur_opt->x_rs6000_builtin_mask;
27060 diff_bumask = (prev_bumask ^ cur_bumask);
27061 diff_flags = (prev_flags ^ cur_flags);
27063 if ((diff_flags != 0) || (diff_bumask != 0))
27065 /* Delete old macros. */
27066 rs6000_target_modify_macros_ptr (false,
27067 prev_flags & diff_flags,
27068 prev_bumask & diff_bumask);
27070 /* Define new macros. */
27071 rs6000_target_modify_macros_ptr (true,
27072 cur_flags & diff_flags,
27073 cur_bumask & diff_bumask);
27081 /* Remember the last target of rs6000_set_current_function. */
27082 static GTY(()) tree rs6000_previous_fndecl;
27084 /* Establish appropriate back-end context for processing the function
27085 FNDECL. The argument might be NULL to indicate processing at top
27086 level, outside of any function scope. */
27088 rs6000_set_current_function (tree fndecl)
27090 tree old_tree = (rs6000_previous_fndecl
27091 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
27094 tree new_tree = (fndecl
27095 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
27098 if (TARGET_DEBUG_TARGET)
27100 bool print_final = false;
27101 fprintf (stderr, "\n==================== rs6000_set_current_function");
27104 fprintf (stderr, ", fndecl %s (%p)",
27105 (DECL_NAME (fndecl)
27106 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
27107 : "<unknown>"), (void *)fndecl);
27109 if (rs6000_previous_fndecl)
27110 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
27112 fprintf (stderr, "\n");
27115 fprintf (stderr, "\nnew fndecl target specific options:\n");
27116 debug_tree (new_tree);
27117 print_final = true;
27122 fprintf (stderr, "\nold fndecl target specific options:\n");
27123 debug_tree (old_tree);
27124 print_final = true;
27128 fprintf (stderr, "--------------------\n");
27131 /* Only change the context if the function changes. This hook is called
27132 several times in the course of compiling a function, and we don't want to
27133 slow things down too much or call target_reinit when it isn't safe. */
27134 if (fndecl && fndecl != rs6000_previous_fndecl)
27136 rs6000_previous_fndecl = fndecl;
27137 if (old_tree == new_tree)
27142 cl_target_option_restore (&global_options,
27143 TREE_TARGET_OPTION (new_tree));
27149 struct cl_target_option *def
27150 = TREE_TARGET_OPTION (target_option_current_node);
27152 cl_target_option_restore (&global_options, def);
27159 /* Save the current options */
27162 rs6000_function_specific_save (struct cl_target_option *ptr)
27164 ptr->rs6000_target_flags_explicit = target_flags_explicit;
27167 /* Restore the current options */
27170 rs6000_function_specific_restore (struct cl_target_option *ptr)
27172 target_flags_explicit = ptr->rs6000_target_flags_explicit;
27173 (void) rs6000_option_override_internal (false);
27176 /* Print the current options */
27179 rs6000_function_specific_print (FILE *file, int indent,
27180 struct cl_target_option *ptr)
27183 int flags = ptr->x_target_flags;
27184 unsigned bu_mask = ptr->x_rs6000_builtin_mask;
27186 /* Print the various mask options. */
27187 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27188 if ((flags & rs6000_opt_masks[i].mask) != 0)
27190 flags &= ~ rs6000_opt_masks[i].mask;
27191 fprintf (file, "%*s-m%s%s\n", indent, "",
27192 rs6000_opt_masks[i].invert ? "no-" : "",
27193 rs6000_opt_masks[i].name);
27196 /* Print the various options that are variables. */
27197 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27199 size_t j = rs6000_opt_vars[i].target_offset;
27200 if (((signed char *) ptr)[j])
27201 fprintf (file, "%*s-m%s\n", indent, "",
27202 rs6000_opt_vars[i].name);
27205 /* Print the various builtin flags. */
27206 fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask);
27207 for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++)
27208 if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0)
27210 fprintf (file, "%*s%s builtins supported\n", indent, "",
27211 rs6000_builtin_mask_names[i].name);
27216 /* Hook to determine if one function can safely inline another. */
27219 rs6000_can_inline_p (tree caller, tree callee)
27222 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
27223 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
27225 /* If callee has no option attributes, then it is ok to inline. */
27229 /* If caller has no option attributes, but callee does then it is not ok to
27231 else if (!caller_tree)
27236 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
27237 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
27239 /* Callee's options should a subset of the caller's, i.e. a vsx function
27240 can inline an altivec function but a non-vsx function can't inline a
27242 if ((caller_opts->x_target_flags & callee_opts->x_target_flags)
27243 == callee_opts->x_target_flags)
27247 if (TARGET_DEBUG_TARGET)
27248 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
27249 (DECL_NAME (caller)
27250 ? IDENTIFIER_POINTER (DECL_NAME (caller))
27252 (DECL_NAME (callee)
27253 ? IDENTIFIER_POINTER (DECL_NAME (callee))
27255 (ret ? "can" : "cannot"));
27260 /* Allocate a stack temp and fixup the address so it meets the particular
27261 memory requirements (either offetable or REG+REG addressing). */
27264 rs6000_allocate_stack_temp (enum machine_mode mode,
27265 bool offsettable_p,
27268 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
27269 rtx addr = XEXP (stack, 0);
27270 int strict_p = (reload_in_progress || reload_completed);
27272 if (!legitimate_indirect_address_p (addr, strict_p))
27275 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p))
27276 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27278 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
27279 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27285 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
27286 to such a form to deal with memory reference instructions like STFIWX that
27287 only take reg+reg addressing. */
27290 rs6000_address_for_fpconvert (rtx x)
27292 int strict_p = (reload_in_progress || reload_completed);
27295 gcc_assert (MEM_P (x));
27296 addr = XEXP (x, 0);
27297 if (! legitimate_indirect_address_p (addr, strict_p)
27298 && ! legitimate_indexed_address_p (addr, strict_p))
27300 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
27302 rtx reg = XEXP (addr, 0);
27303 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
27304 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
27305 gcc_assert (REG_P (reg));
27306 emit_insn (gen_add3_insn (reg, reg, size_rtx));
27309 else if (GET_CODE (addr) == PRE_MODIFY)
27311 rtx reg = XEXP (addr, 0);
27312 rtx expr = XEXP (addr, 1);
27313 gcc_assert (REG_P (reg));
27314 gcc_assert (GET_CODE (expr) == PLUS);
27315 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
27319 x = replace_equiv_address (x, copy_addr_to_reg (addr));
27325 /* Given a memory reference, if it is not in the form for altivec memory
27326 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
27327 convert to the altivec format. */
27330 rs6000_address_for_altivec (rtx x)
27332 gcc_assert (MEM_P (x));
27333 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
27335 rtx addr = XEXP (x, 0);
27336 int strict_p = (reload_in_progress || reload_completed);
27338 if (!legitimate_indexed_address_p (addr, strict_p)
27339 && !legitimate_indirect_address_p (addr, strict_p))
27340 addr = copy_to_mode_reg (Pmode, addr);
27342 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
27343 x = change_address (x, GET_MODE (x), addr);
27349 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
27351 On the RS/6000, all integer constants are acceptable, most won't be valid
27352 for particular insns, though. Only easy FP constants are acceptable. */
27355 rs6000_legitimate_constant_p (enum machine_mode mode, rtx x)
27357 if (rs6000_tls_referenced_p (x))
27360 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
27361 || GET_MODE (x) == VOIDmode
27362 || (TARGET_POWERPC64 && mode == DImode)
27363 || easy_fp_constant (x, mode)
27364 || easy_vector_constant (x, mode));
27368 /* A function pointer under AIX is a pointer to a data area whose first word
27369 contains the actual address of the function, whose second word contains a
27370 pointer to its TOC, and whose third word contains a value to place in the
27371 static chain register (r11). Note that if we load the static chain, our
27372 "trampoline" need not have any executable code. */
27375 rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
27381 rtx stack_toc_offset;
27383 rtx func_toc_offset;
27385 rtx func_sc_offset;
27388 rtx (*call_func) (rtx, rtx, rtx, rtx);
27389 rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
27391 stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27392 toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
27394 /* Load up address of the actual function. */
27395 func_desc = force_reg (Pmode, func_desc);
27396 func_addr = gen_reg_rtx (Pmode);
27397 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
27402 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
27403 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
27404 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
27405 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27407 call_func = gen_call_indirect_aix32bit;
27408 call_value_func = gen_call_value_indirect_aix32bit;
27412 call_func = gen_call_indirect_aix32bit_nor11;
27413 call_value_func = gen_call_value_indirect_aix32bit_nor11;
27418 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
27419 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
27420 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
27421 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27423 call_func = gen_call_indirect_aix64bit;
27424 call_value_func = gen_call_value_indirect_aix64bit;
27428 call_func = gen_call_indirect_aix64bit_nor11;
27429 call_value_func = gen_call_value_indirect_aix64bit_nor11;
27433 /* Reserved spot to store the TOC. */
27434 stack_toc_mem = gen_frame_mem (Pmode,
27435 gen_rtx_PLUS (Pmode,
27437 stack_toc_offset));
27440 gcc_assert (cfun->machine);
27442 /* Can we optimize saving the TOC in the prologue or do we need to do it at
27444 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
27445 cfun->machine->save_toc_in_prologue = true;
27449 MEM_VOLATILE_P (stack_toc_mem) = 1;
27450 emit_move_insn (stack_toc_mem, toc_reg);
27453 /* Calculate the address to load the TOC of the called function. We don't
27454 actually load this until the split after reload. */
27455 func_toc_mem = gen_rtx_MEM (Pmode,
27456 gen_rtx_PLUS (Pmode,
27460 /* If we have a static chain, load it up. */
27461 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27463 func_sc_mem = gen_rtx_MEM (Pmode,
27464 gen_rtx_PLUS (Pmode,
27468 sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
27469 emit_move_insn (sc_reg, func_sc_mem);
27472 /* Create the call. */
27474 insn = call_value_func (value, func_addr, flag, func_toc_mem,
27477 insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
27479 emit_call_insn (insn);
27482 /* Return whether we need to always update the saved TOC pointer when we update
27483 the stack pointer. */
27486 rs6000_save_toc_in_prologue_p (void)
27488 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
27491 #ifdef HAVE_GAS_HIDDEN
27492 # define USE_HIDDEN_LINKONCE 1
27494 # define USE_HIDDEN_LINKONCE 0
27497 /* Fills in the label name that should be used for a 476 link stack thunk. */
27500 get_ppc476_thunk_name (char name[32])
27502 gcc_assert (TARGET_LINK_STACK);
27504 if (USE_HIDDEN_LINKONCE)
27505 sprintf (name, "__ppc476.get_thunk");
27507 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
27510 /* This function emits the simple thunk routine that is used to preserve
27511 the link stack on the 476 cpu. */
27514 rs6000_code_end (void)
27519 if (!TARGET_LINK_STACK)
27522 get_ppc476_thunk_name (name);
27524 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
27525 build_function_type_list (void_type_node, NULL_TREE));
27526 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
27527 NULL_TREE, void_type_node);
27528 TREE_PUBLIC (decl) = 1;
27529 TREE_STATIC (decl) = 1;
27531 if (USE_HIDDEN_LINKONCE)
27533 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
27534 targetm.asm_out.unique_section (decl, 0);
27535 switch_to_section (get_named_section (decl, NULL, 0));
27536 DECL_WEAK (decl) = 1;
27537 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
27538 targetm.asm_out.globalize_label (asm_out_file, name);
27539 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
27540 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
27544 switch_to_section (text_section);
27545 ASM_OUTPUT_LABEL (asm_out_file, name);
27548 DECL_INITIAL (decl) = make_node (BLOCK);
27549 current_function_decl = decl;
27550 init_function_start (decl);
27551 first_function_block_is_cold = false;
27552 /* Make sure unwind info is emitted for the thunk if needed. */
27553 final_start_function (emit_barrier (), asm_out_file, 1);
27555 fputs ("\tblr\n", asm_out_file);
27557 final_end_function ();
27558 init_insn_lengths ();
27559 free_after_compilation (cfun);
27561 current_function_decl = NULL;
27564 struct gcc_target targetm = TARGET_INITIALIZER;
27566 #include "gt-rs6000.h"