1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 /* Always emit branch hint bits. */
142 static GTY(()) bool rs6000_always_hint;
144 /* Schedule instructions for group formation. */
145 static GTY(()) bool rs6000_sched_groups;
147 /* Support for -msched-costly-dep option. */
148 const char *rs6000_sched_costly_dep_str;
149 enum rs6000_dependence_cost rs6000_sched_costly_dep;
151 /* Support for -minsert-sched-nops option. */
152 const char *rs6000_sched_insert_nops_str;
153 enum rs6000_nop_insertion rs6000_sched_insert_nops;
155 /* Support targetm.vectorize.builtin_mask_for_load. */
156 static GTY(()) tree altivec_builtin_mask_for_load;
158 /* Size of long double. */
159 int rs6000_long_double_type_size;
161 /* IEEE quad extended precision long double. */
164 /* Whether -mabi=altivec has appeared. */
165 int rs6000_altivec_abi;
167 /* Nonzero if we want SPE ABI extensions. */
170 /* Nonzero if floating point operations are done in the GPRs. */
171 int rs6000_float_gprs = 0;
173 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
174 int rs6000_darwin64_abi;
176 /* Set to nonzero once AIX common-mode calls have been defined. */
177 static GTY(()) int common_mode_defined;
179 /* Save information from a "cmpxx" operation until the branch or scc is
181 rtx rs6000_compare_op0, rs6000_compare_op1;
182 int rs6000_compare_fp_p;
184 /* Label number of label created for -mrelocatable, to call to so we can
185 get the address of the GOT section */
186 int rs6000_pic_labelno;
189 /* Which abi to adhere to */
190 const char *rs6000_abi_name;
192 /* Semantics of the small data area */
193 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
195 /* Which small data model to use */
196 const char *rs6000_sdata_name = (char *)0;
198 /* Counter for labels which are to be placed in .fixup. */
199 int fixuplabelno = 0;
202 /* Bit size of immediate TLS offsets and string from which it is decoded. */
203 int rs6000_tls_size = 32;
204 const char *rs6000_tls_size_string;
206 /* ABI enumeration available for subtarget to use. */
207 enum rs6000_abi rs6000_current_abi;
209 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
213 const char *rs6000_debug_name;
214 int rs6000_debug_stack; /* debug stack applications */
215 int rs6000_debug_arg; /* debug argument handling */
217 /* Value is TRUE if register/mode pair is acceptable. */
218 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
220 /* Built in types. */
222 tree rs6000_builtin_types[RS6000_BTI_MAX];
223 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
225 const char *rs6000_traceback_name;
227 traceback_default = 0,
233 /* Flag to say the TOC is initialized */
235 char toc_label_name[10];
237 static GTY(()) section *read_only_data_section;
238 static GTY(()) section *private_data_section;
239 static GTY(()) section *read_only_private_data_section;
240 static GTY(()) section *sdata2_section;
241 static GTY(()) section *toc_section;
243 /* Control alignment for fields within structures. */
244 /* String from -malign-XXXXX. */
245 int rs6000_alignment_flags;
247 /* True for any options that were explicitly set. */
249 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
250 bool alignment; /* True if -malign- was used. */
251 bool abi; /* True if -mabi= was used. */
252 bool spe; /* True if -mspe= was used. */
253 bool float_gprs; /* True if -mfloat-gprs= was used. */
254 bool isel; /* True if -misel was used. */
255 bool long_double; /* True if -mlong-double- was used. */
256 } rs6000_explicit_options;
258 struct builtin_description
260 /* mask is not const because we're going to alter it below. This
261 nonsense will go away when we rewrite the -march infrastructure
262 to give us more target flag bits. */
264 const enum insn_code icode;
265 const char *const name;
266 const enum rs6000_builtins code;
269 /* Target cpu costs. */
271 struct processor_costs {
272 const int mulsi; /* cost of SImode multiplication. */
273 const int mulsi_const; /* cost of SImode multiplication by constant. */
274 const int mulsi_const9; /* cost of SImode mult by short constant. */
275 const int muldi; /* cost of DImode multiplication. */
276 const int divsi; /* cost of SImode division. */
277 const int divdi; /* cost of DImode division. */
278 const int fp; /* cost of simple SFmode and DFmode insns. */
279 const int dmul; /* cost of DFmode multiplication (and fmadd). */
280 const int sdiv; /* cost of SFmode division (fdivs). */
281 const int ddiv; /* cost of DFmode division (fdiv). */
284 const struct processor_costs *rs6000_cost;
286 /* Processor costs (relative to an add) */
288 /* Instruction size costs on 32bit processors. */
290 struct processor_costs size32_cost = {
291 COSTS_N_INSNS (1), /* mulsi */
292 COSTS_N_INSNS (1), /* mulsi_const */
293 COSTS_N_INSNS (1), /* mulsi_const9 */
294 COSTS_N_INSNS (1), /* muldi */
295 COSTS_N_INSNS (1), /* divsi */
296 COSTS_N_INSNS (1), /* divdi */
297 COSTS_N_INSNS (1), /* fp */
298 COSTS_N_INSNS (1), /* dmul */
299 COSTS_N_INSNS (1), /* sdiv */
300 COSTS_N_INSNS (1), /* ddiv */
303 /* Instruction size costs on 64bit processors. */
305 struct processor_costs size64_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
318 /* Instruction costs on RIOS1 processors. */
320 struct processor_costs rios1_cost = {
321 COSTS_N_INSNS (5), /* mulsi */
322 COSTS_N_INSNS (4), /* mulsi_const */
323 COSTS_N_INSNS (3), /* mulsi_const9 */
324 COSTS_N_INSNS (5), /* muldi */
325 COSTS_N_INSNS (19), /* divsi */
326 COSTS_N_INSNS (19), /* divdi */
327 COSTS_N_INSNS (2), /* fp */
328 COSTS_N_INSNS (2), /* dmul */
329 COSTS_N_INSNS (19), /* sdiv */
330 COSTS_N_INSNS (19), /* ddiv */
333 /* Instruction costs on RIOS2 processors. */
335 struct processor_costs rios2_cost = {
336 COSTS_N_INSNS (2), /* mulsi */
337 COSTS_N_INSNS (2), /* mulsi_const */
338 COSTS_N_INSNS (2), /* mulsi_const9 */
339 COSTS_N_INSNS (2), /* muldi */
340 COSTS_N_INSNS (13), /* divsi */
341 COSTS_N_INSNS (13), /* divdi */
342 COSTS_N_INSNS (2), /* fp */
343 COSTS_N_INSNS (2), /* dmul */
344 COSTS_N_INSNS (17), /* sdiv */
345 COSTS_N_INSNS (17), /* ddiv */
348 /* Instruction costs on RS64A processors. */
350 struct processor_costs rs64a_cost = {
351 COSTS_N_INSNS (20), /* mulsi */
352 COSTS_N_INSNS (12), /* mulsi_const */
353 COSTS_N_INSNS (8), /* mulsi_const9 */
354 COSTS_N_INSNS (34), /* muldi */
355 COSTS_N_INSNS (65), /* divsi */
356 COSTS_N_INSNS (67), /* divdi */
357 COSTS_N_INSNS (4), /* fp */
358 COSTS_N_INSNS (4), /* dmul */
359 COSTS_N_INSNS (31), /* sdiv */
360 COSTS_N_INSNS (31), /* ddiv */
363 /* Instruction costs on MPCCORE processors. */
365 struct processor_costs mpccore_cost = {
366 COSTS_N_INSNS (2), /* mulsi */
367 COSTS_N_INSNS (2), /* mulsi_const */
368 COSTS_N_INSNS (2), /* mulsi_const9 */
369 COSTS_N_INSNS (2), /* muldi */
370 COSTS_N_INSNS (6), /* divsi */
371 COSTS_N_INSNS (6), /* divdi */
372 COSTS_N_INSNS (4), /* fp */
373 COSTS_N_INSNS (5), /* dmul */
374 COSTS_N_INSNS (10), /* sdiv */
375 COSTS_N_INSNS (17), /* ddiv */
378 /* Instruction costs on PPC403 processors. */
380 struct processor_costs ppc403_cost = {
381 COSTS_N_INSNS (4), /* mulsi */
382 COSTS_N_INSNS (4), /* mulsi_const */
383 COSTS_N_INSNS (4), /* mulsi_const9 */
384 COSTS_N_INSNS (4), /* muldi */
385 COSTS_N_INSNS (33), /* divsi */
386 COSTS_N_INSNS (33), /* divdi */
387 COSTS_N_INSNS (11), /* fp */
388 COSTS_N_INSNS (11), /* dmul */
389 COSTS_N_INSNS (11), /* sdiv */
390 COSTS_N_INSNS (11), /* ddiv */
393 /* Instruction costs on PPC405 processors. */
395 struct processor_costs ppc405_cost = {
396 COSTS_N_INSNS (5), /* mulsi */
397 COSTS_N_INSNS (4), /* mulsi_const */
398 COSTS_N_INSNS (3), /* mulsi_const9 */
399 COSTS_N_INSNS (5), /* muldi */
400 COSTS_N_INSNS (35), /* divsi */
401 COSTS_N_INSNS (35), /* divdi */
402 COSTS_N_INSNS (11), /* fp */
403 COSTS_N_INSNS (11), /* dmul */
404 COSTS_N_INSNS (11), /* sdiv */
405 COSTS_N_INSNS (11), /* ddiv */
408 /* Instruction costs on PPC440 processors. */
410 struct processor_costs ppc440_cost = {
411 COSTS_N_INSNS (3), /* mulsi */
412 COSTS_N_INSNS (2), /* mulsi_const */
413 COSTS_N_INSNS (2), /* mulsi_const9 */
414 COSTS_N_INSNS (3), /* muldi */
415 COSTS_N_INSNS (34), /* divsi */
416 COSTS_N_INSNS (34), /* divdi */
417 COSTS_N_INSNS (5), /* fp */
418 COSTS_N_INSNS (5), /* dmul */
419 COSTS_N_INSNS (19), /* sdiv */
420 COSTS_N_INSNS (33), /* ddiv */
423 /* Instruction costs on PPC601 processors. */
425 struct processor_costs ppc601_cost = {
426 COSTS_N_INSNS (5), /* mulsi */
427 COSTS_N_INSNS (5), /* mulsi_const */
428 COSTS_N_INSNS (5), /* mulsi_const9 */
429 COSTS_N_INSNS (5), /* muldi */
430 COSTS_N_INSNS (36), /* divsi */
431 COSTS_N_INSNS (36), /* divdi */
432 COSTS_N_INSNS (4), /* fp */
433 COSTS_N_INSNS (5), /* dmul */
434 COSTS_N_INSNS (17), /* sdiv */
435 COSTS_N_INSNS (31), /* ddiv */
438 /* Instruction costs on PPC603 processors. */
440 struct processor_costs ppc603_cost = {
441 COSTS_N_INSNS (5), /* mulsi */
442 COSTS_N_INSNS (3), /* mulsi_const */
443 COSTS_N_INSNS (2), /* mulsi_const9 */
444 COSTS_N_INSNS (5), /* muldi */
445 COSTS_N_INSNS (37), /* divsi */
446 COSTS_N_INSNS (37), /* divdi */
447 COSTS_N_INSNS (3), /* fp */
448 COSTS_N_INSNS (4), /* dmul */
449 COSTS_N_INSNS (18), /* sdiv */
450 COSTS_N_INSNS (33), /* ddiv */
453 /* Instruction costs on PPC604 processors. */
455 struct processor_costs ppc604_cost = {
456 COSTS_N_INSNS (4), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (4), /* mulsi_const9 */
459 COSTS_N_INSNS (4), /* muldi */
460 COSTS_N_INSNS (20), /* divsi */
461 COSTS_N_INSNS (20), /* divdi */
462 COSTS_N_INSNS (3), /* fp */
463 COSTS_N_INSNS (3), /* dmul */
464 COSTS_N_INSNS (18), /* sdiv */
465 COSTS_N_INSNS (32), /* ddiv */
468 /* Instruction costs on PPC604e processors. */
470 struct processor_costs ppc604e_cost = {
471 COSTS_N_INSNS (2), /* mulsi */
472 COSTS_N_INSNS (2), /* mulsi_const */
473 COSTS_N_INSNS (2), /* mulsi_const9 */
474 COSTS_N_INSNS (2), /* muldi */
475 COSTS_N_INSNS (20), /* divsi */
476 COSTS_N_INSNS (20), /* divdi */
477 COSTS_N_INSNS (3), /* fp */
478 COSTS_N_INSNS (3), /* dmul */
479 COSTS_N_INSNS (18), /* sdiv */
480 COSTS_N_INSNS (32), /* ddiv */
483 /* Instruction costs on PPC620 processors. */
485 struct processor_costs ppc620_cost = {
486 COSTS_N_INSNS (5), /* mulsi */
487 COSTS_N_INSNS (4), /* mulsi_const */
488 COSTS_N_INSNS (3), /* mulsi_const9 */
489 COSTS_N_INSNS (7), /* muldi */
490 COSTS_N_INSNS (21), /* divsi */
491 COSTS_N_INSNS (37), /* divdi */
492 COSTS_N_INSNS (3), /* fp */
493 COSTS_N_INSNS (3), /* dmul */
494 COSTS_N_INSNS (18), /* sdiv */
495 COSTS_N_INSNS (32), /* ddiv */
498 /* Instruction costs on PPC630 processors. */
500 struct processor_costs ppc630_cost = {
501 COSTS_N_INSNS (5), /* mulsi */
502 COSTS_N_INSNS (4), /* mulsi_const */
503 COSTS_N_INSNS (3), /* mulsi_const9 */
504 COSTS_N_INSNS (7), /* muldi */
505 COSTS_N_INSNS (21), /* divsi */
506 COSTS_N_INSNS (37), /* divdi */
507 COSTS_N_INSNS (3), /* fp */
508 COSTS_N_INSNS (3), /* dmul */
509 COSTS_N_INSNS (17), /* sdiv */
510 COSTS_N_INSNS (21), /* ddiv */
513 /* Instruction costs on PPC750 and PPC7400 processors. */
515 struct processor_costs ppc750_cost = {
516 COSTS_N_INSNS (5), /* mulsi */
517 COSTS_N_INSNS (3), /* mulsi_const */
518 COSTS_N_INSNS (2), /* mulsi_const9 */
519 COSTS_N_INSNS (5), /* muldi */
520 COSTS_N_INSNS (17), /* divsi */
521 COSTS_N_INSNS (17), /* divdi */
522 COSTS_N_INSNS (3), /* fp */
523 COSTS_N_INSNS (3), /* dmul */
524 COSTS_N_INSNS (17), /* sdiv */
525 COSTS_N_INSNS (31), /* ddiv */
528 /* Instruction costs on PPC7450 processors. */
530 struct processor_costs ppc7450_cost = {
531 COSTS_N_INSNS (4), /* mulsi */
532 COSTS_N_INSNS (3), /* mulsi_const */
533 COSTS_N_INSNS (3), /* mulsi_const9 */
534 COSTS_N_INSNS (4), /* muldi */
535 COSTS_N_INSNS (23), /* divsi */
536 COSTS_N_INSNS (23), /* divdi */
537 COSTS_N_INSNS (5), /* fp */
538 COSTS_N_INSNS (5), /* dmul */
539 COSTS_N_INSNS (21), /* sdiv */
540 COSTS_N_INSNS (35), /* ddiv */
543 /* Instruction costs on PPC8540 processors. */
545 struct processor_costs ppc8540_cost = {
546 COSTS_N_INSNS (4), /* mulsi */
547 COSTS_N_INSNS (4), /* mulsi_const */
548 COSTS_N_INSNS (4), /* mulsi_const9 */
549 COSTS_N_INSNS (4), /* muldi */
550 COSTS_N_INSNS (19), /* divsi */
551 COSTS_N_INSNS (19), /* divdi */
552 COSTS_N_INSNS (4), /* fp */
553 COSTS_N_INSNS (4), /* dmul */
554 COSTS_N_INSNS (29), /* sdiv */
555 COSTS_N_INSNS (29), /* ddiv */
558 /* Instruction costs on POWER4 and POWER5 processors. */
560 struct processor_costs power4_cost = {
561 COSTS_N_INSNS (3), /* mulsi */
562 COSTS_N_INSNS (2), /* mulsi_const */
563 COSTS_N_INSNS (2), /* mulsi_const9 */
564 COSTS_N_INSNS (4), /* muldi */
565 COSTS_N_INSNS (18), /* divsi */
566 COSTS_N_INSNS (34), /* divdi */
567 COSTS_N_INSNS (3), /* fp */
568 COSTS_N_INSNS (3), /* dmul */
569 COSTS_N_INSNS (17), /* sdiv */
570 COSTS_N_INSNS (17), /* ddiv */
574 static bool rs6000_function_ok_for_sibcall (tree, tree);
575 static const char *rs6000_invalid_within_doloop (rtx);
576 static rtx rs6000_generate_compare (enum rtx_code);
577 static void rs6000_maybe_dead (rtx);
578 static void rs6000_emit_stack_tie (void);
579 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
580 static rtx spe_synthesize_frame_save (rtx);
581 static bool spe_func_has_64bit_regs_p (void);
582 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
584 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
585 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
586 static unsigned rs6000_hash_constant (rtx);
587 static unsigned toc_hash_function (const void *);
588 static int toc_hash_eq (const void *, const void *);
589 static int constant_pool_expr_1 (rtx, int *, int *);
590 static bool constant_pool_expr_p (rtx);
591 static bool legitimate_indexed_address_p (rtx, int);
592 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
593 static struct machine_function * rs6000_init_machine_status (void);
594 static bool rs6000_assemble_integer (rtx, unsigned int, int);
595 static bool no_global_regs_above (int);
596 #ifdef HAVE_GAS_HIDDEN
597 static void rs6000_assemble_visibility (tree, int);
599 static int rs6000_ra_ever_killed (void);
600 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
601 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
602 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
603 static const char *rs6000_mangle_fundamental_type (tree);
604 extern const struct attribute_spec rs6000_attribute_table[];
605 static void rs6000_set_default_type_attributes (tree);
606 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
607 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
608 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
610 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
611 static bool rs6000_return_in_memory (tree, tree);
612 static void rs6000_file_start (void);
614 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
615 static void rs6000_elf_asm_out_constructor (rtx, int);
616 static void rs6000_elf_asm_out_destructor (rtx, int);
617 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
618 static void rs6000_elf_asm_init_sections (void);
619 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
620 static void rs6000_elf_unique_section (tree, int);
621 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
622 unsigned HOST_WIDE_INT);
623 static void rs6000_elf_encode_section_info (tree, rtx, int)
626 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
628 static void rs6000_xcoff_asm_output_anchor (rtx);
629 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
630 static void rs6000_xcoff_asm_init_sections (void);
631 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
632 static section *rs6000_xcoff_select_section (tree, int,
633 unsigned HOST_WIDE_INT);
634 static void rs6000_xcoff_unique_section (tree, int);
635 static section *rs6000_xcoff_select_rtx_section
636 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
637 static const char * rs6000_xcoff_strip_name_encoding (const char *);
638 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
639 static void rs6000_xcoff_file_start (void);
640 static void rs6000_xcoff_file_end (void);
642 static int rs6000_variable_issue (FILE *, int, rtx, int);
643 static bool rs6000_rtx_costs (rtx, int, int, int *);
644 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
645 static bool is_microcoded_insn (rtx);
646 static int is_dispatch_slot_restricted (rtx);
647 static bool is_cracked_insn (rtx);
648 static bool is_branch_slot_insn (rtx);
649 static int rs6000_adjust_priority (rtx, int);
650 static int rs6000_issue_rate (void);
651 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
652 static rtx get_next_active_insn (rtx, rtx);
653 static bool insn_terminates_group_p (rtx , enum group_termination);
654 static bool is_costly_group (rtx *, rtx);
655 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
656 static int redefine_groups (FILE *, int, rtx, rtx);
657 static int pad_groups (FILE *, int, rtx, rtx);
658 static void rs6000_sched_finish (FILE *, int);
659 static int rs6000_use_sched_lookahead (void);
660 static tree rs6000_builtin_mask_for_load (void);
662 static void def_builtin (int, const char *, tree, int);
663 static void rs6000_init_builtins (void);
664 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
665 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
666 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
667 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
668 static void altivec_init_builtins (void);
669 static void rs6000_common_init_builtins (void);
670 static void rs6000_init_libfuncs (void);
672 static void enable_mask_for_builtins (struct builtin_description *, int,
673 enum rs6000_builtins,
674 enum rs6000_builtins);
675 static tree build_opaque_vector_type (tree, int);
676 static void spe_init_builtins (void);
677 static rtx spe_expand_builtin (tree, rtx, bool *);
678 static rtx spe_expand_stv_builtin (enum insn_code, tree);
679 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
680 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
681 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
682 static rs6000_stack_t *rs6000_stack_info (void);
683 static void debug_stack_info (rs6000_stack_t *);
685 static rtx altivec_expand_builtin (tree, rtx, bool *);
686 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
687 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
688 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
689 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
690 static rtx altivec_expand_predicate_builtin (enum insn_code,
691 const char *, tree, rtx);
692 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
693 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
694 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
695 static rtx altivec_expand_vec_set_builtin (tree);
696 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
697 static int get_element_number (tree, tree);
698 static bool rs6000_handle_option (size_t, const char *, int);
699 static void rs6000_parse_tls_size_option (void);
700 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
701 static int first_altivec_reg_to_save (void);
702 static unsigned int compute_vrsave_mask (void);
703 static void compute_save_world_info (rs6000_stack_t *info_ptr);
704 static void is_altivec_return_reg (rtx, void *);
705 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
706 int easy_vector_constant (rtx, enum machine_mode);
707 static bool rs6000_is_opaque_type (tree);
708 static rtx rs6000_dwarf_register_span (rtx);
709 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
710 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
711 static rtx rs6000_tls_get_addr (void);
712 static rtx rs6000_got_sym (void);
713 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
714 static const char *rs6000_get_some_local_dynamic_name (void);
715 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
716 static rtx rs6000_complex_function_value (enum machine_mode);
717 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
718 enum machine_mode, tree);
719 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
721 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
722 tree, HOST_WIDE_INT);
723 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
726 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
729 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
730 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
731 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
732 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
733 enum machine_mode, tree,
735 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
737 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
739 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
741 static void macho_branch_islands (void);
742 static void add_compiler_branch_island (tree, tree, int);
743 static int no_previous_def (tree function_name);
744 static tree get_prev_label (tree function_name);
745 static void rs6000_darwin_file_start (void);
748 static tree rs6000_build_builtin_va_list (void);
749 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
750 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
751 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
752 static bool rs6000_vector_mode_supported_p (enum machine_mode);
753 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
755 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
757 static int get_vsel_insn (enum machine_mode);
758 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
759 static tree rs6000_stack_protect_fail (void);
761 const int INSN_NOT_AVAILABLE = -1;
762 static enum machine_mode rs6000_eh_return_filter_mode (void);
764 /* Hash table stuff for keeping track of TOC entries. */
766 struct toc_hash_struct GTY(())
768 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
769 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
771 enum machine_mode key_mode;
775 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
777 /* Default register names. */
778 char rs6000_reg_names[][8] =
780 "0", "1", "2", "3", "4", "5", "6", "7",
781 "8", "9", "10", "11", "12", "13", "14", "15",
782 "16", "17", "18", "19", "20", "21", "22", "23",
783 "24", "25", "26", "27", "28", "29", "30", "31",
784 "0", "1", "2", "3", "4", "5", "6", "7",
785 "8", "9", "10", "11", "12", "13", "14", "15",
786 "16", "17", "18", "19", "20", "21", "22", "23",
787 "24", "25", "26", "27", "28", "29", "30", "31",
788 "mq", "lr", "ctr","ap",
789 "0", "1", "2", "3", "4", "5", "6", "7",
791 /* AltiVec registers. */
792 "0", "1", "2", "3", "4", "5", "6", "7",
793 "8", "9", "10", "11", "12", "13", "14", "15",
794 "16", "17", "18", "19", "20", "21", "22", "23",
795 "24", "25", "26", "27", "28", "29", "30", "31",
798 "spe_acc", "spefscr",
799 /* Soft frame pointer. */
803 #ifdef TARGET_REGNAMES
804 static const char alt_reg_names[][8] =
806 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
807 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
808 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
809 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
810 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
811 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
812 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
813 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
814 "mq", "lr", "ctr", "ap",
815 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
817 /* AltiVec registers. */
818 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
819 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
820 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
821 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
824 "spe_acc", "spefscr",
825 /* Soft frame pointer. */
830 #ifndef MASK_STRICT_ALIGN
831 #define MASK_STRICT_ALIGN 0
833 #ifndef TARGET_PROFILE_KERNEL
834 #define TARGET_PROFILE_KERNEL 0
837 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
838 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
840 /* Initialize the GCC target structure. */
841 #undef TARGET_ATTRIBUTE_TABLE
842 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
843 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
844 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
846 #undef TARGET_ASM_ALIGNED_DI_OP
847 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
849 /* Default unaligned ops are only provided for ELF. Find the ops needed
850 for non-ELF systems. */
851 #ifndef OBJECT_FORMAT_ELF
853 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
855 #undef TARGET_ASM_UNALIGNED_HI_OP
856 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
857 #undef TARGET_ASM_UNALIGNED_SI_OP
858 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
859 #undef TARGET_ASM_UNALIGNED_DI_OP
860 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
863 #undef TARGET_ASM_UNALIGNED_HI_OP
864 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
865 #undef TARGET_ASM_UNALIGNED_SI_OP
866 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
867 #undef TARGET_ASM_UNALIGNED_DI_OP
868 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
869 #undef TARGET_ASM_ALIGNED_DI_OP
870 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
874 /* This hook deals with fixups for relocatable code and DI-mode objects
876 #undef TARGET_ASM_INTEGER
877 #define TARGET_ASM_INTEGER rs6000_assemble_integer
879 #ifdef HAVE_GAS_HIDDEN
880 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
881 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
884 #undef TARGET_HAVE_TLS
885 #define TARGET_HAVE_TLS HAVE_AS_TLS
887 #undef TARGET_CANNOT_FORCE_CONST_MEM
888 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
890 #undef TARGET_ASM_FUNCTION_PROLOGUE
891 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
892 #undef TARGET_ASM_FUNCTION_EPILOGUE
893 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
895 #undef TARGET_SCHED_VARIABLE_ISSUE
896 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
898 #undef TARGET_SCHED_ISSUE_RATE
899 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
900 #undef TARGET_SCHED_ADJUST_COST
901 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
902 #undef TARGET_SCHED_ADJUST_PRIORITY
903 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
904 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
905 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
906 #undef TARGET_SCHED_FINISH
907 #define TARGET_SCHED_FINISH rs6000_sched_finish
909 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
910 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
912 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
913 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
915 #undef TARGET_INIT_BUILTINS
916 #define TARGET_INIT_BUILTINS rs6000_init_builtins
918 #undef TARGET_EXPAND_BUILTIN
919 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
921 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
922 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
924 #undef TARGET_INIT_LIBFUNCS
925 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
928 #undef TARGET_BINDS_LOCAL_P
929 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
932 #undef TARGET_ASM_OUTPUT_MI_THUNK
933 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
935 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
936 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
938 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
939 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
941 #undef TARGET_INVALID_WITHIN_DOLOOP
942 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
944 #undef TARGET_RTX_COSTS
945 #define TARGET_RTX_COSTS rs6000_rtx_costs
946 #undef TARGET_ADDRESS_COST
947 #define TARGET_ADDRESS_COST hook_int_rtx_0
949 #undef TARGET_VECTOR_OPAQUE_P
950 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
952 #undef TARGET_DWARF_REGISTER_SPAN
953 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
955 /* On rs6000, function arguments are promoted, as are function return
957 #undef TARGET_PROMOTE_FUNCTION_ARGS
958 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
959 #undef TARGET_PROMOTE_FUNCTION_RETURN
960 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
962 #undef TARGET_RETURN_IN_MEMORY
963 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
965 #undef TARGET_SETUP_INCOMING_VARARGS
966 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
968 /* Always strict argument naming on rs6000. */
969 #undef TARGET_STRICT_ARGUMENT_NAMING
970 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
971 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
972 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
973 #undef TARGET_SPLIT_COMPLEX_ARG
974 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
975 #undef TARGET_MUST_PASS_IN_STACK
976 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
977 #undef TARGET_PASS_BY_REFERENCE
978 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
979 #undef TARGET_ARG_PARTIAL_BYTES
980 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
982 #undef TARGET_BUILD_BUILTIN_VA_LIST
983 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
985 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
986 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
988 #undef TARGET_EH_RETURN_FILTER_MODE
989 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
991 #undef TARGET_SCALAR_MODE_SUPPORTED_P
992 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
994 #undef TARGET_VECTOR_MODE_SUPPORTED_P
995 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
997 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
998 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1000 #undef TARGET_HANDLE_OPTION
1001 #define TARGET_HANDLE_OPTION rs6000_handle_option
1003 #undef TARGET_DEFAULT_TARGET_FLAGS
1004 #define TARGET_DEFAULT_TARGET_FLAGS \
1007 #undef TARGET_STACK_PROTECT_FAIL
1008 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1010 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1011 The PowerPC architecture requires only weak consistency among
1012 processors--that is, memory accesses between processors need not be
1013 sequentially consistent and memory accesses among processors can occur
1014 in any order. The ability to order memory accesses weakly provides
1015 opportunities for more efficient use of the system bus. Unless a
1016 dependency exists, the 604e allows read operations to precede store
1018 #undef TARGET_RELAXED_ORDERING
1019 #define TARGET_RELAXED_ORDERING true
1022 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1023 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1026 /* Use a 32-bit anchor range. This leads to sequences like:
1028 addis tmp,anchor,high
1031 where tmp itself acts as an anchor, and can be shared between
1032 accesses to the same 64k page. */
1033 #undef TARGET_MIN_ANCHOR_OFFSET
1034 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1035 #undef TARGET_MAX_ANCHOR_OFFSET
1036 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1037 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1038 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1040 struct gcc_target targetm = TARGET_INITIALIZER;
1043 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1046 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1048 /* The GPRs can hold any mode, but values bigger than one register
1049 cannot go past R31. */
1050 if (INT_REGNO_P (regno))
1051 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1053 /* The float registers can only hold floating modes and DImode.
1054 This also excludes decimal float modes. */
1055 if (FP_REGNO_P (regno))
1057 (SCALAR_FLOAT_MODE_P (mode)
1058 && !DECIMAL_FLOAT_MODE_P (mode)
1059 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1060 || (GET_MODE_CLASS (mode) == MODE_INT
1061 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1063 /* The CR register can only hold CC modes. */
1064 if (CR_REGNO_P (regno))
1065 return GET_MODE_CLASS (mode) == MODE_CC;
1067 if (XER_REGNO_P (regno))
1068 return mode == PSImode;
1070 /* AltiVec only in AldyVec registers. */
1071 if (ALTIVEC_REGNO_P (regno))
1072 return ALTIVEC_VECTOR_MODE (mode);
1074 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1075 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1078 /* We cannot put TImode anywhere except general register and it must be
1079 able to fit within the register set. */
1081 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1084 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1086 rs6000_init_hard_regno_mode_ok (void)
1090 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1091 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1092 if (rs6000_hard_regno_mode_ok (r, m))
1093 rs6000_hard_regno_mode_ok_p[m][r] = true;
1096 /* If not otherwise specified by a target, make 'long double' equivalent to
1099 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1100 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1103 /* Override command line options. Mostly we process the processor
1104 type and sometimes adjust other TARGET_ options. */
1107 rs6000_override_options (const char *default_cpu)
1110 struct rs6000_cpu_select *ptr;
1113 /* Simplifications for entries below. */
1116 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1117 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1120 /* This table occasionally claims that a processor does not support
1121 a particular feature even though it does, but the feature is slower
1122 than the alternative. Thus, it shouldn't be relied on as a
1123 complete description of the processor's support.
1125 Please keep this list in order, and don't forget to update the
1126 documentation in invoke.texi when adding a new processor or
1130 const char *const name; /* Canonical processor name. */
1131 const enum processor_type processor; /* Processor type enum value. */
1132 const int target_enable; /* Target flags to enable. */
1133 } const processor_target_table[]
1134 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1135 {"403", PROCESSOR_PPC403,
1136 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1137 {"405", PROCESSOR_PPC405,
1138 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1139 {"405fp", PROCESSOR_PPC405,
1140 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1141 {"440", PROCESSOR_PPC440,
1142 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1143 {"440fp", PROCESSOR_PPC440,
1144 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1145 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1146 {"601", PROCESSOR_PPC601,
1147 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1148 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1150 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1151 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1152 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1153 {"620", PROCESSOR_PPC620,
1154 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1155 {"630", PROCESSOR_PPC630,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1158 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1159 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1160 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1161 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1162 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1163 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1164 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1165 /* 8548 has a dummy entry for now. */
1166 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1167 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1168 {"970", PROCESSOR_POWER4,
1169 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1170 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1171 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1172 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1173 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1174 {"G5", PROCESSOR_POWER4,
1175 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1176 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1177 {"power2", PROCESSOR_POWER,
1178 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1179 {"power3", PROCESSOR_PPC630,
1180 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1181 {"power4", PROCESSOR_POWER4,
1182 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1183 {"power5", PROCESSOR_POWER5,
1184 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1185 | MASK_MFCRF | MASK_POPCNTB},
1186 {"power5+", PROCESSOR_POWER5,
1187 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1188 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1189 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1190 {"powerpc64", PROCESSOR_POWERPC64,
1191 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1192 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1193 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1194 {"rios2", PROCESSOR_RIOS2,
1195 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1196 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1197 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1198 {"rs64", PROCESSOR_RS64A,
1199 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1202 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1204 /* Some OSs don't support saving the high part of 64-bit registers on
1205 context switch. Other OSs don't support saving Altivec registers.
1206 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1207 settings; if the user wants either, the user must explicitly specify
1208 them and we won't interfere with the user's specification. */
1211 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1212 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1213 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1214 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1218 rs6000_init_hard_regno_mode_ok ();
1220 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1221 #ifdef OS_MISSING_POWERPC64
1222 if (OS_MISSING_POWERPC64)
1223 set_masks &= ~MASK_POWERPC64;
1225 #ifdef OS_MISSING_ALTIVEC
1226 if (OS_MISSING_ALTIVEC)
1227 set_masks &= ~MASK_ALTIVEC;
1230 /* Don't override by the processor default if given explicitly. */
1231 set_masks &= ~target_flags_explicit;
1233 /* Identify the processor type. */
1234 rs6000_select[0].string = default_cpu;
1235 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1237 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1239 ptr = &rs6000_select[i];
1240 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1242 for (j = 0; j < ptt_size; j++)
1243 if (! strcmp (ptr->string, processor_target_table[j].name))
1245 if (ptr->set_tune_p)
1246 rs6000_cpu = processor_target_table[j].processor;
1248 if (ptr->set_arch_p)
1250 target_flags &= ~set_masks;
1251 target_flags |= (processor_target_table[j].target_enable
1258 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1265 /* If we are optimizing big endian systems for space, use the load/store
1266 multiple and string instructions. */
1267 if (BYTES_BIG_ENDIAN && optimize_size)
1268 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1270 /* Don't allow -mmultiple or -mstring on little endian systems
1271 unless the cpu is a 750, because the hardware doesn't support the
1272 instructions used in little endian mode, and causes an alignment
1273 trap. The 750 does not cause an alignment trap (except when the
1274 target is unaligned). */
1276 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1278 if (TARGET_MULTIPLE)
1280 target_flags &= ~MASK_MULTIPLE;
1281 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1282 warning (0, "-mmultiple is not supported on little endian systems");
1287 target_flags &= ~MASK_STRING;
1288 if ((target_flags_explicit & MASK_STRING) != 0)
1289 warning (0, "-mstring is not supported on little endian systems");
1293 /* Set debug flags */
1294 if (rs6000_debug_name)
1296 if (! strcmp (rs6000_debug_name, "all"))
1297 rs6000_debug_stack = rs6000_debug_arg = 1;
1298 else if (! strcmp (rs6000_debug_name, "stack"))
1299 rs6000_debug_stack = 1;
1300 else if (! strcmp (rs6000_debug_name, "arg"))
1301 rs6000_debug_arg = 1;
1303 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1306 if (rs6000_traceback_name)
1308 if (! strncmp (rs6000_traceback_name, "full", 4))
1309 rs6000_traceback = traceback_full;
1310 else if (! strncmp (rs6000_traceback_name, "part", 4))
1311 rs6000_traceback = traceback_part;
1312 else if (! strncmp (rs6000_traceback_name, "no", 2))
1313 rs6000_traceback = traceback_none;
1315 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1316 rs6000_traceback_name);
1319 if (!rs6000_explicit_options.long_double)
1320 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1322 #ifndef POWERPC_LINUX
1323 if (!rs6000_explicit_options.abi)
1324 rs6000_ieeequad = 1;
1327 /* Set Altivec ABI as default for powerpc64 linux. */
1328 if (TARGET_ELF && TARGET_64BIT)
1330 rs6000_altivec_abi = 1;
1331 TARGET_ALTIVEC_VRSAVE = 1;
1334 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1335 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1337 rs6000_darwin64_abi = 1;
1339 darwin_one_byte_bool = 1;
1341 /* Default to natural alignment, for better performance. */
1342 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1345 /* Handle -mtls-size option. */
1346 rs6000_parse_tls_size_option ();
1348 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1349 SUBTARGET_OVERRIDE_OPTIONS;
1351 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1352 SUBSUBTARGET_OVERRIDE_OPTIONS;
1354 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1355 SUB3TARGET_OVERRIDE_OPTIONS;
1361 error ("AltiVec and E500 instructions cannot coexist");
1363 /* The e500 does not have string instructions, and we set
1364 MASK_STRING above when optimizing for size. */
1365 if ((target_flags & MASK_STRING) != 0)
1366 target_flags = target_flags & ~MASK_STRING;
1368 else if (rs6000_select[1].string != NULL)
1370 /* For the powerpc-eabispe configuration, we set all these by
1371 default, so let's unset them if we manually set another
1372 CPU that is not the E500. */
1373 if (!rs6000_explicit_options.abi)
1375 if (!rs6000_explicit_options.spe)
1377 if (!rs6000_explicit_options.float_gprs)
1378 rs6000_float_gprs = 0;
1379 if (!rs6000_explicit_options.isel)
1381 if (!rs6000_explicit_options.long_double)
1382 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1385 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1386 && rs6000_cpu != PROCESSOR_POWER5);
1387 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1388 || rs6000_cpu == PROCESSOR_POWER5);
1390 rs6000_sched_restricted_insns_priority
1391 = (rs6000_sched_groups ? 1 : 0);
1393 /* Handle -msched-costly-dep option. */
1394 rs6000_sched_costly_dep
1395 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1397 if (rs6000_sched_costly_dep_str)
1399 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1400 rs6000_sched_costly_dep = no_dep_costly;
1401 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1402 rs6000_sched_costly_dep = all_deps_costly;
1403 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1404 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1405 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1406 rs6000_sched_costly_dep = store_to_load_dep_costly;
1408 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1411 /* Handle -minsert-sched-nops option. */
1412 rs6000_sched_insert_nops
1413 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1415 if (rs6000_sched_insert_nops_str)
1417 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1418 rs6000_sched_insert_nops = sched_finish_none;
1419 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1420 rs6000_sched_insert_nops = sched_finish_pad_groups;
1421 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1422 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1424 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1427 #ifdef TARGET_REGNAMES
1428 /* If the user desires alternate register names, copy in the
1429 alternate names now. */
1430 if (TARGET_REGNAMES)
1431 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1434 /* Set aix_struct_return last, after the ABI is determined.
1435 If -maix-struct-return or -msvr4-struct-return was explicitly
1436 used, don't override with the ABI default. */
1437 if (!rs6000_explicit_options.aix_struct_ret)
1438 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1440 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1441 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1444 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1446 /* We can only guarantee the availability of DI pseudo-ops when
1447 assembling for 64-bit targets. */
1450 targetm.asm_out.aligned_op.di = NULL;
1451 targetm.asm_out.unaligned_op.di = NULL;
1454 /* Set branch target alignment, if not optimizing for size. */
1457 if (rs6000_sched_groups)
1459 if (align_functions <= 0)
1460 align_functions = 16;
1461 if (align_jumps <= 0)
1463 if (align_loops <= 0)
1466 if (align_jumps_max_skip <= 0)
1467 align_jumps_max_skip = 15;
1468 if (align_loops_max_skip <= 0)
1469 align_loops_max_skip = 15;
1472 /* Arrange to save and restore machine status around nested functions. */
1473 init_machine_status = rs6000_init_machine_status;
1475 /* We should always be splitting complex arguments, but we can't break
1476 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1477 if (DEFAULT_ABI != ABI_AIX)
1478 targetm.calls.split_complex_arg = NULL;
1480 /* Initialize rs6000_cost with the appropriate target costs. */
1482 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1486 case PROCESSOR_RIOS1:
1487 rs6000_cost = &rios1_cost;
1490 case PROCESSOR_RIOS2:
1491 rs6000_cost = &rios2_cost;
1494 case PROCESSOR_RS64A:
1495 rs6000_cost = &rs64a_cost;
1498 case PROCESSOR_MPCCORE:
1499 rs6000_cost = &mpccore_cost;
1502 case PROCESSOR_PPC403:
1503 rs6000_cost = &ppc403_cost;
1506 case PROCESSOR_PPC405:
1507 rs6000_cost = &ppc405_cost;
1510 case PROCESSOR_PPC440:
1511 rs6000_cost = &ppc440_cost;
1514 case PROCESSOR_PPC601:
1515 rs6000_cost = &ppc601_cost;
1518 case PROCESSOR_PPC603:
1519 rs6000_cost = &ppc603_cost;
1522 case PROCESSOR_PPC604:
1523 rs6000_cost = &ppc604_cost;
1526 case PROCESSOR_PPC604e:
1527 rs6000_cost = &ppc604e_cost;
1530 case PROCESSOR_PPC620:
1531 rs6000_cost = &ppc620_cost;
1534 case PROCESSOR_PPC630:
1535 rs6000_cost = &ppc630_cost;
1538 case PROCESSOR_PPC750:
1539 case PROCESSOR_PPC7400:
1540 rs6000_cost = &ppc750_cost;
1543 case PROCESSOR_PPC7450:
1544 rs6000_cost = &ppc7450_cost;
1547 case PROCESSOR_PPC8540:
1548 rs6000_cost = &ppc8540_cost;
1551 case PROCESSOR_POWER4:
1552 case PROCESSOR_POWER5:
1553 rs6000_cost = &power4_cost;
1561 /* Implement targetm.vectorize.builtin_mask_for_load. */
1563 rs6000_builtin_mask_for_load (void)
1566 return altivec_builtin_mask_for_load;
1571 /* Handle generic options of the form -mfoo=yes/no.
1572 NAME is the option name.
1573 VALUE is the option value.
1574 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1575 whether the option value is 'yes' or 'no' respectively. */
1577 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1581 else if (!strcmp (value, "yes"))
1583 else if (!strcmp (value, "no"))
1586 error ("unknown -m%s= option specified: '%s'", name, value);
1589 /* Validate and record the size specified with the -mtls-size option. */
1592 rs6000_parse_tls_size_option (void)
1594 if (rs6000_tls_size_string == 0)
1596 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1597 rs6000_tls_size = 16;
1598 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1599 rs6000_tls_size = 32;
1600 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1601 rs6000_tls_size = 64;
1603 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1607 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1609 if (DEFAULT_ABI == ABI_DARWIN)
1610 /* The Darwin libraries never set errno, so we might as well
1611 avoid calling them when that's the only reason we would. */
1612 flag_errno_math = 0;
1614 /* Double growth factor to counter reduced min jump length. */
1615 set_param_value ("max-grow-copy-bb-insns", 16);
1618 /* Implement TARGET_HANDLE_OPTION. */
1621 rs6000_handle_option (size_t code, const char *arg, int value)
1626 target_flags &= ~(MASK_POWER | MASK_POWER2
1627 | MASK_MULTIPLE | MASK_STRING);
1628 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1629 | MASK_MULTIPLE | MASK_STRING);
1631 case OPT_mno_powerpc:
1632 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1633 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1634 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1635 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1638 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1639 | MASK_NO_SUM_IN_TOC);
1640 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1641 | MASK_NO_SUM_IN_TOC);
1642 #ifdef TARGET_USES_SYSV4_OPT
1643 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1644 just the same as -mminimal-toc. */
1645 target_flags |= MASK_MINIMAL_TOC;
1646 target_flags_explicit |= MASK_MINIMAL_TOC;
1650 #ifdef TARGET_USES_SYSV4_OPT
1652 /* Make -mtoc behave like -mminimal-toc. */
1653 target_flags |= MASK_MINIMAL_TOC;
1654 target_flags_explicit |= MASK_MINIMAL_TOC;
1658 #ifdef TARGET_USES_AIX64_OPT
1663 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1664 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1665 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1668 #ifdef TARGET_USES_AIX64_OPT
1673 target_flags &= ~MASK_POWERPC64;
1674 target_flags_explicit |= MASK_POWERPC64;
1677 case OPT_minsert_sched_nops_:
1678 rs6000_sched_insert_nops_str = arg;
1681 case OPT_mminimal_toc:
1684 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1685 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1692 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1693 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1700 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1701 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1705 case OPT_mpowerpc_gpopt:
1706 case OPT_mpowerpc_gfxopt:
1709 target_flags |= MASK_POWERPC;
1710 target_flags_explicit |= MASK_POWERPC;
1714 case OPT_maix_struct_return:
1715 case OPT_msvr4_struct_return:
1716 rs6000_explicit_options.aix_struct_ret = true;
1720 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1724 rs6000_explicit_options.isel = true;
1725 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1729 rs6000_explicit_options.spe = true;
1730 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1731 /* No SPE means 64-bit long doubles, even if an E500. */
1733 rs6000_long_double_type_size = 64;
1737 rs6000_debug_name = arg;
1740 #ifdef TARGET_USES_SYSV4_OPT
1742 rs6000_abi_name = arg;
1746 rs6000_sdata_name = arg;
1749 case OPT_mtls_size_:
1750 rs6000_tls_size_string = arg;
1753 case OPT_mrelocatable:
1756 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1757 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1761 case OPT_mrelocatable_lib:
1764 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1765 | MASK_NO_FP_IN_TOC;
1766 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1767 | MASK_NO_FP_IN_TOC;
1771 target_flags &= ~MASK_RELOCATABLE;
1772 target_flags_explicit |= MASK_RELOCATABLE;
1778 rs6000_explicit_options.abi = true;
1779 if (!strcmp (arg, "altivec"))
1781 rs6000_altivec_abi = 1;
1784 else if (! strcmp (arg, "no-altivec"))
1785 rs6000_altivec_abi = 0;
1786 else if (! strcmp (arg, "spe"))
1789 rs6000_altivec_abi = 0;
1790 if (!TARGET_SPE_ABI)
1791 error ("not configured for ABI: '%s'", arg);
1793 else if (! strcmp (arg, "no-spe"))
1796 /* These are here for testing during development only, do not
1797 document in the manual please. */
1798 else if (! strcmp (arg, "d64"))
1800 rs6000_darwin64_abi = 1;
1801 warning (0, "Using darwin64 ABI");
1803 else if (! strcmp (arg, "d32"))
1805 rs6000_darwin64_abi = 0;
1806 warning (0, "Using old darwin ABI");
1809 else if (! strcmp (arg, "ibmlongdouble"))
1811 rs6000_ieeequad = 0;
1812 warning (0, "Using IBM extended precision long double");
1814 else if (! strcmp (arg, "ieeelongdouble"))
1816 rs6000_ieeequad = 1;
1817 warning (0, "Using IEEE extended precision long double");
1822 error ("unknown ABI specified: '%s'", arg);
1828 rs6000_select[1].string = arg;
1832 rs6000_select[2].string = arg;
1835 case OPT_mtraceback_:
1836 rs6000_traceback_name = arg;
1839 case OPT_mfloat_gprs_:
1840 rs6000_explicit_options.float_gprs = true;
1841 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1842 rs6000_float_gprs = 1;
1843 else if (! strcmp (arg, "double"))
1844 rs6000_float_gprs = 2;
1845 else if (! strcmp (arg, "no"))
1846 rs6000_float_gprs = 0;
1849 error ("invalid option for -mfloat-gprs: '%s'", arg);
1854 case OPT_mlong_double_:
1855 rs6000_explicit_options.long_double = true;
1856 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1857 if (value != 64 && value != 128)
1859 error ("Unknown switch -mlong-double-%s", arg);
1860 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1864 rs6000_long_double_type_size = value;
1867 case OPT_msched_costly_dep_:
1868 rs6000_sched_costly_dep_str = arg;
1872 rs6000_explicit_options.alignment = true;
1873 if (! strcmp (arg, "power"))
1875 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1876 some C library functions, so warn about it. The flag may be
1877 useful for performance studies from time to time though, so
1878 don't disable it entirely. */
1879 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1880 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1881 " it is incompatible with the installed C and C++ libraries");
1882 rs6000_alignment_flags = MASK_ALIGN_POWER;
1884 else if (! strcmp (arg, "natural"))
1885 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1888 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1896 /* Do anything needed at the start of the asm file. */
1899 rs6000_file_start (void)
1903 const char *start = buffer;
1904 struct rs6000_cpu_select *ptr;
1905 const char *default_cpu = TARGET_CPU_DEFAULT;
1906 FILE *file = asm_out_file;
1908 default_file_start ();
1910 #ifdef TARGET_BI_ARCH
1911 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1915 if (flag_verbose_asm)
1917 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1918 rs6000_select[0].string = default_cpu;
1920 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1922 ptr = &rs6000_select[i];
1923 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1925 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1930 if (PPC405_ERRATUM77)
1932 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1936 #ifdef USING_ELFOS_H
1937 switch (rs6000_sdata)
1939 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1940 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1941 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1942 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1945 if (rs6000_sdata && g_switch_value)
1947 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1957 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1959 switch_to_section (toc_section);
1960 switch_to_section (text_section);
1965 /* Return nonzero if this function is known to have a null epilogue. */
1968 direct_return (void)
1970 if (reload_completed)
1972 rs6000_stack_t *info = rs6000_stack_info ();
1974 if (info->first_gp_reg_save == 32
1975 && info->first_fp_reg_save == 64
1976 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1977 && ! info->lr_save_p
1978 && ! info->cr_save_p
1979 && info->vrsave_mask == 0
1987 /* Return the number of instructions it takes to form a constant in an
1988 integer register. */
1991 num_insns_constant_wide (HOST_WIDE_INT value)
1993 /* signed constant loadable with {cal|addi} */
1994 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1997 /* constant loadable with {cau|addis} */
1998 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2001 #if HOST_BITS_PER_WIDE_INT == 64
2002 else if (TARGET_POWERPC64)
2004 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2005 HOST_WIDE_INT high = value >> 31;
2007 if (high == 0 || high == -1)
2013 return num_insns_constant_wide (high) + 1;
2015 return (num_insns_constant_wide (high)
2016 + num_insns_constant_wide (low) + 1);
2025 num_insns_constant (rtx op, enum machine_mode mode)
2027 HOST_WIDE_INT low, high;
2029 switch (GET_CODE (op))
2032 #if HOST_BITS_PER_WIDE_INT == 64
2033 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2034 && mask64_operand (op, mode))
2038 return num_insns_constant_wide (INTVAL (op));
2046 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2047 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2048 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2051 if (mode == VOIDmode || mode == DImode)
2053 high = CONST_DOUBLE_HIGH (op);
2054 low = CONST_DOUBLE_LOW (op);
2061 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2062 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2063 high = l[WORDS_BIG_ENDIAN == 0];
2064 low = l[WORDS_BIG_ENDIAN != 0];
2068 return (num_insns_constant_wide (low)
2069 + num_insns_constant_wide (high));
2072 if ((high == 0 && low >= 0)
2073 || (high == -1 && low < 0))
2074 return num_insns_constant_wide (low);
2076 else if (mask64_operand (op, mode))
2080 return num_insns_constant_wide (high) + 1;
2083 return (num_insns_constant_wide (high)
2084 + num_insns_constant_wide (low) + 1);
2093 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2094 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2095 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2096 all items are set to the same value and contain COPIES replicas of the
2097 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2098 operand and the others are set to the value of the operand's msb. */
2101 vspltis_constant (rtx op, unsigned step, unsigned copies)
2103 enum machine_mode mode = GET_MODE (op);
2104 enum machine_mode inner = GET_MODE_INNER (mode);
2107 unsigned nunits = GET_MODE_NUNITS (mode);
2108 unsigned bitsize = GET_MODE_BITSIZE (inner);
2109 unsigned mask = GET_MODE_MASK (inner);
2111 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2112 HOST_WIDE_INT val = INTVAL (last);
2113 HOST_WIDE_INT splat_val = val;
2114 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2116 /* Construct the value to be splatted, if possible. If not, return 0. */
2117 for (i = 2; i <= copies; i *= 2)
2119 HOST_WIDE_INT small_val;
2121 small_val = splat_val >> bitsize;
2123 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2125 splat_val = small_val;
2128 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2129 if (EASY_VECTOR_15 (splat_val))
2132 /* Also check if we can splat, and then add the result to itself. Do so if
2133 the value is positive, of if the splat instruction is using OP's mode;
2134 for splat_val < 0, the splat and the add should use the same mode. */
2135 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2136 && (splat_val >= 0 || (step == 1 && copies == 1)))
2142 /* Check if VAL is present in every STEP-th element, and the
2143 other elements are filled with its most significant bit. */
2144 for (i = 0; i < nunits - 1; ++i)
2146 HOST_WIDE_INT desired_val;
2147 if (((i + 1) & (step - 1)) == 0)
2150 desired_val = msb_val;
2152 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2160 /* Return true if OP is of the given MODE and can be synthesized
2161 with a vspltisb, vspltish or vspltisw. */
2164 easy_altivec_constant (rtx op, enum machine_mode mode)
2166 unsigned step, copies;
2168 if (mode == VOIDmode)
2169 mode = GET_MODE (op);
2170 else if (mode != GET_MODE (op))
2173 /* Start with a vspltisw. */
2174 step = GET_MODE_NUNITS (mode) / 4;
2177 if (vspltis_constant (op, step, copies))
2180 /* Then try with a vspltish. */
2186 if (vspltis_constant (op, step, copies))
2189 /* And finally a vspltisb. */
2195 if (vspltis_constant (op, step, copies))
2201 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2202 result is OP. Abort if it is not possible. */
2205 gen_easy_altivec_constant (rtx op)
2207 enum machine_mode mode = GET_MODE (op);
2208 int nunits = GET_MODE_NUNITS (mode);
2209 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2210 unsigned step = nunits / 4;
2211 unsigned copies = 1;
2213 /* Start with a vspltisw. */
2214 if (vspltis_constant (op, step, copies))
2215 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2217 /* Then try with a vspltish. */
2223 if (vspltis_constant (op, step, copies))
2224 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2226 /* And finally a vspltisb. */
2232 if (vspltis_constant (op, step, copies))
2233 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2239 output_vec_const_move (rtx *operands)
2242 enum machine_mode mode;
2247 mode = GET_MODE (dest);
2252 if (zero_constant (vec, mode))
2253 return "vxor %0,%0,%0";
2255 splat_vec = gen_easy_altivec_constant (vec);
2256 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2257 operands[1] = XEXP (splat_vec, 0);
2258 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2261 switch (GET_MODE (splat_vec))
2264 return "vspltisw %0,%1";
2267 return "vspltish %0,%1";
2270 return "vspltisb %0,%1";
2277 gcc_assert (TARGET_SPE);
2279 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2280 pattern of V1DI, V4HI, and V2SF.
2282 FIXME: We should probably return # and add post reload
2283 splitters for these, but this way is so easy ;-). */
2284 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2285 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2286 operands[1] = CONST_VECTOR_ELT (vec, 0);
2287 operands[2] = CONST_VECTOR_ELT (vec, 1);
2289 return "li %0,%1\n\tevmergelo %0,%0,%0";
2291 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2294 /* Initialize vector TARGET to VALS. */
2297 rs6000_expand_vector_init (rtx target, rtx vals)
2299 enum machine_mode mode = GET_MODE (target);
2300 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2301 int n_elts = GET_MODE_NUNITS (mode);
2302 int n_var = 0, one_var = -1;
2303 bool all_same = true, all_const_zero = true;
2307 for (i = 0; i < n_elts; ++i)
2309 x = XVECEXP (vals, 0, i);
2310 if (!CONSTANT_P (x))
2311 ++n_var, one_var = i;
2312 else if (x != CONST0_RTX (inner_mode))
2313 all_const_zero = false;
2315 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2321 if (mode != V4SFmode && all_const_zero)
2323 /* Zero register. */
2324 emit_insn (gen_rtx_SET (VOIDmode, target,
2325 gen_rtx_XOR (mode, target, target)));
2328 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2330 /* Splat immediate. */
2331 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2335 ; /* Splat vector element. */
2338 /* Load from constant pool. */
2339 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2344 /* Store value to stack temp. Load vector element. Splat. */
2347 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2348 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2349 XVECEXP (vals, 0, 0));
2350 x = gen_rtx_UNSPEC (VOIDmode,
2351 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2352 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2354 gen_rtx_SET (VOIDmode,
2357 x = gen_rtx_VEC_SELECT (inner_mode, target,
2358 gen_rtx_PARALLEL (VOIDmode,
2359 gen_rtvec (1, const0_rtx)));
2360 emit_insn (gen_rtx_SET (VOIDmode, target,
2361 gen_rtx_VEC_DUPLICATE (mode, x)));
2365 /* One field is non-constant. Load constant then overwrite
2369 rtx copy = copy_rtx (vals);
2371 /* Load constant part of vector, substitute neighboring value for
2373 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2374 rs6000_expand_vector_init (target, copy);
2376 /* Insert variable. */
2377 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2381 /* Construct the vector in memory one field at a time
2382 and load the whole vector. */
2383 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2384 for (i = 0; i < n_elts; i++)
2385 emit_move_insn (adjust_address_nv (mem, inner_mode,
2386 i * GET_MODE_SIZE (inner_mode)),
2387 XVECEXP (vals, 0, i));
2388 emit_move_insn (target, mem);
2391 /* Set field ELT of TARGET to VAL. */
2394 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2396 enum machine_mode mode = GET_MODE (target);
2397 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2398 rtx reg = gen_reg_rtx (mode);
2400 int width = GET_MODE_SIZE (inner_mode);
2403 /* Load single variable value. */
2404 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2405 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2406 x = gen_rtx_UNSPEC (VOIDmode,
2407 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2408 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2410 gen_rtx_SET (VOIDmode,
2414 /* Linear sequence. */
2415 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2416 for (i = 0; i < 16; ++i)
2417 XVECEXP (mask, 0, i) = GEN_INT (i);
2419 /* Set permute mask to insert element into target. */
2420 for (i = 0; i < width; ++i)
2421 XVECEXP (mask, 0, elt*width + i)
2422 = GEN_INT (i + 0x10);
2423 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2424 x = gen_rtx_UNSPEC (mode,
2425 gen_rtvec (3, target, reg,
2426 force_reg (V16QImode, x)),
2428 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2431 /* Extract field ELT from VEC into TARGET. */
2434 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2436 enum machine_mode mode = GET_MODE (vec);
2437 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2440 /* Allocate mode-sized buffer. */
2441 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2443 /* Add offset to field within buffer matching vector element. */
2444 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2446 /* Store single field into mode-sized buffer. */
2447 x = gen_rtx_UNSPEC (VOIDmode,
2448 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2449 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2451 gen_rtx_SET (VOIDmode,
2454 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2457 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2458 implement ANDing by the mask IN. */
2460 build_mask64_2_operands (rtx in, rtx *out)
2462 #if HOST_BITS_PER_WIDE_INT >= 64
2463 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2466 gcc_assert (GET_CODE (in) == CONST_INT);
2471 /* Assume c initially something like 0x00fff000000fffff. The idea
2472 is to rotate the word so that the middle ^^^^^^ group of zeros
2473 is at the MS end and can be cleared with an rldicl mask. We then
2474 rotate back and clear off the MS ^^ group of zeros with a
2476 c = ~c; /* c == 0xff000ffffff00000 */
2477 lsb = c & -c; /* lsb == 0x0000000000100000 */
2478 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2479 c = ~c; /* c == 0x00fff000000fffff */
2480 c &= -lsb; /* c == 0x00fff00000000000 */
2481 lsb = c & -c; /* lsb == 0x0000100000000000 */
2482 c = ~c; /* c == 0xff000fffffffffff */
2483 c &= -lsb; /* c == 0xff00000000000000 */
2485 while ((lsb >>= 1) != 0)
2486 shift++; /* shift == 44 on exit from loop */
2487 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2488 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2489 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2493 /* Assume c initially something like 0xff000f0000000000. The idea
2494 is to rotate the word so that the ^^^ middle group of zeros
2495 is at the LS end and can be cleared with an rldicr mask. We then
2496 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2498 lsb = c & -c; /* lsb == 0x0000010000000000 */
2499 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2500 c = ~c; /* c == 0x00fff0ffffffffff */
2501 c &= -lsb; /* c == 0x00fff00000000000 */
2502 lsb = c & -c; /* lsb == 0x0000100000000000 */
2503 c = ~c; /* c == 0xff000fffffffffff */
2504 c &= -lsb; /* c == 0xff00000000000000 */
2506 while ((lsb >>= 1) != 0)
2507 shift++; /* shift == 44 on exit from loop */
2508 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2509 m1 >>= shift; /* m1 == 0x0000000000000fff */
2510 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2513 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2514 masks will be all 1's. We are guaranteed more than one transition. */
2515 out[0] = GEN_INT (64 - shift);
2516 out[1] = GEN_INT (m1);
2517 out[2] = GEN_INT (shift);
2518 out[3] = GEN_INT (m2);
2526 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2529 invalid_e500_subreg (rtx op, enum machine_mode mode)
2531 /* Reject (subreg:SI (reg:DF)). */
2532 if (GET_CODE (op) == SUBREG
2534 && REG_P (SUBREG_REG (op))
2535 && GET_MODE (SUBREG_REG (op)) == DFmode)
2538 /* Reject (subreg:DF (reg:DI)). */
2539 if (GET_CODE (op) == SUBREG
2541 && REG_P (SUBREG_REG (op))
2542 && GET_MODE (SUBREG_REG (op)) == DImode)
2548 /* Darwin, AIX increases natural record alignment to doubleword if the first
2549 field is an FP double while the FP fields remain word aligned. */
2552 rs6000_special_round_type_align (tree type, unsigned int computed,
2553 unsigned int specified)
2555 unsigned int align = MAX (computed, specified);
2556 tree field = TYPE_FIELDS (type);
2558 /* Skip all non field decls */
2559 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2560 field = TREE_CHAIN (field);
2562 if (field != NULL && field != type)
2564 type = TREE_TYPE (field);
2565 while (TREE_CODE (type) == ARRAY_TYPE)
2566 type = TREE_TYPE (type);
2568 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2569 align = MAX (align, 64);
2575 /* Return 1 for an operand in small memory on V.4/eabi. */
2578 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2579 enum machine_mode mode ATTRIBUTE_UNUSED)
2584 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2587 if (DEFAULT_ABI != ABI_V4)
2590 if (GET_CODE (op) == SYMBOL_REF)
2593 else if (GET_CODE (op) != CONST
2594 || GET_CODE (XEXP (op, 0)) != PLUS
2595 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2596 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2601 rtx sum = XEXP (op, 0);
2602 HOST_WIDE_INT summand;
2604 /* We have to be careful here, because it is the referenced address
2605 that must be 32k from _SDA_BASE_, not just the symbol. */
2606 summand = INTVAL (XEXP (sum, 1));
2607 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2610 sym_ref = XEXP (sum, 0);
2613 return SYMBOL_REF_SMALL_P (sym_ref);
2619 /* Return true if either operand is a general purpose register. */
2622 gpr_or_gpr_p (rtx op0, rtx op1)
2624 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2625 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2629 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2632 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2634 switch (GET_CODE (op))
2637 if (RS6000_SYMBOL_REF_TLS_P (op))
2639 else if (CONSTANT_POOL_ADDRESS_P (op))
2641 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2649 else if (! strcmp (XSTR (op, 0), toc_label_name))
2658 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2659 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2661 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2670 constant_pool_expr_p (rtx op)
2674 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2678 toc_relative_expr_p (rtx op)
2682 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2686 legitimate_constant_pool_address_p (rtx x)
2689 && GET_CODE (x) == PLUS
2690 && GET_CODE (XEXP (x, 0)) == REG
2691 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2692 && constant_pool_expr_p (XEXP (x, 1)));
2696 rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x)
2698 return (DEFAULT_ABI == ABI_V4
2699 && !flag_pic && !TARGET_TOC
2700 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2701 && small_data_operand (x, mode));
2704 /* SPE offset addressing is limited to 5-bits worth of double words. */
2705 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2708 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2710 unsigned HOST_WIDE_INT offset, extra;
2712 if (GET_CODE (x) != PLUS)
2714 if (GET_CODE (XEXP (x, 0)) != REG)
2716 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2718 if (legitimate_constant_pool_address_p (x))
2720 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2723 offset = INTVAL (XEXP (x, 1));
2731 /* AltiVec vector modes. Only reg+reg addressing is valid and
2732 constant offset zero should not occur due to canonicalization.
2733 Allow any offset when not strict before reload. */
2740 /* SPE vector modes. */
2741 return SPE_CONST_OFFSET_OK (offset);
2744 if (TARGET_E500_DOUBLE)
2745 return SPE_CONST_OFFSET_OK (offset);
2748 /* On e500v2, we may have:
2750 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2752 Which gets addressed with evldd instructions. */
2753 if (TARGET_E500_DOUBLE)
2754 return SPE_CONST_OFFSET_OK (offset);
2756 if (mode == DFmode || !TARGET_POWERPC64)
2758 else if (offset & 3)
2764 if (mode == TFmode || !TARGET_POWERPC64)
2766 else if (offset & 3)
2777 return (offset < 0x10000) && (offset + extra < 0x10000);
2781 legitimate_indexed_address_p (rtx x, int strict)
2785 if (GET_CODE (x) != PLUS)
2791 /* Recognize the rtl generated by reload which we know will later be
2792 replaced with proper base and index regs. */
2794 && reload_in_progress
2795 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2799 return (REG_P (op0) && REG_P (op1)
2800 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2801 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2802 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2803 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2807 legitimate_indirect_address_p (rtx x, int strict)
2809 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2813 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2815 if (!TARGET_MACHO || !flag_pic
2816 || mode != SImode || GET_CODE (x) != MEM)
2820 if (GET_CODE (x) != LO_SUM)
2822 if (GET_CODE (XEXP (x, 0)) != REG)
2824 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2828 return CONSTANT_P (x);
2832 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2834 if (GET_CODE (x) != LO_SUM)
2836 if (GET_CODE (XEXP (x, 0)) != REG)
2838 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2840 /* Restrict addressing for DI because of our SUBREG hackery. */
2841 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2845 if (TARGET_ELF || TARGET_MACHO)
2847 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2851 if (GET_MODE_NUNITS (mode) != 1)
2853 if (GET_MODE_BITSIZE (mode) > 64
2854 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2855 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2858 return CONSTANT_P (x);
2865 /* Try machine-dependent ways of modifying an illegitimate address
2866 to be legitimate. If we find one, return the new, valid address.
2867 This is used from only one place: `memory_address' in explow.c.
2869 OLDX is the address as it was before break_out_memory_refs was
2870 called. In some cases it is useful to look at this to decide what
2873 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2875 It is always safe for this function to do nothing. It exists to
2876 recognize opportunities to optimize the output.
2878 On RS/6000, first check for the sum of a register with a constant
2879 integer that is out of range. If so, generate code to add the
2880 constant with the low-order 16 bits masked to the register and force
2881 this result into another register (this can be done with `cau').
2882 Then generate an address of REG+(CONST&0xffff), allowing for the
2883 possibility of bit 16 being a one.
2885 Then check for the sum of a register and something not constant, try to
2886 load the other things into a register and return the sum. */
2889 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2890 enum machine_mode mode)
2892 if (GET_CODE (x) == SYMBOL_REF)
2894 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2896 return rs6000_legitimize_tls_address (x, model);
2899 if (GET_CODE (x) == PLUS
2900 && GET_CODE (XEXP (x, 0)) == REG
2901 && GET_CODE (XEXP (x, 1)) == CONST_INT
2902 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2904 HOST_WIDE_INT high_int, low_int;
2906 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2907 high_int = INTVAL (XEXP (x, 1)) - low_int;
2908 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2909 GEN_INT (high_int)), 0);
2910 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2912 else if (GET_CODE (x) == PLUS
2913 && GET_CODE (XEXP (x, 0)) == REG
2914 && GET_CODE (XEXP (x, 1)) != CONST_INT
2915 && GET_MODE_NUNITS (mode) == 1
2916 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2918 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2920 && (TARGET_POWERPC64 || mode != DImode)
2923 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2924 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2926 else if (ALTIVEC_VECTOR_MODE (mode))
2930 /* Make sure both operands are registers. */
2931 if (GET_CODE (x) == PLUS)
2932 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2933 force_reg (Pmode, XEXP (x, 1)));
2935 reg = force_reg (Pmode, x);
2938 else if (SPE_VECTOR_MODE (mode)
2939 || (TARGET_E500_DOUBLE && (mode == DFmode
2940 || mode == DImode)))
2944 /* We accept [reg + reg] and [reg + OFFSET]. */
2946 if (GET_CODE (x) == PLUS)
2948 rtx op1 = XEXP (x, 0);
2949 rtx op2 = XEXP (x, 1);
2951 op1 = force_reg (Pmode, op1);
2953 if (GET_CODE (op2) != REG
2954 && (GET_CODE (op2) != CONST_INT
2955 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2956 op2 = force_reg (Pmode, op2);
2958 return gen_rtx_PLUS (Pmode, op1, op2);
2961 return force_reg (Pmode, x);
2967 && GET_CODE (x) != CONST_INT
2968 && GET_CODE (x) != CONST_DOUBLE
2970 && GET_MODE_NUNITS (mode) == 1
2971 && (GET_MODE_BITSIZE (mode) <= 32
2972 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2974 rtx reg = gen_reg_rtx (Pmode);
2975 emit_insn (gen_elf_high (reg, x));
2976 return gen_rtx_LO_SUM (Pmode, reg, x);
2978 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2981 && ! MACHO_DYNAMIC_NO_PIC_P
2983 && GET_CODE (x) != CONST_INT
2984 && GET_CODE (x) != CONST_DOUBLE
2986 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2990 rtx reg = gen_reg_rtx (Pmode);
2991 emit_insn (gen_macho_high (reg, x));
2992 return gen_rtx_LO_SUM (Pmode, reg, x);
2995 && constant_pool_expr_p (x)
2996 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2998 return create_TOC_reference (x);
3004 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3005 We need to emit DTP-relative relocations. */
3008 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3013 fputs ("\t.long\t", file);
3016 fputs (DOUBLE_INT_ASM_OP, file);
3021 output_addr_const (file, x);
3022 fputs ("@dtprel+0x8000", file);
3025 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3027 static GTY(()) rtx rs6000_tls_symbol;
3029 rs6000_tls_get_addr (void)
3031 if (!rs6000_tls_symbol)
3032 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3034 return rs6000_tls_symbol;
3037 /* Construct the SYMBOL_REF for TLS GOT references. */
3039 static GTY(()) rtx rs6000_got_symbol;
3041 rs6000_got_sym (void)
3043 if (!rs6000_got_symbol)
3045 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3046 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3047 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3050 return rs6000_got_symbol;
3053 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3054 this (thread-local) address. */
3057 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3061 dest = gen_reg_rtx (Pmode);
3062 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3068 tlsreg = gen_rtx_REG (Pmode, 13);
3069 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3073 tlsreg = gen_rtx_REG (Pmode, 2);
3074 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3078 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3082 tmp = gen_reg_rtx (Pmode);
3085 tlsreg = gen_rtx_REG (Pmode, 13);
3086 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3090 tlsreg = gen_rtx_REG (Pmode, 2);
3091 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3095 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3097 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3102 rtx r3, got, tga, tmp1, tmp2, eqv;
3104 /* We currently use relocations like @got@tlsgd for tls, which
3105 means the linker will handle allocation of tls entries, placing
3106 them in the .got section. So use a pointer to the .got section,
3107 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3108 or to secondary GOT sections used by 32-bit -fPIC. */
3110 got = gen_rtx_REG (Pmode, 2);
3114 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3117 rtx gsym = rs6000_got_sym ();
3118 got = gen_reg_rtx (Pmode);
3120 rs6000_emit_move (got, gsym, Pmode);
3123 rtx tempLR, tmp3, mem;
3126 tempLR = gen_reg_rtx (Pmode);
3127 tmp1 = gen_reg_rtx (Pmode);
3128 tmp2 = gen_reg_rtx (Pmode);
3129 tmp3 = gen_reg_rtx (Pmode);
3130 mem = gen_const_mem (Pmode, tmp1);
3132 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3133 emit_move_insn (tmp1, tempLR);
3134 emit_move_insn (tmp2, mem);
3135 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3136 last = emit_move_insn (got, tmp3);
3137 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3139 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3141 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3147 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3149 r3 = gen_rtx_REG (Pmode, 3);
3151 insn = gen_tls_gd_64 (r3, got, addr);
3153 insn = gen_tls_gd_32 (r3, got, addr);
3156 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3157 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3158 insn = emit_call_insn (insn);
3159 CONST_OR_PURE_CALL_P (insn) = 1;
3160 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3161 insn = get_insns ();
3163 emit_libcall_block (insn, dest, r3, addr);
3165 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3167 r3 = gen_rtx_REG (Pmode, 3);
3169 insn = gen_tls_ld_64 (r3, got);
3171 insn = gen_tls_ld_32 (r3, got);
3174 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3175 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3176 insn = emit_call_insn (insn);
3177 CONST_OR_PURE_CALL_P (insn) = 1;
3178 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3179 insn = get_insns ();
3181 tmp1 = gen_reg_rtx (Pmode);
3182 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3184 emit_libcall_block (insn, tmp1, r3, eqv);
3185 if (rs6000_tls_size == 16)
3188 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3190 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3192 else if (rs6000_tls_size == 32)
3194 tmp2 = gen_reg_rtx (Pmode);
3196 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3198 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3201 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3203 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3207 tmp2 = gen_reg_rtx (Pmode);
3209 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3211 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3213 insn = gen_rtx_SET (Pmode, dest,
3214 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3220 /* IE, or 64 bit offset LE. */
3221 tmp2 = gen_reg_rtx (Pmode);
3223 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3225 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3228 insn = gen_tls_tls_64 (dest, tmp2, addr);
3230 insn = gen_tls_tls_32 (dest, tmp2, addr);
3238 /* Return 1 if X contains a thread-local symbol. */
3241 rs6000_tls_referenced_p (rtx x)
3243 if (! TARGET_HAVE_TLS)
3246 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3249 /* Return 1 if *X is a thread-local symbol. This is the same as
3250 rs6000_tls_symbol_ref except for the type of the unused argument. */
3253 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3255 return RS6000_SYMBOL_REF_TLS_P (*x);
3258 /* The convention appears to be to define this wherever it is used.
3259 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3260 is now used here. */
3261 #ifndef REG_MODE_OK_FOR_BASE_P
3262 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3265 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3266 replace the input X, or the original X if no replacement is called for.
3267 The output parameter *WIN is 1 if the calling macro should goto WIN,
3270 For RS/6000, we wish to handle large displacements off a base
3271 register by splitting the addend across an addiu/addis and the mem insn.
3272 This cuts number of extra insns needed from 3 to 1.
3274 On Darwin, we use this to generate code for floating point constants.
3275 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3276 The Darwin code is inside #if TARGET_MACHO because only then is
3277 machopic_function_base_name() defined. */
3279 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3280 int opnum, int type,
3281 int ind_levels ATTRIBUTE_UNUSED, int *win)
3283 /* We must recognize output that we have already generated ourselves. */
3284 if (GET_CODE (x) == PLUS
3285 && GET_CODE (XEXP (x, 0)) == PLUS
3286 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3287 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3288 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3290 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3291 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3292 opnum, (enum reload_type)type);
3298 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3299 && GET_CODE (x) == LO_SUM
3300 && GET_CODE (XEXP (x, 0)) == PLUS
3301 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3302 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3303 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3304 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3305 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3306 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3307 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3309 /* Result of previous invocation of this function on Darwin
3310 floating point constant. */
3311 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3312 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3313 opnum, (enum reload_type)type);
3319 /* Force ld/std non-word aligned offset into base register by wrapping
3321 if (GET_CODE (x) == PLUS
3322 && GET_CODE (XEXP (x, 0)) == REG
3323 && REGNO (XEXP (x, 0)) < 32
3324 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3325 && GET_CODE (XEXP (x, 1)) == CONST_INT
3326 && (INTVAL (XEXP (x, 1)) & 3) != 0
3327 && !ALTIVEC_VECTOR_MODE (mode)
3328 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3329 && TARGET_POWERPC64)
3331 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3332 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3333 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3334 opnum, (enum reload_type) type);
3339 if (GET_CODE (x) == PLUS
3340 && GET_CODE (XEXP (x, 0)) == REG
3341 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3342 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3343 && GET_CODE (XEXP (x, 1)) == CONST_INT
3344 && !SPE_VECTOR_MODE (mode)
3345 && !(TARGET_E500_DOUBLE && (mode == DFmode
3347 && !ALTIVEC_VECTOR_MODE (mode))
3349 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3350 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3352 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3354 /* Check for 32-bit overflow. */
3355 if (high + low != val)
3361 /* Reload the high part into a base reg; leave the low part
3362 in the mem directly. */
3364 x = gen_rtx_PLUS (GET_MODE (x),
3365 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3369 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3370 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3371 opnum, (enum reload_type)type);
3376 if (GET_CODE (x) == SYMBOL_REF
3377 && !ALTIVEC_VECTOR_MODE (mode)
3379 && DEFAULT_ABI == ABI_DARWIN
3380 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3382 && DEFAULT_ABI == ABI_V4
3385 /* Don't do this for TFmode, since the result isn't offsettable.
3386 The same goes for DImode without 64-bit gprs. */
3388 && (mode != DImode || TARGET_POWERPC64))
3393 rtx offset = gen_rtx_CONST (Pmode,
3394 gen_rtx_MINUS (Pmode, x,
3395 machopic_function_base_sym ()));
3396 x = gen_rtx_LO_SUM (GET_MODE (x),
3397 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3398 gen_rtx_HIGH (Pmode, offset)), offset);
3402 x = gen_rtx_LO_SUM (GET_MODE (x),
3403 gen_rtx_HIGH (Pmode, x), x);
3405 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3406 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3407 opnum, (enum reload_type)type);
3412 /* Reload an offset address wrapped by an AND that represents the
3413 masking of the lower bits. Strip the outer AND and let reload
3414 convert the offset address into an indirect address. */
3416 && ALTIVEC_VECTOR_MODE (mode)
3417 && GET_CODE (x) == AND
3418 && GET_CODE (XEXP (x, 0)) == PLUS
3419 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3420 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3421 && GET_CODE (XEXP (x, 1)) == CONST_INT
3422 && INTVAL (XEXP (x, 1)) == -16)
3430 && constant_pool_expr_p (x)
3431 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3433 (x) = create_TOC_reference (x);
3441 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3442 that is a valid memory address for an instruction.
3443 The MODE argument is the machine mode for the MEM expression
3444 that wants to use this address.
3446 On the RS/6000, there are four valid address: a SYMBOL_REF that
3447 refers to a constant pool entry of an address (or the sum of it
3448 plus a constant), a short (16-bit signed) constant plus a register,
3449 the sum of two registers, or a register indirect, possibly with an
3450 auto-increment. For DFmode and DImode with a constant plus register,
3451 we must ensure that both words are addressable or PowerPC64 with offset
3454 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3455 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3456 adjacent memory cells are accessed by adding word-sized offsets
3457 during assembly output. */
3459 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3461 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3463 && ALTIVEC_VECTOR_MODE (mode)
3464 && GET_CODE (x) == AND
3465 && GET_CODE (XEXP (x, 1)) == CONST_INT
3466 && INTVAL (XEXP (x, 1)) == -16)
3469 if (RS6000_SYMBOL_REF_TLS_P (x))
3471 if (legitimate_indirect_address_p (x, reg_ok_strict))
3473 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3474 && !ALTIVEC_VECTOR_MODE (mode)
3475 && !SPE_VECTOR_MODE (mode)
3476 /* Restrict addressing for DI because of our SUBREG hackery. */
3477 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3479 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3481 if (rs6000_legitimate_small_data_p (mode, x))
3483 if (legitimate_constant_pool_address_p (x))
3485 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3487 && GET_CODE (x) == PLUS
3488 && GET_CODE (XEXP (x, 0)) == REG
3489 && (XEXP (x, 0) == virtual_stack_vars_rtx
3490 || XEXP (x, 0) == arg_pointer_rtx)
3491 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3493 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3497 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3499 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3500 && (TARGET_POWERPC64 || mode != DImode)
3501 && legitimate_indexed_address_p (x, reg_ok_strict))
3503 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3508 /* Go to LABEL if ADDR (a legitimate address expression)
3509 has an effect that depends on the machine mode it is used for.
3511 On the RS/6000 this is true of all integral offsets (since AltiVec
3512 modes don't allow them) or is a pre-increment or decrement.
3514 ??? Except that due to conceptual problems in offsettable_address_p
3515 we can't really report the problems of integral offsets. So leave
3516 this assuming that the adjustable offset must be valid for the
3517 sub-words of a TFmode operand, which is what we had before. */
3520 rs6000_mode_dependent_address (rtx addr)
3522 switch (GET_CODE (addr))
3525 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3527 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3528 return val + 12 + 0x8000 >= 0x10000;
3537 return TARGET_UPDATE;
3546 /* Return number of consecutive hard regs needed starting at reg REGNO
3547 to hold something of mode MODE.
3548 This is ordinarily the length in words of a value of mode MODE
3549 but can be less for certain modes in special long registers.
3551 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3552 scalar instructions. The upper 32 bits are only available to the
3555 POWER and PowerPC GPRs hold 32 bits worth;
3556 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3559 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3561 if (FP_REGNO_P (regno))
3562 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3564 if (TARGET_E500_DOUBLE && mode == DFmode)
3567 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3568 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3570 if (ALTIVEC_REGNO_P (regno))
3572 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3574 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3577 /* Change register usage conditional on target flags. */
3579 rs6000_conditional_register_usage (void)
3583 /* Set MQ register fixed (already call_used) if not POWER
3584 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3589 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3591 fixed_regs[13] = call_used_regs[13]
3592 = call_really_used_regs[13] = 1;
3594 /* Conditionally disable FPRs. */
3595 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3596 for (i = 32; i < 64; i++)
3597 fixed_regs[i] = call_used_regs[i]
3598 = call_really_used_regs[i] = 1;
3600 /* The TOC register is not killed across calls in a way that is
3601 visible to the compiler. */
3602 if (DEFAULT_ABI == ABI_AIX)
3603 call_really_used_regs[2] = 0;
3605 if (DEFAULT_ABI == ABI_V4
3606 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3608 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3610 if (DEFAULT_ABI == ABI_V4
3611 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3613 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3614 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3615 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3617 if (DEFAULT_ABI == ABI_DARWIN
3618 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3619 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3620 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3621 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3623 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3624 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3625 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3628 global_regs[VSCR_REGNO] = 1;
3632 global_regs[SPEFSCR_REGNO] = 1;
3633 fixed_regs[FIXED_SCRATCH]
3634 = call_used_regs[FIXED_SCRATCH]
3635 = call_really_used_regs[FIXED_SCRATCH] = 1;
3638 if (! TARGET_ALTIVEC)
3640 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3641 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3642 call_really_used_regs[VRSAVE_REGNO] = 1;
3645 if (TARGET_ALTIVEC_ABI)
3646 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3647 call_used_regs[i] = call_really_used_regs[i] = 1;
3650 /* Try to output insns to set TARGET equal to the constant C if it can
3651 be done in less than N insns. Do all computations in MODE.
3652 Returns the place where the output has been placed if it can be
3653 done and the insns have been emitted. If it would take more than N
3654 insns, zero is returned and no insns and emitted. */
3657 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3658 rtx source, int n ATTRIBUTE_UNUSED)
3660 rtx result, insn, set;
3661 HOST_WIDE_INT c0, c1;
3668 dest = gen_reg_rtx (mode);
3669 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3673 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3675 emit_insn (gen_rtx_SET (VOIDmode, result,
3676 GEN_INT (INTVAL (source)
3677 & (~ (HOST_WIDE_INT) 0xffff))));
3678 emit_insn (gen_rtx_SET (VOIDmode, dest,
3679 gen_rtx_IOR (SImode, result,
3680 GEN_INT (INTVAL (source) & 0xffff))));
3685 switch (GET_CODE (source))
3688 c0 = INTVAL (source);
3693 #if HOST_BITS_PER_WIDE_INT >= 64
3694 c0 = CONST_DOUBLE_LOW (source);
3697 c0 = CONST_DOUBLE_LOW (source);
3698 c1 = CONST_DOUBLE_HIGH (source);
3706 result = rs6000_emit_set_long_const (dest, c0, c1);
3713 insn = get_last_insn ();
3714 set = single_set (insn);
3715 if (! CONSTANT_P (SET_SRC (set)))
3716 set_unique_reg_note (insn, REG_EQUAL, source);
3721 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3722 fall back to a straight forward decomposition. We do this to avoid
3723 exponential run times encountered when looking for longer sequences
3724 with rs6000_emit_set_const. */
3726 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3728 if (!TARGET_POWERPC64)
3730 rtx operand1, operand2;
3732 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3734 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3736 emit_move_insn (operand1, GEN_INT (c1));
3737 emit_move_insn (operand2, GEN_INT (c2));
3741 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3744 ud2 = (c1 & 0xffff0000) >> 16;
3745 #if HOST_BITS_PER_WIDE_INT >= 64
3749 ud4 = (c2 & 0xffff0000) >> 16;
3751 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3752 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3755 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3757 emit_move_insn (dest, GEN_INT (ud1));
3760 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3761 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3764 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3767 emit_move_insn (dest, GEN_INT (ud2 << 16));
3769 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3771 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3772 || (ud4 == 0 && ! (ud3 & 0x8000)))
3775 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3778 emit_move_insn (dest, GEN_INT (ud3 << 16));
3781 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3782 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3784 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3789 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3792 emit_move_insn (dest, GEN_INT (ud4 << 16));
3795 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3797 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3799 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3800 GEN_INT (ud2 << 16)));
3802 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3808 /* Helper for the following. Get rid of [r+r] memory refs
3809 in cases where it won't work (TImode, TFmode). */
3812 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3814 if (GET_CODE (operands[0]) == MEM
3815 && GET_CODE (XEXP (operands[0], 0)) != REG
3816 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3817 && ! reload_in_progress)
3819 = replace_equiv_address (operands[0],
3820 copy_addr_to_reg (XEXP (operands[0], 0)));
3822 if (GET_CODE (operands[1]) == MEM
3823 && GET_CODE (XEXP (operands[1], 0)) != REG
3824 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3825 && ! reload_in_progress)
3827 = replace_equiv_address (operands[1],
3828 copy_addr_to_reg (XEXP (operands[1], 0)));
3831 /* Emit a move from SOURCE to DEST in mode MODE. */
3833 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3837 operands[1] = source;
3839 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3840 if (GET_CODE (operands[1]) == CONST_DOUBLE
3841 && ! FLOAT_MODE_P (mode)
3842 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3844 /* FIXME. This should never happen. */
3845 /* Since it seems that it does, do the safe thing and convert
3847 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3849 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3850 || FLOAT_MODE_P (mode)
3851 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3852 || CONST_DOUBLE_LOW (operands[1]) < 0)
3853 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3854 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3856 /* Check if GCC is setting up a block move that will end up using FP
3857 registers as temporaries. We must make sure this is acceptable. */
3858 if (GET_CODE (operands[0]) == MEM
3859 && GET_CODE (operands[1]) == MEM
3861 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3862 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3863 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3864 ? 32 : MEM_ALIGN (operands[0])))
3865 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3867 : MEM_ALIGN (operands[1]))))
3868 && ! MEM_VOLATILE_P (operands [0])
3869 && ! MEM_VOLATILE_P (operands [1]))
3871 emit_move_insn (adjust_address (operands[0], SImode, 0),
3872 adjust_address (operands[1], SImode, 0));
3873 emit_move_insn (adjust_address (operands[0], SImode, 4),
3874 adjust_address (operands[1], SImode, 4));
3878 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3879 && !gpc_reg_operand (operands[1], mode))
3880 operands[1] = force_reg (mode, operands[1]);
3882 if (mode == SFmode && ! TARGET_POWERPC
3883 && TARGET_HARD_FLOAT && TARGET_FPRS
3884 && GET_CODE (operands[0]) == MEM)
3888 if (reload_in_progress || reload_completed)
3889 regnum = true_regnum (operands[1]);
3890 else if (GET_CODE (operands[1]) == REG)
3891 regnum = REGNO (operands[1]);
3895 /* If operands[1] is a register, on POWER it may have
3896 double-precision data in it, so truncate it to single
3898 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3901 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3902 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3903 operands[1] = newreg;
3907 /* Recognize the case where operand[1] is a reference to thread-local
3908 data and load its address to a register. */
3909 if (rs6000_tls_referenced_p (operands[1]))
3911 enum tls_model model;
3912 rtx tmp = operands[1];
3915 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3917 addend = XEXP (XEXP (tmp, 0), 1);
3918 tmp = XEXP (XEXP (tmp, 0), 0);
3921 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3922 model = SYMBOL_REF_TLS_MODEL (tmp);
3923 gcc_assert (model != 0);
3925 tmp = rs6000_legitimize_tls_address (tmp, model);
3928 tmp = gen_rtx_PLUS (mode, tmp, addend);
3929 tmp = force_operand (tmp, operands[0]);
3934 /* Handle the case where reload calls us with an invalid address. */
3935 if (reload_in_progress && mode == Pmode
3936 && (! general_operand (operands[1], mode)
3937 || ! nonimmediate_operand (operands[0], mode)))
3940 /* 128-bit constant floating-point values on Darwin should really be
3941 loaded as two parts. */
3942 if (!TARGET_IEEEQUAD
3943 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3944 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3946 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3947 know how to get a DFmode SUBREG of a TFmode. */
3948 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3949 simplify_gen_subreg (DImode, operands[1], mode, 0),
3951 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3952 GET_MODE_SIZE (DImode)),
3953 simplify_gen_subreg (DImode, operands[1], mode,
3954 GET_MODE_SIZE (DImode)),
3959 /* FIXME: In the long term, this switch statement should go away
3960 and be replaced by a sequence of tests based on things like
3966 if (CONSTANT_P (operands[1])
3967 && GET_CODE (operands[1]) != CONST_INT)
3968 operands[1] = force_const_mem (mode, operands[1]);
3972 rs6000_eliminate_indexed_memrefs (operands);
3977 if (CONSTANT_P (operands[1])
3978 && ! easy_fp_constant (operands[1], mode))
3979 operands[1] = force_const_mem (mode, operands[1]);
3990 if (CONSTANT_P (operands[1])
3991 && !easy_vector_constant (operands[1], mode))
3992 operands[1] = force_const_mem (mode, operands[1]);
3997 /* Use default pattern for address of ELF small data */
4000 && DEFAULT_ABI == ABI_V4
4001 && (GET_CODE (operands[1]) == SYMBOL_REF
4002 || GET_CODE (operands[1]) == CONST)
4003 && small_data_operand (operands[1], mode))
4005 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4009 if (DEFAULT_ABI == ABI_V4
4010 && mode == Pmode && mode == SImode
4011 && flag_pic == 1 && got_operand (operands[1], mode))
4013 emit_insn (gen_movsi_got (operands[0], operands[1]));
4017 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4021 && CONSTANT_P (operands[1])
4022 && GET_CODE (operands[1]) != HIGH
4023 && GET_CODE (operands[1]) != CONST_INT)
4025 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4027 /* If this is a function address on -mcall-aixdesc,
4028 convert it to the address of the descriptor. */
4029 if (DEFAULT_ABI == ABI_AIX
4030 && GET_CODE (operands[1]) == SYMBOL_REF
4031 && XSTR (operands[1], 0)[0] == '.')
4033 const char *name = XSTR (operands[1], 0);
4035 while (*name == '.')
4037 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4038 CONSTANT_POOL_ADDRESS_P (new_ref)
4039 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4040 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4041 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4042 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4043 operands[1] = new_ref;
4046 if (DEFAULT_ABI == ABI_DARWIN)
4049 if (MACHO_DYNAMIC_NO_PIC_P)
4051 /* Take care of any required data indirection. */
4052 operands[1] = rs6000_machopic_legitimize_pic_address (
4053 operands[1], mode, operands[0]);
4054 if (operands[0] != operands[1])
4055 emit_insn (gen_rtx_SET (VOIDmode,
4056 operands[0], operands[1]));
4060 emit_insn (gen_macho_high (target, operands[1]));
4061 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4065 emit_insn (gen_elf_high (target, operands[1]));
4066 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4070 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4071 and we have put it in the TOC, we just need to make a TOC-relative
4074 && GET_CODE (operands[1]) == SYMBOL_REF
4075 && constant_pool_expr_p (operands[1])
4076 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4077 get_pool_mode (operands[1])))
4079 operands[1] = create_TOC_reference (operands[1]);
4081 else if (mode == Pmode
4082 && CONSTANT_P (operands[1])
4083 && ((GET_CODE (operands[1]) != CONST_INT
4084 && ! easy_fp_constant (operands[1], mode))
4085 || (GET_CODE (operands[1]) == CONST_INT
4086 && num_insns_constant (operands[1], mode) > 2)
4087 || (GET_CODE (operands[0]) == REG
4088 && FP_REGNO_P (REGNO (operands[0]))))
4089 && GET_CODE (operands[1]) != HIGH
4090 && ! legitimate_constant_pool_address_p (operands[1])
4091 && ! toc_relative_expr_p (operands[1]))
4093 /* Emit a USE operation so that the constant isn't deleted if
4094 expensive optimizations are turned on because nobody
4095 references it. This should only be done for operands that
4096 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4097 This should not be done for operands that contain LABEL_REFs.
4098 For now, we just handle the obvious case. */
4099 if (GET_CODE (operands[1]) != LABEL_REF)
4100 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4103 /* Darwin uses a special PIC legitimizer. */
4104 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4107 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4109 if (operands[0] != operands[1])
4110 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4115 /* If we are to limit the number of things we put in the TOC and
4116 this is a symbol plus a constant we can add in one insn,
4117 just put the symbol in the TOC and add the constant. Don't do
4118 this if reload is in progress. */
4119 if (GET_CODE (operands[1]) == CONST
4120 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4121 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4122 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4123 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4124 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4125 && ! side_effects_p (operands[0]))
4128 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4129 rtx other = XEXP (XEXP (operands[1], 0), 1);
4131 sym = force_reg (mode, sym);
4133 emit_insn (gen_addsi3 (operands[0], sym, other));
4135 emit_insn (gen_adddi3 (operands[0], sym, other));
4139 operands[1] = force_const_mem (mode, operands[1]);
4142 && constant_pool_expr_p (XEXP (operands[1], 0))
4143 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4144 get_pool_constant (XEXP (operands[1], 0)),
4145 get_pool_mode (XEXP (operands[1], 0))))
4148 = gen_const_mem (mode,
4149 create_TOC_reference (XEXP (operands[1], 0)));
4150 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4156 rs6000_eliminate_indexed_memrefs (operands);
4160 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4162 gen_rtx_SET (VOIDmode,
4163 operands[0], operands[1]),
4164 gen_rtx_CLOBBER (VOIDmode,
4165 gen_rtx_SCRATCH (SImode)))));
4174 /* Above, we may have called force_const_mem which may have returned
4175 an invalid address. If we can, fix this up; otherwise, reload will
4176 have to deal with it. */
4177 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4178 operands[1] = validize_mem (operands[1]);
4181 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4184 /* Nonzero if we can use a floating-point register to pass this arg. */
4185 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4186 (SCALAR_FLOAT_MODE_P (MODE) \
4187 && !DECIMAL_FLOAT_MODE_P (MODE) \
4188 && (CUM)->fregno <= FP_ARG_MAX_REG \
4189 && TARGET_HARD_FLOAT && TARGET_FPRS)
4191 /* Nonzero if we can use an AltiVec register to pass this arg. */
4192 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4193 (ALTIVEC_VECTOR_MODE (MODE) \
4194 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4195 && TARGET_ALTIVEC_ABI \
4198 /* Return a nonzero value to say to return the function value in
4199 memory, just as large structures are always returned. TYPE will be
4200 the data type of the value, and FNTYPE will be the type of the
4201 function doing the returning, or @code{NULL} for libcalls.
4203 The AIX ABI for the RS/6000 specifies that all structures are
4204 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4205 specifies that structures <= 8 bytes are returned in r3/r4, but a
4206 draft put them in memory, and GCC used to implement the draft
4207 instead of the final standard. Therefore, aix_struct_return
4208 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4209 compatibility can change DRAFT_V4_STRUCT_RET to override the
4210 default, and -m switches get the final word. See
4211 rs6000_override_options for more details.
4213 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4214 long double support is enabled. These values are returned in memory.
4216 int_size_in_bytes returns -1 for variable size objects, which go in
4217 memory always. The cast to unsigned makes -1 > 8. */
4220 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4222 /* In the darwin64 abi, try to use registers for larger structs
4224 if (rs6000_darwin64_abi
4225 && TREE_CODE (type) == RECORD_TYPE
4226 && int_size_in_bytes (type) > 0)
4228 CUMULATIVE_ARGS valcum;
4232 valcum.fregno = FP_ARG_MIN_REG;
4233 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4234 /* Do a trial code generation as if this were going to be passed
4235 as an argument; if any part goes in memory, we return NULL. */
4236 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4239 /* Otherwise fall through to more conventional ABI rules. */
4242 if (AGGREGATE_TYPE_P (type)
4243 && (aix_struct_return
4244 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4247 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4248 modes only exist for GCC vector types if -maltivec. */
4249 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4250 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4253 /* Return synthetic vectors in memory. */
4254 if (TREE_CODE (type) == VECTOR_TYPE
4255 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4257 static bool warned_for_return_big_vectors = false;
4258 if (!warned_for_return_big_vectors)
4260 warning (0, "GCC vector returned by reference: "
4261 "non-standard ABI extension with no compatibility guarantee");
4262 warned_for_return_big_vectors = true;
4267 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4273 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4274 for a call to a function whose data type is FNTYPE.
4275 For a library call, FNTYPE is 0.
4277 For incoming args we set the number of arguments in the prototype large
4278 so we never return a PARALLEL. */
4281 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4282 rtx libname ATTRIBUTE_UNUSED, int incoming,
4283 int libcall, int n_named_args)
4285 static CUMULATIVE_ARGS zero_cumulative;
4287 *cum = zero_cumulative;
4289 cum->fregno = FP_ARG_MIN_REG;
4290 cum->vregno = ALTIVEC_ARG_MIN_REG;
4291 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4292 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4293 ? CALL_LIBCALL : CALL_NORMAL);
4294 cum->sysv_gregno = GP_ARG_MIN_REG;
4295 cum->stdarg = fntype
4296 && (TYPE_ARG_TYPES (fntype) != 0
4297 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4298 != void_type_node));
4300 cum->nargs_prototype = 0;
4301 if (incoming || cum->prototype)
4302 cum->nargs_prototype = n_named_args;
4304 /* Check for a longcall attribute. */
4305 if ((!fntype && rs6000_default_long_calls)
4307 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4308 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4309 cum->call_cookie |= CALL_LONG;
4311 if (TARGET_DEBUG_ARG)
4313 fprintf (stderr, "\ninit_cumulative_args:");
4316 tree ret_type = TREE_TYPE (fntype);
4317 fprintf (stderr, " ret code = %s,",
4318 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4321 if (cum->call_cookie & CALL_LONG)
4322 fprintf (stderr, " longcall,");
4324 fprintf (stderr, " proto = %d, nargs = %d\n",
4325 cum->prototype, cum->nargs_prototype);
4330 && TARGET_ALTIVEC_ABI
4331 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4333 error ("cannot return value in vector register because"
4334 " altivec instructions are disabled, use -maltivec"
4339 /* Return true if TYPE must be passed on the stack and not in registers. */
4342 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4344 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4345 return must_pass_in_stack_var_size (mode, type);
4347 return must_pass_in_stack_var_size_or_pad (mode, type);
4350 /* If defined, a C expression which determines whether, and in which
4351 direction, to pad out an argument with extra space. The value
4352 should be of type `enum direction': either `upward' to pad above
4353 the argument, `downward' to pad below, or `none' to inhibit
4356 For the AIX ABI structs are always stored left shifted in their
4360 function_arg_padding (enum machine_mode mode, tree type)
4362 #ifndef AGGREGATE_PADDING_FIXED
4363 #define AGGREGATE_PADDING_FIXED 0
4365 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4366 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4369 if (!AGGREGATE_PADDING_FIXED)
4371 /* GCC used to pass structures of the same size as integer types as
4372 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4373 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4374 passed padded downward, except that -mstrict-align further
4375 muddied the water in that multi-component structures of 2 and 4
4376 bytes in size were passed padded upward.
4378 The following arranges for best compatibility with previous
4379 versions of gcc, but removes the -mstrict-align dependency. */
4380 if (BYTES_BIG_ENDIAN)
4382 HOST_WIDE_INT size = 0;
4384 if (mode == BLKmode)
4386 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4387 size = int_size_in_bytes (type);
4390 size = GET_MODE_SIZE (mode);
4392 if (size == 1 || size == 2 || size == 4)
4398 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4400 if (type != 0 && AGGREGATE_TYPE_P (type))
4404 /* Fall back to the default. */
4405 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4408 /* If defined, a C expression that gives the alignment boundary, in bits,
4409 of an argument with the specified mode and type. If it is not defined,
4410 PARM_BOUNDARY is used for all arguments.
4412 V.4 wants long longs to be double word aligned.
4413 Doubleword align SPE vectors.
4414 Quadword align Altivec vectors.
4415 Quadword align large synthetic vector types. */
4418 function_arg_boundary (enum machine_mode mode, tree type)
4420 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4422 else if (SPE_VECTOR_MODE (mode)
4423 || (type && TREE_CODE (type) == VECTOR_TYPE
4424 && int_size_in_bytes (type) >= 8
4425 && int_size_in_bytes (type) < 16))
4427 else if (ALTIVEC_VECTOR_MODE (mode)
4428 || (type && TREE_CODE (type) == VECTOR_TYPE
4429 && int_size_in_bytes (type) >= 16))
4431 else if (rs6000_darwin64_abi && mode == BLKmode
4432 && type && TYPE_ALIGN (type) > 64)
4435 return PARM_BOUNDARY;
4438 /* For a function parm of MODE and TYPE, return the starting word in
4439 the parameter area. NWORDS of the parameter area are already used. */
4442 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4445 unsigned int parm_offset;
4447 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4448 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4449 return nwords + (-(parm_offset + nwords) & align);
4452 /* Compute the size (in words) of a function argument. */
4454 static unsigned long
4455 rs6000_arg_size (enum machine_mode mode, tree type)
4459 if (mode != BLKmode)
4460 size = GET_MODE_SIZE (mode);
4462 size = int_size_in_bytes (type);
4465 return (size + 3) >> 2;
4467 return (size + 7) >> 3;
4470 /* Use this to flush pending int fields. */
4473 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4474 HOST_WIDE_INT bitpos)
4476 unsigned int startbit, endbit;
4477 int intregs, intoffset;
4478 enum machine_mode mode;
4480 if (cum->intoffset == -1)
4483 intoffset = cum->intoffset;
4484 cum->intoffset = -1;
4486 if (intoffset % BITS_PER_WORD != 0)
4488 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4490 if (mode == BLKmode)
4492 /* We couldn't find an appropriate mode, which happens,
4493 e.g., in packed structs when there are 3 bytes to load.
4494 Back intoffset back to the beginning of the word in this
4496 intoffset = intoffset & -BITS_PER_WORD;
4500 startbit = intoffset & -BITS_PER_WORD;
4501 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4502 intregs = (endbit - startbit) / BITS_PER_WORD;
4503 cum->words += intregs;
4506 /* The darwin64 ABI calls for us to recurse down through structs,
4507 looking for elements passed in registers. Unfortunately, we have
4508 to track int register count here also because of misalignments
4509 in powerpc alignment mode. */
4512 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4514 HOST_WIDE_INT startbitpos)
4518 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4519 if (TREE_CODE (f) == FIELD_DECL)
4521 HOST_WIDE_INT bitpos = startbitpos;
4522 tree ftype = TREE_TYPE (f);
4523 enum machine_mode mode = TYPE_MODE (ftype);
4525 if (DECL_SIZE (f) != 0
4526 && host_integerp (bit_position (f), 1))
4527 bitpos += int_bit_position (f);
4529 /* ??? FIXME: else assume zero offset. */
4531 if (TREE_CODE (ftype) == RECORD_TYPE)
4532 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4533 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4535 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4536 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4537 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4539 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4541 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4545 else if (cum->intoffset == -1)
4546 cum->intoffset = bitpos;
4550 /* Update the data in CUM to advance over an argument
4551 of mode MODE and data type TYPE.
4552 (TYPE is null for libcalls where that information may not be available.)
4554 Note that for args passed by reference, function_arg will be called
4555 with MODE and TYPE set to that of the pointer to the arg, not the arg
4559 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4560 tree type, int named, int depth)
4564 /* Only tick off an argument if we're not recursing. */
4566 cum->nargs_prototype--;
4568 if (TARGET_ALTIVEC_ABI
4569 && (ALTIVEC_VECTOR_MODE (mode)
4570 || (type && TREE_CODE (type) == VECTOR_TYPE
4571 && int_size_in_bytes (type) == 16)))
4575 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4578 if (!TARGET_ALTIVEC)
4579 error ("cannot pass argument in vector register because"
4580 " altivec instructions are disabled, use -maltivec"
4583 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4584 even if it is going to be passed in a vector register.
4585 Darwin does the same for variable-argument functions. */
4586 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4587 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4597 /* Vector parameters must be 16-byte aligned. This places
4598 them at 2 mod 4 in terms of words in 32-bit mode, since
4599 the parameter save area starts at offset 24 from the
4600 stack. In 64-bit mode, they just have to start on an
4601 even word, since the parameter save area is 16-byte
4602 aligned. Space for GPRs is reserved even if the argument
4603 will be passed in memory. */
4605 align = (2 - cum->words) & 3;
4607 align = cum->words & 1;
4608 cum->words += align + rs6000_arg_size (mode, type);
4610 if (TARGET_DEBUG_ARG)
4612 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4614 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4615 cum->nargs_prototype, cum->prototype,
4616 GET_MODE_NAME (mode));
4620 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4622 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4625 else if (rs6000_darwin64_abi
4627 && TREE_CODE (type) == RECORD_TYPE
4628 && (size = int_size_in_bytes (type)) > 0)
4630 /* Variable sized types have size == -1 and are
4631 treated as if consisting entirely of ints.
4632 Pad to 16 byte boundary if needed. */
4633 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4634 && (cum->words % 2) != 0)
4636 /* For varargs, we can just go up by the size of the struct. */
4638 cum->words += (size + 7) / 8;
4641 /* It is tempting to say int register count just goes up by
4642 sizeof(type)/8, but this is wrong in a case such as
4643 { int; double; int; } [powerpc alignment]. We have to
4644 grovel through the fields for these too. */
4646 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4647 rs6000_darwin64_record_arg_advance_flush (cum,
4648 size * BITS_PER_UNIT);
4651 else if (DEFAULT_ABI == ABI_V4)
4653 if (TARGET_HARD_FLOAT && TARGET_FPRS
4654 && (mode == SFmode || mode == DFmode
4655 || (mode == TFmode && !TARGET_IEEEQUAD)))
4657 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4658 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4661 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4662 if (mode == DFmode || mode == TFmode)
4663 cum->words += cum->words & 1;
4664 cum->words += rs6000_arg_size (mode, type);
4669 int n_words = rs6000_arg_size (mode, type);
4670 int gregno = cum->sysv_gregno;
4672 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4673 (r7,r8) or (r9,r10). As does any other 2 word item such
4674 as complex int due to a historical mistake. */
4676 gregno += (1 - gregno) & 1;
4678 /* Multi-reg args are not split between registers and stack. */
4679 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4681 /* Long long and SPE vectors are aligned on the stack.
4682 So are other 2 word items such as complex int due to
4683 a historical mistake. */
4685 cum->words += cum->words & 1;
4686 cum->words += n_words;
4689 /* Note: continuing to accumulate gregno past when we've started
4690 spilling to the stack indicates the fact that we've started
4691 spilling to the stack to expand_builtin_saveregs. */
4692 cum->sysv_gregno = gregno + n_words;
4695 if (TARGET_DEBUG_ARG)
4697 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4698 cum->words, cum->fregno);
4699 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4700 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4701 fprintf (stderr, "mode = %4s, named = %d\n",
4702 GET_MODE_NAME (mode), named);
4707 int n_words = rs6000_arg_size (mode, type);
4708 int start_words = cum->words;
4709 int align_words = rs6000_parm_start (mode, type, start_words);
4711 cum->words = align_words + n_words;
4713 if (SCALAR_FLOAT_MODE_P (mode)
4714 && !DECIMAL_FLOAT_MODE_P (mode)
4715 && TARGET_HARD_FLOAT && TARGET_FPRS)
4716 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4718 if (TARGET_DEBUG_ARG)
4720 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4721 cum->words, cum->fregno);
4722 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4723 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4724 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4725 named, align_words - start_words, depth);
4731 spe_build_register_parallel (enum machine_mode mode, int gregno)
4738 r1 = gen_rtx_REG (DImode, gregno);
4739 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4740 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4743 r1 = gen_rtx_REG (DImode, gregno);
4744 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4745 r3 = gen_rtx_REG (DImode, gregno + 2);
4746 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4747 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4754 /* Determine where to put a SIMD argument on the SPE. */
4756 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4759 int gregno = cum->sysv_gregno;
4761 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4762 are passed and returned in a pair of GPRs for ABI compatibility. */
4763 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4765 int n_words = rs6000_arg_size (mode, type);
4767 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4769 gregno += (1 - gregno) & 1;
4771 /* Multi-reg args are not split between registers and stack. */
4772 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4775 return spe_build_register_parallel (mode, gregno);
4779 int n_words = rs6000_arg_size (mode, type);
4781 /* SPE vectors are put in odd registers. */
4782 if (n_words == 2 && (gregno & 1) == 0)
4785 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4788 enum machine_mode m = SImode;
4790 r1 = gen_rtx_REG (m, gregno);
4791 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4792 r2 = gen_rtx_REG (m, gregno + 1);
4793 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4794 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4801 if (gregno <= GP_ARG_MAX_REG)
4802 return gen_rtx_REG (mode, gregno);
4808 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4809 structure between cum->intoffset and bitpos to integer registers. */
4812 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4813 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4815 enum machine_mode mode;
4817 unsigned int startbit, endbit;
4818 int this_regno, intregs, intoffset;
4821 if (cum->intoffset == -1)
4824 intoffset = cum->intoffset;
4825 cum->intoffset = -1;
4827 /* If this is the trailing part of a word, try to only load that
4828 much into the register. Otherwise load the whole register. Note
4829 that in the latter case we may pick up unwanted bits. It's not a
4830 problem at the moment but may wish to revisit. */
4832 if (intoffset % BITS_PER_WORD != 0)
4834 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4836 if (mode == BLKmode)
4838 /* We couldn't find an appropriate mode, which happens,
4839 e.g., in packed structs when there are 3 bytes to load.
4840 Back intoffset back to the beginning of the word in this
4842 intoffset = intoffset & -BITS_PER_WORD;
4849 startbit = intoffset & -BITS_PER_WORD;
4850 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4851 intregs = (endbit - startbit) / BITS_PER_WORD;
4852 this_regno = cum->words + intoffset / BITS_PER_WORD;
4854 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4857 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4861 intoffset /= BITS_PER_UNIT;
4864 regno = GP_ARG_MIN_REG + this_regno;
4865 reg = gen_rtx_REG (mode, regno);
4867 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4870 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4874 while (intregs > 0);
4877 /* Recursive workhorse for the following. */
4880 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4881 HOST_WIDE_INT startbitpos, rtx rvec[],
4886 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4887 if (TREE_CODE (f) == FIELD_DECL)
4889 HOST_WIDE_INT bitpos = startbitpos;
4890 tree ftype = TREE_TYPE (f);
4891 enum machine_mode mode = TYPE_MODE (ftype);
4893 if (DECL_SIZE (f) != 0
4894 && host_integerp (bit_position (f), 1))
4895 bitpos += int_bit_position (f);
4897 /* ??? FIXME: else assume zero offset. */
4899 if (TREE_CODE (ftype) == RECORD_TYPE)
4900 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4901 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4906 case SCmode: mode = SFmode; break;
4907 case DCmode: mode = DFmode; break;
4908 case TCmode: mode = TFmode; break;
4912 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4914 = gen_rtx_EXPR_LIST (VOIDmode,
4915 gen_rtx_REG (mode, cum->fregno++),
4916 GEN_INT (bitpos / BITS_PER_UNIT));
4920 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4922 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4924 = gen_rtx_EXPR_LIST (VOIDmode,
4925 gen_rtx_REG (mode, cum->vregno++),
4926 GEN_INT (bitpos / BITS_PER_UNIT));
4928 else if (cum->intoffset == -1)
4929 cum->intoffset = bitpos;
4933 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4934 the register(s) to be used for each field and subfield of a struct
4935 being passed by value, along with the offset of where the
4936 register's value may be found in the block. FP fields go in FP
4937 register, vector fields go in vector registers, and everything
4938 else goes in int registers, packed as in memory.
4940 This code is also used for function return values. RETVAL indicates
4941 whether this is the case.
4943 Much of this is taken from the SPARC V9 port, which has a similar
4944 calling convention. */
4947 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4948 int named, bool retval)
4950 rtx rvec[FIRST_PSEUDO_REGISTER];
4951 int k = 1, kbase = 1;
4952 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4953 /* This is a copy; modifications are not visible to our caller. */
4954 CUMULATIVE_ARGS copy_cum = *orig_cum;
4955 CUMULATIVE_ARGS *cum = ©_cum;
4957 /* Pad to 16 byte boundary if needed. */
4958 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4959 && (cum->words % 2) != 0)
4966 /* Put entries into rvec[] for individual FP and vector fields, and
4967 for the chunks of memory that go in int regs. Note we start at
4968 element 1; 0 is reserved for an indication of using memory, and
4969 may or may not be filled in below. */
4970 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4971 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4973 /* If any part of the struct went on the stack put all of it there.
4974 This hack is because the generic code for
4975 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4976 parts of the struct are not at the beginning. */
4980 return NULL_RTX; /* doesn't go in registers at all */
4982 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4984 if (k > 1 || cum->use_stack)
4985 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4990 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4993 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4997 rtx rvec[GP_ARG_NUM_REG + 1];
4999 if (align_words >= GP_ARG_NUM_REG)
5002 n_units = rs6000_arg_size (mode, type);
5004 /* Optimize the simple case where the arg fits in one gpr, except in
5005 the case of BLKmode due to assign_parms assuming that registers are
5006 BITS_PER_WORD wide. */
5008 || (n_units == 1 && mode != BLKmode))
5009 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5012 if (align_words + n_units > GP_ARG_NUM_REG)
5013 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5014 using a magic NULL_RTX component.
5015 FIXME: This is not strictly correct. Only some of the arg
5016 belongs in memory, not all of it. However, there isn't any way
5017 to do this currently, apart from building rtx descriptions for
5018 the pieces of memory we want stored. Due to bugs in the generic
5019 code we can't use the normal function_arg_partial_nregs scheme
5020 with the PARALLEL arg description we emit here.
5021 In any case, the code to store the whole arg to memory is often
5022 more efficient than code to store pieces, and we know that space
5023 is available in the right place for the whole arg. */
5024 /* FIXME: This should be fixed since the conversion to
5025 TARGET_ARG_PARTIAL_BYTES. */
5026 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5031 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5032 rtx off = GEN_INT (i++ * 4);
5033 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5035 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5037 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5040 /* Determine where to put an argument to a function.
5041 Value is zero to push the argument on the stack,
5042 or a hard register in which to store the argument.
5044 MODE is the argument's machine mode.
5045 TYPE is the data type of the argument (as a tree).
5046 This is null for libcalls where that information may
5048 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5049 the preceding args and about the function being called. It is
5050 not modified in this routine.
5051 NAMED is nonzero if this argument is a named parameter
5052 (otherwise it is an extra parameter matching an ellipsis).
5054 On RS/6000 the first eight words of non-FP are normally in registers
5055 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5056 Under V.4, the first 8 FP args are in registers.
5058 If this is floating-point and no prototype is specified, we use
5059 both an FP and integer register (or possibly FP reg and stack). Library
5060 functions (when CALL_LIBCALL is set) always have the proper types for args,
5061 so we can pass the FP value just in one register. emit_library_function
5062 doesn't support PARALLEL anyway.
5064 Note that for args passed by reference, function_arg will be called
5065 with MODE and TYPE set to that of the pointer to the arg, not the arg
5069 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5070 tree type, int named)
5072 enum rs6000_abi abi = DEFAULT_ABI;
5074 /* Return a marker to indicate whether CR1 needs to set or clear the
5075 bit that V.4 uses to say fp args were passed in registers.
5076 Assume that we don't need the marker for software floating point,
5077 or compiler generated library calls. */
5078 if (mode == VOIDmode)
5081 && (cum->call_cookie & CALL_LIBCALL) == 0
5083 || (cum->nargs_prototype < 0
5084 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5086 /* For the SPE, we need to crxor CR6 always. */
5088 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5089 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5090 return GEN_INT (cum->call_cookie
5091 | ((cum->fregno == FP_ARG_MIN_REG)
5092 ? CALL_V4_SET_FP_ARGS
5093 : CALL_V4_CLEAR_FP_ARGS));
5096 return GEN_INT (cum->call_cookie);
5099 if (rs6000_darwin64_abi && mode == BLKmode
5100 && TREE_CODE (type) == RECORD_TYPE)
5102 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5103 if (rslt != NULL_RTX)
5105 /* Else fall through to usual handling. */
5108 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5109 if (TARGET_64BIT && ! cum->prototype)
5111 /* Vector parameters get passed in vector register
5112 and also in GPRs or memory, in absence of prototype. */
5115 align_words = (cum->words + 1) & ~1;
5117 if (align_words >= GP_ARG_NUM_REG)
5123 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5125 return gen_rtx_PARALLEL (mode,
5127 gen_rtx_EXPR_LIST (VOIDmode,
5129 gen_rtx_EXPR_LIST (VOIDmode,
5130 gen_rtx_REG (mode, cum->vregno),
5134 return gen_rtx_REG (mode, cum->vregno);
5135 else if (TARGET_ALTIVEC_ABI
5136 && (ALTIVEC_VECTOR_MODE (mode)
5137 || (type && TREE_CODE (type) == VECTOR_TYPE
5138 && int_size_in_bytes (type) == 16)))
5140 if (named || abi == ABI_V4)
5144 /* Vector parameters to varargs functions under AIX or Darwin
5145 get passed in memory and possibly also in GPRs. */
5146 int align, align_words, n_words;
5147 enum machine_mode part_mode;
5149 /* Vector parameters must be 16-byte aligned. This places them at
5150 2 mod 4 in terms of words in 32-bit mode, since the parameter
5151 save area starts at offset 24 from the stack. In 64-bit mode,
5152 they just have to start on an even word, since the parameter
5153 save area is 16-byte aligned. */
5155 align = (2 - cum->words) & 3;
5157 align = cum->words & 1;
5158 align_words = cum->words + align;
5160 /* Out of registers? Memory, then. */
5161 if (align_words >= GP_ARG_NUM_REG)
5164 if (TARGET_32BIT && TARGET_POWERPC64)
5165 return rs6000_mixed_function_arg (mode, type, align_words);
5167 /* The vector value goes in GPRs. Only the part of the
5168 value in GPRs is reported here. */
5170 n_words = rs6000_arg_size (mode, type);
5171 if (align_words + n_words > GP_ARG_NUM_REG)
5172 /* Fortunately, there are only two possibilities, the value
5173 is either wholly in GPRs or half in GPRs and half not. */
5176 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5179 else if (TARGET_SPE_ABI && TARGET_SPE
5180 && (SPE_VECTOR_MODE (mode)
5181 || (TARGET_E500_DOUBLE && (mode == DFmode
5182 || mode == DCmode))))
5183 return rs6000_spe_function_arg (cum, mode, type);
5185 else if (abi == ABI_V4)
5187 if (TARGET_HARD_FLOAT && TARGET_FPRS
5188 && (mode == SFmode || mode == DFmode
5189 || (mode == TFmode && !TARGET_IEEEQUAD)))
5191 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5192 return gen_rtx_REG (mode, cum->fregno);
5198 int n_words = rs6000_arg_size (mode, type);
5199 int gregno = cum->sysv_gregno;
5201 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5202 (r7,r8) or (r9,r10). As does any other 2 word item such
5203 as complex int due to a historical mistake. */
5205 gregno += (1 - gregno) & 1;
5207 /* Multi-reg args are not split between registers and stack. */
5208 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5211 if (TARGET_32BIT && TARGET_POWERPC64)
5212 return rs6000_mixed_function_arg (mode, type,
5213 gregno - GP_ARG_MIN_REG);
5214 return gen_rtx_REG (mode, gregno);
5219 int align_words = rs6000_parm_start (mode, type, cum->words);
5221 if (USE_FP_FOR_ARG_P (cum, mode, type))
5223 rtx rvec[GP_ARG_NUM_REG + 1];
5227 enum machine_mode fmode = mode;
5228 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5230 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5232 /* Currently, we only ever need one reg here because complex
5233 doubles are split. */
5234 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5236 /* Long double split over regs and memory. */
5240 /* Do we also need to pass this arg in the parameter save
5243 && (cum->nargs_prototype <= 0
5244 || (DEFAULT_ABI == ABI_AIX
5246 && align_words >= GP_ARG_NUM_REG)));
5248 if (!needs_psave && mode == fmode)
5249 return gen_rtx_REG (fmode, cum->fregno);
5254 /* Describe the part that goes in gprs or the stack.
5255 This piece must come first, before the fprs. */
5256 if (align_words < GP_ARG_NUM_REG)
5258 unsigned long n_words = rs6000_arg_size (mode, type);
5260 if (align_words + n_words > GP_ARG_NUM_REG
5261 || (TARGET_32BIT && TARGET_POWERPC64))
5263 /* If this is partially on the stack, then we only
5264 include the portion actually in registers here. */
5265 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5268 if (align_words + n_words > GP_ARG_NUM_REG
5269 && (TARGET_32BIT && TARGET_POWERPC64))
5270 /* Not all of the arg fits in gprs. Say that it
5271 goes in memory too, using a magic NULL_RTX
5272 component. Also see comment in
5273 rs6000_mixed_function_arg for why the normal
5274 function_arg_partial_nregs scheme doesn't work
5276 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5280 r = gen_rtx_REG (rmode,
5281 GP_ARG_MIN_REG + align_words);
5282 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5283 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5285 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5289 /* The whole arg fits in gprs. */
5290 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5291 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5295 /* It's entirely in memory. */
5296 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5299 /* Describe where this piece goes in the fprs. */
5300 r = gen_rtx_REG (fmode, cum->fregno);
5301 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5303 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5305 else if (align_words < GP_ARG_NUM_REG)
5307 if (TARGET_32BIT && TARGET_POWERPC64)
5308 return rs6000_mixed_function_arg (mode, type, align_words);
5310 if (mode == BLKmode)
5313 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5320 /* For an arg passed partly in registers and partly in memory, this is
5321 the number of bytes passed in registers. For args passed entirely in
5322 registers or entirely in memory, zero. When an arg is described by a
5323 PARALLEL, perhaps using more than one register type, this function
5324 returns the number of bytes used by the first element of the PARALLEL. */
5327 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5328 tree type, bool named)
5333 if (DEFAULT_ABI == ABI_V4)
5336 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5337 && cum->nargs_prototype >= 0)
5340 /* In this complicated case we just disable the partial_nregs code. */
5341 if (rs6000_darwin64_abi && mode == BLKmode
5342 && TREE_CODE (type) == RECORD_TYPE
5343 && int_size_in_bytes (type) > 0)
5346 align_words = rs6000_parm_start (mode, type, cum->words);
5348 if (USE_FP_FOR_ARG_P (cum, mode, type)
5349 /* If we are passing this arg in the fixed parameter save area
5350 (gprs or memory) as well as fprs, then this function should
5351 return the number of bytes passed in the parameter save area
5352 rather than bytes passed in fprs. */
5354 && (cum->nargs_prototype <= 0
5355 || (DEFAULT_ABI == ABI_AIX
5357 && align_words >= GP_ARG_NUM_REG))))
5359 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5360 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5361 else if (cum->nargs_prototype >= 0)
5365 if (align_words < GP_ARG_NUM_REG
5366 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5367 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5369 if (ret != 0 && TARGET_DEBUG_ARG)
5370 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5375 /* A C expression that indicates when an argument must be passed by
5376 reference. If nonzero for an argument, a copy of that argument is
5377 made in memory and a pointer to the argument is passed instead of
5378 the argument itself. The pointer is passed in whatever way is
5379 appropriate for passing a pointer to that type.
5381 Under V.4, aggregates and long double are passed by reference.
5383 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5384 reference unless the AltiVec vector extension ABI is in force.
5386 As an extension to all ABIs, variable sized types are passed by
5390 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5391 enum machine_mode mode, tree type,
5392 bool named ATTRIBUTE_UNUSED)
5394 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5396 if (TARGET_DEBUG_ARG)
5397 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5404 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5406 if (TARGET_DEBUG_ARG)
5407 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5411 if (int_size_in_bytes (type) < 0)
5413 if (TARGET_DEBUG_ARG)
5414 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5418 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5419 modes only exist for GCC vector types if -maltivec. */
5420 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5422 if (TARGET_DEBUG_ARG)
5423 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5427 /* Pass synthetic vectors in memory. */
5428 if (TREE_CODE (type) == VECTOR_TYPE
5429 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5431 static bool warned_for_pass_big_vectors = false;
5432 if (TARGET_DEBUG_ARG)
5433 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5434 if (!warned_for_pass_big_vectors)
5436 warning (0, "GCC vector passed by reference: "
5437 "non-standard ABI extension with no compatibility guarantee");
5438 warned_for_pass_big_vectors = true;
5447 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5450 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5455 for (i = 0; i < nregs; i++)
5457 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5458 if (reload_completed)
5460 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5463 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5464 i * GET_MODE_SIZE (reg_mode));
5467 tem = replace_equiv_address (tem, XEXP (tem, 0));
5471 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5475 /* Perform any needed actions needed for a function that is receiving a
5476 variable number of arguments.
5480 MODE and TYPE are the mode and type of the current parameter.
5482 PRETEND_SIZE is a variable that should be set to the amount of stack
5483 that must be pushed by the prolog to pretend that our caller pushed
5486 Normally, this macro will push all remaining incoming registers on the
5487 stack and set PRETEND_SIZE to the length of the registers pushed. */
5490 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5491 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5494 CUMULATIVE_ARGS next_cum;
5495 int reg_size = TARGET_32BIT ? 4 : 8;
5496 rtx save_area = NULL_RTX, mem;
5497 int first_reg_offset, set;
5499 /* Skip the last named argument. */
5501 function_arg_advance (&next_cum, mode, type, 1, 0);
5503 if (DEFAULT_ABI == ABI_V4)
5505 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5509 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5510 HOST_WIDE_INT offset = 0;
5512 /* Try to optimize the size of the varargs save area.
5513 The ABI requires that ap.reg_save_area is doubleword
5514 aligned, but we don't need to allocate space for all
5515 the bytes, only those to which we actually will save
5517 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5518 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5519 if (TARGET_HARD_FLOAT && TARGET_FPRS
5520 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5521 && cfun->va_list_fpr_size)
5524 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5525 * UNITS_PER_FP_WORD;
5526 if (cfun->va_list_fpr_size
5527 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5528 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5530 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5531 * UNITS_PER_FP_WORD;
5535 offset = -((first_reg_offset * reg_size) & ~7);
5536 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5538 gpr_reg_num = cfun->va_list_gpr_size;
5539 if (reg_size == 4 && (first_reg_offset & 1))
5542 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5545 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5547 - (int) (GP_ARG_NUM_REG * reg_size);
5549 if (gpr_size + fpr_size)
5552 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5553 gcc_assert (GET_CODE (reg_save_area) == MEM);
5554 reg_save_area = XEXP (reg_save_area, 0);
5555 if (GET_CODE (reg_save_area) == PLUS)
5557 gcc_assert (XEXP (reg_save_area, 0)
5558 == virtual_stack_vars_rtx);
5559 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5560 offset += INTVAL (XEXP (reg_save_area, 1));
5563 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5566 cfun->machine->varargs_save_offset = offset;
5567 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5572 first_reg_offset = next_cum.words;
5573 save_area = virtual_incoming_args_rtx;
5575 if (targetm.calls.must_pass_in_stack (mode, type))
5576 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5579 set = get_varargs_alias_set ();
5580 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5581 && cfun->va_list_gpr_size)
5583 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5585 if (va_list_gpr_counter_field)
5587 /* V4 va_list_gpr_size counts number of registers needed. */
5588 if (nregs > cfun->va_list_gpr_size)
5589 nregs = cfun->va_list_gpr_size;
5593 /* char * va_list instead counts number of bytes needed. */
5594 if (nregs > cfun->va_list_gpr_size / reg_size)
5595 nregs = cfun->va_list_gpr_size / reg_size;
5598 mem = gen_rtx_MEM (BLKmode,
5599 plus_constant (save_area,
5600 first_reg_offset * reg_size));
5601 MEM_NOTRAP_P (mem) = 1;
5602 set_mem_alias_set (mem, set);
5603 set_mem_align (mem, BITS_PER_WORD);
5605 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5609 /* Save FP registers if needed. */
5610 if (DEFAULT_ABI == ABI_V4
5611 && TARGET_HARD_FLOAT && TARGET_FPRS
5613 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5614 && cfun->va_list_fpr_size)
5616 int fregno = next_cum.fregno, nregs;
5617 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5618 rtx lab = gen_label_rtx ();
5619 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5620 * UNITS_PER_FP_WORD);
5623 (gen_rtx_SET (VOIDmode,
5625 gen_rtx_IF_THEN_ELSE (VOIDmode,
5626 gen_rtx_NE (VOIDmode, cr1,
5628 gen_rtx_LABEL_REF (VOIDmode, lab),
5632 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5633 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5635 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5636 MEM_NOTRAP_P (mem) = 1;
5637 set_mem_alias_set (mem, set);
5638 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5639 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5646 /* Create the va_list data type. */
5649 rs6000_build_builtin_va_list (void)
5651 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5653 /* For AIX, prefer 'char *' because that's what the system
5654 header files like. */
5655 if (DEFAULT_ABI != ABI_V4)
5656 return build_pointer_type (char_type_node);
5658 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5659 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5661 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5662 unsigned_char_type_node);
5663 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5664 unsigned_char_type_node);
5665 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5667 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5668 short_unsigned_type_node);
5669 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5671 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5674 va_list_gpr_counter_field = f_gpr;
5675 va_list_fpr_counter_field = f_fpr;
5677 DECL_FIELD_CONTEXT (f_gpr) = record;
5678 DECL_FIELD_CONTEXT (f_fpr) = record;
5679 DECL_FIELD_CONTEXT (f_res) = record;
5680 DECL_FIELD_CONTEXT (f_ovf) = record;
5681 DECL_FIELD_CONTEXT (f_sav) = record;
5683 TREE_CHAIN (record) = type_decl;
5684 TYPE_NAME (record) = type_decl;
5685 TYPE_FIELDS (record) = f_gpr;
5686 TREE_CHAIN (f_gpr) = f_fpr;
5687 TREE_CHAIN (f_fpr) = f_res;
5688 TREE_CHAIN (f_res) = f_ovf;
5689 TREE_CHAIN (f_ovf) = f_sav;
5691 layout_type (record);
5693 /* The correct type is an array type of one element. */
5694 return build_array_type (record, build_index_type (size_zero_node));
5697 /* Implement va_start. */
5700 rs6000_va_start (tree valist, rtx nextarg)
5702 HOST_WIDE_INT words, n_gpr, n_fpr;
5703 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5704 tree gpr, fpr, ovf, sav, t;
5706 /* Only SVR4 needs something special. */
5707 if (DEFAULT_ABI != ABI_V4)
5709 std_expand_builtin_va_start (valist, nextarg);
5713 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5714 f_fpr = TREE_CHAIN (f_gpr);
5715 f_res = TREE_CHAIN (f_fpr);
5716 f_ovf = TREE_CHAIN (f_res);
5717 f_sav = TREE_CHAIN (f_ovf);
5719 valist = build_va_arg_indirect_ref (valist);
5720 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5721 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5722 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5723 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5725 /* Count number of gp and fp argument registers used. */
5726 words = current_function_args_info.words;
5727 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5729 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5732 if (TARGET_DEBUG_ARG)
5733 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5734 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5735 words, n_gpr, n_fpr);
5737 if (cfun->va_list_gpr_size)
5739 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5740 build_int_cst (NULL_TREE, n_gpr));
5741 TREE_SIDE_EFFECTS (t) = 1;
5742 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5745 if (cfun->va_list_fpr_size)
5747 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5748 build_int_cst (NULL_TREE, n_fpr));
5749 TREE_SIDE_EFFECTS (t) = 1;
5750 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5753 /* Find the overflow area. */
5754 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5756 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5757 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5758 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5759 TREE_SIDE_EFFECTS (t) = 1;
5760 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5762 /* If there were no va_arg invocations, don't set up the register
5764 if (!cfun->va_list_gpr_size
5765 && !cfun->va_list_fpr_size
5766 && n_gpr < GP_ARG_NUM_REG
5767 && n_fpr < FP_ARG_V4_MAX_REG)
5770 /* Find the register save area. */
5771 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5772 if (cfun->machine->varargs_save_offset)
5773 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5774 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5775 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5776 TREE_SIDE_EFFECTS (t) = 1;
5777 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5780 /* Implement va_arg. */
5783 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5785 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5786 tree gpr, fpr, ovf, sav, reg, t, u;
5787 int size, rsize, n_reg, sav_ofs, sav_scale;
5788 tree lab_false, lab_over, addr;
5790 tree ptrtype = build_pointer_type (type);
5792 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5794 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5795 return build_va_arg_indirect_ref (t);
5798 if (DEFAULT_ABI != ABI_V4)
5800 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5802 tree elem_type = TREE_TYPE (type);
5803 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5804 int elem_size = GET_MODE_SIZE (elem_mode);
5806 if (elem_size < UNITS_PER_WORD)
5808 tree real_part, imag_part;
5809 tree post = NULL_TREE;
5811 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5813 /* Copy the value into a temporary, lest the formal temporary
5814 be reused out from under us. */
5815 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5816 append_to_statement_list (post, pre_p);
5818 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5821 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5825 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5828 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5829 f_fpr = TREE_CHAIN (f_gpr);
5830 f_res = TREE_CHAIN (f_fpr);
5831 f_ovf = TREE_CHAIN (f_res);
5832 f_sav = TREE_CHAIN (f_ovf);
5834 valist = build_va_arg_indirect_ref (valist);
5835 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5836 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5837 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5838 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5840 size = int_size_in_bytes (type);
5841 rsize = (size + 3) / 4;
5844 if (TARGET_HARD_FLOAT && TARGET_FPRS
5845 && (TYPE_MODE (type) == SFmode
5846 || TYPE_MODE (type) == DFmode
5847 || TYPE_MODE (type) == TFmode))
5849 /* FP args go in FP registers, if present. */
5851 n_reg = (size + 7) / 8;
5854 if (TYPE_MODE (type) != SFmode)
5859 /* Otherwise into GP registers. */
5868 /* Pull the value out of the saved registers.... */
5871 addr = create_tmp_var (ptr_type_node, "addr");
5872 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5874 /* AltiVec vectors never go in registers when -mabi=altivec. */
5875 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5879 lab_false = create_artificial_label ();
5880 lab_over = create_artificial_label ();
5882 /* Long long and SPE vectors are aligned in the registers.
5883 As are any other 2 gpr item such as complex int due to a
5884 historical mistake. */
5886 if (n_reg == 2 && reg == gpr)
5888 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5889 size_int (n_reg - 1));
5890 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5893 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5894 t = build2 (GE_EXPR, boolean_type_node, u, t);
5895 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5896 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5897 gimplify_and_add (t, pre_p);
5901 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5903 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5904 u = build1 (CONVERT_EXPR, integer_type_node, u);
5905 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5906 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5908 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5909 gimplify_and_add (t, pre_p);
5911 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5912 gimplify_and_add (t, pre_p);
5914 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5915 append_to_statement_list (t, pre_p);
5919 /* Ensure that we don't find any more args in regs.
5920 Alignment has taken care of the n_reg == 2 case. */
5921 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5922 gimplify_and_add (t, pre_p);
5926 /* ... otherwise out of the overflow area. */
5928 /* Care for on-stack alignment if needed. */
5932 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5933 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5934 build_int_cst (NULL_TREE, -align));
5936 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5938 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5939 gimplify_and_add (u, pre_p);
5941 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5942 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5943 gimplify_and_add (t, pre_p);
5947 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5948 append_to_statement_list (t, pre_p);
5951 addr = fold_convert (ptrtype, addr);
5952 return build_va_arg_indirect_ref (addr);
5958 def_builtin (int mask, const char *name, tree type, int code)
5960 if (mask & target_flags)
5962 if (rs6000_builtin_decls[code])
5965 rs6000_builtin_decls[code] =
5966 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5971 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5973 static const struct builtin_description bdesc_3arg[] =
5975 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5976 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5977 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5978 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5979 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5980 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5981 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5982 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5983 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5984 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5985 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5986 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5987 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5988 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5989 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5990 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5991 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5992 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5993 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5994 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5995 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5996 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5997 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5999 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6000 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6001 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6002 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6003 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6004 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6005 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6006 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6007 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6008 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6009 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6010 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6011 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6012 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6013 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6016 /* DST operations: void foo (void *, const int, const char). */
6018 static const struct builtin_description bdesc_dst[] =
6020 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6021 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6025 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6026 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6027 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6028 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6031 /* Simple binary operations: VECc = foo (VECa, VECb). */
6033 static struct builtin_description bdesc_2arg[] =
6035 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6036 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6037 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6038 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6039 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6040 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6041 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6042 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6043 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6044 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6045 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6046 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6047 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6048 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6049 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6050 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6053 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6054 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6055 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6056 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6057 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6058 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6059 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6060 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6061 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6062 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6063 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6064 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6065 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6066 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6067 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6068 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6069 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6070 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6071 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6072 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6073 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6074 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6075 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6076 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6077 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6078 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6079 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6080 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6081 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6082 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6083 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6084 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6085 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6086 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6087 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6088 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6089 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6090 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6094 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6096 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6097 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6099 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6100 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6101 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6102 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6103 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6104 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6105 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6106 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6107 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6108 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6109 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6110 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6111 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6112 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6113 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6114 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6115 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6116 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6117 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6118 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6119 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6120 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6121 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6122 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6123 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6124 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6125 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6126 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6127 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6128 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6129 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6130 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6131 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6132 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6133 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6134 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6136 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6140 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6142 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6143 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6145 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6149 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6275 /* Place holder, leave as first spe builtin. */
6276 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6277 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6278 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6279 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6280 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6281 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6282 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6283 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6284 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6285 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6286 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6287 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6288 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6289 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6290 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6291 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6292 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6293 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6294 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6295 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6296 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6297 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6298 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6299 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6300 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6301 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6302 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6303 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6304 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6305 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6306 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6307 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6308 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6309 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6310 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6311 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6312 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6313 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6314 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6315 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6316 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6317 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6318 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6319 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6320 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6321 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6322 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6323 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6324 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6325 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6326 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6327 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6328 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6329 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6330 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6331 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6332 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6333 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6334 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6335 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6336 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6337 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6338 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6339 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6340 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6341 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6342 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6343 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6344 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6345 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6346 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6347 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6348 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6349 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6350 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6351 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6352 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6353 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6354 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6355 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6356 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6357 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6358 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6359 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6360 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6361 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6362 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6363 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6364 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6365 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6366 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6367 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6368 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6369 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6370 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6371 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6372 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6373 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6374 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6375 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6376 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6377 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6378 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6379 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6380 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6381 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6382 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6383 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6384 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6386 /* SPE binary operations expecting a 5-bit unsigned literal. */
6387 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6389 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6390 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6391 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6392 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6393 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6394 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6395 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6396 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6397 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6398 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6399 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6400 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6401 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6402 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6403 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6404 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6405 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6406 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6407 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6408 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6409 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6410 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6411 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6412 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6413 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6414 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6416 /* Place-holder. Leave as last binary SPE builtin. */
6417 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6420 /* AltiVec predicates. */
6422 struct builtin_description_predicates
6424 const unsigned int mask;
6425 const enum insn_code icode;
6427 const char *const name;
6428 const enum rs6000_builtins code;
6431 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6433 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6434 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6435 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6436 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6437 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6438 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6439 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6440 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6441 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6442 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6443 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6444 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6445 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6447 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6448 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6449 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6452 /* SPE predicates. */
6453 static struct builtin_description bdesc_spe_predicates[] =
6455 /* Place-holder. Leave as first. */
6456 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6457 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6458 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6459 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6460 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6461 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6462 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6463 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6464 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6465 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6466 /* Place-holder. Leave as last. */
6467 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6470 /* SPE evsel predicates. */
6471 static struct builtin_description bdesc_spe_evsel[] =
6473 /* Place-holder. Leave as first. */
6474 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6475 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6476 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6477 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6478 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6479 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6480 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6481 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6482 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6483 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6484 /* Place-holder. Leave as last. */
6485 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6488 /* ABS* operations. */
6490 static const struct builtin_description bdesc_abs[] =
6492 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6493 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6494 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6495 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6496 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6497 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6498 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6501 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6504 static struct builtin_description bdesc_1arg[] =
6506 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6507 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6508 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6509 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6510 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6511 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6512 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6513 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6514 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6515 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6516 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6520 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6521 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6522 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6524 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6525 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6526 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6527 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6528 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6529 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6530 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6531 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6532 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6533 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6534 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6535 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6536 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6537 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6538 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6539 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6540 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6541 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6542 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6544 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6545 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6546 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6547 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6548 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6549 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6550 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6551 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6552 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6553 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6554 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6555 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6556 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6557 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6558 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6559 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6560 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6561 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6562 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6563 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6564 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6565 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6566 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6567 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6568 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6569 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6570 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6571 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6572 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6573 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6575 /* Place-holder. Leave as last unary SPE builtin. */
6576 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6580 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6583 tree arg0 = TREE_VALUE (arglist);
6584 rtx op0 = expand_normal (arg0);
6585 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6586 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6588 if (icode == CODE_FOR_nothing)
6589 /* Builtin not supported on this processor. */
6592 /* If we got invalid arguments bail out before generating bad rtl. */
6593 if (arg0 == error_mark_node)
6596 if (icode == CODE_FOR_altivec_vspltisb
6597 || icode == CODE_FOR_altivec_vspltish
6598 || icode == CODE_FOR_altivec_vspltisw
6599 || icode == CODE_FOR_spe_evsplatfi
6600 || icode == CODE_FOR_spe_evsplati)
6602 /* Only allow 5-bit *signed* literals. */
6603 if (GET_CODE (op0) != CONST_INT
6604 || INTVAL (op0) > 15
6605 || INTVAL (op0) < -16)
6607 error ("argument 1 must be a 5-bit signed literal");
6613 || GET_MODE (target) != tmode
6614 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6615 target = gen_reg_rtx (tmode);
6617 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6618 op0 = copy_to_mode_reg (mode0, op0);
6620 pat = GEN_FCN (icode) (target, op0);
6629 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6631 rtx pat, scratch1, scratch2;
6632 tree arg0 = TREE_VALUE (arglist);
6633 rtx op0 = expand_normal (arg0);
6634 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6635 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6637 /* If we have invalid arguments, bail out before generating bad rtl. */
6638 if (arg0 == error_mark_node)
6642 || GET_MODE (target) != tmode
6643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6644 target = gen_reg_rtx (tmode);
6646 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6647 op0 = copy_to_mode_reg (mode0, op0);
6649 scratch1 = gen_reg_rtx (mode0);
6650 scratch2 = gen_reg_rtx (mode0);
6652 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6661 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6664 tree arg0 = TREE_VALUE (arglist);
6665 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6666 rtx op0 = expand_normal (arg0);
6667 rtx op1 = expand_normal (arg1);
6668 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6669 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6670 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6672 if (icode == CODE_FOR_nothing)
6673 /* Builtin not supported on this processor. */
6676 /* If we got invalid arguments bail out before generating bad rtl. */
6677 if (arg0 == error_mark_node || arg1 == error_mark_node)
6680 if (icode == CODE_FOR_altivec_vcfux
6681 || icode == CODE_FOR_altivec_vcfsx
6682 || icode == CODE_FOR_altivec_vctsxs
6683 || icode == CODE_FOR_altivec_vctuxs
6684 || icode == CODE_FOR_altivec_vspltb
6685 || icode == CODE_FOR_altivec_vsplth
6686 || icode == CODE_FOR_altivec_vspltw
6687 || icode == CODE_FOR_spe_evaddiw
6688 || icode == CODE_FOR_spe_evldd
6689 || icode == CODE_FOR_spe_evldh
6690 || icode == CODE_FOR_spe_evldw
6691 || icode == CODE_FOR_spe_evlhhesplat
6692 || icode == CODE_FOR_spe_evlhhossplat
6693 || icode == CODE_FOR_spe_evlhhousplat
6694 || icode == CODE_FOR_spe_evlwhe
6695 || icode == CODE_FOR_spe_evlwhos
6696 || icode == CODE_FOR_spe_evlwhou
6697 || icode == CODE_FOR_spe_evlwhsplat
6698 || icode == CODE_FOR_spe_evlwwsplat
6699 || icode == CODE_FOR_spe_evrlwi
6700 || icode == CODE_FOR_spe_evslwi
6701 || icode == CODE_FOR_spe_evsrwis
6702 || icode == CODE_FOR_spe_evsubifw
6703 || icode == CODE_FOR_spe_evsrwiu)
6705 /* Only allow 5-bit unsigned literals. */
6707 if (TREE_CODE (arg1) != INTEGER_CST
6708 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6710 error ("argument 2 must be a 5-bit unsigned literal");
6716 || GET_MODE (target) != tmode
6717 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6718 target = gen_reg_rtx (tmode);
6720 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6721 op0 = copy_to_mode_reg (mode0, op0);
6722 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6723 op1 = copy_to_mode_reg (mode1, op1);
6725 pat = GEN_FCN (icode) (target, op0, op1);
6734 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6735 tree arglist, rtx target)
6738 tree cr6_form = TREE_VALUE (arglist);
6739 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6740 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6741 rtx op0 = expand_normal (arg0);
6742 rtx op1 = expand_normal (arg1);
6743 enum machine_mode tmode = SImode;
6744 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6745 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6748 if (TREE_CODE (cr6_form) != INTEGER_CST)
6750 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6754 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6756 gcc_assert (mode0 == mode1);
6758 /* If we have invalid arguments, bail out before generating bad rtl. */
6759 if (arg0 == error_mark_node || arg1 == error_mark_node)
6763 || GET_MODE (target) != tmode
6764 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6765 target = gen_reg_rtx (tmode);
6767 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6768 op0 = copy_to_mode_reg (mode0, op0);
6769 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6770 op1 = copy_to_mode_reg (mode1, op1);
6772 scratch = gen_reg_rtx (mode0);
6774 pat = GEN_FCN (icode) (scratch, op0, op1,
6775 gen_rtx_SYMBOL_REF (Pmode, opcode));
6780 /* The vec_any* and vec_all* predicates use the same opcodes for two
6781 different operations, but the bits in CR6 will be different
6782 depending on what information we want. So we have to play tricks
6783 with CR6 to get the right bits out.
6785 If you think this is disgusting, look at the specs for the
6786 AltiVec predicates. */
6788 switch (cr6_form_int)
6791 emit_insn (gen_cr6_test_for_zero (target));
6794 emit_insn (gen_cr6_test_for_zero_reverse (target));
6797 emit_insn (gen_cr6_test_for_lt (target));
6800 emit_insn (gen_cr6_test_for_lt_reverse (target));
6803 error ("argument 1 of __builtin_altivec_predicate is out of range");
6811 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6814 tree arg0 = TREE_VALUE (arglist);
6815 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6816 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6817 enum machine_mode mode0 = Pmode;
6818 enum machine_mode mode1 = Pmode;
6819 rtx op0 = expand_normal (arg0);
6820 rtx op1 = expand_normal (arg1);
6822 if (icode == CODE_FOR_nothing)
6823 /* Builtin not supported on this processor. */
6826 /* If we got invalid arguments bail out before generating bad rtl. */
6827 if (arg0 == error_mark_node || arg1 == error_mark_node)
6831 || GET_MODE (target) != tmode
6832 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6833 target = gen_reg_rtx (tmode);
6835 op1 = copy_to_mode_reg (mode1, op1);
6837 if (op0 == const0_rtx)
6839 addr = gen_rtx_MEM (tmode, op1);
6843 op0 = copy_to_mode_reg (mode0, op0);
6844 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6847 pat = GEN_FCN (icode) (target, addr);
6857 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6859 tree arg0 = TREE_VALUE (arglist);
6860 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6861 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6862 rtx op0 = expand_normal (arg0);
6863 rtx op1 = expand_normal (arg1);
6864 rtx op2 = expand_normal (arg2);
6866 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6867 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6868 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6870 /* Invalid arguments. Bail before doing anything stoopid! */
6871 if (arg0 == error_mark_node
6872 || arg1 == error_mark_node
6873 || arg2 == error_mark_node)
6876 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6877 op0 = copy_to_mode_reg (mode2, op0);
6878 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6879 op1 = copy_to_mode_reg (mode0, op1);
6880 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6881 op2 = copy_to_mode_reg (mode1, op2);
6883 pat = GEN_FCN (icode) (op1, op2, op0);
6890 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6892 tree arg0 = TREE_VALUE (arglist);
6893 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6894 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6895 rtx op0 = expand_normal (arg0);
6896 rtx op1 = expand_normal (arg1);
6897 rtx op2 = expand_normal (arg2);
6899 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6900 enum machine_mode mode1 = Pmode;
6901 enum machine_mode mode2 = Pmode;
6903 /* Invalid arguments. Bail before doing anything stoopid! */
6904 if (arg0 == error_mark_node
6905 || arg1 == error_mark_node
6906 || arg2 == error_mark_node)
6909 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6910 op0 = copy_to_mode_reg (tmode, op0);
6912 op2 = copy_to_mode_reg (mode2, op2);
6914 if (op1 == const0_rtx)
6916 addr = gen_rtx_MEM (tmode, op2);
6920 op1 = copy_to_mode_reg (mode1, op1);
6921 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6924 pat = GEN_FCN (icode) (addr, op0);
6931 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6934 tree arg0 = TREE_VALUE (arglist);
6935 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6936 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6937 rtx op0 = expand_normal (arg0);
6938 rtx op1 = expand_normal (arg1);
6939 rtx op2 = expand_normal (arg2);
6940 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6941 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6942 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6943 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6945 if (icode == CODE_FOR_nothing)
6946 /* Builtin not supported on this processor. */
6949 /* If we got invalid arguments bail out before generating bad rtl. */
6950 if (arg0 == error_mark_node
6951 || arg1 == error_mark_node
6952 || arg2 == error_mark_node)
6955 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6956 || icode == CODE_FOR_altivec_vsldoi_v4si
6957 || icode == CODE_FOR_altivec_vsldoi_v8hi
6958 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6960 /* Only allow 4-bit unsigned literals. */
6962 if (TREE_CODE (arg2) != INTEGER_CST
6963 || TREE_INT_CST_LOW (arg2) & ~0xf)
6965 error ("argument 3 must be a 4-bit unsigned literal");
6971 || GET_MODE (target) != tmode
6972 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6973 target = gen_reg_rtx (tmode);
6975 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6976 op0 = copy_to_mode_reg (mode0, op0);
6977 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6978 op1 = copy_to_mode_reg (mode1, op1);
6979 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6980 op2 = copy_to_mode_reg (mode2, op2);
6982 pat = GEN_FCN (icode) (target, op0, op1, op2);
6990 /* Expand the lvx builtins. */
6992 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6994 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6995 tree arglist = TREE_OPERAND (exp, 1);
6996 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6998 enum machine_mode tmode, mode0;
7000 enum insn_code icode;
7004 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7005 icode = CODE_FOR_altivec_lvx_v16qi;
7007 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7008 icode = CODE_FOR_altivec_lvx_v8hi;
7010 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7011 icode = CODE_FOR_altivec_lvx_v4si;
7013 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7014 icode = CODE_FOR_altivec_lvx_v4sf;
7023 arg0 = TREE_VALUE (arglist);
7024 op0 = expand_normal (arg0);
7025 tmode = insn_data[icode].operand[0].mode;
7026 mode0 = insn_data[icode].operand[1].mode;
7029 || GET_MODE (target) != tmode
7030 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7031 target = gen_reg_rtx (tmode);
7033 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7034 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7036 pat = GEN_FCN (icode) (target, op0);
7043 /* Expand the stvx builtins. */
7045 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7048 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7049 tree arglist = TREE_OPERAND (exp, 1);
7050 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7052 enum machine_mode mode0, mode1;
7054 enum insn_code icode;
7058 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7059 icode = CODE_FOR_altivec_stvx_v16qi;
7061 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7062 icode = CODE_FOR_altivec_stvx_v8hi;
7064 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7065 icode = CODE_FOR_altivec_stvx_v4si;
7067 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7068 icode = CODE_FOR_altivec_stvx_v4sf;
7075 arg0 = TREE_VALUE (arglist);
7076 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7077 op0 = expand_normal (arg0);
7078 op1 = expand_normal (arg1);
7079 mode0 = insn_data[icode].operand[0].mode;
7080 mode1 = insn_data[icode].operand[1].mode;
7082 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7083 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7084 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7085 op1 = copy_to_mode_reg (mode1, op1);
7087 pat = GEN_FCN (icode) (op0, op1);
7095 /* Expand the dst builtins. */
7097 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7100 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7101 tree arglist = TREE_OPERAND (exp, 1);
7102 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7103 tree arg0, arg1, arg2;
7104 enum machine_mode mode0, mode1, mode2;
7105 rtx pat, op0, op1, op2;
7106 struct builtin_description *d;
7111 /* Handle DST variants. */
7112 d = (struct builtin_description *) bdesc_dst;
7113 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7114 if (d->code == fcode)
7116 arg0 = TREE_VALUE (arglist);
7117 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7118 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7119 op0 = expand_normal (arg0);
7120 op1 = expand_normal (arg1);
7121 op2 = expand_normal (arg2);
7122 mode0 = insn_data[d->icode].operand[0].mode;
7123 mode1 = insn_data[d->icode].operand[1].mode;
7124 mode2 = insn_data[d->icode].operand[2].mode;
7126 /* Invalid arguments, bail out before generating bad rtl. */
7127 if (arg0 == error_mark_node
7128 || arg1 == error_mark_node
7129 || arg2 == error_mark_node)
7134 if (TREE_CODE (arg2) != INTEGER_CST
7135 || TREE_INT_CST_LOW (arg2) & ~0x3)
7137 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7141 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7142 op0 = copy_to_mode_reg (Pmode, op0);
7143 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7144 op1 = copy_to_mode_reg (mode1, op1);
7146 pat = GEN_FCN (d->icode) (op0, op1, op2);
7156 /* Expand vec_init builtin. */
7158 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7160 enum machine_mode tmode = TYPE_MODE (type);
7161 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7162 int i, n_elt = GET_MODE_NUNITS (tmode);
7163 rtvec v = rtvec_alloc (n_elt);
7165 gcc_assert (VECTOR_MODE_P (tmode));
7167 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7169 rtx x = expand_normal (TREE_VALUE (arglist));
7170 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7173 gcc_assert (arglist == NULL);
7175 if (!target || !register_operand (target, tmode))
7176 target = gen_reg_rtx (tmode);
7178 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7182 /* Return the integer constant in ARG. Constrain it to be in the range
7183 of the subparts of VEC_TYPE; issue an error if not. */
7186 get_element_number (tree vec_type, tree arg)
7188 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7190 if (!host_integerp (arg, 1)
7191 || (elt = tree_low_cst (arg, 1), elt > max))
7193 error ("selector must be an integer constant in the range 0..%wi", max);
7200 /* Expand vec_set builtin. */
7202 altivec_expand_vec_set_builtin (tree arglist)
7204 enum machine_mode tmode, mode1;
7205 tree arg0, arg1, arg2;
7209 arg0 = TREE_VALUE (arglist);
7210 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7211 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7213 tmode = TYPE_MODE (TREE_TYPE (arg0));
7214 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7215 gcc_assert (VECTOR_MODE_P (tmode));
7217 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7218 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7219 elt = get_element_number (TREE_TYPE (arg0), arg2);
7221 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7222 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7224 op0 = force_reg (tmode, op0);
7225 op1 = force_reg (mode1, op1);
7227 rs6000_expand_vector_set (op0, op1, elt);
7232 /* Expand vec_ext builtin. */
7234 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7236 enum machine_mode tmode, mode0;
7241 arg0 = TREE_VALUE (arglist);
7242 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7244 op0 = expand_normal (arg0);
7245 elt = get_element_number (TREE_TYPE (arg0), arg1);
7247 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7248 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7249 gcc_assert (VECTOR_MODE_P (mode0));
7251 op0 = force_reg (mode0, op0);
7253 if (optimize || !target || !register_operand (target, tmode))
7254 target = gen_reg_rtx (tmode);
7256 rs6000_expand_vector_extract (target, op0, elt);
7261 /* Expand the builtin in EXP and store the result in TARGET. Store
7262 true in *EXPANDEDP if we found a builtin to expand. */
7264 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7266 struct builtin_description *d;
7267 struct builtin_description_predicates *dp;
7269 enum insn_code icode;
7270 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7271 tree arglist = TREE_OPERAND (exp, 1);
7274 enum machine_mode tmode, mode0;
7275 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7277 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7278 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7281 error ("unresolved overload for Altivec builtin %qF", fndecl);
7285 target = altivec_expand_ld_builtin (exp, target, expandedp);
7289 target = altivec_expand_st_builtin (exp, target, expandedp);
7293 target = altivec_expand_dst_builtin (exp, target, expandedp);
7301 case ALTIVEC_BUILTIN_STVX:
7302 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7303 case ALTIVEC_BUILTIN_STVEBX:
7304 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7305 case ALTIVEC_BUILTIN_STVEHX:
7306 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7307 case ALTIVEC_BUILTIN_STVEWX:
7308 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7309 case ALTIVEC_BUILTIN_STVXL:
7310 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7312 case ALTIVEC_BUILTIN_MFVSCR:
7313 icode = CODE_FOR_altivec_mfvscr;
7314 tmode = insn_data[icode].operand[0].mode;
7317 || GET_MODE (target) != tmode
7318 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7319 target = gen_reg_rtx (tmode);
7321 pat = GEN_FCN (icode) (target);
7327 case ALTIVEC_BUILTIN_MTVSCR:
7328 icode = CODE_FOR_altivec_mtvscr;
7329 arg0 = TREE_VALUE (arglist);
7330 op0 = expand_normal (arg0);
7331 mode0 = insn_data[icode].operand[0].mode;
7333 /* If we got invalid arguments bail out before generating bad rtl. */
7334 if (arg0 == error_mark_node)
7337 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7338 op0 = copy_to_mode_reg (mode0, op0);
7340 pat = GEN_FCN (icode) (op0);
7345 case ALTIVEC_BUILTIN_DSSALL:
7346 emit_insn (gen_altivec_dssall ());
7349 case ALTIVEC_BUILTIN_DSS:
7350 icode = CODE_FOR_altivec_dss;
7351 arg0 = TREE_VALUE (arglist);
7353 op0 = expand_normal (arg0);
7354 mode0 = insn_data[icode].operand[0].mode;
7356 /* If we got invalid arguments bail out before generating bad rtl. */
7357 if (arg0 == error_mark_node)
7360 if (TREE_CODE (arg0) != INTEGER_CST
7361 || TREE_INT_CST_LOW (arg0) & ~0x3)
7363 error ("argument to dss must be a 2-bit unsigned literal");
7367 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7368 op0 = copy_to_mode_reg (mode0, op0);
7370 emit_insn (gen_altivec_dss (op0));
7373 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7374 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7375 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7376 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7377 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7379 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7380 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7381 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7382 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7383 return altivec_expand_vec_set_builtin (arglist);
7385 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7386 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7387 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7388 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7389 return altivec_expand_vec_ext_builtin (arglist, target);
7396 /* Expand abs* operations. */
7397 d = (struct builtin_description *) bdesc_abs;
7398 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7399 if (d->code == fcode)
7400 return altivec_expand_abs_builtin (d->icode, arglist, target);
7402 /* Expand the AltiVec predicates. */
7403 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7404 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7405 if (dp->code == fcode)
7406 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7409 /* LV* are funky. We initialized them differently. */
7412 case ALTIVEC_BUILTIN_LVSL:
7413 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7415 case ALTIVEC_BUILTIN_LVSR:
7416 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7418 case ALTIVEC_BUILTIN_LVEBX:
7419 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7421 case ALTIVEC_BUILTIN_LVEHX:
7422 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7424 case ALTIVEC_BUILTIN_LVEWX:
7425 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7427 case ALTIVEC_BUILTIN_LVXL:
7428 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7430 case ALTIVEC_BUILTIN_LVX:
7431 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7442 /* Binops that need to be initialized manually, but can be expanded
7443 automagically by rs6000_expand_binop_builtin. */
7444 static struct builtin_description bdesc_2arg_spe[] =
7446 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7447 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7448 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7449 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7450 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7451 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7452 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7453 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7454 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7455 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7456 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7457 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7458 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7459 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7460 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7461 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7462 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7463 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7464 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7465 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7466 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7467 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7470 /* Expand the builtin in EXP and store the result in TARGET. Store
7471 true in *EXPANDEDP if we found a builtin to expand.
7473 This expands the SPE builtins that are not simple unary and binary
7476 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7478 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7479 tree arglist = TREE_OPERAND (exp, 1);
7481 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7482 enum insn_code icode;
7483 enum machine_mode tmode, mode0;
7485 struct builtin_description *d;
7490 /* Syntax check for a 5-bit unsigned immediate. */
7493 case SPE_BUILTIN_EVSTDD:
7494 case SPE_BUILTIN_EVSTDH:
7495 case SPE_BUILTIN_EVSTDW:
7496 case SPE_BUILTIN_EVSTWHE:
7497 case SPE_BUILTIN_EVSTWHO:
7498 case SPE_BUILTIN_EVSTWWE:
7499 case SPE_BUILTIN_EVSTWWO:
7500 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7501 if (TREE_CODE (arg1) != INTEGER_CST
7502 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7504 error ("argument 2 must be a 5-bit unsigned literal");
7512 /* The evsplat*i instructions are not quite generic. */
7515 case SPE_BUILTIN_EVSPLATFI:
7516 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7518 case SPE_BUILTIN_EVSPLATI:
7519 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7525 d = (struct builtin_description *) bdesc_2arg_spe;
7526 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7527 if (d->code == fcode)
7528 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7530 d = (struct builtin_description *) bdesc_spe_predicates;
7531 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7532 if (d->code == fcode)
7533 return spe_expand_predicate_builtin (d->icode, arglist, target);
7535 d = (struct builtin_description *) bdesc_spe_evsel;
7536 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7537 if (d->code == fcode)
7538 return spe_expand_evsel_builtin (d->icode, arglist, target);
7542 case SPE_BUILTIN_EVSTDDX:
7543 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7544 case SPE_BUILTIN_EVSTDHX:
7545 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7546 case SPE_BUILTIN_EVSTDWX:
7547 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7548 case SPE_BUILTIN_EVSTWHEX:
7549 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7550 case SPE_BUILTIN_EVSTWHOX:
7551 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7552 case SPE_BUILTIN_EVSTWWEX:
7553 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7554 case SPE_BUILTIN_EVSTWWOX:
7555 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7556 case SPE_BUILTIN_EVSTDD:
7557 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7558 case SPE_BUILTIN_EVSTDH:
7559 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7560 case SPE_BUILTIN_EVSTDW:
7561 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7562 case SPE_BUILTIN_EVSTWHE:
7563 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7564 case SPE_BUILTIN_EVSTWHO:
7565 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7566 case SPE_BUILTIN_EVSTWWE:
7567 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7568 case SPE_BUILTIN_EVSTWWO:
7569 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7570 case SPE_BUILTIN_MFSPEFSCR:
7571 icode = CODE_FOR_spe_mfspefscr;
7572 tmode = insn_data[icode].operand[0].mode;
7575 || GET_MODE (target) != tmode
7576 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7577 target = gen_reg_rtx (tmode);
7579 pat = GEN_FCN (icode) (target);
7584 case SPE_BUILTIN_MTSPEFSCR:
7585 icode = CODE_FOR_spe_mtspefscr;
7586 arg0 = TREE_VALUE (arglist);
7587 op0 = expand_normal (arg0);
7588 mode0 = insn_data[icode].operand[0].mode;
7590 if (arg0 == error_mark_node)
7593 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7594 op0 = copy_to_mode_reg (mode0, op0);
7596 pat = GEN_FCN (icode) (op0);
7609 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7611 rtx pat, scratch, tmp;
7612 tree form = TREE_VALUE (arglist);
7613 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7614 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7615 rtx op0 = expand_normal (arg0);
7616 rtx op1 = expand_normal (arg1);
7617 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7618 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7622 if (TREE_CODE (form) != INTEGER_CST)
7624 error ("argument 1 of __builtin_spe_predicate must be a constant");
7628 form_int = TREE_INT_CST_LOW (form);
7630 gcc_assert (mode0 == mode1);
7632 if (arg0 == error_mark_node || arg1 == error_mark_node)
7636 || GET_MODE (target) != SImode
7637 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7638 target = gen_reg_rtx (SImode);
7640 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7641 op0 = copy_to_mode_reg (mode0, op0);
7642 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7643 op1 = copy_to_mode_reg (mode1, op1);
7645 scratch = gen_reg_rtx (CCmode);
7647 pat = GEN_FCN (icode) (scratch, op0, op1);
7652 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7653 _lower_. We use one compare, but look in different bits of the
7654 CR for each variant.
7656 There are 2 elements in each SPE simd type (upper/lower). The CR
7657 bits are set as follows:
7659 BIT0 | BIT 1 | BIT 2 | BIT 3
7660 U | L | (U | L) | (U & L)
7662 So, for an "all" relationship, BIT 3 would be set.
7663 For an "any" relationship, BIT 2 would be set. Etc.
7665 Following traditional nomenclature, these bits map to:
7667 BIT0 | BIT 1 | BIT 2 | BIT 3
7670 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7675 /* All variant. OV bit. */
7677 /* We need to get to the OV bit, which is the ORDERED bit. We
7678 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7679 that's ugly and will make validate_condition_mode die.
7680 So let's just use another pattern. */
7681 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7683 /* Any variant. EQ bit. */
7687 /* Upper variant. LT bit. */
7691 /* Lower variant. GT bit. */
7696 error ("argument 1 of __builtin_spe_predicate is out of range");
7700 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7701 emit_move_insn (target, tmp);
7706 /* The evsel builtins look like this:
7708 e = __builtin_spe_evsel_OP (a, b, c, d);
7712 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7713 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7717 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7720 tree arg0 = TREE_VALUE (arglist);
7721 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7722 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7723 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7724 rtx op0 = expand_normal (arg0);
7725 rtx op1 = expand_normal (arg1);
7726 rtx op2 = expand_normal (arg2);
7727 rtx op3 = expand_normal (arg3);
7728 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7729 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7731 gcc_assert (mode0 == mode1);
7733 if (arg0 == error_mark_node || arg1 == error_mark_node
7734 || arg2 == error_mark_node || arg3 == error_mark_node)
7738 || GET_MODE (target) != mode0
7739 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7740 target = gen_reg_rtx (mode0);
7742 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7743 op0 = copy_to_mode_reg (mode0, op0);
7744 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7745 op1 = copy_to_mode_reg (mode0, op1);
7746 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7747 op2 = copy_to_mode_reg (mode0, op2);
7748 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7749 op3 = copy_to_mode_reg (mode0, op3);
7751 /* Generate the compare. */
7752 scratch = gen_reg_rtx (CCmode);
7753 pat = GEN_FCN (icode) (scratch, op0, op1);
7758 if (mode0 == V2SImode)
7759 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7761 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7766 /* Expand an expression EXP that calls a built-in function,
7767 with result going to TARGET if that's convenient
7768 (and in mode MODE if that's convenient).
7769 SUBTARGET may be used as the target for computing one of EXP's operands.
7770 IGNORE is nonzero if the value is to be ignored. */
7773 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7774 enum machine_mode mode ATTRIBUTE_UNUSED,
7775 int ignore ATTRIBUTE_UNUSED)
7777 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7778 tree arglist = TREE_OPERAND (exp, 1);
7779 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7780 struct builtin_description *d;
7785 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7786 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7788 int icode = (int) CODE_FOR_altivec_lvsr;
7789 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7790 enum machine_mode mode = insn_data[icode].operand[1].mode;
7794 gcc_assert (TARGET_ALTIVEC);
7796 arg = TREE_VALUE (arglist);
7797 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7798 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7799 addr = memory_address (mode, op);
7800 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7804 /* For the load case need to negate the address. */
7805 op = gen_reg_rtx (GET_MODE (addr));
7806 emit_insn (gen_rtx_SET (VOIDmode, op,
7807 gen_rtx_NEG (GET_MODE (addr), addr)));
7809 op = gen_rtx_MEM (mode, op);
7812 || GET_MODE (target) != tmode
7813 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7814 target = gen_reg_rtx (tmode);
7816 /*pat = gen_altivec_lvsr (target, op);*/
7817 pat = GEN_FCN (icode) (target, op);
7827 ret = altivec_expand_builtin (exp, target, &success);
7834 ret = spe_expand_builtin (exp, target, &success);
7840 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7842 /* Handle simple unary operations. */
7843 d = (struct builtin_description *) bdesc_1arg;
7844 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7845 if (d->code == fcode)
7846 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7848 /* Handle simple binary operations. */
7849 d = (struct builtin_description *) bdesc_2arg;
7850 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7851 if (d->code == fcode)
7852 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7854 /* Handle simple ternary operations. */
7855 d = (struct builtin_description *) bdesc_3arg;
7856 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7857 if (d->code == fcode)
7858 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7864 build_opaque_vector_type (tree node, int nunits)
7866 node = copy_node (node);
7867 TYPE_MAIN_VARIANT (node) = node;
7868 return build_vector_type (node, nunits);
7872 rs6000_init_builtins (void)
7874 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7875 V2SF_type_node = build_vector_type (float_type_node, 2);
7876 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7877 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7878 V4SF_type_node = build_vector_type (float_type_node, 4);
7879 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7880 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7882 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7883 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7884 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7886 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7887 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7888 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7889 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7891 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7892 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7893 'vector unsigned short'. */
7895 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7896 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7897 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7898 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7900 long_integer_type_internal_node = long_integer_type_node;
7901 long_unsigned_type_internal_node = long_unsigned_type_node;
7902 intQI_type_internal_node = intQI_type_node;
7903 uintQI_type_internal_node = unsigned_intQI_type_node;
7904 intHI_type_internal_node = intHI_type_node;
7905 uintHI_type_internal_node = unsigned_intHI_type_node;
7906 intSI_type_internal_node = intSI_type_node;
7907 uintSI_type_internal_node = unsigned_intSI_type_node;
7908 float_type_internal_node = float_type_node;
7909 void_type_internal_node = void_type_node;
7911 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7912 get_identifier ("__bool char"),
7913 bool_char_type_node));
7914 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7915 get_identifier ("__bool short"),
7916 bool_short_type_node));
7917 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7918 get_identifier ("__bool int"),
7919 bool_int_type_node));
7920 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7921 get_identifier ("__pixel"),
7924 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7925 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7926 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7927 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7929 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7930 get_identifier ("__vector unsigned char"),
7931 unsigned_V16QI_type_node));
7932 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7933 get_identifier ("__vector signed char"),
7935 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7936 get_identifier ("__vector __bool char"),
7937 bool_V16QI_type_node));
7939 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7940 get_identifier ("__vector unsigned short"),
7941 unsigned_V8HI_type_node));
7942 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7943 get_identifier ("__vector signed short"),
7945 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7946 get_identifier ("__vector __bool short"),
7947 bool_V8HI_type_node));
7949 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7950 get_identifier ("__vector unsigned int"),
7951 unsigned_V4SI_type_node));
7952 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7953 get_identifier ("__vector signed int"),
7955 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7956 get_identifier ("__vector __bool int"),
7957 bool_V4SI_type_node));
7959 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7960 get_identifier ("__vector float"),
7962 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7963 get_identifier ("__vector __pixel"),
7964 pixel_V8HI_type_node));
7967 spe_init_builtins ();
7969 altivec_init_builtins ();
7970 if (TARGET_ALTIVEC || TARGET_SPE)
7971 rs6000_common_init_builtins ();
7974 /* AIX libm provides clog as __clog. */
7975 if (built_in_decls [BUILT_IN_CLOG])
7976 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
7980 /* Search through a set of builtins and enable the mask bits.
7981 DESC is an array of builtins.
7982 SIZE is the total number of builtins.
7983 START is the builtin enum at which to start.
7984 END is the builtin enum at which to end. */
7986 enable_mask_for_builtins (struct builtin_description *desc, int size,
7987 enum rs6000_builtins start,
7988 enum rs6000_builtins end)
7992 for (i = 0; i < size; ++i)
7993 if (desc[i].code == start)
7999 for (; i < size; ++i)
8001 /* Flip all the bits on. */
8002 desc[i].mask = target_flags;
8003 if (desc[i].code == end)
8009 spe_init_builtins (void)
8011 tree endlink = void_list_node;
8012 tree puint_type_node = build_pointer_type (unsigned_type_node);
8013 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8014 struct builtin_description *d;
8017 tree v2si_ftype_4_v2si
8018 = build_function_type
8019 (opaque_V2SI_type_node,
8020 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8021 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8022 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8023 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8026 tree v2sf_ftype_4_v2sf
8027 = build_function_type
8028 (opaque_V2SF_type_node,
8029 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8030 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8031 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8032 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8035 tree int_ftype_int_v2si_v2si
8036 = build_function_type
8038 tree_cons (NULL_TREE, integer_type_node,
8039 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8040 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8043 tree int_ftype_int_v2sf_v2sf
8044 = build_function_type
8046 tree_cons (NULL_TREE, integer_type_node,
8047 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8048 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8051 tree void_ftype_v2si_puint_int
8052 = build_function_type (void_type_node,
8053 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8054 tree_cons (NULL_TREE, puint_type_node,
8055 tree_cons (NULL_TREE,
8059 tree void_ftype_v2si_puint_char
8060 = build_function_type (void_type_node,
8061 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8062 tree_cons (NULL_TREE, puint_type_node,
8063 tree_cons (NULL_TREE,
8067 tree void_ftype_v2si_pv2si_int
8068 = build_function_type (void_type_node,
8069 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8070 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8071 tree_cons (NULL_TREE,
8075 tree void_ftype_v2si_pv2si_char
8076 = build_function_type (void_type_node,
8077 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8078 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8079 tree_cons (NULL_TREE,
8084 = build_function_type (void_type_node,
8085 tree_cons (NULL_TREE, integer_type_node, endlink));
8088 = build_function_type (integer_type_node, endlink);
8090 tree v2si_ftype_pv2si_int
8091 = build_function_type (opaque_V2SI_type_node,
8092 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8093 tree_cons (NULL_TREE, integer_type_node,
8096 tree v2si_ftype_puint_int
8097 = build_function_type (opaque_V2SI_type_node,
8098 tree_cons (NULL_TREE, puint_type_node,
8099 tree_cons (NULL_TREE, integer_type_node,
8102 tree v2si_ftype_pushort_int
8103 = build_function_type (opaque_V2SI_type_node,
8104 tree_cons (NULL_TREE, pushort_type_node,
8105 tree_cons (NULL_TREE, integer_type_node,
8108 tree v2si_ftype_signed_char
8109 = build_function_type (opaque_V2SI_type_node,
8110 tree_cons (NULL_TREE, signed_char_type_node,
8113 /* The initialization of the simple binary and unary builtins is
8114 done in rs6000_common_init_builtins, but we have to enable the
8115 mask bits here manually because we have run out of `target_flags'
8116 bits. We really need to redesign this mask business. */
8118 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8119 ARRAY_SIZE (bdesc_2arg),
8122 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8123 ARRAY_SIZE (bdesc_1arg),
8125 SPE_BUILTIN_EVSUBFUSIAAW);
8126 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8127 ARRAY_SIZE (bdesc_spe_predicates),
8128 SPE_BUILTIN_EVCMPEQ,
8129 SPE_BUILTIN_EVFSTSTLT);
8130 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8131 ARRAY_SIZE (bdesc_spe_evsel),
8132 SPE_BUILTIN_EVSEL_CMPGTS,
8133 SPE_BUILTIN_EVSEL_FSTSTEQ);
8135 (*lang_hooks.decls.pushdecl)
8136 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8137 opaque_V2SI_type_node));
8139 /* Initialize irregular SPE builtins. */
8141 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8142 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8143 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8144 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8145 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8146 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8147 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8148 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8149 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8150 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8151 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8152 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8153 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8154 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8155 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8156 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8157 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8158 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8161 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8162 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8163 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8164 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8165 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8166 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8167 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8168 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8169 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8170 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8171 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8172 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8173 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8174 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8175 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8176 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8177 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8178 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8179 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8180 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8181 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8182 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8185 d = (struct builtin_description *) bdesc_spe_predicates;
8186 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8190 switch (insn_data[d->icode].operand[1].mode)
8193 type = int_ftype_int_v2si_v2si;
8196 type = int_ftype_int_v2sf_v2sf;
8202 def_builtin (d->mask, d->name, type, d->code);
8205 /* Evsel predicates. */
8206 d = (struct builtin_description *) bdesc_spe_evsel;
8207 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8211 switch (insn_data[d->icode].operand[1].mode)
8214 type = v2si_ftype_4_v2si;
8217 type = v2sf_ftype_4_v2sf;
8223 def_builtin (d->mask, d->name, type, d->code);
8228 altivec_init_builtins (void)
8230 struct builtin_description *d;
8231 struct builtin_description_predicates *dp;
8235 tree pfloat_type_node = build_pointer_type (float_type_node);
8236 tree pint_type_node = build_pointer_type (integer_type_node);
8237 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8238 tree pchar_type_node = build_pointer_type (char_type_node);
8240 tree pvoid_type_node = build_pointer_type (void_type_node);
8242 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8243 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8244 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8245 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8247 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8249 tree int_ftype_opaque
8250 = build_function_type_list (integer_type_node,
8251 opaque_V4SI_type_node, NULL_TREE);
8253 tree opaque_ftype_opaque_int
8254 = build_function_type_list (opaque_V4SI_type_node,
8255 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8256 tree opaque_ftype_opaque_opaque_int
8257 = build_function_type_list (opaque_V4SI_type_node,
8258 opaque_V4SI_type_node, opaque_V4SI_type_node,
8259 integer_type_node, NULL_TREE);
8260 tree int_ftype_int_opaque_opaque
8261 = build_function_type_list (integer_type_node,
8262 integer_type_node, opaque_V4SI_type_node,
8263 opaque_V4SI_type_node, NULL_TREE);
8264 tree int_ftype_int_v4si_v4si
8265 = build_function_type_list (integer_type_node,
8266 integer_type_node, V4SI_type_node,
8267 V4SI_type_node, NULL_TREE);
8268 tree v4sf_ftype_pcfloat
8269 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8270 tree void_ftype_pfloat_v4sf
8271 = build_function_type_list (void_type_node,
8272 pfloat_type_node, V4SF_type_node, NULL_TREE);
8273 tree v4si_ftype_pcint
8274 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8275 tree void_ftype_pint_v4si
8276 = build_function_type_list (void_type_node,
8277 pint_type_node, V4SI_type_node, NULL_TREE);
8278 tree v8hi_ftype_pcshort
8279 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8280 tree void_ftype_pshort_v8hi
8281 = build_function_type_list (void_type_node,
8282 pshort_type_node, V8HI_type_node, NULL_TREE);
8283 tree v16qi_ftype_pcchar
8284 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8285 tree void_ftype_pchar_v16qi
8286 = build_function_type_list (void_type_node,
8287 pchar_type_node, V16QI_type_node, NULL_TREE);
8288 tree void_ftype_v4si
8289 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8290 tree v8hi_ftype_void
8291 = build_function_type (V8HI_type_node, void_list_node);
8292 tree void_ftype_void
8293 = build_function_type (void_type_node, void_list_node);
8295 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8297 tree opaque_ftype_long_pcvoid
8298 = build_function_type_list (opaque_V4SI_type_node,
8299 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8300 tree v16qi_ftype_long_pcvoid
8301 = build_function_type_list (V16QI_type_node,
8302 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8303 tree v8hi_ftype_long_pcvoid
8304 = build_function_type_list (V8HI_type_node,
8305 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8306 tree v4si_ftype_long_pcvoid
8307 = build_function_type_list (V4SI_type_node,
8308 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8310 tree void_ftype_opaque_long_pvoid
8311 = build_function_type_list (void_type_node,
8312 opaque_V4SI_type_node, long_integer_type_node,
8313 pvoid_type_node, NULL_TREE);
8314 tree void_ftype_v4si_long_pvoid
8315 = build_function_type_list (void_type_node,
8316 V4SI_type_node, long_integer_type_node,
8317 pvoid_type_node, NULL_TREE);
8318 tree void_ftype_v16qi_long_pvoid
8319 = build_function_type_list (void_type_node,
8320 V16QI_type_node, long_integer_type_node,
8321 pvoid_type_node, NULL_TREE);
8322 tree void_ftype_v8hi_long_pvoid
8323 = build_function_type_list (void_type_node,
8324 V8HI_type_node, long_integer_type_node,
8325 pvoid_type_node, NULL_TREE);
8326 tree int_ftype_int_v8hi_v8hi
8327 = build_function_type_list (integer_type_node,
8328 integer_type_node, V8HI_type_node,
8329 V8HI_type_node, NULL_TREE);
8330 tree int_ftype_int_v16qi_v16qi
8331 = build_function_type_list (integer_type_node,
8332 integer_type_node, V16QI_type_node,
8333 V16QI_type_node, NULL_TREE);
8334 tree int_ftype_int_v4sf_v4sf
8335 = build_function_type_list (integer_type_node,
8336 integer_type_node, V4SF_type_node,
8337 V4SF_type_node, NULL_TREE);
8338 tree v4si_ftype_v4si
8339 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8340 tree v8hi_ftype_v8hi
8341 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8342 tree v16qi_ftype_v16qi
8343 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8344 tree v4sf_ftype_v4sf
8345 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8346 tree void_ftype_pcvoid_int_int
8347 = build_function_type_list (void_type_node,
8348 pcvoid_type_node, integer_type_node,
8349 integer_type_node, NULL_TREE);
8351 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8352 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8353 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8354 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8355 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8356 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8357 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8358 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8359 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8360 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8361 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8362 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8363 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8364 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8365 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8366 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8367 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8368 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8369 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8370 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8371 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8372 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8373 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8374 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8375 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8376 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8377 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8378 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8379 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8380 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8381 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8382 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8383 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8384 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8385 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8386 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8387 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8388 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8389 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8390 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8391 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8392 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8393 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8394 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8395 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8396 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8398 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8400 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8401 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8402 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8403 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8404 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8405 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8406 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8407 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8408 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8409 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8411 /* Add the DST variants. */
8412 d = (struct builtin_description *) bdesc_dst;
8413 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8414 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8416 /* Initialize the predicates. */
8417 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8418 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8420 enum machine_mode mode1;
8422 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8423 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8428 mode1 = insn_data[dp->icode].operand[1].mode;
8433 type = int_ftype_int_opaque_opaque;
8436 type = int_ftype_int_v4si_v4si;
8439 type = int_ftype_int_v8hi_v8hi;
8442 type = int_ftype_int_v16qi_v16qi;
8445 type = int_ftype_int_v4sf_v4sf;
8451 def_builtin (dp->mask, dp->name, type, dp->code);
8454 /* Initialize the abs* operators. */
8455 d = (struct builtin_description *) bdesc_abs;
8456 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8458 enum machine_mode mode0;
8461 mode0 = insn_data[d->icode].operand[0].mode;
8466 type = v4si_ftype_v4si;
8469 type = v8hi_ftype_v8hi;
8472 type = v16qi_ftype_v16qi;
8475 type = v4sf_ftype_v4sf;
8481 def_builtin (d->mask, d->name, type, d->code);
8488 /* Initialize target builtin that implements
8489 targetm.vectorize.builtin_mask_for_load. */
8491 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8492 v16qi_ftype_long_pcvoid,
8493 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8495 tree_cons (get_identifier ("const"),
8496 NULL_TREE, NULL_TREE));
8497 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8498 altivec_builtin_mask_for_load = decl;
8501 /* Access to the vec_init patterns. */
8502 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8503 integer_type_node, integer_type_node,
8504 integer_type_node, NULL_TREE);
8505 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8506 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8508 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8509 short_integer_type_node,
8510 short_integer_type_node,
8511 short_integer_type_node,
8512 short_integer_type_node,
8513 short_integer_type_node,
8514 short_integer_type_node,
8515 short_integer_type_node, NULL_TREE);
8516 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8517 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8519 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8520 char_type_node, char_type_node,
8521 char_type_node, char_type_node,
8522 char_type_node, char_type_node,
8523 char_type_node, char_type_node,
8524 char_type_node, char_type_node,
8525 char_type_node, char_type_node,
8526 char_type_node, char_type_node,
8527 char_type_node, NULL_TREE);
8528 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8529 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8531 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8532 float_type_node, float_type_node,
8533 float_type_node, NULL_TREE);
8534 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8535 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8537 /* Access to the vec_set patterns. */
8538 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8540 integer_type_node, NULL_TREE);
8541 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8542 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8544 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8546 integer_type_node, NULL_TREE);
8547 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8548 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8550 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8552 integer_type_node, NULL_TREE);
8553 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8554 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8556 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8558 integer_type_node, NULL_TREE);
8559 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8560 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8562 /* Access to the vec_extract patterns. */
8563 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8564 integer_type_node, NULL_TREE);
8565 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8566 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8568 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8569 integer_type_node, NULL_TREE);
8570 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8571 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8573 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8574 integer_type_node, NULL_TREE);
8575 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8576 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8578 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8579 integer_type_node, NULL_TREE);
8580 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8581 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8585 rs6000_common_init_builtins (void)
8587 struct builtin_description *d;
8590 tree v4sf_ftype_v4sf_v4sf_v16qi
8591 = build_function_type_list (V4SF_type_node,
8592 V4SF_type_node, V4SF_type_node,
8593 V16QI_type_node, NULL_TREE);
8594 tree v4si_ftype_v4si_v4si_v16qi
8595 = build_function_type_list (V4SI_type_node,
8596 V4SI_type_node, V4SI_type_node,
8597 V16QI_type_node, NULL_TREE);
8598 tree v8hi_ftype_v8hi_v8hi_v16qi
8599 = build_function_type_list (V8HI_type_node,
8600 V8HI_type_node, V8HI_type_node,
8601 V16QI_type_node, NULL_TREE);
8602 tree v16qi_ftype_v16qi_v16qi_v16qi
8603 = build_function_type_list (V16QI_type_node,
8604 V16QI_type_node, V16QI_type_node,
8605 V16QI_type_node, NULL_TREE);
8607 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8609 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8610 tree v16qi_ftype_int
8611 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8612 tree v8hi_ftype_v16qi
8613 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8614 tree v4sf_ftype_v4sf
8615 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8617 tree v2si_ftype_v2si_v2si
8618 = build_function_type_list (opaque_V2SI_type_node,
8619 opaque_V2SI_type_node,
8620 opaque_V2SI_type_node, NULL_TREE);
8622 tree v2sf_ftype_v2sf_v2sf
8623 = build_function_type_list (opaque_V2SF_type_node,
8624 opaque_V2SF_type_node,
8625 opaque_V2SF_type_node, NULL_TREE);
8627 tree v2si_ftype_int_int
8628 = build_function_type_list (opaque_V2SI_type_node,
8629 integer_type_node, integer_type_node,
8632 tree opaque_ftype_opaque
8633 = build_function_type_list (opaque_V4SI_type_node,
8634 opaque_V4SI_type_node, NULL_TREE);
8636 tree v2si_ftype_v2si
8637 = build_function_type_list (opaque_V2SI_type_node,
8638 opaque_V2SI_type_node, NULL_TREE);
8640 tree v2sf_ftype_v2sf
8641 = build_function_type_list (opaque_V2SF_type_node,
8642 opaque_V2SF_type_node, NULL_TREE);
8644 tree v2sf_ftype_v2si
8645 = build_function_type_list (opaque_V2SF_type_node,
8646 opaque_V2SI_type_node, NULL_TREE);
8648 tree v2si_ftype_v2sf
8649 = build_function_type_list (opaque_V2SI_type_node,
8650 opaque_V2SF_type_node, NULL_TREE);
8652 tree v2si_ftype_v2si_char
8653 = build_function_type_list (opaque_V2SI_type_node,
8654 opaque_V2SI_type_node,
8655 char_type_node, NULL_TREE);
8657 tree v2si_ftype_int_char
8658 = build_function_type_list (opaque_V2SI_type_node,
8659 integer_type_node, char_type_node, NULL_TREE);
8661 tree v2si_ftype_char
8662 = build_function_type_list (opaque_V2SI_type_node,
8663 char_type_node, NULL_TREE);
8665 tree int_ftype_int_int
8666 = build_function_type_list (integer_type_node,
8667 integer_type_node, integer_type_node,
8670 tree opaque_ftype_opaque_opaque
8671 = build_function_type_list (opaque_V4SI_type_node,
8672 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8673 tree v4si_ftype_v4si_v4si
8674 = build_function_type_list (V4SI_type_node,
8675 V4SI_type_node, V4SI_type_node, NULL_TREE);
8676 tree v4sf_ftype_v4si_int
8677 = build_function_type_list (V4SF_type_node,
8678 V4SI_type_node, integer_type_node, NULL_TREE);
8679 tree v4si_ftype_v4sf_int
8680 = build_function_type_list (V4SI_type_node,
8681 V4SF_type_node, integer_type_node, NULL_TREE);
8682 tree v4si_ftype_v4si_int
8683 = build_function_type_list (V4SI_type_node,
8684 V4SI_type_node, integer_type_node, NULL_TREE);
8685 tree v8hi_ftype_v8hi_int
8686 = build_function_type_list (V8HI_type_node,
8687 V8HI_type_node, integer_type_node, NULL_TREE);
8688 tree v16qi_ftype_v16qi_int
8689 = build_function_type_list (V16QI_type_node,
8690 V16QI_type_node, integer_type_node, NULL_TREE);
8691 tree v16qi_ftype_v16qi_v16qi_int
8692 = build_function_type_list (V16QI_type_node,
8693 V16QI_type_node, V16QI_type_node,
8694 integer_type_node, NULL_TREE);
8695 tree v8hi_ftype_v8hi_v8hi_int
8696 = build_function_type_list (V8HI_type_node,
8697 V8HI_type_node, V8HI_type_node,
8698 integer_type_node, NULL_TREE);
8699 tree v4si_ftype_v4si_v4si_int
8700 = build_function_type_list (V4SI_type_node,
8701 V4SI_type_node, V4SI_type_node,
8702 integer_type_node, NULL_TREE);
8703 tree v4sf_ftype_v4sf_v4sf_int
8704 = build_function_type_list (V4SF_type_node,
8705 V4SF_type_node, V4SF_type_node,
8706 integer_type_node, NULL_TREE);
8707 tree v4sf_ftype_v4sf_v4sf
8708 = build_function_type_list (V4SF_type_node,
8709 V4SF_type_node, V4SF_type_node, NULL_TREE);
8710 tree opaque_ftype_opaque_opaque_opaque
8711 = build_function_type_list (opaque_V4SI_type_node,
8712 opaque_V4SI_type_node, opaque_V4SI_type_node,
8713 opaque_V4SI_type_node, NULL_TREE);
8714 tree v4sf_ftype_v4sf_v4sf_v4si
8715 = build_function_type_list (V4SF_type_node,
8716 V4SF_type_node, V4SF_type_node,
8717 V4SI_type_node, NULL_TREE);
8718 tree v4sf_ftype_v4sf_v4sf_v4sf
8719 = build_function_type_list (V4SF_type_node,
8720 V4SF_type_node, V4SF_type_node,
8721 V4SF_type_node, NULL_TREE);
8722 tree v4si_ftype_v4si_v4si_v4si
8723 = build_function_type_list (V4SI_type_node,
8724 V4SI_type_node, V4SI_type_node,
8725 V4SI_type_node, NULL_TREE);
8726 tree v8hi_ftype_v8hi_v8hi
8727 = build_function_type_list (V8HI_type_node,
8728 V8HI_type_node, V8HI_type_node, NULL_TREE);
8729 tree v8hi_ftype_v8hi_v8hi_v8hi
8730 = build_function_type_list (V8HI_type_node,
8731 V8HI_type_node, V8HI_type_node,
8732 V8HI_type_node, NULL_TREE);
8733 tree v4si_ftype_v8hi_v8hi_v4si
8734 = build_function_type_list (V4SI_type_node,
8735 V8HI_type_node, V8HI_type_node,
8736 V4SI_type_node, NULL_TREE);
8737 tree v4si_ftype_v16qi_v16qi_v4si
8738 = build_function_type_list (V4SI_type_node,
8739 V16QI_type_node, V16QI_type_node,
8740 V4SI_type_node, NULL_TREE);
8741 tree v16qi_ftype_v16qi_v16qi
8742 = build_function_type_list (V16QI_type_node,
8743 V16QI_type_node, V16QI_type_node, NULL_TREE);
8744 tree v4si_ftype_v4sf_v4sf
8745 = build_function_type_list (V4SI_type_node,
8746 V4SF_type_node, V4SF_type_node, NULL_TREE);
8747 tree v8hi_ftype_v16qi_v16qi
8748 = build_function_type_list (V8HI_type_node,
8749 V16QI_type_node, V16QI_type_node, NULL_TREE);
8750 tree v4si_ftype_v8hi_v8hi
8751 = build_function_type_list (V4SI_type_node,
8752 V8HI_type_node, V8HI_type_node, NULL_TREE);
8753 tree v8hi_ftype_v4si_v4si
8754 = build_function_type_list (V8HI_type_node,
8755 V4SI_type_node, V4SI_type_node, NULL_TREE);
8756 tree v16qi_ftype_v8hi_v8hi
8757 = build_function_type_list (V16QI_type_node,
8758 V8HI_type_node, V8HI_type_node, NULL_TREE);
8759 tree v4si_ftype_v16qi_v4si
8760 = build_function_type_list (V4SI_type_node,
8761 V16QI_type_node, V4SI_type_node, NULL_TREE);
8762 tree v4si_ftype_v16qi_v16qi
8763 = build_function_type_list (V4SI_type_node,
8764 V16QI_type_node, V16QI_type_node, NULL_TREE);
8765 tree v4si_ftype_v8hi_v4si
8766 = build_function_type_list (V4SI_type_node,
8767 V8HI_type_node, V4SI_type_node, NULL_TREE);
8768 tree v4si_ftype_v8hi
8769 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8770 tree int_ftype_v4si_v4si
8771 = build_function_type_list (integer_type_node,
8772 V4SI_type_node, V4SI_type_node, NULL_TREE);
8773 tree int_ftype_v4sf_v4sf
8774 = build_function_type_list (integer_type_node,
8775 V4SF_type_node, V4SF_type_node, NULL_TREE);
8776 tree int_ftype_v16qi_v16qi
8777 = build_function_type_list (integer_type_node,
8778 V16QI_type_node, V16QI_type_node, NULL_TREE);
8779 tree int_ftype_v8hi_v8hi
8780 = build_function_type_list (integer_type_node,
8781 V8HI_type_node, V8HI_type_node, NULL_TREE);
8783 /* Add the simple ternary operators. */
8784 d = (struct builtin_description *) bdesc_3arg;
8785 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8787 enum machine_mode mode0, mode1, mode2, mode3;
8789 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8790 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8801 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8804 mode0 = insn_data[d->icode].operand[0].mode;
8805 mode1 = insn_data[d->icode].operand[1].mode;
8806 mode2 = insn_data[d->icode].operand[2].mode;
8807 mode3 = insn_data[d->icode].operand[3].mode;
8810 /* When all four are of the same mode. */
8811 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8816 type = opaque_ftype_opaque_opaque_opaque;
8819 type = v4si_ftype_v4si_v4si_v4si;
8822 type = v4sf_ftype_v4sf_v4sf_v4sf;
8825 type = v8hi_ftype_v8hi_v8hi_v8hi;
8828 type = v16qi_ftype_v16qi_v16qi_v16qi;
8834 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8839 type = v4si_ftype_v4si_v4si_v16qi;
8842 type = v4sf_ftype_v4sf_v4sf_v16qi;
8845 type = v8hi_ftype_v8hi_v8hi_v16qi;
8848 type = v16qi_ftype_v16qi_v16qi_v16qi;
8854 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8855 && mode3 == V4SImode)
8856 type = v4si_ftype_v16qi_v16qi_v4si;
8857 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8858 && mode3 == V4SImode)
8859 type = v4si_ftype_v8hi_v8hi_v4si;
8860 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8861 && mode3 == V4SImode)
8862 type = v4sf_ftype_v4sf_v4sf_v4si;
8864 /* vchar, vchar, vchar, 4 bit literal. */
8865 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8867 type = v16qi_ftype_v16qi_v16qi_int;
8869 /* vshort, vshort, vshort, 4 bit literal. */
8870 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8872 type = v8hi_ftype_v8hi_v8hi_int;
8874 /* vint, vint, vint, 4 bit literal. */
8875 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8877 type = v4si_ftype_v4si_v4si_int;
8879 /* vfloat, vfloat, vfloat, 4 bit literal. */
8880 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8882 type = v4sf_ftype_v4sf_v4sf_int;
8887 def_builtin (d->mask, d->name, type, d->code);
8890 /* Add the simple binary operators. */
8891 d = (struct builtin_description *) bdesc_2arg;
8892 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8894 enum machine_mode mode0, mode1, mode2;
8896 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8897 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8907 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8910 mode0 = insn_data[d->icode].operand[0].mode;
8911 mode1 = insn_data[d->icode].operand[1].mode;
8912 mode2 = insn_data[d->icode].operand[2].mode;
8915 /* When all three operands are of the same mode. */
8916 if (mode0 == mode1 && mode1 == mode2)
8921 type = opaque_ftype_opaque_opaque;
8924 type = v4sf_ftype_v4sf_v4sf;
8927 type = v4si_ftype_v4si_v4si;
8930 type = v16qi_ftype_v16qi_v16qi;
8933 type = v8hi_ftype_v8hi_v8hi;
8936 type = v2si_ftype_v2si_v2si;
8939 type = v2sf_ftype_v2sf_v2sf;
8942 type = int_ftype_int_int;
8949 /* A few other combos we really don't want to do manually. */
8951 /* vint, vfloat, vfloat. */
8952 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8953 type = v4si_ftype_v4sf_v4sf;
8955 /* vshort, vchar, vchar. */
8956 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8957 type = v8hi_ftype_v16qi_v16qi;
8959 /* vint, vshort, vshort. */
8960 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8961 type = v4si_ftype_v8hi_v8hi;
8963 /* vshort, vint, vint. */
8964 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8965 type = v8hi_ftype_v4si_v4si;
8967 /* vchar, vshort, vshort. */
8968 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8969 type = v16qi_ftype_v8hi_v8hi;
8971 /* vint, vchar, vint. */
8972 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8973 type = v4si_ftype_v16qi_v4si;
8975 /* vint, vchar, vchar. */
8976 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8977 type = v4si_ftype_v16qi_v16qi;
8979 /* vint, vshort, vint. */
8980 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8981 type = v4si_ftype_v8hi_v4si;
8983 /* vint, vint, 5 bit literal. */
8984 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8985 type = v4si_ftype_v4si_int;
8987 /* vshort, vshort, 5 bit literal. */
8988 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8989 type = v8hi_ftype_v8hi_int;
8991 /* vchar, vchar, 5 bit literal. */
8992 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8993 type = v16qi_ftype_v16qi_int;
8995 /* vfloat, vint, 5 bit literal. */
8996 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8997 type = v4sf_ftype_v4si_int;
8999 /* vint, vfloat, 5 bit literal. */
9000 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9001 type = v4si_ftype_v4sf_int;
9003 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9004 type = v2si_ftype_int_int;
9006 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9007 type = v2si_ftype_v2si_char;
9009 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9010 type = v2si_ftype_int_char;
9015 gcc_assert (mode0 == SImode);
9019 type = int_ftype_v4si_v4si;
9022 type = int_ftype_v4sf_v4sf;
9025 type = int_ftype_v16qi_v16qi;
9028 type = int_ftype_v8hi_v8hi;
9035 def_builtin (d->mask, d->name, type, d->code);
9038 /* Add the simple unary operators. */
9039 d = (struct builtin_description *) bdesc_1arg;
9040 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9042 enum machine_mode mode0, mode1;
9044 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9045 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9054 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9057 mode0 = insn_data[d->icode].operand[0].mode;
9058 mode1 = insn_data[d->icode].operand[1].mode;
9061 if (mode0 == V4SImode && mode1 == QImode)
9062 type = v4si_ftype_int;
9063 else if (mode0 == V8HImode && mode1 == QImode)
9064 type = v8hi_ftype_int;
9065 else if (mode0 == V16QImode && mode1 == QImode)
9066 type = v16qi_ftype_int;
9067 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9068 type = opaque_ftype_opaque;
9069 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9070 type = v4sf_ftype_v4sf;
9071 else if (mode0 == V8HImode && mode1 == V16QImode)
9072 type = v8hi_ftype_v16qi;
9073 else if (mode0 == V4SImode && mode1 == V8HImode)
9074 type = v4si_ftype_v8hi;
9075 else if (mode0 == V2SImode && mode1 == V2SImode)
9076 type = v2si_ftype_v2si;
9077 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9078 type = v2sf_ftype_v2sf;
9079 else if (mode0 == V2SFmode && mode1 == V2SImode)
9080 type = v2sf_ftype_v2si;
9081 else if (mode0 == V2SImode && mode1 == V2SFmode)
9082 type = v2si_ftype_v2sf;
9083 else if (mode0 == V2SImode && mode1 == QImode)
9084 type = v2si_ftype_char;
9088 def_builtin (d->mask, d->name, type, d->code);
9093 rs6000_init_libfuncs (void)
9095 if (!TARGET_HARD_FLOAT)
9098 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9099 && !TARGET_POWER2 && !TARGET_POWERPC)
9101 /* AIX library routines for float->int conversion. */
9102 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9103 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9104 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9105 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9108 if (!TARGET_IEEEQUAD)
9109 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9110 if (!TARGET_XL_COMPAT)
9112 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9113 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9114 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9115 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9119 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9120 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9121 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9122 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9126 /* 32-bit SVR4 quad floating point routines. */
9128 set_optab_libfunc (add_optab, TFmode, "_q_add");
9129 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9130 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9131 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9132 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9133 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9134 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9136 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9137 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9138 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9139 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9140 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9141 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9143 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9144 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9145 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9146 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9147 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9148 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9149 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9150 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9155 /* Expand a block clear operation, and return 1 if successful. Return 0
9156 if we should let the compiler generate normal code.
9158 operands[0] is the destination
9159 operands[1] is the length
9160 operands[3] is the alignment */
9163 expand_block_clear (rtx operands[])
9165 rtx orig_dest = operands[0];
9166 rtx bytes_rtx = operands[1];
9167 rtx align_rtx = operands[3];
9168 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9169 HOST_WIDE_INT align;
9170 HOST_WIDE_INT bytes;
9175 /* If this is not a fixed size move, just call memcpy */
9179 /* This must be a fixed size alignment */
9180 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9181 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9183 /* Anything to clear? */
9184 bytes = INTVAL (bytes_rtx);
9188 /* Use the builtin memset after a point, to avoid huge code bloat.
9189 When optimize_size, avoid any significant code bloat; calling
9190 memset is about 4 instructions, so allow for one instruction to
9191 load zero and three to do clearing. */
9192 if (TARGET_ALTIVEC && align >= 128)
9194 else if (TARGET_POWERPC64 && align >= 32)
9199 if (optimize_size && bytes > 3 * clear_step)
9201 if (! optimize_size && bytes > 8 * clear_step)
9204 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9206 enum machine_mode mode = BLKmode;
9209 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9214 else if (bytes >= 8 && TARGET_POWERPC64
9215 /* 64-bit loads and stores require word-aligned
9217 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9222 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9223 { /* move 4 bytes */
9227 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9228 { /* move 2 bytes */
9232 else /* move 1 byte at a time */
9238 dest = adjust_address (orig_dest, mode, offset);
9240 emit_move_insn (dest, CONST0_RTX (mode));
9247 /* Expand a block move operation, and return 1 if successful. Return 0
9248 if we should let the compiler generate normal code.
9250 operands[0] is the destination
9251 operands[1] is the source
9252 operands[2] is the length
9253 operands[3] is the alignment */
9255 #define MAX_MOVE_REG 4
9258 expand_block_move (rtx operands[])
9260 rtx orig_dest = operands[0];
9261 rtx orig_src = operands[1];
9262 rtx bytes_rtx = operands[2];
9263 rtx align_rtx = operands[3];
9264 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9269 rtx stores[MAX_MOVE_REG];
9272 /* If this is not a fixed size move, just call memcpy */
9276 /* This must be a fixed size alignment */
9277 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9278 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9280 /* Anything to move? */
9281 bytes = INTVAL (bytes_rtx);
9285 /* store_one_arg depends on expand_block_move to handle at least the size of
9286 reg_parm_stack_space. */
9287 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9290 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9293 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9294 rtx (*mov) (rtx, rtx);
9296 enum machine_mode mode = BLKmode;
9299 /* Altivec first, since it will be faster than a string move
9300 when it applies, and usually not significantly larger. */
9301 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9305 gen_func.mov = gen_movv4si;
9307 else if (TARGET_STRING
9308 && bytes > 24 /* move up to 32 bytes at a time */
9316 && ! fixed_regs[12])
9318 move_bytes = (bytes > 32) ? 32 : bytes;
9319 gen_func.movmemsi = gen_movmemsi_8reg;
9321 else if (TARGET_STRING
9322 && bytes > 16 /* move up to 24 bytes at a time */
9328 && ! fixed_regs[10])
9330 move_bytes = (bytes > 24) ? 24 : bytes;
9331 gen_func.movmemsi = gen_movmemsi_6reg;
9333 else if (TARGET_STRING
9334 && bytes > 8 /* move up to 16 bytes at a time */
9340 move_bytes = (bytes > 16) ? 16 : bytes;
9341 gen_func.movmemsi = gen_movmemsi_4reg;
9343 else if (bytes >= 8 && TARGET_POWERPC64
9344 /* 64-bit loads and stores require word-aligned
9346 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9350 gen_func.mov = gen_movdi;
9352 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9353 { /* move up to 8 bytes at a time */
9354 move_bytes = (bytes > 8) ? 8 : bytes;
9355 gen_func.movmemsi = gen_movmemsi_2reg;
9357 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9358 { /* move 4 bytes */
9361 gen_func.mov = gen_movsi;
9363 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9364 { /* move 2 bytes */
9367 gen_func.mov = gen_movhi;
9369 else if (TARGET_STRING && bytes > 1)
9370 { /* move up to 4 bytes at a time */
9371 move_bytes = (bytes > 4) ? 4 : bytes;
9372 gen_func.movmemsi = gen_movmemsi_1reg;
9374 else /* move 1 byte at a time */
9378 gen_func.mov = gen_movqi;
9381 src = adjust_address (orig_src, mode, offset);
9382 dest = adjust_address (orig_dest, mode, offset);
9384 if (mode != BLKmode)
9386 rtx tmp_reg = gen_reg_rtx (mode);
9388 emit_insn ((*gen_func.mov) (tmp_reg, src));
9389 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9392 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9395 for (i = 0; i < num_reg; i++)
9396 emit_insn (stores[i]);
9400 if (mode == BLKmode)
9402 /* Move the address into scratch registers. The movmemsi
9403 patterns require zero offset. */
9404 if (!REG_P (XEXP (src, 0)))
9406 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9407 src = replace_equiv_address (src, src_reg);
9409 set_mem_size (src, GEN_INT (move_bytes));
9411 if (!REG_P (XEXP (dest, 0)))
9413 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9414 dest = replace_equiv_address (dest, dest_reg);
9416 set_mem_size (dest, GEN_INT (move_bytes));
9418 emit_insn ((*gen_func.movmemsi) (dest, src,
9419 GEN_INT (move_bytes & 31),
9428 /* Return a string to perform a load_multiple operation.
9429 operands[0] is the vector.
9430 operands[1] is the source address.
9431 operands[2] is the first destination register. */
9434 rs6000_output_load_multiple (rtx operands[3])
9436 /* We have to handle the case where the pseudo used to contain the address
9437 is assigned to one of the output registers. */
9439 int words = XVECLEN (operands[0], 0);
9442 if (XVECLEN (operands[0], 0) == 1)
9443 return "{l|lwz} %2,0(%1)";
9445 for (i = 0; i < words; i++)
9446 if (refers_to_regno_p (REGNO (operands[2]) + i,
9447 REGNO (operands[2]) + i + 1, operands[1], 0))
9451 xop[0] = GEN_INT (4 * (words-1));
9452 xop[1] = operands[1];
9453 xop[2] = operands[2];
9454 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9459 xop[0] = GEN_INT (4 * (words-1));
9460 xop[1] = operands[1];
9461 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9462 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9467 for (j = 0; j < words; j++)
9470 xop[0] = GEN_INT (j * 4);
9471 xop[1] = operands[1];
9472 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9473 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9475 xop[0] = GEN_INT (i * 4);
9476 xop[1] = operands[1];
9477 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9482 return "{lsi|lswi} %2,%1,%N0";
9486 /* A validation routine: say whether CODE, a condition code, and MODE
9487 match. The other alternatives either don't make sense or should
9488 never be generated. */
9491 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9493 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9494 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9495 && GET_MODE_CLASS (mode) == MODE_CC);
9497 /* These don't make sense. */
9498 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9499 || mode != CCUNSmode);
9501 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9502 || mode == CCUNSmode);
9504 gcc_assert (mode == CCFPmode
9505 || (code != ORDERED && code != UNORDERED
9506 && code != UNEQ && code != LTGT
9507 && code != UNGT && code != UNLT
9508 && code != UNGE && code != UNLE));
9510 /* These should never be generated except for
9511 flag_finite_math_only. */
9512 gcc_assert (mode != CCFPmode
9513 || flag_finite_math_only
9514 || (code != LE && code != GE
9515 && code != UNEQ && code != LTGT
9516 && code != UNGT && code != UNLT));
9518 /* These are invalid; the information is not there. */
9519 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9523 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9524 mask required to convert the result of a rotate insn into a shift
9525 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9528 includes_lshift_p (rtx shiftop, rtx andop)
9530 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9532 shift_mask <<= INTVAL (shiftop);
9534 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9537 /* Similar, but for right shift. */
9540 includes_rshift_p (rtx shiftop, rtx andop)
9542 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9544 shift_mask >>= INTVAL (shiftop);
9546 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9549 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9550 to perform a left shift. It must have exactly SHIFTOP least
9551 significant 0's, then one or more 1's, then zero or more 0's. */
9554 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9556 if (GET_CODE (andop) == CONST_INT)
9558 HOST_WIDE_INT c, lsb, shift_mask;
9561 if (c == 0 || c == ~0)
9565 shift_mask <<= INTVAL (shiftop);
9567 /* Find the least significant one bit. */
9570 /* It must coincide with the LSB of the shift mask. */
9571 if (-lsb != shift_mask)
9574 /* Invert to look for the next transition (if any). */
9577 /* Remove the low group of ones (originally low group of zeros). */
9580 /* Again find the lsb, and check we have all 1's above. */
9584 else if (GET_CODE (andop) == CONST_DOUBLE
9585 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9587 HOST_WIDE_INT low, high, lsb;
9588 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9590 low = CONST_DOUBLE_LOW (andop);
9591 if (HOST_BITS_PER_WIDE_INT < 64)
9592 high = CONST_DOUBLE_HIGH (andop);
9594 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9595 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9598 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9600 shift_mask_high = ~0;
9601 if (INTVAL (shiftop) > 32)
9602 shift_mask_high <<= INTVAL (shiftop) - 32;
9606 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9613 return high == -lsb;
9616 shift_mask_low = ~0;
9617 shift_mask_low <<= INTVAL (shiftop);
9621 if (-lsb != shift_mask_low)
9624 if (HOST_BITS_PER_WIDE_INT < 64)
9629 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9632 return high == -lsb;
9636 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9642 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9643 to perform a left shift. It must have SHIFTOP or more least
9644 significant 0's, with the remainder of the word 1's. */
9647 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9649 if (GET_CODE (andop) == CONST_INT)
9651 HOST_WIDE_INT c, lsb, shift_mask;
9654 shift_mask <<= INTVAL (shiftop);
9657 /* Find the least significant one bit. */
9660 /* It must be covered by the shift mask.
9661 This test also rejects c == 0. */
9662 if ((lsb & shift_mask) == 0)
9665 /* Check we have all 1's above the transition, and reject all 1's. */
9666 return c == -lsb && lsb != 1;
9668 else if (GET_CODE (andop) == CONST_DOUBLE
9669 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9671 HOST_WIDE_INT low, lsb, shift_mask_low;
9673 low = CONST_DOUBLE_LOW (andop);
9675 if (HOST_BITS_PER_WIDE_INT < 64)
9677 HOST_WIDE_INT high, shift_mask_high;
9679 high = CONST_DOUBLE_HIGH (andop);
9683 shift_mask_high = ~0;
9684 if (INTVAL (shiftop) > 32)
9685 shift_mask_high <<= INTVAL (shiftop) - 32;
9689 if ((lsb & shift_mask_high) == 0)
9692 return high == -lsb;
9698 shift_mask_low = ~0;
9699 shift_mask_low <<= INTVAL (shiftop);
9703 if ((lsb & shift_mask_low) == 0)
9706 return low == -lsb && lsb != 1;
9712 /* Return 1 if operands will generate a valid arguments to rlwimi
9713 instruction for insert with right shift in 64-bit mode. The mask may
9714 not start on the first bit or stop on the last bit because wrap-around
9715 effects of instruction do not correspond to semantics of RTL insn. */
9718 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9720 if (INTVAL (startop) < 64
9721 && INTVAL (startop) > 32
9722 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9723 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9724 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9725 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9726 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9732 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9733 for lfq and stfq insns iff the registers are hard registers. */
9736 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9738 /* We might have been passed a SUBREG. */
9739 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9742 /* We might have been passed non floating point registers. */
9743 if (!FP_REGNO_P (REGNO (reg1))
9744 || !FP_REGNO_P (REGNO (reg2)))
9747 return (REGNO (reg1) == REGNO (reg2) - 1);
9750 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9751 addr1 and addr2 must be in consecutive memory locations
9752 (addr2 == addr1 + 8). */
9755 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9758 unsigned int reg1, reg2;
9759 int offset1, offset2;
9761 /* The mems cannot be volatile. */
9762 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9765 addr1 = XEXP (mem1, 0);
9766 addr2 = XEXP (mem2, 0);
9768 /* Extract an offset (if used) from the first addr. */
9769 if (GET_CODE (addr1) == PLUS)
9771 /* If not a REG, return zero. */
9772 if (GET_CODE (XEXP (addr1, 0)) != REG)
9776 reg1 = REGNO (XEXP (addr1, 0));
9777 /* The offset must be constant! */
9778 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9780 offset1 = INTVAL (XEXP (addr1, 1));
9783 else if (GET_CODE (addr1) != REG)
9787 reg1 = REGNO (addr1);
9788 /* This was a simple (mem (reg)) expression. Offset is 0. */
9792 /* And now for the second addr. */
9793 if (GET_CODE (addr2) == PLUS)
9795 /* If not a REG, return zero. */
9796 if (GET_CODE (XEXP (addr2, 0)) != REG)
9800 reg2 = REGNO (XEXP (addr2, 0));
9801 /* The offset must be constant. */
9802 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9804 offset2 = INTVAL (XEXP (addr2, 1));
9807 else if (GET_CODE (addr2) != REG)
9811 reg2 = REGNO (addr2);
9812 /* This was a simple (mem (reg)) expression. Offset is 0. */
9816 /* Both of these must have the same base register. */
9820 /* The offset for the second addr must be 8 more than the first addr. */
9821 if (offset2 != offset1 + 8)
9824 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9829 /* Return the register class of a scratch register needed to copy IN into
9830 or out of a register in CLASS in MODE. If it can be done directly,
9831 NO_REGS is returned. */
9834 rs6000_secondary_reload_class (enum reg_class class,
9835 enum machine_mode mode ATTRIBUTE_UNUSED,
9840 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9842 && MACHOPIC_INDIRECT
9846 /* We cannot copy a symbolic operand directly into anything
9847 other than BASE_REGS for TARGET_ELF. So indicate that a
9848 register from BASE_REGS is needed as an intermediate
9851 On Darwin, pic addresses require a load from memory, which
9852 needs a base register. */
9853 if (class != BASE_REGS
9854 && (GET_CODE (in) == SYMBOL_REF
9855 || GET_CODE (in) == HIGH
9856 || GET_CODE (in) == LABEL_REF
9857 || GET_CODE (in) == CONST))
9861 if (GET_CODE (in) == REG)
9864 if (regno >= FIRST_PSEUDO_REGISTER)
9866 regno = true_regnum (in);
9867 if (regno >= FIRST_PSEUDO_REGISTER)
9871 else if (GET_CODE (in) == SUBREG)
9873 regno = true_regnum (in);
9874 if (regno >= FIRST_PSEUDO_REGISTER)
9880 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9882 if (class == GENERAL_REGS || class == BASE_REGS
9883 || (regno >= 0 && INT_REGNO_P (regno)))
9886 /* Constants, memory, and FP registers can go into FP registers. */
9887 if ((regno == -1 || FP_REGNO_P (regno))
9888 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9891 /* Memory, and AltiVec registers can go into AltiVec registers. */
9892 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9893 && class == ALTIVEC_REGS)
9896 /* We can copy among the CR registers. */
9897 if ((class == CR_REGS || class == CR0_REGS)
9898 && regno >= 0 && CR_REGNO_P (regno))
9901 /* Otherwise, we need GENERAL_REGS. */
9902 return GENERAL_REGS;
9905 /* Given a comparison operation, return the bit number in CCR to test. We
9906 know this is a valid comparison.
9908 SCC_P is 1 if this is for an scc. That means that %D will have been
9909 used instead of %C, so the bits will be in different places.
9911 Return -1 if OP isn't a valid comparison for some reason. */
9914 ccr_bit (rtx op, int scc_p)
9916 enum rtx_code code = GET_CODE (op);
9917 enum machine_mode cc_mode;
9922 if (!COMPARISON_P (op))
9927 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9929 cc_mode = GET_MODE (reg);
9930 cc_regnum = REGNO (reg);
9931 base_bit = 4 * (cc_regnum - CR0_REGNO);
9933 validate_condition_mode (code, cc_mode);
9935 /* When generating a sCOND operation, only positive conditions are
9938 || code == EQ || code == GT || code == LT || code == UNORDERED
9939 || code == GTU || code == LTU);
9944 return scc_p ? base_bit + 3 : base_bit + 2;
9946 return base_bit + 2;
9947 case GT: case GTU: case UNLE:
9948 return base_bit + 1;
9949 case LT: case LTU: case UNGE:
9951 case ORDERED: case UNORDERED:
9952 return base_bit + 3;
9955 /* If scc, we will have done a cror to put the bit in the
9956 unordered position. So test that bit. For integer, this is ! LT
9957 unless this is an scc insn. */
9958 return scc_p ? base_bit + 3 : base_bit;
9961 return scc_p ? base_bit + 3 : base_bit + 1;
9968 /* Return the GOT register. */
9971 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9973 /* The second flow pass currently (June 1999) can't update
9974 regs_ever_live without disturbing other parts of the compiler, so
9975 update it here to make the prolog/epilogue code happy. */
9976 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9977 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9979 current_function_uses_pic_offset_table = 1;
9981 return pic_offset_table_rtx;
9984 /* Function to init struct machine_function.
9985 This will be called, via a pointer variable,
9986 from push_function_context. */
9988 static struct machine_function *
9989 rs6000_init_machine_status (void)
9991 return ggc_alloc_cleared (sizeof (machine_function));
9994 /* These macros test for integers and extract the low-order bits. */
9996 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9997 && GET_MODE (X) == VOIDmode)
9999 #define INT_LOWPART(X) \
10000 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10003 extract_MB (rtx op)
10006 unsigned long val = INT_LOWPART (op);
10008 /* If the high bit is zero, the value is the first 1 bit we find
10010 if ((val & 0x80000000) == 0)
10012 gcc_assert (val & 0xffffffff);
10015 while (((val <<= 1) & 0x80000000) == 0)
10020 /* If the high bit is set and the low bit is not, or the mask is all
10021 1's, the value is zero. */
10022 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10025 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10028 while (((val >>= 1) & 1) != 0)
10035 extract_ME (rtx op)
10038 unsigned long val = INT_LOWPART (op);
10040 /* If the low bit is zero, the value is the first 1 bit we find from
10042 if ((val & 1) == 0)
10044 gcc_assert (val & 0xffffffff);
10047 while (((val >>= 1) & 1) == 0)
10053 /* If the low bit is set and the high bit is not, or the mask is all
10054 1's, the value is 31. */
10055 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10058 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10061 while (((val <<= 1) & 0x80000000) != 0)
10067 /* Locate some local-dynamic symbol still in use by this function
10068 so that we can print its name in some tls_ld pattern. */
10070 static const char *
10071 rs6000_get_some_local_dynamic_name (void)
10075 if (cfun->machine->some_ld_name)
10076 return cfun->machine->some_ld_name;
10078 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10080 && for_each_rtx (&PATTERN (insn),
10081 rs6000_get_some_local_dynamic_name_1, 0))
10082 return cfun->machine->some_ld_name;
10084 gcc_unreachable ();
10087 /* Helper function for rs6000_get_some_local_dynamic_name. */
10090 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10094 if (GET_CODE (x) == SYMBOL_REF)
10096 const char *str = XSTR (x, 0);
10097 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10099 cfun->machine->some_ld_name = str;
10107 /* Write out a function code label. */
10110 rs6000_output_function_entry (FILE *file, const char *fname)
10112 if (fname[0] != '.')
10114 switch (DEFAULT_ABI)
10117 gcc_unreachable ();
10123 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10132 RS6000_OUTPUT_BASENAME (file, fname);
10134 assemble_name (file, fname);
10137 /* Print an operand. Recognize special options, documented below. */
10140 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10141 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10143 #define SMALL_DATA_RELOC "sda21"
10144 #define SMALL_DATA_REG 0
10148 print_operand (FILE *file, rtx x, int code)
10152 unsigned HOST_WIDE_INT uval;
10157 /* Write out an instruction after the call which may be replaced
10158 with glue code by the loader. This depends on the AIX version. */
10159 asm_fprintf (file, RS6000_CALL_GLUE);
10162 /* %a is output_address. */
10165 /* If X is a constant integer whose low-order 5 bits are zero,
10166 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10167 in the AIX assembler where "sri" with a zero shift count
10168 writes a trash instruction. */
10169 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10176 /* If constant, low-order 16 bits of constant, unsigned.
10177 Otherwise, write normally. */
10179 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10181 print_operand (file, x, 0);
10185 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10186 for 64-bit mask direction. */
10187 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10190 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10194 /* X is a CR register. Print the number of the GT bit of the CR. */
10195 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10196 output_operand_lossage ("invalid %%E value");
10198 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10202 /* Like 'J' but get to the EQ bit. */
10203 gcc_assert (GET_CODE (x) == REG);
10205 /* Bit 1 is EQ bit. */
10206 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10208 fprintf (file, "%d", i);
10212 /* X is a CR register. Print the number of the EQ bit of the CR */
10213 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10214 output_operand_lossage ("invalid %%E value");
10216 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10220 /* X is a CR register. Print the shift count needed to move it
10221 to the high-order four bits. */
10222 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10223 output_operand_lossage ("invalid %%f value");
10225 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10229 /* Similar, but print the count for the rotate in the opposite
10231 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10232 output_operand_lossage ("invalid %%F value");
10234 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10238 /* X is a constant integer. If it is negative, print "m",
10239 otherwise print "z". This is to make an aze or ame insn. */
10240 if (GET_CODE (x) != CONST_INT)
10241 output_operand_lossage ("invalid %%G value");
10242 else if (INTVAL (x) >= 0)
10249 /* If constant, output low-order five bits. Otherwise, write
10252 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10254 print_operand (file, x, 0);
10258 /* If constant, output low-order six bits. Otherwise, write
10261 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10263 print_operand (file, x, 0);
10267 /* Print `i' if this is a constant, else nothing. */
10273 /* Write the bit number in CCR for jump. */
10274 i = ccr_bit (x, 0);
10276 output_operand_lossage ("invalid %%j code");
10278 fprintf (file, "%d", i);
10282 /* Similar, but add one for shift count in rlinm for scc and pass
10283 scc flag to `ccr_bit'. */
10284 i = ccr_bit (x, 1);
10286 output_operand_lossage ("invalid %%J code");
10288 /* If we want bit 31, write a shift count of zero, not 32. */
10289 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10293 /* X must be a constant. Write the 1's complement of the
10296 output_operand_lossage ("invalid %%k value");
10298 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10302 /* X must be a symbolic constant on ELF. Write an
10303 expression suitable for an 'addi' that adds in the low 16
10304 bits of the MEM. */
10305 if (GET_CODE (x) != CONST)
10307 print_operand_address (file, x);
10308 fputs ("@l", file);
10312 if (GET_CODE (XEXP (x, 0)) != PLUS
10313 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10314 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10315 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10316 output_operand_lossage ("invalid %%K value");
10317 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10318 fputs ("@l", file);
10319 /* For GNU as, there must be a non-alphanumeric character
10320 between 'l' and the number. The '-' is added by
10321 print_operand() already. */
10322 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10324 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10328 /* %l is output_asm_label. */
10331 /* Write second word of DImode or DFmode reference. Works on register
10332 or non-indexed memory only. */
10333 if (GET_CODE (x) == REG)
10334 fputs (reg_names[REGNO (x) + 1], file);
10335 else if (GET_CODE (x) == MEM)
10337 /* Handle possible auto-increment. Since it is pre-increment and
10338 we have already done it, we can just use an offset of word. */
10339 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10340 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10341 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10344 output_address (XEXP (adjust_address_nv (x, SImode,
10348 if (small_data_operand (x, GET_MODE (x)))
10349 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10350 reg_names[SMALL_DATA_REG]);
10355 /* MB value for a mask operand. */
10356 if (! mask_operand (x, SImode))
10357 output_operand_lossage ("invalid %%m value");
10359 fprintf (file, "%d", extract_MB (x));
10363 /* ME value for a mask operand. */
10364 if (! mask_operand (x, SImode))
10365 output_operand_lossage ("invalid %%M value");
10367 fprintf (file, "%d", extract_ME (x));
10370 /* %n outputs the negative of its operand. */
10373 /* Write the number of elements in the vector times 4. */
10374 if (GET_CODE (x) != PARALLEL)
10375 output_operand_lossage ("invalid %%N value");
10377 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10381 /* Similar, but subtract 1 first. */
10382 if (GET_CODE (x) != PARALLEL)
10383 output_operand_lossage ("invalid %%O value");
10385 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10389 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10391 || INT_LOWPART (x) < 0
10392 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10393 output_operand_lossage ("invalid %%p value");
10395 fprintf (file, "%d", i);
10399 /* The operand must be an indirect memory reference. The result
10400 is the register name. */
10401 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10402 || REGNO (XEXP (x, 0)) >= 32)
10403 output_operand_lossage ("invalid %%P value");
10405 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10409 /* This outputs the logical code corresponding to a boolean
10410 expression. The expression may have one or both operands
10411 negated (if one, only the first one). For condition register
10412 logical operations, it will also treat the negated
10413 CR codes as NOTs, but not handle NOTs of them. */
10415 const char *const *t = 0;
10417 enum rtx_code code = GET_CODE (x);
10418 static const char * const tbl[3][3] = {
10419 { "and", "andc", "nor" },
10420 { "or", "orc", "nand" },
10421 { "xor", "eqv", "xor" } };
10425 else if (code == IOR)
10427 else if (code == XOR)
10430 output_operand_lossage ("invalid %%q value");
10432 if (GET_CODE (XEXP (x, 0)) != NOT)
10436 if (GET_CODE (XEXP (x, 1)) == NOT)
10454 /* X is a CR register. Print the mask for `mtcrf'. */
10455 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10456 output_operand_lossage ("invalid %%R value");
10458 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10462 /* Low 5 bits of 32 - value */
10464 output_operand_lossage ("invalid %%s value");
10466 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10470 /* PowerPC64 mask position. All 0's is excluded.
10471 CONST_INT 32-bit mask is considered sign-extended so any
10472 transition must occur within the CONST_INT, not on the boundary. */
10473 if (! mask64_operand (x, DImode))
10474 output_operand_lossage ("invalid %%S value");
10476 uval = INT_LOWPART (x);
10478 if (uval & 1) /* Clear Left */
10480 #if HOST_BITS_PER_WIDE_INT > 64
10481 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10485 else /* Clear Right */
10488 #if HOST_BITS_PER_WIDE_INT > 64
10489 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10495 gcc_assert (i >= 0);
10496 fprintf (file, "%d", i);
10500 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10501 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10503 /* Bit 3 is OV bit. */
10504 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10506 /* If we want bit 31, write a shift count of zero, not 32. */
10507 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10511 /* Print the symbolic name of a branch target register. */
10512 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10513 && REGNO (x) != COUNT_REGISTER_REGNUM))
10514 output_operand_lossage ("invalid %%T value");
10515 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10516 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10518 fputs ("ctr", file);
10522 /* High-order 16 bits of constant for use in unsigned operand. */
10524 output_operand_lossage ("invalid %%u value");
10526 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10527 (INT_LOWPART (x) >> 16) & 0xffff);
10531 /* High-order 16 bits of constant for use in signed operand. */
10533 output_operand_lossage ("invalid %%v value");
10535 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10536 (INT_LOWPART (x) >> 16) & 0xffff);
10540 /* Print `u' if this has an auto-increment or auto-decrement. */
10541 if (GET_CODE (x) == MEM
10542 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10543 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10548 /* Print the trap code for this operand. */
10549 switch (GET_CODE (x))
10552 fputs ("eq", file); /* 4 */
10555 fputs ("ne", file); /* 24 */
10558 fputs ("lt", file); /* 16 */
10561 fputs ("le", file); /* 20 */
10564 fputs ("gt", file); /* 8 */
10567 fputs ("ge", file); /* 12 */
10570 fputs ("llt", file); /* 2 */
10573 fputs ("lle", file); /* 6 */
10576 fputs ("lgt", file); /* 1 */
10579 fputs ("lge", file); /* 5 */
10582 gcc_unreachable ();
10587 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10590 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10591 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10593 print_operand (file, x, 0);
10597 /* MB value for a PowerPC64 rldic operand. */
10598 val = (GET_CODE (x) == CONST_INT
10599 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10604 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10605 if ((val <<= 1) < 0)
10608 #if HOST_BITS_PER_WIDE_INT == 32
10609 if (GET_CODE (x) == CONST_INT && i >= 0)
10610 i += 32; /* zero-extend high-part was all 0's */
10611 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10613 val = CONST_DOUBLE_LOW (x);
10619 for ( ; i < 64; i++)
10620 if ((val <<= 1) < 0)
10625 fprintf (file, "%d", i + 1);
10629 if (GET_CODE (x) == MEM
10630 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10635 /* Like 'L', for third word of TImode */
10636 if (GET_CODE (x) == REG)
10637 fputs (reg_names[REGNO (x) + 2], file);
10638 else if (GET_CODE (x) == MEM)
10640 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10641 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10642 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10644 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10645 if (small_data_operand (x, GET_MODE (x)))
10646 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10647 reg_names[SMALL_DATA_REG]);
10652 /* X is a SYMBOL_REF. Write out the name preceded by a
10653 period and without any trailing data in brackets. Used for function
10654 names. If we are configured for System V (or the embedded ABI) on
10655 the PowerPC, do not emit the period, since those systems do not use
10656 TOCs and the like. */
10657 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10659 /* Mark the decl as referenced so that cgraph will output the
10661 if (SYMBOL_REF_DECL (x))
10662 mark_decl_referenced (SYMBOL_REF_DECL (x));
10664 /* For macho, check to see if we need a stub. */
10667 const char *name = XSTR (x, 0);
10669 if (MACHOPIC_INDIRECT
10670 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10671 name = machopic_indirection_name (x, /*stub_p=*/true);
10673 assemble_name (file, name);
10675 else if (!DOT_SYMBOLS)
10676 assemble_name (file, XSTR (x, 0));
10678 rs6000_output_function_entry (file, XSTR (x, 0));
10682 /* Like 'L', for last word of TImode. */
10683 if (GET_CODE (x) == REG)
10684 fputs (reg_names[REGNO (x) + 3], file);
10685 else if (GET_CODE (x) == MEM)
10687 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10688 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10689 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10691 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10692 if (small_data_operand (x, GET_MODE (x)))
10693 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10694 reg_names[SMALL_DATA_REG]);
10698 /* Print AltiVec or SPE memory operand. */
10703 gcc_assert (GET_CODE (x) == MEM);
10709 /* Handle [reg]. */
10710 if (GET_CODE (tmp) == REG)
10712 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10715 /* Handle [reg+UIMM]. */
10716 else if (GET_CODE (tmp) == PLUS &&
10717 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10721 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10723 x = INTVAL (XEXP (tmp, 1));
10724 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10728 /* Fall through. Must be [reg+reg]. */
10731 && GET_CODE (tmp) == AND
10732 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10733 && INTVAL (XEXP (tmp, 1)) == -16)
10734 tmp = XEXP (tmp, 0);
10735 if (GET_CODE (tmp) == REG)
10736 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10739 gcc_assert (GET_CODE (tmp) == PLUS
10740 && REG_P (XEXP (tmp, 0))
10741 && REG_P (XEXP (tmp, 1)));
10743 if (REGNO (XEXP (tmp, 0)) == 0)
10744 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10745 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10747 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10748 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10754 if (GET_CODE (x) == REG)
10755 fprintf (file, "%s", reg_names[REGNO (x)]);
10756 else if (GET_CODE (x) == MEM)
10758 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10759 know the width from the mode. */
10760 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10761 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10762 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10763 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10764 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10765 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10767 output_address (XEXP (x, 0));
10770 output_addr_const (file, x);
10774 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10778 output_operand_lossage ("invalid %%xn code");
10782 /* Print the address of an operand. */
10785 print_operand_address (FILE *file, rtx x)
10787 if (GET_CODE (x) == REG)
10788 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10789 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10790 || GET_CODE (x) == LABEL_REF)
10792 output_addr_const (file, x);
10793 if (small_data_operand (x, GET_MODE (x)))
10794 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10795 reg_names[SMALL_DATA_REG]);
10797 gcc_assert (!TARGET_TOC);
10799 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10801 gcc_assert (REG_P (XEXP (x, 0)));
10802 if (REGNO (XEXP (x, 0)) == 0)
10803 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10804 reg_names[ REGNO (XEXP (x, 0)) ]);
10806 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10807 reg_names[ REGNO (XEXP (x, 1)) ]);
10809 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10810 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10811 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10813 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10814 && CONSTANT_P (XEXP (x, 1)))
10816 output_addr_const (file, XEXP (x, 1));
10817 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10821 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10822 && CONSTANT_P (XEXP (x, 1)))
10824 fprintf (file, "lo16(");
10825 output_addr_const (file, XEXP (x, 1));
10826 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10829 else if (legitimate_constant_pool_address_p (x))
10831 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10833 rtx contains_minus = XEXP (x, 1);
10837 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10838 turn it into (sym) for output_addr_const. */
10839 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10840 contains_minus = XEXP (contains_minus, 0);
10842 minus = XEXP (contains_minus, 0);
10843 symref = XEXP (minus, 0);
10844 XEXP (contains_minus, 0) = symref;
10849 name = XSTR (symref, 0);
10850 newname = alloca (strlen (name) + sizeof ("@toc"));
10851 strcpy (newname, name);
10852 strcat (newname, "@toc");
10853 XSTR (symref, 0) = newname;
10855 output_addr_const (file, XEXP (x, 1));
10857 XSTR (symref, 0) = name;
10858 XEXP (contains_minus, 0) = minus;
10861 output_addr_const (file, XEXP (x, 1));
10863 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10866 gcc_unreachable ();
10869 /* Target hook for assembling integer objects. The PowerPC version has
10870 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10871 is defined. It also needs to handle DI-mode objects on 64-bit
10875 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10877 #ifdef RELOCATABLE_NEEDS_FIXUP
10878 /* Special handling for SI values. */
10879 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10881 static int recurse = 0;
10883 /* For -mrelocatable, we mark all addresses that need to be fixed up
10884 in the .fixup section. */
10885 if (TARGET_RELOCATABLE
10886 && in_section != toc_section
10887 && in_section != text_section
10888 && !unlikely_text_section_p (in_section)
10890 && GET_CODE (x) != CONST_INT
10891 && GET_CODE (x) != CONST_DOUBLE
10897 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10899 ASM_OUTPUT_LABEL (asm_out_file, buf);
10900 fprintf (asm_out_file, "\t.long\t(");
10901 output_addr_const (asm_out_file, x);
10902 fprintf (asm_out_file, ")@fixup\n");
10903 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10904 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10905 fprintf (asm_out_file, "\t.long\t");
10906 assemble_name (asm_out_file, buf);
10907 fprintf (asm_out_file, "\n\t.previous\n");
10911 /* Remove initial .'s to turn a -mcall-aixdesc function
10912 address into the address of the descriptor, not the function
10914 else if (GET_CODE (x) == SYMBOL_REF
10915 && XSTR (x, 0)[0] == '.'
10916 && DEFAULT_ABI == ABI_AIX)
10918 const char *name = XSTR (x, 0);
10919 while (*name == '.')
10922 fprintf (asm_out_file, "\t.long\t%s\n", name);
10926 #endif /* RELOCATABLE_NEEDS_FIXUP */
10927 return default_assemble_integer (x, size, aligned_p);
10930 #ifdef HAVE_GAS_HIDDEN
10931 /* Emit an assembler directive to set symbol visibility for DECL to
10932 VISIBILITY_TYPE. */
10935 rs6000_assemble_visibility (tree decl, int vis)
10937 /* Functions need to have their entry point symbol visibility set as
10938 well as their descriptor symbol visibility. */
10939 if (DEFAULT_ABI == ABI_AIX
10941 && TREE_CODE (decl) == FUNCTION_DECL)
10943 static const char * const visibility_types[] = {
10944 NULL, "internal", "hidden", "protected"
10947 const char *name, *type;
10949 name = ((* targetm.strip_name_encoding)
10950 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10951 type = visibility_types[vis];
10953 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10954 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10957 default_assemble_visibility (decl, vis);
10962 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10964 /* Reversal of FP compares takes care -- an ordered compare
10965 becomes an unordered compare and vice versa. */
10966 if (mode == CCFPmode
10967 && (!flag_finite_math_only
10968 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10969 || code == UNEQ || code == LTGT))
10970 return reverse_condition_maybe_unordered (code);
10972 return reverse_condition (code);
10975 /* Generate a compare for CODE. Return a brand-new rtx that
10976 represents the result of the compare. */
10979 rs6000_generate_compare (enum rtx_code code)
10981 enum machine_mode comp_mode;
10982 rtx compare_result;
10984 if (rs6000_compare_fp_p)
10985 comp_mode = CCFPmode;
10986 else if (code == GTU || code == LTU
10987 || code == GEU || code == LEU)
10988 comp_mode = CCUNSmode;
10989 else if ((code == EQ || code == NE)
10990 && GET_CODE (rs6000_compare_op0) == SUBREG
10991 && GET_CODE (rs6000_compare_op1) == SUBREG
10992 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10993 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10994 /* These are unsigned values, perhaps there will be a later
10995 ordering compare that can be shared with this one.
10996 Unfortunately we cannot detect the signedness of the operands
10997 for non-subregs. */
10998 comp_mode = CCUNSmode;
11000 comp_mode = CCmode;
11002 /* First, the compare. */
11003 compare_result = gen_reg_rtx (comp_mode);
11005 /* SPE FP compare instructions on the GPRs. Yuck! */
11006 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11007 && rs6000_compare_fp_p)
11009 rtx cmp, or_result, compare_result2;
11010 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11012 if (op_mode == VOIDmode)
11013 op_mode = GET_MODE (rs6000_compare_op1);
11015 /* Note: The E500 comparison instructions set the GT bit (x +
11016 1), on success. This explains the mess. */
11020 case EQ: case UNEQ: case NE: case LTGT:
11024 cmp = flag_unsafe_math_optimizations
11025 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11026 rs6000_compare_op1)
11027 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11028 rs6000_compare_op1);
11032 cmp = flag_unsafe_math_optimizations
11033 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11034 rs6000_compare_op1)
11035 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11036 rs6000_compare_op1);
11040 gcc_unreachable ();
11044 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11048 cmp = flag_unsafe_math_optimizations
11049 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11050 rs6000_compare_op1)
11051 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11052 rs6000_compare_op1);
11056 cmp = flag_unsafe_math_optimizations
11057 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11058 rs6000_compare_op1)
11059 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11060 rs6000_compare_op1);
11064 gcc_unreachable ();
11068 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11072 cmp = flag_unsafe_math_optimizations
11073 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11074 rs6000_compare_op1)
11075 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11076 rs6000_compare_op1);
11080 cmp = flag_unsafe_math_optimizations
11081 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11082 rs6000_compare_op1)
11083 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11084 rs6000_compare_op1);
11088 gcc_unreachable ();
11092 gcc_unreachable ();
11095 /* Synthesize LE and GE from LT/GT || EQ. */
11096 if (code == LE || code == GE || code == LEU || code == GEU)
11102 case LE: code = LT; break;
11103 case GE: code = GT; break;
11104 case LEU: code = LT; break;
11105 case GEU: code = GT; break;
11106 default: gcc_unreachable ();
11109 compare_result2 = gen_reg_rtx (CCFPmode);
11115 cmp = flag_unsafe_math_optimizations
11116 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11117 rs6000_compare_op1)
11118 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11119 rs6000_compare_op1);
11123 cmp = flag_unsafe_math_optimizations
11124 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11125 rs6000_compare_op1)
11126 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11127 rs6000_compare_op1);
11131 gcc_unreachable ();
11135 /* OR them together. */
11136 or_result = gen_reg_rtx (CCFPmode);
11137 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11139 compare_result = or_result;
11144 if (code == NE || code == LTGT)
11154 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11155 CLOBBERs to match cmptf_internal2 pattern. */
11156 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11157 && GET_MODE (rs6000_compare_op0) == TFmode
11158 && !TARGET_IEEEQUAD
11159 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11160 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11162 gen_rtx_SET (VOIDmode,
11164 gen_rtx_COMPARE (comp_mode,
11165 rs6000_compare_op0,
11166 rs6000_compare_op1)),
11167 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11168 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11169 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11170 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11171 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11172 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11173 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11174 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11175 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11176 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11178 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11179 comp_mode = CCEQmode;
11180 compare_result = gen_reg_rtx (CCEQmode);
11182 emit_insn (gen_stack_protect_testdi (compare_result,
11183 rs6000_compare_op0, op1));
11185 emit_insn (gen_stack_protect_testsi (compare_result,
11186 rs6000_compare_op0, op1));
11189 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11190 gen_rtx_COMPARE (comp_mode,
11191 rs6000_compare_op0,
11192 rs6000_compare_op1)));
11195 /* Some kinds of FP comparisons need an OR operation;
11196 under flag_finite_math_only we don't bother. */
11197 if (rs6000_compare_fp_p
11198 && !flag_finite_math_only
11199 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11200 && (code == LE || code == GE
11201 || code == UNEQ || code == LTGT
11202 || code == UNGT || code == UNLT))
11204 enum rtx_code or1, or2;
11205 rtx or1_rtx, or2_rtx, compare2_rtx;
11206 rtx or_result = gen_reg_rtx (CCEQmode);
11210 case LE: or1 = LT; or2 = EQ; break;
11211 case GE: or1 = GT; or2 = EQ; break;
11212 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11213 case LTGT: or1 = LT; or2 = GT; break;
11214 case UNGT: or1 = UNORDERED; or2 = GT; break;
11215 case UNLT: or1 = UNORDERED; or2 = LT; break;
11216 default: gcc_unreachable ();
11218 validate_condition_mode (or1, comp_mode);
11219 validate_condition_mode (or2, comp_mode);
11220 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11221 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11222 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11223 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11225 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11227 compare_result = or_result;
11231 validate_condition_mode (code, GET_MODE (compare_result));
11233 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11237 /* Emit the RTL for an sCOND pattern. */
11240 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11243 enum machine_mode op_mode;
11244 enum rtx_code cond_code;
11246 condition_rtx = rs6000_generate_compare (code);
11247 cond_code = GET_CODE (condition_rtx);
11249 if (TARGET_E500 && rs6000_compare_fp_p
11250 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11254 PUT_MODE (condition_rtx, SImode);
11255 t = XEXP (condition_rtx, 0);
11257 gcc_assert (cond_code == NE || cond_code == EQ);
11259 if (cond_code == NE)
11260 emit_insn (gen_e500_flip_gt_bit (t, t));
11262 emit_insn (gen_move_from_CR_gt_bit (result, t));
11266 if (cond_code == NE
11267 || cond_code == GE || cond_code == LE
11268 || cond_code == GEU || cond_code == LEU
11269 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11271 rtx not_result = gen_reg_rtx (CCEQmode);
11272 rtx not_op, rev_cond_rtx;
11273 enum machine_mode cc_mode;
11275 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11277 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11278 SImode, XEXP (condition_rtx, 0), const0_rtx);
11279 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11280 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11281 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11284 op_mode = GET_MODE (rs6000_compare_op0);
11285 if (op_mode == VOIDmode)
11286 op_mode = GET_MODE (rs6000_compare_op1);
11288 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11290 PUT_MODE (condition_rtx, DImode);
11291 convert_move (result, condition_rtx, 0);
11295 PUT_MODE (condition_rtx, SImode);
11296 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11300 /* Emit a branch of kind CODE to location LOC. */
11303 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11305 rtx condition_rtx, loc_ref;
11307 condition_rtx = rs6000_generate_compare (code);
11308 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11309 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11310 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11311 loc_ref, pc_rtx)));
11314 /* Return the string to output a conditional branch to LABEL, which is
11315 the operand number of the label, or -1 if the branch is really a
11316 conditional return.
11318 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11319 condition code register and its mode specifies what kind of
11320 comparison we made.
11322 REVERSED is nonzero if we should reverse the sense of the comparison.
11324 INSN is the insn. */
11327 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11329 static char string[64];
11330 enum rtx_code code = GET_CODE (op);
11331 rtx cc_reg = XEXP (op, 0);
11332 enum machine_mode mode = GET_MODE (cc_reg);
11333 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11334 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11335 int really_reversed = reversed ^ need_longbranch;
11341 validate_condition_mode (code, mode);
11343 /* Work out which way this really branches. We could use
11344 reverse_condition_maybe_unordered here always but this
11345 makes the resulting assembler clearer. */
11346 if (really_reversed)
11348 /* Reversal of FP compares takes care -- an ordered compare
11349 becomes an unordered compare and vice versa. */
11350 if (mode == CCFPmode)
11351 code = reverse_condition_maybe_unordered (code);
11353 code = reverse_condition (code);
11356 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11358 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11363 /* Opposite of GT. */
11372 gcc_unreachable ();
11378 /* Not all of these are actually distinct opcodes, but
11379 we distinguish them for clarity of the resulting assembler. */
11380 case NE: case LTGT:
11381 ccode = "ne"; break;
11382 case EQ: case UNEQ:
11383 ccode = "eq"; break;
11385 ccode = "ge"; break;
11386 case GT: case GTU: case UNGT:
11387 ccode = "gt"; break;
11389 ccode = "le"; break;
11390 case LT: case LTU: case UNLT:
11391 ccode = "lt"; break;
11392 case UNORDERED: ccode = "un"; break;
11393 case ORDERED: ccode = "nu"; break;
11394 case UNGE: ccode = "nl"; break;
11395 case UNLE: ccode = "ng"; break;
11397 gcc_unreachable ();
11400 /* Maybe we have a guess as to how likely the branch is.
11401 The old mnemonics don't have a way to specify this information. */
11403 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11404 if (note != NULL_RTX)
11406 /* PROB is the difference from 50%. */
11407 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11409 /* Only hint for highly probable/improbable branches on newer
11410 cpus as static prediction overrides processor dynamic
11411 prediction. For older cpus we may as well always hint, but
11412 assume not taken for branches that are very close to 50% as a
11413 mispredicted taken branch is more expensive than a
11414 mispredicted not-taken branch. */
11415 if (rs6000_always_hint
11416 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11418 if (abs (prob) > REG_BR_PROB_BASE / 20
11419 && ((prob > 0) ^ need_longbranch))
11427 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11429 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11431 /* We need to escape any '%' characters in the reg_names string.
11432 Assume they'd only be the first character.... */
11433 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11435 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11439 /* If the branch distance was too far, we may have to use an
11440 unconditional branch to go the distance. */
11441 if (need_longbranch)
11442 s += sprintf (s, ",$+8\n\tb %s", label);
11444 s += sprintf (s, ",%s", label);
11450 /* Return the string to flip the GT bit on a CR. */
11452 output_e500_flip_gt_bit (rtx dst, rtx src)
11454 static char string[64];
11457 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11458 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11461 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11462 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11464 sprintf (string, "crnot %d,%d", a, b);
11468 /* Return insn index for the vector compare instruction for given CODE,
11469 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11473 get_vec_cmp_insn (enum rtx_code code,
11474 enum machine_mode dest_mode,
11475 enum machine_mode op_mode)
11477 if (!TARGET_ALTIVEC)
11478 return INSN_NOT_AVAILABLE;
11483 if (dest_mode == V16QImode && op_mode == V16QImode)
11484 return UNSPEC_VCMPEQUB;
11485 if (dest_mode == V8HImode && op_mode == V8HImode)
11486 return UNSPEC_VCMPEQUH;
11487 if (dest_mode == V4SImode && op_mode == V4SImode)
11488 return UNSPEC_VCMPEQUW;
11489 if (dest_mode == V4SImode && op_mode == V4SFmode)
11490 return UNSPEC_VCMPEQFP;
11493 if (dest_mode == V4SImode && op_mode == V4SFmode)
11494 return UNSPEC_VCMPGEFP;
11496 if (dest_mode == V16QImode && op_mode == V16QImode)
11497 return UNSPEC_VCMPGTSB;
11498 if (dest_mode == V8HImode && op_mode == V8HImode)
11499 return UNSPEC_VCMPGTSH;
11500 if (dest_mode == V4SImode && op_mode == V4SImode)
11501 return UNSPEC_VCMPGTSW;
11502 if (dest_mode == V4SImode && op_mode == V4SFmode)
11503 return UNSPEC_VCMPGTFP;
11506 if (dest_mode == V16QImode && op_mode == V16QImode)
11507 return UNSPEC_VCMPGTUB;
11508 if (dest_mode == V8HImode && op_mode == V8HImode)
11509 return UNSPEC_VCMPGTUH;
11510 if (dest_mode == V4SImode && op_mode == V4SImode)
11511 return UNSPEC_VCMPGTUW;
11516 return INSN_NOT_AVAILABLE;
11519 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11520 DMODE is expected destination mode. This is a recursive function. */
11523 rs6000_emit_vector_compare (enum rtx_code rcode,
11525 enum machine_mode dmode)
11529 enum machine_mode dest_mode;
11530 enum machine_mode op_mode = GET_MODE (op1);
11532 gcc_assert (TARGET_ALTIVEC);
11533 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11535 /* Floating point vector compare instructions uses destination V4SImode.
11536 Move destination to appropriate mode later. */
11537 if (dmode == V4SFmode)
11538 dest_mode = V4SImode;
11542 mask = gen_reg_rtx (dest_mode);
11543 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11545 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11547 bool swap_operands = false;
11548 bool try_again = false;
11553 swap_operands = true;
11558 swap_operands = true;
11562 /* Treat A != B as ~(A==B). */
11564 enum insn_code nor_code;
11565 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11568 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11569 gcc_assert (nor_code != CODE_FOR_nothing);
11570 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11572 if (dmode != dest_mode)
11574 rtx temp = gen_reg_rtx (dest_mode);
11575 convert_move (temp, mask, 0);
11585 /* Try GT/GTU/LT/LTU OR EQ */
11588 enum insn_code ior_code;
11589 enum rtx_code new_code;
11610 gcc_unreachable ();
11613 c_rtx = rs6000_emit_vector_compare (new_code,
11614 op0, op1, dest_mode);
11615 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11618 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11619 gcc_assert (ior_code != CODE_FOR_nothing);
11620 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11621 if (dmode != dest_mode)
11623 rtx temp = gen_reg_rtx (dest_mode);
11624 convert_move (temp, mask, 0);
11631 gcc_unreachable ();
11636 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11637 /* You only get two chances. */
11638 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11650 emit_insn (gen_rtx_SET (VOIDmode, mask,
11651 gen_rtx_UNSPEC (dest_mode,
11652 gen_rtvec (2, op0, op1),
11654 if (dmode != dest_mode)
11656 rtx temp = gen_reg_rtx (dest_mode);
11657 convert_move (temp, mask, 0);
11663 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11664 valid insn doesn exist for given mode. */
11667 get_vsel_insn (enum machine_mode mode)
11672 return UNSPEC_VSEL4SI;
11675 return UNSPEC_VSEL4SF;
11678 return UNSPEC_VSEL8HI;
11681 return UNSPEC_VSEL16QI;
11684 return INSN_NOT_AVAILABLE;
11687 return INSN_NOT_AVAILABLE;
11690 /* Emit vector select insn where DEST is destination using
11691 operands OP1, OP2 and MASK. */
11694 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11697 enum machine_mode dest_mode = GET_MODE (dest);
11698 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11700 temp = gen_reg_rtx (dest_mode);
11702 /* For each vector element, select op1 when mask is 1 otherwise
11704 t = gen_rtx_SET (VOIDmode, temp,
11705 gen_rtx_UNSPEC (dest_mode,
11706 gen_rtvec (3, op2, op1, mask),
11709 emit_move_insn (dest, temp);
11713 /* Emit vector conditional expression.
11714 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11715 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11718 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11719 rtx cond, rtx cc_op0, rtx cc_op1)
11721 enum machine_mode dest_mode = GET_MODE (dest);
11722 enum rtx_code rcode = GET_CODE (cond);
11725 if (!TARGET_ALTIVEC)
11728 /* Get the vector mask for the given relational operations. */
11729 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11731 rs6000_emit_vector_select (dest, op1, op2, mask);
11736 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11737 operands of the last comparison is nonzero/true, FALSE_COND if it
11738 is zero/false. Return 0 if the hardware has no such operation. */
11741 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11743 enum rtx_code code = GET_CODE (op);
11744 rtx op0 = rs6000_compare_op0;
11745 rtx op1 = rs6000_compare_op1;
11746 REAL_VALUE_TYPE c1;
11747 enum machine_mode compare_mode = GET_MODE (op0);
11748 enum machine_mode result_mode = GET_MODE (dest);
11750 bool is_against_zero;
11752 /* These modes should always match. */
11753 if (GET_MODE (op1) != compare_mode
11754 /* In the isel case however, we can use a compare immediate, so
11755 op1 may be a small constant. */
11756 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11758 if (GET_MODE (true_cond) != result_mode)
11760 if (GET_MODE (false_cond) != result_mode)
11763 /* First, work out if the hardware can do this at all, or
11764 if it's too slow.... */
11765 if (! rs6000_compare_fp_p)
11768 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11771 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11772 && SCALAR_FLOAT_MODE_P (compare_mode))
11775 is_against_zero = op1 == CONST0_RTX (compare_mode);
11777 /* A floating-point subtract might overflow, underflow, or produce
11778 an inexact result, thus changing the floating-point flags, so it
11779 can't be generated if we care about that. It's safe if one side
11780 of the construct is zero, since then no subtract will be
11782 if (SCALAR_FLOAT_MODE_P (compare_mode)
11783 && flag_trapping_math && ! is_against_zero)
11786 /* Eliminate half of the comparisons by switching operands, this
11787 makes the remaining code simpler. */
11788 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11789 || code == LTGT || code == LT || code == UNLE)
11791 code = reverse_condition_maybe_unordered (code);
11793 true_cond = false_cond;
11797 /* UNEQ and LTGT take four instructions for a comparison with zero,
11798 it'll probably be faster to use a branch here too. */
11799 if (code == UNEQ && HONOR_NANS (compare_mode))
11802 if (GET_CODE (op1) == CONST_DOUBLE)
11803 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11805 /* We're going to try to implement comparisons by performing
11806 a subtract, then comparing against zero. Unfortunately,
11807 Inf - Inf is NaN which is not zero, and so if we don't
11808 know that the operand is finite and the comparison
11809 would treat EQ different to UNORDERED, we can't do it. */
11810 if (HONOR_INFINITIES (compare_mode)
11811 && code != GT && code != UNGE
11812 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11813 /* Constructs of the form (a OP b ? a : b) are safe. */
11814 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11815 || (! rtx_equal_p (op0, true_cond)
11816 && ! rtx_equal_p (op1, true_cond))))
11819 /* At this point we know we can use fsel. */
11821 /* Reduce the comparison to a comparison against zero. */
11822 if (! is_against_zero)
11824 temp = gen_reg_rtx (compare_mode);
11825 emit_insn (gen_rtx_SET (VOIDmode, temp,
11826 gen_rtx_MINUS (compare_mode, op0, op1)));
11828 op1 = CONST0_RTX (compare_mode);
11831 /* If we don't care about NaNs we can reduce some of the comparisons
11832 down to faster ones. */
11833 if (! HONOR_NANS (compare_mode))
11839 true_cond = false_cond;
11852 /* Now, reduce everything down to a GE. */
11859 temp = gen_reg_rtx (compare_mode);
11860 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11865 temp = gen_reg_rtx (compare_mode);
11866 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11871 temp = gen_reg_rtx (compare_mode);
11872 emit_insn (gen_rtx_SET (VOIDmode, temp,
11873 gen_rtx_NEG (compare_mode,
11874 gen_rtx_ABS (compare_mode, op0))));
11879 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11880 temp = gen_reg_rtx (result_mode);
11881 emit_insn (gen_rtx_SET (VOIDmode, temp,
11882 gen_rtx_IF_THEN_ELSE (result_mode,
11883 gen_rtx_GE (VOIDmode,
11885 true_cond, false_cond)));
11886 false_cond = true_cond;
11889 temp = gen_reg_rtx (compare_mode);
11890 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11895 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11896 temp = gen_reg_rtx (result_mode);
11897 emit_insn (gen_rtx_SET (VOIDmode, temp,
11898 gen_rtx_IF_THEN_ELSE (result_mode,
11899 gen_rtx_GE (VOIDmode,
11901 true_cond, false_cond)));
11902 true_cond = false_cond;
11905 temp = gen_reg_rtx (compare_mode);
11906 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11911 gcc_unreachable ();
11914 emit_insn (gen_rtx_SET (VOIDmode, dest,
11915 gen_rtx_IF_THEN_ELSE (result_mode,
11916 gen_rtx_GE (VOIDmode,
11918 true_cond, false_cond)));
11922 /* Same as above, but for ints (isel). */
11925 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11927 rtx condition_rtx, cr;
11929 /* All isel implementations thus far are 32-bits. */
11930 if (GET_MODE (rs6000_compare_op0) != SImode)
11933 /* We still have to do the compare, because isel doesn't do a
11934 compare, it just looks at the CRx bits set by a previous compare
11936 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11937 cr = XEXP (condition_rtx, 0);
11939 if (GET_MODE (cr) == CCmode)
11940 emit_insn (gen_isel_signed (dest, condition_rtx,
11941 true_cond, false_cond, cr));
11943 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11944 true_cond, false_cond, cr));
11950 output_isel (rtx *operands)
11952 enum rtx_code code;
11954 code = GET_CODE (operands[1]);
11955 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11957 PUT_CODE (operands[1], reverse_condition (code));
11958 return "isel %0,%3,%2,%j1";
11961 return "isel %0,%2,%3,%j1";
11965 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11967 enum machine_mode mode = GET_MODE (op0);
11971 if (code == SMAX || code == SMIN)
11976 if (code == SMAX || code == UMAX)
11977 target = emit_conditional_move (dest, c, op0, op1, mode,
11978 op0, op1, mode, 0);
11980 target = emit_conditional_move (dest, c, op0, op1, mode,
11981 op1, op0, mode, 0);
11982 gcc_assert (target);
11983 if (target != dest)
11984 emit_move_insn (dest, target);
11987 /* Emit instructions to perform a load-reserved/store-conditional operation.
11988 The operation performed is an atomic
11989 (set M (CODE:MODE M OP))
11990 If not NULL, BEFORE is atomically set to M before the operation, and
11991 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11992 If SYNC_P then a memory barrier is emitted before the operation.
11993 Either OP or M may be wrapped in a NOT operation. */
11996 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11997 rtx m, rtx op, rtx before_param, rtx after_param,
12000 enum machine_mode used_mode;
12001 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12004 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12005 rtx shift = NULL_RTX;
12008 emit_insn (gen_memory_barrier ());
12010 if (GET_CODE (m) == NOT)
12011 used_m = XEXP (m, 0);
12015 /* If this is smaller than SImode, we'll have to use SImode with
12017 if (mode == QImode || mode == HImode)
12021 if (MEM_ALIGN (used_m) >= 32)
12024 if (BYTES_BIG_ENDIAN)
12025 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12027 shift = GEN_INT (ishift);
12031 rtx addrSI, aligned_addr;
12032 int shift_mask = mode == QImode ? 0x18 : 0x10;
12034 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12035 XEXP (used_m, 0)));
12036 shift = gen_reg_rtx (SImode);
12038 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12039 GEN_INT (shift_mask)));
12040 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12042 aligned_addr = expand_binop (Pmode, and_optab,
12044 GEN_INT (-4), NULL_RTX,
12045 1, OPTAB_LIB_WIDEN);
12046 used_m = change_address (used_m, SImode, aligned_addr);
12047 set_mem_align (used_m, 32);
12048 /* It's safe to keep the old alias set of USED_M, because
12049 the operation is atomic and only affects the original
12051 if (GET_CODE (m) == NOT)
12052 m = gen_rtx_NOT (SImode, used_m);
12057 if (GET_CODE (op) == NOT)
12059 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12060 oldop = gen_rtx_NOT (SImode, oldop);
12063 oldop = lowpart_subreg (SImode, op, mode);
12069 newop = expand_binop (SImode, and_optab,
12070 oldop, GEN_INT (imask), NULL_RTX,
12071 1, OPTAB_LIB_WIDEN);
12072 emit_insn (gen_ashlsi3 (newop, newop, shift));
12076 newop = expand_binop (SImode, ior_optab,
12077 oldop, GEN_INT (~imask), NULL_RTX,
12078 1, OPTAB_LIB_WIDEN);
12079 emit_insn (gen_rotlsi3 (newop, newop, shift));
12087 newop = expand_binop (SImode, and_optab,
12088 oldop, GEN_INT (imask), NULL_RTX,
12089 1, OPTAB_LIB_WIDEN);
12090 emit_insn (gen_ashlsi3 (newop, newop, shift));
12092 mask = gen_reg_rtx (SImode);
12093 emit_move_insn (mask, GEN_INT (imask));
12094 emit_insn (gen_ashlsi3 (mask, mask, shift));
12097 newop = gen_rtx_PLUS (SImode, m, newop);
12099 newop = gen_rtx_MINUS (SImode, m, newop);
12100 newop = gen_rtx_AND (SImode, newop, mask);
12101 newop = gen_rtx_IOR (SImode, newop,
12102 gen_rtx_AND (SImode,
12103 gen_rtx_NOT (SImode, mask),
12109 gcc_unreachable ();
12112 if (GET_CODE (m) == NOT)
12116 mask = gen_reg_rtx (SImode);
12117 emit_move_insn (mask, GEN_INT (imask));
12118 emit_insn (gen_ashlsi3 (mask, mask, shift));
12120 xorm = gen_rtx_XOR (SImode, used_m, mask);
12121 /* Depending on the value of 'op', the XOR or the operation might
12122 be able to be simplified away. */
12123 newop = simplify_gen_binary (code, SImode, xorm, newop);
12126 used_mode = SImode;
12127 before = gen_reg_rtx (used_mode);
12128 after = gen_reg_rtx (used_mode);
12133 before = before_param;
12134 after = after_param;
12136 if (before == NULL_RTX)
12137 before = gen_reg_rtx (used_mode);
12138 if (after == NULL_RTX)
12139 after = gen_reg_rtx (used_mode);
12142 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12143 && used_mode != mode)
12144 the_op = op; /* Computed above. */
12145 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12146 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12148 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12150 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12151 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12152 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12153 gen_rtx_UNSPEC (used_mode,
12154 gen_rtvec (1, the_op),
12156 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12158 if ((code == PLUS || code == MINUS) && used_mode != mode)
12159 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12160 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12162 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12163 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12165 /* Shift and mask the return values properly. */
12166 if (used_mode != mode && before_param)
12168 emit_insn (gen_lshrsi3 (before, before, shift));
12169 convert_move (before_param, before, 1);
12172 if (used_mode != mode && after_param)
12174 emit_insn (gen_lshrsi3 (after, after, shift));
12175 convert_move (after_param, after, 1);
12178 /* The previous sequence will end with a branch that's dependent on
12179 the conditional store, so placing an isync will ensure that no
12180 other instructions (especially, no load or store instructions)
12181 can start before the atomic operation completes. */
12183 emit_insn (gen_isync ());
12186 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12187 COND is true. Mark the jump as unlikely to be taken. */
12190 emit_unlikely_jump (rtx cond, rtx label)
12192 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12195 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12196 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12197 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12200 /* A subroutine of the atomic operation splitters. Emit a load-locked
12201 instruction in MODE. */
12204 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12206 rtx (*fn) (rtx, rtx) = NULL;
12207 if (mode == SImode)
12208 fn = gen_load_locked_si;
12209 else if (mode == DImode)
12210 fn = gen_load_locked_di;
12211 emit_insn (fn (reg, mem));
12214 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12215 instruction in MODE. */
12218 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12220 rtx (*fn) (rtx, rtx, rtx) = NULL;
12221 if (mode == SImode)
12222 fn = gen_store_conditional_si;
12223 else if (mode == DImode)
12224 fn = gen_store_conditional_di;
12226 /* Emit sync before stwcx. to address PPC405 Erratum. */
12227 if (PPC405_ERRATUM77)
12228 emit_insn (gen_memory_barrier ());
12230 emit_insn (fn (res, mem, val));
12233 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12234 to perform. MEM is the memory on which to operate. VAL is the second
12235 operand of the binary operator. BEFORE and AFTER are optional locations to
12236 return the value of MEM either before of after the operation. SCRATCH is
12237 a scratch register. */
12240 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12241 rtx before, rtx after, rtx scratch)
12243 enum machine_mode mode = GET_MODE (mem);
12244 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12246 emit_insn (gen_memory_barrier ());
12248 label = gen_label_rtx ();
12249 emit_label (label);
12250 label = gen_rtx_LABEL_REF (VOIDmode, label);
12252 if (before == NULL_RTX)
12254 emit_load_locked (mode, before, mem);
12257 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12258 else if (code == AND)
12259 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12261 x = gen_rtx_fmt_ee (code, mode, before, val);
12263 if (after != NULL_RTX)
12264 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12265 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12267 emit_store_conditional (mode, cond, mem, scratch);
12269 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12270 emit_unlikely_jump (x, label);
12272 emit_insn (gen_isync ());
12275 /* Expand an atomic compare and swap operation. MEM is the memory on which
12276 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12277 value to be stored. SCRATCH is a scratch GPR. */
12280 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12283 enum machine_mode mode = GET_MODE (mem);
12284 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12286 emit_insn (gen_memory_barrier ());
12288 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12289 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12290 emit_label (XEXP (label1, 0));
12292 emit_load_locked (mode, retval, mem);
12294 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12295 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12297 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12298 emit_unlikely_jump (x, label2);
12300 emit_move_insn (scratch, newval);
12301 emit_store_conditional (mode, cond, mem, scratch);
12303 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12304 emit_unlikely_jump (x, label1);
12306 emit_insn (gen_isync ());
12307 emit_label (XEXP (label2, 0));
12310 /* Expand an atomic test and set operation. MEM is the memory on which
12311 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12314 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12316 enum machine_mode mode = GET_MODE (mem);
12317 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12319 emit_insn (gen_memory_barrier ());
12321 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12322 emit_label (XEXP (label, 0));
12324 emit_load_locked (mode, retval, mem);
12325 emit_move_insn (scratch, val);
12326 emit_store_conditional (mode, cond, mem, scratch);
12328 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12329 emit_unlikely_jump (x, label);
12331 emit_insn (gen_isync ());
12335 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12337 enum machine_mode mode = GET_MODE (mem);
12338 rtx addrSI, align, wdst, shift, mask;
12339 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12340 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12342 /* Shift amount for subword relative to aligned word. */
12343 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12344 shift = gen_reg_rtx (SImode);
12345 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12346 GEN_INT (shift_mask)));
12347 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12349 /* Shift and mask old value into position within word. */
12350 oldval = convert_modes (SImode, mode, oldval, 1);
12351 oldval = expand_binop (SImode, and_optab,
12352 oldval, GEN_INT (imask), NULL_RTX,
12353 1, OPTAB_LIB_WIDEN);
12354 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12356 /* Shift and mask new value into position within word. */
12357 newval = convert_modes (SImode, mode, newval, 1);
12358 newval = expand_binop (SImode, and_optab,
12359 newval, GEN_INT (imask), NULL_RTX,
12360 1, OPTAB_LIB_WIDEN);
12361 emit_insn (gen_ashlsi3 (newval, newval, shift));
12363 /* Mask for insertion. */
12364 mask = gen_reg_rtx (SImode);
12365 emit_move_insn (mask, GEN_INT (imask));
12366 emit_insn (gen_ashlsi3 (mask, mask, shift));
12368 /* Address of aligned word containing subword. */
12369 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12370 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12371 mem = change_address (mem, SImode, align);
12372 set_mem_align (mem, 32);
12373 MEM_VOLATILE_P (mem) = 1;
12375 wdst = gen_reg_rtx (SImode);
12376 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12377 oldval, newval, mem));
12379 emit_move_insn (dst, gen_lowpart (mode, wdst));
12383 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12384 rtx oldval, rtx newval, rtx mem,
12387 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12389 emit_insn (gen_memory_barrier ());
12390 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12391 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12392 emit_label (XEXP (label1, 0));
12394 emit_load_locked (SImode, scratch, mem);
12396 /* Mask subword within loaded value for comparison with oldval.
12397 Use UNSPEC_AND to avoid clobber.*/
12398 emit_insn (gen_rtx_SET (SImode, dest,
12399 gen_rtx_UNSPEC (SImode,
12400 gen_rtvec (2, scratch, mask),
12403 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12404 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12406 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12407 emit_unlikely_jump (x, label2);
12409 /* Clear subword within loaded value for insertion of new value. */
12410 emit_insn (gen_rtx_SET (SImode, scratch,
12411 gen_rtx_AND (SImode,
12412 gen_rtx_NOT (SImode, mask), scratch)));
12413 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12414 emit_store_conditional (SImode, cond, mem, scratch);
12416 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12417 emit_unlikely_jump (x, label1);
12419 emit_insn (gen_isync ());
12420 emit_label (XEXP (label2, 0));
12424 /* Emit instructions to move SRC to DST. Called by splitters for
12425 multi-register moves. It will emit at most one instruction for
12426 each register that is accessed; that is, it won't emit li/lis pairs
12427 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12431 rs6000_split_multireg_move (rtx dst, rtx src)
12433 /* The register number of the first register being moved. */
12435 /* The mode that is to be moved. */
12436 enum machine_mode mode;
12437 /* The mode that the move is being done in, and its size. */
12438 enum machine_mode reg_mode;
12440 /* The number of registers that will be moved. */
12443 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12444 mode = GET_MODE (dst);
12445 nregs = hard_regno_nregs[reg][mode];
12446 if (FP_REGNO_P (reg))
12448 else if (ALTIVEC_REGNO_P (reg))
12449 reg_mode = V16QImode;
12451 reg_mode = word_mode;
12452 reg_mode_size = GET_MODE_SIZE (reg_mode);
12454 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12456 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12458 /* Move register range backwards, if we might have destructive
12461 for (i = nregs - 1; i >= 0; i--)
12462 emit_insn (gen_rtx_SET (VOIDmode,
12463 simplify_gen_subreg (reg_mode, dst, mode,
12464 i * reg_mode_size),
12465 simplify_gen_subreg (reg_mode, src, mode,
12466 i * reg_mode_size)));
12472 bool used_update = false;
12474 if (MEM_P (src) && INT_REGNO_P (reg))
12478 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12479 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12482 breg = XEXP (XEXP (src, 0), 0);
12483 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12484 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12485 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12486 emit_insn (TARGET_32BIT
12487 ? gen_addsi3 (breg, breg, delta_rtx)
12488 : gen_adddi3 (breg, breg, delta_rtx));
12489 src = replace_equiv_address (src, breg);
12491 else if (! offsettable_memref_p (src))
12494 basereg = gen_rtx_REG (Pmode, reg);
12495 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12496 src = replace_equiv_address (src, basereg);
12499 breg = XEXP (src, 0);
12500 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12501 breg = XEXP (breg, 0);
12503 /* If the base register we are using to address memory is
12504 also a destination reg, then change that register last. */
12506 && REGNO (breg) >= REGNO (dst)
12507 && REGNO (breg) < REGNO (dst) + nregs)
12508 j = REGNO (breg) - REGNO (dst);
12511 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12515 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12516 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12519 breg = XEXP (XEXP (dst, 0), 0);
12520 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12521 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12522 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12524 /* We have to update the breg before doing the store.
12525 Use store with update, if available. */
12529 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12530 emit_insn (TARGET_32BIT
12531 ? (TARGET_POWERPC64
12532 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12533 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12534 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12535 used_update = true;
12538 emit_insn (TARGET_32BIT
12539 ? gen_addsi3 (breg, breg, delta_rtx)
12540 : gen_adddi3 (breg, breg, delta_rtx));
12541 dst = replace_equiv_address (dst, breg);
12544 gcc_assert (offsettable_memref_p (dst));
12547 for (i = 0; i < nregs; i++)
12549 /* Calculate index to next subword. */
12554 /* If compiler already emitted move of first word by
12555 store with update, no need to do anything. */
12556 if (j == 0 && used_update)
12559 emit_insn (gen_rtx_SET (VOIDmode,
12560 simplify_gen_subreg (reg_mode, dst, mode,
12561 j * reg_mode_size),
12562 simplify_gen_subreg (reg_mode, src, mode,
12563 j * reg_mode_size)));
12569 /* This page contains routines that are used to determine what the
12570 function prologue and epilogue code will do and write them out. */
12572 /* Return the first fixed-point register that is required to be
12573 saved. 32 if none. */
12576 first_reg_to_save (void)
12580 /* Find lowest numbered live register. */
12581 for (first_reg = 13; first_reg <= 31; first_reg++)
12582 if (regs_ever_live[first_reg]
12583 && (! call_used_regs[first_reg]
12584 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12585 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12586 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12587 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12592 && current_function_uses_pic_offset_table
12593 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12594 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12600 /* Similar, for FP regs. */
12603 first_fp_reg_to_save (void)
12607 /* Find lowest numbered live register. */
12608 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12609 if (regs_ever_live[first_reg])
12615 /* Similar, for AltiVec regs. */
12618 first_altivec_reg_to_save (void)
12622 /* Stack frame remains as is unless we are in AltiVec ABI. */
12623 if (! TARGET_ALTIVEC_ABI)
12624 return LAST_ALTIVEC_REGNO + 1;
12626 /* Find lowest numbered live register. */
12627 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12628 if (regs_ever_live[i])
12634 /* Return a 32-bit mask of the AltiVec registers we need to set in
12635 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12636 the 32-bit word is 0. */
12638 static unsigned int
12639 compute_vrsave_mask (void)
12641 unsigned int i, mask = 0;
12643 /* First, find out if we use _any_ altivec registers. */
12644 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12645 if (regs_ever_live[i])
12646 mask |= ALTIVEC_REG_BIT (i);
12651 /* Next, remove the argument registers from the set. These must
12652 be in the VRSAVE mask set by the caller, so we don't need to add
12653 them in again. More importantly, the mask we compute here is
12654 used to generate CLOBBERs in the set_vrsave insn, and we do not
12655 wish the argument registers to die. */
12656 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12657 mask &= ~ALTIVEC_REG_BIT (i);
12659 /* Similarly, remove the return value from the set. */
12662 diddle_return_value (is_altivec_return_reg, &yes);
12664 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12670 /* For a very restricted set of circumstances, we can cut down the
12671 size of prologues/epilogues by calling our own save/restore-the-world
12675 compute_save_world_info (rs6000_stack_t *info_ptr)
12677 info_ptr->world_save_p = 1;
12678 info_ptr->world_save_p
12679 = (WORLD_SAVE_P (info_ptr)
12680 && DEFAULT_ABI == ABI_DARWIN
12681 && ! (current_function_calls_setjmp && flag_exceptions)
12682 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12683 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12684 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12685 && info_ptr->cr_save_p);
12687 /* This will not work in conjunction with sibcalls. Make sure there
12688 are none. (This check is expensive, but seldom executed.) */
12689 if (WORLD_SAVE_P (info_ptr))
12692 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12693 if ( GET_CODE (insn) == CALL_INSN
12694 && SIBLING_CALL_P (insn))
12696 info_ptr->world_save_p = 0;
12701 if (WORLD_SAVE_P (info_ptr))
12703 /* Even if we're not touching VRsave, make sure there's room on the
12704 stack for it, if it looks like we're calling SAVE_WORLD, which
12705 will attempt to save it. */
12706 info_ptr->vrsave_size = 4;
12708 /* "Save" the VRsave register too if we're saving the world. */
12709 if (info_ptr->vrsave_mask == 0)
12710 info_ptr->vrsave_mask = compute_vrsave_mask ();
12712 /* Because the Darwin register save/restore routines only handle
12713 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12715 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12716 && (info_ptr->first_altivec_reg_save
12717 >= FIRST_SAVED_ALTIVEC_REGNO));
12724 is_altivec_return_reg (rtx reg, void *xyes)
12726 bool *yes = (bool *) xyes;
12727 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12732 /* Calculate the stack information for the current function. This is
12733 complicated by having two separate calling sequences, the AIX calling
12734 sequence and the V.4 calling sequence.
12736 AIX (and Darwin/Mac OS X) stack frames look like:
12738 SP----> +---------------------------------------+
12739 | back chain to caller | 0 0
12740 +---------------------------------------+
12741 | saved CR | 4 8 (8-11)
12742 +---------------------------------------+
12744 +---------------------------------------+
12745 | reserved for compilers | 12 24
12746 +---------------------------------------+
12747 | reserved for binders | 16 32
12748 +---------------------------------------+
12749 | saved TOC pointer | 20 40
12750 +---------------------------------------+
12751 | Parameter save area (P) | 24 48
12752 +---------------------------------------+
12753 | Alloca space (A) | 24+P etc.
12754 +---------------------------------------+
12755 | Local variable space (L) | 24+P+A
12756 +---------------------------------------+
12757 | Float/int conversion temporary (X) | 24+P+A+L
12758 +---------------------------------------+
12759 | Save area for AltiVec registers (W) | 24+P+A+L+X
12760 +---------------------------------------+
12761 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12762 +---------------------------------------+
12763 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12764 +---------------------------------------+
12765 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12766 +---------------------------------------+
12767 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12768 +---------------------------------------+
12769 old SP->| back chain to caller's caller |
12770 +---------------------------------------+
12772 The required alignment for AIX configurations is two words (i.e., 8
12776 V.4 stack frames look like:
12778 SP----> +---------------------------------------+
12779 | back chain to caller | 0
12780 +---------------------------------------+
12781 | caller's saved LR | 4
12782 +---------------------------------------+
12783 | Parameter save area (P) | 8
12784 +---------------------------------------+
12785 | Alloca space (A) | 8+P
12786 +---------------------------------------+
12787 | Varargs save area (V) | 8+P+A
12788 +---------------------------------------+
12789 | Local variable space (L) | 8+P+A+V
12790 +---------------------------------------+
12791 | Float/int conversion temporary (X) | 8+P+A+V+L
12792 +---------------------------------------+
12793 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12794 +---------------------------------------+
12795 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12796 +---------------------------------------+
12797 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12798 +---------------------------------------+
12799 | SPE: area for 64-bit GP registers |
12800 +---------------------------------------+
12801 | SPE alignment padding |
12802 +---------------------------------------+
12803 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12804 +---------------------------------------+
12805 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12806 +---------------------------------------+
12807 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12808 +---------------------------------------+
12809 old SP->| back chain to caller's caller |
12810 +---------------------------------------+
12812 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12813 given. (But note below and in sysv4.h that we require only 8 and
12814 may round up the size of our stack frame anyways. The historical
12815 reason is early versions of powerpc-linux which didn't properly
12816 align the stack at program startup. A happy side-effect is that
12817 -mno-eabi libraries can be used with -meabi programs.)
12819 The EABI configuration defaults to the V.4 layout. However,
12820 the stack alignment requirements may differ. If -mno-eabi is not
12821 given, the required stack alignment is 8 bytes; if -mno-eabi is
12822 given, the required alignment is 16 bytes. (But see V.4 comment
12825 #ifndef ABI_STACK_BOUNDARY
12826 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12829 static rs6000_stack_t *
12830 rs6000_stack_info (void)
12832 static rs6000_stack_t info;
12833 rs6000_stack_t *info_ptr = &info;
12834 int reg_size = TARGET_32BIT ? 4 : 8;
12837 HOST_WIDE_INT non_fixed_size;
12839 memset (&info, 0, sizeof (info));
12843 /* Cache value so we don't rescan instruction chain over and over. */
12844 if (cfun->machine->insn_chain_scanned_p == 0)
12845 cfun->machine->insn_chain_scanned_p
12846 = spe_func_has_64bit_regs_p () + 1;
12847 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12850 /* Select which calling sequence. */
12851 info_ptr->abi = DEFAULT_ABI;
12853 /* Calculate which registers need to be saved & save area size. */
12854 info_ptr->first_gp_reg_save = first_reg_to_save ();
12855 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12856 even if it currently looks like we won't. */
12857 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12858 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12859 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12860 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12861 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12863 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12865 /* For the SPE, we have an additional upper 32-bits on each GPR.
12866 Ideally we should save the entire 64-bits only when the upper
12867 half is used in SIMD instructions. Since we only record
12868 registers live (not the size they are used in), this proves
12869 difficult because we'd have to traverse the instruction chain at
12870 the right time, taking reload into account. This is a real pain,
12871 so we opt to save the GPRs in 64-bits always if but one register
12872 gets used in 64-bits. Otherwise, all the registers in the frame
12873 get saved in 32-bits.
12875 So... since when we save all GPRs (except the SP) in 64-bits, the
12876 traditional GP save area will be empty. */
12877 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12878 info_ptr->gp_size = 0;
12880 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12881 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12883 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12884 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12885 - info_ptr->first_altivec_reg_save);
12887 /* Does this function call anything? */
12888 info_ptr->calls_p = (! current_function_is_leaf
12889 || cfun->machine->ra_needs_full_frame);
12891 /* Determine if we need to save the link register. */
12892 if ((DEFAULT_ABI == ABI_AIX
12893 && current_function_profile
12894 && !TARGET_PROFILE_KERNEL)
12895 #ifdef TARGET_RELOCATABLE
12896 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12898 || (info_ptr->first_fp_reg_save != 64
12899 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12900 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12901 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12902 || info_ptr->calls_p
12903 || rs6000_ra_ever_killed ())
12905 info_ptr->lr_save_p = 1;
12906 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12909 /* Determine if we need to save the condition code registers. */
12910 if (regs_ever_live[CR2_REGNO]
12911 || regs_ever_live[CR3_REGNO]
12912 || regs_ever_live[CR4_REGNO])
12914 info_ptr->cr_save_p = 1;
12915 if (DEFAULT_ABI == ABI_V4)
12916 info_ptr->cr_size = reg_size;
12919 /* If the current function calls __builtin_eh_return, then we need
12920 to allocate stack space for registers that will hold data for
12921 the exception handler. */
12922 if (current_function_calls_eh_return)
12925 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12928 /* SPE saves EH registers in 64-bits. */
12929 ehrd_size = i * (TARGET_SPE_ABI
12930 && info_ptr->spe_64bit_regs_used != 0
12931 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12936 /* Determine various sizes. */
12937 info_ptr->reg_size = reg_size;
12938 info_ptr->fixed_size = RS6000_SAVE_AREA;
12939 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12940 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12941 TARGET_ALTIVEC ? 16 : 8);
12942 if (FRAME_GROWS_DOWNWARD)
12943 info_ptr->vars_size
12944 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12945 + info_ptr->parm_size,
12946 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12947 - (info_ptr->fixed_size + info_ptr->vars_size
12948 + info_ptr->parm_size);
12950 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12951 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12953 info_ptr->spe_gp_size = 0;
12955 if (TARGET_ALTIVEC_ABI)
12956 info_ptr->vrsave_mask = compute_vrsave_mask ();
12958 info_ptr->vrsave_mask = 0;
12960 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12961 info_ptr->vrsave_size = 4;
12963 info_ptr->vrsave_size = 0;
12965 compute_save_world_info (info_ptr);
12967 /* Calculate the offsets. */
12968 switch (DEFAULT_ABI)
12972 gcc_unreachable ();
12976 info_ptr->fp_save_offset = - info_ptr->fp_size;
12977 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12979 if (TARGET_ALTIVEC_ABI)
12981 info_ptr->vrsave_save_offset
12982 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12984 /* Align stack so vector save area is on a quadword boundary. */
12985 if (info_ptr->altivec_size != 0)
12986 info_ptr->altivec_padding_size
12987 = 16 - (-info_ptr->vrsave_save_offset % 16);
12989 info_ptr->altivec_padding_size = 0;
12991 info_ptr->altivec_save_offset
12992 = info_ptr->vrsave_save_offset
12993 - info_ptr->altivec_padding_size
12994 - info_ptr->altivec_size;
12996 /* Adjust for AltiVec case. */
12997 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13000 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13001 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13002 info_ptr->lr_save_offset = 2*reg_size;
13006 info_ptr->fp_save_offset = - info_ptr->fp_size;
13007 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13008 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13010 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13012 /* Align stack so SPE GPR save area is aligned on a
13013 double-word boundary. */
13014 if (info_ptr->spe_gp_size != 0)
13015 info_ptr->spe_padding_size
13016 = 8 - (-info_ptr->cr_save_offset % 8);
13018 info_ptr->spe_padding_size = 0;
13020 info_ptr->spe_gp_save_offset
13021 = info_ptr->cr_save_offset
13022 - info_ptr->spe_padding_size
13023 - info_ptr->spe_gp_size;
13025 /* Adjust for SPE case. */
13026 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13028 else if (TARGET_ALTIVEC_ABI)
13030 info_ptr->vrsave_save_offset
13031 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13033 /* Align stack so vector save area is on a quadword boundary. */
13034 if (info_ptr->altivec_size != 0)
13035 info_ptr->altivec_padding_size
13036 = 16 - (-info_ptr->vrsave_save_offset % 16);
13038 info_ptr->altivec_padding_size = 0;
13040 info_ptr->altivec_save_offset
13041 = info_ptr->vrsave_save_offset
13042 - info_ptr->altivec_padding_size
13043 - info_ptr->altivec_size;
13045 /* Adjust for AltiVec case. */
13046 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13049 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13050 info_ptr->ehrd_offset -= ehrd_size;
13051 info_ptr->lr_save_offset = reg_size;
13055 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13056 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13057 + info_ptr->gp_size
13058 + info_ptr->altivec_size
13059 + info_ptr->altivec_padding_size
13060 + info_ptr->spe_gp_size
13061 + info_ptr->spe_padding_size
13063 + info_ptr->cr_size
13064 + info_ptr->vrsave_size,
13067 non_fixed_size = (info_ptr->vars_size
13068 + info_ptr->parm_size
13069 + info_ptr->save_size);
13071 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13072 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13074 /* Determine if we need to allocate any stack frame:
13076 For AIX we need to push the stack if a frame pointer is needed
13077 (because the stack might be dynamically adjusted), if we are
13078 debugging, if we make calls, or if the sum of fp_save, gp_save,
13079 and local variables are more than the space needed to save all
13080 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13081 + 18*8 = 288 (GPR13 reserved).
13083 For V.4 we don't have the stack cushion that AIX uses, but assume
13084 that the debugger can handle stackless frames. */
13086 if (info_ptr->calls_p)
13087 info_ptr->push_p = 1;
13089 else if (DEFAULT_ABI == ABI_V4)
13090 info_ptr->push_p = non_fixed_size != 0;
13092 else if (frame_pointer_needed)
13093 info_ptr->push_p = 1;
13095 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13096 info_ptr->push_p = 1;
13099 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13101 /* Zero offsets if we're not saving those registers. */
13102 if (info_ptr->fp_size == 0)
13103 info_ptr->fp_save_offset = 0;
13105 if (info_ptr->gp_size == 0)
13106 info_ptr->gp_save_offset = 0;
13108 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13109 info_ptr->altivec_save_offset = 0;
13111 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13112 info_ptr->vrsave_save_offset = 0;
13114 if (! TARGET_SPE_ABI
13115 || info_ptr->spe_64bit_regs_used == 0
13116 || info_ptr->spe_gp_size == 0)
13117 info_ptr->spe_gp_save_offset = 0;
13119 if (! info_ptr->lr_save_p)
13120 info_ptr->lr_save_offset = 0;
13122 if (! info_ptr->cr_save_p)
13123 info_ptr->cr_save_offset = 0;
13128 /* Return true if the current function uses any GPRs in 64-bit SIMD
13132 spe_func_has_64bit_regs_p (void)
13136 /* Functions that save and restore all the call-saved registers will
13137 need to save/restore the registers in 64-bits. */
13138 if (current_function_calls_eh_return
13139 || current_function_calls_setjmp
13140 || current_function_has_nonlocal_goto)
13143 insns = get_insns ();
13145 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13151 /* FIXME: This should be implemented with attributes...
13153 (set_attr "spe64" "true")....then,
13154 if (get_spe64(insn)) return true;
13156 It's the only reliable way to do the stuff below. */
13158 i = PATTERN (insn);
13159 if (GET_CODE (i) == SET)
13161 enum machine_mode mode = GET_MODE (SET_SRC (i));
13163 if (SPE_VECTOR_MODE (mode))
13165 if (TARGET_E500_DOUBLE && mode == DFmode)
13175 debug_stack_info (rs6000_stack_t *info)
13177 const char *abi_string;
13180 info = rs6000_stack_info ();
13182 fprintf (stderr, "\nStack information for function %s:\n",
13183 ((current_function_decl && DECL_NAME (current_function_decl))
13184 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13189 default: abi_string = "Unknown"; break;
13190 case ABI_NONE: abi_string = "NONE"; break;
13191 case ABI_AIX: abi_string = "AIX"; break;
13192 case ABI_DARWIN: abi_string = "Darwin"; break;
13193 case ABI_V4: abi_string = "V.4"; break;
13196 fprintf (stderr, "\tABI = %5s\n", abi_string);
13198 if (TARGET_ALTIVEC_ABI)
13199 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13201 if (TARGET_SPE_ABI)
13202 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13204 if (info->first_gp_reg_save != 32)
13205 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13207 if (info->first_fp_reg_save != 64)
13208 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13210 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13211 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13212 info->first_altivec_reg_save);
13214 if (info->lr_save_p)
13215 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13217 if (info->cr_save_p)
13218 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13220 if (info->vrsave_mask)
13221 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13224 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13227 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13229 if (info->gp_save_offset)
13230 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13232 if (info->fp_save_offset)
13233 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13235 if (info->altivec_save_offset)
13236 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13237 info->altivec_save_offset);
13239 if (info->spe_gp_save_offset)
13240 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13241 info->spe_gp_save_offset);
13243 if (info->vrsave_save_offset)
13244 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13245 info->vrsave_save_offset);
13247 if (info->lr_save_offset)
13248 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13250 if (info->cr_save_offset)
13251 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13253 if (info->varargs_save_offset)
13254 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13256 if (info->total_size)
13257 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13260 if (info->vars_size)
13261 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13264 if (info->parm_size)
13265 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13267 if (info->fixed_size)
13268 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13271 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13273 if (info->spe_gp_size)
13274 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13277 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13279 if (info->altivec_size)
13280 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13282 if (info->vrsave_size)
13283 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13285 if (info->altivec_padding_size)
13286 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13287 info->altivec_padding_size);
13289 if (info->spe_padding_size)
13290 fprintf (stderr, "\tspe_padding_size = %5d\n",
13291 info->spe_padding_size);
13294 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13296 if (info->save_size)
13297 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13299 if (info->reg_size != 4)
13300 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13302 fprintf (stderr, "\n");
13306 rs6000_return_addr (int count, rtx frame)
13308 /* Currently we don't optimize very well between prolog and body
13309 code and for PIC code the code can be actually quite bad, so
13310 don't try to be too clever here. */
13311 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13313 cfun->machine->ra_needs_full_frame = 1;
13320 plus_constant (copy_to_reg
13321 (gen_rtx_MEM (Pmode,
13322 memory_address (Pmode, frame))),
13323 RETURN_ADDRESS_OFFSET)));
13326 cfun->machine->ra_need_lr = 1;
13327 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13330 /* Say whether a function is a candidate for sibcall handling or not.
13331 We do not allow indirect calls to be optimized into sibling calls.
13332 Also, we can't do it if there are any vector parameters; there's
13333 nowhere to put the VRsave code so it works; note that functions with
13334 vector parameters are required to have a prototype, so the argument
13335 type info must be available here. (The tail recursion case can work
13336 with vector parameters, but there's no way to distinguish here.) */
13338 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13343 if (TARGET_ALTIVEC_VRSAVE)
13345 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13346 type; type = TREE_CHAIN (type))
13348 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13352 if (DEFAULT_ABI == ABI_DARWIN
13353 || (*targetm.binds_local_p) (decl))
13355 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13357 if (!lookup_attribute ("longcall", attr_list)
13358 || lookup_attribute ("shortcall", attr_list))
13365 /* NULL if INSN insn is valid within a low-overhead loop.
13366 Otherwise return why doloop cannot be applied.
13367 PowerPC uses the COUNT register for branch on table instructions. */
13369 static const char *
13370 rs6000_invalid_within_doloop (rtx insn)
13373 return "Function call in the loop.";
13376 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13377 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13378 return "Computed branch in the loop.";
13384 rs6000_ra_ever_killed (void)
13390 if (current_function_is_thunk)
13393 /* regs_ever_live has LR marked as used if any sibcalls are present,
13394 but this should not force saving and restoring in the
13395 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13396 clobbers LR, so that is inappropriate. */
13398 /* Also, the prologue can generate a store into LR that
13399 doesn't really count, like this:
13402 bcl to set PIC register
13406 When we're called from the epilogue, we need to avoid counting
13407 this as a store. */
13409 push_topmost_sequence ();
13410 top = get_insns ();
13411 pop_topmost_sequence ();
13412 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13414 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13420 if (!SIBLING_CALL_P (insn))
13423 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13425 else if (set_of (reg, insn) != NULL_RTX
13426 && !prologue_epilogue_contains (insn))
13433 /* Add a REG_MAYBE_DEAD note to the insn. */
13435 rs6000_maybe_dead (rtx insn)
13437 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13442 /* Emit instructions needed to load the TOC register.
13443 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13444 a constant pool; or for SVR4 -fpic. */
13447 rs6000_emit_load_toc_table (int fromprolog)
13450 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13452 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13455 rtx lab, tmp1, tmp2, got, tempLR;
13457 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13458 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13460 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13462 got = rs6000_got_sym ();
13463 tmp1 = tmp2 = dest;
13466 tmp1 = gen_reg_rtx (Pmode);
13467 tmp2 = gen_reg_rtx (Pmode);
13469 tempLR = (fromprolog
13470 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13471 : gen_reg_rtx (Pmode));
13472 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13474 rs6000_maybe_dead (insn);
13475 insn = emit_move_insn (tmp1, tempLR);
13477 rs6000_maybe_dead (insn);
13478 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13480 rs6000_maybe_dead (insn);
13481 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13483 rs6000_maybe_dead (insn);
13485 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13487 rtx tempLR = (fromprolog
13488 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13489 : gen_reg_rtx (Pmode));
13491 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13493 rs6000_maybe_dead (insn);
13494 insn = emit_move_insn (dest, tempLR);
13496 rs6000_maybe_dead (insn);
13498 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13501 rtx tempLR = (fromprolog
13502 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13503 : gen_reg_rtx (Pmode));
13504 rtx temp0 = (fromprolog
13505 ? gen_rtx_REG (Pmode, 0)
13506 : gen_reg_rtx (Pmode));
13512 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13513 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13515 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13516 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13518 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13520 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13521 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13529 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13530 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13531 emit_move_insn (dest, tempLR);
13532 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13534 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13536 rs6000_maybe_dead (insn);
13538 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13540 /* This is for AIX code running in non-PIC ELF32. */
13543 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13544 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13546 insn = emit_insn (gen_elf_high (dest, realsym));
13548 rs6000_maybe_dead (insn);
13549 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13551 rs6000_maybe_dead (insn);
13555 gcc_assert (DEFAULT_ABI == ABI_AIX);
13558 insn = emit_insn (gen_load_toc_aix_si (dest));
13560 insn = emit_insn (gen_load_toc_aix_di (dest));
13562 rs6000_maybe_dead (insn);
13566 /* Emit instructions to restore the link register after determining where
13567 its value has been stored. */
13570 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13572 rs6000_stack_t *info = rs6000_stack_info ();
13575 operands[0] = source;
13576 operands[1] = scratch;
13578 if (info->lr_save_p)
13580 rtx frame_rtx = stack_pointer_rtx;
13581 HOST_WIDE_INT sp_offset = 0;
13584 if (frame_pointer_needed
13585 || current_function_calls_alloca
13586 || info->total_size > 32767)
13588 tmp = gen_frame_mem (Pmode, frame_rtx);
13589 emit_move_insn (operands[1], tmp);
13590 frame_rtx = operands[1];
13592 else if (info->push_p)
13593 sp_offset = info->total_size;
13595 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13596 tmp = gen_frame_mem (Pmode, tmp);
13597 emit_move_insn (tmp, operands[0]);
13600 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13603 static GTY(()) int set = -1;
13606 get_TOC_alias_set (void)
13609 set = new_alias_set ();
13613 /* This returns nonzero if the current function uses the TOC. This is
13614 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13615 is generated by the ABI_V4 load_toc_* patterns. */
13622 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13625 rtx pat = PATTERN (insn);
13628 if (GET_CODE (pat) == PARALLEL)
13629 for (i = 0; i < XVECLEN (pat, 0); i++)
13631 rtx sub = XVECEXP (pat, 0, i);
13632 if (GET_CODE (sub) == USE)
13634 sub = XEXP (sub, 0);
13635 if (GET_CODE (sub) == UNSPEC
13636 && XINT (sub, 1) == UNSPEC_TOC)
13646 create_TOC_reference (rtx symbol)
13648 if (no_new_pseudos)
13649 regs_ever_live[TOC_REGISTER] = 1;
13650 return gen_rtx_PLUS (Pmode,
13651 gen_rtx_REG (Pmode, TOC_REGISTER),
13652 gen_rtx_CONST (Pmode,
13653 gen_rtx_MINUS (Pmode, symbol,
13654 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13657 /* If _Unwind_* has been called from within the same module,
13658 toc register is not guaranteed to be saved to 40(1) on function
13659 entry. Save it there in that case. */
13662 rs6000_aix_emit_builtin_unwind_init (void)
13665 rtx stack_top = gen_reg_rtx (Pmode);
13666 rtx opcode_addr = gen_reg_rtx (Pmode);
13667 rtx opcode = gen_reg_rtx (SImode);
13668 rtx tocompare = gen_reg_rtx (SImode);
13669 rtx no_toc_save_needed = gen_label_rtx ();
13671 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13672 emit_move_insn (stack_top, mem);
13674 mem = gen_frame_mem (Pmode,
13675 gen_rtx_PLUS (Pmode, stack_top,
13676 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13677 emit_move_insn (opcode_addr, mem);
13678 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13679 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13680 : 0xE8410028, SImode));
13682 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13683 SImode, NULL_RTX, NULL_RTX,
13684 no_toc_save_needed);
13686 mem = gen_frame_mem (Pmode,
13687 gen_rtx_PLUS (Pmode, stack_top,
13688 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13689 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13690 emit_label (no_toc_save_needed);
13693 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13694 and the change to the stack pointer. */
13697 rs6000_emit_stack_tie (void)
13699 rtx mem = gen_frame_mem (BLKmode,
13700 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13702 emit_insn (gen_stack_tie (mem));
13705 /* Emit the correct code for allocating stack space, as insns.
13706 If COPY_R12, make sure a copy of the old frame is left in r12.
13707 The generated code may use hard register 0 as a temporary. */
13710 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13713 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13714 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13715 rtx todec = gen_int_mode (-size, Pmode);
13717 if (INTVAL (todec) != -size)
13719 warning (0, "stack frame too large");
13720 emit_insn (gen_trap ());
13724 if (current_function_limit_stack)
13726 if (REG_P (stack_limit_rtx)
13727 && REGNO (stack_limit_rtx) > 1
13728 && REGNO (stack_limit_rtx) <= 31)
13730 emit_insn (TARGET_32BIT
13731 ? gen_addsi3 (tmp_reg,
13734 : gen_adddi3 (tmp_reg,
13738 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13741 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13743 && DEFAULT_ABI == ABI_V4)
13745 rtx toload = gen_rtx_CONST (VOIDmode,
13746 gen_rtx_PLUS (Pmode,
13750 emit_insn (gen_elf_high (tmp_reg, toload));
13751 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13752 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13756 warning (0, "stack limit expression is not supported");
13759 if (copy_r12 || ! TARGET_UPDATE)
13760 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13766 /* Need a note here so that try_split doesn't get confused. */
13767 if (get_last_insn () == NULL_RTX)
13768 emit_note (NOTE_INSN_DELETED);
13769 insn = emit_move_insn (tmp_reg, todec);
13770 try_split (PATTERN (insn), insn, 0);
13774 insn = emit_insn (TARGET_32BIT
13775 ? gen_movsi_update (stack_reg, stack_reg,
13777 : gen_movdi_di_update (stack_reg, stack_reg,
13778 todec, stack_reg));
13782 insn = emit_insn (TARGET_32BIT
13783 ? gen_addsi3 (stack_reg, stack_reg, todec)
13784 : gen_adddi3 (stack_reg, stack_reg, todec));
13785 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13786 gen_rtx_REG (Pmode, 12));
13789 RTX_FRAME_RELATED_P (insn) = 1;
13791 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13792 gen_rtx_SET (VOIDmode, stack_reg,
13793 gen_rtx_PLUS (Pmode, stack_reg,
13798 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13799 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13800 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13801 deduce these equivalences by itself so it wasn't necessary to hold
13802 its hand so much. */
13805 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13806 rtx reg2, rtx rreg)
13810 /* copy_rtx will not make unique copies of registers, so we need to
13811 ensure we don't have unwanted sharing here. */
13813 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13816 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13818 real = copy_rtx (PATTERN (insn));
13820 if (reg2 != NULL_RTX)
13821 real = replace_rtx (real, reg2, rreg);
13823 real = replace_rtx (real, reg,
13824 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13825 STACK_POINTER_REGNUM),
13828 /* We expect that 'real' is either a SET or a PARALLEL containing
13829 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13830 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13832 if (GET_CODE (real) == SET)
13836 temp = simplify_rtx (SET_SRC (set));
13838 SET_SRC (set) = temp;
13839 temp = simplify_rtx (SET_DEST (set));
13841 SET_DEST (set) = temp;
13842 if (GET_CODE (SET_DEST (set)) == MEM)
13844 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13846 XEXP (SET_DEST (set), 0) = temp;
13853 gcc_assert (GET_CODE (real) == PARALLEL);
13854 for (i = 0; i < XVECLEN (real, 0); i++)
13855 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13857 rtx set = XVECEXP (real, 0, i);
13859 temp = simplify_rtx (SET_SRC (set));
13861 SET_SRC (set) = temp;
13862 temp = simplify_rtx (SET_DEST (set));
13864 SET_DEST (set) = temp;
13865 if (GET_CODE (SET_DEST (set)) == MEM)
13867 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13869 XEXP (SET_DEST (set), 0) = temp;
13871 RTX_FRAME_RELATED_P (set) = 1;
13876 real = spe_synthesize_frame_save (real);
13878 RTX_FRAME_RELATED_P (insn) = 1;
13879 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13884 /* Given an SPE frame note, return a PARALLEL of SETs with the
13885 original note, plus a synthetic register save. */
13888 spe_synthesize_frame_save (rtx real)
13890 rtx synth, offset, reg, real2;
13892 if (GET_CODE (real) != SET
13893 || GET_MODE (SET_SRC (real)) != V2SImode)
13896 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13897 frame related note. The parallel contains a set of the register
13898 being saved, and another set to a synthetic register (n+1200).
13899 This is so we can differentiate between 64-bit and 32-bit saves.
13900 Words cannot describe this nastiness. */
13902 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13903 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13904 && GET_CODE (SET_SRC (real)) == REG);
13907 (set (mem (plus (reg x) (const y)))
13910 (set (mem (plus (reg x) (const y+4)))
13914 real2 = copy_rtx (real);
13915 PUT_MODE (SET_DEST (real2), SImode);
13916 reg = SET_SRC (real2);
13917 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13918 synth = copy_rtx (real2);
13920 if (BYTES_BIG_ENDIAN)
13922 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13923 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13926 reg = SET_SRC (synth);
13928 synth = replace_rtx (synth, reg,
13929 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13931 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13932 synth = replace_rtx (synth, offset,
13933 GEN_INT (INTVAL (offset)
13934 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13936 RTX_FRAME_RELATED_P (synth) = 1;
13937 RTX_FRAME_RELATED_P (real2) = 1;
13938 if (BYTES_BIG_ENDIAN)
13939 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13941 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13946 /* Returns an insn that has a vrsave set operation with the
13947 appropriate CLOBBERs. */
13950 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13953 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13954 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13957 = gen_rtx_SET (VOIDmode,
13959 gen_rtx_UNSPEC_VOLATILE (SImode,
13960 gen_rtvec (2, reg, vrsave),
13961 UNSPECV_SET_VRSAVE));
13965 /* We need to clobber the registers in the mask so the scheduler
13966 does not move sets to VRSAVE before sets of AltiVec registers.
13968 However, if the function receives nonlocal gotos, reload will set
13969 all call saved registers live. We will end up with:
13971 (set (reg 999) (mem))
13972 (parallel [ (set (reg vrsave) (unspec blah))
13973 (clobber (reg 999))])
13975 The clobber will cause the store into reg 999 to be dead, and
13976 flow will attempt to delete an epilogue insn. In this case, we
13977 need an unspec use/set of the register. */
13979 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13980 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13982 if (!epiloguep || call_used_regs [i])
13983 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13984 gen_rtx_REG (V4SImode, i));
13987 rtx reg = gen_rtx_REG (V4SImode, i);
13990 = gen_rtx_SET (VOIDmode,
13992 gen_rtx_UNSPEC (V4SImode,
13993 gen_rtvec (1, reg), 27));
13997 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13999 for (i = 0; i < nclobs; ++i)
14000 XVECEXP (insn, 0, i) = clobs[i];
14005 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14006 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14009 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14010 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14012 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14013 rtx replacea, replaceb;
14015 int_rtx = GEN_INT (offset);
14017 /* Some cases that need register indexed addressing. */
14018 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14019 || (TARGET_E500_DOUBLE && mode == DFmode)
14021 && SPE_VECTOR_MODE (mode)
14022 && !SPE_CONST_OFFSET_OK (offset)))
14024 /* Whomever calls us must make sure r11 is available in the
14025 flow path of instructions in the prologue. */
14026 offset_rtx = gen_rtx_REG (Pmode, 11);
14027 emit_move_insn (offset_rtx, int_rtx);
14029 replacea = offset_rtx;
14030 replaceb = int_rtx;
14034 offset_rtx = int_rtx;
14035 replacea = NULL_RTX;
14036 replaceb = NULL_RTX;
14039 reg = gen_rtx_REG (mode, regno);
14040 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14041 mem = gen_frame_mem (mode, addr);
14043 insn = emit_move_insn (mem, reg);
14045 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14048 /* Emit an offset memory reference suitable for a frame store, while
14049 converting to a valid addressing mode. */
14052 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14054 rtx int_rtx, offset_rtx;
14056 int_rtx = GEN_INT (offset);
14058 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14059 || (TARGET_E500_DOUBLE && mode == DFmode))
14061 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14062 emit_move_insn (offset_rtx, int_rtx);
14065 offset_rtx = int_rtx;
14067 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14070 /* Look for user-defined global regs. We should not save and restore these,
14071 and cannot use stmw/lmw if there are any in its range. */
14074 no_global_regs_above (int first_greg)
14077 for (i = 0; i < 32 - first_greg; i++)
14078 if (global_regs[first_greg + i])
14083 #ifndef TARGET_FIX_AND_CONTINUE
14084 #define TARGET_FIX_AND_CONTINUE 0
14087 /* Emit function prologue as insns. */
14090 rs6000_emit_prologue (void)
14092 rs6000_stack_t *info = rs6000_stack_info ();
14093 enum machine_mode reg_mode = Pmode;
14094 int reg_size = TARGET_32BIT ? 4 : 8;
14095 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14096 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14097 rtx frame_reg_rtx = sp_reg_rtx;
14098 rtx cr_save_rtx = NULL_RTX;
14100 int saving_FPRs_inline;
14101 int using_store_multiple;
14102 HOST_WIDE_INT sp_offset = 0;
14104 if (TARGET_FIX_AND_CONTINUE)
14106 /* gdb on darwin arranges to forward a function from the old
14107 address by modifying the first 5 instructions of the function
14108 to branch to the overriding function. This is necessary to
14109 permit function pointers that point to the old function to
14110 actually forward to the new function. */
14111 emit_insn (gen_nop ());
14112 emit_insn (gen_nop ());
14113 emit_insn (gen_nop ());
14114 emit_insn (gen_nop ());
14115 emit_insn (gen_nop ());
14118 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14120 reg_mode = V2SImode;
14124 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14125 && (!TARGET_SPE_ABI
14126 || info->spe_64bit_regs_used == 0)
14127 && info->first_gp_reg_save < 31
14128 && no_global_regs_above (info->first_gp_reg_save));
14129 saving_FPRs_inline = (info->first_fp_reg_save == 64
14130 || FP_SAVE_INLINE (info->first_fp_reg_save)
14131 || current_function_calls_eh_return
14132 || cfun->machine->ra_need_lr);
14134 /* For V.4, update stack before we do any saving and set back pointer. */
14136 && (DEFAULT_ABI == ABI_V4
14137 || current_function_calls_eh_return))
14139 if (info->total_size < 32767)
14140 sp_offset = info->total_size;
14142 frame_reg_rtx = frame_ptr_rtx;
14143 rs6000_emit_allocate_stack (info->total_size,
14144 (frame_reg_rtx != sp_reg_rtx
14145 && (info->cr_save_p
14147 || info->first_fp_reg_save < 64
14148 || info->first_gp_reg_save < 32
14150 if (frame_reg_rtx != sp_reg_rtx)
14151 rs6000_emit_stack_tie ();
14154 /* Handle world saves specially here. */
14155 if (WORLD_SAVE_P (info))
14161 /* save_world expects lr in r0. */
14162 if (info->lr_save_p)
14164 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14165 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14166 RTX_FRAME_RELATED_P (insn) = 1;
14169 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14170 assumptions about the offsets of various bits of the stack
14172 gcc_assert (info->gp_save_offset == -220
14173 && info->fp_save_offset == -144
14174 && info->lr_save_offset == 8
14175 && info->cr_save_offset == 4
14178 && (!current_function_calls_eh_return
14179 || info->ehrd_offset == -432)
14180 && info->vrsave_save_offset == -224
14181 && info->altivec_save_offset == (-224 -16 -192));
14183 treg = gen_rtx_REG (SImode, 11);
14184 emit_move_insn (treg, GEN_INT (-info->total_size));
14186 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14187 in R11. It also clobbers R12, so beware! */
14189 /* Preserve CR2 for save_world prologues */
14191 sz += 32 - info->first_gp_reg_save;
14192 sz += 64 - info->first_fp_reg_save;
14193 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14194 p = rtvec_alloc (sz);
14196 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14197 gen_rtx_REG (Pmode,
14198 LINK_REGISTER_REGNUM));
14199 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14200 gen_rtx_SYMBOL_REF (Pmode,
14202 /* We do floats first so that the instruction pattern matches
14204 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14206 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14207 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14208 GEN_INT (info->fp_save_offset
14209 + sp_offset + 8 * i));
14210 rtx mem = gen_frame_mem (DFmode, addr);
14212 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14214 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14216 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14217 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14218 GEN_INT (info->altivec_save_offset
14219 + sp_offset + 16 * i));
14220 rtx mem = gen_frame_mem (V4SImode, addr);
14222 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14224 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14226 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14227 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14228 GEN_INT (info->gp_save_offset
14229 + sp_offset + reg_size * i));
14230 rtx mem = gen_frame_mem (reg_mode, addr);
14232 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14236 /* CR register traditionally saved as CR2. */
14237 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14238 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14239 GEN_INT (info->cr_save_offset
14241 rtx mem = gen_frame_mem (reg_mode, addr);
14243 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14245 /* Prevent any attempt to delete the setting of r0 and treg! */
14246 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14247 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14248 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14250 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14251 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14252 NULL_RTX, NULL_RTX);
14254 if (current_function_calls_eh_return)
14259 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14260 if (regno == INVALID_REGNUM)
14262 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14263 info->ehrd_offset + sp_offset
14264 + reg_size * (int) i,
14270 /* Save AltiVec registers if needed. */
14271 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14275 /* There should be a non inline version of this, for when we
14276 are saving lots of vector registers. */
14277 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14278 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14280 rtx areg, savereg, mem;
14283 offset = info->altivec_save_offset + sp_offset
14284 + 16 * (i - info->first_altivec_reg_save);
14286 savereg = gen_rtx_REG (V4SImode, i);
14288 areg = gen_rtx_REG (Pmode, 0);
14289 emit_move_insn (areg, GEN_INT (offset));
14291 /* AltiVec addressing mode is [reg+reg]. */
14292 mem = gen_frame_mem (V4SImode,
14293 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14295 insn = emit_move_insn (mem, savereg);
14297 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14298 areg, GEN_INT (offset));
14302 /* VRSAVE is a bit vector representing which AltiVec registers
14303 are used. The OS uses this to determine which vector
14304 registers to save on a context switch. We need to save
14305 VRSAVE on the stack frame, add whatever AltiVec registers we
14306 used in this function, and do the corresponding magic in the
14309 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14310 && info->vrsave_mask != 0)
14312 rtx reg, mem, vrsave;
14315 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14316 as frame_reg_rtx and r11 as the static chain pointer for
14317 nested functions. */
14318 reg = gen_rtx_REG (SImode, 0);
14319 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14321 emit_insn (gen_get_vrsave_internal (reg));
14323 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14325 if (!WORLD_SAVE_P (info))
14328 offset = info->vrsave_save_offset + sp_offset;
14329 mem = gen_frame_mem (SImode,
14330 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14331 GEN_INT (offset)));
14332 insn = emit_move_insn (mem, reg);
14335 /* Include the registers in the mask. */
14336 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14338 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14341 /* If we use the link register, get it into r0. */
14342 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14344 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14345 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14346 RTX_FRAME_RELATED_P (insn) = 1;
14349 /* If we need to save CR, put it into r12. */
14350 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14354 cr_save_rtx = gen_rtx_REG (SImode, 12);
14355 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14356 RTX_FRAME_RELATED_P (insn) = 1;
14357 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14358 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14359 But that's OK. All we have to do is specify that _one_ condition
14360 code register is saved in this stack slot. The thrower's epilogue
14361 will then restore all the call-saved registers.
14362 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14363 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14364 gen_rtx_REG (SImode, CR2_REGNO));
14365 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14370 /* Do any required saving of fpr's. If only one or two to save, do
14371 it ourselves. Otherwise, call function. */
14372 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14375 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14376 if ((regs_ever_live[info->first_fp_reg_save+i]
14377 && ! call_used_regs[info->first_fp_reg_save+i]))
14378 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14379 info->first_fp_reg_save + i,
14380 info->fp_save_offset + sp_offset + 8 * i,
14383 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14387 const char *alloc_rname;
14389 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14391 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14392 gen_rtx_REG (Pmode,
14393 LINK_REGISTER_REGNUM));
14394 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14395 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14396 alloc_rname = ggc_strdup (rname);
14397 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14398 gen_rtx_SYMBOL_REF (Pmode,
14400 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14402 rtx addr, reg, mem;
14403 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14404 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14405 GEN_INT (info->fp_save_offset
14406 + sp_offset + 8*i));
14407 mem = gen_frame_mem (DFmode, addr);
14409 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14411 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14412 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14413 NULL_RTX, NULL_RTX);
14416 /* Save GPRs. This is done as a PARALLEL if we are using
14417 the store-multiple instructions. */
14418 if (!WORLD_SAVE_P (info) && using_store_multiple)
14422 p = rtvec_alloc (32 - info->first_gp_reg_save);
14423 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14425 rtx addr, reg, mem;
14426 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14427 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14428 GEN_INT (info->gp_save_offset
14431 mem = gen_frame_mem (reg_mode, addr);
14433 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14435 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14436 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14437 NULL_RTX, NULL_RTX);
14439 else if (!WORLD_SAVE_P (info))
14442 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14443 if ((regs_ever_live[info->first_gp_reg_save + i]
14444 && (!call_used_regs[info->first_gp_reg_save + i]
14445 || (i + info->first_gp_reg_save
14446 == RS6000_PIC_OFFSET_TABLE_REGNUM
14447 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14448 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14449 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14450 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14452 rtx addr, reg, mem;
14453 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14455 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14457 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14460 if (!SPE_CONST_OFFSET_OK (offset))
14462 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14463 emit_move_insn (b, GEN_INT (offset));
14466 b = GEN_INT (offset);
14468 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14469 mem = gen_frame_mem (V2SImode, addr);
14470 insn = emit_move_insn (mem, reg);
14472 if (GET_CODE (b) == CONST_INT)
14473 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14474 NULL_RTX, NULL_RTX);
14476 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14477 b, GEN_INT (offset));
14481 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14482 GEN_INT (info->gp_save_offset
14485 mem = gen_frame_mem (reg_mode, addr);
14487 insn = emit_move_insn (mem, reg);
14488 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14489 NULL_RTX, NULL_RTX);
14494 /* ??? There's no need to emit actual instructions here, but it's the
14495 easiest way to get the frame unwind information emitted. */
14496 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14498 unsigned int i, regno;
14500 /* In AIX ABI we need to pretend we save r2 here. */
14503 rtx addr, reg, mem;
14505 reg = gen_rtx_REG (reg_mode, 2);
14506 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14507 GEN_INT (sp_offset + 5 * reg_size));
14508 mem = gen_frame_mem (reg_mode, addr);
14510 insn = emit_move_insn (mem, reg);
14511 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14512 NULL_RTX, NULL_RTX);
14513 PATTERN (insn) = gen_blockage ();
14518 regno = EH_RETURN_DATA_REGNO (i);
14519 if (regno == INVALID_REGNUM)
14522 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14523 info->ehrd_offset + sp_offset
14524 + reg_size * (int) i,
14529 /* Save lr if we used it. */
14530 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14532 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14533 GEN_INT (info->lr_save_offset + sp_offset));
14534 rtx reg = gen_rtx_REG (Pmode, 0);
14535 rtx mem = gen_rtx_MEM (Pmode, addr);
14536 /* This should not be of frame_alias_set, because of
14537 __builtin_return_address. */
14539 insn = emit_move_insn (mem, reg);
14540 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14541 NULL_RTX, NULL_RTX);
14544 /* Save CR if we use any that must be preserved. */
14545 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14547 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14548 GEN_INT (info->cr_save_offset + sp_offset));
14549 rtx mem = gen_frame_mem (SImode, addr);
14550 /* See the large comment above about why CR2_REGNO is used. */
14551 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14553 /* If r12 was used to hold the original sp, copy cr into r0 now
14555 if (REGNO (frame_reg_rtx) == 12)
14559 cr_save_rtx = gen_rtx_REG (SImode, 0);
14560 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14561 RTX_FRAME_RELATED_P (insn) = 1;
14562 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14563 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14568 insn = emit_move_insn (mem, cr_save_rtx);
14570 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14571 NULL_RTX, NULL_RTX);
14574 /* Update stack and set back pointer unless this is V.4,
14575 for which it was done previously. */
14576 if (!WORLD_SAVE_P (info) && info->push_p
14577 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14578 rs6000_emit_allocate_stack (info->total_size, FALSE);
14580 /* Set frame pointer, if needed. */
14581 if (frame_pointer_needed)
14583 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14585 RTX_FRAME_RELATED_P (insn) = 1;
14588 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14589 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14590 || (DEFAULT_ABI == ABI_V4
14591 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14592 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14594 /* If emit_load_toc_table will use the link register, we need to save
14595 it. We use R12 for this purpose because emit_load_toc_table
14596 can use register 0. This allows us to use a plain 'blr' to return
14597 from the procedure more often. */
14598 int save_LR_around_toc_setup = (TARGET_ELF
14599 && DEFAULT_ABI != ABI_AIX
14601 && ! info->lr_save_p
14602 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14603 if (save_LR_around_toc_setup)
14605 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14607 insn = emit_move_insn (frame_ptr_rtx, lr);
14608 rs6000_maybe_dead (insn);
14609 RTX_FRAME_RELATED_P (insn) = 1;
14611 rs6000_emit_load_toc_table (TRUE);
14613 insn = emit_move_insn (lr, frame_ptr_rtx);
14614 rs6000_maybe_dead (insn);
14615 RTX_FRAME_RELATED_P (insn) = 1;
14618 rs6000_emit_load_toc_table (TRUE);
14622 if (DEFAULT_ABI == ABI_DARWIN
14623 && flag_pic && current_function_uses_pic_offset_table)
14625 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14626 rtx src = machopic_function_base_sym ();
14628 /* Save and restore LR locally around this call (in R0). */
14629 if (!info->lr_save_p)
14630 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14632 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14634 insn = emit_move_insn (gen_rtx_REG (Pmode,
14635 RS6000_PIC_OFFSET_TABLE_REGNUM),
14637 rs6000_maybe_dead (insn);
14639 if (!info->lr_save_p)
14640 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14645 /* Write function prologue. */
14648 rs6000_output_function_prologue (FILE *file,
14649 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14651 rs6000_stack_t *info = rs6000_stack_info ();
14653 if (TARGET_DEBUG_STACK)
14654 debug_stack_info (info);
14656 /* Write .extern for any function we will call to save and restore
14658 if (info->first_fp_reg_save < 64
14659 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14660 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14661 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14662 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14663 RESTORE_FP_SUFFIX);
14665 /* Write .extern for AIX common mode routines, if needed. */
14666 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14668 fputs ("\t.extern __mulh\n", file);
14669 fputs ("\t.extern __mull\n", file);
14670 fputs ("\t.extern __divss\n", file);
14671 fputs ("\t.extern __divus\n", file);
14672 fputs ("\t.extern __quoss\n", file);
14673 fputs ("\t.extern __quous\n", file);
14674 common_mode_defined = 1;
14677 if (! HAVE_prologue)
14681 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14682 the "toplevel" insn chain. */
14683 emit_note (NOTE_INSN_DELETED);
14684 rs6000_emit_prologue ();
14685 emit_note (NOTE_INSN_DELETED);
14687 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14691 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14693 INSN_ADDRESSES_NEW (insn, addr);
14698 if (TARGET_DEBUG_STACK)
14699 debug_rtx_list (get_insns (), 100);
14700 final (get_insns (), file, FALSE);
14704 rs6000_pic_labelno++;
14707 /* Emit function epilogue as insns.
14709 At present, dwarf2out_frame_debug_expr doesn't understand
14710 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14711 anywhere in the epilogue. Most of the insns below would in any case
14712 need special notes to explain where r11 is in relation to the stack. */
14715 rs6000_emit_epilogue (int sibcall)
14717 rs6000_stack_t *info;
14718 int restoring_FPRs_inline;
14719 int using_load_multiple;
14720 int using_mfcr_multiple;
14721 int use_backchain_to_restore_sp;
14723 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14724 rtx frame_reg_rtx = sp_reg_rtx;
14725 enum machine_mode reg_mode = Pmode;
14726 int reg_size = TARGET_32BIT ? 4 : 8;
14729 info = rs6000_stack_info ();
14731 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14733 reg_mode = V2SImode;
14737 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14738 && (!TARGET_SPE_ABI
14739 || info->spe_64bit_regs_used == 0)
14740 && info->first_gp_reg_save < 31
14741 && no_global_regs_above (info->first_gp_reg_save));
14742 restoring_FPRs_inline = (sibcall
14743 || current_function_calls_eh_return
14744 || info->first_fp_reg_save == 64
14745 || FP_SAVE_INLINE (info->first_fp_reg_save));
14746 use_backchain_to_restore_sp = (frame_pointer_needed
14747 || current_function_calls_alloca
14748 || info->total_size > 32767);
14749 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14750 || rs6000_cpu == PROCESSOR_PPC603
14751 || rs6000_cpu == PROCESSOR_PPC750
14754 if (WORLD_SAVE_P (info))
14758 const char *alloc_rname;
14761 /* eh_rest_world_r10 will return to the location saved in the LR
14762 stack slot (which is not likely to be our caller.)
14763 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14764 rest_world is similar, except any R10 parameter is ignored.
14765 The exception-handling stuff that was here in 2.95 is no
14766 longer necessary. */
14770 + 32 - info->first_gp_reg_save
14771 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14772 + 63 + 1 - info->first_fp_reg_save);
14774 strcpy (rname, ((current_function_calls_eh_return) ?
14775 "*eh_rest_world_r10" : "*rest_world"));
14776 alloc_rname = ggc_strdup (rname);
14779 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14780 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14781 gen_rtx_REG (Pmode,
14782 LINK_REGISTER_REGNUM));
14784 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14785 /* The instruction pattern requires a clobber here;
14786 it is shared with the restVEC helper. */
14788 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14791 /* CR register traditionally saved as CR2. */
14792 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14793 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14794 GEN_INT (info->cr_save_offset));
14795 rtx mem = gen_frame_mem (reg_mode, addr);
14797 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14800 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14802 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14803 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14804 GEN_INT (info->gp_save_offset
14806 rtx mem = gen_frame_mem (reg_mode, addr);
14808 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14810 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14812 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14813 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14814 GEN_INT (info->altivec_save_offset
14816 rtx mem = gen_frame_mem (V4SImode, addr);
14818 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14820 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14822 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14823 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14824 GEN_INT (info->fp_save_offset
14826 rtx mem = gen_frame_mem (DFmode, addr);
14828 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14831 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14833 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14835 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14837 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14839 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14840 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14845 /* If we have a frame pointer, a call to alloca, or a large stack
14846 frame, restore the old stack pointer using the backchain. Otherwise,
14847 we know what size to update it with. */
14848 if (use_backchain_to_restore_sp)
14850 /* Under V.4, don't reset the stack pointer until after we're done
14851 loading the saved registers. */
14852 if (DEFAULT_ABI == ABI_V4)
14853 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14855 emit_move_insn (frame_reg_rtx,
14856 gen_rtx_MEM (Pmode, sp_reg_rtx));
14858 else if (info->push_p)
14860 if (DEFAULT_ABI == ABI_V4
14861 || current_function_calls_eh_return)
14862 sp_offset = info->total_size;
14865 emit_insn (TARGET_32BIT
14866 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14867 GEN_INT (info->total_size))
14868 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14869 GEN_INT (info->total_size)));
14873 /* Restore AltiVec registers if needed. */
14874 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14878 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14879 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14881 rtx addr, areg, mem;
14883 areg = gen_rtx_REG (Pmode, 0);
14885 (areg, GEN_INT (info->altivec_save_offset
14887 + 16 * (i - info->first_altivec_reg_save)));
14889 /* AltiVec addressing mode is [reg+reg]. */
14890 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14891 mem = gen_frame_mem (V4SImode, addr);
14893 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14897 /* Restore VRSAVE if needed. */
14898 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14899 && info->vrsave_mask != 0)
14901 rtx addr, mem, reg;
14903 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14904 GEN_INT (info->vrsave_save_offset + sp_offset));
14905 mem = gen_frame_mem (SImode, addr);
14906 reg = gen_rtx_REG (SImode, 12);
14907 emit_move_insn (reg, mem);
14909 emit_insn (generate_set_vrsave (reg, info, 1));
14912 /* Get the old lr if we saved it. */
14913 if (info->lr_save_p)
14915 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14916 info->lr_save_offset + sp_offset);
14918 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14921 /* Get the old cr if we saved it. */
14922 if (info->cr_save_p)
14924 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14925 GEN_INT (info->cr_save_offset + sp_offset));
14926 rtx mem = gen_frame_mem (SImode, addr);
14928 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14931 /* Set LR here to try to overlap restores below. */
14932 if (info->lr_save_p)
14933 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14934 gen_rtx_REG (Pmode, 0));
14936 /* Load exception handler data registers, if needed. */
14937 if (current_function_calls_eh_return)
14939 unsigned int i, regno;
14943 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14944 GEN_INT (sp_offset + 5 * reg_size));
14945 rtx mem = gen_frame_mem (reg_mode, addr);
14947 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14954 regno = EH_RETURN_DATA_REGNO (i);
14955 if (regno == INVALID_REGNUM)
14958 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14959 info->ehrd_offset + sp_offset
14960 + reg_size * (int) i);
14962 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14966 /* Restore GPRs. This is done as a PARALLEL if we are using
14967 the load-multiple instructions. */
14968 if (using_load_multiple)
14971 p = rtvec_alloc (32 - info->first_gp_reg_save);
14972 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14974 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14975 GEN_INT (info->gp_save_offset
14978 rtx mem = gen_frame_mem (reg_mode, addr);
14981 gen_rtx_SET (VOIDmode,
14982 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14985 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14988 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14989 if ((regs_ever_live[info->first_gp_reg_save + i]
14990 && (!call_used_regs[info->first_gp_reg_save + i]
14991 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14992 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14993 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14994 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14995 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14997 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14998 GEN_INT (info->gp_save_offset
15001 rtx mem = gen_frame_mem (reg_mode, addr);
15003 /* Restore 64-bit quantities for SPE. */
15004 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15006 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15009 if (!SPE_CONST_OFFSET_OK (offset))
15011 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15012 emit_move_insn (b, GEN_INT (offset));
15015 b = GEN_INT (offset);
15017 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15018 mem = gen_frame_mem (V2SImode, addr);
15021 emit_move_insn (gen_rtx_REG (reg_mode,
15022 info->first_gp_reg_save + i), mem);
15025 /* Restore fpr's if we need to do it without calling a function. */
15026 if (restoring_FPRs_inline)
15027 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15028 if ((regs_ever_live[info->first_fp_reg_save+i]
15029 && ! call_used_regs[info->first_fp_reg_save+i]))
15032 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15033 GEN_INT (info->fp_save_offset
15036 mem = gen_frame_mem (DFmode, addr);
15038 emit_move_insn (gen_rtx_REG (DFmode,
15039 info->first_fp_reg_save + i),
15043 /* If we saved cr, restore it here. Just those that were used. */
15044 if (info->cr_save_p)
15046 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15049 if (using_mfcr_multiple)
15051 for (i = 0; i < 8; i++)
15052 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15054 gcc_assert (count);
15057 if (using_mfcr_multiple && count > 1)
15062 p = rtvec_alloc (count);
15065 for (i = 0; i < 8; i++)
15066 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15068 rtvec r = rtvec_alloc (2);
15069 RTVEC_ELT (r, 0) = r12_rtx;
15070 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15071 RTVEC_ELT (p, ndx) =
15072 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15073 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15076 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15077 gcc_assert (ndx == count);
15080 for (i = 0; i < 8; i++)
15081 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15083 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15089 /* If this is V.4, unwind the stack pointer after all of the loads
15091 if (frame_reg_rtx != sp_reg_rtx)
15093 /* This blockage is needed so that sched doesn't decide to move
15094 the sp change before the register restores. */
15095 rs6000_emit_stack_tie ();
15096 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15098 else if (sp_offset != 0)
15099 emit_insn (TARGET_32BIT
15100 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15101 GEN_INT (sp_offset))
15102 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15103 GEN_INT (sp_offset)));
15105 if (current_function_calls_eh_return)
15107 rtx sa = EH_RETURN_STACKADJ_RTX;
15108 emit_insn (TARGET_32BIT
15109 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15110 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15116 if (! restoring_FPRs_inline)
15117 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15119 p = rtvec_alloc (2);
15121 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15122 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15123 gen_rtx_REG (Pmode,
15124 LINK_REGISTER_REGNUM));
15126 /* If we have to restore more than two FP registers, branch to the
15127 restore function. It will return to our caller. */
15128 if (! restoring_FPRs_inline)
15132 const char *alloc_rname;
15134 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15135 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15136 alloc_rname = ggc_strdup (rname);
15137 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15138 gen_rtx_SYMBOL_REF (Pmode,
15141 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15144 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15145 GEN_INT (info->fp_save_offset + 8*i));
15146 mem = gen_frame_mem (DFmode, addr);
15148 RTVEC_ELT (p, i+3) =
15149 gen_rtx_SET (VOIDmode,
15150 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15155 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15159 /* Write function epilogue. */
15162 rs6000_output_function_epilogue (FILE *file,
15163 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15165 if (! HAVE_epilogue)
15167 rtx insn = get_last_insn ();
15168 /* If the last insn was a BARRIER, we don't have to write anything except
15169 the trace table. */
15170 if (GET_CODE (insn) == NOTE)
15171 insn = prev_nonnote_insn (insn);
15172 if (insn == 0 || GET_CODE (insn) != BARRIER)
15174 /* This is slightly ugly, but at least we don't have two
15175 copies of the epilogue-emitting code. */
15178 /* A NOTE_INSN_DELETED is supposed to be at the start
15179 and end of the "toplevel" insn chain. */
15180 emit_note (NOTE_INSN_DELETED);
15181 rs6000_emit_epilogue (FALSE);
15182 emit_note (NOTE_INSN_DELETED);
15184 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15188 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15190 INSN_ADDRESSES_NEW (insn, addr);
15195 if (TARGET_DEBUG_STACK)
15196 debug_rtx_list (get_insns (), 100);
15197 final (get_insns (), file, FALSE);
15203 macho_branch_islands ();
15204 /* Mach-O doesn't support labels at the end of objects, so if
15205 it looks like we might want one, insert a NOP. */
15207 rtx insn = get_last_insn ();
15210 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15211 insn = PREV_INSN (insn);
15215 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15216 fputs ("\tnop\n", file);
15220 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15223 We don't output a traceback table if -finhibit-size-directive was
15224 used. The documentation for -finhibit-size-directive reads
15225 ``don't output a @code{.size} assembler directive, or anything
15226 else that would cause trouble if the function is split in the
15227 middle, and the two halves are placed at locations far apart in
15228 memory.'' The traceback table has this property, since it
15229 includes the offset from the start of the function to the
15230 traceback table itself.
15232 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15233 different traceback table. */
15234 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15235 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15237 const char *fname = NULL;
15238 const char *language_string = lang_hooks.name;
15239 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15241 int optional_tbtab;
15242 rs6000_stack_t *info = rs6000_stack_info ();
15244 if (rs6000_traceback == traceback_full)
15245 optional_tbtab = 1;
15246 else if (rs6000_traceback == traceback_part)
15247 optional_tbtab = 0;
15249 optional_tbtab = !optimize_size && !TARGET_ELF;
15251 if (optional_tbtab)
15253 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15254 while (*fname == '.') /* V.4 encodes . in the name */
15257 /* Need label immediately before tbtab, so we can compute
15258 its offset from the function start. */
15259 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15260 ASM_OUTPUT_LABEL (file, fname);
15263 /* The .tbtab pseudo-op can only be used for the first eight
15264 expressions, since it can't handle the possibly variable
15265 length fields that follow. However, if you omit the optional
15266 fields, the assembler outputs zeros for all optional fields
15267 anyways, giving each variable length field is minimum length
15268 (as defined in sys/debug.h). Thus we can not use the .tbtab
15269 pseudo-op at all. */
15271 /* An all-zero word flags the start of the tbtab, for debuggers
15272 that have to find it by searching forward from the entry
15273 point or from the current pc. */
15274 fputs ("\t.long 0\n", file);
15276 /* Tbtab format type. Use format type 0. */
15277 fputs ("\t.byte 0,", file);
15279 /* Language type. Unfortunately, there does not seem to be any
15280 official way to discover the language being compiled, so we
15281 use language_string.
15282 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15283 Java is 13. Objective-C is 14. */
15284 if (! strcmp (language_string, "GNU C"))
15286 else if (! strcmp (language_string, "GNU F77")
15287 || ! strcmp (language_string, "GNU F95"))
15289 else if (! strcmp (language_string, "GNU Pascal"))
15291 else if (! strcmp (language_string, "GNU Ada"))
15293 else if (! strcmp (language_string, "GNU C++"))
15295 else if (! strcmp (language_string, "GNU Java"))
15297 else if (! strcmp (language_string, "GNU Objective-C"))
15300 gcc_unreachable ();
15301 fprintf (file, "%d,", i);
15303 /* 8 single bit fields: global linkage (not set for C extern linkage,
15304 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15305 from start of procedure stored in tbtab, internal function, function
15306 has controlled storage, function has no toc, function uses fp,
15307 function logs/aborts fp operations. */
15308 /* Assume that fp operations are used if any fp reg must be saved. */
15309 fprintf (file, "%d,",
15310 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15312 /* 6 bitfields: function is interrupt handler, name present in
15313 proc table, function calls alloca, on condition directives
15314 (controls stack walks, 3 bits), saves condition reg, saves
15316 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15317 set up as a frame pointer, even when there is no alloca call. */
15318 fprintf (file, "%d,",
15319 ((optional_tbtab << 6)
15320 | ((optional_tbtab & frame_pointer_needed) << 5)
15321 | (info->cr_save_p << 1)
15322 | (info->lr_save_p)));
15324 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15326 fprintf (file, "%d,",
15327 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15329 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15330 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15332 if (optional_tbtab)
15334 /* Compute the parameter info from the function decl argument
15337 int next_parm_info_bit = 31;
15339 for (decl = DECL_ARGUMENTS (current_function_decl);
15340 decl; decl = TREE_CHAIN (decl))
15342 rtx parameter = DECL_INCOMING_RTL (decl);
15343 enum machine_mode mode = GET_MODE (parameter);
15345 if (GET_CODE (parameter) == REG)
15347 if (SCALAR_FLOAT_MODE_P (mode))
15365 gcc_unreachable ();
15368 /* If only one bit will fit, don't or in this entry. */
15369 if (next_parm_info_bit > 0)
15370 parm_info |= (bits << (next_parm_info_bit - 1));
15371 next_parm_info_bit -= 2;
15375 fixed_parms += ((GET_MODE_SIZE (mode)
15376 + (UNITS_PER_WORD - 1))
15378 next_parm_info_bit -= 1;
15384 /* Number of fixed point parameters. */
15385 /* This is actually the number of words of fixed point parameters; thus
15386 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15387 fprintf (file, "%d,", fixed_parms);
15389 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15391 /* This is actually the number of fp registers that hold parameters;
15392 and thus the maximum value is 13. */
15393 /* Set parameters on stack bit if parameters are not in their original
15394 registers, regardless of whether they are on the stack? Xlc
15395 seems to set the bit when not optimizing. */
15396 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15398 if (! optional_tbtab)
15401 /* Optional fields follow. Some are variable length. */
15403 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15404 11 double float. */
15405 /* There is an entry for each parameter in a register, in the order that
15406 they occur in the parameter list. Any intervening arguments on the
15407 stack are ignored. If the list overflows a long (max possible length
15408 34 bits) then completely leave off all elements that don't fit. */
15409 /* Only emit this long if there was at least one parameter. */
15410 if (fixed_parms || float_parms)
15411 fprintf (file, "\t.long %d\n", parm_info);
15413 /* Offset from start of code to tb table. */
15414 fputs ("\t.long ", file);
15415 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15417 RS6000_OUTPUT_BASENAME (file, fname);
15419 assemble_name (file, fname);
15421 rs6000_output_function_entry (file, fname);
15424 /* Interrupt handler mask. */
15425 /* Omit this long, since we never set the interrupt handler bit
15428 /* Number of CTL (controlled storage) anchors. */
15429 /* Omit this long, since the has_ctl bit is never set above. */
15431 /* Displacement into stack of each CTL anchor. */
15432 /* Omit this list of longs, because there are no CTL anchors. */
15434 /* Length of function name. */
15437 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15439 /* Function name. */
15440 assemble_string (fname, strlen (fname));
15442 /* Register for alloca automatic storage; this is always reg 31.
15443 Only emit this if the alloca bit was set above. */
15444 if (frame_pointer_needed)
15445 fputs ("\t.byte 31\n", file);
15447 fputs ("\t.align 2\n", file);
15451 /* A C compound statement that outputs the assembler code for a thunk
15452 function, used to implement C++ virtual function calls with
15453 multiple inheritance. The thunk acts as a wrapper around a virtual
15454 function, adjusting the implicit object parameter before handing
15455 control off to the real function.
15457 First, emit code to add the integer DELTA to the location that
15458 contains the incoming first argument. Assume that this argument
15459 contains a pointer, and is the one used to pass the `this' pointer
15460 in C++. This is the incoming argument *before* the function
15461 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15462 values of all other incoming arguments.
15464 After the addition, emit code to jump to FUNCTION, which is a
15465 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15466 not touch the return address. Hence returning from FUNCTION will
15467 return to whoever called the current `thunk'.
15469 The effect must be as if FUNCTION had been called directly with the
15470 adjusted first argument. This macro is responsible for emitting
15471 all of the code for a thunk function; output_function_prologue()
15472 and output_function_epilogue() are not invoked.
15474 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15475 been extracted from it.) It might possibly be useful on some
15476 targets, but probably not.
15478 If you do not define this macro, the target-independent code in the
15479 C++ frontend will generate a less efficient heavyweight thunk that
15480 calls FUNCTION instead of jumping to it. The generic approach does
15481 not support varargs. */
15484 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15485 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15488 rtx this, insn, funexp;
15490 reload_completed = 1;
15491 epilogue_completed = 1;
15492 no_new_pseudos = 1;
15493 reset_block_changes ();
15495 /* Mark the end of the (empty) prologue. */
15496 emit_note (NOTE_INSN_PROLOGUE_END);
15498 /* Find the "this" pointer. If the function returns a structure,
15499 the structure return pointer is in r3. */
15500 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15501 this = gen_rtx_REG (Pmode, 4);
15503 this = gen_rtx_REG (Pmode, 3);
15505 /* Apply the constant offset, if required. */
15508 rtx delta_rtx = GEN_INT (delta);
15509 emit_insn (TARGET_32BIT
15510 ? gen_addsi3 (this, this, delta_rtx)
15511 : gen_adddi3 (this, this, delta_rtx));
15514 /* Apply the offset from the vtable, if required. */
15517 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15518 rtx tmp = gen_rtx_REG (Pmode, 12);
15520 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15521 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15523 emit_insn (TARGET_32BIT
15524 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15525 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15526 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15530 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15532 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15534 emit_insn (TARGET_32BIT
15535 ? gen_addsi3 (this, this, tmp)
15536 : gen_adddi3 (this, this, tmp));
15539 /* Generate a tail call to the target function. */
15540 if (!TREE_USED (function))
15542 assemble_external (function);
15543 TREE_USED (function) = 1;
15545 funexp = XEXP (DECL_RTL (function), 0);
15546 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15549 if (MACHOPIC_INDIRECT)
15550 funexp = machopic_indirect_call_target (funexp);
15553 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15554 generate sibcall RTL explicitly. */
15555 insn = emit_call_insn (
15556 gen_rtx_PARALLEL (VOIDmode,
15558 gen_rtx_CALL (VOIDmode,
15559 funexp, const0_rtx),
15560 gen_rtx_USE (VOIDmode, const0_rtx),
15561 gen_rtx_USE (VOIDmode,
15562 gen_rtx_REG (SImode,
15563 LINK_REGISTER_REGNUM)),
15564 gen_rtx_RETURN (VOIDmode))));
15565 SIBLING_CALL_P (insn) = 1;
15568 /* Run just enough of rest_of_compilation to get the insns emitted.
15569 There's not really enough bulk here to make other passes such as
15570 instruction scheduling worth while. Note that use_thunk calls
15571 assemble_start_function and assemble_end_function. */
15572 insn = get_insns ();
15573 insn_locators_initialize ();
15574 shorten_branches (insn);
15575 final_start_function (insn, file, 1);
15576 final (insn, file, 1);
15577 final_end_function ();
15579 reload_completed = 0;
15580 epilogue_completed = 0;
15581 no_new_pseudos = 0;
15584 /* A quick summary of the various types of 'constant-pool tables'
15587 Target Flags Name One table per
15588 AIX (none) AIX TOC object file
15589 AIX -mfull-toc AIX TOC object file
15590 AIX -mminimal-toc AIX minimal TOC translation unit
15591 SVR4/EABI (none) SVR4 SDATA object file
15592 SVR4/EABI -fpic SVR4 pic object file
15593 SVR4/EABI -fPIC SVR4 PIC translation unit
15594 SVR4/EABI -mrelocatable EABI TOC function
15595 SVR4/EABI -maix AIX TOC object file
15596 SVR4/EABI -maix -mminimal-toc
15597 AIX minimal TOC translation unit
15599 Name Reg. Set by entries contains:
15600 made by addrs? fp? sum?
15602 AIX TOC 2 crt0 as Y option option
15603 AIX minimal TOC 30 prolog gcc Y Y option
15604 SVR4 SDATA 13 crt0 gcc N Y N
15605 SVR4 pic 30 prolog ld Y not yet N
15606 SVR4 PIC 30 prolog gcc Y option option
15607 EABI TOC 30 prolog gcc Y option option
15611 /* Hash functions for the hash table. */
15614 rs6000_hash_constant (rtx k)
15616 enum rtx_code code = GET_CODE (k);
15617 enum machine_mode mode = GET_MODE (k);
15618 unsigned result = (code << 3) ^ mode;
15619 const char *format;
15622 format = GET_RTX_FORMAT (code);
15623 flen = strlen (format);
15629 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15632 if (mode != VOIDmode)
15633 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15645 for (; fidx < flen; fidx++)
15646 switch (format[fidx])
15651 const char *str = XSTR (k, fidx);
15652 len = strlen (str);
15653 result = result * 613 + len;
15654 for (i = 0; i < len; i++)
15655 result = result * 613 + (unsigned) str[i];
15660 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15664 result = result * 613 + (unsigned) XINT (k, fidx);
15667 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15668 result = result * 613 + (unsigned) XWINT (k, fidx);
15672 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15673 result = result * 613 + (unsigned) (XWINT (k, fidx)
15680 gcc_unreachable ();
15687 toc_hash_function (const void *hash_entry)
15689 const struct toc_hash_struct *thc =
15690 (const struct toc_hash_struct *) hash_entry;
15691 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15694 /* Compare H1 and H2 for equivalence. */
15697 toc_hash_eq (const void *h1, const void *h2)
15699 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15700 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15702 if (((const struct toc_hash_struct *) h1)->key_mode
15703 != ((const struct toc_hash_struct *) h2)->key_mode)
15706 return rtx_equal_p (r1, r2);
15709 /* These are the names given by the C++ front-end to vtables, and
15710 vtable-like objects. Ideally, this logic should not be here;
15711 instead, there should be some programmatic way of inquiring as
15712 to whether or not an object is a vtable. */
15714 #define VTABLE_NAME_P(NAME) \
15715 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15716 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15717 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15718 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15719 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15722 rs6000_output_symbol_ref (FILE *file, rtx x)
15724 /* Currently C++ toc references to vtables can be emitted before it
15725 is decided whether the vtable is public or private. If this is
15726 the case, then the linker will eventually complain that there is
15727 a reference to an unknown section. Thus, for vtables only,
15728 we emit the TOC reference to reference the symbol and not the
15730 const char *name = XSTR (x, 0);
15732 if (VTABLE_NAME_P (name))
15734 RS6000_OUTPUT_BASENAME (file, name);
15737 assemble_name (file, name);
15740 /* Output a TOC entry. We derive the entry name from what is being
15744 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15747 const char *name = buf;
15748 const char *real_name;
15750 HOST_WIDE_INT offset = 0;
15752 gcc_assert (!TARGET_NO_TOC);
15754 /* When the linker won't eliminate them, don't output duplicate
15755 TOC entries (this happens on AIX if there is any kind of TOC,
15756 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15758 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15760 struct toc_hash_struct *h;
15763 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15764 time because GGC is not initialized at that point. */
15765 if (toc_hash_table == NULL)
15766 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15767 toc_hash_eq, NULL);
15769 h = ggc_alloc (sizeof (*h));
15771 h->key_mode = mode;
15772 h->labelno = labelno;
15774 found = htab_find_slot (toc_hash_table, h, 1);
15775 if (*found == NULL)
15777 else /* This is indeed a duplicate.
15778 Set this label equal to that label. */
15780 fputs ("\t.set ", file);
15781 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15782 fprintf (file, "%d,", labelno);
15783 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15784 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15790 /* If we're going to put a double constant in the TOC, make sure it's
15791 aligned properly when strict alignment is on. */
15792 if (GET_CODE (x) == CONST_DOUBLE
15793 && STRICT_ALIGNMENT
15794 && GET_MODE_BITSIZE (mode) >= 64
15795 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15796 ASM_OUTPUT_ALIGN (file, 3);
15799 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15801 /* Handle FP constants specially. Note that if we have a minimal
15802 TOC, things we put here aren't actually in the TOC, so we can allow
15804 if (GET_CODE (x) == CONST_DOUBLE &&
15805 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15807 REAL_VALUE_TYPE rv;
15810 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15811 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15812 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15814 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15818 if (TARGET_MINIMAL_TOC)
15819 fputs (DOUBLE_INT_ASM_OP, file);
15821 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15822 k[0] & 0xffffffff, k[1] & 0xffffffff,
15823 k[2] & 0xffffffff, k[3] & 0xffffffff);
15824 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15825 k[0] & 0xffffffff, k[1] & 0xffffffff,
15826 k[2] & 0xffffffff, k[3] & 0xffffffff);
15831 if (TARGET_MINIMAL_TOC)
15832 fputs ("\t.long ", file);
15834 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15835 k[0] & 0xffffffff, k[1] & 0xffffffff,
15836 k[2] & 0xffffffff, k[3] & 0xffffffff);
15837 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15838 k[0] & 0xffffffff, k[1] & 0xffffffff,
15839 k[2] & 0xffffffff, k[3] & 0xffffffff);
15843 else if (GET_CODE (x) == CONST_DOUBLE &&
15844 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
15846 REAL_VALUE_TYPE rv;
15849 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15851 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15852 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
15854 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15858 if (TARGET_MINIMAL_TOC)
15859 fputs (DOUBLE_INT_ASM_OP, file);
15861 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15862 k[0] & 0xffffffff, k[1] & 0xffffffff);
15863 fprintf (file, "0x%lx%08lx\n",
15864 k[0] & 0xffffffff, k[1] & 0xffffffff);
15869 if (TARGET_MINIMAL_TOC)
15870 fputs ("\t.long ", file);
15872 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15873 k[0] & 0xffffffff, k[1] & 0xffffffff);
15874 fprintf (file, "0x%lx,0x%lx\n",
15875 k[0] & 0xffffffff, k[1] & 0xffffffff);
15879 else if (GET_CODE (x) == CONST_DOUBLE &&
15880 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
15882 REAL_VALUE_TYPE rv;
15885 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15886 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15887 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
15889 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15893 if (TARGET_MINIMAL_TOC)
15894 fputs (DOUBLE_INT_ASM_OP, file);
15896 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15897 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15902 if (TARGET_MINIMAL_TOC)
15903 fputs ("\t.long ", file);
15905 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15906 fprintf (file, "0x%lx\n", l & 0xffffffff);
15910 else if (GET_MODE (x) == VOIDmode
15911 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15913 unsigned HOST_WIDE_INT low;
15914 HOST_WIDE_INT high;
15916 if (GET_CODE (x) == CONST_DOUBLE)
15918 low = CONST_DOUBLE_LOW (x);
15919 high = CONST_DOUBLE_HIGH (x);
15922 #if HOST_BITS_PER_WIDE_INT == 32
15925 high = (low & 0x80000000) ? ~0 : 0;
15929 low = INTVAL (x) & 0xffffffff;
15930 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15934 /* TOC entries are always Pmode-sized, but since this
15935 is a bigendian machine then if we're putting smaller
15936 integer constants in the TOC we have to pad them.
15937 (This is still a win over putting the constants in
15938 a separate constant pool, because then we'd have
15939 to have both a TOC entry _and_ the actual constant.)
15941 For a 32-bit target, CONST_INT values are loaded and shifted
15942 entirely within `low' and can be stored in one TOC entry. */
15944 /* It would be easy to make this work, but it doesn't now. */
15945 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15947 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15949 #if HOST_BITS_PER_WIDE_INT == 32
15950 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15951 POINTER_SIZE, &low, &high, 0);
15954 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15955 high = (HOST_WIDE_INT) low >> 32;
15962 if (TARGET_MINIMAL_TOC)
15963 fputs (DOUBLE_INT_ASM_OP, file);
15965 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15966 (long) high & 0xffffffff, (long) low & 0xffffffff);
15967 fprintf (file, "0x%lx%08lx\n",
15968 (long) high & 0xffffffff, (long) low & 0xffffffff);
15973 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15975 if (TARGET_MINIMAL_TOC)
15976 fputs ("\t.long ", file);
15978 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15979 (long) high & 0xffffffff, (long) low & 0xffffffff);
15980 fprintf (file, "0x%lx,0x%lx\n",
15981 (long) high & 0xffffffff, (long) low & 0xffffffff);
15985 if (TARGET_MINIMAL_TOC)
15986 fputs ("\t.long ", file);
15988 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15989 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15995 if (GET_CODE (x) == CONST)
15997 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15999 base = XEXP (XEXP (x, 0), 0);
16000 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16003 switch (GET_CODE (base))
16006 name = XSTR (base, 0);
16010 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16011 CODE_LABEL_NUMBER (XEXP (base, 0)));
16015 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16019 gcc_unreachable ();
16022 real_name = (*targetm.strip_name_encoding) (name);
16023 if (TARGET_MINIMAL_TOC)
16024 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16027 fprintf (file, "\t.tc %s", real_name);
16030 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16032 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16034 fputs ("[TC],", file);
16037 /* Currently C++ toc references to vtables can be emitted before it
16038 is decided whether the vtable is public or private. If this is
16039 the case, then the linker will eventually complain that there is
16040 a TOC reference to an unknown section. Thus, for vtables only,
16041 we emit the TOC reference to reference the symbol and not the
16043 if (VTABLE_NAME_P (name))
16045 RS6000_OUTPUT_BASENAME (file, name);
16047 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16048 else if (offset > 0)
16049 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16052 output_addr_const (file, x);
16056 /* Output an assembler pseudo-op to write an ASCII string of N characters
16057 starting at P to FILE.
16059 On the RS/6000, we have to do this using the .byte operation and
16060 write out special characters outside the quoted string.
16061 Also, the assembler is broken; very long strings are truncated,
16062 so we must artificially break them up early. */
16065 output_ascii (FILE *file, const char *p, int n)
16068 int i, count_string;
16069 const char *for_string = "\t.byte \"";
16070 const char *for_decimal = "\t.byte ";
16071 const char *to_close = NULL;
16074 for (i = 0; i < n; i++)
16077 if (c >= ' ' && c < 0177)
16080 fputs (for_string, file);
16083 /* Write two quotes to get one. */
16091 for_decimal = "\"\n\t.byte ";
16095 if (count_string >= 512)
16097 fputs (to_close, file);
16099 for_string = "\t.byte \"";
16100 for_decimal = "\t.byte ";
16108 fputs (for_decimal, file);
16109 fprintf (file, "%d", c);
16111 for_string = "\n\t.byte \"";
16112 for_decimal = ", ";
16118 /* Now close the string if we have written one. Then end the line. */
16120 fputs (to_close, file);
16123 /* Generate a unique section name for FILENAME for a section type
16124 represented by SECTION_DESC. Output goes into BUF.
16126 SECTION_DESC can be any string, as long as it is different for each
16127 possible section type.
16129 We name the section in the same manner as xlc. The name begins with an
16130 underscore followed by the filename (after stripping any leading directory
16131 names) with the last period replaced by the string SECTION_DESC. If
16132 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16136 rs6000_gen_section_name (char **buf, const char *filename,
16137 const char *section_desc)
16139 const char *q, *after_last_slash, *last_period = 0;
16143 after_last_slash = filename;
16144 for (q = filename; *q; q++)
16147 after_last_slash = q + 1;
16148 else if (*q == '.')
16152 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16153 *buf = (char *) xmalloc (len);
16158 for (q = after_last_slash; *q; q++)
16160 if (q == last_period)
16162 strcpy (p, section_desc);
16163 p += strlen (section_desc);
16167 else if (ISALNUM (*q))
16171 if (last_period == 0)
16172 strcpy (p, section_desc);
16177 /* Emit profile function. */
16180 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16182 /* Non-standard profiling for kernels, which just saves LR then calls
16183 _mcount without worrying about arg saves. The idea is to change
16184 the function prologue as little as possible as it isn't easy to
16185 account for arg save/restore code added just for _mcount. */
16186 if (TARGET_PROFILE_KERNEL)
16189 if (DEFAULT_ABI == ABI_AIX)
16191 #ifndef NO_PROFILE_COUNTERS
16192 # define NO_PROFILE_COUNTERS 0
16194 if (NO_PROFILE_COUNTERS)
16195 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16199 const char *label_name;
16202 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16203 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16204 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16206 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16210 else if (DEFAULT_ABI == ABI_DARWIN)
16212 const char *mcount_name = RS6000_MCOUNT;
16213 int caller_addr_regno = LINK_REGISTER_REGNUM;
16215 /* Be conservative and always set this, at least for now. */
16216 current_function_uses_pic_offset_table = 1;
16219 /* For PIC code, set up a stub and collect the caller's address
16220 from r0, which is where the prologue puts it. */
16221 if (MACHOPIC_INDIRECT
16222 && current_function_uses_pic_offset_table)
16223 caller_addr_regno = 0;
16225 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16227 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16231 /* Write function profiler code. */
16234 output_function_profiler (FILE *file, int labelno)
16238 switch (DEFAULT_ABI)
16241 gcc_unreachable ();
16246 warning (0, "no profiling of 64-bit code for this ABI");
16249 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16250 fprintf (file, "\tmflr %s\n", reg_names[0]);
16251 if (NO_PROFILE_COUNTERS)
16253 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16254 reg_names[0], reg_names[1]);
16256 else if (TARGET_SECURE_PLT && flag_pic)
16258 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16259 reg_names[0], reg_names[1]);
16260 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16261 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16262 reg_names[12], reg_names[12]);
16263 assemble_name (file, buf);
16264 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16265 assemble_name (file, buf);
16266 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16268 else if (flag_pic == 1)
16270 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16271 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16272 reg_names[0], reg_names[1]);
16273 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16274 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16275 assemble_name (file, buf);
16276 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16278 else if (flag_pic > 1)
16280 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16281 reg_names[0], reg_names[1]);
16282 /* Now, we need to get the address of the label. */
16283 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16284 assemble_name (file, buf);
16285 fputs ("-.\n1:", file);
16286 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16287 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16288 reg_names[0], reg_names[11]);
16289 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16290 reg_names[0], reg_names[0], reg_names[11]);
16294 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16295 assemble_name (file, buf);
16296 fputs ("@ha\n", file);
16297 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16298 reg_names[0], reg_names[1]);
16299 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16300 assemble_name (file, buf);
16301 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16304 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16305 fprintf (file, "\tbl %s%s\n",
16306 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16311 if (!TARGET_PROFILE_KERNEL)
16313 /* Don't do anything, done in output_profile_hook (). */
16317 gcc_assert (!TARGET_32BIT);
16319 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16320 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16322 if (cfun->static_chain_decl != NULL)
16324 asm_fprintf (file, "\tstd %s,24(%s)\n",
16325 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16326 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16327 asm_fprintf (file, "\tld %s,24(%s)\n",
16328 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16331 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16338 /* Power4 load update and store update instructions are cracked into a
16339 load or store and an integer insn which are executed in the same cycle.
16340 Branches have their own dispatch slot which does not count against the
16341 GCC issue rate, but it changes the program flow so there are no other
16342 instructions to issue in this cycle. */
16345 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16346 int verbose ATTRIBUTE_UNUSED,
16347 rtx insn, int more)
16349 if (GET_CODE (PATTERN (insn)) == USE
16350 || GET_CODE (PATTERN (insn)) == CLOBBER)
16353 if (rs6000_sched_groups)
16355 if (is_microcoded_insn (insn))
16357 else if (is_cracked_insn (insn))
16358 return more > 2 ? more - 2 : 0;
16364 /* Adjust the cost of a scheduling dependency. Return the new cost of
16365 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16368 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16370 if (! recog_memoized (insn))
16373 if (REG_NOTE_KIND (link) != 0)
16376 if (REG_NOTE_KIND (link) == 0)
16378 /* Data dependency; DEP_INSN writes a register that INSN reads
16379 some cycles later. */
16381 /* Separate a load from a narrower, dependent store. */
16382 if (rs6000_sched_groups
16383 && GET_CODE (PATTERN (insn)) == SET
16384 && GET_CODE (PATTERN (dep_insn)) == SET
16385 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16386 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16387 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16388 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16391 switch (get_attr_type (insn))
16394 /* Tell the first scheduling pass about the latency between
16395 a mtctr and bctr (and mtlr and br/blr). The first
16396 scheduling pass will not know about this latency since
16397 the mtctr instruction, which has the latency associated
16398 to it, will be generated by reload. */
16399 return TARGET_POWER ? 5 : 4;
16401 /* Leave some extra cycles between a compare and its
16402 dependent branch, to inhibit expensive mispredicts. */
16403 if ((rs6000_cpu_attr == CPU_PPC603
16404 || rs6000_cpu_attr == CPU_PPC604
16405 || rs6000_cpu_attr == CPU_PPC604E
16406 || rs6000_cpu_attr == CPU_PPC620
16407 || rs6000_cpu_attr == CPU_PPC630
16408 || rs6000_cpu_attr == CPU_PPC750
16409 || rs6000_cpu_attr == CPU_PPC7400
16410 || rs6000_cpu_attr == CPU_PPC7450
16411 || rs6000_cpu_attr == CPU_POWER4
16412 || rs6000_cpu_attr == CPU_POWER5)
16413 && recog_memoized (dep_insn)
16414 && (INSN_CODE (dep_insn) >= 0)
16415 && (get_attr_type (dep_insn) == TYPE_CMP
16416 || get_attr_type (dep_insn) == TYPE_COMPARE
16417 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16418 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16419 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16420 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16421 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16422 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16427 /* Fall out to return default cost. */
16433 /* The function returns a true if INSN is microcoded.
16434 Return false otherwise. */
16437 is_microcoded_insn (rtx insn)
16439 if (!insn || !INSN_P (insn)
16440 || GET_CODE (PATTERN (insn)) == USE
16441 || GET_CODE (PATTERN (insn)) == CLOBBER)
16444 if (rs6000_sched_groups)
16446 enum attr_type type = get_attr_type (insn);
16447 if (type == TYPE_LOAD_EXT_U
16448 || type == TYPE_LOAD_EXT_UX
16449 || type == TYPE_LOAD_UX
16450 || type == TYPE_STORE_UX
16451 || type == TYPE_MFCR)
16458 /* The function returns a nonzero value if INSN can be scheduled only
16459 as the first insn in a dispatch group ("dispatch-slot restricted").
16460 In this case, the returned value indicates how many dispatch slots
16461 the insn occupies (at the beginning of the group).
16462 Return 0 otherwise. */
16465 is_dispatch_slot_restricted (rtx insn)
16467 enum attr_type type;
16469 if (!rs6000_sched_groups)
16473 || insn == NULL_RTX
16474 || GET_CODE (insn) == NOTE
16475 || GET_CODE (PATTERN (insn)) == USE
16476 || GET_CODE (PATTERN (insn)) == CLOBBER)
16479 type = get_attr_type (insn);
16486 case TYPE_DELAYED_CR:
16487 case TYPE_CR_LOGICAL:
16500 if (rs6000_cpu == PROCESSOR_POWER5
16501 && is_cracked_insn (insn))
16507 /* The function returns true if INSN is cracked into 2 instructions
16508 by the processor (and therefore occupies 2 issue slots). */
16511 is_cracked_insn (rtx insn)
16513 if (!insn || !INSN_P (insn)
16514 || GET_CODE (PATTERN (insn)) == USE
16515 || GET_CODE (PATTERN (insn)) == CLOBBER)
16518 if (rs6000_sched_groups)
16520 enum attr_type type = get_attr_type (insn);
16521 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16522 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16523 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16524 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16525 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16526 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16527 || type == TYPE_IDIV || type == TYPE_LDIV
16528 || type == TYPE_INSERT_WORD)
16535 /* The function returns true if INSN can be issued only from
16536 the branch slot. */
16539 is_branch_slot_insn (rtx insn)
16541 if (!insn || !INSN_P (insn)
16542 || GET_CODE (PATTERN (insn)) == USE
16543 || GET_CODE (PATTERN (insn)) == CLOBBER)
16546 if (rs6000_sched_groups)
16548 enum attr_type type = get_attr_type (insn);
16549 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16557 /* A C statement (sans semicolon) to update the integer scheduling
16558 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16559 INSN earlier, reduce the priority to execute INSN later. Do not
16560 define this macro if you do not need to adjust the scheduling
16561 priorities of insns. */
16564 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16566 /* On machines (like the 750) which have asymmetric integer units,
16567 where one integer unit can do multiply and divides and the other
16568 can't, reduce the priority of multiply/divide so it is scheduled
16569 before other integer operations. */
16572 if (! INSN_P (insn))
16575 if (GET_CODE (PATTERN (insn)) == USE)
16578 switch (rs6000_cpu_attr) {
16580 switch (get_attr_type (insn))
16587 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16588 priority, priority);
16589 if (priority >= 0 && priority < 0x01000000)
16596 if (is_dispatch_slot_restricted (insn)
16597 && reload_completed
16598 && current_sched_info->sched_max_insns_priority
16599 && rs6000_sched_restricted_insns_priority)
16602 /* Prioritize insns that can be dispatched only in the first
16604 if (rs6000_sched_restricted_insns_priority == 1)
16605 /* Attach highest priority to insn. This means that in
16606 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16607 precede 'priority' (critical path) considerations. */
16608 return current_sched_info->sched_max_insns_priority;
16609 else if (rs6000_sched_restricted_insns_priority == 2)
16610 /* Increase priority of insn by a minimal amount. This means that in
16611 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16612 considerations precede dispatch-slot restriction considerations. */
16613 return (priority + 1);
16619 /* Return how many instructions the machine can issue per cycle. */
16622 rs6000_issue_rate (void)
16624 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16625 if (!reload_completed)
16628 switch (rs6000_cpu_attr) {
16629 case CPU_RIOS1: /* ? */
16631 case CPU_PPC601: /* ? */
16654 /* Return how many instructions to look ahead for better insn
16658 rs6000_use_sched_lookahead (void)
16660 if (rs6000_cpu_attr == CPU_PPC8540)
16665 /* Determine is PAT refers to memory. */
16668 is_mem_ref (rtx pat)
16674 if (GET_CODE (pat) == MEM)
16677 /* Recursively process the pattern. */
16678 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16680 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16683 ret |= is_mem_ref (XEXP (pat, i));
16684 else if (fmt[i] == 'E')
16685 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16686 ret |= is_mem_ref (XVECEXP (pat, i, j));
16692 /* Determine if PAT is a PATTERN of a load insn. */
16695 is_load_insn1 (rtx pat)
16697 if (!pat || pat == NULL_RTX)
16700 if (GET_CODE (pat) == SET)
16701 return is_mem_ref (SET_SRC (pat));
16703 if (GET_CODE (pat) == PARALLEL)
16707 for (i = 0; i < XVECLEN (pat, 0); i++)
16708 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16715 /* Determine if INSN loads from memory. */
16718 is_load_insn (rtx insn)
16720 if (!insn || !INSN_P (insn))
16723 if (GET_CODE (insn) == CALL_INSN)
16726 return is_load_insn1 (PATTERN (insn));
16729 /* Determine if PAT is a PATTERN of a store insn. */
16732 is_store_insn1 (rtx pat)
16734 if (!pat || pat == NULL_RTX)
16737 if (GET_CODE (pat) == SET)
16738 return is_mem_ref (SET_DEST (pat));
16740 if (GET_CODE (pat) == PARALLEL)
16744 for (i = 0; i < XVECLEN (pat, 0); i++)
16745 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16752 /* Determine if INSN stores to memory. */
16755 is_store_insn (rtx insn)
16757 if (!insn || !INSN_P (insn))
16760 return is_store_insn1 (PATTERN (insn));
16763 /* Returns whether the dependence between INSN and NEXT is considered
16764 costly by the given target. */
16767 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16770 /* If the flag is not enabled - no dependence is considered costly;
16771 allow all dependent insns in the same group.
16772 This is the most aggressive option. */
16773 if (rs6000_sched_costly_dep == no_dep_costly)
16776 /* If the flag is set to 1 - a dependence is always considered costly;
16777 do not allow dependent instructions in the same group.
16778 This is the most conservative option. */
16779 if (rs6000_sched_costly_dep == all_deps_costly)
16782 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16783 && is_load_insn (next)
16784 && is_store_insn (insn))
16785 /* Prevent load after store in the same group. */
16788 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16789 && is_load_insn (next)
16790 && is_store_insn (insn)
16791 && (!link || (int) REG_NOTE_KIND (link) == 0))
16792 /* Prevent load after store in the same group if it is a true
16796 /* The flag is set to X; dependences with latency >= X are considered costly,
16797 and will not be scheduled in the same group. */
16798 if (rs6000_sched_costly_dep <= max_dep_latency
16799 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16805 /* Return the next insn after INSN that is found before TAIL is reached,
16806 skipping any "non-active" insns - insns that will not actually occupy
16807 an issue slot. Return NULL_RTX if such an insn is not found. */
16810 get_next_active_insn (rtx insn, rtx tail)
16812 if (insn == NULL_RTX || insn == tail)
16817 insn = NEXT_INSN (insn);
16818 if (insn == NULL_RTX || insn == tail)
16823 || (NONJUMP_INSN_P (insn)
16824 && GET_CODE (PATTERN (insn)) != USE
16825 && GET_CODE (PATTERN (insn)) != CLOBBER
16826 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16832 /* Return whether the presence of INSN causes a dispatch group termination
16833 of group WHICH_GROUP.
16835 If WHICH_GROUP == current_group, this function will return true if INSN
16836 causes the termination of the current group (i.e, the dispatch group to
16837 which INSN belongs). This means that INSN will be the last insn in the
16838 group it belongs to.
16840 If WHICH_GROUP == previous_group, this function will return true if INSN
16841 causes the termination of the previous group (i.e, the dispatch group that
16842 precedes the group to which INSN belongs). This means that INSN will be
16843 the first insn in the group it belongs to). */
16846 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16848 enum attr_type type;
16853 type = get_attr_type (insn);
16855 if (is_microcoded_insn (insn))
16858 if (which_group == current_group)
16860 if (is_branch_slot_insn (insn))
16864 else if (which_group == previous_group)
16866 if (is_dispatch_slot_restricted (insn))
16874 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16875 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16878 is_costly_group (rtx *group_insns, rtx next_insn)
16883 int issue_rate = rs6000_issue_rate ();
16885 for (i = 0; i < issue_rate; i++)
16887 rtx insn = group_insns[i];
16890 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16892 rtx next = XEXP (link, 0);
16893 if (next == next_insn)
16895 cost = insn_cost (insn, link, next_insn);
16896 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16905 /* Utility of the function redefine_groups.
16906 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16907 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16908 to keep it "far" (in a separate group) from GROUP_INSNS, following
16909 one of the following schemes, depending on the value of the flag
16910 -minsert_sched_nops = X:
16911 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16912 in order to force NEXT_INSN into a separate group.
16913 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16914 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16915 insertion (has a group just ended, how many vacant issue slots remain in the
16916 last group, and how many dispatch groups were encountered so far). */
16919 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16920 rtx next_insn, bool *group_end, int can_issue_more,
16925 int issue_rate = rs6000_issue_rate ();
16926 bool end = *group_end;
16929 if (next_insn == NULL_RTX)
16930 return can_issue_more;
16932 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16933 return can_issue_more;
16935 force = is_costly_group (group_insns, next_insn);
16937 return can_issue_more;
16939 if (sched_verbose > 6)
16940 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16941 *group_count ,can_issue_more);
16943 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16946 can_issue_more = 0;
16948 /* Since only a branch can be issued in the last issue_slot, it is
16949 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16950 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16951 in this case the last nop will start a new group and the branch
16952 will be forced to the new group. */
16953 if (can_issue_more && !is_branch_slot_insn (next_insn))
16956 while (can_issue_more > 0)
16959 emit_insn_before (nop, next_insn);
16967 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16969 int n_nops = rs6000_sched_insert_nops;
16971 /* Nops can't be issued from the branch slot, so the effective
16972 issue_rate for nops is 'issue_rate - 1'. */
16973 if (can_issue_more == 0)
16974 can_issue_more = issue_rate;
16976 if (can_issue_more == 0)
16978 can_issue_more = issue_rate - 1;
16981 for (i = 0; i < issue_rate; i++)
16983 group_insns[i] = 0;
16990 emit_insn_before (nop, next_insn);
16991 if (can_issue_more == issue_rate - 1) /* new group begins */
16994 if (can_issue_more == 0)
16996 can_issue_more = issue_rate - 1;
16999 for (i = 0; i < issue_rate; i++)
17001 group_insns[i] = 0;
17007 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
17010 /* Is next_insn going to start a new group? */
17013 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17014 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17015 || (can_issue_more < issue_rate &&
17016 insn_terminates_group_p (next_insn, previous_group)));
17017 if (*group_end && end)
17020 if (sched_verbose > 6)
17021 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
17022 *group_count, can_issue_more);
17023 return can_issue_more;
17026 return can_issue_more;
17029 /* This function tries to synch the dispatch groups that the compiler "sees"
17030 with the dispatch groups that the processor dispatcher is expected to
17031 form in practice. It tries to achieve this synchronization by forcing the
17032 estimated processor grouping on the compiler (as opposed to the function
17033 'pad_goups' which tries to force the scheduler's grouping on the processor).
17035 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
17036 examines the (estimated) dispatch groups that will be formed by the processor
17037 dispatcher. It marks these group boundaries to reflect the estimated
17038 processor grouping, overriding the grouping that the scheduler had marked.
17039 Depending on the value of the flag '-minsert-sched-nops' this function can
17040 force certain insns into separate groups or force a certain distance between
17041 them by inserting nops, for example, if there exists a "costly dependence"
17044 The function estimates the group boundaries that the processor will form as
17045 follows: It keeps track of how many vacant issue slots are available after
17046 each insn. A subsequent insn will start a new group if one of the following
17048 - no more vacant issue slots remain in the current dispatch group.
17049 - only the last issue slot, which is the branch slot, is vacant, but the next
17050 insn is not a branch.
17051 - only the last 2 or less issue slots, including the branch slot, are vacant,
17052 which means that a cracked insn (which occupies two issue slots) can't be
17053 issued in this group.
17054 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17055 start a new group. */
17058 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17060 rtx insn, next_insn;
17062 int can_issue_more;
17065 int group_count = 0;
17069 issue_rate = rs6000_issue_rate ();
17070 group_insns = alloca (issue_rate * sizeof (rtx));
17071 for (i = 0; i < issue_rate; i++)
17073 group_insns[i] = 0;
17075 can_issue_more = issue_rate;
17077 insn = get_next_active_insn (prev_head_insn, tail);
17080 while (insn != NULL_RTX)
17082 slot = (issue_rate - can_issue_more);
17083 group_insns[slot] = insn;
17085 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17086 if (insn_terminates_group_p (insn, current_group))
17087 can_issue_more = 0;
17089 next_insn = get_next_active_insn (insn, tail);
17090 if (next_insn == NULL_RTX)
17091 return group_count + 1;
17093 /* Is next_insn going to start a new group? */
17095 = (can_issue_more == 0
17096 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17097 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17098 || (can_issue_more < issue_rate &&
17099 insn_terminates_group_p (next_insn, previous_group)));
17101 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17102 next_insn, &group_end, can_issue_more,
17108 can_issue_more = 0;
17109 for (i = 0; i < issue_rate; i++)
17111 group_insns[i] = 0;
17115 if (GET_MODE (next_insn) == TImode && can_issue_more)
17116 PUT_MODE (next_insn, VOIDmode);
17117 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17118 PUT_MODE (next_insn, TImode);
17121 if (can_issue_more == 0)
17122 can_issue_more = issue_rate;
17125 return group_count;
17128 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17129 dispatch group boundaries that the scheduler had marked. Pad with nops
17130 any dispatch groups which have vacant issue slots, in order to force the
17131 scheduler's grouping on the processor dispatcher. The function
17132 returns the number of dispatch groups found. */
17135 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17137 rtx insn, next_insn;
17140 int can_issue_more;
17142 int group_count = 0;
17144 /* Initialize issue_rate. */
17145 issue_rate = rs6000_issue_rate ();
17146 can_issue_more = issue_rate;
17148 insn = get_next_active_insn (prev_head_insn, tail);
17149 next_insn = get_next_active_insn (insn, tail);
17151 while (insn != NULL_RTX)
17154 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17156 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17158 if (next_insn == NULL_RTX)
17163 /* If the scheduler had marked group termination at this location
17164 (between insn and next_indn), and neither insn nor next_insn will
17165 force group termination, pad the group with nops to force group
17168 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17169 && !insn_terminates_group_p (insn, current_group)
17170 && !insn_terminates_group_p (next_insn, previous_group))
17172 if (!is_branch_slot_insn (next_insn))
17175 while (can_issue_more)
17178 emit_insn_before (nop, next_insn);
17183 can_issue_more = issue_rate;
17188 next_insn = get_next_active_insn (insn, tail);
17191 return group_count;
17194 /* The following function is called at the end of scheduling BB.
17195 After reload, it inserts nops at insn group bundling. */
17198 rs6000_sched_finish (FILE *dump, int sched_verbose)
17203 fprintf (dump, "=== Finishing schedule.\n");
17205 if (reload_completed && rs6000_sched_groups)
17207 if (rs6000_sched_insert_nops == sched_finish_none)
17210 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17211 n_groups = pad_groups (dump, sched_verbose,
17212 current_sched_info->prev_head,
17213 current_sched_info->next_tail);
17215 n_groups = redefine_groups (dump, sched_verbose,
17216 current_sched_info->prev_head,
17217 current_sched_info->next_tail);
17219 if (sched_verbose >= 6)
17221 fprintf (dump, "ngroups = %d\n", n_groups);
17222 print_rtl (dump, current_sched_info->prev_head);
17223 fprintf (dump, "Done finish_sched\n");
17228 /* Length in units of the trampoline for entering a nested function. */
17231 rs6000_trampoline_size (void)
17235 switch (DEFAULT_ABI)
17238 gcc_unreachable ();
17241 ret = (TARGET_32BIT) ? 12 : 24;
17246 ret = (TARGET_32BIT) ? 40 : 48;
17253 /* Emit RTL insns to initialize the variable parts of a trampoline.
17254 FNADDR is an RTX for the address of the function's pure code.
17255 CXT is an RTX for the static chain value for the function. */
17258 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17260 enum machine_mode pmode = Pmode;
17261 int regsize = (TARGET_32BIT) ? 4 : 8;
17262 rtx ctx_reg = force_reg (pmode, cxt);
17264 switch (DEFAULT_ABI)
17267 gcc_unreachable ();
17269 /* Macros to shorten the code expansions below. */
17270 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17271 #define MEM_PLUS(addr,offset) \
17272 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17274 /* Under AIX, just build the 3 word function descriptor */
17277 rtx fn_reg = gen_reg_rtx (pmode);
17278 rtx toc_reg = gen_reg_rtx (pmode);
17279 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17280 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17281 emit_move_insn (MEM_DEREF (addr), fn_reg);
17282 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17283 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17287 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17290 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17291 FALSE, VOIDmode, 4,
17293 GEN_INT (rs6000_trampoline_size ()), SImode,
17303 /* Table of valid machine attributes. */
17305 const struct attribute_spec rs6000_attribute_table[] =
17307 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17308 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17309 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17310 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17311 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17312 SUBTARGET_ATTRIBUTE_TABLE,
17314 { NULL, 0, 0, false, false, false, NULL }
17317 /* Handle the "altivec" attribute. The attribute may have
17318 arguments as follows:
17320 __attribute__((altivec(vector__)))
17321 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17322 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17324 and may appear more than once (e.g., 'vector bool char') in a
17325 given declaration. */
17328 rs6000_handle_altivec_attribute (tree *node,
17329 tree name ATTRIBUTE_UNUSED,
17331 int flags ATTRIBUTE_UNUSED,
17332 bool *no_add_attrs)
17334 tree type = *node, result = NULL_TREE;
17335 enum machine_mode mode;
17338 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17339 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17340 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17343 while (POINTER_TYPE_P (type)
17344 || TREE_CODE (type) == FUNCTION_TYPE
17345 || TREE_CODE (type) == METHOD_TYPE
17346 || TREE_CODE (type) == ARRAY_TYPE)
17347 type = TREE_TYPE (type);
17349 mode = TYPE_MODE (type);
17351 /* Check for invalid AltiVec type qualifiers. */
17352 if (type == long_unsigned_type_node || type == long_integer_type_node)
17355 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17356 else if (rs6000_warn_altivec_long)
17357 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17359 else if (type == long_long_unsigned_type_node
17360 || type == long_long_integer_type_node)
17361 error ("use of %<long long%> in AltiVec types is invalid");
17362 else if (type == double_type_node)
17363 error ("use of %<double%> in AltiVec types is invalid");
17364 else if (type == long_double_type_node)
17365 error ("use of %<long double%> in AltiVec types is invalid");
17366 else if (type == boolean_type_node)
17367 error ("use of boolean types in AltiVec types is invalid");
17368 else if (TREE_CODE (type) == COMPLEX_TYPE)
17369 error ("use of %<complex%> in AltiVec types is invalid");
17370 else if (DECIMAL_FLOAT_MODE_P (mode))
17371 error ("use of decimal floating point types in AltiVec types is invalid");
17373 switch (altivec_type)
17376 unsigned_p = TYPE_UNSIGNED (type);
17380 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17383 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17386 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17388 case SFmode: result = V4SF_type_node; break;
17389 /* If the user says 'vector int bool', we may be handed the 'bool'
17390 attribute _before_ the 'vector' attribute, and so select the
17391 proper type in the 'b' case below. */
17392 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17400 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17401 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17402 case QImode: case V16QImode: result = bool_V16QI_type_node;
17409 case V8HImode: result = pixel_V8HI_type_node;
17415 if (result && result != type && TYPE_READONLY (type))
17416 result = build_qualified_type (result, TYPE_QUAL_CONST);
17418 *no_add_attrs = true; /* No need to hang on to the attribute. */
17421 *node = reconstruct_complex_type (*node, result);
17426 /* AltiVec defines four built-in scalar types that serve as vector
17427 elements; we must teach the compiler how to mangle them. */
17429 static const char *
17430 rs6000_mangle_fundamental_type (tree type)
17432 if (type == bool_char_type_node) return "U6__boolc";
17433 if (type == bool_short_type_node) return "U6__bools";
17434 if (type == pixel_type_node) return "u7__pixel";
17435 if (type == bool_int_type_node) return "U6__booli";
17437 /* Mangle IBM extended float long double as `g' (__float128) on
17438 powerpc*-linux where long-double-64 previously was the default. */
17439 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
17441 && TARGET_LONG_DOUBLE_128
17442 && !TARGET_IEEEQUAD)
17445 /* For all other types, use normal C++ mangling. */
17449 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17450 struct attribute_spec.handler. */
17453 rs6000_handle_longcall_attribute (tree *node, tree name,
17454 tree args ATTRIBUTE_UNUSED,
17455 int flags ATTRIBUTE_UNUSED,
17456 bool *no_add_attrs)
17458 if (TREE_CODE (*node) != FUNCTION_TYPE
17459 && TREE_CODE (*node) != FIELD_DECL
17460 && TREE_CODE (*node) != TYPE_DECL)
17462 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17463 IDENTIFIER_POINTER (name));
17464 *no_add_attrs = true;
17470 /* Set longcall attributes on all functions declared when
17471 rs6000_default_long_calls is true. */
17473 rs6000_set_default_type_attributes (tree type)
17475 if (rs6000_default_long_calls
17476 && (TREE_CODE (type) == FUNCTION_TYPE
17477 || TREE_CODE (type) == METHOD_TYPE))
17478 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17480 TYPE_ATTRIBUTES (type));
17483 /* Return a reference suitable for calling a function with the
17484 longcall attribute. */
17487 rs6000_longcall_ref (rtx call_ref)
17489 const char *call_name;
17492 if (GET_CODE (call_ref) != SYMBOL_REF)
17495 /* System V adds '.' to the internal name, so skip them. */
17496 call_name = XSTR (call_ref, 0);
17497 if (*call_name == '.')
17499 while (*call_name == '.')
17502 node = get_identifier (call_name);
17503 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17506 return force_reg (Pmode, call_ref);
17509 #ifdef USING_ELFOS_H
17511 /* A get_unnamed_section callback, used for switching to toc_section. */
17514 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17516 if (DEFAULT_ABI == ABI_AIX
17517 && TARGET_MINIMAL_TOC
17518 && !TARGET_RELOCATABLE)
17520 if (!toc_initialized)
17522 toc_initialized = 1;
17523 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17524 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17525 fprintf (asm_out_file, "\t.tc ");
17526 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17527 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17528 fprintf (asm_out_file, "\n");
17530 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17531 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17532 fprintf (asm_out_file, " = .+32768\n");
17535 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17537 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17538 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17541 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17542 if (!toc_initialized)
17544 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17545 fprintf (asm_out_file, " = .+32768\n");
17546 toc_initialized = 1;
17551 /* Implement TARGET_ASM_INIT_SECTIONS. */
17554 rs6000_elf_asm_init_sections (void)
17557 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17560 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17561 SDATA2_SECTION_ASM_OP);
17564 /* Implement TARGET_SELECT_RTX_SECTION. */
17567 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17568 unsigned HOST_WIDE_INT align)
17570 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17571 return toc_section;
17573 return default_elf_select_rtx_section (mode, x, align);
17576 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17579 rs6000_elf_select_section (tree decl, int reloc,
17580 unsigned HOST_WIDE_INT align)
17582 /* Pretend that we're always building for a shared library when
17583 ABI_AIX, because otherwise we end up with dynamic relocations
17584 in read-only sections. This happens for function pointers,
17585 references to vtables in typeinfo, and probably other cases. */
17586 return default_elf_select_section_1 (decl, reloc, align,
17587 flag_pic || DEFAULT_ABI == ABI_AIX);
17590 /* A C statement to build up a unique section name, expressed as a
17591 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17592 RELOC indicates whether the initial value of EXP requires
17593 link-time relocations. If you do not define this macro, GCC will use
17594 the symbol name prefixed by `.' as the section name. Note - this
17595 macro can now be called for uninitialized data items as well as
17596 initialized data and functions. */
17599 rs6000_elf_unique_section (tree decl, int reloc)
17601 /* As above, pretend that we're always building for a shared library
17602 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17603 default_unique_section_1 (decl, reloc,
17604 flag_pic || DEFAULT_ABI == ABI_AIX);
17607 /* For a SYMBOL_REF, set generic flags and then perform some
17608 target-specific processing.
17610 When the AIX ABI is requested on a non-AIX system, replace the
17611 function name with the real name (with a leading .) rather than the
17612 function descriptor name. This saves a lot of overriding code to
17613 read the prefixes. */
17616 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17618 default_encode_section_info (decl, rtl, first);
17621 && TREE_CODE (decl) == FUNCTION_DECL
17623 && DEFAULT_ABI == ABI_AIX)
17625 rtx sym_ref = XEXP (rtl, 0);
17626 size_t len = strlen (XSTR (sym_ref, 0));
17627 char *str = alloca (len + 2);
17629 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17630 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17635 rs6000_elf_in_small_data_p (tree decl)
17637 if (rs6000_sdata == SDATA_NONE)
17640 /* We want to merge strings, so we never consider them small data. */
17641 if (TREE_CODE (decl) == STRING_CST)
17644 /* Functions are never in the small data area. */
17645 if (TREE_CODE (decl) == FUNCTION_DECL)
17648 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17650 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17651 if (strcmp (section, ".sdata") == 0
17652 || strcmp (section, ".sdata2") == 0
17653 || strcmp (section, ".sbss") == 0
17654 || strcmp (section, ".sbss2") == 0
17655 || strcmp (section, ".PPC.EMB.sdata0") == 0
17656 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17661 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17664 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17665 /* If it's not public, and we're not going to reference it there,
17666 there's no need to put it in the small data section. */
17667 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17674 #endif /* USING_ELFOS_H */
17676 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
17679 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
17681 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
17684 /* Return a REG that occurs in ADDR with coefficient 1.
17685 ADDR can be effectively incremented by incrementing REG.
17687 r0 is special and we must not select it as an address
17688 register by this routine since our caller will try to
17689 increment the returned register via an "la" instruction. */
17692 find_addr_reg (rtx addr)
17694 while (GET_CODE (addr) == PLUS)
17696 if (GET_CODE (XEXP (addr, 0)) == REG
17697 && REGNO (XEXP (addr, 0)) != 0)
17698 addr = XEXP (addr, 0);
17699 else if (GET_CODE (XEXP (addr, 1)) == REG
17700 && REGNO (XEXP (addr, 1)) != 0)
17701 addr = XEXP (addr, 1);
17702 else if (CONSTANT_P (XEXP (addr, 0)))
17703 addr = XEXP (addr, 1);
17704 else if (CONSTANT_P (XEXP (addr, 1)))
17705 addr = XEXP (addr, 0);
17707 gcc_unreachable ();
17709 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17714 rs6000_fatal_bad_address (rtx op)
17716 fatal_insn ("bad address", op);
17721 static tree branch_island_list = 0;
17723 /* Remember to generate a branch island for far calls to the given
17727 add_compiler_branch_island (tree label_name, tree function_name,
17730 tree branch_island = build_tree_list (function_name, label_name);
17731 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17732 TREE_CHAIN (branch_island) = branch_island_list;
17733 branch_island_list = branch_island;
17736 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17737 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17738 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17739 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17741 /* Generate far-jump branch islands for everything on the
17742 branch_island_list. Invoked immediately after the last instruction
17743 of the epilogue has been emitted; the branch-islands must be
17744 appended to, and contiguous with, the function body. Mach-O stubs
17745 are generated in machopic_output_stub(). */
17748 macho_branch_islands (void)
17751 tree branch_island;
17753 for (branch_island = branch_island_list;
17755 branch_island = TREE_CHAIN (branch_island))
17757 const char *label =
17758 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17760 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17761 char name_buf[512];
17762 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17763 if (name[0] == '*' || name[0] == '&')
17764 strcpy (name_buf, name+1);
17768 strcpy (name_buf+1, name);
17770 strcpy (tmp_buf, "\n");
17771 strcat (tmp_buf, label);
17772 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17773 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17774 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17775 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17778 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17779 strcat (tmp_buf, label);
17780 strcat (tmp_buf, "_pic\n");
17781 strcat (tmp_buf, label);
17782 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17784 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17785 strcat (tmp_buf, name_buf);
17786 strcat (tmp_buf, " - ");
17787 strcat (tmp_buf, label);
17788 strcat (tmp_buf, "_pic)\n");
17790 strcat (tmp_buf, "\tmtlr r0\n");
17792 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17793 strcat (tmp_buf, name_buf);
17794 strcat (tmp_buf, " - ");
17795 strcat (tmp_buf, label);
17796 strcat (tmp_buf, "_pic)\n");
17798 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17802 strcat (tmp_buf, ":\nlis r12,hi16(");
17803 strcat (tmp_buf, name_buf);
17804 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17805 strcat (tmp_buf, name_buf);
17806 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17808 output_asm_insn (tmp_buf, 0);
17809 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17810 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17811 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17812 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17815 branch_island_list = 0;
17818 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17819 already there or not. */
17822 no_previous_def (tree function_name)
17824 tree branch_island;
17825 for (branch_island = branch_island_list;
17827 branch_island = TREE_CHAIN (branch_island))
17828 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17833 /* GET_PREV_LABEL gets the label name from the previous definition of
17837 get_prev_label (tree function_name)
17839 tree branch_island;
17840 for (branch_island = branch_island_list;
17842 branch_island = TREE_CHAIN (branch_island))
17843 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17844 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17848 /* INSN is either a function call or a millicode call. It may have an
17849 unconditional jump in its delay slot.
17851 CALL_DEST is the routine we are calling. */
17854 output_call (rtx insn, rtx *operands, int dest_operand_number,
17855 int cookie_operand_number)
17857 static char buf[256];
17858 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17859 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17862 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17864 if (no_previous_def (funname))
17866 int line_number = 0;
17867 rtx label_rtx = gen_label_rtx ();
17868 char *label_buf, temp_buf[256];
17869 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17870 CODE_LABEL_NUMBER (label_rtx));
17871 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17872 labelname = get_identifier (label_buf);
17873 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17875 line_number = NOTE_LINE_NUMBER (insn);
17876 add_compiler_branch_island (labelname, funname, line_number);
17879 labelname = get_prev_label (funname);
17881 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17882 instruction will reach 'foo', otherwise link as 'bl L42'".
17883 "L42" should be a 'branch island', that will do a far jump to
17884 'foo'. Branch islands are generated in
17885 macho_branch_islands(). */
17886 sprintf (buf, "jbsr %%z%d,%.246s",
17887 dest_operand_number, IDENTIFIER_POINTER (labelname));
17890 sprintf (buf, "bl %%z%d", dest_operand_number);
17894 /* Generate PIC and indirect symbol stubs. */
17897 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17899 unsigned int length;
17900 char *symbol_name, *lazy_ptr_name;
17901 char *local_label_0;
17902 static int label = 0;
17904 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17905 symb = (*targetm.strip_name_encoding) (symb);
17908 length = strlen (symb);
17909 symbol_name = alloca (length + 32);
17910 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17912 lazy_ptr_name = alloca (length + 32);
17913 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17916 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
17918 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
17922 fprintf (file, "\t.align 5\n");
17924 fprintf (file, "%s:\n", stub);
17925 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17928 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17929 sprintf (local_label_0, "\"L%011d$spb\"", label);
17931 fprintf (file, "\tmflr r0\n");
17932 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17933 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17934 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17935 lazy_ptr_name, local_label_0);
17936 fprintf (file, "\tmtlr r0\n");
17937 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17938 (TARGET_64BIT ? "ldu" : "lwzu"),
17939 lazy_ptr_name, local_label_0);
17940 fprintf (file, "\tmtctr r12\n");
17941 fprintf (file, "\tbctr\n");
17945 fprintf (file, "\t.align 4\n");
17947 fprintf (file, "%s:\n", stub);
17948 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17950 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17951 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17952 (TARGET_64BIT ? "ldu" : "lwzu"),
17954 fprintf (file, "\tmtctr r12\n");
17955 fprintf (file, "\tbctr\n");
17958 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
17959 fprintf (file, "%s:\n", lazy_ptr_name);
17960 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17961 fprintf (file, "%sdyld_stub_binding_helper\n",
17962 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17965 /* Legitimize PIC addresses. If the address is already
17966 position-independent, we return ORIG. Newly generated
17967 position-independent addresses go into a reg. This is REG if non
17968 zero, otherwise we allocate register(s) as necessary. */
17970 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17973 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17978 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17979 reg = gen_reg_rtx (Pmode);
17981 if (GET_CODE (orig) == CONST)
17985 if (GET_CODE (XEXP (orig, 0)) == PLUS
17986 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17989 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17991 /* Use a different reg for the intermediate value, as
17992 it will be marked UNCHANGING. */
17993 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17994 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17997 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
18000 if (GET_CODE (offset) == CONST_INT)
18002 if (SMALL_INT (offset))
18003 return plus_constant (base, INTVAL (offset));
18004 else if (! reload_in_progress && ! reload_completed)
18005 offset = force_reg (Pmode, offset);
18008 rtx mem = force_const_mem (Pmode, orig);
18009 return machopic_legitimize_pic_address (mem, Pmode, reg);
18012 return gen_rtx_PLUS (Pmode, base, offset);
18015 /* Fall back on generic machopic code. */
18016 return machopic_legitimize_pic_address (orig, mode, reg);
18019 /* Output a .machine directive for the Darwin assembler, and call
18020 the generic start_file routine. */
18023 rs6000_darwin_file_start (void)
18025 static const struct
18031 { "ppc64", "ppc64", MASK_64BIT },
18032 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
18033 { "power4", "ppc970", 0 },
18034 { "G5", "ppc970", 0 },
18035 { "7450", "ppc7450", 0 },
18036 { "7400", "ppc7400", MASK_ALTIVEC },
18037 { "G4", "ppc7400", 0 },
18038 { "750", "ppc750", 0 },
18039 { "740", "ppc750", 0 },
18040 { "G3", "ppc750", 0 },
18041 { "604e", "ppc604e", 0 },
18042 { "604", "ppc604", 0 },
18043 { "603e", "ppc603", 0 },
18044 { "603", "ppc603", 0 },
18045 { "601", "ppc601", 0 },
18046 { NULL, "ppc", 0 } };
18047 const char *cpu_id = "";
18050 rs6000_file_start ();
18051 darwin_file_start ();
18053 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
18054 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
18055 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
18056 && rs6000_select[i].string[0] != '\0')
18057 cpu_id = rs6000_select[i].string;
18059 /* Look through the mapping array. Pick the first name that either
18060 matches the argument, has a bit set in IF_SET that is also set
18061 in the target flags, or has a NULL name. */
18064 while (mapping[i].arg != NULL
18065 && strcmp (mapping[i].arg, cpu_id) != 0
18066 && (mapping[i].if_set & target_flags) == 0)
18069 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18072 #endif /* TARGET_MACHO */
18075 static unsigned int
18076 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
18078 return default_section_type_flags_1 (decl, name, reloc,
18079 flag_pic || DEFAULT_ABI == ABI_AIX);
18082 /* Record an element in the table of global constructors. SYMBOL is
18083 a SYMBOL_REF of the function to be called; PRIORITY is a number
18084 between 0 and MAX_INIT_PRIORITY.
18086 This differs from default_named_section_asm_out_constructor in
18087 that we have special handling for -mrelocatable. */
18090 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18092 const char *section = ".ctors";
18095 if (priority != DEFAULT_INIT_PRIORITY)
18097 sprintf (buf, ".ctors.%.5u",
18098 /* Invert the numbering so the linker puts us in the proper
18099 order; constructors are run from right to left, and the
18100 linker sorts in increasing order. */
18101 MAX_INIT_PRIORITY - priority);
18105 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18106 assemble_align (POINTER_SIZE);
18108 if (TARGET_RELOCATABLE)
18110 fputs ("\t.long (", asm_out_file);
18111 output_addr_const (asm_out_file, symbol);
18112 fputs (")@fixup\n", asm_out_file);
18115 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18119 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18121 const char *section = ".dtors";
18124 if (priority != DEFAULT_INIT_PRIORITY)
18126 sprintf (buf, ".dtors.%.5u",
18127 /* Invert the numbering so the linker puts us in the proper
18128 order; constructors are run from right to left, and the
18129 linker sorts in increasing order. */
18130 MAX_INIT_PRIORITY - priority);
18134 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18135 assemble_align (POINTER_SIZE);
18137 if (TARGET_RELOCATABLE)
18139 fputs ("\t.long (", asm_out_file);
18140 output_addr_const (asm_out_file, symbol);
18141 fputs (")@fixup\n", asm_out_file);
18144 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18148 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18152 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18153 ASM_OUTPUT_LABEL (file, name);
18154 fputs (DOUBLE_INT_ASM_OP, file);
18155 rs6000_output_function_entry (file, name);
18156 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18159 fputs ("\t.size\t", file);
18160 assemble_name (file, name);
18161 fputs (",24\n\t.type\t.", file);
18162 assemble_name (file, name);
18163 fputs (",@function\n", file);
18164 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18166 fputs ("\t.globl\t.", file);
18167 assemble_name (file, name);
18172 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18173 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18174 rs6000_output_function_entry (file, name);
18175 fputs (":\n", file);
18179 if (TARGET_RELOCATABLE
18180 && !TARGET_SECURE_PLT
18181 && (get_pool_size () != 0 || current_function_profile)
18186 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18188 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18189 fprintf (file, "\t.long ");
18190 assemble_name (file, buf);
18192 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18193 assemble_name (file, buf);
18197 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18198 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18200 if (DEFAULT_ABI == ABI_AIX)
18202 const char *desc_name, *orig_name;
18204 orig_name = (*targetm.strip_name_encoding) (name);
18205 desc_name = orig_name;
18206 while (*desc_name == '.')
18209 if (TREE_PUBLIC (decl))
18210 fprintf (file, "\t.globl %s\n", desc_name);
18212 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18213 fprintf (file, "%s:\n", desc_name);
18214 fprintf (file, "\t.long %s\n", orig_name);
18215 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18216 if (DEFAULT_ABI == ABI_AIX)
18217 fputs ("\t.long 0\n", file);
18218 fprintf (file, "\t.previous\n");
18220 ASM_OUTPUT_LABEL (file, name);
18224 rs6000_elf_end_indicate_exec_stack (void)
18227 file_end_indicate_exec_stack ();
18233 rs6000_xcoff_asm_output_anchor (rtx symbol)
18237 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
18238 SYMBOL_REF_BLOCK_OFFSET (symbol));
18239 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
18243 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18245 fputs (GLOBAL_ASM_OP, stream);
18246 RS6000_OUTPUT_BASENAME (stream, name);
18247 putc ('\n', stream);
18250 /* A get_unnamed_decl callback, used for read-only sections. PTR
18251 points to the section string variable. */
18254 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18256 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18257 *(const char *const *) directive);
18260 /* Likewise for read-write sections. */
18263 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18265 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18266 *(const char *const *) directive);
18269 /* A get_unnamed_section callback, used for switching to toc_section. */
18272 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18274 if (TARGET_MINIMAL_TOC)
18276 /* toc_section is always selected at least once from
18277 rs6000_xcoff_file_start, so this is guaranteed to
18278 always be defined once and only once in each file. */
18279 if (!toc_initialized)
18281 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18282 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18283 toc_initialized = 1;
18285 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18286 (TARGET_32BIT ? "" : ",3"));
18289 fputs ("\t.toc\n", asm_out_file);
18292 /* Implement TARGET_ASM_INIT_SECTIONS. */
18295 rs6000_xcoff_asm_init_sections (void)
18297 read_only_data_section
18298 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18299 &xcoff_read_only_section_name);
18301 private_data_section
18302 = get_unnamed_section (SECTION_WRITE,
18303 rs6000_xcoff_output_readwrite_section_asm_op,
18304 &xcoff_private_data_section_name);
18306 read_only_private_data_section
18307 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18308 &xcoff_private_data_section_name);
18311 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18313 readonly_data_section = read_only_data_section;
18314 exception_section = data_section;
18318 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18319 tree decl ATTRIBUTE_UNUSED)
18322 static const char * const suffix[3] = { "PR", "RO", "RW" };
18324 if (flags & SECTION_CODE)
18326 else if (flags & SECTION_WRITE)
18331 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18332 (flags & SECTION_CODE) ? "." : "",
18333 name, suffix[smclass], flags & SECTION_ENTSIZE);
18337 rs6000_xcoff_select_section (tree decl, int reloc,
18338 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18340 if (decl_readonly_section_1 (decl, reloc, 1))
18342 if (TREE_PUBLIC (decl))
18343 return read_only_data_section;
18345 return read_only_private_data_section;
18349 if (TREE_PUBLIC (decl))
18350 return data_section;
18352 return private_data_section;
18357 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18361 /* Use select_section for private and uninitialized data. */
18362 if (!TREE_PUBLIC (decl)
18363 || DECL_COMMON (decl)
18364 || DECL_INITIAL (decl) == NULL_TREE
18365 || DECL_INITIAL (decl) == error_mark_node
18366 || (flag_zero_initialized_in_bss
18367 && initializer_zerop (DECL_INITIAL (decl))))
18370 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18371 name = (*targetm.strip_name_encoding) (name);
18372 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18375 /* Select section for constant in constant pool.
18377 On RS/6000, all constants are in the private read-only data area.
18378 However, if this is being placed in the TOC it must be output as a
18382 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18383 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18385 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18386 return toc_section;
18388 return read_only_private_data_section;
18391 /* Remove any trailing [DS] or the like from the symbol name. */
18393 static const char *
18394 rs6000_xcoff_strip_name_encoding (const char *name)
18399 len = strlen (name);
18400 if (name[len - 1] == ']')
18401 return ggc_alloc_string (name, len - 4);
18406 /* Section attributes. AIX is always PIC. */
18408 static unsigned int
18409 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18411 unsigned int align;
18412 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18414 /* Align to at least UNIT size. */
18415 if (flags & SECTION_CODE)
18416 align = MIN_UNITS_PER_WORD;
18418 /* Increase alignment of large objects if not already stricter. */
18419 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18420 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18421 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18423 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18426 /* Output at beginning of assembler file.
18428 Initialize the section names for the RS/6000 at this point.
18430 Specify filename, including full path, to assembler.
18432 We want to go into the TOC section so at least one .toc will be emitted.
18433 Also, in order to output proper .bs/.es pairs, we need at least one static
18434 [RW] section emitted.
18436 Finally, declare mcount when profiling to make the assembler happy. */
18439 rs6000_xcoff_file_start (void)
18441 rs6000_gen_section_name (&xcoff_bss_section_name,
18442 main_input_filename, ".bss_");
18443 rs6000_gen_section_name (&xcoff_private_data_section_name,
18444 main_input_filename, ".rw_");
18445 rs6000_gen_section_name (&xcoff_read_only_section_name,
18446 main_input_filename, ".ro_");
18448 fputs ("\t.file\t", asm_out_file);
18449 output_quoted_string (asm_out_file, main_input_filename);
18450 fputc ('\n', asm_out_file);
18451 if (write_symbols != NO_DEBUG)
18452 switch_to_section (private_data_section);
18453 switch_to_section (text_section);
18455 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18456 rs6000_file_start ();
18459 /* Output at end of assembler file.
18460 On the RS/6000, referencing data should automatically pull in text. */
18463 rs6000_xcoff_file_end (void)
18465 switch_to_section (text_section);
18466 fputs ("_section_.text:\n", asm_out_file);
18467 switch_to_section (data_section);
18468 fputs (TARGET_32BIT
18469 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18472 #endif /* TARGET_XCOFF */
18474 /* Compute a (partial) cost for rtx X. Return true if the complete
18475 cost has been computed, and false if subexpressions should be
18476 scanned. In either case, *TOTAL contains the cost result. */
18479 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18481 enum machine_mode mode = GET_MODE (x);
18485 /* On the RS/6000, if it is valid in the insn, it is free. */
18487 if (((outer_code == SET
18488 || outer_code == PLUS
18489 || outer_code == MINUS)
18490 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18491 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18492 || (outer_code == AND
18493 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18494 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18495 mode == SImode ? 'L' : 'J'))
18496 || mask_operand (x, mode)
18498 && mask64_operand (x, DImode))))
18499 || ((outer_code == IOR || outer_code == XOR)
18500 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18501 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18502 mode == SImode ? 'L' : 'J'))))
18503 || outer_code == ASHIFT
18504 || outer_code == ASHIFTRT
18505 || outer_code == LSHIFTRT
18506 || outer_code == ROTATE
18507 || outer_code == ROTATERT
18508 || outer_code == ZERO_EXTRACT
18509 || (outer_code == MULT
18510 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18511 || ((outer_code == DIV || outer_code == UDIV
18512 || outer_code == MOD || outer_code == UMOD)
18513 && exact_log2 (INTVAL (x)) >= 0)
18514 || (outer_code == COMPARE
18515 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18516 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18517 || (outer_code == EQ
18518 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18519 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18520 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18521 mode == SImode ? 'L' : 'J'))))
18522 || (outer_code == GTU
18523 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18524 || (outer_code == LTU
18525 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18530 else if ((outer_code == PLUS
18531 && reg_or_add_cint_operand (x, VOIDmode))
18532 || (outer_code == MINUS
18533 && reg_or_sub_cint_operand (x, VOIDmode))
18534 || ((outer_code == SET
18535 || outer_code == IOR
18536 || outer_code == XOR)
18538 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18540 *total = COSTS_N_INSNS (1);
18547 && ((outer_code == AND
18548 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18549 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18550 || mask_operand (x, DImode)
18551 || mask64_operand (x, DImode)))
18552 || ((outer_code == IOR || outer_code == XOR)
18553 && CONST_DOUBLE_HIGH (x) == 0
18554 && (CONST_DOUBLE_LOW (x)
18555 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18560 else if (mode == DImode
18561 && (outer_code == SET
18562 || outer_code == IOR
18563 || outer_code == XOR)
18564 && CONST_DOUBLE_HIGH (x) == 0)
18566 *total = COSTS_N_INSNS (1);
18575 /* When optimizing for size, MEM should be slightly more expensive
18576 than generating address, e.g., (plus (reg) (const)).
18577 L1 cache latency is about two instructions. */
18578 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18586 if (mode == DFmode)
18588 if (GET_CODE (XEXP (x, 0)) == MULT)
18590 /* FNMA accounted in outer NEG. */
18591 if (outer_code == NEG)
18592 *total = rs6000_cost->dmul - rs6000_cost->fp;
18594 *total = rs6000_cost->dmul;
18597 *total = rs6000_cost->fp;
18599 else if (mode == SFmode)
18601 /* FNMA accounted in outer NEG. */
18602 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18605 *total = rs6000_cost->fp;
18608 *total = COSTS_N_INSNS (1);
18612 if (mode == DFmode)
18614 if (GET_CODE (XEXP (x, 0)) == MULT)
18616 /* FNMA accounted in outer NEG. */
18617 if (outer_code == NEG)
18620 *total = rs6000_cost->dmul;
18623 *total = rs6000_cost->fp;
18625 else if (mode == SFmode)
18627 /* FNMA accounted in outer NEG. */
18628 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18631 *total = rs6000_cost->fp;
18634 *total = COSTS_N_INSNS (1);
18638 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18639 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18641 if (INTVAL (XEXP (x, 1)) >= -256
18642 && INTVAL (XEXP (x, 1)) <= 255)
18643 *total = rs6000_cost->mulsi_const9;
18645 *total = rs6000_cost->mulsi_const;
18647 /* FMA accounted in outer PLUS/MINUS. */
18648 else if ((mode == DFmode || mode == SFmode)
18649 && (outer_code == PLUS || outer_code == MINUS))
18651 else if (mode == DFmode)
18652 *total = rs6000_cost->dmul;
18653 else if (mode == SFmode)
18654 *total = rs6000_cost->fp;
18655 else if (mode == DImode)
18656 *total = rs6000_cost->muldi;
18658 *total = rs6000_cost->mulsi;
18663 if (FLOAT_MODE_P (mode))
18665 *total = mode == DFmode ? rs6000_cost->ddiv
18666 : rs6000_cost->sdiv;
18673 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18674 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18676 if (code == DIV || code == MOD)
18678 *total = COSTS_N_INSNS (2);
18681 *total = COSTS_N_INSNS (1);
18685 if (GET_MODE (XEXP (x, 1)) == DImode)
18686 *total = rs6000_cost->divdi;
18688 *total = rs6000_cost->divsi;
18690 /* Add in shift and subtract for MOD. */
18691 if (code == MOD || code == UMOD)
18692 *total += COSTS_N_INSNS (2);
18696 *total = COSTS_N_INSNS (4);
18700 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18711 *total = COSTS_N_INSNS (1);
18719 /* Handle mul_highpart. */
18720 if (outer_code == TRUNCATE
18721 && GET_CODE (XEXP (x, 0)) == MULT)
18723 if (mode == DImode)
18724 *total = rs6000_cost->muldi;
18726 *total = rs6000_cost->mulsi;
18729 else if (outer_code == AND)
18732 *total = COSTS_N_INSNS (1);
18737 if (GET_CODE (XEXP (x, 0)) == MEM)
18740 *total = COSTS_N_INSNS (1);
18746 if (!FLOAT_MODE_P (mode))
18748 *total = COSTS_N_INSNS (1);
18754 case UNSIGNED_FLOAT:
18757 case FLOAT_TRUNCATE:
18758 *total = rs6000_cost->fp;
18762 if (mode == DFmode)
18765 *total = rs6000_cost->fp;
18769 switch (XINT (x, 1))
18772 *total = rs6000_cost->fp;
18784 *total = COSTS_N_INSNS (1);
18787 else if (FLOAT_MODE_P (mode)
18788 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18790 *total = rs6000_cost->fp;
18798 /* Carry bit requires mode == Pmode.
18799 NEG or PLUS already counted so only add one. */
18801 && (outer_code == NEG || outer_code == PLUS))
18803 *total = COSTS_N_INSNS (1);
18806 if (outer_code == SET)
18808 if (XEXP (x, 1) == const0_rtx)
18810 *total = COSTS_N_INSNS (2);
18813 else if (mode == Pmode)
18815 *total = COSTS_N_INSNS (3);
18824 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18826 *total = COSTS_N_INSNS (2);
18830 if (outer_code == COMPARE)
18844 /* A C expression returning the cost of moving data from a register of class
18845 CLASS1 to one of CLASS2. */
18848 rs6000_register_move_cost (enum machine_mode mode,
18849 enum reg_class from, enum reg_class to)
18851 /* Moves from/to GENERAL_REGS. */
18852 if (reg_classes_intersect_p (to, GENERAL_REGS)
18853 || reg_classes_intersect_p (from, GENERAL_REGS))
18855 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18858 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18859 return (rs6000_memory_move_cost (mode, from, 0)
18860 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18862 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18864 else if (from == CR_REGS)
18868 /* A move will cost one instruction per GPR moved. */
18869 return 2 * hard_regno_nregs[0][mode];
18872 /* Moving between two similar registers is just one instruction. */
18873 else if (reg_classes_intersect_p (to, from))
18874 return mode == TFmode ? 4 : 2;
18876 /* Everything else has to go through GENERAL_REGS. */
18878 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18879 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18882 /* A C expressions returning the cost of moving data of MODE from a register to
18886 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18887 int in ATTRIBUTE_UNUSED)
18889 if (reg_classes_intersect_p (class, GENERAL_REGS))
18890 return 4 * hard_regno_nregs[0][mode];
18891 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18892 return 4 * hard_regno_nregs[32][mode];
18893 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18894 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18896 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18899 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18900 Assumes no trapping math and finite arguments. */
18903 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18905 rtx x0, e0, e1, y1, u0, v0, one;
18907 x0 = gen_reg_rtx (SFmode);
18908 e0 = gen_reg_rtx (SFmode);
18909 e1 = gen_reg_rtx (SFmode);
18910 y1 = gen_reg_rtx (SFmode);
18911 u0 = gen_reg_rtx (SFmode);
18912 v0 = gen_reg_rtx (SFmode);
18913 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18915 /* x0 = 1./d estimate */
18916 emit_insn (gen_rtx_SET (VOIDmode, x0,
18917 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18919 /* e0 = 1. - d * x0 */
18920 emit_insn (gen_rtx_SET (VOIDmode, e0,
18921 gen_rtx_MINUS (SFmode, one,
18922 gen_rtx_MULT (SFmode, d, x0))));
18923 /* e1 = e0 + e0 * e0 */
18924 emit_insn (gen_rtx_SET (VOIDmode, e1,
18925 gen_rtx_PLUS (SFmode,
18926 gen_rtx_MULT (SFmode, e0, e0), e0)));
18927 /* y1 = x0 + e1 * x0 */
18928 emit_insn (gen_rtx_SET (VOIDmode, y1,
18929 gen_rtx_PLUS (SFmode,
18930 gen_rtx_MULT (SFmode, e1, x0), x0)));
18932 emit_insn (gen_rtx_SET (VOIDmode, u0,
18933 gen_rtx_MULT (SFmode, n, y1)));
18934 /* v0 = n - d * u0 */
18935 emit_insn (gen_rtx_SET (VOIDmode, v0,
18936 gen_rtx_MINUS (SFmode, n,
18937 gen_rtx_MULT (SFmode, d, u0))));
18938 /* res = u0 + v0 * y1 */
18939 emit_insn (gen_rtx_SET (VOIDmode, res,
18940 gen_rtx_PLUS (SFmode,
18941 gen_rtx_MULT (SFmode, v0, y1), u0)));
18944 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18945 Assumes no trapping math and finite arguments. */
18948 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18950 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18952 x0 = gen_reg_rtx (DFmode);
18953 e0 = gen_reg_rtx (DFmode);
18954 e1 = gen_reg_rtx (DFmode);
18955 e2 = gen_reg_rtx (DFmode);
18956 y1 = gen_reg_rtx (DFmode);
18957 y2 = gen_reg_rtx (DFmode);
18958 y3 = gen_reg_rtx (DFmode);
18959 u0 = gen_reg_rtx (DFmode);
18960 v0 = gen_reg_rtx (DFmode);
18961 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18963 /* x0 = 1./d estimate */
18964 emit_insn (gen_rtx_SET (VOIDmode, x0,
18965 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18967 /* e0 = 1. - d * x0 */
18968 emit_insn (gen_rtx_SET (VOIDmode, e0,
18969 gen_rtx_MINUS (DFmode, one,
18970 gen_rtx_MULT (SFmode, d, x0))));
18971 /* y1 = x0 + e0 * x0 */
18972 emit_insn (gen_rtx_SET (VOIDmode, y1,
18973 gen_rtx_PLUS (DFmode,
18974 gen_rtx_MULT (DFmode, e0, x0), x0)));
18976 emit_insn (gen_rtx_SET (VOIDmode, e1,
18977 gen_rtx_MULT (DFmode, e0, e0)));
18978 /* y2 = y1 + e1 * y1 */
18979 emit_insn (gen_rtx_SET (VOIDmode, y2,
18980 gen_rtx_PLUS (DFmode,
18981 gen_rtx_MULT (DFmode, e1, y1), y1)));
18983 emit_insn (gen_rtx_SET (VOIDmode, e2,
18984 gen_rtx_MULT (DFmode, e1, e1)));
18985 /* y3 = y2 + e2 * y2 */
18986 emit_insn (gen_rtx_SET (VOIDmode, y3,
18987 gen_rtx_PLUS (DFmode,
18988 gen_rtx_MULT (DFmode, e2, y2), y2)));
18990 emit_insn (gen_rtx_SET (VOIDmode, u0,
18991 gen_rtx_MULT (DFmode, n, y3)));
18992 /* v0 = n - d * u0 */
18993 emit_insn (gen_rtx_SET (VOIDmode, v0,
18994 gen_rtx_MINUS (DFmode, n,
18995 gen_rtx_MULT (DFmode, d, u0))));
18996 /* res = u0 + v0 * y3 */
18997 emit_insn (gen_rtx_SET (VOIDmode, res,
18998 gen_rtx_PLUS (DFmode,
18999 gen_rtx_MULT (DFmode, v0, y3), u0)));
19002 /* Return an RTX representing where to find the function value of a
19003 function returning MODE. */
19005 rs6000_complex_function_value (enum machine_mode mode)
19007 unsigned int regno;
19009 enum machine_mode inner = GET_MODE_INNER (mode);
19010 unsigned int inner_bytes = GET_MODE_SIZE (inner);
19012 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
19013 regno = FP_ARG_RETURN;
19016 regno = GP_ARG_RETURN;
19018 /* 32-bit is OK since it'll go in r3/r4. */
19019 if (TARGET_32BIT && inner_bytes >= 4)
19020 return gen_rtx_REG (mode, regno);
19023 if (inner_bytes >= 8)
19024 return gen_rtx_REG (mode, regno);
19026 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
19028 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
19029 GEN_INT (inner_bytes));
19030 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
19033 /* Define how to find the value returned by a function.
19034 VALTYPE is the data type of the value (as a tree).
19035 If the precise function being called is known, FUNC is its FUNCTION_DECL;
19036 otherwise, FUNC is 0.
19038 On the SPE, both FPs and vectors are returned in r3.
19040 On RS/6000 an integer value is in r3 and a floating-point value is in
19041 fp1, unless -msoft-float. */
19044 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
19046 enum machine_mode mode;
19047 unsigned int regno;
19049 /* Special handling for structs in darwin64. */
19050 if (rs6000_darwin64_abi
19051 && TYPE_MODE (valtype) == BLKmode
19052 && TREE_CODE (valtype) == RECORD_TYPE
19053 && int_size_in_bytes (valtype) > 0)
19055 CUMULATIVE_ARGS valcum;
19059 valcum.fregno = FP_ARG_MIN_REG;
19060 valcum.vregno = ALTIVEC_ARG_MIN_REG;
19061 /* Do a trial code generation as if this were going to be passed as
19062 an argument; if any part goes in memory, we return NULL. */
19063 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
19066 /* Otherwise fall through to standard ABI rules. */
19069 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
19071 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19072 return gen_rtx_PARALLEL (DImode,
19074 gen_rtx_EXPR_LIST (VOIDmode,
19075 gen_rtx_REG (SImode, GP_ARG_RETURN),
19077 gen_rtx_EXPR_LIST (VOIDmode,
19078 gen_rtx_REG (SImode,
19079 GP_ARG_RETURN + 1),
19082 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19084 return gen_rtx_PARALLEL (DCmode,
19086 gen_rtx_EXPR_LIST (VOIDmode,
19087 gen_rtx_REG (SImode, GP_ARG_RETURN),
19089 gen_rtx_EXPR_LIST (VOIDmode,
19090 gen_rtx_REG (SImode,
19091 GP_ARG_RETURN + 1),
19093 gen_rtx_EXPR_LIST (VOIDmode,
19094 gen_rtx_REG (SImode,
19095 GP_ARG_RETURN + 2),
19097 gen_rtx_EXPR_LIST (VOIDmode,
19098 gen_rtx_REG (SImode,
19099 GP_ARG_RETURN + 3),
19103 if ((INTEGRAL_TYPE_P (valtype)
19104 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
19105 || POINTER_TYPE_P (valtype))
19106 mode = TARGET_32BIT ? SImode : DImode;
19108 mode = TYPE_MODE (valtype);
19110 if (DECIMAL_FLOAT_MODE_P (mode))
19111 regno = GP_ARG_RETURN;
19112 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19113 regno = FP_ARG_RETURN;
19114 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19115 && targetm.calls.split_complex_arg)
19116 return rs6000_complex_function_value (mode);
19117 else if (TREE_CODE (valtype) == VECTOR_TYPE
19118 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19119 && ALTIVEC_VECTOR_MODE (mode))
19120 regno = ALTIVEC_ARG_RETURN;
19121 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19122 && (mode == DFmode || mode == DCmode))
19123 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19125 regno = GP_ARG_RETURN;
19127 return gen_rtx_REG (mode, regno);
19130 /* Define how to find the value returned by a library function
19131 assuming the value has mode MODE. */
19133 rs6000_libcall_value (enum machine_mode mode)
19135 unsigned int regno;
19137 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19139 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19140 return gen_rtx_PARALLEL (DImode,
19142 gen_rtx_EXPR_LIST (VOIDmode,
19143 gen_rtx_REG (SImode, GP_ARG_RETURN),
19145 gen_rtx_EXPR_LIST (VOIDmode,
19146 gen_rtx_REG (SImode,
19147 GP_ARG_RETURN + 1),
19151 if (DECIMAL_FLOAT_MODE_P (mode))
19152 regno = GP_ARG_RETURN;
19153 else if (SCALAR_FLOAT_MODE_P (mode)
19154 && TARGET_HARD_FLOAT && TARGET_FPRS)
19155 regno = FP_ARG_RETURN;
19156 else if (ALTIVEC_VECTOR_MODE (mode)
19157 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19158 regno = ALTIVEC_ARG_RETURN;
19159 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19160 return rs6000_complex_function_value (mode);
19161 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19162 && (mode == DFmode || mode == DCmode))
19163 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19165 regno = GP_ARG_RETURN;
19167 return gen_rtx_REG (mode, regno);
19170 /* Define the offset between two registers, FROM to be eliminated and its
19171 replacement TO, at the start of a routine. */
19173 rs6000_initial_elimination_offset (int from, int to)
19175 rs6000_stack_t *info = rs6000_stack_info ();
19176 HOST_WIDE_INT offset;
19178 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19179 offset = info->push_p ? 0 : -info->total_size;
19180 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19182 offset = info->push_p ? 0 : -info->total_size;
19183 if (FRAME_GROWS_DOWNWARD)
19184 offset += info->fixed_size + info->vars_size + info->parm_size;
19186 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19187 offset = FRAME_GROWS_DOWNWARD
19188 ? info->fixed_size + info->vars_size + info->parm_size
19190 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19191 offset = info->total_size;
19192 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19193 offset = info->push_p ? info->total_size : 0;
19194 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19197 gcc_unreachable ();
19202 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19205 rs6000_is_opaque_type (tree type)
19207 return (type == opaque_V2SI_type_node
19208 || type == opaque_V2SF_type_node
19209 || type == opaque_p_V2SI_type_node
19210 || type == opaque_V4SI_type_node);
19214 rs6000_dwarf_register_span (rtx reg)
19219 && (SPE_VECTOR_MODE (GET_MODE (reg))
19220 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19225 regno = REGNO (reg);
19227 /* The duality of the SPE register size wreaks all kinds of havoc.
19228 This is a way of distinguishing r0 in 32-bits from r0 in
19231 gen_rtx_PARALLEL (VOIDmode,
19234 gen_rtx_REG (SImode, regno + 1200),
19235 gen_rtx_REG (SImode, regno))
19237 gen_rtx_REG (SImode, regno),
19238 gen_rtx_REG (SImode, regno + 1200)));
19241 /* Map internal gcc register numbers to DWARF2 register numbers. */
19244 rs6000_dbx_register_number (unsigned int regno)
19246 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19248 if (regno == MQ_REGNO)
19250 if (regno == LINK_REGISTER_REGNUM)
19252 if (regno == COUNT_REGISTER_REGNUM)
19254 if (CR_REGNO_P (regno))
19255 return regno - CR0_REGNO + 86;
19256 if (regno == XER_REGNO)
19258 if (ALTIVEC_REGNO_P (regno))
19259 return regno - FIRST_ALTIVEC_REGNO + 1124;
19260 if (regno == VRSAVE_REGNO)
19262 if (regno == VSCR_REGNO)
19264 if (regno == SPE_ACC_REGNO)
19266 if (regno == SPEFSCR_REGNO)
19268 /* SPE high reg number. We get these values of regno from
19269 rs6000_dwarf_register_span. */
19270 gcc_assert (regno >= 1200 && regno < 1232);
19274 /* target hook eh_return_filter_mode */
19275 static enum machine_mode
19276 rs6000_eh_return_filter_mode (void)
19278 return TARGET_32BIT ? SImode : word_mode;
19281 /* Target hook for scalar_mode_supported_p. */
19283 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19285 if (DECIMAL_FLOAT_MODE_P (mode))
19288 return default_scalar_mode_supported_p (mode);
19291 /* Target hook for vector_mode_supported_p. */
19293 rs6000_vector_mode_supported_p (enum machine_mode mode)
19296 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19299 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19306 /* Target hook for invalid_arg_for_unprototyped_fn. */
19307 static const char *
19308 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19310 return (!rs6000_darwin64_abi
19312 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19313 && (funcdecl == NULL_TREE
19314 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19315 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19316 ? N_("AltiVec argument passed to unprototyped function")
19320 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19321 setup by using __stack_chk_fail_local hidden function instead of
19322 calling __stack_chk_fail directly. Otherwise it is better to call
19323 __stack_chk_fail directly. */
19326 rs6000_stack_protect_fail (void)
19328 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19329 ? default_hidden_stack_protect_fail ()
19330 : default_external_stack_protect_fail ();
19333 #include "gt-rs6000.h"