1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
59 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
62 #include "gstab.h" /* for N_SLINE */
65 #ifndef TARGET_NO_PROTOTYPE
66 #define TARGET_NO_PROTOTYPE 0
69 #define min(A,B) ((A) < (B) ? (A) : (B))
70 #define max(A,B) ((A) > (B) ? (A) : (B))
72 /* Structure used to define the rs6000 stack */
73 typedef struct rs6000_stack {
74 int first_gp_reg_save; /* first callee saved GP register used */
75 int first_fp_reg_save; /* first callee saved FP register used */
76 int first_altivec_reg_save; /* first callee saved AltiVec register used */
77 int lr_save_p; /* true if the link reg needs to be saved */
78 int cr_save_p; /* true if the CR reg needs to be saved */
79 unsigned int vrsave_mask; /* mask of vec registers to save */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int varargs_save_offset; /* offset to save the varargs registers */
93 int ehrd_offset; /* offset to EH return data */
94 int reg_size; /* register size (4 or 8) */
95 HOST_WIDE_INT vars_size; /* variable save area size */
96 int parm_size; /* outgoing parameter size */
97 int save_size; /* save area size */
98 int fixed_size; /* fixed size of stack frame */
99 int gp_size; /* size of saved GP registers */
100 int fp_size; /* size of saved FP registers */
101 int altivec_size; /* size of saved AltiVec registers */
102 int cr_size; /* size to hold CR if not in save_size */
103 int vrsave_size; /* size to hold VRSAVE if not in save_size */
104 int altivec_padding_size; /* size of altivec alignment padding if
106 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
107 int spe_padding_size;
108 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
109 int spe_64bit_regs_used;
112 /* A C structure for machine-specific, per-function data.
113 This is added to the cfun structure. */
114 typedef struct machine_function GTY(())
116 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
117 int ra_needs_full_frame;
118 /* Some local-dynamic symbol. */
119 const char *some_ld_name;
120 /* Whether the instruction chain has been scanned already. */
121 int insn_chain_scanned_p;
122 /* Flags if __builtin_return_address (0) was used. */
124 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
125 varargs save area. */
126 HOST_WIDE_INT varargs_save_offset;
129 /* Target cpu type */
131 enum processor_type rs6000_cpu;
132 struct rs6000_cpu_select rs6000_select[3] =
134 /* switch name, tune arch */
135 { (const char *)0, "--with-cpu=", 1, 1 },
136 { (const char *)0, "-mcpu=", 1, 1 },
137 { (const char *)0, "-mtune=", 1, 0 },
140 /* Always emit branch hint bits. */
141 static GTY(()) bool rs6000_always_hint;
143 /* Schedule instructions for group formation. */
144 static GTY(()) bool rs6000_sched_groups;
146 /* Support for -msched-costly-dep option. */
147 const char *rs6000_sched_costly_dep_str;
148 enum rs6000_dependence_cost rs6000_sched_costly_dep;
150 /* Support for -minsert-sched-nops option. */
151 const char *rs6000_sched_insert_nops_str;
152 enum rs6000_nop_insertion rs6000_sched_insert_nops;
154 /* Support targetm.vectorize.builtin_mask_for_load. */
155 static GTY(()) tree altivec_builtin_mask_for_load;
157 /* Size of long double */
158 int rs6000_long_double_type_size;
160 /* Whether -mabi=altivec has appeared */
161 int rs6000_altivec_abi;
163 /* Nonzero if we want SPE ABI extensions. */
166 /* Nonzero if floating point operations are done in the GPRs. */
167 int rs6000_float_gprs = 0;
169 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
170 int rs6000_darwin64_abi;
172 /* Set to nonzero once AIX common-mode calls have been defined. */
173 static GTY(()) int common_mode_defined;
175 /* Save information from a "cmpxx" operation until the branch or scc is
177 rtx rs6000_compare_op0, rs6000_compare_op1;
178 int rs6000_compare_fp_p;
180 /* Label number of label created for -mrelocatable, to call to so we can
181 get the address of the GOT section */
182 int rs6000_pic_labelno;
185 /* Which abi to adhere to */
186 const char *rs6000_abi_name;
188 /* Semantics of the small data area */
189 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
191 /* Which small data model to use */
192 const char *rs6000_sdata_name = (char *)0;
194 /* Counter for labels which are to be placed in .fixup. */
195 int fixuplabelno = 0;
198 /* Bit size of immediate TLS offsets and string from which it is decoded. */
199 int rs6000_tls_size = 32;
200 const char *rs6000_tls_size_string;
202 /* ABI enumeration available for subtarget to use. */
203 enum rs6000_abi rs6000_current_abi;
205 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
209 const char *rs6000_debug_name;
210 int rs6000_debug_stack; /* debug stack applications */
211 int rs6000_debug_arg; /* debug argument handling */
213 /* Value is TRUE if register/mode pair is acceptable. */
214 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
216 /* Built in types. */
218 tree rs6000_builtin_types[RS6000_BTI_MAX];
219 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
221 const char *rs6000_traceback_name;
223 traceback_default = 0,
229 /* Flag to say the TOC is initialized */
231 char toc_label_name[10];
233 static GTY(()) section *read_only_data_section;
234 static GTY(()) section *private_data_section;
235 static GTY(()) section *read_only_private_data_section;
236 static GTY(()) section *sdata2_section;
237 static GTY(()) section *toc_section;
239 /* Control alignment for fields within structures. */
240 /* String from -malign-XXXXX. */
241 int rs6000_alignment_flags;
243 /* True for any options that were explicitly set. */
245 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
246 bool alignment; /* True if -malign- was used. */
247 bool abi; /* True if -mabi= was used. */
248 bool spe; /* True if -mspe= was used. */
249 bool float_gprs; /* True if -mfloat-gprs= was used. */
250 bool isel; /* True if -misel was used. */
251 bool long_double; /* True if -mlong-double- was used. */
252 } rs6000_explicit_options;
254 struct builtin_description
256 /* mask is not const because we're going to alter it below. This
257 nonsense will go away when we rewrite the -march infrastructure
258 to give us more target flag bits. */
260 const enum insn_code icode;
261 const char *const name;
262 const enum rs6000_builtins code;
265 /* Target cpu costs. */
267 struct processor_costs {
268 const int mulsi; /* cost of SImode multiplication. */
269 const int mulsi_const; /* cost of SImode multiplication by constant. */
270 const int mulsi_const9; /* cost of SImode mult by short constant. */
271 const int muldi; /* cost of DImode multiplication. */
272 const int divsi; /* cost of SImode division. */
273 const int divdi; /* cost of DImode division. */
274 const int fp; /* cost of simple SFmode and DFmode insns. */
275 const int dmul; /* cost of DFmode multiplication (and fmadd). */
276 const int sdiv; /* cost of SFmode division (fdivs). */
277 const int ddiv; /* cost of DFmode division (fdiv). */
280 const struct processor_costs *rs6000_cost;
282 /* Processor costs (relative to an add) */
284 /* Instruction size costs on 32bit processors. */
286 struct processor_costs size32_cost = {
287 COSTS_N_INSNS (1), /* mulsi */
288 COSTS_N_INSNS (1), /* mulsi_const */
289 COSTS_N_INSNS (1), /* mulsi_const9 */
290 COSTS_N_INSNS (1), /* muldi */
291 COSTS_N_INSNS (1), /* divsi */
292 COSTS_N_INSNS (1), /* divdi */
293 COSTS_N_INSNS (1), /* fp */
294 COSTS_N_INSNS (1), /* dmul */
295 COSTS_N_INSNS (1), /* sdiv */
296 COSTS_N_INSNS (1), /* ddiv */
299 /* Instruction size costs on 64bit processors. */
301 struct processor_costs size64_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction costs on RIOS1 processors. */
316 struct processor_costs rios1_cost = {
317 COSTS_N_INSNS (5), /* mulsi */
318 COSTS_N_INSNS (4), /* mulsi_const */
319 COSTS_N_INSNS (3), /* mulsi_const9 */
320 COSTS_N_INSNS (5), /* muldi */
321 COSTS_N_INSNS (19), /* divsi */
322 COSTS_N_INSNS (19), /* divdi */
323 COSTS_N_INSNS (2), /* fp */
324 COSTS_N_INSNS (2), /* dmul */
325 COSTS_N_INSNS (19), /* sdiv */
326 COSTS_N_INSNS (19), /* ddiv */
329 /* Instruction costs on RIOS2 processors. */
331 struct processor_costs rios2_cost = {
332 COSTS_N_INSNS (2), /* mulsi */
333 COSTS_N_INSNS (2), /* mulsi_const */
334 COSTS_N_INSNS (2), /* mulsi_const9 */
335 COSTS_N_INSNS (2), /* muldi */
336 COSTS_N_INSNS (13), /* divsi */
337 COSTS_N_INSNS (13), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (17), /* sdiv */
341 COSTS_N_INSNS (17), /* ddiv */
344 /* Instruction costs on RS64A processors. */
346 struct processor_costs rs64a_cost = {
347 COSTS_N_INSNS (20), /* mulsi */
348 COSTS_N_INSNS (12), /* mulsi_const */
349 COSTS_N_INSNS (8), /* mulsi_const9 */
350 COSTS_N_INSNS (34), /* muldi */
351 COSTS_N_INSNS (65), /* divsi */
352 COSTS_N_INSNS (67), /* divdi */
353 COSTS_N_INSNS (4), /* fp */
354 COSTS_N_INSNS (4), /* dmul */
355 COSTS_N_INSNS (31), /* sdiv */
356 COSTS_N_INSNS (31), /* ddiv */
359 /* Instruction costs on MPCCORE processors. */
361 struct processor_costs mpccore_cost = {
362 COSTS_N_INSNS (2), /* mulsi */
363 COSTS_N_INSNS (2), /* mulsi_const */
364 COSTS_N_INSNS (2), /* mulsi_const9 */
365 COSTS_N_INSNS (2), /* muldi */
366 COSTS_N_INSNS (6), /* divsi */
367 COSTS_N_INSNS (6), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (5), /* dmul */
370 COSTS_N_INSNS (10), /* sdiv */
371 COSTS_N_INSNS (17), /* ddiv */
374 /* Instruction costs on PPC403 processors. */
376 struct processor_costs ppc403_cost = {
377 COSTS_N_INSNS (4), /* mulsi */
378 COSTS_N_INSNS (4), /* mulsi_const */
379 COSTS_N_INSNS (4), /* mulsi_const9 */
380 COSTS_N_INSNS (4), /* muldi */
381 COSTS_N_INSNS (33), /* divsi */
382 COSTS_N_INSNS (33), /* divdi */
383 COSTS_N_INSNS (11), /* fp */
384 COSTS_N_INSNS (11), /* dmul */
385 COSTS_N_INSNS (11), /* sdiv */
386 COSTS_N_INSNS (11), /* ddiv */
389 /* Instruction costs on PPC405 processors. */
391 struct processor_costs ppc405_cost = {
392 COSTS_N_INSNS (5), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (3), /* mulsi_const9 */
395 COSTS_N_INSNS (5), /* muldi */
396 COSTS_N_INSNS (35), /* divsi */
397 COSTS_N_INSNS (35), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC440 processors. */
406 struct processor_costs ppc440_cost = {
407 COSTS_N_INSNS (3), /* mulsi */
408 COSTS_N_INSNS (2), /* mulsi_const */
409 COSTS_N_INSNS (2), /* mulsi_const9 */
410 COSTS_N_INSNS (3), /* muldi */
411 COSTS_N_INSNS (34), /* divsi */
412 COSTS_N_INSNS (34), /* divdi */
413 COSTS_N_INSNS (5), /* fp */
414 COSTS_N_INSNS (5), /* dmul */
415 COSTS_N_INSNS (19), /* sdiv */
416 COSTS_N_INSNS (33), /* ddiv */
419 /* Instruction costs on PPC601 processors. */
421 struct processor_costs ppc601_cost = {
422 COSTS_N_INSNS (5), /* mulsi */
423 COSTS_N_INSNS (5), /* mulsi_const */
424 COSTS_N_INSNS (5), /* mulsi_const9 */
425 COSTS_N_INSNS (5), /* muldi */
426 COSTS_N_INSNS (36), /* divsi */
427 COSTS_N_INSNS (36), /* divdi */
428 COSTS_N_INSNS (4), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (17), /* sdiv */
431 COSTS_N_INSNS (31), /* ddiv */
434 /* Instruction costs on PPC603 processors. */
436 struct processor_costs ppc603_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (3), /* mulsi_const */
439 COSTS_N_INSNS (2), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (37), /* divsi */
442 COSTS_N_INSNS (37), /* divdi */
443 COSTS_N_INSNS (3), /* fp */
444 COSTS_N_INSNS (4), /* dmul */
445 COSTS_N_INSNS (18), /* sdiv */
446 COSTS_N_INSNS (33), /* ddiv */
449 /* Instruction costs on PPC604 processors. */
451 struct processor_costs ppc604_cost = {
452 COSTS_N_INSNS (4), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (4), /* mulsi_const9 */
455 COSTS_N_INSNS (4), /* muldi */
456 COSTS_N_INSNS (20), /* divsi */
457 COSTS_N_INSNS (20), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (3), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (32), /* ddiv */
464 /* Instruction costs on PPC604e processors. */
466 struct processor_costs ppc604e_cost = {
467 COSTS_N_INSNS (2), /* mulsi */
468 COSTS_N_INSNS (2), /* mulsi_const */
469 COSTS_N_INSNS (2), /* mulsi_const9 */
470 COSTS_N_INSNS (2), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC620 processors. */
481 struct processor_costs ppc620_cost = {
482 COSTS_N_INSNS (5), /* mulsi */
483 COSTS_N_INSNS (4), /* mulsi_const */
484 COSTS_N_INSNS (3), /* mulsi_const9 */
485 COSTS_N_INSNS (7), /* muldi */
486 COSTS_N_INSNS (21), /* divsi */
487 COSTS_N_INSNS (37), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC630 processors. */
496 struct processor_costs ppc630_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (17), /* sdiv */
506 COSTS_N_INSNS (21), /* ddiv */
509 /* Instruction costs on PPC750 and PPC7400 processors. */
511 struct processor_costs ppc750_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (3), /* mulsi_const */
514 COSTS_N_INSNS (2), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (17), /* divsi */
517 COSTS_N_INSNS (17), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (31), /* ddiv */
524 /* Instruction costs on PPC7450 processors. */
526 struct processor_costs ppc7450_cost = {
527 COSTS_N_INSNS (4), /* mulsi */
528 COSTS_N_INSNS (3), /* mulsi_const */
529 COSTS_N_INSNS (3), /* mulsi_const9 */
530 COSTS_N_INSNS (4), /* muldi */
531 COSTS_N_INSNS (23), /* divsi */
532 COSTS_N_INSNS (23), /* divdi */
533 COSTS_N_INSNS (5), /* fp */
534 COSTS_N_INSNS (5), /* dmul */
535 COSTS_N_INSNS (21), /* sdiv */
536 COSTS_N_INSNS (35), /* ddiv */
539 /* Instruction costs on PPC8540 processors. */
541 struct processor_costs ppc8540_cost = {
542 COSTS_N_INSNS (4), /* mulsi */
543 COSTS_N_INSNS (4), /* mulsi_const */
544 COSTS_N_INSNS (4), /* mulsi_const9 */
545 COSTS_N_INSNS (4), /* muldi */
546 COSTS_N_INSNS (19), /* divsi */
547 COSTS_N_INSNS (19), /* divdi */
548 COSTS_N_INSNS (4), /* fp */
549 COSTS_N_INSNS (4), /* dmul */
550 COSTS_N_INSNS (29), /* sdiv */
551 COSTS_N_INSNS (29), /* ddiv */
554 /* Instruction costs on POWER4 and POWER5 processors. */
556 struct processor_costs power4_cost = {
557 COSTS_N_INSNS (3), /* mulsi */
558 COSTS_N_INSNS (2), /* mulsi_const */
559 COSTS_N_INSNS (2), /* mulsi_const9 */
560 COSTS_N_INSNS (4), /* muldi */
561 COSTS_N_INSNS (18), /* divsi */
562 COSTS_N_INSNS (34), /* divdi */
563 COSTS_N_INSNS (3), /* fp */
564 COSTS_N_INSNS (3), /* dmul */
565 COSTS_N_INSNS (17), /* sdiv */
566 COSTS_N_INSNS (17), /* ddiv */
570 static bool rs6000_function_ok_for_sibcall (tree, tree);
571 static const char *rs6000_invalid_within_doloop (rtx);
572 static rtx rs6000_generate_compare (enum rtx_code);
573 static void rs6000_maybe_dead (rtx);
574 static void rs6000_emit_stack_tie (void);
575 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
576 static rtx spe_synthesize_frame_save (rtx);
577 static bool spe_func_has_64bit_regs_p (void);
578 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
580 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
581 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
582 static unsigned rs6000_hash_constant (rtx);
583 static unsigned toc_hash_function (const void *);
584 static int toc_hash_eq (const void *, const void *);
585 static int constant_pool_expr_1 (rtx, int *, int *);
586 static bool constant_pool_expr_p (rtx);
587 static bool legitimate_indexed_address_p (rtx, int);
588 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
589 static struct machine_function * rs6000_init_machine_status (void);
590 static bool rs6000_assemble_integer (rtx, unsigned int, int);
591 static bool no_global_regs_above (int);
592 #ifdef HAVE_GAS_HIDDEN
593 static void rs6000_assemble_visibility (tree, int);
595 static int rs6000_ra_ever_killed (void);
596 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
597 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
598 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
599 static const char *rs6000_mangle_fundamental_type (tree);
600 extern const struct attribute_spec rs6000_attribute_table[];
601 static void rs6000_set_default_type_attributes (tree);
602 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
603 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
604 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
606 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
607 static bool rs6000_return_in_memory (tree, tree);
608 static void rs6000_file_start (void);
610 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
611 static void rs6000_elf_asm_out_constructor (rtx, int);
612 static void rs6000_elf_asm_out_destructor (rtx, int);
613 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
614 static void rs6000_elf_asm_init_sections (void);
615 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
616 static void rs6000_elf_unique_section (tree, int);
617 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
618 unsigned HOST_WIDE_INT);
619 static void rs6000_elf_encode_section_info (tree, rtx, int)
623 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
624 static void rs6000_xcoff_asm_init_sections (void);
625 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
626 static section *rs6000_xcoff_select_section (tree, int,
627 unsigned HOST_WIDE_INT);
628 static void rs6000_xcoff_unique_section (tree, int);
629 static section *rs6000_xcoff_select_rtx_section
630 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
631 static const char * rs6000_xcoff_strip_name_encoding (const char *);
632 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
633 static void rs6000_xcoff_file_start (void);
634 static void rs6000_xcoff_file_end (void);
636 static int rs6000_variable_issue (FILE *, int, rtx, int);
637 static bool rs6000_rtx_costs (rtx, int, int, int *);
638 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
639 static bool is_microcoded_insn (rtx);
640 static int is_dispatch_slot_restricted (rtx);
641 static bool is_cracked_insn (rtx);
642 static bool is_branch_slot_insn (rtx);
643 static int rs6000_adjust_priority (rtx, int);
644 static int rs6000_issue_rate (void);
645 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
646 static rtx get_next_active_insn (rtx, rtx);
647 static bool insn_terminates_group_p (rtx , enum group_termination);
648 static bool is_costly_group (rtx *, rtx);
649 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
650 static int redefine_groups (FILE *, int, rtx, rtx);
651 static int pad_groups (FILE *, int, rtx, rtx);
652 static void rs6000_sched_finish (FILE *, int);
653 static int rs6000_use_sched_lookahead (void);
654 static tree rs6000_builtin_mask_for_load (void);
656 static void def_builtin (int, const char *, tree, int);
657 static void rs6000_init_builtins (void);
658 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
659 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
660 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
661 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
662 static void altivec_init_builtins (void);
663 static void rs6000_common_init_builtins (void);
664 static void rs6000_init_libfuncs (void);
666 static void enable_mask_for_builtins (struct builtin_description *, int,
667 enum rs6000_builtins,
668 enum rs6000_builtins);
669 static tree build_opaque_vector_type (tree, int);
670 static void spe_init_builtins (void);
671 static rtx spe_expand_builtin (tree, rtx, bool *);
672 static rtx spe_expand_stv_builtin (enum insn_code, tree);
673 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
674 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
675 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
676 static rs6000_stack_t *rs6000_stack_info (void);
677 static void debug_stack_info (rs6000_stack_t *);
679 static rtx altivec_expand_builtin (tree, rtx, bool *);
680 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
681 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
682 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
683 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
684 static rtx altivec_expand_predicate_builtin (enum insn_code,
685 const char *, tree, rtx);
686 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
687 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
688 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
689 static rtx altivec_expand_vec_set_builtin (tree);
690 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
691 static int get_element_number (tree, tree);
692 static bool rs6000_handle_option (size_t, const char *, int);
693 static void rs6000_parse_tls_size_option (void);
694 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
695 static int first_altivec_reg_to_save (void);
696 static unsigned int compute_vrsave_mask (void);
697 static void compute_save_world_info (rs6000_stack_t *info_ptr);
698 static void is_altivec_return_reg (rtx, void *);
699 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
700 int easy_vector_constant (rtx, enum machine_mode);
701 static bool rs6000_is_opaque_type (tree);
702 static rtx rs6000_dwarf_register_span (rtx);
703 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
704 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
705 static rtx rs6000_tls_get_addr (void);
706 static rtx rs6000_got_sym (void);
707 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
708 static const char *rs6000_get_some_local_dynamic_name (void);
709 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
710 static rtx rs6000_complex_function_value (enum machine_mode);
711 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
712 enum machine_mode, tree);
713 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
715 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
716 tree, HOST_WIDE_INT);
717 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
720 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
723 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
724 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
725 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
726 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
727 enum machine_mode, tree,
729 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
731 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
733 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
735 static void macho_branch_islands (void);
736 static void add_compiler_branch_island (tree, tree, int);
737 static int no_previous_def (tree function_name);
738 static tree get_prev_label (tree function_name);
739 static void rs6000_darwin_file_start (void);
742 static tree rs6000_build_builtin_va_list (void);
743 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
744 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
745 static bool rs6000_vector_mode_supported_p (enum machine_mode);
746 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
748 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
750 static int get_vsel_insn (enum machine_mode);
751 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
752 static tree rs6000_stack_protect_fail (void);
754 const int INSN_NOT_AVAILABLE = -1;
755 static enum machine_mode rs6000_eh_return_filter_mode (void);
757 /* Hash table stuff for keeping track of TOC entries. */
759 struct toc_hash_struct GTY(())
761 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
762 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
764 enum machine_mode key_mode;
768 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
770 /* Default register names. */
771 char rs6000_reg_names[][8] =
773 "0", "1", "2", "3", "4", "5", "6", "7",
774 "8", "9", "10", "11", "12", "13", "14", "15",
775 "16", "17", "18", "19", "20", "21", "22", "23",
776 "24", "25", "26", "27", "28", "29", "30", "31",
777 "0", "1", "2", "3", "4", "5", "6", "7",
778 "8", "9", "10", "11", "12", "13", "14", "15",
779 "16", "17", "18", "19", "20", "21", "22", "23",
780 "24", "25", "26", "27", "28", "29", "30", "31",
781 "mq", "lr", "ctr","ap",
782 "0", "1", "2", "3", "4", "5", "6", "7",
784 /* AltiVec registers. */
785 "0", "1", "2", "3", "4", "5", "6", "7",
786 "8", "9", "10", "11", "12", "13", "14", "15",
787 "16", "17", "18", "19", "20", "21", "22", "23",
788 "24", "25", "26", "27", "28", "29", "30", "31",
791 "spe_acc", "spefscr",
792 /* Soft frame pointer. */
796 #ifdef TARGET_REGNAMES
797 static const char alt_reg_names[][8] =
799 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
800 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
801 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
802 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
803 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
804 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
805 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
806 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
807 "mq", "lr", "ctr", "ap",
808 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
810 /* AltiVec registers. */
811 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
812 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
813 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
814 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
817 "spe_acc", "spefscr",
818 /* Soft frame pointer. */
823 #ifndef MASK_STRICT_ALIGN
824 #define MASK_STRICT_ALIGN 0
826 #ifndef TARGET_PROFILE_KERNEL
827 #define TARGET_PROFILE_KERNEL 0
830 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
831 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
833 /* Initialize the GCC target structure. */
834 #undef TARGET_ATTRIBUTE_TABLE
835 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
836 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
837 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
839 #undef TARGET_ASM_ALIGNED_DI_OP
840 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
842 /* Default unaligned ops are only provided for ELF. Find the ops needed
843 for non-ELF systems. */
844 #ifndef OBJECT_FORMAT_ELF
846 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
848 #undef TARGET_ASM_UNALIGNED_HI_OP
849 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
850 #undef TARGET_ASM_UNALIGNED_SI_OP
851 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
852 #undef TARGET_ASM_UNALIGNED_DI_OP
853 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
856 #undef TARGET_ASM_UNALIGNED_HI_OP
857 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
858 #undef TARGET_ASM_UNALIGNED_SI_OP
859 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
860 #undef TARGET_ASM_UNALIGNED_DI_OP
861 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
862 #undef TARGET_ASM_ALIGNED_DI_OP
863 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
867 /* This hook deals with fixups for relocatable code and DI-mode objects
869 #undef TARGET_ASM_INTEGER
870 #define TARGET_ASM_INTEGER rs6000_assemble_integer
872 #ifdef HAVE_GAS_HIDDEN
873 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
874 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
877 #undef TARGET_HAVE_TLS
878 #define TARGET_HAVE_TLS HAVE_AS_TLS
880 #undef TARGET_CANNOT_FORCE_CONST_MEM
881 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
883 #undef TARGET_ASM_FUNCTION_PROLOGUE
884 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
885 #undef TARGET_ASM_FUNCTION_EPILOGUE
886 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
888 #undef TARGET_SCHED_VARIABLE_ISSUE
889 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
891 #undef TARGET_SCHED_ISSUE_RATE
892 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
893 #undef TARGET_SCHED_ADJUST_COST
894 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
895 #undef TARGET_SCHED_ADJUST_PRIORITY
896 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
897 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
898 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
899 #undef TARGET_SCHED_FINISH
900 #define TARGET_SCHED_FINISH rs6000_sched_finish
902 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
903 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
905 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
906 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
908 #undef TARGET_INIT_BUILTINS
909 #define TARGET_INIT_BUILTINS rs6000_init_builtins
911 #undef TARGET_EXPAND_BUILTIN
912 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
914 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
915 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
917 #undef TARGET_INIT_LIBFUNCS
918 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
921 #undef TARGET_BINDS_LOCAL_P
922 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
925 #undef TARGET_ASM_OUTPUT_MI_THUNK
926 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
928 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
929 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
931 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
932 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
934 #undef TARGET_INVALID_WITHIN_DOLOOP
935 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
937 #undef TARGET_RTX_COSTS
938 #define TARGET_RTX_COSTS rs6000_rtx_costs
939 #undef TARGET_ADDRESS_COST
940 #define TARGET_ADDRESS_COST hook_int_rtx_0
942 #undef TARGET_VECTOR_OPAQUE_P
943 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
945 #undef TARGET_DWARF_REGISTER_SPAN
946 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
948 /* On rs6000, function arguments are promoted, as are function return
950 #undef TARGET_PROMOTE_FUNCTION_ARGS
951 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
952 #undef TARGET_PROMOTE_FUNCTION_RETURN
953 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
955 #undef TARGET_RETURN_IN_MEMORY
956 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
958 #undef TARGET_SETUP_INCOMING_VARARGS
959 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
961 /* Always strict argument naming on rs6000. */
962 #undef TARGET_STRICT_ARGUMENT_NAMING
963 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
964 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
965 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
966 #undef TARGET_SPLIT_COMPLEX_ARG
967 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
968 #undef TARGET_MUST_PASS_IN_STACK
969 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
970 #undef TARGET_PASS_BY_REFERENCE
971 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
972 #undef TARGET_ARG_PARTIAL_BYTES
973 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
975 #undef TARGET_BUILD_BUILTIN_VA_LIST
976 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
978 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
979 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
981 #undef TARGET_EH_RETURN_FILTER_MODE
982 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
984 #undef TARGET_VECTOR_MODE_SUPPORTED_P
985 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
987 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
988 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
990 #undef TARGET_HANDLE_OPTION
991 #define TARGET_HANDLE_OPTION rs6000_handle_option
993 #undef TARGET_DEFAULT_TARGET_FLAGS
994 #define TARGET_DEFAULT_TARGET_FLAGS \
995 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
997 #undef TARGET_STACK_PROTECT_FAIL
998 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1000 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1001 The PowerPC architecture requires only weak consistency among
1002 processors--that is, memory accesses between processors need not be
1003 sequentially consistent and memory accesses among processors can occur
1004 in any order. The ability to order memory accesses weakly provides
1005 opportunities for more efficient use of the system bus. Unless a
1006 dependency exists, the 604e allows read operations to precede store
1008 #undef TARGET_RELAXED_ORDERING
1009 #define TARGET_RELAXED_ORDERING true
1012 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1013 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1016 struct gcc_target targetm = TARGET_INITIALIZER;
1019 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1022 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1024 /* The GPRs can hold any mode, but values bigger than one register
1025 cannot go past R31. */
1026 if (INT_REGNO_P (regno))
1027 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1029 /* The float registers can only hold floating modes and DImode. */
1030 if (FP_REGNO_P (regno))
1032 (SCALAR_FLOAT_MODE_P (mode)
1033 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1034 || (GET_MODE_CLASS (mode) == MODE_INT
1035 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1037 /* The CR register can only hold CC modes. */
1038 if (CR_REGNO_P (regno))
1039 return GET_MODE_CLASS (mode) == MODE_CC;
1041 if (XER_REGNO_P (regno))
1042 return mode == PSImode;
1044 /* AltiVec only in AldyVec registers. */
1045 if (ALTIVEC_REGNO_P (regno))
1046 return ALTIVEC_VECTOR_MODE (mode);
1048 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1049 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1052 /* We cannot put TImode anywhere except general register and it must be
1053 able to fit within the register set. */
1055 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1058 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1060 rs6000_init_hard_regno_mode_ok (void)
1064 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1065 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1066 if (rs6000_hard_regno_mode_ok (r, m))
1067 rs6000_hard_regno_mode_ok_p[m][r] = true;
1070 /* If not otherwise specified by a target, make 'long double' equivalent to
1073 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1074 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1077 /* Override command line options. Mostly we process the processor
1078 type and sometimes adjust other TARGET_ options. */
1081 rs6000_override_options (const char *default_cpu)
1084 struct rs6000_cpu_select *ptr;
1087 /* Simplifications for entries below. */
1090 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1091 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1094 /* This table occasionally claims that a processor does not support
1095 a particular feature even though it does, but the feature is slower
1096 than the alternative. Thus, it shouldn't be relied on as a
1097 complete description of the processor's support.
1099 Please keep this list in order, and don't forget to update the
1100 documentation in invoke.texi when adding a new processor or
1104 const char *const name; /* Canonical processor name. */
1105 const enum processor_type processor; /* Processor type enum value. */
1106 const int target_enable; /* Target flags to enable. */
1107 } const processor_target_table[]
1108 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1109 {"403", PROCESSOR_PPC403,
1110 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1111 {"405", PROCESSOR_PPC405,
1112 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1113 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_MULHW},
1114 {"440", PROCESSOR_PPC440,
1115 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1116 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_MULHW},
1117 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1118 {"601", PROCESSOR_PPC601,
1119 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1120 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1121 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1123 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1124 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"620", PROCESSOR_PPC620,
1126 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1127 {"630", PROCESSOR_PPC630,
1128 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1129 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1130 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1131 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1132 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1133 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1134 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1135 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1136 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 /* 8548 has a dummy entry for now. */
1138 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1139 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"970", PROCESSOR_POWER4,
1141 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1142 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1143 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1144 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1145 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1146 {"G5", PROCESSOR_POWER4,
1147 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1148 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1149 {"power2", PROCESSOR_POWER,
1150 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1151 {"power3", PROCESSOR_PPC630,
1152 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1153 {"power4", PROCESSOR_POWER4,
1154 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1155 {"power5", PROCESSOR_POWER5,
1156 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1157 | MASK_MFCRF | MASK_POPCNTB},
1158 {"power5+", PROCESSOR_POWER5,
1159 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1160 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1170 {"rs64", PROCESSOR_RS64A,
1171 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1174 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1176 /* Some OSs don't support saving the high part of 64-bit registers on
1177 context switch. Other OSs don't support saving Altivec registers.
1178 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1179 settings; if the user wants either, the user must explicitly specify
1180 them and we won't interfere with the user's specification. */
1183 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1184 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1185 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1186 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW)
1189 rs6000_init_hard_regno_mode_ok ();
1191 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1192 #ifdef OS_MISSING_POWERPC64
1193 if (OS_MISSING_POWERPC64)
1194 set_masks &= ~MASK_POWERPC64;
1196 #ifdef OS_MISSING_ALTIVEC
1197 if (OS_MISSING_ALTIVEC)
1198 set_masks &= ~MASK_ALTIVEC;
1201 /* Don't override by the processor default if given explicitly. */
1202 set_masks &= ~target_flags_explicit;
1204 /* Identify the processor type. */
1205 rs6000_select[0].string = default_cpu;
1206 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1208 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1210 ptr = &rs6000_select[i];
1211 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1213 for (j = 0; j < ptt_size; j++)
1214 if (! strcmp (ptr->string, processor_target_table[j].name))
1216 if (ptr->set_tune_p)
1217 rs6000_cpu = processor_target_table[j].processor;
1219 if (ptr->set_arch_p)
1221 target_flags &= ~set_masks;
1222 target_flags |= (processor_target_table[j].target_enable
1229 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1236 /* If we are optimizing big endian systems for space, use the load/store
1237 multiple and string instructions. */
1238 if (BYTES_BIG_ENDIAN && optimize_size)
1239 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1241 /* Don't allow -mmultiple or -mstring on little endian systems
1242 unless the cpu is a 750, because the hardware doesn't support the
1243 instructions used in little endian mode, and causes an alignment
1244 trap. The 750 does not cause an alignment trap (except when the
1245 target is unaligned). */
1247 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1249 if (TARGET_MULTIPLE)
1251 target_flags &= ~MASK_MULTIPLE;
1252 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1253 warning (0, "-mmultiple is not supported on little endian systems");
1258 target_flags &= ~MASK_STRING;
1259 if ((target_flags_explicit & MASK_STRING) != 0)
1260 warning (0, "-mstring is not supported on little endian systems");
1264 /* Set debug flags */
1265 if (rs6000_debug_name)
1267 if (! strcmp (rs6000_debug_name, "all"))
1268 rs6000_debug_stack = rs6000_debug_arg = 1;
1269 else if (! strcmp (rs6000_debug_name, "stack"))
1270 rs6000_debug_stack = 1;
1271 else if (! strcmp (rs6000_debug_name, "arg"))
1272 rs6000_debug_arg = 1;
1274 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1277 if (rs6000_traceback_name)
1279 if (! strncmp (rs6000_traceback_name, "full", 4))
1280 rs6000_traceback = traceback_full;
1281 else if (! strncmp (rs6000_traceback_name, "part", 4))
1282 rs6000_traceback = traceback_part;
1283 else if (! strncmp (rs6000_traceback_name, "no", 2))
1284 rs6000_traceback = traceback_none;
1286 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1287 rs6000_traceback_name);
1290 if (!rs6000_explicit_options.long_double)
1291 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1293 /* Set Altivec ABI as default for powerpc64 linux. */
1294 if (TARGET_ELF && TARGET_64BIT)
1296 rs6000_altivec_abi = 1;
1297 TARGET_ALTIVEC_VRSAVE = 1;
1300 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1301 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1303 rs6000_darwin64_abi = 1;
1305 darwin_one_byte_bool = 1;
1307 /* Default to natural alignment, for better performance. */
1308 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1311 /* Handle -mtls-size option. */
1312 rs6000_parse_tls_size_option ();
1314 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1315 SUBTARGET_OVERRIDE_OPTIONS;
1317 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1318 SUBSUBTARGET_OVERRIDE_OPTIONS;
1320 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1321 SUB3TARGET_OVERRIDE_OPTIONS;
1327 error ("AltiVec and E500 instructions cannot coexist");
1329 /* The e500 does not have string instructions, and we set
1330 MASK_STRING above when optimizing for size. */
1331 if ((target_flags & MASK_STRING) != 0)
1332 target_flags = target_flags & ~MASK_STRING;
1334 else if (rs6000_select[1].string != NULL)
1336 /* For the powerpc-eabispe configuration, we set all these by
1337 default, so let's unset them if we manually set another
1338 CPU that is not the E500. */
1339 if (!rs6000_explicit_options.abi)
1341 if (!rs6000_explicit_options.spe)
1343 if (!rs6000_explicit_options.float_gprs)
1344 rs6000_float_gprs = 0;
1345 if (!rs6000_explicit_options.isel)
1347 if (!rs6000_explicit_options.long_double)
1348 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1351 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1352 && rs6000_cpu != PROCESSOR_POWER5);
1353 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1354 || rs6000_cpu == PROCESSOR_POWER5);
1356 rs6000_sched_restricted_insns_priority
1357 = (rs6000_sched_groups ? 1 : 0);
1359 /* Handle -msched-costly-dep option. */
1360 rs6000_sched_costly_dep
1361 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1363 if (rs6000_sched_costly_dep_str)
1365 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1366 rs6000_sched_costly_dep = no_dep_costly;
1367 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1368 rs6000_sched_costly_dep = all_deps_costly;
1369 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1370 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1371 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1372 rs6000_sched_costly_dep = store_to_load_dep_costly;
1374 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1377 /* Handle -minsert-sched-nops option. */
1378 rs6000_sched_insert_nops
1379 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1381 if (rs6000_sched_insert_nops_str)
1383 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1384 rs6000_sched_insert_nops = sched_finish_none;
1385 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1386 rs6000_sched_insert_nops = sched_finish_pad_groups;
1387 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1388 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1390 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1393 #ifdef TARGET_REGNAMES
1394 /* If the user desires alternate register names, copy in the
1395 alternate names now. */
1396 if (TARGET_REGNAMES)
1397 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1400 /* Set aix_struct_return last, after the ABI is determined.
1401 If -maix-struct-return or -msvr4-struct-return was explicitly
1402 used, don't override with the ABI default. */
1403 if (!rs6000_explicit_options.aix_struct_ret)
1404 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1406 if (TARGET_LONG_DOUBLE_128
1407 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1408 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1411 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1413 /* We can only guarantee the availability of DI pseudo-ops when
1414 assembling for 64-bit targets. */
1417 targetm.asm_out.aligned_op.di = NULL;
1418 targetm.asm_out.unaligned_op.di = NULL;
1421 /* Set branch target alignment, if not optimizing for size. */
1424 if (rs6000_sched_groups)
1426 if (align_functions <= 0)
1427 align_functions = 16;
1428 if (align_jumps <= 0)
1430 if (align_loops <= 0)
1433 if (align_jumps_max_skip <= 0)
1434 align_jumps_max_skip = 15;
1435 if (align_loops_max_skip <= 0)
1436 align_loops_max_skip = 15;
1439 /* Arrange to save and restore machine status around nested functions. */
1440 init_machine_status = rs6000_init_machine_status;
1442 /* We should always be splitting complex arguments, but we can't break
1443 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1444 if (DEFAULT_ABI != ABI_AIX)
1445 targetm.calls.split_complex_arg = NULL;
1447 /* Initialize rs6000_cost with the appropriate target costs. */
1449 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1453 case PROCESSOR_RIOS1:
1454 rs6000_cost = &rios1_cost;
1457 case PROCESSOR_RIOS2:
1458 rs6000_cost = &rios2_cost;
1461 case PROCESSOR_RS64A:
1462 rs6000_cost = &rs64a_cost;
1465 case PROCESSOR_MPCCORE:
1466 rs6000_cost = &mpccore_cost;
1469 case PROCESSOR_PPC403:
1470 rs6000_cost = &ppc403_cost;
1473 case PROCESSOR_PPC405:
1474 rs6000_cost = &ppc405_cost;
1477 case PROCESSOR_PPC440:
1478 rs6000_cost = &ppc440_cost;
1481 case PROCESSOR_PPC601:
1482 rs6000_cost = &ppc601_cost;
1485 case PROCESSOR_PPC603:
1486 rs6000_cost = &ppc603_cost;
1489 case PROCESSOR_PPC604:
1490 rs6000_cost = &ppc604_cost;
1493 case PROCESSOR_PPC604e:
1494 rs6000_cost = &ppc604e_cost;
1497 case PROCESSOR_PPC620:
1498 rs6000_cost = &ppc620_cost;
1501 case PROCESSOR_PPC630:
1502 rs6000_cost = &ppc630_cost;
1505 case PROCESSOR_PPC750:
1506 case PROCESSOR_PPC7400:
1507 rs6000_cost = &ppc750_cost;
1510 case PROCESSOR_PPC7450:
1511 rs6000_cost = &ppc7450_cost;
1514 case PROCESSOR_PPC8540:
1515 rs6000_cost = &ppc8540_cost;
1518 case PROCESSOR_POWER4:
1519 case PROCESSOR_POWER5:
1520 rs6000_cost = &power4_cost;
1528 /* Implement targetm.vectorize.builtin_mask_for_load. */
1530 rs6000_builtin_mask_for_load (void)
1533 return altivec_builtin_mask_for_load;
1538 /* Handle generic options of the form -mfoo=yes/no.
1539 NAME is the option name.
1540 VALUE is the option value.
1541 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1542 whether the option value is 'yes' or 'no' respectively. */
1544 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1548 else if (!strcmp (value, "yes"))
1550 else if (!strcmp (value, "no"))
1553 error ("unknown -m%s= option specified: '%s'", name, value);
1556 /* Validate and record the size specified with the -mtls-size option. */
1559 rs6000_parse_tls_size_option (void)
1561 if (rs6000_tls_size_string == 0)
1563 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1564 rs6000_tls_size = 16;
1565 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1566 rs6000_tls_size = 32;
1567 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1568 rs6000_tls_size = 64;
1570 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1574 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1576 if (DEFAULT_ABI == ABI_DARWIN)
1577 /* The Darwin libraries never set errno, so we might as well
1578 avoid calling them when that's the only reason we would. */
1579 flag_errno_math = 0;
1581 /* Double growth factor to counter reduced min jump length. */
1582 set_param_value ("max-grow-copy-bb-insns", 16);
1585 /* Implement TARGET_HANDLE_OPTION. */
1588 rs6000_handle_option (size_t code, const char *arg, int value)
1593 target_flags &= ~(MASK_POWER | MASK_POWER2
1594 | MASK_MULTIPLE | MASK_STRING);
1595 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1596 | MASK_MULTIPLE | MASK_STRING);
1598 case OPT_mno_powerpc:
1599 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1600 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1601 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1602 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1605 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1606 | MASK_NO_SUM_IN_TOC);
1607 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1608 | MASK_NO_SUM_IN_TOC);
1609 #ifdef TARGET_USES_SYSV4_OPT
1610 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1611 just the same as -mminimal-toc. */
1612 target_flags |= MASK_MINIMAL_TOC;
1613 target_flags_explicit |= MASK_MINIMAL_TOC;
1617 #ifdef TARGET_USES_SYSV4_OPT
1619 /* Make -mtoc behave like -mminimal-toc. */
1620 target_flags |= MASK_MINIMAL_TOC;
1621 target_flags_explicit |= MASK_MINIMAL_TOC;
1625 #ifdef TARGET_USES_AIX64_OPT
1630 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1631 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1632 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1635 #ifdef TARGET_USES_AIX64_OPT
1640 target_flags &= ~MASK_POWERPC64;
1641 target_flags_explicit |= MASK_POWERPC64;
1644 case OPT_minsert_sched_nops_:
1645 rs6000_sched_insert_nops_str = arg;
1648 case OPT_mminimal_toc:
1651 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1652 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1659 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1660 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1667 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1668 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1672 case OPT_mpowerpc_gpopt:
1673 case OPT_mpowerpc_gfxopt:
1676 target_flags |= MASK_POWERPC;
1677 target_flags_explicit |= MASK_POWERPC;
1681 case OPT_maix_struct_return:
1682 case OPT_msvr4_struct_return:
1683 rs6000_explicit_options.aix_struct_ret = true;
1687 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1691 rs6000_explicit_options.isel = true;
1692 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1696 rs6000_explicit_options.spe = true;
1697 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1698 /* No SPE means 64-bit long doubles, even if an E500. */
1700 rs6000_long_double_type_size = 64;
1704 rs6000_debug_name = arg;
1707 #ifdef TARGET_USES_SYSV4_OPT
1709 rs6000_abi_name = arg;
1713 rs6000_sdata_name = arg;
1716 case OPT_mtls_size_:
1717 rs6000_tls_size_string = arg;
1720 case OPT_mrelocatable:
1723 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1724 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1728 case OPT_mrelocatable_lib:
1731 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1732 | MASK_NO_FP_IN_TOC;
1733 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1734 | MASK_NO_FP_IN_TOC;
1738 target_flags &= ~MASK_RELOCATABLE;
1739 target_flags_explicit |= MASK_RELOCATABLE;
1745 rs6000_explicit_options.abi = true;
1746 if (!strcmp (arg, "altivec"))
1748 rs6000_altivec_abi = 1;
1751 else if (! strcmp (arg, "no-altivec"))
1752 rs6000_altivec_abi = 0;
1753 else if (! strcmp (arg, "spe"))
1756 rs6000_altivec_abi = 0;
1757 if (!TARGET_SPE_ABI)
1758 error ("not configured for ABI: '%s'", arg);
1760 else if (! strcmp (arg, "no-spe"))
1763 /* These are here for testing during development only, do not
1764 document in the manual please. */
1765 else if (! strcmp (arg, "d64"))
1767 rs6000_darwin64_abi = 1;
1768 warning (0, "Using darwin64 ABI");
1770 else if (! strcmp (arg, "d32"))
1772 rs6000_darwin64_abi = 0;
1773 warning (0, "Using old darwin ABI");
1778 error ("unknown ABI specified: '%s'", arg);
1784 rs6000_select[1].string = arg;
1788 rs6000_select[2].string = arg;
1791 case OPT_mtraceback_:
1792 rs6000_traceback_name = arg;
1795 case OPT_mfloat_gprs_:
1796 rs6000_explicit_options.float_gprs = true;
1797 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1798 rs6000_float_gprs = 1;
1799 else if (! strcmp (arg, "double"))
1800 rs6000_float_gprs = 2;
1801 else if (! strcmp (arg, "no"))
1802 rs6000_float_gprs = 0;
1805 error ("invalid option for -mfloat-gprs: '%s'", arg);
1810 case OPT_mlong_double_:
1811 rs6000_explicit_options.long_double = true;
1812 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1813 if (value != 64 && value != 128)
1815 error ("Unknown switch -mlong-double-%s", arg);
1816 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1820 rs6000_long_double_type_size = value;
1823 case OPT_msched_costly_dep_:
1824 rs6000_sched_costly_dep_str = arg;
1828 rs6000_explicit_options.alignment = true;
1829 if (! strcmp (arg, "power"))
1831 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1832 some C library functions, so warn about it. The flag may be
1833 useful for performance studies from time to time though, so
1834 don't disable it entirely. */
1835 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1836 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1837 " it is incompatible with the installed C and C++ libraries");
1838 rs6000_alignment_flags = MASK_ALIGN_POWER;
1840 else if (! strcmp (arg, "natural"))
1841 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1844 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1852 /* Do anything needed at the start of the asm file. */
1855 rs6000_file_start (void)
1859 const char *start = buffer;
1860 struct rs6000_cpu_select *ptr;
1861 const char *default_cpu = TARGET_CPU_DEFAULT;
1862 FILE *file = asm_out_file;
1864 default_file_start ();
1866 #ifdef TARGET_BI_ARCH
1867 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1871 if (flag_verbose_asm)
1873 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1874 rs6000_select[0].string = default_cpu;
1876 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1878 ptr = &rs6000_select[i];
1879 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1881 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1886 if (PPC405_ERRATUM77)
1888 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1892 #ifdef USING_ELFOS_H
1893 switch (rs6000_sdata)
1895 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1896 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1897 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1898 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1901 if (rs6000_sdata && g_switch_value)
1903 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1913 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1915 switch_to_section (toc_section);
1916 switch_to_section (text_section);
1921 /* Return nonzero if this function is known to have a null epilogue. */
1924 direct_return (void)
1926 if (reload_completed)
1928 rs6000_stack_t *info = rs6000_stack_info ();
1930 if (info->first_gp_reg_save == 32
1931 && info->first_fp_reg_save == 64
1932 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1933 && ! info->lr_save_p
1934 && ! info->cr_save_p
1935 && info->vrsave_mask == 0
1943 /* Return the number of instructions it takes to form a constant in an
1944 integer register. */
1947 num_insns_constant_wide (HOST_WIDE_INT value)
1949 /* signed constant loadable with {cal|addi} */
1950 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1953 /* constant loadable with {cau|addis} */
1954 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1957 #if HOST_BITS_PER_WIDE_INT == 64
1958 else if (TARGET_POWERPC64)
1960 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1961 HOST_WIDE_INT high = value >> 31;
1963 if (high == 0 || high == -1)
1969 return num_insns_constant_wide (high) + 1;
1971 return (num_insns_constant_wide (high)
1972 + num_insns_constant_wide (low) + 1);
1981 num_insns_constant (rtx op, enum machine_mode mode)
1983 HOST_WIDE_INT low, high;
1985 switch (GET_CODE (op))
1988 #if HOST_BITS_PER_WIDE_INT == 64
1989 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1990 && mask64_operand (op, mode))
1994 return num_insns_constant_wide (INTVAL (op));
2002 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2003 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2004 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2007 if (mode == VOIDmode || mode == DImode)
2009 high = CONST_DOUBLE_HIGH (op);
2010 low = CONST_DOUBLE_LOW (op);
2017 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2018 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2019 high = l[WORDS_BIG_ENDIAN == 0];
2020 low = l[WORDS_BIG_ENDIAN != 0];
2024 return (num_insns_constant_wide (low)
2025 + num_insns_constant_wide (high));
2028 if ((high == 0 && low >= 0)
2029 || (high == -1 && low < 0))
2030 return num_insns_constant_wide (low);
2032 else if (mask64_operand (op, mode))
2036 return num_insns_constant_wide (high) + 1;
2039 return (num_insns_constant_wide (high)
2040 + num_insns_constant_wide (low) + 1);
2049 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2050 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2051 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2052 all items are set to the same value and contain COPIES replicas of the
2053 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2054 operand and the others are set to the value of the operand's msb. */
2057 vspltis_constant (rtx op, unsigned step, unsigned copies)
2059 enum machine_mode mode = GET_MODE (op);
2060 enum machine_mode inner = GET_MODE_INNER (mode);
2063 unsigned nunits = GET_MODE_NUNITS (mode);
2064 unsigned bitsize = GET_MODE_BITSIZE (inner);
2065 unsigned mask = GET_MODE_MASK (inner);
2067 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2068 HOST_WIDE_INT val = INTVAL (last);
2069 HOST_WIDE_INT splat_val = val;
2070 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2072 /* Construct the value to be splatted, if possible. If not, return 0. */
2073 for (i = 2; i <= copies; i *= 2)
2075 HOST_WIDE_INT small_val;
2077 small_val = splat_val >> bitsize;
2079 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2081 splat_val = small_val;
2084 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2085 if (EASY_VECTOR_15 (splat_val))
2088 /* Also check if we can splat, and then add the result to itself. Do so if
2089 the value is positive, of if the splat instruction is using OP's mode;
2090 for splat_val < 0, the splat and the add should use the same mode. */
2091 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2092 && (splat_val >= 0 || (step == 1 && copies == 1)))
2098 /* Check if VAL is present in every STEP-th element, and the
2099 other elements are filled with its most significant bit. */
2100 for (i = 0; i < nunits - 1; ++i)
2102 HOST_WIDE_INT desired_val;
2103 if (((i + 1) & (step - 1)) == 0)
2106 desired_val = msb_val;
2108 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2116 /* Return true if OP is of the given MODE and can be synthesized
2117 with a vspltisb, vspltish or vspltisw. */
2120 easy_altivec_constant (rtx op, enum machine_mode mode)
2122 unsigned step, copies;
2124 if (mode == VOIDmode)
2125 mode = GET_MODE (op);
2126 else if (mode != GET_MODE (op))
2129 /* Start with a vspltisw. */
2130 step = GET_MODE_NUNITS (mode) / 4;
2133 if (vspltis_constant (op, step, copies))
2136 /* Then try with a vspltish. */
2142 if (vspltis_constant (op, step, copies))
2145 /* And finally a vspltisb. */
2151 if (vspltis_constant (op, step, copies))
2157 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2158 result is OP. Abort if it is not possible. */
2161 gen_easy_altivec_constant (rtx op)
2163 enum machine_mode mode = GET_MODE (op);
2164 int nunits = GET_MODE_NUNITS (mode);
2165 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2166 unsigned step = nunits / 4;
2167 unsigned copies = 1;
2169 /* Start with a vspltisw. */
2170 if (vspltis_constant (op, step, copies))
2171 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2173 /* Then try with a vspltish. */
2179 if (vspltis_constant (op, step, copies))
2180 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2182 /* And finally a vspltisb. */
2188 if (vspltis_constant (op, step, copies))
2189 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2195 output_vec_const_move (rtx *operands)
2198 enum machine_mode mode;
2203 mode = GET_MODE (dest);
2208 if (zero_constant (vec, mode))
2209 return "vxor %0,%0,%0";
2211 splat_vec = gen_easy_altivec_constant (vec);
2212 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2213 operands[1] = XEXP (splat_vec, 0);
2214 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2217 switch (GET_MODE (splat_vec))
2220 return "vspltisw %0,%1";
2223 return "vspltish %0,%1";
2226 return "vspltisb %0,%1";
2233 gcc_assert (TARGET_SPE);
2235 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2236 pattern of V1DI, V4HI, and V2SF.
2238 FIXME: We should probably return # and add post reload
2239 splitters for these, but this way is so easy ;-). */
2240 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2241 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2242 operands[1] = CONST_VECTOR_ELT (vec, 0);
2243 operands[2] = CONST_VECTOR_ELT (vec, 1);
2245 return "li %0,%1\n\tevmergelo %0,%0,%0";
2247 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2250 /* Initialize vector TARGET to VALS. */
2253 rs6000_expand_vector_init (rtx target, rtx vals)
2255 enum machine_mode mode = GET_MODE (target);
2256 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2257 int n_elts = GET_MODE_NUNITS (mode);
2258 int n_var = 0, one_var = -1;
2259 bool all_same = true, all_const_zero = true;
2263 for (i = 0; i < n_elts; ++i)
2265 x = XVECEXP (vals, 0, i);
2266 if (!CONSTANT_P (x))
2267 ++n_var, one_var = i;
2268 else if (x != CONST0_RTX (inner_mode))
2269 all_const_zero = false;
2271 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2277 if (mode != V4SFmode && all_const_zero)
2279 /* Zero register. */
2280 emit_insn (gen_rtx_SET (VOIDmode, target,
2281 gen_rtx_XOR (mode, target, target)));
2284 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2286 /* Splat immediate. */
2287 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2291 ; /* Splat vector element. */
2294 /* Load from constant pool. */
2295 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2300 /* Store value to stack temp. Load vector element. Splat. */
2303 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2304 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2305 XVECEXP (vals, 0, 0));
2306 x = gen_rtx_UNSPEC (VOIDmode,
2307 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2308 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2310 gen_rtx_SET (VOIDmode,
2313 x = gen_rtx_VEC_SELECT (inner_mode, target,
2314 gen_rtx_PARALLEL (VOIDmode,
2315 gen_rtvec (1, const0_rtx)));
2316 emit_insn (gen_rtx_SET (VOIDmode, target,
2317 gen_rtx_VEC_DUPLICATE (mode, x)));
2321 /* One field is non-constant. Load constant then overwrite
2325 rtx copy = copy_rtx (vals);
2327 /* Load constant part of vector, substitute neighboring value for
2329 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2330 rs6000_expand_vector_init (target, copy);
2332 /* Insert variable. */
2333 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2337 /* Construct the vector in memory one field at a time
2338 and load the whole vector. */
2339 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2340 for (i = 0; i < n_elts; i++)
2341 emit_move_insn (adjust_address_nv (mem, inner_mode,
2342 i * GET_MODE_SIZE (inner_mode)),
2343 XVECEXP (vals, 0, i));
2344 emit_move_insn (target, mem);
2347 /* Set field ELT of TARGET to VAL. */
2350 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2352 enum machine_mode mode = GET_MODE (target);
2353 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2354 rtx reg = gen_reg_rtx (mode);
2356 int width = GET_MODE_SIZE (inner_mode);
2359 /* Load single variable value. */
2360 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2361 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2362 x = gen_rtx_UNSPEC (VOIDmode,
2363 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2364 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2366 gen_rtx_SET (VOIDmode,
2370 /* Linear sequence. */
2371 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2372 for (i = 0; i < 16; ++i)
2373 XVECEXP (mask, 0, i) = GEN_INT (i);
2375 /* Set permute mask to insert element into target. */
2376 for (i = 0; i < width; ++i)
2377 XVECEXP (mask, 0, elt*width + i)
2378 = GEN_INT (i + 0x10);
2379 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2380 x = gen_rtx_UNSPEC (mode,
2381 gen_rtvec (3, target, reg,
2382 force_reg (V16QImode, x)),
2384 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2387 /* Extract field ELT from VEC into TARGET. */
2390 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2392 enum machine_mode mode = GET_MODE (vec);
2393 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2396 /* Allocate mode-sized buffer. */
2397 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2399 /* Add offset to field within buffer matching vector element. */
2400 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2402 /* Store single field into mode-sized buffer. */
2403 x = gen_rtx_UNSPEC (VOIDmode,
2404 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2405 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2407 gen_rtx_SET (VOIDmode,
2410 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2413 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2414 implement ANDing by the mask IN. */
2416 build_mask64_2_operands (rtx in, rtx *out)
2418 #if HOST_BITS_PER_WIDE_INT >= 64
2419 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2422 gcc_assert (GET_CODE (in) == CONST_INT);
2427 /* Assume c initially something like 0x00fff000000fffff. The idea
2428 is to rotate the word so that the middle ^^^^^^ group of zeros
2429 is at the MS end and can be cleared with an rldicl mask. We then
2430 rotate back and clear off the MS ^^ group of zeros with a
2432 c = ~c; /* c == 0xff000ffffff00000 */
2433 lsb = c & -c; /* lsb == 0x0000000000100000 */
2434 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2435 c = ~c; /* c == 0x00fff000000fffff */
2436 c &= -lsb; /* c == 0x00fff00000000000 */
2437 lsb = c & -c; /* lsb == 0x0000100000000000 */
2438 c = ~c; /* c == 0xff000fffffffffff */
2439 c &= -lsb; /* c == 0xff00000000000000 */
2441 while ((lsb >>= 1) != 0)
2442 shift++; /* shift == 44 on exit from loop */
2443 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2444 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2445 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2449 /* Assume c initially something like 0xff000f0000000000. The idea
2450 is to rotate the word so that the ^^^ middle group of zeros
2451 is at the LS end and can be cleared with an rldicr mask. We then
2452 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2454 lsb = c & -c; /* lsb == 0x0000010000000000 */
2455 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2456 c = ~c; /* c == 0x00fff0ffffffffff */
2457 c &= -lsb; /* c == 0x00fff00000000000 */
2458 lsb = c & -c; /* lsb == 0x0000100000000000 */
2459 c = ~c; /* c == 0xff000fffffffffff */
2460 c &= -lsb; /* c == 0xff00000000000000 */
2462 while ((lsb >>= 1) != 0)
2463 shift++; /* shift == 44 on exit from loop */
2464 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2465 m1 >>= shift; /* m1 == 0x0000000000000fff */
2466 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2469 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2470 masks will be all 1's. We are guaranteed more than one transition. */
2471 out[0] = GEN_INT (64 - shift);
2472 out[1] = GEN_INT (m1);
2473 out[2] = GEN_INT (shift);
2474 out[3] = GEN_INT (m2);
2482 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2485 invalid_e500_subreg (rtx op, enum machine_mode mode)
2487 /* Reject (subreg:SI (reg:DF)). */
2488 if (GET_CODE (op) == SUBREG
2490 && REG_P (SUBREG_REG (op))
2491 && GET_MODE (SUBREG_REG (op)) == DFmode)
2494 /* Reject (subreg:DF (reg:DI)). */
2495 if (GET_CODE (op) == SUBREG
2497 && REG_P (SUBREG_REG (op))
2498 && GET_MODE (SUBREG_REG (op)) == DImode)
2504 /* Darwin, AIX increases natural record alignment to doubleword if the first
2505 field is an FP double while the FP fields remain word aligned. */
2508 rs6000_special_round_type_align (tree type, int computed, int specified)
2510 tree field = TYPE_FIELDS (type);
2512 /* Skip all non field decls */
2513 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2514 field = TREE_CHAIN (field);
2516 if (field == NULL || field == type
2517 || TYPE_MODE (TREE_CODE (TREE_TYPE (field)) == ARRAY_TYPE
2518 ? get_inner_array_type (field)
2519 : TREE_TYPE (field)) != DFmode)
2520 return MAX (computed, specified);
2522 return MAX (MAX (computed, specified), 64);
2525 /* Return 1 for an operand in small memory on V.4/eabi. */
2528 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2529 enum machine_mode mode ATTRIBUTE_UNUSED)
2534 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2537 if (DEFAULT_ABI != ABI_V4)
2540 if (GET_CODE (op) == SYMBOL_REF)
2543 else if (GET_CODE (op) != CONST
2544 || GET_CODE (XEXP (op, 0)) != PLUS
2545 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2546 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2551 rtx sum = XEXP (op, 0);
2552 HOST_WIDE_INT summand;
2554 /* We have to be careful here, because it is the referenced address
2555 that must be 32k from _SDA_BASE_, not just the symbol. */
2556 summand = INTVAL (XEXP (sum, 1));
2557 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2560 sym_ref = XEXP (sum, 0);
2563 return SYMBOL_REF_SMALL_P (sym_ref);
2569 /* Return true if either operand is a general purpose register. */
2572 gpr_or_gpr_p (rtx op0, rtx op1)
2574 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2575 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2579 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2582 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2584 switch (GET_CODE (op))
2587 if (RS6000_SYMBOL_REF_TLS_P (op))
2589 else if (CONSTANT_POOL_ADDRESS_P (op))
2591 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2599 else if (! strcmp (XSTR (op, 0), toc_label_name))
2608 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2609 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2611 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2620 constant_pool_expr_p (rtx op)
2624 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2628 toc_relative_expr_p (rtx op)
2632 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2636 legitimate_constant_pool_address_p (rtx x)
2639 && GET_CODE (x) == PLUS
2640 && GET_CODE (XEXP (x, 0)) == REG
2641 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2642 && constant_pool_expr_p (XEXP (x, 1)));
2646 rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x)
2648 return (DEFAULT_ABI == ABI_V4
2649 && !flag_pic && !TARGET_TOC
2650 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2651 && small_data_operand (x, mode));
2654 /* SPE offset addressing is limited to 5-bits worth of double words. */
2655 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2658 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2660 unsigned HOST_WIDE_INT offset, extra;
2662 if (GET_CODE (x) != PLUS)
2664 if (GET_CODE (XEXP (x, 0)) != REG)
2666 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2668 if (legitimate_constant_pool_address_p (x))
2670 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2673 offset = INTVAL (XEXP (x, 1));
2681 /* AltiVec vector modes. Only reg+reg addressing is valid and
2682 constant offset zero should not occur due to canonicalization.
2683 Allow any offset when not strict before reload. */
2690 /* SPE vector modes. */
2691 return SPE_CONST_OFFSET_OK (offset);
2694 if (TARGET_E500_DOUBLE)
2695 return SPE_CONST_OFFSET_OK (offset);
2698 /* On e500v2, we may have:
2700 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2702 Which gets addressed with evldd instructions. */
2703 if (TARGET_E500_DOUBLE)
2704 return SPE_CONST_OFFSET_OK (offset);
2706 if (mode == DFmode || !TARGET_POWERPC64)
2708 else if (offset & 3)
2714 if (mode == TFmode || !TARGET_POWERPC64)
2716 else if (offset & 3)
2727 return (offset < 0x10000) && (offset + extra < 0x10000);
2731 legitimate_indexed_address_p (rtx x, int strict)
2735 if (GET_CODE (x) != PLUS)
2741 /* Recognize the rtl generated by reload which we know will later be
2742 replaced with proper base and index regs. */
2744 && reload_in_progress
2745 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2749 return (REG_P (op0) && REG_P (op1)
2750 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2751 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2752 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2753 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2757 legitimate_indirect_address_p (rtx x, int strict)
2759 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2763 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2765 if (!TARGET_MACHO || !flag_pic
2766 || mode != SImode || GET_CODE (x) != MEM)
2770 if (GET_CODE (x) != LO_SUM)
2772 if (GET_CODE (XEXP (x, 0)) != REG)
2774 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2778 return CONSTANT_P (x);
2782 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2784 if (GET_CODE (x) != LO_SUM)
2786 if (GET_CODE (XEXP (x, 0)) != REG)
2788 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2790 /* Restrict addressing for DI because of our SUBREG hackery. */
2791 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2795 if (TARGET_ELF || TARGET_MACHO)
2797 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2801 if (GET_MODE_NUNITS (mode) != 1)
2803 if (GET_MODE_BITSIZE (mode) > 64
2804 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2805 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2808 return CONSTANT_P (x);
2815 /* Try machine-dependent ways of modifying an illegitimate address
2816 to be legitimate. If we find one, return the new, valid address.
2817 This is used from only one place: `memory_address' in explow.c.
2819 OLDX is the address as it was before break_out_memory_refs was
2820 called. In some cases it is useful to look at this to decide what
2823 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2825 It is always safe for this function to do nothing. It exists to
2826 recognize opportunities to optimize the output.
2828 On RS/6000, first check for the sum of a register with a constant
2829 integer that is out of range. If so, generate code to add the
2830 constant with the low-order 16 bits masked to the register and force
2831 this result into another register (this can be done with `cau').
2832 Then generate an address of REG+(CONST&0xffff), allowing for the
2833 possibility of bit 16 being a one.
2835 Then check for the sum of a register and something not constant, try to
2836 load the other things into a register and return the sum. */
2839 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2840 enum machine_mode mode)
2842 if (GET_CODE (x) == SYMBOL_REF)
2844 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2846 return rs6000_legitimize_tls_address (x, model);
2849 if (GET_CODE (x) == PLUS
2850 && GET_CODE (XEXP (x, 0)) == REG
2851 && GET_CODE (XEXP (x, 1)) == CONST_INT
2852 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2854 HOST_WIDE_INT high_int, low_int;
2856 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2857 high_int = INTVAL (XEXP (x, 1)) - low_int;
2858 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2859 GEN_INT (high_int)), 0);
2860 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2862 else if (GET_CODE (x) == PLUS
2863 && GET_CODE (XEXP (x, 0)) == REG
2864 && GET_CODE (XEXP (x, 1)) != CONST_INT
2865 && GET_MODE_NUNITS (mode) == 1
2866 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2868 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2870 && (TARGET_POWERPC64 || mode != DImode)
2873 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2874 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2876 else if (ALTIVEC_VECTOR_MODE (mode))
2880 /* Make sure both operands are registers. */
2881 if (GET_CODE (x) == PLUS)
2882 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2883 force_reg (Pmode, XEXP (x, 1)));
2885 reg = force_reg (Pmode, x);
2888 else if (SPE_VECTOR_MODE (mode)
2889 || (TARGET_E500_DOUBLE && (mode == DFmode
2890 || mode == DImode)))
2894 /* We accept [reg + reg] and [reg + OFFSET]. */
2896 if (GET_CODE (x) == PLUS)
2898 rtx op1 = XEXP (x, 0);
2899 rtx op2 = XEXP (x, 1);
2901 op1 = force_reg (Pmode, op1);
2903 if (GET_CODE (op2) != REG
2904 && (GET_CODE (op2) != CONST_INT
2905 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2906 op2 = force_reg (Pmode, op2);
2908 return gen_rtx_PLUS (Pmode, op1, op2);
2911 return force_reg (Pmode, x);
2917 && GET_CODE (x) != CONST_INT
2918 && GET_CODE (x) != CONST_DOUBLE
2920 && GET_MODE_NUNITS (mode) == 1
2921 && (GET_MODE_BITSIZE (mode) <= 32
2922 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2924 rtx reg = gen_reg_rtx (Pmode);
2925 emit_insn (gen_elf_high (reg, x));
2926 return gen_rtx_LO_SUM (Pmode, reg, x);
2928 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2931 && ! MACHO_DYNAMIC_NO_PIC_P
2933 && GET_CODE (x) != CONST_INT
2934 && GET_CODE (x) != CONST_DOUBLE
2936 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2940 rtx reg = gen_reg_rtx (Pmode);
2941 emit_insn (gen_macho_high (reg, x));
2942 return gen_rtx_LO_SUM (Pmode, reg, x);
2945 && constant_pool_expr_p (x)
2946 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2948 return create_TOC_reference (x);
2954 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
2955 We need to emit DTP-relative relocations. */
2958 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2963 fputs ("\t.long\t", file);
2966 fputs (DOUBLE_INT_ASM_OP, file);
2971 output_addr_const (file, x);
2972 fputs ("@dtprel+0x8000", file);
2975 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2977 static GTY(()) rtx rs6000_tls_symbol;
2979 rs6000_tls_get_addr (void)
2981 if (!rs6000_tls_symbol)
2982 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2984 return rs6000_tls_symbol;
2987 /* Construct the SYMBOL_REF for TLS GOT references. */
2989 static GTY(()) rtx rs6000_got_symbol;
2991 rs6000_got_sym (void)
2993 if (!rs6000_got_symbol)
2995 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2996 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2997 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3000 return rs6000_got_symbol;
3003 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3004 this (thread-local) address. */
3007 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3011 dest = gen_reg_rtx (Pmode);
3012 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3018 tlsreg = gen_rtx_REG (Pmode, 13);
3019 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3023 tlsreg = gen_rtx_REG (Pmode, 2);
3024 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3028 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3032 tmp = gen_reg_rtx (Pmode);
3035 tlsreg = gen_rtx_REG (Pmode, 13);
3036 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3040 tlsreg = gen_rtx_REG (Pmode, 2);
3041 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3045 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3047 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3052 rtx r3, got, tga, tmp1, tmp2, eqv;
3054 /* We currently use relocations like @got@tlsgd for tls, which
3055 means the linker will handle allocation of tls entries, placing
3056 them in the .got section. So use a pointer to the .got section,
3057 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3058 or to secondary GOT sections used by 32-bit -fPIC. */
3060 got = gen_rtx_REG (Pmode, 2);
3064 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3067 rtx gsym = rs6000_got_sym ();
3068 got = gen_reg_rtx (Pmode);
3070 rs6000_emit_move (got, gsym, Pmode);
3073 rtx tempLR, tmp3, mem;
3076 tempLR = gen_reg_rtx (Pmode);
3077 tmp1 = gen_reg_rtx (Pmode);
3078 tmp2 = gen_reg_rtx (Pmode);
3079 tmp3 = gen_reg_rtx (Pmode);
3080 mem = gen_const_mem (Pmode, tmp1);
3082 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3083 emit_move_insn (tmp1, tempLR);
3084 emit_move_insn (tmp2, mem);
3085 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3086 last = emit_move_insn (got, tmp3);
3087 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3089 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3091 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3097 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3099 r3 = gen_rtx_REG (Pmode, 3);
3101 insn = gen_tls_gd_64 (r3, got, addr);
3103 insn = gen_tls_gd_32 (r3, got, addr);
3106 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3107 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3108 insn = emit_call_insn (insn);
3109 CONST_OR_PURE_CALL_P (insn) = 1;
3110 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3111 insn = get_insns ();
3113 emit_libcall_block (insn, dest, r3, addr);
3115 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3117 r3 = gen_rtx_REG (Pmode, 3);
3119 insn = gen_tls_ld_64 (r3, got);
3121 insn = gen_tls_ld_32 (r3, got);
3124 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3125 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3126 insn = emit_call_insn (insn);
3127 CONST_OR_PURE_CALL_P (insn) = 1;
3128 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3129 insn = get_insns ();
3131 tmp1 = gen_reg_rtx (Pmode);
3132 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3134 emit_libcall_block (insn, tmp1, r3, eqv);
3135 if (rs6000_tls_size == 16)
3138 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3140 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3142 else if (rs6000_tls_size == 32)
3144 tmp2 = gen_reg_rtx (Pmode);
3146 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3148 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3151 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3153 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3157 tmp2 = gen_reg_rtx (Pmode);
3159 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3161 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3163 insn = gen_rtx_SET (Pmode, dest,
3164 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3170 /* IE, or 64 bit offset LE. */
3171 tmp2 = gen_reg_rtx (Pmode);
3173 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3175 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3178 insn = gen_tls_tls_64 (dest, tmp2, addr);
3180 insn = gen_tls_tls_32 (dest, tmp2, addr);
3188 /* Return 1 if X contains a thread-local symbol. */
3191 rs6000_tls_referenced_p (rtx x)
3193 if (! TARGET_HAVE_TLS)
3196 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3199 /* Return 1 if *X is a thread-local symbol. This is the same as
3200 rs6000_tls_symbol_ref except for the type of the unused argument. */
3203 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3205 return RS6000_SYMBOL_REF_TLS_P (*x);
3208 /* The convention appears to be to define this wherever it is used.
3209 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3210 is now used here. */
3211 #ifndef REG_MODE_OK_FOR_BASE_P
3212 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3215 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3216 replace the input X, or the original X if no replacement is called for.
3217 The output parameter *WIN is 1 if the calling macro should goto WIN,
3220 For RS/6000, we wish to handle large displacements off a base
3221 register by splitting the addend across an addiu/addis and the mem insn.
3222 This cuts number of extra insns needed from 3 to 1.
3224 On Darwin, we use this to generate code for floating point constants.
3225 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3226 The Darwin code is inside #if TARGET_MACHO because only then is
3227 machopic_function_base_name() defined. */
3229 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3230 int opnum, int type,
3231 int ind_levels ATTRIBUTE_UNUSED, int *win)
3233 /* We must recognize output that we have already generated ourselves. */
3234 if (GET_CODE (x) == PLUS
3235 && GET_CODE (XEXP (x, 0)) == PLUS
3236 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3237 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3238 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3240 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3241 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3242 opnum, (enum reload_type)type);
3248 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3249 && GET_CODE (x) == LO_SUM
3250 && GET_CODE (XEXP (x, 0)) == PLUS
3251 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3252 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3253 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3254 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3255 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3256 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3257 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3259 /* Result of previous invocation of this function on Darwin
3260 floating point constant. */
3261 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3262 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3263 opnum, (enum reload_type)type);
3269 /* Force ld/std non-word aligned offset into base register by wrapping
3271 if (GET_CODE (x) == PLUS
3272 && GET_CODE (XEXP (x, 0)) == REG
3273 && REGNO (XEXP (x, 0)) < 32
3274 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3275 && GET_CODE (XEXP (x, 1)) == CONST_INT
3276 && (INTVAL (XEXP (x, 1)) & 3) != 0
3277 && !ALTIVEC_VECTOR_MODE (mode)
3278 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3279 && TARGET_POWERPC64)
3281 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3282 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3283 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3284 opnum, (enum reload_type) type);
3289 if (GET_CODE (x) == PLUS
3290 && GET_CODE (XEXP (x, 0)) == REG
3291 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3292 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3293 && GET_CODE (XEXP (x, 1)) == CONST_INT
3294 && !SPE_VECTOR_MODE (mode)
3295 && !(TARGET_E500_DOUBLE && (mode == DFmode
3297 && !ALTIVEC_VECTOR_MODE (mode))
3299 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3300 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3302 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3304 /* Check for 32-bit overflow. */
3305 if (high + low != val)
3311 /* Reload the high part into a base reg; leave the low part
3312 in the mem directly. */
3314 x = gen_rtx_PLUS (GET_MODE (x),
3315 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3319 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3320 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3321 opnum, (enum reload_type)type);
3326 if (GET_CODE (x) == SYMBOL_REF
3327 && !ALTIVEC_VECTOR_MODE (mode)
3329 && DEFAULT_ABI == ABI_DARWIN
3330 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3332 && DEFAULT_ABI == ABI_V4
3335 /* Don't do this for TFmode, since the result isn't offsettable.
3336 The same goes for DImode without 64-bit gprs. */
3338 && (mode != DImode || TARGET_POWERPC64))
3343 rtx offset = gen_rtx_CONST (Pmode,
3344 gen_rtx_MINUS (Pmode, x,
3345 machopic_function_base_sym ()));
3346 x = gen_rtx_LO_SUM (GET_MODE (x),
3347 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3348 gen_rtx_HIGH (Pmode, offset)), offset);
3352 x = gen_rtx_LO_SUM (GET_MODE (x),
3353 gen_rtx_HIGH (Pmode, x), x);
3355 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3356 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3357 opnum, (enum reload_type)type);
3362 /* Reload an offset address wrapped by an AND that represents the
3363 masking of the lower bits. Strip the outer AND and let reload
3364 convert the offset address into an indirect address. */
3366 && ALTIVEC_VECTOR_MODE (mode)
3367 && GET_CODE (x) == AND
3368 && GET_CODE (XEXP (x, 0)) == PLUS
3369 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3370 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3371 && GET_CODE (XEXP (x, 1)) == CONST_INT
3372 && INTVAL (XEXP (x, 1)) == -16)
3380 && constant_pool_expr_p (x)
3381 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3383 (x) = create_TOC_reference (x);
3391 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3392 that is a valid memory address for an instruction.
3393 The MODE argument is the machine mode for the MEM expression
3394 that wants to use this address.
3396 On the RS/6000, there are four valid address: a SYMBOL_REF that
3397 refers to a constant pool entry of an address (or the sum of it
3398 plus a constant), a short (16-bit signed) constant plus a register,
3399 the sum of two registers, or a register indirect, possibly with an
3400 auto-increment. For DFmode and DImode with a constant plus register,
3401 we must ensure that both words are addressable or PowerPC64 with offset
3404 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3405 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3406 adjacent memory cells are accessed by adding word-sized offsets
3407 during assembly output. */
3409 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3411 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3413 && ALTIVEC_VECTOR_MODE (mode)
3414 && GET_CODE (x) == AND
3415 && GET_CODE (XEXP (x, 1)) == CONST_INT
3416 && INTVAL (XEXP (x, 1)) == -16)
3419 if (RS6000_SYMBOL_REF_TLS_P (x))
3421 if (legitimate_indirect_address_p (x, reg_ok_strict))
3423 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3424 && !ALTIVEC_VECTOR_MODE (mode)
3425 && !SPE_VECTOR_MODE (mode)
3426 /* Restrict addressing for DI because of our SUBREG hackery. */
3427 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3429 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3431 if (rs6000_legitimate_small_data_p (mode, x))
3433 if (legitimate_constant_pool_address_p (x))
3435 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3437 && GET_CODE (x) == PLUS
3438 && GET_CODE (XEXP (x, 0)) == REG
3439 && (XEXP (x, 0) == virtual_stack_vars_rtx
3440 || XEXP (x, 0) == arg_pointer_rtx)
3441 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3443 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3447 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3449 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3450 && (TARGET_POWERPC64 || mode != DImode)
3451 && legitimate_indexed_address_p (x, reg_ok_strict))
3453 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3458 /* Go to LABEL if ADDR (a legitimate address expression)
3459 has an effect that depends on the machine mode it is used for.
3461 On the RS/6000 this is true of all integral offsets (since AltiVec
3462 modes don't allow them) or is a pre-increment or decrement.
3464 ??? Except that due to conceptual problems in offsettable_address_p
3465 we can't really report the problems of integral offsets. So leave
3466 this assuming that the adjustable offset must be valid for the
3467 sub-words of a TFmode operand, which is what we had before. */
3470 rs6000_mode_dependent_address (rtx addr)
3472 switch (GET_CODE (addr))
3475 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3477 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3478 return val + 12 + 0x8000 >= 0x10000;
3487 return TARGET_UPDATE;
3496 /* Return number of consecutive hard regs needed starting at reg REGNO
3497 to hold something of mode MODE.
3498 This is ordinarily the length in words of a value of mode MODE
3499 but can be less for certain modes in special long registers.
3501 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3502 scalar instructions. The upper 32 bits are only available to the
3505 POWER and PowerPC GPRs hold 32 bits worth;
3506 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3509 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3511 if (FP_REGNO_P (regno))
3512 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3514 if (TARGET_E500_DOUBLE && mode == DFmode)
3517 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3518 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3520 if (ALTIVEC_REGNO_P (regno))
3522 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3524 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3527 /* Change register usage conditional on target flags. */
3529 rs6000_conditional_register_usage (void)
3533 /* Set MQ register fixed (already call_used) if not POWER
3534 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3539 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3541 fixed_regs[13] = call_used_regs[13]
3542 = call_really_used_regs[13] = 1;
3544 /* Conditionally disable FPRs. */
3545 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3546 for (i = 32; i < 64; i++)
3547 fixed_regs[i] = call_used_regs[i]
3548 = call_really_used_regs[i] = 1;
3550 /* The TOC register is not killed across calls in a way that is
3551 visible to the compiler. */
3552 if (DEFAULT_ABI == ABI_AIX)
3553 call_really_used_regs[2] = 0;
3555 if (DEFAULT_ABI == ABI_V4
3556 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3558 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3560 if (DEFAULT_ABI == ABI_V4
3561 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3563 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3564 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3565 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3567 if (DEFAULT_ABI == ABI_DARWIN
3568 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3569 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3570 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3571 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3573 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3574 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3575 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3578 global_regs[VSCR_REGNO] = 1;
3582 global_regs[SPEFSCR_REGNO] = 1;
3583 fixed_regs[FIXED_SCRATCH]
3584 = call_used_regs[FIXED_SCRATCH]
3585 = call_really_used_regs[FIXED_SCRATCH] = 1;
3588 if (! TARGET_ALTIVEC)
3590 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3591 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3592 call_really_used_regs[VRSAVE_REGNO] = 1;
3595 if (TARGET_ALTIVEC_ABI)
3596 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3597 call_used_regs[i] = call_really_used_regs[i] = 1;
3600 /* Try to output insns to set TARGET equal to the constant C if it can
3601 be done in less than N insns. Do all computations in MODE.
3602 Returns the place where the output has been placed if it can be
3603 done and the insns have been emitted. If it would take more than N
3604 insns, zero is returned and no insns and emitted. */
3607 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3608 rtx source, int n ATTRIBUTE_UNUSED)
3610 rtx result, insn, set;
3611 HOST_WIDE_INT c0, c1;
3618 dest = gen_reg_rtx (mode);
3619 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3623 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3625 emit_insn (gen_rtx_SET (VOIDmode, result,
3626 GEN_INT (INTVAL (source)
3627 & (~ (HOST_WIDE_INT) 0xffff))));
3628 emit_insn (gen_rtx_SET (VOIDmode, dest,
3629 gen_rtx_IOR (SImode, result,
3630 GEN_INT (INTVAL (source) & 0xffff))));
3635 switch (GET_CODE (source))
3638 c0 = INTVAL (source);
3643 #if HOST_BITS_PER_WIDE_INT >= 64
3644 c0 = CONST_DOUBLE_LOW (source);
3647 c0 = CONST_DOUBLE_LOW (source);
3648 c1 = CONST_DOUBLE_HIGH (source);
3656 result = rs6000_emit_set_long_const (dest, c0, c1);
3663 insn = get_last_insn ();
3664 set = single_set (insn);
3665 if (! CONSTANT_P (SET_SRC (set)))
3666 set_unique_reg_note (insn, REG_EQUAL, source);
3671 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3672 fall back to a straight forward decomposition. We do this to avoid
3673 exponential run times encountered when looking for longer sequences
3674 with rs6000_emit_set_const. */
3676 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3678 if (!TARGET_POWERPC64)
3680 rtx operand1, operand2;
3682 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3684 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3686 emit_move_insn (operand1, GEN_INT (c1));
3687 emit_move_insn (operand2, GEN_INT (c2));
3691 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3694 ud2 = (c1 & 0xffff0000) >> 16;
3695 #if HOST_BITS_PER_WIDE_INT >= 64
3699 ud4 = (c2 & 0xffff0000) >> 16;
3701 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3702 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3705 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3707 emit_move_insn (dest, GEN_INT (ud1));
3710 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3711 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3714 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3717 emit_move_insn (dest, GEN_INT (ud2 << 16));
3719 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3721 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3722 || (ud4 == 0 && ! (ud3 & 0x8000)))
3725 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3728 emit_move_insn (dest, GEN_INT (ud3 << 16));
3731 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3732 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3734 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3739 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3742 emit_move_insn (dest, GEN_INT (ud4 << 16));
3745 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3747 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3749 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3750 GEN_INT (ud2 << 16)));
3752 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3758 /* Helper for the following. Get rid of [r+r] memory refs
3759 in cases where it won't work (TImode, TFmode). */
3762 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3764 if (GET_CODE (operands[0]) == MEM
3765 && GET_CODE (XEXP (operands[0], 0)) != REG
3766 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3767 && ! reload_in_progress)
3769 = replace_equiv_address (operands[0],
3770 copy_addr_to_reg (XEXP (operands[0], 0)));
3772 if (GET_CODE (operands[1]) == MEM
3773 && GET_CODE (XEXP (operands[1], 0)) != REG
3774 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3775 && ! reload_in_progress)
3777 = replace_equiv_address (operands[1],
3778 copy_addr_to_reg (XEXP (operands[1], 0)));
3781 /* Emit a move from SOURCE to DEST in mode MODE. */
3783 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3787 operands[1] = source;
3789 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3790 if (GET_CODE (operands[1]) == CONST_DOUBLE
3791 && ! FLOAT_MODE_P (mode)
3792 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3794 /* FIXME. This should never happen. */
3795 /* Since it seems that it does, do the safe thing and convert
3797 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3799 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3800 || FLOAT_MODE_P (mode)
3801 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3802 || CONST_DOUBLE_LOW (operands[1]) < 0)
3803 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3804 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3806 /* Check if GCC is setting up a block move that will end up using FP
3807 registers as temporaries. We must make sure this is acceptable. */
3808 if (GET_CODE (operands[0]) == MEM
3809 && GET_CODE (operands[1]) == MEM
3811 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3812 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3813 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3814 ? 32 : MEM_ALIGN (operands[0])))
3815 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3817 : MEM_ALIGN (operands[1]))))
3818 && ! MEM_VOLATILE_P (operands [0])
3819 && ! MEM_VOLATILE_P (operands [1]))
3821 emit_move_insn (adjust_address (operands[0], SImode, 0),
3822 adjust_address (operands[1], SImode, 0));
3823 emit_move_insn (adjust_address (operands[0], SImode, 4),
3824 adjust_address (operands[1], SImode, 4));
3828 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3829 && !gpc_reg_operand (operands[1], mode))
3830 operands[1] = force_reg (mode, operands[1]);
3832 if (mode == SFmode && ! TARGET_POWERPC
3833 && TARGET_HARD_FLOAT && TARGET_FPRS
3834 && GET_CODE (operands[0]) == MEM)
3838 if (reload_in_progress || reload_completed)
3839 regnum = true_regnum (operands[1]);
3840 else if (GET_CODE (operands[1]) == REG)
3841 regnum = REGNO (operands[1]);
3845 /* If operands[1] is a register, on POWER it may have
3846 double-precision data in it, so truncate it to single
3848 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3851 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3852 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3853 operands[1] = newreg;
3857 /* Recognize the case where operand[1] is a reference to thread-local
3858 data and load its address to a register. */
3859 if (rs6000_tls_referenced_p (operands[1]))
3861 enum tls_model model;
3862 rtx tmp = operands[1];
3865 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3867 addend = XEXP (XEXP (tmp, 0), 1);
3868 tmp = XEXP (XEXP (tmp, 0), 0);
3871 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3872 model = SYMBOL_REF_TLS_MODEL (tmp);
3873 gcc_assert (model != 0);
3875 tmp = rs6000_legitimize_tls_address (tmp, model);
3878 tmp = gen_rtx_PLUS (mode, tmp, addend);
3879 tmp = force_operand (tmp, operands[0]);
3884 /* Handle the case where reload calls us with an invalid address. */
3885 if (reload_in_progress && mode == Pmode
3886 && (! general_operand (operands[1], mode)
3887 || ! nonimmediate_operand (operands[0], mode)))
3890 /* 128-bit constant floating-point values on Darwin should really be
3891 loaded as two parts. */
3892 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3893 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3894 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3896 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3897 know how to get a DFmode SUBREG of a TFmode. */
3898 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3899 simplify_gen_subreg (DImode, operands[1], mode, 0),
3901 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3902 GET_MODE_SIZE (DImode)),
3903 simplify_gen_subreg (DImode, operands[1], mode,
3904 GET_MODE_SIZE (DImode)),
3909 /* FIXME: In the long term, this switch statement should go away
3910 and be replaced by a sequence of tests based on things like
3916 if (CONSTANT_P (operands[1])
3917 && GET_CODE (operands[1]) != CONST_INT)
3918 operands[1] = force_const_mem (mode, operands[1]);
3922 rs6000_eliminate_indexed_memrefs (operands);
3927 if (CONSTANT_P (operands[1])
3928 && ! easy_fp_constant (operands[1], mode))
3929 operands[1] = force_const_mem (mode, operands[1]);
3940 if (CONSTANT_P (operands[1])
3941 && !easy_vector_constant (operands[1], mode))
3942 operands[1] = force_const_mem (mode, operands[1]);
3947 /* Use default pattern for address of ELF small data */
3950 && DEFAULT_ABI == ABI_V4
3951 && (GET_CODE (operands[1]) == SYMBOL_REF
3952 || GET_CODE (operands[1]) == CONST)
3953 && small_data_operand (operands[1], mode))
3955 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3959 if (DEFAULT_ABI == ABI_V4
3960 && mode == Pmode && mode == SImode
3961 && flag_pic == 1 && got_operand (operands[1], mode))
3963 emit_insn (gen_movsi_got (operands[0], operands[1]));
3967 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3971 && CONSTANT_P (operands[1])
3972 && GET_CODE (operands[1]) != HIGH
3973 && GET_CODE (operands[1]) != CONST_INT)
3975 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3977 /* If this is a function address on -mcall-aixdesc,
3978 convert it to the address of the descriptor. */
3979 if (DEFAULT_ABI == ABI_AIX
3980 && GET_CODE (operands[1]) == SYMBOL_REF
3981 && XSTR (operands[1], 0)[0] == '.')
3983 const char *name = XSTR (operands[1], 0);
3985 while (*name == '.')
3987 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3988 CONSTANT_POOL_ADDRESS_P (new_ref)
3989 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3990 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3991 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3992 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3993 operands[1] = new_ref;
3996 if (DEFAULT_ABI == ABI_DARWIN)
3999 if (MACHO_DYNAMIC_NO_PIC_P)
4001 /* Take care of any required data indirection. */
4002 operands[1] = rs6000_machopic_legitimize_pic_address (
4003 operands[1], mode, operands[0]);
4004 if (operands[0] != operands[1])
4005 emit_insn (gen_rtx_SET (VOIDmode,
4006 operands[0], operands[1]));
4010 emit_insn (gen_macho_high (target, operands[1]));
4011 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4015 emit_insn (gen_elf_high (target, operands[1]));
4016 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4020 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4021 and we have put it in the TOC, we just need to make a TOC-relative
4024 && GET_CODE (operands[1]) == SYMBOL_REF
4025 && constant_pool_expr_p (operands[1])
4026 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4027 get_pool_mode (operands[1])))
4029 operands[1] = create_TOC_reference (operands[1]);
4031 else if (mode == Pmode
4032 && CONSTANT_P (operands[1])
4033 && ((GET_CODE (operands[1]) != CONST_INT
4034 && ! easy_fp_constant (operands[1], mode))
4035 || (GET_CODE (operands[1]) == CONST_INT
4036 && num_insns_constant (operands[1], mode) > 2)
4037 || (GET_CODE (operands[0]) == REG
4038 && FP_REGNO_P (REGNO (operands[0]))))
4039 && GET_CODE (operands[1]) != HIGH
4040 && ! legitimate_constant_pool_address_p (operands[1])
4041 && ! toc_relative_expr_p (operands[1]))
4043 /* Emit a USE operation so that the constant isn't deleted if
4044 expensive optimizations are turned on because nobody
4045 references it. This should only be done for operands that
4046 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4047 This should not be done for operands that contain LABEL_REFs.
4048 For now, we just handle the obvious case. */
4049 if (GET_CODE (operands[1]) != LABEL_REF)
4050 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4053 /* Darwin uses a special PIC legitimizer. */
4054 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4057 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4059 if (operands[0] != operands[1])
4060 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4065 /* If we are to limit the number of things we put in the TOC and
4066 this is a symbol plus a constant we can add in one insn,
4067 just put the symbol in the TOC and add the constant. Don't do
4068 this if reload is in progress. */
4069 if (GET_CODE (operands[1]) == CONST
4070 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4071 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4072 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4073 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4074 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4075 && ! side_effects_p (operands[0]))
4078 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4079 rtx other = XEXP (XEXP (operands[1], 0), 1);
4081 sym = force_reg (mode, sym);
4083 emit_insn (gen_addsi3 (operands[0], sym, other));
4085 emit_insn (gen_adddi3 (operands[0], sym, other));
4089 operands[1] = force_const_mem (mode, operands[1]);
4092 && constant_pool_expr_p (XEXP (operands[1], 0))
4093 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4094 get_pool_constant (XEXP (operands[1], 0)),
4095 get_pool_mode (XEXP (operands[1], 0))))
4098 = gen_const_mem (mode,
4099 create_TOC_reference (XEXP (operands[1], 0)));
4100 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4106 rs6000_eliminate_indexed_memrefs (operands);
4110 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4112 gen_rtx_SET (VOIDmode,
4113 operands[0], operands[1]),
4114 gen_rtx_CLOBBER (VOIDmode,
4115 gen_rtx_SCRATCH (SImode)))));
4124 /* Above, we may have called force_const_mem which may have returned
4125 an invalid address. If we can, fix this up; otherwise, reload will
4126 have to deal with it. */
4127 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4128 operands[1] = validize_mem (operands[1]);
4131 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4134 /* Nonzero if we can use a floating-point register to pass this arg. */
4135 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4136 (SCALAR_FLOAT_MODE_P (MODE) \
4137 && (CUM)->fregno <= FP_ARG_MAX_REG \
4138 && TARGET_HARD_FLOAT && TARGET_FPRS)
4140 /* Nonzero if we can use an AltiVec register to pass this arg. */
4141 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4142 (ALTIVEC_VECTOR_MODE (MODE) \
4143 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4144 && TARGET_ALTIVEC_ABI \
4147 /* Return a nonzero value to say to return the function value in
4148 memory, just as large structures are always returned. TYPE will be
4149 the data type of the value, and FNTYPE will be the type of the
4150 function doing the returning, or @code{NULL} for libcalls.
4152 The AIX ABI for the RS/6000 specifies that all structures are
4153 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4154 specifies that structures <= 8 bytes are returned in r3/r4, but a
4155 draft put them in memory, and GCC used to implement the draft
4156 instead of the final standard. Therefore, aix_struct_return
4157 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4158 compatibility can change DRAFT_V4_STRUCT_RET to override the
4159 default, and -m switches get the final word. See
4160 rs6000_override_options for more details.
4162 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4163 long double support is enabled. These values are returned in memory.
4165 int_size_in_bytes returns -1 for variable size objects, which go in
4166 memory always. The cast to unsigned makes -1 > 8. */
4169 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4171 /* In the darwin64 abi, try to use registers for larger structs
4173 if (rs6000_darwin64_abi
4174 && TREE_CODE (type) == RECORD_TYPE
4175 && int_size_in_bytes (type) > 0)
4177 CUMULATIVE_ARGS valcum;
4181 valcum.fregno = FP_ARG_MIN_REG;
4182 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4183 /* Do a trial code generation as if this were going to be passed
4184 as an argument; if any part goes in memory, we return NULL. */
4185 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4188 /* Otherwise fall through to more conventional ABI rules. */
4191 if (AGGREGATE_TYPE_P (type)
4192 && (aix_struct_return
4193 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4196 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4197 modes only exist for GCC vector types if -maltivec. */
4198 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4199 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4202 /* Return synthetic vectors in memory. */
4203 if (TREE_CODE (type) == VECTOR_TYPE
4204 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4206 static bool warned_for_return_big_vectors = false;
4207 if (!warned_for_return_big_vectors)
4209 warning (0, "GCC vector returned by reference: "
4210 "non-standard ABI extension with no compatibility guarantee");
4211 warned_for_return_big_vectors = true;
4216 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4222 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4223 for a call to a function whose data type is FNTYPE.
4224 For a library call, FNTYPE is 0.
4226 For incoming args we set the number of arguments in the prototype large
4227 so we never return a PARALLEL. */
4230 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4231 rtx libname ATTRIBUTE_UNUSED, int incoming,
4232 int libcall, int n_named_args)
4234 static CUMULATIVE_ARGS zero_cumulative;
4236 *cum = zero_cumulative;
4238 cum->fregno = FP_ARG_MIN_REG;
4239 cum->vregno = ALTIVEC_ARG_MIN_REG;
4240 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4241 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4242 ? CALL_LIBCALL : CALL_NORMAL);
4243 cum->sysv_gregno = GP_ARG_MIN_REG;
4244 cum->stdarg = fntype
4245 && (TYPE_ARG_TYPES (fntype) != 0
4246 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4247 != void_type_node));
4249 cum->nargs_prototype = 0;
4250 if (incoming || cum->prototype)
4251 cum->nargs_prototype = n_named_args;
4253 /* Check for a longcall attribute. */
4254 if ((!fntype && rs6000_default_long_calls)
4256 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4257 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4258 cum->call_cookie |= CALL_LONG;
4260 if (TARGET_DEBUG_ARG)
4262 fprintf (stderr, "\ninit_cumulative_args:");
4265 tree ret_type = TREE_TYPE (fntype);
4266 fprintf (stderr, " ret code = %s,",
4267 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4270 if (cum->call_cookie & CALL_LONG)
4271 fprintf (stderr, " longcall,");
4273 fprintf (stderr, " proto = %d, nargs = %d\n",
4274 cum->prototype, cum->nargs_prototype);
4279 && TARGET_ALTIVEC_ABI
4280 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4282 error ("cannot return value in vector register because"
4283 " altivec instructions are disabled, use -maltivec"
4288 /* Return true if TYPE must be passed on the stack and not in registers. */
4291 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4293 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4294 return must_pass_in_stack_var_size (mode, type);
4296 return must_pass_in_stack_var_size_or_pad (mode, type);
4299 /* If defined, a C expression which determines whether, and in which
4300 direction, to pad out an argument with extra space. The value
4301 should be of type `enum direction': either `upward' to pad above
4302 the argument, `downward' to pad below, or `none' to inhibit
4305 For the AIX ABI structs are always stored left shifted in their
4309 function_arg_padding (enum machine_mode mode, tree type)
4311 #ifndef AGGREGATE_PADDING_FIXED
4312 #define AGGREGATE_PADDING_FIXED 0
4314 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4315 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4318 if (!AGGREGATE_PADDING_FIXED)
4320 /* GCC used to pass structures of the same size as integer types as
4321 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4322 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4323 passed padded downward, except that -mstrict-align further
4324 muddied the water in that multi-component structures of 2 and 4
4325 bytes in size were passed padded upward.
4327 The following arranges for best compatibility with previous
4328 versions of gcc, but removes the -mstrict-align dependency. */
4329 if (BYTES_BIG_ENDIAN)
4331 HOST_WIDE_INT size = 0;
4333 if (mode == BLKmode)
4335 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4336 size = int_size_in_bytes (type);
4339 size = GET_MODE_SIZE (mode);
4341 if (size == 1 || size == 2 || size == 4)
4347 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4349 if (type != 0 && AGGREGATE_TYPE_P (type))
4353 /* Fall back to the default. */
4354 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4357 /* If defined, a C expression that gives the alignment boundary, in bits,
4358 of an argument with the specified mode and type. If it is not defined,
4359 PARM_BOUNDARY is used for all arguments.
4361 V.4 wants long longs to be double word aligned.
4362 Doubleword align SPE vectors.
4363 Quadword align Altivec vectors.
4364 Quadword align large synthetic vector types. */
4367 function_arg_boundary (enum machine_mode mode, tree type)
4369 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4371 else if (SPE_VECTOR_MODE (mode)
4372 || (type && TREE_CODE (type) == VECTOR_TYPE
4373 && int_size_in_bytes (type) >= 8
4374 && int_size_in_bytes (type) < 16))
4376 else if (ALTIVEC_VECTOR_MODE (mode)
4377 || (type && TREE_CODE (type) == VECTOR_TYPE
4378 && int_size_in_bytes (type) >= 16))
4380 else if (rs6000_darwin64_abi && mode == BLKmode
4381 && type && TYPE_ALIGN (type) > 64)
4384 return PARM_BOUNDARY;
4387 /* For a function parm of MODE and TYPE, return the starting word in
4388 the parameter area. NWORDS of the parameter area are already used. */
4391 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4394 unsigned int parm_offset;
4396 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4397 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4398 return nwords + (-(parm_offset + nwords) & align);
4401 /* Compute the size (in words) of a function argument. */
4403 static unsigned long
4404 rs6000_arg_size (enum machine_mode mode, tree type)
4408 if (mode != BLKmode)
4409 size = GET_MODE_SIZE (mode);
4411 size = int_size_in_bytes (type);
4414 return (size + 3) >> 2;
4416 return (size + 7) >> 3;
4419 /* Use this to flush pending int fields. */
4422 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4423 HOST_WIDE_INT bitpos)
4425 unsigned int startbit, endbit;
4426 int intregs, intoffset;
4427 enum machine_mode mode;
4429 if (cum->intoffset == -1)
4432 intoffset = cum->intoffset;
4433 cum->intoffset = -1;
4435 if (intoffset % BITS_PER_WORD != 0)
4437 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4439 if (mode == BLKmode)
4441 /* We couldn't find an appropriate mode, which happens,
4442 e.g., in packed structs when there are 3 bytes to load.
4443 Back intoffset back to the beginning of the word in this
4445 intoffset = intoffset & -BITS_PER_WORD;
4449 startbit = intoffset & -BITS_PER_WORD;
4450 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4451 intregs = (endbit - startbit) / BITS_PER_WORD;
4452 cum->words += intregs;
4455 /* The darwin64 ABI calls for us to recurse down through structs,
4456 looking for elements passed in registers. Unfortunately, we have
4457 to track int register count here also because of misalignments
4458 in powerpc alignment mode. */
4461 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4463 HOST_WIDE_INT startbitpos)
4467 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4468 if (TREE_CODE (f) == FIELD_DECL)
4470 HOST_WIDE_INT bitpos = startbitpos;
4471 tree ftype = TREE_TYPE (f);
4472 enum machine_mode mode = TYPE_MODE (ftype);
4474 if (DECL_SIZE (f) != 0
4475 && host_integerp (bit_position (f), 1))
4476 bitpos += int_bit_position (f);
4478 /* ??? FIXME: else assume zero offset. */
4480 if (TREE_CODE (ftype) == RECORD_TYPE)
4481 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4482 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4484 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4485 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4486 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4488 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4490 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4494 else if (cum->intoffset == -1)
4495 cum->intoffset = bitpos;
4499 /* Update the data in CUM to advance over an argument
4500 of mode MODE and data type TYPE.
4501 (TYPE is null for libcalls where that information may not be available.)
4503 Note that for args passed by reference, function_arg will be called
4504 with MODE and TYPE set to that of the pointer to the arg, not the arg
4508 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4509 tree type, int named, int depth)
4513 /* Only tick off an argument if we're not recursing. */
4515 cum->nargs_prototype--;
4517 if (TARGET_ALTIVEC_ABI
4518 && (ALTIVEC_VECTOR_MODE (mode)
4519 || (type && TREE_CODE (type) == VECTOR_TYPE
4520 && int_size_in_bytes (type) == 16)))
4524 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4527 if (!TARGET_ALTIVEC)
4528 error ("cannot pass argument in vector register because"
4529 " altivec instructions are disabled, use -maltivec"
4532 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4533 even if it is going to be passed in a vector register.
4534 Darwin does the same for variable-argument functions. */
4535 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4536 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4546 /* Vector parameters must be 16-byte aligned. This places
4547 them at 2 mod 4 in terms of words in 32-bit mode, since
4548 the parameter save area starts at offset 24 from the
4549 stack. In 64-bit mode, they just have to start on an
4550 even word, since the parameter save area is 16-byte
4551 aligned. Space for GPRs is reserved even if the argument
4552 will be passed in memory. */
4554 align = (2 - cum->words) & 3;
4556 align = cum->words & 1;
4557 cum->words += align + rs6000_arg_size (mode, type);
4559 if (TARGET_DEBUG_ARG)
4561 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4563 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4564 cum->nargs_prototype, cum->prototype,
4565 GET_MODE_NAME (mode));
4569 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4571 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4574 else if (rs6000_darwin64_abi
4576 && TREE_CODE (type) == RECORD_TYPE
4577 && (size = int_size_in_bytes (type)) > 0)
4579 /* Variable sized types have size == -1 and are
4580 treated as if consisting entirely of ints.
4581 Pad to 16 byte boundary if needed. */
4582 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4583 && (cum->words % 2) != 0)
4585 /* For varargs, we can just go up by the size of the struct. */
4587 cum->words += (size + 7) / 8;
4590 /* It is tempting to say int register count just goes up by
4591 sizeof(type)/8, but this is wrong in a case such as
4592 { int; double; int; } [powerpc alignment]. We have to
4593 grovel through the fields for these too. */
4595 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4596 rs6000_darwin64_record_arg_advance_flush (cum,
4597 size * BITS_PER_UNIT);
4600 else if (DEFAULT_ABI == ABI_V4)
4602 if (TARGET_HARD_FLOAT && TARGET_FPRS
4603 && (mode == SFmode || mode == DFmode))
4605 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4610 cum->words += cum->words & 1;
4611 cum->words += rs6000_arg_size (mode, type);
4616 int n_words = rs6000_arg_size (mode, type);
4617 int gregno = cum->sysv_gregno;
4619 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4620 (r7,r8) or (r9,r10). As does any other 2 word item such
4621 as complex int due to a historical mistake. */
4623 gregno += (1 - gregno) & 1;
4625 /* Multi-reg args are not split between registers and stack. */
4626 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4628 /* Long long and SPE vectors are aligned on the stack.
4629 So are other 2 word items such as complex int due to
4630 a historical mistake. */
4632 cum->words += cum->words & 1;
4633 cum->words += n_words;
4636 /* Note: continuing to accumulate gregno past when we've started
4637 spilling to the stack indicates the fact that we've started
4638 spilling to the stack to expand_builtin_saveregs. */
4639 cum->sysv_gregno = gregno + n_words;
4642 if (TARGET_DEBUG_ARG)
4644 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4645 cum->words, cum->fregno);
4646 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4647 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4648 fprintf (stderr, "mode = %4s, named = %d\n",
4649 GET_MODE_NAME (mode), named);
4654 int n_words = rs6000_arg_size (mode, type);
4655 int start_words = cum->words;
4656 int align_words = rs6000_parm_start (mode, type, start_words);
4658 cum->words = align_words + n_words;
4660 if (SCALAR_FLOAT_MODE_P (mode)
4661 && TARGET_HARD_FLOAT && TARGET_FPRS)
4662 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4664 if (TARGET_DEBUG_ARG)
4666 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4667 cum->words, cum->fregno);
4668 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4669 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4670 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4671 named, align_words - start_words, depth);
4677 spe_build_register_parallel (enum machine_mode mode, int gregno)
4684 r1 = gen_rtx_REG (DImode, gregno);
4685 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4686 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4689 r1 = gen_rtx_REG (DImode, gregno);
4690 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4691 r3 = gen_rtx_REG (DImode, gregno + 2);
4692 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4693 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4700 /* Determine where to put a SIMD argument on the SPE. */
4702 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4705 int gregno = cum->sysv_gregno;
4707 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4708 are passed and returned in a pair of GPRs for ABI compatibility. */
4709 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4711 int n_words = rs6000_arg_size (mode, type);
4713 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4715 gregno += (1 - gregno) & 1;
4717 /* Multi-reg args are not split between registers and stack. */
4718 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4721 return spe_build_register_parallel (mode, gregno);
4725 int n_words = rs6000_arg_size (mode, type);
4727 /* SPE vectors are put in odd registers. */
4728 if (n_words == 2 && (gregno & 1) == 0)
4731 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4734 enum machine_mode m = SImode;
4736 r1 = gen_rtx_REG (m, gregno);
4737 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4738 r2 = gen_rtx_REG (m, gregno + 1);
4739 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4740 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4747 if (gregno <= GP_ARG_MAX_REG)
4748 return gen_rtx_REG (mode, gregno);
4754 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4755 structure between cum->intoffset and bitpos to integer registers. */
4758 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4759 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4761 enum machine_mode mode;
4763 unsigned int startbit, endbit;
4764 int this_regno, intregs, intoffset;
4767 if (cum->intoffset == -1)
4770 intoffset = cum->intoffset;
4771 cum->intoffset = -1;
4773 /* If this is the trailing part of a word, try to only load that
4774 much into the register. Otherwise load the whole register. Note
4775 that in the latter case we may pick up unwanted bits. It's not a
4776 problem at the moment but may wish to revisit. */
4778 if (intoffset % BITS_PER_WORD != 0)
4780 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4782 if (mode == BLKmode)
4784 /* We couldn't find an appropriate mode, which happens,
4785 e.g., in packed structs when there are 3 bytes to load.
4786 Back intoffset back to the beginning of the word in this
4788 intoffset = intoffset & -BITS_PER_WORD;
4795 startbit = intoffset & -BITS_PER_WORD;
4796 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4797 intregs = (endbit - startbit) / BITS_PER_WORD;
4798 this_regno = cum->words + intoffset / BITS_PER_WORD;
4800 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4803 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4807 intoffset /= BITS_PER_UNIT;
4810 regno = GP_ARG_MIN_REG + this_regno;
4811 reg = gen_rtx_REG (mode, regno);
4813 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4816 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4820 while (intregs > 0);
4823 /* Recursive workhorse for the following. */
4826 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4827 HOST_WIDE_INT startbitpos, rtx rvec[],
4832 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4833 if (TREE_CODE (f) == FIELD_DECL)
4835 HOST_WIDE_INT bitpos = startbitpos;
4836 tree ftype = TREE_TYPE (f);
4837 enum machine_mode mode = TYPE_MODE (ftype);
4839 if (DECL_SIZE (f) != 0
4840 && host_integerp (bit_position (f), 1))
4841 bitpos += int_bit_position (f);
4843 /* ??? FIXME: else assume zero offset. */
4845 if (TREE_CODE (ftype) == RECORD_TYPE)
4846 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4847 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4852 case SCmode: mode = SFmode; break;
4853 case DCmode: mode = DFmode; break;
4854 case TCmode: mode = TFmode; break;
4858 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4860 = gen_rtx_EXPR_LIST (VOIDmode,
4861 gen_rtx_REG (mode, cum->fregno++),
4862 GEN_INT (bitpos / BITS_PER_UNIT));
4866 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4868 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4870 = gen_rtx_EXPR_LIST (VOIDmode,
4871 gen_rtx_REG (mode, cum->vregno++),
4872 GEN_INT (bitpos / BITS_PER_UNIT));
4874 else if (cum->intoffset == -1)
4875 cum->intoffset = bitpos;
4879 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4880 the register(s) to be used for each field and subfield of a struct
4881 being passed by value, along with the offset of where the
4882 register's value may be found in the block. FP fields go in FP
4883 register, vector fields go in vector registers, and everything
4884 else goes in int registers, packed as in memory.
4886 This code is also used for function return values. RETVAL indicates
4887 whether this is the case.
4889 Much of this is taken from the SPARC V9 port, which has a similar
4890 calling convention. */
4893 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4894 int named, bool retval)
4896 rtx rvec[FIRST_PSEUDO_REGISTER];
4897 int k = 1, kbase = 1;
4898 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4899 /* This is a copy; modifications are not visible to our caller. */
4900 CUMULATIVE_ARGS copy_cum = *orig_cum;
4901 CUMULATIVE_ARGS *cum = ©_cum;
4903 /* Pad to 16 byte boundary if needed. */
4904 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4905 && (cum->words % 2) != 0)
4912 /* Put entries into rvec[] for individual FP and vector fields, and
4913 for the chunks of memory that go in int regs. Note we start at
4914 element 1; 0 is reserved for an indication of using memory, and
4915 may or may not be filled in below. */
4916 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4917 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4919 /* If any part of the struct went on the stack put all of it there.
4920 This hack is because the generic code for
4921 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4922 parts of the struct are not at the beginning. */
4926 return NULL_RTX; /* doesn't go in registers at all */
4928 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4930 if (k > 1 || cum->use_stack)
4931 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4936 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4939 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4943 rtx rvec[GP_ARG_NUM_REG + 1];
4945 if (align_words >= GP_ARG_NUM_REG)
4948 n_units = rs6000_arg_size (mode, type);
4950 /* Optimize the simple case where the arg fits in one gpr, except in
4951 the case of BLKmode due to assign_parms assuming that registers are
4952 BITS_PER_WORD wide. */
4954 || (n_units == 1 && mode != BLKmode))
4955 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4958 if (align_words + n_units > GP_ARG_NUM_REG)
4959 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4960 using a magic NULL_RTX component.
4961 FIXME: This is not strictly correct. Only some of the arg
4962 belongs in memory, not all of it. However, there isn't any way
4963 to do this currently, apart from building rtx descriptions for
4964 the pieces of memory we want stored. Due to bugs in the generic
4965 code we can't use the normal function_arg_partial_nregs scheme
4966 with the PARALLEL arg description we emit here.
4967 In any case, the code to store the whole arg to memory is often
4968 more efficient than code to store pieces, and we know that space
4969 is available in the right place for the whole arg. */
4970 /* FIXME: This should be fixed since the conversion to
4971 TARGET_ARG_PARTIAL_BYTES. */
4972 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4977 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4978 rtx off = GEN_INT (i++ * 4);
4979 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4981 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4983 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4986 /* Determine where to put an argument to a function.
4987 Value is zero to push the argument on the stack,
4988 or a hard register in which to store the argument.
4990 MODE is the argument's machine mode.
4991 TYPE is the data type of the argument (as a tree).
4992 This is null for libcalls where that information may
4994 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4995 the preceding args and about the function being called. It is
4996 not modified in this routine.
4997 NAMED is nonzero if this argument is a named parameter
4998 (otherwise it is an extra parameter matching an ellipsis).
5000 On RS/6000 the first eight words of non-FP are normally in registers
5001 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5002 Under V.4, the first 8 FP args are in registers.
5004 If this is floating-point and no prototype is specified, we use
5005 both an FP and integer register (or possibly FP reg and stack). Library
5006 functions (when CALL_LIBCALL is set) always have the proper types for args,
5007 so we can pass the FP value just in one register. emit_library_function
5008 doesn't support PARALLEL anyway.
5010 Note that for args passed by reference, function_arg will be called
5011 with MODE and TYPE set to that of the pointer to the arg, not the arg
5015 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5016 tree type, int named)
5018 enum rs6000_abi abi = DEFAULT_ABI;
5020 /* Return a marker to indicate whether CR1 needs to set or clear the
5021 bit that V.4 uses to say fp args were passed in registers.
5022 Assume that we don't need the marker for software floating point,
5023 or compiler generated library calls. */
5024 if (mode == VOIDmode)
5027 && (cum->call_cookie & CALL_LIBCALL) == 0
5029 || (cum->nargs_prototype < 0
5030 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5032 /* For the SPE, we need to crxor CR6 always. */
5034 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5035 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5036 return GEN_INT (cum->call_cookie
5037 | ((cum->fregno == FP_ARG_MIN_REG)
5038 ? CALL_V4_SET_FP_ARGS
5039 : CALL_V4_CLEAR_FP_ARGS));
5042 return GEN_INT (cum->call_cookie);
5045 if (rs6000_darwin64_abi && mode == BLKmode
5046 && TREE_CODE (type) == RECORD_TYPE)
5048 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5049 if (rslt != NULL_RTX)
5051 /* Else fall through to usual handling. */
5054 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5055 if (TARGET_64BIT && ! cum->prototype)
5057 /* Vector parameters get passed in vector register
5058 and also in GPRs or memory, in absence of prototype. */
5061 align_words = (cum->words + 1) & ~1;
5063 if (align_words >= GP_ARG_NUM_REG)
5069 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5071 return gen_rtx_PARALLEL (mode,
5073 gen_rtx_EXPR_LIST (VOIDmode,
5075 gen_rtx_EXPR_LIST (VOIDmode,
5076 gen_rtx_REG (mode, cum->vregno),
5080 return gen_rtx_REG (mode, cum->vregno);
5081 else if (TARGET_ALTIVEC_ABI
5082 && (ALTIVEC_VECTOR_MODE (mode)
5083 || (type && TREE_CODE (type) == VECTOR_TYPE
5084 && int_size_in_bytes (type) == 16)))
5086 if (named || abi == ABI_V4)
5090 /* Vector parameters to varargs functions under AIX or Darwin
5091 get passed in memory and possibly also in GPRs. */
5092 int align, align_words, n_words;
5093 enum machine_mode part_mode;
5095 /* Vector parameters must be 16-byte aligned. This places them at
5096 2 mod 4 in terms of words in 32-bit mode, since the parameter
5097 save area starts at offset 24 from the stack. In 64-bit mode,
5098 they just have to start on an even word, since the parameter
5099 save area is 16-byte aligned. */
5101 align = (2 - cum->words) & 3;
5103 align = cum->words & 1;
5104 align_words = cum->words + align;
5106 /* Out of registers? Memory, then. */
5107 if (align_words >= GP_ARG_NUM_REG)
5110 if (TARGET_32BIT && TARGET_POWERPC64)
5111 return rs6000_mixed_function_arg (mode, type, align_words);
5113 /* The vector value goes in GPRs. Only the part of the
5114 value in GPRs is reported here. */
5116 n_words = rs6000_arg_size (mode, type);
5117 if (align_words + n_words > GP_ARG_NUM_REG)
5118 /* Fortunately, there are only two possibilities, the value
5119 is either wholly in GPRs or half in GPRs and half not. */
5122 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5125 else if (TARGET_SPE_ABI && TARGET_SPE
5126 && (SPE_VECTOR_MODE (mode)
5127 || (TARGET_E500_DOUBLE && (mode == DFmode
5128 || mode == DCmode))))
5129 return rs6000_spe_function_arg (cum, mode, type);
5131 else if (abi == ABI_V4)
5133 if (TARGET_HARD_FLOAT && TARGET_FPRS
5134 && (mode == SFmode || mode == DFmode))
5136 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5137 return gen_rtx_REG (mode, cum->fregno);
5143 int n_words = rs6000_arg_size (mode, type);
5144 int gregno = cum->sysv_gregno;
5146 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5147 (r7,r8) or (r9,r10). As does any other 2 word item such
5148 as complex int due to a historical mistake. */
5150 gregno += (1 - gregno) & 1;
5152 /* Multi-reg args are not split between registers and stack. */
5153 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5156 if (TARGET_32BIT && TARGET_POWERPC64)
5157 return rs6000_mixed_function_arg (mode, type,
5158 gregno - GP_ARG_MIN_REG);
5159 return gen_rtx_REG (mode, gregno);
5164 int align_words = rs6000_parm_start (mode, type, cum->words);
5166 if (USE_FP_FOR_ARG_P (cum, mode, type))
5168 rtx rvec[GP_ARG_NUM_REG + 1];
5172 enum machine_mode fmode = mode;
5173 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5175 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5177 /* Currently, we only ever need one reg here because complex
5178 doubles are split. */
5179 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5181 /* Long double split over regs and memory. */
5185 /* Do we also need to pass this arg in the parameter save
5188 && (cum->nargs_prototype <= 0
5189 || (DEFAULT_ABI == ABI_AIX
5191 && align_words >= GP_ARG_NUM_REG)));
5193 if (!needs_psave && mode == fmode)
5194 return gen_rtx_REG (fmode, cum->fregno);
5199 /* Describe the part that goes in gprs or the stack.
5200 This piece must come first, before the fprs. */
5201 if (align_words < GP_ARG_NUM_REG)
5203 unsigned long n_words = rs6000_arg_size (mode, type);
5205 if (align_words + n_words > GP_ARG_NUM_REG
5206 || (TARGET_32BIT && TARGET_POWERPC64))
5208 /* If this is partially on the stack, then we only
5209 include the portion actually in registers here. */
5210 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5213 if (align_words + n_words > GP_ARG_NUM_REG
5214 && (TARGET_32BIT && TARGET_POWERPC64))
5215 /* Not all of the arg fits in gprs. Say that it
5216 goes in memory too, using a magic NULL_RTX
5217 component. Also see comment in
5218 rs6000_mixed_function_arg for why the normal
5219 function_arg_partial_nregs scheme doesn't work
5221 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5225 r = gen_rtx_REG (rmode,
5226 GP_ARG_MIN_REG + align_words);
5227 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5228 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5230 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5234 /* The whole arg fits in gprs. */
5235 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5236 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5240 /* It's entirely in memory. */
5241 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5244 /* Describe where this piece goes in the fprs. */
5245 r = gen_rtx_REG (fmode, cum->fregno);
5246 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5248 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5250 else if (align_words < GP_ARG_NUM_REG)
5252 if (TARGET_32BIT && TARGET_POWERPC64)
5253 return rs6000_mixed_function_arg (mode, type, align_words);
5255 if (mode == BLKmode)
5258 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5265 /* For an arg passed partly in registers and partly in memory, this is
5266 the number of bytes passed in registers. For args passed entirely in
5267 registers or entirely in memory, zero. When an arg is described by a
5268 PARALLEL, perhaps using more than one register type, this function
5269 returns the number of bytes used by the first element of the PARALLEL. */
5272 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5273 tree type, bool named)
5278 if (DEFAULT_ABI == ABI_V4)
5281 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5282 && cum->nargs_prototype >= 0)
5285 /* In this complicated case we just disable the partial_nregs code. */
5286 if (rs6000_darwin64_abi && mode == BLKmode
5287 && TREE_CODE (type) == RECORD_TYPE
5288 && int_size_in_bytes (type) > 0)
5291 align_words = rs6000_parm_start (mode, type, cum->words);
5293 if (USE_FP_FOR_ARG_P (cum, mode, type)
5294 /* If we are passing this arg in the fixed parameter save area
5295 (gprs or memory) as well as fprs, then this function should
5296 return the number of bytes passed in the parameter save area
5297 rather than bytes passed in fprs. */
5299 && (cum->nargs_prototype <= 0
5300 || (DEFAULT_ABI == ABI_AIX
5302 && align_words >= GP_ARG_NUM_REG))))
5304 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5305 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5306 else if (cum->nargs_prototype >= 0)
5310 if (align_words < GP_ARG_NUM_REG
5311 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5312 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5314 if (ret != 0 && TARGET_DEBUG_ARG)
5315 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5320 /* A C expression that indicates when an argument must be passed by
5321 reference. If nonzero for an argument, a copy of that argument is
5322 made in memory and a pointer to the argument is passed instead of
5323 the argument itself. The pointer is passed in whatever way is
5324 appropriate for passing a pointer to that type.
5326 Under V.4, aggregates and long double are passed by reference.
5328 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5329 reference unless the AltiVec vector extension ABI is in force.
5331 As an extension to all ABIs, variable sized types are passed by
5335 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5336 enum machine_mode mode, tree type,
5337 bool named ATTRIBUTE_UNUSED)
5339 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5341 if (TARGET_DEBUG_ARG)
5342 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5349 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5351 if (TARGET_DEBUG_ARG)
5352 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5356 if (int_size_in_bytes (type) < 0)
5358 if (TARGET_DEBUG_ARG)
5359 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5363 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5364 modes only exist for GCC vector types if -maltivec. */
5365 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5367 if (TARGET_DEBUG_ARG)
5368 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5372 /* Pass synthetic vectors in memory. */
5373 if (TREE_CODE (type) == VECTOR_TYPE
5374 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5376 static bool warned_for_pass_big_vectors = false;
5377 if (TARGET_DEBUG_ARG)
5378 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5379 if (!warned_for_pass_big_vectors)
5381 warning (0, "GCC vector passed by reference: "
5382 "non-standard ABI extension with no compatibility guarantee");
5383 warned_for_pass_big_vectors = true;
5392 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5395 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5400 for (i = 0; i < nregs; i++)
5402 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5403 if (reload_completed)
5405 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5408 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5409 i * GET_MODE_SIZE (reg_mode));
5412 tem = replace_equiv_address (tem, XEXP (tem, 0));
5416 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5420 /* Perform any needed actions needed for a function that is receiving a
5421 variable number of arguments.
5425 MODE and TYPE are the mode and type of the current parameter.
5427 PRETEND_SIZE is a variable that should be set to the amount of stack
5428 that must be pushed by the prolog to pretend that our caller pushed
5431 Normally, this macro will push all remaining incoming registers on the
5432 stack and set PRETEND_SIZE to the length of the registers pushed. */
5435 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5436 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5439 CUMULATIVE_ARGS next_cum;
5440 int reg_size = TARGET_32BIT ? 4 : 8;
5441 rtx save_area = NULL_RTX, mem;
5442 int first_reg_offset, set;
5444 /* Skip the last named argument. */
5446 function_arg_advance (&next_cum, mode, type, 1, 0);
5448 if (DEFAULT_ABI == ABI_V4)
5450 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5454 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5455 HOST_WIDE_INT offset = 0;
5457 /* Try to optimize the size of the varargs save area.
5458 The ABI requires that ap.reg_save_area is doubleword
5459 aligned, but we don't need to allocate space for all
5460 the bytes, only those to which we actually will save
5462 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5463 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5464 if (TARGET_HARD_FLOAT && TARGET_FPRS
5465 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5466 && cfun->va_list_fpr_size)
5469 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5470 * UNITS_PER_FP_WORD;
5471 if (cfun->va_list_fpr_size
5472 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5473 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5475 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5476 * UNITS_PER_FP_WORD;
5480 offset = -((first_reg_offset * reg_size) & ~7);
5481 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5483 gpr_reg_num = cfun->va_list_gpr_size;
5484 if (reg_size == 4 && (first_reg_offset & 1))
5487 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5490 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5492 - (int) (GP_ARG_NUM_REG * reg_size);
5494 if (gpr_size + fpr_size)
5497 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5498 gcc_assert (GET_CODE (reg_save_area) == MEM);
5499 reg_save_area = XEXP (reg_save_area, 0);
5500 if (GET_CODE (reg_save_area) == PLUS)
5502 gcc_assert (XEXP (reg_save_area, 0)
5503 == virtual_stack_vars_rtx);
5504 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5505 offset += INTVAL (XEXP (reg_save_area, 1));
5508 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5511 cfun->machine->varargs_save_offset = offset;
5512 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5517 first_reg_offset = next_cum.words;
5518 save_area = virtual_incoming_args_rtx;
5520 if (targetm.calls.must_pass_in_stack (mode, type))
5521 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5524 set = get_varargs_alias_set ();
5525 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5526 && cfun->va_list_gpr_size)
5528 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5530 if (va_list_gpr_counter_field)
5532 /* V4 va_list_gpr_size counts number of registers needed. */
5533 if (nregs > cfun->va_list_gpr_size)
5534 nregs = cfun->va_list_gpr_size;
5538 /* char * va_list instead counts number of bytes needed. */
5539 if (nregs > cfun->va_list_gpr_size / reg_size)
5540 nregs = cfun->va_list_gpr_size / reg_size;
5543 mem = gen_rtx_MEM (BLKmode,
5544 plus_constant (save_area,
5545 first_reg_offset * reg_size));
5546 MEM_NOTRAP_P (mem) = 1;
5547 set_mem_alias_set (mem, set);
5548 set_mem_align (mem, BITS_PER_WORD);
5550 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5554 /* Save FP registers if needed. */
5555 if (DEFAULT_ABI == ABI_V4
5556 && TARGET_HARD_FLOAT && TARGET_FPRS
5558 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5559 && cfun->va_list_fpr_size)
5561 int fregno = next_cum.fregno, nregs;
5562 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5563 rtx lab = gen_label_rtx ();
5564 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5565 * UNITS_PER_FP_WORD);
5568 (gen_rtx_SET (VOIDmode,
5570 gen_rtx_IF_THEN_ELSE (VOIDmode,
5571 gen_rtx_NE (VOIDmode, cr1,
5573 gen_rtx_LABEL_REF (VOIDmode, lab),
5577 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5578 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5580 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5581 MEM_NOTRAP_P (mem) = 1;
5582 set_mem_alias_set (mem, set);
5583 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5584 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5591 /* Create the va_list data type. */
5594 rs6000_build_builtin_va_list (void)
5596 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5598 /* For AIX, prefer 'char *' because that's what the system
5599 header files like. */
5600 if (DEFAULT_ABI != ABI_V4)
5601 return build_pointer_type (char_type_node);
5603 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5604 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5606 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5607 unsigned_char_type_node);
5608 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5609 unsigned_char_type_node);
5610 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5612 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5613 short_unsigned_type_node);
5614 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5616 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5619 va_list_gpr_counter_field = f_gpr;
5620 va_list_fpr_counter_field = f_fpr;
5622 DECL_FIELD_CONTEXT (f_gpr) = record;
5623 DECL_FIELD_CONTEXT (f_fpr) = record;
5624 DECL_FIELD_CONTEXT (f_res) = record;
5625 DECL_FIELD_CONTEXT (f_ovf) = record;
5626 DECL_FIELD_CONTEXT (f_sav) = record;
5628 TREE_CHAIN (record) = type_decl;
5629 TYPE_NAME (record) = type_decl;
5630 TYPE_FIELDS (record) = f_gpr;
5631 TREE_CHAIN (f_gpr) = f_fpr;
5632 TREE_CHAIN (f_fpr) = f_res;
5633 TREE_CHAIN (f_res) = f_ovf;
5634 TREE_CHAIN (f_ovf) = f_sav;
5636 layout_type (record);
5638 /* The correct type is an array type of one element. */
5639 return build_array_type (record, build_index_type (size_zero_node));
5642 /* Implement va_start. */
5645 rs6000_va_start (tree valist, rtx nextarg)
5647 HOST_WIDE_INT words, n_gpr, n_fpr;
5648 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5649 tree gpr, fpr, ovf, sav, t;
5651 /* Only SVR4 needs something special. */
5652 if (DEFAULT_ABI != ABI_V4)
5654 std_expand_builtin_va_start (valist, nextarg);
5658 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5659 f_fpr = TREE_CHAIN (f_gpr);
5660 f_res = TREE_CHAIN (f_fpr);
5661 f_ovf = TREE_CHAIN (f_res);
5662 f_sav = TREE_CHAIN (f_ovf);
5664 valist = build_va_arg_indirect_ref (valist);
5665 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5666 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5667 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5668 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5670 /* Count number of gp and fp argument registers used. */
5671 words = current_function_args_info.words;
5672 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5674 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5677 if (TARGET_DEBUG_ARG)
5678 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5679 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5680 words, n_gpr, n_fpr);
5682 if (cfun->va_list_gpr_size)
5684 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5685 build_int_cst (NULL_TREE, n_gpr));
5686 TREE_SIDE_EFFECTS (t) = 1;
5687 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5690 if (cfun->va_list_fpr_size)
5692 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5693 build_int_cst (NULL_TREE, n_fpr));
5694 TREE_SIDE_EFFECTS (t) = 1;
5695 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5698 /* Find the overflow area. */
5699 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5701 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5702 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5703 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5704 TREE_SIDE_EFFECTS (t) = 1;
5705 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5707 /* If there were no va_arg invocations, don't set up the register
5709 if (!cfun->va_list_gpr_size
5710 && !cfun->va_list_fpr_size
5711 && n_gpr < GP_ARG_NUM_REG
5712 && n_fpr < FP_ARG_V4_MAX_REG)
5715 /* Find the register save area. */
5716 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5717 if (cfun->machine->varargs_save_offset)
5718 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5719 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5720 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5721 TREE_SIDE_EFFECTS (t) = 1;
5722 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5725 /* Implement va_arg. */
5728 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5730 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5731 tree gpr, fpr, ovf, sav, reg, t, u;
5732 int size, rsize, n_reg, sav_ofs, sav_scale;
5733 tree lab_false, lab_over, addr;
5735 tree ptrtype = build_pointer_type (type);
5737 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5739 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5740 return build_va_arg_indirect_ref (t);
5743 if (DEFAULT_ABI != ABI_V4)
5745 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5747 tree elem_type = TREE_TYPE (type);
5748 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5749 int elem_size = GET_MODE_SIZE (elem_mode);
5751 if (elem_size < UNITS_PER_WORD)
5753 tree real_part, imag_part;
5754 tree post = NULL_TREE;
5756 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5758 /* Copy the value into a temporary, lest the formal temporary
5759 be reused out from under us. */
5760 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5761 append_to_statement_list (post, pre_p);
5763 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5766 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5770 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5773 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5774 f_fpr = TREE_CHAIN (f_gpr);
5775 f_res = TREE_CHAIN (f_fpr);
5776 f_ovf = TREE_CHAIN (f_res);
5777 f_sav = TREE_CHAIN (f_ovf);
5779 valist = build_va_arg_indirect_ref (valist);
5780 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5781 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5782 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5783 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5785 size = int_size_in_bytes (type);
5786 rsize = (size + 3) / 4;
5789 if (TARGET_HARD_FLOAT && TARGET_FPRS
5790 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5792 /* FP args go in FP registers, if present. */
5797 if (TYPE_MODE (type) == DFmode)
5802 /* Otherwise into GP registers. */
5811 /* Pull the value out of the saved registers.... */
5814 addr = create_tmp_var (ptr_type_node, "addr");
5815 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5817 /* AltiVec vectors never go in registers when -mabi=altivec. */
5818 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5822 lab_false = create_artificial_label ();
5823 lab_over = create_artificial_label ();
5825 /* Long long and SPE vectors are aligned in the registers.
5826 As are any other 2 gpr item such as complex int due to a
5827 historical mistake. */
5831 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5832 size_int (n_reg - 1));
5833 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5836 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5837 t = build2 (GE_EXPR, boolean_type_node, u, t);
5838 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5839 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5840 gimplify_and_add (t, pre_p);
5844 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5846 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5847 u = build1 (CONVERT_EXPR, integer_type_node, u);
5848 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5849 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5851 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5852 gimplify_and_add (t, pre_p);
5854 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5855 gimplify_and_add (t, pre_p);
5857 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5858 append_to_statement_list (t, pre_p);
5862 /* Ensure that we don't find any more args in regs.
5863 Alignment has taken care of the n_reg == 2 case. */
5864 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5865 gimplify_and_add (t, pre_p);
5869 /* ... otherwise out of the overflow area. */
5871 /* Care for on-stack alignment if needed. */
5875 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5876 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5877 build_int_cst (NULL_TREE, -align));
5879 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5881 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5882 gimplify_and_add (u, pre_p);
5884 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5885 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5886 gimplify_and_add (t, pre_p);
5890 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5891 append_to_statement_list (t, pre_p);
5894 addr = fold_convert (ptrtype, addr);
5895 return build_va_arg_indirect_ref (addr);
5901 def_builtin (int mask, const char *name, tree type, int code)
5903 if (mask & target_flags)
5905 if (rs6000_builtin_decls[code])
5908 rs6000_builtin_decls[code] =
5909 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5914 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5916 static const struct builtin_description bdesc_3arg[] =
5918 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5919 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5920 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5921 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5922 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5923 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5924 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5925 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5926 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5927 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5928 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5929 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5930 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5931 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5932 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5933 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5934 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5935 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5936 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5937 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5938 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5939 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5940 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5942 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5943 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5944 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5945 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5946 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5947 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5948 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5949 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5950 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5951 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5952 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5953 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5954 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5955 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5956 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
5959 /* DST operations: void foo (void *, const int, const char). */
5961 static const struct builtin_description bdesc_dst[] =
5963 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5964 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5965 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5966 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5968 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5969 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5970 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5971 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
5974 /* Simple binary operations: VECc = foo (VECa, VECb). */
5976 static struct builtin_description bdesc_2arg[] =
5978 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5979 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5980 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5981 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5982 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5983 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5984 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5985 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5986 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5987 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5988 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5989 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5990 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5991 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5992 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5993 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5994 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5995 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5996 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5997 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5998 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5999 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6000 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6001 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6002 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6003 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6004 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6005 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6006 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6007 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6008 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6009 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6010 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6011 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6012 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6013 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6014 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6015 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6016 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6017 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6018 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6019 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6020 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6021 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6025 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6026 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6027 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6028 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6029 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6030 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6031 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6032 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6033 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6034 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6035 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6036 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6037 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6038 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6039 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6040 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6041 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6042 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6043 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6044 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6045 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6046 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6047 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6048 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6049 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6050 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6053 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6054 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6055 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6056 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6057 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6058 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6059 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6060 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6061 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6062 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6063 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6064 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6065 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6066 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6067 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6068 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6069 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6070 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6071 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6072 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6073 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6074 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6075 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6076 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6077 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6078 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6079 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6080 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6081 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6082 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6083 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6084 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6086 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6087 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6088 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6090 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6091 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6092 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6093 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6094 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6095 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6096 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6097 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6098 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6099 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6100 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6101 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6102 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6103 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6104 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6105 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6106 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6107 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6108 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6109 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6110 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6111 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6112 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6113 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6114 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6115 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6116 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6117 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6118 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6119 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6120 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6121 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6122 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6123 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6124 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6125 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6126 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6127 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6128 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6129 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6139 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6140 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6141 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6142 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6143 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6146 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6149 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6218 /* Place holder, leave as first spe builtin. */
6219 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6220 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6221 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6222 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6223 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6224 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6225 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6226 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6227 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6228 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6229 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6230 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6231 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6232 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6233 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6234 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6235 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6236 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6237 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6238 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6239 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6240 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6241 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6242 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6243 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6244 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6245 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6246 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6247 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6248 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6249 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6250 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6251 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6252 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6253 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6254 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6255 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6256 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6257 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6258 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6259 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6260 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6261 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6262 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6263 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6264 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6265 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6266 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6267 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6268 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6269 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6270 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6271 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6272 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6273 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6274 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6275 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6276 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6277 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6278 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6279 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6280 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6281 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6282 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6283 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6284 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6285 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6286 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6287 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6288 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6289 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6290 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6291 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6292 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6293 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6294 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6295 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6296 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6297 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6298 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6299 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6300 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6301 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6302 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6303 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6304 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6305 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6306 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6307 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6308 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6309 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6310 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6311 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6312 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6313 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6314 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6315 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6316 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6317 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6318 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6319 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6320 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6321 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6322 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6323 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6324 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6325 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6326 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6327 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6329 /* SPE binary operations expecting a 5-bit unsigned literal. */
6330 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6332 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6333 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6334 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6335 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6336 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6337 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6338 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6339 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6340 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6341 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6342 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6343 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6344 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6345 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6346 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6347 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6348 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6349 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6350 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6351 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6352 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6353 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6354 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6355 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6356 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6357 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6359 /* Place-holder. Leave as last binary SPE builtin. */
6360 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6363 /* AltiVec predicates. */
6365 struct builtin_description_predicates
6367 const unsigned int mask;
6368 const enum insn_code icode;
6370 const char *const name;
6371 const enum rs6000_builtins code;
6374 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6376 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6377 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6378 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6379 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6380 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6381 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6382 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6383 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6384 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6385 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6386 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6387 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6388 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6390 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6391 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6392 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6395 /* SPE predicates. */
6396 static struct builtin_description bdesc_spe_predicates[] =
6398 /* Place-holder. Leave as first. */
6399 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6400 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6401 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6402 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6403 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6404 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6405 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6406 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6407 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6408 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6409 /* Place-holder. Leave as last. */
6410 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6413 /* SPE evsel predicates. */
6414 static struct builtin_description bdesc_spe_evsel[] =
6416 /* Place-holder. Leave as first. */
6417 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6418 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6419 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6420 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6421 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6422 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6423 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6424 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6425 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6426 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6427 /* Place-holder. Leave as last. */
6428 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6431 /* ABS* operations. */
6433 static const struct builtin_description bdesc_abs[] =
6435 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6436 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6437 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6438 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6439 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6440 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6441 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6444 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6447 static struct builtin_description bdesc_1arg[] =
6449 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6450 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6451 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6452 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6453 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6454 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6455 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6456 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6457 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6458 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6459 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6460 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6461 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6462 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6463 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6464 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6465 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6467 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6468 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6469 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6470 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6471 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6472 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6473 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6474 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6475 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6476 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6477 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6478 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6479 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6480 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6481 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6482 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6483 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6484 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6485 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6487 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6488 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6489 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6490 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6491 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6492 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6493 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6494 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6495 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6496 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6497 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6498 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6499 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6500 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6501 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6502 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6503 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6504 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6505 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6506 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6507 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6508 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6509 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6510 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6511 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6512 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6513 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6514 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6515 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6516 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6518 /* Place-holder. Leave as last unary SPE builtin. */
6519 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6523 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6526 tree arg0 = TREE_VALUE (arglist);
6527 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6528 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6529 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6531 if (icode == CODE_FOR_nothing)
6532 /* Builtin not supported on this processor. */
6535 /* If we got invalid arguments bail out before generating bad rtl. */
6536 if (arg0 == error_mark_node)
6539 if (icode == CODE_FOR_altivec_vspltisb
6540 || icode == CODE_FOR_altivec_vspltish
6541 || icode == CODE_FOR_altivec_vspltisw
6542 || icode == CODE_FOR_spe_evsplatfi
6543 || icode == CODE_FOR_spe_evsplati)
6545 /* Only allow 5-bit *signed* literals. */
6546 if (GET_CODE (op0) != CONST_INT
6547 || INTVAL (op0) > 15
6548 || INTVAL (op0) < -16)
6550 error ("argument 1 must be a 5-bit signed literal");
6556 || GET_MODE (target) != tmode
6557 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6558 target = gen_reg_rtx (tmode);
6560 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6561 op0 = copy_to_mode_reg (mode0, op0);
6563 pat = GEN_FCN (icode) (target, op0);
6572 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6574 rtx pat, scratch1, scratch2;
6575 tree arg0 = TREE_VALUE (arglist);
6576 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6577 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6578 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6580 /* If we have invalid arguments, bail out before generating bad rtl. */
6581 if (arg0 == error_mark_node)
6585 || GET_MODE (target) != tmode
6586 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6587 target = gen_reg_rtx (tmode);
6589 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6590 op0 = copy_to_mode_reg (mode0, op0);
6592 scratch1 = gen_reg_rtx (mode0);
6593 scratch2 = gen_reg_rtx (mode0);
6595 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6604 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6607 tree arg0 = TREE_VALUE (arglist);
6608 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6609 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6610 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6611 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6612 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6613 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6615 if (icode == CODE_FOR_nothing)
6616 /* Builtin not supported on this processor. */
6619 /* If we got invalid arguments bail out before generating bad rtl. */
6620 if (arg0 == error_mark_node || arg1 == error_mark_node)
6623 if (icode == CODE_FOR_altivec_vcfux
6624 || icode == CODE_FOR_altivec_vcfsx
6625 || icode == CODE_FOR_altivec_vctsxs
6626 || icode == CODE_FOR_altivec_vctuxs
6627 || icode == CODE_FOR_altivec_vspltb
6628 || icode == CODE_FOR_altivec_vsplth
6629 || icode == CODE_FOR_altivec_vspltw
6630 || icode == CODE_FOR_spe_evaddiw
6631 || icode == CODE_FOR_spe_evldd
6632 || icode == CODE_FOR_spe_evldh
6633 || icode == CODE_FOR_spe_evldw
6634 || icode == CODE_FOR_spe_evlhhesplat
6635 || icode == CODE_FOR_spe_evlhhossplat
6636 || icode == CODE_FOR_spe_evlhhousplat
6637 || icode == CODE_FOR_spe_evlwhe
6638 || icode == CODE_FOR_spe_evlwhos
6639 || icode == CODE_FOR_spe_evlwhou
6640 || icode == CODE_FOR_spe_evlwhsplat
6641 || icode == CODE_FOR_spe_evlwwsplat
6642 || icode == CODE_FOR_spe_evrlwi
6643 || icode == CODE_FOR_spe_evslwi
6644 || icode == CODE_FOR_spe_evsrwis
6645 || icode == CODE_FOR_spe_evsubifw
6646 || icode == CODE_FOR_spe_evsrwiu)
6648 /* Only allow 5-bit unsigned literals. */
6650 if (TREE_CODE (arg1) != INTEGER_CST
6651 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6653 error ("argument 2 must be a 5-bit unsigned literal");
6659 || GET_MODE (target) != tmode
6660 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6661 target = gen_reg_rtx (tmode);
6663 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6664 op0 = copy_to_mode_reg (mode0, op0);
6665 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6666 op1 = copy_to_mode_reg (mode1, op1);
6668 pat = GEN_FCN (icode) (target, op0, op1);
6677 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6678 tree arglist, rtx target)
6681 tree cr6_form = TREE_VALUE (arglist);
6682 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6683 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6684 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6685 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6686 enum machine_mode tmode = SImode;
6687 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6688 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6691 if (TREE_CODE (cr6_form) != INTEGER_CST)
6693 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6697 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6699 gcc_assert (mode0 == mode1);
6701 /* If we have invalid arguments, bail out before generating bad rtl. */
6702 if (arg0 == error_mark_node || arg1 == error_mark_node)
6706 || GET_MODE (target) != tmode
6707 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6708 target = gen_reg_rtx (tmode);
6710 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6711 op0 = copy_to_mode_reg (mode0, op0);
6712 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6713 op1 = copy_to_mode_reg (mode1, op1);
6715 scratch = gen_reg_rtx (mode0);
6717 pat = GEN_FCN (icode) (scratch, op0, op1,
6718 gen_rtx_SYMBOL_REF (Pmode, opcode));
6723 /* The vec_any* and vec_all* predicates use the same opcodes for two
6724 different operations, but the bits in CR6 will be different
6725 depending on what information we want. So we have to play tricks
6726 with CR6 to get the right bits out.
6728 If you think this is disgusting, look at the specs for the
6729 AltiVec predicates. */
6731 switch (cr6_form_int)
6734 emit_insn (gen_cr6_test_for_zero (target));
6737 emit_insn (gen_cr6_test_for_zero_reverse (target));
6740 emit_insn (gen_cr6_test_for_lt (target));
6743 emit_insn (gen_cr6_test_for_lt_reverse (target));
6746 error ("argument 1 of __builtin_altivec_predicate is out of range");
6754 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6757 tree arg0 = TREE_VALUE (arglist);
6758 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6759 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6760 enum machine_mode mode0 = Pmode;
6761 enum machine_mode mode1 = Pmode;
6762 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6763 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6765 if (icode == CODE_FOR_nothing)
6766 /* Builtin not supported on this processor. */
6769 /* If we got invalid arguments bail out before generating bad rtl. */
6770 if (arg0 == error_mark_node || arg1 == error_mark_node)
6774 || GET_MODE (target) != tmode
6775 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6776 target = gen_reg_rtx (tmode);
6778 op1 = copy_to_mode_reg (mode1, op1);
6780 if (op0 == const0_rtx)
6782 addr = gen_rtx_MEM (tmode, op1);
6786 op0 = copy_to_mode_reg (mode0, op0);
6787 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6790 pat = GEN_FCN (icode) (target, addr);
6800 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6802 tree arg0 = TREE_VALUE (arglist);
6803 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6804 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6805 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6806 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6807 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6809 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6810 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6811 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6813 /* Invalid arguments. Bail before doing anything stoopid! */
6814 if (arg0 == error_mark_node
6815 || arg1 == error_mark_node
6816 || arg2 == error_mark_node)
6819 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6820 op0 = copy_to_mode_reg (mode2, op0);
6821 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6822 op1 = copy_to_mode_reg (mode0, op1);
6823 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6824 op2 = copy_to_mode_reg (mode1, op2);
6826 pat = GEN_FCN (icode) (op1, op2, op0);
6833 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6835 tree arg0 = TREE_VALUE (arglist);
6836 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6837 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6838 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6839 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6840 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6842 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6843 enum machine_mode mode1 = Pmode;
6844 enum machine_mode mode2 = Pmode;
6846 /* Invalid arguments. Bail before doing anything stoopid! */
6847 if (arg0 == error_mark_node
6848 || arg1 == error_mark_node
6849 || arg2 == error_mark_node)
6852 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6853 op0 = copy_to_mode_reg (tmode, op0);
6855 op2 = copy_to_mode_reg (mode2, op2);
6857 if (op1 == const0_rtx)
6859 addr = gen_rtx_MEM (tmode, op2);
6863 op1 = copy_to_mode_reg (mode1, op1);
6864 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6867 pat = GEN_FCN (icode) (addr, op0);
6874 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6877 tree arg0 = TREE_VALUE (arglist);
6878 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6879 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6880 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6881 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6882 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6883 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6884 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6885 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6886 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6888 if (icode == CODE_FOR_nothing)
6889 /* Builtin not supported on this processor. */
6892 /* If we got invalid arguments bail out before generating bad rtl. */
6893 if (arg0 == error_mark_node
6894 || arg1 == error_mark_node
6895 || arg2 == error_mark_node)
6898 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6899 || icode == CODE_FOR_altivec_vsldoi_v4si
6900 || icode == CODE_FOR_altivec_vsldoi_v8hi
6901 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6903 /* Only allow 4-bit unsigned literals. */
6905 if (TREE_CODE (arg2) != INTEGER_CST
6906 || TREE_INT_CST_LOW (arg2) & ~0xf)
6908 error ("argument 3 must be a 4-bit unsigned literal");
6914 || GET_MODE (target) != tmode
6915 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6916 target = gen_reg_rtx (tmode);
6918 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6919 op0 = copy_to_mode_reg (mode0, op0);
6920 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6921 op1 = copy_to_mode_reg (mode1, op1);
6922 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6923 op2 = copy_to_mode_reg (mode2, op2);
6925 pat = GEN_FCN (icode) (target, op0, op1, op2);
6933 /* Expand the lvx builtins. */
6935 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6937 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6938 tree arglist = TREE_OPERAND (exp, 1);
6939 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6941 enum machine_mode tmode, mode0;
6943 enum insn_code icode;
6947 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6948 icode = CODE_FOR_altivec_lvx_v16qi;
6950 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6951 icode = CODE_FOR_altivec_lvx_v8hi;
6953 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6954 icode = CODE_FOR_altivec_lvx_v4si;
6956 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6957 icode = CODE_FOR_altivec_lvx_v4sf;
6966 arg0 = TREE_VALUE (arglist);
6967 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6968 tmode = insn_data[icode].operand[0].mode;
6969 mode0 = insn_data[icode].operand[1].mode;
6972 || GET_MODE (target) != tmode
6973 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6974 target = gen_reg_rtx (tmode);
6976 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6977 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6979 pat = GEN_FCN (icode) (target, op0);
6986 /* Expand the stvx builtins. */
6988 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6991 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6992 tree arglist = TREE_OPERAND (exp, 1);
6993 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6995 enum machine_mode mode0, mode1;
6997 enum insn_code icode;
7001 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7002 icode = CODE_FOR_altivec_stvx_v16qi;
7004 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7005 icode = CODE_FOR_altivec_stvx_v8hi;
7007 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7008 icode = CODE_FOR_altivec_stvx_v4si;
7010 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7011 icode = CODE_FOR_altivec_stvx_v4sf;
7018 arg0 = TREE_VALUE (arglist);
7019 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7020 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7021 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7022 mode0 = insn_data[icode].operand[0].mode;
7023 mode1 = insn_data[icode].operand[1].mode;
7025 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7026 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7027 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7028 op1 = copy_to_mode_reg (mode1, op1);
7030 pat = GEN_FCN (icode) (op0, op1);
7038 /* Expand the dst builtins. */
7040 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7043 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7044 tree arglist = TREE_OPERAND (exp, 1);
7045 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7046 tree arg0, arg1, arg2;
7047 enum machine_mode mode0, mode1, mode2;
7048 rtx pat, op0, op1, op2;
7049 struct builtin_description *d;
7054 /* Handle DST variants. */
7055 d = (struct builtin_description *) bdesc_dst;
7056 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7057 if (d->code == fcode)
7059 arg0 = TREE_VALUE (arglist);
7060 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7061 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7062 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7063 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7064 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7065 mode0 = insn_data[d->icode].operand[0].mode;
7066 mode1 = insn_data[d->icode].operand[1].mode;
7067 mode2 = insn_data[d->icode].operand[2].mode;
7069 /* Invalid arguments, bail out before generating bad rtl. */
7070 if (arg0 == error_mark_node
7071 || arg1 == error_mark_node
7072 || arg2 == error_mark_node)
7077 if (TREE_CODE (arg2) != INTEGER_CST
7078 || TREE_INT_CST_LOW (arg2) & ~0x3)
7080 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7084 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7085 op0 = copy_to_mode_reg (Pmode, op0);
7086 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7087 op1 = copy_to_mode_reg (mode1, op1);
7089 pat = GEN_FCN (d->icode) (op0, op1, op2);
7099 /* Expand vec_init builtin. */
7101 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7103 enum machine_mode tmode = TYPE_MODE (type);
7104 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7105 int i, n_elt = GET_MODE_NUNITS (tmode);
7106 rtvec v = rtvec_alloc (n_elt);
7108 gcc_assert (VECTOR_MODE_P (tmode));
7110 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7112 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
7113 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7116 gcc_assert (arglist == NULL);
7118 if (!target || !register_operand (target, tmode))
7119 target = gen_reg_rtx (tmode);
7121 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7125 /* Return the integer constant in ARG. Constrain it to be in the range
7126 of the subparts of VEC_TYPE; issue an error if not. */
7129 get_element_number (tree vec_type, tree arg)
7131 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7133 if (!host_integerp (arg, 1)
7134 || (elt = tree_low_cst (arg, 1), elt > max))
7136 error ("selector must be an integer constant in the range 0..%wi", max);
7143 /* Expand vec_set builtin. */
7145 altivec_expand_vec_set_builtin (tree arglist)
7147 enum machine_mode tmode, mode1;
7148 tree arg0, arg1, arg2;
7152 arg0 = TREE_VALUE (arglist);
7153 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7154 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7156 tmode = TYPE_MODE (TREE_TYPE (arg0));
7157 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7158 gcc_assert (VECTOR_MODE_P (tmode));
7160 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7161 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7162 elt = get_element_number (TREE_TYPE (arg0), arg2);
7164 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7165 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7167 op0 = force_reg (tmode, op0);
7168 op1 = force_reg (mode1, op1);
7170 rs6000_expand_vector_set (op0, op1, elt);
7175 /* Expand vec_ext builtin. */
7177 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7179 enum machine_mode tmode, mode0;
7184 arg0 = TREE_VALUE (arglist);
7185 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7187 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7188 elt = get_element_number (TREE_TYPE (arg0), arg1);
7190 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7191 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7192 gcc_assert (VECTOR_MODE_P (mode0));
7194 op0 = force_reg (mode0, op0);
7196 if (optimize || !target || !register_operand (target, tmode))
7197 target = gen_reg_rtx (tmode);
7199 rs6000_expand_vector_extract (target, op0, elt);
7204 /* Expand the builtin in EXP and store the result in TARGET. Store
7205 true in *EXPANDEDP if we found a builtin to expand. */
7207 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7209 struct builtin_description *d;
7210 struct builtin_description_predicates *dp;
7212 enum insn_code icode;
7213 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7214 tree arglist = TREE_OPERAND (exp, 1);
7217 enum machine_mode tmode, mode0;
7218 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7220 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7221 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7224 error ("unresolved overload for Altivec builtin %qF", fndecl);
7228 target = altivec_expand_ld_builtin (exp, target, expandedp);
7232 target = altivec_expand_st_builtin (exp, target, expandedp);
7236 target = altivec_expand_dst_builtin (exp, target, expandedp);
7244 case ALTIVEC_BUILTIN_STVX:
7245 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7246 case ALTIVEC_BUILTIN_STVEBX:
7247 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7248 case ALTIVEC_BUILTIN_STVEHX:
7249 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7250 case ALTIVEC_BUILTIN_STVEWX:
7251 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7252 case ALTIVEC_BUILTIN_STVXL:
7253 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7255 case ALTIVEC_BUILTIN_MFVSCR:
7256 icode = CODE_FOR_altivec_mfvscr;
7257 tmode = insn_data[icode].operand[0].mode;
7260 || GET_MODE (target) != tmode
7261 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7262 target = gen_reg_rtx (tmode);
7264 pat = GEN_FCN (icode) (target);
7270 case ALTIVEC_BUILTIN_MTVSCR:
7271 icode = CODE_FOR_altivec_mtvscr;
7272 arg0 = TREE_VALUE (arglist);
7273 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7274 mode0 = insn_data[icode].operand[0].mode;
7276 /* If we got invalid arguments bail out before generating bad rtl. */
7277 if (arg0 == error_mark_node)
7280 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7281 op0 = copy_to_mode_reg (mode0, op0);
7283 pat = GEN_FCN (icode) (op0);
7288 case ALTIVEC_BUILTIN_DSSALL:
7289 emit_insn (gen_altivec_dssall ());
7292 case ALTIVEC_BUILTIN_DSS:
7293 icode = CODE_FOR_altivec_dss;
7294 arg0 = TREE_VALUE (arglist);
7296 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7297 mode0 = insn_data[icode].operand[0].mode;
7299 /* If we got invalid arguments bail out before generating bad rtl. */
7300 if (arg0 == error_mark_node)
7303 if (TREE_CODE (arg0) != INTEGER_CST
7304 || TREE_INT_CST_LOW (arg0) & ~0x3)
7306 error ("argument to dss must be a 2-bit unsigned literal");
7310 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7311 op0 = copy_to_mode_reg (mode0, op0);
7313 emit_insn (gen_altivec_dss (op0));
7316 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7317 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7318 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7319 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7320 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7322 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7323 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7324 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7325 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7326 return altivec_expand_vec_set_builtin (arglist);
7328 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7329 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7330 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7331 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7332 return altivec_expand_vec_ext_builtin (arglist, target);
7339 /* Expand abs* operations. */
7340 d = (struct builtin_description *) bdesc_abs;
7341 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7342 if (d->code == fcode)
7343 return altivec_expand_abs_builtin (d->icode, arglist, target);
7345 /* Expand the AltiVec predicates. */
7346 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7347 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7348 if (dp->code == fcode)
7349 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7352 /* LV* are funky. We initialized them differently. */
7355 case ALTIVEC_BUILTIN_LVSL:
7356 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7358 case ALTIVEC_BUILTIN_LVSR:
7359 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7361 case ALTIVEC_BUILTIN_LVEBX:
7362 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7364 case ALTIVEC_BUILTIN_LVEHX:
7365 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7367 case ALTIVEC_BUILTIN_LVEWX:
7368 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7370 case ALTIVEC_BUILTIN_LVXL:
7371 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7373 case ALTIVEC_BUILTIN_LVX:
7374 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7385 /* Binops that need to be initialized manually, but can be expanded
7386 automagically by rs6000_expand_binop_builtin. */
7387 static struct builtin_description bdesc_2arg_spe[] =
7389 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7390 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7391 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7392 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7393 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7394 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7395 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7396 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7397 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7398 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7399 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7400 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7401 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7402 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7403 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7404 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7405 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7406 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7407 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7408 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7409 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7410 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7413 /* Expand the builtin in EXP and store the result in TARGET. Store
7414 true in *EXPANDEDP if we found a builtin to expand.
7416 This expands the SPE builtins that are not simple unary and binary
7419 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7421 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7422 tree arglist = TREE_OPERAND (exp, 1);
7424 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7425 enum insn_code icode;
7426 enum machine_mode tmode, mode0;
7428 struct builtin_description *d;
7433 /* Syntax check for a 5-bit unsigned immediate. */
7436 case SPE_BUILTIN_EVSTDD:
7437 case SPE_BUILTIN_EVSTDH:
7438 case SPE_BUILTIN_EVSTDW:
7439 case SPE_BUILTIN_EVSTWHE:
7440 case SPE_BUILTIN_EVSTWHO:
7441 case SPE_BUILTIN_EVSTWWE:
7442 case SPE_BUILTIN_EVSTWWO:
7443 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7444 if (TREE_CODE (arg1) != INTEGER_CST
7445 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7447 error ("argument 2 must be a 5-bit unsigned literal");
7455 /* The evsplat*i instructions are not quite generic. */
7458 case SPE_BUILTIN_EVSPLATFI:
7459 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7461 case SPE_BUILTIN_EVSPLATI:
7462 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7468 d = (struct builtin_description *) bdesc_2arg_spe;
7469 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7470 if (d->code == fcode)
7471 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7473 d = (struct builtin_description *) bdesc_spe_predicates;
7474 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7475 if (d->code == fcode)
7476 return spe_expand_predicate_builtin (d->icode, arglist, target);
7478 d = (struct builtin_description *) bdesc_spe_evsel;
7479 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7480 if (d->code == fcode)
7481 return spe_expand_evsel_builtin (d->icode, arglist, target);
7485 case SPE_BUILTIN_EVSTDDX:
7486 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7487 case SPE_BUILTIN_EVSTDHX:
7488 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7489 case SPE_BUILTIN_EVSTDWX:
7490 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7491 case SPE_BUILTIN_EVSTWHEX:
7492 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7493 case SPE_BUILTIN_EVSTWHOX:
7494 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7495 case SPE_BUILTIN_EVSTWWEX:
7496 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7497 case SPE_BUILTIN_EVSTWWOX:
7498 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7499 case SPE_BUILTIN_EVSTDD:
7500 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7501 case SPE_BUILTIN_EVSTDH:
7502 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7503 case SPE_BUILTIN_EVSTDW:
7504 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7505 case SPE_BUILTIN_EVSTWHE:
7506 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7507 case SPE_BUILTIN_EVSTWHO:
7508 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7509 case SPE_BUILTIN_EVSTWWE:
7510 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7511 case SPE_BUILTIN_EVSTWWO:
7512 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7513 case SPE_BUILTIN_MFSPEFSCR:
7514 icode = CODE_FOR_spe_mfspefscr;
7515 tmode = insn_data[icode].operand[0].mode;
7518 || GET_MODE (target) != tmode
7519 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7520 target = gen_reg_rtx (tmode);
7522 pat = GEN_FCN (icode) (target);
7527 case SPE_BUILTIN_MTSPEFSCR:
7528 icode = CODE_FOR_spe_mtspefscr;
7529 arg0 = TREE_VALUE (arglist);
7530 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7531 mode0 = insn_data[icode].operand[0].mode;
7533 if (arg0 == error_mark_node)
7536 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7537 op0 = copy_to_mode_reg (mode0, op0);
7539 pat = GEN_FCN (icode) (op0);
7552 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7554 rtx pat, scratch, tmp;
7555 tree form = TREE_VALUE (arglist);
7556 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7557 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7558 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7559 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7560 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7561 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7565 if (TREE_CODE (form) != INTEGER_CST)
7567 error ("argument 1 of __builtin_spe_predicate must be a constant");
7571 form_int = TREE_INT_CST_LOW (form);
7573 gcc_assert (mode0 == mode1);
7575 if (arg0 == error_mark_node || arg1 == error_mark_node)
7579 || GET_MODE (target) != SImode
7580 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7581 target = gen_reg_rtx (SImode);
7583 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7584 op0 = copy_to_mode_reg (mode0, op0);
7585 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7586 op1 = copy_to_mode_reg (mode1, op1);
7588 scratch = gen_reg_rtx (CCmode);
7590 pat = GEN_FCN (icode) (scratch, op0, op1);
7595 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7596 _lower_. We use one compare, but look in different bits of the
7597 CR for each variant.
7599 There are 2 elements in each SPE simd type (upper/lower). The CR
7600 bits are set as follows:
7602 BIT0 | BIT 1 | BIT 2 | BIT 3
7603 U | L | (U | L) | (U & L)
7605 So, for an "all" relationship, BIT 3 would be set.
7606 For an "any" relationship, BIT 2 would be set. Etc.
7608 Following traditional nomenclature, these bits map to:
7610 BIT0 | BIT 1 | BIT 2 | BIT 3
7613 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7618 /* All variant. OV bit. */
7620 /* We need to get to the OV bit, which is the ORDERED bit. We
7621 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7622 that's ugly and will make validate_condition_mode die.
7623 So let's just use another pattern. */
7624 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7626 /* Any variant. EQ bit. */
7630 /* Upper variant. LT bit. */
7634 /* Lower variant. GT bit. */
7639 error ("argument 1 of __builtin_spe_predicate is out of range");
7643 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7644 emit_move_insn (target, tmp);
7649 /* The evsel builtins look like this:
7651 e = __builtin_spe_evsel_OP (a, b, c, d);
7655 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7656 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7660 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7663 tree arg0 = TREE_VALUE (arglist);
7664 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7665 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7666 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7667 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7668 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7669 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7670 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7671 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7672 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7674 gcc_assert (mode0 == mode1);
7676 if (arg0 == error_mark_node || arg1 == error_mark_node
7677 || arg2 == error_mark_node || arg3 == error_mark_node)
7681 || GET_MODE (target) != mode0
7682 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7683 target = gen_reg_rtx (mode0);
7685 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7686 op0 = copy_to_mode_reg (mode0, op0);
7687 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7688 op1 = copy_to_mode_reg (mode0, op1);
7689 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7690 op2 = copy_to_mode_reg (mode0, op2);
7691 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7692 op3 = copy_to_mode_reg (mode0, op3);
7694 /* Generate the compare. */
7695 scratch = gen_reg_rtx (CCmode);
7696 pat = GEN_FCN (icode) (scratch, op0, op1);
7701 if (mode0 == V2SImode)
7702 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7704 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7709 /* Expand an expression EXP that calls a built-in function,
7710 with result going to TARGET if that's convenient
7711 (and in mode MODE if that's convenient).
7712 SUBTARGET may be used as the target for computing one of EXP's operands.
7713 IGNORE is nonzero if the value is to be ignored. */
7716 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7717 enum machine_mode mode ATTRIBUTE_UNUSED,
7718 int ignore ATTRIBUTE_UNUSED)
7720 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7721 tree arglist = TREE_OPERAND (exp, 1);
7722 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7723 struct builtin_description *d;
7728 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7729 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7731 int icode = (int) CODE_FOR_altivec_lvsr;
7732 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7733 enum machine_mode mode = insn_data[icode].operand[1].mode;
7737 gcc_assert (TARGET_ALTIVEC);
7739 arg = TREE_VALUE (arglist);
7740 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7741 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7742 addr = memory_address (mode, op);
7743 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7747 /* For the load case need to negate the address. */
7748 op = gen_reg_rtx (GET_MODE (addr));
7749 emit_insn (gen_rtx_SET (VOIDmode, op,
7750 gen_rtx_NEG (GET_MODE (addr), addr)));
7752 op = gen_rtx_MEM (mode, op);
7755 || GET_MODE (target) != tmode
7756 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7757 target = gen_reg_rtx (tmode);
7759 /*pat = gen_altivec_lvsr (target, op);*/
7760 pat = GEN_FCN (icode) (target, op);
7770 ret = altivec_expand_builtin (exp, target, &success);
7777 ret = spe_expand_builtin (exp, target, &success);
7783 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7785 /* Handle simple unary operations. */
7786 d = (struct builtin_description *) bdesc_1arg;
7787 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7788 if (d->code == fcode)
7789 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7791 /* Handle simple binary operations. */
7792 d = (struct builtin_description *) bdesc_2arg;
7793 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7794 if (d->code == fcode)
7795 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7797 /* Handle simple ternary operations. */
7798 d = (struct builtin_description *) bdesc_3arg;
7799 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7800 if (d->code == fcode)
7801 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7807 build_opaque_vector_type (tree node, int nunits)
7809 node = copy_node (node);
7810 TYPE_MAIN_VARIANT (node) = node;
7811 return build_vector_type (node, nunits);
7815 rs6000_init_builtins (void)
7817 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7818 V2SF_type_node = build_vector_type (float_type_node, 2);
7819 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7820 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7821 V4SF_type_node = build_vector_type (float_type_node, 4);
7822 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7823 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7825 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7826 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7827 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7829 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7830 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7831 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7832 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7834 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7835 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7836 'vector unsigned short'. */
7838 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7839 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7840 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7841 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7843 long_integer_type_internal_node = long_integer_type_node;
7844 long_unsigned_type_internal_node = long_unsigned_type_node;
7845 intQI_type_internal_node = intQI_type_node;
7846 uintQI_type_internal_node = unsigned_intQI_type_node;
7847 intHI_type_internal_node = intHI_type_node;
7848 uintHI_type_internal_node = unsigned_intHI_type_node;
7849 intSI_type_internal_node = intSI_type_node;
7850 uintSI_type_internal_node = unsigned_intSI_type_node;
7851 float_type_internal_node = float_type_node;
7852 void_type_internal_node = void_type_node;
7854 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7855 get_identifier ("__bool char"),
7856 bool_char_type_node));
7857 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7858 get_identifier ("__bool short"),
7859 bool_short_type_node));
7860 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7861 get_identifier ("__bool int"),
7862 bool_int_type_node));
7863 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7864 get_identifier ("__pixel"),
7867 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7868 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7869 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7870 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7872 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7873 get_identifier ("__vector unsigned char"),
7874 unsigned_V16QI_type_node));
7875 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7876 get_identifier ("__vector signed char"),
7878 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7879 get_identifier ("__vector __bool char"),
7880 bool_V16QI_type_node));
7882 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7883 get_identifier ("__vector unsigned short"),
7884 unsigned_V8HI_type_node));
7885 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7886 get_identifier ("__vector signed short"),
7888 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7889 get_identifier ("__vector __bool short"),
7890 bool_V8HI_type_node));
7892 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7893 get_identifier ("__vector unsigned int"),
7894 unsigned_V4SI_type_node));
7895 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7896 get_identifier ("__vector signed int"),
7898 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7899 get_identifier ("__vector __bool int"),
7900 bool_V4SI_type_node));
7902 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7903 get_identifier ("__vector float"),
7905 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7906 get_identifier ("__vector __pixel"),
7907 pixel_V8HI_type_node));
7910 spe_init_builtins ();
7912 altivec_init_builtins ();
7913 if (TARGET_ALTIVEC || TARGET_SPE)
7914 rs6000_common_init_builtins ();
7917 /* Search through a set of builtins and enable the mask bits.
7918 DESC is an array of builtins.
7919 SIZE is the total number of builtins.
7920 START is the builtin enum at which to start.
7921 END is the builtin enum at which to end. */
7923 enable_mask_for_builtins (struct builtin_description *desc, int size,
7924 enum rs6000_builtins start,
7925 enum rs6000_builtins end)
7929 for (i = 0; i < size; ++i)
7930 if (desc[i].code == start)
7936 for (; i < size; ++i)
7938 /* Flip all the bits on. */
7939 desc[i].mask = target_flags;
7940 if (desc[i].code == end)
7946 spe_init_builtins (void)
7948 tree endlink = void_list_node;
7949 tree puint_type_node = build_pointer_type (unsigned_type_node);
7950 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7951 struct builtin_description *d;
7954 tree v2si_ftype_4_v2si
7955 = build_function_type
7956 (opaque_V2SI_type_node,
7957 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7958 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7959 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7960 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7963 tree v2sf_ftype_4_v2sf
7964 = build_function_type
7965 (opaque_V2SF_type_node,
7966 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7967 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7968 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7969 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7972 tree int_ftype_int_v2si_v2si
7973 = build_function_type
7975 tree_cons (NULL_TREE, integer_type_node,
7976 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7977 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7980 tree int_ftype_int_v2sf_v2sf
7981 = build_function_type
7983 tree_cons (NULL_TREE, integer_type_node,
7984 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7985 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7988 tree void_ftype_v2si_puint_int
7989 = build_function_type (void_type_node,
7990 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7991 tree_cons (NULL_TREE, puint_type_node,
7992 tree_cons (NULL_TREE,
7996 tree void_ftype_v2si_puint_char
7997 = build_function_type (void_type_node,
7998 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7999 tree_cons (NULL_TREE, puint_type_node,
8000 tree_cons (NULL_TREE,
8004 tree void_ftype_v2si_pv2si_int
8005 = build_function_type (void_type_node,
8006 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8007 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8008 tree_cons (NULL_TREE,
8012 tree void_ftype_v2si_pv2si_char
8013 = build_function_type (void_type_node,
8014 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8015 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8016 tree_cons (NULL_TREE,
8021 = build_function_type (void_type_node,
8022 tree_cons (NULL_TREE, integer_type_node, endlink));
8025 = build_function_type (integer_type_node, endlink);
8027 tree v2si_ftype_pv2si_int
8028 = build_function_type (opaque_V2SI_type_node,
8029 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8030 tree_cons (NULL_TREE, integer_type_node,
8033 tree v2si_ftype_puint_int
8034 = build_function_type (opaque_V2SI_type_node,
8035 tree_cons (NULL_TREE, puint_type_node,
8036 tree_cons (NULL_TREE, integer_type_node,
8039 tree v2si_ftype_pushort_int
8040 = build_function_type (opaque_V2SI_type_node,
8041 tree_cons (NULL_TREE, pushort_type_node,
8042 tree_cons (NULL_TREE, integer_type_node,
8045 tree v2si_ftype_signed_char
8046 = build_function_type (opaque_V2SI_type_node,
8047 tree_cons (NULL_TREE, signed_char_type_node,
8050 /* The initialization of the simple binary and unary builtins is
8051 done in rs6000_common_init_builtins, but we have to enable the
8052 mask bits here manually because we have run out of `target_flags'
8053 bits. We really need to redesign this mask business. */
8055 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8056 ARRAY_SIZE (bdesc_2arg),
8059 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8060 ARRAY_SIZE (bdesc_1arg),
8062 SPE_BUILTIN_EVSUBFUSIAAW);
8063 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8064 ARRAY_SIZE (bdesc_spe_predicates),
8065 SPE_BUILTIN_EVCMPEQ,
8066 SPE_BUILTIN_EVFSTSTLT);
8067 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8068 ARRAY_SIZE (bdesc_spe_evsel),
8069 SPE_BUILTIN_EVSEL_CMPGTS,
8070 SPE_BUILTIN_EVSEL_FSTSTEQ);
8072 (*lang_hooks.decls.pushdecl)
8073 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8074 opaque_V2SI_type_node));
8076 /* Initialize irregular SPE builtins. */
8078 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8079 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8080 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8081 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8082 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8083 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8084 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8085 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8086 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8087 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8088 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8089 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8090 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8091 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8092 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8093 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8094 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8095 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8098 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8099 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8100 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8101 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8102 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8103 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8104 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8105 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8106 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8107 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8108 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8109 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8110 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8111 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8112 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8113 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8114 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8115 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8116 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8117 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8118 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8119 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8122 d = (struct builtin_description *) bdesc_spe_predicates;
8123 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8127 switch (insn_data[d->icode].operand[1].mode)
8130 type = int_ftype_int_v2si_v2si;
8133 type = int_ftype_int_v2sf_v2sf;
8139 def_builtin (d->mask, d->name, type, d->code);
8142 /* Evsel predicates. */
8143 d = (struct builtin_description *) bdesc_spe_evsel;
8144 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8148 switch (insn_data[d->icode].operand[1].mode)
8151 type = v2si_ftype_4_v2si;
8154 type = v2sf_ftype_4_v2sf;
8160 def_builtin (d->mask, d->name, type, d->code);
8165 altivec_init_builtins (void)
8167 struct builtin_description *d;
8168 struct builtin_description_predicates *dp;
8172 tree pfloat_type_node = build_pointer_type (float_type_node);
8173 tree pint_type_node = build_pointer_type (integer_type_node);
8174 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8175 tree pchar_type_node = build_pointer_type (char_type_node);
8177 tree pvoid_type_node = build_pointer_type (void_type_node);
8179 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8180 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8181 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8182 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8184 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8186 tree int_ftype_opaque
8187 = build_function_type_list (integer_type_node,
8188 opaque_V4SI_type_node, NULL_TREE);
8190 tree opaque_ftype_opaque_int
8191 = build_function_type_list (opaque_V4SI_type_node,
8192 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8193 tree opaque_ftype_opaque_opaque_int
8194 = build_function_type_list (opaque_V4SI_type_node,
8195 opaque_V4SI_type_node, opaque_V4SI_type_node,
8196 integer_type_node, NULL_TREE);
8197 tree int_ftype_int_opaque_opaque
8198 = build_function_type_list (integer_type_node,
8199 integer_type_node, opaque_V4SI_type_node,
8200 opaque_V4SI_type_node, NULL_TREE);
8201 tree int_ftype_int_v4si_v4si
8202 = build_function_type_list (integer_type_node,
8203 integer_type_node, V4SI_type_node,
8204 V4SI_type_node, NULL_TREE);
8205 tree v4sf_ftype_pcfloat
8206 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8207 tree void_ftype_pfloat_v4sf
8208 = build_function_type_list (void_type_node,
8209 pfloat_type_node, V4SF_type_node, NULL_TREE);
8210 tree v4si_ftype_pcint
8211 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8212 tree void_ftype_pint_v4si
8213 = build_function_type_list (void_type_node,
8214 pint_type_node, V4SI_type_node, NULL_TREE);
8215 tree v8hi_ftype_pcshort
8216 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8217 tree void_ftype_pshort_v8hi
8218 = build_function_type_list (void_type_node,
8219 pshort_type_node, V8HI_type_node, NULL_TREE);
8220 tree v16qi_ftype_pcchar
8221 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8222 tree void_ftype_pchar_v16qi
8223 = build_function_type_list (void_type_node,
8224 pchar_type_node, V16QI_type_node, NULL_TREE);
8225 tree void_ftype_v4si
8226 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8227 tree v8hi_ftype_void
8228 = build_function_type (V8HI_type_node, void_list_node);
8229 tree void_ftype_void
8230 = build_function_type (void_type_node, void_list_node);
8232 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8234 tree opaque_ftype_long_pcvoid
8235 = build_function_type_list (opaque_V4SI_type_node,
8236 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8237 tree v16qi_ftype_long_pcvoid
8238 = build_function_type_list (V16QI_type_node,
8239 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8240 tree v8hi_ftype_long_pcvoid
8241 = build_function_type_list (V8HI_type_node,
8242 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8243 tree v4si_ftype_long_pcvoid
8244 = build_function_type_list (V4SI_type_node,
8245 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8247 tree void_ftype_opaque_long_pvoid
8248 = build_function_type_list (void_type_node,
8249 opaque_V4SI_type_node, long_integer_type_node,
8250 pvoid_type_node, NULL_TREE);
8251 tree void_ftype_v4si_long_pvoid
8252 = build_function_type_list (void_type_node,
8253 V4SI_type_node, long_integer_type_node,
8254 pvoid_type_node, NULL_TREE);
8255 tree void_ftype_v16qi_long_pvoid
8256 = build_function_type_list (void_type_node,
8257 V16QI_type_node, long_integer_type_node,
8258 pvoid_type_node, NULL_TREE);
8259 tree void_ftype_v8hi_long_pvoid
8260 = build_function_type_list (void_type_node,
8261 V8HI_type_node, long_integer_type_node,
8262 pvoid_type_node, NULL_TREE);
8263 tree int_ftype_int_v8hi_v8hi
8264 = build_function_type_list (integer_type_node,
8265 integer_type_node, V8HI_type_node,
8266 V8HI_type_node, NULL_TREE);
8267 tree int_ftype_int_v16qi_v16qi
8268 = build_function_type_list (integer_type_node,
8269 integer_type_node, V16QI_type_node,
8270 V16QI_type_node, NULL_TREE);
8271 tree int_ftype_int_v4sf_v4sf
8272 = build_function_type_list (integer_type_node,
8273 integer_type_node, V4SF_type_node,
8274 V4SF_type_node, NULL_TREE);
8275 tree v4si_ftype_v4si
8276 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8277 tree v8hi_ftype_v8hi
8278 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8279 tree v16qi_ftype_v16qi
8280 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8281 tree v4sf_ftype_v4sf
8282 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8283 tree void_ftype_pcvoid_int_int
8284 = build_function_type_list (void_type_node,
8285 pcvoid_type_node, integer_type_node,
8286 integer_type_node, NULL_TREE);
8288 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8289 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8290 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8291 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8292 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8293 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8294 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8295 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8296 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8297 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8298 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8299 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8300 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8301 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8302 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8303 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8304 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8305 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8306 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8307 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8308 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8309 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8310 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8311 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8312 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8313 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8314 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8315 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8316 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8317 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8318 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8319 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8320 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8321 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8322 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8323 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8324 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8325 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8326 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8327 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8328 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8329 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8330 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8331 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8332 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8333 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8335 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8337 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8338 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8339 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8340 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8341 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8342 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8343 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8344 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8345 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8346 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8348 /* Add the DST variants. */
8349 d = (struct builtin_description *) bdesc_dst;
8350 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8351 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8353 /* Initialize the predicates. */
8354 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8355 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8357 enum machine_mode mode1;
8359 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8360 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8365 mode1 = insn_data[dp->icode].operand[1].mode;
8370 type = int_ftype_int_opaque_opaque;
8373 type = int_ftype_int_v4si_v4si;
8376 type = int_ftype_int_v8hi_v8hi;
8379 type = int_ftype_int_v16qi_v16qi;
8382 type = int_ftype_int_v4sf_v4sf;
8388 def_builtin (dp->mask, dp->name, type, dp->code);
8391 /* Initialize the abs* operators. */
8392 d = (struct builtin_description *) bdesc_abs;
8393 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8395 enum machine_mode mode0;
8398 mode0 = insn_data[d->icode].operand[0].mode;
8403 type = v4si_ftype_v4si;
8406 type = v8hi_ftype_v8hi;
8409 type = v16qi_ftype_v16qi;
8412 type = v4sf_ftype_v4sf;
8418 def_builtin (d->mask, d->name, type, d->code);
8425 /* Initialize target builtin that implements
8426 targetm.vectorize.builtin_mask_for_load. */
8428 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8429 v16qi_ftype_long_pcvoid,
8430 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8432 tree_cons (get_identifier ("const"),
8433 NULL_TREE, NULL_TREE));
8434 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8435 altivec_builtin_mask_for_load = decl;
8438 /* Access to the vec_init patterns. */
8439 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8440 integer_type_node, integer_type_node,
8441 integer_type_node, NULL_TREE);
8442 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8443 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8445 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8446 short_integer_type_node,
8447 short_integer_type_node,
8448 short_integer_type_node,
8449 short_integer_type_node,
8450 short_integer_type_node,
8451 short_integer_type_node,
8452 short_integer_type_node, NULL_TREE);
8453 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8454 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8456 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8457 char_type_node, char_type_node,
8458 char_type_node, char_type_node,
8459 char_type_node, char_type_node,
8460 char_type_node, char_type_node,
8461 char_type_node, char_type_node,
8462 char_type_node, char_type_node,
8463 char_type_node, char_type_node,
8464 char_type_node, NULL_TREE);
8465 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8466 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8468 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8469 float_type_node, float_type_node,
8470 float_type_node, NULL_TREE);
8471 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8472 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8474 /* Access to the vec_set patterns. */
8475 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8477 integer_type_node, NULL_TREE);
8478 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8479 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8481 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8483 integer_type_node, NULL_TREE);
8484 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8485 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8487 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8489 integer_type_node, NULL_TREE);
8490 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8491 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8493 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8495 integer_type_node, NULL_TREE);
8496 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8497 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8499 /* Access to the vec_extract patterns. */
8500 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8501 integer_type_node, NULL_TREE);
8502 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8503 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8505 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8506 integer_type_node, NULL_TREE);
8507 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8508 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8510 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8511 integer_type_node, NULL_TREE);
8512 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8513 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8515 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8516 integer_type_node, NULL_TREE);
8517 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8518 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8522 rs6000_common_init_builtins (void)
8524 struct builtin_description *d;
8527 tree v4sf_ftype_v4sf_v4sf_v16qi
8528 = build_function_type_list (V4SF_type_node,
8529 V4SF_type_node, V4SF_type_node,
8530 V16QI_type_node, NULL_TREE);
8531 tree v4si_ftype_v4si_v4si_v16qi
8532 = build_function_type_list (V4SI_type_node,
8533 V4SI_type_node, V4SI_type_node,
8534 V16QI_type_node, NULL_TREE);
8535 tree v8hi_ftype_v8hi_v8hi_v16qi
8536 = build_function_type_list (V8HI_type_node,
8537 V8HI_type_node, V8HI_type_node,
8538 V16QI_type_node, NULL_TREE);
8539 tree v16qi_ftype_v16qi_v16qi_v16qi
8540 = build_function_type_list (V16QI_type_node,
8541 V16QI_type_node, V16QI_type_node,
8542 V16QI_type_node, NULL_TREE);
8544 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8546 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8547 tree v16qi_ftype_int
8548 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8549 tree v8hi_ftype_v16qi
8550 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8551 tree v4sf_ftype_v4sf
8552 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8554 tree v2si_ftype_v2si_v2si
8555 = build_function_type_list (opaque_V2SI_type_node,
8556 opaque_V2SI_type_node,
8557 opaque_V2SI_type_node, NULL_TREE);
8559 tree v2sf_ftype_v2sf_v2sf
8560 = build_function_type_list (opaque_V2SF_type_node,
8561 opaque_V2SF_type_node,
8562 opaque_V2SF_type_node, NULL_TREE);
8564 tree v2si_ftype_int_int
8565 = build_function_type_list (opaque_V2SI_type_node,
8566 integer_type_node, integer_type_node,
8569 tree opaque_ftype_opaque
8570 = build_function_type_list (opaque_V4SI_type_node,
8571 opaque_V4SI_type_node, NULL_TREE);
8573 tree v2si_ftype_v2si
8574 = build_function_type_list (opaque_V2SI_type_node,
8575 opaque_V2SI_type_node, NULL_TREE);
8577 tree v2sf_ftype_v2sf
8578 = build_function_type_list (opaque_V2SF_type_node,
8579 opaque_V2SF_type_node, NULL_TREE);
8581 tree v2sf_ftype_v2si
8582 = build_function_type_list (opaque_V2SF_type_node,
8583 opaque_V2SI_type_node, NULL_TREE);
8585 tree v2si_ftype_v2sf
8586 = build_function_type_list (opaque_V2SI_type_node,
8587 opaque_V2SF_type_node, NULL_TREE);
8589 tree v2si_ftype_v2si_char
8590 = build_function_type_list (opaque_V2SI_type_node,
8591 opaque_V2SI_type_node,
8592 char_type_node, NULL_TREE);
8594 tree v2si_ftype_int_char
8595 = build_function_type_list (opaque_V2SI_type_node,
8596 integer_type_node, char_type_node, NULL_TREE);
8598 tree v2si_ftype_char
8599 = build_function_type_list (opaque_V2SI_type_node,
8600 char_type_node, NULL_TREE);
8602 tree int_ftype_int_int
8603 = build_function_type_list (integer_type_node,
8604 integer_type_node, integer_type_node,
8607 tree opaque_ftype_opaque_opaque
8608 = build_function_type_list (opaque_V4SI_type_node,
8609 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8610 tree v4si_ftype_v4si_v4si
8611 = build_function_type_list (V4SI_type_node,
8612 V4SI_type_node, V4SI_type_node, NULL_TREE);
8613 tree v4sf_ftype_v4si_int
8614 = build_function_type_list (V4SF_type_node,
8615 V4SI_type_node, integer_type_node, NULL_TREE);
8616 tree v4si_ftype_v4sf_int
8617 = build_function_type_list (V4SI_type_node,
8618 V4SF_type_node, integer_type_node, NULL_TREE);
8619 tree v4si_ftype_v4si_int
8620 = build_function_type_list (V4SI_type_node,
8621 V4SI_type_node, integer_type_node, NULL_TREE);
8622 tree v8hi_ftype_v8hi_int
8623 = build_function_type_list (V8HI_type_node,
8624 V8HI_type_node, integer_type_node, NULL_TREE);
8625 tree v16qi_ftype_v16qi_int
8626 = build_function_type_list (V16QI_type_node,
8627 V16QI_type_node, integer_type_node, NULL_TREE);
8628 tree v16qi_ftype_v16qi_v16qi_int
8629 = build_function_type_list (V16QI_type_node,
8630 V16QI_type_node, V16QI_type_node,
8631 integer_type_node, NULL_TREE);
8632 tree v8hi_ftype_v8hi_v8hi_int
8633 = build_function_type_list (V8HI_type_node,
8634 V8HI_type_node, V8HI_type_node,
8635 integer_type_node, NULL_TREE);
8636 tree v4si_ftype_v4si_v4si_int
8637 = build_function_type_list (V4SI_type_node,
8638 V4SI_type_node, V4SI_type_node,
8639 integer_type_node, NULL_TREE);
8640 tree v4sf_ftype_v4sf_v4sf_int
8641 = build_function_type_list (V4SF_type_node,
8642 V4SF_type_node, V4SF_type_node,
8643 integer_type_node, NULL_TREE);
8644 tree v4sf_ftype_v4sf_v4sf
8645 = build_function_type_list (V4SF_type_node,
8646 V4SF_type_node, V4SF_type_node, NULL_TREE);
8647 tree opaque_ftype_opaque_opaque_opaque
8648 = build_function_type_list (opaque_V4SI_type_node,
8649 opaque_V4SI_type_node, opaque_V4SI_type_node,
8650 opaque_V4SI_type_node, NULL_TREE);
8651 tree v4sf_ftype_v4sf_v4sf_v4si
8652 = build_function_type_list (V4SF_type_node,
8653 V4SF_type_node, V4SF_type_node,
8654 V4SI_type_node, NULL_TREE);
8655 tree v4sf_ftype_v4sf_v4sf_v4sf
8656 = build_function_type_list (V4SF_type_node,
8657 V4SF_type_node, V4SF_type_node,
8658 V4SF_type_node, NULL_TREE);
8659 tree v4si_ftype_v4si_v4si_v4si
8660 = build_function_type_list (V4SI_type_node,
8661 V4SI_type_node, V4SI_type_node,
8662 V4SI_type_node, NULL_TREE);
8663 tree v8hi_ftype_v8hi_v8hi
8664 = build_function_type_list (V8HI_type_node,
8665 V8HI_type_node, V8HI_type_node, NULL_TREE);
8666 tree v8hi_ftype_v8hi_v8hi_v8hi
8667 = build_function_type_list (V8HI_type_node,
8668 V8HI_type_node, V8HI_type_node,
8669 V8HI_type_node, NULL_TREE);
8670 tree v4si_ftype_v8hi_v8hi_v4si
8671 = build_function_type_list (V4SI_type_node,
8672 V8HI_type_node, V8HI_type_node,
8673 V4SI_type_node, NULL_TREE);
8674 tree v4si_ftype_v16qi_v16qi_v4si
8675 = build_function_type_list (V4SI_type_node,
8676 V16QI_type_node, V16QI_type_node,
8677 V4SI_type_node, NULL_TREE);
8678 tree v16qi_ftype_v16qi_v16qi
8679 = build_function_type_list (V16QI_type_node,
8680 V16QI_type_node, V16QI_type_node, NULL_TREE);
8681 tree v4si_ftype_v4sf_v4sf
8682 = build_function_type_list (V4SI_type_node,
8683 V4SF_type_node, V4SF_type_node, NULL_TREE);
8684 tree v8hi_ftype_v16qi_v16qi
8685 = build_function_type_list (V8HI_type_node,
8686 V16QI_type_node, V16QI_type_node, NULL_TREE);
8687 tree v4si_ftype_v8hi_v8hi
8688 = build_function_type_list (V4SI_type_node,
8689 V8HI_type_node, V8HI_type_node, NULL_TREE);
8690 tree v8hi_ftype_v4si_v4si
8691 = build_function_type_list (V8HI_type_node,
8692 V4SI_type_node, V4SI_type_node, NULL_TREE);
8693 tree v16qi_ftype_v8hi_v8hi
8694 = build_function_type_list (V16QI_type_node,
8695 V8HI_type_node, V8HI_type_node, NULL_TREE);
8696 tree v4si_ftype_v16qi_v4si
8697 = build_function_type_list (V4SI_type_node,
8698 V16QI_type_node, V4SI_type_node, NULL_TREE);
8699 tree v4si_ftype_v16qi_v16qi
8700 = build_function_type_list (V4SI_type_node,
8701 V16QI_type_node, V16QI_type_node, NULL_TREE);
8702 tree v4si_ftype_v8hi_v4si
8703 = build_function_type_list (V4SI_type_node,
8704 V8HI_type_node, V4SI_type_node, NULL_TREE);
8705 tree v4si_ftype_v8hi
8706 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8707 tree int_ftype_v4si_v4si
8708 = build_function_type_list (integer_type_node,
8709 V4SI_type_node, V4SI_type_node, NULL_TREE);
8710 tree int_ftype_v4sf_v4sf
8711 = build_function_type_list (integer_type_node,
8712 V4SF_type_node, V4SF_type_node, NULL_TREE);
8713 tree int_ftype_v16qi_v16qi
8714 = build_function_type_list (integer_type_node,
8715 V16QI_type_node, V16QI_type_node, NULL_TREE);
8716 tree int_ftype_v8hi_v8hi
8717 = build_function_type_list (integer_type_node,
8718 V8HI_type_node, V8HI_type_node, NULL_TREE);
8720 /* Add the simple ternary operators. */
8721 d = (struct builtin_description *) bdesc_3arg;
8722 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8724 enum machine_mode mode0, mode1, mode2, mode3;
8726 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8727 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8738 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8741 mode0 = insn_data[d->icode].operand[0].mode;
8742 mode1 = insn_data[d->icode].operand[1].mode;
8743 mode2 = insn_data[d->icode].operand[2].mode;
8744 mode3 = insn_data[d->icode].operand[3].mode;
8747 /* When all four are of the same mode. */
8748 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8753 type = opaque_ftype_opaque_opaque_opaque;
8756 type = v4si_ftype_v4si_v4si_v4si;
8759 type = v4sf_ftype_v4sf_v4sf_v4sf;
8762 type = v8hi_ftype_v8hi_v8hi_v8hi;
8765 type = v16qi_ftype_v16qi_v16qi_v16qi;
8771 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8776 type = v4si_ftype_v4si_v4si_v16qi;
8779 type = v4sf_ftype_v4sf_v4sf_v16qi;
8782 type = v8hi_ftype_v8hi_v8hi_v16qi;
8785 type = v16qi_ftype_v16qi_v16qi_v16qi;
8791 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8792 && mode3 == V4SImode)
8793 type = v4si_ftype_v16qi_v16qi_v4si;
8794 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8795 && mode3 == V4SImode)
8796 type = v4si_ftype_v8hi_v8hi_v4si;
8797 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8798 && mode3 == V4SImode)
8799 type = v4sf_ftype_v4sf_v4sf_v4si;
8801 /* vchar, vchar, vchar, 4 bit literal. */
8802 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8804 type = v16qi_ftype_v16qi_v16qi_int;
8806 /* vshort, vshort, vshort, 4 bit literal. */
8807 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8809 type = v8hi_ftype_v8hi_v8hi_int;
8811 /* vint, vint, vint, 4 bit literal. */
8812 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8814 type = v4si_ftype_v4si_v4si_int;
8816 /* vfloat, vfloat, vfloat, 4 bit literal. */
8817 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8819 type = v4sf_ftype_v4sf_v4sf_int;
8824 def_builtin (d->mask, d->name, type, d->code);
8827 /* Add the simple binary operators. */
8828 d = (struct builtin_description *) bdesc_2arg;
8829 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8831 enum machine_mode mode0, mode1, mode2;
8833 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8834 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8844 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8847 mode0 = insn_data[d->icode].operand[0].mode;
8848 mode1 = insn_data[d->icode].operand[1].mode;
8849 mode2 = insn_data[d->icode].operand[2].mode;
8852 /* When all three operands are of the same mode. */
8853 if (mode0 == mode1 && mode1 == mode2)
8858 type = opaque_ftype_opaque_opaque;
8861 type = v4sf_ftype_v4sf_v4sf;
8864 type = v4si_ftype_v4si_v4si;
8867 type = v16qi_ftype_v16qi_v16qi;
8870 type = v8hi_ftype_v8hi_v8hi;
8873 type = v2si_ftype_v2si_v2si;
8876 type = v2sf_ftype_v2sf_v2sf;
8879 type = int_ftype_int_int;
8886 /* A few other combos we really don't want to do manually. */
8888 /* vint, vfloat, vfloat. */
8889 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8890 type = v4si_ftype_v4sf_v4sf;
8892 /* vshort, vchar, vchar. */
8893 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8894 type = v8hi_ftype_v16qi_v16qi;
8896 /* vint, vshort, vshort. */
8897 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8898 type = v4si_ftype_v8hi_v8hi;
8900 /* vshort, vint, vint. */
8901 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8902 type = v8hi_ftype_v4si_v4si;
8904 /* vchar, vshort, vshort. */
8905 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8906 type = v16qi_ftype_v8hi_v8hi;
8908 /* vint, vchar, vint. */
8909 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8910 type = v4si_ftype_v16qi_v4si;
8912 /* vint, vchar, vchar. */
8913 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8914 type = v4si_ftype_v16qi_v16qi;
8916 /* vint, vshort, vint. */
8917 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8918 type = v4si_ftype_v8hi_v4si;
8920 /* vint, vint, 5 bit literal. */
8921 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8922 type = v4si_ftype_v4si_int;
8924 /* vshort, vshort, 5 bit literal. */
8925 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8926 type = v8hi_ftype_v8hi_int;
8928 /* vchar, vchar, 5 bit literal. */
8929 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8930 type = v16qi_ftype_v16qi_int;
8932 /* vfloat, vint, 5 bit literal. */
8933 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8934 type = v4sf_ftype_v4si_int;
8936 /* vint, vfloat, 5 bit literal. */
8937 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8938 type = v4si_ftype_v4sf_int;
8940 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8941 type = v2si_ftype_int_int;
8943 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8944 type = v2si_ftype_v2si_char;
8946 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8947 type = v2si_ftype_int_char;
8952 gcc_assert (mode0 == SImode);
8956 type = int_ftype_v4si_v4si;
8959 type = int_ftype_v4sf_v4sf;
8962 type = int_ftype_v16qi_v16qi;
8965 type = int_ftype_v8hi_v8hi;
8972 def_builtin (d->mask, d->name, type, d->code);
8975 /* Add the simple unary operators. */
8976 d = (struct builtin_description *) bdesc_1arg;
8977 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8979 enum machine_mode mode0, mode1;
8981 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8982 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8991 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8994 mode0 = insn_data[d->icode].operand[0].mode;
8995 mode1 = insn_data[d->icode].operand[1].mode;
8998 if (mode0 == V4SImode && mode1 == QImode)
8999 type = v4si_ftype_int;
9000 else if (mode0 == V8HImode && mode1 == QImode)
9001 type = v8hi_ftype_int;
9002 else if (mode0 == V16QImode && mode1 == QImode)
9003 type = v16qi_ftype_int;
9004 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9005 type = opaque_ftype_opaque;
9006 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9007 type = v4sf_ftype_v4sf;
9008 else if (mode0 == V8HImode && mode1 == V16QImode)
9009 type = v8hi_ftype_v16qi;
9010 else if (mode0 == V4SImode && mode1 == V8HImode)
9011 type = v4si_ftype_v8hi;
9012 else if (mode0 == V2SImode && mode1 == V2SImode)
9013 type = v2si_ftype_v2si;
9014 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9015 type = v2sf_ftype_v2sf;
9016 else if (mode0 == V2SFmode && mode1 == V2SImode)
9017 type = v2sf_ftype_v2si;
9018 else if (mode0 == V2SImode && mode1 == V2SFmode)
9019 type = v2si_ftype_v2sf;
9020 else if (mode0 == V2SImode && mode1 == QImode)
9021 type = v2si_ftype_char;
9025 def_builtin (d->mask, d->name, type, d->code);
9030 rs6000_init_libfuncs (void)
9032 if (!TARGET_HARD_FLOAT)
9035 if (DEFAULT_ABI != ABI_V4)
9037 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
9039 /* AIX library routines for float->int conversion. */
9040 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9041 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9042 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9043 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9046 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9047 if (!TARGET_XL_COMPAT)
9049 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9050 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9051 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9052 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9056 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9057 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9058 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9059 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9064 /* 32-bit SVR4 quad floating point routines. */
9066 set_optab_libfunc (add_optab, TFmode, "_q_add");
9067 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9068 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9069 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9070 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9071 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9072 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9074 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9075 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9076 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9077 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9078 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9079 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9081 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9082 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9083 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9084 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9085 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9086 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9087 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9088 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9093 /* Expand a block clear operation, and return 1 if successful. Return 0
9094 if we should let the compiler generate normal code.
9096 operands[0] is the destination
9097 operands[1] is the length
9098 operands[3] is the alignment */
9101 expand_block_clear (rtx operands[])
9103 rtx orig_dest = operands[0];
9104 rtx bytes_rtx = operands[1];
9105 rtx align_rtx = operands[3];
9106 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9107 HOST_WIDE_INT align;
9108 HOST_WIDE_INT bytes;
9113 /* If this is not a fixed size move, just call memcpy */
9117 /* This must be a fixed size alignment */
9118 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9119 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9121 /* Anything to clear? */
9122 bytes = INTVAL (bytes_rtx);
9126 /* Use the builtin memset after a point, to avoid huge code bloat.
9127 When optimize_size, avoid any significant code bloat; calling
9128 memset is about 4 instructions, so allow for one instruction to
9129 load zero and three to do clearing. */
9130 if (TARGET_ALTIVEC && align >= 128)
9132 else if (TARGET_POWERPC64 && align >= 32)
9137 if (optimize_size && bytes > 3 * clear_step)
9139 if (! optimize_size && bytes > 8 * clear_step)
9142 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9144 enum machine_mode mode = BLKmode;
9147 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9152 else if (bytes >= 8 && TARGET_POWERPC64
9153 /* 64-bit loads and stores require word-aligned
9155 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9160 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9161 { /* move 4 bytes */
9165 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9166 { /* move 2 bytes */
9170 else /* move 1 byte at a time */
9176 dest = adjust_address (orig_dest, mode, offset);
9178 emit_move_insn (dest, CONST0_RTX (mode));
9185 /* Expand a block move operation, and return 1 if successful. Return 0
9186 if we should let the compiler generate normal code.
9188 operands[0] is the destination
9189 operands[1] is the source
9190 operands[2] is the length
9191 operands[3] is the alignment */
9193 #define MAX_MOVE_REG 4
9196 expand_block_move (rtx operands[])
9198 rtx orig_dest = operands[0];
9199 rtx orig_src = operands[1];
9200 rtx bytes_rtx = operands[2];
9201 rtx align_rtx = operands[3];
9202 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9207 rtx stores[MAX_MOVE_REG];
9210 /* If this is not a fixed size move, just call memcpy */
9214 /* This must be a fixed size alignment */
9215 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9216 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9218 /* Anything to move? */
9219 bytes = INTVAL (bytes_rtx);
9223 /* store_one_arg depends on expand_block_move to handle at least the size of
9224 reg_parm_stack_space. */
9225 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9228 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9231 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9232 rtx (*mov) (rtx, rtx);
9234 enum machine_mode mode = BLKmode;
9237 /* Altivec first, since it will be faster than a string move
9238 when it applies, and usually not significantly larger. */
9239 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9243 gen_func.mov = gen_movv4si;
9245 else if (TARGET_STRING
9246 && bytes > 24 /* move up to 32 bytes at a time */
9254 && ! fixed_regs[12])
9256 move_bytes = (bytes > 32) ? 32 : bytes;
9257 gen_func.movmemsi = gen_movmemsi_8reg;
9259 else if (TARGET_STRING
9260 && bytes > 16 /* move up to 24 bytes at a time */
9266 && ! fixed_regs[10])
9268 move_bytes = (bytes > 24) ? 24 : bytes;
9269 gen_func.movmemsi = gen_movmemsi_6reg;
9271 else if (TARGET_STRING
9272 && bytes > 8 /* move up to 16 bytes at a time */
9278 move_bytes = (bytes > 16) ? 16 : bytes;
9279 gen_func.movmemsi = gen_movmemsi_4reg;
9281 else if (bytes >= 8 && TARGET_POWERPC64
9282 /* 64-bit loads and stores require word-aligned
9284 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9288 gen_func.mov = gen_movdi;
9290 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9291 { /* move up to 8 bytes at a time */
9292 move_bytes = (bytes > 8) ? 8 : bytes;
9293 gen_func.movmemsi = gen_movmemsi_2reg;
9295 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9296 { /* move 4 bytes */
9299 gen_func.mov = gen_movsi;
9301 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9302 { /* move 2 bytes */
9305 gen_func.mov = gen_movhi;
9307 else if (TARGET_STRING && bytes > 1)
9308 { /* move up to 4 bytes at a time */
9309 move_bytes = (bytes > 4) ? 4 : bytes;
9310 gen_func.movmemsi = gen_movmemsi_1reg;
9312 else /* move 1 byte at a time */
9316 gen_func.mov = gen_movqi;
9319 src = adjust_address (orig_src, mode, offset);
9320 dest = adjust_address (orig_dest, mode, offset);
9322 if (mode != BLKmode)
9324 rtx tmp_reg = gen_reg_rtx (mode);
9326 emit_insn ((*gen_func.mov) (tmp_reg, src));
9327 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9330 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9333 for (i = 0; i < num_reg; i++)
9334 emit_insn (stores[i]);
9338 if (mode == BLKmode)
9340 /* Move the address into scratch registers. The movmemsi
9341 patterns require zero offset. */
9342 if (!REG_P (XEXP (src, 0)))
9344 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9345 src = replace_equiv_address (src, src_reg);
9347 set_mem_size (src, GEN_INT (move_bytes));
9349 if (!REG_P (XEXP (dest, 0)))
9351 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9352 dest = replace_equiv_address (dest, dest_reg);
9354 set_mem_size (dest, GEN_INT (move_bytes));
9356 emit_insn ((*gen_func.movmemsi) (dest, src,
9357 GEN_INT (move_bytes & 31),
9366 /* Return a string to perform a load_multiple operation.
9367 operands[0] is the vector.
9368 operands[1] is the source address.
9369 operands[2] is the first destination register. */
9372 rs6000_output_load_multiple (rtx operands[3])
9374 /* We have to handle the case where the pseudo used to contain the address
9375 is assigned to one of the output registers. */
9377 int words = XVECLEN (operands[0], 0);
9380 if (XVECLEN (operands[0], 0) == 1)
9381 return "{l|lwz} %2,0(%1)";
9383 for (i = 0; i < words; i++)
9384 if (refers_to_regno_p (REGNO (operands[2]) + i,
9385 REGNO (operands[2]) + i + 1, operands[1], 0))
9389 xop[0] = GEN_INT (4 * (words-1));
9390 xop[1] = operands[1];
9391 xop[2] = operands[2];
9392 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9397 xop[0] = GEN_INT (4 * (words-1));
9398 xop[1] = operands[1];
9399 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9400 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9405 for (j = 0; j < words; j++)
9408 xop[0] = GEN_INT (j * 4);
9409 xop[1] = operands[1];
9410 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9411 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9413 xop[0] = GEN_INT (i * 4);
9414 xop[1] = operands[1];
9415 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9420 return "{lsi|lswi} %2,%1,%N0";
9424 /* A validation routine: say whether CODE, a condition code, and MODE
9425 match. The other alternatives either don't make sense or should
9426 never be generated. */
9429 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9431 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9432 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9433 && GET_MODE_CLASS (mode) == MODE_CC);
9435 /* These don't make sense. */
9436 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9437 || mode != CCUNSmode);
9439 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9440 || mode == CCUNSmode);
9442 gcc_assert (mode == CCFPmode
9443 || (code != ORDERED && code != UNORDERED
9444 && code != UNEQ && code != LTGT
9445 && code != UNGT && code != UNLT
9446 && code != UNGE && code != UNLE));
9448 /* These should never be generated except for
9449 flag_finite_math_only. */
9450 gcc_assert (mode != CCFPmode
9451 || flag_finite_math_only
9452 || (code != LE && code != GE
9453 && code != UNEQ && code != LTGT
9454 && code != UNGT && code != UNLT));
9456 /* These are invalid; the information is not there. */
9457 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9461 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9462 mask required to convert the result of a rotate insn into a shift
9463 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9466 includes_lshift_p (rtx shiftop, rtx andop)
9468 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9470 shift_mask <<= INTVAL (shiftop);
9472 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9475 /* Similar, but for right shift. */
9478 includes_rshift_p (rtx shiftop, rtx andop)
9480 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9482 shift_mask >>= INTVAL (shiftop);
9484 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9487 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9488 to perform a left shift. It must have exactly SHIFTOP least
9489 significant 0's, then one or more 1's, then zero or more 0's. */
9492 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9494 if (GET_CODE (andop) == CONST_INT)
9496 HOST_WIDE_INT c, lsb, shift_mask;
9499 if (c == 0 || c == ~0)
9503 shift_mask <<= INTVAL (shiftop);
9505 /* Find the least significant one bit. */
9508 /* It must coincide with the LSB of the shift mask. */
9509 if (-lsb != shift_mask)
9512 /* Invert to look for the next transition (if any). */
9515 /* Remove the low group of ones (originally low group of zeros). */
9518 /* Again find the lsb, and check we have all 1's above. */
9522 else if (GET_CODE (andop) == CONST_DOUBLE
9523 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9525 HOST_WIDE_INT low, high, lsb;
9526 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9528 low = CONST_DOUBLE_LOW (andop);
9529 if (HOST_BITS_PER_WIDE_INT < 64)
9530 high = CONST_DOUBLE_HIGH (andop);
9532 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9533 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9536 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9538 shift_mask_high = ~0;
9539 if (INTVAL (shiftop) > 32)
9540 shift_mask_high <<= INTVAL (shiftop) - 32;
9544 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9551 return high == -lsb;
9554 shift_mask_low = ~0;
9555 shift_mask_low <<= INTVAL (shiftop);
9559 if (-lsb != shift_mask_low)
9562 if (HOST_BITS_PER_WIDE_INT < 64)
9567 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9570 return high == -lsb;
9574 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9580 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9581 to perform a left shift. It must have SHIFTOP or more least
9582 significant 0's, with the remainder of the word 1's. */
9585 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9587 if (GET_CODE (andop) == CONST_INT)
9589 HOST_WIDE_INT c, lsb, shift_mask;
9592 shift_mask <<= INTVAL (shiftop);
9595 /* Find the least significant one bit. */
9598 /* It must be covered by the shift mask.
9599 This test also rejects c == 0. */
9600 if ((lsb & shift_mask) == 0)
9603 /* Check we have all 1's above the transition, and reject all 1's. */
9604 return c == -lsb && lsb != 1;
9606 else if (GET_CODE (andop) == CONST_DOUBLE
9607 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9609 HOST_WIDE_INT low, lsb, shift_mask_low;
9611 low = CONST_DOUBLE_LOW (andop);
9613 if (HOST_BITS_PER_WIDE_INT < 64)
9615 HOST_WIDE_INT high, shift_mask_high;
9617 high = CONST_DOUBLE_HIGH (andop);
9621 shift_mask_high = ~0;
9622 if (INTVAL (shiftop) > 32)
9623 shift_mask_high <<= INTVAL (shiftop) - 32;
9627 if ((lsb & shift_mask_high) == 0)
9630 return high == -lsb;
9636 shift_mask_low = ~0;
9637 shift_mask_low <<= INTVAL (shiftop);
9641 if ((lsb & shift_mask_low) == 0)
9644 return low == -lsb && lsb != 1;
9650 /* Return 1 if operands will generate a valid arguments to rlwimi
9651 instruction for insert with right shift in 64-bit mode. The mask may
9652 not start on the first bit or stop on the last bit because wrap-around
9653 effects of instruction do not correspond to semantics of RTL insn. */
9656 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9658 if (INTVAL (startop) < 64
9659 && INTVAL (startop) > 32
9660 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9661 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9662 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9663 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9664 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9670 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9671 for lfq and stfq insns iff the registers are hard registers. */
9674 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9676 /* We might have been passed a SUBREG. */
9677 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9680 /* We might have been passed non floating point registers. */
9681 if (!FP_REGNO_P (REGNO (reg1))
9682 || !FP_REGNO_P (REGNO (reg2)))
9685 return (REGNO (reg1) == REGNO (reg2) - 1);
9688 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9689 addr1 and addr2 must be in consecutive memory locations
9690 (addr2 == addr1 + 8). */
9693 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9696 unsigned int reg1, reg2;
9697 int offset1, offset2;
9699 /* The mems cannot be volatile. */
9700 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9703 addr1 = XEXP (mem1, 0);
9704 addr2 = XEXP (mem2, 0);
9706 /* Extract an offset (if used) from the first addr. */
9707 if (GET_CODE (addr1) == PLUS)
9709 /* If not a REG, return zero. */
9710 if (GET_CODE (XEXP (addr1, 0)) != REG)
9714 reg1 = REGNO (XEXP (addr1, 0));
9715 /* The offset must be constant! */
9716 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9718 offset1 = INTVAL (XEXP (addr1, 1));
9721 else if (GET_CODE (addr1) != REG)
9725 reg1 = REGNO (addr1);
9726 /* This was a simple (mem (reg)) expression. Offset is 0. */
9730 /* And now for the second addr. */
9731 if (GET_CODE (addr2) == PLUS)
9733 /* If not a REG, return zero. */
9734 if (GET_CODE (XEXP (addr2, 0)) != REG)
9738 reg2 = REGNO (XEXP (addr2, 0));
9739 /* The offset must be constant. */
9740 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9742 offset2 = INTVAL (XEXP (addr2, 1));
9745 else if (GET_CODE (addr2) != REG)
9749 reg2 = REGNO (addr2);
9750 /* This was a simple (mem (reg)) expression. Offset is 0. */
9754 /* Both of these must have the same base register. */
9758 /* The offset for the second addr must be 8 more than the first addr. */
9759 if (offset2 != offset1 + 8)
9762 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9767 /* Return the register class of a scratch register needed to copy IN into
9768 or out of a register in CLASS in MODE. If it can be done directly,
9769 NO_REGS is returned. */
9772 rs6000_secondary_reload_class (enum reg_class class,
9773 enum machine_mode mode ATTRIBUTE_UNUSED,
9778 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9780 && MACHOPIC_INDIRECT
9784 /* We cannot copy a symbolic operand directly into anything
9785 other than BASE_REGS for TARGET_ELF. So indicate that a
9786 register from BASE_REGS is needed as an intermediate
9789 On Darwin, pic addresses require a load from memory, which
9790 needs a base register. */
9791 if (class != BASE_REGS
9792 && (GET_CODE (in) == SYMBOL_REF
9793 || GET_CODE (in) == HIGH
9794 || GET_CODE (in) == LABEL_REF
9795 || GET_CODE (in) == CONST))
9799 if (GET_CODE (in) == REG)
9802 if (regno >= FIRST_PSEUDO_REGISTER)
9804 regno = true_regnum (in);
9805 if (regno >= FIRST_PSEUDO_REGISTER)
9809 else if (GET_CODE (in) == SUBREG)
9811 regno = true_regnum (in);
9812 if (regno >= FIRST_PSEUDO_REGISTER)
9818 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9820 if (class == GENERAL_REGS || class == BASE_REGS
9821 || (regno >= 0 && INT_REGNO_P (regno)))
9824 /* Constants, memory, and FP registers can go into FP registers. */
9825 if ((regno == -1 || FP_REGNO_P (regno))
9826 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9829 /* Memory, and AltiVec registers can go into AltiVec registers. */
9830 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9831 && class == ALTIVEC_REGS)
9834 /* We can copy among the CR registers. */
9835 if ((class == CR_REGS || class == CR0_REGS)
9836 && regno >= 0 && CR_REGNO_P (regno))
9839 /* Otherwise, we need GENERAL_REGS. */
9840 return GENERAL_REGS;
9843 /* Given a comparison operation, return the bit number in CCR to test. We
9844 know this is a valid comparison.
9846 SCC_P is 1 if this is for an scc. That means that %D will have been
9847 used instead of %C, so the bits will be in different places.
9849 Return -1 if OP isn't a valid comparison for some reason. */
9852 ccr_bit (rtx op, int scc_p)
9854 enum rtx_code code = GET_CODE (op);
9855 enum machine_mode cc_mode;
9860 if (!COMPARISON_P (op))
9865 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9867 cc_mode = GET_MODE (reg);
9868 cc_regnum = REGNO (reg);
9869 base_bit = 4 * (cc_regnum - CR0_REGNO);
9871 validate_condition_mode (code, cc_mode);
9873 /* When generating a sCOND operation, only positive conditions are
9876 || code == EQ || code == GT || code == LT || code == UNORDERED
9877 || code == GTU || code == LTU);
9882 return scc_p ? base_bit + 3 : base_bit + 2;
9884 return base_bit + 2;
9885 case GT: case GTU: case UNLE:
9886 return base_bit + 1;
9887 case LT: case LTU: case UNGE:
9889 case ORDERED: case UNORDERED:
9890 return base_bit + 3;
9893 /* If scc, we will have done a cror to put the bit in the
9894 unordered position. So test that bit. For integer, this is ! LT
9895 unless this is an scc insn. */
9896 return scc_p ? base_bit + 3 : base_bit;
9899 return scc_p ? base_bit + 3 : base_bit + 1;
9906 /* Return the GOT register. */
9909 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9911 /* The second flow pass currently (June 1999) can't update
9912 regs_ever_live without disturbing other parts of the compiler, so
9913 update it here to make the prolog/epilogue code happy. */
9914 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9915 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9917 current_function_uses_pic_offset_table = 1;
9919 return pic_offset_table_rtx;
9922 /* Function to init struct machine_function.
9923 This will be called, via a pointer variable,
9924 from push_function_context. */
9926 static struct machine_function *
9927 rs6000_init_machine_status (void)
9929 return ggc_alloc_cleared (sizeof (machine_function));
9932 /* These macros test for integers and extract the low-order bits. */
9934 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9935 && GET_MODE (X) == VOIDmode)
9937 #define INT_LOWPART(X) \
9938 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9944 unsigned long val = INT_LOWPART (op);
9946 /* If the high bit is zero, the value is the first 1 bit we find
9948 if ((val & 0x80000000) == 0)
9950 gcc_assert (val & 0xffffffff);
9953 while (((val <<= 1) & 0x80000000) == 0)
9958 /* If the high bit is set and the low bit is not, or the mask is all
9959 1's, the value is zero. */
9960 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9963 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9966 while (((val >>= 1) & 1) != 0)
9976 unsigned long val = INT_LOWPART (op);
9978 /* If the low bit is zero, the value is the first 1 bit we find from
9982 gcc_assert (val & 0xffffffff);
9985 while (((val >>= 1) & 1) == 0)
9991 /* If the low bit is set and the high bit is not, or the mask is all
9992 1's, the value is 31. */
9993 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9996 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9999 while (((val <<= 1) & 0x80000000) != 0)
10005 /* Locate some local-dynamic symbol still in use by this function
10006 so that we can print its name in some tls_ld pattern. */
10008 static const char *
10009 rs6000_get_some_local_dynamic_name (void)
10013 if (cfun->machine->some_ld_name)
10014 return cfun->machine->some_ld_name;
10016 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10018 && for_each_rtx (&PATTERN (insn),
10019 rs6000_get_some_local_dynamic_name_1, 0))
10020 return cfun->machine->some_ld_name;
10022 gcc_unreachable ();
10025 /* Helper function for rs6000_get_some_local_dynamic_name. */
10028 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10032 if (GET_CODE (x) == SYMBOL_REF)
10034 const char *str = XSTR (x, 0);
10035 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10037 cfun->machine->some_ld_name = str;
10045 /* Write out a function code label. */
10048 rs6000_output_function_entry (FILE *file, const char *fname)
10050 if (fname[0] != '.')
10052 switch (DEFAULT_ABI)
10055 gcc_unreachable ();
10061 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10070 RS6000_OUTPUT_BASENAME (file, fname);
10072 assemble_name (file, fname);
10075 /* Print an operand. Recognize special options, documented below. */
10078 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10079 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10081 #define SMALL_DATA_RELOC "sda21"
10082 #define SMALL_DATA_REG 0
10086 print_operand (FILE *file, rtx x, int code)
10090 unsigned HOST_WIDE_INT uval;
10095 /* Write out an instruction after the call which may be replaced
10096 with glue code by the loader. This depends on the AIX version. */
10097 asm_fprintf (file, RS6000_CALL_GLUE);
10100 /* %a is output_address. */
10103 /* If X is a constant integer whose low-order 5 bits are zero,
10104 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10105 in the AIX assembler where "sri" with a zero shift count
10106 writes a trash instruction. */
10107 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10114 /* If constant, low-order 16 bits of constant, unsigned.
10115 Otherwise, write normally. */
10117 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10119 print_operand (file, x, 0);
10123 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10124 for 64-bit mask direction. */
10125 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10128 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10132 /* X is a CR register. Print the number of the GT bit of the CR. */
10133 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10134 output_operand_lossage ("invalid %%E value");
10136 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10140 /* Like 'J' but get to the EQ bit. */
10141 gcc_assert (GET_CODE (x) == REG);
10143 /* Bit 1 is EQ bit. */
10144 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10146 fprintf (file, "%d", i);
10150 /* X is a CR register. Print the number of the EQ bit of the CR */
10151 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10152 output_operand_lossage ("invalid %%E value");
10154 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10158 /* X is a CR register. Print the shift count needed to move it
10159 to the high-order four bits. */
10160 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10161 output_operand_lossage ("invalid %%f value");
10163 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10167 /* Similar, but print the count for the rotate in the opposite
10169 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10170 output_operand_lossage ("invalid %%F value");
10172 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10176 /* X is a constant integer. If it is negative, print "m",
10177 otherwise print "z". This is to make an aze or ame insn. */
10178 if (GET_CODE (x) != CONST_INT)
10179 output_operand_lossage ("invalid %%G value");
10180 else if (INTVAL (x) >= 0)
10187 /* If constant, output low-order five bits. Otherwise, write
10190 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10192 print_operand (file, x, 0);
10196 /* If constant, output low-order six bits. Otherwise, write
10199 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10201 print_operand (file, x, 0);
10205 /* Print `i' if this is a constant, else nothing. */
10211 /* Write the bit number in CCR for jump. */
10212 i = ccr_bit (x, 0);
10214 output_operand_lossage ("invalid %%j code");
10216 fprintf (file, "%d", i);
10220 /* Similar, but add one for shift count in rlinm for scc and pass
10221 scc flag to `ccr_bit'. */
10222 i = ccr_bit (x, 1);
10224 output_operand_lossage ("invalid %%J code");
10226 /* If we want bit 31, write a shift count of zero, not 32. */
10227 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10231 /* X must be a constant. Write the 1's complement of the
10234 output_operand_lossage ("invalid %%k value");
10236 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10240 /* X must be a symbolic constant on ELF. Write an
10241 expression suitable for an 'addi' that adds in the low 16
10242 bits of the MEM. */
10243 if (GET_CODE (x) != CONST)
10245 print_operand_address (file, x);
10246 fputs ("@l", file);
10250 if (GET_CODE (XEXP (x, 0)) != PLUS
10251 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10252 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10253 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10254 output_operand_lossage ("invalid %%K value");
10255 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10256 fputs ("@l", file);
10257 /* For GNU as, there must be a non-alphanumeric character
10258 between 'l' and the number. The '-' is added by
10259 print_operand() already. */
10260 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10262 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10266 /* %l is output_asm_label. */
10269 /* Write second word of DImode or DFmode reference. Works on register
10270 or non-indexed memory only. */
10271 if (GET_CODE (x) == REG)
10272 fputs (reg_names[REGNO (x) + 1], file);
10273 else if (GET_CODE (x) == MEM)
10275 /* Handle possible auto-increment. Since it is pre-increment and
10276 we have already done it, we can just use an offset of word. */
10277 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10278 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10279 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10282 output_address (XEXP (adjust_address_nv (x, SImode,
10286 if (small_data_operand (x, GET_MODE (x)))
10287 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10288 reg_names[SMALL_DATA_REG]);
10293 /* MB value for a mask operand. */
10294 if (! mask_operand (x, SImode))
10295 output_operand_lossage ("invalid %%m value");
10297 fprintf (file, "%d", extract_MB (x));
10301 /* ME value for a mask operand. */
10302 if (! mask_operand (x, SImode))
10303 output_operand_lossage ("invalid %%M value");
10305 fprintf (file, "%d", extract_ME (x));
10308 /* %n outputs the negative of its operand. */
10311 /* Write the number of elements in the vector times 4. */
10312 if (GET_CODE (x) != PARALLEL)
10313 output_operand_lossage ("invalid %%N value");
10315 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10319 /* Similar, but subtract 1 first. */
10320 if (GET_CODE (x) != PARALLEL)
10321 output_operand_lossage ("invalid %%O value");
10323 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10327 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10329 || INT_LOWPART (x) < 0
10330 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10331 output_operand_lossage ("invalid %%p value");
10333 fprintf (file, "%d", i);
10337 /* The operand must be an indirect memory reference. The result
10338 is the register name. */
10339 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10340 || REGNO (XEXP (x, 0)) >= 32)
10341 output_operand_lossage ("invalid %%P value");
10343 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10347 /* This outputs the logical code corresponding to a boolean
10348 expression. The expression may have one or both operands
10349 negated (if one, only the first one). For condition register
10350 logical operations, it will also treat the negated
10351 CR codes as NOTs, but not handle NOTs of them. */
10353 const char *const *t = 0;
10355 enum rtx_code code = GET_CODE (x);
10356 static const char * const tbl[3][3] = {
10357 { "and", "andc", "nor" },
10358 { "or", "orc", "nand" },
10359 { "xor", "eqv", "xor" } };
10363 else if (code == IOR)
10365 else if (code == XOR)
10368 output_operand_lossage ("invalid %%q value");
10370 if (GET_CODE (XEXP (x, 0)) != NOT)
10374 if (GET_CODE (XEXP (x, 1)) == NOT)
10392 /* X is a CR register. Print the mask for `mtcrf'. */
10393 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10394 output_operand_lossage ("invalid %%R value");
10396 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10400 /* Low 5 bits of 32 - value */
10402 output_operand_lossage ("invalid %%s value");
10404 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10408 /* PowerPC64 mask position. All 0's is excluded.
10409 CONST_INT 32-bit mask is considered sign-extended so any
10410 transition must occur within the CONST_INT, not on the boundary. */
10411 if (! mask64_operand (x, DImode))
10412 output_operand_lossage ("invalid %%S value");
10414 uval = INT_LOWPART (x);
10416 if (uval & 1) /* Clear Left */
10418 #if HOST_BITS_PER_WIDE_INT > 64
10419 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10423 else /* Clear Right */
10426 #if HOST_BITS_PER_WIDE_INT > 64
10427 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10433 gcc_assert (i >= 0);
10434 fprintf (file, "%d", i);
10438 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10439 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10441 /* Bit 3 is OV bit. */
10442 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10444 /* If we want bit 31, write a shift count of zero, not 32. */
10445 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10449 /* Print the symbolic name of a branch target register. */
10450 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10451 && REGNO (x) != COUNT_REGISTER_REGNUM))
10452 output_operand_lossage ("invalid %%T value");
10453 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10454 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10456 fputs ("ctr", file);
10460 /* High-order 16 bits of constant for use in unsigned operand. */
10462 output_operand_lossage ("invalid %%u value");
10464 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10465 (INT_LOWPART (x) >> 16) & 0xffff);
10469 /* High-order 16 bits of constant for use in signed operand. */
10471 output_operand_lossage ("invalid %%v value");
10473 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10474 (INT_LOWPART (x) >> 16) & 0xffff);
10478 /* Print `u' if this has an auto-increment or auto-decrement. */
10479 if (GET_CODE (x) == MEM
10480 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10481 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10486 /* Print the trap code for this operand. */
10487 switch (GET_CODE (x))
10490 fputs ("eq", file); /* 4 */
10493 fputs ("ne", file); /* 24 */
10496 fputs ("lt", file); /* 16 */
10499 fputs ("le", file); /* 20 */
10502 fputs ("gt", file); /* 8 */
10505 fputs ("ge", file); /* 12 */
10508 fputs ("llt", file); /* 2 */
10511 fputs ("lle", file); /* 6 */
10514 fputs ("lgt", file); /* 1 */
10517 fputs ("lge", file); /* 5 */
10520 gcc_unreachable ();
10525 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10528 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10529 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10531 print_operand (file, x, 0);
10535 /* MB value for a PowerPC64 rldic operand. */
10536 val = (GET_CODE (x) == CONST_INT
10537 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10542 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10543 if ((val <<= 1) < 0)
10546 #if HOST_BITS_PER_WIDE_INT == 32
10547 if (GET_CODE (x) == CONST_INT && i >= 0)
10548 i += 32; /* zero-extend high-part was all 0's */
10549 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10551 val = CONST_DOUBLE_LOW (x);
10557 for ( ; i < 64; i++)
10558 if ((val <<= 1) < 0)
10563 fprintf (file, "%d", i + 1);
10567 if (GET_CODE (x) == MEM
10568 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10573 /* Like 'L', for third word of TImode */
10574 if (GET_CODE (x) == REG)
10575 fputs (reg_names[REGNO (x) + 2], file);
10576 else if (GET_CODE (x) == MEM)
10578 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10579 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10580 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10582 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10583 if (small_data_operand (x, GET_MODE (x)))
10584 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10585 reg_names[SMALL_DATA_REG]);
10590 /* X is a SYMBOL_REF. Write out the name preceded by a
10591 period and without any trailing data in brackets. Used for function
10592 names. If we are configured for System V (or the embedded ABI) on
10593 the PowerPC, do not emit the period, since those systems do not use
10594 TOCs and the like. */
10595 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10597 /* Mark the decl as referenced so that cgraph will output the
10599 if (SYMBOL_REF_DECL (x))
10600 mark_decl_referenced (SYMBOL_REF_DECL (x));
10602 /* For macho, check to see if we need a stub. */
10605 const char *name = XSTR (x, 0);
10607 if (MACHOPIC_INDIRECT
10608 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10609 name = machopic_indirection_name (x, /*stub_p=*/true);
10611 assemble_name (file, name);
10613 else if (!DOT_SYMBOLS)
10614 assemble_name (file, XSTR (x, 0));
10616 rs6000_output_function_entry (file, XSTR (x, 0));
10620 /* Like 'L', for last word of TImode. */
10621 if (GET_CODE (x) == REG)
10622 fputs (reg_names[REGNO (x) + 3], file);
10623 else if (GET_CODE (x) == MEM)
10625 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10626 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10627 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10629 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10630 if (small_data_operand (x, GET_MODE (x)))
10631 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10632 reg_names[SMALL_DATA_REG]);
10636 /* Print AltiVec or SPE memory operand. */
10641 gcc_assert (GET_CODE (x) == MEM);
10647 /* Handle [reg]. */
10648 if (GET_CODE (tmp) == REG)
10650 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10653 /* Handle [reg+UIMM]. */
10654 else if (GET_CODE (tmp) == PLUS &&
10655 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10659 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10661 x = INTVAL (XEXP (tmp, 1));
10662 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10666 /* Fall through. Must be [reg+reg]. */
10669 && GET_CODE (tmp) == AND
10670 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10671 && INTVAL (XEXP (tmp, 1)) == -16)
10672 tmp = XEXP (tmp, 0);
10673 if (GET_CODE (tmp) == REG)
10674 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10677 gcc_assert (GET_CODE (tmp) == PLUS
10678 && REG_P (XEXP (tmp, 0))
10679 && REG_P (XEXP (tmp, 1)));
10681 if (REGNO (XEXP (tmp, 0)) == 0)
10682 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10683 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10685 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10686 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10692 if (GET_CODE (x) == REG)
10693 fprintf (file, "%s", reg_names[REGNO (x)]);
10694 else if (GET_CODE (x) == MEM)
10696 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10697 know the width from the mode. */
10698 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10699 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10700 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10701 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10702 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10703 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10705 output_address (XEXP (x, 0));
10708 output_addr_const (file, x);
10712 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10716 output_operand_lossage ("invalid %%xn code");
10720 /* Print the address of an operand. */
10723 print_operand_address (FILE *file, rtx x)
10725 if (GET_CODE (x) == REG)
10726 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10727 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10728 || GET_CODE (x) == LABEL_REF)
10730 output_addr_const (file, x);
10731 if (small_data_operand (x, GET_MODE (x)))
10732 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10733 reg_names[SMALL_DATA_REG]);
10735 gcc_assert (!TARGET_TOC);
10737 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10739 gcc_assert (REG_P (XEXP (x, 0)));
10740 if (REGNO (XEXP (x, 0)) == 0)
10741 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10742 reg_names[ REGNO (XEXP (x, 0)) ]);
10744 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10745 reg_names[ REGNO (XEXP (x, 1)) ]);
10747 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10748 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10749 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10751 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10752 && CONSTANT_P (XEXP (x, 1)))
10754 output_addr_const (file, XEXP (x, 1));
10755 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10759 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10760 && CONSTANT_P (XEXP (x, 1)))
10762 fprintf (file, "lo16(");
10763 output_addr_const (file, XEXP (x, 1));
10764 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10767 else if (legitimate_constant_pool_address_p (x))
10769 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10771 rtx contains_minus = XEXP (x, 1);
10775 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10776 turn it into (sym) for output_addr_const. */
10777 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10778 contains_minus = XEXP (contains_minus, 0);
10780 minus = XEXP (contains_minus, 0);
10781 symref = XEXP (minus, 0);
10782 XEXP (contains_minus, 0) = symref;
10787 name = XSTR (symref, 0);
10788 newname = alloca (strlen (name) + sizeof ("@toc"));
10789 strcpy (newname, name);
10790 strcat (newname, "@toc");
10791 XSTR (symref, 0) = newname;
10793 output_addr_const (file, XEXP (x, 1));
10795 XSTR (symref, 0) = name;
10796 XEXP (contains_minus, 0) = minus;
10799 output_addr_const (file, XEXP (x, 1));
10801 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10804 gcc_unreachable ();
10807 /* Target hook for assembling integer objects. The PowerPC version has
10808 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10809 is defined. It also needs to handle DI-mode objects on 64-bit
10813 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10815 #ifdef RELOCATABLE_NEEDS_FIXUP
10816 /* Special handling for SI values. */
10817 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10819 static int recurse = 0;
10821 /* For -mrelocatable, we mark all addresses that need to be fixed up
10822 in the .fixup section. */
10823 if (TARGET_RELOCATABLE
10824 && in_section != toc_section
10825 && in_section != text_section
10826 && unlikely_text_section_p (in_section)
10828 && GET_CODE (x) != CONST_INT
10829 && GET_CODE (x) != CONST_DOUBLE
10835 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10837 ASM_OUTPUT_LABEL (asm_out_file, buf);
10838 fprintf (asm_out_file, "\t.long\t(");
10839 output_addr_const (asm_out_file, x);
10840 fprintf (asm_out_file, ")@fixup\n");
10841 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10842 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10843 fprintf (asm_out_file, "\t.long\t");
10844 assemble_name (asm_out_file, buf);
10845 fprintf (asm_out_file, "\n\t.previous\n");
10849 /* Remove initial .'s to turn a -mcall-aixdesc function
10850 address into the address of the descriptor, not the function
10852 else if (GET_CODE (x) == SYMBOL_REF
10853 && XSTR (x, 0)[0] == '.'
10854 && DEFAULT_ABI == ABI_AIX)
10856 const char *name = XSTR (x, 0);
10857 while (*name == '.')
10860 fprintf (asm_out_file, "\t.long\t%s\n", name);
10864 #endif /* RELOCATABLE_NEEDS_FIXUP */
10865 return default_assemble_integer (x, size, aligned_p);
10868 #ifdef HAVE_GAS_HIDDEN
10869 /* Emit an assembler directive to set symbol visibility for DECL to
10870 VISIBILITY_TYPE. */
10873 rs6000_assemble_visibility (tree decl, int vis)
10875 /* Functions need to have their entry point symbol visibility set as
10876 well as their descriptor symbol visibility. */
10877 if (DEFAULT_ABI == ABI_AIX
10879 && TREE_CODE (decl) == FUNCTION_DECL)
10881 static const char * const visibility_types[] = {
10882 NULL, "internal", "hidden", "protected"
10885 const char *name, *type;
10887 name = ((* targetm.strip_name_encoding)
10888 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10889 type = visibility_types[vis];
10891 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10892 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10895 default_assemble_visibility (decl, vis);
10900 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10902 /* Reversal of FP compares takes care -- an ordered compare
10903 becomes an unordered compare and vice versa. */
10904 if (mode == CCFPmode
10905 && (!flag_finite_math_only
10906 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10907 || code == UNEQ || code == LTGT))
10908 return reverse_condition_maybe_unordered (code);
10910 return reverse_condition (code);
10913 /* Generate a compare for CODE. Return a brand-new rtx that
10914 represents the result of the compare. */
10917 rs6000_generate_compare (enum rtx_code code)
10919 enum machine_mode comp_mode;
10920 rtx compare_result;
10922 if (rs6000_compare_fp_p)
10923 comp_mode = CCFPmode;
10924 else if (code == GTU || code == LTU
10925 || code == GEU || code == LEU)
10926 comp_mode = CCUNSmode;
10927 else if ((code == EQ || code == NE)
10928 && GET_CODE (rs6000_compare_op0) == SUBREG
10929 && GET_CODE (rs6000_compare_op1) == SUBREG
10930 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10931 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10932 /* These are unsigned values, perhaps there will be a later
10933 ordering compare that can be shared with this one.
10934 Unfortunately we cannot detect the signedness of the operands
10935 for non-subregs. */
10936 comp_mode = CCUNSmode;
10938 comp_mode = CCmode;
10940 /* First, the compare. */
10941 compare_result = gen_reg_rtx (comp_mode);
10943 /* SPE FP compare instructions on the GPRs. Yuck! */
10944 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10945 && rs6000_compare_fp_p)
10947 rtx cmp, or_result, compare_result2;
10948 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10950 if (op_mode == VOIDmode)
10951 op_mode = GET_MODE (rs6000_compare_op1);
10953 /* Note: The E500 comparison instructions set the GT bit (x +
10954 1), on success. This explains the mess. */
10958 case EQ: case UNEQ: case NE: case LTGT:
10962 cmp = flag_unsafe_math_optimizations
10963 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10964 rs6000_compare_op1)
10965 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10966 rs6000_compare_op1);
10970 cmp = flag_unsafe_math_optimizations
10971 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10972 rs6000_compare_op1)
10973 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10974 rs6000_compare_op1);
10978 gcc_unreachable ();
10982 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10986 cmp = flag_unsafe_math_optimizations
10987 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10988 rs6000_compare_op1)
10989 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10990 rs6000_compare_op1);
10994 cmp = flag_unsafe_math_optimizations
10995 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10996 rs6000_compare_op1)
10997 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10998 rs6000_compare_op1);
11002 gcc_unreachable ();
11006 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11010 cmp = flag_unsafe_math_optimizations
11011 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11012 rs6000_compare_op1)
11013 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11014 rs6000_compare_op1);
11018 cmp = flag_unsafe_math_optimizations
11019 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11020 rs6000_compare_op1)
11021 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11022 rs6000_compare_op1);
11026 gcc_unreachable ();
11030 gcc_unreachable ();
11033 /* Synthesize LE and GE from LT/GT || EQ. */
11034 if (code == LE || code == GE || code == LEU || code == GEU)
11040 case LE: code = LT; break;
11041 case GE: code = GT; break;
11042 case LEU: code = LT; break;
11043 case GEU: code = GT; break;
11044 default: gcc_unreachable ();
11047 compare_result2 = gen_reg_rtx (CCFPmode);
11053 cmp = flag_unsafe_math_optimizations
11054 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11055 rs6000_compare_op1)
11056 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11057 rs6000_compare_op1);
11061 cmp = flag_unsafe_math_optimizations
11062 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11063 rs6000_compare_op1)
11064 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11065 rs6000_compare_op1);
11069 gcc_unreachable ();
11073 /* OR them together. */
11074 or_result = gen_reg_rtx (CCFPmode);
11075 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11077 compare_result = or_result;
11082 if (code == NE || code == LTGT)
11092 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11093 CLOBBERs to match cmptf_internal2 pattern. */
11094 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11095 && GET_MODE (rs6000_compare_op0) == TFmode
11096 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11097 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11098 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11100 gen_rtx_SET (VOIDmode,
11102 gen_rtx_COMPARE (comp_mode,
11103 rs6000_compare_op0,
11104 rs6000_compare_op1)),
11105 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11106 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11107 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11108 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11109 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11110 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11111 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11112 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11113 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11114 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11116 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11117 comp_mode = CCEQmode;
11118 compare_result = gen_reg_rtx (CCEQmode);
11120 emit_insn (gen_stack_protect_testdi (compare_result,
11121 rs6000_compare_op0, op1));
11123 emit_insn (gen_stack_protect_testsi (compare_result,
11124 rs6000_compare_op0, op1));
11127 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11128 gen_rtx_COMPARE (comp_mode,
11129 rs6000_compare_op0,
11130 rs6000_compare_op1)));
11133 /* Some kinds of FP comparisons need an OR operation;
11134 under flag_finite_math_only we don't bother. */
11135 if (rs6000_compare_fp_p
11136 && !flag_finite_math_only
11137 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11138 && (code == LE || code == GE
11139 || code == UNEQ || code == LTGT
11140 || code == UNGT || code == UNLT))
11142 enum rtx_code or1, or2;
11143 rtx or1_rtx, or2_rtx, compare2_rtx;
11144 rtx or_result = gen_reg_rtx (CCEQmode);
11148 case LE: or1 = LT; or2 = EQ; break;
11149 case GE: or1 = GT; or2 = EQ; break;
11150 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11151 case LTGT: or1 = LT; or2 = GT; break;
11152 case UNGT: or1 = UNORDERED; or2 = GT; break;
11153 case UNLT: or1 = UNORDERED; or2 = LT; break;
11154 default: gcc_unreachable ();
11156 validate_condition_mode (or1, comp_mode);
11157 validate_condition_mode (or2, comp_mode);
11158 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11159 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11160 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11161 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11163 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11165 compare_result = or_result;
11169 validate_condition_mode (code, GET_MODE (compare_result));
11171 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11175 /* Emit the RTL for an sCOND pattern. */
11178 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11181 enum machine_mode op_mode;
11182 enum rtx_code cond_code;
11184 condition_rtx = rs6000_generate_compare (code);
11185 cond_code = GET_CODE (condition_rtx);
11187 if (TARGET_E500 && rs6000_compare_fp_p
11188 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11192 PUT_MODE (condition_rtx, SImode);
11193 t = XEXP (condition_rtx, 0);
11195 gcc_assert (cond_code == NE || cond_code == EQ);
11197 if (cond_code == NE)
11198 emit_insn (gen_e500_flip_gt_bit (t, t));
11200 emit_insn (gen_move_from_CR_gt_bit (result, t));
11204 if (cond_code == NE
11205 || cond_code == GE || cond_code == LE
11206 || cond_code == GEU || cond_code == LEU
11207 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11209 rtx not_result = gen_reg_rtx (CCEQmode);
11210 rtx not_op, rev_cond_rtx;
11211 enum machine_mode cc_mode;
11213 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11215 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11216 SImode, XEXP (condition_rtx, 0), const0_rtx);
11217 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11218 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11219 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11222 op_mode = GET_MODE (rs6000_compare_op0);
11223 if (op_mode == VOIDmode)
11224 op_mode = GET_MODE (rs6000_compare_op1);
11226 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11228 PUT_MODE (condition_rtx, DImode);
11229 convert_move (result, condition_rtx, 0);
11233 PUT_MODE (condition_rtx, SImode);
11234 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11238 /* Emit a branch of kind CODE to location LOC. */
11241 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11243 rtx condition_rtx, loc_ref;
11245 condition_rtx = rs6000_generate_compare (code);
11246 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11247 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11248 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11249 loc_ref, pc_rtx)));
11252 /* Return the string to output a conditional branch to LABEL, which is
11253 the operand number of the label, or -1 if the branch is really a
11254 conditional return.
11256 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11257 condition code register and its mode specifies what kind of
11258 comparison we made.
11260 REVERSED is nonzero if we should reverse the sense of the comparison.
11262 INSN is the insn. */
11265 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11267 static char string[64];
11268 enum rtx_code code = GET_CODE (op);
11269 rtx cc_reg = XEXP (op, 0);
11270 enum machine_mode mode = GET_MODE (cc_reg);
11271 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11272 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11273 int really_reversed = reversed ^ need_longbranch;
11279 validate_condition_mode (code, mode);
11281 /* Work out which way this really branches. We could use
11282 reverse_condition_maybe_unordered here always but this
11283 makes the resulting assembler clearer. */
11284 if (really_reversed)
11286 /* Reversal of FP compares takes care -- an ordered compare
11287 becomes an unordered compare and vice versa. */
11288 if (mode == CCFPmode)
11289 code = reverse_condition_maybe_unordered (code);
11291 code = reverse_condition (code);
11294 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11296 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11301 /* Opposite of GT. */
11310 gcc_unreachable ();
11316 /* Not all of these are actually distinct opcodes, but
11317 we distinguish them for clarity of the resulting assembler. */
11318 case NE: case LTGT:
11319 ccode = "ne"; break;
11320 case EQ: case UNEQ:
11321 ccode = "eq"; break;
11323 ccode = "ge"; break;
11324 case GT: case GTU: case UNGT:
11325 ccode = "gt"; break;
11327 ccode = "le"; break;
11328 case LT: case LTU: case UNLT:
11329 ccode = "lt"; break;
11330 case UNORDERED: ccode = "un"; break;
11331 case ORDERED: ccode = "nu"; break;
11332 case UNGE: ccode = "nl"; break;
11333 case UNLE: ccode = "ng"; break;
11335 gcc_unreachable ();
11338 /* Maybe we have a guess as to how likely the branch is.
11339 The old mnemonics don't have a way to specify this information. */
11341 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11342 if (note != NULL_RTX)
11344 /* PROB is the difference from 50%. */
11345 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11347 /* Only hint for highly probable/improbable branches on newer
11348 cpus as static prediction overrides processor dynamic
11349 prediction. For older cpus we may as well always hint, but
11350 assume not taken for branches that are very close to 50% as a
11351 mispredicted taken branch is more expensive than a
11352 mispredicted not-taken branch. */
11353 if (rs6000_always_hint
11354 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11356 if (abs (prob) > REG_BR_PROB_BASE / 20
11357 && ((prob > 0) ^ need_longbranch))
11365 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11367 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11369 /* We need to escape any '%' characters in the reg_names string.
11370 Assume they'd only be the first character.... */
11371 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11373 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11377 /* If the branch distance was too far, we may have to use an
11378 unconditional branch to go the distance. */
11379 if (need_longbranch)
11380 s += sprintf (s, ",$+8\n\tb %s", label);
11382 s += sprintf (s, ",%s", label);
11388 /* Return the string to flip the GT bit on a CR. */
11390 output_e500_flip_gt_bit (rtx dst, rtx src)
11392 static char string[64];
11395 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11396 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11399 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11400 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11402 sprintf (string, "crnot %d,%d", a, b);
11406 /* Return insn index for the vector compare instruction for given CODE,
11407 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11411 get_vec_cmp_insn (enum rtx_code code,
11412 enum machine_mode dest_mode,
11413 enum machine_mode op_mode)
11415 if (!TARGET_ALTIVEC)
11416 return INSN_NOT_AVAILABLE;
11421 if (dest_mode == V16QImode && op_mode == V16QImode)
11422 return UNSPEC_VCMPEQUB;
11423 if (dest_mode == V8HImode && op_mode == V8HImode)
11424 return UNSPEC_VCMPEQUH;
11425 if (dest_mode == V4SImode && op_mode == V4SImode)
11426 return UNSPEC_VCMPEQUW;
11427 if (dest_mode == V4SImode && op_mode == V4SFmode)
11428 return UNSPEC_VCMPEQFP;
11431 if (dest_mode == V4SImode && op_mode == V4SFmode)
11432 return UNSPEC_VCMPGEFP;
11434 if (dest_mode == V16QImode && op_mode == V16QImode)
11435 return UNSPEC_VCMPGTSB;
11436 if (dest_mode == V8HImode && op_mode == V8HImode)
11437 return UNSPEC_VCMPGTSH;
11438 if (dest_mode == V4SImode && op_mode == V4SImode)
11439 return UNSPEC_VCMPGTSW;
11440 if (dest_mode == V4SImode && op_mode == V4SFmode)
11441 return UNSPEC_VCMPGTFP;
11444 if (dest_mode == V16QImode && op_mode == V16QImode)
11445 return UNSPEC_VCMPGTUB;
11446 if (dest_mode == V8HImode && op_mode == V8HImode)
11447 return UNSPEC_VCMPGTUH;
11448 if (dest_mode == V4SImode && op_mode == V4SImode)
11449 return UNSPEC_VCMPGTUW;
11454 return INSN_NOT_AVAILABLE;
11457 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11458 DMODE is expected destination mode. This is a recursive function. */
11461 rs6000_emit_vector_compare (enum rtx_code rcode,
11463 enum machine_mode dmode)
11467 enum machine_mode dest_mode;
11468 enum machine_mode op_mode = GET_MODE (op1);
11470 gcc_assert (TARGET_ALTIVEC);
11471 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11473 /* Floating point vector compare instructions uses destination V4SImode.
11474 Move destination to appropriate mode later. */
11475 if (dmode == V4SFmode)
11476 dest_mode = V4SImode;
11480 mask = gen_reg_rtx (dest_mode);
11481 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11483 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11485 bool swap_operands = false;
11486 bool try_again = false;
11491 swap_operands = true;
11496 swap_operands = true;
11500 /* Treat A != B as ~(A==B). */
11502 enum insn_code nor_code;
11503 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11506 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11507 gcc_assert (nor_code != CODE_FOR_nothing);
11508 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11510 if (dmode != dest_mode)
11512 rtx temp = gen_reg_rtx (dest_mode);
11513 convert_move (temp, mask, 0);
11523 /* Try GT/GTU/LT/LTU OR EQ */
11526 enum insn_code ior_code;
11527 enum rtx_code new_code;
11548 gcc_unreachable ();
11551 c_rtx = rs6000_emit_vector_compare (new_code,
11552 op0, op1, dest_mode);
11553 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11556 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11557 gcc_assert (ior_code != CODE_FOR_nothing);
11558 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11559 if (dmode != dest_mode)
11561 rtx temp = gen_reg_rtx (dest_mode);
11562 convert_move (temp, mask, 0);
11569 gcc_unreachable ();
11574 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11575 /* You only get two chances. */
11576 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11588 emit_insn (gen_rtx_SET (VOIDmode, mask,
11589 gen_rtx_UNSPEC (dest_mode,
11590 gen_rtvec (2, op0, op1),
11592 if (dmode != dest_mode)
11594 rtx temp = gen_reg_rtx (dest_mode);
11595 convert_move (temp, mask, 0);
11601 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11602 valid insn doesn exist for given mode. */
11605 get_vsel_insn (enum machine_mode mode)
11610 return UNSPEC_VSEL4SI;
11613 return UNSPEC_VSEL4SF;
11616 return UNSPEC_VSEL8HI;
11619 return UNSPEC_VSEL16QI;
11622 return INSN_NOT_AVAILABLE;
11625 return INSN_NOT_AVAILABLE;
11628 /* Emit vector select insn where DEST is destination using
11629 operands OP1, OP2 and MASK. */
11632 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11635 enum machine_mode dest_mode = GET_MODE (dest);
11636 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11638 temp = gen_reg_rtx (dest_mode);
11640 /* For each vector element, select op1 when mask is 1 otherwise
11642 t = gen_rtx_SET (VOIDmode, temp,
11643 gen_rtx_UNSPEC (dest_mode,
11644 gen_rtvec (3, op2, op1, mask),
11647 emit_move_insn (dest, temp);
11651 /* Emit vector conditional expression.
11652 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11653 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11656 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11657 rtx cond, rtx cc_op0, rtx cc_op1)
11659 enum machine_mode dest_mode = GET_MODE (dest);
11660 enum rtx_code rcode = GET_CODE (cond);
11663 if (!TARGET_ALTIVEC)
11666 /* Get the vector mask for the given relational operations. */
11667 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11669 rs6000_emit_vector_select (dest, op1, op2, mask);
11674 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11675 operands of the last comparison is nonzero/true, FALSE_COND if it
11676 is zero/false. Return 0 if the hardware has no such operation. */
11679 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11681 enum rtx_code code = GET_CODE (op);
11682 rtx op0 = rs6000_compare_op0;
11683 rtx op1 = rs6000_compare_op1;
11684 REAL_VALUE_TYPE c1;
11685 enum machine_mode compare_mode = GET_MODE (op0);
11686 enum machine_mode result_mode = GET_MODE (dest);
11688 bool is_against_zero;
11690 /* These modes should always match. */
11691 if (GET_MODE (op1) != compare_mode
11692 /* In the isel case however, we can use a compare immediate, so
11693 op1 may be a small constant. */
11694 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11696 if (GET_MODE (true_cond) != result_mode)
11698 if (GET_MODE (false_cond) != result_mode)
11701 /* First, work out if the hardware can do this at all, or
11702 if it's too slow.... */
11703 if (! rs6000_compare_fp_p)
11706 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11709 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11710 && SCALAR_FLOAT_MODE_P (compare_mode))
11713 is_against_zero = op1 == CONST0_RTX (compare_mode);
11715 /* A floating-point subtract might overflow, underflow, or produce
11716 an inexact result, thus changing the floating-point flags, so it
11717 can't be generated if we care about that. It's safe if one side
11718 of the construct is zero, since then no subtract will be
11720 if (SCALAR_FLOAT_MODE_P (compare_mode)
11721 && flag_trapping_math && ! is_against_zero)
11724 /* Eliminate half of the comparisons by switching operands, this
11725 makes the remaining code simpler. */
11726 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11727 || code == LTGT || code == LT || code == UNLE)
11729 code = reverse_condition_maybe_unordered (code);
11731 true_cond = false_cond;
11735 /* UNEQ and LTGT take four instructions for a comparison with zero,
11736 it'll probably be faster to use a branch here too. */
11737 if (code == UNEQ && HONOR_NANS (compare_mode))
11740 if (GET_CODE (op1) == CONST_DOUBLE)
11741 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11743 /* We're going to try to implement comparisons by performing
11744 a subtract, then comparing against zero. Unfortunately,
11745 Inf - Inf is NaN which is not zero, and so if we don't
11746 know that the operand is finite and the comparison
11747 would treat EQ different to UNORDERED, we can't do it. */
11748 if (HONOR_INFINITIES (compare_mode)
11749 && code != GT && code != UNGE
11750 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11751 /* Constructs of the form (a OP b ? a : b) are safe. */
11752 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11753 || (! rtx_equal_p (op0, true_cond)
11754 && ! rtx_equal_p (op1, true_cond))))
11757 /* At this point we know we can use fsel. */
11759 /* Reduce the comparison to a comparison against zero. */
11760 if (! is_against_zero)
11762 temp = gen_reg_rtx (compare_mode);
11763 emit_insn (gen_rtx_SET (VOIDmode, temp,
11764 gen_rtx_MINUS (compare_mode, op0, op1)));
11766 op1 = CONST0_RTX (compare_mode);
11769 /* If we don't care about NaNs we can reduce some of the comparisons
11770 down to faster ones. */
11771 if (! HONOR_NANS (compare_mode))
11777 true_cond = false_cond;
11790 /* Now, reduce everything down to a GE. */
11797 temp = gen_reg_rtx (compare_mode);
11798 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11803 temp = gen_reg_rtx (compare_mode);
11804 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11809 temp = gen_reg_rtx (compare_mode);
11810 emit_insn (gen_rtx_SET (VOIDmode, temp,
11811 gen_rtx_NEG (compare_mode,
11812 gen_rtx_ABS (compare_mode, op0))));
11817 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11818 temp = gen_reg_rtx (result_mode);
11819 emit_insn (gen_rtx_SET (VOIDmode, temp,
11820 gen_rtx_IF_THEN_ELSE (result_mode,
11821 gen_rtx_GE (VOIDmode,
11823 true_cond, false_cond)));
11824 false_cond = true_cond;
11827 temp = gen_reg_rtx (compare_mode);
11828 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11833 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11834 temp = gen_reg_rtx (result_mode);
11835 emit_insn (gen_rtx_SET (VOIDmode, temp,
11836 gen_rtx_IF_THEN_ELSE (result_mode,
11837 gen_rtx_GE (VOIDmode,
11839 true_cond, false_cond)));
11840 true_cond = false_cond;
11843 temp = gen_reg_rtx (compare_mode);
11844 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11849 gcc_unreachable ();
11852 emit_insn (gen_rtx_SET (VOIDmode, dest,
11853 gen_rtx_IF_THEN_ELSE (result_mode,
11854 gen_rtx_GE (VOIDmode,
11856 true_cond, false_cond)));
11860 /* Same as above, but for ints (isel). */
11863 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11865 rtx condition_rtx, cr;
11867 /* All isel implementations thus far are 32-bits. */
11868 if (GET_MODE (rs6000_compare_op0) != SImode)
11871 /* We still have to do the compare, because isel doesn't do a
11872 compare, it just looks at the CRx bits set by a previous compare
11874 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11875 cr = XEXP (condition_rtx, 0);
11877 if (GET_MODE (cr) == CCmode)
11878 emit_insn (gen_isel_signed (dest, condition_rtx,
11879 true_cond, false_cond, cr));
11881 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11882 true_cond, false_cond, cr));
11888 output_isel (rtx *operands)
11890 enum rtx_code code;
11892 code = GET_CODE (operands[1]);
11893 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11895 PUT_CODE (operands[1], reverse_condition (code));
11896 return "isel %0,%3,%2,%j1";
11899 return "isel %0,%2,%3,%j1";
11903 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11905 enum machine_mode mode = GET_MODE (op0);
11909 if (code == SMAX || code == SMIN)
11914 if (code == SMAX || code == UMAX)
11915 target = emit_conditional_move (dest, c, op0, op1, mode,
11916 op0, op1, mode, 0);
11918 target = emit_conditional_move (dest, c, op0, op1, mode,
11919 op1, op0, mode, 0);
11920 gcc_assert (target);
11921 if (target != dest)
11922 emit_move_insn (dest, target);
11925 /* Emit instructions to perform a load-reserved/store-conditional operation.
11926 The operation performed is an atomic
11927 (set M (CODE:MODE M OP))
11928 If not NULL, BEFORE is atomically set to M before the operation, and
11929 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11930 If SYNC_P then a memory barrier is emitted before the operation.
11931 Either OP or M may be wrapped in a NOT operation. */
11934 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11935 rtx m, rtx op, rtx before_param, rtx after_param,
11938 enum machine_mode used_mode;
11939 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11942 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11943 rtx shift = NULL_RTX;
11946 emit_insn (gen_memory_barrier ());
11948 if (GET_CODE (m) == NOT)
11949 used_m = XEXP (m, 0);
11953 /* If this is smaller than SImode, we'll have to use SImode with
11955 if (mode == QImode || mode == HImode)
11959 if (MEM_ALIGN (used_m) >= 32)
11962 if (BYTES_BIG_ENDIAN)
11963 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11965 shift = GEN_INT (ishift);
11969 rtx addrSI, aligned_addr;
11970 int shift_mask = mode == QImode ? 0x18 : 0x10;
11972 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11973 XEXP (used_m, 0)));
11974 shift = gen_reg_rtx (SImode);
11976 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11977 GEN_INT (shift_mask)));
11978 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
11980 aligned_addr = expand_binop (Pmode, and_optab,
11982 GEN_INT (-4), NULL_RTX,
11983 1, OPTAB_LIB_WIDEN);
11984 used_m = change_address (used_m, SImode, aligned_addr);
11985 set_mem_align (used_m, 32);
11986 /* It's safe to keep the old alias set of USED_M, because
11987 the operation is atomic and only affects the original
11989 if (GET_CODE (m) == NOT)
11990 m = gen_rtx_NOT (SImode, used_m);
11995 if (GET_CODE (op) == NOT)
11997 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
11998 oldop = gen_rtx_NOT (SImode, oldop);
12001 oldop = lowpart_subreg (SImode, op, mode);
12007 newop = expand_binop (SImode, and_optab,
12008 oldop, GEN_INT (imask), NULL_RTX,
12009 1, OPTAB_LIB_WIDEN);
12010 emit_insn (gen_ashlsi3 (newop, newop, shift));
12014 newop = expand_binop (SImode, ior_optab,
12015 oldop, GEN_INT (~imask), NULL_RTX,
12016 1, OPTAB_LIB_WIDEN);
12017 emit_insn (gen_rotlsi3 (newop, newop, shift));
12025 newop = expand_binop (SImode, and_optab,
12026 oldop, GEN_INT (imask), NULL_RTX,
12027 1, OPTAB_LIB_WIDEN);
12028 emit_insn (gen_ashlsi3 (newop, newop, shift));
12030 mask = gen_reg_rtx (SImode);
12031 emit_move_insn (mask, GEN_INT (imask));
12032 emit_insn (gen_ashlsi3 (mask, mask, shift));
12035 newop = gen_rtx_PLUS (SImode, m, newop);
12037 newop = gen_rtx_MINUS (SImode, m, newop);
12038 newop = gen_rtx_AND (SImode, newop, mask);
12039 newop = gen_rtx_IOR (SImode, newop,
12040 gen_rtx_AND (SImode,
12041 gen_rtx_NOT (SImode, mask),
12047 gcc_unreachable ();
12050 if (GET_CODE (m) == NOT)
12054 mask = gen_reg_rtx (SImode);
12055 emit_move_insn (mask, GEN_INT (imask));
12056 emit_insn (gen_ashlsi3 (mask, mask, shift));
12058 xorm = gen_rtx_XOR (SImode, used_m, mask);
12059 /* Depending on the value of 'op', the XOR or the operation might
12060 be able to be simplified away. */
12061 newop = simplify_gen_binary (code, SImode, xorm, newop);
12064 used_mode = SImode;
12065 before = gen_reg_rtx (used_mode);
12066 after = gen_reg_rtx (used_mode);
12071 before = before_param;
12072 after = after_param;
12074 if (before == NULL_RTX)
12075 before = gen_reg_rtx (used_mode);
12076 if (after == NULL_RTX)
12077 after = gen_reg_rtx (used_mode);
12080 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12081 && used_mode != mode)
12082 the_op = op; /* Computed above. */
12083 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12084 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12086 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12088 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12089 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12090 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12091 gen_rtx_UNSPEC (used_mode,
12092 gen_rtvec (1, the_op),
12094 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12096 if ((code == PLUS || code == MINUS) && used_mode != mode)
12097 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12098 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12100 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12101 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12103 /* Shift and mask the return values properly. */
12104 if (used_mode != mode && before_param)
12106 emit_insn (gen_lshrsi3 (before, before, shift));
12107 convert_move (before_param, before, 1);
12110 if (used_mode != mode && after_param)
12112 emit_insn (gen_lshrsi3 (after, after, shift));
12113 convert_move (after_param, after, 1);
12116 /* The previous sequence will end with a branch that's dependent on
12117 the conditional store, so placing an isync will ensure that no
12118 other instructions (especially, no load or store instructions)
12119 can start before the atomic operation completes. */
12121 emit_insn (gen_isync ());
12124 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12125 COND is true. Mark the jump as unlikely to be taken. */
12128 emit_unlikely_jump (rtx cond, rtx label)
12130 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12133 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12134 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12135 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12138 /* A subroutine of the atomic operation splitters. Emit a load-locked
12139 instruction in MODE. */
12142 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12144 rtx (*fn) (rtx, rtx) = NULL;
12145 if (mode == SImode)
12146 fn = gen_load_locked_si;
12147 else if (mode == DImode)
12148 fn = gen_load_locked_di;
12149 emit_insn (fn (reg, mem));
12152 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12153 instruction in MODE. */
12156 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12158 rtx (*fn) (rtx, rtx, rtx) = NULL;
12159 if (mode == SImode)
12160 fn = gen_store_conditional_si;
12161 else if (mode == DImode)
12162 fn = gen_store_conditional_di;
12164 /* Emit sync before stwcx. to address PPC405 Erratum. */
12165 if (PPC405_ERRATUM77)
12166 emit_insn (gen_memory_barrier ());
12168 emit_insn (fn (res, mem, val));
12171 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12172 to perform. MEM is the memory on which to operate. VAL is the second
12173 operand of the binary operator. BEFORE and AFTER are optional locations to
12174 return the value of MEM either before of after the operation. SCRATCH is
12175 a scratch register. */
12178 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12179 rtx before, rtx after, rtx scratch)
12181 enum machine_mode mode = GET_MODE (mem);
12182 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12184 emit_insn (gen_memory_barrier ());
12186 label = gen_label_rtx ();
12187 emit_label (label);
12188 label = gen_rtx_LABEL_REF (VOIDmode, label);
12190 if (before == NULL_RTX)
12192 emit_load_locked (mode, before, mem);
12195 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12196 else if (code == AND)
12197 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12199 x = gen_rtx_fmt_ee (code, mode, before, val);
12201 if (after != NULL_RTX)
12202 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12203 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12205 emit_store_conditional (mode, cond, mem, scratch);
12207 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12208 emit_unlikely_jump (x, label);
12210 emit_insn (gen_isync ());
12213 /* Expand an atomic compare and swap operation. MEM is the memory on which
12214 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12215 value to be stored. SCRATCH is a scratch GPR. */
12218 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12221 enum machine_mode mode = GET_MODE (mem);
12222 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12224 emit_insn (gen_memory_barrier ());
12226 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12227 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12228 emit_label (XEXP (label1, 0));
12230 emit_load_locked (mode, retval, mem);
12232 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12233 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12235 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12236 emit_unlikely_jump (x, label2);
12238 emit_move_insn (scratch, newval);
12239 emit_store_conditional (mode, cond, mem, scratch);
12241 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12242 emit_unlikely_jump (x, label1);
12244 emit_insn (gen_isync ());
12245 emit_label (XEXP (label2, 0));
12248 /* Expand an atomic test and set operation. MEM is the memory on which
12249 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12252 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12254 enum machine_mode mode = GET_MODE (mem);
12255 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12257 emit_insn (gen_memory_barrier ());
12259 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12260 emit_label (XEXP (label, 0));
12262 emit_load_locked (mode, retval, mem);
12263 emit_move_insn (scratch, val);
12264 emit_store_conditional (mode, cond, mem, scratch);
12266 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12267 emit_unlikely_jump (x, label);
12269 emit_insn (gen_isync ());
12272 /* Emit instructions to move SRC to DST. Called by splitters for
12273 multi-register moves. It will emit at most one instruction for
12274 each register that is accessed; that is, it won't emit li/lis pairs
12275 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12279 rs6000_split_multireg_move (rtx dst, rtx src)
12281 /* The register number of the first register being moved. */
12283 /* The mode that is to be moved. */
12284 enum machine_mode mode;
12285 /* The mode that the move is being done in, and its size. */
12286 enum machine_mode reg_mode;
12288 /* The number of registers that will be moved. */
12291 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12292 mode = GET_MODE (dst);
12293 nregs = hard_regno_nregs[reg][mode];
12294 if (FP_REGNO_P (reg))
12296 else if (ALTIVEC_REGNO_P (reg))
12297 reg_mode = V16QImode;
12299 reg_mode = word_mode;
12300 reg_mode_size = GET_MODE_SIZE (reg_mode);
12302 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12304 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12306 /* Move register range backwards, if we might have destructive
12309 for (i = nregs - 1; i >= 0; i--)
12310 emit_insn (gen_rtx_SET (VOIDmode,
12311 simplify_gen_subreg (reg_mode, dst, mode,
12312 i * reg_mode_size),
12313 simplify_gen_subreg (reg_mode, src, mode,
12314 i * reg_mode_size)));
12320 bool used_update = false;
12322 if (MEM_P (src) && INT_REGNO_P (reg))
12326 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12327 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12330 breg = XEXP (XEXP (src, 0), 0);
12331 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12332 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12333 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12334 emit_insn (TARGET_32BIT
12335 ? gen_addsi3 (breg, breg, delta_rtx)
12336 : gen_adddi3 (breg, breg, delta_rtx));
12337 src = replace_equiv_address (src, breg);
12339 else if (! offsettable_memref_p (src))
12342 basereg = gen_rtx_REG (Pmode, reg);
12343 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12344 src = replace_equiv_address (src, basereg);
12347 breg = XEXP (src, 0);
12348 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12349 breg = XEXP (breg, 0);
12351 /* If the base register we are using to address memory is
12352 also a destination reg, then change that register last. */
12354 && REGNO (breg) >= REGNO (dst)
12355 && REGNO (breg) < REGNO (dst) + nregs)
12356 j = REGNO (breg) - REGNO (dst);
12359 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12363 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12364 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12367 breg = XEXP (XEXP (dst, 0), 0);
12368 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12369 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12370 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12372 /* We have to update the breg before doing the store.
12373 Use store with update, if available. */
12377 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12378 emit_insn (TARGET_32BIT
12379 ? (TARGET_POWERPC64
12380 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12381 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12382 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12383 used_update = true;
12386 emit_insn (TARGET_32BIT
12387 ? gen_addsi3 (breg, breg, delta_rtx)
12388 : gen_adddi3 (breg, breg, delta_rtx));
12389 dst = replace_equiv_address (dst, breg);
12392 gcc_assert (offsettable_memref_p (dst));
12395 for (i = 0; i < nregs; i++)
12397 /* Calculate index to next subword. */
12402 /* If compiler already emitted move of first word by
12403 store with update, no need to do anything. */
12404 if (j == 0 && used_update)
12407 emit_insn (gen_rtx_SET (VOIDmode,
12408 simplify_gen_subreg (reg_mode, dst, mode,
12409 j * reg_mode_size),
12410 simplify_gen_subreg (reg_mode, src, mode,
12411 j * reg_mode_size)));
12417 /* This page contains routines that are used to determine what the
12418 function prologue and epilogue code will do and write them out. */
12420 /* Return the first fixed-point register that is required to be
12421 saved. 32 if none. */
12424 first_reg_to_save (void)
12428 /* Find lowest numbered live register. */
12429 for (first_reg = 13; first_reg <= 31; first_reg++)
12430 if (regs_ever_live[first_reg]
12431 && (! call_used_regs[first_reg]
12432 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12433 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12434 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12435 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12440 && current_function_uses_pic_offset_table
12441 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12442 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12448 /* Similar, for FP regs. */
12451 first_fp_reg_to_save (void)
12455 /* Find lowest numbered live register. */
12456 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12457 if (regs_ever_live[first_reg])
12463 /* Similar, for AltiVec regs. */
12466 first_altivec_reg_to_save (void)
12470 /* Stack frame remains as is unless we are in AltiVec ABI. */
12471 if (! TARGET_ALTIVEC_ABI)
12472 return LAST_ALTIVEC_REGNO + 1;
12474 /* Find lowest numbered live register. */
12475 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12476 if (regs_ever_live[i])
12482 /* Return a 32-bit mask of the AltiVec registers we need to set in
12483 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12484 the 32-bit word is 0. */
12486 static unsigned int
12487 compute_vrsave_mask (void)
12489 unsigned int i, mask = 0;
12491 /* First, find out if we use _any_ altivec registers. */
12492 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12493 if (regs_ever_live[i])
12494 mask |= ALTIVEC_REG_BIT (i);
12499 /* Next, remove the argument registers from the set. These must
12500 be in the VRSAVE mask set by the caller, so we don't need to add
12501 them in again. More importantly, the mask we compute here is
12502 used to generate CLOBBERs in the set_vrsave insn, and we do not
12503 wish the argument registers to die. */
12504 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12505 mask &= ~ALTIVEC_REG_BIT (i);
12507 /* Similarly, remove the return value from the set. */
12510 diddle_return_value (is_altivec_return_reg, &yes);
12512 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12518 /* For a very restricted set of circumstances, we can cut down the
12519 size of prologues/epilogues by calling our own save/restore-the-world
12523 compute_save_world_info (rs6000_stack_t *info_ptr)
12525 info_ptr->world_save_p = 1;
12526 info_ptr->world_save_p
12527 = (WORLD_SAVE_P (info_ptr)
12528 && DEFAULT_ABI == ABI_DARWIN
12529 && ! (current_function_calls_setjmp && flag_exceptions)
12530 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12531 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12532 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12533 && info_ptr->cr_save_p);
12535 /* This will not work in conjunction with sibcalls. Make sure there
12536 are none. (This check is expensive, but seldom executed.) */
12537 if (WORLD_SAVE_P (info_ptr))
12540 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12541 if ( GET_CODE (insn) == CALL_INSN
12542 && SIBLING_CALL_P (insn))
12544 info_ptr->world_save_p = 0;
12549 if (WORLD_SAVE_P (info_ptr))
12551 /* Even if we're not touching VRsave, make sure there's room on the
12552 stack for it, if it looks like we're calling SAVE_WORLD, which
12553 will attempt to save it. */
12554 info_ptr->vrsave_size = 4;
12556 /* "Save" the VRsave register too if we're saving the world. */
12557 if (info_ptr->vrsave_mask == 0)
12558 info_ptr->vrsave_mask = compute_vrsave_mask ();
12560 /* Because the Darwin register save/restore routines only handle
12561 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12563 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12564 && (info_ptr->first_altivec_reg_save
12565 >= FIRST_SAVED_ALTIVEC_REGNO));
12572 is_altivec_return_reg (rtx reg, void *xyes)
12574 bool *yes = (bool *) xyes;
12575 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12580 /* Calculate the stack information for the current function. This is
12581 complicated by having two separate calling sequences, the AIX calling
12582 sequence and the V.4 calling sequence.
12584 AIX (and Darwin/Mac OS X) stack frames look like:
12586 SP----> +---------------------------------------+
12587 | back chain to caller | 0 0
12588 +---------------------------------------+
12589 | saved CR | 4 8 (8-11)
12590 +---------------------------------------+
12592 +---------------------------------------+
12593 | reserved for compilers | 12 24
12594 +---------------------------------------+
12595 | reserved for binders | 16 32
12596 +---------------------------------------+
12597 | saved TOC pointer | 20 40
12598 +---------------------------------------+
12599 | Parameter save area (P) | 24 48
12600 +---------------------------------------+
12601 | Alloca space (A) | 24+P etc.
12602 +---------------------------------------+
12603 | Local variable space (L) | 24+P+A
12604 +---------------------------------------+
12605 | Float/int conversion temporary (X) | 24+P+A+L
12606 +---------------------------------------+
12607 | Save area for AltiVec registers (W) | 24+P+A+L+X
12608 +---------------------------------------+
12609 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12610 +---------------------------------------+
12611 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12612 +---------------------------------------+
12613 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12614 +---------------------------------------+
12615 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12616 +---------------------------------------+
12617 old SP->| back chain to caller's caller |
12618 +---------------------------------------+
12620 The required alignment for AIX configurations is two words (i.e., 8
12624 V.4 stack frames look like:
12626 SP----> +---------------------------------------+
12627 | back chain to caller | 0
12628 +---------------------------------------+
12629 | caller's saved LR | 4
12630 +---------------------------------------+
12631 | Parameter save area (P) | 8
12632 +---------------------------------------+
12633 | Alloca space (A) | 8+P
12634 +---------------------------------------+
12635 | Varargs save area (V) | 8+P+A
12636 +---------------------------------------+
12637 | Local variable space (L) | 8+P+A+V
12638 +---------------------------------------+
12639 | Float/int conversion temporary (X) | 8+P+A+V+L
12640 +---------------------------------------+
12641 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12642 +---------------------------------------+
12643 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12644 +---------------------------------------+
12645 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12646 +---------------------------------------+
12647 | SPE: area for 64-bit GP registers |
12648 +---------------------------------------+
12649 | SPE alignment padding |
12650 +---------------------------------------+
12651 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12652 +---------------------------------------+
12653 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12654 +---------------------------------------+
12655 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12656 +---------------------------------------+
12657 old SP->| back chain to caller's caller |
12658 +---------------------------------------+
12660 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12661 given. (But note below and in sysv4.h that we require only 8 and
12662 may round up the size of our stack frame anyways. The historical
12663 reason is early versions of powerpc-linux which didn't properly
12664 align the stack at program startup. A happy side-effect is that
12665 -mno-eabi libraries can be used with -meabi programs.)
12667 The EABI configuration defaults to the V.4 layout. However,
12668 the stack alignment requirements may differ. If -mno-eabi is not
12669 given, the required stack alignment is 8 bytes; if -mno-eabi is
12670 given, the required alignment is 16 bytes. (But see V.4 comment
12673 #ifndef ABI_STACK_BOUNDARY
12674 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12677 static rs6000_stack_t *
12678 rs6000_stack_info (void)
12680 static rs6000_stack_t info;
12681 rs6000_stack_t *info_ptr = &info;
12682 int reg_size = TARGET_32BIT ? 4 : 8;
12685 HOST_WIDE_INT non_fixed_size;
12687 memset (&info, 0, sizeof (info));
12691 /* Cache value so we don't rescan instruction chain over and over. */
12692 if (cfun->machine->insn_chain_scanned_p == 0)
12693 cfun->machine->insn_chain_scanned_p
12694 = spe_func_has_64bit_regs_p () + 1;
12695 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12698 /* Select which calling sequence. */
12699 info_ptr->abi = DEFAULT_ABI;
12701 /* Calculate which registers need to be saved & save area size. */
12702 info_ptr->first_gp_reg_save = first_reg_to_save ();
12703 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12704 even if it currently looks like we won't. */
12705 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12706 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12707 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12708 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12709 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12711 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12713 /* For the SPE, we have an additional upper 32-bits on each GPR.
12714 Ideally we should save the entire 64-bits only when the upper
12715 half is used in SIMD instructions. Since we only record
12716 registers live (not the size they are used in), this proves
12717 difficult because we'd have to traverse the instruction chain at
12718 the right time, taking reload into account. This is a real pain,
12719 so we opt to save the GPRs in 64-bits always if but one register
12720 gets used in 64-bits. Otherwise, all the registers in the frame
12721 get saved in 32-bits.
12723 So... since when we save all GPRs (except the SP) in 64-bits, the
12724 traditional GP save area will be empty. */
12725 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12726 info_ptr->gp_size = 0;
12728 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12729 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12731 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12732 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12733 - info_ptr->first_altivec_reg_save);
12735 /* Does this function call anything? */
12736 info_ptr->calls_p = (! current_function_is_leaf
12737 || cfun->machine->ra_needs_full_frame);
12739 /* Determine if we need to save the link register. */
12740 if ((DEFAULT_ABI == ABI_AIX
12741 && current_function_profile
12742 && !TARGET_PROFILE_KERNEL)
12743 #ifdef TARGET_RELOCATABLE
12744 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12746 || (info_ptr->first_fp_reg_save != 64
12747 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12748 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12749 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12750 || info_ptr->calls_p
12751 || rs6000_ra_ever_killed ())
12753 info_ptr->lr_save_p = 1;
12754 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12757 /* Determine if we need to save the condition code registers. */
12758 if (regs_ever_live[CR2_REGNO]
12759 || regs_ever_live[CR3_REGNO]
12760 || regs_ever_live[CR4_REGNO])
12762 info_ptr->cr_save_p = 1;
12763 if (DEFAULT_ABI == ABI_V4)
12764 info_ptr->cr_size = reg_size;
12767 /* If the current function calls __builtin_eh_return, then we need
12768 to allocate stack space for registers that will hold data for
12769 the exception handler. */
12770 if (current_function_calls_eh_return)
12773 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12776 /* SPE saves EH registers in 64-bits. */
12777 ehrd_size = i * (TARGET_SPE_ABI
12778 && info_ptr->spe_64bit_regs_used != 0
12779 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12784 /* Determine various sizes. */
12785 info_ptr->reg_size = reg_size;
12786 info_ptr->fixed_size = RS6000_SAVE_AREA;
12787 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12788 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12789 TARGET_ALTIVEC ? 16 : 8);
12790 if (FRAME_GROWS_DOWNWARD)
12791 info_ptr->vars_size
12792 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12793 + info_ptr->parm_size,
12794 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12795 - (info_ptr->fixed_size + info_ptr->vars_size
12796 + info_ptr->parm_size);
12798 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12799 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12801 info_ptr->spe_gp_size = 0;
12803 if (TARGET_ALTIVEC_ABI)
12804 info_ptr->vrsave_mask = compute_vrsave_mask ();
12806 info_ptr->vrsave_mask = 0;
12808 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12809 info_ptr->vrsave_size = 4;
12811 info_ptr->vrsave_size = 0;
12813 compute_save_world_info (info_ptr);
12815 /* Calculate the offsets. */
12816 switch (DEFAULT_ABI)
12820 gcc_unreachable ();
12824 info_ptr->fp_save_offset = - info_ptr->fp_size;
12825 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12827 if (TARGET_ALTIVEC_ABI)
12829 info_ptr->vrsave_save_offset
12830 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12832 /* Align stack so vector save area is on a quadword boundary. */
12833 if (info_ptr->altivec_size != 0)
12834 info_ptr->altivec_padding_size
12835 = 16 - (-info_ptr->vrsave_save_offset % 16);
12837 info_ptr->altivec_padding_size = 0;
12839 info_ptr->altivec_save_offset
12840 = info_ptr->vrsave_save_offset
12841 - info_ptr->altivec_padding_size
12842 - info_ptr->altivec_size;
12844 /* Adjust for AltiVec case. */
12845 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12848 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12849 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12850 info_ptr->lr_save_offset = 2*reg_size;
12854 info_ptr->fp_save_offset = - info_ptr->fp_size;
12855 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12856 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12858 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12860 /* Align stack so SPE GPR save area is aligned on a
12861 double-word boundary. */
12862 if (info_ptr->spe_gp_size != 0)
12863 info_ptr->spe_padding_size
12864 = 8 - (-info_ptr->cr_save_offset % 8);
12866 info_ptr->spe_padding_size = 0;
12868 info_ptr->spe_gp_save_offset
12869 = info_ptr->cr_save_offset
12870 - info_ptr->spe_padding_size
12871 - info_ptr->spe_gp_size;
12873 /* Adjust for SPE case. */
12874 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
12876 else if (TARGET_ALTIVEC_ABI)
12878 info_ptr->vrsave_save_offset
12879 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12881 /* Align stack so vector save area is on a quadword boundary. */
12882 if (info_ptr->altivec_size != 0)
12883 info_ptr->altivec_padding_size
12884 = 16 - (-info_ptr->vrsave_save_offset % 16);
12886 info_ptr->altivec_padding_size = 0;
12888 info_ptr->altivec_save_offset
12889 = info_ptr->vrsave_save_offset
12890 - info_ptr->altivec_padding_size
12891 - info_ptr->altivec_size;
12893 /* Adjust for AltiVec case. */
12894 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
12897 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
12898 info_ptr->ehrd_offset -= ehrd_size;
12899 info_ptr->lr_save_offset = reg_size;
12903 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12904 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12905 + info_ptr->gp_size
12906 + info_ptr->altivec_size
12907 + info_ptr->altivec_padding_size
12908 + info_ptr->spe_gp_size
12909 + info_ptr->spe_padding_size
12911 + info_ptr->cr_size
12912 + info_ptr->vrsave_size,
12915 non_fixed_size = (info_ptr->vars_size
12916 + info_ptr->parm_size
12917 + info_ptr->save_size);
12919 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12920 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12922 /* Determine if we need to allocate any stack frame:
12924 For AIX we need to push the stack if a frame pointer is needed
12925 (because the stack might be dynamically adjusted), if we are
12926 debugging, if we make calls, or if the sum of fp_save, gp_save,
12927 and local variables are more than the space needed to save all
12928 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12929 + 18*8 = 288 (GPR13 reserved).
12931 For V.4 we don't have the stack cushion that AIX uses, but assume
12932 that the debugger can handle stackless frames. */
12934 if (info_ptr->calls_p)
12935 info_ptr->push_p = 1;
12937 else if (DEFAULT_ABI == ABI_V4)
12938 info_ptr->push_p = non_fixed_size != 0;
12940 else if (frame_pointer_needed)
12941 info_ptr->push_p = 1;
12943 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12944 info_ptr->push_p = 1;
12947 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12949 /* Zero offsets if we're not saving those registers. */
12950 if (info_ptr->fp_size == 0)
12951 info_ptr->fp_save_offset = 0;
12953 if (info_ptr->gp_size == 0)
12954 info_ptr->gp_save_offset = 0;
12956 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12957 info_ptr->altivec_save_offset = 0;
12959 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12960 info_ptr->vrsave_save_offset = 0;
12962 if (! TARGET_SPE_ABI
12963 || info_ptr->spe_64bit_regs_used == 0
12964 || info_ptr->spe_gp_size == 0)
12965 info_ptr->spe_gp_save_offset = 0;
12967 if (! info_ptr->lr_save_p)
12968 info_ptr->lr_save_offset = 0;
12970 if (! info_ptr->cr_save_p)
12971 info_ptr->cr_save_offset = 0;
12976 /* Return true if the current function uses any GPRs in 64-bit SIMD
12980 spe_func_has_64bit_regs_p (void)
12984 /* Functions that save and restore all the call-saved registers will
12985 need to save/restore the registers in 64-bits. */
12986 if (current_function_calls_eh_return
12987 || current_function_calls_setjmp
12988 || current_function_has_nonlocal_goto)
12991 insns = get_insns ();
12993 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12999 /* FIXME: This should be implemented with attributes...
13001 (set_attr "spe64" "true")....then,
13002 if (get_spe64(insn)) return true;
13004 It's the only reliable way to do the stuff below. */
13006 i = PATTERN (insn);
13007 if (GET_CODE (i) == SET)
13009 enum machine_mode mode = GET_MODE (SET_SRC (i));
13011 if (SPE_VECTOR_MODE (mode))
13013 if (TARGET_E500_DOUBLE && mode == DFmode)
13023 debug_stack_info (rs6000_stack_t *info)
13025 const char *abi_string;
13028 info = rs6000_stack_info ();
13030 fprintf (stderr, "\nStack information for function %s:\n",
13031 ((current_function_decl && DECL_NAME (current_function_decl))
13032 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13037 default: abi_string = "Unknown"; break;
13038 case ABI_NONE: abi_string = "NONE"; break;
13039 case ABI_AIX: abi_string = "AIX"; break;
13040 case ABI_DARWIN: abi_string = "Darwin"; break;
13041 case ABI_V4: abi_string = "V.4"; break;
13044 fprintf (stderr, "\tABI = %5s\n", abi_string);
13046 if (TARGET_ALTIVEC_ABI)
13047 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13049 if (TARGET_SPE_ABI)
13050 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13052 if (info->first_gp_reg_save != 32)
13053 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13055 if (info->first_fp_reg_save != 64)
13056 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13058 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13059 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13060 info->first_altivec_reg_save);
13062 if (info->lr_save_p)
13063 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13065 if (info->cr_save_p)
13066 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13068 if (info->vrsave_mask)
13069 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13072 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13075 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13077 if (info->gp_save_offset)
13078 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13080 if (info->fp_save_offset)
13081 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13083 if (info->altivec_save_offset)
13084 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13085 info->altivec_save_offset);
13087 if (info->spe_gp_save_offset)
13088 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13089 info->spe_gp_save_offset);
13091 if (info->vrsave_save_offset)
13092 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13093 info->vrsave_save_offset);
13095 if (info->lr_save_offset)
13096 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13098 if (info->cr_save_offset)
13099 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13101 if (info->varargs_save_offset)
13102 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13104 if (info->total_size)
13105 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13108 if (info->vars_size)
13109 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13112 if (info->parm_size)
13113 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13115 if (info->fixed_size)
13116 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13119 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13121 if (info->spe_gp_size)
13122 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13125 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13127 if (info->altivec_size)
13128 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13130 if (info->vrsave_size)
13131 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13133 if (info->altivec_padding_size)
13134 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13135 info->altivec_padding_size);
13137 if (info->spe_padding_size)
13138 fprintf (stderr, "\tspe_padding_size = %5d\n",
13139 info->spe_padding_size);
13142 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13144 if (info->save_size)
13145 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13147 if (info->reg_size != 4)
13148 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13150 fprintf (stderr, "\n");
13154 rs6000_return_addr (int count, rtx frame)
13156 /* Currently we don't optimize very well between prolog and body
13157 code and for PIC code the code can be actually quite bad, so
13158 don't try to be too clever here. */
13159 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13161 cfun->machine->ra_needs_full_frame = 1;
13168 plus_constant (copy_to_reg
13169 (gen_rtx_MEM (Pmode,
13170 memory_address (Pmode, frame))),
13171 RETURN_ADDRESS_OFFSET)));
13174 cfun->machine->ra_need_lr = 1;
13175 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13178 /* Say whether a function is a candidate for sibcall handling or not.
13179 We do not allow indirect calls to be optimized into sibling calls.
13180 Also, we can't do it if there are any vector parameters; there's
13181 nowhere to put the VRsave code so it works; note that functions with
13182 vector parameters are required to have a prototype, so the argument
13183 type info must be available here. (The tail recursion case can work
13184 with vector parameters, but there's no way to distinguish here.) */
13186 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13191 if (TARGET_ALTIVEC_VRSAVE)
13193 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13194 type; type = TREE_CHAIN (type))
13196 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13200 if (DEFAULT_ABI == ABI_DARWIN
13201 || (*targetm.binds_local_p) (decl))
13203 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13205 if (!lookup_attribute ("longcall", attr_list)
13206 || lookup_attribute ("shortcall", attr_list))
13213 /* NULL if INSN insn is valid within a low-overhead loop.
13214 Otherwise return why doloop cannot be applied.
13215 PowerPC uses the COUNT register for branch on table instructions. */
13217 static const char *
13218 rs6000_invalid_within_doloop (rtx insn)
13221 return "Function call in the loop.";
13224 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13225 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13226 return "Computed branch in the loop.";
13232 rs6000_ra_ever_killed (void)
13238 if (current_function_is_thunk)
13241 /* regs_ever_live has LR marked as used if any sibcalls are present,
13242 but this should not force saving and restoring in the
13243 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13244 clobbers LR, so that is inappropriate. */
13246 /* Also, the prologue can generate a store into LR that
13247 doesn't really count, like this:
13250 bcl to set PIC register
13254 When we're called from the epilogue, we need to avoid counting
13255 this as a store. */
13257 push_topmost_sequence ();
13258 top = get_insns ();
13259 pop_topmost_sequence ();
13260 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13262 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13268 if (!SIBLING_CALL_P (insn))
13271 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13273 else if (set_of (reg, insn) != NULL_RTX
13274 && !prologue_epilogue_contains (insn))
13281 /* Add a REG_MAYBE_DEAD note to the insn. */
13283 rs6000_maybe_dead (rtx insn)
13285 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13290 /* Emit instructions needed to load the TOC register.
13291 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13292 a constant pool; or for SVR4 -fpic. */
13295 rs6000_emit_load_toc_table (int fromprolog)
13298 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13300 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13303 rtx lab, tmp1, tmp2, got, tempLR;
13305 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13306 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13308 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13310 got = rs6000_got_sym ();
13311 tmp1 = tmp2 = dest;
13314 tmp1 = gen_reg_rtx (Pmode);
13315 tmp2 = gen_reg_rtx (Pmode);
13317 tempLR = (fromprolog
13318 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13319 : gen_reg_rtx (Pmode));
13320 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13322 rs6000_maybe_dead (insn);
13323 insn = emit_move_insn (tmp1, tempLR);
13325 rs6000_maybe_dead (insn);
13326 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13328 rs6000_maybe_dead (insn);
13329 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13331 rs6000_maybe_dead (insn);
13333 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13335 rtx tempLR = (fromprolog
13336 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13337 : gen_reg_rtx (Pmode));
13339 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13341 rs6000_maybe_dead (insn);
13342 insn = emit_move_insn (dest, tempLR);
13344 rs6000_maybe_dead (insn);
13346 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13349 rtx tempLR = (fromprolog
13350 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13351 : gen_reg_rtx (Pmode));
13352 rtx temp0 = (fromprolog
13353 ? gen_rtx_REG (Pmode, 0)
13354 : gen_reg_rtx (Pmode));
13360 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13361 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13363 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13364 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13366 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13368 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13369 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13377 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13378 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13379 emit_move_insn (dest, tempLR);
13380 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13382 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13384 rs6000_maybe_dead (insn);
13386 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13388 /* This is for AIX code running in non-PIC ELF32. */
13391 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13392 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13394 insn = emit_insn (gen_elf_high (dest, realsym));
13396 rs6000_maybe_dead (insn);
13397 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13399 rs6000_maybe_dead (insn);
13403 gcc_assert (DEFAULT_ABI == ABI_AIX);
13406 insn = emit_insn (gen_load_toc_aix_si (dest));
13408 insn = emit_insn (gen_load_toc_aix_di (dest));
13410 rs6000_maybe_dead (insn);
13414 /* Emit instructions to restore the link register after determining where
13415 its value has been stored. */
13418 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13420 rs6000_stack_t *info = rs6000_stack_info ();
13423 operands[0] = source;
13424 operands[1] = scratch;
13426 if (info->lr_save_p)
13428 rtx frame_rtx = stack_pointer_rtx;
13429 HOST_WIDE_INT sp_offset = 0;
13432 if (frame_pointer_needed
13433 || current_function_calls_alloca
13434 || info->total_size > 32767)
13436 tmp = gen_frame_mem (Pmode, frame_rtx);
13437 emit_move_insn (operands[1], tmp);
13438 frame_rtx = operands[1];
13440 else if (info->push_p)
13441 sp_offset = info->total_size;
13443 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13444 tmp = gen_frame_mem (Pmode, tmp);
13445 emit_move_insn (tmp, operands[0]);
13448 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13451 static GTY(()) int set = -1;
13454 get_TOC_alias_set (void)
13457 set = new_alias_set ();
13461 /* This returns nonzero if the current function uses the TOC. This is
13462 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13463 is generated by the ABI_V4 load_toc_* patterns. */
13470 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13473 rtx pat = PATTERN (insn);
13476 if (GET_CODE (pat) == PARALLEL)
13477 for (i = 0; i < XVECLEN (pat, 0); i++)
13479 rtx sub = XVECEXP (pat, 0, i);
13480 if (GET_CODE (sub) == USE)
13482 sub = XEXP (sub, 0);
13483 if (GET_CODE (sub) == UNSPEC
13484 && XINT (sub, 1) == UNSPEC_TOC)
13494 create_TOC_reference (rtx symbol)
13496 return gen_rtx_PLUS (Pmode,
13497 gen_rtx_REG (Pmode, TOC_REGISTER),
13498 gen_rtx_CONST (Pmode,
13499 gen_rtx_MINUS (Pmode, symbol,
13500 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13503 /* If _Unwind_* has been called from within the same module,
13504 toc register is not guaranteed to be saved to 40(1) on function
13505 entry. Save it there in that case. */
13508 rs6000_aix_emit_builtin_unwind_init (void)
13511 rtx stack_top = gen_reg_rtx (Pmode);
13512 rtx opcode_addr = gen_reg_rtx (Pmode);
13513 rtx opcode = gen_reg_rtx (SImode);
13514 rtx tocompare = gen_reg_rtx (SImode);
13515 rtx no_toc_save_needed = gen_label_rtx ();
13517 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13518 emit_move_insn (stack_top, mem);
13520 mem = gen_frame_mem (Pmode,
13521 gen_rtx_PLUS (Pmode, stack_top,
13522 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13523 emit_move_insn (opcode_addr, mem);
13524 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13525 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13526 : 0xE8410028, SImode));
13528 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13529 SImode, NULL_RTX, NULL_RTX,
13530 no_toc_save_needed);
13532 mem = gen_frame_mem (Pmode,
13533 gen_rtx_PLUS (Pmode, stack_top,
13534 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13535 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13536 emit_label (no_toc_save_needed);
13539 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13540 and the change to the stack pointer. */
13543 rs6000_emit_stack_tie (void)
13545 rtx mem = gen_frame_mem (BLKmode,
13546 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13548 emit_insn (gen_stack_tie (mem));
13551 /* Emit the correct code for allocating stack space, as insns.
13552 If COPY_R12, make sure a copy of the old frame is left in r12.
13553 The generated code may use hard register 0 as a temporary. */
13556 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13559 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13560 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13561 rtx todec = gen_int_mode (-size, Pmode);
13563 if (INTVAL (todec) != -size)
13565 warning (0, "stack frame too large");
13566 emit_insn (gen_trap ());
13570 if (current_function_limit_stack)
13572 if (REG_P (stack_limit_rtx)
13573 && REGNO (stack_limit_rtx) > 1
13574 && REGNO (stack_limit_rtx) <= 31)
13576 emit_insn (TARGET_32BIT
13577 ? gen_addsi3 (tmp_reg,
13580 : gen_adddi3 (tmp_reg,
13584 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13587 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13589 && DEFAULT_ABI == ABI_V4)
13591 rtx toload = gen_rtx_CONST (VOIDmode,
13592 gen_rtx_PLUS (Pmode,
13596 emit_insn (gen_elf_high (tmp_reg, toload));
13597 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13598 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13602 warning (0, "stack limit expression is not supported");
13605 if (copy_r12 || ! TARGET_UPDATE)
13606 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13612 /* Need a note here so that try_split doesn't get confused. */
13613 if (get_last_insn () == NULL_RTX)
13614 emit_note (NOTE_INSN_DELETED);
13615 insn = emit_move_insn (tmp_reg, todec);
13616 try_split (PATTERN (insn), insn, 0);
13620 insn = emit_insn (TARGET_32BIT
13621 ? gen_movsi_update (stack_reg, stack_reg,
13623 : gen_movdi_di_update (stack_reg, stack_reg,
13624 todec, stack_reg));
13628 insn = emit_insn (TARGET_32BIT
13629 ? gen_addsi3 (stack_reg, stack_reg, todec)
13630 : gen_adddi3 (stack_reg, stack_reg, todec));
13631 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13632 gen_rtx_REG (Pmode, 12));
13635 RTX_FRAME_RELATED_P (insn) = 1;
13637 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13638 gen_rtx_SET (VOIDmode, stack_reg,
13639 gen_rtx_PLUS (Pmode, stack_reg,
13644 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13645 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13646 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13647 deduce these equivalences by itself so it wasn't necessary to hold
13648 its hand so much. */
13651 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13652 rtx reg2, rtx rreg)
13656 /* copy_rtx will not make unique copies of registers, so we need to
13657 ensure we don't have unwanted sharing here. */
13659 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13662 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13664 real = copy_rtx (PATTERN (insn));
13666 if (reg2 != NULL_RTX)
13667 real = replace_rtx (real, reg2, rreg);
13669 real = replace_rtx (real, reg,
13670 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13671 STACK_POINTER_REGNUM),
13674 /* We expect that 'real' is either a SET or a PARALLEL containing
13675 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13676 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13678 if (GET_CODE (real) == SET)
13682 temp = simplify_rtx (SET_SRC (set));
13684 SET_SRC (set) = temp;
13685 temp = simplify_rtx (SET_DEST (set));
13687 SET_DEST (set) = temp;
13688 if (GET_CODE (SET_DEST (set)) == MEM)
13690 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13692 XEXP (SET_DEST (set), 0) = temp;
13699 gcc_assert (GET_CODE (real) == PARALLEL);
13700 for (i = 0; i < XVECLEN (real, 0); i++)
13701 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13703 rtx set = XVECEXP (real, 0, i);
13705 temp = simplify_rtx (SET_SRC (set));
13707 SET_SRC (set) = temp;
13708 temp = simplify_rtx (SET_DEST (set));
13710 SET_DEST (set) = temp;
13711 if (GET_CODE (SET_DEST (set)) == MEM)
13713 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13715 XEXP (SET_DEST (set), 0) = temp;
13717 RTX_FRAME_RELATED_P (set) = 1;
13722 real = spe_synthesize_frame_save (real);
13724 RTX_FRAME_RELATED_P (insn) = 1;
13725 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13730 /* Given an SPE frame note, return a PARALLEL of SETs with the
13731 original note, plus a synthetic register save. */
13734 spe_synthesize_frame_save (rtx real)
13736 rtx synth, offset, reg, real2;
13738 if (GET_CODE (real) != SET
13739 || GET_MODE (SET_SRC (real)) != V2SImode)
13742 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13743 frame related note. The parallel contains a set of the register
13744 being saved, and another set to a synthetic register (n+1200).
13745 This is so we can differentiate between 64-bit and 32-bit saves.
13746 Words cannot describe this nastiness. */
13748 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13749 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13750 && GET_CODE (SET_SRC (real)) == REG);
13753 (set (mem (plus (reg x) (const y)))
13756 (set (mem (plus (reg x) (const y+4)))
13760 real2 = copy_rtx (real);
13761 PUT_MODE (SET_DEST (real2), SImode);
13762 reg = SET_SRC (real2);
13763 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13764 synth = copy_rtx (real2);
13766 if (BYTES_BIG_ENDIAN)
13768 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13769 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13772 reg = SET_SRC (synth);
13774 synth = replace_rtx (synth, reg,
13775 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13777 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13778 synth = replace_rtx (synth, offset,
13779 GEN_INT (INTVAL (offset)
13780 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13782 RTX_FRAME_RELATED_P (synth) = 1;
13783 RTX_FRAME_RELATED_P (real2) = 1;
13784 if (BYTES_BIG_ENDIAN)
13785 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13787 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13792 /* Returns an insn that has a vrsave set operation with the
13793 appropriate CLOBBERs. */
13796 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13799 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13800 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13803 = gen_rtx_SET (VOIDmode,
13805 gen_rtx_UNSPEC_VOLATILE (SImode,
13806 gen_rtvec (2, reg, vrsave),
13807 UNSPECV_SET_VRSAVE));
13811 /* We need to clobber the registers in the mask so the scheduler
13812 does not move sets to VRSAVE before sets of AltiVec registers.
13814 However, if the function receives nonlocal gotos, reload will set
13815 all call saved registers live. We will end up with:
13817 (set (reg 999) (mem))
13818 (parallel [ (set (reg vrsave) (unspec blah))
13819 (clobber (reg 999))])
13821 The clobber will cause the store into reg 999 to be dead, and
13822 flow will attempt to delete an epilogue insn. In this case, we
13823 need an unspec use/set of the register. */
13825 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13826 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13828 if (!epiloguep || call_used_regs [i])
13829 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13830 gen_rtx_REG (V4SImode, i));
13833 rtx reg = gen_rtx_REG (V4SImode, i);
13836 = gen_rtx_SET (VOIDmode,
13838 gen_rtx_UNSPEC (V4SImode,
13839 gen_rtvec (1, reg), 27));
13843 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13845 for (i = 0; i < nclobs; ++i)
13846 XVECEXP (insn, 0, i) = clobs[i];
13851 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13852 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13855 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13856 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13858 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13859 rtx replacea, replaceb;
13861 int_rtx = GEN_INT (offset);
13863 /* Some cases that need register indexed addressing. */
13864 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13865 || (TARGET_E500_DOUBLE && mode == DFmode)
13867 && SPE_VECTOR_MODE (mode)
13868 && !SPE_CONST_OFFSET_OK (offset)))
13870 /* Whomever calls us must make sure r11 is available in the
13871 flow path of instructions in the prologue. */
13872 offset_rtx = gen_rtx_REG (Pmode, 11);
13873 emit_move_insn (offset_rtx, int_rtx);
13875 replacea = offset_rtx;
13876 replaceb = int_rtx;
13880 offset_rtx = int_rtx;
13881 replacea = NULL_RTX;
13882 replaceb = NULL_RTX;
13885 reg = gen_rtx_REG (mode, regno);
13886 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13887 mem = gen_frame_mem (mode, addr);
13889 insn = emit_move_insn (mem, reg);
13891 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13894 /* Emit an offset memory reference suitable for a frame store, while
13895 converting to a valid addressing mode. */
13898 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13900 rtx int_rtx, offset_rtx;
13902 int_rtx = GEN_INT (offset);
13904 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13905 || (TARGET_E500_DOUBLE && mode == DFmode))
13907 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13908 emit_move_insn (offset_rtx, int_rtx);
13911 offset_rtx = int_rtx;
13913 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13916 /* Look for user-defined global regs. We should not save and restore these,
13917 and cannot use stmw/lmw if there are any in its range. */
13920 no_global_regs_above (int first_greg)
13923 for (i = 0; i < 32 - first_greg; i++)
13924 if (global_regs[first_greg + i])
13929 #ifndef TARGET_FIX_AND_CONTINUE
13930 #define TARGET_FIX_AND_CONTINUE 0
13933 /* Emit function prologue as insns. */
13936 rs6000_emit_prologue (void)
13938 rs6000_stack_t *info = rs6000_stack_info ();
13939 enum machine_mode reg_mode = Pmode;
13940 int reg_size = TARGET_32BIT ? 4 : 8;
13941 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13942 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13943 rtx frame_reg_rtx = sp_reg_rtx;
13944 rtx cr_save_rtx = NULL_RTX;
13946 int saving_FPRs_inline;
13947 int using_store_multiple;
13948 HOST_WIDE_INT sp_offset = 0;
13950 if (TARGET_FIX_AND_CONTINUE)
13952 /* gdb on darwin arranges to forward a function from the old
13953 address by modifying the first 5 instructions of the function
13954 to branch to the overriding function. This is necessary to
13955 permit function pointers that point to the old function to
13956 actually forward to the new function. */
13957 emit_insn (gen_nop ());
13958 emit_insn (gen_nop ());
13959 emit_insn (gen_nop ());
13960 emit_insn (gen_nop ());
13961 emit_insn (gen_nop ());
13964 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13966 reg_mode = V2SImode;
13970 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13971 && (!TARGET_SPE_ABI
13972 || info->spe_64bit_regs_used == 0)
13973 && info->first_gp_reg_save < 31
13974 && no_global_regs_above (info->first_gp_reg_save));
13975 saving_FPRs_inline = (info->first_fp_reg_save == 64
13976 || FP_SAVE_INLINE (info->first_fp_reg_save)
13977 || current_function_calls_eh_return
13978 || cfun->machine->ra_need_lr);
13980 /* For V.4, update stack before we do any saving and set back pointer. */
13982 && (DEFAULT_ABI == ABI_V4
13983 || current_function_calls_eh_return))
13985 if (info->total_size < 32767)
13986 sp_offset = info->total_size;
13988 frame_reg_rtx = frame_ptr_rtx;
13989 rs6000_emit_allocate_stack (info->total_size,
13990 (frame_reg_rtx != sp_reg_rtx
13991 && (info->cr_save_p
13993 || info->first_fp_reg_save < 64
13994 || info->first_gp_reg_save < 32
13996 if (frame_reg_rtx != sp_reg_rtx)
13997 rs6000_emit_stack_tie ();
14000 /* Handle world saves specially here. */
14001 if (WORLD_SAVE_P (info))
14007 /* save_world expects lr in r0. */
14008 if (info->lr_save_p)
14010 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14011 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14012 RTX_FRAME_RELATED_P (insn) = 1;
14015 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14016 assumptions about the offsets of various bits of the stack
14018 gcc_assert (info->gp_save_offset == -220
14019 && info->fp_save_offset == -144
14020 && info->lr_save_offset == 8
14021 && info->cr_save_offset == 4
14024 && (!current_function_calls_eh_return
14025 || info->ehrd_offset == -432)
14026 && info->vrsave_save_offset == -224
14027 && info->altivec_save_offset == (-224 -16 -192));
14029 treg = gen_rtx_REG (SImode, 11);
14030 emit_move_insn (treg, GEN_INT (-info->total_size));
14032 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14033 in R11. It also clobbers R12, so beware! */
14035 /* Preserve CR2 for save_world prologues */
14037 sz += 32 - info->first_gp_reg_save;
14038 sz += 64 - info->first_fp_reg_save;
14039 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14040 p = rtvec_alloc (sz);
14042 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14043 gen_rtx_REG (Pmode,
14044 LINK_REGISTER_REGNUM));
14045 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14046 gen_rtx_SYMBOL_REF (Pmode,
14048 /* We do floats first so that the instruction pattern matches
14050 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14052 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14053 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14054 GEN_INT (info->fp_save_offset
14055 + sp_offset + 8 * i));
14056 rtx mem = gen_frame_mem (DFmode, addr);
14058 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14060 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14062 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14063 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14064 GEN_INT (info->altivec_save_offset
14065 + sp_offset + 16 * i));
14066 rtx mem = gen_frame_mem (V4SImode, addr);
14068 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14070 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14072 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14073 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14074 GEN_INT (info->gp_save_offset
14075 + sp_offset + reg_size * i));
14076 rtx mem = gen_frame_mem (reg_mode, addr);
14078 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14082 /* CR register traditionally saved as CR2. */
14083 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14084 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14085 GEN_INT (info->cr_save_offset
14087 rtx mem = gen_frame_mem (reg_mode, addr);
14089 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14091 /* Prevent any attempt to delete the setting of r0 and treg! */
14092 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14093 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14094 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14096 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14097 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14098 NULL_RTX, NULL_RTX);
14100 if (current_function_calls_eh_return)
14105 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14106 if (regno == INVALID_REGNUM)
14108 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14109 info->ehrd_offset + sp_offset
14110 + reg_size * (int) i,
14116 /* Save AltiVec registers if needed. */
14117 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14121 /* There should be a non inline version of this, for when we
14122 are saving lots of vector registers. */
14123 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14124 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14126 rtx areg, savereg, mem;
14129 offset = info->altivec_save_offset + sp_offset
14130 + 16 * (i - info->first_altivec_reg_save);
14132 savereg = gen_rtx_REG (V4SImode, i);
14134 areg = gen_rtx_REG (Pmode, 0);
14135 emit_move_insn (areg, GEN_INT (offset));
14137 /* AltiVec addressing mode is [reg+reg]. */
14138 mem = gen_frame_mem (V4SImode,
14139 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14141 insn = emit_move_insn (mem, savereg);
14143 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14144 areg, GEN_INT (offset));
14148 /* VRSAVE is a bit vector representing which AltiVec registers
14149 are used. The OS uses this to determine which vector
14150 registers to save on a context switch. We need to save
14151 VRSAVE on the stack frame, add whatever AltiVec registers we
14152 used in this function, and do the corresponding magic in the
14155 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14156 && info->vrsave_mask != 0)
14158 rtx reg, mem, vrsave;
14161 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14162 as frame_reg_rtx and r11 as the static chain pointer for
14163 nested functions. */
14164 reg = gen_rtx_REG (SImode, 0);
14165 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14167 emit_insn (gen_get_vrsave_internal (reg));
14169 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14171 if (!WORLD_SAVE_P (info))
14174 offset = info->vrsave_save_offset + sp_offset;
14175 mem = gen_frame_mem (SImode,
14176 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14177 GEN_INT (offset)));
14178 insn = emit_move_insn (mem, reg);
14181 /* Include the registers in the mask. */
14182 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14184 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14187 /* If we use the link register, get it into r0. */
14188 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14190 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14191 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14192 RTX_FRAME_RELATED_P (insn) = 1;
14195 /* If we need to save CR, put it into r12. */
14196 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14200 cr_save_rtx = gen_rtx_REG (SImode, 12);
14201 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14202 RTX_FRAME_RELATED_P (insn) = 1;
14203 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14204 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14205 But that's OK. All we have to do is specify that _one_ condition
14206 code register is saved in this stack slot. The thrower's epilogue
14207 will then restore all the call-saved registers.
14208 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14209 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14210 gen_rtx_REG (SImode, CR2_REGNO));
14211 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14216 /* Do any required saving of fpr's. If only one or two to save, do
14217 it ourselves. Otherwise, call function. */
14218 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14221 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14222 if ((regs_ever_live[info->first_fp_reg_save+i]
14223 && ! call_used_regs[info->first_fp_reg_save+i]))
14224 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14225 info->first_fp_reg_save + i,
14226 info->fp_save_offset + sp_offset + 8 * i,
14229 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14233 const char *alloc_rname;
14235 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14237 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14238 gen_rtx_REG (Pmode,
14239 LINK_REGISTER_REGNUM));
14240 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14241 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14242 alloc_rname = ggc_strdup (rname);
14243 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14244 gen_rtx_SYMBOL_REF (Pmode,
14246 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14248 rtx addr, reg, mem;
14249 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14250 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14251 GEN_INT (info->fp_save_offset
14252 + sp_offset + 8*i));
14253 mem = gen_frame_mem (DFmode, addr);
14255 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14257 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14258 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14259 NULL_RTX, NULL_RTX);
14262 /* Save GPRs. This is done as a PARALLEL if we are using
14263 the store-multiple instructions. */
14264 if (!WORLD_SAVE_P (info) && using_store_multiple)
14268 p = rtvec_alloc (32 - info->first_gp_reg_save);
14269 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14271 rtx addr, reg, mem;
14272 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14273 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14274 GEN_INT (info->gp_save_offset
14277 mem = gen_frame_mem (reg_mode, addr);
14279 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14281 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14282 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14283 NULL_RTX, NULL_RTX);
14285 else if (!WORLD_SAVE_P (info))
14288 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14289 if ((regs_ever_live[info->first_gp_reg_save + i]
14290 && (!call_used_regs[info->first_gp_reg_save + i]
14291 || (i + info->first_gp_reg_save
14292 == RS6000_PIC_OFFSET_TABLE_REGNUM
14293 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14294 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14295 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14296 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14298 rtx addr, reg, mem;
14299 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14301 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14303 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14306 if (!SPE_CONST_OFFSET_OK (offset))
14308 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14309 emit_move_insn (b, GEN_INT (offset));
14312 b = GEN_INT (offset);
14314 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14315 mem = gen_frame_mem (V2SImode, addr);
14316 insn = emit_move_insn (mem, reg);
14318 if (GET_CODE (b) == CONST_INT)
14319 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14320 NULL_RTX, NULL_RTX);
14322 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14323 b, GEN_INT (offset));
14327 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14328 GEN_INT (info->gp_save_offset
14331 mem = gen_frame_mem (reg_mode, addr);
14333 insn = emit_move_insn (mem, reg);
14334 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14335 NULL_RTX, NULL_RTX);
14340 /* ??? There's no need to emit actual instructions here, but it's the
14341 easiest way to get the frame unwind information emitted. */
14342 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14344 unsigned int i, regno;
14346 /* In AIX ABI we need to pretend we save r2 here. */
14349 rtx addr, reg, mem;
14351 reg = gen_rtx_REG (reg_mode, 2);
14352 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14353 GEN_INT (sp_offset + 5 * reg_size));
14354 mem = gen_frame_mem (reg_mode, addr);
14356 insn = emit_move_insn (mem, reg);
14357 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14358 NULL_RTX, NULL_RTX);
14359 PATTERN (insn) = gen_blockage ();
14364 regno = EH_RETURN_DATA_REGNO (i);
14365 if (regno == INVALID_REGNUM)
14368 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14369 info->ehrd_offset + sp_offset
14370 + reg_size * (int) i,
14375 /* Save lr if we used it. */
14376 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14378 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14379 GEN_INT (info->lr_save_offset + sp_offset));
14380 rtx reg = gen_rtx_REG (Pmode, 0);
14381 rtx mem = gen_rtx_MEM (Pmode, addr);
14382 /* This should not be of frame_alias_set, because of
14383 __builtin_return_address. */
14385 insn = emit_move_insn (mem, reg);
14386 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14387 NULL_RTX, NULL_RTX);
14390 /* Save CR if we use any that must be preserved. */
14391 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14393 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14394 GEN_INT (info->cr_save_offset + sp_offset));
14395 rtx mem = gen_frame_mem (SImode, addr);
14396 /* See the large comment above about why CR2_REGNO is used. */
14397 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14399 /* If r12 was used to hold the original sp, copy cr into r0 now
14401 if (REGNO (frame_reg_rtx) == 12)
14405 cr_save_rtx = gen_rtx_REG (SImode, 0);
14406 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14407 RTX_FRAME_RELATED_P (insn) = 1;
14408 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14409 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14414 insn = emit_move_insn (mem, cr_save_rtx);
14416 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14417 NULL_RTX, NULL_RTX);
14420 /* Update stack and set back pointer unless this is V.4,
14421 for which it was done previously. */
14422 if (!WORLD_SAVE_P (info) && info->push_p
14423 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14424 rs6000_emit_allocate_stack (info->total_size, FALSE);
14426 /* Set frame pointer, if needed. */
14427 if (frame_pointer_needed)
14429 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14431 RTX_FRAME_RELATED_P (insn) = 1;
14434 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14435 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14436 || (DEFAULT_ABI == ABI_V4
14437 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14438 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14440 /* If emit_load_toc_table will use the link register, we need to save
14441 it. We use R12 for this purpose because emit_load_toc_table
14442 can use register 0. This allows us to use a plain 'blr' to return
14443 from the procedure more often. */
14444 int save_LR_around_toc_setup = (TARGET_ELF
14445 && DEFAULT_ABI != ABI_AIX
14447 && ! info->lr_save_p
14448 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14449 if (save_LR_around_toc_setup)
14451 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14453 insn = emit_move_insn (frame_ptr_rtx, lr);
14454 rs6000_maybe_dead (insn);
14455 RTX_FRAME_RELATED_P (insn) = 1;
14457 rs6000_emit_load_toc_table (TRUE);
14459 insn = emit_move_insn (lr, frame_ptr_rtx);
14460 rs6000_maybe_dead (insn);
14461 RTX_FRAME_RELATED_P (insn) = 1;
14464 rs6000_emit_load_toc_table (TRUE);
14468 if (DEFAULT_ABI == ABI_DARWIN
14469 && flag_pic && current_function_uses_pic_offset_table)
14471 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14472 rtx src = machopic_function_base_sym ();
14474 /* Save and restore LR locally around this call (in R0). */
14475 if (!info->lr_save_p)
14476 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14478 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14480 insn = emit_move_insn (gen_rtx_REG (Pmode,
14481 RS6000_PIC_OFFSET_TABLE_REGNUM),
14483 rs6000_maybe_dead (insn);
14485 if (!info->lr_save_p)
14486 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14491 /* Write function prologue. */
14494 rs6000_output_function_prologue (FILE *file,
14495 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14497 rs6000_stack_t *info = rs6000_stack_info ();
14499 if (TARGET_DEBUG_STACK)
14500 debug_stack_info (info);
14502 /* Write .extern for any function we will call to save and restore
14504 if (info->first_fp_reg_save < 64
14505 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14506 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14507 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14508 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14509 RESTORE_FP_SUFFIX);
14511 /* Write .extern for AIX common mode routines, if needed. */
14512 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14514 fputs ("\t.extern __mulh\n", file);
14515 fputs ("\t.extern __mull\n", file);
14516 fputs ("\t.extern __divss\n", file);
14517 fputs ("\t.extern __divus\n", file);
14518 fputs ("\t.extern __quoss\n", file);
14519 fputs ("\t.extern __quous\n", file);
14520 common_mode_defined = 1;
14523 if (! HAVE_prologue)
14527 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14528 the "toplevel" insn chain. */
14529 emit_note (NOTE_INSN_DELETED);
14530 rs6000_emit_prologue ();
14531 emit_note (NOTE_INSN_DELETED);
14533 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14537 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14539 INSN_ADDRESSES_NEW (insn, addr);
14544 if (TARGET_DEBUG_STACK)
14545 debug_rtx_list (get_insns (), 100);
14546 final (get_insns (), file, FALSE);
14550 rs6000_pic_labelno++;
14553 /* Emit function epilogue as insns.
14555 At present, dwarf2out_frame_debug_expr doesn't understand
14556 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14557 anywhere in the epilogue. Most of the insns below would in any case
14558 need special notes to explain where r11 is in relation to the stack. */
14561 rs6000_emit_epilogue (int sibcall)
14563 rs6000_stack_t *info;
14564 int restoring_FPRs_inline;
14565 int using_load_multiple;
14566 int using_mfcr_multiple;
14567 int use_backchain_to_restore_sp;
14569 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14570 rtx frame_reg_rtx = sp_reg_rtx;
14571 enum machine_mode reg_mode = Pmode;
14572 int reg_size = TARGET_32BIT ? 4 : 8;
14575 info = rs6000_stack_info ();
14577 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14579 reg_mode = V2SImode;
14583 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14584 && (!TARGET_SPE_ABI
14585 || info->spe_64bit_regs_used == 0)
14586 && info->first_gp_reg_save < 31
14587 && no_global_regs_above (info->first_gp_reg_save));
14588 restoring_FPRs_inline = (sibcall
14589 || current_function_calls_eh_return
14590 || info->first_fp_reg_save == 64
14591 || FP_SAVE_INLINE (info->first_fp_reg_save));
14592 use_backchain_to_restore_sp = (frame_pointer_needed
14593 || current_function_calls_alloca
14594 || info->total_size > 32767);
14595 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14596 || rs6000_cpu == PROCESSOR_PPC603
14597 || rs6000_cpu == PROCESSOR_PPC750
14600 if (WORLD_SAVE_P (info))
14604 const char *alloc_rname;
14607 /* eh_rest_world_r10 will return to the location saved in the LR
14608 stack slot (which is not likely to be our caller.)
14609 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14610 rest_world is similar, except any R10 parameter is ignored.
14611 The exception-handling stuff that was here in 2.95 is no
14612 longer necessary. */
14616 + 32 - info->first_gp_reg_save
14617 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14618 + 63 + 1 - info->first_fp_reg_save);
14620 strcpy (rname, ((current_function_calls_eh_return) ?
14621 "*eh_rest_world_r10" : "*rest_world"));
14622 alloc_rname = ggc_strdup (rname);
14625 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14626 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14627 gen_rtx_REG (Pmode,
14628 LINK_REGISTER_REGNUM));
14630 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14631 /* The instruction pattern requires a clobber here;
14632 it is shared with the restVEC helper. */
14634 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14637 /* CR register traditionally saved as CR2. */
14638 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14639 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14640 GEN_INT (info->cr_save_offset));
14641 rtx mem = gen_frame_mem (reg_mode, addr);
14643 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14646 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14648 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14649 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14650 GEN_INT (info->gp_save_offset
14652 rtx mem = gen_frame_mem (reg_mode, addr);
14654 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14656 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14658 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14659 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14660 GEN_INT (info->altivec_save_offset
14662 rtx mem = gen_frame_mem (V4SImode, addr);
14664 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14666 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14668 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14669 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14670 GEN_INT (info->fp_save_offset
14672 rtx mem = gen_frame_mem (DFmode, addr);
14674 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14677 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14679 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14681 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14683 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14685 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14686 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14691 /* If we have a frame pointer, a call to alloca, or a large stack
14692 frame, restore the old stack pointer using the backchain. Otherwise,
14693 we know what size to update it with. */
14694 if (use_backchain_to_restore_sp)
14696 /* Under V.4, don't reset the stack pointer until after we're done
14697 loading the saved registers. */
14698 if (DEFAULT_ABI == ABI_V4)
14699 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14701 emit_move_insn (frame_reg_rtx,
14702 gen_rtx_MEM (Pmode, sp_reg_rtx));
14704 else if (info->push_p)
14706 if (DEFAULT_ABI == ABI_V4
14707 || current_function_calls_eh_return)
14708 sp_offset = info->total_size;
14711 emit_insn (TARGET_32BIT
14712 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14713 GEN_INT (info->total_size))
14714 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14715 GEN_INT (info->total_size)));
14719 /* Restore AltiVec registers if needed. */
14720 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14724 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14725 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14727 rtx addr, areg, mem;
14729 areg = gen_rtx_REG (Pmode, 0);
14731 (areg, GEN_INT (info->altivec_save_offset
14733 + 16 * (i - info->first_altivec_reg_save)));
14735 /* AltiVec addressing mode is [reg+reg]. */
14736 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14737 mem = gen_frame_mem (V4SImode, addr);
14739 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14743 /* Restore VRSAVE if needed. */
14744 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14745 && info->vrsave_mask != 0)
14747 rtx addr, mem, reg;
14749 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14750 GEN_INT (info->vrsave_save_offset + sp_offset));
14751 mem = gen_frame_mem (SImode, addr);
14752 reg = gen_rtx_REG (SImode, 12);
14753 emit_move_insn (reg, mem);
14755 emit_insn (generate_set_vrsave (reg, info, 1));
14758 /* Get the old lr if we saved it. */
14759 if (info->lr_save_p)
14761 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14762 info->lr_save_offset + sp_offset);
14764 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14767 /* Get the old cr if we saved it. */
14768 if (info->cr_save_p)
14770 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14771 GEN_INT (info->cr_save_offset + sp_offset));
14772 rtx mem = gen_frame_mem (SImode, addr);
14774 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14777 /* Set LR here to try to overlap restores below. */
14778 if (info->lr_save_p)
14779 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14780 gen_rtx_REG (Pmode, 0));
14782 /* Load exception handler data registers, if needed. */
14783 if (current_function_calls_eh_return)
14785 unsigned int i, regno;
14789 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14790 GEN_INT (sp_offset + 5 * reg_size));
14791 rtx mem = gen_frame_mem (reg_mode, addr);
14793 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14800 regno = EH_RETURN_DATA_REGNO (i);
14801 if (regno == INVALID_REGNUM)
14804 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14805 info->ehrd_offset + sp_offset
14806 + reg_size * (int) i);
14808 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14812 /* Restore GPRs. This is done as a PARALLEL if we are using
14813 the load-multiple instructions. */
14814 if (using_load_multiple)
14817 p = rtvec_alloc (32 - info->first_gp_reg_save);
14818 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14820 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14821 GEN_INT (info->gp_save_offset
14824 rtx mem = gen_frame_mem (reg_mode, addr);
14827 gen_rtx_SET (VOIDmode,
14828 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14831 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14834 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14835 if ((regs_ever_live[info->first_gp_reg_save + i]
14836 && (!call_used_regs[info->first_gp_reg_save + i]
14837 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14838 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14839 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14840 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14841 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14843 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14844 GEN_INT (info->gp_save_offset
14847 rtx mem = gen_frame_mem (reg_mode, addr);
14849 /* Restore 64-bit quantities for SPE. */
14850 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14852 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14855 if (!SPE_CONST_OFFSET_OK (offset))
14857 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14858 emit_move_insn (b, GEN_INT (offset));
14861 b = GEN_INT (offset);
14863 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14864 mem = gen_frame_mem (V2SImode, addr);
14867 emit_move_insn (gen_rtx_REG (reg_mode,
14868 info->first_gp_reg_save + i), mem);
14871 /* Restore fpr's if we need to do it without calling a function. */
14872 if (restoring_FPRs_inline)
14873 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14874 if ((regs_ever_live[info->first_fp_reg_save+i]
14875 && ! call_used_regs[info->first_fp_reg_save+i]))
14878 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14879 GEN_INT (info->fp_save_offset
14882 mem = gen_frame_mem (DFmode, addr);
14884 emit_move_insn (gen_rtx_REG (DFmode,
14885 info->first_fp_reg_save + i),
14889 /* If we saved cr, restore it here. Just those that were used. */
14890 if (info->cr_save_p)
14892 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14895 if (using_mfcr_multiple)
14897 for (i = 0; i < 8; i++)
14898 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14900 gcc_assert (count);
14903 if (using_mfcr_multiple && count > 1)
14908 p = rtvec_alloc (count);
14911 for (i = 0; i < 8; i++)
14912 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14914 rtvec r = rtvec_alloc (2);
14915 RTVEC_ELT (r, 0) = r12_rtx;
14916 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14917 RTVEC_ELT (p, ndx) =
14918 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14919 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14922 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14923 gcc_assert (ndx == count);
14926 for (i = 0; i < 8; i++)
14927 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14929 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14935 /* If this is V.4, unwind the stack pointer after all of the loads
14937 if (frame_reg_rtx != sp_reg_rtx)
14939 /* This blockage is needed so that sched doesn't decide to move
14940 the sp change before the register restores. */
14941 rs6000_emit_stack_tie ();
14942 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14944 else if (sp_offset != 0)
14945 emit_insn (TARGET_32BIT
14946 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14947 GEN_INT (sp_offset))
14948 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14949 GEN_INT (sp_offset)));
14951 if (current_function_calls_eh_return)
14953 rtx sa = EH_RETURN_STACKADJ_RTX;
14954 emit_insn (TARGET_32BIT
14955 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14956 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14962 if (! restoring_FPRs_inline)
14963 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14965 p = rtvec_alloc (2);
14967 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14968 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14969 gen_rtx_REG (Pmode,
14970 LINK_REGISTER_REGNUM));
14972 /* If we have to restore more than two FP registers, branch to the
14973 restore function. It will return to our caller. */
14974 if (! restoring_FPRs_inline)
14978 const char *alloc_rname;
14980 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14981 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14982 alloc_rname = ggc_strdup (rname);
14983 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14984 gen_rtx_SYMBOL_REF (Pmode,
14987 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14990 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14991 GEN_INT (info->fp_save_offset + 8*i));
14992 mem = gen_frame_mem (DFmode, addr);
14994 RTVEC_ELT (p, i+3) =
14995 gen_rtx_SET (VOIDmode,
14996 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15001 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15005 /* Write function epilogue. */
15008 rs6000_output_function_epilogue (FILE *file,
15009 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15011 rs6000_stack_t *info = rs6000_stack_info ();
15013 if (! HAVE_epilogue)
15015 rtx insn = get_last_insn ();
15016 /* If the last insn was a BARRIER, we don't have to write anything except
15017 the trace table. */
15018 if (GET_CODE (insn) == NOTE)
15019 insn = prev_nonnote_insn (insn);
15020 if (insn == 0 || GET_CODE (insn) != BARRIER)
15022 /* This is slightly ugly, but at least we don't have two
15023 copies of the epilogue-emitting code. */
15026 /* A NOTE_INSN_DELETED is supposed to be at the start
15027 and end of the "toplevel" insn chain. */
15028 emit_note (NOTE_INSN_DELETED);
15029 rs6000_emit_epilogue (FALSE);
15030 emit_note (NOTE_INSN_DELETED);
15032 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15036 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15038 INSN_ADDRESSES_NEW (insn, addr);
15043 if (TARGET_DEBUG_STACK)
15044 debug_rtx_list (get_insns (), 100);
15045 final (get_insns (), file, FALSE);
15051 macho_branch_islands ();
15052 /* Mach-O doesn't support labels at the end of objects, so if
15053 it looks like we might want one, insert a NOP. */
15055 rtx insn = get_last_insn ();
15058 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15059 insn = PREV_INSN (insn);
15063 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15064 fputs ("\tnop\n", file);
15068 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15071 We don't output a traceback table if -finhibit-size-directive was
15072 used. The documentation for -finhibit-size-directive reads
15073 ``don't output a @code{.size} assembler directive, or anything
15074 else that would cause trouble if the function is split in the
15075 middle, and the two halves are placed at locations far apart in
15076 memory.'' The traceback table has this property, since it
15077 includes the offset from the start of the function to the
15078 traceback table itself.
15080 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15081 different traceback table. */
15082 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15083 && rs6000_traceback != traceback_none)
15085 const char *fname = NULL;
15086 const char *language_string = lang_hooks.name;
15087 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15089 int optional_tbtab;
15091 if (rs6000_traceback == traceback_full)
15092 optional_tbtab = 1;
15093 else if (rs6000_traceback == traceback_part)
15094 optional_tbtab = 0;
15096 optional_tbtab = !optimize_size && !TARGET_ELF;
15098 if (optional_tbtab)
15100 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15101 while (*fname == '.') /* V.4 encodes . in the name */
15104 /* Need label immediately before tbtab, so we can compute
15105 its offset from the function start. */
15106 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15107 ASM_OUTPUT_LABEL (file, fname);
15110 /* The .tbtab pseudo-op can only be used for the first eight
15111 expressions, since it can't handle the possibly variable
15112 length fields that follow. However, if you omit the optional
15113 fields, the assembler outputs zeros for all optional fields
15114 anyways, giving each variable length field is minimum length
15115 (as defined in sys/debug.h). Thus we can not use the .tbtab
15116 pseudo-op at all. */
15118 /* An all-zero word flags the start of the tbtab, for debuggers
15119 that have to find it by searching forward from the entry
15120 point or from the current pc. */
15121 fputs ("\t.long 0\n", file);
15123 /* Tbtab format type. Use format type 0. */
15124 fputs ("\t.byte 0,", file);
15126 /* Language type. Unfortunately, there does not seem to be any
15127 official way to discover the language being compiled, so we
15128 use language_string.
15129 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15130 Java is 13. Objective-C is 14. */
15131 if (! strcmp (language_string, "GNU C"))
15133 else if (! strcmp (language_string, "GNU F77")
15134 || ! strcmp (language_string, "GNU F95"))
15136 else if (! strcmp (language_string, "GNU Pascal"))
15138 else if (! strcmp (language_string, "GNU Ada"))
15140 else if (! strcmp (language_string, "GNU C++"))
15142 else if (! strcmp (language_string, "GNU Java"))
15144 else if (! strcmp (language_string, "GNU Objective-C"))
15147 gcc_unreachable ();
15148 fprintf (file, "%d,", i);
15150 /* 8 single bit fields: global linkage (not set for C extern linkage,
15151 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15152 from start of procedure stored in tbtab, internal function, function
15153 has controlled storage, function has no toc, function uses fp,
15154 function logs/aborts fp operations. */
15155 /* Assume that fp operations are used if any fp reg must be saved. */
15156 fprintf (file, "%d,",
15157 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15159 /* 6 bitfields: function is interrupt handler, name present in
15160 proc table, function calls alloca, on condition directives
15161 (controls stack walks, 3 bits), saves condition reg, saves
15163 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15164 set up as a frame pointer, even when there is no alloca call. */
15165 fprintf (file, "%d,",
15166 ((optional_tbtab << 6)
15167 | ((optional_tbtab & frame_pointer_needed) << 5)
15168 | (info->cr_save_p << 1)
15169 | (info->lr_save_p)));
15171 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15173 fprintf (file, "%d,",
15174 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15176 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15177 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15179 if (optional_tbtab)
15181 /* Compute the parameter info from the function decl argument
15184 int next_parm_info_bit = 31;
15186 for (decl = DECL_ARGUMENTS (current_function_decl);
15187 decl; decl = TREE_CHAIN (decl))
15189 rtx parameter = DECL_INCOMING_RTL (decl);
15190 enum machine_mode mode = GET_MODE (parameter);
15192 if (GET_CODE (parameter) == REG)
15194 if (SCALAR_FLOAT_MODE_P (mode))
15212 gcc_unreachable ();
15215 /* If only one bit will fit, don't or in this entry. */
15216 if (next_parm_info_bit > 0)
15217 parm_info |= (bits << (next_parm_info_bit - 1));
15218 next_parm_info_bit -= 2;
15222 fixed_parms += ((GET_MODE_SIZE (mode)
15223 + (UNITS_PER_WORD - 1))
15225 next_parm_info_bit -= 1;
15231 /* Number of fixed point parameters. */
15232 /* This is actually the number of words of fixed point parameters; thus
15233 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15234 fprintf (file, "%d,", fixed_parms);
15236 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15238 /* This is actually the number of fp registers that hold parameters;
15239 and thus the maximum value is 13. */
15240 /* Set parameters on stack bit if parameters are not in their original
15241 registers, regardless of whether they are on the stack? Xlc
15242 seems to set the bit when not optimizing. */
15243 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15245 if (! optional_tbtab)
15248 /* Optional fields follow. Some are variable length. */
15250 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15251 11 double float. */
15252 /* There is an entry for each parameter in a register, in the order that
15253 they occur in the parameter list. Any intervening arguments on the
15254 stack are ignored. If the list overflows a long (max possible length
15255 34 bits) then completely leave off all elements that don't fit. */
15256 /* Only emit this long if there was at least one parameter. */
15257 if (fixed_parms || float_parms)
15258 fprintf (file, "\t.long %d\n", parm_info);
15260 /* Offset from start of code to tb table. */
15261 fputs ("\t.long ", file);
15262 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15264 RS6000_OUTPUT_BASENAME (file, fname);
15266 assemble_name (file, fname);
15268 rs6000_output_function_entry (file, fname);
15271 /* Interrupt handler mask. */
15272 /* Omit this long, since we never set the interrupt handler bit
15275 /* Number of CTL (controlled storage) anchors. */
15276 /* Omit this long, since the has_ctl bit is never set above. */
15278 /* Displacement into stack of each CTL anchor. */
15279 /* Omit this list of longs, because there are no CTL anchors. */
15281 /* Length of function name. */
15284 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15286 /* Function name. */
15287 assemble_string (fname, strlen (fname));
15289 /* Register for alloca automatic storage; this is always reg 31.
15290 Only emit this if the alloca bit was set above. */
15291 if (frame_pointer_needed)
15292 fputs ("\t.byte 31\n", file);
15294 fputs ("\t.align 2\n", file);
15298 /* A C compound statement that outputs the assembler code for a thunk
15299 function, used to implement C++ virtual function calls with
15300 multiple inheritance. The thunk acts as a wrapper around a virtual
15301 function, adjusting the implicit object parameter before handing
15302 control off to the real function.
15304 First, emit code to add the integer DELTA to the location that
15305 contains the incoming first argument. Assume that this argument
15306 contains a pointer, and is the one used to pass the `this' pointer
15307 in C++. This is the incoming argument *before* the function
15308 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15309 values of all other incoming arguments.
15311 After the addition, emit code to jump to FUNCTION, which is a
15312 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15313 not touch the return address. Hence returning from FUNCTION will
15314 return to whoever called the current `thunk'.
15316 The effect must be as if FUNCTION had been called directly with the
15317 adjusted first argument. This macro is responsible for emitting
15318 all of the code for a thunk function; output_function_prologue()
15319 and output_function_epilogue() are not invoked.
15321 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15322 been extracted from it.) It might possibly be useful on some
15323 targets, but probably not.
15325 If you do not define this macro, the target-independent code in the
15326 C++ frontend will generate a less efficient heavyweight thunk that
15327 calls FUNCTION instead of jumping to it. The generic approach does
15328 not support varargs. */
15331 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15332 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15335 rtx this, insn, funexp;
15337 reload_completed = 1;
15338 epilogue_completed = 1;
15339 no_new_pseudos = 1;
15340 reset_block_changes ();
15342 /* Mark the end of the (empty) prologue. */
15343 emit_note (NOTE_INSN_PROLOGUE_END);
15345 /* Find the "this" pointer. If the function returns a structure,
15346 the structure return pointer is in r3. */
15347 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15348 this = gen_rtx_REG (Pmode, 4);
15350 this = gen_rtx_REG (Pmode, 3);
15352 /* Apply the constant offset, if required. */
15355 rtx delta_rtx = GEN_INT (delta);
15356 emit_insn (TARGET_32BIT
15357 ? gen_addsi3 (this, this, delta_rtx)
15358 : gen_adddi3 (this, this, delta_rtx));
15361 /* Apply the offset from the vtable, if required. */
15364 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15365 rtx tmp = gen_rtx_REG (Pmode, 12);
15367 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15368 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15370 emit_insn (TARGET_32BIT
15371 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15372 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15373 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15377 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15379 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15381 emit_insn (TARGET_32BIT
15382 ? gen_addsi3 (this, this, tmp)
15383 : gen_adddi3 (this, this, tmp));
15386 /* Generate a tail call to the target function. */
15387 if (!TREE_USED (function))
15389 assemble_external (function);
15390 TREE_USED (function) = 1;
15392 funexp = XEXP (DECL_RTL (function), 0);
15393 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15396 if (MACHOPIC_INDIRECT)
15397 funexp = machopic_indirect_call_target (funexp);
15400 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15401 generate sibcall RTL explicitly. */
15402 insn = emit_call_insn (
15403 gen_rtx_PARALLEL (VOIDmode,
15405 gen_rtx_CALL (VOIDmode,
15406 funexp, const0_rtx),
15407 gen_rtx_USE (VOIDmode, const0_rtx),
15408 gen_rtx_USE (VOIDmode,
15409 gen_rtx_REG (SImode,
15410 LINK_REGISTER_REGNUM)),
15411 gen_rtx_RETURN (VOIDmode))));
15412 SIBLING_CALL_P (insn) = 1;
15415 /* Run just enough of rest_of_compilation to get the insns emitted.
15416 There's not really enough bulk here to make other passes such as
15417 instruction scheduling worth while. Note that use_thunk calls
15418 assemble_start_function and assemble_end_function. */
15419 insn = get_insns ();
15420 insn_locators_initialize ();
15421 shorten_branches (insn);
15422 final_start_function (insn, file, 1);
15423 final (insn, file, 1);
15424 final_end_function ();
15426 reload_completed = 0;
15427 epilogue_completed = 0;
15428 no_new_pseudos = 0;
15431 /* A quick summary of the various types of 'constant-pool tables'
15434 Target Flags Name One table per
15435 AIX (none) AIX TOC object file
15436 AIX -mfull-toc AIX TOC object file
15437 AIX -mminimal-toc AIX minimal TOC translation unit
15438 SVR4/EABI (none) SVR4 SDATA object file
15439 SVR4/EABI -fpic SVR4 pic object file
15440 SVR4/EABI -fPIC SVR4 PIC translation unit
15441 SVR4/EABI -mrelocatable EABI TOC function
15442 SVR4/EABI -maix AIX TOC object file
15443 SVR4/EABI -maix -mminimal-toc
15444 AIX minimal TOC translation unit
15446 Name Reg. Set by entries contains:
15447 made by addrs? fp? sum?
15449 AIX TOC 2 crt0 as Y option option
15450 AIX minimal TOC 30 prolog gcc Y Y option
15451 SVR4 SDATA 13 crt0 gcc N Y N
15452 SVR4 pic 30 prolog ld Y not yet N
15453 SVR4 PIC 30 prolog gcc Y option option
15454 EABI TOC 30 prolog gcc Y option option
15458 /* Hash functions for the hash table. */
15461 rs6000_hash_constant (rtx k)
15463 enum rtx_code code = GET_CODE (k);
15464 enum machine_mode mode = GET_MODE (k);
15465 unsigned result = (code << 3) ^ mode;
15466 const char *format;
15469 format = GET_RTX_FORMAT (code);
15470 flen = strlen (format);
15476 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15479 if (mode != VOIDmode)
15480 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15492 for (; fidx < flen; fidx++)
15493 switch (format[fidx])
15498 const char *str = XSTR (k, fidx);
15499 len = strlen (str);
15500 result = result * 613 + len;
15501 for (i = 0; i < len; i++)
15502 result = result * 613 + (unsigned) str[i];
15507 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15511 result = result * 613 + (unsigned) XINT (k, fidx);
15514 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15515 result = result * 613 + (unsigned) XWINT (k, fidx);
15519 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15520 result = result * 613 + (unsigned) (XWINT (k, fidx)
15527 gcc_unreachable ();
15534 toc_hash_function (const void *hash_entry)
15536 const struct toc_hash_struct *thc =
15537 (const struct toc_hash_struct *) hash_entry;
15538 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15541 /* Compare H1 and H2 for equivalence. */
15544 toc_hash_eq (const void *h1, const void *h2)
15546 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15547 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15549 if (((const struct toc_hash_struct *) h1)->key_mode
15550 != ((const struct toc_hash_struct *) h2)->key_mode)
15553 return rtx_equal_p (r1, r2);
15556 /* These are the names given by the C++ front-end to vtables, and
15557 vtable-like objects. Ideally, this logic should not be here;
15558 instead, there should be some programmatic way of inquiring as
15559 to whether or not an object is a vtable. */
15561 #define VTABLE_NAME_P(NAME) \
15562 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15563 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15564 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15565 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15566 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15569 rs6000_output_symbol_ref (FILE *file, rtx x)
15571 /* Currently C++ toc references to vtables can be emitted before it
15572 is decided whether the vtable is public or private. If this is
15573 the case, then the linker will eventually complain that there is
15574 a reference to an unknown section. Thus, for vtables only,
15575 we emit the TOC reference to reference the symbol and not the
15577 const char *name = XSTR (x, 0);
15579 if (VTABLE_NAME_P (name))
15581 RS6000_OUTPUT_BASENAME (file, name);
15584 assemble_name (file, name);
15587 /* Output a TOC entry. We derive the entry name from what is being
15591 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15594 const char *name = buf;
15595 const char *real_name;
15597 HOST_WIDE_INT offset = 0;
15599 gcc_assert (!TARGET_NO_TOC);
15601 /* When the linker won't eliminate them, don't output duplicate
15602 TOC entries (this happens on AIX if there is any kind of TOC,
15603 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15605 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15607 struct toc_hash_struct *h;
15610 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15611 time because GGC is not initialized at that point. */
15612 if (toc_hash_table == NULL)
15613 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15614 toc_hash_eq, NULL);
15616 h = ggc_alloc (sizeof (*h));
15618 h->key_mode = mode;
15619 h->labelno = labelno;
15621 found = htab_find_slot (toc_hash_table, h, 1);
15622 if (*found == NULL)
15624 else /* This is indeed a duplicate.
15625 Set this label equal to that label. */
15627 fputs ("\t.set ", file);
15628 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15629 fprintf (file, "%d,", labelno);
15630 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15631 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15637 /* If we're going to put a double constant in the TOC, make sure it's
15638 aligned properly when strict alignment is on. */
15639 if (GET_CODE (x) == CONST_DOUBLE
15640 && STRICT_ALIGNMENT
15641 && GET_MODE_BITSIZE (mode) >= 64
15642 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15643 ASM_OUTPUT_ALIGN (file, 3);
15646 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15648 /* Handle FP constants specially. Note that if we have a minimal
15649 TOC, things we put here aren't actually in the TOC, so we can allow
15651 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15653 REAL_VALUE_TYPE rv;
15656 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15657 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15661 if (TARGET_MINIMAL_TOC)
15662 fputs (DOUBLE_INT_ASM_OP, file);
15664 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15665 k[0] & 0xffffffff, k[1] & 0xffffffff,
15666 k[2] & 0xffffffff, k[3] & 0xffffffff);
15667 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15668 k[0] & 0xffffffff, k[1] & 0xffffffff,
15669 k[2] & 0xffffffff, k[3] & 0xffffffff);
15674 if (TARGET_MINIMAL_TOC)
15675 fputs ("\t.long ", file);
15677 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15678 k[0] & 0xffffffff, k[1] & 0xffffffff,
15679 k[2] & 0xffffffff, k[3] & 0xffffffff);
15680 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15681 k[0] & 0xffffffff, k[1] & 0xffffffff,
15682 k[2] & 0xffffffff, k[3] & 0xffffffff);
15686 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15688 REAL_VALUE_TYPE rv;
15691 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15692 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15696 if (TARGET_MINIMAL_TOC)
15697 fputs (DOUBLE_INT_ASM_OP, file);
15699 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15700 k[0] & 0xffffffff, k[1] & 0xffffffff);
15701 fprintf (file, "0x%lx%08lx\n",
15702 k[0] & 0xffffffff, k[1] & 0xffffffff);
15707 if (TARGET_MINIMAL_TOC)
15708 fputs ("\t.long ", file);
15710 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15711 k[0] & 0xffffffff, k[1] & 0xffffffff);
15712 fprintf (file, "0x%lx,0x%lx\n",
15713 k[0] & 0xffffffff, k[1] & 0xffffffff);
15717 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15719 REAL_VALUE_TYPE rv;
15722 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15723 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15727 if (TARGET_MINIMAL_TOC)
15728 fputs (DOUBLE_INT_ASM_OP, file);
15730 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15731 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15736 if (TARGET_MINIMAL_TOC)
15737 fputs ("\t.long ", file);
15739 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15740 fprintf (file, "0x%lx\n", l & 0xffffffff);
15744 else if (GET_MODE (x) == VOIDmode
15745 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15747 unsigned HOST_WIDE_INT low;
15748 HOST_WIDE_INT high;
15750 if (GET_CODE (x) == CONST_DOUBLE)
15752 low = CONST_DOUBLE_LOW (x);
15753 high = CONST_DOUBLE_HIGH (x);
15756 #if HOST_BITS_PER_WIDE_INT == 32
15759 high = (low & 0x80000000) ? ~0 : 0;
15763 low = INTVAL (x) & 0xffffffff;
15764 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15768 /* TOC entries are always Pmode-sized, but since this
15769 is a bigendian machine then if we're putting smaller
15770 integer constants in the TOC we have to pad them.
15771 (This is still a win over putting the constants in
15772 a separate constant pool, because then we'd have
15773 to have both a TOC entry _and_ the actual constant.)
15775 For a 32-bit target, CONST_INT values are loaded and shifted
15776 entirely within `low' and can be stored in one TOC entry. */
15778 /* It would be easy to make this work, but it doesn't now. */
15779 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15781 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15783 #if HOST_BITS_PER_WIDE_INT == 32
15784 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15785 POINTER_SIZE, &low, &high, 0);
15788 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15789 high = (HOST_WIDE_INT) low >> 32;
15796 if (TARGET_MINIMAL_TOC)
15797 fputs (DOUBLE_INT_ASM_OP, file);
15799 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15800 (long) high & 0xffffffff, (long) low & 0xffffffff);
15801 fprintf (file, "0x%lx%08lx\n",
15802 (long) high & 0xffffffff, (long) low & 0xffffffff);
15807 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15809 if (TARGET_MINIMAL_TOC)
15810 fputs ("\t.long ", file);
15812 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15813 (long) high & 0xffffffff, (long) low & 0xffffffff);
15814 fprintf (file, "0x%lx,0x%lx\n",
15815 (long) high & 0xffffffff, (long) low & 0xffffffff);
15819 if (TARGET_MINIMAL_TOC)
15820 fputs ("\t.long ", file);
15822 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15823 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15829 if (GET_CODE (x) == CONST)
15831 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15833 base = XEXP (XEXP (x, 0), 0);
15834 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15837 switch (GET_CODE (base))
15840 name = XSTR (base, 0);
15844 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15845 CODE_LABEL_NUMBER (XEXP (base, 0)));
15849 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15853 gcc_unreachable ();
15856 real_name = (*targetm.strip_name_encoding) (name);
15857 if (TARGET_MINIMAL_TOC)
15858 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15861 fprintf (file, "\t.tc %s", real_name);
15864 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
15866 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
15868 fputs ("[TC],", file);
15871 /* Currently C++ toc references to vtables can be emitted before it
15872 is decided whether the vtable is public or private. If this is
15873 the case, then the linker will eventually complain that there is
15874 a TOC reference to an unknown section. Thus, for vtables only,
15875 we emit the TOC reference to reference the symbol and not the
15877 if (VTABLE_NAME_P (name))
15879 RS6000_OUTPUT_BASENAME (file, name);
15881 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
15882 else if (offset > 0)
15883 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
15886 output_addr_const (file, x);
15890 /* Output an assembler pseudo-op to write an ASCII string of N characters
15891 starting at P to FILE.
15893 On the RS/6000, we have to do this using the .byte operation and
15894 write out special characters outside the quoted string.
15895 Also, the assembler is broken; very long strings are truncated,
15896 so we must artificially break them up early. */
15899 output_ascii (FILE *file, const char *p, int n)
15902 int i, count_string;
15903 const char *for_string = "\t.byte \"";
15904 const char *for_decimal = "\t.byte ";
15905 const char *to_close = NULL;
15908 for (i = 0; i < n; i++)
15911 if (c >= ' ' && c < 0177)
15914 fputs (for_string, file);
15917 /* Write two quotes to get one. */
15925 for_decimal = "\"\n\t.byte ";
15929 if (count_string >= 512)
15931 fputs (to_close, file);
15933 for_string = "\t.byte \"";
15934 for_decimal = "\t.byte ";
15942 fputs (for_decimal, file);
15943 fprintf (file, "%d", c);
15945 for_string = "\n\t.byte \"";
15946 for_decimal = ", ";
15952 /* Now close the string if we have written one. Then end the line. */
15954 fputs (to_close, file);
15957 /* Generate a unique section name for FILENAME for a section type
15958 represented by SECTION_DESC. Output goes into BUF.
15960 SECTION_DESC can be any string, as long as it is different for each
15961 possible section type.
15963 We name the section in the same manner as xlc. The name begins with an
15964 underscore followed by the filename (after stripping any leading directory
15965 names) with the last period replaced by the string SECTION_DESC. If
15966 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15970 rs6000_gen_section_name (char **buf, const char *filename,
15971 const char *section_desc)
15973 const char *q, *after_last_slash, *last_period = 0;
15977 after_last_slash = filename;
15978 for (q = filename; *q; q++)
15981 after_last_slash = q + 1;
15982 else if (*q == '.')
15986 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15987 *buf = (char *) xmalloc (len);
15992 for (q = after_last_slash; *q; q++)
15994 if (q == last_period)
15996 strcpy (p, section_desc);
15997 p += strlen (section_desc);
16001 else if (ISALNUM (*q))
16005 if (last_period == 0)
16006 strcpy (p, section_desc);
16011 /* Emit profile function. */
16014 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16016 /* Non-standard profiling for kernels, which just saves LR then calls
16017 _mcount without worrying about arg saves. The idea is to change
16018 the function prologue as little as possible as it isn't easy to
16019 account for arg save/restore code added just for _mcount. */
16020 if (TARGET_PROFILE_KERNEL)
16023 if (DEFAULT_ABI == ABI_AIX)
16025 #ifndef NO_PROFILE_COUNTERS
16026 # define NO_PROFILE_COUNTERS 0
16028 if (NO_PROFILE_COUNTERS)
16029 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16033 const char *label_name;
16036 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16037 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16038 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16040 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16044 else if (DEFAULT_ABI == ABI_DARWIN)
16046 const char *mcount_name = RS6000_MCOUNT;
16047 int caller_addr_regno = LINK_REGISTER_REGNUM;
16049 /* Be conservative and always set this, at least for now. */
16050 current_function_uses_pic_offset_table = 1;
16053 /* For PIC code, set up a stub and collect the caller's address
16054 from r0, which is where the prologue puts it. */
16055 if (MACHOPIC_INDIRECT
16056 && current_function_uses_pic_offset_table)
16057 caller_addr_regno = 0;
16059 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16061 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16065 /* Write function profiler code. */
16068 output_function_profiler (FILE *file, int labelno)
16072 switch (DEFAULT_ABI)
16075 gcc_unreachable ();
16080 warning (0, "no profiling of 64-bit code for this ABI");
16083 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16084 fprintf (file, "\tmflr %s\n", reg_names[0]);
16085 if (NO_PROFILE_COUNTERS)
16087 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16088 reg_names[0], reg_names[1]);
16090 else if (TARGET_SECURE_PLT && flag_pic)
16092 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16093 reg_names[0], reg_names[1]);
16094 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16095 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16096 reg_names[12], reg_names[12]);
16097 assemble_name (file, buf);
16098 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16099 assemble_name (file, buf);
16100 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16102 else if (flag_pic == 1)
16104 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16105 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16106 reg_names[0], reg_names[1]);
16107 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16108 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16109 assemble_name (file, buf);
16110 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16112 else if (flag_pic > 1)
16114 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16115 reg_names[0], reg_names[1]);
16116 /* Now, we need to get the address of the label. */
16117 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16118 assemble_name (file, buf);
16119 fputs ("-.\n1:", file);
16120 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16121 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16122 reg_names[0], reg_names[11]);
16123 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16124 reg_names[0], reg_names[0], reg_names[11]);
16128 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16129 assemble_name (file, buf);
16130 fputs ("@ha\n", file);
16131 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16132 reg_names[0], reg_names[1]);
16133 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16134 assemble_name (file, buf);
16135 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16138 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16139 fprintf (file, "\tbl %s%s\n",
16140 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16145 if (!TARGET_PROFILE_KERNEL)
16147 /* Don't do anything, done in output_profile_hook (). */
16151 gcc_assert (!TARGET_32BIT);
16153 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16154 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16156 if (cfun->static_chain_decl != NULL)
16158 asm_fprintf (file, "\tstd %s,24(%s)\n",
16159 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16160 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16161 asm_fprintf (file, "\tld %s,24(%s)\n",
16162 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16165 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16172 /* Power4 load update and store update instructions are cracked into a
16173 load or store and an integer insn which are executed in the same cycle.
16174 Branches have their own dispatch slot which does not count against the
16175 GCC issue rate, but it changes the program flow so there are no other
16176 instructions to issue in this cycle. */
16179 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16180 int verbose ATTRIBUTE_UNUSED,
16181 rtx insn, int more)
16183 if (GET_CODE (PATTERN (insn)) == USE
16184 || GET_CODE (PATTERN (insn)) == CLOBBER)
16187 if (rs6000_sched_groups)
16189 if (is_microcoded_insn (insn))
16191 else if (is_cracked_insn (insn))
16192 return more > 2 ? more - 2 : 0;
16198 /* Adjust the cost of a scheduling dependency. Return the new cost of
16199 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16202 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16204 if (! recog_memoized (insn))
16207 if (REG_NOTE_KIND (link) != 0)
16210 if (REG_NOTE_KIND (link) == 0)
16212 /* Data dependency; DEP_INSN writes a register that INSN reads
16213 some cycles later. */
16215 /* Separate a load from a narrower, dependent store. */
16216 if (rs6000_sched_groups
16217 && GET_CODE (PATTERN (insn)) == SET
16218 && GET_CODE (PATTERN (dep_insn)) == SET
16219 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16220 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16221 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16222 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16225 switch (get_attr_type (insn))
16228 /* Tell the first scheduling pass about the latency between
16229 a mtctr and bctr (and mtlr and br/blr). The first
16230 scheduling pass will not know about this latency since
16231 the mtctr instruction, which has the latency associated
16232 to it, will be generated by reload. */
16233 return TARGET_POWER ? 5 : 4;
16235 /* Leave some extra cycles between a compare and its
16236 dependent branch, to inhibit expensive mispredicts. */
16237 if ((rs6000_cpu_attr == CPU_PPC603
16238 || rs6000_cpu_attr == CPU_PPC604
16239 || rs6000_cpu_attr == CPU_PPC604E
16240 || rs6000_cpu_attr == CPU_PPC620
16241 || rs6000_cpu_attr == CPU_PPC630
16242 || rs6000_cpu_attr == CPU_PPC750
16243 || rs6000_cpu_attr == CPU_PPC7400
16244 || rs6000_cpu_attr == CPU_PPC7450
16245 || rs6000_cpu_attr == CPU_POWER4
16246 || rs6000_cpu_attr == CPU_POWER5)
16247 && recog_memoized (dep_insn)
16248 && (INSN_CODE (dep_insn) >= 0)
16249 && (get_attr_type (dep_insn) == TYPE_CMP
16250 || get_attr_type (dep_insn) == TYPE_COMPARE
16251 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16252 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16253 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16254 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16255 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16256 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16261 /* Fall out to return default cost. */
16267 /* The function returns a true if INSN is microcoded.
16268 Return false otherwise. */
16271 is_microcoded_insn (rtx insn)
16273 if (!insn || !INSN_P (insn)
16274 || GET_CODE (PATTERN (insn)) == USE
16275 || GET_CODE (PATTERN (insn)) == CLOBBER)
16278 if (rs6000_sched_groups)
16280 enum attr_type type = get_attr_type (insn);
16281 if (type == TYPE_LOAD_EXT_U
16282 || type == TYPE_LOAD_EXT_UX
16283 || type == TYPE_LOAD_UX
16284 || type == TYPE_STORE_UX
16285 || type == TYPE_MFCR)
16292 /* The function returns a nonzero value if INSN can be scheduled only
16293 as the first insn in a dispatch group ("dispatch-slot restricted").
16294 In this case, the returned value indicates how many dispatch slots
16295 the insn occupies (at the beginning of the group).
16296 Return 0 otherwise. */
16299 is_dispatch_slot_restricted (rtx insn)
16301 enum attr_type type;
16303 if (!rs6000_sched_groups)
16307 || insn == NULL_RTX
16308 || GET_CODE (insn) == NOTE
16309 || GET_CODE (PATTERN (insn)) == USE
16310 || GET_CODE (PATTERN (insn)) == CLOBBER)
16313 type = get_attr_type (insn);
16320 case TYPE_DELAYED_CR:
16321 case TYPE_CR_LOGICAL:
16334 if (rs6000_cpu == PROCESSOR_POWER5
16335 && is_cracked_insn (insn))
16341 /* The function returns true if INSN is cracked into 2 instructions
16342 by the processor (and therefore occupies 2 issue slots). */
16345 is_cracked_insn (rtx insn)
16347 if (!insn || !INSN_P (insn)
16348 || GET_CODE (PATTERN (insn)) == USE
16349 || GET_CODE (PATTERN (insn)) == CLOBBER)
16352 if (rs6000_sched_groups)
16354 enum attr_type type = get_attr_type (insn);
16355 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16356 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16357 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16358 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16359 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16360 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16361 || type == TYPE_IDIV || type == TYPE_LDIV
16362 || type == TYPE_INSERT_WORD)
16369 /* The function returns true if INSN can be issued only from
16370 the branch slot. */
16373 is_branch_slot_insn (rtx insn)
16375 if (!insn || !INSN_P (insn)
16376 || GET_CODE (PATTERN (insn)) == USE
16377 || GET_CODE (PATTERN (insn)) == CLOBBER)
16380 if (rs6000_sched_groups)
16382 enum attr_type type = get_attr_type (insn);
16383 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16391 /* A C statement (sans semicolon) to update the integer scheduling
16392 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16393 INSN earlier, reduce the priority to execute INSN later. Do not
16394 define this macro if you do not need to adjust the scheduling
16395 priorities of insns. */
16398 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16400 /* On machines (like the 750) which have asymmetric integer units,
16401 where one integer unit can do multiply and divides and the other
16402 can't, reduce the priority of multiply/divide so it is scheduled
16403 before other integer operations. */
16406 if (! INSN_P (insn))
16409 if (GET_CODE (PATTERN (insn)) == USE)
16412 switch (rs6000_cpu_attr) {
16414 switch (get_attr_type (insn))
16421 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16422 priority, priority);
16423 if (priority >= 0 && priority < 0x01000000)
16430 if (is_dispatch_slot_restricted (insn)
16431 && reload_completed
16432 && current_sched_info->sched_max_insns_priority
16433 && rs6000_sched_restricted_insns_priority)
16436 /* Prioritize insns that can be dispatched only in the first
16438 if (rs6000_sched_restricted_insns_priority == 1)
16439 /* Attach highest priority to insn. This means that in
16440 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16441 precede 'priority' (critical path) considerations. */
16442 return current_sched_info->sched_max_insns_priority;
16443 else if (rs6000_sched_restricted_insns_priority == 2)
16444 /* Increase priority of insn by a minimal amount. This means that in
16445 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16446 considerations precede dispatch-slot restriction considerations. */
16447 return (priority + 1);
16453 /* Return how many instructions the machine can issue per cycle. */
16456 rs6000_issue_rate (void)
16458 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16459 if (!reload_completed)
16462 switch (rs6000_cpu_attr) {
16463 case CPU_RIOS1: /* ? */
16465 case CPU_PPC601: /* ? */
16488 /* Return how many instructions to look ahead for better insn
16492 rs6000_use_sched_lookahead (void)
16494 if (rs6000_cpu_attr == CPU_PPC8540)
16499 /* Determine is PAT refers to memory. */
16502 is_mem_ref (rtx pat)
16508 if (GET_CODE (pat) == MEM)
16511 /* Recursively process the pattern. */
16512 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16514 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16517 ret |= is_mem_ref (XEXP (pat, i));
16518 else if (fmt[i] == 'E')
16519 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16520 ret |= is_mem_ref (XVECEXP (pat, i, j));
16526 /* Determine if PAT is a PATTERN of a load insn. */
16529 is_load_insn1 (rtx pat)
16531 if (!pat || pat == NULL_RTX)
16534 if (GET_CODE (pat) == SET)
16535 return is_mem_ref (SET_SRC (pat));
16537 if (GET_CODE (pat) == PARALLEL)
16541 for (i = 0; i < XVECLEN (pat, 0); i++)
16542 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16549 /* Determine if INSN loads from memory. */
16552 is_load_insn (rtx insn)
16554 if (!insn || !INSN_P (insn))
16557 if (GET_CODE (insn) == CALL_INSN)
16560 return is_load_insn1 (PATTERN (insn));
16563 /* Determine if PAT is a PATTERN of a store insn. */
16566 is_store_insn1 (rtx pat)
16568 if (!pat || pat == NULL_RTX)
16571 if (GET_CODE (pat) == SET)
16572 return is_mem_ref (SET_DEST (pat));
16574 if (GET_CODE (pat) == PARALLEL)
16578 for (i = 0; i < XVECLEN (pat, 0); i++)
16579 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16586 /* Determine if INSN stores to memory. */
16589 is_store_insn (rtx insn)
16591 if (!insn || !INSN_P (insn))
16594 return is_store_insn1 (PATTERN (insn));
16597 /* Returns whether the dependence between INSN and NEXT is considered
16598 costly by the given target. */
16601 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16604 /* If the flag is not enabled - no dependence is considered costly;
16605 allow all dependent insns in the same group.
16606 This is the most aggressive option. */
16607 if (rs6000_sched_costly_dep == no_dep_costly)
16610 /* If the flag is set to 1 - a dependence is always considered costly;
16611 do not allow dependent instructions in the same group.
16612 This is the most conservative option. */
16613 if (rs6000_sched_costly_dep == all_deps_costly)
16616 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16617 && is_load_insn (next)
16618 && is_store_insn (insn))
16619 /* Prevent load after store in the same group. */
16622 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16623 && is_load_insn (next)
16624 && is_store_insn (insn)
16625 && (!link || (int) REG_NOTE_KIND (link) == 0))
16626 /* Prevent load after store in the same group if it is a true
16630 /* The flag is set to X; dependences with latency >= X are considered costly,
16631 and will not be scheduled in the same group. */
16632 if (rs6000_sched_costly_dep <= max_dep_latency
16633 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16639 /* Return the next insn after INSN that is found before TAIL is reached,
16640 skipping any "non-active" insns - insns that will not actually occupy
16641 an issue slot. Return NULL_RTX if such an insn is not found. */
16644 get_next_active_insn (rtx insn, rtx tail)
16646 if (insn == NULL_RTX || insn == tail)
16651 insn = NEXT_INSN (insn);
16652 if (insn == NULL_RTX || insn == tail)
16657 || (NONJUMP_INSN_P (insn)
16658 && GET_CODE (PATTERN (insn)) != USE
16659 && GET_CODE (PATTERN (insn)) != CLOBBER
16660 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16666 /* Return whether the presence of INSN causes a dispatch group termination
16667 of group WHICH_GROUP.
16669 If WHICH_GROUP == current_group, this function will return true if INSN
16670 causes the termination of the current group (i.e, the dispatch group to
16671 which INSN belongs). This means that INSN will be the last insn in the
16672 group it belongs to.
16674 If WHICH_GROUP == previous_group, this function will return true if INSN
16675 causes the termination of the previous group (i.e, the dispatch group that
16676 precedes the group to which INSN belongs). This means that INSN will be
16677 the first insn in the group it belongs to). */
16680 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16682 enum attr_type type;
16687 type = get_attr_type (insn);
16689 if (is_microcoded_insn (insn))
16692 if (which_group == current_group)
16694 if (is_branch_slot_insn (insn))
16698 else if (which_group == previous_group)
16700 if (is_dispatch_slot_restricted (insn))
16708 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16709 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16712 is_costly_group (rtx *group_insns, rtx next_insn)
16717 int issue_rate = rs6000_issue_rate ();
16719 for (i = 0; i < issue_rate; i++)
16721 rtx insn = group_insns[i];
16724 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16726 rtx next = XEXP (link, 0);
16727 if (next == next_insn)
16729 cost = insn_cost (insn, link, next_insn);
16730 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16739 /* Utility of the function redefine_groups.
16740 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16741 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16742 to keep it "far" (in a separate group) from GROUP_INSNS, following
16743 one of the following schemes, depending on the value of the flag
16744 -minsert_sched_nops = X:
16745 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16746 in order to force NEXT_INSN into a separate group.
16747 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16748 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16749 insertion (has a group just ended, how many vacant issue slots remain in the
16750 last group, and how many dispatch groups were encountered so far). */
16753 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16754 rtx next_insn, bool *group_end, int can_issue_more,
16759 int issue_rate = rs6000_issue_rate ();
16760 bool end = *group_end;
16763 if (next_insn == NULL_RTX)
16764 return can_issue_more;
16766 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16767 return can_issue_more;
16769 force = is_costly_group (group_insns, next_insn);
16771 return can_issue_more;
16773 if (sched_verbose > 6)
16774 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16775 *group_count ,can_issue_more);
16777 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16780 can_issue_more = 0;
16782 /* Since only a branch can be issued in the last issue_slot, it is
16783 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16784 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16785 in this case the last nop will start a new group and the branch
16786 will be forced to the new group. */
16787 if (can_issue_more && !is_branch_slot_insn (next_insn))
16790 while (can_issue_more > 0)
16793 emit_insn_before (nop, next_insn);
16801 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16803 int n_nops = rs6000_sched_insert_nops;
16805 /* Nops can't be issued from the branch slot, so the effective
16806 issue_rate for nops is 'issue_rate - 1'. */
16807 if (can_issue_more == 0)
16808 can_issue_more = issue_rate;
16810 if (can_issue_more == 0)
16812 can_issue_more = issue_rate - 1;
16815 for (i = 0; i < issue_rate; i++)
16817 group_insns[i] = 0;
16824 emit_insn_before (nop, next_insn);
16825 if (can_issue_more == issue_rate - 1) /* new group begins */
16828 if (can_issue_more == 0)
16830 can_issue_more = issue_rate - 1;
16833 for (i = 0; i < issue_rate; i++)
16835 group_insns[i] = 0;
16841 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16844 /* Is next_insn going to start a new group? */
16847 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16848 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16849 || (can_issue_more < issue_rate &&
16850 insn_terminates_group_p (next_insn, previous_group)));
16851 if (*group_end && end)
16854 if (sched_verbose > 6)
16855 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16856 *group_count, can_issue_more);
16857 return can_issue_more;
16860 return can_issue_more;
16863 /* This function tries to synch the dispatch groups that the compiler "sees"
16864 with the dispatch groups that the processor dispatcher is expected to
16865 form in practice. It tries to achieve this synchronization by forcing the
16866 estimated processor grouping on the compiler (as opposed to the function
16867 'pad_goups' which tries to force the scheduler's grouping on the processor).
16869 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16870 examines the (estimated) dispatch groups that will be formed by the processor
16871 dispatcher. It marks these group boundaries to reflect the estimated
16872 processor grouping, overriding the grouping that the scheduler had marked.
16873 Depending on the value of the flag '-minsert-sched-nops' this function can
16874 force certain insns into separate groups or force a certain distance between
16875 them by inserting nops, for example, if there exists a "costly dependence"
16878 The function estimates the group boundaries that the processor will form as
16879 follows: It keeps track of how many vacant issue slots are available after
16880 each insn. A subsequent insn will start a new group if one of the following
16882 - no more vacant issue slots remain in the current dispatch group.
16883 - only the last issue slot, which is the branch slot, is vacant, but the next
16884 insn is not a branch.
16885 - only the last 2 or less issue slots, including the branch slot, are vacant,
16886 which means that a cracked insn (which occupies two issue slots) can't be
16887 issued in this group.
16888 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16889 start a new group. */
16892 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16894 rtx insn, next_insn;
16896 int can_issue_more;
16899 int group_count = 0;
16903 issue_rate = rs6000_issue_rate ();
16904 group_insns = alloca (issue_rate * sizeof (rtx));
16905 for (i = 0; i < issue_rate; i++)
16907 group_insns[i] = 0;
16909 can_issue_more = issue_rate;
16911 insn = get_next_active_insn (prev_head_insn, tail);
16914 while (insn != NULL_RTX)
16916 slot = (issue_rate - can_issue_more);
16917 group_insns[slot] = insn;
16919 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16920 if (insn_terminates_group_p (insn, current_group))
16921 can_issue_more = 0;
16923 next_insn = get_next_active_insn (insn, tail);
16924 if (next_insn == NULL_RTX)
16925 return group_count + 1;
16927 /* Is next_insn going to start a new group? */
16929 = (can_issue_more == 0
16930 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16931 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16932 || (can_issue_more < issue_rate &&
16933 insn_terminates_group_p (next_insn, previous_group)));
16935 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16936 next_insn, &group_end, can_issue_more,
16942 can_issue_more = 0;
16943 for (i = 0; i < issue_rate; i++)
16945 group_insns[i] = 0;
16949 if (GET_MODE (next_insn) == TImode && can_issue_more)
16950 PUT_MODE (next_insn, VOIDmode);
16951 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16952 PUT_MODE (next_insn, TImode);
16955 if (can_issue_more == 0)
16956 can_issue_more = issue_rate;
16959 return group_count;
16962 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16963 dispatch group boundaries that the scheduler had marked. Pad with nops
16964 any dispatch groups which have vacant issue slots, in order to force the
16965 scheduler's grouping on the processor dispatcher. The function
16966 returns the number of dispatch groups found. */
16969 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16971 rtx insn, next_insn;
16974 int can_issue_more;
16976 int group_count = 0;
16978 /* Initialize issue_rate. */
16979 issue_rate = rs6000_issue_rate ();
16980 can_issue_more = issue_rate;
16982 insn = get_next_active_insn (prev_head_insn, tail);
16983 next_insn = get_next_active_insn (insn, tail);
16985 while (insn != NULL_RTX)
16988 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16990 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16992 if (next_insn == NULL_RTX)
16997 /* If the scheduler had marked group termination at this location
16998 (between insn and next_indn), and neither insn nor next_insn will
16999 force group termination, pad the group with nops to force group
17002 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17003 && !insn_terminates_group_p (insn, current_group)
17004 && !insn_terminates_group_p (next_insn, previous_group))
17006 if (!is_branch_slot_insn (next_insn))
17009 while (can_issue_more)
17012 emit_insn_before (nop, next_insn);
17017 can_issue_more = issue_rate;
17022 next_insn = get_next_active_insn (insn, tail);
17025 return group_count;
17028 /* The following function is called at the end of scheduling BB.
17029 After reload, it inserts nops at insn group bundling. */
17032 rs6000_sched_finish (FILE *dump, int sched_verbose)
17037 fprintf (dump, "=== Finishing schedule.\n");
17039 if (reload_completed && rs6000_sched_groups)
17041 if (rs6000_sched_insert_nops == sched_finish_none)
17044 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17045 n_groups = pad_groups (dump, sched_verbose,
17046 current_sched_info->prev_head,
17047 current_sched_info->next_tail);
17049 n_groups = redefine_groups (dump, sched_verbose,
17050 current_sched_info->prev_head,
17051 current_sched_info->next_tail);
17053 if (sched_verbose >= 6)
17055 fprintf (dump, "ngroups = %d\n", n_groups);
17056 print_rtl (dump, current_sched_info->prev_head);
17057 fprintf (dump, "Done finish_sched\n");
17062 /* Length in units of the trampoline for entering a nested function. */
17065 rs6000_trampoline_size (void)
17069 switch (DEFAULT_ABI)
17072 gcc_unreachable ();
17075 ret = (TARGET_32BIT) ? 12 : 24;
17080 ret = (TARGET_32BIT) ? 40 : 48;
17087 /* Emit RTL insns to initialize the variable parts of a trampoline.
17088 FNADDR is an RTX for the address of the function's pure code.
17089 CXT is an RTX for the static chain value for the function. */
17092 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17094 enum machine_mode pmode = Pmode;
17095 int regsize = (TARGET_32BIT) ? 4 : 8;
17096 rtx ctx_reg = force_reg (pmode, cxt);
17098 switch (DEFAULT_ABI)
17101 gcc_unreachable ();
17103 /* Macros to shorten the code expansions below. */
17104 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17105 #define MEM_PLUS(addr,offset) \
17106 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17108 /* Under AIX, just build the 3 word function descriptor */
17111 rtx fn_reg = gen_reg_rtx (pmode);
17112 rtx toc_reg = gen_reg_rtx (pmode);
17113 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17114 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17115 emit_move_insn (MEM_DEREF (addr), fn_reg);
17116 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17117 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17121 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17124 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17125 FALSE, VOIDmode, 4,
17127 GEN_INT (rs6000_trampoline_size ()), SImode,
17137 /* Table of valid machine attributes. */
17139 const struct attribute_spec rs6000_attribute_table[] =
17141 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17142 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17143 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17144 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17145 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17146 SUBTARGET_ATTRIBUTE_TABLE,
17148 { NULL, 0, 0, false, false, false, NULL }
17151 /* Handle the "altivec" attribute. The attribute may have
17152 arguments as follows:
17154 __attribute__((altivec(vector__)))
17155 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17156 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17158 and may appear more than once (e.g., 'vector bool char') in a
17159 given declaration. */
17162 rs6000_handle_altivec_attribute (tree *node,
17163 tree name ATTRIBUTE_UNUSED,
17165 int flags ATTRIBUTE_UNUSED,
17166 bool *no_add_attrs)
17168 tree type = *node, result = NULL_TREE;
17169 enum machine_mode mode;
17172 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17173 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17174 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17177 while (POINTER_TYPE_P (type)
17178 || TREE_CODE (type) == FUNCTION_TYPE
17179 || TREE_CODE (type) == METHOD_TYPE
17180 || TREE_CODE (type) == ARRAY_TYPE)
17181 type = TREE_TYPE (type);
17183 mode = TYPE_MODE (type);
17185 /* Check for invalid AltiVec type qualifiers. */
17186 if (type == long_unsigned_type_node || type == long_integer_type_node)
17189 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17190 else if (rs6000_warn_altivec_long)
17191 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17193 else if (type == long_long_unsigned_type_node
17194 || type == long_long_integer_type_node)
17195 error ("use of %<long long%> in AltiVec types is invalid");
17196 else if (type == double_type_node)
17197 error ("use of %<double%> in AltiVec types is invalid");
17198 else if (type == long_double_type_node)
17199 error ("use of %<long double%> in AltiVec types is invalid");
17200 else if (type == boolean_type_node)
17201 error ("use of boolean types in AltiVec types is invalid");
17202 else if (TREE_CODE (type) == COMPLEX_TYPE)
17203 error ("use of %<complex%> in AltiVec types is invalid");
17205 switch (altivec_type)
17208 unsigned_p = TYPE_UNSIGNED (type);
17212 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17215 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17218 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17220 case SFmode: result = V4SF_type_node; break;
17221 /* If the user says 'vector int bool', we may be handed the 'bool'
17222 attribute _before_ the 'vector' attribute, and so select the
17223 proper type in the 'b' case below. */
17224 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17232 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17233 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17234 case QImode: case V16QImode: result = bool_V16QI_type_node;
17241 case V8HImode: result = pixel_V8HI_type_node;
17247 if (result && result != type && TYPE_READONLY (type))
17248 result = build_qualified_type (result, TYPE_QUAL_CONST);
17250 *no_add_attrs = true; /* No need to hang on to the attribute. */
17253 *node = reconstruct_complex_type (*node, result);
17258 /* AltiVec defines four built-in scalar types that serve as vector
17259 elements; we must teach the compiler how to mangle them. */
17261 static const char *
17262 rs6000_mangle_fundamental_type (tree type)
17264 if (type == bool_char_type_node) return "U6__boolc";
17265 if (type == bool_short_type_node) return "U6__bools";
17266 if (type == pixel_type_node) return "u7__pixel";
17267 if (type == bool_int_type_node) return "U6__booli";
17269 /* For all other types, use normal C++ mangling. */
17273 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17274 struct attribute_spec.handler. */
17277 rs6000_handle_longcall_attribute (tree *node, tree name,
17278 tree args ATTRIBUTE_UNUSED,
17279 int flags ATTRIBUTE_UNUSED,
17280 bool *no_add_attrs)
17282 if (TREE_CODE (*node) != FUNCTION_TYPE
17283 && TREE_CODE (*node) != FIELD_DECL
17284 && TREE_CODE (*node) != TYPE_DECL)
17286 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17287 IDENTIFIER_POINTER (name));
17288 *no_add_attrs = true;
17294 /* Set longcall attributes on all functions declared when
17295 rs6000_default_long_calls is true. */
17297 rs6000_set_default_type_attributes (tree type)
17299 if (rs6000_default_long_calls
17300 && (TREE_CODE (type) == FUNCTION_TYPE
17301 || TREE_CODE (type) == METHOD_TYPE))
17302 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17304 TYPE_ATTRIBUTES (type));
17307 /* Return a reference suitable for calling a function with the
17308 longcall attribute. */
17311 rs6000_longcall_ref (rtx call_ref)
17313 const char *call_name;
17316 if (GET_CODE (call_ref) != SYMBOL_REF)
17319 /* System V adds '.' to the internal name, so skip them. */
17320 call_name = XSTR (call_ref, 0);
17321 if (*call_name == '.')
17323 while (*call_name == '.')
17326 node = get_identifier (call_name);
17327 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17330 return force_reg (Pmode, call_ref);
17333 #ifdef USING_ELFOS_H
17335 /* A get_unnamed_section callback, used for switching to toc_section. */
17338 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17340 if (DEFAULT_ABI == ABI_AIX
17341 && TARGET_MINIMAL_TOC
17342 && !TARGET_RELOCATABLE)
17344 if (!toc_initialized)
17346 toc_initialized = 1;
17347 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17348 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17349 fprintf (asm_out_file, "\t.tc ");
17350 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17351 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17352 fprintf (asm_out_file, "\n");
17354 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17355 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17356 fprintf (asm_out_file, " = .+32768\n");
17359 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17361 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17362 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17365 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17366 if (!toc_initialized)
17368 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17369 fprintf (asm_out_file, " = .+32768\n");
17370 toc_initialized = 1;
17375 /* Implement TARGET_ASM_INIT_SECTIONS. */
17378 rs6000_elf_asm_init_sections (void)
17381 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17384 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17385 SDATA2_SECTION_ASM_OP);
17388 /* Implement TARGET_SELECT_RTX_SECTION. */
17391 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17392 unsigned HOST_WIDE_INT align)
17394 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17395 return toc_section;
17397 return default_elf_select_rtx_section (mode, x, align);
17400 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17403 rs6000_elf_select_section (tree decl, int reloc,
17404 unsigned HOST_WIDE_INT align)
17406 /* Pretend that we're always building for a shared library when
17407 ABI_AIX, because otherwise we end up with dynamic relocations
17408 in read-only sections. This happens for function pointers,
17409 references to vtables in typeinfo, and probably other cases. */
17410 return default_elf_select_section_1 (decl, reloc, align,
17411 flag_pic || DEFAULT_ABI == ABI_AIX);
17414 /* A C statement to build up a unique section name, expressed as a
17415 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17416 RELOC indicates whether the initial value of EXP requires
17417 link-time relocations. If you do not define this macro, GCC will use
17418 the symbol name prefixed by `.' as the section name. Note - this
17419 macro can now be called for uninitialized data items as well as
17420 initialized data and functions. */
17423 rs6000_elf_unique_section (tree decl, int reloc)
17425 /* As above, pretend that we're always building for a shared library
17426 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17427 default_unique_section_1 (decl, reloc,
17428 flag_pic || DEFAULT_ABI == ABI_AIX);
17431 /* For a SYMBOL_REF, set generic flags and then perform some
17432 target-specific processing.
17434 When the AIX ABI is requested on a non-AIX system, replace the
17435 function name with the real name (with a leading .) rather than the
17436 function descriptor name. This saves a lot of overriding code to
17437 read the prefixes. */
17440 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17442 default_encode_section_info (decl, rtl, first);
17445 && TREE_CODE (decl) == FUNCTION_DECL
17447 && DEFAULT_ABI == ABI_AIX)
17449 rtx sym_ref = XEXP (rtl, 0);
17450 size_t len = strlen (XSTR (sym_ref, 0));
17451 char *str = alloca (len + 2);
17453 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17454 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17459 rs6000_elf_in_small_data_p (tree decl)
17461 if (rs6000_sdata == SDATA_NONE)
17464 /* We want to merge strings, so we never consider them small data. */
17465 if (TREE_CODE (decl) == STRING_CST)
17468 /* Functions are never in the small data area. */
17469 if (TREE_CODE (decl) == FUNCTION_DECL)
17472 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17474 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17475 if (strcmp (section, ".sdata") == 0
17476 || strcmp (section, ".sdata2") == 0
17477 || strcmp (section, ".sbss") == 0
17478 || strcmp (section, ".sbss2") == 0
17479 || strcmp (section, ".PPC.EMB.sdata0") == 0
17480 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17485 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17488 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17489 /* If it's not public, and we're not going to reference it there,
17490 there's no need to put it in the small data section. */
17491 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17498 #endif /* USING_ELFOS_H */
17501 /* Return a REG that occurs in ADDR with coefficient 1.
17502 ADDR can be effectively incremented by incrementing REG.
17504 r0 is special and we must not select it as an address
17505 register by this routine since our caller will try to
17506 increment the returned register via an "la" instruction. */
17509 find_addr_reg (rtx addr)
17511 while (GET_CODE (addr) == PLUS)
17513 if (GET_CODE (XEXP (addr, 0)) == REG
17514 && REGNO (XEXP (addr, 0)) != 0)
17515 addr = XEXP (addr, 0);
17516 else if (GET_CODE (XEXP (addr, 1)) == REG
17517 && REGNO (XEXP (addr, 1)) != 0)
17518 addr = XEXP (addr, 1);
17519 else if (CONSTANT_P (XEXP (addr, 0)))
17520 addr = XEXP (addr, 1);
17521 else if (CONSTANT_P (XEXP (addr, 1)))
17522 addr = XEXP (addr, 0);
17524 gcc_unreachable ();
17526 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17531 rs6000_fatal_bad_address (rtx op)
17533 fatal_insn ("bad address", op);
17538 static tree branch_island_list = 0;
17540 /* Remember to generate a branch island for far calls to the given
17544 add_compiler_branch_island (tree label_name, tree function_name,
17547 tree branch_island = build_tree_list (function_name, label_name);
17548 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17549 TREE_CHAIN (branch_island) = branch_island_list;
17550 branch_island_list = branch_island;
17553 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17554 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17555 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17556 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17558 /* Generate far-jump branch islands for everything on the
17559 branch_island_list. Invoked immediately after the last instruction
17560 of the epilogue has been emitted; the branch-islands must be
17561 appended to, and contiguous with, the function body. Mach-O stubs
17562 are generated in machopic_output_stub(). */
17565 macho_branch_islands (void)
17568 tree branch_island;
17570 for (branch_island = branch_island_list;
17572 branch_island = TREE_CHAIN (branch_island))
17574 const char *label =
17575 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17577 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17578 char name_buf[512];
17579 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17580 if (name[0] == '*' || name[0] == '&')
17581 strcpy (name_buf, name+1);
17585 strcpy (name_buf+1, name);
17587 strcpy (tmp_buf, "\n");
17588 strcat (tmp_buf, label);
17589 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17590 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17591 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17592 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17595 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17596 strcat (tmp_buf, label);
17597 strcat (tmp_buf, "_pic\n");
17598 strcat (tmp_buf, label);
17599 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17601 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17602 strcat (tmp_buf, name_buf);
17603 strcat (tmp_buf, " - ");
17604 strcat (tmp_buf, label);
17605 strcat (tmp_buf, "_pic)\n");
17607 strcat (tmp_buf, "\tmtlr r0\n");
17609 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17610 strcat (tmp_buf, name_buf);
17611 strcat (tmp_buf, " - ");
17612 strcat (tmp_buf, label);
17613 strcat (tmp_buf, "_pic)\n");
17615 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17619 strcat (tmp_buf, ":\nlis r12,hi16(");
17620 strcat (tmp_buf, name_buf);
17621 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17622 strcat (tmp_buf, name_buf);
17623 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17625 output_asm_insn (tmp_buf, 0);
17626 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17627 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17628 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17629 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17632 branch_island_list = 0;
17635 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17636 already there or not. */
17639 no_previous_def (tree function_name)
17641 tree branch_island;
17642 for (branch_island = branch_island_list;
17644 branch_island = TREE_CHAIN (branch_island))
17645 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17650 /* GET_PREV_LABEL gets the label name from the previous definition of
17654 get_prev_label (tree function_name)
17656 tree branch_island;
17657 for (branch_island = branch_island_list;
17659 branch_island = TREE_CHAIN (branch_island))
17660 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17661 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17665 /* INSN is either a function call or a millicode call. It may have an
17666 unconditional jump in its delay slot.
17668 CALL_DEST is the routine we are calling. */
17671 output_call (rtx insn, rtx *operands, int dest_operand_number,
17672 int cookie_operand_number)
17674 static char buf[256];
17675 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17676 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17679 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17681 if (no_previous_def (funname))
17683 int line_number = 0;
17684 rtx label_rtx = gen_label_rtx ();
17685 char *label_buf, temp_buf[256];
17686 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17687 CODE_LABEL_NUMBER (label_rtx));
17688 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17689 labelname = get_identifier (label_buf);
17690 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17692 line_number = NOTE_LINE_NUMBER (insn);
17693 add_compiler_branch_island (labelname, funname, line_number);
17696 labelname = get_prev_label (funname);
17698 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17699 instruction will reach 'foo', otherwise link as 'bl L42'".
17700 "L42" should be a 'branch island', that will do a far jump to
17701 'foo'. Branch islands are generated in
17702 macho_branch_islands(). */
17703 sprintf (buf, "jbsr %%z%d,%.246s",
17704 dest_operand_number, IDENTIFIER_POINTER (labelname));
17707 sprintf (buf, "bl %%z%d", dest_operand_number);
17711 /* Generate PIC and indirect symbol stubs. */
17714 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17716 unsigned int length;
17717 char *symbol_name, *lazy_ptr_name;
17718 char *local_label_0;
17719 static int label = 0;
17721 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17722 symb = (*targetm.strip_name_encoding) (symb);
17725 length = strlen (symb);
17726 symbol_name = alloca (length + 32);
17727 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17729 lazy_ptr_name = alloca (length + 32);
17730 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17733 switch_to_section (machopic_picsymbol_stub1_section);
17735 switch_to_section (machopic_symbol_stub1_section);
17739 fprintf (file, "\t.align 5\n");
17741 fprintf (file, "%s:\n", stub);
17742 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17745 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17746 sprintf (local_label_0, "\"L%011d$spb\"", label);
17748 fprintf (file, "\tmflr r0\n");
17749 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17750 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17751 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17752 lazy_ptr_name, local_label_0);
17753 fprintf (file, "\tmtlr r0\n");
17754 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17755 (TARGET_64BIT ? "ldu" : "lwzu"),
17756 lazy_ptr_name, local_label_0);
17757 fprintf (file, "\tmtctr r12\n");
17758 fprintf (file, "\tbctr\n");
17762 fprintf (file, "\t.align 4\n");
17764 fprintf (file, "%s:\n", stub);
17765 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17767 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17768 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17769 (TARGET_64BIT ? "ldu" : "lwzu"),
17771 fprintf (file, "\tmtctr r12\n");
17772 fprintf (file, "\tbctr\n");
17775 switch_to_section (machopic_lazy_symbol_ptr_section);
17776 fprintf (file, "%s:\n", lazy_ptr_name);
17777 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17778 fprintf (file, "%sdyld_stub_binding_helper\n",
17779 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17782 /* Legitimize PIC addresses. If the address is already
17783 position-independent, we return ORIG. Newly generated
17784 position-independent addresses go into a reg. This is REG if non
17785 zero, otherwise we allocate register(s) as necessary. */
17787 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17790 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17795 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17796 reg = gen_reg_rtx (Pmode);
17798 if (GET_CODE (orig) == CONST)
17802 if (GET_CODE (XEXP (orig, 0)) == PLUS
17803 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17806 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17808 /* Use a different reg for the intermediate value, as
17809 it will be marked UNCHANGING. */
17810 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17811 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17814 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17817 if (GET_CODE (offset) == CONST_INT)
17819 if (SMALL_INT (offset))
17820 return plus_constant (base, INTVAL (offset));
17821 else if (! reload_in_progress && ! reload_completed)
17822 offset = force_reg (Pmode, offset);
17825 rtx mem = force_const_mem (Pmode, orig);
17826 return machopic_legitimize_pic_address (mem, Pmode, reg);
17829 return gen_rtx_PLUS (Pmode, base, offset);
17832 /* Fall back on generic machopic code. */
17833 return machopic_legitimize_pic_address (orig, mode, reg);
17836 /* Output a .machine directive for the Darwin assembler, and call
17837 the generic start_file routine. */
17840 rs6000_darwin_file_start (void)
17842 static const struct
17848 { "ppc64", "ppc64", MASK_64BIT },
17849 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17850 { "power4", "ppc970", 0 },
17851 { "G5", "ppc970", 0 },
17852 { "7450", "ppc7450", 0 },
17853 { "7400", "ppc7400", MASK_ALTIVEC },
17854 { "G4", "ppc7400", 0 },
17855 { "750", "ppc750", 0 },
17856 { "740", "ppc750", 0 },
17857 { "G3", "ppc750", 0 },
17858 { "604e", "ppc604e", 0 },
17859 { "604", "ppc604", 0 },
17860 { "603e", "ppc603", 0 },
17861 { "603", "ppc603", 0 },
17862 { "601", "ppc601", 0 },
17863 { NULL, "ppc", 0 } };
17864 const char *cpu_id = "";
17867 rs6000_file_start ();
17869 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17870 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17871 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17872 && rs6000_select[i].string[0] != '\0')
17873 cpu_id = rs6000_select[i].string;
17875 /* Look through the mapping array. Pick the first name that either
17876 matches the argument, has a bit set in IF_SET that is also set
17877 in the target flags, or has a NULL name. */
17880 while (mapping[i].arg != NULL
17881 && strcmp (mapping[i].arg, cpu_id) != 0
17882 && (mapping[i].if_set & target_flags) == 0)
17885 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17888 #endif /* TARGET_MACHO */
17891 static unsigned int
17892 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17894 return default_section_type_flags_1 (decl, name, reloc,
17895 flag_pic || DEFAULT_ABI == ABI_AIX);
17898 /* Record an element in the table of global constructors. SYMBOL is
17899 a SYMBOL_REF of the function to be called; PRIORITY is a number
17900 between 0 and MAX_INIT_PRIORITY.
17902 This differs from default_named_section_asm_out_constructor in
17903 that we have special handling for -mrelocatable. */
17906 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17908 const char *section = ".ctors";
17911 if (priority != DEFAULT_INIT_PRIORITY)
17913 sprintf (buf, ".ctors.%.5u",
17914 /* Invert the numbering so the linker puts us in the proper
17915 order; constructors are run from right to left, and the
17916 linker sorts in increasing order. */
17917 MAX_INIT_PRIORITY - priority);
17921 switch_to_section (get_section (section, SECTION_WRITE, NULL));
17922 assemble_align (POINTER_SIZE);
17924 if (TARGET_RELOCATABLE)
17926 fputs ("\t.long (", asm_out_file);
17927 output_addr_const (asm_out_file, symbol);
17928 fputs (")@fixup\n", asm_out_file);
17931 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17935 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17937 const char *section = ".dtors";
17940 if (priority != DEFAULT_INIT_PRIORITY)
17942 sprintf (buf, ".dtors.%.5u",
17943 /* Invert the numbering so the linker puts us in the proper
17944 order; constructors are run from right to left, and the
17945 linker sorts in increasing order. */
17946 MAX_INIT_PRIORITY - priority);
17950 switch_to_section (get_section (section, SECTION_WRITE, NULL));
17951 assemble_align (POINTER_SIZE);
17953 if (TARGET_RELOCATABLE)
17955 fputs ("\t.long (", asm_out_file);
17956 output_addr_const (asm_out_file, symbol);
17957 fputs (")@fixup\n", asm_out_file);
17960 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17964 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17968 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17969 ASM_OUTPUT_LABEL (file, name);
17970 fputs (DOUBLE_INT_ASM_OP, file);
17971 rs6000_output_function_entry (file, name);
17972 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17975 fputs ("\t.size\t", file);
17976 assemble_name (file, name);
17977 fputs (",24\n\t.type\t.", file);
17978 assemble_name (file, name);
17979 fputs (",@function\n", file);
17980 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17982 fputs ("\t.globl\t.", file);
17983 assemble_name (file, name);
17988 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17989 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17990 rs6000_output_function_entry (file, name);
17991 fputs (":\n", file);
17995 if (TARGET_RELOCATABLE
17996 && !TARGET_SECURE_PLT
17997 && (get_pool_size () != 0 || current_function_profile)
18002 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18004 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18005 fprintf (file, "\t.long ");
18006 assemble_name (file, buf);
18008 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18009 assemble_name (file, buf);
18013 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18014 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18016 if (DEFAULT_ABI == ABI_AIX)
18018 const char *desc_name, *orig_name;
18020 orig_name = (*targetm.strip_name_encoding) (name);
18021 desc_name = orig_name;
18022 while (*desc_name == '.')
18025 if (TREE_PUBLIC (decl))
18026 fprintf (file, "\t.globl %s\n", desc_name);
18028 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18029 fprintf (file, "%s:\n", desc_name);
18030 fprintf (file, "\t.long %s\n", orig_name);
18031 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18032 if (DEFAULT_ABI == ABI_AIX)
18033 fputs ("\t.long 0\n", file);
18034 fprintf (file, "\t.previous\n");
18036 ASM_OUTPUT_LABEL (file, name);
18040 rs6000_elf_end_indicate_exec_stack (void)
18043 file_end_indicate_exec_stack ();
18049 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18051 fputs (GLOBAL_ASM_OP, stream);
18052 RS6000_OUTPUT_BASENAME (stream, name);
18053 putc ('\n', stream);
18056 /* A get_unnamed_decl callback, used for read-only sections. PTR
18057 points to the section string variable. */
18060 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18062 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18063 *(const char *const *) directive);
18066 /* Likewise for read-write sections. */
18069 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18071 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18072 *(const char *const *) directive);
18075 /* A get_unnamed_section callback, used for switching to toc_section. */
18078 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18080 if (TARGET_MINIMAL_TOC)
18082 /* toc_section is always selected at least once from
18083 rs6000_xcoff_file_start, so this is guaranteed to
18084 always be defined once and only once in each file. */
18085 if (!toc_initialized)
18087 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18088 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18089 toc_initialized = 1;
18091 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18092 (TARGET_32BIT ? "" : ",3"));
18095 fputs ("\t.toc\n", asm_out_file);
18098 /* Implement TARGET_ASM_INIT_SECTIONS. */
18101 rs6000_xcoff_asm_init_sections (void)
18103 read_only_data_section
18104 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18105 &xcoff_read_only_section_name);
18107 private_data_section
18108 = get_unnamed_section (SECTION_WRITE,
18109 rs6000_xcoff_output_readwrite_section_asm_op,
18110 &xcoff_private_data_section_name);
18112 read_only_private_data_section
18113 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18114 &xcoff_private_data_section_name);
18117 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18119 readonly_data_section = read_only_data_section;
18120 exception_section = data_section;
18124 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18125 tree decl ATTRIBUTE_UNUSED)
18128 static const char * const suffix[3] = { "PR", "RO", "RW" };
18130 if (flags & SECTION_CODE)
18132 else if (flags & SECTION_WRITE)
18137 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18138 (flags & SECTION_CODE) ? "." : "",
18139 name, suffix[smclass], flags & SECTION_ENTSIZE);
18143 rs6000_xcoff_select_section (tree decl, int reloc,
18144 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18146 if (decl_readonly_section_1 (decl, reloc, 1))
18148 if (TREE_PUBLIC (decl))
18149 return read_only_data_section;
18151 return read_only_private_data_section;
18155 if (TREE_PUBLIC (decl))
18156 return data_section;
18158 return private_data_section;
18163 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18167 /* Use select_section for private and uninitialized data. */
18168 if (!TREE_PUBLIC (decl)
18169 || DECL_COMMON (decl)
18170 || DECL_INITIAL (decl) == NULL_TREE
18171 || DECL_INITIAL (decl) == error_mark_node
18172 || (flag_zero_initialized_in_bss
18173 && initializer_zerop (DECL_INITIAL (decl))))
18176 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18177 name = (*targetm.strip_name_encoding) (name);
18178 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18181 /* Select section for constant in constant pool.
18183 On RS/6000, all constants are in the private read-only data area.
18184 However, if this is being placed in the TOC it must be output as a
18188 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18189 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18191 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18192 return toc_section;
18194 return read_only_private_data_section;
18197 /* Remove any trailing [DS] or the like from the symbol name. */
18199 static const char *
18200 rs6000_xcoff_strip_name_encoding (const char *name)
18205 len = strlen (name);
18206 if (name[len - 1] == ']')
18207 return ggc_alloc_string (name, len - 4);
18212 /* Section attributes. AIX is always PIC. */
18214 static unsigned int
18215 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18217 unsigned int align;
18218 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18220 /* Align to at least UNIT size. */
18221 if (flags & SECTION_CODE)
18222 align = MIN_UNITS_PER_WORD;
18224 /* Increase alignment of large objects if not already stricter. */
18225 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18226 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18227 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18229 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18232 /* Output at beginning of assembler file.
18234 Initialize the section names for the RS/6000 at this point.
18236 Specify filename, including full path, to assembler.
18238 We want to go into the TOC section so at least one .toc will be emitted.
18239 Also, in order to output proper .bs/.es pairs, we need at least one static
18240 [RW] section emitted.
18242 Finally, declare mcount when profiling to make the assembler happy. */
18245 rs6000_xcoff_file_start (void)
18247 rs6000_gen_section_name (&xcoff_bss_section_name,
18248 main_input_filename, ".bss_");
18249 rs6000_gen_section_name (&xcoff_private_data_section_name,
18250 main_input_filename, ".rw_");
18251 rs6000_gen_section_name (&xcoff_read_only_section_name,
18252 main_input_filename, ".ro_");
18254 fputs ("\t.file\t", asm_out_file);
18255 output_quoted_string (asm_out_file, main_input_filename);
18256 fputc ('\n', asm_out_file);
18257 if (write_symbols != NO_DEBUG)
18258 switch_to_section (private_data_section);
18259 switch_to_section (text_section);
18261 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18262 rs6000_file_start ();
18265 /* Output at end of assembler file.
18266 On the RS/6000, referencing data should automatically pull in text. */
18269 rs6000_xcoff_file_end (void)
18271 switch_to_section (text_section);
18272 fputs ("_section_.text:\n", asm_out_file);
18273 switch_to_section (data_section);
18274 fputs (TARGET_32BIT
18275 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18278 #endif /* TARGET_XCOFF */
18280 /* Compute a (partial) cost for rtx X. Return true if the complete
18281 cost has been computed, and false if subexpressions should be
18282 scanned. In either case, *TOTAL contains the cost result. */
18285 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18287 enum machine_mode mode = GET_MODE (x);
18291 /* On the RS/6000, if it is valid in the insn, it is free. */
18293 if (((outer_code == SET
18294 || outer_code == PLUS
18295 || outer_code == MINUS)
18296 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18297 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18298 || (outer_code == AND
18299 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18300 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18301 mode == SImode ? 'L' : 'J'))
18302 || mask_operand (x, mode)
18304 && mask64_operand (x, DImode))))
18305 || ((outer_code == IOR || outer_code == XOR)
18306 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18307 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18308 mode == SImode ? 'L' : 'J'))))
18309 || outer_code == ASHIFT
18310 || outer_code == ASHIFTRT
18311 || outer_code == LSHIFTRT
18312 || outer_code == ROTATE
18313 || outer_code == ROTATERT
18314 || outer_code == ZERO_EXTRACT
18315 || (outer_code == MULT
18316 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18317 || ((outer_code == DIV || outer_code == UDIV
18318 || outer_code == MOD || outer_code == UMOD)
18319 && exact_log2 (INTVAL (x)) >= 0)
18320 || (outer_code == COMPARE
18321 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18322 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18323 || (outer_code == EQ
18324 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18325 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18326 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18327 mode == SImode ? 'L' : 'J'))))
18328 || (outer_code == GTU
18329 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18330 || (outer_code == LTU
18331 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18336 else if ((outer_code == PLUS
18337 && reg_or_add_cint_operand (x, VOIDmode))
18338 || (outer_code == MINUS
18339 && reg_or_sub_cint_operand (x, VOIDmode))
18340 || ((outer_code == SET
18341 || outer_code == IOR
18342 || outer_code == XOR)
18344 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18346 *total = COSTS_N_INSNS (1);
18353 && ((outer_code == AND
18354 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18355 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18356 || mask_operand (x, DImode)
18357 || mask64_operand (x, DImode)))
18358 || ((outer_code == IOR || outer_code == XOR)
18359 && CONST_DOUBLE_HIGH (x) == 0
18360 && (CONST_DOUBLE_LOW (x)
18361 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18366 else if (mode == DImode
18367 && (outer_code == SET
18368 || outer_code == IOR
18369 || outer_code == XOR)
18370 && CONST_DOUBLE_HIGH (x) == 0)
18372 *total = COSTS_N_INSNS (1);
18381 /* When optimizing for size, MEM should be slightly more expensive
18382 than generating address, e.g., (plus (reg) (const)).
18383 L1 cache latency is about two instructions. */
18384 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18392 if (mode == DFmode)
18394 if (GET_CODE (XEXP (x, 0)) == MULT)
18396 /* FNMA accounted in outer NEG. */
18397 if (outer_code == NEG)
18398 *total = rs6000_cost->dmul - rs6000_cost->fp;
18400 *total = rs6000_cost->dmul;
18403 *total = rs6000_cost->fp;
18405 else if (mode == SFmode)
18407 /* FNMA accounted in outer NEG. */
18408 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18411 *total = rs6000_cost->fp;
18414 *total = COSTS_N_INSNS (1);
18418 if (mode == DFmode)
18420 if (GET_CODE (XEXP (x, 0)) == MULT)
18422 /* FNMA accounted in outer NEG. */
18423 if (outer_code == NEG)
18426 *total = rs6000_cost->dmul;
18429 *total = rs6000_cost->fp;
18431 else if (mode == SFmode)
18433 /* FNMA accounted in outer NEG. */
18434 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18437 *total = rs6000_cost->fp;
18440 *total = COSTS_N_INSNS (1);
18444 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18445 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18447 if (INTVAL (XEXP (x, 1)) >= -256
18448 && INTVAL (XEXP (x, 1)) <= 255)
18449 *total = rs6000_cost->mulsi_const9;
18451 *total = rs6000_cost->mulsi_const;
18453 /* FMA accounted in outer PLUS/MINUS. */
18454 else if ((mode == DFmode || mode == SFmode)
18455 && (outer_code == PLUS || outer_code == MINUS))
18457 else if (mode == DFmode)
18458 *total = rs6000_cost->dmul;
18459 else if (mode == SFmode)
18460 *total = rs6000_cost->fp;
18461 else if (mode == DImode)
18462 *total = rs6000_cost->muldi;
18464 *total = rs6000_cost->mulsi;
18469 if (FLOAT_MODE_P (mode))
18471 *total = mode == DFmode ? rs6000_cost->ddiv
18472 : rs6000_cost->sdiv;
18479 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18480 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18482 if (code == DIV || code == MOD)
18484 *total = COSTS_N_INSNS (2);
18487 *total = COSTS_N_INSNS (1);
18491 if (GET_MODE (XEXP (x, 1)) == DImode)
18492 *total = rs6000_cost->divdi;
18494 *total = rs6000_cost->divsi;
18496 /* Add in shift and subtract for MOD. */
18497 if (code == MOD || code == UMOD)
18498 *total += COSTS_N_INSNS (2);
18502 *total = COSTS_N_INSNS (4);
18506 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18517 *total = COSTS_N_INSNS (1);
18525 /* Handle mul_highpart. */
18526 if (outer_code == TRUNCATE
18527 && GET_CODE (XEXP (x, 0)) == MULT)
18529 if (mode == DImode)
18530 *total = rs6000_cost->muldi;
18532 *total = rs6000_cost->mulsi;
18535 else if (outer_code == AND)
18538 *total = COSTS_N_INSNS (1);
18543 if (GET_CODE (XEXP (x, 0)) == MEM)
18546 *total = COSTS_N_INSNS (1);
18552 if (!FLOAT_MODE_P (mode))
18554 *total = COSTS_N_INSNS (1);
18560 case UNSIGNED_FLOAT:
18563 case FLOAT_TRUNCATE:
18564 *total = rs6000_cost->fp;
18568 if (mode == DFmode)
18571 *total = rs6000_cost->fp;
18575 switch (XINT (x, 1))
18578 *total = rs6000_cost->fp;
18590 *total = COSTS_N_INSNS (1);
18593 else if (FLOAT_MODE_P (mode)
18594 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18596 *total = rs6000_cost->fp;
18604 /* Carry bit requires mode == Pmode.
18605 NEG or PLUS already counted so only add one. */
18607 && (outer_code == NEG || outer_code == PLUS))
18609 *total = COSTS_N_INSNS (1);
18612 if (outer_code == SET)
18614 if (XEXP (x, 1) == const0_rtx)
18616 *total = COSTS_N_INSNS (2);
18619 else if (mode == Pmode)
18621 *total = COSTS_N_INSNS (3);
18630 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18632 *total = COSTS_N_INSNS (2);
18636 if (outer_code == COMPARE)
18650 /* A C expression returning the cost of moving data from a register of class
18651 CLASS1 to one of CLASS2. */
18654 rs6000_register_move_cost (enum machine_mode mode,
18655 enum reg_class from, enum reg_class to)
18657 /* Moves from/to GENERAL_REGS. */
18658 if (reg_classes_intersect_p (to, GENERAL_REGS)
18659 || reg_classes_intersect_p (from, GENERAL_REGS))
18661 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18664 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18665 return (rs6000_memory_move_cost (mode, from, 0)
18666 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18668 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18670 else if (from == CR_REGS)
18674 /* A move will cost one instruction per GPR moved. */
18675 return 2 * hard_regno_nregs[0][mode];
18678 /* Moving between two similar registers is just one instruction. */
18679 else if (reg_classes_intersect_p (to, from))
18680 return mode == TFmode ? 4 : 2;
18682 /* Everything else has to go through GENERAL_REGS. */
18684 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18685 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18688 /* A C expressions returning the cost of moving data of MODE from a register to
18692 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18693 int in ATTRIBUTE_UNUSED)
18695 if (reg_classes_intersect_p (class, GENERAL_REGS))
18696 return 4 * hard_regno_nregs[0][mode];
18697 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18698 return 4 * hard_regno_nregs[32][mode];
18699 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18700 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18702 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18705 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18706 Assumes no trapping math and finite arguments. */
18709 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18711 rtx x0, e0, e1, y1, u0, v0, one;
18713 x0 = gen_reg_rtx (SFmode);
18714 e0 = gen_reg_rtx (SFmode);
18715 e1 = gen_reg_rtx (SFmode);
18716 y1 = gen_reg_rtx (SFmode);
18717 u0 = gen_reg_rtx (SFmode);
18718 v0 = gen_reg_rtx (SFmode);
18719 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18721 /* x0 = 1./d estimate */
18722 emit_insn (gen_rtx_SET (VOIDmode, x0,
18723 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18725 /* e0 = 1. - d * x0 */
18726 emit_insn (gen_rtx_SET (VOIDmode, e0,
18727 gen_rtx_MINUS (SFmode, one,
18728 gen_rtx_MULT (SFmode, d, x0))));
18729 /* e1 = e0 + e0 * e0 */
18730 emit_insn (gen_rtx_SET (VOIDmode, e1,
18731 gen_rtx_PLUS (SFmode,
18732 gen_rtx_MULT (SFmode, e0, e0), e0)));
18733 /* y1 = x0 + e1 * x0 */
18734 emit_insn (gen_rtx_SET (VOIDmode, y1,
18735 gen_rtx_PLUS (SFmode,
18736 gen_rtx_MULT (SFmode, e1, x0), x0)));
18738 emit_insn (gen_rtx_SET (VOIDmode, u0,
18739 gen_rtx_MULT (SFmode, n, y1)));
18740 /* v0 = n - d * u0 */
18741 emit_insn (gen_rtx_SET (VOIDmode, v0,
18742 gen_rtx_MINUS (SFmode, n,
18743 gen_rtx_MULT (SFmode, d, u0))));
18744 /* res = u0 + v0 * y1 */
18745 emit_insn (gen_rtx_SET (VOIDmode, res,
18746 gen_rtx_PLUS (SFmode,
18747 gen_rtx_MULT (SFmode, v0, y1), u0)));
18750 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18751 Assumes no trapping math and finite arguments. */
18754 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18756 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18758 x0 = gen_reg_rtx (DFmode);
18759 e0 = gen_reg_rtx (DFmode);
18760 e1 = gen_reg_rtx (DFmode);
18761 e2 = gen_reg_rtx (DFmode);
18762 y1 = gen_reg_rtx (DFmode);
18763 y2 = gen_reg_rtx (DFmode);
18764 y3 = gen_reg_rtx (DFmode);
18765 u0 = gen_reg_rtx (DFmode);
18766 v0 = gen_reg_rtx (DFmode);
18767 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18769 /* x0 = 1./d estimate */
18770 emit_insn (gen_rtx_SET (VOIDmode, x0,
18771 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18773 /* e0 = 1. - d * x0 */
18774 emit_insn (gen_rtx_SET (VOIDmode, e0,
18775 gen_rtx_MINUS (DFmode, one,
18776 gen_rtx_MULT (SFmode, d, x0))));
18777 /* y1 = x0 + e0 * x0 */
18778 emit_insn (gen_rtx_SET (VOIDmode, y1,
18779 gen_rtx_PLUS (DFmode,
18780 gen_rtx_MULT (DFmode, e0, x0), x0)));
18782 emit_insn (gen_rtx_SET (VOIDmode, e1,
18783 gen_rtx_MULT (DFmode, e0, e0)));
18784 /* y2 = y1 + e1 * y1 */
18785 emit_insn (gen_rtx_SET (VOIDmode, y2,
18786 gen_rtx_PLUS (DFmode,
18787 gen_rtx_MULT (DFmode, e1, y1), y1)));
18789 emit_insn (gen_rtx_SET (VOIDmode, e2,
18790 gen_rtx_MULT (DFmode, e1, e1)));
18791 /* y3 = y2 + e2 * y2 */
18792 emit_insn (gen_rtx_SET (VOIDmode, y3,
18793 gen_rtx_PLUS (DFmode,
18794 gen_rtx_MULT (DFmode, e2, y2), y2)));
18796 emit_insn (gen_rtx_SET (VOIDmode, u0,
18797 gen_rtx_MULT (DFmode, n, y3)));
18798 /* v0 = n - d * u0 */
18799 emit_insn (gen_rtx_SET (VOIDmode, v0,
18800 gen_rtx_MINUS (DFmode, n,
18801 gen_rtx_MULT (DFmode, d, u0))));
18802 /* res = u0 + v0 * y3 */
18803 emit_insn (gen_rtx_SET (VOIDmode, res,
18804 gen_rtx_PLUS (DFmode,
18805 gen_rtx_MULT (DFmode, v0, y3), u0)));
18808 /* Return an RTX representing where to find the function value of a
18809 function returning MODE. */
18811 rs6000_complex_function_value (enum machine_mode mode)
18813 unsigned int regno;
18815 enum machine_mode inner = GET_MODE_INNER (mode);
18816 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18818 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18819 regno = FP_ARG_RETURN;
18822 regno = GP_ARG_RETURN;
18824 /* 32-bit is OK since it'll go in r3/r4. */
18825 if (TARGET_32BIT && inner_bytes >= 4)
18826 return gen_rtx_REG (mode, regno);
18829 if (inner_bytes >= 8)
18830 return gen_rtx_REG (mode, regno);
18832 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18834 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18835 GEN_INT (inner_bytes));
18836 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18839 /* Define how to find the value returned by a function.
18840 VALTYPE is the data type of the value (as a tree).
18841 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18842 otherwise, FUNC is 0.
18844 On the SPE, both FPs and vectors are returned in r3.
18846 On RS/6000 an integer value is in r3 and a floating-point value is in
18847 fp1, unless -msoft-float. */
18850 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18852 enum machine_mode mode;
18853 unsigned int regno;
18855 /* Special handling for structs in darwin64. */
18856 if (rs6000_darwin64_abi
18857 && TYPE_MODE (valtype) == BLKmode
18858 && TREE_CODE (valtype) == RECORD_TYPE
18859 && int_size_in_bytes (valtype) > 0)
18861 CUMULATIVE_ARGS valcum;
18865 valcum.fregno = FP_ARG_MIN_REG;
18866 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18867 /* Do a trial code generation as if this were going to be passed as
18868 an argument; if any part goes in memory, we return NULL. */
18869 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
18872 /* Otherwise fall through to standard ABI rules. */
18875 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18877 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18878 return gen_rtx_PARALLEL (DImode,
18880 gen_rtx_EXPR_LIST (VOIDmode,
18881 gen_rtx_REG (SImode, GP_ARG_RETURN),
18883 gen_rtx_EXPR_LIST (VOIDmode,
18884 gen_rtx_REG (SImode,
18885 GP_ARG_RETURN + 1),
18888 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
18890 return gen_rtx_PARALLEL (DCmode,
18892 gen_rtx_EXPR_LIST (VOIDmode,
18893 gen_rtx_REG (SImode, GP_ARG_RETURN),
18895 gen_rtx_EXPR_LIST (VOIDmode,
18896 gen_rtx_REG (SImode,
18897 GP_ARG_RETURN + 1),
18899 gen_rtx_EXPR_LIST (VOIDmode,
18900 gen_rtx_REG (SImode,
18901 GP_ARG_RETURN + 2),
18903 gen_rtx_EXPR_LIST (VOIDmode,
18904 gen_rtx_REG (SImode,
18905 GP_ARG_RETURN + 3),
18908 if ((INTEGRAL_TYPE_P (valtype)
18909 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18910 || POINTER_TYPE_P (valtype))
18911 mode = TARGET_32BIT ? SImode : DImode;
18913 mode = TYPE_MODE (valtype);
18915 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18916 regno = FP_ARG_RETURN;
18917 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18918 && targetm.calls.split_complex_arg)
18919 return rs6000_complex_function_value (mode);
18920 else if (TREE_CODE (valtype) == VECTOR_TYPE
18921 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18922 && ALTIVEC_VECTOR_MODE (mode))
18923 regno = ALTIVEC_ARG_RETURN;
18924 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18925 && (mode == DFmode || mode == DCmode))
18926 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18928 regno = GP_ARG_RETURN;
18930 return gen_rtx_REG (mode, regno);
18933 /* Define how to find the value returned by a library function
18934 assuming the value has mode MODE. */
18936 rs6000_libcall_value (enum machine_mode mode)
18938 unsigned int regno;
18940 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18942 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18943 return gen_rtx_PARALLEL (DImode,
18945 gen_rtx_EXPR_LIST (VOIDmode,
18946 gen_rtx_REG (SImode, GP_ARG_RETURN),
18948 gen_rtx_EXPR_LIST (VOIDmode,
18949 gen_rtx_REG (SImode,
18950 GP_ARG_RETURN + 1),
18954 if (SCALAR_FLOAT_MODE_P (mode)
18955 && TARGET_HARD_FLOAT && TARGET_FPRS)
18956 regno = FP_ARG_RETURN;
18957 else if (ALTIVEC_VECTOR_MODE (mode)
18958 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18959 regno = ALTIVEC_ARG_RETURN;
18960 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18961 return rs6000_complex_function_value (mode);
18962 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18963 && (mode == DFmode || mode == DCmode))
18964 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18966 regno = GP_ARG_RETURN;
18968 return gen_rtx_REG (mode, regno);
18971 /* Define the offset between two registers, FROM to be eliminated and its
18972 replacement TO, at the start of a routine. */
18974 rs6000_initial_elimination_offset (int from, int to)
18976 rs6000_stack_t *info = rs6000_stack_info ();
18977 HOST_WIDE_INT offset;
18979 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18980 offset = info->push_p ? 0 : -info->total_size;
18981 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18983 offset = info->push_p ? 0 : -info->total_size;
18984 if (FRAME_GROWS_DOWNWARD)
18985 offset += info->fixed_size + info->vars_size + info->parm_size;
18987 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18988 offset = FRAME_GROWS_DOWNWARD
18989 ? info->fixed_size + info->vars_size + info->parm_size
18991 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18992 offset = info->total_size;
18993 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18994 offset = info->push_p ? info->total_size : 0;
18995 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18998 gcc_unreachable ();
19003 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19006 rs6000_is_opaque_type (tree type)
19008 return (type == opaque_V2SI_type_node
19009 || type == opaque_V2SF_type_node
19010 || type == opaque_p_V2SI_type_node
19011 || type == opaque_V4SI_type_node);
19015 rs6000_dwarf_register_span (rtx reg)
19020 && (SPE_VECTOR_MODE (GET_MODE (reg))
19021 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19026 regno = REGNO (reg);
19028 /* The duality of the SPE register size wreaks all kinds of havoc.
19029 This is a way of distinguishing r0 in 32-bits from r0 in
19032 gen_rtx_PARALLEL (VOIDmode,
19035 gen_rtx_REG (SImode, regno + 1200),
19036 gen_rtx_REG (SImode, regno))
19038 gen_rtx_REG (SImode, regno),
19039 gen_rtx_REG (SImode, regno + 1200)));
19042 /* Map internal gcc register numbers to DWARF2 register numbers. */
19045 rs6000_dbx_register_number (unsigned int regno)
19047 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19049 if (regno == MQ_REGNO)
19051 if (regno == LINK_REGISTER_REGNUM)
19053 if (regno == COUNT_REGISTER_REGNUM)
19055 if (CR_REGNO_P (regno))
19056 return regno - CR0_REGNO + 86;
19057 if (regno == XER_REGNO)
19059 if (ALTIVEC_REGNO_P (regno))
19060 return regno - FIRST_ALTIVEC_REGNO + 1124;
19061 if (regno == VRSAVE_REGNO)
19063 if (regno == VSCR_REGNO)
19065 if (regno == SPE_ACC_REGNO)
19067 if (regno == SPEFSCR_REGNO)
19069 /* SPE high reg number. We get these values of regno from
19070 rs6000_dwarf_register_span. */
19071 gcc_assert (regno >= 1200 && regno < 1232);
19075 /* target hook eh_return_filter_mode */
19076 static enum machine_mode
19077 rs6000_eh_return_filter_mode (void)
19079 return TARGET_32BIT ? SImode : word_mode;
19082 /* Target hook for vector_mode_supported_p. */
19084 rs6000_vector_mode_supported_p (enum machine_mode mode)
19087 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19090 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19097 /* Target hook for invalid_arg_for_unprototyped_fn. */
19098 static const char *
19099 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19101 return (!rs6000_darwin64_abi
19103 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19104 && (funcdecl == NULL_TREE
19105 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19106 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19107 ? N_("AltiVec argument passed to unprototyped function")
19111 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19112 setup by using __stack_chk_fail_local hidden function instead of
19113 calling __stack_chk_fail directly. Otherwise it is better to call
19114 __stack_chk_fail directly. */
19117 rs6000_stack_protect_fail (void)
19119 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19120 ? default_hidden_stack_protect_fail ()
19121 : default_external_stack_protect_fail ();
19124 #include "gt-rs6000.h"