1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 /* Always emit branch hint bits. */
143 static GTY(()) bool rs6000_always_hint;
145 /* Schedule instructions for group formation. */
146 static GTY(()) bool rs6000_sched_groups;
148 /* Support for -msched-costly-dep option. */
149 const char *rs6000_sched_costly_dep_str;
150 enum rs6000_dependence_cost rs6000_sched_costly_dep;
152 /* Support for -minsert-sched-nops option. */
153 const char *rs6000_sched_insert_nops_str;
154 enum rs6000_nop_insertion rs6000_sched_insert_nops;
156 /* Support targetm.vectorize.builtin_mask_for_load. */
157 static GTY(()) tree altivec_builtin_mask_for_load;
159 /* Size of long double. */
160 int rs6000_long_double_type_size;
162 /* IEEE quad extended precision long double. */
165 /* Whether -mabi=altivec has appeared. */
166 int rs6000_altivec_abi;
168 /* Nonzero if we want SPE ABI extensions. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
177 /* Set to nonzero once AIX common-mode calls have been defined. */
178 static GTY(()) int common_mode_defined;
180 /* Save information from a "cmpxx" operation until the branch or scc is
182 rtx rs6000_compare_op0, rs6000_compare_op1;
183 int rs6000_compare_fp_p;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 int rs6000_pic_labelno;
190 /* Which abi to adhere to */
191 const char *rs6000_abi_name;
193 /* Semantics of the small data area */
194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
196 /* Which small data model to use */
197 const char *rs6000_sdata_name = (char *)0;
199 /* Counter for labels which are to be placed in .fixup. */
200 int fixuplabelno = 0;
203 /* Bit size of immediate TLS offsets and string from which it is decoded. */
204 int rs6000_tls_size = 32;
205 const char *rs6000_tls_size_string;
207 /* ABI enumeration available for subtarget to use. */
208 enum rs6000_abi rs6000_current_abi;
210 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
214 const char *rs6000_debug_name;
215 int rs6000_debug_stack; /* debug stack applications */
216 int rs6000_debug_arg; /* debug argument handling */
218 /* Value is TRUE if register/mode pair is acceptable. */
219 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
221 /* Built in types. */
223 tree rs6000_builtin_types[RS6000_BTI_MAX];
224 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
226 const char *rs6000_traceback_name;
228 traceback_default = 0,
234 /* Flag to say the TOC is initialized */
236 char toc_label_name[10];
238 static GTY(()) section *read_only_data_section;
239 static GTY(()) section *private_data_section;
240 static GTY(()) section *read_only_private_data_section;
241 static GTY(()) section *sdata2_section;
242 static GTY(()) section *toc_section;
244 /* Control alignment for fields within structures. */
245 /* String from -malign-XXXXX. */
246 int rs6000_alignment_flags;
248 /* True for any options that were explicitly set. */
250 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
251 bool alignment; /* True if -malign- was used. */
252 bool abi; /* True if -mabi=spe/nospe was used. */
253 bool spe; /* True if -mspe= was used. */
254 bool float_gprs; /* True if -mfloat-gprs= was used. */
255 bool isel; /* True if -misel was used. */
256 bool long_double; /* True if -mlong-double- was used. */
257 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
258 } rs6000_explicit_options;
260 struct builtin_description
262 /* mask is not const because we're going to alter it below. This
263 nonsense will go away when we rewrite the -march infrastructure
264 to give us more target flag bits. */
266 const enum insn_code icode;
267 const char *const name;
268 const enum rs6000_builtins code;
271 /* Target cpu costs. */
273 struct processor_costs {
274 const int mulsi; /* cost of SImode multiplication. */
275 const int mulsi_const; /* cost of SImode multiplication by constant. */
276 const int mulsi_const9; /* cost of SImode mult by short constant. */
277 const int muldi; /* cost of DImode multiplication. */
278 const int divsi; /* cost of SImode division. */
279 const int divdi; /* cost of DImode division. */
280 const int fp; /* cost of simple SFmode and DFmode insns. */
281 const int dmul; /* cost of DFmode multiplication (and fmadd). */
282 const int sdiv; /* cost of SFmode division (fdivs). */
283 const int ddiv; /* cost of DFmode division (fdiv). */
286 const struct processor_costs *rs6000_cost;
288 /* Processor costs (relative to an add) */
290 /* Instruction size costs on 32bit processors. */
292 struct processor_costs size32_cost = {
293 COSTS_N_INSNS (1), /* mulsi */
294 COSTS_N_INSNS (1), /* mulsi_const */
295 COSTS_N_INSNS (1), /* mulsi_const9 */
296 COSTS_N_INSNS (1), /* muldi */
297 COSTS_N_INSNS (1), /* divsi */
298 COSTS_N_INSNS (1), /* divdi */
299 COSTS_N_INSNS (1), /* fp */
300 COSTS_N_INSNS (1), /* dmul */
301 COSTS_N_INSNS (1), /* sdiv */
302 COSTS_N_INSNS (1), /* ddiv */
305 /* Instruction size costs on 64bit processors. */
307 struct processor_costs size64_cost = {
308 COSTS_N_INSNS (1), /* mulsi */
309 COSTS_N_INSNS (1), /* mulsi_const */
310 COSTS_N_INSNS (1), /* mulsi_const9 */
311 COSTS_N_INSNS (1), /* muldi */
312 COSTS_N_INSNS (1), /* divsi */
313 COSTS_N_INSNS (1), /* divdi */
314 COSTS_N_INSNS (1), /* fp */
315 COSTS_N_INSNS (1), /* dmul */
316 COSTS_N_INSNS (1), /* sdiv */
317 COSTS_N_INSNS (1), /* ddiv */
320 /* Instruction costs on RIOS1 processors. */
322 struct processor_costs rios1_cost = {
323 COSTS_N_INSNS (5), /* mulsi */
324 COSTS_N_INSNS (4), /* mulsi_const */
325 COSTS_N_INSNS (3), /* mulsi_const9 */
326 COSTS_N_INSNS (5), /* muldi */
327 COSTS_N_INSNS (19), /* divsi */
328 COSTS_N_INSNS (19), /* divdi */
329 COSTS_N_INSNS (2), /* fp */
330 COSTS_N_INSNS (2), /* dmul */
331 COSTS_N_INSNS (19), /* sdiv */
332 COSTS_N_INSNS (19), /* ddiv */
335 /* Instruction costs on RIOS2 processors. */
337 struct processor_costs rios2_cost = {
338 COSTS_N_INSNS (2), /* mulsi */
339 COSTS_N_INSNS (2), /* mulsi_const */
340 COSTS_N_INSNS (2), /* mulsi_const9 */
341 COSTS_N_INSNS (2), /* muldi */
342 COSTS_N_INSNS (13), /* divsi */
343 COSTS_N_INSNS (13), /* divdi */
344 COSTS_N_INSNS (2), /* fp */
345 COSTS_N_INSNS (2), /* dmul */
346 COSTS_N_INSNS (17), /* sdiv */
347 COSTS_N_INSNS (17), /* ddiv */
350 /* Instruction costs on RS64A processors. */
352 struct processor_costs rs64a_cost = {
353 COSTS_N_INSNS (20), /* mulsi */
354 COSTS_N_INSNS (12), /* mulsi_const */
355 COSTS_N_INSNS (8), /* mulsi_const9 */
356 COSTS_N_INSNS (34), /* muldi */
357 COSTS_N_INSNS (65), /* divsi */
358 COSTS_N_INSNS (67), /* divdi */
359 COSTS_N_INSNS (4), /* fp */
360 COSTS_N_INSNS (4), /* dmul */
361 COSTS_N_INSNS (31), /* sdiv */
362 COSTS_N_INSNS (31), /* ddiv */
365 /* Instruction costs on MPCCORE processors. */
367 struct processor_costs mpccore_cost = {
368 COSTS_N_INSNS (2), /* mulsi */
369 COSTS_N_INSNS (2), /* mulsi_const */
370 COSTS_N_INSNS (2), /* mulsi_const9 */
371 COSTS_N_INSNS (2), /* muldi */
372 COSTS_N_INSNS (6), /* divsi */
373 COSTS_N_INSNS (6), /* divdi */
374 COSTS_N_INSNS (4), /* fp */
375 COSTS_N_INSNS (5), /* dmul */
376 COSTS_N_INSNS (10), /* sdiv */
377 COSTS_N_INSNS (17), /* ddiv */
380 /* Instruction costs on PPC403 processors. */
382 struct processor_costs ppc403_cost = {
383 COSTS_N_INSNS (4), /* mulsi */
384 COSTS_N_INSNS (4), /* mulsi_const */
385 COSTS_N_INSNS (4), /* mulsi_const9 */
386 COSTS_N_INSNS (4), /* muldi */
387 COSTS_N_INSNS (33), /* divsi */
388 COSTS_N_INSNS (33), /* divdi */
389 COSTS_N_INSNS (11), /* fp */
390 COSTS_N_INSNS (11), /* dmul */
391 COSTS_N_INSNS (11), /* sdiv */
392 COSTS_N_INSNS (11), /* ddiv */
395 /* Instruction costs on PPC405 processors. */
397 struct processor_costs ppc405_cost = {
398 COSTS_N_INSNS (5), /* mulsi */
399 COSTS_N_INSNS (4), /* mulsi_const */
400 COSTS_N_INSNS (3), /* mulsi_const9 */
401 COSTS_N_INSNS (5), /* muldi */
402 COSTS_N_INSNS (35), /* divsi */
403 COSTS_N_INSNS (35), /* divdi */
404 COSTS_N_INSNS (11), /* fp */
405 COSTS_N_INSNS (11), /* dmul */
406 COSTS_N_INSNS (11), /* sdiv */
407 COSTS_N_INSNS (11), /* ddiv */
410 /* Instruction costs on PPC440 processors. */
412 struct processor_costs ppc440_cost = {
413 COSTS_N_INSNS (3), /* mulsi */
414 COSTS_N_INSNS (2), /* mulsi_const */
415 COSTS_N_INSNS (2), /* mulsi_const9 */
416 COSTS_N_INSNS (3), /* muldi */
417 COSTS_N_INSNS (34), /* divsi */
418 COSTS_N_INSNS (34), /* divdi */
419 COSTS_N_INSNS (5), /* fp */
420 COSTS_N_INSNS (5), /* dmul */
421 COSTS_N_INSNS (19), /* sdiv */
422 COSTS_N_INSNS (33), /* ddiv */
425 /* Instruction costs on PPC601 processors. */
427 struct processor_costs ppc601_cost = {
428 COSTS_N_INSNS (5), /* mulsi */
429 COSTS_N_INSNS (5), /* mulsi_const */
430 COSTS_N_INSNS (5), /* mulsi_const9 */
431 COSTS_N_INSNS (5), /* muldi */
432 COSTS_N_INSNS (36), /* divsi */
433 COSTS_N_INSNS (36), /* divdi */
434 COSTS_N_INSNS (4), /* fp */
435 COSTS_N_INSNS (5), /* dmul */
436 COSTS_N_INSNS (17), /* sdiv */
437 COSTS_N_INSNS (31), /* ddiv */
440 /* Instruction costs on PPC603 processors. */
442 struct processor_costs ppc603_cost = {
443 COSTS_N_INSNS (5), /* mulsi */
444 COSTS_N_INSNS (3), /* mulsi_const */
445 COSTS_N_INSNS (2), /* mulsi_const9 */
446 COSTS_N_INSNS (5), /* muldi */
447 COSTS_N_INSNS (37), /* divsi */
448 COSTS_N_INSNS (37), /* divdi */
449 COSTS_N_INSNS (3), /* fp */
450 COSTS_N_INSNS (4), /* dmul */
451 COSTS_N_INSNS (18), /* sdiv */
452 COSTS_N_INSNS (33), /* ddiv */
455 /* Instruction costs on PPC604 processors. */
457 struct processor_costs ppc604_cost = {
458 COSTS_N_INSNS (4), /* mulsi */
459 COSTS_N_INSNS (4), /* mulsi_const */
460 COSTS_N_INSNS (4), /* mulsi_const9 */
461 COSTS_N_INSNS (4), /* muldi */
462 COSTS_N_INSNS (20), /* divsi */
463 COSTS_N_INSNS (20), /* divdi */
464 COSTS_N_INSNS (3), /* fp */
465 COSTS_N_INSNS (3), /* dmul */
466 COSTS_N_INSNS (18), /* sdiv */
467 COSTS_N_INSNS (32), /* ddiv */
470 /* Instruction costs on PPC604e processors. */
472 struct processor_costs ppc604e_cost = {
473 COSTS_N_INSNS (2), /* mulsi */
474 COSTS_N_INSNS (2), /* mulsi_const */
475 COSTS_N_INSNS (2), /* mulsi_const9 */
476 COSTS_N_INSNS (2), /* muldi */
477 COSTS_N_INSNS (20), /* divsi */
478 COSTS_N_INSNS (20), /* divdi */
479 COSTS_N_INSNS (3), /* fp */
480 COSTS_N_INSNS (3), /* dmul */
481 COSTS_N_INSNS (18), /* sdiv */
482 COSTS_N_INSNS (32), /* ddiv */
485 /* Instruction costs on PPC620 processors. */
487 struct processor_costs ppc620_cost = {
488 COSTS_N_INSNS (5), /* mulsi */
489 COSTS_N_INSNS (4), /* mulsi_const */
490 COSTS_N_INSNS (3), /* mulsi_const9 */
491 COSTS_N_INSNS (7), /* muldi */
492 COSTS_N_INSNS (21), /* divsi */
493 COSTS_N_INSNS (37), /* divdi */
494 COSTS_N_INSNS (3), /* fp */
495 COSTS_N_INSNS (3), /* dmul */
496 COSTS_N_INSNS (18), /* sdiv */
497 COSTS_N_INSNS (32), /* ddiv */
500 /* Instruction costs on PPC630 processors. */
502 struct processor_costs ppc630_cost = {
503 COSTS_N_INSNS (5), /* mulsi */
504 COSTS_N_INSNS (4), /* mulsi_const */
505 COSTS_N_INSNS (3), /* mulsi_const9 */
506 COSTS_N_INSNS (7), /* muldi */
507 COSTS_N_INSNS (21), /* divsi */
508 COSTS_N_INSNS (37), /* divdi */
509 COSTS_N_INSNS (3), /* fp */
510 COSTS_N_INSNS (3), /* dmul */
511 COSTS_N_INSNS (17), /* sdiv */
512 COSTS_N_INSNS (21), /* ddiv */
515 /* Instruction costs on PPC750 and PPC7400 processors. */
517 struct processor_costs ppc750_cost = {
518 COSTS_N_INSNS (5), /* mulsi */
519 COSTS_N_INSNS (3), /* mulsi_const */
520 COSTS_N_INSNS (2), /* mulsi_const9 */
521 COSTS_N_INSNS (5), /* muldi */
522 COSTS_N_INSNS (17), /* divsi */
523 COSTS_N_INSNS (17), /* divdi */
524 COSTS_N_INSNS (3), /* fp */
525 COSTS_N_INSNS (3), /* dmul */
526 COSTS_N_INSNS (17), /* sdiv */
527 COSTS_N_INSNS (31), /* ddiv */
530 /* Instruction costs on PPC7450 processors. */
532 struct processor_costs ppc7450_cost = {
533 COSTS_N_INSNS (4), /* mulsi */
534 COSTS_N_INSNS (3), /* mulsi_const */
535 COSTS_N_INSNS (3), /* mulsi_const9 */
536 COSTS_N_INSNS (4), /* muldi */
537 COSTS_N_INSNS (23), /* divsi */
538 COSTS_N_INSNS (23), /* divdi */
539 COSTS_N_INSNS (5), /* fp */
540 COSTS_N_INSNS (5), /* dmul */
541 COSTS_N_INSNS (21), /* sdiv */
542 COSTS_N_INSNS (35), /* ddiv */
545 /* Instruction costs on PPC8540 processors. */
547 struct processor_costs ppc8540_cost = {
548 COSTS_N_INSNS (4), /* mulsi */
549 COSTS_N_INSNS (4), /* mulsi_const */
550 COSTS_N_INSNS (4), /* mulsi_const9 */
551 COSTS_N_INSNS (4), /* muldi */
552 COSTS_N_INSNS (19), /* divsi */
553 COSTS_N_INSNS (19), /* divdi */
554 COSTS_N_INSNS (4), /* fp */
555 COSTS_N_INSNS (4), /* dmul */
556 COSTS_N_INSNS (29), /* sdiv */
557 COSTS_N_INSNS (29), /* ddiv */
560 /* Instruction costs on POWER4 and POWER5 processors. */
562 struct processor_costs power4_cost = {
563 COSTS_N_INSNS (3), /* mulsi */
564 COSTS_N_INSNS (2), /* mulsi_const */
565 COSTS_N_INSNS (2), /* mulsi_const9 */
566 COSTS_N_INSNS (4), /* muldi */
567 COSTS_N_INSNS (18), /* divsi */
568 COSTS_N_INSNS (34), /* divdi */
569 COSTS_N_INSNS (3), /* fp */
570 COSTS_N_INSNS (3), /* dmul */
571 COSTS_N_INSNS (17), /* sdiv */
572 COSTS_N_INSNS (17), /* ddiv */
576 static bool rs6000_function_ok_for_sibcall (tree, tree);
577 static const char *rs6000_invalid_within_doloop (rtx);
578 static rtx rs6000_generate_compare (enum rtx_code);
579 static void rs6000_maybe_dead (rtx);
580 static void rs6000_emit_stack_tie (void);
581 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
582 static rtx spe_synthesize_frame_save (rtx);
583 static bool spe_func_has_64bit_regs_p (void);
584 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
586 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
587 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
588 static unsigned rs6000_hash_constant (rtx);
589 static unsigned toc_hash_function (const void *);
590 static int toc_hash_eq (const void *, const void *);
591 static int constant_pool_expr_1 (rtx, int *, int *);
592 static bool constant_pool_expr_p (rtx);
593 static bool legitimate_small_data_p (enum machine_mode, rtx);
594 static bool legitimate_indexed_address_p (rtx, int);
595 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
596 static struct machine_function * rs6000_init_machine_status (void);
597 static bool rs6000_assemble_integer (rtx, unsigned int, int);
598 static bool no_global_regs_above (int);
599 #ifdef HAVE_GAS_HIDDEN
600 static void rs6000_assemble_visibility (tree, int);
602 static int rs6000_ra_ever_killed (void);
603 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
604 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
605 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
606 static const char *rs6000_mangle_fundamental_type (tree);
607 extern const struct attribute_spec rs6000_attribute_table[];
608 static void rs6000_set_default_type_attributes (tree);
609 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
610 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
611 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
613 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
614 static bool rs6000_return_in_memory (tree, tree);
615 static void rs6000_file_start (void);
617 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
618 static void rs6000_elf_asm_out_constructor (rtx, int);
619 static void rs6000_elf_asm_out_destructor (rtx, int);
620 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
621 static void rs6000_elf_asm_init_sections (void);
622 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
623 static void rs6000_elf_unique_section (tree, int);
624 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
625 unsigned HOST_WIDE_INT);
626 static void rs6000_elf_encode_section_info (tree, rtx, int)
629 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
631 static void rs6000_xcoff_asm_output_anchor (rtx);
632 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
633 static void rs6000_xcoff_asm_init_sections (void);
634 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
635 static section *rs6000_xcoff_select_section (tree, int,
636 unsigned HOST_WIDE_INT);
637 static void rs6000_xcoff_unique_section (tree, int);
638 static section *rs6000_xcoff_select_rtx_section
639 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
640 static const char * rs6000_xcoff_strip_name_encoding (const char *);
641 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
642 static void rs6000_xcoff_file_start (void);
643 static void rs6000_xcoff_file_end (void);
645 static int rs6000_variable_issue (FILE *, int, rtx, int);
646 static bool rs6000_rtx_costs (rtx, int, int, int *);
647 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
648 static bool is_microcoded_insn (rtx);
649 static int is_dispatch_slot_restricted (rtx);
650 static bool is_cracked_insn (rtx);
651 static bool is_branch_slot_insn (rtx);
652 static int rs6000_adjust_priority (rtx, int);
653 static int rs6000_issue_rate (void);
654 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
655 static rtx get_next_active_insn (rtx, rtx);
656 static bool insn_terminates_group_p (rtx , enum group_termination);
657 static bool is_costly_group (rtx *, rtx);
658 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
659 static int redefine_groups (FILE *, int, rtx, rtx);
660 static int pad_groups (FILE *, int, rtx, rtx);
661 static void rs6000_sched_finish (FILE *, int);
662 static int rs6000_use_sched_lookahead (void);
663 static tree rs6000_builtin_mask_for_load (void);
665 static void def_builtin (int, const char *, tree, int);
666 static void rs6000_init_builtins (void);
667 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
668 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
669 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
670 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
671 static void altivec_init_builtins (void);
672 static void rs6000_common_init_builtins (void);
673 static void rs6000_init_libfuncs (void);
675 static void enable_mask_for_builtins (struct builtin_description *, int,
676 enum rs6000_builtins,
677 enum rs6000_builtins);
678 static tree build_opaque_vector_type (tree, int);
679 static void spe_init_builtins (void);
680 static rtx spe_expand_builtin (tree, rtx, bool *);
681 static rtx spe_expand_stv_builtin (enum insn_code, tree);
682 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
683 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
684 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
685 static rs6000_stack_t *rs6000_stack_info (void);
686 static void debug_stack_info (rs6000_stack_t *);
688 static rtx altivec_expand_builtin (tree, rtx, bool *);
689 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
690 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
691 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
692 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
693 static rtx altivec_expand_predicate_builtin (enum insn_code,
694 const char *, tree, rtx);
695 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
696 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
697 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
698 static rtx altivec_expand_vec_set_builtin (tree);
699 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
700 static int get_element_number (tree, tree);
701 static bool rs6000_handle_option (size_t, const char *, int);
702 static void rs6000_parse_tls_size_option (void);
703 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
704 static int first_altivec_reg_to_save (void);
705 static unsigned int compute_vrsave_mask (void);
706 static void compute_save_world_info (rs6000_stack_t *info_ptr);
707 static void is_altivec_return_reg (rtx, void *);
708 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
709 int easy_vector_constant (rtx, enum machine_mode);
710 static bool rs6000_is_opaque_type (tree);
711 static rtx rs6000_dwarf_register_span (rtx);
712 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
713 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
714 static rtx rs6000_tls_get_addr (void);
715 static rtx rs6000_got_sym (void);
716 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
717 static const char *rs6000_get_some_local_dynamic_name (void);
718 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
719 static rtx rs6000_complex_function_value (enum machine_mode);
720 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
721 enum machine_mode, tree);
722 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
724 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
725 tree, HOST_WIDE_INT);
726 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
729 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
732 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
733 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
734 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
735 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
736 enum machine_mode, tree,
738 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
740 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
742 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
744 static void macho_branch_islands (void);
745 static void add_compiler_branch_island (tree, tree, int);
746 static int no_previous_def (tree function_name);
747 static tree get_prev_label (tree function_name);
748 static void rs6000_darwin_file_start (void);
751 static tree rs6000_build_builtin_va_list (void);
752 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
753 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
754 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
755 static bool rs6000_vector_mode_supported_p (enum machine_mode);
756 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
758 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
760 static int get_vsel_insn (enum machine_mode);
761 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
762 static tree rs6000_stack_protect_fail (void);
764 const int INSN_NOT_AVAILABLE = -1;
765 static enum machine_mode rs6000_eh_return_filter_mode (void);
767 /* Hash table stuff for keeping track of TOC entries. */
769 struct toc_hash_struct GTY(())
771 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
772 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
774 enum machine_mode key_mode;
778 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
780 /* Default register names. */
781 char rs6000_reg_names[][8] =
783 "0", "1", "2", "3", "4", "5", "6", "7",
784 "8", "9", "10", "11", "12", "13", "14", "15",
785 "16", "17", "18", "19", "20", "21", "22", "23",
786 "24", "25", "26", "27", "28", "29", "30", "31",
787 "0", "1", "2", "3", "4", "5", "6", "7",
788 "8", "9", "10", "11", "12", "13", "14", "15",
789 "16", "17", "18", "19", "20", "21", "22", "23",
790 "24", "25", "26", "27", "28", "29", "30", "31",
791 "mq", "lr", "ctr","ap",
792 "0", "1", "2", "3", "4", "5", "6", "7",
794 /* AltiVec registers. */
795 "0", "1", "2", "3", "4", "5", "6", "7",
796 "8", "9", "10", "11", "12", "13", "14", "15",
797 "16", "17", "18", "19", "20", "21", "22", "23",
798 "24", "25", "26", "27", "28", "29", "30", "31",
801 "spe_acc", "spefscr",
802 /* Soft frame pointer. */
806 #ifdef TARGET_REGNAMES
807 static const char alt_reg_names[][8] =
809 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
810 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
811 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
812 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
813 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
814 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
815 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
816 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
817 "mq", "lr", "ctr", "ap",
818 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
820 /* AltiVec registers. */
821 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
822 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
823 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
824 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
827 "spe_acc", "spefscr",
828 /* Soft frame pointer. */
833 #ifndef MASK_STRICT_ALIGN
834 #define MASK_STRICT_ALIGN 0
836 #ifndef TARGET_PROFILE_KERNEL
837 #define TARGET_PROFILE_KERNEL 0
840 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
841 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
843 /* Initialize the GCC target structure. */
844 #undef TARGET_ATTRIBUTE_TABLE
845 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
846 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
847 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
849 #undef TARGET_ASM_ALIGNED_DI_OP
850 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
852 /* Default unaligned ops are only provided for ELF. Find the ops needed
853 for non-ELF systems. */
854 #ifndef OBJECT_FORMAT_ELF
856 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
858 #undef TARGET_ASM_UNALIGNED_HI_OP
859 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
860 #undef TARGET_ASM_UNALIGNED_SI_OP
861 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
862 #undef TARGET_ASM_UNALIGNED_DI_OP
863 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
866 #undef TARGET_ASM_UNALIGNED_HI_OP
867 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
868 #undef TARGET_ASM_UNALIGNED_SI_OP
869 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
870 #undef TARGET_ASM_UNALIGNED_DI_OP
871 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
872 #undef TARGET_ASM_ALIGNED_DI_OP
873 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
877 /* This hook deals with fixups for relocatable code and DI-mode objects
879 #undef TARGET_ASM_INTEGER
880 #define TARGET_ASM_INTEGER rs6000_assemble_integer
882 #ifdef HAVE_GAS_HIDDEN
883 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
884 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
887 #undef TARGET_HAVE_TLS
888 #define TARGET_HAVE_TLS HAVE_AS_TLS
890 #undef TARGET_CANNOT_FORCE_CONST_MEM
891 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
893 #undef TARGET_ASM_FUNCTION_PROLOGUE
894 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
895 #undef TARGET_ASM_FUNCTION_EPILOGUE
896 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
898 #undef TARGET_SCHED_VARIABLE_ISSUE
899 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
901 #undef TARGET_SCHED_ISSUE_RATE
902 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
903 #undef TARGET_SCHED_ADJUST_COST
904 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
905 #undef TARGET_SCHED_ADJUST_PRIORITY
906 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
907 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
908 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
909 #undef TARGET_SCHED_FINISH
910 #define TARGET_SCHED_FINISH rs6000_sched_finish
912 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
913 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
915 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
916 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
918 #undef TARGET_INIT_BUILTINS
919 #define TARGET_INIT_BUILTINS rs6000_init_builtins
921 #undef TARGET_EXPAND_BUILTIN
922 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
924 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
925 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
927 #undef TARGET_INIT_LIBFUNCS
928 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
931 #undef TARGET_BINDS_LOCAL_P
932 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
935 #undef TARGET_ASM_OUTPUT_MI_THUNK
936 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
938 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
939 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
941 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
942 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
944 #undef TARGET_INVALID_WITHIN_DOLOOP
945 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
947 #undef TARGET_RTX_COSTS
948 #define TARGET_RTX_COSTS rs6000_rtx_costs
949 #undef TARGET_ADDRESS_COST
950 #define TARGET_ADDRESS_COST hook_int_rtx_0
952 #undef TARGET_VECTOR_OPAQUE_P
953 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
955 #undef TARGET_DWARF_REGISTER_SPAN
956 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
958 /* On rs6000, function arguments are promoted, as are function return
960 #undef TARGET_PROMOTE_FUNCTION_ARGS
961 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
962 #undef TARGET_PROMOTE_FUNCTION_RETURN
963 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
965 #undef TARGET_RETURN_IN_MEMORY
966 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
968 #undef TARGET_SETUP_INCOMING_VARARGS
969 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
971 /* Always strict argument naming on rs6000. */
972 #undef TARGET_STRICT_ARGUMENT_NAMING
973 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
974 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
975 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
976 #undef TARGET_SPLIT_COMPLEX_ARG
977 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
978 #undef TARGET_MUST_PASS_IN_STACK
979 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
980 #undef TARGET_PASS_BY_REFERENCE
981 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
982 #undef TARGET_ARG_PARTIAL_BYTES
983 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
985 #undef TARGET_BUILD_BUILTIN_VA_LIST
986 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
988 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
989 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
991 #undef TARGET_EH_RETURN_FILTER_MODE
992 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
994 #undef TARGET_SCALAR_MODE_SUPPORTED_P
995 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
997 #undef TARGET_VECTOR_MODE_SUPPORTED_P
998 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1000 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1001 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1003 #undef TARGET_HANDLE_OPTION
1004 #define TARGET_HANDLE_OPTION rs6000_handle_option
1006 #undef TARGET_DEFAULT_TARGET_FLAGS
1007 #define TARGET_DEFAULT_TARGET_FLAGS \
1010 #undef TARGET_STACK_PROTECT_FAIL
1011 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1013 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1014 The PowerPC architecture requires only weak consistency among
1015 processors--that is, memory accesses between processors need not be
1016 sequentially consistent and memory accesses among processors can occur
1017 in any order. The ability to order memory accesses weakly provides
1018 opportunities for more efficient use of the system bus. Unless a
1019 dependency exists, the 604e allows read operations to precede store
1021 #undef TARGET_RELAXED_ORDERING
1022 #define TARGET_RELAXED_ORDERING true
1025 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1026 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1029 /* Use a 32-bit anchor range. This leads to sequences like:
1031 addis tmp,anchor,high
1034 where tmp itself acts as an anchor, and can be shared between
1035 accesses to the same 64k page. */
1036 #undef TARGET_MIN_ANCHOR_OFFSET
1037 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1038 #undef TARGET_MAX_ANCHOR_OFFSET
1039 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1040 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1041 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1043 struct gcc_target targetm = TARGET_INITIALIZER;
1046 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1049 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1051 /* The GPRs can hold any mode, but values bigger than one register
1052 cannot go past R31. */
1053 if (INT_REGNO_P (regno))
1054 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1056 /* The float registers can only hold floating modes and DImode.
1057 This also excludes decimal float modes. */
1058 if (FP_REGNO_P (regno))
1060 (SCALAR_FLOAT_MODE_P (mode)
1061 && !DECIMAL_FLOAT_MODE_P (mode)
1062 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1063 || (GET_MODE_CLASS (mode) == MODE_INT
1064 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1066 /* The CR register can only hold CC modes. */
1067 if (CR_REGNO_P (regno))
1068 return GET_MODE_CLASS (mode) == MODE_CC;
1070 if (XER_REGNO_P (regno))
1071 return mode == PSImode;
1073 /* AltiVec only in AldyVec registers. */
1074 if (ALTIVEC_REGNO_P (regno))
1075 return ALTIVEC_VECTOR_MODE (mode);
1077 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1078 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1081 /* We cannot put TImode anywhere except general register and it must be
1082 able to fit within the register set. */
1084 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1087 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1089 rs6000_init_hard_regno_mode_ok (void)
1093 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1094 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1095 if (rs6000_hard_regno_mode_ok (r, m))
1096 rs6000_hard_regno_mode_ok_p[m][r] = true;
1099 /* If not otherwise specified by a target, make 'long double' equivalent to
1102 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1103 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1106 /* Override command line options. Mostly we process the processor
1107 type and sometimes adjust other TARGET_ options. */
1110 rs6000_override_options (const char *default_cpu)
1113 struct rs6000_cpu_select *ptr;
1116 /* Simplifications for entries below. */
1119 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1120 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1123 /* This table occasionally claims that a processor does not support
1124 a particular feature even though it does, but the feature is slower
1125 than the alternative. Thus, it shouldn't be relied on as a
1126 complete description of the processor's support.
1128 Please keep this list in order, and don't forget to update the
1129 documentation in invoke.texi when adding a new processor or
1133 const char *const name; /* Canonical processor name. */
1134 const enum processor_type processor; /* Processor type enum value. */
1135 const int target_enable; /* Target flags to enable. */
1136 } const processor_target_table[]
1137 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1138 {"403", PROCESSOR_PPC403,
1139 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1140 {"405", PROCESSOR_PPC405,
1141 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1142 {"405fp", PROCESSOR_PPC405,
1143 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1144 {"440", PROCESSOR_PPC440,
1145 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1146 {"440fp", PROCESSOR_PPC440,
1147 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1148 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1149 {"601", PROCESSOR_PPC601,
1150 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1151 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1152 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1153 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1154 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1155 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1156 {"620", PROCESSOR_PPC620,
1157 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1158 {"630", PROCESSOR_PPC630,
1159 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1160 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1161 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1162 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1163 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1164 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1165 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1166 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1167 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1168 /* 8548 has a dummy entry for now. */
1169 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1170 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1171 {"970", PROCESSOR_POWER4,
1172 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1173 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1174 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1175 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1176 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1177 {"G5", PROCESSOR_POWER4,
1178 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1179 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1180 {"power2", PROCESSOR_POWER,
1181 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1182 {"power3", PROCESSOR_PPC630,
1183 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1184 {"power4", PROCESSOR_POWER4,
1185 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1186 {"power5", PROCESSOR_POWER5,
1187 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1188 | MASK_MFCRF | MASK_POPCNTB},
1189 {"power5+", PROCESSOR_POWER5,
1190 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1191 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1192 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1193 {"powerpc64", PROCESSOR_POWERPC64,
1194 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1195 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1196 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1197 {"rios2", PROCESSOR_RIOS2,
1198 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1199 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1200 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1201 {"rs64", PROCESSOR_RS64A,
1202 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1205 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1207 /* Some OSs don't support saving the high part of 64-bit registers on
1208 context switch. Other OSs don't support saving Altivec registers.
1209 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1210 settings; if the user wants either, the user must explicitly specify
1211 them and we won't interfere with the user's specification. */
1214 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1215 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1216 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1217 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1221 rs6000_init_hard_regno_mode_ok ();
1223 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1224 #ifdef OS_MISSING_POWERPC64
1225 if (OS_MISSING_POWERPC64)
1226 set_masks &= ~MASK_POWERPC64;
1228 #ifdef OS_MISSING_ALTIVEC
1229 if (OS_MISSING_ALTIVEC)
1230 set_masks &= ~MASK_ALTIVEC;
1233 /* Don't override by the processor default if given explicitly. */
1234 set_masks &= ~target_flags_explicit;
1236 /* Identify the processor type. */
1237 rs6000_select[0].string = default_cpu;
1238 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1240 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1242 ptr = &rs6000_select[i];
1243 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1245 for (j = 0; j < ptt_size; j++)
1246 if (! strcmp (ptr->string, processor_target_table[j].name))
1248 if (ptr->set_tune_p)
1249 rs6000_cpu = processor_target_table[j].processor;
1251 if (ptr->set_arch_p)
1253 target_flags &= ~set_masks;
1254 target_flags |= (processor_target_table[j].target_enable
1261 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1268 /* If we are optimizing big endian systems for space, use the load/store
1269 multiple and string instructions. */
1270 if (BYTES_BIG_ENDIAN && optimize_size)
1271 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1273 /* Don't allow -mmultiple or -mstring on little endian systems
1274 unless the cpu is a 750, because the hardware doesn't support the
1275 instructions used in little endian mode, and causes an alignment
1276 trap. The 750 does not cause an alignment trap (except when the
1277 target is unaligned). */
1279 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1281 if (TARGET_MULTIPLE)
1283 target_flags &= ~MASK_MULTIPLE;
1284 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1285 warning (0, "-mmultiple is not supported on little endian systems");
1290 target_flags &= ~MASK_STRING;
1291 if ((target_flags_explicit & MASK_STRING) != 0)
1292 warning (0, "-mstring is not supported on little endian systems");
1296 /* Set debug flags */
1297 if (rs6000_debug_name)
1299 if (! strcmp (rs6000_debug_name, "all"))
1300 rs6000_debug_stack = rs6000_debug_arg = 1;
1301 else if (! strcmp (rs6000_debug_name, "stack"))
1302 rs6000_debug_stack = 1;
1303 else if (! strcmp (rs6000_debug_name, "arg"))
1304 rs6000_debug_arg = 1;
1306 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1309 if (rs6000_traceback_name)
1311 if (! strncmp (rs6000_traceback_name, "full", 4))
1312 rs6000_traceback = traceback_full;
1313 else if (! strncmp (rs6000_traceback_name, "part", 4))
1314 rs6000_traceback = traceback_part;
1315 else if (! strncmp (rs6000_traceback_name, "no", 2))
1316 rs6000_traceback = traceback_none;
1318 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1319 rs6000_traceback_name);
1322 if (!rs6000_explicit_options.long_double)
1323 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1325 #ifndef POWERPC_LINUX
1326 if (!rs6000_explicit_options.ieee)
1327 rs6000_ieeequad = 1;
1330 /* Set Altivec ABI as default for powerpc64 linux. */
1331 if (TARGET_ELF && TARGET_64BIT)
1333 rs6000_altivec_abi = 1;
1334 TARGET_ALTIVEC_VRSAVE = 1;
1337 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1338 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1340 rs6000_darwin64_abi = 1;
1342 darwin_one_byte_bool = 1;
1344 /* Default to natural alignment, for better performance. */
1345 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1348 /* Handle -mtls-size option. */
1349 rs6000_parse_tls_size_option ();
1351 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1352 SUBTARGET_OVERRIDE_OPTIONS;
1354 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1355 SUBSUBTARGET_OVERRIDE_OPTIONS;
1357 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1358 SUB3TARGET_OVERRIDE_OPTIONS;
1364 error ("AltiVec and E500 instructions cannot coexist");
1366 /* The e500 does not have string instructions, and we set
1367 MASK_STRING above when optimizing for size. */
1368 if ((target_flags & MASK_STRING) != 0)
1369 target_flags = target_flags & ~MASK_STRING;
1371 else if (rs6000_select[1].string != NULL)
1373 /* For the powerpc-eabispe configuration, we set all these by
1374 default, so let's unset them if we manually set another
1375 CPU that is not the E500. */
1376 if (!rs6000_explicit_options.abi)
1378 if (!rs6000_explicit_options.spe)
1380 if (!rs6000_explicit_options.float_gprs)
1381 rs6000_float_gprs = 0;
1382 if (!rs6000_explicit_options.isel)
1384 if (!rs6000_explicit_options.long_double)
1385 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1388 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1389 && rs6000_cpu != PROCESSOR_POWER5);
1390 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1391 || rs6000_cpu == PROCESSOR_POWER5);
1393 rs6000_sched_restricted_insns_priority
1394 = (rs6000_sched_groups ? 1 : 0);
1396 /* Handle -msched-costly-dep option. */
1397 rs6000_sched_costly_dep
1398 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1400 if (rs6000_sched_costly_dep_str)
1402 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1403 rs6000_sched_costly_dep = no_dep_costly;
1404 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1405 rs6000_sched_costly_dep = all_deps_costly;
1406 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1407 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1408 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1409 rs6000_sched_costly_dep = store_to_load_dep_costly;
1411 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1414 /* Handle -minsert-sched-nops option. */
1415 rs6000_sched_insert_nops
1416 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1418 if (rs6000_sched_insert_nops_str)
1420 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1421 rs6000_sched_insert_nops = sched_finish_none;
1422 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1423 rs6000_sched_insert_nops = sched_finish_pad_groups;
1424 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1425 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1427 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1430 #ifdef TARGET_REGNAMES
1431 /* If the user desires alternate register names, copy in the
1432 alternate names now. */
1433 if (TARGET_REGNAMES)
1434 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1437 /* Set aix_struct_return last, after the ABI is determined.
1438 If -maix-struct-return or -msvr4-struct-return was explicitly
1439 used, don't override with the ABI default. */
1440 if (!rs6000_explicit_options.aix_struct_ret)
1441 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1443 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1444 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1447 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1449 /* We can only guarantee the availability of DI pseudo-ops when
1450 assembling for 64-bit targets. */
1453 targetm.asm_out.aligned_op.di = NULL;
1454 targetm.asm_out.unaligned_op.di = NULL;
1457 /* Set branch target alignment, if not optimizing for size. */
1460 if (rs6000_sched_groups)
1462 if (align_functions <= 0)
1463 align_functions = 16;
1464 if (align_jumps <= 0)
1466 if (align_loops <= 0)
1469 if (align_jumps_max_skip <= 0)
1470 align_jumps_max_skip = 15;
1471 if (align_loops_max_skip <= 0)
1472 align_loops_max_skip = 15;
1475 /* Arrange to save and restore machine status around nested functions. */
1476 init_machine_status = rs6000_init_machine_status;
1478 /* We should always be splitting complex arguments, but we can't break
1479 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1480 if (DEFAULT_ABI != ABI_AIX)
1481 targetm.calls.split_complex_arg = NULL;
1483 /* Initialize rs6000_cost with the appropriate target costs. */
1485 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1489 case PROCESSOR_RIOS1:
1490 rs6000_cost = &rios1_cost;
1493 case PROCESSOR_RIOS2:
1494 rs6000_cost = &rios2_cost;
1497 case PROCESSOR_RS64A:
1498 rs6000_cost = &rs64a_cost;
1501 case PROCESSOR_MPCCORE:
1502 rs6000_cost = &mpccore_cost;
1505 case PROCESSOR_PPC403:
1506 rs6000_cost = &ppc403_cost;
1509 case PROCESSOR_PPC405:
1510 rs6000_cost = &ppc405_cost;
1513 case PROCESSOR_PPC440:
1514 rs6000_cost = &ppc440_cost;
1517 case PROCESSOR_PPC601:
1518 rs6000_cost = &ppc601_cost;
1521 case PROCESSOR_PPC603:
1522 rs6000_cost = &ppc603_cost;
1525 case PROCESSOR_PPC604:
1526 rs6000_cost = &ppc604_cost;
1529 case PROCESSOR_PPC604e:
1530 rs6000_cost = &ppc604e_cost;
1533 case PROCESSOR_PPC620:
1534 rs6000_cost = &ppc620_cost;
1537 case PROCESSOR_PPC630:
1538 rs6000_cost = &ppc630_cost;
1541 case PROCESSOR_PPC750:
1542 case PROCESSOR_PPC7400:
1543 rs6000_cost = &ppc750_cost;
1546 case PROCESSOR_PPC7450:
1547 rs6000_cost = &ppc7450_cost;
1550 case PROCESSOR_PPC8540:
1551 rs6000_cost = &ppc8540_cost;
1554 case PROCESSOR_POWER4:
1555 case PROCESSOR_POWER5:
1556 rs6000_cost = &power4_cost;
1564 /* Implement targetm.vectorize.builtin_mask_for_load. */
1566 rs6000_builtin_mask_for_load (void)
1569 return altivec_builtin_mask_for_load;
1574 /* Handle generic options of the form -mfoo=yes/no.
1575 NAME is the option name.
1576 VALUE is the option value.
1577 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1578 whether the option value is 'yes' or 'no' respectively. */
1580 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1584 else if (!strcmp (value, "yes"))
1586 else if (!strcmp (value, "no"))
1589 error ("unknown -m%s= option specified: '%s'", name, value);
1592 /* Validate and record the size specified with the -mtls-size option. */
1595 rs6000_parse_tls_size_option (void)
1597 if (rs6000_tls_size_string == 0)
1599 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1600 rs6000_tls_size = 16;
1601 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1602 rs6000_tls_size = 32;
1603 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1604 rs6000_tls_size = 64;
1606 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1610 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1612 if (DEFAULT_ABI == ABI_DARWIN)
1613 /* The Darwin libraries never set errno, so we might as well
1614 avoid calling them when that's the only reason we would. */
1615 flag_errno_math = 0;
1617 /* Double growth factor to counter reduced min jump length. */
1618 set_param_value ("max-grow-copy-bb-insns", 16);
1621 /* Implement TARGET_HANDLE_OPTION. */
1624 rs6000_handle_option (size_t code, const char *arg, int value)
1629 target_flags &= ~(MASK_POWER | MASK_POWER2
1630 | MASK_MULTIPLE | MASK_STRING);
1631 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1632 | MASK_MULTIPLE | MASK_STRING);
1634 case OPT_mno_powerpc:
1635 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1636 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1637 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1638 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1641 target_flags &= ~MASK_MINIMAL_TOC;
1642 TARGET_NO_FP_IN_TOC = 0;
1643 TARGET_NO_SUM_IN_TOC = 0;
1644 target_flags_explicit |= MASK_MINIMAL_TOC;
1645 #ifdef TARGET_USES_SYSV4_OPT
1646 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1647 just the same as -mminimal-toc. */
1648 target_flags |= MASK_MINIMAL_TOC;
1649 target_flags_explicit |= MASK_MINIMAL_TOC;
1653 #ifdef TARGET_USES_SYSV4_OPT
1655 /* Make -mtoc behave like -mminimal-toc. */
1656 target_flags |= MASK_MINIMAL_TOC;
1657 target_flags_explicit |= MASK_MINIMAL_TOC;
1661 #ifdef TARGET_USES_AIX64_OPT
1666 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1667 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1668 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1671 #ifdef TARGET_USES_AIX64_OPT
1676 target_flags &= ~MASK_POWERPC64;
1677 target_flags_explicit |= MASK_POWERPC64;
1680 case OPT_minsert_sched_nops_:
1681 rs6000_sched_insert_nops_str = arg;
1684 case OPT_mminimal_toc:
1687 TARGET_NO_FP_IN_TOC = 0;
1688 TARGET_NO_SUM_IN_TOC = 0;
1695 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1696 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1703 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1704 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1708 case OPT_mpowerpc_gpopt:
1709 case OPT_mpowerpc_gfxopt:
1712 target_flags |= MASK_POWERPC;
1713 target_flags_explicit |= MASK_POWERPC;
1717 case OPT_maix_struct_return:
1718 case OPT_msvr4_struct_return:
1719 rs6000_explicit_options.aix_struct_ret = true;
1723 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1727 rs6000_explicit_options.isel = true;
1728 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1732 rs6000_explicit_options.spe = true;
1733 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1734 /* No SPE means 64-bit long doubles, even if an E500. */
1736 rs6000_long_double_type_size = 64;
1740 rs6000_debug_name = arg;
1743 #ifdef TARGET_USES_SYSV4_OPT
1745 rs6000_abi_name = arg;
1749 rs6000_sdata_name = arg;
1752 case OPT_mtls_size_:
1753 rs6000_tls_size_string = arg;
1756 case OPT_mrelocatable:
1759 target_flags |= MASK_MINIMAL_TOC;
1760 target_flags_explicit |= MASK_MINIMAL_TOC;
1761 TARGET_NO_FP_IN_TOC = 1;
1765 case OPT_mrelocatable_lib:
1768 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1769 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1770 TARGET_NO_FP_IN_TOC = 1;
1774 target_flags &= ~MASK_RELOCATABLE;
1775 target_flags_explicit |= MASK_RELOCATABLE;
1781 if (!strcmp (arg, "altivec"))
1783 rs6000_explicit_options.abi = true;
1784 rs6000_altivec_abi = 1;
1787 else if (! strcmp (arg, "no-altivec"))
1789 /* ??? Don't set rs6000_explicit_options.abi here, to allow
1790 the default for rs6000_spe_abi to be chosen later. */
1791 rs6000_altivec_abi = 0;
1793 else if (! strcmp (arg, "spe"))
1795 rs6000_explicit_options.abi = true;
1797 rs6000_altivec_abi = 0;
1798 if (!TARGET_SPE_ABI)
1799 error ("not configured for ABI: '%s'", arg);
1801 else if (! strcmp (arg, "no-spe"))
1803 rs6000_explicit_options.abi = true;
1807 /* These are here for testing during development only, do not
1808 document in the manual please. */
1809 else if (! strcmp (arg, "d64"))
1811 rs6000_darwin64_abi = 1;
1812 warning (0, "Using darwin64 ABI");
1814 else if (! strcmp (arg, "d32"))
1816 rs6000_darwin64_abi = 0;
1817 warning (0, "Using old darwin ABI");
1820 else if (! strcmp (arg, "ibmlongdouble"))
1822 rs6000_explicit_options.ieee = true;
1823 rs6000_ieeequad = 0;
1824 warning (0, "Using IBM extended precision long double");
1826 else if (! strcmp (arg, "ieeelongdouble"))
1828 rs6000_explicit_options.ieee = true;
1829 rs6000_ieeequad = 1;
1830 warning (0, "Using IEEE extended precision long double");
1835 error ("unknown ABI specified: '%s'", arg);
1841 rs6000_select[1].string = arg;
1845 rs6000_select[2].string = arg;
1848 case OPT_mtraceback_:
1849 rs6000_traceback_name = arg;
1852 case OPT_mfloat_gprs_:
1853 rs6000_explicit_options.float_gprs = true;
1854 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1855 rs6000_float_gprs = 1;
1856 else if (! strcmp (arg, "double"))
1857 rs6000_float_gprs = 2;
1858 else if (! strcmp (arg, "no"))
1859 rs6000_float_gprs = 0;
1862 error ("invalid option for -mfloat-gprs: '%s'", arg);
1867 case OPT_mlong_double_:
1868 rs6000_explicit_options.long_double = true;
1869 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1870 if (value != 64 && value != 128)
1872 error ("Unknown switch -mlong-double-%s", arg);
1873 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1877 rs6000_long_double_type_size = value;
1880 case OPT_msched_costly_dep_:
1881 rs6000_sched_costly_dep_str = arg;
1885 rs6000_explicit_options.alignment = true;
1886 if (! strcmp (arg, "power"))
1888 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1889 some C library functions, so warn about it. The flag may be
1890 useful for performance studies from time to time though, so
1891 don't disable it entirely. */
1892 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1893 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1894 " it is incompatible with the installed C and C++ libraries");
1895 rs6000_alignment_flags = MASK_ALIGN_POWER;
1897 else if (! strcmp (arg, "natural"))
1898 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1901 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1909 /* Do anything needed at the start of the asm file. */
1912 rs6000_file_start (void)
1916 const char *start = buffer;
1917 struct rs6000_cpu_select *ptr;
1918 const char *default_cpu = TARGET_CPU_DEFAULT;
1919 FILE *file = asm_out_file;
1921 default_file_start ();
1923 #ifdef TARGET_BI_ARCH
1924 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1928 if (flag_verbose_asm)
1930 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1931 rs6000_select[0].string = default_cpu;
1933 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1935 ptr = &rs6000_select[i];
1936 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1938 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1943 if (PPC405_ERRATUM77)
1945 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1949 #ifdef USING_ELFOS_H
1950 switch (rs6000_sdata)
1952 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1953 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1954 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1955 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1958 if (rs6000_sdata && g_switch_value)
1960 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1970 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1972 switch_to_section (toc_section);
1973 switch_to_section (text_section);
1978 /* Return nonzero if this function is known to have a null epilogue. */
1981 direct_return (void)
1983 if (reload_completed)
1985 rs6000_stack_t *info = rs6000_stack_info ();
1987 if (info->first_gp_reg_save == 32
1988 && info->first_fp_reg_save == 64
1989 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1990 && ! info->lr_save_p
1991 && ! info->cr_save_p
1992 && info->vrsave_mask == 0
2000 /* Return the number of instructions it takes to form a constant in an
2001 integer register. */
2004 num_insns_constant_wide (HOST_WIDE_INT value)
2006 /* signed constant loadable with {cal|addi} */
2007 if (satisfies_constraint_I (GEN_INT (value)))
2010 /* constant loadable with {cau|addis} */
2011 else if (satisfies_constraint_L (GEN_INT (value)))
2014 #if HOST_BITS_PER_WIDE_INT == 64
2015 else if (TARGET_POWERPC64)
2017 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2018 HOST_WIDE_INT high = value >> 31;
2020 if (high == 0 || high == -1)
2026 return num_insns_constant_wide (high) + 1;
2028 return (num_insns_constant_wide (high)
2029 + num_insns_constant_wide (low) + 1);
2038 num_insns_constant (rtx op, enum machine_mode mode)
2040 HOST_WIDE_INT low, high;
2042 switch (GET_CODE (op))
2045 #if HOST_BITS_PER_WIDE_INT == 64
2046 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2047 && mask64_operand (op, mode))
2051 return num_insns_constant_wide (INTVAL (op));
2059 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2060 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2061 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2064 if (mode == VOIDmode || mode == DImode)
2066 high = CONST_DOUBLE_HIGH (op);
2067 low = CONST_DOUBLE_LOW (op);
2074 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2075 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2076 high = l[WORDS_BIG_ENDIAN == 0];
2077 low = l[WORDS_BIG_ENDIAN != 0];
2081 return (num_insns_constant_wide (low)
2082 + num_insns_constant_wide (high));
2085 if ((high == 0 && low >= 0)
2086 || (high == -1 && low < 0))
2087 return num_insns_constant_wide (low);
2089 else if (mask64_operand (op, mode))
2093 return num_insns_constant_wide (high) + 1;
2096 return (num_insns_constant_wide (high)
2097 + num_insns_constant_wide (low) + 1);
2106 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2107 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2108 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2109 all items are set to the same value and contain COPIES replicas of the
2110 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2111 operand and the others are set to the value of the operand's msb. */
2114 vspltis_constant (rtx op, unsigned step, unsigned copies)
2116 enum machine_mode mode = GET_MODE (op);
2117 enum machine_mode inner = GET_MODE_INNER (mode);
2120 unsigned nunits = GET_MODE_NUNITS (mode);
2121 unsigned bitsize = GET_MODE_BITSIZE (inner);
2122 unsigned mask = GET_MODE_MASK (inner);
2124 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2125 HOST_WIDE_INT val = INTVAL (last);
2126 HOST_WIDE_INT splat_val = val;
2127 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2129 /* Construct the value to be splatted, if possible. If not, return 0. */
2130 for (i = 2; i <= copies; i *= 2)
2132 HOST_WIDE_INT small_val;
2134 small_val = splat_val >> bitsize;
2136 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2138 splat_val = small_val;
2141 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2142 if (EASY_VECTOR_15 (splat_val))
2145 /* Also check if we can splat, and then add the result to itself. Do so if
2146 the value is positive, of if the splat instruction is using OP's mode;
2147 for splat_val < 0, the splat and the add should use the same mode. */
2148 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2149 && (splat_val >= 0 || (step == 1 && copies == 1)))
2155 /* Check if VAL is present in every STEP-th element, and the
2156 other elements are filled with its most significant bit. */
2157 for (i = 0; i < nunits - 1; ++i)
2159 HOST_WIDE_INT desired_val;
2160 if (((i + 1) & (step - 1)) == 0)
2163 desired_val = msb_val;
2165 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2173 /* Return true if OP is of the given MODE and can be synthesized
2174 with a vspltisb, vspltish or vspltisw. */
2177 easy_altivec_constant (rtx op, enum machine_mode mode)
2179 unsigned step, copies;
2181 if (mode == VOIDmode)
2182 mode = GET_MODE (op);
2183 else if (mode != GET_MODE (op))
2186 /* Start with a vspltisw. */
2187 step = GET_MODE_NUNITS (mode) / 4;
2190 if (vspltis_constant (op, step, copies))
2193 /* Then try with a vspltish. */
2199 if (vspltis_constant (op, step, copies))
2202 /* And finally a vspltisb. */
2208 if (vspltis_constant (op, step, copies))
2214 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2215 result is OP. Abort if it is not possible. */
2218 gen_easy_altivec_constant (rtx op)
2220 enum machine_mode mode = GET_MODE (op);
2221 int nunits = GET_MODE_NUNITS (mode);
2222 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2223 unsigned step = nunits / 4;
2224 unsigned copies = 1;
2226 /* Start with a vspltisw. */
2227 if (vspltis_constant (op, step, copies))
2228 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2230 /* Then try with a vspltish. */
2236 if (vspltis_constant (op, step, copies))
2237 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2239 /* And finally a vspltisb. */
2245 if (vspltis_constant (op, step, copies))
2246 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2252 output_vec_const_move (rtx *operands)
2255 enum machine_mode mode;
2260 mode = GET_MODE (dest);
2265 if (zero_constant (vec, mode))
2266 return "vxor %0,%0,%0";
2268 splat_vec = gen_easy_altivec_constant (vec);
2269 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2270 operands[1] = XEXP (splat_vec, 0);
2271 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2274 switch (GET_MODE (splat_vec))
2277 return "vspltisw %0,%1";
2280 return "vspltish %0,%1";
2283 return "vspltisb %0,%1";
2290 gcc_assert (TARGET_SPE);
2292 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2293 pattern of V1DI, V4HI, and V2SF.
2295 FIXME: We should probably return # and add post reload
2296 splitters for these, but this way is so easy ;-). */
2297 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2298 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2299 operands[1] = CONST_VECTOR_ELT (vec, 0);
2300 operands[2] = CONST_VECTOR_ELT (vec, 1);
2302 return "li %0,%1\n\tevmergelo %0,%0,%0";
2304 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2307 /* Initialize vector TARGET to VALS. */
2310 rs6000_expand_vector_init (rtx target, rtx vals)
2312 enum machine_mode mode = GET_MODE (target);
2313 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2314 int n_elts = GET_MODE_NUNITS (mode);
2315 int n_var = 0, one_var = -1;
2316 bool all_same = true, all_const_zero = true;
2320 for (i = 0; i < n_elts; ++i)
2322 x = XVECEXP (vals, 0, i);
2323 if (!CONSTANT_P (x))
2324 ++n_var, one_var = i;
2325 else if (x != CONST0_RTX (inner_mode))
2326 all_const_zero = false;
2328 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2334 if (mode != V4SFmode && all_const_zero)
2336 /* Zero register. */
2337 emit_insn (gen_rtx_SET (VOIDmode, target,
2338 gen_rtx_XOR (mode, target, target)));
2341 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2343 /* Splat immediate. */
2344 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2348 ; /* Splat vector element. */
2351 /* Load from constant pool. */
2352 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2357 /* Store value to stack temp. Load vector element. Splat. */
2360 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2361 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2362 XVECEXP (vals, 0, 0));
2363 x = gen_rtx_UNSPEC (VOIDmode,
2364 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2365 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2367 gen_rtx_SET (VOIDmode,
2370 x = gen_rtx_VEC_SELECT (inner_mode, target,
2371 gen_rtx_PARALLEL (VOIDmode,
2372 gen_rtvec (1, const0_rtx)));
2373 emit_insn (gen_rtx_SET (VOIDmode, target,
2374 gen_rtx_VEC_DUPLICATE (mode, x)));
2378 /* One field is non-constant. Load constant then overwrite
2382 rtx copy = copy_rtx (vals);
2384 /* Load constant part of vector, substitute neighboring value for
2386 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2387 rs6000_expand_vector_init (target, copy);
2389 /* Insert variable. */
2390 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2394 /* Construct the vector in memory one field at a time
2395 and load the whole vector. */
2396 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2397 for (i = 0; i < n_elts; i++)
2398 emit_move_insn (adjust_address_nv (mem, inner_mode,
2399 i * GET_MODE_SIZE (inner_mode)),
2400 XVECEXP (vals, 0, i));
2401 emit_move_insn (target, mem);
2404 /* Set field ELT of TARGET to VAL. */
2407 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2409 enum machine_mode mode = GET_MODE (target);
2410 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2411 rtx reg = gen_reg_rtx (mode);
2413 int width = GET_MODE_SIZE (inner_mode);
2416 /* Load single variable value. */
2417 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2418 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2419 x = gen_rtx_UNSPEC (VOIDmode,
2420 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2421 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2423 gen_rtx_SET (VOIDmode,
2427 /* Linear sequence. */
2428 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2429 for (i = 0; i < 16; ++i)
2430 XVECEXP (mask, 0, i) = GEN_INT (i);
2432 /* Set permute mask to insert element into target. */
2433 for (i = 0; i < width; ++i)
2434 XVECEXP (mask, 0, elt*width + i)
2435 = GEN_INT (i + 0x10);
2436 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2437 x = gen_rtx_UNSPEC (mode,
2438 gen_rtvec (3, target, reg,
2439 force_reg (V16QImode, x)),
2441 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2444 /* Extract field ELT from VEC into TARGET. */
2447 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2449 enum machine_mode mode = GET_MODE (vec);
2450 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2453 /* Allocate mode-sized buffer. */
2454 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2456 /* Add offset to field within buffer matching vector element. */
2457 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2459 /* Store single field into mode-sized buffer. */
2460 x = gen_rtx_UNSPEC (VOIDmode,
2461 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2462 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2464 gen_rtx_SET (VOIDmode,
2467 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2470 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2471 implement ANDing by the mask IN. */
2473 build_mask64_2_operands (rtx in, rtx *out)
2475 #if HOST_BITS_PER_WIDE_INT >= 64
2476 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2479 gcc_assert (GET_CODE (in) == CONST_INT);
2484 /* Assume c initially something like 0x00fff000000fffff. The idea
2485 is to rotate the word so that the middle ^^^^^^ group of zeros
2486 is at the MS end and can be cleared with an rldicl mask. We then
2487 rotate back and clear off the MS ^^ group of zeros with a
2489 c = ~c; /* c == 0xff000ffffff00000 */
2490 lsb = c & -c; /* lsb == 0x0000000000100000 */
2491 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2492 c = ~c; /* c == 0x00fff000000fffff */
2493 c &= -lsb; /* c == 0x00fff00000000000 */
2494 lsb = c & -c; /* lsb == 0x0000100000000000 */
2495 c = ~c; /* c == 0xff000fffffffffff */
2496 c &= -lsb; /* c == 0xff00000000000000 */
2498 while ((lsb >>= 1) != 0)
2499 shift++; /* shift == 44 on exit from loop */
2500 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2501 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2502 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2506 /* Assume c initially something like 0xff000f0000000000. The idea
2507 is to rotate the word so that the ^^^ middle group of zeros
2508 is at the LS end and can be cleared with an rldicr mask. We then
2509 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2511 lsb = c & -c; /* lsb == 0x0000010000000000 */
2512 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2513 c = ~c; /* c == 0x00fff0ffffffffff */
2514 c &= -lsb; /* c == 0x00fff00000000000 */
2515 lsb = c & -c; /* lsb == 0x0000100000000000 */
2516 c = ~c; /* c == 0xff000fffffffffff */
2517 c &= -lsb; /* c == 0xff00000000000000 */
2519 while ((lsb >>= 1) != 0)
2520 shift++; /* shift == 44 on exit from loop */
2521 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2522 m1 >>= shift; /* m1 == 0x0000000000000fff */
2523 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2526 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2527 masks will be all 1's. We are guaranteed more than one transition. */
2528 out[0] = GEN_INT (64 - shift);
2529 out[1] = GEN_INT (m1);
2530 out[2] = GEN_INT (shift);
2531 out[3] = GEN_INT (m2);
2539 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2542 invalid_e500_subreg (rtx op, enum machine_mode mode)
2544 /* Reject (subreg:SI (reg:DF)). */
2545 if (GET_CODE (op) == SUBREG
2547 && REG_P (SUBREG_REG (op))
2548 && GET_MODE (SUBREG_REG (op)) == DFmode)
2551 /* Reject (subreg:DF (reg:DI)). */
2552 if (GET_CODE (op) == SUBREG
2554 && REG_P (SUBREG_REG (op))
2555 && GET_MODE (SUBREG_REG (op)) == DImode)
2561 /* Darwin, AIX increases natural record alignment to doubleword if the first
2562 field is an FP double while the FP fields remain word aligned. */
2565 rs6000_special_round_type_align (tree type, unsigned int computed,
2566 unsigned int specified)
2568 unsigned int align = MAX (computed, specified);
2569 tree field = TYPE_FIELDS (type);
2571 /* Skip all non field decls */
2572 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2573 field = TREE_CHAIN (field);
2575 if (field != NULL && field != type)
2577 type = TREE_TYPE (field);
2578 while (TREE_CODE (type) == ARRAY_TYPE)
2579 type = TREE_TYPE (type);
2581 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2582 align = MAX (align, 64);
2588 /* Return 1 for an operand in small memory on V.4/eabi. */
2591 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2592 enum machine_mode mode ATTRIBUTE_UNUSED)
2597 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2600 if (DEFAULT_ABI != ABI_V4)
2603 if (GET_CODE (op) == SYMBOL_REF)
2606 else if (GET_CODE (op) != CONST
2607 || GET_CODE (XEXP (op, 0)) != PLUS
2608 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2609 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2614 rtx sum = XEXP (op, 0);
2615 HOST_WIDE_INT summand;
2617 /* We have to be careful here, because it is the referenced address
2618 that must be 32k from _SDA_BASE_, not just the symbol. */
2619 summand = INTVAL (XEXP (sum, 1));
2620 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2623 sym_ref = XEXP (sum, 0);
2626 return SYMBOL_REF_SMALL_P (sym_ref);
2632 /* Return true if either operand is a general purpose register. */
2635 gpr_or_gpr_p (rtx op0, rtx op1)
2637 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2638 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2642 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2645 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2647 switch (GET_CODE (op))
2650 if (RS6000_SYMBOL_REF_TLS_P (op))
2652 else if (CONSTANT_POOL_ADDRESS_P (op))
2654 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2662 else if (! strcmp (XSTR (op, 0), toc_label_name))
2671 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2672 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2674 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2683 constant_pool_expr_p (rtx op)
2687 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2691 toc_relative_expr_p (rtx op)
2695 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2699 legitimate_constant_pool_address_p (rtx x)
2702 && GET_CODE (x) == PLUS
2703 && GET_CODE (XEXP (x, 0)) == REG
2704 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2705 && constant_pool_expr_p (XEXP (x, 1)));
2709 legitimate_small_data_p (enum machine_mode mode, rtx x)
2711 return (DEFAULT_ABI == ABI_V4
2712 && !flag_pic && !TARGET_TOC
2713 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2714 && small_data_operand (x, mode));
2717 /* SPE offset addressing is limited to 5-bits worth of double words. */
2718 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2721 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2723 unsigned HOST_WIDE_INT offset, extra;
2725 if (GET_CODE (x) != PLUS)
2727 if (GET_CODE (XEXP (x, 0)) != REG)
2729 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2731 if (legitimate_constant_pool_address_p (x))
2733 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2736 offset = INTVAL (XEXP (x, 1));
2744 /* AltiVec vector modes. Only reg+reg addressing is valid and
2745 constant offset zero should not occur due to canonicalization.
2746 Allow any offset when not strict before reload. */
2753 /* SPE vector modes. */
2754 return SPE_CONST_OFFSET_OK (offset);
2757 if (TARGET_E500_DOUBLE)
2758 return SPE_CONST_OFFSET_OK (offset);
2761 /* On e500v2, we may have:
2763 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2765 Which gets addressed with evldd instructions. */
2766 if (TARGET_E500_DOUBLE)
2767 return SPE_CONST_OFFSET_OK (offset);
2769 if (mode == DFmode || !TARGET_POWERPC64)
2771 else if (offset & 3)
2777 if (mode == TFmode || !TARGET_POWERPC64)
2779 else if (offset & 3)
2790 return (offset < 0x10000) && (offset + extra < 0x10000);
2794 legitimate_indexed_address_p (rtx x, int strict)
2798 if (GET_CODE (x) != PLUS)
2804 /* Recognize the rtl generated by reload which we know will later be
2805 replaced with proper base and index regs. */
2807 && reload_in_progress
2808 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2812 return (REG_P (op0) && REG_P (op1)
2813 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2814 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2815 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2816 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2820 legitimate_indirect_address_p (rtx x, int strict)
2822 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2826 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2828 if (!TARGET_MACHO || !flag_pic
2829 || mode != SImode || GET_CODE (x) != MEM)
2833 if (GET_CODE (x) != LO_SUM)
2835 if (GET_CODE (XEXP (x, 0)) != REG)
2837 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2841 return CONSTANT_P (x);
2845 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2847 if (GET_CODE (x) != LO_SUM)
2849 if (GET_CODE (XEXP (x, 0)) != REG)
2851 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2853 /* Restrict addressing for DI because of our SUBREG hackery. */
2854 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2858 if (TARGET_ELF || TARGET_MACHO)
2860 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2864 if (GET_MODE_NUNITS (mode) != 1)
2866 if (GET_MODE_BITSIZE (mode) > 64
2867 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2868 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2871 return CONSTANT_P (x);
2878 /* Try machine-dependent ways of modifying an illegitimate address
2879 to be legitimate. If we find one, return the new, valid address.
2880 This is used from only one place: `memory_address' in explow.c.
2882 OLDX is the address as it was before break_out_memory_refs was
2883 called. In some cases it is useful to look at this to decide what
2886 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2888 It is always safe for this function to do nothing. It exists to
2889 recognize opportunities to optimize the output.
2891 On RS/6000, first check for the sum of a register with a constant
2892 integer that is out of range. If so, generate code to add the
2893 constant with the low-order 16 bits masked to the register and force
2894 this result into another register (this can be done with `cau').
2895 Then generate an address of REG+(CONST&0xffff), allowing for the
2896 possibility of bit 16 being a one.
2898 Then check for the sum of a register and something not constant, try to
2899 load the other things into a register and return the sum. */
2902 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2903 enum machine_mode mode)
2905 if (GET_CODE (x) == SYMBOL_REF)
2907 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2909 return rs6000_legitimize_tls_address (x, model);
2912 if (GET_CODE (x) == PLUS
2913 && GET_CODE (XEXP (x, 0)) == REG
2914 && GET_CODE (XEXP (x, 1)) == CONST_INT
2915 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2917 HOST_WIDE_INT high_int, low_int;
2919 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2920 high_int = INTVAL (XEXP (x, 1)) - low_int;
2921 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2922 GEN_INT (high_int)), 0);
2923 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2925 else if (GET_CODE (x) == PLUS
2926 && GET_CODE (XEXP (x, 0)) == REG
2927 && GET_CODE (XEXP (x, 1)) != CONST_INT
2928 && GET_MODE_NUNITS (mode) == 1
2929 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2931 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2933 && (TARGET_POWERPC64 || mode != DImode)
2936 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2937 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2939 else if (ALTIVEC_VECTOR_MODE (mode))
2943 /* Make sure both operands are registers. */
2944 if (GET_CODE (x) == PLUS)
2945 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2946 force_reg (Pmode, XEXP (x, 1)));
2948 reg = force_reg (Pmode, x);
2951 else if (SPE_VECTOR_MODE (mode)
2952 || (TARGET_E500_DOUBLE && (mode == DFmode
2953 || mode == DImode)))
2957 /* We accept [reg + reg] and [reg + OFFSET]. */
2959 if (GET_CODE (x) == PLUS)
2961 rtx op1 = XEXP (x, 0);
2962 rtx op2 = XEXP (x, 1);
2964 op1 = force_reg (Pmode, op1);
2966 if (GET_CODE (op2) != REG
2967 && (GET_CODE (op2) != CONST_INT
2968 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2969 op2 = force_reg (Pmode, op2);
2971 return gen_rtx_PLUS (Pmode, op1, op2);
2974 return force_reg (Pmode, x);
2980 && GET_CODE (x) != CONST_INT
2981 && GET_CODE (x) != CONST_DOUBLE
2983 && GET_MODE_NUNITS (mode) == 1
2984 && (GET_MODE_BITSIZE (mode) <= 32
2985 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2987 rtx reg = gen_reg_rtx (Pmode);
2988 emit_insn (gen_elf_high (reg, x));
2989 return gen_rtx_LO_SUM (Pmode, reg, x);
2991 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2994 && ! MACHO_DYNAMIC_NO_PIC_P
2996 && GET_CODE (x) != CONST_INT
2997 && GET_CODE (x) != CONST_DOUBLE
2999 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3003 rtx reg = gen_reg_rtx (Pmode);
3004 emit_insn (gen_macho_high (reg, x));
3005 return gen_rtx_LO_SUM (Pmode, reg, x);
3008 && constant_pool_expr_p (x)
3009 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3011 return create_TOC_reference (x);
3017 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3018 We need to emit DTP-relative relocations. */
3021 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3026 fputs ("\t.long\t", file);
3029 fputs (DOUBLE_INT_ASM_OP, file);
3034 output_addr_const (file, x);
3035 fputs ("@dtprel+0x8000", file);
3038 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3040 static GTY(()) rtx rs6000_tls_symbol;
3042 rs6000_tls_get_addr (void)
3044 if (!rs6000_tls_symbol)
3045 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3047 return rs6000_tls_symbol;
3050 /* Construct the SYMBOL_REF for TLS GOT references. */
3052 static GTY(()) rtx rs6000_got_symbol;
3054 rs6000_got_sym (void)
3056 if (!rs6000_got_symbol)
3058 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3059 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3060 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3063 return rs6000_got_symbol;
3066 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3067 this (thread-local) address. */
3070 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3074 dest = gen_reg_rtx (Pmode);
3075 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3081 tlsreg = gen_rtx_REG (Pmode, 13);
3082 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3086 tlsreg = gen_rtx_REG (Pmode, 2);
3087 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3091 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3095 tmp = gen_reg_rtx (Pmode);
3098 tlsreg = gen_rtx_REG (Pmode, 13);
3099 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3103 tlsreg = gen_rtx_REG (Pmode, 2);
3104 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3108 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3110 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3115 rtx r3, got, tga, tmp1, tmp2, eqv;
3117 /* We currently use relocations like @got@tlsgd for tls, which
3118 means the linker will handle allocation of tls entries, placing
3119 them in the .got section. So use a pointer to the .got section,
3120 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3121 or to secondary GOT sections used by 32-bit -fPIC. */
3123 got = gen_rtx_REG (Pmode, 2);
3127 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3130 rtx gsym = rs6000_got_sym ();
3131 got = gen_reg_rtx (Pmode);
3133 rs6000_emit_move (got, gsym, Pmode);
3136 rtx tempLR, tmp3, mem;
3139 tempLR = gen_reg_rtx (Pmode);
3140 tmp1 = gen_reg_rtx (Pmode);
3141 tmp2 = gen_reg_rtx (Pmode);
3142 tmp3 = gen_reg_rtx (Pmode);
3143 mem = gen_const_mem (Pmode, tmp1);
3145 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3146 emit_move_insn (tmp1, tempLR);
3147 emit_move_insn (tmp2, mem);
3148 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3149 last = emit_move_insn (got, tmp3);
3150 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3152 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3154 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3160 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3162 r3 = gen_rtx_REG (Pmode, 3);
3164 insn = gen_tls_gd_64 (r3, got, addr);
3166 insn = gen_tls_gd_32 (r3, got, addr);
3169 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3170 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3171 insn = emit_call_insn (insn);
3172 CONST_OR_PURE_CALL_P (insn) = 1;
3173 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3174 insn = get_insns ();
3176 emit_libcall_block (insn, dest, r3, addr);
3178 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3180 r3 = gen_rtx_REG (Pmode, 3);
3182 insn = gen_tls_ld_64 (r3, got);
3184 insn = gen_tls_ld_32 (r3, got);
3187 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3188 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3189 insn = emit_call_insn (insn);
3190 CONST_OR_PURE_CALL_P (insn) = 1;
3191 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3192 insn = get_insns ();
3194 tmp1 = gen_reg_rtx (Pmode);
3195 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3197 emit_libcall_block (insn, tmp1, r3, eqv);
3198 if (rs6000_tls_size == 16)
3201 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3203 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3205 else if (rs6000_tls_size == 32)
3207 tmp2 = gen_reg_rtx (Pmode);
3209 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3211 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3214 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3216 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3220 tmp2 = gen_reg_rtx (Pmode);
3222 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3224 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3226 insn = gen_rtx_SET (Pmode, dest,
3227 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3233 /* IE, or 64 bit offset LE. */
3234 tmp2 = gen_reg_rtx (Pmode);
3236 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3238 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3241 insn = gen_tls_tls_64 (dest, tmp2, addr);
3243 insn = gen_tls_tls_32 (dest, tmp2, addr);
3251 /* Return 1 if X contains a thread-local symbol. */
3254 rs6000_tls_referenced_p (rtx x)
3256 if (! TARGET_HAVE_TLS)
3259 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3262 /* Return 1 if *X is a thread-local symbol. This is the same as
3263 rs6000_tls_symbol_ref except for the type of the unused argument. */
3266 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3268 return RS6000_SYMBOL_REF_TLS_P (*x);
3271 /* The convention appears to be to define this wherever it is used.
3272 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3273 is now used here. */
3274 #ifndef REG_MODE_OK_FOR_BASE_P
3275 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3278 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3279 replace the input X, or the original X if no replacement is called for.
3280 The output parameter *WIN is 1 if the calling macro should goto WIN,
3283 For RS/6000, we wish to handle large displacements off a base
3284 register by splitting the addend across an addiu/addis and the mem insn.
3285 This cuts number of extra insns needed from 3 to 1.
3287 On Darwin, we use this to generate code for floating point constants.
3288 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3289 The Darwin code is inside #if TARGET_MACHO because only then is
3290 machopic_function_base_name() defined. */
3292 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3293 int opnum, int type,
3294 int ind_levels ATTRIBUTE_UNUSED, int *win)
3296 /* We must recognize output that we have already generated ourselves. */
3297 if (GET_CODE (x) == PLUS
3298 && GET_CODE (XEXP (x, 0)) == PLUS
3299 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3300 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3301 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3303 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3304 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3305 opnum, (enum reload_type)type);
3311 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3312 && GET_CODE (x) == LO_SUM
3313 && GET_CODE (XEXP (x, 0)) == PLUS
3314 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3315 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3316 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3317 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3318 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3319 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3320 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3322 /* Result of previous invocation of this function on Darwin
3323 floating point constant. */
3324 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3325 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3326 opnum, (enum reload_type)type);
3332 /* Force ld/std non-word aligned offset into base register by wrapping
3334 if (GET_CODE (x) == PLUS
3335 && GET_CODE (XEXP (x, 0)) == REG
3336 && REGNO (XEXP (x, 0)) < 32
3337 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3338 && GET_CODE (XEXP (x, 1)) == CONST_INT
3339 && (INTVAL (XEXP (x, 1)) & 3) != 0
3340 && !ALTIVEC_VECTOR_MODE (mode)
3341 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3342 && TARGET_POWERPC64)
3344 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3345 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3346 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3347 opnum, (enum reload_type) type);
3352 if (GET_CODE (x) == PLUS
3353 && GET_CODE (XEXP (x, 0)) == REG
3354 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3355 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3356 && GET_CODE (XEXP (x, 1)) == CONST_INT
3357 && !SPE_VECTOR_MODE (mode)
3358 && !(TARGET_E500_DOUBLE && (mode == DFmode
3360 && !ALTIVEC_VECTOR_MODE (mode))
3362 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3363 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3365 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3367 /* Check for 32-bit overflow. */
3368 if (high + low != val)
3374 /* Reload the high part into a base reg; leave the low part
3375 in the mem directly. */
3377 x = gen_rtx_PLUS (GET_MODE (x),
3378 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3382 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3383 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3384 opnum, (enum reload_type)type);
3389 if (GET_CODE (x) == SYMBOL_REF
3390 && !ALTIVEC_VECTOR_MODE (mode)
3392 && DEFAULT_ABI == ABI_DARWIN
3393 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3395 && DEFAULT_ABI == ABI_V4
3398 /* Don't do this for TFmode, since the result isn't offsettable.
3399 The same goes for DImode without 64-bit gprs. */
3401 && (mode != DImode || TARGET_POWERPC64))
3406 rtx offset = gen_rtx_CONST (Pmode,
3407 gen_rtx_MINUS (Pmode, x,
3408 machopic_function_base_sym ()));
3409 x = gen_rtx_LO_SUM (GET_MODE (x),
3410 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3411 gen_rtx_HIGH (Pmode, offset)), offset);
3415 x = gen_rtx_LO_SUM (GET_MODE (x),
3416 gen_rtx_HIGH (Pmode, x), x);
3418 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3419 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3420 opnum, (enum reload_type)type);
3425 /* Reload an offset address wrapped by an AND that represents the
3426 masking of the lower bits. Strip the outer AND and let reload
3427 convert the offset address into an indirect address. */
3429 && ALTIVEC_VECTOR_MODE (mode)
3430 && GET_CODE (x) == AND
3431 && GET_CODE (XEXP (x, 0)) == PLUS
3432 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3433 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3434 && GET_CODE (XEXP (x, 1)) == CONST_INT
3435 && INTVAL (XEXP (x, 1)) == -16)
3443 && constant_pool_expr_p (x)
3444 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3446 (x) = create_TOC_reference (x);
3454 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3455 that is a valid memory address for an instruction.
3456 The MODE argument is the machine mode for the MEM expression
3457 that wants to use this address.
3459 On the RS/6000, there are four valid address: a SYMBOL_REF that
3460 refers to a constant pool entry of an address (or the sum of it
3461 plus a constant), a short (16-bit signed) constant plus a register,
3462 the sum of two registers, or a register indirect, possibly with an
3463 auto-increment. For DFmode and DImode with a constant plus register,
3464 we must ensure that both words are addressable or PowerPC64 with offset
3467 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3468 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3469 adjacent memory cells are accessed by adding word-sized offsets
3470 during assembly output. */
3472 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3474 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3476 && ALTIVEC_VECTOR_MODE (mode)
3477 && GET_CODE (x) == AND
3478 && GET_CODE (XEXP (x, 1)) == CONST_INT
3479 && INTVAL (XEXP (x, 1)) == -16)
3482 if (RS6000_SYMBOL_REF_TLS_P (x))
3484 if (legitimate_indirect_address_p (x, reg_ok_strict))
3486 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3487 && !ALTIVEC_VECTOR_MODE (mode)
3488 && !SPE_VECTOR_MODE (mode)
3489 /* Restrict addressing for DI because of our SUBREG hackery. */
3490 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3492 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3494 if (legitimate_small_data_p (mode, x))
3496 if (legitimate_constant_pool_address_p (x))
3498 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3500 && GET_CODE (x) == PLUS
3501 && GET_CODE (XEXP (x, 0)) == REG
3502 && (XEXP (x, 0) == virtual_stack_vars_rtx
3503 || XEXP (x, 0) == arg_pointer_rtx)
3504 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3506 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3510 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3512 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3513 && (TARGET_POWERPC64 || mode != DImode)
3514 && legitimate_indexed_address_p (x, reg_ok_strict))
3516 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3521 /* Go to LABEL if ADDR (a legitimate address expression)
3522 has an effect that depends on the machine mode it is used for.
3524 On the RS/6000 this is true of all integral offsets (since AltiVec
3525 modes don't allow them) or is a pre-increment or decrement.
3527 ??? Except that due to conceptual problems in offsettable_address_p
3528 we can't really report the problems of integral offsets. So leave
3529 this assuming that the adjustable offset must be valid for the
3530 sub-words of a TFmode operand, which is what we had before. */
3533 rs6000_mode_dependent_address (rtx addr)
3535 switch (GET_CODE (addr))
3538 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3540 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3541 return val + 12 + 0x8000 >= 0x10000;
3550 return TARGET_UPDATE;
3559 /* More elaborate version of recog's offsettable_memref_p predicate
3560 that works around the ??? note of rs6000_mode_dependent_address.
3561 In particular it accepts
3563 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3565 in 32-bit mode, that the recog predicate rejects. */
3568 rs6000_offsettable_memref_p (rtx op)
3573 /* First mimic offsettable_memref_p. */
3574 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3577 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3578 the latter predicate knows nothing about the mode of the memory
3579 reference and, therefore, assumes that it is the largest supported
3580 mode (TFmode). As a consequence, legitimate offsettable memory
3581 references are rejected. rs6000_legitimate_offset_address_p contains
3582 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3583 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3586 /* Return number of consecutive hard regs needed starting at reg REGNO
3587 to hold something of mode MODE.
3588 This is ordinarily the length in words of a value of mode MODE
3589 but can be less for certain modes in special long registers.
3591 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3592 scalar instructions. The upper 32 bits are only available to the
3595 POWER and PowerPC GPRs hold 32 bits worth;
3596 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3599 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3601 if (FP_REGNO_P (regno))
3602 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3604 if (TARGET_E500_DOUBLE && mode == DFmode)
3607 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3608 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3610 if (ALTIVEC_REGNO_P (regno))
3612 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3614 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3617 /* Change register usage conditional on target flags. */
3619 rs6000_conditional_register_usage (void)
3623 /* Set MQ register fixed (already call_used) if not POWER
3624 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3629 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3631 fixed_regs[13] = call_used_regs[13]
3632 = call_really_used_regs[13] = 1;
3634 /* Conditionally disable FPRs. */
3635 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3636 for (i = 32; i < 64; i++)
3637 fixed_regs[i] = call_used_regs[i]
3638 = call_really_used_regs[i] = 1;
3640 /* The TOC register is not killed across calls in a way that is
3641 visible to the compiler. */
3642 if (DEFAULT_ABI == ABI_AIX)
3643 call_really_used_regs[2] = 0;
3645 if (DEFAULT_ABI == ABI_V4
3646 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3648 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3650 if (DEFAULT_ABI == ABI_V4
3651 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3653 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3654 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3655 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3657 if (DEFAULT_ABI == ABI_DARWIN
3658 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3659 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3660 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3661 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3663 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3664 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3665 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3668 global_regs[VSCR_REGNO] = 1;
3672 global_regs[SPEFSCR_REGNO] = 1;
3673 fixed_regs[FIXED_SCRATCH]
3674 = call_used_regs[FIXED_SCRATCH]
3675 = call_really_used_regs[FIXED_SCRATCH] = 1;
3678 if (! TARGET_ALTIVEC)
3680 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3681 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3682 call_really_used_regs[VRSAVE_REGNO] = 1;
3685 if (TARGET_ALTIVEC_ABI)
3686 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3687 call_used_regs[i] = call_really_used_regs[i] = 1;
3690 /* Try to output insns to set TARGET equal to the constant C if it can
3691 be done in less than N insns. Do all computations in MODE.
3692 Returns the place where the output has been placed if it can be
3693 done and the insns have been emitted. If it would take more than N
3694 insns, zero is returned and no insns and emitted. */
3697 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3698 rtx source, int n ATTRIBUTE_UNUSED)
3700 rtx result, insn, set;
3701 HOST_WIDE_INT c0, c1;
3708 dest = gen_reg_rtx (mode);
3709 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3713 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3715 emit_insn (gen_rtx_SET (VOIDmode, result,
3716 GEN_INT (INTVAL (source)
3717 & (~ (HOST_WIDE_INT) 0xffff))));
3718 emit_insn (gen_rtx_SET (VOIDmode, dest,
3719 gen_rtx_IOR (SImode, result,
3720 GEN_INT (INTVAL (source) & 0xffff))));
3725 switch (GET_CODE (source))
3728 c0 = INTVAL (source);
3733 #if HOST_BITS_PER_WIDE_INT >= 64
3734 c0 = CONST_DOUBLE_LOW (source);
3737 c0 = CONST_DOUBLE_LOW (source);
3738 c1 = CONST_DOUBLE_HIGH (source);
3746 result = rs6000_emit_set_long_const (dest, c0, c1);
3753 insn = get_last_insn ();
3754 set = single_set (insn);
3755 if (! CONSTANT_P (SET_SRC (set)))
3756 set_unique_reg_note (insn, REG_EQUAL, source);
3761 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3762 fall back to a straight forward decomposition. We do this to avoid
3763 exponential run times encountered when looking for longer sequences
3764 with rs6000_emit_set_const. */
3766 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3768 if (!TARGET_POWERPC64)
3770 rtx operand1, operand2;
3772 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3774 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3776 emit_move_insn (operand1, GEN_INT (c1));
3777 emit_move_insn (operand2, GEN_INT (c2));
3781 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3784 ud2 = (c1 & 0xffff0000) >> 16;
3785 #if HOST_BITS_PER_WIDE_INT >= 64
3789 ud4 = (c2 & 0xffff0000) >> 16;
3791 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3792 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3795 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3797 emit_move_insn (dest, GEN_INT (ud1));
3800 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3801 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3804 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3807 emit_move_insn (dest, GEN_INT (ud2 << 16));
3809 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3811 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3812 || (ud4 == 0 && ! (ud3 & 0x8000)))
3815 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3818 emit_move_insn (dest, GEN_INT (ud3 << 16));
3821 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3822 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3824 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3829 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3832 emit_move_insn (dest, GEN_INT (ud4 << 16));
3835 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3837 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3839 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3840 GEN_INT (ud2 << 16)));
3842 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3848 /* Helper for the following. Get rid of [r+r] memory refs
3849 in cases where it won't work (TImode, TFmode). */
3852 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3854 if (GET_CODE (operands[0]) == MEM
3855 && GET_CODE (XEXP (operands[0], 0)) != REG
3856 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3857 && ! reload_in_progress)
3859 = replace_equiv_address (operands[0],
3860 copy_addr_to_reg (XEXP (operands[0], 0)));
3862 if (GET_CODE (operands[1]) == MEM
3863 && GET_CODE (XEXP (operands[1], 0)) != REG
3864 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3865 && ! reload_in_progress)
3867 = replace_equiv_address (operands[1],
3868 copy_addr_to_reg (XEXP (operands[1], 0)));
3871 /* Emit a move from SOURCE to DEST in mode MODE. */
3873 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3877 operands[1] = source;
3879 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3880 if (GET_CODE (operands[1]) == CONST_DOUBLE
3881 && ! FLOAT_MODE_P (mode)
3882 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3884 /* FIXME. This should never happen. */
3885 /* Since it seems that it does, do the safe thing and convert
3887 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3889 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3890 || FLOAT_MODE_P (mode)
3891 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3892 || CONST_DOUBLE_LOW (operands[1]) < 0)
3893 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3894 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3896 /* Check if GCC is setting up a block move that will end up using FP
3897 registers as temporaries. We must make sure this is acceptable. */
3898 if (GET_CODE (operands[0]) == MEM
3899 && GET_CODE (operands[1]) == MEM
3901 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3902 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3903 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3904 ? 32 : MEM_ALIGN (operands[0])))
3905 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3907 : MEM_ALIGN (operands[1]))))
3908 && ! MEM_VOLATILE_P (operands [0])
3909 && ! MEM_VOLATILE_P (operands [1]))
3911 emit_move_insn (adjust_address (operands[0], SImode, 0),
3912 adjust_address (operands[1], SImode, 0));
3913 emit_move_insn (adjust_address (operands[0], SImode, 4),
3914 adjust_address (operands[1], SImode, 4));
3918 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3919 && !gpc_reg_operand (operands[1], mode))
3920 operands[1] = force_reg (mode, operands[1]);
3922 if (mode == SFmode && ! TARGET_POWERPC
3923 && TARGET_HARD_FLOAT && TARGET_FPRS
3924 && GET_CODE (operands[0]) == MEM)
3928 if (reload_in_progress || reload_completed)
3929 regnum = true_regnum (operands[1]);
3930 else if (GET_CODE (operands[1]) == REG)
3931 regnum = REGNO (operands[1]);
3935 /* If operands[1] is a register, on POWER it may have
3936 double-precision data in it, so truncate it to single
3938 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3941 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3942 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3943 operands[1] = newreg;
3947 /* Recognize the case where operand[1] is a reference to thread-local
3948 data and load its address to a register. */
3949 if (rs6000_tls_referenced_p (operands[1]))
3951 enum tls_model model;
3952 rtx tmp = operands[1];
3955 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3957 addend = XEXP (XEXP (tmp, 0), 1);
3958 tmp = XEXP (XEXP (tmp, 0), 0);
3961 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3962 model = SYMBOL_REF_TLS_MODEL (tmp);
3963 gcc_assert (model != 0);
3965 tmp = rs6000_legitimize_tls_address (tmp, model);
3968 tmp = gen_rtx_PLUS (mode, tmp, addend);
3969 tmp = force_operand (tmp, operands[0]);
3974 /* Handle the case where reload calls us with an invalid address. */
3975 if (reload_in_progress && mode == Pmode
3976 && (! general_operand (operands[1], mode)
3977 || ! nonimmediate_operand (operands[0], mode)))
3980 /* 128-bit constant floating-point values on Darwin should really be
3981 loaded as two parts. */
3982 if (!TARGET_IEEEQUAD
3983 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3984 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3986 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3987 know how to get a DFmode SUBREG of a TFmode. */
3988 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3989 simplify_gen_subreg (DImode, operands[1], mode, 0),
3991 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3992 GET_MODE_SIZE (DImode)),
3993 simplify_gen_subreg (DImode, operands[1], mode,
3994 GET_MODE_SIZE (DImode)),
3999 /* FIXME: In the long term, this switch statement should go away
4000 and be replaced by a sequence of tests based on things like
4006 if (CONSTANT_P (operands[1])
4007 && GET_CODE (operands[1]) != CONST_INT)
4008 operands[1] = force_const_mem (mode, operands[1]);
4012 rs6000_eliminate_indexed_memrefs (operands);
4017 if (CONSTANT_P (operands[1])
4018 && ! easy_fp_constant (operands[1], mode))
4019 operands[1] = force_const_mem (mode, operands[1]);
4030 if (CONSTANT_P (operands[1])
4031 && !easy_vector_constant (operands[1], mode))
4032 operands[1] = force_const_mem (mode, operands[1]);
4037 /* Use default pattern for address of ELF small data */
4040 && DEFAULT_ABI == ABI_V4
4041 && (GET_CODE (operands[1]) == SYMBOL_REF
4042 || GET_CODE (operands[1]) == CONST)
4043 && small_data_operand (operands[1], mode))
4045 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4049 if (DEFAULT_ABI == ABI_V4
4050 && mode == Pmode && mode == SImode
4051 && flag_pic == 1 && got_operand (operands[1], mode))
4053 emit_insn (gen_movsi_got (operands[0], operands[1]));
4057 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4061 && CONSTANT_P (operands[1])
4062 && GET_CODE (operands[1]) != HIGH
4063 && GET_CODE (operands[1]) != CONST_INT)
4065 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4067 /* If this is a function address on -mcall-aixdesc,
4068 convert it to the address of the descriptor. */
4069 if (DEFAULT_ABI == ABI_AIX
4070 && GET_CODE (operands[1]) == SYMBOL_REF
4071 && XSTR (operands[1], 0)[0] == '.')
4073 const char *name = XSTR (operands[1], 0);
4075 while (*name == '.')
4077 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4078 CONSTANT_POOL_ADDRESS_P (new_ref)
4079 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4080 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4081 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4082 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4083 operands[1] = new_ref;
4086 if (DEFAULT_ABI == ABI_DARWIN)
4089 if (MACHO_DYNAMIC_NO_PIC_P)
4091 /* Take care of any required data indirection. */
4092 operands[1] = rs6000_machopic_legitimize_pic_address (
4093 operands[1], mode, operands[0]);
4094 if (operands[0] != operands[1])
4095 emit_insn (gen_rtx_SET (VOIDmode,
4096 operands[0], operands[1]));
4100 emit_insn (gen_macho_high (target, operands[1]));
4101 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4105 emit_insn (gen_elf_high (target, operands[1]));
4106 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4110 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4111 and we have put it in the TOC, we just need to make a TOC-relative
4114 && GET_CODE (operands[1]) == SYMBOL_REF
4115 && constant_pool_expr_p (operands[1])
4116 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4117 get_pool_mode (operands[1])))
4119 operands[1] = create_TOC_reference (operands[1]);
4121 else if (mode == Pmode
4122 && CONSTANT_P (operands[1])
4123 && ((GET_CODE (operands[1]) != CONST_INT
4124 && ! easy_fp_constant (operands[1], mode))
4125 || (GET_CODE (operands[1]) == CONST_INT
4126 && num_insns_constant (operands[1], mode) > 2)
4127 || (GET_CODE (operands[0]) == REG
4128 && FP_REGNO_P (REGNO (operands[0]))))
4129 && GET_CODE (operands[1]) != HIGH
4130 && ! legitimate_constant_pool_address_p (operands[1])
4131 && ! toc_relative_expr_p (operands[1]))
4133 /* Emit a USE operation so that the constant isn't deleted if
4134 expensive optimizations are turned on because nobody
4135 references it. This should only be done for operands that
4136 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4137 This should not be done for operands that contain LABEL_REFs.
4138 For now, we just handle the obvious case. */
4139 if (GET_CODE (operands[1]) != LABEL_REF)
4140 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4143 /* Darwin uses a special PIC legitimizer. */
4144 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4147 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4149 if (operands[0] != operands[1])
4150 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4155 /* If we are to limit the number of things we put in the TOC and
4156 this is a symbol plus a constant we can add in one insn,
4157 just put the symbol in the TOC and add the constant. Don't do
4158 this if reload is in progress. */
4159 if (GET_CODE (operands[1]) == CONST
4160 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4161 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4162 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4163 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4164 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4165 && ! side_effects_p (operands[0]))
4168 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4169 rtx other = XEXP (XEXP (operands[1], 0), 1);
4171 sym = force_reg (mode, sym);
4173 emit_insn (gen_addsi3 (operands[0], sym, other));
4175 emit_insn (gen_adddi3 (operands[0], sym, other));
4179 operands[1] = force_const_mem (mode, operands[1]);
4182 && constant_pool_expr_p (XEXP (operands[1], 0))
4183 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4184 get_pool_constant (XEXP (operands[1], 0)),
4185 get_pool_mode (XEXP (operands[1], 0))))
4188 = gen_const_mem (mode,
4189 create_TOC_reference (XEXP (operands[1], 0)));
4190 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4196 rs6000_eliminate_indexed_memrefs (operands);
4200 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4202 gen_rtx_SET (VOIDmode,
4203 operands[0], operands[1]),
4204 gen_rtx_CLOBBER (VOIDmode,
4205 gen_rtx_SCRATCH (SImode)))));
4214 /* Above, we may have called force_const_mem which may have returned
4215 an invalid address. If we can, fix this up; otherwise, reload will
4216 have to deal with it. */
4217 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4218 operands[1] = validize_mem (operands[1]);
4221 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4224 /* Nonzero if we can use a floating-point register to pass this arg. */
4225 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4226 (SCALAR_FLOAT_MODE_P (MODE) \
4227 && !DECIMAL_FLOAT_MODE_P (MODE) \
4228 && (CUM)->fregno <= FP_ARG_MAX_REG \
4229 && TARGET_HARD_FLOAT && TARGET_FPRS)
4231 /* Nonzero if we can use an AltiVec register to pass this arg. */
4232 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4233 (ALTIVEC_VECTOR_MODE (MODE) \
4234 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4235 && TARGET_ALTIVEC_ABI \
4238 /* Return a nonzero value to say to return the function value in
4239 memory, just as large structures are always returned. TYPE will be
4240 the data type of the value, and FNTYPE will be the type of the
4241 function doing the returning, or @code{NULL} for libcalls.
4243 The AIX ABI for the RS/6000 specifies that all structures are
4244 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4245 specifies that structures <= 8 bytes are returned in r3/r4, but a
4246 draft put them in memory, and GCC used to implement the draft
4247 instead of the final standard. Therefore, aix_struct_return
4248 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4249 compatibility can change DRAFT_V4_STRUCT_RET to override the
4250 default, and -m switches get the final word. See
4251 rs6000_override_options for more details.
4253 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4254 long double support is enabled. These values are returned in memory.
4256 int_size_in_bytes returns -1 for variable size objects, which go in
4257 memory always. The cast to unsigned makes -1 > 8. */
4260 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4262 /* In the darwin64 abi, try to use registers for larger structs
4264 if (rs6000_darwin64_abi
4265 && TREE_CODE (type) == RECORD_TYPE
4266 && int_size_in_bytes (type) > 0)
4268 CUMULATIVE_ARGS valcum;
4272 valcum.fregno = FP_ARG_MIN_REG;
4273 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4274 /* Do a trial code generation as if this were going to be passed
4275 as an argument; if any part goes in memory, we return NULL. */
4276 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4279 /* Otherwise fall through to more conventional ABI rules. */
4282 if (AGGREGATE_TYPE_P (type)
4283 && (aix_struct_return
4284 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4287 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4288 modes only exist for GCC vector types if -maltivec. */
4289 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4290 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4293 /* Return synthetic vectors in memory. */
4294 if (TREE_CODE (type) == VECTOR_TYPE
4295 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4297 static bool warned_for_return_big_vectors = false;
4298 if (!warned_for_return_big_vectors)
4300 warning (0, "GCC vector returned by reference: "
4301 "non-standard ABI extension with no compatibility guarantee");
4302 warned_for_return_big_vectors = true;
4307 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4313 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4314 for a call to a function whose data type is FNTYPE.
4315 For a library call, FNTYPE is 0.
4317 For incoming args we set the number of arguments in the prototype large
4318 so we never return a PARALLEL. */
4321 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4322 rtx libname ATTRIBUTE_UNUSED, int incoming,
4323 int libcall, int n_named_args)
4325 static CUMULATIVE_ARGS zero_cumulative;
4327 *cum = zero_cumulative;
4329 cum->fregno = FP_ARG_MIN_REG;
4330 cum->vregno = ALTIVEC_ARG_MIN_REG;
4331 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4332 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4333 ? CALL_LIBCALL : CALL_NORMAL);
4334 cum->sysv_gregno = GP_ARG_MIN_REG;
4335 cum->stdarg = fntype
4336 && (TYPE_ARG_TYPES (fntype) != 0
4337 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4338 != void_type_node));
4340 cum->nargs_prototype = 0;
4341 if (incoming || cum->prototype)
4342 cum->nargs_prototype = n_named_args;
4344 /* Check for a longcall attribute. */
4345 if ((!fntype && rs6000_default_long_calls)
4347 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4348 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4349 cum->call_cookie |= CALL_LONG;
4351 if (TARGET_DEBUG_ARG)
4353 fprintf (stderr, "\ninit_cumulative_args:");
4356 tree ret_type = TREE_TYPE (fntype);
4357 fprintf (stderr, " ret code = %s,",
4358 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4361 if (cum->call_cookie & CALL_LONG)
4362 fprintf (stderr, " longcall,");
4364 fprintf (stderr, " proto = %d, nargs = %d\n",
4365 cum->prototype, cum->nargs_prototype);
4370 && TARGET_ALTIVEC_ABI
4371 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4373 error ("cannot return value in vector register because"
4374 " altivec instructions are disabled, use -maltivec"
4379 /* Return true if TYPE must be passed on the stack and not in registers. */
4382 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4384 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4385 return must_pass_in_stack_var_size (mode, type);
4387 return must_pass_in_stack_var_size_or_pad (mode, type);
4390 /* If defined, a C expression which determines whether, and in which
4391 direction, to pad out an argument with extra space. The value
4392 should be of type `enum direction': either `upward' to pad above
4393 the argument, `downward' to pad below, or `none' to inhibit
4396 For the AIX ABI structs are always stored left shifted in their
4400 function_arg_padding (enum machine_mode mode, tree type)
4402 #ifndef AGGREGATE_PADDING_FIXED
4403 #define AGGREGATE_PADDING_FIXED 0
4405 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4406 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4409 if (!AGGREGATE_PADDING_FIXED)
4411 /* GCC used to pass structures of the same size as integer types as
4412 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4413 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4414 passed padded downward, except that -mstrict-align further
4415 muddied the water in that multi-component structures of 2 and 4
4416 bytes in size were passed padded upward.
4418 The following arranges for best compatibility with previous
4419 versions of gcc, but removes the -mstrict-align dependency. */
4420 if (BYTES_BIG_ENDIAN)
4422 HOST_WIDE_INT size = 0;
4424 if (mode == BLKmode)
4426 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4427 size = int_size_in_bytes (type);
4430 size = GET_MODE_SIZE (mode);
4432 if (size == 1 || size == 2 || size == 4)
4438 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4440 if (type != 0 && AGGREGATE_TYPE_P (type))
4444 /* Fall back to the default. */
4445 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4448 /* If defined, a C expression that gives the alignment boundary, in bits,
4449 of an argument with the specified mode and type. If it is not defined,
4450 PARM_BOUNDARY is used for all arguments.
4452 V.4 wants long longs to be double word aligned.
4453 Doubleword align SPE vectors.
4454 Quadword align Altivec vectors.
4455 Quadword align large synthetic vector types. */
4458 function_arg_boundary (enum machine_mode mode, tree type)
4460 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4462 else if (SPE_VECTOR_MODE (mode)
4463 || (type && TREE_CODE (type) == VECTOR_TYPE
4464 && int_size_in_bytes (type) >= 8
4465 && int_size_in_bytes (type) < 16))
4467 else if (ALTIVEC_VECTOR_MODE (mode)
4468 || (type && TREE_CODE (type) == VECTOR_TYPE
4469 && int_size_in_bytes (type) >= 16))
4471 else if (rs6000_darwin64_abi && mode == BLKmode
4472 && type && TYPE_ALIGN (type) > 64)
4475 return PARM_BOUNDARY;
4478 /* For a function parm of MODE and TYPE, return the starting word in
4479 the parameter area. NWORDS of the parameter area are already used. */
4482 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4485 unsigned int parm_offset;
4487 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4488 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4489 return nwords + (-(parm_offset + nwords) & align);
4492 /* Compute the size (in words) of a function argument. */
4494 static unsigned long
4495 rs6000_arg_size (enum machine_mode mode, tree type)
4499 if (mode != BLKmode)
4500 size = GET_MODE_SIZE (mode);
4502 size = int_size_in_bytes (type);
4505 return (size + 3) >> 2;
4507 return (size + 7) >> 3;
4510 /* Use this to flush pending int fields. */
4513 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4514 HOST_WIDE_INT bitpos)
4516 unsigned int startbit, endbit;
4517 int intregs, intoffset;
4518 enum machine_mode mode;
4520 if (cum->intoffset == -1)
4523 intoffset = cum->intoffset;
4524 cum->intoffset = -1;
4526 if (intoffset % BITS_PER_WORD != 0)
4528 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4530 if (mode == BLKmode)
4532 /* We couldn't find an appropriate mode, which happens,
4533 e.g., in packed structs when there are 3 bytes to load.
4534 Back intoffset back to the beginning of the word in this
4536 intoffset = intoffset & -BITS_PER_WORD;
4540 startbit = intoffset & -BITS_PER_WORD;
4541 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4542 intregs = (endbit - startbit) / BITS_PER_WORD;
4543 cum->words += intregs;
4546 /* The darwin64 ABI calls for us to recurse down through structs,
4547 looking for elements passed in registers. Unfortunately, we have
4548 to track int register count here also because of misalignments
4549 in powerpc alignment mode. */
4552 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4554 HOST_WIDE_INT startbitpos)
4558 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4559 if (TREE_CODE (f) == FIELD_DECL)
4561 HOST_WIDE_INT bitpos = startbitpos;
4562 tree ftype = TREE_TYPE (f);
4563 enum machine_mode mode = TYPE_MODE (ftype);
4565 if (DECL_SIZE (f) != 0
4566 && host_integerp (bit_position (f), 1))
4567 bitpos += int_bit_position (f);
4569 /* ??? FIXME: else assume zero offset. */
4571 if (TREE_CODE (ftype) == RECORD_TYPE)
4572 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4573 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4575 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4576 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4577 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4579 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4581 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4585 else if (cum->intoffset == -1)
4586 cum->intoffset = bitpos;
4590 /* Update the data in CUM to advance over an argument
4591 of mode MODE and data type TYPE.
4592 (TYPE is null for libcalls where that information may not be available.)
4594 Note that for args passed by reference, function_arg will be called
4595 with MODE and TYPE set to that of the pointer to the arg, not the arg
4599 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4600 tree type, int named, int depth)
4604 /* Only tick off an argument if we're not recursing. */
4606 cum->nargs_prototype--;
4608 if (TARGET_ALTIVEC_ABI
4609 && (ALTIVEC_VECTOR_MODE (mode)
4610 || (type && TREE_CODE (type) == VECTOR_TYPE
4611 && int_size_in_bytes (type) == 16)))
4615 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4618 if (!TARGET_ALTIVEC)
4619 error ("cannot pass argument in vector register because"
4620 " altivec instructions are disabled, use -maltivec"
4623 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4624 even if it is going to be passed in a vector register.
4625 Darwin does the same for variable-argument functions. */
4626 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4627 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4637 /* Vector parameters must be 16-byte aligned. This places
4638 them at 2 mod 4 in terms of words in 32-bit mode, since
4639 the parameter save area starts at offset 24 from the
4640 stack. In 64-bit mode, they just have to start on an
4641 even word, since the parameter save area is 16-byte
4642 aligned. Space for GPRs is reserved even if the argument
4643 will be passed in memory. */
4645 align = (2 - cum->words) & 3;
4647 align = cum->words & 1;
4648 cum->words += align + rs6000_arg_size (mode, type);
4650 if (TARGET_DEBUG_ARG)
4652 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4654 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4655 cum->nargs_prototype, cum->prototype,
4656 GET_MODE_NAME (mode));
4660 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4662 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4665 else if (rs6000_darwin64_abi
4667 && TREE_CODE (type) == RECORD_TYPE
4668 && (size = int_size_in_bytes (type)) > 0)
4670 /* Variable sized types have size == -1 and are
4671 treated as if consisting entirely of ints.
4672 Pad to 16 byte boundary if needed. */
4673 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4674 && (cum->words % 2) != 0)
4676 /* For varargs, we can just go up by the size of the struct. */
4678 cum->words += (size + 7) / 8;
4681 /* It is tempting to say int register count just goes up by
4682 sizeof(type)/8, but this is wrong in a case such as
4683 { int; double; int; } [powerpc alignment]. We have to
4684 grovel through the fields for these too. */
4686 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4687 rs6000_darwin64_record_arg_advance_flush (cum,
4688 size * BITS_PER_UNIT);
4691 else if (DEFAULT_ABI == ABI_V4)
4693 if (TARGET_HARD_FLOAT && TARGET_FPRS
4694 && (mode == SFmode || mode == DFmode
4695 || (mode == TFmode && !TARGET_IEEEQUAD)))
4697 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4698 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4701 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4702 if (mode == DFmode || mode == TFmode)
4703 cum->words += cum->words & 1;
4704 cum->words += rs6000_arg_size (mode, type);
4709 int n_words = rs6000_arg_size (mode, type);
4710 int gregno = cum->sysv_gregno;
4712 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4713 (r7,r8) or (r9,r10). As does any other 2 word item such
4714 as complex int due to a historical mistake. */
4716 gregno += (1 - gregno) & 1;
4718 /* Multi-reg args are not split between registers and stack. */
4719 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4721 /* Long long and SPE vectors are aligned on the stack.
4722 So are other 2 word items such as complex int due to
4723 a historical mistake. */
4725 cum->words += cum->words & 1;
4726 cum->words += n_words;
4729 /* Note: continuing to accumulate gregno past when we've started
4730 spilling to the stack indicates the fact that we've started
4731 spilling to the stack to expand_builtin_saveregs. */
4732 cum->sysv_gregno = gregno + n_words;
4735 if (TARGET_DEBUG_ARG)
4737 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4738 cum->words, cum->fregno);
4739 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4740 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4741 fprintf (stderr, "mode = %4s, named = %d\n",
4742 GET_MODE_NAME (mode), named);
4747 int n_words = rs6000_arg_size (mode, type);
4748 int start_words = cum->words;
4749 int align_words = rs6000_parm_start (mode, type, start_words);
4751 cum->words = align_words + n_words;
4753 if (SCALAR_FLOAT_MODE_P (mode)
4754 && !DECIMAL_FLOAT_MODE_P (mode)
4755 && TARGET_HARD_FLOAT && TARGET_FPRS)
4756 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4758 if (TARGET_DEBUG_ARG)
4760 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4761 cum->words, cum->fregno);
4762 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4763 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4764 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4765 named, align_words - start_words, depth);
4771 spe_build_register_parallel (enum machine_mode mode, int gregno)
4778 r1 = gen_rtx_REG (DImode, gregno);
4779 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4780 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4783 r1 = gen_rtx_REG (DImode, gregno);
4784 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4785 r3 = gen_rtx_REG (DImode, gregno + 2);
4786 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4787 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4794 /* Determine where to put a SIMD argument on the SPE. */
4796 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4799 int gregno = cum->sysv_gregno;
4801 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4802 are passed and returned in a pair of GPRs for ABI compatibility. */
4803 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4805 int n_words = rs6000_arg_size (mode, type);
4807 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4809 gregno += (1 - gregno) & 1;
4811 /* Multi-reg args are not split between registers and stack. */
4812 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4815 return spe_build_register_parallel (mode, gregno);
4819 int n_words = rs6000_arg_size (mode, type);
4821 /* SPE vectors are put in odd registers. */
4822 if (n_words == 2 && (gregno & 1) == 0)
4825 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4828 enum machine_mode m = SImode;
4830 r1 = gen_rtx_REG (m, gregno);
4831 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4832 r2 = gen_rtx_REG (m, gregno + 1);
4833 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4834 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4841 if (gregno <= GP_ARG_MAX_REG)
4842 return gen_rtx_REG (mode, gregno);
4848 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4849 structure between cum->intoffset and bitpos to integer registers. */
4852 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4853 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4855 enum machine_mode mode;
4857 unsigned int startbit, endbit;
4858 int this_regno, intregs, intoffset;
4861 if (cum->intoffset == -1)
4864 intoffset = cum->intoffset;
4865 cum->intoffset = -1;
4867 /* If this is the trailing part of a word, try to only load that
4868 much into the register. Otherwise load the whole register. Note
4869 that in the latter case we may pick up unwanted bits. It's not a
4870 problem at the moment but may wish to revisit. */
4872 if (intoffset % BITS_PER_WORD != 0)
4874 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4876 if (mode == BLKmode)
4878 /* We couldn't find an appropriate mode, which happens,
4879 e.g., in packed structs when there are 3 bytes to load.
4880 Back intoffset back to the beginning of the word in this
4882 intoffset = intoffset & -BITS_PER_WORD;
4889 startbit = intoffset & -BITS_PER_WORD;
4890 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4891 intregs = (endbit - startbit) / BITS_PER_WORD;
4892 this_regno = cum->words + intoffset / BITS_PER_WORD;
4894 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4897 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4901 intoffset /= BITS_PER_UNIT;
4904 regno = GP_ARG_MIN_REG + this_regno;
4905 reg = gen_rtx_REG (mode, regno);
4907 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4910 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4914 while (intregs > 0);
4917 /* Recursive workhorse for the following. */
4920 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4921 HOST_WIDE_INT startbitpos, rtx rvec[],
4926 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4927 if (TREE_CODE (f) == FIELD_DECL)
4929 HOST_WIDE_INT bitpos = startbitpos;
4930 tree ftype = TREE_TYPE (f);
4931 enum machine_mode mode = TYPE_MODE (ftype);
4933 if (DECL_SIZE (f) != 0
4934 && host_integerp (bit_position (f), 1))
4935 bitpos += int_bit_position (f);
4937 /* ??? FIXME: else assume zero offset. */
4939 if (TREE_CODE (ftype) == RECORD_TYPE)
4940 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4941 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4946 case SCmode: mode = SFmode; break;
4947 case DCmode: mode = DFmode; break;
4948 case TCmode: mode = TFmode; break;
4952 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4954 = gen_rtx_EXPR_LIST (VOIDmode,
4955 gen_rtx_REG (mode, cum->fregno++),
4956 GEN_INT (bitpos / BITS_PER_UNIT));
4960 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4962 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4964 = gen_rtx_EXPR_LIST (VOIDmode,
4965 gen_rtx_REG (mode, cum->vregno++),
4966 GEN_INT (bitpos / BITS_PER_UNIT));
4968 else if (cum->intoffset == -1)
4969 cum->intoffset = bitpos;
4973 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4974 the register(s) to be used for each field and subfield of a struct
4975 being passed by value, along with the offset of where the
4976 register's value may be found in the block. FP fields go in FP
4977 register, vector fields go in vector registers, and everything
4978 else goes in int registers, packed as in memory.
4980 This code is also used for function return values. RETVAL indicates
4981 whether this is the case.
4983 Much of this is taken from the SPARC V9 port, which has a similar
4984 calling convention. */
4987 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4988 int named, bool retval)
4990 rtx rvec[FIRST_PSEUDO_REGISTER];
4991 int k = 1, kbase = 1;
4992 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4993 /* This is a copy; modifications are not visible to our caller. */
4994 CUMULATIVE_ARGS copy_cum = *orig_cum;
4995 CUMULATIVE_ARGS *cum = ©_cum;
4997 /* Pad to 16 byte boundary if needed. */
4998 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4999 && (cum->words % 2) != 0)
5006 /* Put entries into rvec[] for individual FP and vector fields, and
5007 for the chunks of memory that go in int regs. Note we start at
5008 element 1; 0 is reserved for an indication of using memory, and
5009 may or may not be filled in below. */
5010 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5011 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5013 /* If any part of the struct went on the stack put all of it there.
5014 This hack is because the generic code for
5015 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5016 parts of the struct are not at the beginning. */
5020 return NULL_RTX; /* doesn't go in registers at all */
5022 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5024 if (k > 1 || cum->use_stack)
5025 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5030 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5033 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5037 rtx rvec[GP_ARG_NUM_REG + 1];
5039 if (align_words >= GP_ARG_NUM_REG)
5042 n_units = rs6000_arg_size (mode, type);
5044 /* Optimize the simple case where the arg fits in one gpr, except in
5045 the case of BLKmode due to assign_parms assuming that registers are
5046 BITS_PER_WORD wide. */
5048 || (n_units == 1 && mode != BLKmode))
5049 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5052 if (align_words + n_units > GP_ARG_NUM_REG)
5053 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5054 using a magic NULL_RTX component.
5055 FIXME: This is not strictly correct. Only some of the arg
5056 belongs in memory, not all of it. However, there isn't any way
5057 to do this currently, apart from building rtx descriptions for
5058 the pieces of memory we want stored. Due to bugs in the generic
5059 code we can't use the normal function_arg_partial_nregs scheme
5060 with the PARALLEL arg description we emit here.
5061 In any case, the code to store the whole arg to memory is often
5062 more efficient than code to store pieces, and we know that space
5063 is available in the right place for the whole arg. */
5064 /* FIXME: This should be fixed since the conversion to
5065 TARGET_ARG_PARTIAL_BYTES. */
5066 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5071 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5072 rtx off = GEN_INT (i++ * 4);
5073 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5075 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5077 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5080 /* Determine where to put an argument to a function.
5081 Value is zero to push the argument on the stack,
5082 or a hard register in which to store the argument.
5084 MODE is the argument's machine mode.
5085 TYPE is the data type of the argument (as a tree).
5086 This is null for libcalls where that information may
5088 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5089 the preceding args and about the function being called. It is
5090 not modified in this routine.
5091 NAMED is nonzero if this argument is a named parameter
5092 (otherwise it is an extra parameter matching an ellipsis).
5094 On RS/6000 the first eight words of non-FP are normally in registers
5095 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5096 Under V.4, the first 8 FP args are in registers.
5098 If this is floating-point and no prototype is specified, we use
5099 both an FP and integer register (or possibly FP reg and stack). Library
5100 functions (when CALL_LIBCALL is set) always have the proper types for args,
5101 so we can pass the FP value just in one register. emit_library_function
5102 doesn't support PARALLEL anyway.
5104 Note that for args passed by reference, function_arg will be called
5105 with MODE and TYPE set to that of the pointer to the arg, not the arg
5109 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5110 tree type, int named)
5112 enum rs6000_abi abi = DEFAULT_ABI;
5114 /* Return a marker to indicate whether CR1 needs to set or clear the
5115 bit that V.4 uses to say fp args were passed in registers.
5116 Assume that we don't need the marker for software floating point,
5117 or compiler generated library calls. */
5118 if (mode == VOIDmode)
5121 && (cum->call_cookie & CALL_LIBCALL) == 0
5123 || (cum->nargs_prototype < 0
5124 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5126 /* For the SPE, we need to crxor CR6 always. */
5128 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5129 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5130 return GEN_INT (cum->call_cookie
5131 | ((cum->fregno == FP_ARG_MIN_REG)
5132 ? CALL_V4_SET_FP_ARGS
5133 : CALL_V4_CLEAR_FP_ARGS));
5136 return GEN_INT (cum->call_cookie);
5139 if (rs6000_darwin64_abi && mode == BLKmode
5140 && TREE_CODE (type) == RECORD_TYPE)
5142 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5143 if (rslt != NULL_RTX)
5145 /* Else fall through to usual handling. */
5148 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5149 if (TARGET_64BIT && ! cum->prototype)
5151 /* Vector parameters get passed in vector register
5152 and also in GPRs or memory, in absence of prototype. */
5155 align_words = (cum->words + 1) & ~1;
5157 if (align_words >= GP_ARG_NUM_REG)
5163 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5165 return gen_rtx_PARALLEL (mode,
5167 gen_rtx_EXPR_LIST (VOIDmode,
5169 gen_rtx_EXPR_LIST (VOIDmode,
5170 gen_rtx_REG (mode, cum->vregno),
5174 return gen_rtx_REG (mode, cum->vregno);
5175 else if (TARGET_ALTIVEC_ABI
5176 && (ALTIVEC_VECTOR_MODE (mode)
5177 || (type && TREE_CODE (type) == VECTOR_TYPE
5178 && int_size_in_bytes (type) == 16)))
5180 if (named || abi == ABI_V4)
5184 /* Vector parameters to varargs functions under AIX or Darwin
5185 get passed in memory and possibly also in GPRs. */
5186 int align, align_words, n_words;
5187 enum machine_mode part_mode;
5189 /* Vector parameters must be 16-byte aligned. This places them at
5190 2 mod 4 in terms of words in 32-bit mode, since the parameter
5191 save area starts at offset 24 from the stack. In 64-bit mode,
5192 they just have to start on an even word, since the parameter
5193 save area is 16-byte aligned. */
5195 align = (2 - cum->words) & 3;
5197 align = cum->words & 1;
5198 align_words = cum->words + align;
5200 /* Out of registers? Memory, then. */
5201 if (align_words >= GP_ARG_NUM_REG)
5204 if (TARGET_32BIT && TARGET_POWERPC64)
5205 return rs6000_mixed_function_arg (mode, type, align_words);
5207 /* The vector value goes in GPRs. Only the part of the
5208 value in GPRs is reported here. */
5210 n_words = rs6000_arg_size (mode, type);
5211 if (align_words + n_words > GP_ARG_NUM_REG)
5212 /* Fortunately, there are only two possibilities, the value
5213 is either wholly in GPRs or half in GPRs and half not. */
5216 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5219 else if (TARGET_SPE_ABI && TARGET_SPE
5220 && (SPE_VECTOR_MODE (mode)
5221 || (TARGET_E500_DOUBLE && (mode == DFmode
5222 || mode == DCmode))))
5223 return rs6000_spe_function_arg (cum, mode, type);
5225 else if (abi == ABI_V4)
5227 if (TARGET_HARD_FLOAT && TARGET_FPRS
5228 && (mode == SFmode || mode == DFmode
5229 || (mode == TFmode && !TARGET_IEEEQUAD)))
5231 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5232 return gen_rtx_REG (mode, cum->fregno);
5238 int n_words = rs6000_arg_size (mode, type);
5239 int gregno = cum->sysv_gregno;
5241 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5242 (r7,r8) or (r9,r10). As does any other 2 word item such
5243 as complex int due to a historical mistake. */
5245 gregno += (1 - gregno) & 1;
5247 /* Multi-reg args are not split between registers and stack. */
5248 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5251 if (TARGET_32BIT && TARGET_POWERPC64)
5252 return rs6000_mixed_function_arg (mode, type,
5253 gregno - GP_ARG_MIN_REG);
5254 return gen_rtx_REG (mode, gregno);
5259 int align_words = rs6000_parm_start (mode, type, cum->words);
5261 if (USE_FP_FOR_ARG_P (cum, mode, type))
5263 rtx rvec[GP_ARG_NUM_REG + 1];
5267 enum machine_mode fmode = mode;
5268 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5270 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5272 /* Currently, we only ever need one reg here because complex
5273 doubles are split. */
5274 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5276 /* Long double split over regs and memory. */
5280 /* Do we also need to pass this arg in the parameter save
5283 && (cum->nargs_prototype <= 0
5284 || (DEFAULT_ABI == ABI_AIX
5286 && align_words >= GP_ARG_NUM_REG)));
5288 if (!needs_psave && mode == fmode)
5289 return gen_rtx_REG (fmode, cum->fregno);
5294 /* Describe the part that goes in gprs or the stack.
5295 This piece must come first, before the fprs. */
5296 if (align_words < GP_ARG_NUM_REG)
5298 unsigned long n_words = rs6000_arg_size (mode, type);
5300 if (align_words + n_words > GP_ARG_NUM_REG
5301 || (TARGET_32BIT && TARGET_POWERPC64))
5303 /* If this is partially on the stack, then we only
5304 include the portion actually in registers here. */
5305 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5308 if (align_words + n_words > GP_ARG_NUM_REG
5309 && (TARGET_32BIT && TARGET_POWERPC64))
5310 /* Not all of the arg fits in gprs. Say that it
5311 goes in memory too, using a magic NULL_RTX
5312 component. Also see comment in
5313 rs6000_mixed_function_arg for why the normal
5314 function_arg_partial_nregs scheme doesn't work
5316 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5320 r = gen_rtx_REG (rmode,
5321 GP_ARG_MIN_REG + align_words);
5322 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5323 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5325 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5329 /* The whole arg fits in gprs. */
5330 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5331 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5335 /* It's entirely in memory. */
5336 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5339 /* Describe where this piece goes in the fprs. */
5340 r = gen_rtx_REG (fmode, cum->fregno);
5341 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5343 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5345 else if (align_words < GP_ARG_NUM_REG)
5347 if (TARGET_32BIT && TARGET_POWERPC64)
5348 return rs6000_mixed_function_arg (mode, type, align_words);
5350 if (mode == BLKmode)
5353 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5360 /* For an arg passed partly in registers and partly in memory, this is
5361 the number of bytes passed in registers. For args passed entirely in
5362 registers or entirely in memory, zero. When an arg is described by a
5363 PARALLEL, perhaps using more than one register type, this function
5364 returns the number of bytes used by the first element of the PARALLEL. */
5367 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5368 tree type, bool named)
5373 if (DEFAULT_ABI == ABI_V4)
5376 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5377 && cum->nargs_prototype >= 0)
5380 /* In this complicated case we just disable the partial_nregs code. */
5381 if (rs6000_darwin64_abi && mode == BLKmode
5382 && TREE_CODE (type) == RECORD_TYPE
5383 && int_size_in_bytes (type) > 0)
5386 align_words = rs6000_parm_start (mode, type, cum->words);
5388 if (USE_FP_FOR_ARG_P (cum, mode, type)
5389 /* If we are passing this arg in the fixed parameter save area
5390 (gprs or memory) as well as fprs, then this function should
5391 return the number of bytes passed in the parameter save area
5392 rather than bytes passed in fprs. */
5394 && (cum->nargs_prototype <= 0
5395 || (DEFAULT_ABI == ABI_AIX
5397 && align_words >= GP_ARG_NUM_REG))))
5399 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5400 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5401 else if (cum->nargs_prototype >= 0)
5405 if (align_words < GP_ARG_NUM_REG
5406 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5407 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5409 if (ret != 0 && TARGET_DEBUG_ARG)
5410 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5415 /* A C expression that indicates when an argument must be passed by
5416 reference. If nonzero for an argument, a copy of that argument is
5417 made in memory and a pointer to the argument is passed instead of
5418 the argument itself. The pointer is passed in whatever way is
5419 appropriate for passing a pointer to that type.
5421 Under V.4, aggregates and long double are passed by reference.
5423 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5424 reference unless the AltiVec vector extension ABI is in force.
5426 As an extension to all ABIs, variable sized types are passed by
5430 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5431 enum machine_mode mode, tree type,
5432 bool named ATTRIBUTE_UNUSED)
5434 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5436 if (TARGET_DEBUG_ARG)
5437 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5444 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5446 if (TARGET_DEBUG_ARG)
5447 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5451 if (int_size_in_bytes (type) < 0)
5453 if (TARGET_DEBUG_ARG)
5454 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5458 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5459 modes only exist for GCC vector types if -maltivec. */
5460 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5462 if (TARGET_DEBUG_ARG)
5463 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5467 /* Pass synthetic vectors in memory. */
5468 if (TREE_CODE (type) == VECTOR_TYPE
5469 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5471 static bool warned_for_pass_big_vectors = false;
5472 if (TARGET_DEBUG_ARG)
5473 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5474 if (!warned_for_pass_big_vectors)
5476 warning (0, "GCC vector passed by reference: "
5477 "non-standard ABI extension with no compatibility guarantee");
5478 warned_for_pass_big_vectors = true;
5487 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5490 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5495 for (i = 0; i < nregs; i++)
5497 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5498 if (reload_completed)
5500 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5503 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5504 i * GET_MODE_SIZE (reg_mode));
5507 tem = replace_equiv_address (tem, XEXP (tem, 0));
5511 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5515 /* Perform any needed actions needed for a function that is receiving a
5516 variable number of arguments.
5520 MODE and TYPE are the mode and type of the current parameter.
5522 PRETEND_SIZE is a variable that should be set to the amount of stack
5523 that must be pushed by the prolog to pretend that our caller pushed
5526 Normally, this macro will push all remaining incoming registers on the
5527 stack and set PRETEND_SIZE to the length of the registers pushed. */
5530 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5531 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5534 CUMULATIVE_ARGS next_cum;
5535 int reg_size = TARGET_32BIT ? 4 : 8;
5536 rtx save_area = NULL_RTX, mem;
5537 int first_reg_offset, set;
5539 /* Skip the last named argument. */
5541 function_arg_advance (&next_cum, mode, type, 1, 0);
5543 if (DEFAULT_ABI == ABI_V4)
5545 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5549 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5550 HOST_WIDE_INT offset = 0;
5552 /* Try to optimize the size of the varargs save area.
5553 The ABI requires that ap.reg_save_area is doubleword
5554 aligned, but we don't need to allocate space for all
5555 the bytes, only those to which we actually will save
5557 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5558 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5559 if (TARGET_HARD_FLOAT && TARGET_FPRS
5560 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5561 && cfun->va_list_fpr_size)
5564 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5565 * UNITS_PER_FP_WORD;
5566 if (cfun->va_list_fpr_size
5567 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5568 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5570 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5571 * UNITS_PER_FP_WORD;
5575 offset = -((first_reg_offset * reg_size) & ~7);
5576 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5578 gpr_reg_num = cfun->va_list_gpr_size;
5579 if (reg_size == 4 && (first_reg_offset & 1))
5582 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5585 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5587 - (int) (GP_ARG_NUM_REG * reg_size);
5589 if (gpr_size + fpr_size)
5592 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5593 gcc_assert (GET_CODE (reg_save_area) == MEM);
5594 reg_save_area = XEXP (reg_save_area, 0);
5595 if (GET_CODE (reg_save_area) == PLUS)
5597 gcc_assert (XEXP (reg_save_area, 0)
5598 == virtual_stack_vars_rtx);
5599 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5600 offset += INTVAL (XEXP (reg_save_area, 1));
5603 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5606 cfun->machine->varargs_save_offset = offset;
5607 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5612 first_reg_offset = next_cum.words;
5613 save_area = virtual_incoming_args_rtx;
5615 if (targetm.calls.must_pass_in_stack (mode, type))
5616 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5619 set = get_varargs_alias_set ();
5620 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5621 && cfun->va_list_gpr_size)
5623 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5625 if (va_list_gpr_counter_field)
5627 /* V4 va_list_gpr_size counts number of registers needed. */
5628 if (nregs > cfun->va_list_gpr_size)
5629 nregs = cfun->va_list_gpr_size;
5633 /* char * va_list instead counts number of bytes needed. */
5634 if (nregs > cfun->va_list_gpr_size / reg_size)
5635 nregs = cfun->va_list_gpr_size / reg_size;
5638 mem = gen_rtx_MEM (BLKmode,
5639 plus_constant (save_area,
5640 first_reg_offset * reg_size));
5641 MEM_NOTRAP_P (mem) = 1;
5642 set_mem_alias_set (mem, set);
5643 set_mem_align (mem, BITS_PER_WORD);
5645 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5649 /* Save FP registers if needed. */
5650 if (DEFAULT_ABI == ABI_V4
5651 && TARGET_HARD_FLOAT && TARGET_FPRS
5653 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5654 && cfun->va_list_fpr_size)
5656 int fregno = next_cum.fregno, nregs;
5657 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5658 rtx lab = gen_label_rtx ();
5659 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5660 * UNITS_PER_FP_WORD);
5663 (gen_rtx_SET (VOIDmode,
5665 gen_rtx_IF_THEN_ELSE (VOIDmode,
5666 gen_rtx_NE (VOIDmode, cr1,
5668 gen_rtx_LABEL_REF (VOIDmode, lab),
5672 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5673 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5675 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5676 MEM_NOTRAP_P (mem) = 1;
5677 set_mem_alias_set (mem, set);
5678 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5679 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5686 /* Create the va_list data type. */
5689 rs6000_build_builtin_va_list (void)
5691 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5693 /* For AIX, prefer 'char *' because that's what the system
5694 header files like. */
5695 if (DEFAULT_ABI != ABI_V4)
5696 return build_pointer_type (char_type_node);
5698 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5699 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5701 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5702 unsigned_char_type_node);
5703 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5704 unsigned_char_type_node);
5705 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5707 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5708 short_unsigned_type_node);
5709 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5711 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5714 va_list_gpr_counter_field = f_gpr;
5715 va_list_fpr_counter_field = f_fpr;
5717 DECL_FIELD_CONTEXT (f_gpr) = record;
5718 DECL_FIELD_CONTEXT (f_fpr) = record;
5719 DECL_FIELD_CONTEXT (f_res) = record;
5720 DECL_FIELD_CONTEXT (f_ovf) = record;
5721 DECL_FIELD_CONTEXT (f_sav) = record;
5723 TREE_CHAIN (record) = type_decl;
5724 TYPE_NAME (record) = type_decl;
5725 TYPE_FIELDS (record) = f_gpr;
5726 TREE_CHAIN (f_gpr) = f_fpr;
5727 TREE_CHAIN (f_fpr) = f_res;
5728 TREE_CHAIN (f_res) = f_ovf;
5729 TREE_CHAIN (f_ovf) = f_sav;
5731 layout_type (record);
5733 /* The correct type is an array type of one element. */
5734 return build_array_type (record, build_index_type (size_zero_node));
5737 /* Implement va_start. */
5740 rs6000_va_start (tree valist, rtx nextarg)
5742 HOST_WIDE_INT words, n_gpr, n_fpr;
5743 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5744 tree gpr, fpr, ovf, sav, t;
5746 /* Only SVR4 needs something special. */
5747 if (DEFAULT_ABI != ABI_V4)
5749 std_expand_builtin_va_start (valist, nextarg);
5753 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5754 f_fpr = TREE_CHAIN (f_gpr);
5755 f_res = TREE_CHAIN (f_fpr);
5756 f_ovf = TREE_CHAIN (f_res);
5757 f_sav = TREE_CHAIN (f_ovf);
5759 valist = build_va_arg_indirect_ref (valist);
5760 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5761 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5762 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5763 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5765 /* Count number of gp and fp argument registers used. */
5766 words = current_function_args_info.words;
5767 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5769 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5772 if (TARGET_DEBUG_ARG)
5773 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5774 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5775 words, n_gpr, n_fpr);
5777 if (cfun->va_list_gpr_size)
5779 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5780 build_int_cst (NULL_TREE, n_gpr));
5781 TREE_SIDE_EFFECTS (t) = 1;
5782 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5785 if (cfun->va_list_fpr_size)
5787 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5788 build_int_cst (NULL_TREE, n_fpr));
5789 TREE_SIDE_EFFECTS (t) = 1;
5790 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5793 /* Find the overflow area. */
5794 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5796 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5797 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5798 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5799 TREE_SIDE_EFFECTS (t) = 1;
5800 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5802 /* If there were no va_arg invocations, don't set up the register
5804 if (!cfun->va_list_gpr_size
5805 && !cfun->va_list_fpr_size
5806 && n_gpr < GP_ARG_NUM_REG
5807 && n_fpr < FP_ARG_V4_MAX_REG)
5810 /* Find the register save area. */
5811 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5812 if (cfun->machine->varargs_save_offset)
5813 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5814 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5815 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5816 TREE_SIDE_EFFECTS (t) = 1;
5817 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5820 /* Implement va_arg. */
5823 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5825 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5826 tree gpr, fpr, ovf, sav, reg, t, u;
5827 int size, rsize, n_reg, sav_ofs, sav_scale;
5828 tree lab_false, lab_over, addr;
5830 tree ptrtype = build_pointer_type (type);
5832 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5834 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5835 return build_va_arg_indirect_ref (t);
5838 if (DEFAULT_ABI != ABI_V4)
5840 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5842 tree elem_type = TREE_TYPE (type);
5843 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5844 int elem_size = GET_MODE_SIZE (elem_mode);
5846 if (elem_size < UNITS_PER_WORD)
5848 tree real_part, imag_part;
5849 tree post = NULL_TREE;
5851 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5853 /* Copy the value into a temporary, lest the formal temporary
5854 be reused out from under us. */
5855 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5856 append_to_statement_list (post, pre_p);
5858 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5861 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5865 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5868 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5869 f_fpr = TREE_CHAIN (f_gpr);
5870 f_res = TREE_CHAIN (f_fpr);
5871 f_ovf = TREE_CHAIN (f_res);
5872 f_sav = TREE_CHAIN (f_ovf);
5874 valist = build_va_arg_indirect_ref (valist);
5875 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5876 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5877 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5878 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5880 size = int_size_in_bytes (type);
5881 rsize = (size + 3) / 4;
5884 if (TARGET_HARD_FLOAT && TARGET_FPRS
5885 && (TYPE_MODE (type) == SFmode
5886 || TYPE_MODE (type) == DFmode
5887 || TYPE_MODE (type) == TFmode))
5889 /* FP args go in FP registers, if present. */
5891 n_reg = (size + 7) / 8;
5894 if (TYPE_MODE (type) != SFmode)
5899 /* Otherwise into GP registers. */
5908 /* Pull the value out of the saved registers.... */
5911 addr = create_tmp_var (ptr_type_node, "addr");
5912 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5914 /* AltiVec vectors never go in registers when -mabi=altivec. */
5915 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5919 lab_false = create_artificial_label ();
5920 lab_over = create_artificial_label ();
5922 /* Long long and SPE vectors are aligned in the registers.
5923 As are any other 2 gpr item such as complex int due to a
5924 historical mistake. */
5926 if (n_reg == 2 && reg == gpr)
5928 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5929 size_int (n_reg - 1));
5930 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5933 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5934 t = build2 (GE_EXPR, boolean_type_node, u, t);
5935 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5936 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5937 gimplify_and_add (t, pre_p);
5941 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5943 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5944 u = build1 (CONVERT_EXPR, integer_type_node, u);
5945 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5946 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5948 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5949 gimplify_and_add (t, pre_p);
5951 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5952 gimplify_and_add (t, pre_p);
5954 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5955 append_to_statement_list (t, pre_p);
5959 /* Ensure that we don't find any more args in regs.
5960 Alignment has taken care of the n_reg == 2 case. */
5961 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5962 gimplify_and_add (t, pre_p);
5966 /* ... otherwise out of the overflow area. */
5968 /* Care for on-stack alignment if needed. */
5972 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5973 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5974 build_int_cst (NULL_TREE, -align));
5976 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5978 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5979 gimplify_and_add (u, pre_p);
5981 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5982 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5983 gimplify_and_add (t, pre_p);
5987 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5988 append_to_statement_list (t, pre_p);
5991 addr = fold_convert (ptrtype, addr);
5992 return build_va_arg_indirect_ref (addr);
5998 def_builtin (int mask, const char *name, tree type, int code)
6000 if (mask & target_flags)
6002 if (rs6000_builtin_decls[code])
6005 rs6000_builtin_decls[code] =
6006 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
6011 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6013 static const struct builtin_description bdesc_3arg[] =
6015 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6017 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6019 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6020 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6021 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6025 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6026 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6027 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6028 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6029 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6030 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6031 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6032 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6033 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6034 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6035 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6036 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6037 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6039 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6040 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6041 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6042 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6043 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6044 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6045 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6046 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6047 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6048 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6049 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6050 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6051 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6052 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6053 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6056 /* DST operations: void foo (void *, const int, const char). */
6058 static const struct builtin_description bdesc_dst[] =
6060 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6061 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6062 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6063 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6065 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6066 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6067 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6068 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6071 /* Simple binary operations: VECc = foo (VECa, VECb). */
6073 static struct builtin_description bdesc_2arg[] =
6075 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6076 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6077 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6078 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6079 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6080 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6081 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6082 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6083 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6084 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6086 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6087 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6088 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6094 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6096 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6097 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6099 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6100 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6101 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6102 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6103 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6104 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6105 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6106 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6107 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6108 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6109 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6110 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6111 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6112 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6113 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6114 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6115 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6116 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6117 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6118 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6119 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6120 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6121 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6122 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6123 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6124 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6125 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6126 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6127 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6128 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6129 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6130 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6131 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6132 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6133 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6134 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6136 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6140 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6142 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6143 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6145 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6146 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6147 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6148 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6149 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6150 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6151 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6152 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6153 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6154 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6155 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6156 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6157 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6158 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6159 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6160 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6161 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6162 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6163 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6164 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6165 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6166 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6167 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6168 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6169 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6170 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6171 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6172 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6173 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6174 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6175 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6176 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6177 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6178 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6179 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6180 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6181 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6182 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6183 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6184 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6185 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6312 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6313 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6315 /* Place holder, leave as first spe builtin. */
6316 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6317 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6318 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6319 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6320 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6321 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6322 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6323 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6324 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6325 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6326 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6327 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6328 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6329 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6330 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6331 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6332 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6333 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6334 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6335 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6336 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6337 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6338 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6339 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6340 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6341 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6342 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6343 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6344 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6345 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6346 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6347 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6348 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6349 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6350 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6351 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6352 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6353 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6354 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6355 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6356 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6357 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6358 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6359 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6360 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6361 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6362 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6363 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6364 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6365 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6366 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6367 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6368 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6369 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6370 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6371 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6372 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6373 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6374 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6375 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6376 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6377 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6378 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6379 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6380 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6381 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6382 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6383 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6384 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6385 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6386 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6387 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6388 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6389 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6390 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6391 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6392 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6393 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6394 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6395 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6396 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6397 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6398 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6399 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6400 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6401 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6402 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6403 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6404 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6405 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6406 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6407 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6408 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6409 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6410 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6411 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6412 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6413 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6414 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6415 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6416 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6417 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6418 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6419 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6420 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6421 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6422 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6423 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6424 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6426 /* SPE binary operations expecting a 5-bit unsigned literal. */
6427 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6429 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6430 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6431 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6432 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6433 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6434 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6435 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6436 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6437 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6438 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6439 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6440 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6441 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6442 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6443 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6444 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6445 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6446 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6447 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6448 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6449 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6450 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6451 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6452 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6453 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6454 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6456 /* Place-holder. Leave as last binary SPE builtin. */
6457 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6460 /* AltiVec predicates. */
6462 struct builtin_description_predicates
6464 const unsigned int mask;
6465 const enum insn_code icode;
6467 const char *const name;
6468 const enum rs6000_builtins code;
6471 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6473 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6474 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6475 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6476 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6477 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6478 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6479 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6480 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6481 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6482 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6483 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6484 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6485 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6487 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6488 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6489 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6492 /* SPE predicates. */
6493 static struct builtin_description bdesc_spe_predicates[] =
6495 /* Place-holder. Leave as first. */
6496 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6497 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6498 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6499 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6500 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6501 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6502 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6503 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6504 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6505 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6506 /* Place-holder. Leave as last. */
6507 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6510 /* SPE evsel predicates. */
6511 static struct builtin_description bdesc_spe_evsel[] =
6513 /* Place-holder. Leave as first. */
6514 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6515 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6516 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6517 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6518 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6519 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6520 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6521 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6522 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6523 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6524 /* Place-holder. Leave as last. */
6525 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6528 /* ABS* operations. */
6530 static const struct builtin_description bdesc_abs[] =
6532 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6533 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6534 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6535 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6536 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6537 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6538 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6541 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6544 static struct builtin_description bdesc_1arg[] =
6546 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6547 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6548 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6549 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6550 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6551 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6552 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6553 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6554 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6555 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6556 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6557 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6558 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6559 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6560 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6561 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6562 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6564 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6565 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6566 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6567 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6568 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6569 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6570 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6571 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6572 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6573 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6574 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6575 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6576 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6577 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6578 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6579 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6580 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6581 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6582 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6584 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6585 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6586 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6587 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6588 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6589 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6590 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6591 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6592 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6593 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6594 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6595 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6596 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6597 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6598 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6599 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6600 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6601 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6602 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6603 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6604 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6605 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6606 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6607 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6608 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6609 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6610 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6611 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6612 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6613 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6615 /* Place-holder. Leave as last unary SPE builtin. */
6616 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6620 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6623 tree arg0 = TREE_VALUE (arglist);
6624 rtx op0 = expand_normal (arg0);
6625 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6626 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6628 if (icode == CODE_FOR_nothing)
6629 /* Builtin not supported on this processor. */
6632 /* If we got invalid arguments bail out before generating bad rtl. */
6633 if (arg0 == error_mark_node)
6636 if (icode == CODE_FOR_altivec_vspltisb
6637 || icode == CODE_FOR_altivec_vspltish
6638 || icode == CODE_FOR_altivec_vspltisw
6639 || icode == CODE_FOR_spe_evsplatfi
6640 || icode == CODE_FOR_spe_evsplati)
6642 /* Only allow 5-bit *signed* literals. */
6643 if (GET_CODE (op0) != CONST_INT
6644 || INTVAL (op0) > 15
6645 || INTVAL (op0) < -16)
6647 error ("argument 1 must be a 5-bit signed literal");
6653 || GET_MODE (target) != tmode
6654 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6655 target = gen_reg_rtx (tmode);
6657 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6658 op0 = copy_to_mode_reg (mode0, op0);
6660 pat = GEN_FCN (icode) (target, op0);
6669 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6671 rtx pat, scratch1, scratch2;
6672 tree arg0 = TREE_VALUE (arglist);
6673 rtx op0 = expand_normal (arg0);
6674 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6675 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6677 /* If we have invalid arguments, bail out before generating bad rtl. */
6678 if (arg0 == error_mark_node)
6682 || GET_MODE (target) != tmode
6683 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6684 target = gen_reg_rtx (tmode);
6686 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6687 op0 = copy_to_mode_reg (mode0, op0);
6689 scratch1 = gen_reg_rtx (mode0);
6690 scratch2 = gen_reg_rtx (mode0);
6692 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6701 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6704 tree arg0 = TREE_VALUE (arglist);
6705 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6706 rtx op0 = expand_normal (arg0);
6707 rtx op1 = expand_normal (arg1);
6708 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6709 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6710 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6712 if (icode == CODE_FOR_nothing)
6713 /* Builtin not supported on this processor. */
6716 /* If we got invalid arguments bail out before generating bad rtl. */
6717 if (arg0 == error_mark_node || arg1 == error_mark_node)
6720 if (icode == CODE_FOR_altivec_vcfux
6721 || icode == CODE_FOR_altivec_vcfsx
6722 || icode == CODE_FOR_altivec_vctsxs
6723 || icode == CODE_FOR_altivec_vctuxs
6724 || icode == CODE_FOR_altivec_vspltb
6725 || icode == CODE_FOR_altivec_vsplth
6726 || icode == CODE_FOR_altivec_vspltw
6727 || icode == CODE_FOR_spe_evaddiw
6728 || icode == CODE_FOR_spe_evldd
6729 || icode == CODE_FOR_spe_evldh
6730 || icode == CODE_FOR_spe_evldw
6731 || icode == CODE_FOR_spe_evlhhesplat
6732 || icode == CODE_FOR_spe_evlhhossplat
6733 || icode == CODE_FOR_spe_evlhhousplat
6734 || icode == CODE_FOR_spe_evlwhe
6735 || icode == CODE_FOR_spe_evlwhos
6736 || icode == CODE_FOR_spe_evlwhou
6737 || icode == CODE_FOR_spe_evlwhsplat
6738 || icode == CODE_FOR_spe_evlwwsplat
6739 || icode == CODE_FOR_spe_evrlwi
6740 || icode == CODE_FOR_spe_evslwi
6741 || icode == CODE_FOR_spe_evsrwis
6742 || icode == CODE_FOR_spe_evsubifw
6743 || icode == CODE_FOR_spe_evsrwiu)
6745 /* Only allow 5-bit unsigned literals. */
6747 if (TREE_CODE (arg1) != INTEGER_CST
6748 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6750 error ("argument 2 must be a 5-bit unsigned literal");
6756 || GET_MODE (target) != tmode
6757 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6758 target = gen_reg_rtx (tmode);
6760 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6761 op0 = copy_to_mode_reg (mode0, op0);
6762 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6763 op1 = copy_to_mode_reg (mode1, op1);
6765 pat = GEN_FCN (icode) (target, op0, op1);
6774 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6775 tree arglist, rtx target)
6778 tree cr6_form = TREE_VALUE (arglist);
6779 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6780 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6781 rtx op0 = expand_normal (arg0);
6782 rtx op1 = expand_normal (arg1);
6783 enum machine_mode tmode = SImode;
6784 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6785 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6788 if (TREE_CODE (cr6_form) != INTEGER_CST)
6790 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6794 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6796 gcc_assert (mode0 == mode1);
6798 /* If we have invalid arguments, bail out before generating bad rtl. */
6799 if (arg0 == error_mark_node || arg1 == error_mark_node)
6803 || GET_MODE (target) != tmode
6804 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6805 target = gen_reg_rtx (tmode);
6807 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6808 op0 = copy_to_mode_reg (mode0, op0);
6809 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6810 op1 = copy_to_mode_reg (mode1, op1);
6812 scratch = gen_reg_rtx (mode0);
6814 pat = GEN_FCN (icode) (scratch, op0, op1,
6815 gen_rtx_SYMBOL_REF (Pmode, opcode));
6820 /* The vec_any* and vec_all* predicates use the same opcodes for two
6821 different operations, but the bits in CR6 will be different
6822 depending on what information we want. So we have to play tricks
6823 with CR6 to get the right bits out.
6825 If you think this is disgusting, look at the specs for the
6826 AltiVec predicates. */
6828 switch (cr6_form_int)
6831 emit_insn (gen_cr6_test_for_zero (target));
6834 emit_insn (gen_cr6_test_for_zero_reverse (target));
6837 emit_insn (gen_cr6_test_for_lt (target));
6840 emit_insn (gen_cr6_test_for_lt_reverse (target));
6843 error ("argument 1 of __builtin_altivec_predicate is out of range");
6851 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6854 tree arg0 = TREE_VALUE (arglist);
6855 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6856 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6857 enum machine_mode mode0 = Pmode;
6858 enum machine_mode mode1 = Pmode;
6859 rtx op0 = expand_normal (arg0);
6860 rtx op1 = expand_normal (arg1);
6862 if (icode == CODE_FOR_nothing)
6863 /* Builtin not supported on this processor. */
6866 /* If we got invalid arguments bail out before generating bad rtl. */
6867 if (arg0 == error_mark_node || arg1 == error_mark_node)
6871 || GET_MODE (target) != tmode
6872 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6873 target = gen_reg_rtx (tmode);
6875 op1 = copy_to_mode_reg (mode1, op1);
6877 if (op0 == const0_rtx)
6879 addr = gen_rtx_MEM (tmode, op1);
6883 op0 = copy_to_mode_reg (mode0, op0);
6884 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6887 pat = GEN_FCN (icode) (target, addr);
6897 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6899 tree arg0 = TREE_VALUE (arglist);
6900 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6901 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6902 rtx op0 = expand_normal (arg0);
6903 rtx op1 = expand_normal (arg1);
6904 rtx op2 = expand_normal (arg2);
6906 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6907 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6908 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6910 /* Invalid arguments. Bail before doing anything stoopid! */
6911 if (arg0 == error_mark_node
6912 || arg1 == error_mark_node
6913 || arg2 == error_mark_node)
6916 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6917 op0 = copy_to_mode_reg (mode2, op0);
6918 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6919 op1 = copy_to_mode_reg (mode0, op1);
6920 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6921 op2 = copy_to_mode_reg (mode1, op2);
6923 pat = GEN_FCN (icode) (op1, op2, op0);
6930 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6932 tree arg0 = TREE_VALUE (arglist);
6933 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6934 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6935 rtx op0 = expand_normal (arg0);
6936 rtx op1 = expand_normal (arg1);
6937 rtx op2 = expand_normal (arg2);
6939 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6940 enum machine_mode mode1 = Pmode;
6941 enum machine_mode mode2 = Pmode;
6943 /* Invalid arguments. Bail before doing anything stoopid! */
6944 if (arg0 == error_mark_node
6945 || arg1 == error_mark_node
6946 || arg2 == error_mark_node)
6949 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6950 op0 = copy_to_mode_reg (tmode, op0);
6952 op2 = copy_to_mode_reg (mode2, op2);
6954 if (op1 == const0_rtx)
6956 addr = gen_rtx_MEM (tmode, op2);
6960 op1 = copy_to_mode_reg (mode1, op1);
6961 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6964 pat = GEN_FCN (icode) (addr, op0);
6971 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6974 tree arg0 = TREE_VALUE (arglist);
6975 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6976 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6977 rtx op0 = expand_normal (arg0);
6978 rtx op1 = expand_normal (arg1);
6979 rtx op2 = expand_normal (arg2);
6980 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6981 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6982 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6983 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6985 if (icode == CODE_FOR_nothing)
6986 /* Builtin not supported on this processor. */
6989 /* If we got invalid arguments bail out before generating bad rtl. */
6990 if (arg0 == error_mark_node
6991 || arg1 == error_mark_node
6992 || arg2 == error_mark_node)
6995 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6996 || icode == CODE_FOR_altivec_vsldoi_v4si
6997 || icode == CODE_FOR_altivec_vsldoi_v8hi
6998 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7000 /* Only allow 4-bit unsigned literals. */
7002 if (TREE_CODE (arg2) != INTEGER_CST
7003 || TREE_INT_CST_LOW (arg2) & ~0xf)
7005 error ("argument 3 must be a 4-bit unsigned literal");
7011 || GET_MODE (target) != tmode
7012 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7013 target = gen_reg_rtx (tmode);
7015 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7016 op0 = copy_to_mode_reg (mode0, op0);
7017 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7018 op1 = copy_to_mode_reg (mode1, op1);
7019 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7020 op2 = copy_to_mode_reg (mode2, op2);
7022 pat = GEN_FCN (icode) (target, op0, op1, op2);
7030 /* Expand the lvx builtins. */
7032 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7034 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7035 tree arglist = TREE_OPERAND (exp, 1);
7036 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7038 enum machine_mode tmode, mode0;
7040 enum insn_code icode;
7044 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7045 icode = CODE_FOR_altivec_lvx_v16qi;
7047 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7048 icode = CODE_FOR_altivec_lvx_v8hi;
7050 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7051 icode = CODE_FOR_altivec_lvx_v4si;
7053 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7054 icode = CODE_FOR_altivec_lvx_v4sf;
7063 arg0 = TREE_VALUE (arglist);
7064 op0 = expand_normal (arg0);
7065 tmode = insn_data[icode].operand[0].mode;
7066 mode0 = insn_data[icode].operand[1].mode;
7069 || GET_MODE (target) != tmode
7070 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7071 target = gen_reg_rtx (tmode);
7073 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7074 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7076 pat = GEN_FCN (icode) (target, op0);
7083 /* Expand the stvx builtins. */
7085 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7088 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7089 tree arglist = TREE_OPERAND (exp, 1);
7090 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7092 enum machine_mode mode0, mode1;
7094 enum insn_code icode;
7098 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7099 icode = CODE_FOR_altivec_stvx_v16qi;
7101 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7102 icode = CODE_FOR_altivec_stvx_v8hi;
7104 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7105 icode = CODE_FOR_altivec_stvx_v4si;
7107 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7108 icode = CODE_FOR_altivec_stvx_v4sf;
7115 arg0 = TREE_VALUE (arglist);
7116 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7117 op0 = expand_normal (arg0);
7118 op1 = expand_normal (arg1);
7119 mode0 = insn_data[icode].operand[0].mode;
7120 mode1 = insn_data[icode].operand[1].mode;
7122 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7123 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7124 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7125 op1 = copy_to_mode_reg (mode1, op1);
7127 pat = GEN_FCN (icode) (op0, op1);
7135 /* Expand the dst builtins. */
7137 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7140 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7141 tree arglist = TREE_OPERAND (exp, 1);
7142 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7143 tree arg0, arg1, arg2;
7144 enum machine_mode mode0, mode1, mode2;
7145 rtx pat, op0, op1, op2;
7146 struct builtin_description *d;
7151 /* Handle DST variants. */
7152 d = (struct builtin_description *) bdesc_dst;
7153 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7154 if (d->code == fcode)
7156 arg0 = TREE_VALUE (arglist);
7157 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7158 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7159 op0 = expand_normal (arg0);
7160 op1 = expand_normal (arg1);
7161 op2 = expand_normal (arg2);
7162 mode0 = insn_data[d->icode].operand[0].mode;
7163 mode1 = insn_data[d->icode].operand[1].mode;
7164 mode2 = insn_data[d->icode].operand[2].mode;
7166 /* Invalid arguments, bail out before generating bad rtl. */
7167 if (arg0 == error_mark_node
7168 || arg1 == error_mark_node
7169 || arg2 == error_mark_node)
7174 if (TREE_CODE (arg2) != INTEGER_CST
7175 || TREE_INT_CST_LOW (arg2) & ~0x3)
7177 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7181 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7182 op0 = copy_to_mode_reg (Pmode, op0);
7183 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7184 op1 = copy_to_mode_reg (mode1, op1);
7186 pat = GEN_FCN (d->icode) (op0, op1, op2);
7196 /* Expand vec_init builtin. */
7198 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7200 enum machine_mode tmode = TYPE_MODE (type);
7201 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7202 int i, n_elt = GET_MODE_NUNITS (tmode);
7203 rtvec v = rtvec_alloc (n_elt);
7205 gcc_assert (VECTOR_MODE_P (tmode));
7207 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7209 rtx x = expand_normal (TREE_VALUE (arglist));
7210 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7213 gcc_assert (arglist == NULL);
7215 if (!target || !register_operand (target, tmode))
7216 target = gen_reg_rtx (tmode);
7218 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7222 /* Return the integer constant in ARG. Constrain it to be in the range
7223 of the subparts of VEC_TYPE; issue an error if not. */
7226 get_element_number (tree vec_type, tree arg)
7228 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7230 if (!host_integerp (arg, 1)
7231 || (elt = tree_low_cst (arg, 1), elt > max))
7233 error ("selector must be an integer constant in the range 0..%wi", max);
7240 /* Expand vec_set builtin. */
7242 altivec_expand_vec_set_builtin (tree arglist)
7244 enum machine_mode tmode, mode1;
7245 tree arg0, arg1, arg2;
7249 arg0 = TREE_VALUE (arglist);
7250 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7251 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7253 tmode = TYPE_MODE (TREE_TYPE (arg0));
7254 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7255 gcc_assert (VECTOR_MODE_P (tmode));
7257 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7258 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7259 elt = get_element_number (TREE_TYPE (arg0), arg2);
7261 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7262 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7264 op0 = force_reg (tmode, op0);
7265 op1 = force_reg (mode1, op1);
7267 rs6000_expand_vector_set (op0, op1, elt);
7272 /* Expand vec_ext builtin. */
7274 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7276 enum machine_mode tmode, mode0;
7281 arg0 = TREE_VALUE (arglist);
7282 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7284 op0 = expand_normal (arg0);
7285 elt = get_element_number (TREE_TYPE (arg0), arg1);
7287 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7288 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7289 gcc_assert (VECTOR_MODE_P (mode0));
7291 op0 = force_reg (mode0, op0);
7293 if (optimize || !target || !register_operand (target, tmode))
7294 target = gen_reg_rtx (tmode);
7296 rs6000_expand_vector_extract (target, op0, elt);
7301 /* Expand the builtin in EXP and store the result in TARGET. Store
7302 true in *EXPANDEDP if we found a builtin to expand. */
7304 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7306 struct builtin_description *d;
7307 struct builtin_description_predicates *dp;
7309 enum insn_code icode;
7310 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7311 tree arglist = TREE_OPERAND (exp, 1);
7314 enum machine_mode tmode, mode0;
7315 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7317 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7318 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7321 error ("unresolved overload for Altivec builtin %qF", fndecl);
7325 target = altivec_expand_ld_builtin (exp, target, expandedp);
7329 target = altivec_expand_st_builtin (exp, target, expandedp);
7333 target = altivec_expand_dst_builtin (exp, target, expandedp);
7341 case ALTIVEC_BUILTIN_STVX:
7342 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7343 case ALTIVEC_BUILTIN_STVEBX:
7344 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7345 case ALTIVEC_BUILTIN_STVEHX:
7346 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7347 case ALTIVEC_BUILTIN_STVEWX:
7348 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7349 case ALTIVEC_BUILTIN_STVXL:
7350 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7352 case ALTIVEC_BUILTIN_MFVSCR:
7353 icode = CODE_FOR_altivec_mfvscr;
7354 tmode = insn_data[icode].operand[0].mode;
7357 || GET_MODE (target) != tmode
7358 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7359 target = gen_reg_rtx (tmode);
7361 pat = GEN_FCN (icode) (target);
7367 case ALTIVEC_BUILTIN_MTVSCR:
7368 icode = CODE_FOR_altivec_mtvscr;
7369 arg0 = TREE_VALUE (arglist);
7370 op0 = expand_normal (arg0);
7371 mode0 = insn_data[icode].operand[0].mode;
7373 /* If we got invalid arguments bail out before generating bad rtl. */
7374 if (arg0 == error_mark_node)
7377 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7378 op0 = copy_to_mode_reg (mode0, op0);
7380 pat = GEN_FCN (icode) (op0);
7385 case ALTIVEC_BUILTIN_DSSALL:
7386 emit_insn (gen_altivec_dssall ());
7389 case ALTIVEC_BUILTIN_DSS:
7390 icode = CODE_FOR_altivec_dss;
7391 arg0 = TREE_VALUE (arglist);
7393 op0 = expand_normal (arg0);
7394 mode0 = insn_data[icode].operand[0].mode;
7396 /* If we got invalid arguments bail out before generating bad rtl. */
7397 if (arg0 == error_mark_node)
7400 if (TREE_CODE (arg0) != INTEGER_CST
7401 || TREE_INT_CST_LOW (arg0) & ~0x3)
7403 error ("argument to dss must be a 2-bit unsigned literal");
7407 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7408 op0 = copy_to_mode_reg (mode0, op0);
7410 emit_insn (gen_altivec_dss (op0));
7413 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7414 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7415 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7416 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7417 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7419 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7420 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7421 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7422 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7423 return altivec_expand_vec_set_builtin (arglist);
7425 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7426 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7427 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7428 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7429 return altivec_expand_vec_ext_builtin (arglist, target);
7436 /* Expand abs* operations. */
7437 d = (struct builtin_description *) bdesc_abs;
7438 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7439 if (d->code == fcode)
7440 return altivec_expand_abs_builtin (d->icode, arglist, target);
7442 /* Expand the AltiVec predicates. */
7443 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7444 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7445 if (dp->code == fcode)
7446 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7449 /* LV* are funky. We initialized them differently. */
7452 case ALTIVEC_BUILTIN_LVSL:
7453 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7455 case ALTIVEC_BUILTIN_LVSR:
7456 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7458 case ALTIVEC_BUILTIN_LVEBX:
7459 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7461 case ALTIVEC_BUILTIN_LVEHX:
7462 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7464 case ALTIVEC_BUILTIN_LVEWX:
7465 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7467 case ALTIVEC_BUILTIN_LVXL:
7468 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7470 case ALTIVEC_BUILTIN_LVX:
7471 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7482 /* Binops that need to be initialized manually, but can be expanded
7483 automagically by rs6000_expand_binop_builtin. */
7484 static struct builtin_description bdesc_2arg_spe[] =
7486 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7487 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7488 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7489 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7490 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7491 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7492 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7493 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7494 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7495 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7496 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7497 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7498 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7499 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7500 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7501 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7502 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7503 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7504 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7505 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7506 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7507 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7510 /* Expand the builtin in EXP and store the result in TARGET. Store
7511 true in *EXPANDEDP if we found a builtin to expand.
7513 This expands the SPE builtins that are not simple unary and binary
7516 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7518 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7519 tree arglist = TREE_OPERAND (exp, 1);
7521 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7522 enum insn_code icode;
7523 enum machine_mode tmode, mode0;
7525 struct builtin_description *d;
7530 /* Syntax check for a 5-bit unsigned immediate. */
7533 case SPE_BUILTIN_EVSTDD:
7534 case SPE_BUILTIN_EVSTDH:
7535 case SPE_BUILTIN_EVSTDW:
7536 case SPE_BUILTIN_EVSTWHE:
7537 case SPE_BUILTIN_EVSTWHO:
7538 case SPE_BUILTIN_EVSTWWE:
7539 case SPE_BUILTIN_EVSTWWO:
7540 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7541 if (TREE_CODE (arg1) != INTEGER_CST
7542 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7544 error ("argument 2 must be a 5-bit unsigned literal");
7552 /* The evsplat*i instructions are not quite generic. */
7555 case SPE_BUILTIN_EVSPLATFI:
7556 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7558 case SPE_BUILTIN_EVSPLATI:
7559 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7565 d = (struct builtin_description *) bdesc_2arg_spe;
7566 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7567 if (d->code == fcode)
7568 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7570 d = (struct builtin_description *) bdesc_spe_predicates;
7571 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7572 if (d->code == fcode)
7573 return spe_expand_predicate_builtin (d->icode, arglist, target);
7575 d = (struct builtin_description *) bdesc_spe_evsel;
7576 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7577 if (d->code == fcode)
7578 return spe_expand_evsel_builtin (d->icode, arglist, target);
7582 case SPE_BUILTIN_EVSTDDX:
7583 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7584 case SPE_BUILTIN_EVSTDHX:
7585 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7586 case SPE_BUILTIN_EVSTDWX:
7587 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7588 case SPE_BUILTIN_EVSTWHEX:
7589 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7590 case SPE_BUILTIN_EVSTWHOX:
7591 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7592 case SPE_BUILTIN_EVSTWWEX:
7593 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7594 case SPE_BUILTIN_EVSTWWOX:
7595 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7596 case SPE_BUILTIN_EVSTDD:
7597 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7598 case SPE_BUILTIN_EVSTDH:
7599 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7600 case SPE_BUILTIN_EVSTDW:
7601 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7602 case SPE_BUILTIN_EVSTWHE:
7603 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7604 case SPE_BUILTIN_EVSTWHO:
7605 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7606 case SPE_BUILTIN_EVSTWWE:
7607 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7608 case SPE_BUILTIN_EVSTWWO:
7609 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7610 case SPE_BUILTIN_MFSPEFSCR:
7611 icode = CODE_FOR_spe_mfspefscr;
7612 tmode = insn_data[icode].operand[0].mode;
7615 || GET_MODE (target) != tmode
7616 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7617 target = gen_reg_rtx (tmode);
7619 pat = GEN_FCN (icode) (target);
7624 case SPE_BUILTIN_MTSPEFSCR:
7625 icode = CODE_FOR_spe_mtspefscr;
7626 arg0 = TREE_VALUE (arglist);
7627 op0 = expand_normal (arg0);
7628 mode0 = insn_data[icode].operand[0].mode;
7630 if (arg0 == error_mark_node)
7633 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7634 op0 = copy_to_mode_reg (mode0, op0);
7636 pat = GEN_FCN (icode) (op0);
7649 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7651 rtx pat, scratch, tmp;
7652 tree form = TREE_VALUE (arglist);
7653 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7654 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7655 rtx op0 = expand_normal (arg0);
7656 rtx op1 = expand_normal (arg1);
7657 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7658 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7662 if (TREE_CODE (form) != INTEGER_CST)
7664 error ("argument 1 of __builtin_spe_predicate must be a constant");
7668 form_int = TREE_INT_CST_LOW (form);
7670 gcc_assert (mode0 == mode1);
7672 if (arg0 == error_mark_node || arg1 == error_mark_node)
7676 || GET_MODE (target) != SImode
7677 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7678 target = gen_reg_rtx (SImode);
7680 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7681 op0 = copy_to_mode_reg (mode0, op0);
7682 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7683 op1 = copy_to_mode_reg (mode1, op1);
7685 scratch = gen_reg_rtx (CCmode);
7687 pat = GEN_FCN (icode) (scratch, op0, op1);
7692 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7693 _lower_. We use one compare, but look in different bits of the
7694 CR for each variant.
7696 There are 2 elements in each SPE simd type (upper/lower). The CR
7697 bits are set as follows:
7699 BIT0 | BIT 1 | BIT 2 | BIT 3
7700 U | L | (U | L) | (U & L)
7702 So, for an "all" relationship, BIT 3 would be set.
7703 For an "any" relationship, BIT 2 would be set. Etc.
7705 Following traditional nomenclature, these bits map to:
7707 BIT0 | BIT 1 | BIT 2 | BIT 3
7710 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7715 /* All variant. OV bit. */
7717 /* We need to get to the OV bit, which is the ORDERED bit. We
7718 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7719 that's ugly and will make validate_condition_mode die.
7720 So let's just use another pattern. */
7721 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7723 /* Any variant. EQ bit. */
7727 /* Upper variant. LT bit. */
7731 /* Lower variant. GT bit. */
7736 error ("argument 1 of __builtin_spe_predicate is out of range");
7740 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7741 emit_move_insn (target, tmp);
7746 /* The evsel builtins look like this:
7748 e = __builtin_spe_evsel_OP (a, b, c, d);
7752 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7753 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7757 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7760 tree arg0 = TREE_VALUE (arglist);
7761 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7762 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7763 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7764 rtx op0 = expand_normal (arg0);
7765 rtx op1 = expand_normal (arg1);
7766 rtx op2 = expand_normal (arg2);
7767 rtx op3 = expand_normal (arg3);
7768 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7769 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7771 gcc_assert (mode0 == mode1);
7773 if (arg0 == error_mark_node || arg1 == error_mark_node
7774 || arg2 == error_mark_node || arg3 == error_mark_node)
7778 || GET_MODE (target) != mode0
7779 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7780 target = gen_reg_rtx (mode0);
7782 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7783 op0 = copy_to_mode_reg (mode0, op0);
7784 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7785 op1 = copy_to_mode_reg (mode0, op1);
7786 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7787 op2 = copy_to_mode_reg (mode0, op2);
7788 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7789 op3 = copy_to_mode_reg (mode0, op3);
7791 /* Generate the compare. */
7792 scratch = gen_reg_rtx (CCmode);
7793 pat = GEN_FCN (icode) (scratch, op0, op1);
7798 if (mode0 == V2SImode)
7799 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7801 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7806 /* Expand an expression EXP that calls a built-in function,
7807 with result going to TARGET if that's convenient
7808 (and in mode MODE if that's convenient).
7809 SUBTARGET may be used as the target for computing one of EXP's operands.
7810 IGNORE is nonzero if the value is to be ignored. */
7813 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7814 enum machine_mode mode ATTRIBUTE_UNUSED,
7815 int ignore ATTRIBUTE_UNUSED)
7817 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7818 tree arglist = TREE_OPERAND (exp, 1);
7819 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7820 struct builtin_description *d;
7825 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7826 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7828 int icode = (int) CODE_FOR_altivec_lvsr;
7829 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7830 enum machine_mode mode = insn_data[icode].operand[1].mode;
7834 gcc_assert (TARGET_ALTIVEC);
7836 arg = TREE_VALUE (arglist);
7837 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7838 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7839 addr = memory_address (mode, op);
7840 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7844 /* For the load case need to negate the address. */
7845 op = gen_reg_rtx (GET_MODE (addr));
7846 emit_insn (gen_rtx_SET (VOIDmode, op,
7847 gen_rtx_NEG (GET_MODE (addr), addr)));
7849 op = gen_rtx_MEM (mode, op);
7852 || GET_MODE (target) != tmode
7853 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7854 target = gen_reg_rtx (tmode);
7856 /*pat = gen_altivec_lvsr (target, op);*/
7857 pat = GEN_FCN (icode) (target, op);
7867 ret = altivec_expand_builtin (exp, target, &success);
7874 ret = spe_expand_builtin (exp, target, &success);
7880 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7882 /* Handle simple unary operations. */
7883 d = (struct builtin_description *) bdesc_1arg;
7884 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7885 if (d->code == fcode)
7886 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7888 /* Handle simple binary operations. */
7889 d = (struct builtin_description *) bdesc_2arg;
7890 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7891 if (d->code == fcode)
7892 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7894 /* Handle simple ternary operations. */
7895 d = (struct builtin_description *) bdesc_3arg;
7896 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7897 if (d->code == fcode)
7898 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7904 build_opaque_vector_type (tree node, int nunits)
7906 node = copy_node (node);
7907 TYPE_MAIN_VARIANT (node) = node;
7908 return build_vector_type (node, nunits);
7912 rs6000_init_builtins (void)
7914 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7915 V2SF_type_node = build_vector_type (float_type_node, 2);
7916 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7917 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7918 V4SF_type_node = build_vector_type (float_type_node, 4);
7919 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7920 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7922 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7923 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7924 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7926 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7927 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7928 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7929 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7931 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7932 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7933 'vector unsigned short'. */
7935 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7936 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7937 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7938 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7940 long_integer_type_internal_node = long_integer_type_node;
7941 long_unsigned_type_internal_node = long_unsigned_type_node;
7942 intQI_type_internal_node = intQI_type_node;
7943 uintQI_type_internal_node = unsigned_intQI_type_node;
7944 intHI_type_internal_node = intHI_type_node;
7945 uintHI_type_internal_node = unsigned_intHI_type_node;
7946 intSI_type_internal_node = intSI_type_node;
7947 uintSI_type_internal_node = unsigned_intSI_type_node;
7948 float_type_internal_node = float_type_node;
7949 void_type_internal_node = void_type_node;
7951 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7952 get_identifier ("__bool char"),
7953 bool_char_type_node));
7954 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7955 get_identifier ("__bool short"),
7956 bool_short_type_node));
7957 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7958 get_identifier ("__bool int"),
7959 bool_int_type_node));
7960 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7961 get_identifier ("__pixel"),
7964 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7965 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7966 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7967 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7969 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7970 get_identifier ("__vector unsigned char"),
7971 unsigned_V16QI_type_node));
7972 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7973 get_identifier ("__vector signed char"),
7975 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7976 get_identifier ("__vector __bool char"),
7977 bool_V16QI_type_node));
7979 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7980 get_identifier ("__vector unsigned short"),
7981 unsigned_V8HI_type_node));
7982 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7983 get_identifier ("__vector signed short"),
7985 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7986 get_identifier ("__vector __bool short"),
7987 bool_V8HI_type_node));
7989 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7990 get_identifier ("__vector unsigned int"),
7991 unsigned_V4SI_type_node));
7992 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7993 get_identifier ("__vector signed int"),
7995 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7996 get_identifier ("__vector __bool int"),
7997 bool_V4SI_type_node));
7999 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8000 get_identifier ("__vector float"),
8002 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8003 get_identifier ("__vector __pixel"),
8004 pixel_V8HI_type_node));
8007 spe_init_builtins ();
8009 altivec_init_builtins ();
8010 if (TARGET_ALTIVEC || TARGET_SPE)
8011 rs6000_common_init_builtins ();
8014 /* AIX libm provides clog as __clog. */
8015 if (built_in_decls [BUILT_IN_CLOG])
8016 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8020 /* Search through a set of builtins and enable the mask bits.
8021 DESC is an array of builtins.
8022 SIZE is the total number of builtins.
8023 START is the builtin enum at which to start.
8024 END is the builtin enum at which to end. */
8026 enable_mask_for_builtins (struct builtin_description *desc, int size,
8027 enum rs6000_builtins start,
8028 enum rs6000_builtins end)
8032 for (i = 0; i < size; ++i)
8033 if (desc[i].code == start)
8039 for (; i < size; ++i)
8041 /* Flip all the bits on. */
8042 desc[i].mask = target_flags;
8043 if (desc[i].code == end)
8049 spe_init_builtins (void)
8051 tree endlink = void_list_node;
8052 tree puint_type_node = build_pointer_type (unsigned_type_node);
8053 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8054 struct builtin_description *d;
8057 tree v2si_ftype_4_v2si
8058 = build_function_type
8059 (opaque_V2SI_type_node,
8060 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8061 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8062 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8063 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8066 tree v2sf_ftype_4_v2sf
8067 = build_function_type
8068 (opaque_V2SF_type_node,
8069 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8070 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8071 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8072 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8075 tree int_ftype_int_v2si_v2si
8076 = build_function_type
8078 tree_cons (NULL_TREE, integer_type_node,
8079 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8080 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8083 tree int_ftype_int_v2sf_v2sf
8084 = build_function_type
8086 tree_cons (NULL_TREE, integer_type_node,
8087 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8088 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8091 tree void_ftype_v2si_puint_int
8092 = build_function_type (void_type_node,
8093 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8094 tree_cons (NULL_TREE, puint_type_node,
8095 tree_cons (NULL_TREE,
8099 tree void_ftype_v2si_puint_char
8100 = build_function_type (void_type_node,
8101 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8102 tree_cons (NULL_TREE, puint_type_node,
8103 tree_cons (NULL_TREE,
8107 tree void_ftype_v2si_pv2si_int
8108 = build_function_type (void_type_node,
8109 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8110 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8111 tree_cons (NULL_TREE,
8115 tree void_ftype_v2si_pv2si_char
8116 = build_function_type (void_type_node,
8117 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8118 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8119 tree_cons (NULL_TREE,
8124 = build_function_type (void_type_node,
8125 tree_cons (NULL_TREE, integer_type_node, endlink));
8128 = build_function_type (integer_type_node, endlink);
8130 tree v2si_ftype_pv2si_int
8131 = build_function_type (opaque_V2SI_type_node,
8132 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8133 tree_cons (NULL_TREE, integer_type_node,
8136 tree v2si_ftype_puint_int
8137 = build_function_type (opaque_V2SI_type_node,
8138 tree_cons (NULL_TREE, puint_type_node,
8139 tree_cons (NULL_TREE, integer_type_node,
8142 tree v2si_ftype_pushort_int
8143 = build_function_type (opaque_V2SI_type_node,
8144 tree_cons (NULL_TREE, pushort_type_node,
8145 tree_cons (NULL_TREE, integer_type_node,
8148 tree v2si_ftype_signed_char
8149 = build_function_type (opaque_V2SI_type_node,
8150 tree_cons (NULL_TREE, signed_char_type_node,
8153 /* The initialization of the simple binary and unary builtins is
8154 done in rs6000_common_init_builtins, but we have to enable the
8155 mask bits here manually because we have run out of `target_flags'
8156 bits. We really need to redesign this mask business. */
8158 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8159 ARRAY_SIZE (bdesc_2arg),
8162 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8163 ARRAY_SIZE (bdesc_1arg),
8165 SPE_BUILTIN_EVSUBFUSIAAW);
8166 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8167 ARRAY_SIZE (bdesc_spe_predicates),
8168 SPE_BUILTIN_EVCMPEQ,
8169 SPE_BUILTIN_EVFSTSTLT);
8170 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8171 ARRAY_SIZE (bdesc_spe_evsel),
8172 SPE_BUILTIN_EVSEL_CMPGTS,
8173 SPE_BUILTIN_EVSEL_FSTSTEQ);
8175 (*lang_hooks.decls.pushdecl)
8176 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8177 opaque_V2SI_type_node));
8179 /* Initialize irregular SPE builtins. */
8181 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8182 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8183 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8184 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8185 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8186 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8187 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8188 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8189 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8190 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8191 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8192 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8193 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8194 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8195 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8196 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8197 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8198 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8201 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8202 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8203 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8204 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8205 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8206 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8207 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8208 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8209 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8210 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8211 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8212 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8213 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8214 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8215 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8216 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8217 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8218 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8219 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8220 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8221 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8222 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8225 d = (struct builtin_description *) bdesc_spe_predicates;
8226 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8230 switch (insn_data[d->icode].operand[1].mode)
8233 type = int_ftype_int_v2si_v2si;
8236 type = int_ftype_int_v2sf_v2sf;
8242 def_builtin (d->mask, d->name, type, d->code);
8245 /* Evsel predicates. */
8246 d = (struct builtin_description *) bdesc_spe_evsel;
8247 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8251 switch (insn_data[d->icode].operand[1].mode)
8254 type = v2si_ftype_4_v2si;
8257 type = v2sf_ftype_4_v2sf;
8263 def_builtin (d->mask, d->name, type, d->code);
8268 altivec_init_builtins (void)
8270 struct builtin_description *d;
8271 struct builtin_description_predicates *dp;
8275 tree pfloat_type_node = build_pointer_type (float_type_node);
8276 tree pint_type_node = build_pointer_type (integer_type_node);
8277 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8278 tree pchar_type_node = build_pointer_type (char_type_node);
8280 tree pvoid_type_node = build_pointer_type (void_type_node);
8282 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8283 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8284 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8285 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8287 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8289 tree int_ftype_opaque
8290 = build_function_type_list (integer_type_node,
8291 opaque_V4SI_type_node, NULL_TREE);
8293 tree opaque_ftype_opaque_int
8294 = build_function_type_list (opaque_V4SI_type_node,
8295 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8296 tree opaque_ftype_opaque_opaque_int
8297 = build_function_type_list (opaque_V4SI_type_node,
8298 opaque_V4SI_type_node, opaque_V4SI_type_node,
8299 integer_type_node, NULL_TREE);
8300 tree int_ftype_int_opaque_opaque
8301 = build_function_type_list (integer_type_node,
8302 integer_type_node, opaque_V4SI_type_node,
8303 opaque_V4SI_type_node, NULL_TREE);
8304 tree int_ftype_int_v4si_v4si
8305 = build_function_type_list (integer_type_node,
8306 integer_type_node, V4SI_type_node,
8307 V4SI_type_node, NULL_TREE);
8308 tree v4sf_ftype_pcfloat
8309 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8310 tree void_ftype_pfloat_v4sf
8311 = build_function_type_list (void_type_node,
8312 pfloat_type_node, V4SF_type_node, NULL_TREE);
8313 tree v4si_ftype_pcint
8314 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8315 tree void_ftype_pint_v4si
8316 = build_function_type_list (void_type_node,
8317 pint_type_node, V4SI_type_node, NULL_TREE);
8318 tree v8hi_ftype_pcshort
8319 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8320 tree void_ftype_pshort_v8hi
8321 = build_function_type_list (void_type_node,
8322 pshort_type_node, V8HI_type_node, NULL_TREE);
8323 tree v16qi_ftype_pcchar
8324 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8325 tree void_ftype_pchar_v16qi
8326 = build_function_type_list (void_type_node,
8327 pchar_type_node, V16QI_type_node, NULL_TREE);
8328 tree void_ftype_v4si
8329 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8330 tree v8hi_ftype_void
8331 = build_function_type (V8HI_type_node, void_list_node);
8332 tree void_ftype_void
8333 = build_function_type (void_type_node, void_list_node);
8335 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8337 tree opaque_ftype_long_pcvoid
8338 = build_function_type_list (opaque_V4SI_type_node,
8339 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8340 tree v16qi_ftype_long_pcvoid
8341 = build_function_type_list (V16QI_type_node,
8342 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8343 tree v8hi_ftype_long_pcvoid
8344 = build_function_type_list (V8HI_type_node,
8345 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8346 tree v4si_ftype_long_pcvoid
8347 = build_function_type_list (V4SI_type_node,
8348 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8350 tree void_ftype_opaque_long_pvoid
8351 = build_function_type_list (void_type_node,
8352 opaque_V4SI_type_node, long_integer_type_node,
8353 pvoid_type_node, NULL_TREE);
8354 tree void_ftype_v4si_long_pvoid
8355 = build_function_type_list (void_type_node,
8356 V4SI_type_node, long_integer_type_node,
8357 pvoid_type_node, NULL_TREE);
8358 tree void_ftype_v16qi_long_pvoid
8359 = build_function_type_list (void_type_node,
8360 V16QI_type_node, long_integer_type_node,
8361 pvoid_type_node, NULL_TREE);
8362 tree void_ftype_v8hi_long_pvoid
8363 = build_function_type_list (void_type_node,
8364 V8HI_type_node, long_integer_type_node,
8365 pvoid_type_node, NULL_TREE);
8366 tree int_ftype_int_v8hi_v8hi
8367 = build_function_type_list (integer_type_node,
8368 integer_type_node, V8HI_type_node,
8369 V8HI_type_node, NULL_TREE);
8370 tree int_ftype_int_v16qi_v16qi
8371 = build_function_type_list (integer_type_node,
8372 integer_type_node, V16QI_type_node,
8373 V16QI_type_node, NULL_TREE);
8374 tree int_ftype_int_v4sf_v4sf
8375 = build_function_type_list (integer_type_node,
8376 integer_type_node, V4SF_type_node,
8377 V4SF_type_node, NULL_TREE);
8378 tree v4si_ftype_v4si
8379 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8380 tree v8hi_ftype_v8hi
8381 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8382 tree v16qi_ftype_v16qi
8383 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8384 tree v4sf_ftype_v4sf
8385 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8386 tree void_ftype_pcvoid_int_int
8387 = build_function_type_list (void_type_node,
8388 pcvoid_type_node, integer_type_node,
8389 integer_type_node, NULL_TREE);
8391 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8392 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8393 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8394 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8395 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8396 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8397 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8398 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8399 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8400 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8401 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8402 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8403 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8404 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8405 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8406 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8407 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8408 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8409 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8410 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8411 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8412 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8413 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8414 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8415 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8416 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8417 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8418 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8419 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8420 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8421 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8422 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8423 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8424 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8425 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8426 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8427 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8428 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8429 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8430 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8431 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8432 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8433 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8434 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8435 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8436 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8438 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8440 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8441 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8442 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8443 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8444 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8445 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8446 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8447 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8448 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8449 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8451 /* Add the DST variants. */
8452 d = (struct builtin_description *) bdesc_dst;
8453 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8454 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8456 /* Initialize the predicates. */
8457 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8458 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8460 enum machine_mode mode1;
8462 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8463 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8468 mode1 = insn_data[dp->icode].operand[1].mode;
8473 type = int_ftype_int_opaque_opaque;
8476 type = int_ftype_int_v4si_v4si;
8479 type = int_ftype_int_v8hi_v8hi;
8482 type = int_ftype_int_v16qi_v16qi;
8485 type = int_ftype_int_v4sf_v4sf;
8491 def_builtin (dp->mask, dp->name, type, dp->code);
8494 /* Initialize the abs* operators. */
8495 d = (struct builtin_description *) bdesc_abs;
8496 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8498 enum machine_mode mode0;
8501 mode0 = insn_data[d->icode].operand[0].mode;
8506 type = v4si_ftype_v4si;
8509 type = v8hi_ftype_v8hi;
8512 type = v16qi_ftype_v16qi;
8515 type = v4sf_ftype_v4sf;
8521 def_builtin (d->mask, d->name, type, d->code);
8528 /* Initialize target builtin that implements
8529 targetm.vectorize.builtin_mask_for_load. */
8531 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8532 v16qi_ftype_long_pcvoid,
8533 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8535 tree_cons (get_identifier ("const"),
8536 NULL_TREE, NULL_TREE));
8537 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8538 altivec_builtin_mask_for_load = decl;
8541 /* Access to the vec_init patterns. */
8542 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8543 integer_type_node, integer_type_node,
8544 integer_type_node, NULL_TREE);
8545 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8546 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8548 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8549 short_integer_type_node,
8550 short_integer_type_node,
8551 short_integer_type_node,
8552 short_integer_type_node,
8553 short_integer_type_node,
8554 short_integer_type_node,
8555 short_integer_type_node, NULL_TREE);
8556 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8557 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8559 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8560 char_type_node, char_type_node,
8561 char_type_node, char_type_node,
8562 char_type_node, char_type_node,
8563 char_type_node, char_type_node,
8564 char_type_node, char_type_node,
8565 char_type_node, char_type_node,
8566 char_type_node, char_type_node,
8567 char_type_node, NULL_TREE);
8568 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8569 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8571 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8572 float_type_node, float_type_node,
8573 float_type_node, NULL_TREE);
8574 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8575 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8577 /* Access to the vec_set patterns. */
8578 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8580 integer_type_node, NULL_TREE);
8581 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8582 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8584 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8586 integer_type_node, NULL_TREE);
8587 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8588 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8590 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8592 integer_type_node, NULL_TREE);
8593 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8594 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8596 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8598 integer_type_node, NULL_TREE);
8599 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8600 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8602 /* Access to the vec_extract patterns. */
8603 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8604 integer_type_node, NULL_TREE);
8605 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8606 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8608 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8609 integer_type_node, NULL_TREE);
8610 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8611 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8613 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8614 integer_type_node, NULL_TREE);
8615 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8616 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8618 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8619 integer_type_node, NULL_TREE);
8620 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8621 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8625 rs6000_common_init_builtins (void)
8627 struct builtin_description *d;
8630 tree v4sf_ftype_v4sf_v4sf_v16qi
8631 = build_function_type_list (V4SF_type_node,
8632 V4SF_type_node, V4SF_type_node,
8633 V16QI_type_node, NULL_TREE);
8634 tree v4si_ftype_v4si_v4si_v16qi
8635 = build_function_type_list (V4SI_type_node,
8636 V4SI_type_node, V4SI_type_node,
8637 V16QI_type_node, NULL_TREE);
8638 tree v8hi_ftype_v8hi_v8hi_v16qi
8639 = build_function_type_list (V8HI_type_node,
8640 V8HI_type_node, V8HI_type_node,
8641 V16QI_type_node, NULL_TREE);
8642 tree v16qi_ftype_v16qi_v16qi_v16qi
8643 = build_function_type_list (V16QI_type_node,
8644 V16QI_type_node, V16QI_type_node,
8645 V16QI_type_node, NULL_TREE);
8647 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8649 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8650 tree v16qi_ftype_int
8651 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8652 tree v8hi_ftype_v16qi
8653 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8654 tree v4sf_ftype_v4sf
8655 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8657 tree v2si_ftype_v2si_v2si
8658 = build_function_type_list (opaque_V2SI_type_node,
8659 opaque_V2SI_type_node,
8660 opaque_V2SI_type_node, NULL_TREE);
8662 tree v2sf_ftype_v2sf_v2sf
8663 = build_function_type_list (opaque_V2SF_type_node,
8664 opaque_V2SF_type_node,
8665 opaque_V2SF_type_node, NULL_TREE);
8667 tree v2si_ftype_int_int
8668 = build_function_type_list (opaque_V2SI_type_node,
8669 integer_type_node, integer_type_node,
8672 tree opaque_ftype_opaque
8673 = build_function_type_list (opaque_V4SI_type_node,
8674 opaque_V4SI_type_node, NULL_TREE);
8676 tree v2si_ftype_v2si
8677 = build_function_type_list (opaque_V2SI_type_node,
8678 opaque_V2SI_type_node, NULL_TREE);
8680 tree v2sf_ftype_v2sf
8681 = build_function_type_list (opaque_V2SF_type_node,
8682 opaque_V2SF_type_node, NULL_TREE);
8684 tree v2sf_ftype_v2si
8685 = build_function_type_list (opaque_V2SF_type_node,
8686 opaque_V2SI_type_node, NULL_TREE);
8688 tree v2si_ftype_v2sf
8689 = build_function_type_list (opaque_V2SI_type_node,
8690 opaque_V2SF_type_node, NULL_TREE);
8692 tree v2si_ftype_v2si_char
8693 = build_function_type_list (opaque_V2SI_type_node,
8694 opaque_V2SI_type_node,
8695 char_type_node, NULL_TREE);
8697 tree v2si_ftype_int_char
8698 = build_function_type_list (opaque_V2SI_type_node,
8699 integer_type_node, char_type_node, NULL_TREE);
8701 tree v2si_ftype_char
8702 = build_function_type_list (opaque_V2SI_type_node,
8703 char_type_node, NULL_TREE);
8705 tree int_ftype_int_int
8706 = build_function_type_list (integer_type_node,
8707 integer_type_node, integer_type_node,
8710 tree opaque_ftype_opaque_opaque
8711 = build_function_type_list (opaque_V4SI_type_node,
8712 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8713 tree v4si_ftype_v4si_v4si
8714 = build_function_type_list (V4SI_type_node,
8715 V4SI_type_node, V4SI_type_node, NULL_TREE);
8716 tree v4sf_ftype_v4si_int
8717 = build_function_type_list (V4SF_type_node,
8718 V4SI_type_node, integer_type_node, NULL_TREE);
8719 tree v4si_ftype_v4sf_int
8720 = build_function_type_list (V4SI_type_node,
8721 V4SF_type_node, integer_type_node, NULL_TREE);
8722 tree v4si_ftype_v4si_int
8723 = build_function_type_list (V4SI_type_node,
8724 V4SI_type_node, integer_type_node, NULL_TREE);
8725 tree v8hi_ftype_v8hi_int
8726 = build_function_type_list (V8HI_type_node,
8727 V8HI_type_node, integer_type_node, NULL_TREE);
8728 tree v16qi_ftype_v16qi_int
8729 = build_function_type_list (V16QI_type_node,
8730 V16QI_type_node, integer_type_node, NULL_TREE);
8731 tree v16qi_ftype_v16qi_v16qi_int
8732 = build_function_type_list (V16QI_type_node,
8733 V16QI_type_node, V16QI_type_node,
8734 integer_type_node, NULL_TREE);
8735 tree v8hi_ftype_v8hi_v8hi_int
8736 = build_function_type_list (V8HI_type_node,
8737 V8HI_type_node, V8HI_type_node,
8738 integer_type_node, NULL_TREE);
8739 tree v4si_ftype_v4si_v4si_int
8740 = build_function_type_list (V4SI_type_node,
8741 V4SI_type_node, V4SI_type_node,
8742 integer_type_node, NULL_TREE);
8743 tree v4sf_ftype_v4sf_v4sf_int
8744 = build_function_type_list (V4SF_type_node,
8745 V4SF_type_node, V4SF_type_node,
8746 integer_type_node, NULL_TREE);
8747 tree v4sf_ftype_v4sf_v4sf
8748 = build_function_type_list (V4SF_type_node,
8749 V4SF_type_node, V4SF_type_node, NULL_TREE);
8750 tree opaque_ftype_opaque_opaque_opaque
8751 = build_function_type_list (opaque_V4SI_type_node,
8752 opaque_V4SI_type_node, opaque_V4SI_type_node,
8753 opaque_V4SI_type_node, NULL_TREE);
8754 tree v4sf_ftype_v4sf_v4sf_v4si
8755 = build_function_type_list (V4SF_type_node,
8756 V4SF_type_node, V4SF_type_node,
8757 V4SI_type_node, NULL_TREE);
8758 tree v4sf_ftype_v4sf_v4sf_v4sf
8759 = build_function_type_list (V4SF_type_node,
8760 V4SF_type_node, V4SF_type_node,
8761 V4SF_type_node, NULL_TREE);
8762 tree v4si_ftype_v4si_v4si_v4si
8763 = build_function_type_list (V4SI_type_node,
8764 V4SI_type_node, V4SI_type_node,
8765 V4SI_type_node, NULL_TREE);
8766 tree v8hi_ftype_v8hi_v8hi
8767 = build_function_type_list (V8HI_type_node,
8768 V8HI_type_node, V8HI_type_node, NULL_TREE);
8769 tree v8hi_ftype_v8hi_v8hi_v8hi
8770 = build_function_type_list (V8HI_type_node,
8771 V8HI_type_node, V8HI_type_node,
8772 V8HI_type_node, NULL_TREE);
8773 tree v4si_ftype_v8hi_v8hi_v4si
8774 = build_function_type_list (V4SI_type_node,
8775 V8HI_type_node, V8HI_type_node,
8776 V4SI_type_node, NULL_TREE);
8777 tree v4si_ftype_v16qi_v16qi_v4si
8778 = build_function_type_list (V4SI_type_node,
8779 V16QI_type_node, V16QI_type_node,
8780 V4SI_type_node, NULL_TREE);
8781 tree v16qi_ftype_v16qi_v16qi
8782 = build_function_type_list (V16QI_type_node,
8783 V16QI_type_node, V16QI_type_node, NULL_TREE);
8784 tree v4si_ftype_v4sf_v4sf
8785 = build_function_type_list (V4SI_type_node,
8786 V4SF_type_node, V4SF_type_node, NULL_TREE);
8787 tree v8hi_ftype_v16qi_v16qi
8788 = build_function_type_list (V8HI_type_node,
8789 V16QI_type_node, V16QI_type_node, NULL_TREE);
8790 tree v4si_ftype_v8hi_v8hi
8791 = build_function_type_list (V4SI_type_node,
8792 V8HI_type_node, V8HI_type_node, NULL_TREE);
8793 tree v8hi_ftype_v4si_v4si
8794 = build_function_type_list (V8HI_type_node,
8795 V4SI_type_node, V4SI_type_node, NULL_TREE);
8796 tree v16qi_ftype_v8hi_v8hi
8797 = build_function_type_list (V16QI_type_node,
8798 V8HI_type_node, V8HI_type_node, NULL_TREE);
8799 tree v4si_ftype_v16qi_v4si
8800 = build_function_type_list (V4SI_type_node,
8801 V16QI_type_node, V4SI_type_node, NULL_TREE);
8802 tree v4si_ftype_v16qi_v16qi
8803 = build_function_type_list (V4SI_type_node,
8804 V16QI_type_node, V16QI_type_node, NULL_TREE);
8805 tree v4si_ftype_v8hi_v4si
8806 = build_function_type_list (V4SI_type_node,
8807 V8HI_type_node, V4SI_type_node, NULL_TREE);
8808 tree v4si_ftype_v8hi
8809 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8810 tree int_ftype_v4si_v4si
8811 = build_function_type_list (integer_type_node,
8812 V4SI_type_node, V4SI_type_node, NULL_TREE);
8813 tree int_ftype_v4sf_v4sf
8814 = build_function_type_list (integer_type_node,
8815 V4SF_type_node, V4SF_type_node, NULL_TREE);
8816 tree int_ftype_v16qi_v16qi
8817 = build_function_type_list (integer_type_node,
8818 V16QI_type_node, V16QI_type_node, NULL_TREE);
8819 tree int_ftype_v8hi_v8hi
8820 = build_function_type_list (integer_type_node,
8821 V8HI_type_node, V8HI_type_node, NULL_TREE);
8823 /* Add the simple ternary operators. */
8824 d = (struct builtin_description *) bdesc_3arg;
8825 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8827 enum machine_mode mode0, mode1, mode2, mode3;
8829 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8830 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8841 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8844 mode0 = insn_data[d->icode].operand[0].mode;
8845 mode1 = insn_data[d->icode].operand[1].mode;
8846 mode2 = insn_data[d->icode].operand[2].mode;
8847 mode3 = insn_data[d->icode].operand[3].mode;
8850 /* When all four are of the same mode. */
8851 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8856 type = opaque_ftype_opaque_opaque_opaque;
8859 type = v4si_ftype_v4si_v4si_v4si;
8862 type = v4sf_ftype_v4sf_v4sf_v4sf;
8865 type = v8hi_ftype_v8hi_v8hi_v8hi;
8868 type = v16qi_ftype_v16qi_v16qi_v16qi;
8874 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8879 type = v4si_ftype_v4si_v4si_v16qi;
8882 type = v4sf_ftype_v4sf_v4sf_v16qi;
8885 type = v8hi_ftype_v8hi_v8hi_v16qi;
8888 type = v16qi_ftype_v16qi_v16qi_v16qi;
8894 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8895 && mode3 == V4SImode)
8896 type = v4si_ftype_v16qi_v16qi_v4si;
8897 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8898 && mode3 == V4SImode)
8899 type = v4si_ftype_v8hi_v8hi_v4si;
8900 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8901 && mode3 == V4SImode)
8902 type = v4sf_ftype_v4sf_v4sf_v4si;
8904 /* vchar, vchar, vchar, 4 bit literal. */
8905 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8907 type = v16qi_ftype_v16qi_v16qi_int;
8909 /* vshort, vshort, vshort, 4 bit literal. */
8910 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8912 type = v8hi_ftype_v8hi_v8hi_int;
8914 /* vint, vint, vint, 4 bit literal. */
8915 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8917 type = v4si_ftype_v4si_v4si_int;
8919 /* vfloat, vfloat, vfloat, 4 bit literal. */
8920 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8922 type = v4sf_ftype_v4sf_v4sf_int;
8927 def_builtin (d->mask, d->name, type, d->code);
8930 /* Add the simple binary operators. */
8931 d = (struct builtin_description *) bdesc_2arg;
8932 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8934 enum machine_mode mode0, mode1, mode2;
8936 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8937 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8947 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8950 mode0 = insn_data[d->icode].operand[0].mode;
8951 mode1 = insn_data[d->icode].operand[1].mode;
8952 mode2 = insn_data[d->icode].operand[2].mode;
8955 /* When all three operands are of the same mode. */
8956 if (mode0 == mode1 && mode1 == mode2)
8961 type = opaque_ftype_opaque_opaque;
8964 type = v4sf_ftype_v4sf_v4sf;
8967 type = v4si_ftype_v4si_v4si;
8970 type = v16qi_ftype_v16qi_v16qi;
8973 type = v8hi_ftype_v8hi_v8hi;
8976 type = v2si_ftype_v2si_v2si;
8979 type = v2sf_ftype_v2sf_v2sf;
8982 type = int_ftype_int_int;
8989 /* A few other combos we really don't want to do manually. */
8991 /* vint, vfloat, vfloat. */
8992 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8993 type = v4si_ftype_v4sf_v4sf;
8995 /* vshort, vchar, vchar. */
8996 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8997 type = v8hi_ftype_v16qi_v16qi;
8999 /* vint, vshort, vshort. */
9000 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9001 type = v4si_ftype_v8hi_v8hi;
9003 /* vshort, vint, vint. */
9004 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9005 type = v8hi_ftype_v4si_v4si;
9007 /* vchar, vshort, vshort. */
9008 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9009 type = v16qi_ftype_v8hi_v8hi;
9011 /* vint, vchar, vint. */
9012 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9013 type = v4si_ftype_v16qi_v4si;
9015 /* vint, vchar, vchar. */
9016 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9017 type = v4si_ftype_v16qi_v16qi;
9019 /* vint, vshort, vint. */
9020 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9021 type = v4si_ftype_v8hi_v4si;
9023 /* vint, vint, 5 bit literal. */
9024 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9025 type = v4si_ftype_v4si_int;
9027 /* vshort, vshort, 5 bit literal. */
9028 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9029 type = v8hi_ftype_v8hi_int;
9031 /* vchar, vchar, 5 bit literal. */
9032 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9033 type = v16qi_ftype_v16qi_int;
9035 /* vfloat, vint, 5 bit literal. */
9036 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9037 type = v4sf_ftype_v4si_int;
9039 /* vint, vfloat, 5 bit literal. */
9040 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9041 type = v4si_ftype_v4sf_int;
9043 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9044 type = v2si_ftype_int_int;
9046 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9047 type = v2si_ftype_v2si_char;
9049 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9050 type = v2si_ftype_int_char;
9055 gcc_assert (mode0 == SImode);
9059 type = int_ftype_v4si_v4si;
9062 type = int_ftype_v4sf_v4sf;
9065 type = int_ftype_v16qi_v16qi;
9068 type = int_ftype_v8hi_v8hi;
9075 def_builtin (d->mask, d->name, type, d->code);
9078 /* Add the simple unary operators. */
9079 d = (struct builtin_description *) bdesc_1arg;
9080 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9082 enum machine_mode mode0, mode1;
9084 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9085 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9094 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9097 mode0 = insn_data[d->icode].operand[0].mode;
9098 mode1 = insn_data[d->icode].operand[1].mode;
9101 if (mode0 == V4SImode && mode1 == QImode)
9102 type = v4si_ftype_int;
9103 else if (mode0 == V8HImode && mode1 == QImode)
9104 type = v8hi_ftype_int;
9105 else if (mode0 == V16QImode && mode1 == QImode)
9106 type = v16qi_ftype_int;
9107 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9108 type = opaque_ftype_opaque;
9109 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9110 type = v4sf_ftype_v4sf;
9111 else if (mode0 == V8HImode && mode1 == V16QImode)
9112 type = v8hi_ftype_v16qi;
9113 else if (mode0 == V4SImode && mode1 == V8HImode)
9114 type = v4si_ftype_v8hi;
9115 else if (mode0 == V2SImode && mode1 == V2SImode)
9116 type = v2si_ftype_v2si;
9117 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9118 type = v2sf_ftype_v2sf;
9119 else if (mode0 == V2SFmode && mode1 == V2SImode)
9120 type = v2sf_ftype_v2si;
9121 else if (mode0 == V2SImode && mode1 == V2SFmode)
9122 type = v2si_ftype_v2sf;
9123 else if (mode0 == V2SImode && mode1 == QImode)
9124 type = v2si_ftype_char;
9128 def_builtin (d->mask, d->name, type, d->code);
9133 rs6000_init_libfuncs (void)
9135 if (!TARGET_HARD_FLOAT)
9138 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9139 && !TARGET_POWER2 && !TARGET_POWERPC)
9141 /* AIX library routines for float->int conversion. */
9142 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9143 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9144 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9145 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9148 if (!TARGET_IEEEQUAD)
9149 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9150 if (!TARGET_XL_COMPAT)
9152 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9153 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9154 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9155 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9159 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9160 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9161 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9162 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9166 /* 32-bit SVR4 quad floating point routines. */
9168 set_optab_libfunc (add_optab, TFmode, "_q_add");
9169 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9170 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9171 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9172 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9173 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9174 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9176 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9177 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9178 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9179 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9180 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9181 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9183 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9184 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9185 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9186 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9187 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9188 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9189 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9190 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9195 /* Expand a block clear operation, and return 1 if successful. Return 0
9196 if we should let the compiler generate normal code.
9198 operands[0] is the destination
9199 operands[1] is the length
9200 operands[3] is the alignment */
9203 expand_block_clear (rtx operands[])
9205 rtx orig_dest = operands[0];
9206 rtx bytes_rtx = operands[1];
9207 rtx align_rtx = operands[3];
9208 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9209 HOST_WIDE_INT align;
9210 HOST_WIDE_INT bytes;
9215 /* If this is not a fixed size move, just call memcpy */
9219 /* This must be a fixed size alignment */
9220 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9221 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9223 /* Anything to clear? */
9224 bytes = INTVAL (bytes_rtx);
9228 /* Use the builtin memset after a point, to avoid huge code bloat.
9229 When optimize_size, avoid any significant code bloat; calling
9230 memset is about 4 instructions, so allow for one instruction to
9231 load zero and three to do clearing. */
9232 if (TARGET_ALTIVEC && align >= 128)
9234 else if (TARGET_POWERPC64 && align >= 32)
9239 if (optimize_size && bytes > 3 * clear_step)
9241 if (! optimize_size && bytes > 8 * clear_step)
9244 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9246 enum machine_mode mode = BLKmode;
9249 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9254 else if (bytes >= 8 && TARGET_POWERPC64
9255 /* 64-bit loads and stores require word-aligned
9257 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9262 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9263 { /* move 4 bytes */
9267 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9268 { /* move 2 bytes */
9272 else /* move 1 byte at a time */
9278 dest = adjust_address (orig_dest, mode, offset);
9280 emit_move_insn (dest, CONST0_RTX (mode));
9287 /* Expand a block move operation, and return 1 if successful. Return 0
9288 if we should let the compiler generate normal code.
9290 operands[0] is the destination
9291 operands[1] is the source
9292 operands[2] is the length
9293 operands[3] is the alignment */
9295 #define MAX_MOVE_REG 4
9298 expand_block_move (rtx operands[])
9300 rtx orig_dest = operands[0];
9301 rtx orig_src = operands[1];
9302 rtx bytes_rtx = operands[2];
9303 rtx align_rtx = operands[3];
9304 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9309 rtx stores[MAX_MOVE_REG];
9312 /* If this is not a fixed size move, just call memcpy */
9316 /* This must be a fixed size alignment */
9317 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9318 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9320 /* Anything to move? */
9321 bytes = INTVAL (bytes_rtx);
9325 /* store_one_arg depends on expand_block_move to handle at least the size of
9326 reg_parm_stack_space. */
9327 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9330 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9333 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9334 rtx (*mov) (rtx, rtx);
9336 enum machine_mode mode = BLKmode;
9339 /* Altivec first, since it will be faster than a string move
9340 when it applies, and usually not significantly larger. */
9341 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9345 gen_func.mov = gen_movv4si;
9347 else if (TARGET_STRING
9348 && bytes > 24 /* move up to 32 bytes at a time */
9356 && ! fixed_regs[12])
9358 move_bytes = (bytes > 32) ? 32 : bytes;
9359 gen_func.movmemsi = gen_movmemsi_8reg;
9361 else if (TARGET_STRING
9362 && bytes > 16 /* move up to 24 bytes at a time */
9368 && ! fixed_regs[10])
9370 move_bytes = (bytes > 24) ? 24 : bytes;
9371 gen_func.movmemsi = gen_movmemsi_6reg;
9373 else if (TARGET_STRING
9374 && bytes > 8 /* move up to 16 bytes at a time */
9380 move_bytes = (bytes > 16) ? 16 : bytes;
9381 gen_func.movmemsi = gen_movmemsi_4reg;
9383 else if (bytes >= 8 && TARGET_POWERPC64
9384 /* 64-bit loads and stores require word-aligned
9386 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9390 gen_func.mov = gen_movdi;
9392 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9393 { /* move up to 8 bytes at a time */
9394 move_bytes = (bytes > 8) ? 8 : bytes;
9395 gen_func.movmemsi = gen_movmemsi_2reg;
9397 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9398 { /* move 4 bytes */
9401 gen_func.mov = gen_movsi;
9403 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9404 { /* move 2 bytes */
9407 gen_func.mov = gen_movhi;
9409 else if (TARGET_STRING && bytes > 1)
9410 { /* move up to 4 bytes at a time */
9411 move_bytes = (bytes > 4) ? 4 : bytes;
9412 gen_func.movmemsi = gen_movmemsi_1reg;
9414 else /* move 1 byte at a time */
9418 gen_func.mov = gen_movqi;
9421 src = adjust_address (orig_src, mode, offset);
9422 dest = adjust_address (orig_dest, mode, offset);
9424 if (mode != BLKmode)
9426 rtx tmp_reg = gen_reg_rtx (mode);
9428 emit_insn ((*gen_func.mov) (tmp_reg, src));
9429 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9432 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9435 for (i = 0; i < num_reg; i++)
9436 emit_insn (stores[i]);
9440 if (mode == BLKmode)
9442 /* Move the address into scratch registers. The movmemsi
9443 patterns require zero offset. */
9444 if (!REG_P (XEXP (src, 0)))
9446 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9447 src = replace_equiv_address (src, src_reg);
9449 set_mem_size (src, GEN_INT (move_bytes));
9451 if (!REG_P (XEXP (dest, 0)))
9453 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9454 dest = replace_equiv_address (dest, dest_reg);
9456 set_mem_size (dest, GEN_INT (move_bytes));
9458 emit_insn ((*gen_func.movmemsi) (dest, src,
9459 GEN_INT (move_bytes & 31),
9468 /* Return a string to perform a load_multiple operation.
9469 operands[0] is the vector.
9470 operands[1] is the source address.
9471 operands[2] is the first destination register. */
9474 rs6000_output_load_multiple (rtx operands[3])
9476 /* We have to handle the case where the pseudo used to contain the address
9477 is assigned to one of the output registers. */
9479 int words = XVECLEN (operands[0], 0);
9482 if (XVECLEN (operands[0], 0) == 1)
9483 return "{l|lwz} %2,0(%1)";
9485 for (i = 0; i < words; i++)
9486 if (refers_to_regno_p (REGNO (operands[2]) + i,
9487 REGNO (operands[2]) + i + 1, operands[1], 0))
9491 xop[0] = GEN_INT (4 * (words-1));
9492 xop[1] = operands[1];
9493 xop[2] = operands[2];
9494 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9499 xop[0] = GEN_INT (4 * (words-1));
9500 xop[1] = operands[1];
9501 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9502 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9507 for (j = 0; j < words; j++)
9510 xop[0] = GEN_INT (j * 4);
9511 xop[1] = operands[1];
9512 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9513 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9515 xop[0] = GEN_INT (i * 4);
9516 xop[1] = operands[1];
9517 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9522 return "{lsi|lswi} %2,%1,%N0";
9526 /* A validation routine: say whether CODE, a condition code, and MODE
9527 match. The other alternatives either don't make sense or should
9528 never be generated. */
9531 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9533 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9534 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9535 && GET_MODE_CLASS (mode) == MODE_CC);
9537 /* These don't make sense. */
9538 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9539 || mode != CCUNSmode);
9541 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9542 || mode == CCUNSmode);
9544 gcc_assert (mode == CCFPmode
9545 || (code != ORDERED && code != UNORDERED
9546 && code != UNEQ && code != LTGT
9547 && code != UNGT && code != UNLT
9548 && code != UNGE && code != UNLE));
9550 /* These should never be generated except for
9551 flag_finite_math_only. */
9552 gcc_assert (mode != CCFPmode
9553 || flag_finite_math_only
9554 || (code != LE && code != GE
9555 && code != UNEQ && code != LTGT
9556 && code != UNGT && code != UNLT));
9558 /* These are invalid; the information is not there. */
9559 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9563 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9564 mask required to convert the result of a rotate insn into a shift
9565 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9568 includes_lshift_p (rtx shiftop, rtx andop)
9570 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9572 shift_mask <<= INTVAL (shiftop);
9574 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9577 /* Similar, but for right shift. */
9580 includes_rshift_p (rtx shiftop, rtx andop)
9582 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9584 shift_mask >>= INTVAL (shiftop);
9586 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9589 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9590 to perform a left shift. It must have exactly SHIFTOP least
9591 significant 0's, then one or more 1's, then zero or more 0's. */
9594 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9596 if (GET_CODE (andop) == CONST_INT)
9598 HOST_WIDE_INT c, lsb, shift_mask;
9601 if (c == 0 || c == ~0)
9605 shift_mask <<= INTVAL (shiftop);
9607 /* Find the least significant one bit. */
9610 /* It must coincide with the LSB of the shift mask. */
9611 if (-lsb != shift_mask)
9614 /* Invert to look for the next transition (if any). */
9617 /* Remove the low group of ones (originally low group of zeros). */
9620 /* Again find the lsb, and check we have all 1's above. */
9624 else if (GET_CODE (andop) == CONST_DOUBLE
9625 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9627 HOST_WIDE_INT low, high, lsb;
9628 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9630 low = CONST_DOUBLE_LOW (andop);
9631 if (HOST_BITS_PER_WIDE_INT < 64)
9632 high = CONST_DOUBLE_HIGH (andop);
9634 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9635 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9638 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9640 shift_mask_high = ~0;
9641 if (INTVAL (shiftop) > 32)
9642 shift_mask_high <<= INTVAL (shiftop) - 32;
9646 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9653 return high == -lsb;
9656 shift_mask_low = ~0;
9657 shift_mask_low <<= INTVAL (shiftop);
9661 if (-lsb != shift_mask_low)
9664 if (HOST_BITS_PER_WIDE_INT < 64)
9669 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9672 return high == -lsb;
9676 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9682 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9683 to perform a left shift. It must have SHIFTOP or more least
9684 significant 0's, with the remainder of the word 1's. */
9687 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9689 if (GET_CODE (andop) == CONST_INT)
9691 HOST_WIDE_INT c, lsb, shift_mask;
9694 shift_mask <<= INTVAL (shiftop);
9697 /* Find the least significant one bit. */
9700 /* It must be covered by the shift mask.
9701 This test also rejects c == 0. */
9702 if ((lsb & shift_mask) == 0)
9705 /* Check we have all 1's above the transition, and reject all 1's. */
9706 return c == -lsb && lsb != 1;
9708 else if (GET_CODE (andop) == CONST_DOUBLE
9709 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9711 HOST_WIDE_INT low, lsb, shift_mask_low;
9713 low = CONST_DOUBLE_LOW (andop);
9715 if (HOST_BITS_PER_WIDE_INT < 64)
9717 HOST_WIDE_INT high, shift_mask_high;
9719 high = CONST_DOUBLE_HIGH (andop);
9723 shift_mask_high = ~0;
9724 if (INTVAL (shiftop) > 32)
9725 shift_mask_high <<= INTVAL (shiftop) - 32;
9729 if ((lsb & shift_mask_high) == 0)
9732 return high == -lsb;
9738 shift_mask_low = ~0;
9739 shift_mask_low <<= INTVAL (shiftop);
9743 if ((lsb & shift_mask_low) == 0)
9746 return low == -lsb && lsb != 1;
9752 /* Return 1 if operands will generate a valid arguments to rlwimi
9753 instruction for insert with right shift in 64-bit mode. The mask may
9754 not start on the first bit or stop on the last bit because wrap-around
9755 effects of instruction do not correspond to semantics of RTL insn. */
9758 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9760 if (INTVAL (startop) < 64
9761 && INTVAL (startop) > 32
9762 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9763 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9764 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9765 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9766 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9772 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9773 for lfq and stfq insns iff the registers are hard registers. */
9776 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9778 /* We might have been passed a SUBREG. */
9779 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9782 /* We might have been passed non floating point registers. */
9783 if (!FP_REGNO_P (REGNO (reg1))
9784 || !FP_REGNO_P (REGNO (reg2)))
9787 return (REGNO (reg1) == REGNO (reg2) - 1);
9790 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9791 addr1 and addr2 must be in consecutive memory locations
9792 (addr2 == addr1 + 8). */
9795 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9798 unsigned int reg1, reg2;
9799 int offset1, offset2;
9801 /* The mems cannot be volatile. */
9802 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9805 addr1 = XEXP (mem1, 0);
9806 addr2 = XEXP (mem2, 0);
9808 /* Extract an offset (if used) from the first addr. */
9809 if (GET_CODE (addr1) == PLUS)
9811 /* If not a REG, return zero. */
9812 if (GET_CODE (XEXP (addr1, 0)) != REG)
9816 reg1 = REGNO (XEXP (addr1, 0));
9817 /* The offset must be constant! */
9818 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9820 offset1 = INTVAL (XEXP (addr1, 1));
9823 else if (GET_CODE (addr1) != REG)
9827 reg1 = REGNO (addr1);
9828 /* This was a simple (mem (reg)) expression. Offset is 0. */
9832 /* And now for the second addr. */
9833 if (GET_CODE (addr2) == PLUS)
9835 /* If not a REG, return zero. */
9836 if (GET_CODE (XEXP (addr2, 0)) != REG)
9840 reg2 = REGNO (XEXP (addr2, 0));
9841 /* The offset must be constant. */
9842 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9844 offset2 = INTVAL (XEXP (addr2, 1));
9847 else if (GET_CODE (addr2) != REG)
9851 reg2 = REGNO (addr2);
9852 /* This was a simple (mem (reg)) expression. Offset is 0. */
9856 /* Both of these must have the same base register. */
9860 /* The offset for the second addr must be 8 more than the first addr. */
9861 if (offset2 != offset1 + 8)
9864 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9869 /* Return the register class of a scratch register needed to copy IN into
9870 or out of a register in CLASS in MODE. If it can be done directly,
9871 NO_REGS is returned. */
9874 rs6000_secondary_reload_class (enum reg_class class,
9875 enum machine_mode mode ATTRIBUTE_UNUSED,
9880 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9882 && MACHOPIC_INDIRECT
9886 /* We cannot copy a symbolic operand directly into anything
9887 other than BASE_REGS for TARGET_ELF. So indicate that a
9888 register from BASE_REGS is needed as an intermediate
9891 On Darwin, pic addresses require a load from memory, which
9892 needs a base register. */
9893 if (class != BASE_REGS
9894 && (GET_CODE (in) == SYMBOL_REF
9895 || GET_CODE (in) == HIGH
9896 || GET_CODE (in) == LABEL_REF
9897 || GET_CODE (in) == CONST))
9901 if (GET_CODE (in) == REG)
9904 if (regno >= FIRST_PSEUDO_REGISTER)
9906 regno = true_regnum (in);
9907 if (regno >= FIRST_PSEUDO_REGISTER)
9911 else if (GET_CODE (in) == SUBREG)
9913 regno = true_regnum (in);
9914 if (regno >= FIRST_PSEUDO_REGISTER)
9920 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9922 if (class == GENERAL_REGS || class == BASE_REGS
9923 || (regno >= 0 && INT_REGNO_P (regno)))
9926 /* Constants, memory, and FP registers can go into FP registers. */
9927 if ((regno == -1 || FP_REGNO_P (regno))
9928 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9931 /* Memory, and AltiVec registers can go into AltiVec registers. */
9932 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9933 && class == ALTIVEC_REGS)
9936 /* We can copy among the CR registers. */
9937 if ((class == CR_REGS || class == CR0_REGS)
9938 && regno >= 0 && CR_REGNO_P (regno))
9941 /* Otherwise, we need GENERAL_REGS. */
9942 return GENERAL_REGS;
9945 /* Given a comparison operation, return the bit number in CCR to test. We
9946 know this is a valid comparison.
9948 SCC_P is 1 if this is for an scc. That means that %D will have been
9949 used instead of %C, so the bits will be in different places.
9951 Return -1 if OP isn't a valid comparison for some reason. */
9954 ccr_bit (rtx op, int scc_p)
9956 enum rtx_code code = GET_CODE (op);
9957 enum machine_mode cc_mode;
9962 if (!COMPARISON_P (op))
9967 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9969 cc_mode = GET_MODE (reg);
9970 cc_regnum = REGNO (reg);
9971 base_bit = 4 * (cc_regnum - CR0_REGNO);
9973 validate_condition_mode (code, cc_mode);
9975 /* When generating a sCOND operation, only positive conditions are
9978 || code == EQ || code == GT || code == LT || code == UNORDERED
9979 || code == GTU || code == LTU);
9984 return scc_p ? base_bit + 3 : base_bit + 2;
9986 return base_bit + 2;
9987 case GT: case GTU: case UNLE:
9988 return base_bit + 1;
9989 case LT: case LTU: case UNGE:
9991 case ORDERED: case UNORDERED:
9992 return base_bit + 3;
9995 /* If scc, we will have done a cror to put the bit in the
9996 unordered position. So test that bit. For integer, this is ! LT
9997 unless this is an scc insn. */
9998 return scc_p ? base_bit + 3 : base_bit;
10001 return scc_p ? base_bit + 3 : base_bit + 1;
10004 gcc_unreachable ();
10008 /* Return the GOT register. */
10011 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10013 /* The second flow pass currently (June 1999) can't update
10014 regs_ever_live without disturbing other parts of the compiler, so
10015 update it here to make the prolog/epilogue code happy. */
10016 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10017 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10019 current_function_uses_pic_offset_table = 1;
10021 return pic_offset_table_rtx;
10024 /* Function to init struct machine_function.
10025 This will be called, via a pointer variable,
10026 from push_function_context. */
10028 static struct machine_function *
10029 rs6000_init_machine_status (void)
10031 return ggc_alloc_cleared (sizeof (machine_function));
10034 /* These macros test for integers and extract the low-order bits. */
10036 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10037 && GET_MODE (X) == VOIDmode)
10039 #define INT_LOWPART(X) \
10040 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10043 extract_MB (rtx op)
10046 unsigned long val = INT_LOWPART (op);
10048 /* If the high bit is zero, the value is the first 1 bit we find
10050 if ((val & 0x80000000) == 0)
10052 gcc_assert (val & 0xffffffff);
10055 while (((val <<= 1) & 0x80000000) == 0)
10060 /* If the high bit is set and the low bit is not, or the mask is all
10061 1's, the value is zero. */
10062 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10065 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10068 while (((val >>= 1) & 1) != 0)
10075 extract_ME (rtx op)
10078 unsigned long val = INT_LOWPART (op);
10080 /* If the low bit is zero, the value is the first 1 bit we find from
10082 if ((val & 1) == 0)
10084 gcc_assert (val & 0xffffffff);
10087 while (((val >>= 1) & 1) == 0)
10093 /* If the low bit is set and the high bit is not, or the mask is all
10094 1's, the value is 31. */
10095 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10098 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10101 while (((val <<= 1) & 0x80000000) != 0)
10107 /* Locate some local-dynamic symbol still in use by this function
10108 so that we can print its name in some tls_ld pattern. */
10110 static const char *
10111 rs6000_get_some_local_dynamic_name (void)
10115 if (cfun->machine->some_ld_name)
10116 return cfun->machine->some_ld_name;
10118 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10120 && for_each_rtx (&PATTERN (insn),
10121 rs6000_get_some_local_dynamic_name_1, 0))
10122 return cfun->machine->some_ld_name;
10124 gcc_unreachable ();
10127 /* Helper function for rs6000_get_some_local_dynamic_name. */
10130 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10134 if (GET_CODE (x) == SYMBOL_REF)
10136 const char *str = XSTR (x, 0);
10137 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10139 cfun->machine->some_ld_name = str;
10147 /* Write out a function code label. */
10150 rs6000_output_function_entry (FILE *file, const char *fname)
10152 if (fname[0] != '.')
10154 switch (DEFAULT_ABI)
10157 gcc_unreachable ();
10163 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10172 RS6000_OUTPUT_BASENAME (file, fname);
10174 assemble_name (file, fname);
10177 /* Print an operand. Recognize special options, documented below. */
10180 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10181 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10183 #define SMALL_DATA_RELOC "sda21"
10184 #define SMALL_DATA_REG 0
10188 print_operand (FILE *file, rtx x, int code)
10192 unsigned HOST_WIDE_INT uval;
10197 /* Write out an instruction after the call which may be replaced
10198 with glue code by the loader. This depends on the AIX version. */
10199 asm_fprintf (file, RS6000_CALL_GLUE);
10202 /* %a is output_address. */
10205 /* If X is a constant integer whose low-order 5 bits are zero,
10206 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10207 in the AIX assembler where "sri" with a zero shift count
10208 writes a trash instruction. */
10209 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10216 /* If constant, low-order 16 bits of constant, unsigned.
10217 Otherwise, write normally. */
10219 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10221 print_operand (file, x, 0);
10225 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10226 for 64-bit mask direction. */
10227 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10230 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10234 /* X is a CR register. Print the number of the GT bit of the CR. */
10235 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10236 output_operand_lossage ("invalid %%E value");
10238 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10242 /* Like 'J' but get to the EQ bit. */
10243 gcc_assert (GET_CODE (x) == REG);
10245 /* Bit 1 is EQ bit. */
10246 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10248 fprintf (file, "%d", i);
10252 /* X is a CR register. Print the number of the EQ bit of the CR */
10253 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10254 output_operand_lossage ("invalid %%E value");
10256 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10260 /* X is a CR register. Print the shift count needed to move it
10261 to the high-order four bits. */
10262 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10263 output_operand_lossage ("invalid %%f value");
10265 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10269 /* Similar, but print the count for the rotate in the opposite
10271 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10272 output_operand_lossage ("invalid %%F value");
10274 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10278 /* X is a constant integer. If it is negative, print "m",
10279 otherwise print "z". This is to make an aze or ame insn. */
10280 if (GET_CODE (x) != CONST_INT)
10281 output_operand_lossage ("invalid %%G value");
10282 else if (INTVAL (x) >= 0)
10289 /* If constant, output low-order five bits. Otherwise, write
10292 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10294 print_operand (file, x, 0);
10298 /* If constant, output low-order six bits. Otherwise, write
10301 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10303 print_operand (file, x, 0);
10307 /* Print `i' if this is a constant, else nothing. */
10313 /* Write the bit number in CCR for jump. */
10314 i = ccr_bit (x, 0);
10316 output_operand_lossage ("invalid %%j code");
10318 fprintf (file, "%d", i);
10322 /* Similar, but add one for shift count in rlinm for scc and pass
10323 scc flag to `ccr_bit'. */
10324 i = ccr_bit (x, 1);
10326 output_operand_lossage ("invalid %%J code");
10328 /* If we want bit 31, write a shift count of zero, not 32. */
10329 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10333 /* X must be a constant. Write the 1's complement of the
10336 output_operand_lossage ("invalid %%k value");
10338 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10342 /* X must be a symbolic constant on ELF. Write an
10343 expression suitable for an 'addi' that adds in the low 16
10344 bits of the MEM. */
10345 if (GET_CODE (x) != CONST)
10347 print_operand_address (file, x);
10348 fputs ("@l", file);
10352 if (GET_CODE (XEXP (x, 0)) != PLUS
10353 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10354 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10355 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10356 output_operand_lossage ("invalid %%K value");
10357 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10358 fputs ("@l", file);
10359 /* For GNU as, there must be a non-alphanumeric character
10360 between 'l' and the number. The '-' is added by
10361 print_operand() already. */
10362 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10364 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10368 /* %l is output_asm_label. */
10371 /* Write second word of DImode or DFmode reference. Works on register
10372 or non-indexed memory only. */
10373 if (GET_CODE (x) == REG)
10374 fputs (reg_names[REGNO (x) + 1], file);
10375 else if (GET_CODE (x) == MEM)
10377 /* Handle possible auto-increment. Since it is pre-increment and
10378 we have already done it, we can just use an offset of word. */
10379 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10380 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10381 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10384 output_address (XEXP (adjust_address_nv (x, SImode,
10388 if (small_data_operand (x, GET_MODE (x)))
10389 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10390 reg_names[SMALL_DATA_REG]);
10395 /* MB value for a mask operand. */
10396 if (! mask_operand (x, SImode))
10397 output_operand_lossage ("invalid %%m value");
10399 fprintf (file, "%d", extract_MB (x));
10403 /* ME value for a mask operand. */
10404 if (! mask_operand (x, SImode))
10405 output_operand_lossage ("invalid %%M value");
10407 fprintf (file, "%d", extract_ME (x));
10410 /* %n outputs the negative of its operand. */
10413 /* Write the number of elements in the vector times 4. */
10414 if (GET_CODE (x) != PARALLEL)
10415 output_operand_lossage ("invalid %%N value");
10417 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10421 /* Similar, but subtract 1 first. */
10422 if (GET_CODE (x) != PARALLEL)
10423 output_operand_lossage ("invalid %%O value");
10425 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10429 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10431 || INT_LOWPART (x) < 0
10432 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10433 output_operand_lossage ("invalid %%p value");
10435 fprintf (file, "%d", i);
10439 /* The operand must be an indirect memory reference. The result
10440 is the register name. */
10441 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10442 || REGNO (XEXP (x, 0)) >= 32)
10443 output_operand_lossage ("invalid %%P value");
10445 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10449 /* This outputs the logical code corresponding to a boolean
10450 expression. The expression may have one or both operands
10451 negated (if one, only the first one). For condition register
10452 logical operations, it will also treat the negated
10453 CR codes as NOTs, but not handle NOTs of them. */
10455 const char *const *t = 0;
10457 enum rtx_code code = GET_CODE (x);
10458 static const char * const tbl[3][3] = {
10459 { "and", "andc", "nor" },
10460 { "or", "orc", "nand" },
10461 { "xor", "eqv", "xor" } };
10465 else if (code == IOR)
10467 else if (code == XOR)
10470 output_operand_lossage ("invalid %%q value");
10472 if (GET_CODE (XEXP (x, 0)) != NOT)
10476 if (GET_CODE (XEXP (x, 1)) == NOT)
10494 /* X is a CR register. Print the mask for `mtcrf'. */
10495 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10496 output_operand_lossage ("invalid %%R value");
10498 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10502 /* Low 5 bits of 32 - value */
10504 output_operand_lossage ("invalid %%s value");
10506 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10510 /* PowerPC64 mask position. All 0's is excluded.
10511 CONST_INT 32-bit mask is considered sign-extended so any
10512 transition must occur within the CONST_INT, not on the boundary. */
10513 if (! mask64_operand (x, DImode))
10514 output_operand_lossage ("invalid %%S value");
10516 uval = INT_LOWPART (x);
10518 if (uval & 1) /* Clear Left */
10520 #if HOST_BITS_PER_WIDE_INT > 64
10521 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10525 else /* Clear Right */
10528 #if HOST_BITS_PER_WIDE_INT > 64
10529 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10535 gcc_assert (i >= 0);
10536 fprintf (file, "%d", i);
10540 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10541 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10543 /* Bit 3 is OV bit. */
10544 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10546 /* If we want bit 31, write a shift count of zero, not 32. */
10547 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10551 /* Print the symbolic name of a branch target register. */
10552 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10553 && REGNO (x) != COUNT_REGISTER_REGNUM))
10554 output_operand_lossage ("invalid %%T value");
10555 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10556 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10558 fputs ("ctr", file);
10562 /* High-order 16 bits of constant for use in unsigned operand. */
10564 output_operand_lossage ("invalid %%u value");
10566 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10567 (INT_LOWPART (x) >> 16) & 0xffff);
10571 /* High-order 16 bits of constant for use in signed operand. */
10573 output_operand_lossage ("invalid %%v value");
10575 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10576 (INT_LOWPART (x) >> 16) & 0xffff);
10580 /* Print `u' if this has an auto-increment or auto-decrement. */
10581 if (GET_CODE (x) == MEM
10582 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10583 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10588 /* Print the trap code for this operand. */
10589 switch (GET_CODE (x))
10592 fputs ("eq", file); /* 4 */
10595 fputs ("ne", file); /* 24 */
10598 fputs ("lt", file); /* 16 */
10601 fputs ("le", file); /* 20 */
10604 fputs ("gt", file); /* 8 */
10607 fputs ("ge", file); /* 12 */
10610 fputs ("llt", file); /* 2 */
10613 fputs ("lle", file); /* 6 */
10616 fputs ("lgt", file); /* 1 */
10619 fputs ("lge", file); /* 5 */
10622 gcc_unreachable ();
10627 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10630 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10631 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10633 print_operand (file, x, 0);
10637 /* MB value for a PowerPC64 rldic operand. */
10638 val = (GET_CODE (x) == CONST_INT
10639 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10644 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10645 if ((val <<= 1) < 0)
10648 #if HOST_BITS_PER_WIDE_INT == 32
10649 if (GET_CODE (x) == CONST_INT && i >= 0)
10650 i += 32; /* zero-extend high-part was all 0's */
10651 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10653 val = CONST_DOUBLE_LOW (x);
10659 for ( ; i < 64; i++)
10660 if ((val <<= 1) < 0)
10665 fprintf (file, "%d", i + 1);
10669 if (GET_CODE (x) == MEM
10670 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10675 /* Like 'L', for third word of TImode */
10676 if (GET_CODE (x) == REG)
10677 fputs (reg_names[REGNO (x) + 2], file);
10678 else if (GET_CODE (x) == MEM)
10680 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10681 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10682 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10684 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10685 if (small_data_operand (x, GET_MODE (x)))
10686 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10687 reg_names[SMALL_DATA_REG]);
10692 /* X is a SYMBOL_REF. Write out the name preceded by a
10693 period and without any trailing data in brackets. Used for function
10694 names. If we are configured for System V (or the embedded ABI) on
10695 the PowerPC, do not emit the period, since those systems do not use
10696 TOCs and the like. */
10697 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10699 /* Mark the decl as referenced so that cgraph will output the
10701 if (SYMBOL_REF_DECL (x))
10702 mark_decl_referenced (SYMBOL_REF_DECL (x));
10704 /* For macho, check to see if we need a stub. */
10707 const char *name = XSTR (x, 0);
10709 if (MACHOPIC_INDIRECT
10710 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10711 name = machopic_indirection_name (x, /*stub_p=*/true);
10713 assemble_name (file, name);
10715 else if (!DOT_SYMBOLS)
10716 assemble_name (file, XSTR (x, 0));
10718 rs6000_output_function_entry (file, XSTR (x, 0));
10722 /* Like 'L', for last word of TImode. */
10723 if (GET_CODE (x) == REG)
10724 fputs (reg_names[REGNO (x) + 3], file);
10725 else if (GET_CODE (x) == MEM)
10727 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10728 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10729 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10731 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10732 if (small_data_operand (x, GET_MODE (x)))
10733 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10734 reg_names[SMALL_DATA_REG]);
10738 /* Print AltiVec or SPE memory operand. */
10743 gcc_assert (GET_CODE (x) == MEM);
10749 /* Handle [reg]. */
10750 if (GET_CODE (tmp) == REG)
10752 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10755 /* Handle [reg+UIMM]. */
10756 else if (GET_CODE (tmp) == PLUS &&
10757 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10761 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10763 x = INTVAL (XEXP (tmp, 1));
10764 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10768 /* Fall through. Must be [reg+reg]. */
10771 && GET_CODE (tmp) == AND
10772 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10773 && INTVAL (XEXP (tmp, 1)) == -16)
10774 tmp = XEXP (tmp, 0);
10775 if (GET_CODE (tmp) == REG)
10776 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10779 gcc_assert (GET_CODE (tmp) == PLUS
10780 && REG_P (XEXP (tmp, 0))
10781 && REG_P (XEXP (tmp, 1)));
10783 if (REGNO (XEXP (tmp, 0)) == 0)
10784 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10785 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10787 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10788 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10794 if (GET_CODE (x) == REG)
10795 fprintf (file, "%s", reg_names[REGNO (x)]);
10796 else if (GET_CODE (x) == MEM)
10798 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10799 know the width from the mode. */
10800 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10801 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10802 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10803 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10804 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10805 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10807 output_address (XEXP (x, 0));
10810 output_addr_const (file, x);
10814 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10818 output_operand_lossage ("invalid %%xn code");
10822 /* Print the address of an operand. */
10825 print_operand_address (FILE *file, rtx x)
10827 if (GET_CODE (x) == REG)
10828 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10829 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10830 || GET_CODE (x) == LABEL_REF)
10832 output_addr_const (file, x);
10833 if (small_data_operand (x, GET_MODE (x)))
10834 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10835 reg_names[SMALL_DATA_REG]);
10837 gcc_assert (!TARGET_TOC);
10839 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10841 gcc_assert (REG_P (XEXP (x, 0)));
10842 if (REGNO (XEXP (x, 0)) == 0)
10843 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10844 reg_names[ REGNO (XEXP (x, 0)) ]);
10846 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10847 reg_names[ REGNO (XEXP (x, 1)) ]);
10849 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10850 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10851 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10853 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10854 && CONSTANT_P (XEXP (x, 1)))
10856 output_addr_const (file, XEXP (x, 1));
10857 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10861 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10862 && CONSTANT_P (XEXP (x, 1)))
10864 fprintf (file, "lo16(");
10865 output_addr_const (file, XEXP (x, 1));
10866 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10869 else if (legitimate_constant_pool_address_p (x))
10871 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10873 rtx contains_minus = XEXP (x, 1);
10877 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10878 turn it into (sym) for output_addr_const. */
10879 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10880 contains_minus = XEXP (contains_minus, 0);
10882 minus = XEXP (contains_minus, 0);
10883 symref = XEXP (minus, 0);
10884 XEXP (contains_minus, 0) = symref;
10889 name = XSTR (symref, 0);
10890 newname = alloca (strlen (name) + sizeof ("@toc"));
10891 strcpy (newname, name);
10892 strcat (newname, "@toc");
10893 XSTR (symref, 0) = newname;
10895 output_addr_const (file, XEXP (x, 1));
10897 XSTR (symref, 0) = name;
10898 XEXP (contains_minus, 0) = minus;
10901 output_addr_const (file, XEXP (x, 1));
10903 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10906 gcc_unreachable ();
10909 /* Target hook for assembling integer objects. The PowerPC version has
10910 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10911 is defined. It also needs to handle DI-mode objects on 64-bit
10915 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10917 #ifdef RELOCATABLE_NEEDS_FIXUP
10918 /* Special handling for SI values. */
10919 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10921 static int recurse = 0;
10923 /* For -mrelocatable, we mark all addresses that need to be fixed up
10924 in the .fixup section. */
10925 if (TARGET_RELOCATABLE
10926 && in_section != toc_section
10927 && in_section != text_section
10928 && !unlikely_text_section_p (in_section)
10930 && GET_CODE (x) != CONST_INT
10931 && GET_CODE (x) != CONST_DOUBLE
10937 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10939 ASM_OUTPUT_LABEL (asm_out_file, buf);
10940 fprintf (asm_out_file, "\t.long\t(");
10941 output_addr_const (asm_out_file, x);
10942 fprintf (asm_out_file, ")@fixup\n");
10943 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10944 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10945 fprintf (asm_out_file, "\t.long\t");
10946 assemble_name (asm_out_file, buf);
10947 fprintf (asm_out_file, "\n\t.previous\n");
10951 /* Remove initial .'s to turn a -mcall-aixdesc function
10952 address into the address of the descriptor, not the function
10954 else if (GET_CODE (x) == SYMBOL_REF
10955 && XSTR (x, 0)[0] == '.'
10956 && DEFAULT_ABI == ABI_AIX)
10958 const char *name = XSTR (x, 0);
10959 while (*name == '.')
10962 fprintf (asm_out_file, "\t.long\t%s\n", name);
10966 #endif /* RELOCATABLE_NEEDS_FIXUP */
10967 return default_assemble_integer (x, size, aligned_p);
10970 #ifdef HAVE_GAS_HIDDEN
10971 /* Emit an assembler directive to set symbol visibility for DECL to
10972 VISIBILITY_TYPE. */
10975 rs6000_assemble_visibility (tree decl, int vis)
10977 /* Functions need to have their entry point symbol visibility set as
10978 well as their descriptor symbol visibility. */
10979 if (DEFAULT_ABI == ABI_AIX
10981 && TREE_CODE (decl) == FUNCTION_DECL)
10983 static const char * const visibility_types[] = {
10984 NULL, "internal", "hidden", "protected"
10987 const char *name, *type;
10989 name = ((* targetm.strip_name_encoding)
10990 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10991 type = visibility_types[vis];
10993 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10994 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10997 default_assemble_visibility (decl, vis);
11002 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11004 /* Reversal of FP compares takes care -- an ordered compare
11005 becomes an unordered compare and vice versa. */
11006 if (mode == CCFPmode
11007 && (!flag_finite_math_only
11008 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11009 || code == UNEQ || code == LTGT))
11010 return reverse_condition_maybe_unordered (code);
11012 return reverse_condition (code);
11015 /* Generate a compare for CODE. Return a brand-new rtx that
11016 represents the result of the compare. */
11019 rs6000_generate_compare (enum rtx_code code)
11021 enum machine_mode comp_mode;
11022 rtx compare_result;
11024 if (rs6000_compare_fp_p)
11025 comp_mode = CCFPmode;
11026 else if (code == GTU || code == LTU
11027 || code == GEU || code == LEU)
11028 comp_mode = CCUNSmode;
11029 else if ((code == EQ || code == NE)
11030 && GET_CODE (rs6000_compare_op0) == SUBREG
11031 && GET_CODE (rs6000_compare_op1) == SUBREG
11032 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11033 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11034 /* These are unsigned values, perhaps there will be a later
11035 ordering compare that can be shared with this one.
11036 Unfortunately we cannot detect the signedness of the operands
11037 for non-subregs. */
11038 comp_mode = CCUNSmode;
11040 comp_mode = CCmode;
11042 /* First, the compare. */
11043 compare_result = gen_reg_rtx (comp_mode);
11045 /* SPE FP compare instructions on the GPRs. Yuck! */
11046 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11047 && rs6000_compare_fp_p)
11049 rtx cmp, or_result, compare_result2;
11050 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11052 if (op_mode == VOIDmode)
11053 op_mode = GET_MODE (rs6000_compare_op1);
11055 /* Note: The E500 comparison instructions set the GT bit (x +
11056 1), on success. This explains the mess. */
11060 case EQ: case UNEQ: case NE: case LTGT:
11064 cmp = flag_unsafe_math_optimizations
11065 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11066 rs6000_compare_op1)
11067 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11068 rs6000_compare_op1);
11072 cmp = flag_unsafe_math_optimizations
11073 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11074 rs6000_compare_op1)
11075 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11076 rs6000_compare_op1);
11080 gcc_unreachable ();
11084 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11088 cmp = flag_unsafe_math_optimizations
11089 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11090 rs6000_compare_op1)
11091 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11092 rs6000_compare_op1);
11096 cmp = flag_unsafe_math_optimizations
11097 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11098 rs6000_compare_op1)
11099 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11100 rs6000_compare_op1);
11104 gcc_unreachable ();
11108 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11112 cmp = flag_unsafe_math_optimizations
11113 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11114 rs6000_compare_op1)
11115 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11116 rs6000_compare_op1);
11120 cmp = flag_unsafe_math_optimizations
11121 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11122 rs6000_compare_op1)
11123 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11124 rs6000_compare_op1);
11128 gcc_unreachable ();
11132 gcc_unreachable ();
11135 /* Synthesize LE and GE from LT/GT || EQ. */
11136 if (code == LE || code == GE || code == LEU || code == GEU)
11142 case LE: code = LT; break;
11143 case GE: code = GT; break;
11144 case LEU: code = LT; break;
11145 case GEU: code = GT; break;
11146 default: gcc_unreachable ();
11149 compare_result2 = gen_reg_rtx (CCFPmode);
11155 cmp = flag_unsafe_math_optimizations
11156 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11157 rs6000_compare_op1)
11158 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11159 rs6000_compare_op1);
11163 cmp = flag_unsafe_math_optimizations
11164 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11165 rs6000_compare_op1)
11166 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11167 rs6000_compare_op1);
11171 gcc_unreachable ();
11175 /* OR them together. */
11176 or_result = gen_reg_rtx (CCFPmode);
11177 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11179 compare_result = or_result;
11184 if (code == NE || code == LTGT)
11194 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11195 CLOBBERs to match cmptf_internal2 pattern. */
11196 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11197 && GET_MODE (rs6000_compare_op0) == TFmode
11198 && !TARGET_IEEEQUAD
11199 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11200 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11202 gen_rtx_SET (VOIDmode,
11204 gen_rtx_COMPARE (comp_mode,
11205 rs6000_compare_op0,
11206 rs6000_compare_op1)),
11207 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11208 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11209 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11210 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11211 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11212 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11213 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11214 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11215 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11216 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11218 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11219 comp_mode = CCEQmode;
11220 compare_result = gen_reg_rtx (CCEQmode);
11222 emit_insn (gen_stack_protect_testdi (compare_result,
11223 rs6000_compare_op0, op1));
11225 emit_insn (gen_stack_protect_testsi (compare_result,
11226 rs6000_compare_op0, op1));
11229 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11230 gen_rtx_COMPARE (comp_mode,
11231 rs6000_compare_op0,
11232 rs6000_compare_op1)));
11235 /* Some kinds of FP comparisons need an OR operation;
11236 under flag_finite_math_only we don't bother. */
11237 if (rs6000_compare_fp_p
11238 && !flag_finite_math_only
11239 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11240 && (code == LE || code == GE
11241 || code == UNEQ || code == LTGT
11242 || code == UNGT || code == UNLT))
11244 enum rtx_code or1, or2;
11245 rtx or1_rtx, or2_rtx, compare2_rtx;
11246 rtx or_result = gen_reg_rtx (CCEQmode);
11250 case LE: or1 = LT; or2 = EQ; break;
11251 case GE: or1 = GT; or2 = EQ; break;
11252 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11253 case LTGT: or1 = LT; or2 = GT; break;
11254 case UNGT: or1 = UNORDERED; or2 = GT; break;
11255 case UNLT: or1 = UNORDERED; or2 = LT; break;
11256 default: gcc_unreachable ();
11258 validate_condition_mode (or1, comp_mode);
11259 validate_condition_mode (or2, comp_mode);
11260 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11261 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11262 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11263 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11265 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11267 compare_result = or_result;
11271 validate_condition_mode (code, GET_MODE (compare_result));
11273 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11277 /* Emit the RTL for an sCOND pattern. */
11280 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11283 enum machine_mode op_mode;
11284 enum rtx_code cond_code;
11286 condition_rtx = rs6000_generate_compare (code);
11287 cond_code = GET_CODE (condition_rtx);
11289 if (TARGET_E500 && rs6000_compare_fp_p
11290 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11294 PUT_MODE (condition_rtx, SImode);
11295 t = XEXP (condition_rtx, 0);
11297 gcc_assert (cond_code == NE || cond_code == EQ);
11299 if (cond_code == NE)
11300 emit_insn (gen_e500_flip_gt_bit (t, t));
11302 emit_insn (gen_move_from_CR_gt_bit (result, t));
11306 if (cond_code == NE
11307 || cond_code == GE || cond_code == LE
11308 || cond_code == GEU || cond_code == LEU
11309 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11311 rtx not_result = gen_reg_rtx (CCEQmode);
11312 rtx not_op, rev_cond_rtx;
11313 enum machine_mode cc_mode;
11315 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11317 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11318 SImode, XEXP (condition_rtx, 0), const0_rtx);
11319 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11320 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11321 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11324 op_mode = GET_MODE (rs6000_compare_op0);
11325 if (op_mode == VOIDmode)
11326 op_mode = GET_MODE (rs6000_compare_op1);
11328 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11330 PUT_MODE (condition_rtx, DImode);
11331 convert_move (result, condition_rtx, 0);
11335 PUT_MODE (condition_rtx, SImode);
11336 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11340 /* Emit a branch of kind CODE to location LOC. */
11343 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11345 rtx condition_rtx, loc_ref;
11347 condition_rtx = rs6000_generate_compare (code);
11348 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11349 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11350 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11351 loc_ref, pc_rtx)));
11354 /* Return the string to output a conditional branch to LABEL, which is
11355 the operand number of the label, or -1 if the branch is really a
11356 conditional return.
11358 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11359 condition code register and its mode specifies what kind of
11360 comparison we made.
11362 REVERSED is nonzero if we should reverse the sense of the comparison.
11364 INSN is the insn. */
11367 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11369 static char string[64];
11370 enum rtx_code code = GET_CODE (op);
11371 rtx cc_reg = XEXP (op, 0);
11372 enum machine_mode mode = GET_MODE (cc_reg);
11373 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11374 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11375 int really_reversed = reversed ^ need_longbranch;
11381 validate_condition_mode (code, mode);
11383 /* Work out which way this really branches. We could use
11384 reverse_condition_maybe_unordered here always but this
11385 makes the resulting assembler clearer. */
11386 if (really_reversed)
11388 /* Reversal of FP compares takes care -- an ordered compare
11389 becomes an unordered compare and vice versa. */
11390 if (mode == CCFPmode)
11391 code = reverse_condition_maybe_unordered (code);
11393 code = reverse_condition (code);
11396 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11398 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11403 /* Opposite of GT. */
11412 gcc_unreachable ();
11418 /* Not all of these are actually distinct opcodes, but
11419 we distinguish them for clarity of the resulting assembler. */
11420 case NE: case LTGT:
11421 ccode = "ne"; break;
11422 case EQ: case UNEQ:
11423 ccode = "eq"; break;
11425 ccode = "ge"; break;
11426 case GT: case GTU: case UNGT:
11427 ccode = "gt"; break;
11429 ccode = "le"; break;
11430 case LT: case LTU: case UNLT:
11431 ccode = "lt"; break;
11432 case UNORDERED: ccode = "un"; break;
11433 case ORDERED: ccode = "nu"; break;
11434 case UNGE: ccode = "nl"; break;
11435 case UNLE: ccode = "ng"; break;
11437 gcc_unreachable ();
11440 /* Maybe we have a guess as to how likely the branch is.
11441 The old mnemonics don't have a way to specify this information. */
11443 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11444 if (note != NULL_RTX)
11446 /* PROB is the difference from 50%. */
11447 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11449 /* Only hint for highly probable/improbable branches on newer
11450 cpus as static prediction overrides processor dynamic
11451 prediction. For older cpus we may as well always hint, but
11452 assume not taken for branches that are very close to 50% as a
11453 mispredicted taken branch is more expensive than a
11454 mispredicted not-taken branch. */
11455 if (rs6000_always_hint
11456 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11458 if (abs (prob) > REG_BR_PROB_BASE / 20
11459 && ((prob > 0) ^ need_longbranch))
11467 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11469 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11471 /* We need to escape any '%' characters in the reg_names string.
11472 Assume they'd only be the first character.... */
11473 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11475 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11479 /* If the branch distance was too far, we may have to use an
11480 unconditional branch to go the distance. */
11481 if (need_longbranch)
11482 s += sprintf (s, ",$+8\n\tb %s", label);
11484 s += sprintf (s, ",%s", label);
11490 /* Return the string to flip the GT bit on a CR. */
11492 output_e500_flip_gt_bit (rtx dst, rtx src)
11494 static char string[64];
11497 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11498 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11501 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11502 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11504 sprintf (string, "crnot %d,%d", a, b);
11508 /* Return insn index for the vector compare instruction for given CODE,
11509 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11513 get_vec_cmp_insn (enum rtx_code code,
11514 enum machine_mode dest_mode,
11515 enum machine_mode op_mode)
11517 if (!TARGET_ALTIVEC)
11518 return INSN_NOT_AVAILABLE;
11523 if (dest_mode == V16QImode && op_mode == V16QImode)
11524 return UNSPEC_VCMPEQUB;
11525 if (dest_mode == V8HImode && op_mode == V8HImode)
11526 return UNSPEC_VCMPEQUH;
11527 if (dest_mode == V4SImode && op_mode == V4SImode)
11528 return UNSPEC_VCMPEQUW;
11529 if (dest_mode == V4SImode && op_mode == V4SFmode)
11530 return UNSPEC_VCMPEQFP;
11533 if (dest_mode == V4SImode && op_mode == V4SFmode)
11534 return UNSPEC_VCMPGEFP;
11536 if (dest_mode == V16QImode && op_mode == V16QImode)
11537 return UNSPEC_VCMPGTSB;
11538 if (dest_mode == V8HImode && op_mode == V8HImode)
11539 return UNSPEC_VCMPGTSH;
11540 if (dest_mode == V4SImode && op_mode == V4SImode)
11541 return UNSPEC_VCMPGTSW;
11542 if (dest_mode == V4SImode && op_mode == V4SFmode)
11543 return UNSPEC_VCMPGTFP;
11546 if (dest_mode == V16QImode && op_mode == V16QImode)
11547 return UNSPEC_VCMPGTUB;
11548 if (dest_mode == V8HImode && op_mode == V8HImode)
11549 return UNSPEC_VCMPGTUH;
11550 if (dest_mode == V4SImode && op_mode == V4SImode)
11551 return UNSPEC_VCMPGTUW;
11556 return INSN_NOT_AVAILABLE;
11559 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11560 DMODE is expected destination mode. This is a recursive function. */
11563 rs6000_emit_vector_compare (enum rtx_code rcode,
11565 enum machine_mode dmode)
11569 enum machine_mode dest_mode;
11570 enum machine_mode op_mode = GET_MODE (op1);
11572 gcc_assert (TARGET_ALTIVEC);
11573 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11575 /* Floating point vector compare instructions uses destination V4SImode.
11576 Move destination to appropriate mode later. */
11577 if (dmode == V4SFmode)
11578 dest_mode = V4SImode;
11582 mask = gen_reg_rtx (dest_mode);
11583 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11585 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11587 bool swap_operands = false;
11588 bool try_again = false;
11593 swap_operands = true;
11598 swap_operands = true;
11602 /* Treat A != B as ~(A==B). */
11604 enum insn_code nor_code;
11605 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11608 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11609 gcc_assert (nor_code != CODE_FOR_nothing);
11610 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11612 if (dmode != dest_mode)
11614 rtx temp = gen_reg_rtx (dest_mode);
11615 convert_move (temp, mask, 0);
11625 /* Try GT/GTU/LT/LTU OR EQ */
11628 enum insn_code ior_code;
11629 enum rtx_code new_code;
11650 gcc_unreachable ();
11653 c_rtx = rs6000_emit_vector_compare (new_code,
11654 op0, op1, dest_mode);
11655 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11658 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11659 gcc_assert (ior_code != CODE_FOR_nothing);
11660 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11661 if (dmode != dest_mode)
11663 rtx temp = gen_reg_rtx (dest_mode);
11664 convert_move (temp, mask, 0);
11671 gcc_unreachable ();
11676 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11677 /* You only get two chances. */
11678 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11690 emit_insn (gen_rtx_SET (VOIDmode, mask,
11691 gen_rtx_UNSPEC (dest_mode,
11692 gen_rtvec (2, op0, op1),
11694 if (dmode != dest_mode)
11696 rtx temp = gen_reg_rtx (dest_mode);
11697 convert_move (temp, mask, 0);
11703 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11704 valid insn doesn exist for given mode. */
11707 get_vsel_insn (enum machine_mode mode)
11712 return UNSPEC_VSEL4SI;
11715 return UNSPEC_VSEL4SF;
11718 return UNSPEC_VSEL8HI;
11721 return UNSPEC_VSEL16QI;
11724 return INSN_NOT_AVAILABLE;
11727 return INSN_NOT_AVAILABLE;
11730 /* Emit vector select insn where DEST is destination using
11731 operands OP1, OP2 and MASK. */
11734 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11737 enum machine_mode dest_mode = GET_MODE (dest);
11738 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11740 temp = gen_reg_rtx (dest_mode);
11742 /* For each vector element, select op1 when mask is 1 otherwise
11744 t = gen_rtx_SET (VOIDmode, temp,
11745 gen_rtx_UNSPEC (dest_mode,
11746 gen_rtvec (3, op2, op1, mask),
11749 emit_move_insn (dest, temp);
11753 /* Emit vector conditional expression.
11754 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11755 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11758 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11759 rtx cond, rtx cc_op0, rtx cc_op1)
11761 enum machine_mode dest_mode = GET_MODE (dest);
11762 enum rtx_code rcode = GET_CODE (cond);
11765 if (!TARGET_ALTIVEC)
11768 /* Get the vector mask for the given relational operations. */
11769 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11771 rs6000_emit_vector_select (dest, op1, op2, mask);
11776 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11777 operands of the last comparison is nonzero/true, FALSE_COND if it
11778 is zero/false. Return 0 if the hardware has no such operation. */
11781 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11783 enum rtx_code code = GET_CODE (op);
11784 rtx op0 = rs6000_compare_op0;
11785 rtx op1 = rs6000_compare_op1;
11786 REAL_VALUE_TYPE c1;
11787 enum machine_mode compare_mode = GET_MODE (op0);
11788 enum machine_mode result_mode = GET_MODE (dest);
11790 bool is_against_zero;
11792 /* These modes should always match. */
11793 if (GET_MODE (op1) != compare_mode
11794 /* In the isel case however, we can use a compare immediate, so
11795 op1 may be a small constant. */
11796 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11798 if (GET_MODE (true_cond) != result_mode)
11800 if (GET_MODE (false_cond) != result_mode)
11803 /* First, work out if the hardware can do this at all, or
11804 if it's too slow.... */
11805 if (! rs6000_compare_fp_p)
11808 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11811 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11812 && SCALAR_FLOAT_MODE_P (compare_mode))
11815 is_against_zero = op1 == CONST0_RTX (compare_mode);
11817 /* A floating-point subtract might overflow, underflow, or produce
11818 an inexact result, thus changing the floating-point flags, so it
11819 can't be generated if we care about that. It's safe if one side
11820 of the construct is zero, since then no subtract will be
11822 if (SCALAR_FLOAT_MODE_P (compare_mode)
11823 && flag_trapping_math && ! is_against_zero)
11826 /* Eliminate half of the comparisons by switching operands, this
11827 makes the remaining code simpler. */
11828 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11829 || code == LTGT || code == LT || code == UNLE)
11831 code = reverse_condition_maybe_unordered (code);
11833 true_cond = false_cond;
11837 /* UNEQ and LTGT take four instructions for a comparison with zero,
11838 it'll probably be faster to use a branch here too. */
11839 if (code == UNEQ && HONOR_NANS (compare_mode))
11842 if (GET_CODE (op1) == CONST_DOUBLE)
11843 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11845 /* We're going to try to implement comparisons by performing
11846 a subtract, then comparing against zero. Unfortunately,
11847 Inf - Inf is NaN which is not zero, and so if we don't
11848 know that the operand is finite and the comparison
11849 would treat EQ different to UNORDERED, we can't do it. */
11850 if (HONOR_INFINITIES (compare_mode)
11851 && code != GT && code != UNGE
11852 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11853 /* Constructs of the form (a OP b ? a : b) are safe. */
11854 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11855 || (! rtx_equal_p (op0, true_cond)
11856 && ! rtx_equal_p (op1, true_cond))))
11859 /* At this point we know we can use fsel. */
11861 /* Reduce the comparison to a comparison against zero. */
11862 if (! is_against_zero)
11864 temp = gen_reg_rtx (compare_mode);
11865 emit_insn (gen_rtx_SET (VOIDmode, temp,
11866 gen_rtx_MINUS (compare_mode, op0, op1)));
11868 op1 = CONST0_RTX (compare_mode);
11871 /* If we don't care about NaNs we can reduce some of the comparisons
11872 down to faster ones. */
11873 if (! HONOR_NANS (compare_mode))
11879 true_cond = false_cond;
11892 /* Now, reduce everything down to a GE. */
11899 temp = gen_reg_rtx (compare_mode);
11900 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11905 temp = gen_reg_rtx (compare_mode);
11906 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11911 temp = gen_reg_rtx (compare_mode);
11912 emit_insn (gen_rtx_SET (VOIDmode, temp,
11913 gen_rtx_NEG (compare_mode,
11914 gen_rtx_ABS (compare_mode, op0))));
11919 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11920 temp = gen_reg_rtx (result_mode);
11921 emit_insn (gen_rtx_SET (VOIDmode, temp,
11922 gen_rtx_IF_THEN_ELSE (result_mode,
11923 gen_rtx_GE (VOIDmode,
11925 true_cond, false_cond)));
11926 false_cond = true_cond;
11929 temp = gen_reg_rtx (compare_mode);
11930 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11935 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11936 temp = gen_reg_rtx (result_mode);
11937 emit_insn (gen_rtx_SET (VOIDmode, temp,
11938 gen_rtx_IF_THEN_ELSE (result_mode,
11939 gen_rtx_GE (VOIDmode,
11941 true_cond, false_cond)));
11942 true_cond = false_cond;
11945 temp = gen_reg_rtx (compare_mode);
11946 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11951 gcc_unreachable ();
11954 emit_insn (gen_rtx_SET (VOIDmode, dest,
11955 gen_rtx_IF_THEN_ELSE (result_mode,
11956 gen_rtx_GE (VOIDmode,
11958 true_cond, false_cond)));
11962 /* Same as above, but for ints (isel). */
11965 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11967 rtx condition_rtx, cr;
11969 /* All isel implementations thus far are 32-bits. */
11970 if (GET_MODE (rs6000_compare_op0) != SImode)
11973 /* We still have to do the compare, because isel doesn't do a
11974 compare, it just looks at the CRx bits set by a previous compare
11976 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11977 cr = XEXP (condition_rtx, 0);
11979 if (GET_MODE (cr) == CCmode)
11980 emit_insn (gen_isel_signed (dest, condition_rtx,
11981 true_cond, false_cond, cr));
11983 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11984 true_cond, false_cond, cr));
11990 output_isel (rtx *operands)
11992 enum rtx_code code;
11994 code = GET_CODE (operands[1]);
11995 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11997 PUT_CODE (operands[1], reverse_condition (code));
11998 return "isel %0,%3,%2,%j1";
12001 return "isel %0,%2,%3,%j1";
12005 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12007 enum machine_mode mode = GET_MODE (op0);
12011 if (code == SMAX || code == SMIN)
12016 if (code == SMAX || code == UMAX)
12017 target = emit_conditional_move (dest, c, op0, op1, mode,
12018 op0, op1, mode, 0);
12020 target = emit_conditional_move (dest, c, op0, op1, mode,
12021 op1, op0, mode, 0);
12022 gcc_assert (target);
12023 if (target != dest)
12024 emit_move_insn (dest, target);
12027 /* Emit instructions to perform a load-reserved/store-conditional operation.
12028 The operation performed is an atomic
12029 (set M (CODE:MODE M OP))
12030 If not NULL, BEFORE is atomically set to M before the operation, and
12031 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12032 If SYNC_P then a memory barrier is emitted before the operation.
12033 Either OP or M may be wrapped in a NOT operation. */
12036 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12037 rtx m, rtx op, rtx before_param, rtx after_param,
12040 enum machine_mode used_mode;
12041 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12044 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12045 rtx shift = NULL_RTX;
12048 emit_insn (gen_memory_barrier ());
12050 if (GET_CODE (m) == NOT)
12051 used_m = XEXP (m, 0);
12055 /* If this is smaller than SImode, we'll have to use SImode with
12057 if (mode == QImode || mode == HImode)
12061 if (MEM_ALIGN (used_m) >= 32)
12064 if (BYTES_BIG_ENDIAN)
12065 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12067 shift = GEN_INT (ishift);
12071 rtx addrSI, aligned_addr;
12072 int shift_mask = mode == QImode ? 0x18 : 0x10;
12074 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12075 XEXP (used_m, 0)));
12076 shift = gen_reg_rtx (SImode);
12078 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12079 GEN_INT (shift_mask)));
12080 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12082 aligned_addr = expand_binop (Pmode, and_optab,
12084 GEN_INT (-4), NULL_RTX,
12085 1, OPTAB_LIB_WIDEN);
12086 used_m = change_address (used_m, SImode, aligned_addr);
12087 set_mem_align (used_m, 32);
12088 /* It's safe to keep the old alias set of USED_M, because
12089 the operation is atomic and only affects the original
12091 if (GET_CODE (m) == NOT)
12092 m = gen_rtx_NOT (SImode, used_m);
12097 if (GET_CODE (op) == NOT)
12099 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12100 oldop = gen_rtx_NOT (SImode, oldop);
12103 oldop = lowpart_subreg (SImode, op, mode);
12109 newop = expand_binop (SImode, and_optab,
12110 oldop, GEN_INT (imask), NULL_RTX,
12111 1, OPTAB_LIB_WIDEN);
12112 emit_insn (gen_ashlsi3 (newop, newop, shift));
12116 newop = expand_binop (SImode, ior_optab,
12117 oldop, GEN_INT (~imask), NULL_RTX,
12118 1, OPTAB_LIB_WIDEN);
12119 emit_insn (gen_rotlsi3 (newop, newop, shift));
12127 newop = expand_binop (SImode, and_optab,
12128 oldop, GEN_INT (imask), NULL_RTX,
12129 1, OPTAB_LIB_WIDEN);
12130 emit_insn (gen_ashlsi3 (newop, newop, shift));
12132 mask = gen_reg_rtx (SImode);
12133 emit_move_insn (mask, GEN_INT (imask));
12134 emit_insn (gen_ashlsi3 (mask, mask, shift));
12137 newop = gen_rtx_PLUS (SImode, m, newop);
12139 newop = gen_rtx_MINUS (SImode, m, newop);
12140 newop = gen_rtx_AND (SImode, newop, mask);
12141 newop = gen_rtx_IOR (SImode, newop,
12142 gen_rtx_AND (SImode,
12143 gen_rtx_NOT (SImode, mask),
12149 gcc_unreachable ();
12152 if (GET_CODE (m) == NOT)
12156 mask = gen_reg_rtx (SImode);
12157 emit_move_insn (mask, GEN_INT (imask));
12158 emit_insn (gen_ashlsi3 (mask, mask, shift));
12160 xorm = gen_rtx_XOR (SImode, used_m, mask);
12161 /* Depending on the value of 'op', the XOR or the operation might
12162 be able to be simplified away. */
12163 newop = simplify_gen_binary (code, SImode, xorm, newop);
12166 used_mode = SImode;
12167 before = gen_reg_rtx (used_mode);
12168 after = gen_reg_rtx (used_mode);
12173 before = before_param;
12174 after = after_param;
12176 if (before == NULL_RTX)
12177 before = gen_reg_rtx (used_mode);
12178 if (after == NULL_RTX)
12179 after = gen_reg_rtx (used_mode);
12182 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12183 && used_mode != mode)
12184 the_op = op; /* Computed above. */
12185 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12186 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12188 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12190 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12191 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12192 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12193 gen_rtx_UNSPEC (used_mode,
12194 gen_rtvec (1, the_op),
12196 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12198 if ((code == PLUS || code == MINUS) && used_mode != mode)
12199 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12200 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12202 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12203 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12205 /* Shift and mask the return values properly. */
12206 if (used_mode != mode && before_param)
12208 emit_insn (gen_lshrsi3 (before, before, shift));
12209 convert_move (before_param, before, 1);
12212 if (used_mode != mode && after_param)
12214 emit_insn (gen_lshrsi3 (after, after, shift));
12215 convert_move (after_param, after, 1);
12218 /* The previous sequence will end with a branch that's dependent on
12219 the conditional store, so placing an isync will ensure that no
12220 other instructions (especially, no load or store instructions)
12221 can start before the atomic operation completes. */
12223 emit_insn (gen_isync ());
12226 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12227 COND is true. Mark the jump as unlikely to be taken. */
12230 emit_unlikely_jump (rtx cond, rtx label)
12232 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12235 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12236 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12237 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12240 /* A subroutine of the atomic operation splitters. Emit a load-locked
12241 instruction in MODE. */
12244 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12246 rtx (*fn) (rtx, rtx) = NULL;
12247 if (mode == SImode)
12248 fn = gen_load_locked_si;
12249 else if (mode == DImode)
12250 fn = gen_load_locked_di;
12251 emit_insn (fn (reg, mem));
12254 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12255 instruction in MODE. */
12258 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12260 rtx (*fn) (rtx, rtx, rtx) = NULL;
12261 if (mode == SImode)
12262 fn = gen_store_conditional_si;
12263 else if (mode == DImode)
12264 fn = gen_store_conditional_di;
12266 /* Emit sync before stwcx. to address PPC405 Erratum. */
12267 if (PPC405_ERRATUM77)
12268 emit_insn (gen_memory_barrier ());
12270 emit_insn (fn (res, mem, val));
12273 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12274 to perform. MEM is the memory on which to operate. VAL is the second
12275 operand of the binary operator. BEFORE and AFTER are optional locations to
12276 return the value of MEM either before of after the operation. SCRATCH is
12277 a scratch register. */
12280 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12281 rtx before, rtx after, rtx scratch)
12283 enum machine_mode mode = GET_MODE (mem);
12284 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12286 emit_insn (gen_memory_barrier ());
12288 label = gen_label_rtx ();
12289 emit_label (label);
12290 label = gen_rtx_LABEL_REF (VOIDmode, label);
12292 if (before == NULL_RTX)
12294 emit_load_locked (mode, before, mem);
12297 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12298 else if (code == AND)
12299 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12301 x = gen_rtx_fmt_ee (code, mode, before, val);
12303 if (after != NULL_RTX)
12304 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12305 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12307 emit_store_conditional (mode, cond, mem, scratch);
12309 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12310 emit_unlikely_jump (x, label);
12312 emit_insn (gen_isync ());
12315 /* Expand an atomic compare and swap operation. MEM is the memory on which
12316 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12317 value to be stored. SCRATCH is a scratch GPR. */
12320 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12323 enum machine_mode mode = GET_MODE (mem);
12324 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12326 emit_insn (gen_memory_barrier ());
12328 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12329 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12330 emit_label (XEXP (label1, 0));
12332 emit_load_locked (mode, retval, mem);
12334 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12335 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12337 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12338 emit_unlikely_jump (x, label2);
12340 emit_move_insn (scratch, newval);
12341 emit_store_conditional (mode, cond, mem, scratch);
12343 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12344 emit_unlikely_jump (x, label1);
12346 emit_insn (gen_isync ());
12347 emit_label (XEXP (label2, 0));
12350 /* Expand an atomic test and set operation. MEM is the memory on which
12351 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12354 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12356 enum machine_mode mode = GET_MODE (mem);
12357 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12359 emit_insn (gen_memory_barrier ());
12361 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12362 emit_label (XEXP (label, 0));
12364 emit_load_locked (mode, retval, mem);
12365 emit_move_insn (scratch, val);
12366 emit_store_conditional (mode, cond, mem, scratch);
12368 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12369 emit_unlikely_jump (x, label);
12371 emit_insn (gen_isync ());
12375 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12377 enum machine_mode mode = GET_MODE (mem);
12378 rtx addrSI, align, wdst, shift, mask;
12379 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12380 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12382 /* Shift amount for subword relative to aligned word. */
12383 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12384 shift = gen_reg_rtx (SImode);
12385 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12386 GEN_INT (shift_mask)));
12387 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12389 /* Shift and mask old value into position within word. */
12390 oldval = convert_modes (SImode, mode, oldval, 1);
12391 oldval = expand_binop (SImode, and_optab,
12392 oldval, GEN_INT (imask), NULL_RTX,
12393 1, OPTAB_LIB_WIDEN);
12394 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12396 /* Shift and mask new value into position within word. */
12397 newval = convert_modes (SImode, mode, newval, 1);
12398 newval = expand_binop (SImode, and_optab,
12399 newval, GEN_INT (imask), NULL_RTX,
12400 1, OPTAB_LIB_WIDEN);
12401 emit_insn (gen_ashlsi3 (newval, newval, shift));
12403 /* Mask for insertion. */
12404 mask = gen_reg_rtx (SImode);
12405 emit_move_insn (mask, GEN_INT (imask));
12406 emit_insn (gen_ashlsi3 (mask, mask, shift));
12408 /* Address of aligned word containing subword. */
12409 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12410 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12411 mem = change_address (mem, SImode, align);
12412 set_mem_align (mem, 32);
12413 MEM_VOLATILE_P (mem) = 1;
12415 wdst = gen_reg_rtx (SImode);
12416 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12417 oldval, newval, mem));
12419 emit_move_insn (dst, gen_lowpart (mode, wdst));
12423 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12424 rtx oldval, rtx newval, rtx mem,
12427 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12429 emit_insn (gen_memory_barrier ());
12430 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12431 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12432 emit_label (XEXP (label1, 0));
12434 emit_load_locked (SImode, scratch, mem);
12436 /* Mask subword within loaded value for comparison with oldval.
12437 Use UNSPEC_AND to avoid clobber.*/
12438 emit_insn (gen_rtx_SET (SImode, dest,
12439 gen_rtx_UNSPEC (SImode,
12440 gen_rtvec (2, scratch, mask),
12443 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12444 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12446 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12447 emit_unlikely_jump (x, label2);
12449 /* Clear subword within loaded value for insertion of new value. */
12450 emit_insn (gen_rtx_SET (SImode, scratch,
12451 gen_rtx_AND (SImode,
12452 gen_rtx_NOT (SImode, mask), scratch)));
12453 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12454 emit_store_conditional (SImode, cond, mem, scratch);
12456 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12457 emit_unlikely_jump (x, label1);
12459 emit_insn (gen_isync ());
12460 emit_label (XEXP (label2, 0));
12464 /* Emit instructions to move SRC to DST. Called by splitters for
12465 multi-register moves. It will emit at most one instruction for
12466 each register that is accessed; that is, it won't emit li/lis pairs
12467 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12471 rs6000_split_multireg_move (rtx dst, rtx src)
12473 /* The register number of the first register being moved. */
12475 /* The mode that is to be moved. */
12476 enum machine_mode mode;
12477 /* The mode that the move is being done in, and its size. */
12478 enum machine_mode reg_mode;
12480 /* The number of registers that will be moved. */
12483 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12484 mode = GET_MODE (dst);
12485 nregs = hard_regno_nregs[reg][mode];
12486 if (FP_REGNO_P (reg))
12488 else if (ALTIVEC_REGNO_P (reg))
12489 reg_mode = V16QImode;
12491 reg_mode = word_mode;
12492 reg_mode_size = GET_MODE_SIZE (reg_mode);
12494 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12496 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12498 /* Move register range backwards, if we might have destructive
12501 for (i = nregs - 1; i >= 0; i--)
12502 emit_insn (gen_rtx_SET (VOIDmode,
12503 simplify_gen_subreg (reg_mode, dst, mode,
12504 i * reg_mode_size),
12505 simplify_gen_subreg (reg_mode, src, mode,
12506 i * reg_mode_size)));
12512 bool used_update = false;
12514 if (MEM_P (src) && INT_REGNO_P (reg))
12518 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12519 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12522 breg = XEXP (XEXP (src, 0), 0);
12523 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12524 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12525 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12526 emit_insn (TARGET_32BIT
12527 ? gen_addsi3 (breg, breg, delta_rtx)
12528 : gen_adddi3 (breg, breg, delta_rtx));
12529 src = replace_equiv_address (src, breg);
12531 else if (! rs6000_offsettable_memref_p (src))
12534 basereg = gen_rtx_REG (Pmode, reg);
12535 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12536 src = replace_equiv_address (src, basereg);
12539 breg = XEXP (src, 0);
12540 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12541 breg = XEXP (breg, 0);
12543 /* If the base register we are using to address memory is
12544 also a destination reg, then change that register last. */
12546 && REGNO (breg) >= REGNO (dst)
12547 && REGNO (breg) < REGNO (dst) + nregs)
12548 j = REGNO (breg) - REGNO (dst);
12551 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12555 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12556 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12559 breg = XEXP (XEXP (dst, 0), 0);
12560 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12561 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12562 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12564 /* We have to update the breg before doing the store.
12565 Use store with update, if available. */
12569 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12570 emit_insn (TARGET_32BIT
12571 ? (TARGET_POWERPC64
12572 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12573 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12574 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12575 used_update = true;
12578 emit_insn (TARGET_32BIT
12579 ? gen_addsi3 (breg, breg, delta_rtx)
12580 : gen_adddi3 (breg, breg, delta_rtx));
12581 dst = replace_equiv_address (dst, breg);
12584 gcc_assert (rs6000_offsettable_memref_p (dst));
12587 for (i = 0; i < nregs; i++)
12589 /* Calculate index to next subword. */
12594 /* If compiler already emitted move of first word by
12595 store with update, no need to do anything. */
12596 if (j == 0 && used_update)
12599 emit_insn (gen_rtx_SET (VOIDmode,
12600 simplify_gen_subreg (reg_mode, dst, mode,
12601 j * reg_mode_size),
12602 simplify_gen_subreg (reg_mode, src, mode,
12603 j * reg_mode_size)));
12609 /* This page contains routines that are used to determine what the
12610 function prologue and epilogue code will do and write them out. */
12612 /* Return the first fixed-point register that is required to be
12613 saved. 32 if none. */
12616 first_reg_to_save (void)
12620 /* Find lowest numbered live register. */
12621 for (first_reg = 13; first_reg <= 31; first_reg++)
12622 if (regs_ever_live[first_reg]
12623 && (! call_used_regs[first_reg]
12624 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12625 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12626 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12627 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12632 && current_function_uses_pic_offset_table
12633 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12634 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12640 /* Similar, for FP regs. */
12643 first_fp_reg_to_save (void)
12647 /* Find lowest numbered live register. */
12648 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12649 if (regs_ever_live[first_reg])
12655 /* Similar, for AltiVec regs. */
12658 first_altivec_reg_to_save (void)
12662 /* Stack frame remains as is unless we are in AltiVec ABI. */
12663 if (! TARGET_ALTIVEC_ABI)
12664 return LAST_ALTIVEC_REGNO + 1;
12666 /* Find lowest numbered live register. */
12667 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12668 if (regs_ever_live[i])
12674 /* Return a 32-bit mask of the AltiVec registers we need to set in
12675 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12676 the 32-bit word is 0. */
12678 static unsigned int
12679 compute_vrsave_mask (void)
12681 unsigned int i, mask = 0;
12683 /* First, find out if we use _any_ altivec registers. */
12684 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12685 if (regs_ever_live[i])
12686 mask |= ALTIVEC_REG_BIT (i);
12691 /* Next, remove the argument registers from the set. These must
12692 be in the VRSAVE mask set by the caller, so we don't need to add
12693 them in again. More importantly, the mask we compute here is
12694 used to generate CLOBBERs in the set_vrsave insn, and we do not
12695 wish the argument registers to die. */
12696 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12697 mask &= ~ALTIVEC_REG_BIT (i);
12699 /* Similarly, remove the return value from the set. */
12702 diddle_return_value (is_altivec_return_reg, &yes);
12704 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12710 /* For a very restricted set of circumstances, we can cut down the
12711 size of prologues/epilogues by calling our own save/restore-the-world
12715 compute_save_world_info (rs6000_stack_t *info_ptr)
12717 info_ptr->world_save_p = 1;
12718 info_ptr->world_save_p
12719 = (WORLD_SAVE_P (info_ptr)
12720 && DEFAULT_ABI == ABI_DARWIN
12721 && ! (current_function_calls_setjmp && flag_exceptions)
12722 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12723 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12724 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12725 && info_ptr->cr_save_p);
12727 /* This will not work in conjunction with sibcalls. Make sure there
12728 are none. (This check is expensive, but seldom executed.) */
12729 if (WORLD_SAVE_P (info_ptr))
12732 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12733 if ( GET_CODE (insn) == CALL_INSN
12734 && SIBLING_CALL_P (insn))
12736 info_ptr->world_save_p = 0;
12741 if (WORLD_SAVE_P (info_ptr))
12743 /* Even if we're not touching VRsave, make sure there's room on the
12744 stack for it, if it looks like we're calling SAVE_WORLD, which
12745 will attempt to save it. */
12746 info_ptr->vrsave_size = 4;
12748 /* "Save" the VRsave register too if we're saving the world. */
12749 if (info_ptr->vrsave_mask == 0)
12750 info_ptr->vrsave_mask = compute_vrsave_mask ();
12752 /* Because the Darwin register save/restore routines only handle
12753 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12755 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12756 && (info_ptr->first_altivec_reg_save
12757 >= FIRST_SAVED_ALTIVEC_REGNO));
12764 is_altivec_return_reg (rtx reg, void *xyes)
12766 bool *yes = (bool *) xyes;
12767 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12772 /* Calculate the stack information for the current function. This is
12773 complicated by having two separate calling sequences, the AIX calling
12774 sequence and the V.4 calling sequence.
12776 AIX (and Darwin/Mac OS X) stack frames look like:
12778 SP----> +---------------------------------------+
12779 | back chain to caller | 0 0
12780 +---------------------------------------+
12781 | saved CR | 4 8 (8-11)
12782 +---------------------------------------+
12784 +---------------------------------------+
12785 | reserved for compilers | 12 24
12786 +---------------------------------------+
12787 | reserved for binders | 16 32
12788 +---------------------------------------+
12789 | saved TOC pointer | 20 40
12790 +---------------------------------------+
12791 | Parameter save area (P) | 24 48
12792 +---------------------------------------+
12793 | Alloca space (A) | 24+P etc.
12794 +---------------------------------------+
12795 | Local variable space (L) | 24+P+A
12796 +---------------------------------------+
12797 | Float/int conversion temporary (X) | 24+P+A+L
12798 +---------------------------------------+
12799 | Save area for AltiVec registers (W) | 24+P+A+L+X
12800 +---------------------------------------+
12801 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12802 +---------------------------------------+
12803 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12804 +---------------------------------------+
12805 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12806 +---------------------------------------+
12807 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12808 +---------------------------------------+
12809 old SP->| back chain to caller's caller |
12810 +---------------------------------------+
12812 The required alignment for AIX configurations is two words (i.e., 8
12816 V.4 stack frames look like:
12818 SP----> +---------------------------------------+
12819 | back chain to caller | 0
12820 +---------------------------------------+
12821 | caller's saved LR | 4
12822 +---------------------------------------+
12823 | Parameter save area (P) | 8
12824 +---------------------------------------+
12825 | Alloca space (A) | 8+P
12826 +---------------------------------------+
12827 | Varargs save area (V) | 8+P+A
12828 +---------------------------------------+
12829 | Local variable space (L) | 8+P+A+V
12830 +---------------------------------------+
12831 | Float/int conversion temporary (X) | 8+P+A+V+L
12832 +---------------------------------------+
12833 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12834 +---------------------------------------+
12835 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12836 +---------------------------------------+
12837 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12838 +---------------------------------------+
12839 | SPE: area for 64-bit GP registers |
12840 +---------------------------------------+
12841 | SPE alignment padding |
12842 +---------------------------------------+
12843 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12844 +---------------------------------------+
12845 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12846 +---------------------------------------+
12847 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12848 +---------------------------------------+
12849 old SP->| back chain to caller's caller |
12850 +---------------------------------------+
12852 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12853 given. (But note below and in sysv4.h that we require only 8 and
12854 may round up the size of our stack frame anyways. The historical
12855 reason is early versions of powerpc-linux which didn't properly
12856 align the stack at program startup. A happy side-effect is that
12857 -mno-eabi libraries can be used with -meabi programs.)
12859 The EABI configuration defaults to the V.4 layout. However,
12860 the stack alignment requirements may differ. If -mno-eabi is not
12861 given, the required stack alignment is 8 bytes; if -mno-eabi is
12862 given, the required alignment is 16 bytes. (But see V.4 comment
12865 #ifndef ABI_STACK_BOUNDARY
12866 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12869 static rs6000_stack_t *
12870 rs6000_stack_info (void)
12872 static rs6000_stack_t info;
12873 rs6000_stack_t *info_ptr = &info;
12874 int reg_size = TARGET_32BIT ? 4 : 8;
12877 HOST_WIDE_INT non_fixed_size;
12879 memset (&info, 0, sizeof (info));
12883 /* Cache value so we don't rescan instruction chain over and over. */
12884 if (cfun->machine->insn_chain_scanned_p == 0)
12885 cfun->machine->insn_chain_scanned_p
12886 = spe_func_has_64bit_regs_p () + 1;
12887 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12890 /* Select which calling sequence. */
12891 info_ptr->abi = DEFAULT_ABI;
12893 /* Calculate which registers need to be saved & save area size. */
12894 info_ptr->first_gp_reg_save = first_reg_to_save ();
12895 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12896 even if it currently looks like we won't. */
12897 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12898 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12899 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12900 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12901 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12903 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12905 /* For the SPE, we have an additional upper 32-bits on each GPR.
12906 Ideally we should save the entire 64-bits only when the upper
12907 half is used in SIMD instructions. Since we only record
12908 registers live (not the size they are used in), this proves
12909 difficult because we'd have to traverse the instruction chain at
12910 the right time, taking reload into account. This is a real pain,
12911 so we opt to save the GPRs in 64-bits always if but one register
12912 gets used in 64-bits. Otherwise, all the registers in the frame
12913 get saved in 32-bits.
12915 So... since when we save all GPRs (except the SP) in 64-bits, the
12916 traditional GP save area will be empty. */
12917 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12918 info_ptr->gp_size = 0;
12920 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12921 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12923 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12924 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12925 - info_ptr->first_altivec_reg_save);
12927 /* Does this function call anything? */
12928 info_ptr->calls_p = (! current_function_is_leaf
12929 || cfun->machine->ra_needs_full_frame);
12931 /* Determine if we need to save the link register. */
12932 if ((DEFAULT_ABI == ABI_AIX
12933 && current_function_profile
12934 && !TARGET_PROFILE_KERNEL)
12935 #ifdef TARGET_RELOCATABLE
12936 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12938 || (info_ptr->first_fp_reg_save != 64
12939 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12940 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12941 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12942 || info_ptr->calls_p
12943 || rs6000_ra_ever_killed ())
12945 info_ptr->lr_save_p = 1;
12946 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12949 /* Determine if we need to save the condition code registers. */
12950 if (regs_ever_live[CR2_REGNO]
12951 || regs_ever_live[CR3_REGNO]
12952 || regs_ever_live[CR4_REGNO])
12954 info_ptr->cr_save_p = 1;
12955 if (DEFAULT_ABI == ABI_V4)
12956 info_ptr->cr_size = reg_size;
12959 /* If the current function calls __builtin_eh_return, then we need
12960 to allocate stack space for registers that will hold data for
12961 the exception handler. */
12962 if (current_function_calls_eh_return)
12965 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12968 /* SPE saves EH registers in 64-bits. */
12969 ehrd_size = i * (TARGET_SPE_ABI
12970 && info_ptr->spe_64bit_regs_used != 0
12971 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12976 /* Determine various sizes. */
12977 info_ptr->reg_size = reg_size;
12978 info_ptr->fixed_size = RS6000_SAVE_AREA;
12979 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12980 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12981 TARGET_ALTIVEC ? 16 : 8);
12982 if (FRAME_GROWS_DOWNWARD)
12983 info_ptr->vars_size
12984 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12985 + info_ptr->parm_size,
12986 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12987 - (info_ptr->fixed_size + info_ptr->vars_size
12988 + info_ptr->parm_size);
12990 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12991 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12993 info_ptr->spe_gp_size = 0;
12995 if (TARGET_ALTIVEC_ABI)
12996 info_ptr->vrsave_mask = compute_vrsave_mask ();
12998 info_ptr->vrsave_mask = 0;
13000 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13001 info_ptr->vrsave_size = 4;
13003 info_ptr->vrsave_size = 0;
13005 compute_save_world_info (info_ptr);
13007 /* Calculate the offsets. */
13008 switch (DEFAULT_ABI)
13012 gcc_unreachable ();
13016 info_ptr->fp_save_offset = - info_ptr->fp_size;
13017 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13019 if (TARGET_ALTIVEC_ABI)
13021 info_ptr->vrsave_save_offset
13022 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13024 /* Align stack so vector save area is on a quadword boundary. */
13025 if (info_ptr->altivec_size != 0)
13026 info_ptr->altivec_padding_size
13027 = 16 - (-info_ptr->vrsave_save_offset % 16);
13029 info_ptr->altivec_padding_size = 0;
13031 info_ptr->altivec_save_offset
13032 = info_ptr->vrsave_save_offset
13033 - info_ptr->altivec_padding_size
13034 - info_ptr->altivec_size;
13036 /* Adjust for AltiVec case. */
13037 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13040 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13041 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13042 info_ptr->lr_save_offset = 2*reg_size;
13046 info_ptr->fp_save_offset = - info_ptr->fp_size;
13047 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13048 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13050 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13052 /* Align stack so SPE GPR save area is aligned on a
13053 double-word boundary. */
13054 if (info_ptr->spe_gp_size != 0)
13055 info_ptr->spe_padding_size
13056 = 8 - (-info_ptr->cr_save_offset % 8);
13058 info_ptr->spe_padding_size = 0;
13060 info_ptr->spe_gp_save_offset
13061 = info_ptr->cr_save_offset
13062 - info_ptr->spe_padding_size
13063 - info_ptr->spe_gp_size;
13065 /* Adjust for SPE case. */
13066 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13068 else if (TARGET_ALTIVEC_ABI)
13070 info_ptr->vrsave_save_offset
13071 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13073 /* Align stack so vector save area is on a quadword boundary. */
13074 if (info_ptr->altivec_size != 0)
13075 info_ptr->altivec_padding_size
13076 = 16 - (-info_ptr->vrsave_save_offset % 16);
13078 info_ptr->altivec_padding_size = 0;
13080 info_ptr->altivec_save_offset
13081 = info_ptr->vrsave_save_offset
13082 - info_ptr->altivec_padding_size
13083 - info_ptr->altivec_size;
13085 /* Adjust for AltiVec case. */
13086 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13089 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13090 info_ptr->ehrd_offset -= ehrd_size;
13091 info_ptr->lr_save_offset = reg_size;
13095 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13096 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13097 + info_ptr->gp_size
13098 + info_ptr->altivec_size
13099 + info_ptr->altivec_padding_size
13100 + info_ptr->spe_gp_size
13101 + info_ptr->spe_padding_size
13103 + info_ptr->cr_size
13104 + info_ptr->vrsave_size,
13107 non_fixed_size = (info_ptr->vars_size
13108 + info_ptr->parm_size
13109 + info_ptr->save_size);
13111 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13112 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13114 /* Determine if we need to allocate any stack frame:
13116 For AIX we need to push the stack if a frame pointer is needed
13117 (because the stack might be dynamically adjusted), if we are
13118 debugging, if we make calls, or if the sum of fp_save, gp_save,
13119 and local variables are more than the space needed to save all
13120 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13121 + 18*8 = 288 (GPR13 reserved).
13123 For V.4 we don't have the stack cushion that AIX uses, but assume
13124 that the debugger can handle stackless frames. */
13126 if (info_ptr->calls_p)
13127 info_ptr->push_p = 1;
13129 else if (DEFAULT_ABI == ABI_V4)
13130 info_ptr->push_p = non_fixed_size != 0;
13132 else if (frame_pointer_needed)
13133 info_ptr->push_p = 1;
13135 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13136 info_ptr->push_p = 1;
13139 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13141 /* Zero offsets if we're not saving those registers. */
13142 if (info_ptr->fp_size == 0)
13143 info_ptr->fp_save_offset = 0;
13145 if (info_ptr->gp_size == 0)
13146 info_ptr->gp_save_offset = 0;
13148 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13149 info_ptr->altivec_save_offset = 0;
13151 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13152 info_ptr->vrsave_save_offset = 0;
13154 if (! TARGET_SPE_ABI
13155 || info_ptr->spe_64bit_regs_used == 0
13156 || info_ptr->spe_gp_size == 0)
13157 info_ptr->spe_gp_save_offset = 0;
13159 if (! info_ptr->lr_save_p)
13160 info_ptr->lr_save_offset = 0;
13162 if (! info_ptr->cr_save_p)
13163 info_ptr->cr_save_offset = 0;
13168 /* Return true if the current function uses any GPRs in 64-bit SIMD
13172 spe_func_has_64bit_regs_p (void)
13176 /* Functions that save and restore all the call-saved registers will
13177 need to save/restore the registers in 64-bits. */
13178 if (current_function_calls_eh_return
13179 || current_function_calls_setjmp
13180 || current_function_has_nonlocal_goto)
13183 insns = get_insns ();
13185 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13191 /* FIXME: This should be implemented with attributes...
13193 (set_attr "spe64" "true")....then,
13194 if (get_spe64(insn)) return true;
13196 It's the only reliable way to do the stuff below. */
13198 i = PATTERN (insn);
13199 if (GET_CODE (i) == SET)
13201 enum machine_mode mode = GET_MODE (SET_SRC (i));
13203 if (SPE_VECTOR_MODE (mode))
13205 if (TARGET_E500_DOUBLE && mode == DFmode)
13215 debug_stack_info (rs6000_stack_t *info)
13217 const char *abi_string;
13220 info = rs6000_stack_info ();
13222 fprintf (stderr, "\nStack information for function %s:\n",
13223 ((current_function_decl && DECL_NAME (current_function_decl))
13224 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13229 default: abi_string = "Unknown"; break;
13230 case ABI_NONE: abi_string = "NONE"; break;
13231 case ABI_AIX: abi_string = "AIX"; break;
13232 case ABI_DARWIN: abi_string = "Darwin"; break;
13233 case ABI_V4: abi_string = "V.4"; break;
13236 fprintf (stderr, "\tABI = %5s\n", abi_string);
13238 if (TARGET_ALTIVEC_ABI)
13239 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13241 if (TARGET_SPE_ABI)
13242 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13244 if (info->first_gp_reg_save != 32)
13245 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13247 if (info->first_fp_reg_save != 64)
13248 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13250 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13251 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13252 info->first_altivec_reg_save);
13254 if (info->lr_save_p)
13255 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13257 if (info->cr_save_p)
13258 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13260 if (info->vrsave_mask)
13261 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13264 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13267 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13269 if (info->gp_save_offset)
13270 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13272 if (info->fp_save_offset)
13273 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13275 if (info->altivec_save_offset)
13276 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13277 info->altivec_save_offset);
13279 if (info->spe_gp_save_offset)
13280 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13281 info->spe_gp_save_offset);
13283 if (info->vrsave_save_offset)
13284 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13285 info->vrsave_save_offset);
13287 if (info->lr_save_offset)
13288 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13290 if (info->cr_save_offset)
13291 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13293 if (info->varargs_save_offset)
13294 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13296 if (info->total_size)
13297 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13300 if (info->vars_size)
13301 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13304 if (info->parm_size)
13305 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13307 if (info->fixed_size)
13308 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13311 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13313 if (info->spe_gp_size)
13314 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13317 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13319 if (info->altivec_size)
13320 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13322 if (info->vrsave_size)
13323 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13325 if (info->altivec_padding_size)
13326 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13327 info->altivec_padding_size);
13329 if (info->spe_padding_size)
13330 fprintf (stderr, "\tspe_padding_size = %5d\n",
13331 info->spe_padding_size);
13334 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13336 if (info->save_size)
13337 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13339 if (info->reg_size != 4)
13340 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13342 fprintf (stderr, "\n");
13346 rs6000_return_addr (int count, rtx frame)
13348 /* Currently we don't optimize very well between prolog and body
13349 code and for PIC code the code can be actually quite bad, so
13350 don't try to be too clever here. */
13351 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13353 cfun->machine->ra_needs_full_frame = 1;
13360 plus_constant (copy_to_reg
13361 (gen_rtx_MEM (Pmode,
13362 memory_address (Pmode, frame))),
13363 RETURN_ADDRESS_OFFSET)));
13366 cfun->machine->ra_need_lr = 1;
13367 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13370 /* Say whether a function is a candidate for sibcall handling or not.
13371 We do not allow indirect calls to be optimized into sibling calls.
13372 Also, we can't do it if there are any vector parameters; there's
13373 nowhere to put the VRsave code so it works; note that functions with
13374 vector parameters are required to have a prototype, so the argument
13375 type info must be available here. (The tail recursion case can work
13376 with vector parameters, but there's no way to distinguish here.) */
13378 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13383 if (TARGET_ALTIVEC_VRSAVE)
13385 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13386 type; type = TREE_CHAIN (type))
13388 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13392 if (DEFAULT_ABI == ABI_DARWIN
13393 || (*targetm.binds_local_p) (decl))
13395 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13397 if (!lookup_attribute ("longcall", attr_list)
13398 || lookup_attribute ("shortcall", attr_list))
13405 /* NULL if INSN insn is valid within a low-overhead loop.
13406 Otherwise return why doloop cannot be applied.
13407 PowerPC uses the COUNT register for branch on table instructions. */
13409 static const char *
13410 rs6000_invalid_within_doloop (rtx insn)
13413 return "Function call in the loop.";
13416 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13417 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13418 return "Computed branch in the loop.";
13424 rs6000_ra_ever_killed (void)
13430 if (current_function_is_thunk)
13433 /* regs_ever_live has LR marked as used if any sibcalls are present,
13434 but this should not force saving and restoring in the
13435 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13436 clobbers LR, so that is inappropriate. */
13438 /* Also, the prologue can generate a store into LR that
13439 doesn't really count, like this:
13442 bcl to set PIC register
13446 When we're called from the epilogue, we need to avoid counting
13447 this as a store. */
13449 push_topmost_sequence ();
13450 top = get_insns ();
13451 pop_topmost_sequence ();
13452 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13454 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13460 if (!SIBLING_CALL_P (insn))
13463 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13465 else if (set_of (reg, insn) != NULL_RTX
13466 && !prologue_epilogue_contains (insn))
13473 /* Add a REG_MAYBE_DEAD note to the insn. */
13475 rs6000_maybe_dead (rtx insn)
13477 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13482 /* Emit instructions needed to load the TOC register.
13483 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13484 a constant pool; or for SVR4 -fpic. */
13487 rs6000_emit_load_toc_table (int fromprolog)
13490 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13492 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13495 rtx lab, tmp1, tmp2, got, tempLR;
13497 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13498 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13500 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13502 got = rs6000_got_sym ();
13503 tmp1 = tmp2 = dest;
13506 tmp1 = gen_reg_rtx (Pmode);
13507 tmp2 = gen_reg_rtx (Pmode);
13509 tempLR = (fromprolog
13510 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13511 : gen_reg_rtx (Pmode));
13512 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13514 rs6000_maybe_dead (insn);
13515 insn = emit_move_insn (tmp1, tempLR);
13517 rs6000_maybe_dead (insn);
13518 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13520 rs6000_maybe_dead (insn);
13521 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13523 rs6000_maybe_dead (insn);
13525 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13527 rtx tempLR = (fromprolog
13528 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13529 : gen_reg_rtx (Pmode));
13531 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13533 rs6000_maybe_dead (insn);
13534 insn = emit_move_insn (dest, tempLR);
13536 rs6000_maybe_dead (insn);
13538 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13541 rtx tempLR = (fromprolog
13542 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13543 : gen_reg_rtx (Pmode));
13544 rtx temp0 = (fromprolog
13545 ? gen_rtx_REG (Pmode, 0)
13546 : gen_reg_rtx (Pmode));
13552 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13553 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13555 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13556 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13558 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13560 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13561 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13569 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13570 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13571 emit_move_insn (dest, tempLR);
13572 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13574 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13576 rs6000_maybe_dead (insn);
13578 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13580 /* This is for AIX code running in non-PIC ELF32. */
13583 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13584 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13586 insn = emit_insn (gen_elf_high (dest, realsym));
13588 rs6000_maybe_dead (insn);
13589 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13591 rs6000_maybe_dead (insn);
13595 gcc_assert (DEFAULT_ABI == ABI_AIX);
13598 insn = emit_insn (gen_load_toc_aix_si (dest));
13600 insn = emit_insn (gen_load_toc_aix_di (dest));
13602 rs6000_maybe_dead (insn);
13606 /* Emit instructions to restore the link register after determining where
13607 its value has been stored. */
13610 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13612 rs6000_stack_t *info = rs6000_stack_info ();
13615 operands[0] = source;
13616 operands[1] = scratch;
13618 if (info->lr_save_p)
13620 rtx frame_rtx = stack_pointer_rtx;
13621 HOST_WIDE_INT sp_offset = 0;
13624 if (frame_pointer_needed
13625 || current_function_calls_alloca
13626 || info->total_size > 32767)
13628 tmp = gen_frame_mem (Pmode, frame_rtx);
13629 emit_move_insn (operands[1], tmp);
13630 frame_rtx = operands[1];
13632 else if (info->push_p)
13633 sp_offset = info->total_size;
13635 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13636 tmp = gen_frame_mem (Pmode, tmp);
13637 emit_move_insn (tmp, operands[0]);
13640 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13643 static GTY(()) int set = -1;
13646 get_TOC_alias_set (void)
13649 set = new_alias_set ();
13653 /* This returns nonzero if the current function uses the TOC. This is
13654 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13655 is generated by the ABI_V4 load_toc_* patterns. */
13662 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13665 rtx pat = PATTERN (insn);
13668 if (GET_CODE (pat) == PARALLEL)
13669 for (i = 0; i < XVECLEN (pat, 0); i++)
13671 rtx sub = XVECEXP (pat, 0, i);
13672 if (GET_CODE (sub) == USE)
13674 sub = XEXP (sub, 0);
13675 if (GET_CODE (sub) == UNSPEC
13676 && XINT (sub, 1) == UNSPEC_TOC)
13686 create_TOC_reference (rtx symbol)
13688 if (no_new_pseudos)
13689 regs_ever_live[TOC_REGISTER] = 1;
13690 return gen_rtx_PLUS (Pmode,
13691 gen_rtx_REG (Pmode, TOC_REGISTER),
13692 gen_rtx_CONST (Pmode,
13693 gen_rtx_MINUS (Pmode, symbol,
13694 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13697 /* If _Unwind_* has been called from within the same module,
13698 toc register is not guaranteed to be saved to 40(1) on function
13699 entry. Save it there in that case. */
13702 rs6000_aix_emit_builtin_unwind_init (void)
13705 rtx stack_top = gen_reg_rtx (Pmode);
13706 rtx opcode_addr = gen_reg_rtx (Pmode);
13707 rtx opcode = gen_reg_rtx (SImode);
13708 rtx tocompare = gen_reg_rtx (SImode);
13709 rtx no_toc_save_needed = gen_label_rtx ();
13711 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13712 emit_move_insn (stack_top, mem);
13714 mem = gen_frame_mem (Pmode,
13715 gen_rtx_PLUS (Pmode, stack_top,
13716 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13717 emit_move_insn (opcode_addr, mem);
13718 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13719 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13720 : 0xE8410028, SImode));
13722 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13723 SImode, NULL_RTX, NULL_RTX,
13724 no_toc_save_needed);
13726 mem = gen_frame_mem (Pmode,
13727 gen_rtx_PLUS (Pmode, stack_top,
13728 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13729 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13730 emit_label (no_toc_save_needed);
13733 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13734 and the change to the stack pointer. */
13737 rs6000_emit_stack_tie (void)
13739 rtx mem = gen_frame_mem (BLKmode,
13740 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13742 emit_insn (gen_stack_tie (mem));
13745 /* Emit the correct code for allocating stack space, as insns.
13746 If COPY_R12, make sure a copy of the old frame is left in r12.
13747 The generated code may use hard register 0 as a temporary. */
13750 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13753 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13754 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13755 rtx todec = gen_int_mode (-size, Pmode);
13757 if (INTVAL (todec) != -size)
13759 warning (0, "stack frame too large");
13760 emit_insn (gen_trap ());
13764 if (current_function_limit_stack)
13766 if (REG_P (stack_limit_rtx)
13767 && REGNO (stack_limit_rtx) > 1
13768 && REGNO (stack_limit_rtx) <= 31)
13770 emit_insn (TARGET_32BIT
13771 ? gen_addsi3 (tmp_reg,
13774 : gen_adddi3 (tmp_reg,
13778 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13781 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13783 && DEFAULT_ABI == ABI_V4)
13785 rtx toload = gen_rtx_CONST (VOIDmode,
13786 gen_rtx_PLUS (Pmode,
13790 emit_insn (gen_elf_high (tmp_reg, toload));
13791 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13792 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13796 warning (0, "stack limit expression is not supported");
13799 if (copy_r12 || ! TARGET_UPDATE)
13800 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13806 /* Need a note here so that try_split doesn't get confused. */
13807 if (get_last_insn () == NULL_RTX)
13808 emit_note (NOTE_INSN_DELETED);
13809 insn = emit_move_insn (tmp_reg, todec);
13810 try_split (PATTERN (insn), insn, 0);
13814 insn = emit_insn (TARGET_32BIT
13815 ? gen_movsi_update (stack_reg, stack_reg,
13817 : gen_movdi_di_update (stack_reg, stack_reg,
13818 todec, stack_reg));
13822 insn = emit_insn (TARGET_32BIT
13823 ? gen_addsi3 (stack_reg, stack_reg, todec)
13824 : gen_adddi3 (stack_reg, stack_reg, todec));
13825 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13826 gen_rtx_REG (Pmode, 12));
13829 RTX_FRAME_RELATED_P (insn) = 1;
13831 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13832 gen_rtx_SET (VOIDmode, stack_reg,
13833 gen_rtx_PLUS (Pmode, stack_reg,
13838 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13839 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13840 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13841 deduce these equivalences by itself so it wasn't necessary to hold
13842 its hand so much. */
13845 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13846 rtx reg2, rtx rreg)
13850 /* copy_rtx will not make unique copies of registers, so we need to
13851 ensure we don't have unwanted sharing here. */
13853 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13856 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13858 real = copy_rtx (PATTERN (insn));
13860 if (reg2 != NULL_RTX)
13861 real = replace_rtx (real, reg2, rreg);
13863 real = replace_rtx (real, reg,
13864 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13865 STACK_POINTER_REGNUM),
13868 /* We expect that 'real' is either a SET or a PARALLEL containing
13869 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13870 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13872 if (GET_CODE (real) == SET)
13876 temp = simplify_rtx (SET_SRC (set));
13878 SET_SRC (set) = temp;
13879 temp = simplify_rtx (SET_DEST (set));
13881 SET_DEST (set) = temp;
13882 if (GET_CODE (SET_DEST (set)) == MEM)
13884 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13886 XEXP (SET_DEST (set), 0) = temp;
13893 gcc_assert (GET_CODE (real) == PARALLEL);
13894 for (i = 0; i < XVECLEN (real, 0); i++)
13895 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13897 rtx set = XVECEXP (real, 0, i);
13899 temp = simplify_rtx (SET_SRC (set));
13901 SET_SRC (set) = temp;
13902 temp = simplify_rtx (SET_DEST (set));
13904 SET_DEST (set) = temp;
13905 if (GET_CODE (SET_DEST (set)) == MEM)
13907 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13909 XEXP (SET_DEST (set), 0) = temp;
13911 RTX_FRAME_RELATED_P (set) = 1;
13916 real = spe_synthesize_frame_save (real);
13918 RTX_FRAME_RELATED_P (insn) = 1;
13919 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13924 /* Given an SPE frame note, return a PARALLEL of SETs with the
13925 original note, plus a synthetic register save. */
13928 spe_synthesize_frame_save (rtx real)
13930 rtx synth, offset, reg, real2;
13932 if (GET_CODE (real) != SET
13933 || GET_MODE (SET_SRC (real)) != V2SImode)
13936 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13937 frame related note. The parallel contains a set of the register
13938 being saved, and another set to a synthetic register (n+1200).
13939 This is so we can differentiate between 64-bit and 32-bit saves.
13940 Words cannot describe this nastiness. */
13942 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13943 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13944 && GET_CODE (SET_SRC (real)) == REG);
13947 (set (mem (plus (reg x) (const y)))
13950 (set (mem (plus (reg x) (const y+4)))
13954 real2 = copy_rtx (real);
13955 PUT_MODE (SET_DEST (real2), SImode);
13956 reg = SET_SRC (real2);
13957 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13958 synth = copy_rtx (real2);
13960 if (BYTES_BIG_ENDIAN)
13962 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13963 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13966 reg = SET_SRC (synth);
13968 synth = replace_rtx (synth, reg,
13969 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13971 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13972 synth = replace_rtx (synth, offset,
13973 GEN_INT (INTVAL (offset)
13974 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13976 RTX_FRAME_RELATED_P (synth) = 1;
13977 RTX_FRAME_RELATED_P (real2) = 1;
13978 if (BYTES_BIG_ENDIAN)
13979 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13981 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13986 /* Returns an insn that has a vrsave set operation with the
13987 appropriate CLOBBERs. */
13990 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13993 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13994 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13997 = gen_rtx_SET (VOIDmode,
13999 gen_rtx_UNSPEC_VOLATILE (SImode,
14000 gen_rtvec (2, reg, vrsave),
14001 UNSPECV_SET_VRSAVE));
14005 /* We need to clobber the registers in the mask so the scheduler
14006 does not move sets to VRSAVE before sets of AltiVec registers.
14008 However, if the function receives nonlocal gotos, reload will set
14009 all call saved registers live. We will end up with:
14011 (set (reg 999) (mem))
14012 (parallel [ (set (reg vrsave) (unspec blah))
14013 (clobber (reg 999))])
14015 The clobber will cause the store into reg 999 to be dead, and
14016 flow will attempt to delete an epilogue insn. In this case, we
14017 need an unspec use/set of the register. */
14019 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14020 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14022 if (!epiloguep || call_used_regs [i])
14023 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14024 gen_rtx_REG (V4SImode, i));
14027 rtx reg = gen_rtx_REG (V4SImode, i);
14030 = gen_rtx_SET (VOIDmode,
14032 gen_rtx_UNSPEC (V4SImode,
14033 gen_rtvec (1, reg), 27));
14037 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14039 for (i = 0; i < nclobs; ++i)
14040 XVECEXP (insn, 0, i) = clobs[i];
14045 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14046 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14049 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14050 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14052 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14053 rtx replacea, replaceb;
14055 int_rtx = GEN_INT (offset);
14057 /* Some cases that need register indexed addressing. */
14058 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14059 || (TARGET_E500_DOUBLE && mode == DFmode)
14061 && SPE_VECTOR_MODE (mode)
14062 && !SPE_CONST_OFFSET_OK (offset)))
14064 /* Whomever calls us must make sure r11 is available in the
14065 flow path of instructions in the prologue. */
14066 offset_rtx = gen_rtx_REG (Pmode, 11);
14067 emit_move_insn (offset_rtx, int_rtx);
14069 replacea = offset_rtx;
14070 replaceb = int_rtx;
14074 offset_rtx = int_rtx;
14075 replacea = NULL_RTX;
14076 replaceb = NULL_RTX;
14079 reg = gen_rtx_REG (mode, regno);
14080 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14081 mem = gen_frame_mem (mode, addr);
14083 insn = emit_move_insn (mem, reg);
14085 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14088 /* Emit an offset memory reference suitable for a frame store, while
14089 converting to a valid addressing mode. */
14092 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14094 rtx int_rtx, offset_rtx;
14096 int_rtx = GEN_INT (offset);
14098 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14099 || (TARGET_E500_DOUBLE && mode == DFmode))
14101 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14102 emit_move_insn (offset_rtx, int_rtx);
14105 offset_rtx = int_rtx;
14107 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14110 /* Look for user-defined global regs. We should not save and restore these,
14111 and cannot use stmw/lmw if there are any in its range. */
14114 no_global_regs_above (int first_greg)
14117 for (i = 0; i < 32 - first_greg; i++)
14118 if (global_regs[first_greg + i])
14123 #ifndef TARGET_FIX_AND_CONTINUE
14124 #define TARGET_FIX_AND_CONTINUE 0
14127 /* Emit function prologue as insns. */
14130 rs6000_emit_prologue (void)
14132 rs6000_stack_t *info = rs6000_stack_info ();
14133 enum machine_mode reg_mode = Pmode;
14134 int reg_size = TARGET_32BIT ? 4 : 8;
14135 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14136 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14137 rtx frame_reg_rtx = sp_reg_rtx;
14138 rtx cr_save_rtx = NULL_RTX;
14140 int saving_FPRs_inline;
14141 int using_store_multiple;
14142 HOST_WIDE_INT sp_offset = 0;
14144 if (TARGET_FIX_AND_CONTINUE)
14146 /* gdb on darwin arranges to forward a function from the old
14147 address by modifying the first 5 instructions of the function
14148 to branch to the overriding function. This is necessary to
14149 permit function pointers that point to the old function to
14150 actually forward to the new function. */
14151 emit_insn (gen_nop ());
14152 emit_insn (gen_nop ());
14153 emit_insn (gen_nop ());
14154 emit_insn (gen_nop ());
14155 emit_insn (gen_nop ());
14158 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14160 reg_mode = V2SImode;
14164 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14165 && (!TARGET_SPE_ABI
14166 || info->spe_64bit_regs_used == 0)
14167 && info->first_gp_reg_save < 31
14168 && no_global_regs_above (info->first_gp_reg_save));
14169 saving_FPRs_inline = (info->first_fp_reg_save == 64
14170 || FP_SAVE_INLINE (info->first_fp_reg_save)
14171 || current_function_calls_eh_return
14172 || cfun->machine->ra_need_lr);
14174 /* For V.4, update stack before we do any saving and set back pointer. */
14176 && (DEFAULT_ABI == ABI_V4
14177 || current_function_calls_eh_return))
14179 if (info->total_size < 32767)
14180 sp_offset = info->total_size;
14182 frame_reg_rtx = frame_ptr_rtx;
14183 rs6000_emit_allocate_stack (info->total_size,
14184 (frame_reg_rtx != sp_reg_rtx
14185 && (info->cr_save_p
14187 || info->first_fp_reg_save < 64
14188 || info->first_gp_reg_save < 32
14190 if (frame_reg_rtx != sp_reg_rtx)
14191 rs6000_emit_stack_tie ();
14194 /* Handle world saves specially here. */
14195 if (WORLD_SAVE_P (info))
14201 /* save_world expects lr in r0. */
14202 if (info->lr_save_p)
14204 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14205 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14206 RTX_FRAME_RELATED_P (insn) = 1;
14209 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14210 assumptions about the offsets of various bits of the stack
14212 gcc_assert (info->gp_save_offset == -220
14213 && info->fp_save_offset == -144
14214 && info->lr_save_offset == 8
14215 && info->cr_save_offset == 4
14218 && (!current_function_calls_eh_return
14219 || info->ehrd_offset == -432)
14220 && info->vrsave_save_offset == -224
14221 && info->altivec_save_offset == (-224 -16 -192));
14223 treg = gen_rtx_REG (SImode, 11);
14224 emit_move_insn (treg, GEN_INT (-info->total_size));
14226 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14227 in R11. It also clobbers R12, so beware! */
14229 /* Preserve CR2 for save_world prologues */
14231 sz += 32 - info->first_gp_reg_save;
14232 sz += 64 - info->first_fp_reg_save;
14233 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14234 p = rtvec_alloc (sz);
14236 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14237 gen_rtx_REG (Pmode,
14238 LINK_REGISTER_REGNUM));
14239 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14240 gen_rtx_SYMBOL_REF (Pmode,
14242 /* We do floats first so that the instruction pattern matches
14244 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14246 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14247 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14248 GEN_INT (info->fp_save_offset
14249 + sp_offset + 8 * i));
14250 rtx mem = gen_frame_mem (DFmode, addr);
14252 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14254 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14256 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14257 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14258 GEN_INT (info->altivec_save_offset
14259 + sp_offset + 16 * i));
14260 rtx mem = gen_frame_mem (V4SImode, addr);
14262 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14264 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14266 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14267 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14268 GEN_INT (info->gp_save_offset
14269 + sp_offset + reg_size * i));
14270 rtx mem = gen_frame_mem (reg_mode, addr);
14272 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14276 /* CR register traditionally saved as CR2. */
14277 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14278 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14279 GEN_INT (info->cr_save_offset
14281 rtx mem = gen_frame_mem (reg_mode, addr);
14283 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14285 /* Prevent any attempt to delete the setting of r0 and treg! */
14286 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14287 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14288 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14290 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14291 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14292 NULL_RTX, NULL_RTX);
14294 if (current_function_calls_eh_return)
14299 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14300 if (regno == INVALID_REGNUM)
14302 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14303 info->ehrd_offset + sp_offset
14304 + reg_size * (int) i,
14310 /* Save AltiVec registers if needed. */
14311 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14315 /* There should be a non inline version of this, for when we
14316 are saving lots of vector registers. */
14317 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14318 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14320 rtx areg, savereg, mem;
14323 offset = info->altivec_save_offset + sp_offset
14324 + 16 * (i - info->first_altivec_reg_save);
14326 savereg = gen_rtx_REG (V4SImode, i);
14328 areg = gen_rtx_REG (Pmode, 0);
14329 emit_move_insn (areg, GEN_INT (offset));
14331 /* AltiVec addressing mode is [reg+reg]. */
14332 mem = gen_frame_mem (V4SImode,
14333 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14335 insn = emit_move_insn (mem, savereg);
14337 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14338 areg, GEN_INT (offset));
14342 /* VRSAVE is a bit vector representing which AltiVec registers
14343 are used. The OS uses this to determine which vector
14344 registers to save on a context switch. We need to save
14345 VRSAVE on the stack frame, add whatever AltiVec registers we
14346 used in this function, and do the corresponding magic in the
14349 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14350 && info->vrsave_mask != 0)
14352 rtx reg, mem, vrsave;
14355 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14356 as frame_reg_rtx and r11 as the static chain pointer for
14357 nested functions. */
14358 reg = gen_rtx_REG (SImode, 0);
14359 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14361 emit_insn (gen_get_vrsave_internal (reg));
14363 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14365 if (!WORLD_SAVE_P (info))
14368 offset = info->vrsave_save_offset + sp_offset;
14369 mem = gen_frame_mem (SImode,
14370 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14371 GEN_INT (offset)));
14372 insn = emit_move_insn (mem, reg);
14375 /* Include the registers in the mask. */
14376 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14378 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14381 /* If we use the link register, get it into r0. */
14382 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14384 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14385 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14386 RTX_FRAME_RELATED_P (insn) = 1;
14389 /* If we need to save CR, put it into r12. */
14390 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14394 cr_save_rtx = gen_rtx_REG (SImode, 12);
14395 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14396 RTX_FRAME_RELATED_P (insn) = 1;
14397 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14398 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14399 But that's OK. All we have to do is specify that _one_ condition
14400 code register is saved in this stack slot. The thrower's epilogue
14401 will then restore all the call-saved registers.
14402 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14403 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14404 gen_rtx_REG (SImode, CR2_REGNO));
14405 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14410 /* Do any required saving of fpr's. If only one or two to save, do
14411 it ourselves. Otherwise, call function. */
14412 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14415 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14416 if ((regs_ever_live[info->first_fp_reg_save+i]
14417 && ! call_used_regs[info->first_fp_reg_save+i]))
14418 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14419 info->first_fp_reg_save + i,
14420 info->fp_save_offset + sp_offset + 8 * i,
14423 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14427 const char *alloc_rname;
14429 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14431 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14432 gen_rtx_REG (Pmode,
14433 LINK_REGISTER_REGNUM));
14434 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14435 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14436 alloc_rname = ggc_strdup (rname);
14437 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14438 gen_rtx_SYMBOL_REF (Pmode,
14440 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14442 rtx addr, reg, mem;
14443 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14444 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14445 GEN_INT (info->fp_save_offset
14446 + sp_offset + 8*i));
14447 mem = gen_frame_mem (DFmode, addr);
14449 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14451 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14452 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14453 NULL_RTX, NULL_RTX);
14456 /* Save GPRs. This is done as a PARALLEL if we are using
14457 the store-multiple instructions. */
14458 if (!WORLD_SAVE_P (info) && using_store_multiple)
14462 p = rtvec_alloc (32 - info->first_gp_reg_save);
14463 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14465 rtx addr, reg, mem;
14466 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14467 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14468 GEN_INT (info->gp_save_offset
14471 mem = gen_frame_mem (reg_mode, addr);
14473 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14475 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14476 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14477 NULL_RTX, NULL_RTX);
14479 else if (!WORLD_SAVE_P (info))
14482 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14483 if ((regs_ever_live[info->first_gp_reg_save + i]
14484 && (!call_used_regs[info->first_gp_reg_save + i]
14485 || (i + info->first_gp_reg_save
14486 == RS6000_PIC_OFFSET_TABLE_REGNUM
14487 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14488 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14489 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14490 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14492 rtx addr, reg, mem;
14493 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14495 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14497 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14500 if (!SPE_CONST_OFFSET_OK (offset))
14502 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14503 emit_move_insn (b, GEN_INT (offset));
14506 b = GEN_INT (offset);
14508 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14509 mem = gen_frame_mem (V2SImode, addr);
14510 insn = emit_move_insn (mem, reg);
14512 if (GET_CODE (b) == CONST_INT)
14513 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14514 NULL_RTX, NULL_RTX);
14516 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14517 b, GEN_INT (offset));
14521 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14522 GEN_INT (info->gp_save_offset
14525 mem = gen_frame_mem (reg_mode, addr);
14527 insn = emit_move_insn (mem, reg);
14528 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14529 NULL_RTX, NULL_RTX);
14534 /* ??? There's no need to emit actual instructions here, but it's the
14535 easiest way to get the frame unwind information emitted. */
14536 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14538 unsigned int i, regno;
14540 /* In AIX ABI we need to pretend we save r2 here. */
14543 rtx addr, reg, mem;
14545 reg = gen_rtx_REG (reg_mode, 2);
14546 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14547 GEN_INT (sp_offset + 5 * reg_size));
14548 mem = gen_frame_mem (reg_mode, addr);
14550 insn = emit_move_insn (mem, reg);
14551 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14552 NULL_RTX, NULL_RTX);
14553 PATTERN (insn) = gen_blockage ();
14558 regno = EH_RETURN_DATA_REGNO (i);
14559 if (regno == INVALID_REGNUM)
14562 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14563 info->ehrd_offset + sp_offset
14564 + reg_size * (int) i,
14569 /* Save lr if we used it. */
14570 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14572 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14573 GEN_INT (info->lr_save_offset + sp_offset));
14574 rtx reg = gen_rtx_REG (Pmode, 0);
14575 rtx mem = gen_rtx_MEM (Pmode, addr);
14576 /* This should not be of frame_alias_set, because of
14577 __builtin_return_address. */
14579 insn = emit_move_insn (mem, reg);
14580 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14581 NULL_RTX, NULL_RTX);
14584 /* Save CR if we use any that must be preserved. */
14585 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14587 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14588 GEN_INT (info->cr_save_offset + sp_offset));
14589 rtx mem = gen_frame_mem (SImode, addr);
14590 /* See the large comment above about why CR2_REGNO is used. */
14591 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14593 /* If r12 was used to hold the original sp, copy cr into r0 now
14595 if (REGNO (frame_reg_rtx) == 12)
14599 cr_save_rtx = gen_rtx_REG (SImode, 0);
14600 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14601 RTX_FRAME_RELATED_P (insn) = 1;
14602 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14603 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14608 insn = emit_move_insn (mem, cr_save_rtx);
14610 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14611 NULL_RTX, NULL_RTX);
14614 /* Update stack and set back pointer unless this is V.4,
14615 for which it was done previously. */
14616 if (!WORLD_SAVE_P (info) && info->push_p
14617 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14618 rs6000_emit_allocate_stack (info->total_size, FALSE);
14620 /* Set frame pointer, if needed. */
14621 if (frame_pointer_needed)
14623 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14625 RTX_FRAME_RELATED_P (insn) = 1;
14628 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14629 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14630 || (DEFAULT_ABI == ABI_V4
14631 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14632 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14634 /* If emit_load_toc_table will use the link register, we need to save
14635 it. We use R12 for this purpose because emit_load_toc_table
14636 can use register 0. This allows us to use a plain 'blr' to return
14637 from the procedure more often. */
14638 int save_LR_around_toc_setup = (TARGET_ELF
14639 && DEFAULT_ABI != ABI_AIX
14641 && ! info->lr_save_p
14642 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14643 if (save_LR_around_toc_setup)
14645 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14647 insn = emit_move_insn (frame_ptr_rtx, lr);
14648 rs6000_maybe_dead (insn);
14649 RTX_FRAME_RELATED_P (insn) = 1;
14651 rs6000_emit_load_toc_table (TRUE);
14653 insn = emit_move_insn (lr, frame_ptr_rtx);
14654 rs6000_maybe_dead (insn);
14655 RTX_FRAME_RELATED_P (insn) = 1;
14658 rs6000_emit_load_toc_table (TRUE);
14662 if (DEFAULT_ABI == ABI_DARWIN
14663 && flag_pic && current_function_uses_pic_offset_table)
14665 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14666 rtx src = machopic_function_base_sym ();
14668 /* Save and restore LR locally around this call (in R0). */
14669 if (!info->lr_save_p)
14670 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14672 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14674 insn = emit_move_insn (gen_rtx_REG (Pmode,
14675 RS6000_PIC_OFFSET_TABLE_REGNUM),
14677 rs6000_maybe_dead (insn);
14679 if (!info->lr_save_p)
14680 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14685 /* Write function prologue. */
14688 rs6000_output_function_prologue (FILE *file,
14689 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14691 rs6000_stack_t *info = rs6000_stack_info ();
14693 if (TARGET_DEBUG_STACK)
14694 debug_stack_info (info);
14696 /* Write .extern for any function we will call to save and restore
14698 if (info->first_fp_reg_save < 64
14699 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14700 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14701 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14702 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14703 RESTORE_FP_SUFFIX);
14705 /* Write .extern for AIX common mode routines, if needed. */
14706 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14708 fputs ("\t.extern __mulh\n", file);
14709 fputs ("\t.extern __mull\n", file);
14710 fputs ("\t.extern __divss\n", file);
14711 fputs ("\t.extern __divus\n", file);
14712 fputs ("\t.extern __quoss\n", file);
14713 fputs ("\t.extern __quous\n", file);
14714 common_mode_defined = 1;
14717 if (! HAVE_prologue)
14721 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14722 the "toplevel" insn chain. */
14723 emit_note (NOTE_INSN_DELETED);
14724 rs6000_emit_prologue ();
14725 emit_note (NOTE_INSN_DELETED);
14727 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14731 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14733 INSN_ADDRESSES_NEW (insn, addr);
14738 if (TARGET_DEBUG_STACK)
14739 debug_rtx_list (get_insns (), 100);
14740 final (get_insns (), file, FALSE);
14744 rs6000_pic_labelno++;
14747 /* Emit function epilogue as insns.
14749 At present, dwarf2out_frame_debug_expr doesn't understand
14750 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14751 anywhere in the epilogue. Most of the insns below would in any case
14752 need special notes to explain where r11 is in relation to the stack. */
14755 rs6000_emit_epilogue (int sibcall)
14757 rs6000_stack_t *info;
14758 int restoring_FPRs_inline;
14759 int using_load_multiple;
14760 int using_mfcr_multiple;
14761 int use_backchain_to_restore_sp;
14763 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14764 rtx frame_reg_rtx = sp_reg_rtx;
14765 enum machine_mode reg_mode = Pmode;
14766 int reg_size = TARGET_32BIT ? 4 : 8;
14769 info = rs6000_stack_info ();
14771 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14773 reg_mode = V2SImode;
14777 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14778 && (!TARGET_SPE_ABI
14779 || info->spe_64bit_regs_used == 0)
14780 && info->first_gp_reg_save < 31
14781 && no_global_regs_above (info->first_gp_reg_save));
14782 restoring_FPRs_inline = (sibcall
14783 || current_function_calls_eh_return
14784 || info->first_fp_reg_save == 64
14785 || FP_SAVE_INLINE (info->first_fp_reg_save));
14786 use_backchain_to_restore_sp = (frame_pointer_needed
14787 || current_function_calls_alloca
14788 || info->total_size > 32767);
14789 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14790 || rs6000_cpu == PROCESSOR_PPC603
14791 || rs6000_cpu == PROCESSOR_PPC750
14794 if (WORLD_SAVE_P (info))
14798 const char *alloc_rname;
14801 /* eh_rest_world_r10 will return to the location saved in the LR
14802 stack slot (which is not likely to be our caller.)
14803 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14804 rest_world is similar, except any R10 parameter is ignored.
14805 The exception-handling stuff that was here in 2.95 is no
14806 longer necessary. */
14810 + 32 - info->first_gp_reg_save
14811 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14812 + 63 + 1 - info->first_fp_reg_save);
14814 strcpy (rname, ((current_function_calls_eh_return) ?
14815 "*eh_rest_world_r10" : "*rest_world"));
14816 alloc_rname = ggc_strdup (rname);
14819 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14820 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14821 gen_rtx_REG (Pmode,
14822 LINK_REGISTER_REGNUM));
14824 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14825 /* The instruction pattern requires a clobber here;
14826 it is shared with the restVEC helper. */
14828 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14831 /* CR register traditionally saved as CR2. */
14832 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14833 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14834 GEN_INT (info->cr_save_offset));
14835 rtx mem = gen_frame_mem (reg_mode, addr);
14837 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14840 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14842 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14843 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14844 GEN_INT (info->gp_save_offset
14846 rtx mem = gen_frame_mem (reg_mode, addr);
14848 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14850 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14852 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14853 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14854 GEN_INT (info->altivec_save_offset
14856 rtx mem = gen_frame_mem (V4SImode, addr);
14858 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14860 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14862 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14863 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14864 GEN_INT (info->fp_save_offset
14866 rtx mem = gen_frame_mem (DFmode, addr);
14868 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14871 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14873 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14875 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14877 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14879 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14880 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14885 /* If we have a frame pointer, a call to alloca, or a large stack
14886 frame, restore the old stack pointer using the backchain. Otherwise,
14887 we know what size to update it with. */
14888 if (use_backchain_to_restore_sp)
14890 /* Under V.4, don't reset the stack pointer until after we're done
14891 loading the saved registers. */
14892 if (DEFAULT_ABI == ABI_V4)
14893 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14895 emit_move_insn (frame_reg_rtx,
14896 gen_rtx_MEM (Pmode, sp_reg_rtx));
14898 else if (info->push_p)
14900 if (DEFAULT_ABI == ABI_V4
14901 || current_function_calls_eh_return)
14902 sp_offset = info->total_size;
14905 emit_insn (TARGET_32BIT
14906 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14907 GEN_INT (info->total_size))
14908 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14909 GEN_INT (info->total_size)));
14913 /* Restore AltiVec registers if needed. */
14914 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14918 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14919 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14921 rtx addr, areg, mem;
14923 areg = gen_rtx_REG (Pmode, 0);
14925 (areg, GEN_INT (info->altivec_save_offset
14927 + 16 * (i - info->first_altivec_reg_save)));
14929 /* AltiVec addressing mode is [reg+reg]. */
14930 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14931 mem = gen_frame_mem (V4SImode, addr);
14933 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14937 /* Restore VRSAVE if needed. */
14938 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14939 && info->vrsave_mask != 0)
14941 rtx addr, mem, reg;
14943 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14944 GEN_INT (info->vrsave_save_offset + sp_offset));
14945 mem = gen_frame_mem (SImode, addr);
14946 reg = gen_rtx_REG (SImode, 12);
14947 emit_move_insn (reg, mem);
14949 emit_insn (generate_set_vrsave (reg, info, 1));
14952 /* Get the old lr if we saved it. */
14953 if (info->lr_save_p)
14955 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14956 info->lr_save_offset + sp_offset);
14958 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14961 /* Get the old cr if we saved it. */
14962 if (info->cr_save_p)
14964 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14965 GEN_INT (info->cr_save_offset + sp_offset));
14966 rtx mem = gen_frame_mem (SImode, addr);
14968 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14971 /* Set LR here to try to overlap restores below. */
14972 if (info->lr_save_p)
14973 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14974 gen_rtx_REG (Pmode, 0));
14976 /* Load exception handler data registers, if needed. */
14977 if (current_function_calls_eh_return)
14979 unsigned int i, regno;
14983 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14984 GEN_INT (sp_offset + 5 * reg_size));
14985 rtx mem = gen_frame_mem (reg_mode, addr);
14987 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14994 regno = EH_RETURN_DATA_REGNO (i);
14995 if (regno == INVALID_REGNUM)
14998 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14999 info->ehrd_offset + sp_offset
15000 + reg_size * (int) i);
15002 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15006 /* Restore GPRs. This is done as a PARALLEL if we are using
15007 the load-multiple instructions. */
15008 if (using_load_multiple)
15011 p = rtvec_alloc (32 - info->first_gp_reg_save);
15012 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15014 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15015 GEN_INT (info->gp_save_offset
15018 rtx mem = gen_frame_mem (reg_mode, addr);
15021 gen_rtx_SET (VOIDmode,
15022 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15025 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15028 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15029 if ((regs_ever_live[info->first_gp_reg_save + i]
15030 && (!call_used_regs[info->first_gp_reg_save + i]
15031 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15032 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15033 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15034 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15035 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15037 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15038 GEN_INT (info->gp_save_offset
15041 rtx mem = gen_frame_mem (reg_mode, addr);
15043 /* Restore 64-bit quantities for SPE. */
15044 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15046 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15049 if (!SPE_CONST_OFFSET_OK (offset))
15051 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15052 emit_move_insn (b, GEN_INT (offset));
15055 b = GEN_INT (offset);
15057 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15058 mem = gen_frame_mem (V2SImode, addr);
15061 emit_move_insn (gen_rtx_REG (reg_mode,
15062 info->first_gp_reg_save + i), mem);
15065 /* Restore fpr's if we need to do it without calling a function. */
15066 if (restoring_FPRs_inline)
15067 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15068 if ((regs_ever_live[info->first_fp_reg_save+i]
15069 && ! call_used_regs[info->first_fp_reg_save+i]))
15072 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15073 GEN_INT (info->fp_save_offset
15076 mem = gen_frame_mem (DFmode, addr);
15078 emit_move_insn (gen_rtx_REG (DFmode,
15079 info->first_fp_reg_save + i),
15083 /* If we saved cr, restore it here. Just those that were used. */
15084 if (info->cr_save_p)
15086 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15089 if (using_mfcr_multiple)
15091 for (i = 0; i < 8; i++)
15092 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15094 gcc_assert (count);
15097 if (using_mfcr_multiple && count > 1)
15102 p = rtvec_alloc (count);
15105 for (i = 0; i < 8; i++)
15106 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15108 rtvec r = rtvec_alloc (2);
15109 RTVEC_ELT (r, 0) = r12_rtx;
15110 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15111 RTVEC_ELT (p, ndx) =
15112 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15113 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15116 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15117 gcc_assert (ndx == count);
15120 for (i = 0; i < 8; i++)
15121 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15123 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15129 /* If this is V.4, unwind the stack pointer after all of the loads
15131 if (frame_reg_rtx != sp_reg_rtx)
15133 /* This blockage is needed so that sched doesn't decide to move
15134 the sp change before the register restores. */
15135 rs6000_emit_stack_tie ();
15136 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15138 else if (sp_offset != 0)
15139 emit_insn (TARGET_32BIT
15140 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15141 GEN_INT (sp_offset))
15142 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15143 GEN_INT (sp_offset)));
15145 if (current_function_calls_eh_return)
15147 rtx sa = EH_RETURN_STACKADJ_RTX;
15148 emit_insn (TARGET_32BIT
15149 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15150 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15156 if (! restoring_FPRs_inline)
15157 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15159 p = rtvec_alloc (2);
15161 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15162 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15163 gen_rtx_REG (Pmode,
15164 LINK_REGISTER_REGNUM));
15166 /* If we have to restore more than two FP registers, branch to the
15167 restore function. It will return to our caller. */
15168 if (! restoring_FPRs_inline)
15172 const char *alloc_rname;
15174 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15175 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15176 alloc_rname = ggc_strdup (rname);
15177 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15178 gen_rtx_SYMBOL_REF (Pmode,
15181 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15184 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15185 GEN_INT (info->fp_save_offset + 8*i));
15186 mem = gen_frame_mem (DFmode, addr);
15188 RTVEC_ELT (p, i+3) =
15189 gen_rtx_SET (VOIDmode,
15190 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15195 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15199 /* Write function epilogue. */
15202 rs6000_output_function_epilogue (FILE *file,
15203 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15205 if (! HAVE_epilogue)
15207 rtx insn = get_last_insn ();
15208 /* If the last insn was a BARRIER, we don't have to write anything except
15209 the trace table. */
15210 if (GET_CODE (insn) == NOTE)
15211 insn = prev_nonnote_insn (insn);
15212 if (insn == 0 || GET_CODE (insn) != BARRIER)
15214 /* This is slightly ugly, but at least we don't have two
15215 copies of the epilogue-emitting code. */
15218 /* A NOTE_INSN_DELETED is supposed to be at the start
15219 and end of the "toplevel" insn chain. */
15220 emit_note (NOTE_INSN_DELETED);
15221 rs6000_emit_epilogue (FALSE);
15222 emit_note (NOTE_INSN_DELETED);
15224 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15228 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15230 INSN_ADDRESSES_NEW (insn, addr);
15235 if (TARGET_DEBUG_STACK)
15236 debug_rtx_list (get_insns (), 100);
15237 final (get_insns (), file, FALSE);
15243 macho_branch_islands ();
15244 /* Mach-O doesn't support labels at the end of objects, so if
15245 it looks like we might want one, insert a NOP. */
15247 rtx insn = get_last_insn ();
15250 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15251 insn = PREV_INSN (insn);
15255 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15256 fputs ("\tnop\n", file);
15260 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15263 We don't output a traceback table if -finhibit-size-directive was
15264 used. The documentation for -finhibit-size-directive reads
15265 ``don't output a @code{.size} assembler directive, or anything
15266 else that would cause trouble if the function is split in the
15267 middle, and the two halves are placed at locations far apart in
15268 memory.'' The traceback table has this property, since it
15269 includes the offset from the start of the function to the
15270 traceback table itself.
15272 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15273 different traceback table. */
15274 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15275 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15277 const char *fname = NULL;
15278 const char *language_string = lang_hooks.name;
15279 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15281 int optional_tbtab;
15282 rs6000_stack_t *info = rs6000_stack_info ();
15284 if (rs6000_traceback == traceback_full)
15285 optional_tbtab = 1;
15286 else if (rs6000_traceback == traceback_part)
15287 optional_tbtab = 0;
15289 optional_tbtab = !optimize_size && !TARGET_ELF;
15291 if (optional_tbtab)
15293 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15294 while (*fname == '.') /* V.4 encodes . in the name */
15297 /* Need label immediately before tbtab, so we can compute
15298 its offset from the function start. */
15299 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15300 ASM_OUTPUT_LABEL (file, fname);
15303 /* The .tbtab pseudo-op can only be used for the first eight
15304 expressions, since it can't handle the possibly variable
15305 length fields that follow. However, if you omit the optional
15306 fields, the assembler outputs zeros for all optional fields
15307 anyways, giving each variable length field is minimum length
15308 (as defined in sys/debug.h). Thus we can not use the .tbtab
15309 pseudo-op at all. */
15311 /* An all-zero word flags the start of the tbtab, for debuggers
15312 that have to find it by searching forward from the entry
15313 point or from the current pc. */
15314 fputs ("\t.long 0\n", file);
15316 /* Tbtab format type. Use format type 0. */
15317 fputs ("\t.byte 0,", file);
15319 /* Language type. Unfortunately, there does not seem to be any
15320 official way to discover the language being compiled, so we
15321 use language_string.
15322 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15323 Java is 13. Objective-C is 14. */
15324 if (! strcmp (language_string, "GNU C"))
15326 else if (! strcmp (language_string, "GNU F77")
15327 || ! strcmp (language_string, "GNU F95"))
15329 else if (! strcmp (language_string, "GNU Pascal"))
15331 else if (! strcmp (language_string, "GNU Ada"))
15333 else if (! strcmp (language_string, "GNU C++"))
15335 else if (! strcmp (language_string, "GNU Java"))
15337 else if (! strcmp (language_string, "GNU Objective-C"))
15340 gcc_unreachable ();
15341 fprintf (file, "%d,", i);
15343 /* 8 single bit fields: global linkage (not set for C extern linkage,
15344 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15345 from start of procedure stored in tbtab, internal function, function
15346 has controlled storage, function has no toc, function uses fp,
15347 function logs/aborts fp operations. */
15348 /* Assume that fp operations are used if any fp reg must be saved. */
15349 fprintf (file, "%d,",
15350 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15352 /* 6 bitfields: function is interrupt handler, name present in
15353 proc table, function calls alloca, on condition directives
15354 (controls stack walks, 3 bits), saves condition reg, saves
15356 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15357 set up as a frame pointer, even when there is no alloca call. */
15358 fprintf (file, "%d,",
15359 ((optional_tbtab << 6)
15360 | ((optional_tbtab & frame_pointer_needed) << 5)
15361 | (info->cr_save_p << 1)
15362 | (info->lr_save_p)));
15364 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15366 fprintf (file, "%d,",
15367 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15369 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15370 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15372 if (optional_tbtab)
15374 /* Compute the parameter info from the function decl argument
15377 int next_parm_info_bit = 31;
15379 for (decl = DECL_ARGUMENTS (current_function_decl);
15380 decl; decl = TREE_CHAIN (decl))
15382 rtx parameter = DECL_INCOMING_RTL (decl);
15383 enum machine_mode mode = GET_MODE (parameter);
15385 if (GET_CODE (parameter) == REG)
15387 if (SCALAR_FLOAT_MODE_P (mode))
15405 gcc_unreachable ();
15408 /* If only one bit will fit, don't or in this entry. */
15409 if (next_parm_info_bit > 0)
15410 parm_info |= (bits << (next_parm_info_bit - 1));
15411 next_parm_info_bit -= 2;
15415 fixed_parms += ((GET_MODE_SIZE (mode)
15416 + (UNITS_PER_WORD - 1))
15418 next_parm_info_bit -= 1;
15424 /* Number of fixed point parameters. */
15425 /* This is actually the number of words of fixed point parameters; thus
15426 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15427 fprintf (file, "%d,", fixed_parms);
15429 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15431 /* This is actually the number of fp registers that hold parameters;
15432 and thus the maximum value is 13. */
15433 /* Set parameters on stack bit if parameters are not in their original
15434 registers, regardless of whether they are on the stack? Xlc
15435 seems to set the bit when not optimizing. */
15436 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15438 if (! optional_tbtab)
15441 /* Optional fields follow. Some are variable length. */
15443 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15444 11 double float. */
15445 /* There is an entry for each parameter in a register, in the order that
15446 they occur in the parameter list. Any intervening arguments on the
15447 stack are ignored. If the list overflows a long (max possible length
15448 34 bits) then completely leave off all elements that don't fit. */
15449 /* Only emit this long if there was at least one parameter. */
15450 if (fixed_parms || float_parms)
15451 fprintf (file, "\t.long %d\n", parm_info);
15453 /* Offset from start of code to tb table. */
15454 fputs ("\t.long ", file);
15455 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15457 RS6000_OUTPUT_BASENAME (file, fname);
15459 assemble_name (file, fname);
15461 rs6000_output_function_entry (file, fname);
15464 /* Interrupt handler mask. */
15465 /* Omit this long, since we never set the interrupt handler bit
15468 /* Number of CTL (controlled storage) anchors. */
15469 /* Omit this long, since the has_ctl bit is never set above. */
15471 /* Displacement into stack of each CTL anchor. */
15472 /* Omit this list of longs, because there are no CTL anchors. */
15474 /* Length of function name. */
15477 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15479 /* Function name. */
15480 assemble_string (fname, strlen (fname));
15482 /* Register for alloca automatic storage; this is always reg 31.
15483 Only emit this if the alloca bit was set above. */
15484 if (frame_pointer_needed)
15485 fputs ("\t.byte 31\n", file);
15487 fputs ("\t.align 2\n", file);
15491 /* A C compound statement that outputs the assembler code for a thunk
15492 function, used to implement C++ virtual function calls with
15493 multiple inheritance. The thunk acts as a wrapper around a virtual
15494 function, adjusting the implicit object parameter before handing
15495 control off to the real function.
15497 First, emit code to add the integer DELTA to the location that
15498 contains the incoming first argument. Assume that this argument
15499 contains a pointer, and is the one used to pass the `this' pointer
15500 in C++. This is the incoming argument *before* the function
15501 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15502 values of all other incoming arguments.
15504 After the addition, emit code to jump to FUNCTION, which is a
15505 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15506 not touch the return address. Hence returning from FUNCTION will
15507 return to whoever called the current `thunk'.
15509 The effect must be as if FUNCTION had been called directly with the
15510 adjusted first argument. This macro is responsible for emitting
15511 all of the code for a thunk function; output_function_prologue()
15512 and output_function_epilogue() are not invoked.
15514 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15515 been extracted from it.) It might possibly be useful on some
15516 targets, but probably not.
15518 If you do not define this macro, the target-independent code in the
15519 C++ frontend will generate a less efficient heavyweight thunk that
15520 calls FUNCTION instead of jumping to it. The generic approach does
15521 not support varargs. */
15524 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15525 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15528 rtx this, insn, funexp;
15530 reload_completed = 1;
15531 epilogue_completed = 1;
15532 no_new_pseudos = 1;
15533 reset_block_changes ();
15535 /* Mark the end of the (empty) prologue. */
15536 emit_note (NOTE_INSN_PROLOGUE_END);
15538 /* Find the "this" pointer. If the function returns a structure,
15539 the structure return pointer is in r3. */
15540 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15541 this = gen_rtx_REG (Pmode, 4);
15543 this = gen_rtx_REG (Pmode, 3);
15545 /* Apply the constant offset, if required. */
15548 rtx delta_rtx = GEN_INT (delta);
15549 emit_insn (TARGET_32BIT
15550 ? gen_addsi3 (this, this, delta_rtx)
15551 : gen_adddi3 (this, this, delta_rtx));
15554 /* Apply the offset from the vtable, if required. */
15557 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15558 rtx tmp = gen_rtx_REG (Pmode, 12);
15560 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15561 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15563 emit_insn (TARGET_32BIT
15564 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15565 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15566 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15570 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15572 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15574 emit_insn (TARGET_32BIT
15575 ? gen_addsi3 (this, this, tmp)
15576 : gen_adddi3 (this, this, tmp));
15579 /* Generate a tail call to the target function. */
15580 if (!TREE_USED (function))
15582 assemble_external (function);
15583 TREE_USED (function) = 1;
15585 funexp = XEXP (DECL_RTL (function), 0);
15586 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15589 if (MACHOPIC_INDIRECT)
15590 funexp = machopic_indirect_call_target (funexp);
15593 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15594 generate sibcall RTL explicitly. */
15595 insn = emit_call_insn (
15596 gen_rtx_PARALLEL (VOIDmode,
15598 gen_rtx_CALL (VOIDmode,
15599 funexp, const0_rtx),
15600 gen_rtx_USE (VOIDmode, const0_rtx),
15601 gen_rtx_USE (VOIDmode,
15602 gen_rtx_REG (SImode,
15603 LINK_REGISTER_REGNUM)),
15604 gen_rtx_RETURN (VOIDmode))));
15605 SIBLING_CALL_P (insn) = 1;
15608 /* Run just enough of rest_of_compilation to get the insns emitted.
15609 There's not really enough bulk here to make other passes such as
15610 instruction scheduling worth while. Note that use_thunk calls
15611 assemble_start_function and assemble_end_function. */
15612 insn = get_insns ();
15613 insn_locators_initialize ();
15614 shorten_branches (insn);
15615 final_start_function (insn, file, 1);
15616 final (insn, file, 1);
15617 final_end_function ();
15619 reload_completed = 0;
15620 epilogue_completed = 0;
15621 no_new_pseudos = 0;
15624 /* A quick summary of the various types of 'constant-pool tables'
15627 Target Flags Name One table per
15628 AIX (none) AIX TOC object file
15629 AIX -mfull-toc AIX TOC object file
15630 AIX -mminimal-toc AIX minimal TOC translation unit
15631 SVR4/EABI (none) SVR4 SDATA object file
15632 SVR4/EABI -fpic SVR4 pic object file
15633 SVR4/EABI -fPIC SVR4 PIC translation unit
15634 SVR4/EABI -mrelocatable EABI TOC function
15635 SVR4/EABI -maix AIX TOC object file
15636 SVR4/EABI -maix -mminimal-toc
15637 AIX minimal TOC translation unit
15639 Name Reg. Set by entries contains:
15640 made by addrs? fp? sum?
15642 AIX TOC 2 crt0 as Y option option
15643 AIX minimal TOC 30 prolog gcc Y Y option
15644 SVR4 SDATA 13 crt0 gcc N Y N
15645 SVR4 pic 30 prolog ld Y not yet N
15646 SVR4 PIC 30 prolog gcc Y option option
15647 EABI TOC 30 prolog gcc Y option option
15651 /* Hash functions for the hash table. */
15654 rs6000_hash_constant (rtx k)
15656 enum rtx_code code = GET_CODE (k);
15657 enum machine_mode mode = GET_MODE (k);
15658 unsigned result = (code << 3) ^ mode;
15659 const char *format;
15662 format = GET_RTX_FORMAT (code);
15663 flen = strlen (format);
15669 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15672 if (mode != VOIDmode)
15673 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15685 for (; fidx < flen; fidx++)
15686 switch (format[fidx])
15691 const char *str = XSTR (k, fidx);
15692 len = strlen (str);
15693 result = result * 613 + len;
15694 for (i = 0; i < len; i++)
15695 result = result * 613 + (unsigned) str[i];
15700 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15704 result = result * 613 + (unsigned) XINT (k, fidx);
15707 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15708 result = result * 613 + (unsigned) XWINT (k, fidx);
15712 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15713 result = result * 613 + (unsigned) (XWINT (k, fidx)
15720 gcc_unreachable ();
15727 toc_hash_function (const void *hash_entry)
15729 const struct toc_hash_struct *thc =
15730 (const struct toc_hash_struct *) hash_entry;
15731 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15734 /* Compare H1 and H2 for equivalence. */
15737 toc_hash_eq (const void *h1, const void *h2)
15739 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15740 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15742 if (((const struct toc_hash_struct *) h1)->key_mode
15743 != ((const struct toc_hash_struct *) h2)->key_mode)
15746 return rtx_equal_p (r1, r2);
15749 /* These are the names given by the C++ front-end to vtables, and
15750 vtable-like objects. Ideally, this logic should not be here;
15751 instead, there should be some programmatic way of inquiring as
15752 to whether or not an object is a vtable. */
15754 #define VTABLE_NAME_P(NAME) \
15755 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15756 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15757 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15758 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15759 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15762 rs6000_output_symbol_ref (FILE *file, rtx x)
15764 /* Currently C++ toc references to vtables can be emitted before it
15765 is decided whether the vtable is public or private. If this is
15766 the case, then the linker will eventually complain that there is
15767 a reference to an unknown section. Thus, for vtables only,
15768 we emit the TOC reference to reference the symbol and not the
15770 const char *name = XSTR (x, 0);
15772 if (VTABLE_NAME_P (name))
15774 RS6000_OUTPUT_BASENAME (file, name);
15777 assemble_name (file, name);
15780 /* Output a TOC entry. We derive the entry name from what is being
15784 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15787 const char *name = buf;
15788 const char *real_name;
15790 HOST_WIDE_INT offset = 0;
15792 gcc_assert (!TARGET_NO_TOC);
15794 /* When the linker won't eliminate them, don't output duplicate
15795 TOC entries (this happens on AIX if there is any kind of TOC,
15796 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15798 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15800 struct toc_hash_struct *h;
15803 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15804 time because GGC is not initialized at that point. */
15805 if (toc_hash_table == NULL)
15806 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15807 toc_hash_eq, NULL);
15809 h = ggc_alloc (sizeof (*h));
15811 h->key_mode = mode;
15812 h->labelno = labelno;
15814 found = htab_find_slot (toc_hash_table, h, 1);
15815 if (*found == NULL)
15817 else /* This is indeed a duplicate.
15818 Set this label equal to that label. */
15820 fputs ("\t.set ", file);
15821 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15822 fprintf (file, "%d,", labelno);
15823 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15824 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15830 /* If we're going to put a double constant in the TOC, make sure it's
15831 aligned properly when strict alignment is on. */
15832 if (GET_CODE (x) == CONST_DOUBLE
15833 && STRICT_ALIGNMENT
15834 && GET_MODE_BITSIZE (mode) >= 64
15835 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15836 ASM_OUTPUT_ALIGN (file, 3);
15839 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15841 /* Handle FP constants specially. Note that if we have a minimal
15842 TOC, things we put here aren't actually in the TOC, so we can allow
15844 if (GET_CODE (x) == CONST_DOUBLE &&
15845 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15847 REAL_VALUE_TYPE rv;
15850 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15851 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15852 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15854 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15858 if (TARGET_MINIMAL_TOC)
15859 fputs (DOUBLE_INT_ASM_OP, file);
15861 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15862 k[0] & 0xffffffff, k[1] & 0xffffffff,
15863 k[2] & 0xffffffff, k[3] & 0xffffffff);
15864 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15865 k[0] & 0xffffffff, k[1] & 0xffffffff,
15866 k[2] & 0xffffffff, k[3] & 0xffffffff);
15871 if (TARGET_MINIMAL_TOC)
15872 fputs ("\t.long ", file);
15874 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15875 k[0] & 0xffffffff, k[1] & 0xffffffff,
15876 k[2] & 0xffffffff, k[3] & 0xffffffff);
15877 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15878 k[0] & 0xffffffff, k[1] & 0xffffffff,
15879 k[2] & 0xffffffff, k[3] & 0xffffffff);
15883 else if (GET_CODE (x) == CONST_DOUBLE &&
15884 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
15886 REAL_VALUE_TYPE rv;
15889 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15891 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15892 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
15894 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15898 if (TARGET_MINIMAL_TOC)
15899 fputs (DOUBLE_INT_ASM_OP, file);
15901 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15902 k[0] & 0xffffffff, k[1] & 0xffffffff);
15903 fprintf (file, "0x%lx%08lx\n",
15904 k[0] & 0xffffffff, k[1] & 0xffffffff);
15909 if (TARGET_MINIMAL_TOC)
15910 fputs ("\t.long ", file);
15912 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15913 k[0] & 0xffffffff, k[1] & 0xffffffff);
15914 fprintf (file, "0x%lx,0x%lx\n",
15915 k[0] & 0xffffffff, k[1] & 0xffffffff);
15919 else if (GET_CODE (x) == CONST_DOUBLE &&
15920 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
15922 REAL_VALUE_TYPE rv;
15925 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15926 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15927 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
15929 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15933 if (TARGET_MINIMAL_TOC)
15934 fputs (DOUBLE_INT_ASM_OP, file);
15936 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15937 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15942 if (TARGET_MINIMAL_TOC)
15943 fputs ("\t.long ", file);
15945 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15946 fprintf (file, "0x%lx\n", l & 0xffffffff);
15950 else if (GET_MODE (x) == VOIDmode
15951 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15953 unsigned HOST_WIDE_INT low;
15954 HOST_WIDE_INT high;
15956 if (GET_CODE (x) == CONST_DOUBLE)
15958 low = CONST_DOUBLE_LOW (x);
15959 high = CONST_DOUBLE_HIGH (x);
15962 #if HOST_BITS_PER_WIDE_INT == 32
15965 high = (low & 0x80000000) ? ~0 : 0;
15969 low = INTVAL (x) & 0xffffffff;
15970 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15974 /* TOC entries are always Pmode-sized, but since this
15975 is a bigendian machine then if we're putting smaller
15976 integer constants in the TOC we have to pad them.
15977 (This is still a win over putting the constants in
15978 a separate constant pool, because then we'd have
15979 to have both a TOC entry _and_ the actual constant.)
15981 For a 32-bit target, CONST_INT values are loaded and shifted
15982 entirely within `low' and can be stored in one TOC entry. */
15984 /* It would be easy to make this work, but it doesn't now. */
15985 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15987 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15989 #if HOST_BITS_PER_WIDE_INT == 32
15990 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15991 POINTER_SIZE, &low, &high, 0);
15994 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15995 high = (HOST_WIDE_INT) low >> 32;
16002 if (TARGET_MINIMAL_TOC)
16003 fputs (DOUBLE_INT_ASM_OP, file);
16005 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16006 (long) high & 0xffffffff, (long) low & 0xffffffff);
16007 fprintf (file, "0x%lx%08lx\n",
16008 (long) high & 0xffffffff, (long) low & 0xffffffff);
16013 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16015 if (TARGET_MINIMAL_TOC)
16016 fputs ("\t.long ", file);
16018 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16019 (long) high & 0xffffffff, (long) low & 0xffffffff);
16020 fprintf (file, "0x%lx,0x%lx\n",
16021 (long) high & 0xffffffff, (long) low & 0xffffffff);
16025 if (TARGET_MINIMAL_TOC)
16026 fputs ("\t.long ", file);
16028 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16029 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16035 if (GET_CODE (x) == CONST)
16037 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16039 base = XEXP (XEXP (x, 0), 0);
16040 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16043 switch (GET_CODE (base))
16046 name = XSTR (base, 0);
16050 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16051 CODE_LABEL_NUMBER (XEXP (base, 0)));
16055 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16059 gcc_unreachable ();
16062 real_name = (*targetm.strip_name_encoding) (name);
16063 if (TARGET_MINIMAL_TOC)
16064 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16067 fprintf (file, "\t.tc %s", real_name);
16070 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16072 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16074 fputs ("[TC],", file);
16077 /* Currently C++ toc references to vtables can be emitted before it
16078 is decided whether the vtable is public or private. If this is
16079 the case, then the linker will eventually complain that there is
16080 a TOC reference to an unknown section. Thus, for vtables only,
16081 we emit the TOC reference to reference the symbol and not the
16083 if (VTABLE_NAME_P (name))
16085 RS6000_OUTPUT_BASENAME (file, name);
16087 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16088 else if (offset > 0)
16089 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16092 output_addr_const (file, x);
16096 /* Output an assembler pseudo-op to write an ASCII string of N characters
16097 starting at P to FILE.
16099 On the RS/6000, we have to do this using the .byte operation and
16100 write out special characters outside the quoted string.
16101 Also, the assembler is broken; very long strings are truncated,
16102 so we must artificially break them up early. */
16105 output_ascii (FILE *file, const char *p, int n)
16108 int i, count_string;
16109 const char *for_string = "\t.byte \"";
16110 const char *for_decimal = "\t.byte ";
16111 const char *to_close = NULL;
16114 for (i = 0; i < n; i++)
16117 if (c >= ' ' && c < 0177)
16120 fputs (for_string, file);
16123 /* Write two quotes to get one. */
16131 for_decimal = "\"\n\t.byte ";
16135 if (count_string >= 512)
16137 fputs (to_close, file);
16139 for_string = "\t.byte \"";
16140 for_decimal = "\t.byte ";
16148 fputs (for_decimal, file);
16149 fprintf (file, "%d", c);
16151 for_string = "\n\t.byte \"";
16152 for_decimal = ", ";
16158 /* Now close the string if we have written one. Then end the line. */
16160 fputs (to_close, file);
16163 /* Generate a unique section name for FILENAME for a section type
16164 represented by SECTION_DESC. Output goes into BUF.
16166 SECTION_DESC can be any string, as long as it is different for each
16167 possible section type.
16169 We name the section in the same manner as xlc. The name begins with an
16170 underscore followed by the filename (after stripping any leading directory
16171 names) with the last period replaced by the string SECTION_DESC. If
16172 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16176 rs6000_gen_section_name (char **buf, const char *filename,
16177 const char *section_desc)
16179 const char *q, *after_last_slash, *last_period = 0;
16183 after_last_slash = filename;
16184 for (q = filename; *q; q++)
16187 after_last_slash = q + 1;
16188 else if (*q == '.')
16192 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16193 *buf = (char *) xmalloc (len);
16198 for (q = after_last_slash; *q; q++)
16200 if (q == last_period)
16202 strcpy (p, section_desc);
16203 p += strlen (section_desc);
16207 else if (ISALNUM (*q))
16211 if (last_period == 0)
16212 strcpy (p, section_desc);
16217 /* Emit profile function. */
16220 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16222 /* Non-standard profiling for kernels, which just saves LR then calls
16223 _mcount without worrying about arg saves. The idea is to change
16224 the function prologue as little as possible as it isn't easy to
16225 account for arg save/restore code added just for _mcount. */
16226 if (TARGET_PROFILE_KERNEL)
16229 if (DEFAULT_ABI == ABI_AIX)
16231 #ifndef NO_PROFILE_COUNTERS
16232 # define NO_PROFILE_COUNTERS 0
16234 if (NO_PROFILE_COUNTERS)
16235 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16239 const char *label_name;
16242 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16243 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16244 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16246 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16250 else if (DEFAULT_ABI == ABI_DARWIN)
16252 const char *mcount_name = RS6000_MCOUNT;
16253 int caller_addr_regno = LINK_REGISTER_REGNUM;
16255 /* Be conservative and always set this, at least for now. */
16256 current_function_uses_pic_offset_table = 1;
16259 /* For PIC code, set up a stub and collect the caller's address
16260 from r0, which is where the prologue puts it. */
16261 if (MACHOPIC_INDIRECT
16262 && current_function_uses_pic_offset_table)
16263 caller_addr_regno = 0;
16265 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16267 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16271 /* Write function profiler code. */
16274 output_function_profiler (FILE *file, int labelno)
16278 switch (DEFAULT_ABI)
16281 gcc_unreachable ();
16286 warning (0, "no profiling of 64-bit code for this ABI");
16289 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16290 fprintf (file, "\tmflr %s\n", reg_names[0]);
16291 if (NO_PROFILE_COUNTERS)
16293 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16294 reg_names[0], reg_names[1]);
16296 else if (TARGET_SECURE_PLT && flag_pic)
16298 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16299 reg_names[0], reg_names[1]);
16300 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16301 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16302 reg_names[12], reg_names[12]);
16303 assemble_name (file, buf);
16304 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16305 assemble_name (file, buf);
16306 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16308 else if (flag_pic == 1)
16310 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16311 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16312 reg_names[0], reg_names[1]);
16313 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16314 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16315 assemble_name (file, buf);
16316 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16318 else if (flag_pic > 1)
16320 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16321 reg_names[0], reg_names[1]);
16322 /* Now, we need to get the address of the label. */
16323 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16324 assemble_name (file, buf);
16325 fputs ("-.\n1:", file);
16326 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16327 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16328 reg_names[0], reg_names[11]);
16329 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16330 reg_names[0], reg_names[0], reg_names[11]);
16334 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16335 assemble_name (file, buf);
16336 fputs ("@ha\n", file);
16337 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16338 reg_names[0], reg_names[1]);
16339 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16340 assemble_name (file, buf);
16341 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16344 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16345 fprintf (file, "\tbl %s%s\n",
16346 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16351 if (!TARGET_PROFILE_KERNEL)
16353 /* Don't do anything, done in output_profile_hook (). */
16357 gcc_assert (!TARGET_32BIT);
16359 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16360 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16362 if (cfun->static_chain_decl != NULL)
16364 asm_fprintf (file, "\tstd %s,24(%s)\n",
16365 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16366 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16367 asm_fprintf (file, "\tld %s,24(%s)\n",
16368 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16371 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16378 /* Power4 load update and store update instructions are cracked into a
16379 load or store and an integer insn which are executed in the same cycle.
16380 Branches have their own dispatch slot which does not count against the
16381 GCC issue rate, but it changes the program flow so there are no other
16382 instructions to issue in this cycle. */
16385 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16386 int verbose ATTRIBUTE_UNUSED,
16387 rtx insn, int more)
16389 if (GET_CODE (PATTERN (insn)) == USE
16390 || GET_CODE (PATTERN (insn)) == CLOBBER)
16393 if (rs6000_sched_groups)
16395 if (is_microcoded_insn (insn))
16397 else if (is_cracked_insn (insn))
16398 return more > 2 ? more - 2 : 0;
16404 /* Adjust the cost of a scheduling dependency. Return the new cost of
16405 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16408 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16410 if (! recog_memoized (insn))
16413 if (REG_NOTE_KIND (link) != 0)
16416 if (REG_NOTE_KIND (link) == 0)
16418 /* Data dependency; DEP_INSN writes a register that INSN reads
16419 some cycles later. */
16421 /* Separate a load from a narrower, dependent store. */
16422 if (rs6000_sched_groups
16423 && GET_CODE (PATTERN (insn)) == SET
16424 && GET_CODE (PATTERN (dep_insn)) == SET
16425 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16426 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16427 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16428 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16431 switch (get_attr_type (insn))
16434 /* Tell the first scheduling pass about the latency between
16435 a mtctr and bctr (and mtlr and br/blr). The first
16436 scheduling pass will not know about this latency since
16437 the mtctr instruction, which has the latency associated
16438 to it, will be generated by reload. */
16439 return TARGET_POWER ? 5 : 4;
16441 /* Leave some extra cycles between a compare and its
16442 dependent branch, to inhibit expensive mispredicts. */
16443 if ((rs6000_cpu_attr == CPU_PPC603
16444 || rs6000_cpu_attr == CPU_PPC604
16445 || rs6000_cpu_attr == CPU_PPC604E
16446 || rs6000_cpu_attr == CPU_PPC620
16447 || rs6000_cpu_attr == CPU_PPC630
16448 || rs6000_cpu_attr == CPU_PPC750
16449 || rs6000_cpu_attr == CPU_PPC7400
16450 || rs6000_cpu_attr == CPU_PPC7450
16451 || rs6000_cpu_attr == CPU_POWER4
16452 || rs6000_cpu_attr == CPU_POWER5)
16453 && recog_memoized (dep_insn)
16454 && (INSN_CODE (dep_insn) >= 0)
16455 && (get_attr_type (dep_insn) == TYPE_CMP
16456 || get_attr_type (dep_insn) == TYPE_COMPARE
16457 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16458 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16459 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16460 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16461 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16462 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16467 /* Fall out to return default cost. */
16473 /* The function returns a true if INSN is microcoded.
16474 Return false otherwise. */
16477 is_microcoded_insn (rtx insn)
16479 if (!insn || !INSN_P (insn)
16480 || GET_CODE (PATTERN (insn)) == USE
16481 || GET_CODE (PATTERN (insn)) == CLOBBER)
16484 if (rs6000_sched_groups)
16486 enum attr_type type = get_attr_type (insn);
16487 if (type == TYPE_LOAD_EXT_U
16488 || type == TYPE_LOAD_EXT_UX
16489 || type == TYPE_LOAD_UX
16490 || type == TYPE_STORE_UX
16491 || type == TYPE_MFCR)
16498 /* The function returns a nonzero value if INSN can be scheduled only
16499 as the first insn in a dispatch group ("dispatch-slot restricted").
16500 In this case, the returned value indicates how many dispatch slots
16501 the insn occupies (at the beginning of the group).
16502 Return 0 otherwise. */
16505 is_dispatch_slot_restricted (rtx insn)
16507 enum attr_type type;
16509 if (!rs6000_sched_groups)
16513 || insn == NULL_RTX
16514 || GET_CODE (insn) == NOTE
16515 || GET_CODE (PATTERN (insn)) == USE
16516 || GET_CODE (PATTERN (insn)) == CLOBBER)
16519 type = get_attr_type (insn);
16526 case TYPE_DELAYED_CR:
16527 case TYPE_CR_LOGICAL:
16540 if (rs6000_cpu == PROCESSOR_POWER5
16541 && is_cracked_insn (insn))
16547 /* The function returns true if INSN is cracked into 2 instructions
16548 by the processor (and therefore occupies 2 issue slots). */
16551 is_cracked_insn (rtx insn)
16553 if (!insn || !INSN_P (insn)
16554 || GET_CODE (PATTERN (insn)) == USE
16555 || GET_CODE (PATTERN (insn)) == CLOBBER)
16558 if (rs6000_sched_groups)
16560 enum attr_type type = get_attr_type (insn);
16561 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16562 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16563 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16564 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16565 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16566 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16567 || type == TYPE_IDIV || type == TYPE_LDIV
16568 || type == TYPE_INSERT_WORD)
16575 /* The function returns true if INSN can be issued only from
16576 the branch slot. */
16579 is_branch_slot_insn (rtx insn)
16581 if (!insn || !INSN_P (insn)
16582 || GET_CODE (PATTERN (insn)) == USE
16583 || GET_CODE (PATTERN (insn)) == CLOBBER)
16586 if (rs6000_sched_groups)
16588 enum attr_type type = get_attr_type (insn);
16589 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16597 /* A C statement (sans semicolon) to update the integer scheduling
16598 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16599 INSN earlier, reduce the priority to execute INSN later. Do not
16600 define this macro if you do not need to adjust the scheduling
16601 priorities of insns. */
16604 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16606 /* On machines (like the 750) which have asymmetric integer units,
16607 where one integer unit can do multiply and divides and the other
16608 can't, reduce the priority of multiply/divide so it is scheduled
16609 before other integer operations. */
16612 if (! INSN_P (insn))
16615 if (GET_CODE (PATTERN (insn)) == USE)
16618 switch (rs6000_cpu_attr) {
16620 switch (get_attr_type (insn))
16627 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16628 priority, priority);
16629 if (priority >= 0 && priority < 0x01000000)
16636 if (is_dispatch_slot_restricted (insn)
16637 && reload_completed
16638 && current_sched_info->sched_max_insns_priority
16639 && rs6000_sched_restricted_insns_priority)
16642 /* Prioritize insns that can be dispatched only in the first
16644 if (rs6000_sched_restricted_insns_priority == 1)
16645 /* Attach highest priority to insn. This means that in
16646 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16647 precede 'priority' (critical path) considerations. */
16648 return current_sched_info->sched_max_insns_priority;
16649 else if (rs6000_sched_restricted_insns_priority == 2)
16650 /* Increase priority of insn by a minimal amount. This means that in
16651 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16652 considerations precede dispatch-slot restriction considerations. */
16653 return (priority + 1);
16659 /* Return how many instructions the machine can issue per cycle. */
16662 rs6000_issue_rate (void)
16664 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16665 if (!reload_completed)
16668 switch (rs6000_cpu_attr) {
16669 case CPU_RIOS1: /* ? */
16671 case CPU_PPC601: /* ? */
16694 /* Return how many instructions to look ahead for better insn
16698 rs6000_use_sched_lookahead (void)
16700 if (rs6000_cpu_attr == CPU_PPC8540)
16705 /* Determine is PAT refers to memory. */
16708 is_mem_ref (rtx pat)
16714 if (GET_CODE (pat) == MEM)
16717 /* Recursively process the pattern. */
16718 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16720 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16723 ret |= is_mem_ref (XEXP (pat, i));
16724 else if (fmt[i] == 'E')
16725 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16726 ret |= is_mem_ref (XVECEXP (pat, i, j));
16732 /* Determine if PAT is a PATTERN of a load insn. */
16735 is_load_insn1 (rtx pat)
16737 if (!pat || pat == NULL_RTX)
16740 if (GET_CODE (pat) == SET)
16741 return is_mem_ref (SET_SRC (pat));
16743 if (GET_CODE (pat) == PARALLEL)
16747 for (i = 0; i < XVECLEN (pat, 0); i++)
16748 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16755 /* Determine if INSN loads from memory. */
16758 is_load_insn (rtx insn)
16760 if (!insn || !INSN_P (insn))
16763 if (GET_CODE (insn) == CALL_INSN)
16766 return is_load_insn1 (PATTERN (insn));
16769 /* Determine if PAT is a PATTERN of a store insn. */
16772 is_store_insn1 (rtx pat)
16774 if (!pat || pat == NULL_RTX)
16777 if (GET_CODE (pat) == SET)
16778 return is_mem_ref (SET_DEST (pat));
16780 if (GET_CODE (pat) == PARALLEL)
16784 for (i = 0; i < XVECLEN (pat, 0); i++)
16785 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16792 /* Determine if INSN stores to memory. */
16795 is_store_insn (rtx insn)
16797 if (!insn || !INSN_P (insn))
16800 return is_store_insn1 (PATTERN (insn));
16803 /* Returns whether the dependence between INSN and NEXT is considered
16804 costly by the given target. */
16807 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16810 /* If the flag is not enabled - no dependence is considered costly;
16811 allow all dependent insns in the same group.
16812 This is the most aggressive option. */
16813 if (rs6000_sched_costly_dep == no_dep_costly)
16816 /* If the flag is set to 1 - a dependence is always considered costly;
16817 do not allow dependent instructions in the same group.
16818 This is the most conservative option. */
16819 if (rs6000_sched_costly_dep == all_deps_costly)
16822 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16823 && is_load_insn (next)
16824 && is_store_insn (insn))
16825 /* Prevent load after store in the same group. */
16828 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16829 && is_load_insn (next)
16830 && is_store_insn (insn)
16831 && (!link || (int) REG_NOTE_KIND (link) == 0))
16832 /* Prevent load after store in the same group if it is a true
16836 /* The flag is set to X; dependences with latency >= X are considered costly,
16837 and will not be scheduled in the same group. */
16838 if (rs6000_sched_costly_dep <= max_dep_latency
16839 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16845 /* Return the next insn after INSN that is found before TAIL is reached,
16846 skipping any "non-active" insns - insns that will not actually occupy
16847 an issue slot. Return NULL_RTX if such an insn is not found. */
16850 get_next_active_insn (rtx insn, rtx tail)
16852 if (insn == NULL_RTX || insn == tail)
16857 insn = NEXT_INSN (insn);
16858 if (insn == NULL_RTX || insn == tail)
16863 || (NONJUMP_INSN_P (insn)
16864 && GET_CODE (PATTERN (insn)) != USE
16865 && GET_CODE (PATTERN (insn)) != CLOBBER
16866 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16872 /* Return whether the presence of INSN causes a dispatch group termination
16873 of group WHICH_GROUP.
16875 If WHICH_GROUP == current_group, this function will return true if INSN
16876 causes the termination of the current group (i.e, the dispatch group to
16877 which INSN belongs). This means that INSN will be the last insn in the
16878 group it belongs to.
16880 If WHICH_GROUP == previous_group, this function will return true if INSN
16881 causes the termination of the previous group (i.e, the dispatch group that
16882 precedes the group to which INSN belongs). This means that INSN will be
16883 the first insn in the group it belongs to). */
16886 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16888 enum attr_type type;
16893 type = get_attr_type (insn);
16895 if (is_microcoded_insn (insn))
16898 if (which_group == current_group)
16900 if (is_branch_slot_insn (insn))
16904 else if (which_group == previous_group)
16906 if (is_dispatch_slot_restricted (insn))
16914 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16915 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16918 is_costly_group (rtx *group_insns, rtx next_insn)
16923 int issue_rate = rs6000_issue_rate ();
16925 for (i = 0; i < issue_rate; i++)
16927 rtx insn = group_insns[i];
16930 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16932 rtx next = XEXP (link, 0);
16933 if (next == next_insn)
16935 cost = insn_cost (insn, link, next_insn);
16936 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16945 /* Utility of the function redefine_groups.
16946 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16947 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16948 to keep it "far" (in a separate group) from GROUP_INSNS, following
16949 one of the following schemes, depending on the value of the flag
16950 -minsert_sched_nops = X:
16951 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16952 in order to force NEXT_INSN into a separate group.
16953 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16954 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16955 insertion (has a group just ended, how many vacant issue slots remain in the
16956 last group, and how many dispatch groups were encountered so far). */
16959 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16960 rtx next_insn, bool *group_end, int can_issue_more,
16965 int issue_rate = rs6000_issue_rate ();
16966 bool end = *group_end;
16969 if (next_insn == NULL_RTX)
16970 return can_issue_more;
16972 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16973 return can_issue_more;
16975 force = is_costly_group (group_insns, next_insn);
16977 return can_issue_more;
16979 if (sched_verbose > 6)
16980 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16981 *group_count ,can_issue_more);
16983 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16986 can_issue_more = 0;
16988 /* Since only a branch can be issued in the last issue_slot, it is
16989 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16990 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16991 in this case the last nop will start a new group and the branch
16992 will be forced to the new group. */
16993 if (can_issue_more && !is_branch_slot_insn (next_insn))
16996 while (can_issue_more > 0)
16999 emit_insn_before (nop, next_insn);
17007 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
17009 int n_nops = rs6000_sched_insert_nops;
17011 /* Nops can't be issued from the branch slot, so the effective
17012 issue_rate for nops is 'issue_rate - 1'. */
17013 if (can_issue_more == 0)
17014 can_issue_more = issue_rate;
17016 if (can_issue_more == 0)
17018 can_issue_more = issue_rate - 1;
17021 for (i = 0; i < issue_rate; i++)
17023 group_insns[i] = 0;
17030 emit_insn_before (nop, next_insn);
17031 if (can_issue_more == issue_rate - 1) /* new group begins */
17034 if (can_issue_more == 0)
17036 can_issue_more = issue_rate - 1;
17039 for (i = 0; i < issue_rate; i++)
17041 group_insns[i] = 0;
17047 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
17050 /* Is next_insn going to start a new group? */
17053 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17054 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17055 || (can_issue_more < issue_rate &&
17056 insn_terminates_group_p (next_insn, previous_group)));
17057 if (*group_end && end)
17060 if (sched_verbose > 6)
17061 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
17062 *group_count, can_issue_more);
17063 return can_issue_more;
17066 return can_issue_more;
17069 /* This function tries to synch the dispatch groups that the compiler "sees"
17070 with the dispatch groups that the processor dispatcher is expected to
17071 form in practice. It tries to achieve this synchronization by forcing the
17072 estimated processor grouping on the compiler (as opposed to the function
17073 'pad_goups' which tries to force the scheduler's grouping on the processor).
17075 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
17076 examines the (estimated) dispatch groups that will be formed by the processor
17077 dispatcher. It marks these group boundaries to reflect the estimated
17078 processor grouping, overriding the grouping that the scheduler had marked.
17079 Depending on the value of the flag '-minsert-sched-nops' this function can
17080 force certain insns into separate groups or force a certain distance between
17081 them by inserting nops, for example, if there exists a "costly dependence"
17084 The function estimates the group boundaries that the processor will form as
17085 follows: It keeps track of how many vacant issue slots are available after
17086 each insn. A subsequent insn will start a new group if one of the following
17088 - no more vacant issue slots remain in the current dispatch group.
17089 - only the last issue slot, which is the branch slot, is vacant, but the next
17090 insn is not a branch.
17091 - only the last 2 or less issue slots, including the branch slot, are vacant,
17092 which means that a cracked insn (which occupies two issue slots) can't be
17093 issued in this group.
17094 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17095 start a new group. */
17098 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17100 rtx insn, next_insn;
17102 int can_issue_more;
17105 int group_count = 0;
17109 issue_rate = rs6000_issue_rate ();
17110 group_insns = alloca (issue_rate * sizeof (rtx));
17111 for (i = 0; i < issue_rate; i++)
17113 group_insns[i] = 0;
17115 can_issue_more = issue_rate;
17117 insn = get_next_active_insn (prev_head_insn, tail);
17120 while (insn != NULL_RTX)
17122 slot = (issue_rate - can_issue_more);
17123 group_insns[slot] = insn;
17125 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17126 if (insn_terminates_group_p (insn, current_group))
17127 can_issue_more = 0;
17129 next_insn = get_next_active_insn (insn, tail);
17130 if (next_insn == NULL_RTX)
17131 return group_count + 1;
17133 /* Is next_insn going to start a new group? */
17135 = (can_issue_more == 0
17136 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17137 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17138 || (can_issue_more < issue_rate &&
17139 insn_terminates_group_p (next_insn, previous_group)));
17141 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17142 next_insn, &group_end, can_issue_more,
17148 can_issue_more = 0;
17149 for (i = 0; i < issue_rate; i++)
17151 group_insns[i] = 0;
17155 if (GET_MODE (next_insn) == TImode && can_issue_more)
17156 PUT_MODE (next_insn, VOIDmode);
17157 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17158 PUT_MODE (next_insn, TImode);
17161 if (can_issue_more == 0)
17162 can_issue_more = issue_rate;
17165 return group_count;
17168 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17169 dispatch group boundaries that the scheduler had marked. Pad with nops
17170 any dispatch groups which have vacant issue slots, in order to force the
17171 scheduler's grouping on the processor dispatcher. The function
17172 returns the number of dispatch groups found. */
17175 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17177 rtx insn, next_insn;
17180 int can_issue_more;
17182 int group_count = 0;
17184 /* Initialize issue_rate. */
17185 issue_rate = rs6000_issue_rate ();
17186 can_issue_more = issue_rate;
17188 insn = get_next_active_insn (prev_head_insn, tail);
17189 next_insn = get_next_active_insn (insn, tail);
17191 while (insn != NULL_RTX)
17194 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17196 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17198 if (next_insn == NULL_RTX)
17203 /* If the scheduler had marked group termination at this location
17204 (between insn and next_indn), and neither insn nor next_insn will
17205 force group termination, pad the group with nops to force group
17208 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17209 && !insn_terminates_group_p (insn, current_group)
17210 && !insn_terminates_group_p (next_insn, previous_group))
17212 if (!is_branch_slot_insn (next_insn))
17215 while (can_issue_more)
17218 emit_insn_before (nop, next_insn);
17223 can_issue_more = issue_rate;
17228 next_insn = get_next_active_insn (insn, tail);
17231 return group_count;
17234 /* The following function is called at the end of scheduling BB.
17235 After reload, it inserts nops at insn group bundling. */
17238 rs6000_sched_finish (FILE *dump, int sched_verbose)
17243 fprintf (dump, "=== Finishing schedule.\n");
17245 if (reload_completed && rs6000_sched_groups)
17247 if (rs6000_sched_insert_nops == sched_finish_none)
17250 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17251 n_groups = pad_groups (dump, sched_verbose,
17252 current_sched_info->prev_head,
17253 current_sched_info->next_tail);
17255 n_groups = redefine_groups (dump, sched_verbose,
17256 current_sched_info->prev_head,
17257 current_sched_info->next_tail);
17259 if (sched_verbose >= 6)
17261 fprintf (dump, "ngroups = %d\n", n_groups);
17262 print_rtl (dump, current_sched_info->prev_head);
17263 fprintf (dump, "Done finish_sched\n");
17268 /* Length in units of the trampoline for entering a nested function. */
17271 rs6000_trampoline_size (void)
17275 switch (DEFAULT_ABI)
17278 gcc_unreachable ();
17281 ret = (TARGET_32BIT) ? 12 : 24;
17286 ret = (TARGET_32BIT) ? 40 : 48;
17293 /* Emit RTL insns to initialize the variable parts of a trampoline.
17294 FNADDR is an RTX for the address of the function's pure code.
17295 CXT is an RTX for the static chain value for the function. */
17298 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17300 enum machine_mode pmode = Pmode;
17301 int regsize = (TARGET_32BIT) ? 4 : 8;
17302 rtx ctx_reg = force_reg (pmode, cxt);
17304 switch (DEFAULT_ABI)
17307 gcc_unreachable ();
17309 /* Macros to shorten the code expansions below. */
17310 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17311 #define MEM_PLUS(addr,offset) \
17312 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17314 /* Under AIX, just build the 3 word function descriptor */
17317 rtx fn_reg = gen_reg_rtx (pmode);
17318 rtx toc_reg = gen_reg_rtx (pmode);
17319 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17320 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17321 emit_move_insn (MEM_DEREF (addr), fn_reg);
17322 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17323 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17327 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17330 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17331 FALSE, VOIDmode, 4,
17333 GEN_INT (rs6000_trampoline_size ()), SImode,
17343 /* Table of valid machine attributes. */
17345 const struct attribute_spec rs6000_attribute_table[] =
17347 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17348 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17349 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17350 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17351 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17352 SUBTARGET_ATTRIBUTE_TABLE,
17354 { NULL, 0, 0, false, false, false, NULL }
17357 /* Handle the "altivec" attribute. The attribute may have
17358 arguments as follows:
17360 __attribute__((altivec(vector__)))
17361 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17362 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17364 and may appear more than once (e.g., 'vector bool char') in a
17365 given declaration. */
17368 rs6000_handle_altivec_attribute (tree *node,
17369 tree name ATTRIBUTE_UNUSED,
17371 int flags ATTRIBUTE_UNUSED,
17372 bool *no_add_attrs)
17374 tree type = *node, result = NULL_TREE;
17375 enum machine_mode mode;
17378 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17379 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17380 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17383 while (POINTER_TYPE_P (type)
17384 || TREE_CODE (type) == FUNCTION_TYPE
17385 || TREE_CODE (type) == METHOD_TYPE
17386 || TREE_CODE (type) == ARRAY_TYPE)
17387 type = TREE_TYPE (type);
17389 mode = TYPE_MODE (type);
17391 /* Check for invalid AltiVec type qualifiers. */
17392 if (type == long_unsigned_type_node || type == long_integer_type_node)
17395 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17396 else if (rs6000_warn_altivec_long)
17397 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17399 else if (type == long_long_unsigned_type_node
17400 || type == long_long_integer_type_node)
17401 error ("use of %<long long%> in AltiVec types is invalid");
17402 else if (type == double_type_node)
17403 error ("use of %<double%> in AltiVec types is invalid");
17404 else if (type == long_double_type_node)
17405 error ("use of %<long double%> in AltiVec types is invalid");
17406 else if (type == boolean_type_node)
17407 error ("use of boolean types in AltiVec types is invalid");
17408 else if (TREE_CODE (type) == COMPLEX_TYPE)
17409 error ("use of %<complex%> in AltiVec types is invalid");
17410 else if (DECIMAL_FLOAT_MODE_P (mode))
17411 error ("use of decimal floating point types in AltiVec types is invalid");
17413 switch (altivec_type)
17416 unsigned_p = TYPE_UNSIGNED (type);
17420 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17423 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17426 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17428 case SFmode: result = V4SF_type_node; break;
17429 /* If the user says 'vector int bool', we may be handed the 'bool'
17430 attribute _before_ the 'vector' attribute, and so select the
17431 proper type in the 'b' case below. */
17432 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17440 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17441 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17442 case QImode: case V16QImode: result = bool_V16QI_type_node;
17449 case V8HImode: result = pixel_V8HI_type_node;
17455 if (result && result != type && TYPE_READONLY (type))
17456 result = build_qualified_type (result, TYPE_QUAL_CONST);
17458 *no_add_attrs = true; /* No need to hang on to the attribute. */
17461 *node = reconstruct_complex_type (*node, result);
17466 /* AltiVec defines four built-in scalar types that serve as vector
17467 elements; we must teach the compiler how to mangle them. */
17469 static const char *
17470 rs6000_mangle_fundamental_type (tree type)
17472 if (type == bool_char_type_node) return "U6__boolc";
17473 if (type == bool_short_type_node) return "U6__bools";
17474 if (type == pixel_type_node) return "u7__pixel";
17475 if (type == bool_int_type_node) return "U6__booli";
17477 /* Mangle IBM extended float long double as `g' (__float128) on
17478 powerpc*-linux where long-double-64 previously was the default. */
17479 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
17481 && TARGET_LONG_DOUBLE_128
17482 && !TARGET_IEEEQUAD)
17485 /* For all other types, use normal C++ mangling. */
17489 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17490 struct attribute_spec.handler. */
17493 rs6000_handle_longcall_attribute (tree *node, tree name,
17494 tree args ATTRIBUTE_UNUSED,
17495 int flags ATTRIBUTE_UNUSED,
17496 bool *no_add_attrs)
17498 if (TREE_CODE (*node) != FUNCTION_TYPE
17499 && TREE_CODE (*node) != FIELD_DECL
17500 && TREE_CODE (*node) != TYPE_DECL)
17502 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17503 IDENTIFIER_POINTER (name));
17504 *no_add_attrs = true;
17510 /* Set longcall attributes on all functions declared when
17511 rs6000_default_long_calls is true. */
17513 rs6000_set_default_type_attributes (tree type)
17515 if (rs6000_default_long_calls
17516 && (TREE_CODE (type) == FUNCTION_TYPE
17517 || TREE_CODE (type) == METHOD_TYPE))
17518 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17520 TYPE_ATTRIBUTES (type));
17523 /* Return a reference suitable for calling a function with the
17524 longcall attribute. */
17527 rs6000_longcall_ref (rtx call_ref)
17529 const char *call_name;
17532 if (GET_CODE (call_ref) != SYMBOL_REF)
17535 /* System V adds '.' to the internal name, so skip them. */
17536 call_name = XSTR (call_ref, 0);
17537 if (*call_name == '.')
17539 while (*call_name == '.')
17542 node = get_identifier (call_name);
17543 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17546 return force_reg (Pmode, call_ref);
17549 #ifdef USING_ELFOS_H
17551 /* A get_unnamed_section callback, used for switching to toc_section. */
17554 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17556 if (DEFAULT_ABI == ABI_AIX
17557 && TARGET_MINIMAL_TOC
17558 && !TARGET_RELOCATABLE)
17560 if (!toc_initialized)
17562 toc_initialized = 1;
17563 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17564 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17565 fprintf (asm_out_file, "\t.tc ");
17566 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17567 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17568 fprintf (asm_out_file, "\n");
17570 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17571 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17572 fprintf (asm_out_file, " = .+32768\n");
17575 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17577 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17578 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17581 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17582 if (!toc_initialized)
17584 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17585 fprintf (asm_out_file, " = .+32768\n");
17586 toc_initialized = 1;
17591 /* Implement TARGET_ASM_INIT_SECTIONS. */
17594 rs6000_elf_asm_init_sections (void)
17597 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17600 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17601 SDATA2_SECTION_ASM_OP);
17604 /* Implement TARGET_SELECT_RTX_SECTION. */
17607 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17608 unsigned HOST_WIDE_INT align)
17610 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17611 return toc_section;
17613 return default_elf_select_rtx_section (mode, x, align);
17616 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17619 rs6000_elf_select_section (tree decl, int reloc,
17620 unsigned HOST_WIDE_INT align)
17622 /* Pretend that we're always building for a shared library when
17623 ABI_AIX, because otherwise we end up with dynamic relocations
17624 in read-only sections. This happens for function pointers,
17625 references to vtables in typeinfo, and probably other cases. */
17626 return default_elf_select_section_1 (decl, reloc, align,
17627 flag_pic || DEFAULT_ABI == ABI_AIX);
17630 /* A C statement to build up a unique section name, expressed as a
17631 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17632 RELOC indicates whether the initial value of EXP requires
17633 link-time relocations. If you do not define this macro, GCC will use
17634 the symbol name prefixed by `.' as the section name. Note - this
17635 macro can now be called for uninitialized data items as well as
17636 initialized data and functions. */
17639 rs6000_elf_unique_section (tree decl, int reloc)
17641 /* As above, pretend that we're always building for a shared library
17642 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17643 default_unique_section_1 (decl, reloc,
17644 flag_pic || DEFAULT_ABI == ABI_AIX);
17647 /* For a SYMBOL_REF, set generic flags and then perform some
17648 target-specific processing.
17650 When the AIX ABI is requested on a non-AIX system, replace the
17651 function name with the real name (with a leading .) rather than the
17652 function descriptor name. This saves a lot of overriding code to
17653 read the prefixes. */
17656 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17658 default_encode_section_info (decl, rtl, first);
17661 && TREE_CODE (decl) == FUNCTION_DECL
17663 && DEFAULT_ABI == ABI_AIX)
17665 rtx sym_ref = XEXP (rtl, 0);
17666 size_t len = strlen (XSTR (sym_ref, 0));
17667 char *str = alloca (len + 2);
17669 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17670 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17675 rs6000_elf_in_small_data_p (tree decl)
17677 if (rs6000_sdata == SDATA_NONE)
17680 /* We want to merge strings, so we never consider them small data. */
17681 if (TREE_CODE (decl) == STRING_CST)
17684 /* Functions are never in the small data area. */
17685 if (TREE_CODE (decl) == FUNCTION_DECL)
17688 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17690 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17691 if (strcmp (section, ".sdata") == 0
17692 || strcmp (section, ".sdata2") == 0
17693 || strcmp (section, ".sbss") == 0
17694 || strcmp (section, ".sbss2") == 0
17695 || strcmp (section, ".PPC.EMB.sdata0") == 0
17696 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17701 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17704 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17705 /* If it's not public, and we're not going to reference it there,
17706 there's no need to put it in the small data section. */
17707 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17714 #endif /* USING_ELFOS_H */
17716 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
17719 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
17721 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
17724 /* Return a REG that occurs in ADDR with coefficient 1.
17725 ADDR can be effectively incremented by incrementing REG.
17727 r0 is special and we must not select it as an address
17728 register by this routine since our caller will try to
17729 increment the returned register via an "la" instruction. */
17732 find_addr_reg (rtx addr)
17734 while (GET_CODE (addr) == PLUS)
17736 if (GET_CODE (XEXP (addr, 0)) == REG
17737 && REGNO (XEXP (addr, 0)) != 0)
17738 addr = XEXP (addr, 0);
17739 else if (GET_CODE (XEXP (addr, 1)) == REG
17740 && REGNO (XEXP (addr, 1)) != 0)
17741 addr = XEXP (addr, 1);
17742 else if (CONSTANT_P (XEXP (addr, 0)))
17743 addr = XEXP (addr, 1);
17744 else if (CONSTANT_P (XEXP (addr, 1)))
17745 addr = XEXP (addr, 0);
17747 gcc_unreachable ();
17749 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17754 rs6000_fatal_bad_address (rtx op)
17756 fatal_insn ("bad address", op);
17761 static tree branch_island_list = 0;
17763 /* Remember to generate a branch island for far calls to the given
17767 add_compiler_branch_island (tree label_name, tree function_name,
17770 tree branch_island = build_tree_list (function_name, label_name);
17771 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17772 TREE_CHAIN (branch_island) = branch_island_list;
17773 branch_island_list = branch_island;
17776 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17777 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17778 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17779 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17781 /* Generate far-jump branch islands for everything on the
17782 branch_island_list. Invoked immediately after the last instruction
17783 of the epilogue has been emitted; the branch-islands must be
17784 appended to, and contiguous with, the function body. Mach-O stubs
17785 are generated in machopic_output_stub(). */
17788 macho_branch_islands (void)
17791 tree branch_island;
17793 for (branch_island = branch_island_list;
17795 branch_island = TREE_CHAIN (branch_island))
17797 const char *label =
17798 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17800 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17801 char name_buf[512];
17802 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17803 if (name[0] == '*' || name[0] == '&')
17804 strcpy (name_buf, name+1);
17808 strcpy (name_buf+1, name);
17810 strcpy (tmp_buf, "\n");
17811 strcat (tmp_buf, label);
17812 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17813 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17814 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17815 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17818 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17819 strcat (tmp_buf, label);
17820 strcat (tmp_buf, "_pic\n");
17821 strcat (tmp_buf, label);
17822 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17824 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17825 strcat (tmp_buf, name_buf);
17826 strcat (tmp_buf, " - ");
17827 strcat (tmp_buf, label);
17828 strcat (tmp_buf, "_pic)\n");
17830 strcat (tmp_buf, "\tmtlr r0\n");
17832 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17833 strcat (tmp_buf, name_buf);
17834 strcat (tmp_buf, " - ");
17835 strcat (tmp_buf, label);
17836 strcat (tmp_buf, "_pic)\n");
17838 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17842 strcat (tmp_buf, ":\nlis r12,hi16(");
17843 strcat (tmp_buf, name_buf);
17844 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17845 strcat (tmp_buf, name_buf);
17846 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17848 output_asm_insn (tmp_buf, 0);
17849 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17850 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17851 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17852 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17855 branch_island_list = 0;
17858 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17859 already there or not. */
17862 no_previous_def (tree function_name)
17864 tree branch_island;
17865 for (branch_island = branch_island_list;
17867 branch_island = TREE_CHAIN (branch_island))
17868 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17873 /* GET_PREV_LABEL gets the label name from the previous definition of
17877 get_prev_label (tree function_name)
17879 tree branch_island;
17880 for (branch_island = branch_island_list;
17882 branch_island = TREE_CHAIN (branch_island))
17883 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17884 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17888 /* INSN is either a function call or a millicode call. It may have an
17889 unconditional jump in its delay slot.
17891 CALL_DEST is the routine we are calling. */
17894 output_call (rtx insn, rtx *operands, int dest_operand_number,
17895 int cookie_operand_number)
17897 static char buf[256];
17898 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17899 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17902 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17904 if (no_previous_def (funname))
17906 int line_number = 0;
17907 rtx label_rtx = gen_label_rtx ();
17908 char *label_buf, temp_buf[256];
17909 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17910 CODE_LABEL_NUMBER (label_rtx));
17911 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17912 labelname = get_identifier (label_buf);
17913 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17915 line_number = NOTE_LINE_NUMBER (insn);
17916 add_compiler_branch_island (labelname, funname, line_number);
17919 labelname = get_prev_label (funname);
17921 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17922 instruction will reach 'foo', otherwise link as 'bl L42'".
17923 "L42" should be a 'branch island', that will do a far jump to
17924 'foo'. Branch islands are generated in
17925 macho_branch_islands(). */
17926 sprintf (buf, "jbsr %%z%d,%.246s",
17927 dest_operand_number, IDENTIFIER_POINTER (labelname));
17930 sprintf (buf, "bl %%z%d", dest_operand_number);
17934 /* Generate PIC and indirect symbol stubs. */
17937 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17939 unsigned int length;
17940 char *symbol_name, *lazy_ptr_name;
17941 char *local_label_0;
17942 static int label = 0;
17944 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17945 symb = (*targetm.strip_name_encoding) (symb);
17948 length = strlen (symb);
17949 symbol_name = alloca (length + 32);
17950 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17952 lazy_ptr_name = alloca (length + 32);
17953 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17956 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
17958 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
17962 fprintf (file, "\t.align 5\n");
17964 fprintf (file, "%s:\n", stub);
17965 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17968 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17969 sprintf (local_label_0, "\"L%011d$spb\"", label);
17971 fprintf (file, "\tmflr r0\n");
17972 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17973 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17974 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17975 lazy_ptr_name, local_label_0);
17976 fprintf (file, "\tmtlr r0\n");
17977 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17978 (TARGET_64BIT ? "ldu" : "lwzu"),
17979 lazy_ptr_name, local_label_0);
17980 fprintf (file, "\tmtctr r12\n");
17981 fprintf (file, "\tbctr\n");
17985 fprintf (file, "\t.align 4\n");
17987 fprintf (file, "%s:\n", stub);
17988 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17990 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17991 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17992 (TARGET_64BIT ? "ldu" : "lwzu"),
17994 fprintf (file, "\tmtctr r12\n");
17995 fprintf (file, "\tbctr\n");
17998 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
17999 fprintf (file, "%s:\n", lazy_ptr_name);
18000 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18001 fprintf (file, "%sdyld_stub_binding_helper\n",
18002 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
18005 /* Legitimize PIC addresses. If the address is already
18006 position-independent, we return ORIG. Newly generated
18007 position-independent addresses go into a reg. This is REG if non
18008 zero, otherwise we allocate register(s) as necessary. */
18010 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
18013 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
18018 if (reg == NULL && ! reload_in_progress && ! reload_completed)
18019 reg = gen_reg_rtx (Pmode);
18021 if (GET_CODE (orig) == CONST)
18025 if (GET_CODE (XEXP (orig, 0)) == PLUS
18026 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
18029 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
18031 /* Use a different reg for the intermediate value, as
18032 it will be marked UNCHANGING. */
18033 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
18034 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
18037 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
18040 if (GET_CODE (offset) == CONST_INT)
18042 if (SMALL_INT (offset))
18043 return plus_constant (base, INTVAL (offset));
18044 else if (! reload_in_progress && ! reload_completed)
18045 offset = force_reg (Pmode, offset);
18048 rtx mem = force_const_mem (Pmode, orig);
18049 return machopic_legitimize_pic_address (mem, Pmode, reg);
18052 return gen_rtx_PLUS (Pmode, base, offset);
18055 /* Fall back on generic machopic code. */
18056 return machopic_legitimize_pic_address (orig, mode, reg);
18059 /* Output a .machine directive for the Darwin assembler, and call
18060 the generic start_file routine. */
18063 rs6000_darwin_file_start (void)
18065 static const struct
18071 { "ppc64", "ppc64", MASK_64BIT },
18072 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
18073 { "power4", "ppc970", 0 },
18074 { "G5", "ppc970", 0 },
18075 { "7450", "ppc7450", 0 },
18076 { "7400", "ppc7400", MASK_ALTIVEC },
18077 { "G4", "ppc7400", 0 },
18078 { "750", "ppc750", 0 },
18079 { "740", "ppc750", 0 },
18080 { "G3", "ppc750", 0 },
18081 { "604e", "ppc604e", 0 },
18082 { "604", "ppc604", 0 },
18083 { "603e", "ppc603", 0 },
18084 { "603", "ppc603", 0 },
18085 { "601", "ppc601", 0 },
18086 { NULL, "ppc", 0 } };
18087 const char *cpu_id = "";
18090 rs6000_file_start ();
18091 darwin_file_start ();
18093 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
18094 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
18095 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
18096 && rs6000_select[i].string[0] != '\0')
18097 cpu_id = rs6000_select[i].string;
18099 /* Look through the mapping array. Pick the first name that either
18100 matches the argument, has a bit set in IF_SET that is also set
18101 in the target flags, or has a NULL name. */
18104 while (mapping[i].arg != NULL
18105 && strcmp (mapping[i].arg, cpu_id) != 0
18106 && (mapping[i].if_set & target_flags) == 0)
18109 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18112 #endif /* TARGET_MACHO */
18115 static unsigned int
18116 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
18118 return default_section_type_flags_1 (decl, name, reloc,
18119 flag_pic || DEFAULT_ABI == ABI_AIX);
18122 /* Record an element in the table of global constructors. SYMBOL is
18123 a SYMBOL_REF of the function to be called; PRIORITY is a number
18124 between 0 and MAX_INIT_PRIORITY.
18126 This differs from default_named_section_asm_out_constructor in
18127 that we have special handling for -mrelocatable. */
18130 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18132 const char *section = ".ctors";
18135 if (priority != DEFAULT_INIT_PRIORITY)
18137 sprintf (buf, ".ctors.%.5u",
18138 /* Invert the numbering so the linker puts us in the proper
18139 order; constructors are run from right to left, and the
18140 linker sorts in increasing order. */
18141 MAX_INIT_PRIORITY - priority);
18145 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18146 assemble_align (POINTER_SIZE);
18148 if (TARGET_RELOCATABLE)
18150 fputs ("\t.long (", asm_out_file);
18151 output_addr_const (asm_out_file, symbol);
18152 fputs (")@fixup\n", asm_out_file);
18155 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18159 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18161 const char *section = ".dtors";
18164 if (priority != DEFAULT_INIT_PRIORITY)
18166 sprintf (buf, ".dtors.%.5u",
18167 /* Invert the numbering so the linker puts us in the proper
18168 order; constructors are run from right to left, and the
18169 linker sorts in increasing order. */
18170 MAX_INIT_PRIORITY - priority);
18174 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18175 assemble_align (POINTER_SIZE);
18177 if (TARGET_RELOCATABLE)
18179 fputs ("\t.long (", asm_out_file);
18180 output_addr_const (asm_out_file, symbol);
18181 fputs (")@fixup\n", asm_out_file);
18184 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18188 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18192 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18193 ASM_OUTPUT_LABEL (file, name);
18194 fputs (DOUBLE_INT_ASM_OP, file);
18195 rs6000_output_function_entry (file, name);
18196 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18199 fputs ("\t.size\t", file);
18200 assemble_name (file, name);
18201 fputs (",24\n\t.type\t.", file);
18202 assemble_name (file, name);
18203 fputs (",@function\n", file);
18204 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18206 fputs ("\t.globl\t.", file);
18207 assemble_name (file, name);
18212 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18213 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18214 rs6000_output_function_entry (file, name);
18215 fputs (":\n", file);
18219 if (TARGET_RELOCATABLE
18220 && !TARGET_SECURE_PLT
18221 && (get_pool_size () != 0 || current_function_profile)
18226 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18228 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18229 fprintf (file, "\t.long ");
18230 assemble_name (file, buf);
18232 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18233 assemble_name (file, buf);
18237 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18238 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18240 if (DEFAULT_ABI == ABI_AIX)
18242 const char *desc_name, *orig_name;
18244 orig_name = (*targetm.strip_name_encoding) (name);
18245 desc_name = orig_name;
18246 while (*desc_name == '.')
18249 if (TREE_PUBLIC (decl))
18250 fprintf (file, "\t.globl %s\n", desc_name);
18252 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18253 fprintf (file, "%s:\n", desc_name);
18254 fprintf (file, "\t.long %s\n", orig_name);
18255 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18256 if (DEFAULT_ABI == ABI_AIX)
18257 fputs ("\t.long 0\n", file);
18258 fprintf (file, "\t.previous\n");
18260 ASM_OUTPUT_LABEL (file, name);
18264 rs6000_elf_end_indicate_exec_stack (void)
18267 file_end_indicate_exec_stack ();
18273 rs6000_xcoff_asm_output_anchor (rtx symbol)
18277 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
18278 SYMBOL_REF_BLOCK_OFFSET (symbol));
18279 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
18283 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18285 fputs (GLOBAL_ASM_OP, stream);
18286 RS6000_OUTPUT_BASENAME (stream, name);
18287 putc ('\n', stream);
18290 /* A get_unnamed_decl callback, used for read-only sections. PTR
18291 points to the section string variable. */
18294 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18296 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18297 *(const char *const *) directive);
18300 /* Likewise for read-write sections. */
18303 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18305 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18306 *(const char *const *) directive);
18309 /* A get_unnamed_section callback, used for switching to toc_section. */
18312 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18314 if (TARGET_MINIMAL_TOC)
18316 /* toc_section is always selected at least once from
18317 rs6000_xcoff_file_start, so this is guaranteed to
18318 always be defined once and only once in each file. */
18319 if (!toc_initialized)
18321 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18322 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18323 toc_initialized = 1;
18325 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18326 (TARGET_32BIT ? "" : ",3"));
18329 fputs ("\t.toc\n", asm_out_file);
18332 /* Implement TARGET_ASM_INIT_SECTIONS. */
18335 rs6000_xcoff_asm_init_sections (void)
18337 read_only_data_section
18338 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18339 &xcoff_read_only_section_name);
18341 private_data_section
18342 = get_unnamed_section (SECTION_WRITE,
18343 rs6000_xcoff_output_readwrite_section_asm_op,
18344 &xcoff_private_data_section_name);
18346 read_only_private_data_section
18347 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18348 &xcoff_private_data_section_name);
18351 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18353 readonly_data_section = read_only_data_section;
18354 exception_section = data_section;
18358 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18359 tree decl ATTRIBUTE_UNUSED)
18362 static const char * const suffix[3] = { "PR", "RO", "RW" };
18364 if (flags & SECTION_CODE)
18366 else if (flags & SECTION_WRITE)
18371 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18372 (flags & SECTION_CODE) ? "." : "",
18373 name, suffix[smclass], flags & SECTION_ENTSIZE);
18377 rs6000_xcoff_select_section (tree decl, int reloc,
18378 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18380 if (decl_readonly_section_1 (decl, reloc, 1))
18382 if (TREE_PUBLIC (decl))
18383 return read_only_data_section;
18385 return read_only_private_data_section;
18389 if (TREE_PUBLIC (decl))
18390 return data_section;
18392 return private_data_section;
18397 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18401 /* Use select_section for private and uninitialized data. */
18402 if (!TREE_PUBLIC (decl)
18403 || DECL_COMMON (decl)
18404 || DECL_INITIAL (decl) == NULL_TREE
18405 || DECL_INITIAL (decl) == error_mark_node
18406 || (flag_zero_initialized_in_bss
18407 && initializer_zerop (DECL_INITIAL (decl))))
18410 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18411 name = (*targetm.strip_name_encoding) (name);
18412 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18415 /* Select section for constant in constant pool.
18417 On RS/6000, all constants are in the private read-only data area.
18418 However, if this is being placed in the TOC it must be output as a
18422 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18423 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18425 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18426 return toc_section;
18428 return read_only_private_data_section;
18431 /* Remove any trailing [DS] or the like from the symbol name. */
18433 static const char *
18434 rs6000_xcoff_strip_name_encoding (const char *name)
18439 len = strlen (name);
18440 if (name[len - 1] == ']')
18441 return ggc_alloc_string (name, len - 4);
18446 /* Section attributes. AIX is always PIC. */
18448 static unsigned int
18449 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18451 unsigned int align;
18452 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18454 /* Align to at least UNIT size. */
18455 if (flags & SECTION_CODE)
18456 align = MIN_UNITS_PER_WORD;
18458 /* Increase alignment of large objects if not already stricter. */
18459 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18460 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18461 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18463 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18466 /* Output at beginning of assembler file.
18468 Initialize the section names for the RS/6000 at this point.
18470 Specify filename, including full path, to assembler.
18472 We want to go into the TOC section so at least one .toc will be emitted.
18473 Also, in order to output proper .bs/.es pairs, we need at least one static
18474 [RW] section emitted.
18476 Finally, declare mcount when profiling to make the assembler happy. */
18479 rs6000_xcoff_file_start (void)
18481 rs6000_gen_section_name (&xcoff_bss_section_name,
18482 main_input_filename, ".bss_");
18483 rs6000_gen_section_name (&xcoff_private_data_section_name,
18484 main_input_filename, ".rw_");
18485 rs6000_gen_section_name (&xcoff_read_only_section_name,
18486 main_input_filename, ".ro_");
18488 fputs ("\t.file\t", asm_out_file);
18489 output_quoted_string (asm_out_file, main_input_filename);
18490 fputc ('\n', asm_out_file);
18491 if (write_symbols != NO_DEBUG)
18492 switch_to_section (private_data_section);
18493 switch_to_section (text_section);
18495 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18496 rs6000_file_start ();
18499 /* Output at end of assembler file.
18500 On the RS/6000, referencing data should automatically pull in text. */
18503 rs6000_xcoff_file_end (void)
18505 switch_to_section (text_section);
18506 fputs ("_section_.text:\n", asm_out_file);
18507 switch_to_section (data_section);
18508 fputs (TARGET_32BIT
18509 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18512 #endif /* TARGET_XCOFF */
18514 /* Compute a (partial) cost for rtx X. Return true if the complete
18515 cost has been computed, and false if subexpressions should be
18516 scanned. In either case, *TOTAL contains the cost result. */
18519 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18521 enum machine_mode mode = GET_MODE (x);
18525 /* On the RS/6000, if it is valid in the insn, it is free. */
18527 if (((outer_code == SET
18528 || outer_code == PLUS
18529 || outer_code == MINUS)
18530 && (satisfies_constraint_I (x)
18531 || satisfies_constraint_L (x)))
18532 || (outer_code == AND
18533 && (satisfies_constraint_K (x)
18535 ? satisfies_constraint_L (x)
18536 : satisfies_constraint_J (x))
18537 || mask_operand (x, mode)
18539 && mask64_operand (x, DImode))))
18540 || ((outer_code == IOR || outer_code == XOR)
18541 && (satisfies_constraint_K (x)
18543 ? satisfies_constraint_L (x)
18544 : satisfies_constraint_J (x))))
18545 || outer_code == ASHIFT
18546 || outer_code == ASHIFTRT
18547 || outer_code == LSHIFTRT
18548 || outer_code == ROTATE
18549 || outer_code == ROTATERT
18550 || outer_code == ZERO_EXTRACT
18551 || (outer_code == MULT
18552 && satisfies_constraint_I (x))
18553 || ((outer_code == DIV || outer_code == UDIV
18554 || outer_code == MOD || outer_code == UMOD)
18555 && exact_log2 (INTVAL (x)) >= 0)
18556 || (outer_code == COMPARE
18557 && (satisfies_constraint_I (x)
18558 || satisfies_constraint_K (x)))
18559 || (outer_code == EQ
18560 && (satisfies_constraint_I (x)
18561 || satisfies_constraint_K (x)
18563 ? satisfies_constraint_L (x)
18564 : satisfies_constraint_J (x))))
18565 || (outer_code == GTU
18566 && satisfies_constraint_I (x))
18567 || (outer_code == LTU
18568 && satisfies_constraint_P (x)))
18573 else if ((outer_code == PLUS
18574 && reg_or_add_cint_operand (x, VOIDmode))
18575 || (outer_code == MINUS
18576 && reg_or_sub_cint_operand (x, VOIDmode))
18577 || ((outer_code == SET
18578 || outer_code == IOR
18579 || outer_code == XOR)
18581 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18583 *total = COSTS_N_INSNS (1);
18590 && ((outer_code == AND
18591 && (satisfies_constraint_K (x)
18592 || satisfies_constraint_L (x)
18593 || mask_operand (x, DImode)
18594 || mask64_operand (x, DImode)))
18595 || ((outer_code == IOR || outer_code == XOR)
18596 && CONST_DOUBLE_HIGH (x) == 0
18597 && (CONST_DOUBLE_LOW (x)
18598 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18603 else if (mode == DImode
18604 && (outer_code == SET
18605 || outer_code == IOR
18606 || outer_code == XOR)
18607 && CONST_DOUBLE_HIGH (x) == 0)
18609 *total = COSTS_N_INSNS (1);
18618 /* When optimizing for size, MEM should be slightly more expensive
18619 than generating address, e.g., (plus (reg) (const)).
18620 L1 cache latency is about two instructions. */
18621 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18629 if (mode == DFmode)
18631 if (GET_CODE (XEXP (x, 0)) == MULT)
18633 /* FNMA accounted in outer NEG. */
18634 if (outer_code == NEG)
18635 *total = rs6000_cost->dmul - rs6000_cost->fp;
18637 *total = rs6000_cost->dmul;
18640 *total = rs6000_cost->fp;
18642 else if (mode == SFmode)
18644 /* FNMA accounted in outer NEG. */
18645 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18648 *total = rs6000_cost->fp;
18651 *total = COSTS_N_INSNS (1);
18655 if (mode == DFmode)
18657 if (GET_CODE (XEXP (x, 0)) == MULT)
18659 /* FNMA accounted in outer NEG. */
18660 if (outer_code == NEG)
18663 *total = rs6000_cost->dmul;
18666 *total = rs6000_cost->fp;
18668 else if (mode == SFmode)
18670 /* FNMA accounted in outer NEG. */
18671 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18674 *total = rs6000_cost->fp;
18677 *total = COSTS_N_INSNS (1);
18681 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18682 && satisfies_constraint_I (XEXP (x, 1)))
18684 if (INTVAL (XEXP (x, 1)) >= -256
18685 && INTVAL (XEXP (x, 1)) <= 255)
18686 *total = rs6000_cost->mulsi_const9;
18688 *total = rs6000_cost->mulsi_const;
18690 /* FMA accounted in outer PLUS/MINUS. */
18691 else if ((mode == DFmode || mode == SFmode)
18692 && (outer_code == PLUS || outer_code == MINUS))
18694 else if (mode == DFmode)
18695 *total = rs6000_cost->dmul;
18696 else if (mode == SFmode)
18697 *total = rs6000_cost->fp;
18698 else if (mode == DImode)
18699 *total = rs6000_cost->muldi;
18701 *total = rs6000_cost->mulsi;
18706 if (FLOAT_MODE_P (mode))
18708 *total = mode == DFmode ? rs6000_cost->ddiv
18709 : rs6000_cost->sdiv;
18716 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18717 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18719 if (code == DIV || code == MOD)
18721 *total = COSTS_N_INSNS (2);
18724 *total = COSTS_N_INSNS (1);
18728 if (GET_MODE (XEXP (x, 1)) == DImode)
18729 *total = rs6000_cost->divdi;
18731 *total = rs6000_cost->divsi;
18733 /* Add in shift and subtract for MOD. */
18734 if (code == MOD || code == UMOD)
18735 *total += COSTS_N_INSNS (2);
18739 *total = COSTS_N_INSNS (4);
18743 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18754 *total = COSTS_N_INSNS (1);
18762 /* Handle mul_highpart. */
18763 if (outer_code == TRUNCATE
18764 && GET_CODE (XEXP (x, 0)) == MULT)
18766 if (mode == DImode)
18767 *total = rs6000_cost->muldi;
18769 *total = rs6000_cost->mulsi;
18772 else if (outer_code == AND)
18775 *total = COSTS_N_INSNS (1);
18780 if (GET_CODE (XEXP (x, 0)) == MEM)
18783 *total = COSTS_N_INSNS (1);
18789 if (!FLOAT_MODE_P (mode))
18791 *total = COSTS_N_INSNS (1);
18797 case UNSIGNED_FLOAT:
18800 case FLOAT_TRUNCATE:
18801 *total = rs6000_cost->fp;
18805 if (mode == DFmode)
18808 *total = rs6000_cost->fp;
18812 switch (XINT (x, 1))
18815 *total = rs6000_cost->fp;
18827 *total = COSTS_N_INSNS (1);
18830 else if (FLOAT_MODE_P (mode)
18831 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18833 *total = rs6000_cost->fp;
18841 /* Carry bit requires mode == Pmode.
18842 NEG or PLUS already counted so only add one. */
18844 && (outer_code == NEG || outer_code == PLUS))
18846 *total = COSTS_N_INSNS (1);
18849 if (outer_code == SET)
18851 if (XEXP (x, 1) == const0_rtx)
18853 *total = COSTS_N_INSNS (2);
18856 else if (mode == Pmode)
18858 *total = COSTS_N_INSNS (3);
18867 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18869 *total = COSTS_N_INSNS (2);
18873 if (outer_code == COMPARE)
18887 /* A C expression returning the cost of moving data from a register of class
18888 CLASS1 to one of CLASS2. */
18891 rs6000_register_move_cost (enum machine_mode mode,
18892 enum reg_class from, enum reg_class to)
18894 /* Moves from/to GENERAL_REGS. */
18895 if (reg_classes_intersect_p (to, GENERAL_REGS)
18896 || reg_classes_intersect_p (from, GENERAL_REGS))
18898 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18901 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18902 return (rs6000_memory_move_cost (mode, from, 0)
18903 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18905 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18907 else if (from == CR_REGS)
18911 /* A move will cost one instruction per GPR moved. */
18912 return 2 * hard_regno_nregs[0][mode];
18915 /* Moving between two similar registers is just one instruction. */
18916 else if (reg_classes_intersect_p (to, from))
18917 return mode == TFmode ? 4 : 2;
18919 /* Everything else has to go through GENERAL_REGS. */
18921 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18922 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18925 /* A C expressions returning the cost of moving data of MODE from a register to
18929 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18930 int in ATTRIBUTE_UNUSED)
18932 if (reg_classes_intersect_p (class, GENERAL_REGS))
18933 return 4 * hard_regno_nregs[0][mode];
18934 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18935 return 4 * hard_regno_nregs[32][mode];
18936 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18937 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18939 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18942 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18943 Assumes no trapping math and finite arguments. */
18946 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18948 rtx x0, e0, e1, y1, u0, v0, one;
18950 x0 = gen_reg_rtx (SFmode);
18951 e0 = gen_reg_rtx (SFmode);
18952 e1 = gen_reg_rtx (SFmode);
18953 y1 = gen_reg_rtx (SFmode);
18954 u0 = gen_reg_rtx (SFmode);
18955 v0 = gen_reg_rtx (SFmode);
18956 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18958 /* x0 = 1./d estimate */
18959 emit_insn (gen_rtx_SET (VOIDmode, x0,
18960 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18962 /* e0 = 1. - d * x0 */
18963 emit_insn (gen_rtx_SET (VOIDmode, e0,
18964 gen_rtx_MINUS (SFmode, one,
18965 gen_rtx_MULT (SFmode, d, x0))));
18966 /* e1 = e0 + e0 * e0 */
18967 emit_insn (gen_rtx_SET (VOIDmode, e1,
18968 gen_rtx_PLUS (SFmode,
18969 gen_rtx_MULT (SFmode, e0, e0), e0)));
18970 /* y1 = x0 + e1 * x0 */
18971 emit_insn (gen_rtx_SET (VOIDmode, y1,
18972 gen_rtx_PLUS (SFmode,
18973 gen_rtx_MULT (SFmode, e1, x0), x0)));
18975 emit_insn (gen_rtx_SET (VOIDmode, u0,
18976 gen_rtx_MULT (SFmode, n, y1)));
18977 /* v0 = n - d * u0 */
18978 emit_insn (gen_rtx_SET (VOIDmode, v0,
18979 gen_rtx_MINUS (SFmode, n,
18980 gen_rtx_MULT (SFmode, d, u0))));
18981 /* res = u0 + v0 * y1 */
18982 emit_insn (gen_rtx_SET (VOIDmode, res,
18983 gen_rtx_PLUS (SFmode,
18984 gen_rtx_MULT (SFmode, v0, y1), u0)));
18987 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18988 Assumes no trapping math and finite arguments. */
18991 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18993 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18995 x0 = gen_reg_rtx (DFmode);
18996 e0 = gen_reg_rtx (DFmode);
18997 e1 = gen_reg_rtx (DFmode);
18998 e2 = gen_reg_rtx (DFmode);
18999 y1 = gen_reg_rtx (DFmode);
19000 y2 = gen_reg_rtx (DFmode);
19001 y3 = gen_reg_rtx (DFmode);
19002 u0 = gen_reg_rtx (DFmode);
19003 v0 = gen_reg_rtx (DFmode);
19004 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
19006 /* x0 = 1./d estimate */
19007 emit_insn (gen_rtx_SET (VOIDmode, x0,
19008 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
19010 /* e0 = 1. - d * x0 */
19011 emit_insn (gen_rtx_SET (VOIDmode, e0,
19012 gen_rtx_MINUS (DFmode, one,
19013 gen_rtx_MULT (SFmode, d, x0))));
19014 /* y1 = x0 + e0 * x0 */
19015 emit_insn (gen_rtx_SET (VOIDmode, y1,
19016 gen_rtx_PLUS (DFmode,
19017 gen_rtx_MULT (DFmode, e0, x0), x0)));
19019 emit_insn (gen_rtx_SET (VOIDmode, e1,
19020 gen_rtx_MULT (DFmode, e0, e0)));
19021 /* y2 = y1 + e1 * y1 */
19022 emit_insn (gen_rtx_SET (VOIDmode, y2,
19023 gen_rtx_PLUS (DFmode,
19024 gen_rtx_MULT (DFmode, e1, y1), y1)));
19026 emit_insn (gen_rtx_SET (VOIDmode, e2,
19027 gen_rtx_MULT (DFmode, e1, e1)));
19028 /* y3 = y2 + e2 * y2 */
19029 emit_insn (gen_rtx_SET (VOIDmode, y3,
19030 gen_rtx_PLUS (DFmode,
19031 gen_rtx_MULT (DFmode, e2, y2), y2)));
19033 emit_insn (gen_rtx_SET (VOIDmode, u0,
19034 gen_rtx_MULT (DFmode, n, y3)));
19035 /* v0 = n - d * u0 */
19036 emit_insn (gen_rtx_SET (VOIDmode, v0,
19037 gen_rtx_MINUS (DFmode, n,
19038 gen_rtx_MULT (DFmode, d, u0))));
19039 /* res = u0 + v0 * y3 */
19040 emit_insn (gen_rtx_SET (VOIDmode, res,
19041 gen_rtx_PLUS (DFmode,
19042 gen_rtx_MULT (DFmode, v0, y3), u0)));
19045 /* Return an RTX representing where to find the function value of a
19046 function returning MODE. */
19048 rs6000_complex_function_value (enum machine_mode mode)
19050 unsigned int regno;
19052 enum machine_mode inner = GET_MODE_INNER (mode);
19053 unsigned int inner_bytes = GET_MODE_SIZE (inner);
19055 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
19056 regno = FP_ARG_RETURN;
19059 regno = GP_ARG_RETURN;
19061 /* 32-bit is OK since it'll go in r3/r4. */
19062 if (TARGET_32BIT && inner_bytes >= 4)
19063 return gen_rtx_REG (mode, regno);
19066 if (inner_bytes >= 8)
19067 return gen_rtx_REG (mode, regno);
19069 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
19071 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
19072 GEN_INT (inner_bytes));
19073 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
19076 /* Define how to find the value returned by a function.
19077 VALTYPE is the data type of the value (as a tree).
19078 If the precise function being called is known, FUNC is its FUNCTION_DECL;
19079 otherwise, FUNC is 0.
19081 On the SPE, both FPs and vectors are returned in r3.
19083 On RS/6000 an integer value is in r3 and a floating-point value is in
19084 fp1, unless -msoft-float. */
19087 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
19089 enum machine_mode mode;
19090 unsigned int regno;
19092 /* Special handling for structs in darwin64. */
19093 if (rs6000_darwin64_abi
19094 && TYPE_MODE (valtype) == BLKmode
19095 && TREE_CODE (valtype) == RECORD_TYPE
19096 && int_size_in_bytes (valtype) > 0)
19098 CUMULATIVE_ARGS valcum;
19102 valcum.fregno = FP_ARG_MIN_REG;
19103 valcum.vregno = ALTIVEC_ARG_MIN_REG;
19104 /* Do a trial code generation as if this were going to be passed as
19105 an argument; if any part goes in memory, we return NULL. */
19106 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
19109 /* Otherwise fall through to standard ABI rules. */
19112 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
19114 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19115 return gen_rtx_PARALLEL (DImode,
19117 gen_rtx_EXPR_LIST (VOIDmode,
19118 gen_rtx_REG (SImode, GP_ARG_RETURN),
19120 gen_rtx_EXPR_LIST (VOIDmode,
19121 gen_rtx_REG (SImode,
19122 GP_ARG_RETURN + 1),
19125 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19127 return gen_rtx_PARALLEL (DCmode,
19129 gen_rtx_EXPR_LIST (VOIDmode,
19130 gen_rtx_REG (SImode, GP_ARG_RETURN),
19132 gen_rtx_EXPR_LIST (VOIDmode,
19133 gen_rtx_REG (SImode,
19134 GP_ARG_RETURN + 1),
19136 gen_rtx_EXPR_LIST (VOIDmode,
19137 gen_rtx_REG (SImode,
19138 GP_ARG_RETURN + 2),
19140 gen_rtx_EXPR_LIST (VOIDmode,
19141 gen_rtx_REG (SImode,
19142 GP_ARG_RETURN + 3),
19146 if ((INTEGRAL_TYPE_P (valtype)
19147 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
19148 || POINTER_TYPE_P (valtype))
19149 mode = TARGET_32BIT ? SImode : DImode;
19151 mode = TYPE_MODE (valtype);
19153 if (DECIMAL_FLOAT_MODE_P (mode))
19154 regno = GP_ARG_RETURN;
19155 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19156 regno = FP_ARG_RETURN;
19157 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19158 && targetm.calls.split_complex_arg)
19159 return rs6000_complex_function_value (mode);
19160 else if (TREE_CODE (valtype) == VECTOR_TYPE
19161 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19162 && ALTIVEC_VECTOR_MODE (mode))
19163 regno = ALTIVEC_ARG_RETURN;
19164 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19165 && (mode == DFmode || mode == DCmode))
19166 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19168 regno = GP_ARG_RETURN;
19170 return gen_rtx_REG (mode, regno);
19173 /* Define how to find the value returned by a library function
19174 assuming the value has mode MODE. */
19176 rs6000_libcall_value (enum machine_mode mode)
19178 unsigned int regno;
19180 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19182 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19183 return gen_rtx_PARALLEL (DImode,
19185 gen_rtx_EXPR_LIST (VOIDmode,
19186 gen_rtx_REG (SImode, GP_ARG_RETURN),
19188 gen_rtx_EXPR_LIST (VOIDmode,
19189 gen_rtx_REG (SImode,
19190 GP_ARG_RETURN + 1),
19194 if (DECIMAL_FLOAT_MODE_P (mode))
19195 regno = GP_ARG_RETURN;
19196 else if (SCALAR_FLOAT_MODE_P (mode)
19197 && TARGET_HARD_FLOAT && TARGET_FPRS)
19198 regno = FP_ARG_RETURN;
19199 else if (ALTIVEC_VECTOR_MODE (mode)
19200 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19201 regno = ALTIVEC_ARG_RETURN;
19202 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19203 return rs6000_complex_function_value (mode);
19204 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19205 && (mode == DFmode || mode == DCmode))
19206 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19208 regno = GP_ARG_RETURN;
19210 return gen_rtx_REG (mode, regno);
19213 /* Define the offset between two registers, FROM to be eliminated and its
19214 replacement TO, at the start of a routine. */
19216 rs6000_initial_elimination_offset (int from, int to)
19218 rs6000_stack_t *info = rs6000_stack_info ();
19219 HOST_WIDE_INT offset;
19221 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19222 offset = info->push_p ? 0 : -info->total_size;
19223 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19225 offset = info->push_p ? 0 : -info->total_size;
19226 if (FRAME_GROWS_DOWNWARD)
19227 offset += info->fixed_size + info->vars_size + info->parm_size;
19229 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19230 offset = FRAME_GROWS_DOWNWARD
19231 ? info->fixed_size + info->vars_size + info->parm_size
19233 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19234 offset = info->total_size;
19235 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19236 offset = info->push_p ? info->total_size : 0;
19237 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19240 gcc_unreachable ();
19245 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19248 rs6000_is_opaque_type (tree type)
19250 return (type == opaque_V2SI_type_node
19251 || type == opaque_V2SF_type_node
19252 || type == opaque_p_V2SI_type_node
19253 || type == opaque_V4SI_type_node);
19257 rs6000_dwarf_register_span (rtx reg)
19262 && (SPE_VECTOR_MODE (GET_MODE (reg))
19263 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19268 regno = REGNO (reg);
19270 /* The duality of the SPE register size wreaks all kinds of havoc.
19271 This is a way of distinguishing r0 in 32-bits from r0 in
19274 gen_rtx_PARALLEL (VOIDmode,
19277 gen_rtx_REG (SImode, regno + 1200),
19278 gen_rtx_REG (SImode, regno))
19280 gen_rtx_REG (SImode, regno),
19281 gen_rtx_REG (SImode, regno + 1200)));
19284 /* Map internal gcc register numbers to DWARF2 register numbers. */
19287 rs6000_dbx_register_number (unsigned int regno)
19289 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19291 if (regno == MQ_REGNO)
19293 if (regno == LINK_REGISTER_REGNUM)
19295 if (regno == COUNT_REGISTER_REGNUM)
19297 if (CR_REGNO_P (regno))
19298 return regno - CR0_REGNO + 86;
19299 if (regno == XER_REGNO)
19301 if (ALTIVEC_REGNO_P (regno))
19302 return regno - FIRST_ALTIVEC_REGNO + 1124;
19303 if (regno == VRSAVE_REGNO)
19305 if (regno == VSCR_REGNO)
19307 if (regno == SPE_ACC_REGNO)
19309 if (regno == SPEFSCR_REGNO)
19311 /* SPE high reg number. We get these values of regno from
19312 rs6000_dwarf_register_span. */
19313 gcc_assert (regno >= 1200 && regno < 1232);
19317 /* target hook eh_return_filter_mode */
19318 static enum machine_mode
19319 rs6000_eh_return_filter_mode (void)
19321 return TARGET_32BIT ? SImode : word_mode;
19324 /* Target hook for scalar_mode_supported_p. */
19326 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19328 if (DECIMAL_FLOAT_MODE_P (mode))
19331 return default_scalar_mode_supported_p (mode);
19334 /* Target hook for vector_mode_supported_p. */
19336 rs6000_vector_mode_supported_p (enum machine_mode mode)
19339 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19342 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19349 /* Target hook for invalid_arg_for_unprototyped_fn. */
19350 static const char *
19351 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19353 return (!rs6000_darwin64_abi
19355 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19356 && (funcdecl == NULL_TREE
19357 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19358 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19359 ? N_("AltiVec argument passed to unprototyped function")
19363 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19364 setup by using __stack_chk_fail_local hidden function instead of
19365 calling __stack_chk_fail directly. Otherwise it is better to call
19366 __stack_chk_fail directly. */
19369 rs6000_stack_protect_fail (void)
19371 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19372 ? default_hidden_stack_protect_fail ()
19373 : default_external_stack_protect_fail ();
19376 #include "gt-rs6000.h"